From 887bcbbad85f2bb1a241cb295e9227d6d8c31f89 Mon Sep 17 00:00:00 2001 From: "dzzxzz@gmail.com" Date: Mon, 5 Mar 2012 01:13:30 +0000 Subject: update Fujistu FM3 porting git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1990 bbd45198-f89e-11dd-88c7-29a3b14d5316 --- bsp/fm3/CMSIS/SConscript | 19 - bsp/fm3/CMSIS/core_cm3.c | 359 -- bsp/fm3/CMSIS/core_cm3.h | 1166 ---- bsp/fm3/CMSIS/core_cmFunc.h | 912 --- bsp/fm3/CMSIS/core_cmInstr.h | 684 --- bsp/fm3/CMSIS/mb9bf506r.h | 9739 --------------------------------- bsp/fm3/CMSIS/start_gcc.S | 360 -- bsp/fm3/CMSIS/start_iar.S | 363 -- bsp/fm3/CMSIS/start_rvds.S | 291 - bsp/fm3/CMSIS/system_mb9bf50x.c | 111 - bsp/fm3/CMSIS/system_mb9bf50x.h | 71 - bsp/fm3/mb9bf500r/SConscript | 16 - bsp/fm3/mb9bf500r/SConstruct | 39 - bsp/fm3/mb9bf500r/adc.c | 133 - bsp/fm3/mb9bf500r/adc.h | 32 - bsp/fm3/mb9bf500r/application.c | 143 - bsp/fm3/mb9bf500r/board.c | 54 - bsp/fm3/mb9bf500r/board.h | 29 - bsp/fm3/mb9bf500r/cpuusage.c | 115 - bsp/fm3/mb9bf500r/cpuusage.h | 23 - bsp/fm3/mb9bf500r/fm3_easy_kit.ewp | 2030 ------- bsp/fm3/mb9bf500r/fm3_easy_kit.eww | 10 - bsp/fm3/mb9bf500r/fm3_rom.ld | 122 - bsp/fm3/mb9bf500r/fm3_rom.sct | 15 - bsp/fm3/mb9bf500r/font.h | 961 ---- bsp/fm3/mb9bf500r/info.c | 214 - bsp/fm3/mb9bf500r/key.c | 164 - bsp/fm3/mb9bf500r/key.h | 47 - bsp/fm3/mb9bf500r/lcd.c | 481 -- bsp/fm3/mb9bf500r/lcd.h | 189 - bsp/fm3/mb9bf500r/led.c | 150 - bsp/fm3/mb9bf500r/led.h | 42 - bsp/fm3/mb9bf500r/mb9bf500r.icf | 32 - bsp/fm3/mb9bf500r/project.uvopt | 586 -- bsp/fm3/mb9bf500r/project.uvproj | 555 -- bsp/fm3/mb9bf500r/rtconfig.h | 88 - bsp/fm3/mb9bf500r/rtconfig.py | 114 - bsp/fm3/mb9bf500r/startup.c | 107 - bsp/fm3/mb9bf506r/SConscript | 16 - bsp/fm3/mb9bf506r/SConstruct | 39 - bsp/fm3/mb9bf506r/application.c | 71 - bsp/fm3/mb9bf506r/board.c | 64 - bsp/fm3/mb9bf506r/board.h | 31 - bsp/fm3/mb9bf506r/console.c | 180 - bsp/fm3/mb9bf506r/fm3_easy_kit.ewp | 1897 ------- bsp/fm3/mb9bf506r/fm3_easy_kit.eww | 10 - bsp/fm3/mb9bf506r/fm3_rom.ld | 122 - bsp/fm3/mb9bf506r/led.c | 141 - bsp/fm3/mb9bf506r/led.h | 43 - bsp/fm3/mb9bf506r/mb9bf506.icf | 33 - bsp/fm3/mb9bf506r/nand.c | 667 --- bsp/fm3/mb9bf506r/nand.h | 57 - bsp/fm3/mb9bf506r/rtconfig.h | 90 - bsp/fm3/mb9bf506r/rtconfig.py | 113 - bsp/fm3/mb9bf506r/serial.c | 348 -- bsp/fm3/mb9bf506r/serial.h | 99 - bsp/fm3/mb9bf506r/startup.c | 122 - bsp/mb9bf500r/CMSIS/SConscript | 19 + bsp/mb9bf500r/CMSIS/core_cm3.c | 359 ++ bsp/mb9bf500r/CMSIS/core_cm3.h | 1166 ++++ bsp/mb9bf500r/CMSIS/core_cmFunc.h | 912 +++ bsp/mb9bf500r/CMSIS/core_cmInstr.h | 684 +++ bsp/mb9bf500r/CMSIS/mb9bf506r.h | 9739 +++++++++++++++++++++++++++++++++ bsp/mb9bf500r/CMSIS/start_gcc.S | 360 ++ bsp/mb9bf500r/CMSIS/start_iar.S | 363 ++ bsp/mb9bf500r/CMSIS/start_rvds.S | 291 + bsp/mb9bf500r/CMSIS/system_mb9bf50x.c | 111 + bsp/mb9bf500r/CMSIS/system_mb9bf50x.h | 71 + bsp/mb9bf500r/SConscript | 16 + bsp/mb9bf500r/SConstruct | 39 + bsp/mb9bf500r/adc.c | 133 + bsp/mb9bf500r/adc.h | 32 + bsp/mb9bf500r/application.c | 143 + bsp/mb9bf500r/board.c | 54 + bsp/mb9bf500r/board.h | 29 + bsp/mb9bf500r/cpuusage.c | 115 + bsp/mb9bf500r/cpuusage.h | 23 + bsp/mb9bf500r/fm3_easy_kit.ewp | 2030 +++++++ bsp/mb9bf500r/fm3_easy_kit.eww | 10 + bsp/mb9bf500r/fm3_rom.ld | 122 + bsp/mb9bf500r/fm3_rom.sct | 15 + bsp/mb9bf500r/font.h | 961 ++++ bsp/mb9bf500r/info.c | 214 + bsp/mb9bf500r/key.c | 164 + bsp/mb9bf500r/key.h | 47 + bsp/mb9bf500r/lcd.c | 481 ++ bsp/mb9bf500r/lcd.h | 189 + bsp/mb9bf500r/led.c | 150 + bsp/mb9bf500r/led.h | 42 + bsp/mb9bf500r/mb9bf500r.icf | 32 + bsp/mb9bf500r/project.uvopt | 586 ++ bsp/mb9bf500r/project.uvproj | 555 ++ bsp/mb9bf500r/rtconfig.h | 88 + bsp/mb9bf500r/rtconfig.py | 114 + bsp/mb9bf500r/startup.c | 107 + bsp/mb9bf506r/CMSIS/SConscript | 19 + bsp/mb9bf506r/CMSIS/core_cm3.c | 359 ++ bsp/mb9bf506r/CMSIS/core_cm3.h | 1166 ++++ bsp/mb9bf506r/CMSIS/core_cmFunc.h | 912 +++ bsp/mb9bf506r/CMSIS/core_cmInstr.h | 684 +++ bsp/mb9bf506r/CMSIS/mb9bf506r.h | 9739 +++++++++++++++++++++++++++++++++ bsp/mb9bf506r/CMSIS/start_gcc.S | 360 ++ bsp/mb9bf506r/CMSIS/start_iar.S | 363 ++ bsp/mb9bf506r/CMSIS/start_rvds.S | 291 + bsp/mb9bf506r/CMSIS/system_mb9bf50x.c | 111 + bsp/mb9bf506r/CMSIS/system_mb9bf50x.h | 71 + bsp/mb9bf506r/SConscript | 16 + bsp/mb9bf506r/SConstruct | 39 + bsp/mb9bf506r/application.c | 71 + bsp/mb9bf506r/board.c | 64 + bsp/mb9bf506r/board.h | 31 + bsp/mb9bf506r/console.c | 180 + bsp/mb9bf506r/fm3_easy_kit.ewp | 1894 +++++++ bsp/mb9bf506r/fm3_easy_kit.eww | 10 + bsp/mb9bf506r/fm3_rom.ld | 122 + bsp/mb9bf506r/led.c | 141 + bsp/mb9bf506r/led.h | 43 + bsp/mb9bf506r/mb9bf506.icf | 33 + bsp/mb9bf506r/nand.c | 667 +++ bsp/mb9bf506r/nand.h | 57 + bsp/mb9bf506r/rtconfig.h | 90 + bsp/mb9bf506r/rtconfig.py | 113 + bsp/mb9bf506r/serial.c | 348 ++ bsp/mb9bf506r/serial.h | 99 + bsp/mb9bf506r/startup.c | 122 + 125 files changed, 38781 insertions(+), 24709 deletions(-) delete mode 100644 bsp/fm3/CMSIS/SConscript delete mode 100644 bsp/fm3/CMSIS/core_cm3.c delete mode 100644 bsp/fm3/CMSIS/core_cm3.h delete mode 100644 bsp/fm3/CMSIS/core_cmFunc.h delete mode 100644 bsp/fm3/CMSIS/core_cmInstr.h delete mode 100644 bsp/fm3/CMSIS/mb9bf506r.h delete mode 100644 bsp/fm3/CMSIS/start_gcc.S delete mode 100644 bsp/fm3/CMSIS/start_iar.S delete mode 100644 bsp/fm3/CMSIS/start_rvds.S delete mode 100644 bsp/fm3/CMSIS/system_mb9bf50x.c delete mode 100644 bsp/fm3/CMSIS/system_mb9bf50x.h delete mode 100644 bsp/fm3/mb9bf500r/SConscript delete mode 100644 bsp/fm3/mb9bf500r/SConstruct delete mode 100644 bsp/fm3/mb9bf500r/adc.c delete mode 100644 bsp/fm3/mb9bf500r/adc.h delete mode 100644 bsp/fm3/mb9bf500r/application.c delete mode 100644 bsp/fm3/mb9bf500r/board.c delete mode 100644 bsp/fm3/mb9bf500r/board.h delete mode 100644 bsp/fm3/mb9bf500r/cpuusage.c delete mode 100644 bsp/fm3/mb9bf500r/cpuusage.h delete mode 100644 bsp/fm3/mb9bf500r/fm3_easy_kit.ewp delete mode 100644 bsp/fm3/mb9bf500r/fm3_easy_kit.eww delete mode 100644 bsp/fm3/mb9bf500r/fm3_rom.ld delete mode 100644 bsp/fm3/mb9bf500r/fm3_rom.sct delete mode 100644 bsp/fm3/mb9bf500r/font.h delete mode 100644 bsp/fm3/mb9bf500r/info.c delete mode 100644 bsp/fm3/mb9bf500r/key.c delete mode 100644 bsp/fm3/mb9bf500r/key.h delete mode 100644 bsp/fm3/mb9bf500r/lcd.c delete mode 100644 bsp/fm3/mb9bf500r/lcd.h delete mode 100644 bsp/fm3/mb9bf500r/led.c delete mode 100644 bsp/fm3/mb9bf500r/led.h delete mode 100644 bsp/fm3/mb9bf500r/mb9bf500r.icf delete mode 100644 bsp/fm3/mb9bf500r/project.uvopt delete mode 100644 bsp/fm3/mb9bf500r/project.uvproj delete mode 100644 bsp/fm3/mb9bf500r/rtconfig.h delete mode 100644 bsp/fm3/mb9bf500r/rtconfig.py delete mode 100644 bsp/fm3/mb9bf500r/startup.c delete mode 100644 bsp/fm3/mb9bf506r/SConscript delete mode 100644 bsp/fm3/mb9bf506r/SConstruct delete mode 100644 bsp/fm3/mb9bf506r/application.c delete mode 100644 bsp/fm3/mb9bf506r/board.c delete mode 100644 bsp/fm3/mb9bf506r/board.h delete mode 100644 bsp/fm3/mb9bf506r/console.c delete mode 100644 bsp/fm3/mb9bf506r/fm3_easy_kit.ewp delete mode 100644 bsp/fm3/mb9bf506r/fm3_easy_kit.eww delete mode 100644 bsp/fm3/mb9bf506r/fm3_rom.ld delete mode 100644 bsp/fm3/mb9bf506r/led.c delete mode 100644 bsp/fm3/mb9bf506r/led.h delete mode 100644 bsp/fm3/mb9bf506r/mb9bf506.icf delete mode 100644 bsp/fm3/mb9bf506r/nand.c delete mode 100644 bsp/fm3/mb9bf506r/nand.h delete mode 100644 bsp/fm3/mb9bf506r/rtconfig.h delete mode 100644 bsp/fm3/mb9bf506r/rtconfig.py delete mode 100644 bsp/fm3/mb9bf506r/serial.c delete mode 100644 bsp/fm3/mb9bf506r/serial.h delete mode 100644 bsp/fm3/mb9bf506r/startup.c create mode 100644 bsp/mb9bf500r/CMSIS/SConscript create mode 100644 bsp/mb9bf500r/CMSIS/core_cm3.c create mode 100644 bsp/mb9bf500r/CMSIS/core_cm3.h create mode 100644 bsp/mb9bf500r/CMSIS/core_cmFunc.h create mode 100644 bsp/mb9bf500r/CMSIS/core_cmInstr.h create mode 100644 bsp/mb9bf500r/CMSIS/mb9bf506r.h create mode 100644 bsp/mb9bf500r/CMSIS/start_gcc.S create mode 100644 bsp/mb9bf500r/CMSIS/start_iar.S create mode 100644 bsp/mb9bf500r/CMSIS/start_rvds.S create mode 100644 bsp/mb9bf500r/CMSIS/system_mb9bf50x.c create mode 100644 bsp/mb9bf500r/CMSIS/system_mb9bf50x.h create mode 100644 bsp/mb9bf500r/SConscript create mode 100644 bsp/mb9bf500r/SConstruct create mode 100644 bsp/mb9bf500r/adc.c create mode 100644 bsp/mb9bf500r/adc.h create mode 100644 bsp/mb9bf500r/application.c create mode 100644 bsp/mb9bf500r/board.c create mode 100644 bsp/mb9bf500r/board.h create mode 100644 bsp/mb9bf500r/cpuusage.c create mode 100644 bsp/mb9bf500r/cpuusage.h create mode 100644 bsp/mb9bf500r/fm3_easy_kit.ewp create mode 100644 bsp/mb9bf500r/fm3_easy_kit.eww create mode 100644 bsp/mb9bf500r/fm3_rom.ld create mode 100644 bsp/mb9bf500r/fm3_rom.sct create mode 100644 bsp/mb9bf500r/font.h create mode 100644 bsp/mb9bf500r/info.c create mode 100644 bsp/mb9bf500r/key.c create mode 100644 bsp/mb9bf500r/key.h create mode 100644 bsp/mb9bf500r/lcd.c create mode 100644 bsp/mb9bf500r/lcd.h create mode 100644 bsp/mb9bf500r/led.c create mode 100644 bsp/mb9bf500r/led.h create mode 100644 bsp/mb9bf500r/mb9bf500r.icf create mode 100644 bsp/mb9bf500r/project.uvopt create mode 100644 bsp/mb9bf500r/project.uvproj create mode 100644 bsp/mb9bf500r/rtconfig.h create mode 100644 bsp/mb9bf500r/rtconfig.py create mode 100644 bsp/mb9bf500r/startup.c create mode 100644 bsp/mb9bf506r/CMSIS/SConscript create mode 100644 bsp/mb9bf506r/CMSIS/core_cm3.c create mode 100644 bsp/mb9bf506r/CMSIS/core_cm3.h create mode 100644 bsp/mb9bf506r/CMSIS/core_cmFunc.h create mode 100644 bsp/mb9bf506r/CMSIS/core_cmInstr.h create mode 100644 bsp/mb9bf506r/CMSIS/mb9bf506r.h create mode 100644 bsp/mb9bf506r/CMSIS/start_gcc.S create mode 100644 bsp/mb9bf506r/CMSIS/start_iar.S create mode 100644 bsp/mb9bf506r/CMSIS/start_rvds.S create mode 100644 bsp/mb9bf506r/CMSIS/system_mb9bf50x.c create mode 100644 bsp/mb9bf506r/CMSIS/system_mb9bf50x.h create mode 100644 bsp/mb9bf506r/SConscript create mode 100644 bsp/mb9bf506r/SConstruct create mode 100644 bsp/mb9bf506r/application.c create mode 100644 bsp/mb9bf506r/board.c create mode 100644 bsp/mb9bf506r/board.h create mode 100644 bsp/mb9bf506r/console.c create mode 100644 bsp/mb9bf506r/fm3_easy_kit.ewp create mode 100644 bsp/mb9bf506r/fm3_easy_kit.eww create mode 100644 bsp/mb9bf506r/fm3_rom.ld create mode 100644 bsp/mb9bf506r/led.c create mode 100644 bsp/mb9bf506r/led.h create mode 100644 bsp/mb9bf506r/mb9bf506.icf create mode 100644 bsp/mb9bf506r/nand.c create mode 100644 bsp/mb9bf506r/nand.h create mode 100644 bsp/mb9bf506r/rtconfig.h create mode 100644 bsp/mb9bf506r/rtconfig.py create mode 100644 bsp/mb9bf506r/serial.c create mode 100644 bsp/mb9bf506r/serial.h create mode 100644 bsp/mb9bf506r/startup.c (limited to 'bsp') diff --git a/bsp/fm3/CMSIS/SConscript b/bsp/fm3/CMSIS/SConscript deleted file mode 100644 index e058a7aad1..0000000000 --- a/bsp/fm3/CMSIS/SConscript +++ /dev/null @@ -1,19 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -src = Glob('*.c') - -# add for startup script -if rtconfig.CROSS_TOOL == 'gcc': - src = src + ['start_gcc.S'] -elif rtconfig.CROSS_TOOL == 'keil': - src = src + ['start_rvds.S'] -elif rtconfig.CROSS_TOOL == 'iar': - src = src + ['start_iar.S'] - -CPPPATH = [GetCurrentDir()] - -group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, LIBRARY = '') - -Return('group') diff --git a/bsp/fm3/CMSIS/core_cm3.c b/bsp/fm3/CMSIS/core_cm3.c deleted file mode 100644 index f1bfb2b8e0..0000000000 --- a/bsp/fm3/CMSIS/core_cm3.c +++ /dev/null @@ -1,359 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.c - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File - * @version V1.40 - * @date 18. February 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#include - -/* define compiler specific symbols */ -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - - -/* ########################## Core Instruction Access ######################### */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ - -/** - * @brief Reverse byte order (16 bit) - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -#if (__ARMCC_VERSION < 400677) -__ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -#if (__ARMCC_VERSION < 400677) -__ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - /** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __CLREX(void) -{ - clrex -} -#endif /* __ARMCC_VERSION */ - - -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* obsolete */ -#endif - - -/* ########################### Core Function Access ########################### */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_CONTROL(void) -{ - mrs r0, control - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_CONTROL(uint32_t control) -{ - msr control, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Get IPSR Register value - * - * @return uint32_t IPSR value - * - * return the content of the IPSR register - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_IPSR(void) -{ - mrs r0, ipsr - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Get APSR Register value - * - * @return uint32_t APSR value - * - * return the content of the APSR register - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_APSR(void) -{ - mrs r0, apsr - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Get xPSR Register value - * - * @return uint32_t xPSR value - * - * return the content of the xPSR register - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_xPSR(void) -{ - mrs r0, xpsr - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_PSP(void) -{ - mrs r0, psp - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_PSP(uint32_t topOfProcStack) -{ - msr psp, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_MSP(void) -{ - mrs r0, msp - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_MSP(uint32_t mainStackPointer) -{ - msr msp, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_BASEPRI(void) -{ - mrs r0, basepri - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_BASEPRI(uint32_t basePri) -{ - msr basepri, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_PRIMASK(void) -{ - mrs r0, primask - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_PRIMASK(uint32_t priMask) -{ - msr primask, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -#if (__ARMCC_VERSION < 400000) -__ASM uint32_t __get_FAULTMASK(void) -{ - mrs r0, faultmask - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -#if (__ARMCC_VERSION < 400000) -__ASM void __set_FAULTMASK(uint32_t faultMask) -{ - msr faultmask, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the FPSCR value - * - * @return FloatingPointStatusControlRegister - * - * Return the content of the FPSCR register - */ - -/** - * @brief Set the FPSCR value - * - * @param fpscr FloatingPointStatusControlRegister - * - * Set the FPSCR register - */ - - -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* obsolete */ -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* obsolete */ -#endif diff --git a/bsp/fm3/CMSIS/core_cm3.h b/bsp/fm3/CMSIS/core_cm3.h deleted file mode 100644 index 43be05e58b..0000000000 --- a/bsp/fm3/CMSIS/core_cm3.h +++ /dev/null @@ -1,1166 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V1.40 - * @date 16. February 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CM3_H__ -#define __CORE_CM3_H__ - -/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration - * - * List of Lint messages which will be suppressed and not shown: - * - not yet checked - * . - * Note: To re-enable a Message, insert a space before 'lint' * - * - */ - - -/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions - This file defines all structures and symbols for CMSIS core: - - CMSIS version number - - Cortex-M core registers and bitfields - - Cortex-M core peripheral base address - @{ - */ - -#ifdef __cplusplus - extern "C" { -#endif - -#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (0x40) /*!< [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x03) /*!< Cortex core */ - -#ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ -#endif - - -#include /* Include standard types */ - - - -/** - * IO definitions - * - * define access restrictions to peripheral registers - */ - -#ifdef __cplusplus - #define __I volatile /*!< defines 'read only' permissions */ -#else - #define __I volatile const /*!< defines 'read only' permissions */ -#endif -#define __O volatile /*!< defines 'write only' permissions */ -#define __IO volatile /*!< defines 'read / write' permissions */ - - - -/******************************************************************************* - * Register Abstraction - ******************************************************************************/ -/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register - @{ -*/ - -/** @addtogroup CMSIS_ARM_CORE CMSIS ARM Core - memory mapped structure for Nested Vectored Interrupt Controller (NVIC) - @{ - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; -#else - uint32_t _reserved0:16; - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; - uint32_t w; -} APSR_Type; - -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 00..08 Exception number */ - uint32_t _reserved0:23; - } b; - uint32_t w; -} IPSR_Type; - -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 00..08 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; -#else - uint32_t _reserved0:7; - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; - uint32_t w; -} xPSR_Type; - -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 00 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 01 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 02 FP extension active flag */ - uint32_t _reserved0:29; - } b; - uint32_t w; -} CONTROL_Type; - -/*@}*/ /* end of group CMSIS_ARM_CORE */ - - -/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC - memory mapped structure for Nested Vectored Interrupt Controller (NVIC) - @{ - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ -} NVIC_Type; -/*@}*/ /* end of group CMSIS_CM3_NVIC */ - - -/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB - memory mapped structure for System Control Block (SCB) - @{ - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ -/*@}*/ /* end of group CMSIS_CM3_SCB */ - - -/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick - memory mapped structure for SysTick - @{ - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ -/*@}*/ /* end of group CMSIS_CM3_SysTick */ - - -/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM - memory mapped structure for Instrumentation Trace Macrocell (ITM) - @{ - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ - __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ - __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ -/*@}*/ /* end of group CMSIS_CM3_ITM */ - - -/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type - memory mapped structure for Interrupt Type - @{ - */ -typedef struct -{ - uint32_t RESERVED0; - __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ -} InterruptType_Type; - -/* Interrupt Controller Type Register Definitions */ -#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ -#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ -#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ - -#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ -#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ - -#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ -#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ -/*@}*/ /* end of group CMSIS_CM3_InterruptType */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) -/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU - memory mapped structure for Memory Protection Unit (MPU) - @{ - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ -#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ -#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ -#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ -#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ -#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ -#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@}*/ /* end of group CMSIS_CM3_MPU */ -#endif - - -/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug - memory mapped structure for Core Debug Register - @{ - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ -/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ - - -/* Memory mapping of Cortex-M3 Hardware */ -#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ -#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ - -#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ -#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_register */ - - -/******************************************************************************* - * Hardware Abstraction Layer - ******************************************************************************/ - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - -#endif - -/* ########################## Core Instruction Access ######################### */ -#include "core_cmInstr.h" - -/* ########################### Core Function Access ########################### */ -#include "core_cmFunc.h" - - -/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface - Core Function Interface containing: - - Core NVIC Functions - - Core SysTick Functions - - Core Reset Functions -*/ -/*@{*/ - -/* ########################## NVIC functions #################################### */ - -/** - * @brief Set the Priority Grouping in NVIC Interrupt Controller - * - * @param PriorityGroup is priority grouping field - * - * Set the priority grouping field using the required unlock sequence. - * The parameter priority_grouping is assigned to the field - * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - */ -static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - (0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - -/** - * @brief Get the Priority Grouping from NVIC Interrupt Controller - * - * @return priority grouping field - * - * Get the priority grouping from NVIC Interrupt Controller. - * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. - */ -static __INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - -/** - * @brief Enable Interrupt in NVIC Interrupt Controller - * - * @param IRQn The positive number of the external interrupt to enable - * - * Enable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ -} - -/** - * @brief Disable the interrupt line for external interrupt specified - * - * @param IRQn The positive number of the external interrupt to disable - * - * Disable a device specific interupt in the NVIC interrupt controller. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - -/** - * @brief Read the interrupt pending bit for a device specific interrupt source - * - * @param IRQn The number of the device specifc interrupt - * @return 1 = interrupt pending, 0 = interrupt not pending - * - * Read the pending register in NVIC and return 1 if its status is pending, - * otherwise it returns 0 - */ -static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - -/** - * @brief Set the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for set pending - * - * Set the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - -/** - * @brief Clear the pending bit for an external interrupt - * - * @param IRQn The number of the interrupt for clear pending - * - * Clear the pending bit for the specified interrupt. - * The interrupt number cannot be a negative value. - */ -static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - -/** - * @brief Read the active bit for an external interrupt - * - * @param IRQn The number of the interrupt for read active bit - * @return 1 = interrupt active, 0 = interrupt not active - * - * Read the active register in NVIC and returns 1 if its status is active, - * otherwise it returns 0. - */ -static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - -/** - * @brief Set the priority for an interrupt - * - * @param IRQn The number of the interrupt for set priority - * @param priority The priority to set - * - * Set the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - -/** - * @brief Read the priority for an interrupt - * - * @param IRQn The number of the interrupt for get priority - * @return The priority for the interrupt - * - * Read the priority for the specified interrupt. The interrupt - * number can be positive to specify an external (device specific) - * interrupt, or negative to specify an internal (core) interrupt. - * - * The returned priority value is automatically aligned to the implemented - * priority bits of the microcontroller. - * - * Note: The priority cannot be set for every core interrupt. - */ -static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** - * @brief Encode the priority for an interrupt - * - * @param PriorityGroup The used priority group - * @param PreemptPriority The preemptive priority value (starting from 0) - * @param SubPriority The sub priority value (starting from 0) - * @return The encoded priority for the interrupt - * - * Encode the priority for an interrupt with the given priority group, - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The returned priority value can be used for NVIC_SetPriority(...) function - */ -static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** - * @brief Decode the priority of an interrupt - * - * @param Priority The priority for the interrupt - * @param PriorityGroup The used priority group - * @param pPreemptPriority The preemptive priority value (starting from 0) - * @param pSubPriority The sub priority value (starting from 0) - * - * Decode an interrupt priority value with the given priority group to - * preemptive priority value and sub priority value. - * In case of a conflict between priority grouping and available - * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. - * - * The priority value can be retrieved with NVIC_GetPriority(...) function - */ -static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - - -/* ################################## SysTick function ############################################ */ - -#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) - -/** - * @brief Initialize and start the SysTick counter and its interrupt. - * - * @param ticks number of ticks between two interrupts - * @return 1 = failed, 0 = successful - * - * Initialise the system tick timer and its interrupt and start the - * system tick timer / counter in free running mode to generate - * periodical interrupts. - */ -static __INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - - - - -/* ################################## Reset function ############################################ */ - -/** - * @brief Initiate a system reset request. - * - * Initiate a system reset request to reset the MCU - */ -static __INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ - - - -/* ##################################### Debug In/Output function ########################################### */ - -/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface - Core Debug Interface containing: - - Core Debug Receive / Transmit Functions - - Core Debug Defines - - Core Debug Variables -*/ -/*@{*/ - -extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ - - -/** - * @brief Outputs a character via the ITM channel 0 - * - * @param ch character to output - * @return character to output - * - * The function outputs a character via the ITM channel 0. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ - (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** - * @brief Inputs a character via variable ITM_RxBuffer - * - * @return received character, -1 = no character received - * - * The function inputs a character via variable ITM_RxBuffer. - * The function returns when no debugger is connected that has booked the output. - * It is blocking when a debugger is connected, but the previous character send is not transmitted. - */ -static __INLINE int ITM_ReceiveChar (void) { - int ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - * @brief Check if a character via variable ITM_RxBuffer is available - * - * @return 1 = character available, 0 = no character available - * - * The function checks variable ITM_RxBuffer whether a character is available or not. - * The function returns '1' if a character is available and '0' if no character is available. - */ -static __INLINE int ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ - - -#ifdef __cplusplus -} -#endif - -/*@}*/ /* end of group CMSIS_CM3_core_definitions */ - -#endif /* __CORE_CM3_H__ */ - -/*lint -restore */ diff --git a/bsp/fm3/CMSIS/core_cmFunc.h b/bsp/fm3/CMSIS/core_cmFunc.h deleted file mode 100644 index 03c29d35dc..0000000000 --- a/bsp/fm3/CMSIS/core_cmFunc.h +++ /dev/null @@ -1,912 +0,0 @@ -/**************************************************************************//** - * @file core_cmFunc.h - * @brief CMSIS Cortex-M Core Function Access Header File - * @version V1.40 - * @date 16. February 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMFUNC_H__ -#define __CORE_CMFUNC_H__ - -/* ########################### Core Function Access ########################### */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ -/* ARM armcc specific functions */ - - /** - * @brief Enable IRQ Interrupts - * - * Enables IRQ interrupts by clearing the I-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - /** - * @brief Disable IRQ Interrupts - * - * Disables IRQ interrupts by setting the I-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); */ - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_CONTROL(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_CONTROL(uint32_t control); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Get IPSR Register value - * - * @return uint32_t IPSR value - * - * return the content of the IPSR register - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_IPSR(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Get APSR Register value - * - * @return uint32_t APSR value - * - * return the content of the APSR register - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_APSR(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Get xPSR Register value - * - * @return uint32_t xPSR value - * - * return the content of the xPSR register - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_xPSR(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_PSP(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_PSP(uint32_t topOfProcStack); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_MSP(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_MSP(uint32_t topOfMainStack); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_MSP(uint32_t mainStackPointer) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = mainStackPointer; -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_PRIMASK(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_PRIMASK(uint32_t priMask); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} -#endif /* __ARMCC_VERSION */ - - -#if (__CORTEX_M >= 0x03) - - /** - * @brief Enable FIQ Interrupts - * - * Enables FIQ interrupts by clearing the F-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - /** - * @brief Disable FIQ Interrupts - * - * Disables FIQ interrupts by setting the F-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_BASEPRI(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_BASEPRI(uint32_t basePri); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xff); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -#if (__ARMCC_VERSION < 400000) -extern uint32_t __get_FAULTMASK(void); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -#if (__ARMCC_VERSION < 400000) -extern void __set_FAULTMASK(uint32_t faultMask); -#else /* (__ARMCC_VERSION >= 400000) */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & 1); -} -#endif /* __ARMCC_VERSION */ - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** - * @brief Return the FPSCR value - * - * @return FloatingPointStatusControlRegister - * - * Return the content of the FPSCR register - */ -static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0); -#endif -} - -/** - * @brief Set the FPSCR value - * - * @param fpscr FloatingPointStatusControlRegister - * - * Set the FPSCR register - */ -static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - - #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* IAR iccarm specific functions */ -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - -#pragma diag_suppress=Pe940 - - /** - * @brief Enable IRQ Interrupts - * - * Enables IRQ interrupts by clearing the I-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -#define __enable_irq __enable_interrupt - - /** - * @brief Disable IRQ Interrupts - * - * Disables IRQ interrupts by setting the I-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -#define __disable_irq __disable_interrupt - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */ - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */ - -/** - * @brief Get IPSR Register value - * - * @return uint32_t IPSR value - * - * return the content of the IPSR register - */ -static uint32_t __get_IPSR(void) -{ - __ASM("mrs r0, ipsr"); -} - -/** - * @brief Get APSR Register value - * - * @return uint32_t APSR value - * - * return the content of the APSR register - */ -/* __intrinsic unsigned long __get_APSR( void ); (see intrinsic.h) */ - -/** - * @brief Get xPSR Register value - * - * @return uint32_t xPSR value - * - * return the content of the xPSR register - */ -static uint32_t __get_xPSR(void) -{ - __ASM("mrs r0, psr"); // assembler does not know "xpsr" -} - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ - static uint32_t __get_PSP(void) -{ - __ASM("mrs r0, psp"); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -static void __set_PSP(uint32_t topOfProcStack) -{ - __ASM("msr psp, r0"); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -static uint32_t __get_MSP(void) -{ - __ASM("mrs r0, msp"); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -static void __set_MSP(uint32_t topOfMainStack) -{ - __ASM("msr msp, r0"); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */ - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */ - - -#if (__CORTEX_M >= 0x03) - - /** - * @brief Enable FIQ Interrupts - * - * Enables FIQ interrupts by clearing the F-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } - - /** - * @brief Disable FIQ Interrupts - * - * Disables FIQ interrupts by setting the F-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */ - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */ - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */ - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */ - -#endif /* (__CORTEX_M >= 0x03) */ - - -#if (__CORTEX_M == 0x04) - -/** - * @brief Return the FPSCR value - * - * @return FloatingPointStatusControlRegister - * - * Return the content of the FPSCR register - */ -static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) - /* not yet implemented */ - return(0); -#else - return(0); -#endif -} - -/** - * @brief Set the FPSCR value - * - * @param fpscr FloatingPointStatusControlRegister - * - * Set the FPSCR register - */ -static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) - /* not yet implemented */ -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - /** - * @brief Enable IRQ Interrupts - * - * Enables IRQ interrupts by clearing the I-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } - - /** - * @brief Disable IRQ Interrupts - * - * Disables IRQ interrupts by setting the I-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } - -/** - * @brief Return the Control Register value -* -* @return Control value - * - * Return the content of the control register - */ -static __INLINE uint32_t __get_CONTROL(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Control Register value - * - * @param control Control value - * - * Set the control register - */ -static __INLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) ); -} - -/** - * @brief Get IPSR Register value - * - * @return uint32_t IPSR value - * - * return the content of the IPSR register - */ -static __INLINE uint32_t __get_IPSR(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - -/** - * @brief Get APSR Register value - * - * @return uint32_t APSR value - * - * return the content of the APSR register - */ -static __INLINE uint32_t __get_APSR(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - -/** - * @brief Get xPSR Register value - * - * @return uint32_t xPSR value - * - * return the content of the xPSR register - */ -static __INLINE uint32_t __get_xPSR(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - -/** - * @brief Return the Process Stack Pointer - * - * @return ProcessStackPointer - * - * Return the actual process stack pointer - */ -static __INLINE uint32_t __get_PSP(void) __attribute__( ( naked ) ); -static __INLINE uint32_t __get_PSP(void) -{ - register uint32_t result __ASM ("r0") = 0; - - __ASM volatile ("MRS %0, psp\n" - "BX lr \n" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Process Stack Pointer - * - * @param topOfProcStack Process Stack Pointer - * - * Assign the value ProcessStackPointer to the MSP - * (process stack pointer) Cortex processor register - */ -static __INLINE void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); -static __INLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0\n" - "BX lr \n" : : "r" (topOfProcStack) ); -} - -/** - * @brief Return the Main Stack Pointer - * - * @return Main Stack Pointer - * - * Return the current value of the MSP (main stack pointer) - * Cortex processor register - */ -static __INLINE uint32_t __get_MSP(void) __attribute__( ( naked ) ); -static __INLINE uint32_t __get_MSP(void) -{ - register uint32_t result __ASM ("r0") = 0; - - __ASM volatile ("MRS %0, msp\n" - "BX lr \n" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Main Stack Pointer - * - * @param topOfMainStack Main Stack Pointer - * - * Assign the value mainStackPointer to the MSP - * (main stack pointer) Cortex processor register - */ -static __INLINE void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); -static __INLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0\n" - "BX lr \n" : : "r" (topOfMainStack) ); -} - -/** - * @brief Return the Priority Mask value - * - * @return PriMask - * - * Return state of the priority mask bit from the priority mask register - */ -static __INLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Priority Mask value - * - * @param priMask PriMask - * - * Set the priority mask bit in the priority mask register - */ -static __INLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); -} - - -#if (__CORTEX_M >= 0x03) - - /** - * @brief Enable FIQ Interrupts - * - * Enables FIQ interrupts by clearing the F-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } - - /** - * @brief Disable FIQ Interrupts - * - * Disables FIQ interrupts by setting the F-bit in the CPSR. - * Can only be executed in Privileged modes. - */ -static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } - -/** - * @brief Return the Base Priority value - * - * @return BasePriority - * - * Return the content of the base priority register - */ -static __INLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); - return(result); -} - -/** - * @brief Set the Base Priority value - * - * @param basePri BasePriority - * - * Set the base priority register - */ -static __INLINE void __set_BASEPRI(uint32_t value) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (value) ); -} - -/** - * @brief Return the Fault Mask value - * - * @return FaultMask - * - * Return the content of the fault mask register - */ -static __INLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result=0; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - -#endif /* (__CORTEX_M >= 0x03) */ - -/** - * @brief Set the Fault Mask value - * - * @param faultMask faultMask value - * - * Set the fault mask register - */ -static __INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); -} - - -#if (__CORTEX_M == 0x04) - -/** - * @brief Return the FPSCR value - * - * @return FloatingPointStatusControlRegister - * - * Return the content of the FPSCR register - */ -static __INLINE uint32_t __get_FPSCR(void) -{ -#if (__FPU_PRESENT == 1) - uint32_t result=0; - - __ASM volatile ("MRS %0, fpscr" : "=r" (result) ); - return(result); -#else - return(0); -#endif -} - -/** - * @brief Set the FPSCR value - * - * @param fpscr FloatingPointStatusControlRegister - * - * Set the FPSCR register - */ -static __INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if (__FPU_PRESENT == 1) - __ASM volatile ("MSR control, %0" : : "r" (fpscr) ); -#endif -} - -#endif /* (__CORTEX_M == 0x04) */ - - -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -#endif // __CORE_CMFUNC_H__ diff --git a/bsp/fm3/CMSIS/core_cmInstr.h b/bsp/fm3/CMSIS/core_cmInstr.h deleted file mode 100644 index 514cfb2385..0000000000 --- a/bsp/fm3/CMSIS/core_cmInstr.h +++ /dev/null @@ -1,684 +0,0 @@ -/**************************************************************************//** - * @file core_cmInstr.h - * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V1.40 - * @date 16. February 2010 - * - * @note - * Copyright (C) 2009-2010 ARM Limited. All rights reserved. - * - * @par - * ARM Limited (ARM) is supplying this software for use with Cortex-M - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * @par - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - -#ifndef __CORE_CMINSTR_H__ -#define __CORE_CMINSTR_H__ - -/* ########################## Core Instruction Access ######################### */ - -#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ -/* ARM armcc specific functions */ - - /** - * @brief No Operation - * - * No Operation does nothing. This instruction can be used for code alignment - * purposes. - */ -#define __NOP __nop - - /** - * @brief Wait For Interrupt - * - * Wait For Interrupt is a hint instruction that suspends execution until - * one of a number of events occurs. - */ -#define __WFI __wfi - - /** - * @brief Wait For Event - * - * Wait For Event is a hint instruction that permits the processor to enter - * a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - /** - * @brief Send Event - * - * Send Event is a hint instruction. It causes an event to be signaled - * to the CPU. - */ -#define __SEV __sev - - /** - * @brief Instruction Synchronization Barrier - * - * Instruction Synchronization Barrier flushes the pipeline in the processor, - * so that all instructions following the ISB are fetched from cache or - * memory, after the instruction has been completed - */ -#define __ISB() __isb(0xF) - - /** - * @brief Data Synchronization Barrier - * - * The DSB instruction operation acts as a special kind of Data Memory Barrier. - * The DSB operation completes when all explicit memory accesses before this - * instruction complete. - */ -#define __DSB() __dsb(0xF) - - /** - * @brief Data Memory Barrier - * - * DMB ensures the apparent order of the explicit memory operations before - * and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - -/** - * @brief Reverse byte order (32 bit) - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -#define __REV __rev - -/** - * @brief Reverse byte order (16 bit) - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -#if (__ARMCC_VERSION < 400677) -extern uint32_t __REV16(uint16_t value); -#else /* (__ARMCC_VERSION >= 400677) */ -static __INLINE __ASM uint32_t __REV16(uint16_t value) -{ - rev16 r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -#if (__ARMCC_VERSION < 400677) -extern int32_t __REVSH(int16_t value); -#else /* (__ARMCC_VERSION >= 400677) */ -static __INLINE __ASM int32_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} -#endif /* __ARMCC_VERSION */ - - -#if (__CORTEX_M >= 0x03) - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -#define __RBIT __rbit - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -#define __STREXB(value, ptr) __strex(value, ptr) - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -#define __STREXH(value, ptr) __strex(value, ptr) - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -#define __STREXW(value, ptr) __strex(value, ptr) - - /** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -#if (__ARMCC_VERSION < 400000) -extern void __CLREX(void); -#else /* (__ARMCC_VERSION >= 400000) */ -#define __CLREX __clrex -#endif /* __ARMCC_VERSION */ - -#endif /* (__CORTEX_M >= 0x03) */ - - -#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ -/* IAR iccarm specific functions */ -#if defined (__ICCARM__) - #include /* IAR Intrinsics */ -#endif - -#pragma diag_suppress=Pe940 - - /** - * @brief No Operation - * - * No Operation does nothing. This instruction can be used for code alignment - * purposes. - */ -#define __NOP __no_operation - - /** - * @brief Wait For Interrupt - * - * Wait For Interrupt is a hint instruction that suspends execution until - * one of a number of events occurs. - */ -static __INLINE void __WFI() { __ASM ("wfi"); } - - /** - * @brief Wait For Event - * - * Wait For Event is a hint instruction that permits the processor to enter - * a low-power state until one of a number of events occurs. - */ -static __INLINE void __WFE() { __ASM ("wfe"); } - - /** - * @brief Send Event - * - * Send Event is a hint instruction. It causes an event to be signaled - * to the CPU. - */ -static __INLINE void __SEV() { __ASM ("sev"); } - - /** - * @brief Instruction Synchronization Barrier - * - * Instruction Synchronization Barrier flushes the pipeline in the processor, - * so that all instructions following the ISB are fetched from cache or - * memory, after the instruction has been completed - */ -/* intrinsic void __ISB(void) (see intrinsics.h */ - - /** - * @brief Data Synchronization Barrier - * - * The DSB instruction operation acts as a special kind of Data Memory Barrier. - * The DSB operation completes when all explicit memory accesses before this - * instruction complete. - */ -/* intrinsic void __DSB(void) (see intrinsics.h */ - - /** - * @brief Data Memory Barrier - * - * DMB ensures the apparent order of the explicit memory operations before - * and after the instruction, without ensuring their completion. - */ -/* intrinsic void __DMB(void) (see intrinsics.h */ - -/** - * @brief Reverse byte order (32 bit) - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h */ - -/** - * @brief Reverse byte order (16 bit) - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -static uint32_t __REV16(uint16_t value) -{ - __ASM("rev16 r0, r0"); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */ - - -#if (__CORTEX_M >= 0x03) - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -static uint32_t __RBIT(uint32_t value) -{ - __ASM("rbit r0, r0"); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -static uint8_t __LDREXB(uint8_t *addr) -{ - __ASM("ldrexb r0, [r0]"); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -static uint16_t __LDREXH(uint16_t *addr) -{ - __ASM("ldrexh r0, [r0]"); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h */ -static uint32_t __LDREXW(uint32_t *addr) -{ - __ASM("ldrex r0, [r0]"); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -static uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - __ASM("strexb r0, r0, [r1]"); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -static uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - __ASM("strexh r0, r0, [r1]"); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h */ -static uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - __ASM("strex r0, r0, [r1]"); -} - - /** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -static __INLINE void __CLREX() { __ASM ("clrex"); } - -#endif /* (__CORTEX_M >= 0x03) */ - -#pragma diag_default=Pe940 - - -#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ -/* GNU gcc specific functions */ - - /** - * @brief No Operation - * - * No Operation does nothing. This instruction can be used for code alignment - * purposes. - */ -static __INLINE void __NOP() { __ASM volatile ("nop"); } - - /** - * @brief Wait For Interrupt - * - * Wait For Interrupt is a hint instruction that suspends execution until - * one of a number of events occurs. - */ -static __INLINE void __WFI() { __ASM volatile ("wfi"); } - - /** - * @brief Wait For Event - * - * Wait For Event is a hint instruction that permits the processor to enter - * a low-power state until one of a number of events occurs. - */ -static __INLINE void __WFE() { __ASM volatile ("wfe"); } - - /** - * @brief Send Event - * - * Send Event is a hint instruction. It causes an event to be signaled - * to the CPU. - */ -static __INLINE void __SEV() { __ASM volatile ("sev"); } - - /** - * @brief Instruction Synchronization Barrier - * - * Instruction Synchronization Barrier flushes the pipeline in the processor, - * so that all instructions following the ISB are fetched from cache or - * memory, after the instruction has been completed - */ -static __INLINE void __ISB() { __ASM volatile ("isb"); } - - /** - * @brief Data Synchronization Barrier - * - * The DSB instruction operation acts as a special kind of Data Memory Barrier. - * The DSB operation completes when all explicit memory accesses before this - * instruction complete. - */ -static __INLINE void __DSB() { __ASM volatile ("dsb"); } - - /** - * @brief Data Memory Barrier - * - * DMB ensures the apparent order of the explicit memory operations before - * and after the instruction, without ensuring their completion. - */ -static __INLINE void __DMB() { __ASM volatile ("dmb"); } - -/** - * @brief Reverse byte order (32 bit) - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in integer value - */ -static __INLINE uint32_t __REV(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order (16 bit) - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in unsigned short value - */ -static __INLINE uint32_t __REV16(uint16_t value) -{ - uint32_t result=0; - - __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief Reverse byte order in signed short value with sign extension to integer - * - * @param value value to reverse - * @return reversed value - * - * Reverse byte order in signed short value with sign extension to integer - */ -static __INLINE int32_t __REVSH(int16_t value) -{ - uint32_t result=0; - - __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - - -#if (__CORTEX_M >= 0x03) - -/** - * @brief Reverse bit order of value - * - * @param value value to reverse - * @return reversed value - * - * Reverse bit order of value - */ -static __INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result=0; - - __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); -} - -/** - * @brief LDR Exclusive (8 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 8 bit value - */ -static __INLINE uint8_t __LDREXB(uint8_t *addr) -{ - uint8_t result=0; - - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (16 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 16 bit values - */ -static __INLINE uint16_t __LDREXH(uint16_t *addr) -{ - uint16_t result=0; - - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief LDR Exclusive (32 bit) - * - * @param *addr address pointer - * @return value of (*address) - * - * Exclusive LDR command for 32 bit values - */ -static __INLINE uint32_t __LDREXW(uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); - return(result); -} - -/** - * @brief STR Exclusive (8 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 8 bit values - */ -static __INLINE uint32_t __STREXB(uint8_t value, uint8_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (16 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 16 bit values - */ -static __INLINE uint32_t __STREXH(uint16_t value, uint16_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - -/** - * @brief STR Exclusive (32 bit) - * - * @param value value to store - * @param *addr address pointer - * @return successful / failed - * - * Exclusive STR command for 32 bit values - */ -static __INLINE uint32_t __STREXW(uint32_t value, uint32_t *addr) -{ - uint32_t result=0; - - __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); - return(result); -} - - /** - * @brief Remove the exclusive lock created by ldrex - * - * Removes the exclusive lock which is created by ldrex. - */ -static __INLINE void __CLREX() { __ASM volatile ("clrex"); } - -#endif /* (__CORTEX_M >= 0x03) */ - - -#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ -/* TASKING carm specific functions */ - -/* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all instrinsics, - * Including the CMSIS ones. - */ - -#endif - -#endif // __CORE_CMINSTR_H__ diff --git a/bsp/fm3/CMSIS/mb9bf506r.h b/bsp/fm3/CMSIS/mb9bf506r.h deleted file mode 100644 index 3f0a9481c3..0000000000 --- a/bsp/fm3/CMSIS/mb9bf506r.h +++ /dev/null @@ -1,9739 +0,0 @@ -/************************************************************************/ -/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ -/* */ -/* The following software deliverable is intended for and must only be */ -/* used for reference and in an evaluation laboratory environment. */ -/* It is provided on an as-is basis without charge and is subject to */ -/* alterations. */ -/* It is the user's obligation to fully test the software in its */ -/* environment and to ensure proper functionality, qualification and */ -/* compliance with component specifications. */ -/* */ -/* In the event the software deliverable includes the use of open */ -/* source components, the provisions of the governing open source */ -/* license agreement shall apply with respect to such software */ -/* deliverable. */ -/* FSEU does not warrant that the deliverables do not infringe any */ -/* third party intellectual property right (IPR). In the event that */ -/* the deliverables infringe a third party IPR it is the sole */ -/* responsibility of the customer to obtain necessary licenses to */ -/* continue the usage of the deliverable. */ -/* */ -/* To the maximum extent permitted by applicable law FSEU disclaims all */ -/* warranties, whether express or implied, in particular, but not */ -/* limited to, warranties of merchantability and fitness for a */ -/* particular purpose for which the deliverable is not designated. */ -/* */ -/* To the maximum extent permitted by applicable law, FSEU's liability */ -/* is restricted to intentional misconduct and gross negligence. */ -/* FSEU is not liable for consequential damages. */ -/* */ -/* (V1.5) */ -/************************************************************************/ -/* */ -/* Header File for Device MB9BF506R */ -/* Version V1.00 */ -/* Date 2011-01-21 */ -/* */ -/************************************************************************/ - -#ifndef _MB9BF506R_H_ -#define _MB9BF506R_H_ - -#ifdef __cplusplus -extern "C" { -#endif - - -/****************************************************************************** - * Configuration of the Cortex-M3 Processor and Core Peripherals - ******************************************************************************/ -#define __MPU_PRESENT 1 /* FM3 provide an MPU */ -#define __NVIC_PRIO_BITS 4 /* FM3 uses 4 Bits for the Priority Levels */ -#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ - - -/****************************************************************************** - * Interrupt Number Definition - ******************************************************************************/ -typedef enum IRQn -{ - NMI_IRQn = -14, /* 2 Non Maskable */ - HardFault_IRQn = -13, /* 3 Hard Fault */ - MemManage_IRQn = -12, /* 4 Memory Management */ - BusFault_IRQn = -11, /* 5 Bus Fault */ - UsageFault_IRQn = -10, /* 6 Usage Fault */ - SVC_IRQn = -5, /* 11 SV Call */ - DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ - PendSVC_IRQn = -2, /* 14 Pend SV */ - SysTick_IRQn = -1, /* 15 System Tick */ - - CSV_IRQn = 0, /* Clock Super Visor */ - SWDT_IRQn = 1, /* Software Watchdog Timer */ - LVD_IRQn = 2, /* Low Voltage Detector */ - WFG_IRQn = 3, /* Wave Form Generator */ - EXINT0_7_IRQn = 4, /* External Interrupt Request ch.0 to ch.7 */ - EXINT8_15_IRQn = 5, /* External Interrupt Request ch.8 to ch.15 */ - DTIM_QDU_IRQn = 6, /* Dual Timer / Quad Decoder */ - MFS0RX_IRQn = 7, /* MultiFunction Serial ch.0 */ - MFS0TX_IRQn = 8, /* MultiFunction Serial ch.0 */ - MFS1RX_IRQn = 9, /* MultiFunction Serial ch.1 */ - MFS1TX_IRQn = 10, /* MultiFunction Serial ch.1 */ - MFS2RX_IRQn = 11, /* MultiFunction Serial ch.2 */ - MFS2TX_IRQn = 12, /* MultiFunction Serial ch.2 */ - MFS3RX_IRQn = 13, /* MultiFunction Serial ch.3 */ - MFS3TX_IRQn = 14, /* MultiFunction Serial ch.3 */ - MFS4RX_IRQn = 15, /* MultiFunction Serial ch.4 */ - MFS4TX_IRQn = 16, /* MultiFunction Serial ch.4 */ - MFS5RX_IRQn = 17, /* MultiFunction Serial ch.5 */ - MFS5TX_IRQn = 18, /* MultiFunction Serial ch.5 */ - MFS6RX_IRQn = 19, /* MultiFunction Serial ch.6 */ - MFS6TX_IRQn = 20, /* MultiFunction Serial ch.6 */ - MFS7RX_IRQn = 21, /* MultiFunction Serial ch.7 */ - MFS7TX_IRQn = 22, /* MultiFunction Serial ch.7 */ - PPG_IRQn = 23, /* PPG */ - OSC_PLL_WC_IRQn = 24, /* OSC / PLL / Watch Counter */ - ADC0_IRQn = 25, /* ADC0 */ - ADC1_IRQn = 26, /* ADC1 */ - ADC2_IRQn = 27, /* ADC2 */ - FRTIM_IRQn = 28, /* Free-run Timer */ - INCAP_IRQn = 29, /* Input Capture */ - OUTCOMP_IRQn = 30, /* Output Compare */ - BTIM_IRQn = 31, /* Base Timer ch.0 to ch.7 */ - CAN0_IRQn = 32, /* CAN ch.0 */ - CAN1_IRQn = 33, /* CAN ch.1 */ - USBF_IRQn = 34, /* USB Function */ - USBF_USBH_IRQn = 35, /* USB Function / USB HOST */ - /* Reserved = 36, */ - /* Reserved = 37, */ - DMAC0_IRQn = 38, /* DMAC ch.0 */ - DMAC1_IRQn = 39, /* DMAC ch.1 */ - DMAC2_IRQn = 40, /* DMAC ch.2 */ - DMAC3_IRQn = 41, /* DMAC ch.3 */ - DMAC4_IRQn = 42, /* DMAC ch.4 */ - DMAC5_IRQn = 43, /* DMAC ch.5 */ - DMAC6_IRQn = 44, /* DMAC ch.6 */ - DMAC7_IRQn = 45, /* DMAC ch.7 */ - /* Reserved = 46, */ - /* Reserved = 47, */ -} IRQn_Type; - - -#include "core_cm3.h" -#include "system_mb9bf50x.h" -#include - -#define SUCCESS 0 -#define ERROR -1 - -#ifndef NULL -#define NULL 0 -#endif - - -/******************************************************************************/ -/* Device Specific Peripheral Registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/****************************************************************************** - * Flash_IF_MODULE - ******************************************************************************/ -/* Flash interface registers */ -typedef struct -{ - __IO uint32_t FASZR; - __IO uint32_t FRWTR; - __IO uint32_t FSTR; - uint8_t RESERVED0[4]; - __IO uint32_t FSYNDN; - uint8_t RESERVED1[236]; - __IO uint32_t CRTRMM; -}FM3_FIF_TypeDef; - -/****************************************************************************** - * Clock_Reset_MODULE - ******************************************************************************/ -/* Clock and reset registers */ -typedef struct -{ - __IO uint8_t SCM_CTL; - uint8_t RESERVED0[3]; - __IO uint8_t SCM_STR; - uint8_t RESERVED1[3]; - __IO uint32_t STB_CTL; - __IO uint16_t RST_STR; - uint8_t RESERVED2[2]; - __IO uint8_t BSC_PSR; - uint8_t RESERVED3[3]; - __IO uint8_t APBC0_PSR; - uint8_t RESERVED4[3]; - __IO uint8_t APBC1_PSR; - uint8_t RESERVED5[3]; - __IO uint8_t APBC2_PSR; - uint8_t RESERVED6[3]; - __IO uint8_t SWC_PSR; - uint8_t RESERVED7[7]; - __IO uint8_t TTC_PSR; - uint8_t RESERVED8[7]; - __IO uint8_t CSW_TMR; - uint8_t RESERVED9[3]; - __IO uint8_t PSW_TMR; - uint8_t RESERVED10[3]; - __IO uint8_t PLL_CTL1; - uint8_t RESERVED11[3]; - __IO uint8_t PLL_CTL2; - uint8_t RESERVED12[3]; - __IO uint16_t CSV_CTL; - uint8_t RESERVED13[2]; - __IO uint8_t CSV_STR; - uint8_t RESERVED14[3]; - __IO uint16_t FCSWH_CTL; - uint8_t RESERVED15[2]; - __IO uint16_t FCSWL_CTL; - uint8_t RESERVED16[2]; - __IO uint16_t FCSWD_CTL; - uint8_t RESERVED17[2]; - __IO uint8_t DBWDT_CTL; - uint8_t RESERVED18[11]; - __IO uint8_t INT_ENR; - uint8_t RESERVED19[3]; - __IO uint8_t INT_STR; - uint8_t RESERVED20[3]; - __IO uint8_t INT_CLR; -}FM3_CRG_TypeDef; - -/****************************************************************************** - * HWWDT_MODULE - ******************************************************************************/ -/* Hardware watchdog registers */ -typedef struct -{ - __IO uint32_t WDG_LDR; - __IO uint32_t WDG_VLR; - __IO uint8_t WDG_CTL; - uint8_t RESERVED0[3]; - __IO uint8_t WDG_ICL; - uint8_t RESERVED1[3]; - __IO uint8_t WDG_RIS; - uint8_t RESERVED2[3055]; - __IO uint32_t WDG_LCK; -}FM3_HWWDT_TypeDef; - -/****************************************************************************** - * SWWDT_MODULE - ******************************************************************************/ -/* Software watchdog registers */ -typedef struct -{ - __IO uint32_t WDOGLOAD; - __IO uint32_t WDOGVALUE; - __IO uint8_t WDOGCONTROL; - uint8_t RESERVED0[3]; - __IO uint32_t WDOGINTCLR; - __IO uint8_t WDOGRIS; - uint8_t RESERVED1[3055]; - __IO uint32_t WDOGLOCK; -}FM3_SWWDT_TypeDef; - -/****************************************************************************** - * DTIM_MODULE - ******************************************************************************/ -/* Dual timer 1/2 registers */ -typedef struct -{ - __IO uint32_t TIMER1LOAD; - __IO uint32_t TIMER1VALUE; - __IO uint32_t TIMER1CONTROL; - __IO uint32_t TIMER1INTCLR; - __IO uint32_t TIMER1RIS; - __IO uint32_t TIMER1MIS; - __IO uint32_t TIMER1BGLOAD; - uint8_t RESERVED0[4]; - __IO uint32_t TIMER2LOAD; - __IO uint32_t TIMER2VALUE; - __IO uint32_t TIMER2CONTROL; - __IO uint32_t TIMER2INTCLR; - __IO uint32_t TIMER2RIS; - __IO uint32_t TIMER2MIS; - __IO uint32_t TIMER2BGLOAD; -}FM3_DTIM_TypeDef; - -/****************************************************************************** - * MFT_FRT_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Free Running Timer registers */ -typedef struct -{ - uint8_t RESERVED0[40]; - __IO uint16_t TCCP0; - uint8_t RESERVED1[2]; - __IO uint16_t TCDT0; - uint8_t RESERVED2[2]; - __IO uint16_t TCSA0; - uint8_t RESERVED3[2]; - __IO uint16_t TCSB0; - uint8_t RESERVED4[2]; - __IO uint16_t TCCP1; - uint8_t RESERVED5[2]; - __IO uint16_t TCDT1; - uint8_t RESERVED6[2]; - __IO uint16_t TCSA1; - uint8_t RESERVED7[2]; - __IO uint16_t TCSB1; - uint8_t RESERVED8[2]; - __IO uint16_t TCCP2; - uint8_t RESERVED9[2]; - __IO uint16_t TCDT2; - uint8_t RESERVED10[2]; - __IO uint16_t TCSA2; - uint8_t RESERVED11[2]; - __IO uint16_t TCSB2; -}FM3_MFT_FRT_TypeDef; - -/****************************************************************************** - * MFT_OCU_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Output Compare Unit registers */ -typedef struct -{ - __IO uint16_t OCCP0; - uint8_t RESERVED0[2]; - __IO uint16_t OCCP1; - uint8_t RESERVED1[2]; - __IO uint16_t OCCP2; - uint8_t RESERVED2[2]; - __IO uint16_t OCCP3; - uint8_t RESERVED3[2]; - __IO uint16_t OCCP4; - uint8_t RESERVED4[2]; - __IO uint16_t OCCP5; - uint8_t RESERVED5[2]; - __IO uint8_t OCSA10; - __IO uint8_t OCSB10; - uint8_t RESERVED6[2]; - __IO uint8_t OCSA32; - __IO uint8_t OCSB32; - uint8_t RESERVED7[2]; - __IO uint8_t OCSA54; - __IO uint8_t OCSB54; - uint8_t RESERVED8[3]; - __IO uint8_t OCSC; - uint8_t RESERVED9[50]; - __IO uint8_t OCFS10; - __IO uint8_t OCFS32; - uint8_t RESERVED10[2]; - __IO uint8_t OCFS54; -}FM3_MFT_OCU_TypeDef; - -/****************************************************************************** - * MFT_WFG_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -typedef struct -{ - uint8_t RESERVED0[128]; - __IO uint16_t WFTM10; - uint8_t RESERVED1[2]; - __IO uint16_t WFTM32; - uint8_t RESERVED2[2]; - __IO uint16_t WFTM54; - uint8_t RESERVED3[2]; - __IO uint16_t WFSA10; - uint8_t RESERVED4[2]; - __IO uint16_t WFSA32; - uint8_t RESERVED5[2]; - __IO uint16_t WFSA54; - uint8_t RESERVED6[2]; - __IO uint16_t WFIR; - uint8_t RESERVED7[2]; - __IO uint16_t NZCL; -}FM3_MFT_WFG_TypeDef; - -/****************************************************************************** - * MFT_ICU_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 Input Capture Unit registers */ -typedef struct -{ - uint8_t RESERVED0[96]; - __IO uint8_t ICFS10; - __IO uint8_t ICFS32; - uint8_t RESERVED1[6]; - __IO uint16_t ICCP0; - uint8_t RESERVED2[2]; - __IO uint16_t ICCP1; - uint8_t RESERVED3[2]; - __IO uint16_t ICCP2; - uint8_t RESERVED4[2]; - __IO uint16_t ICCP3; - uint8_t RESERVED5[2]; - __IO uint8_t ICSA10; - __IO uint8_t ICSB10; - uint8_t RESERVED6[2]; - __IO uint8_t ICSA32; - __IO uint8_t ICSB32; -}FM3_MFT_ICU_TypeDef; - -/****************************************************************************** - * MFT_ADCMP_MODULE - ******************************************************************************/ -/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -typedef struct -{ - uint8_t RESERVED0[160]; - __IO uint16_t ACCP0; - uint8_t RESERVED1[2]; - __IO uint16_t ACCPDN0; - uint8_t RESERVED2[2]; - __IO uint16_t ACCP1; - uint8_t RESERVED3[2]; - __IO uint16_t ACCPDN1; - uint8_t RESERVED4[2]; - __IO uint16_t ACCP2; - uint8_t RESERVED5[2]; - __IO uint16_t ACCPDN2; - uint8_t RESERVED6[2]; - __IO uint8_t ACSB; - uint8_t RESERVED7[3]; - __IO uint16_t ACSA; - uint8_t RESERVED8[2]; - __IO uint16_t ATSA; -}FM3_MFT_ADCMP_TypeDef; - -/****************************************************************************** - * MFT_PPG_MODULE - ******************************************************************************/ -/* Multifunction Timer PPG registers */ -typedef struct -{ - uint8_t RESERVED0; - __IO uint8_t TTCR0; - uint8_t RESERVED1[7]; - __IO uint8_t COMP0; - uint8_t RESERVED2[2]; - __IO uint8_t COMP2; - uint8_t RESERVED3[4]; - __IO uint8_t COMP4; - uint8_t RESERVED4[2]; - __IO uint8_t COMP6; - uint8_t RESERVED5[12]; - __IO uint8_t TTCR1; - uint8_t RESERVED6[7]; - __IO uint8_t COMP1; - uint8_t RESERVED7[2]; - __IO uint8_t COMP3; - uint8_t RESERVED8[4]; - __IO uint8_t COMP5; - uint8_t RESERVED9[2]; - __IO uint8_t COMP7; - uint8_t RESERVED10[203]; - __IO uint16_t TRG; - uint8_t RESERVED11[2]; - __IO uint16_t REVC; - uint8_t RESERVED12[250]; - __IO uint8_t PPGC1; - __IO uint8_t PPGC0; - uint8_t RESERVED13[2]; - __IO uint8_t PPGC3; - __IO uint8_t PPGC2; - uint8_t RESERVED14[2]; - union { - __IO uint16_t PRL0; - struct { - __IO uint8_t PRLL0; - __IO uint8_t PRLH0; - }; - }; - uint8_t RESERVED15[2]; - union { - __IO uint16_t PRL1; - struct { - __IO uint8_t PRLL1; - __IO uint8_t PRLH1; - }; - }; - uint8_t RESERVED16[2]; - union { - __IO uint16_t PRL2; - struct { - __IO uint8_t PRLL2; - __IO uint8_t PRLH2; - }; - }; - uint8_t RESERVED17[2]; - union { - __IO uint16_t PRL3; - struct { - __IO uint8_t PRLL3; - __IO uint8_t PRLH3; - }; - }; - uint8_t RESERVED18[2]; - __IO uint8_t GATEC0; - uint8_t RESERVED19[39]; - __IO uint8_t PPGC5; - __IO uint8_t PPGC4; - uint8_t RESERVED20[2]; - __IO uint8_t PPGC7; - __IO uint8_t PPGC6; - uint8_t RESERVED21[2]; - union { - __IO uint16_t PRL4; - struct { - __IO uint8_t PRLL4; - __IO uint8_t PRLH4; - }; - }; - uint8_t RESERVED22[2]; - union { - __IO uint16_t PRL5; - struct { - __IO uint8_t PRLL5; - __IO uint8_t PRLH5; - }; - }; - uint8_t RESERVED23[2]; - union { - __IO uint16_t PRL6; - struct { - __IO uint8_t PRLL6; - __IO uint8_t PRLH6; - }; - }; - uint8_t RESERVED24[2]; - union { - __IO uint16_t PRL7; - struct { - __IO uint8_t PRLL7; - __IO uint8_t PRLH7; - }; - }; - uint8_t RESERVED25[2]; - __IO uint8_t GATEC4; - uint8_t RESERVED26[39]; - __IO uint8_t PPGC9; - __IO uint8_t PPGC8; - uint8_t RESERVED27[2]; - __IO uint8_t PPGC11; - __IO uint8_t PPGC10; - uint8_t RESERVED28[2]; - union { - __IO uint16_t PRL8; - struct { - __IO uint8_t PRLL8; - __IO uint8_t PRLH8; - }; - }; - uint8_t RESERVED29[2]; - union { - __IO uint16_t PRL9; - struct { - __IO uint8_t PRLL9; - __IO uint8_t PRLH9; - }; - }; - uint8_t RESERVED30[2]; - union { - __IO uint16_t PRL10; - struct { - __IO uint8_t PRLL10; - __IO uint8_t PRLH10; - }; - }; - uint8_t RESERVED31[2]; - union { - __IO uint16_t PRL11; - struct { - __IO uint8_t PRLL11; - __IO uint8_t PRLH11; - }; - }; - uint8_t RESERVED32[2]; - __IO uint8_t GATEC8; - uint8_t RESERVED33[39]; - __IO uint8_t PPGC13; - __IO uint8_t PPGC12; - uint8_t RESERVED34[2]; - __IO uint8_t PPGC15; - __IO uint8_t PPGC14; - uint8_t RESERVED35[2]; - union { - __IO uint16_t PRL12; - struct { - __IO uint8_t PRLL12; - __IO uint8_t PRLH12; - }; - }; - uint8_t RESERVED36[2]; - union { - __IO uint16_t PRL13; - struct { - __IO uint8_t PRLL13; - __IO uint8_t PRLH13; - }; - }; - uint8_t RESERVED37[2]; - union { - __IO uint16_t PRL14; - struct { - __IO uint8_t PRLL14; - __IO uint8_t PRLH14; - }; - }; - uint8_t RESERVED38[2]; - union { - __IO uint16_t PRL15; - struct { - __IO uint8_t PRLL15; - __IO uint8_t PRLH15; - }; - }; - uint8_t RESERVED39[2]; - __IO uint8_t GATEC12; -}FM3_MFT_PPG_TypeDef; - -/****************************************************************************** - * BT_PPG_MODULE - ******************************************************************************/ -/* Base Timer 0 PPG registers */ -typedef struct -{ - __IO uint16_t PRLL; - uint8_t RESERVED0[2]; - __IO uint16_t PRLH; - uint8_t RESERVED1[2]; - __IO uint16_t TMR; - uint8_t RESERVED2[2]; - __IO uint16_t TMCR; - uint8_t RESERVED3[2]; - __IO uint8_t STC; - __IO uint8_t TMCR2; -}FM3_BT_PPG_TypeDef; - -/****************************************************************************** - * BT_PWM_MODULE - ******************************************************************************/ -/* Base Timer 0 PWM registers */ -typedef struct -{ - __IO uint16_t PCSR; - uint8_t RESERVED0[2]; - __IO uint16_t PDUT; - uint8_t RESERVED1[2]; - __IO uint16_t TMR; - uint8_t RESERVED2[2]; - __IO uint16_t TMCR; - uint8_t RESERVED3[2]; - __IO uint8_t STC; - __IO uint8_t TMCR2; -}FM3_BT_PWM_TypeDef; - -/****************************************************************************** - * BT_RT_MODULE - ******************************************************************************/ -/* Base Timer 0 RT registers */ -typedef struct -{ - __IO uint16_t PCSR; - uint8_t RESERVED0[6]; - __IO uint16_t TMR; - uint8_t RESERVED1[2]; - __IO uint16_t TMCR; - uint8_t RESERVED2[2]; - __IO uint8_t STC; - __IO uint8_t TMCR2; -}FM3_BT_RT_TypeDef; - -/****************************************************************************** - * BT_PWC_MODULE - ******************************************************************************/ -/* Base Timer 0 PWC registers */ -typedef struct -{ - uint8_t RESERVED0[4]; - __IO uint16_t DTBF; - uint8_t RESERVED1[6]; - __IO uint16_t TMCR; - uint8_t RESERVED2[2]; - __IO uint8_t STC; - __IO uint8_t TMCR2; -}FM3_BT_PWC_TypeDef; - -/****************************************************************************** - * BTIOSEL03_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 0 - channel 3 registers */ -typedef struct -{ - uint8_t RESERVED0; - __IO uint8_t BTSEL0123; -}FM3_BTIOSEL03_TypeDef; - -/****************************************************************************** - * BTIOSEL47_MODULE - ******************************************************************************/ -/* Base Timer I/O selector channel 4 - channel 7 registers */ -typedef struct -{ - uint8_t RESERVED0; - __IO uint8_t BTSEL4567; -}FM3_BTIOSEL47_TypeDef; - -/****************************************************************************** - * SBSSR_MODULE - ******************************************************************************/ -/* Software based Simulation Startup (Base Timer) register */ -typedef struct -{ - __IO uint16_t BTSSSR; -}FM3_SBSSR_TypeDef; - -/****************************************************************************** - * QPRC_MODULE - ******************************************************************************/ -/* Quad position and revolution counter channel 0 registers */ -typedef struct -{ - __IO uint16_t QPCR; - uint8_t RESERVED0[2]; - __IO uint16_t QRCR; - uint8_t RESERVED1[2]; - __IO uint16_t QPCCR; - uint8_t RESERVED2[2]; - __IO uint16_t QPRCR; - uint8_t RESERVED3[2]; - __IO uint16_t QMPR; - uint8_t RESERVED4[2]; - union { - __IO uint16_t QICR; - struct { - __IO uint8_t QICRL; - __IO uint8_t QICRH; - }; - }; - uint8_t RESERVED5[2]; - union { - __IO uint16_t QCR; - struct { - __IO uint8_t QCRL; - __IO uint8_t QCRH; - }; - }; - uint8_t RESERVED6[2]; - __IO uint16_t QECR; -}FM3_QPRC_TypeDef; - -/****************************************************************************** - * ADC12_MODULE - ******************************************************************************/ -/* 12-bit ADC unit 0 registers */ -typedef struct -{ - __IO uint8_t ADSR; - __IO uint8_t ADCR; - uint8_t RESERVED0[6]; - __IO uint8_t SFNS; - __IO uint8_t SCCR; - uint8_t RESERVED1[2]; - union { - __IO uint32_t SCFD; - struct { - __IO uint16_t SCFDL; - __IO uint16_t SCFDH; - }; - }; - union { - __IO uint16_t SCIS23; - struct { - __IO uint8_t SCIS2; - __IO uint8_t SCIS3; - }; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t SCIS01; - struct { - __IO uint8_t SCIS0; - __IO uint8_t SCIS1; - }; - }; - uint8_t RESERVED3[2]; - __IO uint8_t PFNS; - __IO uint8_t PCCR; - uint8_t RESERVED4[2]; - union { - __IO uint32_t PCFD; - struct { - __IO uint16_t PCFDL; - __IO uint16_t PCFDH; - }; - }; - __IO uint8_t PCIS; - uint8_t RESERVED5[3]; - __IO uint8_t CMPCR; - uint8_t RESERVED6; - __IO uint16_t CMPD; - union { - __IO uint16_t ADSS23; - struct { - __IO uint8_t ADSS2; - __IO uint8_t ADSS3; - }; - }; - uint8_t RESERVED7[2]; - union { - __IO uint16_t ADSS01; - struct { - __IO uint8_t ADSS0; - __IO uint8_t ADSS1; - }; - }; - uint8_t RESERVED8[2]; - union { - __IO uint16_t ADST01; - struct { - __IO uint8_t ADST1; - __IO uint8_t ADST0; - }; - }; - uint8_t RESERVED9[2]; - __IO uint8_t ADCT; - uint8_t RESERVED10[3]; - __IO uint8_t PRTSL; - __IO uint8_t SCTSL; - uint8_t RESERVED11[2]; - __IO uint8_t ADCEN; -}FM3_ADC_TypeDef; - -/****************************************************************************** - * CRTRIM_MODULE - ******************************************************************************/ -/* CR trimming registers */ -typedef struct -{ - __IO uint8_t MCR_PSR; - uint8_t RESERVED0[3]; - __IO uint16_t MCR_FTRM; - uint8_t RESERVED1[6]; - __IO uint32_t MCR_RLR; -}FM3_CRTRIM_TypeDef; - -/****************************************************************************** - * EXTI_MODULE - ******************************************************************************/ -/* External interrupt registers */ -typedef struct -{ - __IO uint16_t ENIR; - uint8_t RESERVED0[2]; - __IO uint16_t EIRR; - uint8_t RESERVED1[2]; - __IO uint16_t EICL; - uint8_t RESERVED2[2]; - __IO uint32_t ELVR; - uint8_t RESERVED3[4]; - __IO uint8_t NMIRR; - uint8_t RESERVED4[3]; - __IO uint8_t NMICL; -}FM3_EXTI_TypeDef; - -/****************************************************************************** - * INTREQ_MODULE - ******************************************************************************/ -/* Interrupt request read registers */ -typedef struct -{ - __IO uint32_t DRQSEL; - uint8_t RESERVED0[12]; - __IO uint32_t EXC02MON; - __IO uint32_t IRQ00MON; - __IO uint32_t IRQ01MON; - __IO uint32_t IRQ02MON; - __IO uint32_t IRQ03MON; - __IO uint32_t IRQ04MON; - __IO uint32_t IRQ05MON; - __IO uint32_t IRQ06MON; - __IO uint32_t IRQ07MON; - __IO uint32_t IRQ08MON; - __IO uint32_t IRQ09MON; - __IO uint32_t IRQ10MON; - __IO uint32_t IRQ11MON; - __IO uint32_t IRQ12MON; - __IO uint32_t IRQ13MON; - __IO uint32_t IRQ14MON; - __IO uint32_t IRQ15MON; - __IO uint32_t IRQ16MON; - __IO uint32_t IRQ17MON; - __IO uint32_t IRQ18MON; - __IO uint32_t IRQ19MON; - __IO uint32_t IRQ20MON; - __IO uint32_t IRQ21MON; - __IO uint32_t IRQ22MON; - __IO uint32_t IRQ23MON; - __IO uint32_t IRQ24MON; - __IO uint32_t IRQ25MON; - __IO uint32_t IRQ26MON; - __IO uint32_t IRQ27MON; - __IO uint32_t IRQ28MON; - __IO uint32_t IRQ29MON; - __IO uint32_t IRQ30MON; - __IO uint32_t IRQ31MON; - __IO uint32_t IRQ32MON; - __IO uint32_t IRQ33MON; - __IO uint32_t IRQ34MON; - __IO uint32_t IRQ35MON; - __IO uint32_t IRQ36MON; - __IO uint32_t IRQ37MON; - __IO uint32_t IRQ38MON; - __IO uint32_t IRQ39MON; - __IO uint32_t IRQ40MON; - __IO uint32_t IRQ41MON; - __IO uint32_t IRQ42MON; - __IO uint32_t IRQ43MON; - __IO uint32_t IRQ44MON; - __IO uint32_t IRQ45MON; - __IO uint32_t IRQ46MON; - __IO uint32_t IRQ47MON; -}FM3_INTREQ_TypeDef; - -/****************************************************************************** - * GPIO_MODULE - ******************************************************************************/ -/* General purpose I/O registers */ -typedef struct -{ - __IO uint32_t PFR0; - __IO uint32_t PFR1; - __IO uint32_t PFR2; - __IO uint32_t PFR3; - __IO uint32_t PFR4; - __IO uint32_t PFR5; - __IO uint32_t PFR6; - __IO uint32_t PFR7; - __IO uint32_t PFR8; - uint8_t RESERVED0[220]; - __IO uint32_t PCR0; - __IO uint32_t PCR1; - __IO uint32_t PCR2; - __IO uint32_t PCR3; - __IO uint32_t PCR4; - __IO uint32_t PCR5; - __IO uint32_t PCR6; - __IO uint32_t PCR7; - uint8_t RESERVED1[224]; - __IO uint32_t DDR0; - __IO uint32_t DDR1; - __IO uint32_t DDR2; - __IO uint32_t DDR3; - __IO uint32_t DDR4; - __IO uint32_t DDR5; - __IO uint32_t DDR6; - __IO uint32_t DDR7; - __IO uint32_t DDR8; - uint8_t RESERVED2[220]; - __IO uint32_t PDIR0; - __IO uint32_t PDIR1; - __IO uint32_t PDIR2; - __IO uint32_t PDIR3; - __IO uint32_t PDIR4; - __IO uint32_t PDIR5; - __IO uint32_t PDIR6; - __IO uint32_t PDIR7; - __IO uint32_t PDIR8; - uint8_t RESERVED3[220]; - __IO uint32_t PDOR0; - __IO uint32_t PDOR1; - __IO uint32_t PDOR2; - __IO uint32_t PDOR3; - __IO uint32_t PDOR4; - __IO uint32_t PDOR5; - __IO uint32_t PDOR6; - __IO uint32_t PDOR7; - __IO uint32_t PDOR8; - uint8_t RESERVED4[220]; - __IO uint32_t ADE; - uint8_t RESERVED5[124]; - __IO uint32_t SPSR; - uint8_t RESERVED6[124]; - __IO uint32_t EPFR00; - __IO uint32_t EPFR01; - __IO uint32_t EPFR02; - uint8_t RESERVED7[4]; - __IO uint32_t EPFR04; - __IO uint32_t EPFR05; - __IO uint32_t EPFR06; - __IO uint32_t EPFR07; - __IO uint32_t EPFR08; - __IO uint32_t EPFR09; - __IO uint32_t EPFR10; -}FM3_GPIO_TypeDef; - -/****************************************************************************** - * LVD_MODULE - ******************************************************************************/ -/* Low voltage detection registers */ -typedef struct -{ - __IO uint8_t LVD_CTL; - uint8_t RESERVED0[3]; - __IO uint8_t LVD_STR; - uint8_t RESERVED1[3]; - __IO uint8_t LVD_CLR; - uint8_t RESERVED2[3]; - __IO uint32_t LVD_RLR; - __IO uint8_t LVD_STR2; -}FM3_LVD_TypeDef; - -/****************************************************************************** - * USBCLK - ******************************************************************************/ -/* USB clock registers */ -typedef struct -{ - __IO uint8_t UCCR; - uint8_t RESERVED0[3]; - __IO uint8_t UPCR1; - uint8_t RESERVED1[3]; - __IO uint8_t UPCR2; - uint8_t RESERVED2[3]; - __IO uint8_t UPCR3; - uint8_t RESERVED3[3]; - __IO uint8_t UPCR4; - uint8_t RESERVED4[3]; - __IO uint8_t UP_STR; - uint8_t RESERVED5[3]; - __IO uint8_t UPINT_ENR; - uint8_t RESERVED6[3]; - __IO uint8_t UPINT_CLR; - uint8_t RESERVED7[3]; - __IO uint8_t UPINT_STR; - uint8_t RESERVED8[15]; - __IO uint8_t USBEN; -}FM3_USBCLK_TypeDef; - -/****************************************************************************** - * CANPRE_MODULE - ******************************************************************************/ -/* CAN prescaler register */ -typedef struct -{ - __IO uint8_t CANPRE; -}FM3_CANPRE_TypeDef; - -/****************************************************************************** - * MFS03_UART_MODULE - ******************************************************************************/ -/* UART asynchronous channel 0 registers */ -typedef struct -{ - __IO uint8_t SMR; - __IO uint8_t SCR; - uint8_t RESERVED0[2]; - __IO uint8_t ESCR; - __IO uint8_t SSR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; -}FM3_MFS03_UART_TypeDef; - -/****************************************************************************** - * MFS03_CSIO_MODULE - ******************************************************************************/ -/* UART synchronous channel 0 registers */ -typedef struct -{ - __IO uint8_t SMR; - __IO uint8_t SCR; - uint8_t RESERVED0[2]; - __IO uint8_t ESCR; - __IO uint8_t SSR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; -}FM3_MFS03_CSIO_TypeDef; - -/****************************************************************************** - * MFS03_LIN_MODULE - ******************************************************************************/ -/* UART LIN channel 0 registers */ -typedef struct -{ - __IO uint8_t SMR; - __IO uint8_t SCR; - uint8_t RESERVED0[2]; - __IO uint8_t ESCR; - __IO uint8_t SSR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; -}FM3_MFS03_LIN_TypeDef; - -/****************************************************************************** - * MFS03_I2C_MODULE - ******************************************************************************/ -/* I2C channel 0 registers */ -typedef struct -{ - __IO uint8_t SMR; - __IO uint8_t IBCR; - uint8_t RESERVED0[2]; - __IO uint8_t IBSR; - __IO uint8_t SSR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[2]; - __IO uint8_t ISBA; - __IO uint8_t ISMK; -}FM3_MFS03_I2C_TypeDef; - -/****************************************************************************** - * MFS47_UART_MODULE - ******************************************************************************/ -/* UART asynchronous channel 4 registers */ -typedef struct -{ - __IO uint8_t SMR; - __IO uint8_t SCR; - uint8_t RESERVED0[2]; - __IO uint8_t ESCR; - __IO uint8_t SSR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[6]; - union { - __IO uint16_t FCR; - struct { - __IO uint8_t FCR0; - __IO uint8_t FCR1; - }; - }; - uint8_t RESERVED4[2]; - union { - __IO uint16_t FBYTE; - struct { - __IO uint8_t FBYTE1; - __IO uint8_t FBYTE2; - }; - }; -}FM3_MFS47_UART_TypeDef; - -/****************************************************************************** - * MFS47_CSIO_MODULE - ******************************************************************************/ -/* UART synchronous channel 4 registers */ -typedef struct -{ - __IO uint8_t SMR; - __IO uint8_t SCR; - uint8_t RESERVED0[2]; - __IO uint8_t ESCR; - __IO uint8_t SSR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[6]; - union { - __IO uint16_t FCR; - struct { - __IO uint8_t FCR0; - __IO uint8_t FCR1; - }; - }; - uint8_t RESERVED4[2]; - union { - __IO uint16_t FBYTE; - struct { - __IO uint8_t FBYTE1; - __IO uint8_t FBYTE2; - }; - }; -}FM3_MFS47_CSIO_TypeDef; - -/****************************************************************************** - * MFS47_LIN_MODULE - ******************************************************************************/ -/* UART LIN channel 4 registers */ -typedef struct -{ - __IO uint8_t SMR; - __IO uint8_t SCR; - uint8_t RESERVED0[2]; - __IO uint8_t ESCR; - __IO uint8_t SSR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[6]; - union { - __IO uint16_t FCR; - struct { - __IO uint8_t FCR0; - __IO uint8_t FCR1; - }; - }; - uint8_t RESERVED4[2]; - union { - __IO uint16_t FBYTE; - struct { - __IO uint8_t FBYTE1; - __IO uint8_t FBYTE2; - }; - }; -}FM3_MFS47_LIN_TypeDef; - -/****************************************************************************** - * MFS47_I2C_MODULE - ******************************************************************************/ -/* I2C channel 4 registers */ -typedef struct -{ - __IO uint8_t SMR; - __IO uint8_t IBCR; - uint8_t RESERVED0[2]; - __IO uint8_t IBSR; - __IO uint8_t SSR; - uint8_t RESERVED1[2]; - union { - __IO uint16_t RDR; - __IO uint16_t TDR; - }; - uint8_t RESERVED2[2]; - union { - __IO uint16_t BGR; - struct { - __IO uint8_t BGR0; - __IO uint8_t BGR1; - }; - }; - uint8_t RESERVED3[2]; - __IO uint8_t ISBA; - __IO uint8_t ISMK; - uint8_t RESERVED4[2]; - union { - __IO uint16_t FCR; - struct { - __IO uint8_t FCR0; - __IO uint8_t FCR1; - }; - }; - uint8_t RESERVED5[2]; - union { - __IO uint16_t FBYTE; - struct { - __IO uint8_t FBYTE1; - __IO uint8_t FBYTE2; - }; - }; -}FM3_MFS47_I2C_TypeDef; - -/****************************************************************************** - * CRC_MODULE - ******************************************************************************/ -/* CRC registers */ -typedef struct -{ - __IO uint8_t CRCCR; - uint8_t RESERVED0[3]; - __IO uint32_t CRCINIT; - union { - __IO uint32_t CRCIN; - struct { - union { - __IO uint16_t CRCINL; - struct { - __IO uint8_t CRCINLL; - __IO uint8_t CRCINLH; - }; - }; - union { - __IO uint16_t CRCINH; - struct { - __IO uint8_t CRCINHL; - __IO uint8_t CRCINHH; - }; - }; - }; - }; - __IO uint32_t CRCR; -}FM3_CRC_TypeDef; - -/****************************************************************************** - * WC_MODULE - ******************************************************************************/ -/* Watch counter registers */ -typedef struct -{ - __IO uint8_t WCRD; - __IO uint8_t WCRL; - __IO uint8_t WCCR; - uint8_t RESERVED0[13]; - __IO uint16_t CLK_SEL; - uint8_t RESERVED1[2]; - __IO uint8_t CLK_EN; -}FM3_WC_TypeDef; - -/****************************************************************************** - * EXBUS_MODULE - ******************************************************************************/ -/* External bus interface registers */ -typedef struct -{ - __IO uint32_t MODE0; - __IO uint32_t MODE1; - __IO uint32_t MODE2; - __IO uint32_t MODE3; - __IO uint32_t MODE4; - __IO uint32_t MODE5; - __IO uint32_t MODE6; - __IO uint32_t MODE7; - __IO uint32_t TIM0; - __IO uint32_t TIM1; - __IO uint32_t TIM2; - __IO uint32_t TIM3; - __IO uint32_t TIM4; - __IO uint32_t TIM5; - __IO uint32_t TIM6; - __IO uint32_t TIM7; - __IO uint32_t AREA0; - __IO uint32_t AREA1; - __IO uint32_t AREA2; - __IO uint32_t AREA3; - __IO uint32_t AREA4; - __IO uint32_t AREA5; - __IO uint32_t AREA6; - __IO uint32_t AREA7; -}FM3_EXBUS_TypeDef; - -/****************************************************************************** - * USB_MODULE - ******************************************************************************/ -/* USB channel 0 registers */ -typedef struct -{ - union { - __IO uint16_t HCNT; - struct { - __IO uint8_t HCNT0; - __IO uint8_t HCNT1; - }; - }; - uint8_t RESERVED0[2]; - __IO uint8_t HIRQ; - __IO uint8_t HERR; - uint8_t RESERVED1[2]; - __IO uint8_t HSTATE; - __IO uint8_t HFCOMP; - uint8_t RESERVED2[2]; - union { - __IO uint16_t HRTIMER; - struct { - __IO uint8_t HRTIMER0; - __IO uint8_t HRTIMER1; - }; - }; - uint8_t RESERVED3[2]; - __IO uint8_t HRTIMER2; - __IO uint8_t HADR; - uint8_t RESERVED4[2]; - union { - __IO uint16_t HEOF; - struct { - __IO uint8_t HEOF0; - __IO uint8_t HEOF1; - }; - }; - uint8_t RESERVED5[2]; - union { - __IO uint16_t HFRAME; - struct { - __IO uint8_t HFRAME0; - __IO uint8_t HFRAME1; - }; - }; - uint8_t RESERVED6[2]; - __IO uint8_t HTOKEN; - uint8_t RESERVED7[3]; - __IO uint16_t UDCC; - uint8_t RESERVED8[2]; - __IO uint16_t EP0C; - uint8_t RESERVED9[2]; - __IO uint16_t EP1C; - uint8_t RESERVED10[2]; - __IO uint16_t EP2C; - uint8_t RESERVED11[2]; - __IO uint16_t EP3C; - uint8_t RESERVED12[2]; - __IO uint16_t EP4C; - uint8_t RESERVED13[2]; - __IO uint16_t EP5C; - uint8_t RESERVED14[2]; - __IO uint16_t TMSP; - uint8_t RESERVED15[2]; - __IO uint8_t UDCS; - __IO uint8_t UDCIE; - uint8_t RESERVED16[2]; - __IO uint16_t EP0IS; - uint8_t RESERVED17[2]; - __IO uint16_t EP0OS; - uint8_t RESERVED18[2]; - __IO uint16_t EP1S; - uint8_t RESERVED19[2]; - __IO uint16_t EP2S; - uint8_t RESERVED20[2]; - __IO uint16_t EP3S; - uint8_t RESERVED21[2]; - __IO uint16_t EP4S; - uint8_t RESERVED22[2]; - __IO uint16_t EP5S; - uint8_t RESERVED23[2]; - union { - __IO uint16_t EP0DT; - struct { - __IO uint8_t EP0DTL; - __IO uint8_t EP0DTH; - }; - }; - uint8_t RESERVED24[2]; - union { - __IO uint16_t EP1DT; - struct { - __IO uint8_t EP1DTL; - __IO uint8_t EP1DTH; - }; - }; - uint8_t RESERVED25[2]; - union { - __IO uint16_t EP2DT; - struct { - __IO uint8_t EP2DTL; - __IO uint8_t EP2DTH; - }; - }; - uint8_t RESERVED26[2]; - union { - __IO uint16_t EP3DT; - struct { - __IO uint8_t EP3DTL; - __IO uint8_t EP3DTH; - }; - }; - uint8_t RESERVED27[2]; - union { - __IO uint16_t EP4DT; - struct { - __IO uint8_t EP4DTL; - __IO uint8_t EP4DTH; - }; - }; - uint8_t RESERVED28[2]; - union { - __IO uint16_t EP5DT; - struct { - __IO uint8_t EP5DTL; - __IO uint8_t EP5DTH; - }; - }; -}FM3_USB_TypeDef; - -/****************************************************************************** - * DMAC_MODULE - ******************************************************************************/ -/* DMA controller */ -typedef struct -{ - __IO uint32_t DMACR; - uint8_t RESERVED0[12]; - __IO uint32_t DMACA0; - __IO uint32_t DMACB0; - __IO uint32_t DMACSA0; - __IO uint32_t DMACDA0; - __IO uint32_t DMACA1; - __IO uint32_t DMACB1; - __IO uint32_t DMACSA1; - __IO uint32_t DMACDA1; - __IO uint32_t DMACA2; - __IO uint32_t DMACB2; - __IO uint32_t DMACSA2; - __IO uint32_t DMACDA2; - __IO uint32_t DMACA3; - __IO uint32_t DMACB3; - __IO uint32_t DMACSA3; - __IO uint32_t DMACDA3; - __IO uint32_t DMACA4; - __IO uint32_t DMACB4; - __IO uint32_t DMACSA4; - __IO uint32_t DMACDA4; - __IO uint32_t DMACA5; - __IO uint32_t DMACB5; - __IO uint32_t DMACSA5; - __IO uint32_t DMACDA5; - __IO uint32_t DMACA6; - __IO uint32_t DMACB6; - __IO uint32_t DMACSA6; - __IO uint32_t DMACDA6; - __IO uint32_t DMACA7; - __IO uint32_t DMACB7; - __IO uint32_t DMACSA7; - __IO uint32_t DMACDA7; -}FM3_DMAC_TypeDef; - -/****************************************************************************** - * CAN_MODULE - ******************************************************************************/ -/* CAN channel 0 registers */ -typedef struct -{ - __IO uint16_t CTRLR; - __IO uint16_t STATR; - __IO uint16_t ERRCNT; - __IO uint16_t BTR; - __IO uint16_t INTR; - __IO uint16_t TESTR; - __IO uint16_t BRPER; - uint8_t RESERVED0[2]; - __IO uint16_t IF1CREQ; - __IO uint16_t IF1CMSK; - union { - __IO uint32_t IF1MSK; - struct { - __IO uint16_t IF1MSK1; - __IO uint16_t IF1MSK2; - }; - }; - union { - __IO uint32_t IF1ARB; - struct { - __IO uint16_t IF1ARB1; - __IO uint16_t IF1ARB2; - }; - }; - __IO uint16_t IF1MCTR; - uint8_t RESERVED1[2]; - union { - __IO uint32_t IF1DTA_L; - struct { - __IO uint16_t IF1DTA1_L; - __IO uint16_t IF1DTA2_L; - }; - }; - union { - __IO uint32_t IF1DTB_L; - struct { - __IO uint16_t IF1DTB1_L; - __IO uint16_t IF1DTB2_L; - }; - }; - uint8_t RESERVED2[8]; - union { - __IO uint32_t IF1DTA_B; - struct { - __IO uint16_t IF1DTA2_B; - __IO uint16_t IF1DTA1_B; - }; - }; - union { - __IO uint32_t IF1DTB_B; - struct { - __IO uint16_t IF1DTB2_B; - __IO uint16_t IF1DTB1_B; - }; - }; - uint8_t RESERVED3[8]; - __IO uint16_t IF2CREQ; - __IO uint16_t IF2CMSK; - union { - __IO uint32_t IF2MSK; - struct { - __IO uint16_t IF2MSK1; - __IO uint16_t IF2MSK2; - }; - }; - union { - __IO uint32_t IF2ARB; - struct { - __IO uint16_t IF2ARB1; - __IO uint16_t IF2ARB2; - }; - }; - __IO uint16_t IF2MCTR; - uint8_t RESERVED4[2]; - union { - __IO uint32_t IF2DTA_L; - struct { - __IO uint16_t IF2DTA1_L; - __IO uint16_t IF2DTA2_L; - }; - }; - union { - __IO uint32_t IF2DTB_L; - struct { - __IO uint16_t IF2DTB1_L; - __IO uint16_t IF2DTB2_L; - }; - }; - uint8_t RESERVED5[8]; - union { - __IO uint32_t IF2DTA_B; - struct { - __IO uint16_t IF2DTA2_B; - __IO uint16_t IF2DTA1_B; - }; - }; - union { - __IO uint32_t IF2DTB_B; - struct { - __IO uint16_t IF2DTB2_B; - __IO uint16_t IF2DTB1_B; - }; - }; - uint8_t RESERVED6[24]; - union { - __IO uint32_t TREQR; - struct { - __IO uint16_t TREQR1; - __IO uint16_t TREQR2; - }; - }; - uint8_t RESERVED7[12]; - union { - __IO uint32_t NEWDT; - struct { - __IO uint16_t NEWDT1; - __IO uint16_t NEWDT2; - }; - }; - uint8_t RESERVED8[12]; - union { - __IO uint32_t INTPND; - struct { - __IO uint16_t INTPND1; - __IO uint16_t INTPND2; - }; - }; - uint8_t RESERVED9[12]; - union { - __IO uint32_t MSGVAL; - struct { - __IO uint16_t MSGVAL1; - __IO uint16_t MSGVAL2; - }; - }; -}FM3_CAN_TypeDef; - - -/****************************************************************************** - * Peripheral memory map - ******************************************************************************/ -#define FM3_FLASH_BASE (0x00000000UL) /* Flash Base */ -#define FM3_PERIPH_BASE (0x40000000UL) /* Peripheral Base */ -#define FM3_CM3_BASE (0xE0100000UL) /* CM3 Private */ - -#define FM3_FLASH_IF_BASE (FM3_PERIPH_BASE + 0x00000UL) /* Flash interface registers */ -#define FM3_CRG_BASE (FM3_PERIPH_BASE + 0x10000UL) /* Clock and reset registers */ -#define FM3_HWWDT_BASE (FM3_PERIPH_BASE + 0x11000UL) /* Hardware watchdog registers */ -#define FM3_SWWDT_BASE (FM3_PERIPH_BASE + 0x12000UL) /* Software watchdog registers */ -#define FM3_DTIM_BASE (FM3_PERIPH_BASE + 0x15000UL) /* Dual timer 1/2 registers */ -#define FM3_MFT0_FRT_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Free Running Timer registers */ -#define FM3_MFT0_OCU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Output Compare Unit registers */ -#define FM3_MFT0_WFG_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -#define FM3_MFT0_ICU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Input Capture Unit registers */ -#define FM3_MFT0_ADCMP_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -#define FM3_MFT1_FRT_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Free Running Timer registers */ -#define FM3_MFT1_OCU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Output Compare Unit registers */ -#define FM3_MFT1_WFG_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ -#define FM3_MFT1_ICU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Input Capture Unit registers */ -#define FM3_MFT1_ADCMP_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 ADC Start Compare Unit registers */ -#define FM3_MFT_PPG_BASE (FM3_PERIPH_BASE + 0x24000UL) /* Multifunction Timer PPG registers */ -#define FM3_BT0_PPG_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PPG registers */ -#define FM3_BT0_PWM_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWM registers */ -#define FM3_BT0_RT_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 RT registers */ -#define FM3_BT0_PWC_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWC registers */ -#define FM3_BT1_PPG_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PPG registers */ -#define FM3_BT1_PWM_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWM registers */ -#define FM3_BT1_RT_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 RT registers */ -#define FM3_BT1_PWC_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWC registers */ -#define FM3_BT2_PPG_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PPG registers */ -#define FM3_BT2_PWM_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWM registers */ -#define FM3_BT2_RT_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 RT registers */ -#define FM3_BT2_PWC_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWC registers */ -#define FM3_BT3_PPG_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PPG registers */ -#define FM3_BT3_PWM_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWM registers */ -#define FM3_BT3_RT_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 RT registers */ -#define FM3_BT3_PWC_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWC registers */ -#define FM3_BT4_PPG_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PPG registers */ -#define FM3_BT4_PWM_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWM registers */ -#define FM3_BT4_RT_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 RT registers */ -#define FM3_BT4_PWC_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWC registers */ -#define FM3_BT5_PPG_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PPG registers */ -#define FM3_BT5_PWM_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWM registers */ -#define FM3_BT5_RT_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 RT registers */ -#define FM3_BT5_PWC_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWC registers */ -#define FM3_BT6_PPG_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PPG registers */ -#define FM3_BT6_PWM_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWM registers */ -#define FM3_BT6_RT_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 RT registers */ -#define FM3_BT6_PWC_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWC registers */ -#define FM3_BT7_PPG_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PPG registers */ -#define FM3_BT7_PWM_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWM registers */ -#define FM3_BT7_RT_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 RT registers */ -#define FM3_BT7_PWC_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWC registers */ -#define FM3_BTIOSEL03_BASE (FM3_PERIPH_BASE + 0x25100UL) /* Base Timer I/O selector channel 0 - channel 3 registers */ -#define FM3_BTIOSEL47_BASE (FM3_PERIPH_BASE + 0x25300UL) /* Base Timer I/O selector channel 4 - channel 7 registers */ -#define FM3_SBSSR_BASE (FM3_PERIPH_BASE + 0x25FFCUL) /* Software based Simulation Startup (Base Timer) register */ -#define FM3_QPRC0_BASE (FM3_PERIPH_BASE + 0x26000UL) /* Quad position and revolution counter channel 0 registers */ -#define FM3_QPRC1_BASE (FM3_PERIPH_BASE + 0x26040UL) /* Quad position and revolution counter channel 1 registers */ -#define FM3_ADC0_BASE (FM3_PERIPH_BASE + 0x27000UL) /* 12-bit ADC unit 0 registers */ -#define FM3_ADC1_BASE (FM3_PERIPH_BASE + 0x27100UL) /* 12-bit ADC unit 1 registers */ -#define FM3_ADC2_BASE (FM3_PERIPH_BASE + 0x27200UL) /* 12-bit ADC unit 2 registers */ -#define FM3_CRTRIM_BASE (FM3_PERIPH_BASE + 0x2E000UL) /* CR trimming registers */ -#define FM3_EXTI_BASE (FM3_PERIPH_BASE + 0x30000UL) /* External interrupt registers */ -#define FM3_INTREQ_BASE (FM3_PERIPH_BASE + 0x31000UL) /* Interrupt request read registers */ -#define FM3_GPIO_BASE (FM3_PERIPH_BASE + 0x33000UL) /* General purpose I/O registers */ -#define FM3_LVD_BASE (FM3_PERIPH_BASE + 0x35000UL) /* Low voltage detection registers */ -#define FM3_USBCLK_BASE (FM3_PERIPH_BASE + 0x36000UL) /* USB clock registers */ -#define FM3_CANPRES_BASE (FM3_PERIPH_BASE + 0x37000UL) /* CAN prescaler register */ -#define FM3_MFS0_UART_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART asynchronous channel 0 registers */ -#define FM3_MFS0_CSIO_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART synchronous channel 0 registers */ -#define FM3_MFS0_LIN_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART LIN channel 0 registers */ -#define FM3_MFS0_I2C_BASE (FM3_PERIPH_BASE + 0x38000UL) /* I2C channel 0 registers */ -#define FM3_MFS1_UART_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART asynchronous channel 1 registers */ -#define FM3_MFS1_CSIO_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART synchronous channel 1 registers */ -#define FM3_MFS1_LIN_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART LIN channel 1 registers */ -#define FM3_MFS1_I2C_BASE (FM3_PERIPH_BASE + 0x38100UL) /* I2C channel 1 registers */ -#define FM3_MFS2_UART_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART asynchronous channel 2 registers */ -#define FM3_MFS2_CSIO_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART synchronous channel 2 registers */ -#define FM3_MFS2_LIN_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART LIN channel 2 registers */ -#define FM3_MFS2_I2C_BASE (FM3_PERIPH_BASE + 0x38200UL) /* I2C channel 2 registers */ -#define FM3_MFS3_UART_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART asynchronous channel 3 registers */ -#define FM3_MFS3_CSIO_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART synchronous channel 3 registers */ -#define FM3_MFS3_LIN_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART LIN channel 3 registers */ -#define FM3_MFS3_I2C_BASE (FM3_PERIPH_BASE + 0x38300UL) /* I2C channel 3 registers */ -#define FM3_MFS4_UART_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART asynchronous channel 4 registers */ -#define FM3_MFS4_CSIO_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART synchronous channel 4 registers */ -#define FM3_MFS4_LIN_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART LIN channel 4 registers */ -#define FM3_MFS4_I2C_BASE (FM3_PERIPH_BASE + 0x38400UL) /* I2C channel 4 registers */ -#define FM3_MFS5_UART_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART asynchronous channel 5 registers */ -#define FM3_MFS5_CSIO_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART synchronous channel 5 registers */ -#define FM3_MFS5_LIN_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART LIN channel 5 registers */ -#define FM3_MFS5_I2C_BASE (FM3_PERIPH_BASE + 0x38500UL) /* I2C channel 5 registers */ -#define FM3_MFS6_UART_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART asynchronous channel 6 registers */ -#define FM3_MFS6_CSIO_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART synchronous channel 6 registers */ -#define FM3_MFS6_LIN_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART LIN channel 6 registers */ -#define FM3_MFS6_I2C_BASE (FM3_PERIPH_BASE + 0x38600UL) /* I2C channel 6 registers */ -#define FM3_MFS7_UART_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART asynchronous channel 7 registers */ -#define FM3_MFS7_CSIO_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART synchronous channel 7 registers */ -#define FM3_MFS7_LIN_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART LIN channel 7 registers */ -#define FM3_MFS7_I2C_BASE (FM3_PERIPH_BASE + 0x38700UL) /* I2C channel 7 registers */ -#define FM3_CRC_BASE (FM3_PERIPH_BASE + 0x39000UL) /* CRC registers */ -#define FM3_WC_BASE (FM3_PERIPH_BASE + 0x3A000UL) /* Watch counter registers */ -#define FM3_EXBUS_BASE (FM3_PERIPH_BASE + 0x3F000UL) /* External bus interface registers */ -#define FM3_USB0_BASE (FM3_PERIPH_BASE + 0x42100UL) /* USB channel 0 registers */ -#define FM3_DMAC_BASE (FM3_PERIPH_BASE + 0x60000UL) /* DMA controller */ -#define FM3_CAN0_BASE (FM3_PERIPH_BASE + 0x62000UL) /* CAN channel 0 registers */ -#define FM3_CAN1_BASE (FM3_PERIPH_BASE + 0x63000UL) /* CAN channel 1 registers */ - -/****************************************************************************** - * Peripheral declaration - ******************************************************************************/ -#define FM3_FLASH_IF ((FM3_FIF_TypeDef *)FM3_FLASH_IF_BASE) -#define FM3_CRG ((FM3_CRG_TypeDef *)FM3_CRG_BASE) -#define FM3_HWWDT ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE) -#define FM3_SWWDT ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE) -#define FM3_DTIM ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE) -#define FM3_MFT0_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE) -#define FM3_MFT0_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE) -#define FM3_MFT0_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE) -#define FM3_MFT0_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE) -#define FM3_MFT0_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE) -#define FM3_MFT1_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE) -#define FM3_MFT1_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE) -#define FM3_MFT1_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE) -#define FM3_MFT1_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE) -#define FM3_MFT1_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE) -#define FM3_MFT_PPG ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE) -#define FM3_BT0_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE) -#define FM3_BT0_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE) -#define FM3_BT0_RT ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE) -#define FM3_BT0_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE) -#define FM3_BT1_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE) -#define FM3_BT1_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE) -#define FM3_BT1_RT ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE) -#define FM3_BT1_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE) -#define FM3_BT2_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE) -#define FM3_BT2_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE) -#define FM3_BT2_RT ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE) -#define FM3_BT2_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE) -#define FM3_BT3_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE) -#define FM3_BT3_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE) -#define FM3_BT3_RT ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE) -#define FM3_BT3_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE) -#define FM3_BT4_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE) -#define FM3_BT4_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE) -#define FM3_BT4_RT ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE) -#define FM3_BT4_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE) -#define FM3_BT5_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE) -#define FM3_BT5_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE) -#define FM3_BT5_RT ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE) -#define FM3_BT5_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE) -#define FM3_BT6_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE) -#define FM3_BT6_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE) -#define FM3_BT6_RT ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE) -#define FM3_BT6_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE) -#define FM3_BT7_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE) -#define FM3_BT7_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE) -#define FM3_BT7_RT ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE) -#define FM3_BT7_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE) -#define FM3_BTIOSEL03 ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE) -#define FM3_BTIOSEL47 ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE) -#define FM3_SBSSR ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE) -#define FM3_QPRC0 ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE) -#define FM3_QPRC1 ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE) -#define FM3_ADC0 ((FM3_ADC_TypeDef *)FM3_ADC0_BASE) -#define FM3_ADC1 ((FM3_ADC_TypeDef *)FM3_ADC1_BASE) -#define FM3_ADC2 ((FM3_ADC_TypeDef *)FM3_ADC2_BASE) -#define FM3_CRTRIM ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE) -#define FM3_EXTI ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE) -#define FM3_INTREQ ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE) -#define FM3_GPIO ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE) -#define FM3_LVD ((FM3_LVD_TypeDef *)FM3_LVD_BASE) -#define FM3_USBCLK ((FM3_USBCLK_TypeDef *)FM3_USBCLK_BASE) -#define FM3_CANPRES ((FM3_CANPRE_TypeDef *)FM3_CANPRES_BASE) -#define FM3_MFS0_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE) -#define FM3_MFS0_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE) -#define FM3_MFS0_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE) -#define FM3_MFS0_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE) -#define FM3_MFS1_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE) -#define FM3_MFS1_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE) -#define FM3_MFS1_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE) -#define FM3_MFS1_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE) -#define FM3_MFS2_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE) -#define FM3_MFS2_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE) -#define FM3_MFS2_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE) -#define FM3_MFS2_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE) -#define FM3_MFS3_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE) -#define FM3_MFS3_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE) -#define FM3_MFS3_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE) -#define FM3_MFS3_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE) -#define FM3_MFS4_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE) -#define FM3_MFS4_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE) -#define FM3_MFS4_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE) -#define FM3_MFS4_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE) -#define FM3_MFS5_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE) -#define FM3_MFS5_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE) -#define FM3_MFS5_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE) -#define FM3_MFS5_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE) -#define FM3_MFS6_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE) -#define FM3_MFS6_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE) -#define FM3_MFS6_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE) -#define FM3_MFS6_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE) -#define FM3_MFS7_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE) -#define FM3_MFS7_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE) -#define FM3_MFS7_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE) -#define FM3_MFS7_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE) -#define FM3_CRC ((FM3_CRC_TypeDef *)FM3_CRC_BASE) -#define FM3_WC ((FM3_WC_TypeDef *)FM3_WC_BASE) -#define FM3_EXBUS ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE) -#define FM3_USB0 ((FM3_USB_TypeDef *)FM3_USB0_BASE) -#define FM3_DMAC ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE) -#define FM3_CAN0 ((FM3_CAN_TypeDef *)FM3_CAN0_BASE) -#define FM3_CAN1 ((FM3_CAN_TypeDef *)FM3_CAN1_BASE) - -/****************************************************************************** - * Peripheral Bit Band Alias declaration - ******************************************************************************/ - -/* Flash interface registers */ -#define bFM3_FLASH_IF_FASZR_ASZ0 *((volatile unsigned int*)(0x42000000UL)) -#define bFM3_FLASH_IF_FASZR_ASZ1 *((volatile unsigned int*)(0x42000004UL)) -#define bFM3_FLASH_IF_FRWTR_RWT0 *((volatile unsigned int*)(0x42000080UL)) -#define bFM3_FLASH_IF_FRWTR_RWT1 *((volatile unsigned int*)(0x42000084UL)) -#define bFM3_FLASH_IF_FSTR_RDY *((volatile unsigned int*)(0x42000100UL)) -#define bFM3_FLASH_IF_FSTR_HNG *((volatile unsigned int*)(0x42000104UL)) -#define bFM3_FLASH_IF_FSYNDN_SD0 *((volatile unsigned int*)(0x42000200UL)) -#define bFM3_FLASH_IF_FSYNDN_SD1 *((volatile unsigned int*)(0x42000204UL)) -#define bFM3_FLASH_IF_FSYNDN_SD2 *((volatile unsigned int*)(0x42000208UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM0 *((volatile unsigned int*)(0x42002000UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM1 *((volatile unsigned int*)(0x42002004UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM2 *((volatile unsigned int*)(0x42002008UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM3 *((volatile unsigned int*)(0x4200200CUL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM4 *((volatile unsigned int*)(0x42002010UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM5 *((volatile unsigned int*)(0x42002014UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM6 *((volatile unsigned int*)(0x42002018UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM7 *((volatile unsigned int*)(0x4200201CUL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM8 *((volatile unsigned int*)(0x42002020UL)) -#define bFM3_FLASH_IF_CRTRMM_TRMM9 *((volatile unsigned int*)(0x42002024UL)) - -/* Clock and reset registers */ -#define bFM3_CRG_SCM_CTL_MOSCE *((volatile unsigned int*)(0x42200004UL)) -#define bFM3_CRG_SCM_CTL_SOSCE *((volatile unsigned int*)(0x4220000CUL)) -#define bFM3_CRG_SCM_CTL_PLLE *((volatile unsigned int*)(0x42200010UL)) -#define bFM3_CRG_SCM_CTL_RCS0 *((volatile unsigned int*)(0x42200014UL)) -#define bFM3_CRG_SCM_CTL_RCS1 *((volatile unsigned int*)(0x42200018UL)) -#define bFM3_CRG_SCM_CTL_RCS2 *((volatile unsigned int*)(0x4220001CUL)) -#define bFM3_CRG_SCM_STR_MORDY *((volatile unsigned int*)(0x42200084UL)) -#define bFM3_CRG_SCM_STR_SORDY *((volatile unsigned int*)(0x4220008CUL)) -#define bFM3_CRG_SCM_STR_PLRDY *((volatile unsigned int*)(0x42200090UL)) -#define bFM3_CRG_SCM_STR_RCM0 *((volatile unsigned int*)(0x42200094UL)) -#define bFM3_CRG_SCM_STR_RCM1 *((volatile unsigned int*)(0x42200098UL)) -#define bFM3_CRG_SCM_STR_RCM2 *((volatile unsigned int*)(0x4220009CUL)) -#define bFM3_CRG_RST_STR_PONR *((volatile unsigned int*)(0x42200180UL)) -#define bFM3_CRG_RST_STR_INITX *((volatile unsigned int*)(0x42200184UL)) -#define bFM3_CRG_RST_STR_SWDT *((volatile unsigned int*)(0x42200190UL)) -#define bFM3_CRG_RST_STR_HWDT *((volatile unsigned int*)(0x42200194UL)) -#define bFM3_CRG_RST_STR_CSVR *((volatile unsigned int*)(0x42200198UL)) -#define bFM3_CRG_RST_STR_FCSR *((volatile unsigned int*)(0x4220019CUL)) -#define bFM3_CRG_RST_STR_SRST *((volatile unsigned int*)(0x422001A0UL)) -#define bFM3_CRG_BSC_PSR_BSR0 *((volatile unsigned int*)(0x42200200UL)) -#define bFM3_CRG_BSC_PSR_BSR1 *((volatile unsigned int*)(0x42200204UL)) -#define bFM3_CRG_BSC_PSR_BSR2 *((volatile unsigned int*)(0x42200208UL)) -#define bFM3_CRG_APBC0_PSR_APBC00 *((volatile unsigned int*)(0x42200280UL)) -#define bFM3_CRG_APBC0_PSR_APBC01 *((volatile unsigned int*)(0x42200284UL)) -#define bFM3_CRG_APBC1_PSR_APBC10 *((volatile unsigned int*)(0x42200300UL)) -#define bFM3_CRG_APBC1_PSR_APBC11 *((volatile unsigned int*)(0x42200304UL)) -#define bFM3_CRG_APBC1_PSR_APBC1RST *((volatile unsigned int*)(0x42200310UL)) -#define bFM3_CRG_APBC1_PSR_APBC1EN *((volatile unsigned int*)(0x4220031CUL)) -#define bFM3_CRG_APBC2_PSR_APBC20 *((volatile unsigned int*)(0x42200380UL)) -#define bFM3_CRG_APBC2_PSR_APBC21 *((volatile unsigned int*)(0x42200384UL)) -#define bFM3_CRG_APBC2_PSR_APBC2RST *((volatile unsigned int*)(0x42200390UL)) -#define bFM3_CRG_APBC2_PSR_APBC2EN *((volatile unsigned int*)(0x4220039CUL)) -#define bFM3_CRG_SWC_PSR_SWDS0 *((volatile unsigned int*)(0x42200400UL)) -#define bFM3_CRG_SWC_PSR_SWDS1 *((volatile unsigned int*)(0x42200404UL)) -#define bFM3_CRG_SWC_PSR_TESTB *((volatile unsigned int*)(0x4220041CUL)) -#define bFM3_CRG_TTC_PSR_TTC *((volatile unsigned int*)(0x42200500UL)) -#define bFM3_CRG_CSW_TMR_MOWT0 *((volatile unsigned int*)(0x42200600UL)) -#define bFM3_CRG_CSW_TMR_MOWT1 *((volatile unsigned int*)(0x42200604UL)) -#define bFM3_CRG_CSW_TMR_MOWT2 *((volatile unsigned int*)(0x42200608UL)) -#define bFM3_CRG_CSW_TMR_MOWT3 *((volatile unsigned int*)(0x4220060CUL)) -#define bFM3_CRG_CSW_TMR_SOWT0 *((volatile unsigned int*)(0x42200610UL)) -#define bFM3_CRG_CSW_TMR_SOWT1 *((volatile unsigned int*)(0x42200614UL)) -#define bFM3_CRG_CSW_TMR_SOWT2 *((volatile unsigned int*)(0x42200618UL)) -#define bFM3_CRG_PSW_TMR_POWT0 *((volatile unsigned int*)(0x42200680UL)) -#define bFM3_CRG_PSW_TMR_POWT1 *((volatile unsigned int*)(0x42200684UL)) -#define bFM3_CRG_PSW_TMR_POWT2 *((volatile unsigned int*)(0x42200688UL)) -#define bFM3_CRG_PSW_TMR_PINC *((volatile unsigned int*)(0x42200690UL)) -#define bFM3_CRG_PLL_CTL1_PLLM0 *((volatile unsigned int*)(0x42200700UL)) -#define bFM3_CRG_PLL_CTL1_PLLM1 *((volatile unsigned int*)(0x42200704UL)) -#define bFM3_CRG_PLL_CTL1_PLLM2 *((volatile unsigned int*)(0x42200708UL)) -#define bFM3_CRG_PLL_CTL1_PLLM3 *((volatile unsigned int*)(0x4220070CUL)) -#define bFM3_CRG_PLL_CTL1_PLLK0 *((volatile unsigned int*)(0x42200710UL)) -#define bFM3_CRG_PLL_CTL1_PLLK1 *((volatile unsigned int*)(0x42200714UL)) -#define bFM3_CRG_PLL_CTL1_PLLK2 *((volatile unsigned int*)(0x42200718UL)) -#define bFM3_CRG_PLL_CTL1_PLLK3 *((volatile unsigned int*)(0x4220071CUL)) -#define bFM3_CRG_PLL_CTL2_PLLN0 *((volatile unsigned int*)(0x42200780UL)) -#define bFM3_CRG_PLL_CTL2_PLLN1 *((volatile unsigned int*)(0x42200784UL)) -#define bFM3_CRG_PLL_CTL2_PLLN2 *((volatile unsigned int*)(0x42200788UL)) -#define bFM3_CRG_PLL_CTL2_PLLN3 *((volatile unsigned int*)(0x4220078CUL)) -#define bFM3_CRG_PLL_CTL2_PLLN4 *((volatile unsigned int*)(0x42200790UL)) -#define bFM3_CRG_CSV_CTL_MCSVE *((volatile unsigned int*)(0x42200800UL)) -#define bFM3_CRG_CSV_CTL_SCSVE *((volatile unsigned int*)(0x42200804UL)) -#define bFM3_CRG_CSV_CTL_FCSDE *((volatile unsigned int*)(0x42200820UL)) -#define bFM3_CRG_CSV_CTL_FCSRE *((volatile unsigned int*)(0x42200824UL)) -#define bFM3_CRG_CSV_CTL_FCD0 *((volatile unsigned int*)(0x42200830UL)) -#define bFM3_CRG_CSV_CTL_FCD1 *((volatile unsigned int*)(0x42200834UL)) -#define bFM3_CRG_CSV_CTL_FCD2 *((volatile unsigned int*)(0x42200838UL)) -#define bFM3_CRG_CSV_STR_MCMF *((volatile unsigned int*)(0x42200880UL)) -#define bFM3_CRG_CSV_STR_SCMF *((volatile unsigned int*)(0x42200884UL)) -#define bFM3_CRG_DBWDT_CTL_DPSWBE *((volatile unsigned int*)(0x42200A94UL)) -#define bFM3_CRG_DBWDT_CTL_DPHWBE *((volatile unsigned int*)(0x42200A9CUL)) -#define bFM3_CRG_INT_ENR_MCSE *((volatile unsigned int*)(0x42200C00UL)) -#define bFM3_CRG_INT_ENR_SCSE *((volatile unsigned int*)(0x42200C04UL)) -#define bFM3_CRG_INT_ENR_PCSE *((volatile unsigned int*)(0x42200C08UL)) -#define bFM3_CRG_INT_ENR_FCSE *((volatile unsigned int*)(0x42200C14UL)) -#define bFM3_CRG_INT_STR_MCSI *((volatile unsigned int*)(0x42200C80UL)) -#define bFM3_CRG_INT_STR_SCSI *((volatile unsigned int*)(0x42200C84UL)) -#define bFM3_CRG_INT_STR_PCSI *((volatile unsigned int*)(0x42200C88UL)) -#define bFM3_CRG_INT_STR_FCSI *((volatile unsigned int*)(0x42200C94UL)) -#define bFM3_CRG_INT_CLR_MCSC *((volatile unsigned int*)(0x42200D00UL)) -#define bFM3_CRG_INT_CLR_SCSC *((volatile unsigned int*)(0x42200D04UL)) -#define bFM3_CRG_INT_CLR_PCSC *((volatile unsigned int*)(0x42200D08UL)) -#define bFM3_CRG_INT_CLR_FCSC *((volatile unsigned int*)(0x42200D14UL)) - -/* Hardware watchdog registers */ -#define bFM3_HWWDT_WDG_CTL_INTEN *((volatile unsigned int*)(0x42220100UL)) -#define bFM3_HWWDT_WDG_CTL_RESEN *((volatile unsigned int*)(0x42220104UL)) -#define bFM3_HWWDT_WDG_RIS_RIS *((volatile unsigned int*)(0x42220200UL)) - -/* Software watchdog registers */ -#define bFM3_SWWDT_WDOGCONTROL_INTEN *((volatile unsigned int*)(0x42240100UL)) -#define bFM3_SWWDT_WDOGCONTROL_RESEN *((volatile unsigned int*)(0x42240104UL)) -#define bFM3_SWWDT_WDOGRIS_RIS *((volatile unsigned int*)(0x42240200UL)) - -/* Dual timer 1/2 registers */ -#define bFM3_DTIM_TIMER1CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0100UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0104UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0108UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A010CUL)) -#define bFM3_DTIM_TIMER1CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0114UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0118UL)) -#define bFM3_DTIM_TIMER1CONTROL_TIMEREN *((volatile unsigned int*)(0x422A011CUL)) -#define bFM3_DTIM_TIMER1RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0200UL)) -#define bFM3_DTIM_TIMER1MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0280UL)) -#define bFM3_DTIM_TIMER2CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0500UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0504UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0508UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A050CUL)) -#define bFM3_DTIM_TIMER2CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0514UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0518UL)) -#define bFM3_DTIM_TIMER2CONTROL_TIMEREN *((volatile unsigned int*)(0x422A051CUL)) -#define bFM3_DTIM_TIMER2RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0600UL)) -#define bFM3_DTIM_TIMER2MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0680UL)) - -/* Multifunction Timer unit 0 Free Running Timer registers */ -#define bFM3_MFT0_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42400600UL)) -#define bFM3_MFT0_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42400604UL)) -#define bFM3_MFT0_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42400608UL)) -#define bFM3_MFT0_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4240060CUL)) -#define bFM3_MFT0_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42400610UL)) -#define bFM3_MFT0_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42400614UL)) -#define bFM3_MFT0_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42400618UL)) -#define bFM3_MFT0_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4240061CUL)) -#define bFM3_MFT0_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42400620UL)) -#define bFM3_MFT0_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42400624UL)) -#define bFM3_MFT0_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42400634UL)) -#define bFM3_MFT0_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42400638UL)) -#define bFM3_MFT0_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4240063CUL)) -#define bFM3_MFT0_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42400680UL)) -#define bFM3_MFT0_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42400684UL)) -#define bFM3_MFT0_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42400688UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42400800UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42400804UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42400808UL)) -#define bFM3_MFT0_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4240080CUL)) -#define bFM3_MFT0_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42400810UL)) -#define bFM3_MFT0_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42400814UL)) -#define bFM3_MFT0_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42400818UL)) -#define bFM3_MFT0_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4240081CUL)) -#define bFM3_MFT0_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42400820UL)) -#define bFM3_MFT0_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42400824UL)) -#define bFM3_MFT0_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42400834UL)) -#define bFM3_MFT0_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42400838UL)) -#define bFM3_MFT0_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4240083CUL)) -#define bFM3_MFT0_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42400880UL)) -#define bFM3_MFT0_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42400884UL)) -#define bFM3_MFT0_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42400888UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42400A00UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42400A04UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42400A08UL)) -#define bFM3_MFT0_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42400A0CUL)) -#define bFM3_MFT0_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42400A10UL)) -#define bFM3_MFT0_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42400A14UL)) -#define bFM3_MFT0_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42400A18UL)) -#define bFM3_MFT0_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42400A1CUL)) -#define bFM3_MFT0_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42400A20UL)) -#define bFM3_MFT0_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42400A24UL)) -#define bFM3_MFT0_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42400A34UL)) -#define bFM3_MFT0_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42400A38UL)) -#define bFM3_MFT0_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42400A3CUL)) -#define bFM3_MFT0_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42400A80UL)) -#define bFM3_MFT0_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42400A84UL)) -#define bFM3_MFT0_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42400A88UL)) - -/* Multifunction Timer unit 0 Output Compare Unit registers */ -#define bFM3_MFT0_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42400300UL)) -#define bFM3_MFT0_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42400304UL)) -#define bFM3_MFT0_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42400308UL)) -#define bFM3_MFT0_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4240030CUL)) -#define bFM3_MFT0_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42400310UL)) -#define bFM3_MFT0_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42400314UL)) -#define bFM3_MFT0_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42400318UL)) -#define bFM3_MFT0_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4240031CUL)) -#define bFM3_MFT0_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42400320UL)) -#define bFM3_MFT0_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42400324UL)) -#define bFM3_MFT0_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42400330UL)) -#define bFM3_MFT0_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42400334UL)) -#define bFM3_MFT0_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42400338UL)) -#define bFM3_MFT0_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42400380UL)) -#define bFM3_MFT0_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42400384UL)) -#define bFM3_MFT0_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42400388UL)) -#define bFM3_MFT0_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4240038CUL)) -#define bFM3_MFT0_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42400390UL)) -#define bFM3_MFT0_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42400394UL)) -#define bFM3_MFT0_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42400398UL)) -#define bFM3_MFT0_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4240039CUL)) -#define bFM3_MFT0_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424003A0UL)) -#define bFM3_MFT0_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424003A4UL)) -#define bFM3_MFT0_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424003B0UL)) -#define bFM3_MFT0_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424003B4UL)) -#define bFM3_MFT0_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424003B8UL)) -#define bFM3_MFT0_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42400400UL)) -#define bFM3_MFT0_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42400404UL)) -#define bFM3_MFT0_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42400408UL)) -#define bFM3_MFT0_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4240040CUL)) -#define bFM3_MFT0_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42400410UL)) -#define bFM3_MFT0_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42400414UL)) -#define bFM3_MFT0_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42400418UL)) -#define bFM3_MFT0_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4240041CUL)) -#define bFM3_MFT0_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42400420UL)) -#define bFM3_MFT0_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42400424UL)) -#define bFM3_MFT0_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42400430UL)) -#define bFM3_MFT0_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42400434UL)) -#define bFM3_MFT0_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42400438UL)) -#define bFM3_MFT0_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424004A0UL)) -#define bFM3_MFT0_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424004A4UL)) -#define bFM3_MFT0_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424004A8UL)) -#define bFM3_MFT0_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424004ACUL)) -#define bFM3_MFT0_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424004B0UL)) -#define bFM3_MFT0_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424004B4UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42400B00UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42400B04UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42400B08UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42400B0CUL)) -#define bFM3_MFT0_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42400B10UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42400B14UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42400B18UL)) -#define bFM3_MFT0_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42400B1CUL)) -#define bFM3_MFT0_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42400B20UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42400B24UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42400B28UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42400B2CUL)) -#define bFM3_MFT0_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42400B30UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42400B34UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42400B38UL)) -#define bFM3_MFT0_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42400B3CUL)) -#define bFM3_MFT0_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42400B80UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42400B84UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42400B88UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42400B8CUL)) -#define bFM3_MFT0_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42400B90UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42400B94UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42400B98UL)) -#define bFM3_MFT0_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42400B9CUL)) - -/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ -#define bFM3_MFT0_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42401180UL)) -#define bFM3_MFT0_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42401184UL)) -#define bFM3_MFT0_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42401188UL)) -#define bFM3_MFT0_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4240118CUL)) -#define bFM3_MFT0_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42401190UL)) -#define bFM3_MFT0_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42401194UL)) -#define bFM3_MFT0_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42401198UL)) -#define bFM3_MFT0_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4240119CUL)) -#define bFM3_MFT0_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424011A0UL)) -#define bFM3_MFT0_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424011A4UL)) -#define bFM3_MFT0_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424011A8UL)) -#define bFM3_MFT0_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424011ACUL)) -#define bFM3_MFT0_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424011B0UL)) -#define bFM3_MFT0_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42401200UL)) -#define bFM3_MFT0_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42401204UL)) -#define bFM3_MFT0_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42401208UL)) -#define bFM3_MFT0_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4240120CUL)) -#define bFM3_MFT0_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42401210UL)) -#define bFM3_MFT0_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42401214UL)) -#define bFM3_MFT0_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42401218UL)) -#define bFM3_MFT0_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4240121CUL)) -#define bFM3_MFT0_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42401220UL)) -#define bFM3_MFT0_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42401224UL)) -#define bFM3_MFT0_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42401228UL)) -#define bFM3_MFT0_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4240122CUL)) -#define bFM3_MFT0_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42401230UL)) -#define bFM3_MFT0_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42401280UL)) -#define bFM3_MFT0_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42401284UL)) -#define bFM3_MFT0_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42401288UL)) -#define bFM3_MFT0_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4240128CUL)) -#define bFM3_MFT0_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42401290UL)) -#define bFM3_MFT0_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42401294UL)) -#define bFM3_MFT0_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42401298UL)) -#define bFM3_MFT0_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4240129CUL)) -#define bFM3_MFT0_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424012A0UL)) -#define bFM3_MFT0_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424012A4UL)) -#define bFM3_MFT0_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424012A8UL)) -#define bFM3_MFT0_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424012ACUL)) -#define bFM3_MFT0_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424012B0UL)) -#define bFM3_MFT0_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42401300UL)) -#define bFM3_MFT0_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42401304UL)) -#define bFM3_MFT0_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42401310UL)) -#define bFM3_MFT0_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42401314UL)) -#define bFM3_MFT0_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42401318UL)) -#define bFM3_MFT0_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4240131CUL)) -#define bFM3_MFT0_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42401320UL)) -#define bFM3_MFT0_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42401324UL)) -#define bFM3_MFT0_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42401328UL)) -#define bFM3_MFT0_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4240132CUL)) -#define bFM3_MFT0_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42401330UL)) -#define bFM3_MFT0_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42401334UL)) -#define bFM3_MFT0_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42401338UL)) -#define bFM3_MFT0_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4240133CUL)) -#define bFM3_MFT0_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42401380UL)) -#define bFM3_MFT0_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42401384UL)) -#define bFM3_MFT0_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42401388UL)) -#define bFM3_MFT0_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4240138CUL)) -#define bFM3_MFT0_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42401390UL)) - -/* Multifunction Timer unit 0 Input Capture Unit registers */ -#define bFM3_MFT0_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42400C00UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42400C04UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42400C08UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42400C0CUL)) -#define bFM3_MFT0_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42400C10UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42400C14UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42400C18UL)) -#define bFM3_MFT0_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42400C1CUL)) -#define bFM3_MFT0_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42400C20UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42400C24UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42400C28UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42400C2CUL)) -#define bFM3_MFT0_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42400C30UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42400C34UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42400C38UL)) -#define bFM3_MFT0_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42400C3CUL)) -#define bFM3_MFT0_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42400F00UL)) -#define bFM3_MFT0_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42400F04UL)) -#define bFM3_MFT0_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42400F08UL)) -#define bFM3_MFT0_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42400F0CUL)) -#define bFM3_MFT0_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42400F10UL)) -#define bFM3_MFT0_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42400F14UL)) -#define bFM3_MFT0_ICU_ICSA10_IPC0 *((volatile unsigned int*)(0x42400F18UL)) -#define bFM3_MFT0_ICU_ICSA10_IPC1 *((volatile unsigned int*)(0x42400F1CUL)) -#define bFM3_MFT0_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42400F20UL)) -#define bFM3_MFT0_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42400F24UL)) -#define bFM3_MFT0_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42400F80UL)) -#define bFM3_MFT0_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42400F84UL)) -#define bFM3_MFT0_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42400F88UL)) -#define bFM3_MFT0_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42400F8CUL)) -#define bFM3_MFT0_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42400F90UL)) -#define bFM3_MFT0_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42400F94UL)) -#define bFM3_MFT0_ICU_ICSA32_IPC2 *((volatile unsigned int*)(0x42400F98UL)) -#define bFM3_MFT0_ICU_ICSA32_IPC3 *((volatile unsigned int*)(0x42400F9CUL)) -#define bFM3_MFT0_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42400FA0UL)) -#define bFM3_MFT0_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42400FA4UL)) - -/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ -#define bFM3_MFT0_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42401700UL)) -#define bFM3_MFT0_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42401704UL)) -#define bFM3_MFT0_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42401708UL)) -#define bFM3_MFT0_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42401710UL)) -#define bFM3_MFT0_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42401714UL)) -#define bFM3_MFT0_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42401718UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42401780UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42401784UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42401788UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4240178CUL)) -#define bFM3_MFT0_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42401790UL)) -#define bFM3_MFT0_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42401794UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424017A0UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424017A4UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424017A8UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424017ACUL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424017B0UL)) -#define bFM3_MFT0_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424017B4UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42401800UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42401804UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42401808UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4240180CUL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42401810UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42401814UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42401820UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42401824UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42401828UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4240182CUL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42401830UL)) -#define bFM3_MFT0_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42401834UL)) - -/* Multifunction Timer unit 1 Free Running Timer registers */ -#define bFM3_MFT1_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42420600UL)) -#define bFM3_MFT1_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42420604UL)) -#define bFM3_MFT1_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42420608UL)) -#define bFM3_MFT1_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4242060CUL)) -#define bFM3_MFT1_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42420610UL)) -#define bFM3_MFT1_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42420614UL)) -#define bFM3_MFT1_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42420618UL)) -#define bFM3_MFT1_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4242061CUL)) -#define bFM3_MFT1_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42420620UL)) -#define bFM3_MFT1_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42420624UL)) -#define bFM3_MFT1_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42420634UL)) -#define bFM3_MFT1_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42420638UL)) -#define bFM3_MFT1_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4242063CUL)) -#define bFM3_MFT1_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42420680UL)) -#define bFM3_MFT1_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42420684UL)) -#define bFM3_MFT1_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42420688UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42420800UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42420804UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42420808UL)) -#define bFM3_MFT1_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4242080CUL)) -#define bFM3_MFT1_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42420810UL)) -#define bFM3_MFT1_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42420814UL)) -#define bFM3_MFT1_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42420818UL)) -#define bFM3_MFT1_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4242081CUL)) -#define bFM3_MFT1_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42420820UL)) -#define bFM3_MFT1_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42420824UL)) -#define bFM3_MFT1_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42420834UL)) -#define bFM3_MFT1_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42420838UL)) -#define bFM3_MFT1_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4242083CUL)) -#define bFM3_MFT1_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42420880UL)) -#define bFM3_MFT1_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42420884UL)) -#define bFM3_MFT1_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42420888UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42420A00UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42420A04UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42420A08UL)) -#define bFM3_MFT1_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42420A0CUL)) -#define bFM3_MFT1_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42420A10UL)) -#define bFM3_MFT1_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42420A14UL)) -#define bFM3_MFT1_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42420A18UL)) -#define bFM3_MFT1_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42420A1CUL)) -#define bFM3_MFT1_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42420A20UL)) -#define bFM3_MFT1_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42420A24UL)) -#define bFM3_MFT1_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42420A34UL)) -#define bFM3_MFT1_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42420A38UL)) -#define bFM3_MFT1_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42420A3CUL)) -#define bFM3_MFT1_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42420A80UL)) -#define bFM3_MFT1_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42420A84UL)) -#define bFM3_MFT1_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42420A88UL)) - -/* Multifunction Timer unit 1 Output Compare Unit registers */ -#define bFM3_MFT1_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42420300UL)) -#define bFM3_MFT1_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42420304UL)) -#define bFM3_MFT1_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42420308UL)) -#define bFM3_MFT1_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4242030CUL)) -#define bFM3_MFT1_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42420310UL)) -#define bFM3_MFT1_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42420314UL)) -#define bFM3_MFT1_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42420318UL)) -#define bFM3_MFT1_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4242031CUL)) -#define bFM3_MFT1_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42420320UL)) -#define bFM3_MFT1_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42420324UL)) -#define bFM3_MFT1_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42420330UL)) -#define bFM3_MFT1_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42420334UL)) -#define bFM3_MFT1_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42420338UL)) -#define bFM3_MFT1_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42420380UL)) -#define bFM3_MFT1_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42420384UL)) -#define bFM3_MFT1_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42420388UL)) -#define bFM3_MFT1_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4242038CUL)) -#define bFM3_MFT1_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42420390UL)) -#define bFM3_MFT1_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42420394UL)) -#define bFM3_MFT1_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42420398UL)) -#define bFM3_MFT1_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4242039CUL)) -#define bFM3_MFT1_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424203A0UL)) -#define bFM3_MFT1_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424203A4UL)) -#define bFM3_MFT1_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424203B0UL)) -#define bFM3_MFT1_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424203B4UL)) -#define bFM3_MFT1_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424203B8UL)) -#define bFM3_MFT1_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42420400UL)) -#define bFM3_MFT1_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42420404UL)) -#define bFM3_MFT1_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42420408UL)) -#define bFM3_MFT1_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4242040CUL)) -#define bFM3_MFT1_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42420410UL)) -#define bFM3_MFT1_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42420414UL)) -#define bFM3_MFT1_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42420418UL)) -#define bFM3_MFT1_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4242041CUL)) -#define bFM3_MFT1_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42420420UL)) -#define bFM3_MFT1_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42420424UL)) -#define bFM3_MFT1_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42420430UL)) -#define bFM3_MFT1_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42420434UL)) -#define bFM3_MFT1_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42420438UL)) -#define bFM3_MFT1_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424204A0UL)) -#define bFM3_MFT1_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424204A4UL)) -#define bFM3_MFT1_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424204A8UL)) -#define bFM3_MFT1_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424204ACUL)) -#define bFM3_MFT1_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424204B0UL)) -#define bFM3_MFT1_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424204B4UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42420B00UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42420B04UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42420B08UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42420B0CUL)) -#define bFM3_MFT1_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42420B10UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42420B14UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42420B18UL)) -#define bFM3_MFT1_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42420B1CUL)) -#define bFM3_MFT1_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42420B20UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42420B24UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42420B28UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42420B2CUL)) -#define bFM3_MFT1_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42420B30UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42420B34UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42420B38UL)) -#define bFM3_MFT1_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42420B3CUL)) -#define bFM3_MFT1_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42420B80UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42420B84UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42420B88UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42420B8CUL)) -#define bFM3_MFT1_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42420B90UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42420B94UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42420B98UL)) -#define bFM3_MFT1_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42420B9CUL)) - -/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ -#define bFM3_MFT1_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42421180UL)) -#define bFM3_MFT1_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42421184UL)) -#define bFM3_MFT1_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42421188UL)) -#define bFM3_MFT1_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4242118CUL)) -#define bFM3_MFT1_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42421190UL)) -#define bFM3_MFT1_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42421194UL)) -#define bFM3_MFT1_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42421198UL)) -#define bFM3_MFT1_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4242119CUL)) -#define bFM3_MFT1_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424211A0UL)) -#define bFM3_MFT1_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424211A4UL)) -#define bFM3_MFT1_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424211A8UL)) -#define bFM3_MFT1_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424211ACUL)) -#define bFM3_MFT1_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424211B0UL)) -#define bFM3_MFT1_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42421200UL)) -#define bFM3_MFT1_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42421204UL)) -#define bFM3_MFT1_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42421208UL)) -#define bFM3_MFT1_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4242120CUL)) -#define bFM3_MFT1_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42421210UL)) -#define bFM3_MFT1_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42421214UL)) -#define bFM3_MFT1_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42421218UL)) -#define bFM3_MFT1_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4242121CUL)) -#define bFM3_MFT1_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42421220UL)) -#define bFM3_MFT1_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42421224UL)) -#define bFM3_MFT1_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42421228UL)) -#define bFM3_MFT1_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4242122CUL)) -#define bFM3_MFT1_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42421230UL)) -#define bFM3_MFT1_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42421280UL)) -#define bFM3_MFT1_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42421284UL)) -#define bFM3_MFT1_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42421288UL)) -#define bFM3_MFT1_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4242128CUL)) -#define bFM3_MFT1_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42421290UL)) -#define bFM3_MFT1_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42421294UL)) -#define bFM3_MFT1_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42421298UL)) -#define bFM3_MFT1_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4242129CUL)) -#define bFM3_MFT1_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424212A0UL)) -#define bFM3_MFT1_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424212A4UL)) -#define bFM3_MFT1_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424212A8UL)) -#define bFM3_MFT1_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424212ACUL)) -#define bFM3_MFT1_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424212B0UL)) -#define bFM3_MFT1_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42421300UL)) -#define bFM3_MFT1_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42421304UL)) -#define bFM3_MFT1_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42421310UL)) -#define bFM3_MFT1_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42421314UL)) -#define bFM3_MFT1_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42421318UL)) -#define bFM3_MFT1_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4242131CUL)) -#define bFM3_MFT1_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42421320UL)) -#define bFM3_MFT1_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42421324UL)) -#define bFM3_MFT1_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42421328UL)) -#define bFM3_MFT1_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4242132CUL)) -#define bFM3_MFT1_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42421330UL)) -#define bFM3_MFT1_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42421334UL)) -#define bFM3_MFT1_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42421338UL)) -#define bFM3_MFT1_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4242133CUL)) -#define bFM3_MFT1_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42421380UL)) -#define bFM3_MFT1_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42421384UL)) -#define bFM3_MFT1_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42421388UL)) -#define bFM3_MFT1_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4242138CUL)) -#define bFM3_MFT1_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42421390UL)) - -/* Multifunction Timer unit 1 Input Capture Unit registers */ -#define bFM3_MFT1_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42420C00UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42420C04UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42420C08UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42420C0CUL)) -#define bFM3_MFT1_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42420C10UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42420C14UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42420C18UL)) -#define bFM3_MFT1_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42420C1CUL)) -#define bFM3_MFT1_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42420C20UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42420C24UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42420C28UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42420C2CUL)) -#define bFM3_MFT1_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42420C30UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42420C34UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42420C38UL)) -#define bFM3_MFT1_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42420C3CUL)) -#define bFM3_MFT1_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42420F00UL)) -#define bFM3_MFT1_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42420F04UL)) -#define bFM3_MFT1_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42420F08UL)) -#define bFM3_MFT1_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42420F0CUL)) -#define bFM3_MFT1_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42420F10UL)) -#define bFM3_MFT1_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42420F14UL)) -#define bFM3_MFT1_ICU_ICSA10_IPC0 *((volatile unsigned int*)(0x42420F18UL)) -#define bFM3_MFT1_ICU_ICSA10_IPC1 *((volatile unsigned int*)(0x42420F1CUL)) -#define bFM3_MFT1_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42420F20UL)) -#define bFM3_MFT1_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42420F24UL)) -#define bFM3_MFT1_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42420F80UL)) -#define bFM3_MFT1_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42420F84UL)) -#define bFM3_MFT1_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42420F88UL)) -#define bFM3_MFT1_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42420F8CUL)) -#define bFM3_MFT1_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42420F90UL)) -#define bFM3_MFT1_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42420F94UL)) -#define bFM3_MFT1_ICU_ICSA32_IPC2 *((volatile unsigned int*)(0x42420F98UL)) -#define bFM3_MFT1_ICU_ICSA32_IPC3 *((volatile unsigned int*)(0x42420F9CUL)) -#define bFM3_MFT1_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42420FA0UL)) -#define bFM3_MFT1_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42420FA4UL)) - -/* Multifunction Timer unit 1 ADC Start Compare Unit registers */ -#define bFM3_MFT1_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42421700UL)) -#define bFM3_MFT1_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42421704UL)) -#define bFM3_MFT1_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42421708UL)) -#define bFM3_MFT1_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42421710UL)) -#define bFM3_MFT1_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42421714UL)) -#define bFM3_MFT1_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42421718UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42421780UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42421784UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42421788UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4242178CUL)) -#define bFM3_MFT1_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42421790UL)) -#define bFM3_MFT1_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42421794UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424217A0UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424217A4UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424217A8UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424217ACUL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424217B0UL)) -#define bFM3_MFT1_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424217B4UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42421800UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42421804UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42421808UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4242180CUL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42421810UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42421814UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42421820UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42421824UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42421828UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4242182CUL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42421830UL)) -#define bFM3_MFT1_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42421834UL)) - -/* Multifunction Timer PPG registers */ -#define bFM3_MFT_PPG_TTCR0_STR0 *((volatile unsigned int*)(0x42480020UL)) -#define bFM3_MFT_PPG_TTCR0_MONI0 *((volatile unsigned int*)(0x42480024UL)) -#define bFM3_MFT_PPG_TTCR0_CS00 *((volatile unsigned int*)(0x42480028UL)) -#define bFM3_MFT_PPG_TTCR0_CS01 *((volatile unsigned int*)(0x4248002CUL)) -#define bFM3_MFT_PPG_TTCR0_TRG0O *((volatile unsigned int*)(0x42480030UL)) -#define bFM3_MFT_PPG_TTCR0_TRG2O *((volatile unsigned int*)(0x42480034UL)) -#define bFM3_MFT_PPG_TTCR0_TRG4O *((volatile unsigned int*)(0x42480038UL)) -#define bFM3_MFT_PPG_TTCR0_TRG6O *((volatile unsigned int*)(0x4248003CUL)) -#define bFM3_MFT_PPG_TTCR1_STR1 *((volatile unsigned int*)(0x42480420UL)) -#define bFM3_MFT_PPG_TTCR1_MONI1 *((volatile unsigned int*)(0x42480424UL)) -#define bFM3_MFT_PPG_TTCR1_CS10 *((volatile unsigned int*)(0x42480428UL)) -#define bFM3_MFT_PPG_TTCR1_CS11 *((volatile unsigned int*)(0x4248042CUL)) -#define bFM3_MFT_PPG_TTCR1_TRG1O *((volatile unsigned int*)(0x42480430UL)) -#define bFM3_MFT_PPG_TTCR1_TRG3O *((volatile unsigned int*)(0x42480434UL)) -#define bFM3_MFT_PPG_TTCR1_TRG5O *((volatile unsigned int*)(0x42480438UL)) -#define bFM3_MFT_PPG_TTCR1_TRG7O *((volatile unsigned int*)(0x4248043CUL)) -#define bFM3_MFT_PPG_TRG_PEN00 *((volatile unsigned int*)(0x42482000UL)) -#define bFM3_MFT_PPG_TRG_PEN01 *((volatile unsigned int*)(0x42482004UL)) -#define bFM3_MFT_PPG_TRG_PEN02 *((volatile unsigned int*)(0x42482008UL)) -#define bFM3_MFT_PPG_TRG_PEN03 *((volatile unsigned int*)(0x4248200CUL)) -#define bFM3_MFT_PPG_TRG_PEN04 *((volatile unsigned int*)(0x42482010UL)) -#define bFM3_MFT_PPG_TRG_PEN05 *((volatile unsigned int*)(0x42482014UL)) -#define bFM3_MFT_PPG_TRG_PEN06 *((volatile unsigned int*)(0x42482018UL)) -#define bFM3_MFT_PPG_TRG_PEN07 *((volatile unsigned int*)(0x4248201CUL)) -#define bFM3_MFT_PPG_TRG_PEN08 *((volatile unsigned int*)(0x42482020UL)) -#define bFM3_MFT_PPG_TRG_PEN09 *((volatile unsigned int*)(0x42482024UL)) -#define bFM3_MFT_PPG_TRG_PEN10 *((volatile unsigned int*)(0x42482028UL)) -#define bFM3_MFT_PPG_TRG_PEN11 *((volatile unsigned int*)(0x4248202CUL)) -#define bFM3_MFT_PPG_TRG_PEN12 *((volatile unsigned int*)(0x42482030UL)) -#define bFM3_MFT_PPG_TRG_PEN13 *((volatile unsigned int*)(0x42482034UL)) -#define bFM3_MFT_PPG_TRG_PEN14 *((volatile unsigned int*)(0x42482038UL)) -#define bFM3_MFT_PPG_TRG_PEN15 *((volatile unsigned int*)(0x4248203CUL)) -#define bFM3_MFT_PPG_REVC_REV00 *((volatile unsigned int*)(0x42482080UL)) -#define bFM3_MFT_PPG_REVC_REV01 *((volatile unsigned int*)(0x42482084UL)) -#define bFM3_MFT_PPG_REVC_REV02 *((volatile unsigned int*)(0x42482088UL)) -#define bFM3_MFT_PPG_REVC_REV03 *((volatile unsigned int*)(0x4248208CUL)) -#define bFM3_MFT_PPG_REVC_REV04 *((volatile unsigned int*)(0x42482090UL)) -#define bFM3_MFT_PPG_REVC_REV05 *((volatile unsigned int*)(0x42482094UL)) -#define bFM3_MFT_PPG_REVC_REV06 *((volatile unsigned int*)(0x42482098UL)) -#define bFM3_MFT_PPG_REVC_REV07 *((volatile unsigned int*)(0x4248209CUL)) -#define bFM3_MFT_PPG_REVC_REV08 *((volatile unsigned int*)(0x424820A0UL)) -#define bFM3_MFT_PPG_REVC_REV09 *((volatile unsigned int*)(0x424820A4UL)) -#define bFM3_MFT_PPG_REVC_REV10 *((volatile unsigned int*)(0x424820A8UL)) -#define bFM3_MFT_PPG_REVC_REV11 *((volatile unsigned int*)(0x424820ACUL)) -#define bFM3_MFT_PPG_REVC_REV12 *((volatile unsigned int*)(0x424820B0UL)) -#define bFM3_MFT_PPG_REVC_REV13 *((volatile unsigned int*)(0x424820B4UL)) -#define bFM3_MFT_PPG_REVC_REV14 *((volatile unsigned int*)(0x424820B8UL)) -#define bFM3_MFT_PPG_REVC_REV15 *((volatile unsigned int*)(0x424820BCUL)) -#define bFM3_MFT_PPG_PPGC1_TTRG *((volatile unsigned int*)(0x42484000UL)) -#define bFM3_MFT_PPG_PPGC1_MD0 *((volatile unsigned int*)(0x42484004UL)) -#define bFM3_MFT_PPG_PPGC1_MD1 *((volatile unsigned int*)(0x42484008UL)) -#define bFM3_MFT_PPG_PPGC1_PCS0 *((volatile unsigned int*)(0x4248400CUL)) -#define bFM3_MFT_PPG_PPGC1_PCS1 *((volatile unsigned int*)(0x42484010UL)) -#define bFM3_MFT_PPG_PPGC1_INTM *((volatile unsigned int*)(0x42484014UL)) -#define bFM3_MFT_PPG_PPGC1_PUF *((volatile unsigned int*)(0x42484018UL)) -#define bFM3_MFT_PPG_PPGC1_PIE *((volatile unsigned int*)(0x4248401CUL)) -#define bFM3_MFT_PPG_PPGC0_TTRG *((volatile unsigned int*)(0x42484020UL)) -#define bFM3_MFT_PPG_PPGC0_MD0 *((volatile unsigned int*)(0x42484024UL)) -#define bFM3_MFT_PPG_PPGC0_MD1 *((volatile unsigned int*)(0x42484028UL)) -#define bFM3_MFT_PPG_PPGC0_PCS0 *((volatile unsigned int*)(0x4248402CUL)) -#define bFM3_MFT_PPG_PPGC0_PCS1 *((volatile unsigned int*)(0x42484030UL)) -#define bFM3_MFT_PPG_PPGC0_INTM *((volatile unsigned int*)(0x42484034UL)) -#define bFM3_MFT_PPG_PPGC0_PUF *((volatile unsigned int*)(0x42484038UL)) -#define bFM3_MFT_PPG_PPGC0_PIE *((volatile unsigned int*)(0x4248403CUL)) -#define bFM3_MFT_PPG_PPGC3_TTRG *((volatile unsigned int*)(0x42484080UL)) -#define bFM3_MFT_PPG_PPGC3_MD0 *((volatile unsigned int*)(0x42484084UL)) -#define bFM3_MFT_PPG_PPGC3_MD1 *((volatile unsigned int*)(0x42484088UL)) -#define bFM3_MFT_PPG_PPGC3_PCS0 *((volatile unsigned int*)(0x4248408CUL)) -#define bFM3_MFT_PPG_PPGC3_PCS1 *((volatile unsigned int*)(0x42484090UL)) -#define bFM3_MFT_PPG_PPGC3_INTM *((volatile unsigned int*)(0x42484094UL)) -#define bFM3_MFT_PPG_PPGC3_PUF *((volatile unsigned int*)(0x42484098UL)) -#define bFM3_MFT_PPG_PPGC3_PIE *((volatile unsigned int*)(0x4248409CUL)) -#define bFM3_MFT_PPG_PPGC2_TTRG *((volatile unsigned int*)(0x424840A0UL)) -#define bFM3_MFT_PPG_PPGC2_MD0 *((volatile unsigned int*)(0x424840A4UL)) -#define bFM3_MFT_PPG_PPGC2_MD1 *((volatile unsigned int*)(0x424840A8UL)) -#define bFM3_MFT_PPG_PPGC2_PCS0 *((volatile unsigned int*)(0x424840ACUL)) -#define bFM3_MFT_PPG_PPGC2_PCS1 *((volatile unsigned int*)(0x424840B0UL)) -#define bFM3_MFT_PPG_PPGC2_INTM *((volatile unsigned int*)(0x424840B4UL)) -#define bFM3_MFT_PPG_PPGC2_PUF *((volatile unsigned int*)(0x424840B8UL)) -#define bFM3_MFT_PPG_PPGC2_PIE *((volatile unsigned int*)(0x424840BCUL)) -#define bFM3_MFT_PPG_GATEC0_EDGE0 *((volatile unsigned int*)(0x42484300UL)) -#define bFM3_MFT_PPG_GATEC0_STRG0 *((volatile unsigned int*)(0x42484304UL)) -#define bFM3_MFT_PPG_GATEC0_EDGE2 *((volatile unsigned int*)(0x42484310UL)) -#define bFM3_MFT_PPG_GATEC0_STRG2 *((volatile unsigned int*)(0x42484314UL)) -#define bFM3_MFT_PPG_PPGC5_TTRG *((volatile unsigned int*)(0x42484800UL)) -#define bFM3_MFT_PPG_PPGC5_MD0 *((volatile unsigned int*)(0x42484804UL)) -#define bFM3_MFT_PPG_PPGC5_MD1 *((volatile unsigned int*)(0x42484808UL)) -#define bFM3_MFT_PPG_PPGC5_PCS0 *((volatile unsigned int*)(0x4248480CUL)) -#define bFM3_MFT_PPG_PPGC5_PCS1 *((volatile unsigned int*)(0x42484810UL)) -#define bFM3_MFT_PPG_PPGC5_INTM *((volatile unsigned int*)(0x42484814UL)) -#define bFM3_MFT_PPG_PPGC5_PUF *((volatile unsigned int*)(0x42484818UL)) -#define bFM3_MFT_PPG_PPGC5_PIE *((volatile unsigned int*)(0x4248481CUL)) -#define bFM3_MFT_PPG_PPGC4_TTRG *((volatile unsigned int*)(0x42484820UL)) -#define bFM3_MFT_PPG_PPGC4_MD0 *((volatile unsigned int*)(0x42484824UL)) -#define bFM3_MFT_PPG_PPGC4_MD1 *((volatile unsigned int*)(0x42484828UL)) -#define bFM3_MFT_PPG_PPGC4_PCS0 *((volatile unsigned int*)(0x4248482CUL)) -#define bFM3_MFT_PPG_PPGC4_PCS1 *((volatile unsigned int*)(0x42484830UL)) -#define bFM3_MFT_PPG_PPGC4_INTM *((volatile unsigned int*)(0x42484834UL)) -#define bFM3_MFT_PPG_PPGC4_PUF *((volatile unsigned int*)(0x42484838UL)) -#define bFM3_MFT_PPG_PPGC4_PIE *((volatile unsigned int*)(0x4248483CUL)) -#define bFM3_MFT_PPG_PPGC7_TTRG *((volatile unsigned int*)(0x42484880UL)) -#define bFM3_MFT_PPG_PPGC7_MD0 *((volatile unsigned int*)(0x42484884UL)) -#define bFM3_MFT_PPG_PPGC7_MD1 *((volatile unsigned int*)(0x42484888UL)) -#define bFM3_MFT_PPG_PPGC7_PCS0 *((volatile unsigned int*)(0x4248488CUL)) -#define bFM3_MFT_PPG_PPGC7_PCS1 *((volatile unsigned int*)(0x42484890UL)) -#define bFM3_MFT_PPG_PPGC7_INTM *((volatile unsigned int*)(0x42484894UL)) -#define bFM3_MFT_PPG_PPGC7_PUF *((volatile unsigned int*)(0x42484898UL)) -#define bFM3_MFT_PPG_PPGC7_PIE *((volatile unsigned int*)(0x4248489CUL)) -#define bFM3_MFT_PPG_PPGC6_TTRG *((volatile unsigned int*)(0x424848A0UL)) -#define bFM3_MFT_PPG_PPGC6_MD0 *((volatile unsigned int*)(0x424848A4UL)) -#define bFM3_MFT_PPG_PPGC6_MD1 *((volatile unsigned int*)(0x424848A8UL)) -#define bFM3_MFT_PPG_PPGC6_PCS0 *((volatile unsigned int*)(0x424848ACUL)) -#define bFM3_MFT_PPG_PPGC6_PCS1 *((volatile unsigned int*)(0x424848B0UL)) -#define bFM3_MFT_PPG_PPGC6_INTM *((volatile unsigned int*)(0x424848B4UL)) -#define bFM3_MFT_PPG_PPGC6_PUF *((volatile unsigned int*)(0x424848B8UL)) -#define bFM3_MFT_PPG_PPGC6_PIE *((volatile unsigned int*)(0x424848BCUL)) -#define bFM3_MFT_PPG_GATEC4_EDGE4 *((volatile unsigned int*)(0x42484B00UL)) -#define bFM3_MFT_PPG_GATEC4_STRG4 *((volatile unsigned int*)(0x42484B04UL)) -#define bFM3_MFT_PPG_GATEC4_EDGE6 *((volatile unsigned int*)(0x42484B10UL)) -#define bFM3_MFT_PPG_GATEC4_STRG6 *((volatile unsigned int*)(0x42484B14UL)) -#define bFM3_MFT_PPG_PPGC9_TTRG *((volatile unsigned int*)(0x42485000UL)) -#define bFM3_MFT_PPG_PPGC9_MD0 *((volatile unsigned int*)(0x42485004UL)) -#define bFM3_MFT_PPG_PPGC9_MD1 *((volatile unsigned int*)(0x42485008UL)) -#define bFM3_MFT_PPG_PPGC9_PCS0 *((volatile unsigned int*)(0x4248500CUL)) -#define bFM3_MFT_PPG_PPGC9_PCS1 *((volatile unsigned int*)(0x42485010UL)) -#define bFM3_MFT_PPG_PPGC9_INTM *((volatile unsigned int*)(0x42485014UL)) -#define bFM3_MFT_PPG_PPGC9_PUF *((volatile unsigned int*)(0x42485018UL)) -#define bFM3_MFT_PPG_PPGC9_PIE *((volatile unsigned int*)(0x4248501CUL)) -#define bFM3_MFT_PPG_PPGC8_TTRG *((volatile unsigned int*)(0x42485020UL)) -#define bFM3_MFT_PPG_PPGC8_MD0 *((volatile unsigned int*)(0x42485024UL)) -#define bFM3_MFT_PPG_PPGC8_MD1 *((volatile unsigned int*)(0x42485028UL)) -#define bFM3_MFT_PPG_PPGC8_PCS0 *((volatile unsigned int*)(0x4248502CUL)) -#define bFM3_MFT_PPG_PPGC8_PCS1 *((volatile unsigned int*)(0x42485030UL)) -#define bFM3_MFT_PPG_PPGC8_INTM *((volatile unsigned int*)(0x42485034UL)) -#define bFM3_MFT_PPG_PPGC8_PUF *((volatile unsigned int*)(0x42485038UL)) -#define bFM3_MFT_PPG_PPGC8_PIE *((volatile unsigned int*)(0x4248503CUL)) -#define bFM3_MFT_PPG_PPGC11_TTRG *((volatile unsigned int*)(0x42485080UL)) -#define bFM3_MFT_PPG_PPGC11_MD0 *((volatile unsigned int*)(0x42485084UL)) -#define bFM3_MFT_PPG_PPGC11_MD1 *((volatile unsigned int*)(0x42485088UL)) -#define bFM3_MFT_PPG_PPGC11_PCS0 *((volatile unsigned int*)(0x4248508CUL)) -#define bFM3_MFT_PPG_PPGC11_PCS1 *((volatile unsigned int*)(0x42485090UL)) -#define bFM3_MFT_PPG_PPGC11_INTM *((volatile unsigned int*)(0x42485094UL)) -#define bFM3_MFT_PPG_PPGC11_PUF *((volatile unsigned int*)(0x42485098UL)) -#define bFM3_MFT_PPG_PPGC11_PIE *((volatile unsigned int*)(0x4248509CUL)) -#define bFM3_MFT_PPG_PPGC10_TTRG *((volatile unsigned int*)(0x424850A0UL)) -#define bFM3_MFT_PPG_PPGC10_MD0 *((volatile unsigned int*)(0x424850A4UL)) -#define bFM3_MFT_PPG_PPGC10_MD1 *((volatile unsigned int*)(0x424850A8UL)) -#define bFM3_MFT_PPG_PPGC10_PCS0 *((volatile unsigned int*)(0x424850ACUL)) -#define bFM3_MFT_PPG_PPGC10_PCS1 *((volatile unsigned int*)(0x424850B0UL)) -#define bFM3_MFT_PPG_PPGC10_INTM *((volatile unsigned int*)(0x424850B4UL)) -#define bFM3_MFT_PPG_PPGC10_PUF *((volatile unsigned int*)(0x424850B8UL)) -#define bFM3_MFT_PPG_PPGC10_PIE *((volatile unsigned int*)(0x424850BCUL)) -#define bFM3_MFT_PPG_GATEC8_EDGE8 *((volatile unsigned int*)(0x42485300UL)) -#define bFM3_MFT_PPG_GATEC8_STRG8 *((volatile unsigned int*)(0x42485304UL)) -#define bFM3_MFT_PPG_GATEC8_EDGE10 *((volatile unsigned int*)(0x42485310UL)) -#define bFM3_MFT_PPG_GATEC8_STRG10 *((volatile unsigned int*)(0x42485314UL)) -#define bFM3_MFT_PPG_PPGC13_TTRG *((volatile unsigned int*)(0x42485800UL)) -#define bFM3_MFT_PPG_PPGC13_MD0 *((volatile unsigned int*)(0x42485804UL)) -#define bFM3_MFT_PPG_PPGC13_MD1 *((volatile unsigned int*)(0x42485808UL)) -#define bFM3_MFT_PPG_PPGC13_PCS0 *((volatile unsigned int*)(0x4248580CUL)) -#define bFM3_MFT_PPG_PPGC13_PCS1 *((volatile unsigned int*)(0x42485810UL)) -#define bFM3_MFT_PPG_PPGC13_INTM *((volatile unsigned int*)(0x42485814UL)) -#define bFM3_MFT_PPG_PPGC13_PUF *((volatile unsigned int*)(0x42485818UL)) -#define bFM3_MFT_PPG_PPGC13_PIE *((volatile unsigned int*)(0x4248581CUL)) -#define bFM3_MFT_PPG_PPGC12_TTRG *((volatile unsigned int*)(0x42485820UL)) -#define bFM3_MFT_PPG_PPGC12_MD0 *((volatile unsigned int*)(0x42485824UL)) -#define bFM3_MFT_PPG_PPGC12_MD1 *((volatile unsigned int*)(0x42485828UL)) -#define bFM3_MFT_PPG_PPGC12_PCS0 *((volatile unsigned int*)(0x4248582CUL)) -#define bFM3_MFT_PPG_PPGC12_PCS1 *((volatile unsigned int*)(0x42485830UL)) -#define bFM3_MFT_PPG_PPGC12_INTM *((volatile unsigned int*)(0x42485834UL)) -#define bFM3_MFT_PPG_PPGC12_PUF *((volatile unsigned int*)(0x42485838UL)) -#define bFM3_MFT_PPG_PPGC12_PIE *((volatile unsigned int*)(0x4248583CUL)) -#define bFM3_MFT_PPG_PPGC15_TTRG *((volatile unsigned int*)(0x42485880UL)) -#define bFM3_MFT_PPG_PPGC15_MD0 *((volatile unsigned int*)(0x42485884UL)) -#define bFM3_MFT_PPG_PPGC15_MD1 *((volatile unsigned int*)(0x42485888UL)) -#define bFM3_MFT_PPG_PPGC15_PCS0 *((volatile unsigned int*)(0x4248588CUL)) -#define bFM3_MFT_PPG_PPGC15_PCS1 *((volatile unsigned int*)(0x42485890UL)) -#define bFM3_MFT_PPG_PPGC15_INTM *((volatile unsigned int*)(0x42485894UL)) -#define bFM3_MFT_PPG_PPGC15_PUF *((volatile unsigned int*)(0x42485898UL)) -#define bFM3_MFT_PPG_PPGC15_PIE *((volatile unsigned int*)(0x4248589CUL)) -#define bFM3_MFT_PPG_PPGC14_TTRG *((volatile unsigned int*)(0x424858A0UL)) -#define bFM3_MFT_PPG_PPGC14_MD0 *((volatile unsigned int*)(0x424858A4UL)) -#define bFM3_MFT_PPG_PPGC14_MD1 *((volatile unsigned int*)(0x424858A8UL)) -#define bFM3_MFT_PPG_PPGC14_PCS0 *((volatile unsigned int*)(0x424858ACUL)) -#define bFM3_MFT_PPG_PPGC14_PCS1 *((volatile unsigned int*)(0x424858B0UL)) -#define bFM3_MFT_PPG_PPGC14_INTM *((volatile unsigned int*)(0x424858B4UL)) -#define bFM3_MFT_PPG_PPGC14_PUF *((volatile unsigned int*)(0x424858B8UL)) -#define bFM3_MFT_PPG_PPGC14_PIE *((volatile unsigned int*)(0x424858BCUL)) -#define bFM3_MFT_PPG_GATEC12_EDGE12 *((volatile unsigned int*)(0x42485B00UL)) -#define bFM3_MFT_PPG_GATEC12_STRG12 *((volatile unsigned int*)(0x42485B04UL)) -#define bFM3_MFT_PPG_GATEC12_EDGE14 *((volatile unsigned int*)(0x42485B10UL)) -#define bFM3_MFT_PPG_GATEC12_STRG14 *((volatile unsigned int*)(0x42485B14UL)) - -/* Base Timer 0 PPG registers */ -#define bFM3_BT0_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM3_BT0_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM3_BT0_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM3_BT0_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM3_BT0_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM3_BT0_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM3_BT0_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) -#define bFM3_BT0_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 PWM registers */ -#define bFM3_BT0_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM3_BT0_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM3_BT0_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM3_BT0_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM3_BT0_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM3_BT0_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM3_BT0_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) -#define bFM3_BT0_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0204UL)) -#define bFM3_BT0_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0214UL)) -#define bFM3_BT0_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 RT registers */ -#define bFM3_BT0_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) -#define bFM3_BT0_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) -#define bFM3_BT0_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM3_BT0_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM3_BT0_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM3_BT0_RT_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) -#define bFM3_BT0_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_RT_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_RT_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_RT_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_RT_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 0 PWC registers */ -#define bFM3_BT0_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) -#define bFM3_BT0_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) -#define bFM3_BT0_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) -#define bFM3_BT0_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) -#define bFM3_BT0_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) -#define bFM3_BT0_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) -#define bFM3_BT0_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) -#define bFM3_BT0_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) -#define bFM3_BT0_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A01A8UL)) -#define bFM3_BT0_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) -#define bFM3_BT0_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) -#define bFM3_BT0_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) -#define bFM3_BT0_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0200UL)) -#define bFM3_BT0_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0208UL)) -#define bFM3_BT0_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0210UL)) -#define bFM3_BT0_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0218UL)) -#define bFM3_BT0_PWC_STC_ERR *((volatile unsigned int*)(0x424A021CUL)) -#define bFM3_BT0_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) - -/* Base Timer 1 PPG registers */ -#define bFM3_BT1_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM3_BT1_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM3_BT1_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM3_BT1_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM3_BT1_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM3_BT1_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM3_BT1_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) -#define bFM3_BT1_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 PWM registers */ -#define bFM3_BT1_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM3_BT1_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM3_BT1_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM3_BT1_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM3_BT1_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM3_BT1_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM3_BT1_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) -#define bFM3_BT1_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0A04UL)) -#define bFM3_BT1_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0A14UL)) -#define bFM3_BT1_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 RT registers */ -#define bFM3_BT1_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) -#define bFM3_BT1_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) -#define bFM3_BT1_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM3_BT1_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM3_BT1_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM3_BT1_RT_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) -#define bFM3_BT1_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_RT_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_RT_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_RT_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_RT_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 1 PWC registers */ -#define bFM3_BT1_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) -#define bFM3_BT1_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) -#define bFM3_BT1_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) -#define bFM3_BT1_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) -#define bFM3_BT1_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) -#define bFM3_BT1_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) -#define bFM3_BT1_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) -#define bFM3_BT1_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) -#define bFM3_BT1_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A09A8UL)) -#define bFM3_BT1_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) -#define bFM3_BT1_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) -#define bFM3_BT1_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) -#define bFM3_BT1_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0A00UL)) -#define bFM3_BT1_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0A08UL)) -#define bFM3_BT1_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0A10UL)) -#define bFM3_BT1_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0A18UL)) -#define bFM3_BT1_PWC_STC_ERR *((volatile unsigned int*)(0x424A0A1CUL)) -#define bFM3_BT1_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) - -/* Base Timer 2 PPG registers */ -#define bFM3_BT2_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM3_BT2_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM3_BT2_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM3_BT2_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM3_BT2_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM3_BT2_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM3_BT2_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) -#define bFM3_BT2_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 PWM registers */ -#define bFM3_BT2_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM3_BT2_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM3_BT2_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM3_BT2_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM3_BT2_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM3_BT2_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM3_BT2_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) -#define bFM3_BT2_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1204UL)) -#define bFM3_BT2_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1214UL)) -#define bFM3_BT2_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 RT registers */ -#define bFM3_BT2_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) -#define bFM3_BT2_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) -#define bFM3_BT2_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM3_BT2_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM3_BT2_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM3_BT2_RT_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) -#define bFM3_BT2_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_RT_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_RT_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_RT_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_RT_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 2 PWC registers */ -#define bFM3_BT2_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) -#define bFM3_BT2_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) -#define bFM3_BT2_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) -#define bFM3_BT2_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) -#define bFM3_BT2_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) -#define bFM3_BT2_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) -#define bFM3_BT2_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) -#define bFM3_BT2_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) -#define bFM3_BT2_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A11A8UL)) -#define bFM3_BT2_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) -#define bFM3_BT2_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) -#define bFM3_BT2_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) -#define bFM3_BT2_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1200UL)) -#define bFM3_BT2_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1208UL)) -#define bFM3_BT2_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1210UL)) -#define bFM3_BT2_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1218UL)) -#define bFM3_BT2_PWC_STC_ERR *((volatile unsigned int*)(0x424A121CUL)) -#define bFM3_BT2_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) - -/* Base Timer 3 PPG registers */ -#define bFM3_BT3_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM3_BT3_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM3_BT3_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM3_BT3_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM3_BT3_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM3_BT3_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM3_BT3_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) -#define bFM3_BT3_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 PWM registers */ -#define bFM3_BT3_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM3_BT3_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM3_BT3_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM3_BT3_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM3_BT3_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM3_BT3_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM3_BT3_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) -#define bFM3_BT3_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1A04UL)) -#define bFM3_BT3_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1A14UL)) -#define bFM3_BT3_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 RT registers */ -#define bFM3_BT3_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) -#define bFM3_BT3_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) -#define bFM3_BT3_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM3_BT3_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM3_BT3_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM3_BT3_RT_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) -#define bFM3_BT3_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_RT_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_RT_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_RT_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_RT_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 3 PWC registers */ -#define bFM3_BT3_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) -#define bFM3_BT3_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) -#define bFM3_BT3_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) -#define bFM3_BT3_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) -#define bFM3_BT3_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) -#define bFM3_BT3_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) -#define bFM3_BT3_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) -#define bFM3_BT3_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) -#define bFM3_BT3_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A19A8UL)) -#define bFM3_BT3_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) -#define bFM3_BT3_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) -#define bFM3_BT3_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) -#define bFM3_BT3_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1A00UL)) -#define bFM3_BT3_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1A08UL)) -#define bFM3_BT3_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1A10UL)) -#define bFM3_BT3_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1A18UL)) -#define bFM3_BT3_PWC_STC_ERR *((volatile unsigned int*)(0x424A1A1CUL)) -#define bFM3_BT3_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) - -/* Base Timer 4 PPG registers */ -#define bFM3_BT4_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM3_BT4_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM3_BT4_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM3_BT4_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM3_BT4_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM3_BT4_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM3_BT4_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) -#define bFM3_BT4_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 PWM registers */ -#define bFM3_BT4_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM3_BT4_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM3_BT4_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM3_BT4_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM3_BT4_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM3_BT4_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM3_BT4_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) -#define bFM3_BT4_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4204UL)) -#define bFM3_BT4_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4214UL)) -#define bFM3_BT4_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 RT registers */ -#define bFM3_BT4_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) -#define bFM3_BT4_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) -#define bFM3_BT4_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM3_BT4_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM3_BT4_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM3_BT4_RT_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) -#define bFM3_BT4_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_RT_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_RT_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_RT_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_RT_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 4 PWC registers */ -#define bFM3_BT4_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) -#define bFM3_BT4_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) -#define bFM3_BT4_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) -#define bFM3_BT4_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) -#define bFM3_BT4_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) -#define bFM3_BT4_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) -#define bFM3_BT4_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) -#define bFM3_BT4_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) -#define bFM3_BT4_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A41A8UL)) -#define bFM3_BT4_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) -#define bFM3_BT4_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) -#define bFM3_BT4_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) -#define bFM3_BT4_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4200UL)) -#define bFM3_BT4_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4208UL)) -#define bFM3_BT4_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4210UL)) -#define bFM3_BT4_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4218UL)) -#define bFM3_BT4_PWC_STC_ERR *((volatile unsigned int*)(0x424A421CUL)) -#define bFM3_BT4_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) - -/* Base Timer 5 PPG registers */ -#define bFM3_BT5_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM3_BT5_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM3_BT5_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM3_BT5_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM3_BT5_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM3_BT5_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM3_BT5_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) -#define bFM3_BT5_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 PWM registers */ -#define bFM3_BT5_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM3_BT5_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM3_BT5_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM3_BT5_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM3_BT5_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM3_BT5_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM3_BT5_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) -#define bFM3_BT5_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4A04UL)) -#define bFM3_BT5_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4A14UL)) -#define bFM3_BT5_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 RT registers */ -#define bFM3_BT5_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) -#define bFM3_BT5_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) -#define bFM3_BT5_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM3_BT5_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM3_BT5_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM3_BT5_RT_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) -#define bFM3_BT5_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_RT_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_RT_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_RT_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_RT_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 5 PWC registers */ -#define bFM3_BT5_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) -#define bFM3_BT5_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) -#define bFM3_BT5_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) -#define bFM3_BT5_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) -#define bFM3_BT5_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) -#define bFM3_BT5_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) -#define bFM3_BT5_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) -#define bFM3_BT5_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) -#define bFM3_BT5_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A49A8UL)) -#define bFM3_BT5_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) -#define bFM3_BT5_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) -#define bFM3_BT5_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) -#define bFM3_BT5_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4A00UL)) -#define bFM3_BT5_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4A08UL)) -#define bFM3_BT5_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4A10UL)) -#define bFM3_BT5_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4A18UL)) -#define bFM3_BT5_PWC_STC_ERR *((volatile unsigned int*)(0x424A4A1CUL)) -#define bFM3_BT5_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) - -/* Base Timer 6 PPG registers */ -#define bFM3_BT6_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM3_BT6_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM3_BT6_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM3_BT6_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM3_BT6_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM3_BT6_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM3_BT6_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) -#define bFM3_BT6_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 PWM registers */ -#define bFM3_BT6_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM3_BT6_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM3_BT6_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM3_BT6_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM3_BT6_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM3_BT6_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM3_BT6_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) -#define bFM3_BT6_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5204UL)) -#define bFM3_BT6_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5214UL)) -#define bFM3_BT6_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 RT registers */ -#define bFM3_BT6_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) -#define bFM3_BT6_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) -#define bFM3_BT6_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM3_BT6_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM3_BT6_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM3_BT6_RT_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) -#define bFM3_BT6_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_RT_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_RT_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_RT_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_RT_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 6 PWC registers */ -#define bFM3_BT6_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) -#define bFM3_BT6_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) -#define bFM3_BT6_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) -#define bFM3_BT6_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) -#define bFM3_BT6_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) -#define bFM3_BT6_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) -#define bFM3_BT6_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) -#define bFM3_BT6_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) -#define bFM3_BT6_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A51A8UL)) -#define bFM3_BT6_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) -#define bFM3_BT6_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) -#define bFM3_BT6_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) -#define bFM3_BT6_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5200UL)) -#define bFM3_BT6_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5208UL)) -#define bFM3_BT6_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5210UL)) -#define bFM3_BT6_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5218UL)) -#define bFM3_BT6_PWC_STC_ERR *((volatile unsigned int*)(0x424A521CUL)) -#define bFM3_BT6_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) - -/* Base Timer 7 PPG registers */ -#define bFM3_BT7_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM3_BT7_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM3_BT7_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM3_BT7_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM3_BT7_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM3_BT7_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM3_BT7_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) -#define bFM3_BT7_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 PWM registers */ -#define bFM3_BT7_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM3_BT7_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM3_BT7_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM3_BT7_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM3_BT7_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM3_BT7_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM3_BT7_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) -#define bFM3_BT7_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5A04UL)) -#define bFM3_BT7_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5A14UL)) -#define bFM3_BT7_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 RT registers */ -#define bFM3_BT7_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) -#define bFM3_BT7_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) -#define bFM3_BT7_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM3_BT7_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM3_BT7_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM3_BT7_RT_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) -#define bFM3_BT7_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_RT_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_RT_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_RT_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_RT_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer 7 PWC registers */ -#define bFM3_BT7_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) -#define bFM3_BT7_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) -#define bFM3_BT7_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) -#define bFM3_BT7_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) -#define bFM3_BT7_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) -#define bFM3_BT7_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) -#define bFM3_BT7_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) -#define bFM3_BT7_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) -#define bFM3_BT7_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A59A8UL)) -#define bFM3_BT7_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) -#define bFM3_BT7_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) -#define bFM3_BT7_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) -#define bFM3_BT7_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5A00UL)) -#define bFM3_BT7_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5A08UL)) -#define bFM3_BT7_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5A10UL)) -#define bFM3_BT7_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5A18UL)) -#define bFM3_BT7_PWC_STC_ERR *((volatile unsigned int*)(0x424A5A1CUL)) -#define bFM3_BT7_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) - -/* Base Timer I/O selector channel 0 - channel 3 registers */ -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0 *((volatile unsigned int*)(0x424A2020UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1 *((volatile unsigned int*)(0x424A2024UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2 *((volatile unsigned int*)(0x424A2028UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3 *((volatile unsigned int*)(0x424A202CUL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0 *((volatile unsigned int*)(0x424A2030UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1 *((volatile unsigned int*)(0x424A2034UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2 *((volatile unsigned int*)(0x424A2038UL)) -#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3 *((volatile unsigned int*)(0x424A203CUL)) - -/* Base Timer I/O selector channel 4 - channel 7 registers */ -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0 *((volatile unsigned int*)(0x424A6020UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1 *((volatile unsigned int*)(0x424A6024UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2 *((volatile unsigned int*)(0x424A6028UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3 *((volatile unsigned int*)(0x424A602CUL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0 *((volatile unsigned int*)(0x424A6030UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1 *((volatile unsigned int*)(0x424A6034UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2 *((volatile unsigned int*)(0x424A6038UL)) -#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3 *((volatile unsigned int*)(0x424A603CUL)) - -/* Software based Simulation Startup (Base Timer) register */ -#define bFM3_SBSSR_BTSSSR_SSR0 *((volatile unsigned int*)(0x424BFF80UL)) -#define bFM3_SBSSR_BTSSSR_SSR1 *((volatile unsigned int*)(0x424BFF84UL)) -#define bFM3_SBSSR_BTSSSR_SSR2 *((volatile unsigned int*)(0x424BFF88UL)) -#define bFM3_SBSSR_BTSSSR_SSR3 *((volatile unsigned int*)(0x424BFF8CUL)) -#define bFM3_SBSSR_BTSSSR_SSR4 *((volatile unsigned int*)(0x424BFF90UL)) -#define bFM3_SBSSR_BTSSSR_SSR5 *((volatile unsigned int*)(0x424BFF94UL)) -#define bFM3_SBSSR_BTSSSR_SSR6 *((volatile unsigned int*)(0x424BFF98UL)) -#define bFM3_SBSSR_BTSSSR_SSR7 *((volatile unsigned int*)(0x424BFF9CUL)) -#define bFM3_SBSSR_BTSSSR_SSR8 *((volatile unsigned int*)(0x424BFFA0UL)) -#define bFM3_SBSSR_BTSSSR_SSR9 *((volatile unsigned int*)(0x424BFFA4UL)) -#define bFM3_SBSSR_BTSSSR_SSR10 *((volatile unsigned int*)(0x424BFFA8UL)) -#define bFM3_SBSSR_BTSSSR_SSR11 *((volatile unsigned int*)(0x424BFFACUL)) -#define bFM3_SBSSR_BTSSSR_SSR12 *((volatile unsigned int*)(0x424BFFB0UL)) -#define bFM3_SBSSR_BTSSSR_SSR13 *((volatile unsigned int*)(0x424BFFB4UL)) -#define bFM3_SBSSR_BTSSSR_SSR14 *((volatile unsigned int*)(0x424BFFB8UL)) -#define bFM3_SBSSR_BTSSSR_SSR15 *((volatile unsigned int*)(0x424BFFBCUL)) - -/* Quad position and revolution counter channel 0 registers */ -#define bFM3_QPRC0_QICR_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) -#define bFM3_QPRC0_QICR_QPCMF *((volatile unsigned int*)(0x424C0284UL)) -#define bFM3_QPRC0_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) -#define bFM3_QPRC0_QICR_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) -#define bFM3_QPRC0_QICR_OUZIE *((volatile unsigned int*)(0x424C0290UL)) -#define bFM3_QPRC0_QICR_UFDF *((volatile unsigned int*)(0x424C0294UL)) -#define bFM3_QPRC0_QICR_OFDF *((volatile unsigned int*)(0x424C0298UL)) -#define bFM3_QPRC0_QICR_ZIIF *((volatile unsigned int*)(0x424C029CUL)) -#define bFM3_QPRC0_QICR_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) -#define bFM3_QPRC0_QICR_CDCF *((volatile unsigned int*)(0x424C02A4UL)) -#define bFM3_QPRC0_QICR_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) -#define bFM3_QPRC0_QICR_DIROU *((volatile unsigned int*)(0x424C02ACUL)) -#define bFM3_QPRC0_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) -#define bFM3_QPRC0_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) -#define bFM3_QPRC0_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) -#define bFM3_QPRC0_QICRL_QPCMF *((volatile unsigned int*)(0x424C0284UL)) -#define bFM3_QPRC0_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) -#define bFM3_QPRC0_QICRL_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) -#define bFM3_QPRC0_QICRL_OUZIE *((volatile unsigned int*)(0x424C0290UL)) -#define bFM3_QPRC0_QICRL_UFDF *((volatile unsigned int*)(0x424C0294UL)) -#define bFM3_QPRC0_QICRL_OFDF *((volatile unsigned int*)(0x424C0298UL)) -#define bFM3_QPRC0_QICRL_ZIIF *((volatile unsigned int*)(0x424C029CUL)) -#define bFM3_QPRC0_QICRH_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) -#define bFM3_QPRC0_QICRH_CDCF *((volatile unsigned int*)(0x424C02A4UL)) -#define bFM3_QPRC0_QICRH_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) -#define bFM3_QPRC0_QICRH_DIROU *((volatile unsigned int*)(0x424C02ACUL)) -#define bFM3_QPRC0_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) -#define bFM3_QPRC0_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) -#define bFM3_QPRC0_QCR_PCM0 *((volatile unsigned int*)(0x424C0300UL)) -#define bFM3_QPRC0_QCR_PCM1 *((volatile unsigned int*)(0x424C0304UL)) -#define bFM3_QPRC0_QCR_RCM0 *((volatile unsigned int*)(0x424C0308UL)) -#define bFM3_QPRC0_QCR_RCM1 *((volatile unsigned int*)(0x424C030CUL)) -#define bFM3_QPRC0_QCR_PSTP *((volatile unsigned int*)(0x424C0310UL)) -#define bFM3_QPRC0_QCR_CGSC *((volatile unsigned int*)(0x424C0314UL)) -#define bFM3_QPRC0_QCR_RSEL *((volatile unsigned int*)(0x424C0318UL)) -#define bFM3_QPRC0_QCR_SWAP *((volatile unsigned int*)(0x424C031CUL)) -#define bFM3_QPRC0_QCR_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) -#define bFM3_QPRC0_QCR_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) -#define bFM3_QPRC0_QCR_AES0 *((volatile unsigned int*)(0x424C0328UL)) -#define bFM3_QPRC0_QCR_AES1 *((volatile unsigned int*)(0x424C032CUL)) -#define bFM3_QPRC0_QCR_BES0 *((volatile unsigned int*)(0x424C0330UL)) -#define bFM3_QPRC0_QCR_BES1 *((volatile unsigned int*)(0x424C0334UL)) -#define bFM3_QPRC0_QCR_CGE0 *((volatile unsigned int*)(0x424C0338UL)) -#define bFM3_QPRC0_QCR_CGE1 *((volatile unsigned int*)(0x424C033CUL)) -#define bFM3_QPRC0_QCRL_PCM0 *((volatile unsigned int*)(0x424C0300UL)) -#define bFM3_QPRC0_QCRL_PCM1 *((volatile unsigned int*)(0x424C0304UL)) -#define bFM3_QPRC0_QCRL_RCM0 *((volatile unsigned int*)(0x424C0308UL)) -#define bFM3_QPRC0_QCRL_RCM1 *((volatile unsigned int*)(0x424C030CUL)) -#define bFM3_QPRC0_QCRL_PSTP *((volatile unsigned int*)(0x424C0310UL)) -#define bFM3_QPRC0_QCRL_CGSC *((volatile unsigned int*)(0x424C0314UL)) -#define bFM3_QPRC0_QCRL_RSEL *((volatile unsigned int*)(0x424C0318UL)) -#define bFM3_QPRC0_QCRL_SWAP *((volatile unsigned int*)(0x424C031CUL)) -#define bFM3_QPRC0_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) -#define bFM3_QPRC0_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) -#define bFM3_QPRC0_QCRH_AES0 *((volatile unsigned int*)(0x424C0328UL)) -#define bFM3_QPRC0_QCRH_AES1 *((volatile unsigned int*)(0x424C032CUL)) -#define bFM3_QPRC0_QCRH_BES0 *((volatile unsigned int*)(0x424C0330UL)) -#define bFM3_QPRC0_QCRH_BES1 *((volatile unsigned int*)(0x424C0334UL)) -#define bFM3_QPRC0_QCRH_CGE0 *((volatile unsigned int*)(0x424C0338UL)) -#define bFM3_QPRC0_QCRH_CGE1 *((volatile unsigned int*)(0x424C033CUL)) -#define bFM3_QPRC0_QECR_ORNGMD *((volatile unsigned int*)(0x424C0380UL)) -#define bFM3_QPRC0_QECR_ORNGF *((volatile unsigned int*)(0x424C0384UL)) -#define bFM3_QPRC0_QECR_ORNGIE *((volatile unsigned int*)(0x424C0388UL)) - -/* Quad position and revolution counter channel 1 registers */ -#define bFM3_QPRC1_QICR_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) -#define bFM3_QPRC1_QICR_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) -#define bFM3_QPRC1_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) -#define bFM3_QPRC1_QICR_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) -#define bFM3_QPRC1_QICR_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) -#define bFM3_QPRC1_QICR_UFDF *((volatile unsigned int*)(0x424C0A94UL)) -#define bFM3_QPRC1_QICR_OFDF *((volatile unsigned int*)(0x424C0A98UL)) -#define bFM3_QPRC1_QICR_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) -#define bFM3_QPRC1_QICR_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) -#define bFM3_QPRC1_QICR_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) -#define bFM3_QPRC1_QICR_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) -#define bFM3_QPRC1_QICR_DIROU *((volatile unsigned int*)(0x424C0AACUL)) -#define bFM3_QPRC1_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) -#define bFM3_QPRC1_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) -#define bFM3_QPRC1_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) -#define bFM3_QPRC1_QICRL_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) -#define bFM3_QPRC1_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) -#define bFM3_QPRC1_QICRL_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) -#define bFM3_QPRC1_QICRL_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) -#define bFM3_QPRC1_QICRL_UFDF *((volatile unsigned int*)(0x424C0A94UL)) -#define bFM3_QPRC1_QICRL_OFDF *((volatile unsigned int*)(0x424C0A98UL)) -#define bFM3_QPRC1_QICRL_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) -#define bFM3_QPRC1_QICRH_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) -#define bFM3_QPRC1_QICRH_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) -#define bFM3_QPRC1_QICRH_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) -#define bFM3_QPRC1_QICRH_DIROU *((volatile unsigned int*)(0x424C0AACUL)) -#define bFM3_QPRC1_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) -#define bFM3_QPRC1_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) -#define bFM3_QPRC1_QCR_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) -#define bFM3_QPRC1_QCR_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) -#define bFM3_QPRC1_QCR_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) -#define bFM3_QPRC1_QCR_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) -#define bFM3_QPRC1_QCR_PSTP *((volatile unsigned int*)(0x424C0B10UL)) -#define bFM3_QPRC1_QCR_CGSC *((volatile unsigned int*)(0x424C0B14UL)) -#define bFM3_QPRC1_QCR_RSEL *((volatile unsigned int*)(0x424C0B18UL)) -#define bFM3_QPRC1_QCR_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) -#define bFM3_QPRC1_QCR_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) -#define bFM3_QPRC1_QCR_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) -#define bFM3_QPRC1_QCR_AES0 *((volatile unsigned int*)(0x424C0B28UL)) -#define bFM3_QPRC1_QCR_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) -#define bFM3_QPRC1_QCR_BES0 *((volatile unsigned int*)(0x424C0B30UL)) -#define bFM3_QPRC1_QCR_BES1 *((volatile unsigned int*)(0x424C0B34UL)) -#define bFM3_QPRC1_QCR_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) -#define bFM3_QPRC1_QCR_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) -#define bFM3_QPRC1_QCRL_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) -#define bFM3_QPRC1_QCRL_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) -#define bFM3_QPRC1_QCRL_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) -#define bFM3_QPRC1_QCRL_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) -#define bFM3_QPRC1_QCRL_PSTP *((volatile unsigned int*)(0x424C0B10UL)) -#define bFM3_QPRC1_QCRL_CGSC *((volatile unsigned int*)(0x424C0B14UL)) -#define bFM3_QPRC1_QCRL_RSEL *((volatile unsigned int*)(0x424C0B18UL)) -#define bFM3_QPRC1_QCRL_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) -#define bFM3_QPRC1_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) -#define bFM3_QPRC1_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) -#define bFM3_QPRC1_QCRH_AES0 *((volatile unsigned int*)(0x424C0B28UL)) -#define bFM3_QPRC1_QCRH_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) -#define bFM3_QPRC1_QCRH_BES0 *((volatile unsigned int*)(0x424C0B30UL)) -#define bFM3_QPRC1_QCRH_BES1 *((volatile unsigned int*)(0x424C0B34UL)) -#define bFM3_QPRC1_QCRH_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) -#define bFM3_QPRC1_QCRH_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) -#define bFM3_QPRC1_QECR_ORNGMD *((volatile unsigned int*)(0x424C0B80UL)) -#define bFM3_QPRC1_QECR_ORNGF *((volatile unsigned int*)(0x424C0B84UL)) -#define bFM3_QPRC1_QECR_ORNGIE *((volatile unsigned int*)(0x424C0B88UL)) - -/* 12-bit ADC unit 0 registers */ -#define bFM3_ADC0_ADSR_SCS *((volatile unsigned int*)(0x424E0000UL)) -#define bFM3_ADC0_ADSR_PCS *((volatile unsigned int*)(0x424E0004UL)) -#define bFM3_ADC0_ADSR_PCNS *((volatile unsigned int*)(0x424E0008UL)) -#define bFM3_ADC0_ADSR_FDAS *((volatile unsigned int*)(0x424E0018UL)) -#define bFM3_ADC0_ADSR_ADSTP *((volatile unsigned int*)(0x424E001CUL)) -#define bFM3_ADC0_ADCR_OVRIE *((volatile unsigned int*)(0x424E0020UL)) -#define bFM3_ADC0_ADCR_CMPIE *((volatile unsigned int*)(0x424E0024UL)) -#define bFM3_ADC0_ADCR_PCIE *((volatile unsigned int*)(0x424E0028UL)) -#define bFM3_ADC0_ADCR_SCIE *((volatile unsigned int*)(0x424E002CUL)) -#define bFM3_ADC0_ADCR_CMPIF *((volatile unsigned int*)(0x424E0034UL)) -#define bFM3_ADC0_ADCR_PCIF *((volatile unsigned int*)(0x424E0038UL)) -#define bFM3_ADC0_ADCR_SCIF *((volatile unsigned int*)(0x424E003CUL)) -#define bFM3_ADC0_SFNS_SFS0 *((volatile unsigned int*)(0x424E0100UL)) -#define bFM3_ADC0_SFNS_SFS1 *((volatile unsigned int*)(0x424E0104UL)) -#define bFM3_ADC0_SFNS_SFS2 *((volatile unsigned int*)(0x424E0108UL)) -#define bFM3_ADC0_SFNS_SFS3 *((volatile unsigned int*)(0x424E010CUL)) -#define bFM3_ADC0_SCCR_SSTR *((volatile unsigned int*)(0x424E0120UL)) -#define bFM3_ADC0_SCCR_SHEN *((volatile unsigned int*)(0x424E0124UL)) -#define bFM3_ADC0_SCCR_RPT *((volatile unsigned int*)(0x424E0128UL)) -#define bFM3_ADC0_SCCR_SFCLR *((volatile unsigned int*)(0x424E0130UL)) -#define bFM3_ADC0_SCCR_SOVR *((volatile unsigned int*)(0x424E0134UL)) -#define bFM3_ADC0_SCCR_SFUL *((volatile unsigned int*)(0x424E0138UL)) -#define bFM3_ADC0_SCCR_SEMP *((volatile unsigned int*)(0x424E013CUL)) -#define bFM3_ADC0_SCFD_SC0 *((volatile unsigned int*)(0x424E0180UL)) -#define bFM3_ADC0_SCFD_SC1 *((volatile unsigned int*)(0x424E0184UL)) -#define bFM3_ADC0_SCFD_SC2 *((volatile unsigned int*)(0x424E0188UL)) -#define bFM3_ADC0_SCFD_SC3 *((volatile unsigned int*)(0x424E018CUL)) -#define bFM3_ADC0_SCFD_SC4 *((volatile unsigned int*)(0x424E0190UL)) -#define bFM3_ADC0_SCFD_RS0 *((volatile unsigned int*)(0x424E01A0UL)) -#define bFM3_ADC0_SCFD_RS1 *((volatile unsigned int*)(0x424E01A4UL)) -#define bFM3_ADC0_SCFD_INVL *((volatile unsigned int*)(0x424E01B0UL)) -#define bFM3_ADC0_SCFD_SD0 *((volatile unsigned int*)(0x424E01D0UL)) -#define bFM3_ADC0_SCFD_SD1 *((volatile unsigned int*)(0x424E01D4UL)) -#define bFM3_ADC0_SCFD_SD2 *((volatile unsigned int*)(0x424E01D8UL)) -#define bFM3_ADC0_SCFD_SD3 *((volatile unsigned int*)(0x424E01DCUL)) -#define bFM3_ADC0_SCFD_SD4 *((volatile unsigned int*)(0x424E01E0UL)) -#define bFM3_ADC0_SCFD_SD5 *((volatile unsigned int*)(0x424E01E4UL)) -#define bFM3_ADC0_SCFD_SD6 *((volatile unsigned int*)(0x424E01E8UL)) -#define bFM3_ADC0_SCFD_SD7 *((volatile unsigned int*)(0x424E01ECUL)) -#define bFM3_ADC0_SCFD_SD8 *((volatile unsigned int*)(0x424E01F0UL)) -#define bFM3_ADC0_SCFD_SD9 *((volatile unsigned int*)(0x424E01F4UL)) -#define bFM3_ADC0_SCFD_SD10 *((volatile unsigned int*)(0x424E01F8UL)) -#define bFM3_ADC0_SCFD_SD11 *((volatile unsigned int*)(0x424E01FCUL)) -#define bFM3_ADC0_SCFDL_SC0 *((volatile unsigned int*)(0x424E0180UL)) -#define bFM3_ADC0_SCFDL_SC1 *((volatile unsigned int*)(0x424E0184UL)) -#define bFM3_ADC0_SCFDL_SC2 *((volatile unsigned int*)(0x424E0188UL)) -#define bFM3_ADC0_SCFDL_SC3 *((volatile unsigned int*)(0x424E018CUL)) -#define bFM3_ADC0_SCFDL_SC4 *((volatile unsigned int*)(0x424E0190UL)) -#define bFM3_ADC0_SCFDL_RS0 *((volatile unsigned int*)(0x424E01A0UL)) -#define bFM3_ADC0_SCFDL_RS1 *((volatile unsigned int*)(0x424E01A4UL)) -#define bFM3_ADC0_SCFDL_INVL *((volatile unsigned int*)(0x424E01B0UL)) -#define bFM3_ADC0_SCFDH_SD0 *((volatile unsigned int*)(0x424E01D0UL)) -#define bFM3_ADC0_SCFDH_SD1 *((volatile unsigned int*)(0x424E01D4UL)) -#define bFM3_ADC0_SCFDH_SD2 *((volatile unsigned int*)(0x424E01D8UL)) -#define bFM3_ADC0_SCFDH_SD3 *((volatile unsigned int*)(0x424E01DCUL)) -#define bFM3_ADC0_SCFDH_SD4 *((volatile unsigned int*)(0x424E01E0UL)) -#define bFM3_ADC0_SCFDH_SD5 *((volatile unsigned int*)(0x424E01E4UL)) -#define bFM3_ADC0_SCFDH_SD6 *((volatile unsigned int*)(0x424E01E8UL)) -#define bFM3_ADC0_SCFDH_SD7 *((volatile unsigned int*)(0x424E01ECUL)) -#define bFM3_ADC0_SCFDH_SD8 *((volatile unsigned int*)(0x424E01F0UL)) -#define bFM3_ADC0_SCFDH_SD9 *((volatile unsigned int*)(0x424E01F4UL)) -#define bFM3_ADC0_SCFDH_SD10 *((volatile unsigned int*)(0x424E01F8UL)) -#define bFM3_ADC0_SCFDH_SD11 *((volatile unsigned int*)(0x424E01FCUL)) -#define bFM3_ADC0_SCIS23_AN16 *((volatile unsigned int*)(0x424E0200UL)) -#define bFM3_ADC0_SCIS23_AN17 *((volatile unsigned int*)(0x424E0204UL)) -#define bFM3_ADC0_SCIS23_AN18 *((volatile unsigned int*)(0x424E0208UL)) -#define bFM3_ADC0_SCIS23_AN19 *((volatile unsigned int*)(0x424E020CUL)) -#define bFM3_ADC0_SCIS23_AN20 *((volatile unsigned int*)(0x424E0210UL)) -#define bFM3_ADC0_SCIS23_AN21 *((volatile unsigned int*)(0x424E0214UL)) -#define bFM3_ADC0_SCIS23_AN22 *((volatile unsigned int*)(0x424E0218UL)) -#define bFM3_ADC0_SCIS23_AN23 *((volatile unsigned int*)(0x424E021CUL)) -#define bFM3_ADC0_SCIS23_AN24 *((volatile unsigned int*)(0x424E0220UL)) -#define bFM3_ADC0_SCIS23_AN25 *((volatile unsigned int*)(0x424E0224UL)) -#define bFM3_ADC0_SCIS23_AN26 *((volatile unsigned int*)(0x424E0228UL)) -#define bFM3_ADC0_SCIS23_AN27 *((volatile unsigned int*)(0x424E022CUL)) -#define bFM3_ADC0_SCIS23_AN28 *((volatile unsigned int*)(0x424E0230UL)) -#define bFM3_ADC0_SCIS23_AN29 *((volatile unsigned int*)(0x424E0234UL)) -#define bFM3_ADC0_SCIS23_AN30 *((volatile unsigned int*)(0x424E0238UL)) -#define bFM3_ADC0_SCIS23_AN31 *((volatile unsigned int*)(0x424E023CUL)) -#define bFM3_ADC0_SCIS2_AN16 *((volatile unsigned int*)(0x424E0200UL)) -#define bFM3_ADC0_SCIS2_AN17 *((volatile unsigned int*)(0x424E0204UL)) -#define bFM3_ADC0_SCIS2_AN18 *((volatile unsigned int*)(0x424E0208UL)) -#define bFM3_ADC0_SCIS2_AN19 *((volatile unsigned int*)(0x424E020CUL)) -#define bFM3_ADC0_SCIS2_AN20 *((volatile unsigned int*)(0x424E0210UL)) -#define bFM3_ADC0_SCIS2_AN21 *((volatile unsigned int*)(0x424E0214UL)) -#define bFM3_ADC0_SCIS2_AN22 *((volatile unsigned int*)(0x424E0218UL)) -#define bFM3_ADC0_SCIS2_AN23 *((volatile unsigned int*)(0x424E021CUL)) -#define bFM3_ADC0_SCIS3_AN24 *((volatile unsigned int*)(0x424E0220UL)) -#define bFM3_ADC0_SCIS3_AN25 *((volatile unsigned int*)(0x424E0224UL)) -#define bFM3_ADC0_SCIS3_AN26 *((volatile unsigned int*)(0x424E0228UL)) -#define bFM3_ADC0_SCIS3_AN27 *((volatile unsigned int*)(0x424E022CUL)) -#define bFM3_ADC0_SCIS3_AN28 *((volatile unsigned int*)(0x424E0230UL)) -#define bFM3_ADC0_SCIS3_AN29 *((volatile unsigned int*)(0x424E0234UL)) -#define bFM3_ADC0_SCIS3_AN30 *((volatile unsigned int*)(0x424E0238UL)) -#define bFM3_ADC0_SCIS3_AN31 *((volatile unsigned int*)(0x424E023CUL)) -#define bFM3_ADC0_SCIS01_AN0 *((volatile unsigned int*)(0x424E0280UL)) -#define bFM3_ADC0_SCIS01_AN1 *((volatile unsigned int*)(0x424E0284UL)) -#define bFM3_ADC0_SCIS01_AN2 *((volatile unsigned int*)(0x424E0288UL)) -#define bFM3_ADC0_SCIS01_AN3 *((volatile unsigned int*)(0x424E028CUL)) -#define bFM3_ADC0_SCIS01_AN4 *((volatile unsigned int*)(0x424E0290UL)) -#define bFM3_ADC0_SCIS01_AN5 *((volatile unsigned int*)(0x424E0294UL)) -#define bFM3_ADC0_SCIS01_AN6 *((volatile unsigned int*)(0x424E0298UL)) -#define bFM3_ADC0_SCIS01_AN7 *((volatile unsigned int*)(0x424E029CUL)) -#define bFM3_ADC0_SCIS01_AN8 *((volatile unsigned int*)(0x424E02A0UL)) -#define bFM3_ADC0_SCIS01_AN9 *((volatile unsigned int*)(0x424E02A4UL)) -#define bFM3_ADC0_SCIS01_AN10 *((volatile unsigned int*)(0x424E02A8UL)) -#define bFM3_ADC0_SCIS01_AN11 *((volatile unsigned int*)(0x424E02ACUL)) -#define bFM3_ADC0_SCIS01_AN12 *((volatile unsigned int*)(0x424E02B0UL)) -#define bFM3_ADC0_SCIS01_AN13 *((volatile unsigned int*)(0x424E02B4UL)) -#define bFM3_ADC0_SCIS01_AN14 *((volatile unsigned int*)(0x424E02B8UL)) -#define bFM3_ADC0_SCIS01_AN15 *((volatile unsigned int*)(0x424E02BCUL)) -#define bFM3_ADC0_SCIS0_AN0 *((volatile unsigned int*)(0x424E0280UL)) -#define bFM3_ADC0_SCIS0_AN1 *((volatile unsigned int*)(0x424E0284UL)) -#define bFM3_ADC0_SCIS0_AN2 *((volatile unsigned int*)(0x424E0288UL)) -#define bFM3_ADC0_SCIS0_AN3 *((volatile unsigned int*)(0x424E028CUL)) -#define bFM3_ADC0_SCIS0_AN4 *((volatile unsigned int*)(0x424E0290UL)) -#define bFM3_ADC0_SCIS0_AN5 *((volatile unsigned int*)(0x424E0294UL)) -#define bFM3_ADC0_SCIS0_AN6 *((volatile unsigned int*)(0x424E0298UL)) -#define bFM3_ADC0_SCIS0_AN7 *((volatile unsigned int*)(0x424E029CUL)) -#define bFM3_ADC0_SCIS1_AN8 *((volatile unsigned int*)(0x424E02A0UL)) -#define bFM3_ADC0_SCIS1_AN9 *((volatile unsigned int*)(0x424E02A4UL)) -#define bFM3_ADC0_SCIS1_AN10 *((volatile unsigned int*)(0x424E02A8UL)) -#define bFM3_ADC0_SCIS1_AN11 *((volatile unsigned int*)(0x424E02ACUL)) -#define bFM3_ADC0_SCIS1_AN12 *((volatile unsigned int*)(0x424E02B0UL)) -#define bFM3_ADC0_SCIS1_AN13 *((volatile unsigned int*)(0x424E02B4UL)) -#define bFM3_ADC0_SCIS1_AN14 *((volatile unsigned int*)(0x424E02B8UL)) -#define bFM3_ADC0_SCIS1_AN15 *((volatile unsigned int*)(0x424E02BCUL)) -#define bFM3_ADC0_PFNS_PFS0 *((volatile unsigned int*)(0x424E0300UL)) -#define bFM3_ADC0_PFNS_PFS1 *((volatile unsigned int*)(0x424E0304UL)) -#define bFM3_ADC0_PFNS_TEST0 *((volatile unsigned int*)(0x424E0310UL)) -#define bFM3_ADC0_PFNS_TEST1 *((volatile unsigned int*)(0x424E0314UL)) -#define bFM3_ADC0_PCCR_PSTR *((volatile unsigned int*)(0x424E0320UL)) -#define bFM3_ADC0_PCCR_PHEN *((volatile unsigned int*)(0x424E0324UL)) -#define bFM3_ADC0_PCCR_PEEN *((volatile unsigned int*)(0x424E0328UL)) -#define bFM3_ADC0_PCCR_ESCE *((volatile unsigned int*)(0x424E032CUL)) -#define bFM3_ADC0_PCCR_PFCLR *((volatile unsigned int*)(0x424E0330UL)) -#define bFM3_ADC0_PCCR_POVR *((volatile unsigned int*)(0x424E0334UL)) -#define bFM3_ADC0_PCCR_PFUL *((volatile unsigned int*)(0x424E0338UL)) -#define bFM3_ADC0_PCCR_PEMP *((volatile unsigned int*)(0x424E033CUL)) -#define bFM3_ADC0_PCFD_PC0 *((volatile unsigned int*)(0x424E0380UL)) -#define bFM3_ADC0_PCFD_PC1 *((volatile unsigned int*)(0x424E0384UL)) -#define bFM3_ADC0_PCFD_PC2 *((volatile unsigned int*)(0x424E0388UL)) -#define bFM3_ADC0_PCFD_PC3 *((volatile unsigned int*)(0x424E038CUL)) -#define bFM3_ADC0_PCFD_PC4 *((volatile unsigned int*)(0x424E0390UL)) -#define bFM3_ADC0_PCFD_RS0 *((volatile unsigned int*)(0x424E03A0UL)) -#define bFM3_ADC0_PCFD_RS1 *((volatile unsigned int*)(0x424E03A4UL)) -#define bFM3_ADC0_PCFD_RS2 *((volatile unsigned int*)(0x424E03A8UL)) -#define bFM3_ADC0_PCFD_INVL *((volatile unsigned int*)(0x424E03B0UL)) -#define bFM3_ADC0_PCFD_PD0 *((volatile unsigned int*)(0x424E03D0UL)) -#define bFM3_ADC0_PCFD_PD1 *((volatile unsigned int*)(0x424E03D4UL)) -#define bFM3_ADC0_PCFD_PD2 *((volatile unsigned int*)(0x424E03D8UL)) -#define bFM3_ADC0_PCFD_PD3 *((volatile unsigned int*)(0x424E03DCUL)) -#define bFM3_ADC0_PCFD_PD4 *((volatile unsigned int*)(0x424E03E0UL)) -#define bFM3_ADC0_PCFD_PD5 *((volatile unsigned int*)(0x424E03E4UL)) -#define bFM3_ADC0_PCFD_PD6 *((volatile unsigned int*)(0x424E03E8UL)) -#define bFM3_ADC0_PCFD_PD7 *((volatile unsigned int*)(0x424E03ECUL)) -#define bFM3_ADC0_PCFD_PD8 *((volatile unsigned int*)(0x424E03F0UL)) -#define bFM3_ADC0_PCFD_PD9 *((volatile unsigned int*)(0x424E03F4UL)) -#define bFM3_ADC0_PCFD_PD10 *((volatile unsigned int*)(0x424E03F8UL)) -#define bFM3_ADC0_PCFD_PD11 *((volatile unsigned int*)(0x424E03FCUL)) -#define bFM3_ADC0_PCFDL_PC0 *((volatile unsigned int*)(0x424E0380UL)) -#define bFM3_ADC0_PCFDL_PC1 *((volatile unsigned int*)(0x424E0384UL)) -#define bFM3_ADC0_PCFDL_PC2 *((volatile unsigned int*)(0x424E0388UL)) -#define bFM3_ADC0_PCFDL_PC3 *((volatile unsigned int*)(0x424E038CUL)) -#define bFM3_ADC0_PCFDL_PC4 *((volatile unsigned int*)(0x424E0390UL)) -#define bFM3_ADC0_PCFDL_RS0 *((volatile unsigned int*)(0x424E03A0UL)) -#define bFM3_ADC0_PCFDL_RS1 *((volatile unsigned int*)(0x424E03A4UL)) -#define bFM3_ADC0_PCFDL_RS2 *((volatile unsigned int*)(0x424E03A8UL)) -#define bFM3_ADC0_PCFDL_INVL *((volatile unsigned int*)(0x424E03B0UL)) -#define bFM3_ADC0_PCFDH_PD0 *((volatile unsigned int*)(0x424E03D0UL)) -#define bFM3_ADC0_PCFDH_PD1 *((volatile unsigned int*)(0x424E03D4UL)) -#define bFM3_ADC0_PCFDH_PD2 *((volatile unsigned int*)(0x424E03D8UL)) -#define bFM3_ADC0_PCFDH_PD3 *((volatile unsigned int*)(0x424E03DCUL)) -#define bFM3_ADC0_PCFDH_PD4 *((volatile unsigned int*)(0x424E03E0UL)) -#define bFM3_ADC0_PCFDH_PD5 *((volatile unsigned int*)(0x424E03E4UL)) -#define bFM3_ADC0_PCFDH_PD6 *((volatile unsigned int*)(0x424E03E8UL)) -#define bFM3_ADC0_PCFDH_PD7 *((volatile unsigned int*)(0x424E03ECUL)) -#define bFM3_ADC0_PCFDH_PD8 *((volatile unsigned int*)(0x424E03F0UL)) -#define bFM3_ADC0_PCFDH_PD9 *((volatile unsigned int*)(0x424E03F4UL)) -#define bFM3_ADC0_PCFDH_PD10 *((volatile unsigned int*)(0x424E03F8UL)) -#define bFM3_ADC0_PCFDH_PD11 *((volatile unsigned int*)(0x424E03FCUL)) -#define bFM3_ADC0_PCIS_P1A0 *((volatile unsigned int*)(0x424E0400UL)) -#define bFM3_ADC0_PCIS_P1A1 *((volatile unsigned int*)(0x424E0404UL)) -#define bFM3_ADC0_PCIS_P1A2 *((volatile unsigned int*)(0x424E0408UL)) -#define bFM3_ADC0_PCIS_P2A0 *((volatile unsigned int*)(0x424E040CUL)) -#define bFM3_ADC0_PCIS_P2A1 *((volatile unsigned int*)(0x424E0410UL)) -#define bFM3_ADC0_PCIS_P2A2 *((volatile unsigned int*)(0x424E0414UL)) -#define bFM3_ADC0_PCIS_P2A3 *((volatile unsigned int*)(0x424E0418UL)) -#define bFM3_ADC0_PCIS_P2A4 *((volatile unsigned int*)(0x424E041CUL)) -#define bFM3_ADC0_CMPCR_CCH0 *((volatile unsigned int*)(0x424E0480UL)) -#define bFM3_ADC0_CMPCR_CCH1 *((volatile unsigned int*)(0x424E0484UL)) -#define bFM3_ADC0_CMPCR_CCH2 *((volatile unsigned int*)(0x424E0488UL)) -#define bFM3_ADC0_CMPCR_CCH3 *((volatile unsigned int*)(0x424E048CUL)) -#define bFM3_ADC0_CMPCR_CCH4 *((volatile unsigned int*)(0x424E0490UL)) -#define bFM3_ADC0_CMPCR_CMD0 *((volatile unsigned int*)(0x424E0494UL)) -#define bFM3_ADC0_CMPCR_CMD1 *((volatile unsigned int*)(0x424E0498UL)) -#define bFM3_ADC0_CMPCR_CMPEN *((volatile unsigned int*)(0x424E049CUL)) -#define bFM3_ADC0_CMPD_CMAD2 *((volatile unsigned int*)(0x424E04D8UL)) -#define bFM3_ADC0_CMPD_CMAD3 *((volatile unsigned int*)(0x424E04DCUL)) -#define bFM3_ADC0_CMPD_CMAD4 *((volatile unsigned int*)(0x424E04E0UL)) -#define bFM3_ADC0_CMPD_CMAD5 *((volatile unsigned int*)(0x424E04E4UL)) -#define bFM3_ADC0_CMPD_CMAD6 *((volatile unsigned int*)(0x424E04E8UL)) -#define bFM3_ADC0_CMPD_CMAD7 *((volatile unsigned int*)(0x424E04ECUL)) -#define bFM3_ADC0_CMPD_CMAD8 *((volatile unsigned int*)(0x424E04F0UL)) -#define bFM3_ADC0_CMPD_CMAD9 *((volatile unsigned int*)(0x424E04F4UL)) -#define bFM3_ADC0_CMPD_CMAD10 *((volatile unsigned int*)(0x424E04F8UL)) -#define bFM3_ADC0_CMPD_CMAD11 *((volatile unsigned int*)(0x424E04FCUL)) -#define bFM3_ADC0_ADSS23_TS16 *((volatile unsigned int*)(0x424E0500UL)) -#define bFM3_ADC0_ADSS23_TS17 *((volatile unsigned int*)(0x424E0504UL)) -#define bFM3_ADC0_ADSS23_TS18 *((volatile unsigned int*)(0x424E0508UL)) -#define bFM3_ADC0_ADSS23_TS19 *((volatile unsigned int*)(0x424E050CUL)) -#define bFM3_ADC0_ADSS23_TS20 *((volatile unsigned int*)(0x424E0510UL)) -#define bFM3_ADC0_ADSS23_TS21 *((volatile unsigned int*)(0x424E0514UL)) -#define bFM3_ADC0_ADSS23_TS22 *((volatile unsigned int*)(0x424E0518UL)) -#define bFM3_ADC0_ADSS23_TS23 *((volatile unsigned int*)(0x424E051CUL)) -#define bFM3_ADC0_ADSS23_TS24 *((volatile unsigned int*)(0x424E0520UL)) -#define bFM3_ADC0_ADSS23_TS25 *((volatile unsigned int*)(0x424E0524UL)) -#define bFM3_ADC0_ADSS23_TS26 *((volatile unsigned int*)(0x424E0528UL)) -#define bFM3_ADC0_ADSS23_TS27 *((volatile unsigned int*)(0x424E052CUL)) -#define bFM3_ADC0_ADSS23_TS28 *((volatile unsigned int*)(0x424E0530UL)) -#define bFM3_ADC0_ADSS23_TS29 *((volatile unsigned int*)(0x424E0534UL)) -#define bFM3_ADC0_ADSS23_TS30 *((volatile unsigned int*)(0x424E0538UL)) -#define bFM3_ADC0_ADSS23_TS31 *((volatile unsigned int*)(0x424E053CUL)) -#define bFM3_ADC0_ADSS2_TS16 *((volatile unsigned int*)(0x424E0500UL)) -#define bFM3_ADC0_ADSS2_TS17 *((volatile unsigned int*)(0x424E0504UL)) -#define bFM3_ADC0_ADSS2_TS18 *((volatile unsigned int*)(0x424E0508UL)) -#define bFM3_ADC0_ADSS2_TS19 *((volatile unsigned int*)(0x424E050CUL)) -#define bFM3_ADC0_ADSS2_TS20 *((volatile unsigned int*)(0x424E0510UL)) -#define bFM3_ADC0_ADSS2_TS21 *((volatile unsigned int*)(0x424E0514UL)) -#define bFM3_ADC0_ADSS2_TS22 *((volatile unsigned int*)(0x424E0518UL)) -#define bFM3_ADC0_ADSS2_TS23 *((volatile unsigned int*)(0x424E051CUL)) -#define bFM3_ADC0_ADSS3_TS24 *((volatile unsigned int*)(0x424E0520UL)) -#define bFM3_ADC0_ADSS3_TS25 *((volatile unsigned int*)(0x424E0524UL)) -#define bFM3_ADC0_ADSS3_TS26 *((volatile unsigned int*)(0x424E0528UL)) -#define bFM3_ADC0_ADSS3_TS27 *((volatile unsigned int*)(0x424E052CUL)) -#define bFM3_ADC0_ADSS3_TS28 *((volatile unsigned int*)(0x424E0530UL)) -#define bFM3_ADC0_ADSS3_TS29 *((volatile unsigned int*)(0x424E0534UL)) -#define bFM3_ADC0_ADSS3_TS30 *((volatile unsigned int*)(0x424E0538UL)) -#define bFM3_ADC0_ADSS3_TS31 *((volatile unsigned int*)(0x424E053CUL)) -#define bFM3_ADC0_ADSS01_TS0 *((volatile unsigned int*)(0x424E0580UL)) -#define bFM3_ADC0_ADSS01_TS1 *((volatile unsigned int*)(0x424E0584UL)) -#define bFM3_ADC0_ADSS01_TS2 *((volatile unsigned int*)(0x424E0588UL)) -#define bFM3_ADC0_ADSS01_TS3 *((volatile unsigned int*)(0x424E058CUL)) -#define bFM3_ADC0_ADSS01_TS4 *((volatile unsigned int*)(0x424E0590UL)) -#define bFM3_ADC0_ADSS01_TS5 *((volatile unsigned int*)(0x424E0594UL)) -#define bFM3_ADC0_ADSS01_TS6 *((volatile unsigned int*)(0x424E0598UL)) -#define bFM3_ADC0_ADSS01_TS7 *((volatile unsigned int*)(0x424E059CUL)) -#define bFM3_ADC0_ADSS01_TS8 *((volatile unsigned int*)(0x424E05A0UL)) -#define bFM3_ADC0_ADSS01_TS9 *((volatile unsigned int*)(0x424E05A4UL)) -#define bFM3_ADC0_ADSS01_TS10 *((volatile unsigned int*)(0x424E05A8UL)) -#define bFM3_ADC0_ADSS01_TS11 *((volatile unsigned int*)(0x424E05ACUL)) -#define bFM3_ADC0_ADSS01_TS12 *((volatile unsigned int*)(0x424E05B0UL)) -#define bFM3_ADC0_ADSS01_TS13 *((volatile unsigned int*)(0x424E05B4UL)) -#define bFM3_ADC0_ADSS01_TS14 *((volatile unsigned int*)(0x424E05B8UL)) -#define bFM3_ADC0_ADSS01_TS15 *((volatile unsigned int*)(0x424E05BCUL)) -#define bFM3_ADC0_ADSS0_TS0 *((volatile unsigned int*)(0x424E0580UL)) -#define bFM3_ADC0_ADSS0_TS1 *((volatile unsigned int*)(0x424E0584UL)) -#define bFM3_ADC0_ADSS0_TS2 *((volatile unsigned int*)(0x424E0588UL)) -#define bFM3_ADC0_ADSS0_TS3 *((volatile unsigned int*)(0x424E058CUL)) -#define bFM3_ADC0_ADSS0_TS4 *((volatile unsigned int*)(0x424E0590UL)) -#define bFM3_ADC0_ADSS0_TS5 *((volatile unsigned int*)(0x424E0594UL)) -#define bFM3_ADC0_ADSS0_TS6 *((volatile unsigned int*)(0x424E0598UL)) -#define bFM3_ADC0_ADSS0_TS7 *((volatile unsigned int*)(0x424E059CUL)) -#define bFM3_ADC0_ADSS1_TS8 *((volatile unsigned int*)(0x424E05A0UL)) -#define bFM3_ADC0_ADSS1_TS9 *((volatile unsigned int*)(0x424E05A4UL)) -#define bFM3_ADC0_ADSS1_TS10 *((volatile unsigned int*)(0x424E05A8UL)) -#define bFM3_ADC0_ADSS1_TS11 *((volatile unsigned int*)(0x424E05ACUL)) -#define bFM3_ADC0_ADSS1_TS12 *((volatile unsigned int*)(0x424E05B0UL)) -#define bFM3_ADC0_ADSS1_TS13 *((volatile unsigned int*)(0x424E05B4UL)) -#define bFM3_ADC0_ADSS1_TS14 *((volatile unsigned int*)(0x424E05B8UL)) -#define bFM3_ADC0_ADSS1_TS15 *((volatile unsigned int*)(0x424E05BCUL)) -#define bFM3_ADC0_ADST01_ST10 *((volatile unsigned int*)(0x424E0600UL)) -#define bFM3_ADC0_ADST01_ST11 *((volatile unsigned int*)(0x424E0604UL)) -#define bFM3_ADC0_ADST01_ST12 *((volatile unsigned int*)(0x424E0608UL)) -#define bFM3_ADC0_ADST01_ST13 *((volatile unsigned int*)(0x424E060CUL)) -#define bFM3_ADC0_ADST01_ST14 *((volatile unsigned int*)(0x424E0610UL)) -#define bFM3_ADC0_ADST01_STX10 *((volatile unsigned int*)(0x424E0614UL)) -#define bFM3_ADC0_ADST01_STX11 *((volatile unsigned int*)(0x424E0618UL)) -#define bFM3_ADC0_ADST01_STX12 *((volatile unsigned int*)(0x424E061CUL)) -#define bFM3_ADC0_ADST01_ST00 *((volatile unsigned int*)(0x424E0620UL)) -#define bFM3_ADC0_ADST01_ST01 *((volatile unsigned int*)(0x424E0624UL)) -#define bFM3_ADC0_ADST01_ST02 *((volatile unsigned int*)(0x424E0628UL)) -#define bFM3_ADC0_ADST01_ST03 *((volatile unsigned int*)(0x424E062CUL)) -#define bFM3_ADC0_ADST01_ST04 *((volatile unsigned int*)(0x424E0630UL)) -#define bFM3_ADC0_ADST01_STX00 *((volatile unsigned int*)(0x424E0634UL)) -#define bFM3_ADC0_ADST01_STX01 *((volatile unsigned int*)(0x424E0638UL)) -#define bFM3_ADC0_ADST01_STX02 *((volatile unsigned int*)(0x424E063CUL)) -#define bFM3_ADC0_ADST1_ST10 *((volatile unsigned int*)(0x424E0600UL)) -#define bFM3_ADC0_ADST1_ST11 *((volatile unsigned int*)(0x424E0604UL)) -#define bFM3_ADC0_ADST1_ST12 *((volatile unsigned int*)(0x424E0608UL)) -#define bFM3_ADC0_ADST1_ST13 *((volatile unsigned int*)(0x424E060CUL)) -#define bFM3_ADC0_ADST1_ST14 *((volatile unsigned int*)(0x424E0610UL)) -#define bFM3_ADC0_ADST1_STX10 *((volatile unsigned int*)(0x424E0614UL)) -#define bFM3_ADC0_ADST1_STX11 *((volatile unsigned int*)(0x424E0618UL)) -#define bFM3_ADC0_ADST1_STX12 *((volatile unsigned int*)(0x424E061CUL)) -#define bFM3_ADC0_ADST0_ST00 *((volatile unsigned int*)(0x424E0620UL)) -#define bFM3_ADC0_ADST0_ST01 *((volatile unsigned int*)(0x424E0624UL)) -#define bFM3_ADC0_ADST0_ST02 *((volatile unsigned int*)(0x424E0628UL)) -#define bFM3_ADC0_ADST0_ST03 *((volatile unsigned int*)(0x424E062CUL)) -#define bFM3_ADC0_ADST0_ST04 *((volatile unsigned int*)(0x424E0630UL)) -#define bFM3_ADC0_ADST0_STX00 *((volatile unsigned int*)(0x424E0634UL)) -#define bFM3_ADC0_ADST0_STX01 *((volatile unsigned int*)(0x424E0638UL)) -#define bFM3_ADC0_ADST0_STX02 *((volatile unsigned int*)(0x424E063CUL)) -#define bFM3_ADC0_ADCT_CT0 *((volatile unsigned int*)(0x424E0680UL)) -#define bFM3_ADC0_ADCT_CT1 *((volatile unsigned int*)(0x424E0684UL)) -#define bFM3_ADC0_ADCT_CT2 *((volatile unsigned int*)(0x424E0688UL)) -#define bFM3_ADC0_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E0700UL)) -#define bFM3_ADC0_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E0704UL)) -#define bFM3_ADC0_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E0708UL)) -#define bFM3_ADC0_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E070CUL)) -#define bFM3_ADC0_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E0720UL)) -#define bFM3_ADC0_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E0724UL)) -#define bFM3_ADC0_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E0728UL)) -#define bFM3_ADC0_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E072CUL)) -#define bFM3_ADC0_ADCEN_ENBL *((volatile unsigned int*)(0x424E0780UL)) -#define bFM3_ADC0_ADCEN_READY *((volatile unsigned int*)(0x424E0784UL)) - -/* 12-bit ADC unit 1 registers */ -#define bFM3_ADC1_ADSR_SCS *((volatile unsigned int*)(0x424E2000UL)) -#define bFM3_ADC1_ADSR_PCS *((volatile unsigned int*)(0x424E2004UL)) -#define bFM3_ADC1_ADSR_PCNS *((volatile unsigned int*)(0x424E2008UL)) -#define bFM3_ADC1_ADSR_FDAS *((volatile unsigned int*)(0x424E2018UL)) -#define bFM3_ADC1_ADSR_ADSTP *((volatile unsigned int*)(0x424E201CUL)) -#define bFM3_ADC1_ADCR_OVRIE *((volatile unsigned int*)(0x424E2020UL)) -#define bFM3_ADC1_ADCR_CMPIE *((volatile unsigned int*)(0x424E2024UL)) -#define bFM3_ADC1_ADCR_PCIE *((volatile unsigned int*)(0x424E2028UL)) -#define bFM3_ADC1_ADCR_SCIE *((volatile unsigned int*)(0x424E202CUL)) -#define bFM3_ADC1_ADCR_CMPIF *((volatile unsigned int*)(0x424E2034UL)) -#define bFM3_ADC1_ADCR_PCIF *((volatile unsigned int*)(0x424E2038UL)) -#define bFM3_ADC1_ADCR_SCIF *((volatile unsigned int*)(0x424E203CUL)) -#define bFM3_ADC1_SFNS_SFS0 *((volatile unsigned int*)(0x424E2100UL)) -#define bFM3_ADC1_SFNS_SFS1 *((volatile unsigned int*)(0x424E2104UL)) -#define bFM3_ADC1_SFNS_SFS2 *((volatile unsigned int*)(0x424E2108UL)) -#define bFM3_ADC1_SFNS_SFS3 *((volatile unsigned int*)(0x424E210CUL)) -#define bFM3_ADC1_SCCR_SSTR *((volatile unsigned int*)(0x424E2120UL)) -#define bFM3_ADC1_SCCR_SHEN *((volatile unsigned int*)(0x424E2124UL)) -#define bFM3_ADC1_SCCR_RPT *((volatile unsigned int*)(0x424E2128UL)) -#define bFM3_ADC1_SCCR_SFCLR *((volatile unsigned int*)(0x424E2130UL)) -#define bFM3_ADC1_SCCR_SOVR *((volatile unsigned int*)(0x424E2134UL)) -#define bFM3_ADC1_SCCR_SFUL *((volatile unsigned int*)(0x424E2138UL)) -#define bFM3_ADC1_SCCR_SEMP *((volatile unsigned int*)(0x424E213CUL)) -#define bFM3_ADC1_SCFD_SC0 *((volatile unsigned int*)(0x424E2180UL)) -#define bFM3_ADC1_SCFD_SC1 *((volatile unsigned int*)(0x424E2184UL)) -#define bFM3_ADC1_SCFD_SC2 *((volatile unsigned int*)(0x424E2188UL)) -#define bFM3_ADC1_SCFD_SC3 *((volatile unsigned int*)(0x424E218CUL)) -#define bFM3_ADC1_SCFD_SC4 *((volatile unsigned int*)(0x424E2190UL)) -#define bFM3_ADC1_SCFD_RS0 *((volatile unsigned int*)(0x424E21A0UL)) -#define bFM3_ADC1_SCFD_RS1 *((volatile unsigned int*)(0x424E21A4UL)) -#define bFM3_ADC1_SCFD_INVL *((volatile unsigned int*)(0x424E21B0UL)) -#define bFM3_ADC1_SCFD_SD0 *((volatile unsigned int*)(0x424E21D0UL)) -#define bFM3_ADC1_SCFD_SD1 *((volatile unsigned int*)(0x424E21D4UL)) -#define bFM3_ADC1_SCFD_SD2 *((volatile unsigned int*)(0x424E21D8UL)) -#define bFM3_ADC1_SCFD_SD3 *((volatile unsigned int*)(0x424E21DCUL)) -#define bFM3_ADC1_SCFD_SD4 *((volatile unsigned int*)(0x424E21E0UL)) -#define bFM3_ADC1_SCFD_SD5 *((volatile unsigned int*)(0x424E21E4UL)) -#define bFM3_ADC1_SCFD_SD6 *((volatile unsigned int*)(0x424E21E8UL)) -#define bFM3_ADC1_SCFD_SD7 *((volatile unsigned int*)(0x424E21ECUL)) -#define bFM3_ADC1_SCFD_SD8 *((volatile unsigned int*)(0x424E21F0UL)) -#define bFM3_ADC1_SCFD_SD9 *((volatile unsigned int*)(0x424E21F4UL)) -#define bFM3_ADC1_SCFD_SD10 *((volatile unsigned int*)(0x424E21F8UL)) -#define bFM3_ADC1_SCFD_SD11 *((volatile unsigned int*)(0x424E21FCUL)) -#define bFM3_ADC1_SCFDL_SC0 *((volatile unsigned int*)(0x424E2180UL)) -#define bFM3_ADC1_SCFDL_SC1 *((volatile unsigned int*)(0x424E2184UL)) -#define bFM3_ADC1_SCFDL_SC2 *((volatile unsigned int*)(0x424E2188UL)) -#define bFM3_ADC1_SCFDL_SC3 *((volatile unsigned int*)(0x424E218CUL)) -#define bFM3_ADC1_SCFDL_SC4 *((volatile unsigned int*)(0x424E2190UL)) -#define bFM3_ADC1_SCFDL_RS0 *((volatile unsigned int*)(0x424E21A0UL)) -#define bFM3_ADC1_SCFDL_RS1 *((volatile unsigned int*)(0x424E21A4UL)) -#define bFM3_ADC1_SCFDL_INVL *((volatile unsigned int*)(0x424E21B0UL)) -#define bFM3_ADC1_SCFDH_SD0 *((volatile unsigned int*)(0x424E21D0UL)) -#define bFM3_ADC1_SCFDH_SD1 *((volatile unsigned int*)(0x424E21D4UL)) -#define bFM3_ADC1_SCFDH_SD2 *((volatile unsigned int*)(0x424E21D8UL)) -#define bFM3_ADC1_SCFDH_SD3 *((volatile unsigned int*)(0x424E21DCUL)) -#define bFM3_ADC1_SCFDH_SD4 *((volatile unsigned int*)(0x424E21E0UL)) -#define bFM3_ADC1_SCFDH_SD5 *((volatile unsigned int*)(0x424E21E4UL)) -#define bFM3_ADC1_SCFDH_SD6 *((volatile unsigned int*)(0x424E21E8UL)) -#define bFM3_ADC1_SCFDH_SD7 *((volatile unsigned int*)(0x424E21ECUL)) -#define bFM3_ADC1_SCFDH_SD8 *((volatile unsigned int*)(0x424E21F0UL)) -#define bFM3_ADC1_SCFDH_SD9 *((volatile unsigned int*)(0x424E21F4UL)) -#define bFM3_ADC1_SCFDH_SD10 *((volatile unsigned int*)(0x424E21F8UL)) -#define bFM3_ADC1_SCFDH_SD11 *((volatile unsigned int*)(0x424E21FCUL)) -#define bFM3_ADC1_SCIS23_AN16 *((volatile unsigned int*)(0x424E2200UL)) -#define bFM3_ADC1_SCIS23_AN17 *((volatile unsigned int*)(0x424E2204UL)) -#define bFM3_ADC1_SCIS23_AN18 *((volatile unsigned int*)(0x424E2208UL)) -#define bFM3_ADC1_SCIS23_AN19 *((volatile unsigned int*)(0x424E220CUL)) -#define bFM3_ADC1_SCIS23_AN20 *((volatile unsigned int*)(0x424E2210UL)) -#define bFM3_ADC1_SCIS23_AN21 *((volatile unsigned int*)(0x424E2214UL)) -#define bFM3_ADC1_SCIS23_AN22 *((volatile unsigned int*)(0x424E2218UL)) -#define bFM3_ADC1_SCIS23_AN23 *((volatile unsigned int*)(0x424E221CUL)) -#define bFM3_ADC1_SCIS23_AN24 *((volatile unsigned int*)(0x424E2220UL)) -#define bFM3_ADC1_SCIS23_AN25 *((volatile unsigned int*)(0x424E2224UL)) -#define bFM3_ADC1_SCIS23_AN26 *((volatile unsigned int*)(0x424E2228UL)) -#define bFM3_ADC1_SCIS23_AN27 *((volatile unsigned int*)(0x424E222CUL)) -#define bFM3_ADC1_SCIS23_AN28 *((volatile unsigned int*)(0x424E2230UL)) -#define bFM3_ADC1_SCIS23_AN29 *((volatile unsigned int*)(0x424E2234UL)) -#define bFM3_ADC1_SCIS23_AN30 *((volatile unsigned int*)(0x424E2238UL)) -#define bFM3_ADC1_SCIS23_AN31 *((volatile unsigned int*)(0x424E223CUL)) -#define bFM3_ADC1_SCIS2_AN16 *((volatile unsigned int*)(0x424E2200UL)) -#define bFM3_ADC1_SCIS2_AN17 *((volatile unsigned int*)(0x424E2204UL)) -#define bFM3_ADC1_SCIS2_AN18 *((volatile unsigned int*)(0x424E2208UL)) -#define bFM3_ADC1_SCIS2_AN19 *((volatile unsigned int*)(0x424E220CUL)) -#define bFM3_ADC1_SCIS2_AN20 *((volatile unsigned int*)(0x424E2210UL)) -#define bFM3_ADC1_SCIS2_AN21 *((volatile unsigned int*)(0x424E2214UL)) -#define bFM3_ADC1_SCIS2_AN22 *((volatile unsigned int*)(0x424E2218UL)) -#define bFM3_ADC1_SCIS2_AN23 *((volatile unsigned int*)(0x424E221CUL)) -#define bFM3_ADC1_SCIS3_AN24 *((volatile unsigned int*)(0x424E2220UL)) -#define bFM3_ADC1_SCIS3_AN25 *((volatile unsigned int*)(0x424E2224UL)) -#define bFM3_ADC1_SCIS3_AN26 *((volatile unsigned int*)(0x424E2228UL)) -#define bFM3_ADC1_SCIS3_AN27 *((volatile unsigned int*)(0x424E222CUL)) -#define bFM3_ADC1_SCIS3_AN28 *((volatile unsigned int*)(0x424E2230UL)) -#define bFM3_ADC1_SCIS3_AN29 *((volatile unsigned int*)(0x424E2234UL)) -#define bFM3_ADC1_SCIS3_AN30 *((volatile unsigned int*)(0x424E2238UL)) -#define bFM3_ADC1_SCIS3_AN31 *((volatile unsigned int*)(0x424E223CUL)) -#define bFM3_ADC1_SCIS01_AN0 *((volatile unsigned int*)(0x424E2280UL)) -#define bFM3_ADC1_SCIS01_AN1 *((volatile unsigned int*)(0x424E2284UL)) -#define bFM3_ADC1_SCIS01_AN2 *((volatile unsigned int*)(0x424E2288UL)) -#define bFM3_ADC1_SCIS01_AN3 *((volatile unsigned int*)(0x424E228CUL)) -#define bFM3_ADC1_SCIS01_AN4 *((volatile unsigned int*)(0x424E2290UL)) -#define bFM3_ADC1_SCIS01_AN5 *((volatile unsigned int*)(0x424E2294UL)) -#define bFM3_ADC1_SCIS01_AN6 *((volatile unsigned int*)(0x424E2298UL)) -#define bFM3_ADC1_SCIS01_AN7 *((volatile unsigned int*)(0x424E229CUL)) -#define bFM3_ADC1_SCIS01_AN8 *((volatile unsigned int*)(0x424E22A0UL)) -#define bFM3_ADC1_SCIS01_AN9 *((volatile unsigned int*)(0x424E22A4UL)) -#define bFM3_ADC1_SCIS01_AN10 *((volatile unsigned int*)(0x424E22A8UL)) -#define bFM3_ADC1_SCIS01_AN11 *((volatile unsigned int*)(0x424E22ACUL)) -#define bFM3_ADC1_SCIS01_AN12 *((volatile unsigned int*)(0x424E22B0UL)) -#define bFM3_ADC1_SCIS01_AN13 *((volatile unsigned int*)(0x424E22B4UL)) -#define bFM3_ADC1_SCIS01_AN14 *((volatile unsigned int*)(0x424E22B8UL)) -#define bFM3_ADC1_SCIS01_AN15 *((volatile unsigned int*)(0x424E22BCUL)) -#define bFM3_ADC1_SCIS0_AN0 *((volatile unsigned int*)(0x424E2280UL)) -#define bFM3_ADC1_SCIS0_AN1 *((volatile unsigned int*)(0x424E2284UL)) -#define bFM3_ADC1_SCIS0_AN2 *((volatile unsigned int*)(0x424E2288UL)) -#define bFM3_ADC1_SCIS0_AN3 *((volatile unsigned int*)(0x424E228CUL)) -#define bFM3_ADC1_SCIS0_AN4 *((volatile unsigned int*)(0x424E2290UL)) -#define bFM3_ADC1_SCIS0_AN5 *((volatile unsigned int*)(0x424E2294UL)) -#define bFM3_ADC1_SCIS0_AN6 *((volatile unsigned int*)(0x424E2298UL)) -#define bFM3_ADC1_SCIS0_AN7 *((volatile unsigned int*)(0x424E229CUL)) -#define bFM3_ADC1_SCIS1_AN8 *((volatile unsigned int*)(0x424E22A0UL)) -#define bFM3_ADC1_SCIS1_AN9 *((volatile unsigned int*)(0x424E22A4UL)) -#define bFM3_ADC1_SCIS1_AN10 *((volatile unsigned int*)(0x424E22A8UL)) -#define bFM3_ADC1_SCIS1_AN11 *((volatile unsigned int*)(0x424E22ACUL)) -#define bFM3_ADC1_SCIS1_AN12 *((volatile unsigned int*)(0x424E22B0UL)) -#define bFM3_ADC1_SCIS1_AN13 *((volatile unsigned int*)(0x424E22B4UL)) -#define bFM3_ADC1_SCIS1_AN14 *((volatile unsigned int*)(0x424E22B8UL)) -#define bFM3_ADC1_SCIS1_AN15 *((volatile unsigned int*)(0x424E22BCUL)) -#define bFM3_ADC1_PFNS_PFS0 *((volatile unsigned int*)(0x424E2300UL)) -#define bFM3_ADC1_PFNS_PFS1 *((volatile unsigned int*)(0x424E2304UL)) -#define bFM3_ADC1_PFNS_TEST0 *((volatile unsigned int*)(0x424E2310UL)) -#define bFM3_ADC1_PFNS_TEST1 *((volatile unsigned int*)(0x424E2314UL)) -#define bFM3_ADC1_PCCR_PSTR *((volatile unsigned int*)(0x424E2320UL)) -#define bFM3_ADC1_PCCR_PHEN *((volatile unsigned int*)(0x424E2324UL)) -#define bFM3_ADC1_PCCR_PEEN *((volatile unsigned int*)(0x424E2328UL)) -#define bFM3_ADC1_PCCR_ESCE *((volatile unsigned int*)(0x424E232CUL)) -#define bFM3_ADC1_PCCR_PFCLR *((volatile unsigned int*)(0x424E2330UL)) -#define bFM3_ADC1_PCCR_POVR *((volatile unsigned int*)(0x424E2334UL)) -#define bFM3_ADC1_PCCR_PFUL *((volatile unsigned int*)(0x424E2338UL)) -#define bFM3_ADC1_PCCR_PEMP *((volatile unsigned int*)(0x424E233CUL)) -#define bFM3_ADC1_PCFD_PC0 *((volatile unsigned int*)(0x424E2380UL)) -#define bFM3_ADC1_PCFD_PC1 *((volatile unsigned int*)(0x424E2384UL)) -#define bFM3_ADC1_PCFD_PC2 *((volatile unsigned int*)(0x424E2388UL)) -#define bFM3_ADC1_PCFD_PC3 *((volatile unsigned int*)(0x424E238CUL)) -#define bFM3_ADC1_PCFD_PC4 *((volatile unsigned int*)(0x424E2390UL)) -#define bFM3_ADC1_PCFD_RS0 *((volatile unsigned int*)(0x424E23A0UL)) -#define bFM3_ADC1_PCFD_RS1 *((volatile unsigned int*)(0x424E23A4UL)) -#define bFM3_ADC1_PCFD_RS2 *((volatile unsigned int*)(0x424E23A8UL)) -#define bFM3_ADC1_PCFD_INVL *((volatile unsigned int*)(0x424E23B0UL)) -#define bFM3_ADC1_PCFD_PD0 *((volatile unsigned int*)(0x424E23D0UL)) -#define bFM3_ADC1_PCFD_PD1 *((volatile unsigned int*)(0x424E23D4UL)) -#define bFM3_ADC1_PCFD_PD2 *((volatile unsigned int*)(0x424E23D8UL)) -#define bFM3_ADC1_PCFD_PD3 *((volatile unsigned int*)(0x424E23DCUL)) -#define bFM3_ADC1_PCFD_PD4 *((volatile unsigned int*)(0x424E23E0UL)) -#define bFM3_ADC1_PCFD_PD5 *((volatile unsigned int*)(0x424E23E4UL)) -#define bFM3_ADC1_PCFD_PD6 *((volatile unsigned int*)(0x424E23E8UL)) -#define bFM3_ADC1_PCFD_PD7 *((volatile unsigned int*)(0x424E23ECUL)) -#define bFM3_ADC1_PCFD_PD8 *((volatile unsigned int*)(0x424E23F0UL)) -#define bFM3_ADC1_PCFD_PD9 *((volatile unsigned int*)(0x424E23F4UL)) -#define bFM3_ADC1_PCFD_PD10 *((volatile unsigned int*)(0x424E23F8UL)) -#define bFM3_ADC1_PCFD_PD11 *((volatile unsigned int*)(0x424E23FCUL)) -#define bFM3_ADC1_PCFDL_PC0 *((volatile unsigned int*)(0x424E2380UL)) -#define bFM3_ADC1_PCFDL_PC1 *((volatile unsigned int*)(0x424E2384UL)) -#define bFM3_ADC1_PCFDL_PC2 *((volatile unsigned int*)(0x424E2388UL)) -#define bFM3_ADC1_PCFDL_PC3 *((volatile unsigned int*)(0x424E238CUL)) -#define bFM3_ADC1_PCFDL_PC4 *((volatile unsigned int*)(0x424E2390UL)) -#define bFM3_ADC1_PCFDL_RS0 *((volatile unsigned int*)(0x424E23A0UL)) -#define bFM3_ADC1_PCFDL_RS1 *((volatile unsigned int*)(0x424E23A4UL)) -#define bFM3_ADC1_PCFDL_RS2 *((volatile unsigned int*)(0x424E23A8UL)) -#define bFM3_ADC1_PCFDL_INVL *((volatile unsigned int*)(0x424E23B0UL)) -#define bFM3_ADC1_PCFDH_PD0 *((volatile unsigned int*)(0x424E23D0UL)) -#define bFM3_ADC1_PCFDH_PD1 *((volatile unsigned int*)(0x424E23D4UL)) -#define bFM3_ADC1_PCFDH_PD2 *((volatile unsigned int*)(0x424E23D8UL)) -#define bFM3_ADC1_PCFDH_PD3 *((volatile unsigned int*)(0x424E23DCUL)) -#define bFM3_ADC1_PCFDH_PD4 *((volatile unsigned int*)(0x424E23E0UL)) -#define bFM3_ADC1_PCFDH_PD5 *((volatile unsigned int*)(0x424E23E4UL)) -#define bFM3_ADC1_PCFDH_PD6 *((volatile unsigned int*)(0x424E23E8UL)) -#define bFM3_ADC1_PCFDH_PD7 *((volatile unsigned int*)(0x424E23ECUL)) -#define bFM3_ADC1_PCFDH_PD8 *((volatile unsigned int*)(0x424E23F0UL)) -#define bFM3_ADC1_PCFDH_PD9 *((volatile unsigned int*)(0x424E23F4UL)) -#define bFM3_ADC1_PCFDH_PD10 *((volatile unsigned int*)(0x424E23F8UL)) -#define bFM3_ADC1_PCFDH_PD11 *((volatile unsigned int*)(0x424E23FCUL)) -#define bFM3_ADC1_PCIS_P1A0 *((volatile unsigned int*)(0x424E2400UL)) -#define bFM3_ADC1_PCIS_P1A1 *((volatile unsigned int*)(0x424E2404UL)) -#define bFM3_ADC1_PCIS_P1A2 *((volatile unsigned int*)(0x424E2408UL)) -#define bFM3_ADC1_PCIS_P2A0 *((volatile unsigned int*)(0x424E240CUL)) -#define bFM3_ADC1_PCIS_P2A1 *((volatile unsigned int*)(0x424E2410UL)) -#define bFM3_ADC1_PCIS_P2A2 *((volatile unsigned int*)(0x424E2414UL)) -#define bFM3_ADC1_PCIS_P2A3 *((volatile unsigned int*)(0x424E2418UL)) -#define bFM3_ADC1_PCIS_P2A4 *((volatile unsigned int*)(0x424E241CUL)) -#define bFM3_ADC1_CMPCR_CCH0 *((volatile unsigned int*)(0x424E2480UL)) -#define bFM3_ADC1_CMPCR_CCH1 *((volatile unsigned int*)(0x424E2484UL)) -#define bFM3_ADC1_CMPCR_CCH2 *((volatile unsigned int*)(0x424E2488UL)) -#define bFM3_ADC1_CMPCR_CCH3 *((volatile unsigned int*)(0x424E248CUL)) -#define bFM3_ADC1_CMPCR_CCH4 *((volatile unsigned int*)(0x424E2490UL)) -#define bFM3_ADC1_CMPCR_CMD0 *((volatile unsigned int*)(0x424E2494UL)) -#define bFM3_ADC1_CMPCR_CMD1 *((volatile unsigned int*)(0x424E2498UL)) -#define bFM3_ADC1_CMPCR_CMPEN *((volatile unsigned int*)(0x424E249CUL)) -#define bFM3_ADC1_CMPD_CMAD2 *((volatile unsigned int*)(0x424E24D8UL)) -#define bFM3_ADC1_CMPD_CMAD3 *((volatile unsigned int*)(0x424E24DCUL)) -#define bFM3_ADC1_CMPD_CMAD4 *((volatile unsigned int*)(0x424E24E0UL)) -#define bFM3_ADC1_CMPD_CMAD5 *((volatile unsigned int*)(0x424E24E4UL)) -#define bFM3_ADC1_CMPD_CMAD6 *((volatile unsigned int*)(0x424E24E8UL)) -#define bFM3_ADC1_CMPD_CMAD7 *((volatile unsigned int*)(0x424E24ECUL)) -#define bFM3_ADC1_CMPD_CMAD8 *((volatile unsigned int*)(0x424E24F0UL)) -#define bFM3_ADC1_CMPD_CMAD9 *((volatile unsigned int*)(0x424E24F4UL)) -#define bFM3_ADC1_CMPD_CMAD10 *((volatile unsigned int*)(0x424E24F8UL)) -#define bFM3_ADC1_CMPD_CMAD11 *((volatile unsigned int*)(0x424E24FCUL)) -#define bFM3_ADC1_ADSS23_TS16 *((volatile unsigned int*)(0x424E2500UL)) -#define bFM3_ADC1_ADSS23_TS17 *((volatile unsigned int*)(0x424E2504UL)) -#define bFM3_ADC1_ADSS23_TS18 *((volatile unsigned int*)(0x424E2508UL)) -#define bFM3_ADC1_ADSS23_TS19 *((volatile unsigned int*)(0x424E250CUL)) -#define bFM3_ADC1_ADSS23_TS20 *((volatile unsigned int*)(0x424E2510UL)) -#define bFM3_ADC1_ADSS23_TS21 *((volatile unsigned int*)(0x424E2514UL)) -#define bFM3_ADC1_ADSS23_TS22 *((volatile unsigned int*)(0x424E2518UL)) -#define bFM3_ADC1_ADSS23_TS23 *((volatile unsigned int*)(0x424E251CUL)) -#define bFM3_ADC1_ADSS23_TS24 *((volatile unsigned int*)(0x424E2520UL)) -#define bFM3_ADC1_ADSS23_TS25 *((volatile unsigned int*)(0x424E2524UL)) -#define bFM3_ADC1_ADSS23_TS26 *((volatile unsigned int*)(0x424E2528UL)) -#define bFM3_ADC1_ADSS23_TS27 *((volatile unsigned int*)(0x424E252CUL)) -#define bFM3_ADC1_ADSS23_TS28 *((volatile unsigned int*)(0x424E2530UL)) -#define bFM3_ADC1_ADSS23_TS29 *((volatile unsigned int*)(0x424E2534UL)) -#define bFM3_ADC1_ADSS23_TS30 *((volatile unsigned int*)(0x424E2538UL)) -#define bFM3_ADC1_ADSS23_TS31 *((volatile unsigned int*)(0x424E253CUL)) -#define bFM3_ADC1_ADSS2_TS16 *((volatile unsigned int*)(0x424E2500UL)) -#define bFM3_ADC1_ADSS2_TS17 *((volatile unsigned int*)(0x424E2504UL)) -#define bFM3_ADC1_ADSS2_TS18 *((volatile unsigned int*)(0x424E2508UL)) -#define bFM3_ADC1_ADSS2_TS19 *((volatile unsigned int*)(0x424E250CUL)) -#define bFM3_ADC1_ADSS2_TS20 *((volatile unsigned int*)(0x424E2510UL)) -#define bFM3_ADC1_ADSS2_TS21 *((volatile unsigned int*)(0x424E2514UL)) -#define bFM3_ADC1_ADSS2_TS22 *((volatile unsigned int*)(0x424E2518UL)) -#define bFM3_ADC1_ADSS2_TS23 *((volatile unsigned int*)(0x424E251CUL)) -#define bFM3_ADC1_ADSS3_TS24 *((volatile unsigned int*)(0x424E2520UL)) -#define bFM3_ADC1_ADSS3_TS25 *((volatile unsigned int*)(0x424E2524UL)) -#define bFM3_ADC1_ADSS3_TS26 *((volatile unsigned int*)(0x424E2528UL)) -#define bFM3_ADC1_ADSS3_TS27 *((volatile unsigned int*)(0x424E252CUL)) -#define bFM3_ADC1_ADSS3_TS28 *((volatile unsigned int*)(0x424E2530UL)) -#define bFM3_ADC1_ADSS3_TS29 *((volatile unsigned int*)(0x424E2534UL)) -#define bFM3_ADC1_ADSS3_TS30 *((volatile unsigned int*)(0x424E2538UL)) -#define bFM3_ADC1_ADSS3_TS31 *((volatile unsigned int*)(0x424E253CUL)) -#define bFM3_ADC1_ADSS01_TS0 *((volatile unsigned int*)(0x424E2580UL)) -#define bFM3_ADC1_ADSS01_TS1 *((volatile unsigned int*)(0x424E2584UL)) -#define bFM3_ADC1_ADSS01_TS2 *((volatile unsigned int*)(0x424E2588UL)) -#define bFM3_ADC1_ADSS01_TS3 *((volatile unsigned int*)(0x424E258CUL)) -#define bFM3_ADC1_ADSS01_TS4 *((volatile unsigned int*)(0x424E2590UL)) -#define bFM3_ADC1_ADSS01_TS5 *((volatile unsigned int*)(0x424E2594UL)) -#define bFM3_ADC1_ADSS01_TS6 *((volatile unsigned int*)(0x424E2598UL)) -#define bFM3_ADC1_ADSS01_TS7 *((volatile unsigned int*)(0x424E259CUL)) -#define bFM3_ADC1_ADSS01_TS8 *((volatile unsigned int*)(0x424E25A0UL)) -#define bFM3_ADC1_ADSS01_TS9 *((volatile unsigned int*)(0x424E25A4UL)) -#define bFM3_ADC1_ADSS01_TS10 *((volatile unsigned int*)(0x424E25A8UL)) -#define bFM3_ADC1_ADSS01_TS11 *((volatile unsigned int*)(0x424E25ACUL)) -#define bFM3_ADC1_ADSS01_TS12 *((volatile unsigned int*)(0x424E25B0UL)) -#define bFM3_ADC1_ADSS01_TS13 *((volatile unsigned int*)(0x424E25B4UL)) -#define bFM3_ADC1_ADSS01_TS14 *((volatile unsigned int*)(0x424E25B8UL)) -#define bFM3_ADC1_ADSS01_TS15 *((volatile unsigned int*)(0x424E25BCUL)) -#define bFM3_ADC1_ADSS0_TS0 *((volatile unsigned int*)(0x424E2580UL)) -#define bFM3_ADC1_ADSS0_TS1 *((volatile unsigned int*)(0x424E2584UL)) -#define bFM3_ADC1_ADSS0_TS2 *((volatile unsigned int*)(0x424E2588UL)) -#define bFM3_ADC1_ADSS0_TS3 *((volatile unsigned int*)(0x424E258CUL)) -#define bFM3_ADC1_ADSS0_TS4 *((volatile unsigned int*)(0x424E2590UL)) -#define bFM3_ADC1_ADSS0_TS5 *((volatile unsigned int*)(0x424E2594UL)) -#define bFM3_ADC1_ADSS0_TS6 *((volatile unsigned int*)(0x424E2598UL)) -#define bFM3_ADC1_ADSS0_TS7 *((volatile unsigned int*)(0x424E259CUL)) -#define bFM3_ADC1_ADSS1_TS8 *((volatile unsigned int*)(0x424E25A0UL)) -#define bFM3_ADC1_ADSS1_TS9 *((volatile unsigned int*)(0x424E25A4UL)) -#define bFM3_ADC1_ADSS1_TS10 *((volatile unsigned int*)(0x424E25A8UL)) -#define bFM3_ADC1_ADSS1_TS11 *((volatile unsigned int*)(0x424E25ACUL)) -#define bFM3_ADC1_ADSS1_TS12 *((volatile unsigned int*)(0x424E25B0UL)) -#define bFM3_ADC1_ADSS1_TS13 *((volatile unsigned int*)(0x424E25B4UL)) -#define bFM3_ADC1_ADSS1_TS14 *((volatile unsigned int*)(0x424E25B8UL)) -#define bFM3_ADC1_ADSS1_TS15 *((volatile unsigned int*)(0x424E25BCUL)) -#define bFM3_ADC1_ADST01_ST10 *((volatile unsigned int*)(0x424E2600UL)) -#define bFM3_ADC1_ADST01_ST11 *((volatile unsigned int*)(0x424E2604UL)) -#define bFM3_ADC1_ADST01_ST12 *((volatile unsigned int*)(0x424E2608UL)) -#define bFM3_ADC1_ADST01_ST13 *((volatile unsigned int*)(0x424E260CUL)) -#define bFM3_ADC1_ADST01_ST14 *((volatile unsigned int*)(0x424E2610UL)) -#define bFM3_ADC1_ADST01_STX10 *((volatile unsigned int*)(0x424E2614UL)) -#define bFM3_ADC1_ADST01_STX11 *((volatile unsigned int*)(0x424E2618UL)) -#define bFM3_ADC1_ADST01_STX12 *((volatile unsigned int*)(0x424E261CUL)) -#define bFM3_ADC1_ADST01_ST00 *((volatile unsigned int*)(0x424E2620UL)) -#define bFM3_ADC1_ADST01_ST01 *((volatile unsigned int*)(0x424E2624UL)) -#define bFM3_ADC1_ADST01_ST02 *((volatile unsigned int*)(0x424E2628UL)) -#define bFM3_ADC1_ADST01_ST03 *((volatile unsigned int*)(0x424E262CUL)) -#define bFM3_ADC1_ADST01_ST04 *((volatile unsigned int*)(0x424E2630UL)) -#define bFM3_ADC1_ADST01_STX00 *((volatile unsigned int*)(0x424E2634UL)) -#define bFM3_ADC1_ADST01_STX01 *((volatile unsigned int*)(0x424E2638UL)) -#define bFM3_ADC1_ADST01_STX02 *((volatile unsigned int*)(0x424E263CUL)) -#define bFM3_ADC1_ADST1_ST10 *((volatile unsigned int*)(0x424E2600UL)) -#define bFM3_ADC1_ADST1_ST11 *((volatile unsigned int*)(0x424E2604UL)) -#define bFM3_ADC1_ADST1_ST12 *((volatile unsigned int*)(0x424E2608UL)) -#define bFM3_ADC1_ADST1_ST13 *((volatile unsigned int*)(0x424E260CUL)) -#define bFM3_ADC1_ADST1_ST14 *((volatile unsigned int*)(0x424E2610UL)) -#define bFM3_ADC1_ADST1_STX10 *((volatile unsigned int*)(0x424E2614UL)) -#define bFM3_ADC1_ADST1_STX11 *((volatile unsigned int*)(0x424E2618UL)) -#define bFM3_ADC1_ADST1_STX12 *((volatile unsigned int*)(0x424E261CUL)) -#define bFM3_ADC1_ADST0_ST00 *((volatile unsigned int*)(0x424E2620UL)) -#define bFM3_ADC1_ADST0_ST01 *((volatile unsigned int*)(0x424E2624UL)) -#define bFM3_ADC1_ADST0_ST02 *((volatile unsigned int*)(0x424E2628UL)) -#define bFM3_ADC1_ADST0_ST03 *((volatile unsigned int*)(0x424E262CUL)) -#define bFM3_ADC1_ADST0_ST04 *((volatile unsigned int*)(0x424E2630UL)) -#define bFM3_ADC1_ADST0_STX00 *((volatile unsigned int*)(0x424E2634UL)) -#define bFM3_ADC1_ADST0_STX01 *((volatile unsigned int*)(0x424E2638UL)) -#define bFM3_ADC1_ADST0_STX02 *((volatile unsigned int*)(0x424E263CUL)) -#define bFM3_ADC1_ADCT_CT0 *((volatile unsigned int*)(0x424E2680UL)) -#define bFM3_ADC1_ADCT_CT1 *((volatile unsigned int*)(0x424E2684UL)) -#define bFM3_ADC1_ADCT_CT2 *((volatile unsigned int*)(0x424E2688UL)) -#define bFM3_ADC1_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E2700UL)) -#define bFM3_ADC1_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E2704UL)) -#define bFM3_ADC1_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E2708UL)) -#define bFM3_ADC1_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E270CUL)) -#define bFM3_ADC1_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E2720UL)) -#define bFM3_ADC1_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E2724UL)) -#define bFM3_ADC1_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E2728UL)) -#define bFM3_ADC1_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E272CUL)) -#define bFM3_ADC1_ADCEN_ENBL *((volatile unsigned int*)(0x424E2780UL)) -#define bFM3_ADC1_ADCEN_READY *((volatile unsigned int*)(0x424E2784UL)) - -/* 12-bit ADC unit 2 registers */ -#define bFM3_ADC2_ADSR_SCS *((volatile unsigned int*)(0x424E4000UL)) -#define bFM3_ADC2_ADSR_PCS *((volatile unsigned int*)(0x424E4004UL)) -#define bFM3_ADC2_ADSR_PCNS *((volatile unsigned int*)(0x424E4008UL)) -#define bFM3_ADC2_ADSR_FDAS *((volatile unsigned int*)(0x424E4018UL)) -#define bFM3_ADC2_ADSR_ADSTP *((volatile unsigned int*)(0x424E401CUL)) -#define bFM3_ADC2_ADCR_OVRIE *((volatile unsigned int*)(0x424E4020UL)) -#define bFM3_ADC2_ADCR_CMPIE *((volatile unsigned int*)(0x424E4024UL)) -#define bFM3_ADC2_ADCR_PCIE *((volatile unsigned int*)(0x424E4028UL)) -#define bFM3_ADC2_ADCR_SCIE *((volatile unsigned int*)(0x424E402CUL)) -#define bFM3_ADC2_ADCR_CMPIF *((volatile unsigned int*)(0x424E4034UL)) -#define bFM3_ADC2_ADCR_PCIF *((volatile unsigned int*)(0x424E4038UL)) -#define bFM3_ADC2_ADCR_SCIF *((volatile unsigned int*)(0x424E403CUL)) -#define bFM3_ADC2_SFNS_SFS0 *((volatile unsigned int*)(0x424E4100UL)) -#define bFM3_ADC2_SFNS_SFS1 *((volatile unsigned int*)(0x424E4104UL)) -#define bFM3_ADC2_SFNS_SFS2 *((volatile unsigned int*)(0x424E4108UL)) -#define bFM3_ADC2_SFNS_SFS3 *((volatile unsigned int*)(0x424E410CUL)) -#define bFM3_ADC2_SCCR_SSTR *((volatile unsigned int*)(0x424E4120UL)) -#define bFM3_ADC2_SCCR_SHEN *((volatile unsigned int*)(0x424E4124UL)) -#define bFM3_ADC2_SCCR_RPT *((volatile unsigned int*)(0x424E4128UL)) -#define bFM3_ADC2_SCCR_SFCLR *((volatile unsigned int*)(0x424E4130UL)) -#define bFM3_ADC2_SCCR_SOVR *((volatile unsigned int*)(0x424E4134UL)) -#define bFM3_ADC2_SCCR_SFUL *((volatile unsigned int*)(0x424E4138UL)) -#define bFM3_ADC2_SCCR_SEMP *((volatile unsigned int*)(0x424E413CUL)) -#define bFM3_ADC2_SCFD_SC0 *((volatile unsigned int*)(0x424E4180UL)) -#define bFM3_ADC2_SCFD_SC1 *((volatile unsigned int*)(0x424E4184UL)) -#define bFM3_ADC2_SCFD_SC2 *((volatile unsigned int*)(0x424E4188UL)) -#define bFM3_ADC2_SCFD_SC3 *((volatile unsigned int*)(0x424E418CUL)) -#define bFM3_ADC2_SCFD_SC4 *((volatile unsigned int*)(0x424E4190UL)) -#define bFM3_ADC2_SCFD_RS0 *((volatile unsigned int*)(0x424E41A0UL)) -#define bFM3_ADC2_SCFD_RS1 *((volatile unsigned int*)(0x424E41A4UL)) -#define bFM3_ADC2_SCFD_INVL *((volatile unsigned int*)(0x424E41B0UL)) -#define bFM3_ADC2_SCFD_SD0 *((volatile unsigned int*)(0x424E41D0UL)) -#define bFM3_ADC2_SCFD_SD1 *((volatile unsigned int*)(0x424E41D4UL)) -#define bFM3_ADC2_SCFD_SD2 *((volatile unsigned int*)(0x424E41D8UL)) -#define bFM3_ADC2_SCFD_SD3 *((volatile unsigned int*)(0x424E41DCUL)) -#define bFM3_ADC2_SCFD_SD4 *((volatile unsigned int*)(0x424E41E0UL)) -#define bFM3_ADC2_SCFD_SD5 *((volatile unsigned int*)(0x424E41E4UL)) -#define bFM3_ADC2_SCFD_SD6 *((volatile unsigned int*)(0x424E41E8UL)) -#define bFM3_ADC2_SCFD_SD7 *((volatile unsigned int*)(0x424E41ECUL)) -#define bFM3_ADC2_SCFD_SD8 *((volatile unsigned int*)(0x424E41F0UL)) -#define bFM3_ADC2_SCFD_SD9 *((volatile unsigned int*)(0x424E41F4UL)) -#define bFM3_ADC2_SCFD_SD10 *((volatile unsigned int*)(0x424E41F8UL)) -#define bFM3_ADC2_SCFD_SD11 *((volatile unsigned int*)(0x424E41FCUL)) -#define bFM3_ADC2_SCFDL_SC0 *((volatile unsigned int*)(0x424E4180UL)) -#define bFM3_ADC2_SCFDL_SC1 *((volatile unsigned int*)(0x424E4184UL)) -#define bFM3_ADC2_SCFDL_SC2 *((volatile unsigned int*)(0x424E4188UL)) -#define bFM3_ADC2_SCFDL_SC3 *((volatile unsigned int*)(0x424E418CUL)) -#define bFM3_ADC2_SCFDL_SC4 *((volatile unsigned int*)(0x424E4190UL)) -#define bFM3_ADC2_SCFDL_RS0 *((volatile unsigned int*)(0x424E41A0UL)) -#define bFM3_ADC2_SCFDL_RS1 *((volatile unsigned int*)(0x424E41A4UL)) -#define bFM3_ADC2_SCFDL_INVL *((volatile unsigned int*)(0x424E41B0UL)) -#define bFM3_ADC2_SCFDH_SD0 *((volatile unsigned int*)(0x424E41D0UL)) -#define bFM3_ADC2_SCFDH_SD1 *((volatile unsigned int*)(0x424E41D4UL)) -#define bFM3_ADC2_SCFDH_SD2 *((volatile unsigned int*)(0x424E41D8UL)) -#define bFM3_ADC2_SCFDH_SD3 *((volatile unsigned int*)(0x424E41DCUL)) -#define bFM3_ADC2_SCFDH_SD4 *((volatile unsigned int*)(0x424E41E0UL)) -#define bFM3_ADC2_SCFDH_SD5 *((volatile unsigned int*)(0x424E41E4UL)) -#define bFM3_ADC2_SCFDH_SD6 *((volatile unsigned int*)(0x424E41E8UL)) -#define bFM3_ADC2_SCFDH_SD7 *((volatile unsigned int*)(0x424E41ECUL)) -#define bFM3_ADC2_SCFDH_SD8 *((volatile unsigned int*)(0x424E41F0UL)) -#define bFM3_ADC2_SCFDH_SD9 *((volatile unsigned int*)(0x424E41F4UL)) -#define bFM3_ADC2_SCFDH_SD10 *((volatile unsigned int*)(0x424E41F8UL)) -#define bFM3_ADC2_SCFDH_SD11 *((volatile unsigned int*)(0x424E41FCUL)) -#define bFM3_ADC2_SCIS23_AN16 *((volatile unsigned int*)(0x424E4200UL)) -#define bFM3_ADC2_SCIS23_AN17 *((volatile unsigned int*)(0x424E4204UL)) -#define bFM3_ADC2_SCIS23_AN18 *((volatile unsigned int*)(0x424E4208UL)) -#define bFM3_ADC2_SCIS23_AN19 *((volatile unsigned int*)(0x424E420CUL)) -#define bFM3_ADC2_SCIS23_AN20 *((volatile unsigned int*)(0x424E4210UL)) -#define bFM3_ADC2_SCIS23_AN21 *((volatile unsigned int*)(0x424E4214UL)) -#define bFM3_ADC2_SCIS23_AN22 *((volatile unsigned int*)(0x424E4218UL)) -#define bFM3_ADC2_SCIS23_AN23 *((volatile unsigned int*)(0x424E421CUL)) -#define bFM3_ADC2_SCIS23_AN24 *((volatile unsigned int*)(0x424E4220UL)) -#define bFM3_ADC2_SCIS23_AN25 *((volatile unsigned int*)(0x424E4224UL)) -#define bFM3_ADC2_SCIS23_AN26 *((volatile unsigned int*)(0x424E4228UL)) -#define bFM3_ADC2_SCIS23_AN27 *((volatile unsigned int*)(0x424E422CUL)) -#define bFM3_ADC2_SCIS23_AN28 *((volatile unsigned int*)(0x424E4230UL)) -#define bFM3_ADC2_SCIS23_AN29 *((volatile unsigned int*)(0x424E4234UL)) -#define bFM3_ADC2_SCIS23_AN30 *((volatile unsigned int*)(0x424E4238UL)) -#define bFM3_ADC2_SCIS23_AN31 *((volatile unsigned int*)(0x424E423CUL)) -#define bFM3_ADC2_SCIS2_AN16 *((volatile unsigned int*)(0x424E4200UL)) -#define bFM3_ADC2_SCIS2_AN17 *((volatile unsigned int*)(0x424E4204UL)) -#define bFM3_ADC2_SCIS2_AN18 *((volatile unsigned int*)(0x424E4208UL)) -#define bFM3_ADC2_SCIS2_AN19 *((volatile unsigned int*)(0x424E420CUL)) -#define bFM3_ADC2_SCIS2_AN20 *((volatile unsigned int*)(0x424E4210UL)) -#define bFM3_ADC2_SCIS2_AN21 *((volatile unsigned int*)(0x424E4214UL)) -#define bFM3_ADC2_SCIS2_AN22 *((volatile unsigned int*)(0x424E4218UL)) -#define bFM3_ADC2_SCIS2_AN23 *((volatile unsigned int*)(0x424E421CUL)) -#define bFM3_ADC2_SCIS3_AN24 *((volatile unsigned int*)(0x424E4220UL)) -#define bFM3_ADC2_SCIS3_AN25 *((volatile unsigned int*)(0x424E4224UL)) -#define bFM3_ADC2_SCIS3_AN26 *((volatile unsigned int*)(0x424E4228UL)) -#define bFM3_ADC2_SCIS3_AN27 *((volatile unsigned int*)(0x424E422CUL)) -#define bFM3_ADC2_SCIS3_AN28 *((volatile unsigned int*)(0x424E4230UL)) -#define bFM3_ADC2_SCIS3_AN29 *((volatile unsigned int*)(0x424E4234UL)) -#define bFM3_ADC2_SCIS3_AN30 *((volatile unsigned int*)(0x424E4238UL)) -#define bFM3_ADC2_SCIS3_AN31 *((volatile unsigned int*)(0x424E423CUL)) -#define bFM3_ADC2_SCIS01_AN0 *((volatile unsigned int*)(0x424E4280UL)) -#define bFM3_ADC2_SCIS01_AN1 *((volatile unsigned int*)(0x424E4284UL)) -#define bFM3_ADC2_SCIS01_AN2 *((volatile unsigned int*)(0x424E4288UL)) -#define bFM3_ADC2_SCIS01_AN3 *((volatile unsigned int*)(0x424E428CUL)) -#define bFM3_ADC2_SCIS01_AN4 *((volatile unsigned int*)(0x424E4290UL)) -#define bFM3_ADC2_SCIS01_AN5 *((volatile unsigned int*)(0x424E4294UL)) -#define bFM3_ADC2_SCIS01_AN6 *((volatile unsigned int*)(0x424E4298UL)) -#define bFM3_ADC2_SCIS01_AN7 *((volatile unsigned int*)(0x424E429CUL)) -#define bFM3_ADC2_SCIS01_AN8 *((volatile unsigned int*)(0x424E42A0UL)) -#define bFM3_ADC2_SCIS01_AN9 *((volatile unsigned int*)(0x424E42A4UL)) -#define bFM3_ADC2_SCIS01_AN10 *((volatile unsigned int*)(0x424E42A8UL)) -#define bFM3_ADC2_SCIS01_AN11 *((volatile unsigned int*)(0x424E42ACUL)) -#define bFM3_ADC2_SCIS01_AN12 *((volatile unsigned int*)(0x424E42B0UL)) -#define bFM3_ADC2_SCIS01_AN13 *((volatile unsigned int*)(0x424E42B4UL)) -#define bFM3_ADC2_SCIS01_AN14 *((volatile unsigned int*)(0x424E42B8UL)) -#define bFM3_ADC2_SCIS01_AN15 *((volatile unsigned int*)(0x424E42BCUL)) -#define bFM3_ADC2_SCIS0_AN0 *((volatile unsigned int*)(0x424E4280UL)) -#define bFM3_ADC2_SCIS0_AN1 *((volatile unsigned int*)(0x424E4284UL)) -#define bFM3_ADC2_SCIS0_AN2 *((volatile unsigned int*)(0x424E4288UL)) -#define bFM3_ADC2_SCIS0_AN3 *((volatile unsigned int*)(0x424E428CUL)) -#define bFM3_ADC2_SCIS0_AN4 *((volatile unsigned int*)(0x424E4290UL)) -#define bFM3_ADC2_SCIS0_AN5 *((volatile unsigned int*)(0x424E4294UL)) -#define bFM3_ADC2_SCIS0_AN6 *((volatile unsigned int*)(0x424E4298UL)) -#define bFM3_ADC2_SCIS0_AN7 *((volatile unsigned int*)(0x424E429CUL)) -#define bFM3_ADC2_SCIS1_AN8 *((volatile unsigned int*)(0x424E42A0UL)) -#define bFM3_ADC2_SCIS1_AN9 *((volatile unsigned int*)(0x424E42A4UL)) -#define bFM3_ADC2_SCIS1_AN10 *((volatile unsigned int*)(0x424E42A8UL)) -#define bFM3_ADC2_SCIS1_AN11 *((volatile unsigned int*)(0x424E42ACUL)) -#define bFM3_ADC2_SCIS1_AN12 *((volatile unsigned int*)(0x424E42B0UL)) -#define bFM3_ADC2_SCIS1_AN13 *((volatile unsigned int*)(0x424E42B4UL)) -#define bFM3_ADC2_SCIS1_AN14 *((volatile unsigned int*)(0x424E42B8UL)) -#define bFM3_ADC2_SCIS1_AN15 *((volatile unsigned int*)(0x424E42BCUL)) -#define bFM3_ADC2_PFNS_PFS0 *((volatile unsigned int*)(0x424E4300UL)) -#define bFM3_ADC2_PFNS_PFS1 *((volatile unsigned int*)(0x424E4304UL)) -#define bFM3_ADC2_PFNS_TEST0 *((volatile unsigned int*)(0x424E4310UL)) -#define bFM3_ADC2_PFNS_TEST1 *((volatile unsigned int*)(0x424E4314UL)) -#define bFM3_ADC2_PCCR_PSTR *((volatile unsigned int*)(0x424E4320UL)) -#define bFM3_ADC2_PCCR_PHEN *((volatile unsigned int*)(0x424E4324UL)) -#define bFM3_ADC2_PCCR_PEEN *((volatile unsigned int*)(0x424E4328UL)) -#define bFM3_ADC2_PCCR_ESCE *((volatile unsigned int*)(0x424E432CUL)) -#define bFM3_ADC2_PCCR_PFCLR *((volatile unsigned int*)(0x424E4330UL)) -#define bFM3_ADC2_PCCR_POVR *((volatile unsigned int*)(0x424E4334UL)) -#define bFM3_ADC2_PCCR_PFUL *((volatile unsigned int*)(0x424E4338UL)) -#define bFM3_ADC2_PCCR_PEMP *((volatile unsigned int*)(0x424E433CUL)) -#define bFM3_ADC2_PCFD_PC0 *((volatile unsigned int*)(0x424E4380UL)) -#define bFM3_ADC2_PCFD_PC1 *((volatile unsigned int*)(0x424E4384UL)) -#define bFM3_ADC2_PCFD_PC2 *((volatile unsigned int*)(0x424E4388UL)) -#define bFM3_ADC2_PCFD_PC3 *((volatile unsigned int*)(0x424E438CUL)) -#define bFM3_ADC2_PCFD_PC4 *((volatile unsigned int*)(0x424E4390UL)) -#define bFM3_ADC2_PCFD_RS0 *((volatile unsigned int*)(0x424E43A0UL)) -#define bFM3_ADC2_PCFD_RS1 *((volatile unsigned int*)(0x424E43A4UL)) -#define bFM3_ADC2_PCFD_RS2 *((volatile unsigned int*)(0x424E43A8UL)) -#define bFM3_ADC2_PCFD_INVL *((volatile unsigned int*)(0x424E43B0UL)) -#define bFM3_ADC2_PCFD_PD0 *((volatile unsigned int*)(0x424E43D0UL)) -#define bFM3_ADC2_PCFD_PD1 *((volatile unsigned int*)(0x424E43D4UL)) -#define bFM3_ADC2_PCFD_PD2 *((volatile unsigned int*)(0x424E43D8UL)) -#define bFM3_ADC2_PCFD_PD3 *((volatile unsigned int*)(0x424E43DCUL)) -#define bFM3_ADC2_PCFD_PD4 *((volatile unsigned int*)(0x424E43E0UL)) -#define bFM3_ADC2_PCFD_PD5 *((volatile unsigned int*)(0x424E43E4UL)) -#define bFM3_ADC2_PCFD_PD6 *((volatile unsigned int*)(0x424E43E8UL)) -#define bFM3_ADC2_PCFD_PD7 *((volatile unsigned int*)(0x424E43ECUL)) -#define bFM3_ADC2_PCFD_PD8 *((volatile unsigned int*)(0x424E43F0UL)) -#define bFM3_ADC2_PCFD_PD9 *((volatile unsigned int*)(0x424E43F4UL)) -#define bFM3_ADC2_PCFD_PD10 *((volatile unsigned int*)(0x424E43F8UL)) -#define bFM3_ADC2_PCFD_PD11 *((volatile unsigned int*)(0x424E43FCUL)) -#define bFM3_ADC2_PCFDL_PC0 *((volatile unsigned int*)(0x424E4380UL)) -#define bFM3_ADC2_PCFDL_PC1 *((volatile unsigned int*)(0x424E4384UL)) -#define bFM3_ADC2_PCFDL_PC2 *((volatile unsigned int*)(0x424E4388UL)) -#define bFM3_ADC2_PCFDL_PC3 *((volatile unsigned int*)(0x424E438CUL)) -#define bFM3_ADC2_PCFDL_PC4 *((volatile unsigned int*)(0x424E4390UL)) -#define bFM3_ADC2_PCFDL_RS0 *((volatile unsigned int*)(0x424E43A0UL)) -#define bFM3_ADC2_PCFDL_RS1 *((volatile unsigned int*)(0x424E43A4UL)) -#define bFM3_ADC2_PCFDL_RS2 *((volatile unsigned int*)(0x424E43A8UL)) -#define bFM3_ADC2_PCFDL_INVL *((volatile unsigned int*)(0x424E43B0UL)) -#define bFM3_ADC2_PCFDH_PD0 *((volatile unsigned int*)(0x424E43D0UL)) -#define bFM3_ADC2_PCFDH_PD1 *((volatile unsigned int*)(0x424E43D4UL)) -#define bFM3_ADC2_PCFDH_PD2 *((volatile unsigned int*)(0x424E43D8UL)) -#define bFM3_ADC2_PCFDH_PD3 *((volatile unsigned int*)(0x424E43DCUL)) -#define bFM3_ADC2_PCFDH_PD4 *((volatile unsigned int*)(0x424E43E0UL)) -#define bFM3_ADC2_PCFDH_PD5 *((volatile unsigned int*)(0x424E43E4UL)) -#define bFM3_ADC2_PCFDH_PD6 *((volatile unsigned int*)(0x424E43E8UL)) -#define bFM3_ADC2_PCFDH_PD7 *((volatile unsigned int*)(0x424E43ECUL)) -#define bFM3_ADC2_PCFDH_PD8 *((volatile unsigned int*)(0x424E43F0UL)) -#define bFM3_ADC2_PCFDH_PD9 *((volatile unsigned int*)(0x424E43F4UL)) -#define bFM3_ADC2_PCFDH_PD10 *((volatile unsigned int*)(0x424E43F8UL)) -#define bFM3_ADC2_PCFDH_PD11 *((volatile unsigned int*)(0x424E43FCUL)) -#define bFM3_ADC2_PCIS_P1A0 *((volatile unsigned int*)(0x424E4400UL)) -#define bFM3_ADC2_PCIS_P1A1 *((volatile unsigned int*)(0x424E4404UL)) -#define bFM3_ADC2_PCIS_P1A2 *((volatile unsigned int*)(0x424E4408UL)) -#define bFM3_ADC2_PCIS_P2A0 *((volatile unsigned int*)(0x424E440CUL)) -#define bFM3_ADC2_PCIS_P2A1 *((volatile unsigned int*)(0x424E4410UL)) -#define bFM3_ADC2_PCIS_P2A2 *((volatile unsigned int*)(0x424E4414UL)) -#define bFM3_ADC2_PCIS_P2A3 *((volatile unsigned int*)(0x424E4418UL)) -#define bFM3_ADC2_PCIS_P2A4 *((volatile unsigned int*)(0x424E441CUL)) -#define bFM3_ADC2_CMPCR_CCH0 *((volatile unsigned int*)(0x424E4480UL)) -#define bFM3_ADC2_CMPCR_CCH1 *((volatile unsigned int*)(0x424E4484UL)) -#define bFM3_ADC2_CMPCR_CCH2 *((volatile unsigned int*)(0x424E4488UL)) -#define bFM3_ADC2_CMPCR_CCH3 *((volatile unsigned int*)(0x424E448CUL)) -#define bFM3_ADC2_CMPCR_CCH4 *((volatile unsigned int*)(0x424E4490UL)) -#define bFM3_ADC2_CMPCR_CMD0 *((volatile unsigned int*)(0x424E4494UL)) -#define bFM3_ADC2_CMPCR_CMD1 *((volatile unsigned int*)(0x424E4498UL)) -#define bFM3_ADC2_CMPCR_CMPEN *((volatile unsigned int*)(0x424E449CUL)) -#define bFM3_ADC2_CMPD_CMAD2 *((volatile unsigned int*)(0x424E44D8UL)) -#define bFM3_ADC2_CMPD_CMAD3 *((volatile unsigned int*)(0x424E44DCUL)) -#define bFM3_ADC2_CMPD_CMAD4 *((volatile unsigned int*)(0x424E44E0UL)) -#define bFM3_ADC2_CMPD_CMAD5 *((volatile unsigned int*)(0x424E44E4UL)) -#define bFM3_ADC2_CMPD_CMAD6 *((volatile unsigned int*)(0x424E44E8UL)) -#define bFM3_ADC2_CMPD_CMAD7 *((volatile unsigned int*)(0x424E44ECUL)) -#define bFM3_ADC2_CMPD_CMAD8 *((volatile unsigned int*)(0x424E44F0UL)) -#define bFM3_ADC2_CMPD_CMAD9 *((volatile unsigned int*)(0x424E44F4UL)) -#define bFM3_ADC2_CMPD_CMAD10 *((volatile unsigned int*)(0x424E44F8UL)) -#define bFM3_ADC2_CMPD_CMAD11 *((volatile unsigned int*)(0x424E44FCUL)) -#define bFM3_ADC2_ADSS23_TS16 *((volatile unsigned int*)(0x424E4500UL)) -#define bFM3_ADC2_ADSS23_TS17 *((volatile unsigned int*)(0x424E4504UL)) -#define bFM3_ADC2_ADSS23_TS18 *((volatile unsigned int*)(0x424E4508UL)) -#define bFM3_ADC2_ADSS23_TS19 *((volatile unsigned int*)(0x424E450CUL)) -#define bFM3_ADC2_ADSS23_TS20 *((volatile unsigned int*)(0x424E4510UL)) -#define bFM3_ADC2_ADSS23_TS21 *((volatile unsigned int*)(0x424E4514UL)) -#define bFM3_ADC2_ADSS23_TS22 *((volatile unsigned int*)(0x424E4518UL)) -#define bFM3_ADC2_ADSS23_TS23 *((volatile unsigned int*)(0x424E451CUL)) -#define bFM3_ADC2_ADSS23_TS24 *((volatile unsigned int*)(0x424E4520UL)) -#define bFM3_ADC2_ADSS23_TS25 *((volatile unsigned int*)(0x424E4524UL)) -#define bFM3_ADC2_ADSS23_TS26 *((volatile unsigned int*)(0x424E4528UL)) -#define bFM3_ADC2_ADSS23_TS27 *((volatile unsigned int*)(0x424E452CUL)) -#define bFM3_ADC2_ADSS23_TS28 *((volatile unsigned int*)(0x424E4530UL)) -#define bFM3_ADC2_ADSS23_TS29 *((volatile unsigned int*)(0x424E4534UL)) -#define bFM3_ADC2_ADSS23_TS30 *((volatile unsigned int*)(0x424E4538UL)) -#define bFM3_ADC2_ADSS23_TS31 *((volatile unsigned int*)(0x424E453CUL)) -#define bFM3_ADC2_ADSS2_TS16 *((volatile unsigned int*)(0x424E4500UL)) -#define bFM3_ADC2_ADSS2_TS17 *((volatile unsigned int*)(0x424E4504UL)) -#define bFM3_ADC2_ADSS2_TS18 *((volatile unsigned int*)(0x424E4508UL)) -#define bFM3_ADC2_ADSS2_TS19 *((volatile unsigned int*)(0x424E450CUL)) -#define bFM3_ADC2_ADSS2_TS20 *((volatile unsigned int*)(0x424E4510UL)) -#define bFM3_ADC2_ADSS2_TS21 *((volatile unsigned int*)(0x424E4514UL)) -#define bFM3_ADC2_ADSS2_TS22 *((volatile unsigned int*)(0x424E4518UL)) -#define bFM3_ADC2_ADSS2_TS23 *((volatile unsigned int*)(0x424E451CUL)) -#define bFM3_ADC2_ADSS3_TS24 *((volatile unsigned int*)(0x424E4520UL)) -#define bFM3_ADC2_ADSS3_TS25 *((volatile unsigned int*)(0x424E4524UL)) -#define bFM3_ADC2_ADSS3_TS26 *((volatile unsigned int*)(0x424E4528UL)) -#define bFM3_ADC2_ADSS3_TS27 *((volatile unsigned int*)(0x424E452CUL)) -#define bFM3_ADC2_ADSS3_TS28 *((volatile unsigned int*)(0x424E4530UL)) -#define bFM3_ADC2_ADSS3_TS29 *((volatile unsigned int*)(0x424E4534UL)) -#define bFM3_ADC2_ADSS3_TS30 *((volatile unsigned int*)(0x424E4538UL)) -#define bFM3_ADC2_ADSS3_TS31 *((volatile unsigned int*)(0x424E453CUL)) -#define bFM3_ADC2_ADSS01_TS0 *((volatile unsigned int*)(0x424E4580UL)) -#define bFM3_ADC2_ADSS01_TS1 *((volatile unsigned int*)(0x424E4584UL)) -#define bFM3_ADC2_ADSS01_TS2 *((volatile unsigned int*)(0x424E4588UL)) -#define bFM3_ADC2_ADSS01_TS3 *((volatile unsigned int*)(0x424E458CUL)) -#define bFM3_ADC2_ADSS01_TS4 *((volatile unsigned int*)(0x424E4590UL)) -#define bFM3_ADC2_ADSS01_TS5 *((volatile unsigned int*)(0x424E4594UL)) -#define bFM3_ADC2_ADSS01_TS6 *((volatile unsigned int*)(0x424E4598UL)) -#define bFM3_ADC2_ADSS01_TS7 *((volatile unsigned int*)(0x424E459CUL)) -#define bFM3_ADC2_ADSS01_TS8 *((volatile unsigned int*)(0x424E45A0UL)) -#define bFM3_ADC2_ADSS01_TS9 *((volatile unsigned int*)(0x424E45A4UL)) -#define bFM3_ADC2_ADSS01_TS10 *((volatile unsigned int*)(0x424E45A8UL)) -#define bFM3_ADC2_ADSS01_TS11 *((volatile unsigned int*)(0x424E45ACUL)) -#define bFM3_ADC2_ADSS01_TS12 *((volatile unsigned int*)(0x424E45B0UL)) -#define bFM3_ADC2_ADSS01_TS13 *((volatile unsigned int*)(0x424E45B4UL)) -#define bFM3_ADC2_ADSS01_TS14 *((volatile unsigned int*)(0x424E45B8UL)) -#define bFM3_ADC2_ADSS01_TS15 *((volatile unsigned int*)(0x424E45BCUL)) -#define bFM3_ADC2_ADSS0_TS0 *((volatile unsigned int*)(0x424E4580UL)) -#define bFM3_ADC2_ADSS0_TS1 *((volatile unsigned int*)(0x424E4584UL)) -#define bFM3_ADC2_ADSS0_TS2 *((volatile unsigned int*)(0x424E4588UL)) -#define bFM3_ADC2_ADSS0_TS3 *((volatile unsigned int*)(0x424E458CUL)) -#define bFM3_ADC2_ADSS0_TS4 *((volatile unsigned int*)(0x424E4590UL)) -#define bFM3_ADC2_ADSS0_TS5 *((volatile unsigned int*)(0x424E4594UL)) -#define bFM3_ADC2_ADSS0_TS6 *((volatile unsigned int*)(0x424E4598UL)) -#define bFM3_ADC2_ADSS0_TS7 *((volatile unsigned int*)(0x424E459CUL)) -#define bFM3_ADC2_ADSS1_TS8 *((volatile unsigned int*)(0x424E45A0UL)) -#define bFM3_ADC2_ADSS1_TS9 *((volatile unsigned int*)(0x424E45A4UL)) -#define bFM3_ADC2_ADSS1_TS10 *((volatile unsigned int*)(0x424E45A8UL)) -#define bFM3_ADC2_ADSS1_TS11 *((volatile unsigned int*)(0x424E45ACUL)) -#define bFM3_ADC2_ADSS1_TS12 *((volatile unsigned int*)(0x424E45B0UL)) -#define bFM3_ADC2_ADSS1_TS13 *((volatile unsigned int*)(0x424E45B4UL)) -#define bFM3_ADC2_ADSS1_TS14 *((volatile unsigned int*)(0x424E45B8UL)) -#define bFM3_ADC2_ADSS1_TS15 *((volatile unsigned int*)(0x424E45BCUL)) -#define bFM3_ADC2_ADST01_ST10 *((volatile unsigned int*)(0x424E4600UL)) -#define bFM3_ADC2_ADST01_ST11 *((volatile unsigned int*)(0x424E4604UL)) -#define bFM3_ADC2_ADST01_ST12 *((volatile unsigned int*)(0x424E4608UL)) -#define bFM3_ADC2_ADST01_ST13 *((volatile unsigned int*)(0x424E460CUL)) -#define bFM3_ADC2_ADST01_ST14 *((volatile unsigned int*)(0x424E4610UL)) -#define bFM3_ADC2_ADST01_STX10 *((volatile unsigned int*)(0x424E4614UL)) -#define bFM3_ADC2_ADST01_STX11 *((volatile unsigned int*)(0x424E4618UL)) -#define bFM3_ADC2_ADST01_STX12 *((volatile unsigned int*)(0x424E461CUL)) -#define bFM3_ADC2_ADST01_ST00 *((volatile unsigned int*)(0x424E4620UL)) -#define bFM3_ADC2_ADST01_ST01 *((volatile unsigned int*)(0x424E4624UL)) -#define bFM3_ADC2_ADST01_ST02 *((volatile unsigned int*)(0x424E4628UL)) -#define bFM3_ADC2_ADST01_ST03 *((volatile unsigned int*)(0x424E462CUL)) -#define bFM3_ADC2_ADST01_ST04 *((volatile unsigned int*)(0x424E4630UL)) -#define bFM3_ADC2_ADST01_STX00 *((volatile unsigned int*)(0x424E4634UL)) -#define bFM3_ADC2_ADST01_STX01 *((volatile unsigned int*)(0x424E4638UL)) -#define bFM3_ADC2_ADST01_STX02 *((volatile unsigned int*)(0x424E463CUL)) -#define bFM3_ADC2_ADST1_ST10 *((volatile unsigned int*)(0x424E4600UL)) -#define bFM3_ADC2_ADST1_ST11 *((volatile unsigned int*)(0x424E4604UL)) -#define bFM3_ADC2_ADST1_ST12 *((volatile unsigned int*)(0x424E4608UL)) -#define bFM3_ADC2_ADST1_ST13 *((volatile unsigned int*)(0x424E460CUL)) -#define bFM3_ADC2_ADST1_ST14 *((volatile unsigned int*)(0x424E4610UL)) -#define bFM3_ADC2_ADST1_STX10 *((volatile unsigned int*)(0x424E4614UL)) -#define bFM3_ADC2_ADST1_STX11 *((volatile unsigned int*)(0x424E4618UL)) -#define bFM3_ADC2_ADST1_STX12 *((volatile unsigned int*)(0x424E461CUL)) -#define bFM3_ADC2_ADST0_ST00 *((volatile unsigned int*)(0x424E4620UL)) -#define bFM3_ADC2_ADST0_ST01 *((volatile unsigned int*)(0x424E4624UL)) -#define bFM3_ADC2_ADST0_ST02 *((volatile unsigned int*)(0x424E4628UL)) -#define bFM3_ADC2_ADST0_ST03 *((volatile unsigned int*)(0x424E462CUL)) -#define bFM3_ADC2_ADST0_ST04 *((volatile unsigned int*)(0x424E4630UL)) -#define bFM3_ADC2_ADST0_STX00 *((volatile unsigned int*)(0x424E4634UL)) -#define bFM3_ADC2_ADST0_STX01 *((volatile unsigned int*)(0x424E4638UL)) -#define bFM3_ADC2_ADST0_STX02 *((volatile unsigned int*)(0x424E463CUL)) -#define bFM3_ADC2_ADCT_CT0 *((volatile unsigned int*)(0x424E4680UL)) -#define bFM3_ADC2_ADCT_CT1 *((volatile unsigned int*)(0x424E4684UL)) -#define bFM3_ADC2_ADCT_CT2 *((volatile unsigned int*)(0x424E4688UL)) -#define bFM3_ADC2_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E4700UL)) -#define bFM3_ADC2_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E4704UL)) -#define bFM3_ADC2_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E4708UL)) -#define bFM3_ADC2_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E470CUL)) -#define bFM3_ADC2_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E4720UL)) -#define bFM3_ADC2_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E4724UL)) -#define bFM3_ADC2_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E4728UL)) -#define bFM3_ADC2_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E472CUL)) -#define bFM3_ADC2_ADCEN_ENBL *((volatile unsigned int*)(0x424E4780UL)) -#define bFM3_ADC2_ADCEN_READY *((volatile unsigned int*)(0x424E4784UL)) - -/* CR trimming registers */ -#define bFM3_CRTRIM_MCR_PSR_CSR0 *((volatile unsigned int*)(0x425C0000UL)) -#define bFM3_CRTRIM_MCR_PSR_CSR1 *((volatile unsigned int*)(0x425C0004UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD0 *((volatile unsigned int*)(0x425C0080UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD1 *((volatile unsigned int*)(0x425C0084UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD2 *((volatile unsigned int*)(0x425C0088UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD3 *((volatile unsigned int*)(0x425C008CUL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD4 *((volatile unsigned int*)(0x425C0090UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD5 *((volatile unsigned int*)(0x425C0094UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD6 *((volatile unsigned int*)(0x425C0098UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD7 *((volatile unsigned int*)(0x425C009CUL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD8 *((volatile unsigned int*)(0x425C00A0UL)) -#define bFM3_CRTRIM_MCR_FTRM_TRD9 *((volatile unsigned int*)(0x425C00A4UL)) - -/* External interrupt registers */ -#define bFM3_EXTI_ENIR_EN0 *((volatile unsigned int*)(0x42600000UL)) -#define bFM3_EXTI_ENIR_EN1 *((volatile unsigned int*)(0x42600004UL)) -#define bFM3_EXTI_ENIR_EN2 *((volatile unsigned int*)(0x42600008UL)) -#define bFM3_EXTI_ENIR_EN3 *((volatile unsigned int*)(0x4260000CUL)) -#define bFM3_EXTI_ENIR_EN4 *((volatile unsigned int*)(0x42600010UL)) -#define bFM3_EXTI_ENIR_EN5 *((volatile unsigned int*)(0x42600014UL)) -#define bFM3_EXTI_ENIR_EN6 *((volatile unsigned int*)(0x42600018UL)) -#define bFM3_EXTI_ENIR_EN7 *((volatile unsigned int*)(0x4260001CUL)) -#define bFM3_EXTI_ENIR_EN8 *((volatile unsigned int*)(0x42600020UL)) -#define bFM3_EXTI_ENIR_EN9 *((volatile unsigned int*)(0x42600024UL)) -#define bFM3_EXTI_ENIR_EN10 *((volatile unsigned int*)(0x42600028UL)) -#define bFM3_EXTI_ENIR_EN11 *((volatile unsigned int*)(0x4260002CUL)) -#define bFM3_EXTI_ENIR_EN12 *((volatile unsigned int*)(0x42600030UL)) -#define bFM3_EXTI_ENIR_EN13 *((volatile unsigned int*)(0x42600034UL)) -#define bFM3_EXTI_ENIR_EN14 *((volatile unsigned int*)(0x42600038UL)) -#define bFM3_EXTI_ENIR_EN15 *((volatile unsigned int*)(0x4260003CUL)) -#define bFM3_EXTI_EIRR_ER0 *((volatile unsigned int*)(0x42600080UL)) -#define bFM3_EXTI_EIRR_ER1 *((volatile unsigned int*)(0x42600084UL)) -#define bFM3_EXTI_EIRR_ER2 *((volatile unsigned int*)(0x42600088UL)) -#define bFM3_EXTI_EIRR_ER3 *((volatile unsigned int*)(0x4260008CUL)) -#define bFM3_EXTI_EIRR_ER4 *((volatile unsigned int*)(0x42600090UL)) -#define bFM3_EXTI_EIRR_ER5 *((volatile unsigned int*)(0x42600094UL)) -#define bFM3_EXTI_EIRR_ER6 *((volatile unsigned int*)(0x42600098UL)) -#define bFM3_EXTI_EIRR_ER7 *((volatile unsigned int*)(0x4260009CUL)) -#define bFM3_EXTI_EIRR_ER8 *((volatile unsigned int*)(0x426000A0UL)) -#define bFM3_EXTI_EIRR_ER9 *((volatile unsigned int*)(0x426000A4UL)) -#define bFM3_EXTI_EIRR_ER10 *((volatile unsigned int*)(0x426000A8UL)) -#define bFM3_EXTI_EIRR_ER11 *((volatile unsigned int*)(0x426000ACUL)) -#define bFM3_EXTI_EIRR_ER12 *((volatile unsigned int*)(0x426000B0UL)) -#define bFM3_EXTI_EIRR_ER13 *((volatile unsigned int*)(0x426000B4UL)) -#define bFM3_EXTI_EIRR_ER14 *((volatile unsigned int*)(0x426000B8UL)) -#define bFM3_EXTI_EIRR_ER15 *((volatile unsigned int*)(0x426000BCUL)) -#define bFM3_EXTI_EICL_ECL0 *((volatile unsigned int*)(0x42600100UL)) -#define bFM3_EXTI_EICL_ECL1 *((volatile unsigned int*)(0x42600104UL)) -#define bFM3_EXTI_EICL_ECL2 *((volatile unsigned int*)(0x42600108UL)) -#define bFM3_EXTI_EICL_ECL3 *((volatile unsigned int*)(0x4260010CUL)) -#define bFM3_EXTI_EICL_ECL4 *((volatile unsigned int*)(0x42600110UL)) -#define bFM3_EXTI_EICL_ECL5 *((volatile unsigned int*)(0x42600114UL)) -#define bFM3_EXTI_EICL_ECL6 *((volatile unsigned int*)(0x42600118UL)) -#define bFM3_EXTI_EICL_ECL7 *((volatile unsigned int*)(0x4260011CUL)) -#define bFM3_EXTI_EICL_ECL8 *((volatile unsigned int*)(0x42600120UL)) -#define bFM3_EXTI_EICL_ECL9 *((volatile unsigned int*)(0x42600124UL)) -#define bFM3_EXTI_EICL_ECL10 *((volatile unsigned int*)(0x42600128UL)) -#define bFM3_EXTI_EICL_ECL11 *((volatile unsigned int*)(0x4260012CUL)) -#define bFM3_EXTI_EICL_ECL12 *((volatile unsigned int*)(0x42600130UL)) -#define bFM3_EXTI_EICL_ECL13 *((volatile unsigned int*)(0x42600134UL)) -#define bFM3_EXTI_EICL_ECL14 *((volatile unsigned int*)(0x42600138UL)) -#define bFM3_EXTI_EICL_ECL15 *((volatile unsigned int*)(0x4260013CUL)) -#define bFM3_EXTI_ELVR_LA0 *((volatile unsigned int*)(0x42600180UL)) -#define bFM3_EXTI_ELVR_LB0 *((volatile unsigned int*)(0x42600184UL)) -#define bFM3_EXTI_ELVR_LA1 *((volatile unsigned int*)(0x42600188UL)) -#define bFM3_EXTI_ELVR_LB1 *((volatile unsigned int*)(0x4260018CUL)) -#define bFM3_EXTI_ELVR_LA2 *((volatile unsigned int*)(0x42600190UL)) -#define bFM3_EXTI_ELVR_LB2 *((volatile unsigned int*)(0x42600194UL)) -#define bFM3_EXTI_ELVR_LA3 *((volatile unsigned int*)(0x42600198UL)) -#define bFM3_EXTI_ELVR_LB3 *((volatile unsigned int*)(0x4260019CUL)) -#define bFM3_EXTI_ELVR_LA4 *((volatile unsigned int*)(0x426001A0UL)) -#define bFM3_EXTI_ELVR_LB4 *((volatile unsigned int*)(0x426001A4UL)) -#define bFM3_EXTI_ELVR_LA5 *((volatile unsigned int*)(0x426001A8UL)) -#define bFM3_EXTI_ELVR_LB5 *((volatile unsigned int*)(0x426001ACUL)) -#define bFM3_EXTI_ELVR_LA6 *((volatile unsigned int*)(0x426001B0UL)) -#define bFM3_EXTI_ELVR_LB6 *((volatile unsigned int*)(0x426001B4UL)) -#define bFM3_EXTI_ELVR_LA7 *((volatile unsigned int*)(0x426001B8UL)) -#define bFM3_EXTI_ELVR_LB7 *((volatile unsigned int*)(0x426001BCUL)) -#define bFM3_EXTI_ELVR_LA8 *((volatile unsigned int*)(0x426001C0UL)) -#define bFM3_EXTI_ELVR_LB8 *((volatile unsigned int*)(0x426001C4UL)) -#define bFM3_EXTI_ELVR_LA9 *((volatile unsigned int*)(0x426001C8UL)) -#define bFM3_EXTI_ELVR_LB9 *((volatile unsigned int*)(0x426001CCUL)) -#define bFM3_EXTI_ELVR_LA10 *((volatile unsigned int*)(0x426001D0UL)) -#define bFM3_EXTI_ELVR_LB10 *((volatile unsigned int*)(0x426001D4UL)) -#define bFM3_EXTI_ELVR_LA11 *((volatile unsigned int*)(0x426001D8UL)) -#define bFM3_EXTI_ELVR_LB11 *((volatile unsigned int*)(0x426001DCUL)) -#define bFM3_EXTI_ELVR_LA12 *((volatile unsigned int*)(0x426001E0UL)) -#define bFM3_EXTI_ELVR_LB12 *((volatile unsigned int*)(0x426001E4UL)) -#define bFM3_EXTI_ELVR_LA13 *((volatile unsigned int*)(0x426001E8UL)) -#define bFM3_EXTI_ELVR_LB13 *((volatile unsigned int*)(0x426001ECUL)) -#define bFM3_EXTI_ELVR_LA14 *((volatile unsigned int*)(0x426001F0UL)) -#define bFM3_EXTI_ELVR_LB14 *((volatile unsigned int*)(0x426001F4UL)) -#define bFM3_EXTI_ELVR_LA15 *((volatile unsigned int*)(0x426001F8UL)) -#define bFM3_EXTI_ELVR_LB15 *((volatile unsigned int*)(0x426001FCUL)) -#define bFM3_EXTI_NMIRR_NR0 *((volatile unsigned int*)(0x42600280UL)) -#define bFM3_EXTI_NMICL_NCL0 *((volatile unsigned int*)(0x42600300UL)) - -/* Interrupt request read registers */ -#define bFM3_INTREQ_DRQSEL_DRQSEL0 *((volatile unsigned int*)(0x42620000UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL1 *((volatile unsigned int*)(0x42620004UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL2 *((volatile unsigned int*)(0x42620008UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL3 *((volatile unsigned int*)(0x4262000CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL4 *((volatile unsigned int*)(0x42620010UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL5 *((volatile unsigned int*)(0x42620014UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL6 *((volatile unsigned int*)(0x42620018UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL7 *((volatile unsigned int*)(0x4262001CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL8 *((volatile unsigned int*)(0x42620020UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL9 *((volatile unsigned int*)(0x42620024UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL10 *((volatile unsigned int*)(0x42620028UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL11 *((volatile unsigned int*)(0x4262002CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL12 *((volatile unsigned int*)(0x42620030UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL13 *((volatile unsigned int*)(0x42620034UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL14 *((volatile unsigned int*)(0x42620038UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL15 *((volatile unsigned int*)(0x4262003CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL16 *((volatile unsigned int*)(0x42620040UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL17 *((volatile unsigned int*)(0x42620044UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL18 *((volatile unsigned int*)(0x42620048UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL19 *((volatile unsigned int*)(0x4262004CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL20 *((volatile unsigned int*)(0x42620050UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL21 *((volatile unsigned int*)(0x42620054UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL22 *((volatile unsigned int*)(0x42620058UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL23 *((volatile unsigned int*)(0x4262005CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL24 *((volatile unsigned int*)(0x42620060UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL25 *((volatile unsigned int*)(0x42620064UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL26 *((volatile unsigned int*)(0x42620068UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL27 *((volatile unsigned int*)(0x4262006CUL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL28 *((volatile unsigned int*)(0x42620070UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL29 *((volatile unsigned int*)(0x42620074UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL30 *((volatile unsigned int*)(0x42620078UL)) -#define bFM3_INTREQ_DRQSEL_DRQSEL31 *((volatile unsigned int*)(0x4262007CUL)) -#define bFM3_INTREQ_EXC02MON_NMI *((volatile unsigned int*)(0x42620200UL)) -#define bFM3_INTREQ_EXC02MON_HWINT *((volatile unsigned int*)(0x42620204UL)) -#define bFM3_INTREQ_IRQ00MON_FCSINT *((volatile unsigned int*)(0x42620280UL)) -#define bFM3_INTREQ_IRQ01MON_SWWDTINT *((volatile unsigned int*)(0x42620300UL)) -#define bFM3_INTREQ_IRQ02MON_LVDINT *((volatile unsigned int*)(0x42620380UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT0 *((volatile unsigned int*)(0x42620400UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT1 *((volatile unsigned int*)(0x42620404UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT2 *((volatile unsigned int*)(0x42620408UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE0INT3 *((volatile unsigned int*)(0x4262040CUL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT0 *((volatile unsigned int*)(0x42620410UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT1 *((volatile unsigned int*)(0x42620414UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT2 *((volatile unsigned int*)(0x42620418UL)) -#define bFM3_INTREQ_IRQ03MON_WAVE1INT3 *((volatile unsigned int*)(0x4262041CUL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT0 *((volatile unsigned int*)(0x42620480UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT1 *((volatile unsigned int*)(0x42620484UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT2 *((volatile unsigned int*)(0x42620488UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT3 *((volatile unsigned int*)(0x4262048CUL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT4 *((volatile unsigned int*)(0x42620490UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT5 *((volatile unsigned int*)(0x42620494UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT6 *((volatile unsigned int*)(0x42620498UL)) -#define bFM3_INTREQ_IRQ04MON_EXTINT7 *((volatile unsigned int*)(0x4262049CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT0 *((volatile unsigned int*)(0x42620500UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT1 *((volatile unsigned int*)(0x42620504UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT2 *((volatile unsigned int*)(0x42620508UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT3 *((volatile unsigned int*)(0x4262050CUL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT4 *((volatile unsigned int*)(0x42620510UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT5 *((volatile unsigned int*)(0x42620514UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT6 *((volatile unsigned int*)(0x42620518UL)) -#define bFM3_INTREQ_IRQ05MON_EXTINT7 *((volatile unsigned int*)(0x4262051CUL)) -#define bFM3_INTREQ_IRQ06MON_TIMINT0 *((volatile unsigned int*)(0x42620580UL)) -#define bFM3_INTREQ_IRQ06MON_TIMINT1 *((volatile unsigned int*)(0x42620584UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT0 *((volatile unsigned int*)(0x42620588UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT1 *((volatile unsigned int*)(0x4262058CUL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT2 *((volatile unsigned int*)(0x42620590UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT3 *((volatile unsigned int*)(0x42620594UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT4 *((volatile unsigned int*)(0x42620598UL)) -#define bFM3_INTREQ_IRQ06MON_QUD0INT5 *((volatile unsigned int*)(0x4262059CUL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT0 *((volatile unsigned int*)(0x426205A0UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT1 *((volatile unsigned int*)(0x426205A4UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT2 *((volatile unsigned int*)(0x426205A8UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT3 *((volatile unsigned int*)(0x426205ACUL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT4 *((volatile unsigned int*)(0x426205B0UL)) -#define bFM3_INTREQ_IRQ06MON_QUD1INT5 *((volatile unsigned int*)(0x426205B4UL)) -#define bFM3_INTREQ_IRQ07MON_FMSINT *((volatile unsigned int*)(0x42620600UL)) -#define bFM3_INTREQ_IRQ08MON_MFSINT0 *((volatile unsigned int*)(0x42620680UL)) -#define bFM3_INTREQ_IRQ08MON_MFSINT1 *((volatile unsigned int*)(0x42620684UL)) -#define bFM3_INTREQ_IRQ09MON_FMSINT *((volatile unsigned int*)(0x42620700UL)) -#define bFM3_INTREQ_IRQ10MON_MFSINT0 *((volatile unsigned int*)(0x42620780UL)) -#define bFM3_INTREQ_IRQ10MON_MFSINT1 *((volatile unsigned int*)(0x42620784UL)) -#define bFM3_INTREQ_IRQ11MON_FMSINT *((volatile unsigned int*)(0x42620800UL)) -#define bFM3_INTREQ_IRQ12MON_MFSINT0 *((volatile unsigned int*)(0x42620880UL)) -#define bFM3_INTREQ_IRQ12MON_MFSINT1 *((volatile unsigned int*)(0x42620884UL)) -#define bFM3_INTREQ_IRQ13MON_FMSINT *((volatile unsigned int*)(0x42620900UL)) -#define bFM3_INTREQ_IRQ14MON_MFSINT0 *((volatile unsigned int*)(0x42620980UL)) -#define bFM3_INTREQ_IRQ14MON_MFSINT1 *((volatile unsigned int*)(0x42620984UL)) -#define bFM3_INTREQ_IRQ15MON_FMSINT *((volatile unsigned int*)(0x42620A00UL)) -#define bFM3_INTREQ_IRQ16MON_MFSINT0 *((volatile unsigned int*)(0x42620A80UL)) -#define bFM3_INTREQ_IRQ16MON_MFSINT1 *((volatile unsigned int*)(0x42620A84UL)) -#define bFM3_INTREQ_IRQ17MON_FMSINT *((volatile unsigned int*)(0x42620B00UL)) -#define bFM3_INTREQ_IRQ18MON_MFSINT0 *((volatile unsigned int*)(0x42620B80UL)) -#define bFM3_INTREQ_IRQ18MON_MFSINT1 *((volatile unsigned int*)(0x42620B84UL)) -#define bFM3_INTREQ_IRQ19MON_FMSINT *((volatile unsigned int*)(0x42620C00UL)) -#define bFM3_INTREQ_IRQ20MON_MFSINT0 *((volatile unsigned int*)(0x42620C80UL)) -#define bFM3_INTREQ_IRQ20MON_MFSINT1 *((volatile unsigned int*)(0x42620C84UL)) -#define bFM3_INTREQ_IRQ21MON_FMSINT *((volatile unsigned int*)(0x42620D00UL)) -#define bFM3_INTREQ_IRQ22MON_MFSINT0 *((volatile unsigned int*)(0x42620D80UL)) -#define bFM3_INTREQ_IRQ22MON_MFSINT1 *((volatile unsigned int*)(0x42620D84UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT0 *((volatile unsigned int*)(0x42620E00UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT1 *((volatile unsigned int*)(0x42620E04UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT2 *((volatile unsigned int*)(0x42620E08UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT3 *((volatile unsigned int*)(0x42620E0CUL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT4 *((volatile unsigned int*)(0x42620E10UL)) -#define bFM3_INTREQ_IRQ23MON_PPGINT5 *((volatile unsigned int*)(0x42620E14UL)) -#define bFM3_INTREQ_IRQ24MON_MOSCINT *((volatile unsigned int*)(0x42620E80UL)) -#define bFM3_INTREQ_IRQ24MON_SOSCINT *((volatile unsigned int*)(0x42620E84UL)) -#define bFM3_INTREQ_IRQ24MON_MPLLINT *((volatile unsigned int*)(0x42620E88UL)) -#define bFM3_INTREQ_IRQ24MON_UPLLINT *((volatile unsigned int*)(0x42620E8CUL)) -#define bFM3_INTREQ_IRQ24MON_WCINT *((volatile unsigned int*)(0x42620E90UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT0 *((volatile unsigned int*)(0x42620F00UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT1 *((volatile unsigned int*)(0x42620F04UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT2 *((volatile unsigned int*)(0x42620F08UL)) -#define bFM3_INTREQ_IRQ25MON_ADCINT3 *((volatile unsigned int*)(0x42620F0CUL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT0 *((volatile unsigned int*)(0x42620F80UL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT1 *((volatile unsigned int*)(0x42620F84UL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT2 *((volatile unsigned int*)(0x42620F88UL)) -#define bFM3_INTREQ_IRQ26MON_ADCINT3 *((volatile unsigned int*)(0x42620F8CUL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT0 *((volatile unsigned int*)(0x42621000UL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT1 *((volatile unsigned int*)(0x42621004UL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT2 *((volatile unsigned int*)(0x42621008UL)) -#define bFM3_INTREQ_IRQ27MON_ADCINT3 *((volatile unsigned int*)(0x4262100CUL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT0 *((volatile unsigned int*)(0x42621080UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT1 *((volatile unsigned int*)(0x42621084UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT2 *((volatile unsigned int*)(0x42621088UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT3 *((volatile unsigned int*)(0x4262108CUL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT4 *((volatile unsigned int*)(0x42621090UL)) -#define bFM3_INTREQ_IRQ28MON_FRT0INT5 *((volatile unsigned int*)(0x42621094UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT0 *((volatile unsigned int*)(0x42621098UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT1 *((volatile unsigned int*)(0x4262109CUL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT2 *((volatile unsigned int*)(0x426210A0UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT3 *((volatile unsigned int*)(0x426210A4UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT4 *((volatile unsigned int*)(0x426210A8UL)) -#define bFM3_INTREQ_IRQ28MON_FRT1INT5 *((volatile unsigned int*)(0x426210ACUL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT0 *((volatile unsigned int*)(0x42621100UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT1 *((volatile unsigned int*)(0x42621104UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT2 *((volatile unsigned int*)(0x42621108UL)) -#define bFM3_INTREQ_IRQ29MON_ICU0INT3 *((volatile unsigned int*)(0x4262110CUL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT0 *((volatile unsigned int*)(0x42621110UL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT1 *((volatile unsigned int*)(0x42621114UL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT2 *((volatile unsigned int*)(0x42621118UL)) -#define bFM3_INTREQ_IRQ29MON_ICU1INT3 *((volatile unsigned int*)(0x4262111CUL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT0 *((volatile unsigned int*)(0x42621180UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT1 *((volatile unsigned int*)(0x42621184UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT2 *((volatile unsigned int*)(0x42621188UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT3 *((volatile unsigned int*)(0x4262118CUL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT4 *((volatile unsigned int*)(0x42621190UL)) -#define bFM3_INTREQ_IRQ30MON_OCU0INT5 *((volatile unsigned int*)(0x42621194UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT0 *((volatile unsigned int*)(0x42621198UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT1 *((volatile unsigned int*)(0x4262119CUL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT2 *((volatile unsigned int*)(0x426211A0UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT3 *((volatile unsigned int*)(0x426211A4UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT4 *((volatile unsigned int*)(0x426211A8UL)) -#define bFM3_INTREQ_IRQ30MON_OCU1INT5 *((volatile unsigned int*)(0x426211ACUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT0 *((volatile unsigned int*)(0x42621200UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT1 *((volatile unsigned int*)(0x42621204UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT2 *((volatile unsigned int*)(0x42621208UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT3 *((volatile unsigned int*)(0x4262120CUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT4 *((volatile unsigned int*)(0x42621210UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT5 *((volatile unsigned int*)(0x42621214UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT6 *((volatile unsigned int*)(0x42621218UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT7 *((volatile unsigned int*)(0x4262121CUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT8 *((volatile unsigned int*)(0x42621220UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT9 *((volatile unsigned int*)(0x42621224UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT10 *((volatile unsigned int*)(0x42621228UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT11 *((volatile unsigned int*)(0x4262122CUL)) -#define bFM3_INTREQ_IRQ31MON_BTINT12 *((volatile unsigned int*)(0x42621230UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT13 *((volatile unsigned int*)(0x42621234UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT14 *((volatile unsigned int*)(0x42621238UL)) -#define bFM3_INTREQ_IRQ31MON_BTINT15 *((volatile unsigned int*)(0x4262123CUL)) -#define bFM3_INTREQ_IRQ32MON_CANINT *((volatile unsigned int*)(0x42621280UL)) -#define bFM3_INTREQ_IRQ33MON_CANINT *((volatile unsigned int*)(0x42621300UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT0 *((volatile unsigned int*)(0x42621380UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT1 *((volatile unsigned int*)(0x42621384UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT2 *((volatile unsigned int*)(0x42621388UL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT3 *((volatile unsigned int*)(0x4262138CUL)) -#define bFM3_INTREQ_IRQ34MON_USB0INT4 *((volatile unsigned int*)(0x42621390UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT0 *((volatile unsigned int*)(0x42621400UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT1 *((volatile unsigned int*)(0x42621404UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT2 *((volatile unsigned int*)(0x42621408UL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT3 *((volatile unsigned int*)(0x4262140CUL)) -#define bFM3_INTREQ_IRQ35MON_USB0INT4 *((volatile unsigned int*)(0x42621410UL)) -#define bFM3_INTREQ_IRQ38MON_DMAINT *((volatile unsigned int*)(0x42621580UL)) -#define bFM3_INTREQ_IRQ39MON_DMAINT *((volatile unsigned int*)(0x42621600UL)) -#define bFM3_INTREQ_IRQ40MON_DMAINT *((volatile unsigned int*)(0x42621680UL)) -#define bFM3_INTREQ_IRQ41MON_DMAINT *((volatile unsigned int*)(0x42621700UL)) -#define bFM3_INTREQ_IRQ42MON_DMAINT *((volatile unsigned int*)(0x42621780UL)) -#define bFM3_INTREQ_IRQ43MON_DMAINT *((volatile unsigned int*)(0x42621800UL)) -#define bFM3_INTREQ_IRQ44MON_DMAINT *((volatile unsigned int*)(0x42621880UL)) -#define bFM3_INTREQ_IRQ45MON_DMAINT *((volatile unsigned int*)(0x42621900UL)) - -/* General purpose I/O registers */ -#define bFM3_GPIO_PFR0_P0 *((volatile unsigned int*)(0x42660000UL)) -#define bFM3_GPIO_PFR0_P1 *((volatile unsigned int*)(0x42660004UL)) -#define bFM3_GPIO_PFR0_P2 *((volatile unsigned int*)(0x42660008UL)) -#define bFM3_GPIO_PFR0_P3 *((volatile unsigned int*)(0x4266000CUL)) -#define bFM3_GPIO_PFR0_P4 *((volatile unsigned int*)(0x42660010UL)) -#define bFM3_GPIO_PFR0_P5 *((volatile unsigned int*)(0x42660014UL)) -#define bFM3_GPIO_PFR0_P6 *((volatile unsigned int*)(0x42660018UL)) -#define bFM3_GPIO_PFR0_P7 *((volatile unsigned int*)(0x4266001CUL)) -#define bFM3_GPIO_PFR0_P8 *((volatile unsigned int*)(0x42660020UL)) -#define bFM3_GPIO_PFR0_P9 *((volatile unsigned int*)(0x42660024UL)) -#define bFM3_GPIO_PFR0_PA *((volatile unsigned int*)(0x42660028UL)) -#define bFM3_GPIO_PFR0_PB *((volatile unsigned int*)(0x4266002CUL)) -#define bFM3_GPIO_PFR0_PC *((volatile unsigned int*)(0x42660030UL)) -#define bFM3_GPIO_PFR0_PD *((volatile unsigned int*)(0x42660034UL)) -#define bFM3_GPIO_PFR0_PE *((volatile unsigned int*)(0x42660038UL)) -#define bFM3_GPIO_PFR0_PF *((volatile unsigned int*)(0x4266003CUL)) -#define bFM3_GPIO_PFR1_P0 *((volatile unsigned int*)(0x42660080UL)) -#define bFM3_GPIO_PFR1_P1 *((volatile unsigned int*)(0x42660084UL)) -#define bFM3_GPIO_PFR1_P2 *((volatile unsigned int*)(0x42660088UL)) -#define bFM3_GPIO_PFR1_P3 *((volatile unsigned int*)(0x4266008CUL)) -#define bFM3_GPIO_PFR1_P4 *((volatile unsigned int*)(0x42660090UL)) -#define bFM3_GPIO_PFR1_P5 *((volatile unsigned int*)(0x42660094UL)) -#define bFM3_GPIO_PFR1_P6 *((volatile unsigned int*)(0x42660098UL)) -#define bFM3_GPIO_PFR1_P7 *((volatile unsigned int*)(0x4266009CUL)) -#define bFM3_GPIO_PFR1_P8 *((volatile unsigned int*)(0x426600A0UL)) -#define bFM3_GPIO_PFR1_P9 *((volatile unsigned int*)(0x426600A4UL)) -#define bFM3_GPIO_PFR1_PA *((volatile unsigned int*)(0x426600A8UL)) -#define bFM3_GPIO_PFR1_PB *((volatile unsigned int*)(0x426600ACUL)) -#define bFM3_GPIO_PFR1_PC *((volatile unsigned int*)(0x426600B0UL)) -#define bFM3_GPIO_PFR1_PD *((volatile unsigned int*)(0x426600B4UL)) -#define bFM3_GPIO_PFR1_PE *((volatile unsigned int*)(0x426600B8UL)) -#define bFM3_GPIO_PFR1_PF *((volatile unsigned int*)(0x426600BCUL)) -#define bFM3_GPIO_PFR2_P0 *((volatile unsigned int*)(0x42660100UL)) -#define bFM3_GPIO_PFR2_P1 *((volatile unsigned int*)(0x42660104UL)) -#define bFM3_GPIO_PFR2_P2 *((volatile unsigned int*)(0x42660108UL)) -#define bFM3_GPIO_PFR2_P3 *((volatile unsigned int*)(0x4266010CUL)) -#define bFM3_GPIO_PFR2_P4 *((volatile unsigned int*)(0x42660110UL)) -#define bFM3_GPIO_PFR2_P5 *((volatile unsigned int*)(0x42660114UL)) -#define bFM3_GPIO_PFR2_P6 *((volatile unsigned int*)(0x42660118UL)) -#define bFM3_GPIO_PFR2_P7 *((volatile unsigned int*)(0x4266011CUL)) -#define bFM3_GPIO_PFR2_P8 *((volatile unsigned int*)(0x42660120UL)) -#define bFM3_GPIO_PFR3_P0 *((volatile unsigned int*)(0x42660180UL)) -#define bFM3_GPIO_PFR3_P1 *((volatile unsigned int*)(0x42660184UL)) -#define bFM3_GPIO_PFR3_P2 *((volatile unsigned int*)(0x42660188UL)) -#define bFM3_GPIO_PFR3_P3 *((volatile unsigned int*)(0x4266018CUL)) -#define bFM3_GPIO_PFR3_P4 *((volatile unsigned int*)(0x42660190UL)) -#define bFM3_GPIO_PFR3_P5 *((volatile unsigned int*)(0x42660194UL)) -#define bFM3_GPIO_PFR3_P6 *((volatile unsigned int*)(0x42660198UL)) -#define bFM3_GPIO_PFR3_P7 *((volatile unsigned int*)(0x4266019CUL)) -#define bFM3_GPIO_PFR3_P8 *((volatile unsigned int*)(0x426601A0UL)) -#define bFM3_GPIO_PFR3_P9 *((volatile unsigned int*)(0x426601A4UL)) -#define bFM3_GPIO_PFR3_PA *((volatile unsigned int*)(0x426601A8UL)) -#define bFM3_GPIO_PFR3_PB *((volatile unsigned int*)(0x426601ACUL)) -#define bFM3_GPIO_PFR3_PC *((volatile unsigned int*)(0x426601B0UL)) -#define bFM3_GPIO_PFR3_PD *((volatile unsigned int*)(0x426601B4UL)) -#define bFM3_GPIO_PFR3_PE *((volatile unsigned int*)(0x426601B8UL)) -#define bFM3_GPIO_PFR3_PF *((volatile unsigned int*)(0x426601BCUL)) -#define bFM3_GPIO_PFR4_P0 *((volatile unsigned int*)(0x42660200UL)) -#define bFM3_GPIO_PFR4_P1 *((volatile unsigned int*)(0x42660204UL)) -#define bFM3_GPIO_PFR4_P2 *((volatile unsigned int*)(0x42660208UL)) -#define bFM3_GPIO_PFR4_P3 *((volatile unsigned int*)(0x4266020CUL)) -#define bFM3_GPIO_PFR4_P4 *((volatile unsigned int*)(0x42660210UL)) -#define bFM3_GPIO_PFR4_P5 *((volatile unsigned int*)(0x42660214UL)) -#define bFM3_GPIO_PFR4_P6 *((volatile unsigned int*)(0x42660218UL)) -#define bFM3_GPIO_PFR4_P7 *((volatile unsigned int*)(0x4266021CUL)) -#define bFM3_GPIO_PFR4_P8 *((volatile unsigned int*)(0x42660220UL)) -#define bFM3_GPIO_PFR4_P9 *((volatile unsigned int*)(0x42660224UL)) -#define bFM3_GPIO_PFR4_PA *((volatile unsigned int*)(0x42660228UL)) -#define bFM3_GPIO_PFR4_PB *((volatile unsigned int*)(0x4266022CUL)) -#define bFM3_GPIO_PFR4_PC *((volatile unsigned int*)(0x42660230UL)) -#define bFM3_GPIO_PFR4_PD *((volatile unsigned int*)(0x42660234UL)) -#define bFM3_GPIO_PFR4_PE *((volatile unsigned int*)(0x42660238UL)) -#define bFM3_GPIO_PFR5_P0 *((volatile unsigned int*)(0x42660280UL)) -#define bFM3_GPIO_PFR5_P1 *((volatile unsigned int*)(0x42660284UL)) -#define bFM3_GPIO_PFR5_P2 *((volatile unsigned int*)(0x42660288UL)) -#define bFM3_GPIO_PFR5_P3 *((volatile unsigned int*)(0x4266028CUL)) -#define bFM3_GPIO_PFR5_P4 *((volatile unsigned int*)(0x42660290UL)) -#define bFM3_GPIO_PFR5_P5 *((volatile unsigned int*)(0x42660294UL)) -#define bFM3_GPIO_PFR5_P6 *((volatile unsigned int*)(0x42660298UL)) -#define bFM3_GPIO_PFR5_P7 *((volatile unsigned int*)(0x4266029CUL)) -#define bFM3_GPIO_PFR5_P8 *((volatile unsigned int*)(0x426602A0UL)) -#define bFM3_GPIO_PFR5_P9 *((volatile unsigned int*)(0x426602A4UL)) -#define bFM3_GPIO_PFR5_PA *((volatile unsigned int*)(0x426602A8UL)) -#define bFM3_GPIO_PFR5_PB *((volatile unsigned int*)(0x426602ACUL)) -#define bFM3_GPIO_PFR6_P0 *((volatile unsigned int*)(0x42660300UL)) -#define bFM3_GPIO_PFR6_P1 *((volatile unsigned int*)(0x42660304UL)) -#define bFM3_GPIO_PFR6_P2 *((volatile unsigned int*)(0x42660308UL)) -#define bFM3_GPIO_PFR6_P3 *((volatile unsigned int*)(0x4266030CUL)) -#define bFM3_GPIO_PFR6_P4 *((volatile unsigned int*)(0x42660310UL)) -#define bFM3_GPIO_PFR6_P5 *((volatile unsigned int*)(0x42660314UL)) -#define bFM3_GPIO_PFR6_P6 *((volatile unsigned int*)(0x42660318UL)) -#define bFM3_GPIO_PFR6_P7 *((volatile unsigned int*)(0x4266031CUL)) -#define bFM3_GPIO_PFR6_P8 *((volatile unsigned int*)(0x42660320UL)) -#define bFM3_GPIO_PFR7_P0 *((volatile unsigned int*)(0x42660380UL)) -#define bFM3_GPIO_PFR7_P1 *((volatile unsigned int*)(0x42660384UL)) -#define bFM3_GPIO_PFR7_P2 *((volatile unsigned int*)(0x42660388UL)) -#define bFM3_GPIO_PFR7_P3 *((volatile unsigned int*)(0x4266038CUL)) -#define bFM3_GPIO_PFR7_P4 *((volatile unsigned int*)(0x42660390UL)) -#define bFM3_GPIO_PFR8_P0 *((volatile unsigned int*)(0x42660400UL)) -#define bFM3_GPIO_PFR8_P1 *((volatile unsigned int*)(0x42660404UL)) -#define bFM3_GPIO_PCR0_P0 *((volatile unsigned int*)(0x42662000UL)) -#define bFM3_GPIO_PCR0_P1 *((volatile unsigned int*)(0x42662004UL)) -#define bFM3_GPIO_PCR0_P2 *((volatile unsigned int*)(0x42662008UL)) -#define bFM3_GPIO_PCR0_P3 *((volatile unsigned int*)(0x4266200CUL)) -#define bFM3_GPIO_PCR0_P4 *((volatile unsigned int*)(0x42662010UL)) -#define bFM3_GPIO_PCR0_P5 *((volatile unsigned int*)(0x42662014UL)) -#define bFM3_GPIO_PCR0_P6 *((volatile unsigned int*)(0x42662018UL)) -#define bFM3_GPIO_PCR0_P7 *((volatile unsigned int*)(0x4266201CUL)) -#define bFM3_GPIO_PCR0_P8 *((volatile unsigned int*)(0x42662020UL)) -#define bFM3_GPIO_PCR0_P9 *((volatile unsigned int*)(0x42662024UL)) -#define bFM3_GPIO_PCR0_PA *((volatile unsigned int*)(0x42662028UL)) -#define bFM3_GPIO_PCR0_PB *((volatile unsigned int*)(0x4266202CUL)) -#define bFM3_GPIO_PCR0_PC *((volatile unsigned int*)(0x42662030UL)) -#define bFM3_GPIO_PCR0_PD *((volatile unsigned int*)(0x42662034UL)) -#define bFM3_GPIO_PCR0_PE *((volatile unsigned int*)(0x42662038UL)) -#define bFM3_GPIO_PCR0_PF *((volatile unsigned int*)(0x4266203CUL)) -#define bFM3_GPIO_PCR1_P0 *((volatile unsigned int*)(0x42662080UL)) -#define bFM3_GPIO_PCR1_P1 *((volatile unsigned int*)(0x42662084UL)) -#define bFM3_GPIO_PCR1_P2 *((volatile unsigned int*)(0x42662088UL)) -#define bFM3_GPIO_PCR1_P3 *((volatile unsigned int*)(0x4266208CUL)) -#define bFM3_GPIO_PCR1_P4 *((volatile unsigned int*)(0x42662090UL)) -#define bFM3_GPIO_PCR1_P5 *((volatile unsigned int*)(0x42662094UL)) -#define bFM3_GPIO_PCR1_P6 *((volatile unsigned int*)(0x42662098UL)) -#define bFM3_GPIO_PCR1_P7 *((volatile unsigned int*)(0x4266209CUL)) -#define bFM3_GPIO_PCR1_P8 *((volatile unsigned int*)(0x426620A0UL)) -#define bFM3_GPIO_PCR1_P9 *((volatile unsigned int*)(0x426620A4UL)) -#define bFM3_GPIO_PCR1_PA *((volatile unsigned int*)(0x426620A8UL)) -#define bFM3_GPIO_PCR1_PB *((volatile unsigned int*)(0x426620ACUL)) -#define bFM3_GPIO_PCR1_PC *((volatile unsigned int*)(0x426620B0UL)) -#define bFM3_GPIO_PCR1_PD *((volatile unsigned int*)(0x426620B4UL)) -#define bFM3_GPIO_PCR1_PE *((volatile unsigned int*)(0x426620B8UL)) -#define bFM3_GPIO_PCR1_PF *((volatile unsigned int*)(0x426620BCUL)) -#define bFM3_GPIO_PCR2_P0 *((volatile unsigned int*)(0x42662100UL)) -#define bFM3_GPIO_PCR2_P1 *((volatile unsigned int*)(0x42662104UL)) -#define bFM3_GPIO_PCR2_P2 *((volatile unsigned int*)(0x42662108UL)) -#define bFM3_GPIO_PCR2_P3 *((volatile unsigned int*)(0x4266210CUL)) -#define bFM3_GPIO_PCR2_P4 *((volatile unsigned int*)(0x42662110UL)) -#define bFM3_GPIO_PCR2_P5 *((volatile unsigned int*)(0x42662114UL)) -#define bFM3_GPIO_PCR2_P6 *((volatile unsigned int*)(0x42662118UL)) -#define bFM3_GPIO_PCR2_P7 *((volatile unsigned int*)(0x4266211CUL)) -#define bFM3_GPIO_PCR2_P8 *((volatile unsigned int*)(0x42662120UL)) -#define bFM3_GPIO_PCR3_P0 *((volatile unsigned int*)(0x42662180UL)) -#define bFM3_GPIO_PCR3_P1 *((volatile unsigned int*)(0x42662184UL)) -#define bFM3_GPIO_PCR3_P2 *((volatile unsigned int*)(0x42662188UL)) -#define bFM3_GPIO_PCR3_P3 *((volatile unsigned int*)(0x4266218CUL)) -#define bFM3_GPIO_PCR3_P4 *((volatile unsigned int*)(0x42662190UL)) -#define bFM3_GPIO_PCR3_P5 *((volatile unsigned int*)(0x42662194UL)) -#define bFM3_GPIO_PCR3_P6 *((volatile unsigned int*)(0x42662198UL)) -#define bFM3_GPIO_PCR3_P7 *((volatile unsigned int*)(0x4266219CUL)) -#define bFM3_GPIO_PCR3_P8 *((volatile unsigned int*)(0x426621A0UL)) -#define bFM3_GPIO_PCR3_P9 *((volatile unsigned int*)(0x426621A4UL)) -#define bFM3_GPIO_PCR3_PA *((volatile unsigned int*)(0x426621A8UL)) -#define bFM3_GPIO_PCR3_PB *((volatile unsigned int*)(0x426621ACUL)) -#define bFM3_GPIO_PCR3_PC *((volatile unsigned int*)(0x426621B0UL)) -#define bFM3_GPIO_PCR3_PD *((volatile unsigned int*)(0x426621B4UL)) -#define bFM3_GPIO_PCR3_PE *((volatile unsigned int*)(0x426621B8UL)) -#define bFM3_GPIO_PCR3_PF *((volatile unsigned int*)(0x426621BCUL)) -#define bFM3_GPIO_PCR4_P0 *((volatile unsigned int*)(0x42662200UL)) -#define bFM3_GPIO_PCR4_P1 *((volatile unsigned int*)(0x42662204UL)) -#define bFM3_GPIO_PCR4_P2 *((volatile unsigned int*)(0x42662208UL)) -#define bFM3_GPIO_PCR4_P3 *((volatile unsigned int*)(0x4266220CUL)) -#define bFM3_GPIO_PCR4_P4 *((volatile unsigned int*)(0x42662210UL)) -#define bFM3_GPIO_PCR4_P5 *((volatile unsigned int*)(0x42662214UL)) -#define bFM3_GPIO_PCR4_P6 *((volatile unsigned int*)(0x42662218UL)) -#define bFM3_GPIO_PCR4_P7 *((volatile unsigned int*)(0x4266221CUL)) -#define bFM3_GPIO_PCR4_P8 *((volatile unsigned int*)(0x42662220UL)) -#define bFM3_GPIO_PCR4_P9 *((volatile unsigned int*)(0x42662224UL)) -#define bFM3_GPIO_PCR4_PA *((volatile unsigned int*)(0x42662228UL)) -#define bFM3_GPIO_PCR4_PB *((volatile unsigned int*)(0x4266222CUL)) -#define bFM3_GPIO_PCR4_PC *((volatile unsigned int*)(0x42662230UL)) -#define bFM3_GPIO_PCR4_PD *((volatile unsigned int*)(0x42662234UL)) -#define bFM3_GPIO_PCR4_PE *((volatile unsigned int*)(0x42662238UL)) -#define bFM3_GPIO_PCR5_P0 *((volatile unsigned int*)(0x42662280UL)) -#define bFM3_GPIO_PCR5_P1 *((volatile unsigned int*)(0x42662284UL)) -#define bFM3_GPIO_PCR5_P2 *((volatile unsigned int*)(0x42662288UL)) -#define bFM3_GPIO_PCR5_P3 *((volatile unsigned int*)(0x4266228CUL)) -#define bFM3_GPIO_PCR5_P4 *((volatile unsigned int*)(0x42662290UL)) -#define bFM3_GPIO_PCR5_P5 *((volatile unsigned int*)(0x42662294UL)) -#define bFM3_GPIO_PCR5_P6 *((volatile unsigned int*)(0x42662298UL)) -#define bFM3_GPIO_PCR5_P7 *((volatile unsigned int*)(0x4266229CUL)) -#define bFM3_GPIO_PCR5_P8 *((volatile unsigned int*)(0x426622A0UL)) -#define bFM3_GPIO_PCR5_P9 *((volatile unsigned int*)(0x426622A4UL)) -#define bFM3_GPIO_PCR5_PA *((volatile unsigned int*)(0x426622A8UL)) -#define bFM3_GPIO_PCR5_PB *((volatile unsigned int*)(0x426622ACUL)) -#define bFM3_GPIO_PCR6_P0 *((volatile unsigned int*)(0x42662300UL)) -#define bFM3_GPIO_PCR6_P1 *((volatile unsigned int*)(0x42662304UL)) -#define bFM3_GPIO_PCR6_P2 *((volatile unsigned int*)(0x42662308UL)) -#define bFM3_GPIO_PCR6_P3 *((volatile unsigned int*)(0x4266230CUL)) -#define bFM3_GPIO_PCR6_P4 *((volatile unsigned int*)(0x42662310UL)) -#define bFM3_GPIO_PCR6_P5 *((volatile unsigned int*)(0x42662314UL)) -#define bFM3_GPIO_PCR6_P6 *((volatile unsigned int*)(0x42662318UL)) -#define bFM3_GPIO_PCR6_P7 *((volatile unsigned int*)(0x4266231CUL)) -#define bFM3_GPIO_PCR6_P8 *((volatile unsigned int*)(0x42662320UL)) -#define bFM3_GPIO_PCR7_P0 *((volatile unsigned int*)(0x42662380UL)) -#define bFM3_GPIO_PCR7_P1 *((volatile unsigned int*)(0x42662384UL)) -#define bFM3_GPIO_PCR7_P2 *((volatile unsigned int*)(0x42662388UL)) -#define bFM3_GPIO_PCR7_P3 *((volatile unsigned int*)(0x4266238CUL)) -#define bFM3_GPIO_PCR7_P4 *((volatile unsigned int*)(0x42662390UL)) -#define bFM3_GPIO_DDR0_P0 *((volatile unsigned int*)(0x42664000UL)) -#define bFM3_GPIO_DDR0_P1 *((volatile unsigned int*)(0x42664004UL)) -#define bFM3_GPIO_DDR0_P2 *((volatile unsigned int*)(0x42664008UL)) -#define bFM3_GPIO_DDR0_P3 *((volatile unsigned int*)(0x4266400CUL)) -#define bFM3_GPIO_DDR0_P4 *((volatile unsigned int*)(0x42664010UL)) -#define bFM3_GPIO_DDR0_P5 *((volatile unsigned int*)(0x42664014UL)) -#define bFM3_GPIO_DDR0_P6 *((volatile unsigned int*)(0x42664018UL)) -#define bFM3_GPIO_DDR0_P7 *((volatile unsigned int*)(0x4266401CUL)) -#define bFM3_GPIO_DDR0_P8 *((volatile unsigned int*)(0x42664020UL)) -#define bFM3_GPIO_DDR0_P9 *((volatile unsigned int*)(0x42664024UL)) -#define bFM3_GPIO_DDR0_PA *((volatile unsigned int*)(0x42664028UL)) -#define bFM3_GPIO_DDR0_PB *((volatile unsigned int*)(0x4266402CUL)) -#define bFM3_GPIO_DDR0_PC *((volatile unsigned int*)(0x42664030UL)) -#define bFM3_GPIO_DDR0_PD *((volatile unsigned int*)(0x42664034UL)) -#define bFM3_GPIO_DDR0_PE *((volatile unsigned int*)(0x42664038UL)) -#define bFM3_GPIO_DDR0_PF *((volatile unsigned int*)(0x4266403CUL)) -#define bFM3_GPIO_DDR1_P0 *((volatile unsigned int*)(0x42664080UL)) -#define bFM3_GPIO_DDR1_P1 *((volatile unsigned int*)(0x42664084UL)) -#define bFM3_GPIO_DDR1_P2 *((volatile unsigned int*)(0x42664088UL)) -#define bFM3_GPIO_DDR1_P3 *((volatile unsigned int*)(0x4266408CUL)) -#define bFM3_GPIO_DDR1_P4 *((volatile unsigned int*)(0x42664090UL)) -#define bFM3_GPIO_DDR1_P5 *((volatile unsigned int*)(0x42664094UL)) -#define bFM3_GPIO_DDR1_P6 *((volatile unsigned int*)(0x42664098UL)) -#define bFM3_GPIO_DDR1_P7 *((volatile unsigned int*)(0x4266409CUL)) -#define bFM3_GPIO_DDR1_P8 *((volatile unsigned int*)(0x426640A0UL)) -#define bFM3_GPIO_DDR1_P9 *((volatile unsigned int*)(0x426640A4UL)) -#define bFM3_GPIO_DDR1_PA *((volatile unsigned int*)(0x426640A8UL)) -#define bFM3_GPIO_DDR1_PB *((volatile unsigned int*)(0x426640ACUL)) -#define bFM3_GPIO_DDR1_PC *((volatile unsigned int*)(0x426640B0UL)) -#define bFM3_GPIO_DDR1_PD *((volatile unsigned int*)(0x426640B4UL)) -#define bFM3_GPIO_DDR1_PE *((volatile unsigned int*)(0x426640B8UL)) -#define bFM3_GPIO_DDR1_PF *((volatile unsigned int*)(0x426640BCUL)) -#define bFM3_GPIO_DDR2_P0 *((volatile unsigned int*)(0x42664100UL)) -#define bFM3_GPIO_DDR2_P1 *((volatile unsigned int*)(0x42664104UL)) -#define bFM3_GPIO_DDR2_P2 *((volatile unsigned int*)(0x42664108UL)) -#define bFM3_GPIO_DDR2_P3 *((volatile unsigned int*)(0x4266410CUL)) -#define bFM3_GPIO_DDR2_P4 *((volatile unsigned int*)(0x42664110UL)) -#define bFM3_GPIO_DDR2_P5 *((volatile unsigned int*)(0x42664114UL)) -#define bFM3_GPIO_DDR2_P6 *((volatile unsigned int*)(0x42664118UL)) -#define bFM3_GPIO_DDR2_P7 *((volatile unsigned int*)(0x4266411CUL)) -#define bFM3_GPIO_DDR2_P8 *((volatile unsigned int*)(0x42664120UL)) -#define bFM3_GPIO_DDR3_P0 *((volatile unsigned int*)(0x42664180UL)) -#define bFM3_GPIO_DDR3_P1 *((volatile unsigned int*)(0x42664184UL)) -#define bFM3_GPIO_DDR3_P2 *((volatile unsigned int*)(0x42664188UL)) -#define bFM3_GPIO_DDR3_P3 *((volatile unsigned int*)(0x4266418CUL)) -#define bFM3_GPIO_DDR3_P4 *((volatile unsigned int*)(0x42664190UL)) -#define bFM3_GPIO_DDR3_P5 *((volatile unsigned int*)(0x42664194UL)) -#define bFM3_GPIO_DDR3_P6 *((volatile unsigned int*)(0x42664198UL)) -#define bFM3_GPIO_DDR3_P7 *((volatile unsigned int*)(0x4266419CUL)) -#define bFM3_GPIO_DDR3_P8 *((volatile unsigned int*)(0x426641A0UL)) -#define bFM3_GPIO_DDR3_P9 *((volatile unsigned int*)(0x426641A4UL)) -#define bFM3_GPIO_DDR3_PA *((volatile unsigned int*)(0x426641A8UL)) -#define bFM3_GPIO_DDR3_PB *((volatile unsigned int*)(0x426641ACUL)) -#define bFM3_GPIO_DDR3_PC *((volatile unsigned int*)(0x426641B0UL)) -#define bFM3_GPIO_DDR3_PD *((volatile unsigned int*)(0x426641B4UL)) -#define bFM3_GPIO_DDR3_PE *((volatile unsigned int*)(0x426641B8UL)) -#define bFM3_GPIO_DDR3_PF *((volatile unsigned int*)(0x426641BCUL)) -#define bFM3_GPIO_DDR4_P0 *((volatile unsigned int*)(0x42664200UL)) -#define bFM3_GPIO_DDR4_P1 *((volatile unsigned int*)(0x42664204UL)) -#define bFM3_GPIO_DDR4_P2 *((volatile unsigned int*)(0x42664208UL)) -#define bFM3_GPIO_DDR4_P3 *((volatile unsigned int*)(0x4266420CUL)) -#define bFM3_GPIO_DDR4_P4 *((volatile unsigned int*)(0x42664210UL)) -#define bFM3_GPIO_DDR4_P5 *((volatile unsigned int*)(0x42664214UL)) -#define bFM3_GPIO_DDR4_P6 *((volatile unsigned int*)(0x42664218UL)) -#define bFM3_GPIO_DDR4_P7 *((volatile unsigned int*)(0x4266421CUL)) -#define bFM3_GPIO_DDR4_P8 *((volatile unsigned int*)(0x42664220UL)) -#define bFM3_GPIO_DDR4_P9 *((volatile unsigned int*)(0x42664224UL)) -#define bFM3_GPIO_DDR4_PA *((volatile unsigned int*)(0x42664228UL)) -#define bFM3_GPIO_DDR4_PB *((volatile unsigned int*)(0x4266422CUL)) -#define bFM3_GPIO_DDR4_PC *((volatile unsigned int*)(0x42664230UL)) -#define bFM3_GPIO_DDR4_PD *((volatile unsigned int*)(0x42664234UL)) -#define bFM3_GPIO_DDR4_PE *((volatile unsigned int*)(0x42664238UL)) -#define bFM3_GPIO_DDR5_P0 *((volatile unsigned int*)(0x42664280UL)) -#define bFM3_GPIO_DDR5_P1 *((volatile unsigned int*)(0x42664284UL)) -#define bFM3_GPIO_DDR5_P2 *((volatile unsigned int*)(0x42664288UL)) -#define bFM3_GPIO_DDR5_P3 *((volatile unsigned int*)(0x4266428CUL)) -#define bFM3_GPIO_DDR5_P4 *((volatile unsigned int*)(0x42664290UL)) -#define bFM3_GPIO_DDR5_P5 *((volatile unsigned int*)(0x42664294UL)) -#define bFM3_GPIO_DDR5_P6 *((volatile unsigned int*)(0x42664298UL)) -#define bFM3_GPIO_DDR5_P7 *((volatile unsigned int*)(0x4266429CUL)) -#define bFM3_GPIO_DDR5_P8 *((volatile unsigned int*)(0x426642A0UL)) -#define bFM3_GPIO_DDR5_P9 *((volatile unsigned int*)(0x426642A4UL)) -#define bFM3_GPIO_DDR5_PA *((volatile unsigned int*)(0x426642A8UL)) -#define bFM3_GPIO_DDR5_PB *((volatile unsigned int*)(0x426642ACUL)) -#define bFM3_GPIO_DDR6_P0 *((volatile unsigned int*)(0x42664300UL)) -#define bFM3_GPIO_DDR6_P1 *((volatile unsigned int*)(0x42664304UL)) -#define bFM3_GPIO_DDR6_P2 *((volatile unsigned int*)(0x42664308UL)) -#define bFM3_GPIO_DDR6_P3 *((volatile unsigned int*)(0x4266430CUL)) -#define bFM3_GPIO_DDR6_P4 *((volatile unsigned int*)(0x42664310UL)) -#define bFM3_GPIO_DDR6_P5 *((volatile unsigned int*)(0x42664314UL)) -#define bFM3_GPIO_DDR6_P6 *((volatile unsigned int*)(0x42664318UL)) -#define bFM3_GPIO_DDR6_P7 *((volatile unsigned int*)(0x4266431CUL)) -#define bFM3_GPIO_DDR6_P8 *((volatile unsigned int*)(0x42664320UL)) -#define bFM3_GPIO_DDR7_P0 *((volatile unsigned int*)(0x42664380UL)) -#define bFM3_GPIO_DDR7_P1 *((volatile unsigned int*)(0x42664384UL)) -#define bFM3_GPIO_DDR7_P2 *((volatile unsigned int*)(0x42664388UL)) -#define bFM3_GPIO_DDR7_P3 *((volatile unsigned int*)(0x4266438CUL)) -#define bFM3_GPIO_DDR7_P4 *((volatile unsigned int*)(0x42664390UL)) -#define bFM3_GPIO_DDR8_P0 *((volatile unsigned int*)(0x42664400UL)) -#define bFM3_GPIO_DDR8_P1 *((volatile unsigned int*)(0x42664404UL)) -#define bFM3_GPIO_PDIR0_P0 *((volatile unsigned int*)(0x42666000UL)) -#define bFM3_GPIO_PDIR0_P1 *((volatile unsigned int*)(0x42666004UL)) -#define bFM3_GPIO_PDIR0_P2 *((volatile unsigned int*)(0x42666008UL)) -#define bFM3_GPIO_PDIR0_P3 *((volatile unsigned int*)(0x4266600CUL)) -#define bFM3_GPIO_PDIR0_P4 *((volatile unsigned int*)(0x42666010UL)) -#define bFM3_GPIO_PDIR0_P5 *((volatile unsigned int*)(0x42666014UL)) -#define bFM3_GPIO_PDIR0_P6 *((volatile unsigned int*)(0x42666018UL)) -#define bFM3_GPIO_PDIR0_P7 *((volatile unsigned int*)(0x4266601CUL)) -#define bFM3_GPIO_PDIR0_P8 *((volatile unsigned int*)(0x42666020UL)) -#define bFM3_GPIO_PDIR0_P9 *((volatile unsigned int*)(0x42666024UL)) -#define bFM3_GPIO_PDIR0_PA *((volatile unsigned int*)(0x42666028UL)) -#define bFM3_GPIO_PDIR0_PB *((volatile unsigned int*)(0x4266602CUL)) -#define bFM3_GPIO_PDIR0_PC *((volatile unsigned int*)(0x42666030UL)) -#define bFM3_GPIO_PDIR0_PD *((volatile unsigned int*)(0x42666034UL)) -#define bFM3_GPIO_PDIR0_PE *((volatile unsigned int*)(0x42666038UL)) -#define bFM3_GPIO_PDIR0_PF *((volatile unsigned int*)(0x4266603CUL)) -#define bFM3_GPIO_PDIR1_P0 *((volatile unsigned int*)(0x42666080UL)) -#define bFM3_GPIO_PDIR1_P1 *((volatile unsigned int*)(0x42666084UL)) -#define bFM3_GPIO_PDIR1_P2 *((volatile unsigned int*)(0x42666088UL)) -#define bFM3_GPIO_PDIR1_P3 *((volatile unsigned int*)(0x4266608CUL)) -#define bFM3_GPIO_PDIR1_P4 *((volatile unsigned int*)(0x42666090UL)) -#define bFM3_GPIO_PDIR1_P5 *((volatile unsigned int*)(0x42666094UL)) -#define bFM3_GPIO_PDIR1_P6 *((volatile unsigned int*)(0x42666098UL)) -#define bFM3_GPIO_PDIR1_P7 *((volatile unsigned int*)(0x4266609CUL)) -#define bFM3_GPIO_PDIR1_P8 *((volatile unsigned int*)(0x426660A0UL)) -#define bFM3_GPIO_PDIR1_P9 *((volatile unsigned int*)(0x426660A4UL)) -#define bFM3_GPIO_PDIR1_PA *((volatile unsigned int*)(0x426660A8UL)) -#define bFM3_GPIO_PDIR1_PB *((volatile unsigned int*)(0x426660ACUL)) -#define bFM3_GPIO_PDIR1_PC *((volatile unsigned int*)(0x426660B0UL)) -#define bFM3_GPIO_PDIR1_PD *((volatile unsigned int*)(0x426660B4UL)) -#define bFM3_GPIO_PDIR1_PE *((volatile unsigned int*)(0x426660B8UL)) -#define bFM3_GPIO_PDIR1_PF *((volatile unsigned int*)(0x426660BCUL)) -#define bFM3_GPIO_PDIR2_P0 *((volatile unsigned int*)(0x42666100UL)) -#define bFM3_GPIO_PDIR2_P1 *((volatile unsigned int*)(0x42666104UL)) -#define bFM3_GPIO_PDIR2_P2 *((volatile unsigned int*)(0x42666108UL)) -#define bFM3_GPIO_PDIR2_P3 *((volatile unsigned int*)(0x4266610CUL)) -#define bFM3_GPIO_PDIR2_P4 *((volatile unsigned int*)(0x42666110UL)) -#define bFM3_GPIO_PDIR2_P5 *((volatile unsigned int*)(0x42666114UL)) -#define bFM3_GPIO_PDIR2_P6 *((volatile unsigned int*)(0x42666118UL)) -#define bFM3_GPIO_PDIR2_P7 *((volatile unsigned int*)(0x4266611CUL)) -#define bFM3_GPIO_PDIR2_P8 *((volatile unsigned int*)(0x42666120UL)) -#define bFM3_GPIO_PDIR3_P0 *((volatile unsigned int*)(0x42666180UL)) -#define bFM3_GPIO_PDIR3_P1 *((volatile unsigned int*)(0x42666184UL)) -#define bFM3_GPIO_PDIR3_P2 *((volatile unsigned int*)(0x42666188UL)) -#define bFM3_GPIO_PDIR3_P3 *((volatile unsigned int*)(0x4266618CUL)) -#define bFM3_GPIO_PDIR3_P4 *((volatile unsigned int*)(0x42666190UL)) -#define bFM3_GPIO_PDIR3_P5 *((volatile unsigned int*)(0x42666194UL)) -#define bFM3_GPIO_PDIR3_P6 *((volatile unsigned int*)(0x42666198UL)) -#define bFM3_GPIO_PDIR3_P7 *((volatile unsigned int*)(0x4266619CUL)) -#define bFM3_GPIO_PDIR3_P8 *((volatile unsigned int*)(0x426661A0UL)) -#define bFM3_GPIO_PDIR3_P9 *((volatile unsigned int*)(0x426661A4UL)) -#define bFM3_GPIO_PDIR3_PA *((volatile unsigned int*)(0x426661A8UL)) -#define bFM3_GPIO_PDIR3_PB *((volatile unsigned int*)(0x426661ACUL)) -#define bFM3_GPIO_PDIR3_PC *((volatile unsigned int*)(0x426661B0UL)) -#define bFM3_GPIO_PDIR3_PD *((volatile unsigned int*)(0x426661B4UL)) -#define bFM3_GPIO_PDIR3_PE *((volatile unsigned int*)(0x426661B8UL)) -#define bFM3_GPIO_PDIR3_PF *((volatile unsigned int*)(0x426661BCUL)) -#define bFM3_GPIO_PDIR4_P0 *((volatile unsigned int*)(0x42666200UL)) -#define bFM3_GPIO_PDIR4_P1 *((volatile unsigned int*)(0x42666204UL)) -#define bFM3_GPIO_PDIR4_P2 *((volatile unsigned int*)(0x42666208UL)) -#define bFM3_GPIO_PDIR4_P3 *((volatile unsigned int*)(0x4266620CUL)) -#define bFM3_GPIO_PDIR4_P4 *((volatile unsigned int*)(0x42666210UL)) -#define bFM3_GPIO_PDIR4_P5 *((volatile unsigned int*)(0x42666214UL)) -#define bFM3_GPIO_PDIR4_P6 *((volatile unsigned int*)(0x42666218UL)) -#define bFM3_GPIO_PDIR4_P7 *((volatile unsigned int*)(0x4266621CUL)) -#define bFM3_GPIO_PDIR4_P8 *((volatile unsigned int*)(0x42666220UL)) -#define bFM3_GPIO_PDIR4_P9 *((volatile unsigned int*)(0x42666224UL)) -#define bFM3_GPIO_PDIR4_PA *((volatile unsigned int*)(0x42666228UL)) -#define bFM3_GPIO_PDIR4_PB *((volatile unsigned int*)(0x4266622CUL)) -#define bFM3_GPIO_PDIR4_PC *((volatile unsigned int*)(0x42666230UL)) -#define bFM3_GPIO_PDIR4_PD *((volatile unsigned int*)(0x42666234UL)) -#define bFM3_GPIO_PDIR4_PE *((volatile unsigned int*)(0x42666238UL)) -#define bFM3_GPIO_PDIR5_P0 *((volatile unsigned int*)(0x42666280UL)) -#define bFM3_GPIO_PDIR5_P1 *((volatile unsigned int*)(0x42666284UL)) -#define bFM3_GPIO_PDIR5_P2 *((volatile unsigned int*)(0x42666288UL)) -#define bFM3_GPIO_PDIR5_P3 *((volatile unsigned int*)(0x4266628CUL)) -#define bFM3_GPIO_PDIR5_P4 *((volatile unsigned int*)(0x42666290UL)) -#define bFM3_GPIO_PDIR5_P5 *((volatile unsigned int*)(0x42666294UL)) -#define bFM3_GPIO_PDIR5_P6 *((volatile unsigned int*)(0x42666298UL)) -#define bFM3_GPIO_PDIR5_P7 *((volatile unsigned int*)(0x4266629CUL)) -#define bFM3_GPIO_PDIR5_P8 *((volatile unsigned int*)(0x426662A0UL)) -#define bFM3_GPIO_PDIR5_P9 *((volatile unsigned int*)(0x426662A4UL)) -#define bFM3_GPIO_PDIR5_PA *((volatile unsigned int*)(0x426662A8UL)) -#define bFM3_GPIO_PDIR5_PB *((volatile unsigned int*)(0x426662ACUL)) -#define bFM3_GPIO_PDIR6_P0 *((volatile unsigned int*)(0x42666300UL)) -#define bFM3_GPIO_PDIR6_P1 *((volatile unsigned int*)(0x42666304UL)) -#define bFM3_GPIO_PDIR6_P2 *((volatile unsigned int*)(0x42666308UL)) -#define bFM3_GPIO_PDIR6_P3 *((volatile unsigned int*)(0x4266630CUL)) -#define bFM3_GPIO_PDIR6_P4 *((volatile unsigned int*)(0x42666310UL)) -#define bFM3_GPIO_PDIR6_P5 *((volatile unsigned int*)(0x42666314UL)) -#define bFM3_GPIO_PDIR6_P6 *((volatile unsigned int*)(0x42666318UL)) -#define bFM3_GPIO_PDIR6_P7 *((volatile unsigned int*)(0x4266631CUL)) -#define bFM3_GPIO_PDIR6_P8 *((volatile unsigned int*)(0x42666320UL)) -#define bFM3_GPIO_PDIR7_P0 *((volatile unsigned int*)(0x42666380UL)) -#define bFM3_GPIO_PDIR7_P1 *((volatile unsigned int*)(0x42666384UL)) -#define bFM3_GPIO_PDIR7_P2 *((volatile unsigned int*)(0x42666388UL)) -#define bFM3_GPIO_PDIR7_P3 *((volatile unsigned int*)(0x4266638CUL)) -#define bFM3_GPIO_PDIR7_P4 *((volatile unsigned int*)(0x42666390UL)) -#define bFM3_GPIO_PDIR8_P0 *((volatile unsigned int*)(0x42666400UL)) -#define bFM3_GPIO_PDIR8_P1 *((volatile unsigned int*)(0x42666404UL)) -#define bFM3_GPIO_PDOR0_P0 *((volatile unsigned int*)(0x42668000UL)) -#define bFM3_GPIO_PDOR0_P1 *((volatile unsigned int*)(0x42668004UL)) -#define bFM3_GPIO_PDOR0_P2 *((volatile unsigned int*)(0x42668008UL)) -#define bFM3_GPIO_PDOR0_P3 *((volatile unsigned int*)(0x4266800CUL)) -#define bFM3_GPIO_PDOR0_P4 *((volatile unsigned int*)(0x42668010UL)) -#define bFM3_GPIO_PDOR0_P5 *((volatile unsigned int*)(0x42668014UL)) -#define bFM3_GPIO_PDOR0_P6 *((volatile unsigned int*)(0x42668018UL)) -#define bFM3_GPIO_PDOR0_P7 *((volatile unsigned int*)(0x4266801CUL)) -#define bFM3_GPIO_PDOR0_P8 *((volatile unsigned int*)(0x42668020UL)) -#define bFM3_GPIO_PDOR0_P9 *((volatile unsigned int*)(0x42668024UL)) -#define bFM3_GPIO_PDOR0_PA *((volatile unsigned int*)(0x42668028UL)) -#define bFM3_GPIO_PDOR0_PB *((volatile unsigned int*)(0x4266802CUL)) -#define bFM3_GPIO_PDOR0_PC *((volatile unsigned int*)(0x42668030UL)) -#define bFM3_GPIO_PDOR0_PD *((volatile unsigned int*)(0x42668034UL)) -#define bFM3_GPIO_PDOR0_PE *((volatile unsigned int*)(0x42668038UL)) -#define bFM3_GPIO_PDOR0_PF *((volatile unsigned int*)(0x4266803CUL)) -#define bFM3_GPIO_PDOR1_P0 *((volatile unsigned int*)(0x42668080UL)) -#define bFM3_GPIO_PDOR1_P1 *((volatile unsigned int*)(0x42668084UL)) -#define bFM3_GPIO_PDOR1_P2 *((volatile unsigned int*)(0x42668088UL)) -#define bFM3_GPIO_PDOR1_P3 *((volatile unsigned int*)(0x4266808CUL)) -#define bFM3_GPIO_PDOR1_P4 *((volatile unsigned int*)(0x42668090UL)) -#define bFM3_GPIO_PDOR1_P5 *((volatile unsigned int*)(0x42668094UL)) -#define bFM3_GPIO_PDOR1_P6 *((volatile unsigned int*)(0x42668098UL)) -#define bFM3_GPIO_PDOR1_P7 *((volatile unsigned int*)(0x4266809CUL)) -#define bFM3_GPIO_PDOR1_P8 *((volatile unsigned int*)(0x426680A0UL)) -#define bFM3_GPIO_PDOR1_P9 *((volatile unsigned int*)(0x426680A4UL)) -#define bFM3_GPIO_PDOR1_PA *((volatile unsigned int*)(0x426680A8UL)) -#define bFM3_GPIO_PDOR1_PB *((volatile unsigned int*)(0x426680ACUL)) -#define bFM3_GPIO_PDOR1_PC *((volatile unsigned int*)(0x426680B0UL)) -#define bFM3_GPIO_PDOR1_PD *((volatile unsigned int*)(0x426680B4UL)) -#define bFM3_GPIO_PDOR1_PE *((volatile unsigned int*)(0x426680B8UL)) -#define bFM3_GPIO_PDOR1_PF *((volatile unsigned int*)(0x426680BCUL)) -#define bFM3_GPIO_PDOR2_P0 *((volatile unsigned int*)(0x42668100UL)) -#define bFM3_GPIO_PDOR2_P1 *((volatile unsigned int*)(0x42668104UL)) -#define bFM3_GPIO_PDOR2_P2 *((volatile unsigned int*)(0x42668108UL)) -#define bFM3_GPIO_PDOR2_P3 *((volatile unsigned int*)(0x4266810CUL)) -#define bFM3_GPIO_PDOR2_P4 *((volatile unsigned int*)(0x42668110UL)) -#define bFM3_GPIO_PDOR2_P5 *((volatile unsigned int*)(0x42668114UL)) -#define bFM3_GPIO_PDOR2_P6 *((volatile unsigned int*)(0x42668118UL)) -#define bFM3_GPIO_PDOR2_P7 *((volatile unsigned int*)(0x4266811CUL)) -#define bFM3_GPIO_PDOR2_P8 *((volatile unsigned int*)(0x42668120UL)) -#define bFM3_GPIO_PDOR3_P0 *((volatile unsigned int*)(0x42668180UL)) -#define bFM3_GPIO_PDOR3_P1 *((volatile unsigned int*)(0x42668184UL)) -#define bFM3_GPIO_PDOR3_P2 *((volatile unsigned int*)(0x42668188UL)) -#define bFM3_GPIO_PDOR3_P3 *((volatile unsigned int*)(0x4266818CUL)) -#define bFM3_GPIO_PDOR3_P4 *((volatile unsigned int*)(0x42668190UL)) -#define bFM3_GPIO_PDOR3_P5 *((volatile unsigned int*)(0x42668194UL)) -#define bFM3_GPIO_PDOR3_P6 *((volatile unsigned int*)(0x42668198UL)) -#define bFM3_GPIO_PDOR3_P7 *((volatile unsigned int*)(0x4266819CUL)) -#define bFM3_GPIO_PDOR3_P8 *((volatile unsigned int*)(0x426681A0UL)) -#define bFM3_GPIO_PDOR3_P9 *((volatile unsigned int*)(0x426681A4UL)) -#define bFM3_GPIO_PDOR3_PA *((volatile unsigned int*)(0x426681A8UL)) -#define bFM3_GPIO_PDOR3_PB *((volatile unsigned int*)(0x426681ACUL)) -#define bFM3_GPIO_PDOR3_PC *((volatile unsigned int*)(0x426681B0UL)) -#define bFM3_GPIO_PDOR3_PD *((volatile unsigned int*)(0x426681B4UL)) -#define bFM3_GPIO_PDOR3_PE *((volatile unsigned int*)(0x426681B8UL)) -#define bFM3_GPIO_PDOR3_PF *((volatile unsigned int*)(0x426681BCUL)) -#define bFM3_GPIO_PDOR4_P0 *((volatile unsigned int*)(0x42668200UL)) -#define bFM3_GPIO_PDOR4_P1 *((volatile unsigned int*)(0x42668204UL)) -#define bFM3_GPIO_PDOR4_P2 *((volatile unsigned int*)(0x42668208UL)) -#define bFM3_GPIO_PDOR4_P3 *((volatile unsigned int*)(0x4266820CUL)) -#define bFM3_GPIO_PDOR4_P4 *((volatile unsigned int*)(0x42668210UL)) -#define bFM3_GPIO_PDOR4_P5 *((volatile unsigned int*)(0x42668214UL)) -#define bFM3_GPIO_PDOR4_P6 *((volatile unsigned int*)(0x42668218UL)) -#define bFM3_GPIO_PDOR4_P7 *((volatile unsigned int*)(0x4266821CUL)) -#define bFM3_GPIO_PDOR4_P8 *((volatile unsigned int*)(0x42668220UL)) -#define bFM3_GPIO_PDOR4_P9 *((volatile unsigned int*)(0x42668224UL)) -#define bFM3_GPIO_PDOR4_PA *((volatile unsigned int*)(0x42668228UL)) -#define bFM3_GPIO_PDOR4_PB *((volatile unsigned int*)(0x4266822CUL)) -#define bFM3_GPIO_PDOR4_PC *((volatile unsigned int*)(0x42668230UL)) -#define bFM3_GPIO_PDOR4_PD *((volatile unsigned int*)(0x42668234UL)) -#define bFM3_GPIO_PDOR4_PE *((volatile unsigned int*)(0x42668238UL)) -#define bFM3_GPIO_PDOR5_P0 *((volatile unsigned int*)(0x42668280UL)) -#define bFM3_GPIO_PDOR5_P1 *((volatile unsigned int*)(0x42668284UL)) -#define bFM3_GPIO_PDOR5_P2 *((volatile unsigned int*)(0x42668288UL)) -#define bFM3_GPIO_PDOR5_P3 *((volatile unsigned int*)(0x4266828CUL)) -#define bFM3_GPIO_PDOR5_P4 *((volatile unsigned int*)(0x42668290UL)) -#define bFM3_GPIO_PDOR5_P5 *((volatile unsigned int*)(0x42668294UL)) -#define bFM3_GPIO_PDOR5_P6 *((volatile unsigned int*)(0x42668298UL)) -#define bFM3_GPIO_PDOR5_P7 *((volatile unsigned int*)(0x4266829CUL)) -#define bFM3_GPIO_PDOR5_P8 *((volatile unsigned int*)(0x426682A0UL)) -#define bFM3_GPIO_PDOR5_P9 *((volatile unsigned int*)(0x426682A4UL)) -#define bFM3_GPIO_PDOR5_PA *((volatile unsigned int*)(0x426682A8UL)) -#define bFM3_GPIO_PDOR5_PB *((volatile unsigned int*)(0x426682ACUL)) -#define bFM3_GPIO_PDOR6_P0 *((volatile unsigned int*)(0x42668300UL)) -#define bFM3_GPIO_PDOR6_P1 *((volatile unsigned int*)(0x42668304UL)) -#define bFM3_GPIO_PDOR6_P2 *((volatile unsigned int*)(0x42668308UL)) -#define bFM3_GPIO_PDOR6_P3 *((volatile unsigned int*)(0x4266830CUL)) -#define bFM3_GPIO_PDOR6_P4 *((volatile unsigned int*)(0x42668310UL)) -#define bFM3_GPIO_PDOR6_P5 *((volatile unsigned int*)(0x42668314UL)) -#define bFM3_GPIO_PDOR6_P6 *((volatile unsigned int*)(0x42668318UL)) -#define bFM3_GPIO_PDOR6_P7 *((volatile unsigned int*)(0x4266831CUL)) -#define bFM3_GPIO_PDOR6_P8 *((volatile unsigned int*)(0x42668320UL)) -#define bFM3_GPIO_PDOR7_P0 *((volatile unsigned int*)(0x42668380UL)) -#define bFM3_GPIO_PDOR7_P1 *((volatile unsigned int*)(0x42668384UL)) -#define bFM3_GPIO_PDOR7_P2 *((volatile unsigned int*)(0x42668388UL)) -#define bFM3_GPIO_PDOR7_P3 *((volatile unsigned int*)(0x4266838CUL)) -#define bFM3_GPIO_PDOR7_P4 *((volatile unsigned int*)(0x42668390UL)) -#define bFM3_GPIO_PDOR8_P0 *((volatile unsigned int*)(0x42668400UL)) -#define bFM3_GPIO_PDOR8_P1 *((volatile unsigned int*)(0x42668404UL)) -#define bFM3_GPIO_ADE_AN0 *((volatile unsigned int*)(0x4266A000UL)) -#define bFM3_GPIO_ADE_AN1 *((volatile unsigned int*)(0x4266A004UL)) -#define bFM3_GPIO_ADE_AN2 *((volatile unsigned int*)(0x4266A008UL)) -#define bFM3_GPIO_ADE_AN3 *((volatile unsigned int*)(0x4266A00CUL)) -#define bFM3_GPIO_ADE_AN4 *((volatile unsigned int*)(0x4266A010UL)) -#define bFM3_GPIO_ADE_AN5 *((volatile unsigned int*)(0x4266A014UL)) -#define bFM3_GPIO_ADE_AN6 *((volatile unsigned int*)(0x4266A018UL)) -#define bFM3_GPIO_ADE_AN7 *((volatile unsigned int*)(0x4266A01CUL)) -#define bFM3_GPIO_ADE_AN8 *((volatile unsigned int*)(0x4266A020UL)) -#define bFM3_GPIO_ADE_AN9 *((volatile unsigned int*)(0x4266A024UL)) -#define bFM3_GPIO_ADE_ANA *((volatile unsigned int*)(0x4266A028UL)) -#define bFM3_GPIO_ADE_ANB *((volatile unsigned int*)(0x4266A02CUL)) -#define bFM3_GPIO_ADE_ANC *((volatile unsigned int*)(0x4266A030UL)) -#define bFM3_GPIO_ADE_AND *((volatile unsigned int*)(0x4266A034UL)) -#define bFM3_GPIO_ADE_ANE *((volatile unsigned int*)(0x4266A038UL)) -#define bFM3_GPIO_ADE_ANF *((volatile unsigned int*)(0x4266A03CUL)) -#define bFM3_GPIO_SPSR_SUBXC *((volatile unsigned int*)(0x4266B000UL)) -#define bFM3_GPIO_SPSR_USB0C *((volatile unsigned int*)(0x4266B010UL)) -#define bFM3_GPIO_EPFR00_NMIS *((volatile unsigned int*)(0x4266C000UL)) -#define bFM3_GPIO_EPFR00_CROUTE *((volatile unsigned int*)(0x4266C004UL)) -#define bFM3_GPIO_EPFR00_USB0PE *((volatile unsigned int*)(0x4266C024UL)) -#define bFM3_GPIO_EPFR00_JTAGEN0B *((volatile unsigned int*)(0x4266C040UL)) -#define bFM3_GPIO_EPFR00_JTAGEN1S *((volatile unsigned int*)(0x4266C044UL)) -#define bFM3_GPIO_EPFR00_TRC0E *((volatile unsigned int*)(0x4266C060UL)) -#define bFM3_GPIO_EPFR00_TRC1E *((volatile unsigned int*)(0x4266C064UL)) -#define bFM3_GPIO_EPFR01_RTO00E0 *((volatile unsigned int*)(0x4266C080UL)) -#define bFM3_GPIO_EPFR01_RTO00E1 *((volatile unsigned int*)(0x4266C084UL)) -#define bFM3_GPIO_EPFR01_RTO01E0 *((volatile unsigned int*)(0x4266C088UL)) -#define bFM3_GPIO_EPFR01_RTO01E1 *((volatile unsigned int*)(0x4266C08CUL)) -#define bFM3_GPIO_EPFR01_RTO02E0 *((volatile unsigned int*)(0x4266C090UL)) -#define bFM3_GPIO_EPFR01_RTO02E1 *((volatile unsigned int*)(0x4266C094UL)) -#define bFM3_GPIO_EPFR01_RTO03E0 *((volatile unsigned int*)(0x4266C098UL)) -#define bFM3_GPIO_EPFR01_RTO03E1 *((volatile unsigned int*)(0x4266C09CUL)) -#define bFM3_GPIO_EPFR01_RTO04E0 *((volatile unsigned int*)(0x4266C0A0UL)) -#define bFM3_GPIO_EPFR01_RTO04E1 *((volatile unsigned int*)(0x4266C0A4UL)) -#define bFM3_GPIO_EPFR01_RTO05E0 *((volatile unsigned int*)(0x4266C0A8UL)) -#define bFM3_GPIO_EPFR01_RTO05E1 *((volatile unsigned int*)(0x4266C0ACUL)) -#define bFM3_GPIO_EPFR01_DTTI0C *((volatile unsigned int*)(0x4266C0B0UL)) -#define bFM3_GPIO_EPFR01_DTTI0S0 *((volatile unsigned int*)(0x4266C0C0UL)) -#define bFM3_GPIO_EPFR01_DTTI0S1 *((volatile unsigned int*)(0x4266C0C4UL)) -#define bFM3_GPIO_EPFR01_FRCK0S0 *((volatile unsigned int*)(0x4266C0C8UL)) -#define bFM3_GPIO_EPFR01_FRCK0S1 *((volatile unsigned int*)(0x4266C0CCUL)) -#define bFM3_GPIO_EPFR01_IC00S0 *((volatile unsigned int*)(0x4266C0D0UL)) -#define bFM3_GPIO_EPFR01_IC00S1 *((volatile unsigned int*)(0x4266C0D4UL)) -#define bFM3_GPIO_EPFR01_IC00S2 *((volatile unsigned int*)(0x4266C0D8UL)) -#define bFM3_GPIO_EPFR01_IC01S0 *((volatile unsigned int*)(0x4266C0DCUL)) -#define bFM3_GPIO_EPFR01_IC01S1 *((volatile unsigned int*)(0x4266C0E0UL)) -#define bFM3_GPIO_EPFR01_IC01S2 *((volatile unsigned int*)(0x4266C0E4UL)) -#define bFM3_GPIO_EPFR01_IC02S0 *((volatile unsigned int*)(0x4266C0E8UL)) -#define bFM3_GPIO_EPFR01_IC02S1 *((volatile unsigned int*)(0x4266C0ECUL)) -#define bFM3_GPIO_EPFR01_IC02S2 *((volatile unsigned int*)(0x4266C0F0UL)) -#define bFM3_GPIO_EPFR01_IC03S0 *((volatile unsigned int*)(0x4266C0F4UL)) -#define bFM3_GPIO_EPFR01_IC03S1 *((volatile unsigned int*)(0x4266C0F8UL)) -#define bFM3_GPIO_EPFR01_IC03S2 *((volatile unsigned int*)(0x4266C0FCUL)) -#define bFM3_GPIO_EPFR02_RTO10E0 *((volatile unsigned int*)(0x4266C100UL)) -#define bFM3_GPIO_EPFR02_RTO10E1 *((volatile unsigned int*)(0x4266C104UL)) -#define bFM3_GPIO_EPFR02_RTO11E0 *((volatile unsigned int*)(0x4266C108UL)) -#define bFM3_GPIO_EPFR02_RTO11E1 *((volatile unsigned int*)(0x4266C10CUL)) -#define bFM3_GPIO_EPFR02_RTO12E0 *((volatile unsigned int*)(0x4266C110UL)) -#define bFM3_GPIO_EPFR02_RTO12E1 *((volatile unsigned int*)(0x4266C114UL)) -#define bFM3_GPIO_EPFR02_RTO13E0 *((volatile unsigned int*)(0x4266C118UL)) -#define bFM3_GPIO_EPFR02_RTO13E1 *((volatile unsigned int*)(0x4266C11CUL)) -#define bFM3_GPIO_EPFR02_RTO14E0 *((volatile unsigned int*)(0x4266C120UL)) -#define bFM3_GPIO_EPFR02_RTO14E1 *((volatile unsigned int*)(0x4266C124UL)) -#define bFM3_GPIO_EPFR02_RTO15E0 *((volatile unsigned int*)(0x4266C128UL)) -#define bFM3_GPIO_EPFR02_RTO15E1 *((volatile unsigned int*)(0x4266C12CUL)) -#define bFM3_GPIO_EPFR02_DTTI1C *((volatile unsigned int*)(0x4266C130UL)) -#define bFM3_GPIO_EPFR02_DTTI1S0 *((volatile unsigned int*)(0x4266C140UL)) -#define bFM3_GPIO_EPFR02_DTTI1S1 *((volatile unsigned int*)(0x4266C144UL)) -#define bFM3_GPIO_EPFR02_FRCK1S0 *((volatile unsigned int*)(0x4266C148UL)) -#define bFM3_GPIO_EPFR02_FRCK1S1 *((volatile unsigned int*)(0x4266C14CUL)) -#define bFM3_GPIO_EPFR02_IC10S0 *((volatile unsigned int*)(0x4266C150UL)) -#define bFM3_GPIO_EPFR02_IC10S1 *((volatile unsigned int*)(0x4266C154UL)) -#define bFM3_GPIO_EPFR02_IC10S2 *((volatile unsigned int*)(0x4266C158UL)) -#define bFM3_GPIO_EPFR02_IC11S0 *((volatile unsigned int*)(0x4266C15CUL)) -#define bFM3_GPIO_EPFR02_IC11S1 *((volatile unsigned int*)(0x4266C160UL)) -#define bFM3_GPIO_EPFR02_IC11S2 *((volatile unsigned int*)(0x4266C164UL)) -#define bFM3_GPIO_EPFR02_IC12S0 *((volatile unsigned int*)(0x4266C168UL)) -#define bFM3_GPIO_EPFR02_IC12S1 *((volatile unsigned int*)(0x4266C16CUL)) -#define bFM3_GPIO_EPFR02_IC12S2 *((volatile unsigned int*)(0x4266C170UL)) -#define bFM3_GPIO_EPFR02_IC13S0 *((volatile unsigned int*)(0x4266C174UL)) -#define bFM3_GPIO_EPFR02_IC13S1 *((volatile unsigned int*)(0x4266C178UL)) -#define bFM3_GPIO_EPFR02_IC13S2 *((volatile unsigned int*)(0x4266C17CUL)) -#define bFM3_GPIO_EPFR04_TIOA0E0 *((volatile unsigned int*)(0x4266C208UL)) -#define bFM3_GPIO_EPFR04_TIOA0E1 *((volatile unsigned int*)(0x4266C20CUL)) -#define bFM3_GPIO_EPFR04_TIOB0S0 *((volatile unsigned int*)(0x4266C210UL)) -#define bFM3_GPIO_EPFR04_TIOB0S1 *((volatile unsigned int*)(0x4266C214UL)) -#define bFM3_GPIO_EPFR04_TIOA1S0 *((volatile unsigned int*)(0x4266C220UL)) -#define bFM3_GPIO_EPFR04_TIOA1S1 *((volatile unsigned int*)(0x4266C224UL)) -#define bFM3_GPIO_EPFR04_TIOA1E0 *((volatile unsigned int*)(0x4266C228UL)) -#define bFM3_GPIO_EPFR04_TIOA1E1 *((volatile unsigned int*)(0x4266C22CUL)) -#define bFM3_GPIO_EPFR04_TIOB1S0 *((volatile unsigned int*)(0x4266C230UL)) -#define bFM3_GPIO_EPFR04_TIOB1S1 *((volatile unsigned int*)(0x4266C234UL)) -#define bFM3_GPIO_EPFR04_TIOA2E0 *((volatile unsigned int*)(0x4266C248UL)) -#define bFM3_GPIO_EPFR04_TIOA2E1 *((volatile unsigned int*)(0x4266C24CUL)) -#define bFM3_GPIO_EPFR04_TIOB2S0 *((volatile unsigned int*)(0x4266C250UL)) -#define bFM3_GPIO_EPFR04_TIOB2S1 *((volatile unsigned int*)(0x4266C254UL)) -#define bFM3_GPIO_EPFR04_TIOA3S0 *((volatile unsigned int*)(0x4266C260UL)) -#define bFM3_GPIO_EPFR04_TIOA3S1 *((volatile unsigned int*)(0x4266C264UL)) -#define bFM3_GPIO_EPFR04_TIOA3E0 *((volatile unsigned int*)(0x4266C268UL)) -#define bFM3_GPIO_EPFR04_TIOA3E1 *((volatile unsigned int*)(0x4266C26CUL)) -#define bFM3_GPIO_EPFR04_TIOB3S0 *((volatile unsigned int*)(0x4266C270UL)) -#define bFM3_GPIO_EPFR04_TIOB3S1 *((volatile unsigned int*)(0x4266C274UL)) -#define bFM3_GPIO_EPFR05_TIOA4E0 *((volatile unsigned int*)(0x4266C288UL)) -#define bFM3_GPIO_EPFR05_TIOA4E1 *((volatile unsigned int*)(0x4266C28CUL)) -#define bFM3_GPIO_EPFR05_TIOB4S0 *((volatile unsigned int*)(0x4266C290UL)) -#define bFM3_GPIO_EPFR05_TIOB4S1 *((volatile unsigned int*)(0x4266C294UL)) -#define bFM3_GPIO_EPFR05_TIOA5S0 *((volatile unsigned int*)(0x4266C2A0UL)) -#define bFM3_GPIO_EPFR05_TIOA5S1 *((volatile unsigned int*)(0x4266C2A4UL)) -#define bFM3_GPIO_EPFR05_TIOA5E0 *((volatile unsigned int*)(0x4266C2A8UL)) -#define bFM3_GPIO_EPFR05_TIOA5E1 *((volatile unsigned int*)(0x4266C2ACUL)) -#define bFM3_GPIO_EPFR05_TIOB5S0 *((volatile unsigned int*)(0x4266C2B0UL)) -#define bFM3_GPIO_EPFR05_TIOB5S1 *((volatile unsigned int*)(0x4266C2B4UL)) -#define bFM3_GPIO_EPFR05_TIOA6E0 *((volatile unsigned int*)(0x4266C2C8UL)) -#define bFM3_GPIO_EPFR05_TIOA6E1 *((volatile unsigned int*)(0x4266C2CCUL)) -#define bFM3_GPIO_EPFR05_TIOB6S0 *((volatile unsigned int*)(0x4266C2D0UL)) -#define bFM3_GPIO_EPFR05_TIOB6S1 *((volatile unsigned int*)(0x4266C2D4UL)) -#define bFM3_GPIO_EPFR05_TIOA7S0 *((volatile unsigned int*)(0x4266C2E0UL)) -#define bFM3_GPIO_EPFR05_TIOA7S1 *((volatile unsigned int*)(0x4266C2E4UL)) -#define bFM3_GPIO_EPFR05_TIOA7E0 *((volatile unsigned int*)(0x4266C2E8UL)) -#define bFM3_GPIO_EPFR05_TIOA7E1 *((volatile unsigned int*)(0x4266C2ECUL)) -#define bFM3_GPIO_EPFR05_TIOB7S0 *((volatile unsigned int*)(0x4266C2F0UL)) -#define bFM3_GPIO_EPFR05_TIOB7S1 *((volatile unsigned int*)(0x4266C2F4UL)) -#define bFM3_GPIO_EPFR06_EINT00S0 *((volatile unsigned int*)(0x4266C300UL)) -#define bFM3_GPIO_EPFR06_EINT00S1 *((volatile unsigned int*)(0x4266C304UL)) -#define bFM3_GPIO_EPFR06_EINT01S0 *((volatile unsigned int*)(0x4266C308UL)) -#define bFM3_GPIO_EPFR06_EINT01S1 *((volatile unsigned int*)(0x4266C30CUL)) -#define bFM3_GPIO_EPFR06_EINT02S0 *((volatile unsigned int*)(0x4266C310UL)) -#define bFM3_GPIO_EPFR06_EINT02S1 *((volatile unsigned int*)(0x4266C314UL)) -#define bFM3_GPIO_EPFR06_EINT03S0 *((volatile unsigned int*)(0x4266C318UL)) -#define bFM3_GPIO_EPFR06_EINT03S1 *((volatile unsigned int*)(0x4266C31CUL)) -#define bFM3_GPIO_EPFR06_EINT04S0 *((volatile unsigned int*)(0x4266C320UL)) -#define bFM3_GPIO_EPFR06_EINT04S1 *((volatile unsigned int*)(0x4266C324UL)) -#define bFM3_GPIO_EPFR06_EINT05S0 *((volatile unsigned int*)(0x4266C328UL)) -#define bFM3_GPIO_EPFR06_EINT05S1 *((volatile unsigned int*)(0x4266C32CUL)) -#define bFM3_GPIO_EPFR06_EINT06S0 *((volatile unsigned int*)(0x4266C330UL)) -#define bFM3_GPIO_EPFR06_EINT06S1 *((volatile unsigned int*)(0x4266C334UL)) -#define bFM3_GPIO_EPFR06_EINT07S0 *((volatile unsigned int*)(0x4266C338UL)) -#define bFM3_GPIO_EPFR06_EINT07S1 *((volatile unsigned int*)(0x4266C33CUL)) -#define bFM3_GPIO_EPFR06_EINT08S0 *((volatile unsigned int*)(0x4266C340UL)) -#define bFM3_GPIO_EPFR06_EINT08S1 *((volatile unsigned int*)(0x4266C344UL)) -#define bFM3_GPIO_EPFR06_EINT09S0 *((volatile unsigned int*)(0x4266C348UL)) -#define bFM3_GPIO_EPFR06_EINT09S1 *((volatile unsigned int*)(0x4266C34CUL)) -#define bFM3_GPIO_EPFR06_EINT10S0 *((volatile unsigned int*)(0x4266C350UL)) -#define bFM3_GPIO_EPFR06_EINT10S1 *((volatile unsigned int*)(0x4266C354UL)) -#define bFM3_GPIO_EPFR06_EINT11S0 *((volatile unsigned int*)(0x4266C358UL)) -#define bFM3_GPIO_EPFR06_EINT11S1 *((volatile unsigned int*)(0x4266C35CUL)) -#define bFM3_GPIO_EPFR06_EINT12S0 *((volatile unsigned int*)(0x4266C360UL)) -#define bFM3_GPIO_EPFR06_EINT12S1 *((volatile unsigned int*)(0x4266C364UL)) -#define bFM3_GPIO_EPFR06_EINT13S0 *((volatile unsigned int*)(0x4266C368UL)) -#define bFM3_GPIO_EPFR06_EINT13S1 *((volatile unsigned int*)(0x4266C36CUL)) -#define bFM3_GPIO_EPFR06_EINT14S0 *((volatile unsigned int*)(0x4266C370UL)) -#define bFM3_GPIO_EPFR06_EINT14S1 *((volatile unsigned int*)(0x4266C374UL)) -#define bFM3_GPIO_EPFR06_EINT15S0 *((volatile unsigned int*)(0x4266C378UL)) -#define bFM3_GPIO_EPFR06_EINT15S1 *((volatile unsigned int*)(0x4266C37CUL)) -#define bFM3_GPIO_EPFR07_SIN0S0 *((volatile unsigned int*)(0x4266C390UL)) -#define bFM3_GPIO_EPFR07_SIN0S1 *((volatile unsigned int*)(0x4266C394UL)) -#define bFM3_GPIO_EPFR07_SOT0B0 *((volatile unsigned int*)(0x4266C398UL)) -#define bFM3_GPIO_EPFR07_SOT0B1 *((volatile unsigned int*)(0x4266C39CUL)) -#define bFM3_GPIO_EPFR07_SCK0B0 *((volatile unsigned int*)(0x4266C3A0UL)) -#define bFM3_GPIO_EPFR07_SCK0B1 *((volatile unsigned int*)(0x4266C3A4UL)) -#define bFM3_GPIO_EPFR07_SIN1S0 *((volatile unsigned int*)(0x4266C3A8UL)) -#define bFM3_GPIO_EPFR07_SIN1S1 *((volatile unsigned int*)(0x4266C3ACUL)) -#define bFM3_GPIO_EPFR07_SOT1B0 *((volatile unsigned int*)(0x4266C3B0UL)) -#define bFM3_GPIO_EPFR07_SOT1B1 *((volatile unsigned int*)(0x4266C3B4UL)) -#define bFM3_GPIO_EPFR07_SCK1B0 *((volatile unsigned int*)(0x4266C3B8UL)) -#define bFM3_GPIO_EPFR07_SCK1B1 *((volatile unsigned int*)(0x4266C3BCUL)) -#define bFM3_GPIO_EPFR07_SIN2S0 *((volatile unsigned int*)(0x4266C3C0UL)) -#define bFM3_GPIO_EPFR07_SIN2S1 *((volatile unsigned int*)(0x4266C3C4UL)) -#define bFM3_GPIO_EPFR07_SOT2B0 *((volatile unsigned int*)(0x4266C3C8UL)) -#define bFM3_GPIO_EPFR07_SOT2B1 *((volatile unsigned int*)(0x4266C3CCUL)) -#define bFM3_GPIO_EPFR07_SCK2B0 *((volatile unsigned int*)(0x4266C3D0UL)) -#define bFM3_GPIO_EPFR07_SCK2B1 *((volatile unsigned int*)(0x4266C3D4UL)) -#define bFM3_GPIO_EPFR07_SIN3S0 *((volatile unsigned int*)(0x4266C3D8UL)) -#define bFM3_GPIO_EPFR07_SIN3S1 *((volatile unsigned int*)(0x4266C3DCUL)) -#define bFM3_GPIO_EPFR07_SOT3B0 *((volatile unsigned int*)(0x4266C3E0UL)) -#define bFM3_GPIO_EPFR07_SOT3B1 *((volatile unsigned int*)(0x4266C3E4UL)) -#define bFM3_GPIO_EPFR07_SCK3B0 *((volatile unsigned int*)(0x4266C3E8UL)) -#define bFM3_GPIO_EPFR07_SCK3B1 *((volatile unsigned int*)(0x4266C3ECUL)) -#define bFM3_GPIO_EPFR08_RTS4E0 *((volatile unsigned int*)(0x4266C400UL)) -#define bFM3_GPIO_EPFR08_RTS4E1 *((volatile unsigned int*)(0x4266C404UL)) -#define bFM3_GPIO_EPFR08_CTS4S0 *((volatile unsigned int*)(0x4266C408UL)) -#define bFM3_GPIO_EPFR08_CTS4S1 *((volatile unsigned int*)(0x4266C40CUL)) -#define bFM3_GPIO_EPFR08_SIN4S0 *((volatile unsigned int*)(0x4266C410UL)) -#define bFM3_GPIO_EPFR08_SIN4S1 *((volatile unsigned int*)(0x4266C414UL)) -#define bFM3_GPIO_EPFR08_SOT4B0 *((volatile unsigned int*)(0x4266C418UL)) -#define bFM3_GPIO_EPFR08_SOT4B1 *((volatile unsigned int*)(0x4266C41CUL)) -#define bFM3_GPIO_EPFR08_SCK4B0 *((volatile unsigned int*)(0x4266C420UL)) -#define bFM3_GPIO_EPFR08_SCK4B1 *((volatile unsigned int*)(0x4266C424UL)) -#define bFM3_GPIO_EPFR08_SIN5S0 *((volatile unsigned int*)(0x4266C428UL)) -#define bFM3_GPIO_EPFR08_SIN5S1 *((volatile unsigned int*)(0x4266C42CUL)) -#define bFM3_GPIO_EPFR08_SOT5B0 *((volatile unsigned int*)(0x4266C430UL)) -#define bFM3_GPIO_EPFR08_SOT5B1 *((volatile unsigned int*)(0x4266C434UL)) -#define bFM3_GPIO_EPFR08_SCK5B0 *((volatile unsigned int*)(0x4266C438UL)) -#define bFM3_GPIO_EPFR08_SCK5B1 *((volatile unsigned int*)(0x4266C43CUL)) -#define bFM3_GPIO_EPFR08_SIN6S0 *((volatile unsigned int*)(0x4266C440UL)) -#define bFM3_GPIO_EPFR08_SIN6S1 *((volatile unsigned int*)(0x4266C444UL)) -#define bFM3_GPIO_EPFR08_SOT6B0 *((volatile unsigned int*)(0x4266C448UL)) -#define bFM3_GPIO_EPFR08_SOT6B1 *((volatile unsigned int*)(0x4266C44CUL)) -#define bFM3_GPIO_EPFR08_SCK6B0 *((volatile unsigned int*)(0x4266C450UL)) -#define bFM3_GPIO_EPFR08_SCK6B1 *((volatile unsigned int*)(0x4266C454UL)) -#define bFM3_GPIO_EPFR08_SIN7S0 *((volatile unsigned int*)(0x4266C458UL)) -#define bFM3_GPIO_EPFR08_SIN7S1 *((volatile unsigned int*)(0x4266C45CUL)) -#define bFM3_GPIO_EPFR08_SOT7B0 *((volatile unsigned int*)(0x4266C460UL)) -#define bFM3_GPIO_EPFR08_SOT7B1 *((volatile unsigned int*)(0x4266C464UL)) -#define bFM3_GPIO_EPFR08_SCK7B0 *((volatile unsigned int*)(0x4266C468UL)) -#define bFM3_GPIO_EPFR08_SCK7B1 *((volatile unsigned int*)(0x4266C46CUL)) -#define bFM3_GPIO_EPFR09_QAIN0S0 *((volatile unsigned int*)(0x4266C480UL)) -#define bFM3_GPIO_EPFR09_QAIN0S1 *((volatile unsigned int*)(0x4266C484UL)) -#define bFM3_GPIO_EPFR09_QBIN0S0 *((volatile unsigned int*)(0x4266C488UL)) -#define bFM3_GPIO_EPFR09_QBIN0S1 *((volatile unsigned int*)(0x4266C48CUL)) -#define bFM3_GPIO_EPFR09_QZIN0S0 *((volatile unsigned int*)(0x4266C490UL)) -#define bFM3_GPIO_EPFR09_QZIN0S1 *((volatile unsigned int*)(0x4266C494UL)) -#define bFM3_GPIO_EPFR09_QAIN1S0 *((volatile unsigned int*)(0x4266C498UL)) -#define bFM3_GPIO_EPFR09_QAIN1S1 *((volatile unsigned int*)(0x4266C49CUL)) -#define bFM3_GPIO_EPFR09_QBIN1S0 *((volatile unsigned int*)(0x4266C4A0UL)) -#define bFM3_GPIO_EPFR09_QBIN1S1 *((volatile unsigned int*)(0x4266C4A4UL)) -#define bFM3_GPIO_EPFR09_QZIN1S0 *((volatile unsigned int*)(0x4266C4A8UL)) -#define bFM3_GPIO_EPFR09_QZIN1S1 *((volatile unsigned int*)(0x4266C4ACUL)) -#define bFM3_GPIO_EPFR09_ADTRG0S0 *((volatile unsigned int*)(0x4266C4B0UL)) -#define bFM3_GPIO_EPFR09_ADTRG0S1 *((volatile unsigned int*)(0x4266C4B4UL)) -#define bFM3_GPIO_EPFR09_ADTRG0S2 *((volatile unsigned int*)(0x4266C4B8UL)) -#define bFM3_GPIO_EPFR09_ADTRG0S3 *((volatile unsigned int*)(0x4266C4BCUL)) -#define bFM3_GPIO_EPFR09_ADTRG1S0 *((volatile unsigned int*)(0x4266C4C0UL)) -#define bFM3_GPIO_EPFR09_ADTRG1S1 *((volatile unsigned int*)(0x4266C4C4UL)) -#define bFM3_GPIO_EPFR09_ADTRG1S2 *((volatile unsigned int*)(0x4266C4C8UL)) -#define bFM3_GPIO_EPFR09_ADTRG1S3 *((volatile unsigned int*)(0x4266C4CCUL)) -#define bFM3_GPIO_EPFR09_ADTRG2S0 *((volatile unsigned int*)(0x4266C4D0UL)) -#define bFM3_GPIO_EPFR09_ADTRG2S1 *((volatile unsigned int*)(0x4266C4D4UL)) -#define bFM3_GPIO_EPFR09_ADTRG2S2 *((volatile unsigned int*)(0x4266C4D8UL)) -#define bFM3_GPIO_EPFR09_ADTRG2S3 *((volatile unsigned int*)(0x4266C4DCUL)) -#define bFM3_GPIO_EPFR09_CRX0S0 *((volatile unsigned int*)(0x4266C4E0UL)) -#define bFM3_GPIO_EPFR09_CRX0S1 *((volatile unsigned int*)(0x4266C4E4UL)) -#define bFM3_GPIO_EPFR09_CTX0E0 *((volatile unsigned int*)(0x4266C4E8UL)) -#define bFM3_GPIO_EPFR09_CTX0E1 *((volatile unsigned int*)(0x4266C4ECUL)) -#define bFM3_GPIO_EPFR09_CRX1S0 *((volatile unsigned int*)(0x4266C4F0UL)) -#define bFM3_GPIO_EPFR09_CRX1S1 *((volatile unsigned int*)(0x4266C4F4UL)) -#define bFM3_GPIO_EPFR09_CTX1E0 *((volatile unsigned int*)(0x4266C4F8UL)) -#define bFM3_GPIO_EPFR09_CTX1E1 *((volatile unsigned int*)(0x4266C4FCUL)) -#define bFM3_GPIO_EPFR10_UEDEFB *((volatile unsigned int*)(0x4266C500UL)) -#define bFM3_GPIO_EPFR10_UEDTHB *((volatile unsigned int*)(0x4266C504UL)) -#define bFM3_GPIO_EPFR10_TESTB *((volatile unsigned int*)(0x4266C508UL)) -#define bFM3_GPIO_EPFR10_UEWEXE *((volatile unsigned int*)(0x4266C50CUL)) -#define bFM3_GPIO_EPFR10_UEDQME *((volatile unsigned int*)(0x4266C510UL)) -#define bFM3_GPIO_EPFR10_UEOEXE *((volatile unsigned int*)(0x4266C514UL)) -#define bFM3_GPIO_EPFR10_UEFLSE *((volatile unsigned int*)(0x4266C518UL)) -#define bFM3_GPIO_EPFR10_UECS1E *((volatile unsigned int*)(0x4266C51CUL)) -#define bFM3_GPIO_EPFR10_UECS2E *((volatile unsigned int*)(0x4266C520UL)) -#define bFM3_GPIO_EPFR10_UECS3E *((volatile unsigned int*)(0x4266C524UL)) -#define bFM3_GPIO_EPFR10_UECS4E *((volatile unsigned int*)(0x4266C528UL)) -#define bFM3_GPIO_EPFR10_UECS5E *((volatile unsigned int*)(0x4266C52CUL)) -#define bFM3_GPIO_EPFR10_UECS6E *((volatile unsigned int*)(0x4266C530UL)) -#define bFM3_GPIO_EPFR10_UECS7E *((volatile unsigned int*)(0x4266C534UL)) -#define bFM3_GPIO_EPFR10_UEAOOE *((volatile unsigned int*)(0x4266C538UL)) -#define bFM3_GPIO_EPFR10_UEA08E *((volatile unsigned int*)(0x4266C53CUL)) -#define bFM3_GPIO_EPFR10_UEA09E *((volatile unsigned int*)(0x4266C540UL)) -#define bFM3_GPIO_EPFR10_UEA10E *((volatile unsigned int*)(0x4266C544UL)) -#define bFM3_GPIO_EPFR10_UEA11E *((volatile unsigned int*)(0x4266C548UL)) -#define bFM3_GPIO_EPFR10_UEA12E *((volatile unsigned int*)(0x4266C54CUL)) -#define bFM3_GPIO_EPFR10_UEA13E *((volatile unsigned int*)(0x4266C550UL)) -#define bFM3_GPIO_EPFR10_UEA14E *((volatile unsigned int*)(0x4266C554UL)) -#define bFM3_GPIO_EPFR10_UEA15E *((volatile unsigned int*)(0x4266C558UL)) -#define bFM3_GPIO_EPFR10_UEA16E *((volatile unsigned int*)(0x4266C55CUL)) -#define bFM3_GPIO_EPFR10_UEA17E *((volatile unsigned int*)(0x4266C560UL)) -#define bFM3_GPIO_EPFR10_UEA18E *((volatile unsigned int*)(0x4266C564UL)) -#define bFM3_GPIO_EPFR10_UEA19E *((volatile unsigned int*)(0x4266C568UL)) -#define bFM3_GPIO_EPFR10_UEA20E *((volatile unsigned int*)(0x4266C56CUL)) -#define bFM3_GPIO_EPFR10_UEA21E *((volatile unsigned int*)(0x4266C570UL)) -#define bFM3_GPIO_EPFR10_UEA22E *((volatile unsigned int*)(0x4266C574UL)) -#define bFM3_GPIO_EPFR10_UEA23E *((volatile unsigned int*)(0x4266C578UL)) -#define bFM3_GPIO_EPFR10_UEA24E *((volatile unsigned int*)(0x4266C57CUL)) - -/* Low voltage detection registers */ -#define bFM3_LVD_LVD_CTL_SVHI0 *((volatile unsigned int*)(0x426A0008UL)) -#define bFM3_LVD_LVD_CTL_SVHI1 *((volatile unsigned int*)(0x426A000CUL)) -#define bFM3_LVD_LVD_CTL_SVHI2 *((volatile unsigned int*)(0x426A0010UL)) -#define bFM3_LVD_LVD_CTL_SVHI3 *((volatile unsigned int*)(0x426A0014UL)) -#define bFM3_LVD_LVD_CTL_LVDIE *((volatile unsigned int*)(0x426A001CUL)) -#define bFM3_LVD_LVD_STR_LVDIR *((volatile unsigned int*)(0x426A009CUL)) -#define bFM3_LVD_LVD_CLR_LVDCL *((volatile unsigned int*)(0x426A011CUL)) -#define bFM3_LVD_LVD_STR2_LVDIRDY *((volatile unsigned int*)(0x426A021CUL)) - -/* USB clock registers */ -#define bFM3_USBCLK_UCCR_UCEN *((volatile unsigned int*)(0x426C0000UL)) -#define bFM3_USBCLK_UCCR_UCSEL *((volatile unsigned int*)(0x426C0004UL)) -#define bFM3_USBCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) -#define bFM3_USBCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) -#define bFM3_USBCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) -#define bFM3_USBCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) -#define bFM3_USBCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) -#define bFM3_USBCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) -#define bFM3_USBCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) -#define bFM3_USBCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) -#define bFM3_USBCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) -#define bFM3_USBCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) -#define bFM3_USBCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) -#define bFM3_USBCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) -#define bFM3_USBCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) -#define bFM3_USBCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) -#define bFM3_USBCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) -#define bFM3_USBCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) -#define bFM3_USBCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) -#define bFM3_USBCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) -#define bFM3_USBCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) -#define bFM3_USBCLK_USBEN_USBEN *((volatile unsigned int*)(0x426C0600UL)) - -/* CAN prescaler register */ -#define bFM3_CANPRES_CANPRE_CANPRE0 *((volatile unsigned int*)(0x426E0000UL)) -#define bFM3_CANPRES_CANPRE_CANPRE1 *((volatile unsigned int*)(0x426E0004UL)) -#define bFM3_CANPRES_CANPRE_CANPRE2 *((volatile unsigned int*)(0x426E0008UL)) -#define bFM3_CANPRES_CANPRE_CANPRE3 *((volatile unsigned int*)(0x426E000CUL)) - -/* UART asynchronous channel 0 registers */ -#define bFM3_MFS0_UART_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_UART_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) -#define bFM3_MFS0_UART_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_UART_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_UART_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM3_MFS0_UART_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM3_MFS0_UART_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM3_MFS0_UART_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_UART_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_UART_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_UART_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_UART_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_UART_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_UART_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_UART_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_UART_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_UART_ESCR_P *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_UART_ESCR_PEN *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_UART_ESCR_INV *((volatile unsigned int*)(0x42700094UL)) -#define bFM3_MFS0_UART_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) -#define bFM3_MFS0_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270009CUL)) -#define bFM3_MFS0_UART_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_UART_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_UART_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_UART_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_UART_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM3_MFS0_UART_SSR_PE *((volatile unsigned int*)(0x427000B4UL)) -#define bFM3_MFS0_UART_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM3_MFS0_UART_RDR_AD *((volatile unsigned int*)(0x42700120UL)) -#define bFM3_MFS0_UART_TDR_AD *((volatile unsigned int*)(0x42700120UL)) -#define bFM3_MFS0_UART_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) -#define bFM3_MFS0_UART_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) - -/* UART synchronous channel 0 registers */ -#define bFM3_MFS0_CSIO_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42700004UL)) -#define bFM3_MFS0_CSIO_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) -#define bFM3_MFS0_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM3_MFS0_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM3_MFS0_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM3_MFS0_CSIO_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_CSIO_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_CSIO_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_CSIO_SCR_SPI *((volatile unsigned int*)(0x42700034UL)) -#define bFM3_MFS0_CSIO_SCR_MS *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270009CUL)) -#define bFM3_MFS0_CSIO_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_CSIO_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_CSIO_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) - -/* UART LIN channel 0 registers */ -#define bFM3_MFS0_LIN_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_LIN_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_LIN_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_LIN_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM3_MFS0_LIN_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM3_MFS0_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM3_MFS0_LIN_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_LIN_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_LIN_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_LIN_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_LIN_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_LIN_SCR_LBR *((volatile unsigned int*)(0x42700034UL)) -#define bFM3_MFS0_LIN_SCR_MS *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) -#define bFM3_MFS0_LIN_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_LIN_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_LIN_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_LIN_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_LIN_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM3_MFS0_LIN_SSR_LBD *((volatile unsigned int*)(0x427000B4UL)) -#define bFM3_MFS0_LIN_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM3_MFS0_LIN_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) -#define bFM3_MFS0_LIN_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) - -/* I2C channel 0 registers */ -#define bFM3_MFS0_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42700000UL)) -#define bFM3_MFS0_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42700004UL)) -#define bFM3_MFS0_I2C_SMR_TIE *((volatile unsigned int*)(0x42700008UL)) -#define bFM3_MFS0_I2C_SMR_RIE *((volatile unsigned int*)(0x4270000CUL)) -#define bFM3_MFS0_I2C_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) -#define bFM3_MFS0_I2C_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) -#define bFM3_MFS0_I2C_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) -#define bFM3_MFS0_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) -#define bFM3_MFS0_I2C_IBCR_INT *((volatile unsigned int*)(0x42700020UL)) -#define bFM3_MFS0_I2C_IBCR_BER *((volatile unsigned int*)(0x42700024UL)) -#define bFM3_MFS0_I2C_IBCR_INTE *((volatile unsigned int*)(0x42700028UL)) -#define bFM3_MFS0_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270002CUL)) -#define bFM3_MFS0_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42700030UL)) -#define bFM3_MFS0_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42700034UL)) -#define bFM3_MFS0_I2C_IBCR_ACT *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_I2C_IBCR_SCC *((volatile unsigned int*)(0x42700038UL)) -#define bFM3_MFS0_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270003CUL)) -#define bFM3_MFS0_I2C_IBSR_BB *((volatile unsigned int*)(0x42700080UL)) -#define bFM3_MFS0_I2C_IBSR_SPC *((volatile unsigned int*)(0x42700084UL)) -#define bFM3_MFS0_I2C_IBSR_RSC *((volatile unsigned int*)(0x42700088UL)) -#define bFM3_MFS0_I2C_IBSR_AL *((volatile unsigned int*)(0x4270008CUL)) -#define bFM3_MFS0_I2C_IBSR_TRX *((volatile unsigned int*)(0x42700090UL)) -#define bFM3_MFS0_I2C_IBSR_RSA *((volatile unsigned int*)(0x42700094UL)) -#define bFM3_MFS0_I2C_IBSR_RACK *((volatile unsigned int*)(0x42700098UL)) -#define bFM3_MFS0_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270009CUL)) -#define bFM3_MFS0_I2C_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) -#define bFM3_MFS0_I2C_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) -#define bFM3_MFS0_I2C_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) -#define bFM3_MFS0_I2C_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) -#define bFM3_MFS0_I2C_SSR_TBIE *((volatile unsigned int*)(0x427000B0UL)) -#define bFM3_MFS0_I2C_SSR_DMA *((volatile unsigned int*)(0x427000B4UL)) -#define bFM3_MFS0_I2C_SSR_TSET *((volatile unsigned int*)(0x427000B8UL)) -#define bFM3_MFS0_I2C_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) -#define bFM3_MFS0_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42700200UL)) -#define bFM3_MFS0_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42700204UL)) -#define bFM3_MFS0_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42700208UL)) -#define bFM3_MFS0_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270020CUL)) -#define bFM3_MFS0_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42700210UL)) -#define bFM3_MFS0_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42700214UL)) -#define bFM3_MFS0_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42700218UL)) -#define bFM3_MFS0_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270021CUL)) -#define bFM3_MFS0_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42700220UL)) -#define bFM3_MFS0_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42700224UL)) -#define bFM3_MFS0_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42700228UL)) -#define bFM3_MFS0_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270022CUL)) -#define bFM3_MFS0_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42700230UL)) -#define bFM3_MFS0_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42700234UL)) -#define bFM3_MFS0_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42700238UL)) -#define bFM3_MFS0_I2C_ISMK_EN *((volatile unsigned int*)(0x4270023CUL)) - -/* UART asynchronous channel 1 registers */ -#define bFM3_MFS1_UART_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_UART_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) -#define bFM3_MFS1_UART_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_UART_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_UART_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM3_MFS1_UART_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM3_MFS1_UART_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM3_MFS1_UART_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_UART_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_UART_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_UART_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_UART_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_UART_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_UART_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_UART_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_UART_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_UART_ESCR_P *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_UART_ESCR_PEN *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_UART_ESCR_INV *((volatile unsigned int*)(0x42702094UL)) -#define bFM3_MFS1_UART_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) -#define bFM3_MFS1_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270209CUL)) -#define bFM3_MFS1_UART_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_UART_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_UART_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_UART_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_UART_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM3_MFS1_UART_SSR_PE *((volatile unsigned int*)(0x427020B4UL)) -#define bFM3_MFS1_UART_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM3_MFS1_UART_RDR_AD *((volatile unsigned int*)(0x42702120UL)) -#define bFM3_MFS1_UART_TDR_AD *((volatile unsigned int*)(0x42702120UL)) -#define bFM3_MFS1_UART_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) -#define bFM3_MFS1_UART_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) - -/* UART synchronous channel 1 registers */ -#define bFM3_MFS1_CSIO_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42702004UL)) -#define bFM3_MFS1_CSIO_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) -#define bFM3_MFS1_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM3_MFS1_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM3_MFS1_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM3_MFS1_CSIO_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_CSIO_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_CSIO_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_CSIO_SCR_SPI *((volatile unsigned int*)(0x42702034UL)) -#define bFM3_MFS1_CSIO_SCR_MS *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270209CUL)) -#define bFM3_MFS1_CSIO_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_CSIO_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_CSIO_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) - -/* UART LIN channel 1 registers */ -#define bFM3_MFS1_LIN_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_LIN_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_LIN_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_LIN_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM3_MFS1_LIN_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM3_MFS1_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM3_MFS1_LIN_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_LIN_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_LIN_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_LIN_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_LIN_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_LIN_SCR_LBR *((volatile unsigned int*)(0x42702034UL)) -#define bFM3_MFS1_LIN_SCR_MS *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) -#define bFM3_MFS1_LIN_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_LIN_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_LIN_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_LIN_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_LIN_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM3_MFS1_LIN_SSR_LBD *((volatile unsigned int*)(0x427020B4UL)) -#define bFM3_MFS1_LIN_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM3_MFS1_LIN_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) -#define bFM3_MFS1_LIN_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) - -/* I2C channel 1 registers */ -#define bFM3_MFS1_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42702000UL)) -#define bFM3_MFS1_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42702004UL)) -#define bFM3_MFS1_I2C_SMR_TIE *((volatile unsigned int*)(0x42702008UL)) -#define bFM3_MFS1_I2C_SMR_RIE *((volatile unsigned int*)(0x4270200CUL)) -#define bFM3_MFS1_I2C_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) -#define bFM3_MFS1_I2C_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) -#define bFM3_MFS1_I2C_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) -#define bFM3_MFS1_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) -#define bFM3_MFS1_I2C_IBCR_INT *((volatile unsigned int*)(0x42702020UL)) -#define bFM3_MFS1_I2C_IBCR_BER *((volatile unsigned int*)(0x42702024UL)) -#define bFM3_MFS1_I2C_IBCR_INTE *((volatile unsigned int*)(0x42702028UL)) -#define bFM3_MFS1_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270202CUL)) -#define bFM3_MFS1_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42702030UL)) -#define bFM3_MFS1_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42702034UL)) -#define bFM3_MFS1_I2C_IBCR_ACT *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_I2C_IBCR_SCC *((volatile unsigned int*)(0x42702038UL)) -#define bFM3_MFS1_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270203CUL)) -#define bFM3_MFS1_I2C_IBSR_BB *((volatile unsigned int*)(0x42702080UL)) -#define bFM3_MFS1_I2C_IBSR_SPC *((volatile unsigned int*)(0x42702084UL)) -#define bFM3_MFS1_I2C_IBSR_RSC *((volatile unsigned int*)(0x42702088UL)) -#define bFM3_MFS1_I2C_IBSR_AL *((volatile unsigned int*)(0x4270208CUL)) -#define bFM3_MFS1_I2C_IBSR_TRX *((volatile unsigned int*)(0x42702090UL)) -#define bFM3_MFS1_I2C_IBSR_RSA *((volatile unsigned int*)(0x42702094UL)) -#define bFM3_MFS1_I2C_IBSR_RACK *((volatile unsigned int*)(0x42702098UL)) -#define bFM3_MFS1_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270209CUL)) -#define bFM3_MFS1_I2C_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) -#define bFM3_MFS1_I2C_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) -#define bFM3_MFS1_I2C_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) -#define bFM3_MFS1_I2C_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) -#define bFM3_MFS1_I2C_SSR_TBIE *((volatile unsigned int*)(0x427020B0UL)) -#define bFM3_MFS1_I2C_SSR_DMA *((volatile unsigned int*)(0x427020B4UL)) -#define bFM3_MFS1_I2C_SSR_TSET *((volatile unsigned int*)(0x427020B8UL)) -#define bFM3_MFS1_I2C_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) -#define bFM3_MFS1_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42702200UL)) -#define bFM3_MFS1_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42702204UL)) -#define bFM3_MFS1_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42702208UL)) -#define bFM3_MFS1_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270220CUL)) -#define bFM3_MFS1_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42702210UL)) -#define bFM3_MFS1_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42702214UL)) -#define bFM3_MFS1_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42702218UL)) -#define bFM3_MFS1_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270221CUL)) -#define bFM3_MFS1_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42702220UL)) -#define bFM3_MFS1_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42702224UL)) -#define bFM3_MFS1_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42702228UL)) -#define bFM3_MFS1_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270222CUL)) -#define bFM3_MFS1_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42702230UL)) -#define bFM3_MFS1_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42702234UL)) -#define bFM3_MFS1_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42702238UL)) -#define bFM3_MFS1_I2C_ISMK_EN *((volatile unsigned int*)(0x4270223CUL)) - -/* UART asynchronous channel 2 registers */ -#define bFM3_MFS2_UART_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_UART_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) -#define bFM3_MFS2_UART_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_UART_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_UART_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM3_MFS2_UART_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM3_MFS2_UART_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM3_MFS2_UART_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_UART_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_UART_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_UART_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_UART_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_UART_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_UART_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_UART_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_UART_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_UART_ESCR_P *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_UART_ESCR_PEN *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_UART_ESCR_INV *((volatile unsigned int*)(0x42704094UL)) -#define bFM3_MFS2_UART_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) -#define bFM3_MFS2_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270409CUL)) -#define bFM3_MFS2_UART_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_UART_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_UART_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_UART_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_UART_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM3_MFS2_UART_SSR_PE *((volatile unsigned int*)(0x427040B4UL)) -#define bFM3_MFS2_UART_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM3_MFS2_UART_RDR_AD *((volatile unsigned int*)(0x42704120UL)) -#define bFM3_MFS2_UART_TDR_AD *((volatile unsigned int*)(0x42704120UL)) -#define bFM3_MFS2_UART_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) -#define bFM3_MFS2_UART_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) - -/* UART synchronous channel 2 registers */ -#define bFM3_MFS2_CSIO_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42704004UL)) -#define bFM3_MFS2_CSIO_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) -#define bFM3_MFS2_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM3_MFS2_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM3_MFS2_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM3_MFS2_CSIO_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_CSIO_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_CSIO_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_CSIO_SCR_SPI *((volatile unsigned int*)(0x42704034UL)) -#define bFM3_MFS2_CSIO_SCR_MS *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270409CUL)) -#define bFM3_MFS2_CSIO_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_CSIO_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_CSIO_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) - -/* UART LIN channel 2 registers */ -#define bFM3_MFS2_LIN_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_LIN_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_LIN_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_LIN_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM3_MFS2_LIN_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM3_MFS2_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM3_MFS2_LIN_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_LIN_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_LIN_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_LIN_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_LIN_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_LIN_SCR_LBR *((volatile unsigned int*)(0x42704034UL)) -#define bFM3_MFS2_LIN_SCR_MS *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) -#define bFM3_MFS2_LIN_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_LIN_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_LIN_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_LIN_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_LIN_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM3_MFS2_LIN_SSR_LBD *((volatile unsigned int*)(0x427040B4UL)) -#define bFM3_MFS2_LIN_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM3_MFS2_LIN_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) -#define bFM3_MFS2_LIN_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) - -/* I2C channel 2 registers */ -#define bFM3_MFS2_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42704000UL)) -#define bFM3_MFS2_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42704004UL)) -#define bFM3_MFS2_I2C_SMR_TIE *((volatile unsigned int*)(0x42704008UL)) -#define bFM3_MFS2_I2C_SMR_RIE *((volatile unsigned int*)(0x4270400CUL)) -#define bFM3_MFS2_I2C_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) -#define bFM3_MFS2_I2C_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) -#define bFM3_MFS2_I2C_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) -#define bFM3_MFS2_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) -#define bFM3_MFS2_I2C_IBCR_INT *((volatile unsigned int*)(0x42704020UL)) -#define bFM3_MFS2_I2C_IBCR_BER *((volatile unsigned int*)(0x42704024UL)) -#define bFM3_MFS2_I2C_IBCR_INTE *((volatile unsigned int*)(0x42704028UL)) -#define bFM3_MFS2_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270402CUL)) -#define bFM3_MFS2_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42704030UL)) -#define bFM3_MFS2_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42704034UL)) -#define bFM3_MFS2_I2C_IBCR_ACT *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_I2C_IBCR_SCC *((volatile unsigned int*)(0x42704038UL)) -#define bFM3_MFS2_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270403CUL)) -#define bFM3_MFS2_I2C_IBSR_BB *((volatile unsigned int*)(0x42704080UL)) -#define bFM3_MFS2_I2C_IBSR_SPC *((volatile unsigned int*)(0x42704084UL)) -#define bFM3_MFS2_I2C_IBSR_RSC *((volatile unsigned int*)(0x42704088UL)) -#define bFM3_MFS2_I2C_IBSR_AL *((volatile unsigned int*)(0x4270408CUL)) -#define bFM3_MFS2_I2C_IBSR_TRX *((volatile unsigned int*)(0x42704090UL)) -#define bFM3_MFS2_I2C_IBSR_RSA *((volatile unsigned int*)(0x42704094UL)) -#define bFM3_MFS2_I2C_IBSR_RACK *((volatile unsigned int*)(0x42704098UL)) -#define bFM3_MFS2_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270409CUL)) -#define bFM3_MFS2_I2C_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) -#define bFM3_MFS2_I2C_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) -#define bFM3_MFS2_I2C_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) -#define bFM3_MFS2_I2C_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) -#define bFM3_MFS2_I2C_SSR_TBIE *((volatile unsigned int*)(0x427040B0UL)) -#define bFM3_MFS2_I2C_SSR_DMA *((volatile unsigned int*)(0x427040B4UL)) -#define bFM3_MFS2_I2C_SSR_TSET *((volatile unsigned int*)(0x427040B8UL)) -#define bFM3_MFS2_I2C_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) -#define bFM3_MFS2_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42704200UL)) -#define bFM3_MFS2_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42704204UL)) -#define bFM3_MFS2_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42704208UL)) -#define bFM3_MFS2_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270420CUL)) -#define bFM3_MFS2_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42704210UL)) -#define bFM3_MFS2_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42704214UL)) -#define bFM3_MFS2_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42704218UL)) -#define bFM3_MFS2_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270421CUL)) -#define bFM3_MFS2_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42704220UL)) -#define bFM3_MFS2_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42704224UL)) -#define bFM3_MFS2_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42704228UL)) -#define bFM3_MFS2_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270422CUL)) -#define bFM3_MFS2_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42704230UL)) -#define bFM3_MFS2_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42704234UL)) -#define bFM3_MFS2_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42704238UL)) -#define bFM3_MFS2_I2C_ISMK_EN *((volatile unsigned int*)(0x4270423CUL)) - -/* UART asynchronous channel 3 registers */ -#define bFM3_MFS3_UART_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_UART_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) -#define bFM3_MFS3_UART_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_UART_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_UART_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM3_MFS3_UART_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM3_MFS3_UART_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM3_MFS3_UART_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_UART_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_UART_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_UART_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_UART_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_UART_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_UART_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_UART_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_UART_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_UART_ESCR_P *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_UART_ESCR_PEN *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_UART_ESCR_INV *((volatile unsigned int*)(0x42706094UL)) -#define bFM3_MFS3_UART_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) -#define bFM3_MFS3_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270609CUL)) -#define bFM3_MFS3_UART_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_UART_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_UART_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_UART_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_UART_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM3_MFS3_UART_SSR_PE *((volatile unsigned int*)(0x427060B4UL)) -#define bFM3_MFS3_UART_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM3_MFS3_UART_RDR_AD *((volatile unsigned int*)(0x42706120UL)) -#define bFM3_MFS3_UART_TDR_AD *((volatile unsigned int*)(0x42706120UL)) -#define bFM3_MFS3_UART_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) -#define bFM3_MFS3_UART_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) - -/* UART synchronous channel 3 registers */ -#define bFM3_MFS3_CSIO_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42706004UL)) -#define bFM3_MFS3_CSIO_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) -#define bFM3_MFS3_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM3_MFS3_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM3_MFS3_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM3_MFS3_CSIO_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_CSIO_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_CSIO_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_CSIO_SCR_SPI *((volatile unsigned int*)(0x42706034UL)) -#define bFM3_MFS3_CSIO_SCR_MS *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270609CUL)) -#define bFM3_MFS3_CSIO_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_CSIO_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_CSIO_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) - -/* UART LIN channel 3 registers */ -#define bFM3_MFS3_LIN_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_LIN_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_LIN_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_LIN_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM3_MFS3_LIN_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM3_MFS3_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM3_MFS3_LIN_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_LIN_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_LIN_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_LIN_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_LIN_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_LIN_SCR_LBR *((volatile unsigned int*)(0x42706034UL)) -#define bFM3_MFS3_LIN_SCR_MS *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) -#define bFM3_MFS3_LIN_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_LIN_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_LIN_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_LIN_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_LIN_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM3_MFS3_LIN_SSR_LBD *((volatile unsigned int*)(0x427060B4UL)) -#define bFM3_MFS3_LIN_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM3_MFS3_LIN_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) -#define bFM3_MFS3_LIN_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) - -/* I2C channel 3 registers */ -#define bFM3_MFS3_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42706000UL)) -#define bFM3_MFS3_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42706004UL)) -#define bFM3_MFS3_I2C_SMR_TIE *((volatile unsigned int*)(0x42706008UL)) -#define bFM3_MFS3_I2C_SMR_RIE *((volatile unsigned int*)(0x4270600CUL)) -#define bFM3_MFS3_I2C_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) -#define bFM3_MFS3_I2C_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) -#define bFM3_MFS3_I2C_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) -#define bFM3_MFS3_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) -#define bFM3_MFS3_I2C_IBCR_INT *((volatile unsigned int*)(0x42706020UL)) -#define bFM3_MFS3_I2C_IBCR_BER *((volatile unsigned int*)(0x42706024UL)) -#define bFM3_MFS3_I2C_IBCR_INTE *((volatile unsigned int*)(0x42706028UL)) -#define bFM3_MFS3_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270602CUL)) -#define bFM3_MFS3_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42706030UL)) -#define bFM3_MFS3_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42706034UL)) -#define bFM3_MFS3_I2C_IBCR_ACT *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_I2C_IBCR_SCC *((volatile unsigned int*)(0x42706038UL)) -#define bFM3_MFS3_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270603CUL)) -#define bFM3_MFS3_I2C_IBSR_BB *((volatile unsigned int*)(0x42706080UL)) -#define bFM3_MFS3_I2C_IBSR_SPC *((volatile unsigned int*)(0x42706084UL)) -#define bFM3_MFS3_I2C_IBSR_RSC *((volatile unsigned int*)(0x42706088UL)) -#define bFM3_MFS3_I2C_IBSR_AL *((volatile unsigned int*)(0x4270608CUL)) -#define bFM3_MFS3_I2C_IBSR_TRX *((volatile unsigned int*)(0x42706090UL)) -#define bFM3_MFS3_I2C_IBSR_RSA *((volatile unsigned int*)(0x42706094UL)) -#define bFM3_MFS3_I2C_IBSR_RACK *((volatile unsigned int*)(0x42706098UL)) -#define bFM3_MFS3_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270609CUL)) -#define bFM3_MFS3_I2C_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) -#define bFM3_MFS3_I2C_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) -#define bFM3_MFS3_I2C_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) -#define bFM3_MFS3_I2C_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) -#define bFM3_MFS3_I2C_SSR_TBIE *((volatile unsigned int*)(0x427060B0UL)) -#define bFM3_MFS3_I2C_SSR_DMA *((volatile unsigned int*)(0x427060B4UL)) -#define bFM3_MFS3_I2C_SSR_TSET *((volatile unsigned int*)(0x427060B8UL)) -#define bFM3_MFS3_I2C_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) -#define bFM3_MFS3_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42706200UL)) -#define bFM3_MFS3_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42706204UL)) -#define bFM3_MFS3_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42706208UL)) -#define bFM3_MFS3_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270620CUL)) -#define bFM3_MFS3_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42706210UL)) -#define bFM3_MFS3_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42706214UL)) -#define bFM3_MFS3_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42706218UL)) -#define bFM3_MFS3_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270621CUL)) -#define bFM3_MFS3_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42706220UL)) -#define bFM3_MFS3_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42706224UL)) -#define bFM3_MFS3_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42706228UL)) -#define bFM3_MFS3_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270622CUL)) -#define bFM3_MFS3_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42706230UL)) -#define bFM3_MFS3_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42706234UL)) -#define bFM3_MFS3_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42706238UL)) -#define bFM3_MFS3_I2C_ISMK_EN *((volatile unsigned int*)(0x4270623CUL)) - -/* UART asynchronous channel 4 registers */ -#define bFM3_MFS4_UART_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_UART_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) -#define bFM3_MFS4_UART_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_UART_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_UART_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM3_MFS4_UART_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM3_MFS4_UART_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM3_MFS4_UART_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_UART_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_UART_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_UART_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_UART_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_UART_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_UART_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_UART_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_UART_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_UART_ESCR_P *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_UART_ESCR_PEN *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_UART_ESCR_INV *((volatile unsigned int*)(0x42708094UL)) -#define bFM3_MFS4_UART_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) -#define bFM3_MFS4_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270809CUL)) -#define bFM3_MFS4_UART_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_UART_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_UART_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_UART_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_UART_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM3_MFS4_UART_SSR_PE *((volatile unsigned int*)(0x427080B4UL)) -#define bFM3_MFS4_UART_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_UART_RDR_AD *((volatile unsigned int*)(0x42708120UL)) -#define bFM3_MFS4_UART_TDR_AD *((volatile unsigned int*)(0x42708120UL)) -#define bFM3_MFS4_UART_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_UART_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_UART_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_UART_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_UART_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_UART_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_UART_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_UART_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_UART_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_UART_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_UART_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_UART_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_UART_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_UART_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_UART_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_UART_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_UART_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_UART_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_UART_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_UART_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_UART_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_UART_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_UART_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_UART_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_UART_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) - -/* UART synchronous channel 4 registers */ -#define bFM3_MFS4_CSIO_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42708004UL)) -#define bFM3_MFS4_CSIO_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) -#define bFM3_MFS4_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM3_MFS4_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM3_MFS4_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM3_MFS4_CSIO_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_CSIO_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_CSIO_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_CSIO_SCR_SPI *((volatile unsigned int*)(0x42708034UL)) -#define bFM3_MFS4_CSIO_SCR_MS *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270809CUL)) -#define bFM3_MFS4_CSIO_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_CSIO_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_CSIO_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_CSIO_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_CSIO_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_CSIO_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_CSIO_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL)) -#define bFM3_MFS4_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL)) - -/* UART LIN channel 4 registers */ -#define bFM3_MFS4_LIN_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_LIN_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_LIN_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_LIN_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM3_MFS4_LIN_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM3_MFS4_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM3_MFS4_LIN_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_LIN_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_LIN_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_LIN_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_LIN_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_LIN_SCR_LBR *((volatile unsigned int*)(0x42708034UL)) -#define bFM3_MFS4_LIN_SCR_MS *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) -#define bFM3_MFS4_LIN_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_LIN_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_LIN_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_LIN_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_LIN_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM3_MFS4_LIN_SSR_LBD *((volatile unsigned int*)(0x427080B4UL)) -#define bFM3_MFS4_LIN_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_LIN_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_LIN_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) -#define bFM3_MFS4_LIN_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_LIN_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_LIN_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_LIN_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_LIN_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_LIN_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_LIN_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_LIN_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_LIN_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_LIN_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_LIN_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_LIN_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_LIN_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_LIN_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL)) -#define bFM3_MFS4_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL)) -#define bFM3_MFS4_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL)) - -/* I2C channel 4 registers */ -#define bFM3_MFS4_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42708000UL)) -#define bFM3_MFS4_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42708004UL)) -#define bFM3_MFS4_I2C_SMR_TIE *((volatile unsigned int*)(0x42708008UL)) -#define bFM3_MFS4_I2C_SMR_RIE *((volatile unsigned int*)(0x4270800CUL)) -#define bFM3_MFS4_I2C_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) -#define bFM3_MFS4_I2C_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) -#define bFM3_MFS4_I2C_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) -#define bFM3_MFS4_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) -#define bFM3_MFS4_I2C_IBCR_INT *((volatile unsigned int*)(0x42708020UL)) -#define bFM3_MFS4_I2C_IBCR_BER *((volatile unsigned int*)(0x42708024UL)) -#define bFM3_MFS4_I2C_IBCR_INTE *((volatile unsigned int*)(0x42708028UL)) -#define bFM3_MFS4_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270802CUL)) -#define bFM3_MFS4_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42708030UL)) -#define bFM3_MFS4_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42708034UL)) -#define bFM3_MFS4_I2C_IBCR_ACT *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_I2C_IBCR_SCC *((volatile unsigned int*)(0x42708038UL)) -#define bFM3_MFS4_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270803CUL)) -#define bFM3_MFS4_I2C_IBSR_BB *((volatile unsigned int*)(0x42708080UL)) -#define bFM3_MFS4_I2C_IBSR_SPC *((volatile unsigned int*)(0x42708084UL)) -#define bFM3_MFS4_I2C_IBSR_RSC *((volatile unsigned int*)(0x42708088UL)) -#define bFM3_MFS4_I2C_IBSR_AL *((volatile unsigned int*)(0x4270808CUL)) -#define bFM3_MFS4_I2C_IBSR_TRX *((volatile unsigned int*)(0x42708090UL)) -#define bFM3_MFS4_I2C_IBSR_RSA *((volatile unsigned int*)(0x42708094UL)) -#define bFM3_MFS4_I2C_IBSR_RACK *((volatile unsigned int*)(0x42708098UL)) -#define bFM3_MFS4_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270809CUL)) -#define bFM3_MFS4_I2C_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) -#define bFM3_MFS4_I2C_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) -#define bFM3_MFS4_I2C_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) -#define bFM3_MFS4_I2C_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) -#define bFM3_MFS4_I2C_SSR_TBIE *((volatile unsigned int*)(0x427080B0UL)) -#define bFM3_MFS4_I2C_SSR_DMA *((volatile unsigned int*)(0x427080B4UL)) -#define bFM3_MFS4_I2C_SSR_TSET *((volatile unsigned int*)(0x427080B8UL)) -#define bFM3_MFS4_I2C_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) -#define bFM3_MFS4_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42708200UL)) -#define bFM3_MFS4_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42708204UL)) -#define bFM3_MFS4_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42708208UL)) -#define bFM3_MFS4_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270820CUL)) -#define bFM3_MFS4_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42708210UL)) -#define bFM3_MFS4_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42708214UL)) -#define bFM3_MFS4_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42708218UL)) -#define bFM3_MFS4_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270821CUL)) -#define bFM3_MFS4_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42708220UL)) -#define bFM3_MFS4_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42708224UL)) -#define bFM3_MFS4_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42708228UL)) -#define bFM3_MFS4_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270822CUL)) -#define bFM3_MFS4_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42708230UL)) -#define bFM3_MFS4_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42708234UL)) -#define bFM3_MFS4_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42708238UL)) -#define bFM3_MFS4_I2C_ISMK_EN *((volatile unsigned int*)(0x4270823CUL)) -#define bFM3_MFS4_I2C_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_I2C_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_I2C_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_I2C_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_I2C_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_I2C_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_I2C_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_I2C_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_I2C_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_I2C_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) -#define bFM3_MFS4_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) -#define bFM3_MFS4_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) -#define bFM3_MFS4_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) -#define bFM3_MFS4_I2C_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) -#define bFM3_MFS4_I2C_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) -#define bFM3_MFS4_I2C_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) -#define bFM3_MFS4_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) -#define bFM3_MFS4_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) -#define bFM3_MFS4_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) -#define bFM3_MFS4_I2C_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) -#define bFM3_MFS4_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) -#define bFM3_MFS4_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) -#define bFM3_MFS4_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) -#define bFM3_MFS4_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) -#define bFM3_MFS4_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) -#define bFM3_MFS4_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) -#define bFM3_MFS4_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) -#define bFM3_MFS4_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) -#define bFM3_MFS4_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) -#define bFM3_MFS4_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) -#define bFM3_MFS4_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) -#define bFM3_MFS4_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) -#define bFM3_MFS4_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) -#define bFM3_MFS4_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) -#define bFM3_MFS4_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL)) -#define bFM3_MFS4_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL)) -#define bFM3_MFS4_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL)) - -/* UART asynchronous channel 5 registers */ -#define bFM3_MFS5_UART_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_UART_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) -#define bFM3_MFS5_UART_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_UART_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_UART_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM3_MFS5_UART_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM3_MFS5_UART_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM3_MFS5_UART_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_UART_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_UART_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_UART_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_UART_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_UART_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_UART_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_UART_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_UART_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_UART_ESCR_P *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_UART_ESCR_PEN *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_UART_ESCR_INV *((volatile unsigned int*)(0x4270A094UL)) -#define bFM3_MFS5_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) -#define bFM3_MFS5_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM3_MFS5_UART_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_UART_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_UART_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_UART_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_UART_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM3_MFS5_UART_SSR_PE *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM3_MFS5_UART_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_UART_RDR_AD *((volatile unsigned int*)(0x4270A120UL)) -#define bFM3_MFS5_UART_TDR_AD *((volatile unsigned int*)(0x4270A120UL)) -#define bFM3_MFS5_UART_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_UART_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_UART_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_UART_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_UART_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_UART_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_UART_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_UART_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_UART_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_UART_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_UART_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_UART_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_UART_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) - -/* UART synchronous channel 5 registers */ -#define bFM3_MFS5_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270A004UL)) -#define bFM3_MFS5_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) -#define bFM3_MFS5_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM3_MFS5_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM3_MFS5_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM3_MFS5_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270A034UL)) -#define bFM3_MFS5_CSIO_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM3_MFS5_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_CSIO_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL)) -#define bFM3_MFS5_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL)) - -/* UART LIN channel 5 registers */ -#define bFM3_MFS5_LIN_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_LIN_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM3_MFS5_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM3_MFS5_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM3_MFS5_LIN_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_LIN_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_LIN_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_LIN_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_LIN_SCR_LBR *((volatile unsigned int*)(0x4270A034UL)) -#define bFM3_MFS5_LIN_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) -#define bFM3_MFS5_LIN_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_LIN_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_LIN_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM3_MFS5_LIN_SSR_LBD *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM3_MFS5_LIN_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_LIN_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) -#define bFM3_MFS5_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_LIN_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_LIN_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_LIN_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL)) -#define bFM3_MFS5_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL)) -#define bFM3_MFS5_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL)) - -/* I2C channel 5 registers */ -#define bFM3_MFS5_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270A000UL)) -#define bFM3_MFS5_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270A004UL)) -#define bFM3_MFS5_I2C_SMR_TIE *((volatile unsigned int*)(0x4270A008UL)) -#define bFM3_MFS5_I2C_SMR_RIE *((volatile unsigned int*)(0x4270A00CUL)) -#define bFM3_MFS5_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) -#define bFM3_MFS5_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) -#define bFM3_MFS5_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) -#define bFM3_MFS5_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) -#define bFM3_MFS5_I2C_IBCR_INT *((volatile unsigned int*)(0x4270A020UL)) -#define bFM3_MFS5_I2C_IBCR_BER *((volatile unsigned int*)(0x4270A024UL)) -#define bFM3_MFS5_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270A028UL)) -#define bFM3_MFS5_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270A02CUL)) -#define bFM3_MFS5_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270A030UL)) -#define bFM3_MFS5_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270A034UL)) -#define bFM3_MFS5_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270A038UL)) -#define bFM3_MFS5_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270A03CUL)) -#define bFM3_MFS5_I2C_IBSR_BB *((volatile unsigned int*)(0x4270A080UL)) -#define bFM3_MFS5_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270A084UL)) -#define bFM3_MFS5_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270A088UL)) -#define bFM3_MFS5_I2C_IBSR_AL *((volatile unsigned int*)(0x4270A08CUL)) -#define bFM3_MFS5_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270A090UL)) -#define bFM3_MFS5_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270A094UL)) -#define bFM3_MFS5_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270A098UL)) -#define bFM3_MFS5_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270A09CUL)) -#define bFM3_MFS5_I2C_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) -#define bFM3_MFS5_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) -#define bFM3_MFS5_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) -#define bFM3_MFS5_I2C_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) -#define bFM3_MFS5_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270A0B0UL)) -#define bFM3_MFS5_I2C_SSR_DMA *((volatile unsigned int*)(0x4270A0B4UL)) -#define bFM3_MFS5_I2C_SSR_TSET *((volatile unsigned int*)(0x4270A0B8UL)) -#define bFM3_MFS5_I2C_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) -#define bFM3_MFS5_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270A200UL)) -#define bFM3_MFS5_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270A204UL)) -#define bFM3_MFS5_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270A208UL)) -#define bFM3_MFS5_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270A20CUL)) -#define bFM3_MFS5_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270A210UL)) -#define bFM3_MFS5_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270A214UL)) -#define bFM3_MFS5_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270A218UL)) -#define bFM3_MFS5_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270A21CUL)) -#define bFM3_MFS5_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270A220UL)) -#define bFM3_MFS5_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270A224UL)) -#define bFM3_MFS5_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270A228UL)) -#define bFM3_MFS5_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270A22CUL)) -#define bFM3_MFS5_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270A230UL)) -#define bFM3_MFS5_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270A234UL)) -#define bFM3_MFS5_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270A238UL)) -#define bFM3_MFS5_I2C_ISMK_EN *((volatile unsigned int*)(0x4270A23CUL)) -#define bFM3_MFS5_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_I2C_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_I2C_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_I2C_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) -#define bFM3_MFS5_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) -#define bFM3_MFS5_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) -#define bFM3_MFS5_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) -#define bFM3_MFS5_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) -#define bFM3_MFS5_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) -#define bFM3_MFS5_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) -#define bFM3_MFS5_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) -#define bFM3_MFS5_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) -#define bFM3_MFS5_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) -#define bFM3_MFS5_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) -#define bFM3_MFS5_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) -#define bFM3_MFS5_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) -#define bFM3_MFS5_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) -#define bFM3_MFS5_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) -#define bFM3_MFS5_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) -#define bFM3_MFS5_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) -#define bFM3_MFS5_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) -#define bFM3_MFS5_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) -#define bFM3_MFS5_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) -#define bFM3_MFS5_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) -#define bFM3_MFS5_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) -#define bFM3_MFS5_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) -#define bFM3_MFS5_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) -#define bFM3_MFS5_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) -#define bFM3_MFS5_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL)) -#define bFM3_MFS5_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL)) -#define bFM3_MFS5_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL)) - -/* UART asynchronous channel 6 registers */ -#define bFM3_MFS6_UART_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_UART_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) -#define bFM3_MFS6_UART_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_UART_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_UART_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM3_MFS6_UART_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM3_MFS6_UART_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM3_MFS6_UART_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_UART_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_UART_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_UART_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_UART_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_UART_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_UART_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_UART_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_UART_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_UART_ESCR_P *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_UART_ESCR_PEN *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_UART_ESCR_INV *((volatile unsigned int*)(0x4270C094UL)) -#define bFM3_MFS6_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) -#define bFM3_MFS6_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM3_MFS6_UART_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_UART_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_UART_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_UART_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_UART_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM3_MFS6_UART_SSR_PE *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM3_MFS6_UART_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_UART_RDR_AD *((volatile unsigned int*)(0x4270C120UL)) -#define bFM3_MFS6_UART_TDR_AD *((volatile unsigned int*)(0x4270C120UL)) -#define bFM3_MFS6_UART_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_UART_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_UART_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_UART_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_UART_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_UART_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_UART_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_UART_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_UART_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_UART_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_UART_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_UART_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_UART_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) - -/* UART synchronous channel 6 registers */ -#define bFM3_MFS6_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270C004UL)) -#define bFM3_MFS6_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) -#define bFM3_MFS6_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM3_MFS6_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM3_MFS6_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM3_MFS6_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270C034UL)) -#define bFM3_MFS6_CSIO_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM3_MFS6_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_CSIO_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL)) -#define bFM3_MFS6_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL)) - -/* UART LIN channel 6 registers */ -#define bFM3_MFS6_LIN_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_LIN_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM3_MFS6_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM3_MFS6_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM3_MFS6_LIN_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_LIN_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_LIN_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_LIN_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_LIN_SCR_LBR *((volatile unsigned int*)(0x4270C034UL)) -#define bFM3_MFS6_LIN_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) -#define bFM3_MFS6_LIN_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_LIN_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_LIN_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM3_MFS6_LIN_SSR_LBD *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM3_MFS6_LIN_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_LIN_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) -#define bFM3_MFS6_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_LIN_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_LIN_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_LIN_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL)) -#define bFM3_MFS6_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL)) -#define bFM3_MFS6_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL)) - -/* I2C channel 6 registers */ -#define bFM3_MFS6_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270C000UL)) -#define bFM3_MFS6_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270C004UL)) -#define bFM3_MFS6_I2C_SMR_TIE *((volatile unsigned int*)(0x4270C008UL)) -#define bFM3_MFS6_I2C_SMR_RIE *((volatile unsigned int*)(0x4270C00CUL)) -#define bFM3_MFS6_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) -#define bFM3_MFS6_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) -#define bFM3_MFS6_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) -#define bFM3_MFS6_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) -#define bFM3_MFS6_I2C_IBCR_INT *((volatile unsigned int*)(0x4270C020UL)) -#define bFM3_MFS6_I2C_IBCR_BER *((volatile unsigned int*)(0x4270C024UL)) -#define bFM3_MFS6_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270C028UL)) -#define bFM3_MFS6_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270C02CUL)) -#define bFM3_MFS6_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270C030UL)) -#define bFM3_MFS6_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270C034UL)) -#define bFM3_MFS6_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270C038UL)) -#define bFM3_MFS6_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270C03CUL)) -#define bFM3_MFS6_I2C_IBSR_BB *((volatile unsigned int*)(0x4270C080UL)) -#define bFM3_MFS6_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270C084UL)) -#define bFM3_MFS6_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270C088UL)) -#define bFM3_MFS6_I2C_IBSR_AL *((volatile unsigned int*)(0x4270C08CUL)) -#define bFM3_MFS6_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270C090UL)) -#define bFM3_MFS6_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270C094UL)) -#define bFM3_MFS6_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270C098UL)) -#define bFM3_MFS6_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270C09CUL)) -#define bFM3_MFS6_I2C_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) -#define bFM3_MFS6_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) -#define bFM3_MFS6_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) -#define bFM3_MFS6_I2C_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) -#define bFM3_MFS6_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270C0B0UL)) -#define bFM3_MFS6_I2C_SSR_DMA *((volatile unsigned int*)(0x4270C0B4UL)) -#define bFM3_MFS6_I2C_SSR_TSET *((volatile unsigned int*)(0x4270C0B8UL)) -#define bFM3_MFS6_I2C_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) -#define bFM3_MFS6_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270C200UL)) -#define bFM3_MFS6_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270C204UL)) -#define bFM3_MFS6_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270C208UL)) -#define bFM3_MFS6_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270C20CUL)) -#define bFM3_MFS6_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270C210UL)) -#define bFM3_MFS6_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270C214UL)) -#define bFM3_MFS6_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270C218UL)) -#define bFM3_MFS6_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270C21CUL)) -#define bFM3_MFS6_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270C220UL)) -#define bFM3_MFS6_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270C224UL)) -#define bFM3_MFS6_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270C228UL)) -#define bFM3_MFS6_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270C22CUL)) -#define bFM3_MFS6_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270C230UL)) -#define bFM3_MFS6_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270C234UL)) -#define bFM3_MFS6_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270C238UL)) -#define bFM3_MFS6_I2C_ISMK_EN *((volatile unsigned int*)(0x4270C23CUL)) -#define bFM3_MFS6_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_I2C_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_I2C_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_I2C_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) -#define bFM3_MFS6_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) -#define bFM3_MFS6_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) -#define bFM3_MFS6_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) -#define bFM3_MFS6_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) -#define bFM3_MFS6_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) -#define bFM3_MFS6_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) -#define bFM3_MFS6_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) -#define bFM3_MFS6_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) -#define bFM3_MFS6_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) -#define bFM3_MFS6_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) -#define bFM3_MFS6_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) -#define bFM3_MFS6_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) -#define bFM3_MFS6_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) -#define bFM3_MFS6_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) -#define bFM3_MFS6_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) -#define bFM3_MFS6_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) -#define bFM3_MFS6_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) -#define bFM3_MFS6_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) -#define bFM3_MFS6_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) -#define bFM3_MFS6_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) -#define bFM3_MFS6_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) -#define bFM3_MFS6_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) -#define bFM3_MFS6_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) -#define bFM3_MFS6_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) -#define bFM3_MFS6_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL)) -#define bFM3_MFS6_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL)) -#define bFM3_MFS6_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL)) - -/* UART asynchronous channel 7 registers */ -#define bFM3_MFS7_UART_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_UART_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) -#define bFM3_MFS7_UART_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_UART_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_UART_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM3_MFS7_UART_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM3_MFS7_UART_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM3_MFS7_UART_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_UART_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_UART_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_UART_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_UART_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_UART_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_UART_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_UART_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_UART_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_UART_ESCR_P *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_UART_ESCR_PEN *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_UART_ESCR_INV *((volatile unsigned int*)(0x4270E094UL)) -#define bFM3_MFS7_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) -#define bFM3_MFS7_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM3_MFS7_UART_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_UART_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_UART_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_UART_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_UART_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM3_MFS7_UART_SSR_PE *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM3_MFS7_UART_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_UART_RDR_AD *((volatile unsigned int*)(0x4270E120UL)) -#define bFM3_MFS7_UART_TDR_AD *((volatile unsigned int*)(0x4270E120UL)) -#define bFM3_MFS7_UART_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_UART_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_UART_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_UART_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_UART_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_UART_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_UART_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_UART_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_UART_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_UART_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_UART_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_UART_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_UART_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) - -/* UART synchronous channel 7 registers */ -#define bFM3_MFS7_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270E004UL)) -#define bFM3_MFS7_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) -#define bFM3_MFS7_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM3_MFS7_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM3_MFS7_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM3_MFS7_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270E034UL)) -#define bFM3_MFS7_CSIO_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM3_MFS7_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_CSIO_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL)) -#define bFM3_MFS7_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL)) - -/* UART LIN channel 7 registers */ -#define bFM3_MFS7_LIN_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_LIN_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM3_MFS7_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM3_MFS7_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM3_MFS7_LIN_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_LIN_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_LIN_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_LIN_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_LIN_SCR_LBR *((volatile unsigned int*)(0x4270E034UL)) -#define bFM3_MFS7_LIN_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) -#define bFM3_MFS7_LIN_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_LIN_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_LIN_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM3_MFS7_LIN_SSR_LBD *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM3_MFS7_LIN_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_LIN_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) -#define bFM3_MFS7_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_LIN_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_LIN_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_LIN_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL)) -#define bFM3_MFS7_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL)) -#define bFM3_MFS7_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL)) - -/* I2C channel 7 registers */ -#define bFM3_MFS7_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270E000UL)) -#define bFM3_MFS7_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270E004UL)) -#define bFM3_MFS7_I2C_SMR_TIE *((volatile unsigned int*)(0x4270E008UL)) -#define bFM3_MFS7_I2C_SMR_RIE *((volatile unsigned int*)(0x4270E00CUL)) -#define bFM3_MFS7_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) -#define bFM3_MFS7_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) -#define bFM3_MFS7_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) -#define bFM3_MFS7_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) -#define bFM3_MFS7_I2C_IBCR_INT *((volatile unsigned int*)(0x4270E020UL)) -#define bFM3_MFS7_I2C_IBCR_BER *((volatile unsigned int*)(0x4270E024UL)) -#define bFM3_MFS7_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270E028UL)) -#define bFM3_MFS7_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270E02CUL)) -#define bFM3_MFS7_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270E030UL)) -#define bFM3_MFS7_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270E034UL)) -#define bFM3_MFS7_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270E038UL)) -#define bFM3_MFS7_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270E03CUL)) -#define bFM3_MFS7_I2C_IBSR_BB *((volatile unsigned int*)(0x4270E080UL)) -#define bFM3_MFS7_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270E084UL)) -#define bFM3_MFS7_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270E088UL)) -#define bFM3_MFS7_I2C_IBSR_AL *((volatile unsigned int*)(0x4270E08CUL)) -#define bFM3_MFS7_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270E090UL)) -#define bFM3_MFS7_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270E094UL)) -#define bFM3_MFS7_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270E098UL)) -#define bFM3_MFS7_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270E09CUL)) -#define bFM3_MFS7_I2C_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) -#define bFM3_MFS7_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) -#define bFM3_MFS7_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) -#define bFM3_MFS7_I2C_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) -#define bFM3_MFS7_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270E0B0UL)) -#define bFM3_MFS7_I2C_SSR_DMA *((volatile unsigned int*)(0x4270E0B4UL)) -#define bFM3_MFS7_I2C_SSR_TSET *((volatile unsigned int*)(0x4270E0B8UL)) -#define bFM3_MFS7_I2C_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) -#define bFM3_MFS7_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270E200UL)) -#define bFM3_MFS7_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270E204UL)) -#define bFM3_MFS7_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270E208UL)) -#define bFM3_MFS7_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270E20CUL)) -#define bFM3_MFS7_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270E210UL)) -#define bFM3_MFS7_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270E214UL)) -#define bFM3_MFS7_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270E218UL)) -#define bFM3_MFS7_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270E21CUL)) -#define bFM3_MFS7_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270E220UL)) -#define bFM3_MFS7_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270E224UL)) -#define bFM3_MFS7_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270E228UL)) -#define bFM3_MFS7_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270E22CUL)) -#define bFM3_MFS7_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270E230UL)) -#define bFM3_MFS7_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270E234UL)) -#define bFM3_MFS7_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270E238UL)) -#define bFM3_MFS7_I2C_ISMK_EN *((volatile unsigned int*)(0x4270E23CUL)) -#define bFM3_MFS7_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_I2C_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_I2C_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_I2C_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) -#define bFM3_MFS7_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) -#define bFM3_MFS7_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) -#define bFM3_MFS7_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) -#define bFM3_MFS7_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) -#define bFM3_MFS7_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) -#define bFM3_MFS7_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) -#define bFM3_MFS7_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) -#define bFM3_MFS7_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) -#define bFM3_MFS7_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) -#define bFM3_MFS7_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) -#define bFM3_MFS7_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) -#define bFM3_MFS7_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) -#define bFM3_MFS7_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) -#define bFM3_MFS7_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) -#define bFM3_MFS7_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) -#define bFM3_MFS7_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) -#define bFM3_MFS7_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) -#define bFM3_MFS7_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) -#define bFM3_MFS7_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) -#define bFM3_MFS7_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) -#define bFM3_MFS7_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) -#define bFM3_MFS7_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) -#define bFM3_MFS7_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) -#define bFM3_MFS7_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) -#define bFM3_MFS7_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL)) -#define bFM3_MFS7_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL)) -#define bFM3_MFS7_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL)) - -/* CRC registers */ -#define bFM3_CRC_CRCCR_INIT *((volatile unsigned int*)(0x42720000UL)) -#define bFM3_CRC_CRCCR_CRC32 *((volatile unsigned int*)(0x42720004UL)) -#define bFM3_CRC_CRCCR_LTLEND *((volatile unsigned int*)(0x42720008UL)) -#define bFM3_CRC_CRCCR_LSBFST *((volatile unsigned int*)(0x4272000CUL)) -#define bFM3_CRC_CRCCR_CRCLTE *((volatile unsigned int*)(0x42720010UL)) -#define bFM3_CRC_CRCCR_CRCLSF *((volatile unsigned int*)(0x42720014UL)) -#define bFM3_CRC_CRCCR_FXOR *((volatile unsigned int*)(0x42720018UL)) - -/* Watch counter registers */ -#define bFM3_WC_WCRD_CTR0 *((volatile unsigned int*)(0x42740000UL)) -#define bFM3_WC_WCRD_CTR1 *((volatile unsigned int*)(0x42740004UL)) -#define bFM3_WC_WCRD_CTR2 *((volatile unsigned int*)(0x42740008UL)) -#define bFM3_WC_WCRD_CTR3 *((volatile unsigned int*)(0x4274000CUL)) -#define bFM3_WC_WCRD_CTR4 *((volatile unsigned int*)(0x42740010UL)) -#define bFM3_WC_WCRD_CTR5 *((volatile unsigned int*)(0x42740014UL)) -#define bFM3_WC_WCRL_RLC0 *((volatile unsigned int*)(0x42740020UL)) -#define bFM3_WC_WCRL_RLC1 *((volatile unsigned int*)(0x42740024UL)) -#define bFM3_WC_WCRL_RLC2 *((volatile unsigned int*)(0x42740028UL)) -#define bFM3_WC_WCRL_RLC3 *((volatile unsigned int*)(0x4274002CUL)) -#define bFM3_WC_WCRL_RLC4 *((volatile unsigned int*)(0x42740030UL)) -#define bFM3_WC_WCRL_RLC5 *((volatile unsigned int*)(0x42740034UL)) -#define bFM3_WC_WCCR_WCIF *((volatile unsigned int*)(0x42740040UL)) -#define bFM3_WC_WCCR_WCIE *((volatile unsigned int*)(0x42740044UL)) -#define bFM3_WC_WCCR_CS0 *((volatile unsigned int*)(0x42740048UL)) -#define bFM3_WC_WCCR_CS1 *((volatile unsigned int*)(0x4274004CUL)) -#define bFM3_WC_WCCR_WCOP *((volatile unsigned int*)(0x42740058UL)) -#define bFM3_WC_WCCR_WCEN *((volatile unsigned int*)(0x4274005CUL)) -#define bFM3_WC_CLK_SEL_SEL_IN *((volatile unsigned int*)(0x42740200UL)) -#define bFM3_WC_CLK_SEL_SEL_OUT *((volatile unsigned int*)(0x42740220UL)) -#define bFM3_WC_CLK_EN_CLK_EN *((volatile unsigned int*)(0x42740280UL)) -#define bFM3_WC_CLK_EN_CLK_EN_R *((volatile unsigned int*)(0x42740284UL)) - -/* External bus interface registers */ -#define bFM3_EXBUS_MODE0_WDTH0 *((volatile unsigned int*)(0x427E0000UL)) -#define bFM3_EXBUS_MODE0_WDTH1 *((volatile unsigned int*)(0x427E0004UL)) -#define bFM3_EXBUS_MODE0_RBMON *((volatile unsigned int*)(0x427E0008UL)) -#define bFM3_EXBUS_MODE0_WEOFF *((volatile unsigned int*)(0x427E000CUL)) -#define bFM3_EXBUS_MODE0_NAND *((volatile unsigned int*)(0x427E0010UL)) -#define bFM3_EXBUS_MODE0_PAGE *((volatile unsigned int*)(0x427E0014UL)) -#define bFM3_EXBUS_MODE0_TEST *((volatile unsigned int*)(0x427E0018UL)) -#define bFM3_EXBUS_MODE1_WDTH0 *((volatile unsigned int*)(0x427E0080UL)) -#define bFM3_EXBUS_MODE1_WDTH1 *((volatile unsigned int*)(0x427E0084UL)) -#define bFM3_EXBUS_MODE1_RBMON *((volatile unsigned int*)(0x427E0088UL)) -#define bFM3_EXBUS_MODE1_WEOFF *((volatile unsigned int*)(0x427E008CUL)) -#define bFM3_EXBUS_MODE1_NAND *((volatile unsigned int*)(0x427E0090UL)) -#define bFM3_EXBUS_MODE1_PAGE *((volatile unsigned int*)(0x427E0094UL)) -#define bFM3_EXBUS_MODE1_TEST *((volatile unsigned int*)(0x427E0098UL)) -#define bFM3_EXBUS_MODE2_WDTH0 *((volatile unsigned int*)(0x427E0100UL)) -#define bFM3_EXBUS_MODE2_WDTH1 *((volatile unsigned int*)(0x427E0104UL)) -#define bFM3_EXBUS_MODE2_RBMON *((volatile unsigned int*)(0x427E0108UL)) -#define bFM3_EXBUS_MODE2_WEOFF *((volatile unsigned int*)(0x427E010CUL)) -#define bFM3_EXBUS_MODE2_NAND *((volatile unsigned int*)(0x427E0110UL)) -#define bFM3_EXBUS_MODE2_PAGE *((volatile unsigned int*)(0x427E0114UL)) -#define bFM3_EXBUS_MODE2_TEST *((volatile unsigned int*)(0x427E0118UL)) -#define bFM3_EXBUS_MODE3_WDTH0 *((volatile unsigned int*)(0x427E0180UL)) -#define bFM3_EXBUS_MODE3_WDTH1 *((volatile unsigned int*)(0x427E0184UL)) -#define bFM3_EXBUS_MODE3_RBMON *((volatile unsigned int*)(0x427E0188UL)) -#define bFM3_EXBUS_MODE3_WEOFF *((volatile unsigned int*)(0x427E018CUL)) -#define bFM3_EXBUS_MODE3_NAND *((volatile unsigned int*)(0x427E0190UL)) -#define bFM3_EXBUS_MODE3_PAGE *((volatile unsigned int*)(0x427E0194UL)) -#define bFM3_EXBUS_MODE3_TEST *((volatile unsigned int*)(0x427E0198UL)) -#define bFM3_EXBUS_MODE4_WDTH0 *((volatile unsigned int*)(0x427E0200UL)) -#define bFM3_EXBUS_MODE4_WDTH1 *((volatile unsigned int*)(0x427E0204UL)) -#define bFM3_EXBUS_MODE4_RBMON *((volatile unsigned int*)(0x427E0208UL)) -#define bFM3_EXBUS_MODE4_WEOFF *((volatile unsigned int*)(0x427E020CUL)) -#define bFM3_EXBUS_MODE4_NAND *((volatile unsigned int*)(0x427E0210UL)) -#define bFM3_EXBUS_MODE4_PAGE *((volatile unsigned int*)(0x427E0214UL)) -#define bFM3_EXBUS_MODE4_TEST *((volatile unsigned int*)(0x427E0218UL)) -#define bFM3_EXBUS_MODE5_WDTH0 *((volatile unsigned int*)(0x427E0280UL)) -#define bFM3_EXBUS_MODE5_WDTH1 *((volatile unsigned int*)(0x427E0284UL)) -#define bFM3_EXBUS_MODE5_RBMON *((volatile unsigned int*)(0x427E0288UL)) -#define bFM3_EXBUS_MODE5_WEOFF *((volatile unsigned int*)(0x427E028CUL)) -#define bFM3_EXBUS_MODE5_NAND *((volatile unsigned int*)(0x427E0290UL)) -#define bFM3_EXBUS_MODE5_PAGE *((volatile unsigned int*)(0x427E0294UL)) -#define bFM3_EXBUS_MODE5_TEST *((volatile unsigned int*)(0x427E0298UL)) -#define bFM3_EXBUS_MODE6_WDTH0 *((volatile unsigned int*)(0x427E0300UL)) -#define bFM3_EXBUS_MODE6_WDTH1 *((volatile unsigned int*)(0x427E0304UL)) -#define bFM3_EXBUS_MODE6_RBMON *((volatile unsigned int*)(0x427E0308UL)) -#define bFM3_EXBUS_MODE6_WEOFF *((volatile unsigned int*)(0x427E030CUL)) -#define bFM3_EXBUS_MODE6_NAND *((volatile unsigned int*)(0x427E0310UL)) -#define bFM3_EXBUS_MODE6_PAGE *((volatile unsigned int*)(0x427E0314UL)) -#define bFM3_EXBUS_MODE6_TEST *((volatile unsigned int*)(0x427E0318UL)) -#define bFM3_EXBUS_MODE7_WDTH0 *((volatile unsigned int*)(0x427E0380UL)) -#define bFM3_EXBUS_MODE7_WDTH1 *((volatile unsigned int*)(0x427E0384UL)) -#define bFM3_EXBUS_MODE7_RBMON *((volatile unsigned int*)(0x427E0388UL)) -#define bFM3_EXBUS_MODE7_WEOFF *((volatile unsigned int*)(0x427E038CUL)) -#define bFM3_EXBUS_MODE7_NAND *((volatile unsigned int*)(0x427E0390UL)) -#define bFM3_EXBUS_MODE7_PAGE *((volatile unsigned int*)(0x427E0394UL)) -#define bFM3_EXBUS_MODE7_TEST *((volatile unsigned int*)(0x427E0398UL)) -#define bFM3_EXBUS_TIM0_RACC0 *((volatile unsigned int*)(0x427E0400UL)) -#define bFM3_EXBUS_TIM0_RACC1 *((volatile unsigned int*)(0x427E0404UL)) -#define bFM3_EXBUS_TIM0_RACC2 *((volatile unsigned int*)(0x427E0408UL)) -#define bFM3_EXBUS_TIM0_RACC3 *((volatile unsigned int*)(0x427E040CUL)) -#define bFM3_EXBUS_TIM0_RADC0 *((volatile unsigned int*)(0x427E0410UL)) -#define bFM3_EXBUS_TIM0_RADC1 *((volatile unsigned int*)(0x427E0414UL)) -#define bFM3_EXBUS_TIM0_RADC2 *((volatile unsigned int*)(0x427E0418UL)) -#define bFM3_EXBUS_TIM0_RADC3 *((volatile unsigned int*)(0x427E041CUL)) -#define bFM3_EXBUS_TIM0_FRADC0 *((volatile unsigned int*)(0x427E0420UL)) -#define bFM3_EXBUS_TIM0_FRADC1 *((volatile unsigned int*)(0x427E0424UL)) -#define bFM3_EXBUS_TIM0_FRADC2 *((volatile unsigned int*)(0x427E0428UL)) -#define bFM3_EXBUS_TIM0_FRADC3 *((volatile unsigned int*)(0x427E042CUL)) -#define bFM3_EXBUS_TIM0_RIDLC0 *((volatile unsigned int*)(0x427E0430UL)) -#define bFM3_EXBUS_TIM0_RIDLC1 *((volatile unsigned int*)(0x427E0434UL)) -#define bFM3_EXBUS_TIM0_RIDLC2 *((volatile unsigned int*)(0x427E0438UL)) -#define bFM3_EXBUS_TIM0_RIDLC3 *((volatile unsigned int*)(0x427E043CUL)) -#define bFM3_EXBUS_TIM0_WACC0 *((volatile unsigned int*)(0x427E0440UL)) -#define bFM3_EXBUS_TIM0_WACC1 *((volatile unsigned int*)(0x427E0444UL)) -#define bFM3_EXBUS_TIM0_WACC2 *((volatile unsigned int*)(0x427E0448UL)) -#define bFM3_EXBUS_TIM0_WACC3 *((volatile unsigned int*)(0x427E044CUL)) -#define bFM3_EXBUS_TIM0_WADC0 *((volatile unsigned int*)(0x427E0450UL)) -#define bFM3_EXBUS_TIM0_WADC1 *((volatile unsigned int*)(0x427E0454UL)) -#define bFM3_EXBUS_TIM0_WADC2 *((volatile unsigned int*)(0x427E0458UL)) -#define bFM3_EXBUS_TIM0_WADC3 *((volatile unsigned int*)(0x427E045CUL)) -#define bFM3_EXBUS_TIM0_WWEC0 *((volatile unsigned int*)(0x427E0460UL)) -#define bFM3_EXBUS_TIM0_WWEC1 *((volatile unsigned int*)(0x427E0464UL)) -#define bFM3_EXBUS_TIM0_WWEC2 *((volatile unsigned int*)(0x427E0468UL)) -#define bFM3_EXBUS_TIM0_WWEC3 *((volatile unsigned int*)(0x427E046CUL)) -#define bFM3_EXBUS_TIM0_WIDLC0 *((volatile unsigned int*)(0x427E0470UL)) -#define bFM3_EXBUS_TIM0_WIDLC1 *((volatile unsigned int*)(0x427E0474UL)) -#define bFM3_EXBUS_TIM0_WIDLC2 *((volatile unsigned int*)(0x427E0478UL)) -#define bFM3_EXBUS_TIM0_WIDLC3 *((volatile unsigned int*)(0x427E047CUL)) -#define bFM3_EXBUS_TIM1_RACC0 *((volatile unsigned int*)(0x427E0480UL)) -#define bFM3_EXBUS_TIM1_RACC1 *((volatile unsigned int*)(0x427E0484UL)) -#define bFM3_EXBUS_TIM1_RACC2 *((volatile unsigned int*)(0x427E0488UL)) -#define bFM3_EXBUS_TIM1_RACC3 *((volatile unsigned int*)(0x427E048CUL)) -#define bFM3_EXBUS_TIM1_RADC0 *((volatile unsigned int*)(0x427E0490UL)) -#define bFM3_EXBUS_TIM1_RADC1 *((volatile unsigned int*)(0x427E0494UL)) -#define bFM3_EXBUS_TIM1_RADC2 *((volatile unsigned int*)(0x427E0498UL)) -#define bFM3_EXBUS_TIM1_RADC3 *((volatile unsigned int*)(0x427E049CUL)) -#define bFM3_EXBUS_TIM1_FRADC0 *((volatile unsigned int*)(0x427E04A0UL)) -#define bFM3_EXBUS_TIM1_FRADC1 *((volatile unsigned int*)(0x427E04A4UL)) -#define bFM3_EXBUS_TIM1_FRADC2 *((volatile unsigned int*)(0x427E04A8UL)) -#define bFM3_EXBUS_TIM1_FRADC3 *((volatile unsigned int*)(0x427E04ACUL)) -#define bFM3_EXBUS_TIM1_RIDLC0 *((volatile unsigned int*)(0x427E04B0UL)) -#define bFM3_EXBUS_TIM1_RIDLC1 *((volatile unsigned int*)(0x427E04B4UL)) -#define bFM3_EXBUS_TIM1_RIDLC2 *((volatile unsigned int*)(0x427E04B8UL)) -#define bFM3_EXBUS_TIM1_RIDLC3 *((volatile unsigned int*)(0x427E04BCUL)) -#define bFM3_EXBUS_TIM1_WACC0 *((volatile unsigned int*)(0x427E04C0UL)) -#define bFM3_EXBUS_TIM1_WACC1 *((volatile unsigned int*)(0x427E04C4UL)) -#define bFM3_EXBUS_TIM1_WACC2 *((volatile unsigned int*)(0x427E04C8UL)) -#define bFM3_EXBUS_TIM1_WACC3 *((volatile unsigned int*)(0x427E04CCUL)) -#define bFM3_EXBUS_TIM1_WADC0 *((volatile unsigned int*)(0x427E04D0UL)) -#define bFM3_EXBUS_TIM1_WADC1 *((volatile unsigned int*)(0x427E04D4UL)) -#define bFM3_EXBUS_TIM1_WADC2 *((volatile unsigned int*)(0x427E04D8UL)) -#define bFM3_EXBUS_TIM1_WADC3 *((volatile unsigned int*)(0x427E04DCUL)) -#define bFM3_EXBUS_TIM1_WWEC0 *((volatile unsigned int*)(0x427E04E0UL)) -#define bFM3_EXBUS_TIM1_WWEC1 *((volatile unsigned int*)(0x427E04E4UL)) -#define bFM3_EXBUS_TIM1_WWEC2 *((volatile unsigned int*)(0x427E04E8UL)) -#define bFM3_EXBUS_TIM1_WWEC3 *((volatile unsigned int*)(0x427E04ECUL)) -#define bFM3_EXBUS_TIM1_WIDLC0 *((volatile unsigned int*)(0x427E04F0UL)) -#define bFM3_EXBUS_TIM1_WIDLC1 *((volatile unsigned int*)(0x427E04F4UL)) -#define bFM3_EXBUS_TIM1_WIDLC2 *((volatile unsigned int*)(0x427E04F8UL)) -#define bFM3_EXBUS_TIM1_WIDLC3 *((volatile unsigned int*)(0x427E04FCUL)) -#define bFM3_EXBUS_TIM2_RACC0 *((volatile unsigned int*)(0x427E0500UL)) -#define bFM3_EXBUS_TIM2_RACC1 *((volatile unsigned int*)(0x427E0504UL)) -#define bFM3_EXBUS_TIM2_RACC2 *((volatile unsigned int*)(0x427E0508UL)) -#define bFM3_EXBUS_TIM2_RACC3 *((volatile unsigned int*)(0x427E050CUL)) -#define bFM3_EXBUS_TIM2_RADC0 *((volatile unsigned int*)(0x427E0510UL)) -#define bFM3_EXBUS_TIM2_RADC1 *((volatile unsigned int*)(0x427E0514UL)) -#define bFM3_EXBUS_TIM2_RADC2 *((volatile unsigned int*)(0x427E0518UL)) -#define bFM3_EXBUS_TIM2_RADC3 *((volatile unsigned int*)(0x427E051CUL)) -#define bFM3_EXBUS_TIM2_FRADC0 *((volatile unsigned int*)(0x427E0520UL)) -#define bFM3_EXBUS_TIM2_FRADC1 *((volatile unsigned int*)(0x427E0524UL)) -#define bFM3_EXBUS_TIM2_FRADC2 *((volatile unsigned int*)(0x427E0528UL)) -#define bFM3_EXBUS_TIM2_FRADC3 *((volatile unsigned int*)(0x427E052CUL)) -#define bFM3_EXBUS_TIM2_RIDLC0 *((volatile unsigned int*)(0x427E0530UL)) -#define bFM3_EXBUS_TIM2_RIDLC1 *((volatile unsigned int*)(0x427E0534UL)) -#define bFM3_EXBUS_TIM2_RIDLC2 *((volatile unsigned int*)(0x427E0538UL)) -#define bFM3_EXBUS_TIM2_RIDLC3 *((volatile unsigned int*)(0x427E053CUL)) -#define bFM3_EXBUS_TIM2_WACC0 *((volatile unsigned int*)(0x427E0540UL)) -#define bFM3_EXBUS_TIM2_WACC1 *((volatile unsigned int*)(0x427E0544UL)) -#define bFM3_EXBUS_TIM2_WACC2 *((volatile unsigned int*)(0x427E0548UL)) -#define bFM3_EXBUS_TIM2_WACC3 *((volatile unsigned int*)(0x427E054CUL)) -#define bFM3_EXBUS_TIM2_WADC0 *((volatile unsigned int*)(0x427E0550UL)) -#define bFM3_EXBUS_TIM2_WADC1 *((volatile unsigned int*)(0x427E0554UL)) -#define bFM3_EXBUS_TIM2_WADC2 *((volatile unsigned int*)(0x427E0558UL)) -#define bFM3_EXBUS_TIM2_WADC3 *((volatile unsigned int*)(0x427E055CUL)) -#define bFM3_EXBUS_TIM2_WWEC0 *((volatile unsigned int*)(0x427E0560UL)) -#define bFM3_EXBUS_TIM2_WWEC1 *((volatile unsigned int*)(0x427E0564UL)) -#define bFM3_EXBUS_TIM2_WWEC2 *((volatile unsigned int*)(0x427E0568UL)) -#define bFM3_EXBUS_TIM2_WWEC3 *((volatile unsigned int*)(0x427E056CUL)) -#define bFM3_EXBUS_TIM2_WIDLC0 *((volatile unsigned int*)(0x427E0570UL)) -#define bFM3_EXBUS_TIM2_WIDLC1 *((volatile unsigned int*)(0x427E0574UL)) -#define bFM3_EXBUS_TIM2_WIDLC2 *((volatile unsigned int*)(0x427E0578UL)) -#define bFM3_EXBUS_TIM2_WIDLC3 *((volatile unsigned int*)(0x427E057CUL)) -#define bFM3_EXBUS_TIM3_RACC0 *((volatile unsigned int*)(0x427E0580UL)) -#define bFM3_EXBUS_TIM3_RACC1 *((volatile unsigned int*)(0x427E0584UL)) -#define bFM3_EXBUS_TIM3_RACC2 *((volatile unsigned int*)(0x427E0588UL)) -#define bFM3_EXBUS_TIM3_RACC3 *((volatile unsigned int*)(0x427E058CUL)) -#define bFM3_EXBUS_TIM3_RADC0 *((volatile unsigned int*)(0x427E0590UL)) -#define bFM3_EXBUS_TIM3_RADC1 *((volatile unsigned int*)(0x427E0594UL)) -#define bFM3_EXBUS_TIM3_RADC2 *((volatile unsigned int*)(0x427E0598UL)) -#define bFM3_EXBUS_TIM3_RADC3 *((volatile unsigned int*)(0x427E059CUL)) -#define bFM3_EXBUS_TIM3_FRADC0 *((volatile unsigned int*)(0x427E05A0UL)) -#define bFM3_EXBUS_TIM3_FRADC1 *((volatile unsigned int*)(0x427E05A4UL)) -#define bFM3_EXBUS_TIM3_FRADC2 *((volatile unsigned int*)(0x427E05A8UL)) -#define bFM3_EXBUS_TIM3_FRADC3 *((volatile unsigned int*)(0x427E05ACUL)) -#define bFM3_EXBUS_TIM3_RIDLC0 *((volatile unsigned int*)(0x427E05B0UL)) -#define bFM3_EXBUS_TIM3_RIDLC1 *((volatile unsigned int*)(0x427E05B4UL)) -#define bFM3_EXBUS_TIM3_RIDLC2 *((volatile unsigned int*)(0x427E05B8UL)) -#define bFM3_EXBUS_TIM3_RIDLC3 *((volatile unsigned int*)(0x427E05BCUL)) -#define bFM3_EXBUS_TIM3_WACC0 *((volatile unsigned int*)(0x427E05C0UL)) -#define bFM3_EXBUS_TIM3_WACC1 *((volatile unsigned int*)(0x427E05C4UL)) -#define bFM3_EXBUS_TIM3_WACC2 *((volatile unsigned int*)(0x427E05C8UL)) -#define bFM3_EXBUS_TIM3_WACC3 *((volatile unsigned int*)(0x427E05CCUL)) -#define bFM3_EXBUS_TIM3_WADC0 *((volatile unsigned int*)(0x427E05D0UL)) -#define bFM3_EXBUS_TIM3_WADC1 *((volatile unsigned int*)(0x427E05D4UL)) -#define bFM3_EXBUS_TIM3_WADC2 *((volatile unsigned int*)(0x427E05D8UL)) -#define bFM3_EXBUS_TIM3_WADC3 *((volatile unsigned int*)(0x427E05DCUL)) -#define bFM3_EXBUS_TIM3_WWEC0 *((volatile unsigned int*)(0x427E05E0UL)) -#define bFM3_EXBUS_TIM3_WWEC1 *((volatile unsigned int*)(0x427E05E4UL)) -#define bFM3_EXBUS_TIM3_WWEC2 *((volatile unsigned int*)(0x427E05E8UL)) -#define bFM3_EXBUS_TIM3_WWEC3 *((volatile unsigned int*)(0x427E05ECUL)) -#define bFM3_EXBUS_TIM3_WIDLC0 *((volatile unsigned int*)(0x427E05F0UL)) -#define bFM3_EXBUS_TIM3_WIDLC1 *((volatile unsigned int*)(0x427E05F4UL)) -#define bFM3_EXBUS_TIM3_WIDLC2 *((volatile unsigned int*)(0x427E05F8UL)) -#define bFM3_EXBUS_TIM3_WIDLC3 *((volatile unsigned int*)(0x427E05FCUL)) -#define bFM3_EXBUS_TIM4_RACC0 *((volatile unsigned int*)(0x427E0600UL)) -#define bFM3_EXBUS_TIM4_RACC1 *((volatile unsigned int*)(0x427E0604UL)) -#define bFM3_EXBUS_TIM4_RACC2 *((volatile unsigned int*)(0x427E0608UL)) -#define bFM3_EXBUS_TIM4_RACC3 *((volatile unsigned int*)(0x427E060CUL)) -#define bFM3_EXBUS_TIM4_RADC0 *((volatile unsigned int*)(0x427E0610UL)) -#define bFM3_EXBUS_TIM4_RADC1 *((volatile unsigned int*)(0x427E0614UL)) -#define bFM3_EXBUS_TIM4_RADC2 *((volatile unsigned int*)(0x427E0618UL)) -#define bFM3_EXBUS_TIM4_RADC3 *((volatile unsigned int*)(0x427E061CUL)) -#define bFM3_EXBUS_TIM4_FRADC0 *((volatile unsigned int*)(0x427E0620UL)) -#define bFM3_EXBUS_TIM4_FRADC1 *((volatile unsigned int*)(0x427E0624UL)) -#define bFM3_EXBUS_TIM4_FRADC2 *((volatile unsigned int*)(0x427E0628UL)) -#define bFM3_EXBUS_TIM4_FRADC3 *((volatile unsigned int*)(0x427E062CUL)) -#define bFM3_EXBUS_TIM4_RIDLC0 *((volatile unsigned int*)(0x427E0630UL)) -#define bFM3_EXBUS_TIM4_RIDLC1 *((volatile unsigned int*)(0x427E0634UL)) -#define bFM3_EXBUS_TIM4_RIDLC2 *((volatile unsigned int*)(0x427E0638UL)) -#define bFM3_EXBUS_TIM4_RIDLC3 *((volatile unsigned int*)(0x427E063CUL)) -#define bFM3_EXBUS_TIM4_WACC0 *((volatile unsigned int*)(0x427E0640UL)) -#define bFM3_EXBUS_TIM4_WACC1 *((volatile unsigned int*)(0x427E0644UL)) -#define bFM3_EXBUS_TIM4_WACC2 *((volatile unsigned int*)(0x427E0648UL)) -#define bFM3_EXBUS_TIM4_WACC3 *((volatile unsigned int*)(0x427E064CUL)) -#define bFM3_EXBUS_TIM4_WADC0 *((volatile unsigned int*)(0x427E0650UL)) -#define bFM3_EXBUS_TIM4_WADC1 *((volatile unsigned int*)(0x427E0654UL)) -#define bFM3_EXBUS_TIM4_WADC2 *((volatile unsigned int*)(0x427E0658UL)) -#define bFM3_EXBUS_TIM4_WADC3 *((volatile unsigned int*)(0x427E065CUL)) -#define bFM3_EXBUS_TIM4_WWEC0 *((volatile unsigned int*)(0x427E0660UL)) -#define bFM3_EXBUS_TIM4_WWEC1 *((volatile unsigned int*)(0x427E0664UL)) -#define bFM3_EXBUS_TIM4_WWEC2 *((volatile unsigned int*)(0x427E0668UL)) -#define bFM3_EXBUS_TIM4_WWEC3 *((volatile unsigned int*)(0x427E066CUL)) -#define bFM3_EXBUS_TIM4_WIDLC0 *((volatile unsigned int*)(0x427E0670UL)) -#define bFM3_EXBUS_TIM4_WIDLC1 *((volatile unsigned int*)(0x427E0674UL)) -#define bFM3_EXBUS_TIM4_WIDLC2 *((volatile unsigned int*)(0x427E0678UL)) -#define bFM3_EXBUS_TIM4_WIDLC3 *((volatile unsigned int*)(0x427E067CUL)) -#define bFM3_EXBUS_TIM5_RACC0 *((volatile unsigned int*)(0x427E0680UL)) -#define bFM3_EXBUS_TIM5_RACC1 *((volatile unsigned int*)(0x427E0684UL)) -#define bFM3_EXBUS_TIM5_RACC2 *((volatile unsigned int*)(0x427E0688UL)) -#define bFM3_EXBUS_TIM5_RACC3 *((volatile unsigned int*)(0x427E068CUL)) -#define bFM3_EXBUS_TIM5_RADC0 *((volatile unsigned int*)(0x427E0690UL)) -#define bFM3_EXBUS_TIM5_RADC1 *((volatile unsigned int*)(0x427E0694UL)) -#define bFM3_EXBUS_TIM5_RADC2 *((volatile unsigned int*)(0x427E0698UL)) -#define bFM3_EXBUS_TIM5_RADC3 *((volatile unsigned int*)(0x427E069CUL)) -#define bFM3_EXBUS_TIM5_FRADC0 *((volatile unsigned int*)(0x427E06A0UL)) -#define bFM3_EXBUS_TIM5_FRADC1 *((volatile unsigned int*)(0x427E06A4UL)) -#define bFM3_EXBUS_TIM5_FRADC2 *((volatile unsigned int*)(0x427E06A8UL)) -#define bFM3_EXBUS_TIM5_FRADC3 *((volatile unsigned int*)(0x427E06ACUL)) -#define bFM3_EXBUS_TIM5_RIDLC0 *((volatile unsigned int*)(0x427E06B0UL)) -#define bFM3_EXBUS_TIM5_RIDLC1 *((volatile unsigned int*)(0x427E06B4UL)) -#define bFM3_EXBUS_TIM5_RIDLC2 *((volatile unsigned int*)(0x427E06B8UL)) -#define bFM3_EXBUS_TIM5_RIDLC3 *((volatile unsigned int*)(0x427E06BCUL)) -#define bFM3_EXBUS_TIM5_WACC0 *((volatile unsigned int*)(0x427E06C0UL)) -#define bFM3_EXBUS_TIM5_WACC1 *((volatile unsigned int*)(0x427E06C4UL)) -#define bFM3_EXBUS_TIM5_WACC2 *((volatile unsigned int*)(0x427E06C8UL)) -#define bFM3_EXBUS_TIM5_WACC3 *((volatile unsigned int*)(0x427E06CCUL)) -#define bFM3_EXBUS_TIM5_WADC0 *((volatile unsigned int*)(0x427E06D0UL)) -#define bFM3_EXBUS_TIM5_WADC1 *((volatile unsigned int*)(0x427E06D4UL)) -#define bFM3_EXBUS_TIM5_WADC2 *((volatile unsigned int*)(0x427E06D8UL)) -#define bFM3_EXBUS_TIM5_WADC3 *((volatile unsigned int*)(0x427E06DCUL)) -#define bFM3_EXBUS_TIM5_WWEC0 *((volatile unsigned int*)(0x427E06E0UL)) -#define bFM3_EXBUS_TIM5_WWEC1 *((volatile unsigned int*)(0x427E06E4UL)) -#define bFM3_EXBUS_TIM5_WWEC2 *((volatile unsigned int*)(0x427E06E8UL)) -#define bFM3_EXBUS_TIM5_WWEC3 *((volatile unsigned int*)(0x427E06ECUL)) -#define bFM3_EXBUS_TIM5_WIDLC0 *((volatile unsigned int*)(0x427E06F0UL)) -#define bFM3_EXBUS_TIM5_WIDLC1 *((volatile unsigned int*)(0x427E06F4UL)) -#define bFM3_EXBUS_TIM5_WIDLC2 *((volatile unsigned int*)(0x427E06F8UL)) -#define bFM3_EXBUS_TIM5_WIDLC3 *((volatile unsigned int*)(0x427E06FCUL)) -#define bFM3_EXBUS_TIM6_RACC0 *((volatile unsigned int*)(0x427E0700UL)) -#define bFM3_EXBUS_TIM6_RACC1 *((volatile unsigned int*)(0x427E0704UL)) -#define bFM3_EXBUS_TIM6_RACC2 *((volatile unsigned int*)(0x427E0708UL)) -#define bFM3_EXBUS_TIM6_RACC3 *((volatile unsigned int*)(0x427E070CUL)) -#define bFM3_EXBUS_TIM6_RADC0 *((volatile unsigned int*)(0x427E0710UL)) -#define bFM3_EXBUS_TIM6_RADC1 *((volatile unsigned int*)(0x427E0714UL)) -#define bFM3_EXBUS_TIM6_RADC2 *((volatile unsigned int*)(0x427E0718UL)) -#define bFM3_EXBUS_TIM6_RADC3 *((volatile unsigned int*)(0x427E071CUL)) -#define bFM3_EXBUS_TIM6_FRADC0 *((volatile unsigned int*)(0x427E0720UL)) -#define bFM3_EXBUS_TIM6_FRADC1 *((volatile unsigned int*)(0x427E0724UL)) -#define bFM3_EXBUS_TIM6_FRADC2 *((volatile unsigned int*)(0x427E0728UL)) -#define bFM3_EXBUS_TIM6_FRADC3 *((volatile unsigned int*)(0x427E072CUL)) -#define bFM3_EXBUS_TIM6_RIDLC0 *((volatile unsigned int*)(0x427E0730UL)) -#define bFM3_EXBUS_TIM6_RIDLC1 *((volatile unsigned int*)(0x427E0734UL)) -#define bFM3_EXBUS_TIM6_RIDLC2 *((volatile unsigned int*)(0x427E0738UL)) -#define bFM3_EXBUS_TIM6_RIDLC3 *((volatile unsigned int*)(0x427E073CUL)) -#define bFM3_EXBUS_TIM6_WACC0 *((volatile unsigned int*)(0x427E0740UL)) -#define bFM3_EXBUS_TIM6_WACC1 *((volatile unsigned int*)(0x427E0744UL)) -#define bFM3_EXBUS_TIM6_WACC2 *((volatile unsigned int*)(0x427E0748UL)) -#define bFM3_EXBUS_TIM6_WACC3 *((volatile unsigned int*)(0x427E074CUL)) -#define bFM3_EXBUS_TIM6_WADC0 *((volatile unsigned int*)(0x427E0750UL)) -#define bFM3_EXBUS_TIM6_WADC1 *((volatile unsigned int*)(0x427E0754UL)) -#define bFM3_EXBUS_TIM6_WADC2 *((volatile unsigned int*)(0x427E0758UL)) -#define bFM3_EXBUS_TIM6_WADC3 *((volatile unsigned int*)(0x427E075CUL)) -#define bFM3_EXBUS_TIM6_WWEC0 *((volatile unsigned int*)(0x427E0760UL)) -#define bFM3_EXBUS_TIM6_WWEC1 *((volatile unsigned int*)(0x427E0764UL)) -#define bFM3_EXBUS_TIM6_WWEC2 *((volatile unsigned int*)(0x427E0768UL)) -#define bFM3_EXBUS_TIM6_WWEC3 *((volatile unsigned int*)(0x427E076CUL)) -#define bFM3_EXBUS_TIM6_WIDLC0 *((volatile unsigned int*)(0x427E0770UL)) -#define bFM3_EXBUS_TIM6_WIDLC1 *((volatile unsigned int*)(0x427E0774UL)) -#define bFM3_EXBUS_TIM6_WIDLC2 *((volatile unsigned int*)(0x427E0778UL)) -#define bFM3_EXBUS_TIM6_WIDLC3 *((volatile unsigned int*)(0x427E077CUL)) -#define bFM3_EXBUS_TIM7_RACC0 *((volatile unsigned int*)(0x427E0780UL)) -#define bFM3_EXBUS_TIM7_RACC1 *((volatile unsigned int*)(0x427E0784UL)) -#define bFM3_EXBUS_TIM7_RACC2 *((volatile unsigned int*)(0x427E0788UL)) -#define bFM3_EXBUS_TIM7_RACC3 *((volatile unsigned int*)(0x427E078CUL)) -#define bFM3_EXBUS_TIM7_RADC0 *((volatile unsigned int*)(0x427E0790UL)) -#define bFM3_EXBUS_TIM7_RADC1 *((volatile unsigned int*)(0x427E0794UL)) -#define bFM3_EXBUS_TIM7_RADC2 *((volatile unsigned int*)(0x427E0798UL)) -#define bFM3_EXBUS_TIM7_RADC3 *((volatile unsigned int*)(0x427E079CUL)) -#define bFM3_EXBUS_TIM7_FRADC0 *((volatile unsigned int*)(0x427E07A0UL)) -#define bFM3_EXBUS_TIM7_FRADC1 *((volatile unsigned int*)(0x427E07A4UL)) -#define bFM3_EXBUS_TIM7_FRADC2 *((volatile unsigned int*)(0x427E07A8UL)) -#define bFM3_EXBUS_TIM7_FRADC3 *((volatile unsigned int*)(0x427E07ACUL)) -#define bFM3_EXBUS_TIM7_RIDLC0 *((volatile unsigned int*)(0x427E07B0UL)) -#define bFM3_EXBUS_TIM7_RIDLC1 *((volatile unsigned int*)(0x427E07B4UL)) -#define bFM3_EXBUS_TIM7_RIDLC2 *((volatile unsigned int*)(0x427E07B8UL)) -#define bFM3_EXBUS_TIM7_RIDLC3 *((volatile unsigned int*)(0x427E07BCUL)) -#define bFM3_EXBUS_TIM7_WACC0 *((volatile unsigned int*)(0x427E07C0UL)) -#define bFM3_EXBUS_TIM7_WACC1 *((volatile unsigned int*)(0x427E07C4UL)) -#define bFM3_EXBUS_TIM7_WACC2 *((volatile unsigned int*)(0x427E07C8UL)) -#define bFM3_EXBUS_TIM7_WACC3 *((volatile unsigned int*)(0x427E07CCUL)) -#define bFM3_EXBUS_TIM7_WADC0 *((volatile unsigned int*)(0x427E07D0UL)) -#define bFM3_EXBUS_TIM7_WADC1 *((volatile unsigned int*)(0x427E07D4UL)) -#define bFM3_EXBUS_TIM7_WADC2 *((volatile unsigned int*)(0x427E07D8UL)) -#define bFM3_EXBUS_TIM7_WADC3 *((volatile unsigned int*)(0x427E07DCUL)) -#define bFM3_EXBUS_TIM7_WWEC0 *((volatile unsigned int*)(0x427E07E0UL)) -#define bFM3_EXBUS_TIM7_WWEC1 *((volatile unsigned int*)(0x427E07E4UL)) -#define bFM3_EXBUS_TIM7_WWEC2 *((volatile unsigned int*)(0x427E07E8UL)) -#define bFM3_EXBUS_TIM7_WWEC3 *((volatile unsigned int*)(0x427E07ECUL)) -#define bFM3_EXBUS_TIM7_WIDLC0 *((volatile unsigned int*)(0x427E07F0UL)) -#define bFM3_EXBUS_TIM7_WIDLC1 *((volatile unsigned int*)(0x427E07F4UL)) -#define bFM3_EXBUS_TIM7_WIDLC2 *((volatile unsigned int*)(0x427E07F8UL)) -#define bFM3_EXBUS_TIM7_WIDLC3 *((volatile unsigned int*)(0x427E07FCUL)) -#define bFM3_EXBUS_AREA0_ADDR0 *((volatile unsigned int*)(0x427E0800UL)) -#define bFM3_EXBUS_AREA0_ADDR1 *((volatile unsigned int*)(0x427E0804UL)) -#define bFM3_EXBUS_AREA0_ADDR2 *((volatile unsigned int*)(0x427E0808UL)) -#define bFM3_EXBUS_AREA0_ADDR3 *((volatile unsigned int*)(0x427E080CUL)) -#define bFM3_EXBUS_AREA0_ADDR4 *((volatile unsigned int*)(0x427E0810UL)) -#define bFM3_EXBUS_AREA0_ADDR5 *((volatile unsigned int*)(0x427E0814UL)) -#define bFM3_EXBUS_AREA0_ADDR6 *((volatile unsigned int*)(0x427E0818UL)) -#define bFM3_EXBUS_AREA0_ADDR7 *((volatile unsigned int*)(0x427E081CUL)) -#define bFM3_EXBUS_AREA0_MASK0 *((volatile unsigned int*)(0x427E0840UL)) -#define bFM3_EXBUS_AREA0_MASK1 *((volatile unsigned int*)(0x427E0844UL)) -#define bFM3_EXBUS_AREA0_MASK2 *((volatile unsigned int*)(0x427E0848UL)) -#define bFM3_EXBUS_AREA0_MASK3 *((volatile unsigned int*)(0x427E084CUL)) -#define bFM3_EXBUS_AREA0_MASK4 *((volatile unsigned int*)(0x427E0850UL)) -#define bFM3_EXBUS_AREA0_MASK5 *((volatile unsigned int*)(0x427E0854UL)) -#define bFM3_EXBUS_AREA0_MASK6 *((volatile unsigned int*)(0x427E0858UL)) -#define bFM3_EXBUS_AREA1_ADDR0 *((volatile unsigned int*)(0x427E0880UL)) -#define bFM3_EXBUS_AREA1_ADDR1 *((volatile unsigned int*)(0x427E0884UL)) -#define bFM3_EXBUS_AREA1_ADDR2 *((volatile unsigned int*)(0x427E0888UL)) -#define bFM3_EXBUS_AREA1_ADDR3 *((volatile unsigned int*)(0x427E088CUL)) -#define bFM3_EXBUS_AREA1_ADDR4 *((volatile unsigned int*)(0x427E0890UL)) -#define bFM3_EXBUS_AREA1_ADDR5 *((volatile unsigned int*)(0x427E0894UL)) -#define bFM3_EXBUS_AREA1_ADDR6 *((volatile unsigned int*)(0x427E0898UL)) -#define bFM3_EXBUS_AREA1_ADDR7 *((volatile unsigned int*)(0x427E089CUL)) -#define bFM3_EXBUS_AREA1_MASK0 *((volatile unsigned int*)(0x427E08C0UL)) -#define bFM3_EXBUS_AREA1_MASK1 *((volatile unsigned int*)(0x427E08C4UL)) -#define bFM3_EXBUS_AREA1_MASK2 *((volatile unsigned int*)(0x427E08C8UL)) -#define bFM3_EXBUS_AREA1_MASK3 *((volatile unsigned int*)(0x427E08CCUL)) -#define bFM3_EXBUS_AREA1_MASK4 *((volatile unsigned int*)(0x427E08D0UL)) -#define bFM3_EXBUS_AREA1_MASK5 *((volatile unsigned int*)(0x427E08D4UL)) -#define bFM3_EXBUS_AREA1_MASK6 *((volatile unsigned int*)(0x427E08D8UL)) -#define bFM3_EXBUS_AREA2_ADDR0 *((volatile unsigned int*)(0x427E0900UL)) -#define bFM3_EXBUS_AREA2_ADDR1 *((volatile unsigned int*)(0x427E0904UL)) -#define bFM3_EXBUS_AREA2_ADDR2 *((volatile unsigned int*)(0x427E0908UL)) -#define bFM3_EXBUS_AREA2_ADDR3 *((volatile unsigned int*)(0x427E090CUL)) -#define bFM3_EXBUS_AREA2_ADDR4 *((volatile unsigned int*)(0x427E0910UL)) -#define bFM3_EXBUS_AREA2_ADDR5 *((volatile unsigned int*)(0x427E0914UL)) -#define bFM3_EXBUS_AREA2_ADDR6 *((volatile unsigned int*)(0x427E0918UL)) -#define bFM3_EXBUS_AREA2_ADDR7 *((volatile unsigned int*)(0x427E091CUL)) -#define bFM3_EXBUS_AREA2_MASK0 *((volatile unsigned int*)(0x427E0940UL)) -#define bFM3_EXBUS_AREA2_MASK1 *((volatile unsigned int*)(0x427E0944UL)) -#define bFM3_EXBUS_AREA2_MASK2 *((volatile unsigned int*)(0x427E0948UL)) -#define bFM3_EXBUS_AREA2_MASK3 *((volatile unsigned int*)(0x427E094CUL)) -#define bFM3_EXBUS_AREA2_MASK4 *((volatile unsigned int*)(0x427E0950UL)) -#define bFM3_EXBUS_AREA2_MASK5 *((volatile unsigned int*)(0x427E0954UL)) -#define bFM3_EXBUS_AREA2_MASK6 *((volatile unsigned int*)(0x427E0958UL)) -#define bFM3_EXBUS_AREA3_ADDR0 *((volatile unsigned int*)(0x427E0980UL)) -#define bFM3_EXBUS_AREA3_ADDR1 *((volatile unsigned int*)(0x427E0984UL)) -#define bFM3_EXBUS_AREA3_ADDR2 *((volatile unsigned int*)(0x427E0988UL)) -#define bFM3_EXBUS_AREA3_ADDR3 *((volatile unsigned int*)(0x427E098CUL)) -#define bFM3_EXBUS_AREA3_ADDR4 *((volatile unsigned int*)(0x427E0990UL)) -#define bFM3_EXBUS_AREA3_ADDR5 *((volatile unsigned int*)(0x427E0994UL)) -#define bFM3_EXBUS_AREA3_ADDR6 *((volatile unsigned int*)(0x427E0998UL)) -#define bFM3_EXBUS_AREA3_ADDR7 *((volatile unsigned int*)(0x427E099CUL)) -#define bFM3_EXBUS_AREA3_MASK0 *((volatile unsigned int*)(0x427E09C0UL)) -#define bFM3_EXBUS_AREA3_MASK1 *((volatile unsigned int*)(0x427E09C4UL)) -#define bFM3_EXBUS_AREA3_MASK2 *((volatile unsigned int*)(0x427E09C8UL)) -#define bFM3_EXBUS_AREA3_MASK3 *((volatile unsigned int*)(0x427E09CCUL)) -#define bFM3_EXBUS_AREA3_MASK4 *((volatile unsigned int*)(0x427E09D0UL)) -#define bFM3_EXBUS_AREA3_MASK5 *((volatile unsigned int*)(0x427E09D4UL)) -#define bFM3_EXBUS_AREA3_MASK6 *((volatile unsigned int*)(0x427E09D8UL)) -#define bFM3_EXBUS_AREA4_ADDR0 *((volatile unsigned int*)(0x427E0A00UL)) -#define bFM3_EXBUS_AREA4_ADDR1 *((volatile unsigned int*)(0x427E0A04UL)) -#define bFM3_EXBUS_AREA4_ADDR2 *((volatile unsigned int*)(0x427E0A08UL)) -#define bFM3_EXBUS_AREA4_ADDR3 *((volatile unsigned int*)(0x427E0A0CUL)) -#define bFM3_EXBUS_AREA4_ADDR4 *((volatile unsigned int*)(0x427E0A10UL)) -#define bFM3_EXBUS_AREA4_ADDR5 *((volatile unsigned int*)(0x427E0A14UL)) -#define bFM3_EXBUS_AREA4_ADDR6 *((volatile unsigned int*)(0x427E0A18UL)) -#define bFM3_EXBUS_AREA4_ADDR7 *((volatile unsigned int*)(0x427E0A1CUL)) -#define bFM3_EXBUS_AREA4_MASK0 *((volatile unsigned int*)(0x427E0A40UL)) -#define bFM3_EXBUS_AREA4_MASK1 *((volatile unsigned int*)(0x427E0A44UL)) -#define bFM3_EXBUS_AREA4_MASK2 *((volatile unsigned int*)(0x427E0A48UL)) -#define bFM3_EXBUS_AREA4_MASK3 *((volatile unsigned int*)(0x427E0A4CUL)) -#define bFM3_EXBUS_AREA4_MASK4 *((volatile unsigned int*)(0x427E0A50UL)) -#define bFM3_EXBUS_AREA4_MASK5 *((volatile unsigned int*)(0x427E0A54UL)) -#define bFM3_EXBUS_AREA4_MASK6 *((volatile unsigned int*)(0x427E0A58UL)) -#define bFM3_EXBUS_AREA5_ADDR0 *((volatile unsigned int*)(0x427E0A80UL)) -#define bFM3_EXBUS_AREA5_ADDR1 *((volatile unsigned int*)(0x427E0A84UL)) -#define bFM3_EXBUS_AREA5_ADDR2 *((volatile unsigned int*)(0x427E0A88UL)) -#define bFM3_EXBUS_AREA5_ADDR3 *((volatile unsigned int*)(0x427E0A8CUL)) -#define bFM3_EXBUS_AREA5_ADDR4 *((volatile unsigned int*)(0x427E0A90UL)) -#define bFM3_EXBUS_AREA5_ADDR5 *((volatile unsigned int*)(0x427E0A94UL)) -#define bFM3_EXBUS_AREA5_ADDR6 *((volatile unsigned int*)(0x427E0A98UL)) -#define bFM3_EXBUS_AREA5_ADDR7 *((volatile unsigned int*)(0x427E0A9CUL)) -#define bFM3_EXBUS_AREA5_MASK0 *((volatile unsigned int*)(0x427E0AC0UL)) -#define bFM3_EXBUS_AREA5_MASK1 *((volatile unsigned int*)(0x427E0AC4UL)) -#define bFM3_EXBUS_AREA5_MASK2 *((volatile unsigned int*)(0x427E0AC8UL)) -#define bFM3_EXBUS_AREA5_MASK3 *((volatile unsigned int*)(0x427E0ACCUL)) -#define bFM3_EXBUS_AREA5_MASK4 *((volatile unsigned int*)(0x427E0AD0UL)) -#define bFM3_EXBUS_AREA5_MASK5 *((volatile unsigned int*)(0x427E0AD4UL)) -#define bFM3_EXBUS_AREA5_MASK6 *((volatile unsigned int*)(0x427E0AD8UL)) -#define bFM3_EXBUS_AREA6_ADDR0 *((volatile unsigned int*)(0x427E0B00UL)) -#define bFM3_EXBUS_AREA6_ADDR1 *((volatile unsigned int*)(0x427E0B04UL)) -#define bFM3_EXBUS_AREA6_ADDR2 *((volatile unsigned int*)(0x427E0B08UL)) -#define bFM3_EXBUS_AREA6_ADDR3 *((volatile unsigned int*)(0x427E0B0CUL)) -#define bFM3_EXBUS_AREA6_ADDR4 *((volatile unsigned int*)(0x427E0B10UL)) -#define bFM3_EXBUS_AREA6_ADDR5 *((volatile unsigned int*)(0x427E0B14UL)) -#define bFM3_EXBUS_AREA6_ADDR6 *((volatile unsigned int*)(0x427E0B18UL)) -#define bFM3_EXBUS_AREA6_ADDR7 *((volatile unsigned int*)(0x427E0B1CUL)) -#define bFM3_EXBUS_AREA6_MASK0 *((volatile unsigned int*)(0x427E0B40UL)) -#define bFM3_EXBUS_AREA6_MASK1 *((volatile unsigned int*)(0x427E0B44UL)) -#define bFM3_EXBUS_AREA6_MASK2 *((volatile unsigned int*)(0x427E0B48UL)) -#define bFM3_EXBUS_AREA6_MASK3 *((volatile unsigned int*)(0x427E0B4CUL)) -#define bFM3_EXBUS_AREA6_MASK4 *((volatile unsigned int*)(0x427E0B50UL)) -#define bFM3_EXBUS_AREA6_MASK5 *((volatile unsigned int*)(0x427E0B54UL)) -#define bFM3_EXBUS_AREA6_MASK6 *((volatile unsigned int*)(0x427E0B58UL)) -#define bFM3_EXBUS_AREA7_ADDR0 *((volatile unsigned int*)(0x427E0B80UL)) -#define bFM3_EXBUS_AREA7_ADDR1 *((volatile unsigned int*)(0x427E0B84UL)) -#define bFM3_EXBUS_AREA7_ADDR2 *((volatile unsigned int*)(0x427E0B88UL)) -#define bFM3_EXBUS_AREA7_ADDR3 *((volatile unsigned int*)(0x427E0B8CUL)) -#define bFM3_EXBUS_AREA7_ADDR4 *((volatile unsigned int*)(0x427E0B90UL)) -#define bFM3_EXBUS_AREA7_ADDR5 *((volatile unsigned int*)(0x427E0B94UL)) -#define bFM3_EXBUS_AREA7_ADDR6 *((volatile unsigned int*)(0x427E0B98UL)) -#define bFM3_EXBUS_AREA7_ADDR7 *((volatile unsigned int*)(0x427E0B9CUL)) -#define bFM3_EXBUS_AREA7_MASK0 *((volatile unsigned int*)(0x427E0BC0UL)) -#define bFM3_EXBUS_AREA7_MASK1 *((volatile unsigned int*)(0x427E0BC4UL)) -#define bFM3_EXBUS_AREA7_MASK2 *((volatile unsigned int*)(0x427E0BC8UL)) -#define bFM3_EXBUS_AREA7_MASK3 *((volatile unsigned int*)(0x427E0BCCUL)) -#define bFM3_EXBUS_AREA7_MASK4 *((volatile unsigned int*)(0x427E0BD0UL)) -#define bFM3_EXBUS_AREA7_MASK5 *((volatile unsigned int*)(0x427E0BD4UL)) -#define bFM3_EXBUS_AREA7_MASK6 *((volatile unsigned int*)(0x427E0BD8UL)) - -/* USB channel 0 registers */ -#define bFM3_USB0_HCNT_HOST *((volatile unsigned int*)(0x42842000UL)) -#define bFM3_USB0_HCNT_URST *((volatile unsigned int*)(0x42842004UL)) -#define bFM3_USB0_HCNT_SOFIRE *((volatile unsigned int*)(0x42842008UL)) -#define bFM3_USB0_HCNT_DIRE *((volatile unsigned int*)(0x4284200CUL)) -#define bFM3_USB0_HCNT_CNNIRE *((volatile unsigned int*)(0x42842010UL)) -#define bFM3_USB0_HCNT_CMPIRE *((volatile unsigned int*)(0x42842014UL)) -#define bFM3_USB0_HCNT_URIRE *((volatile unsigned int*)(0x42842018UL)) -#define bFM3_USB0_HCNT_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) -#define bFM3_USB0_HCNT_RETRY *((volatile unsigned int*)(0x42842020UL)) -#define bFM3_USB0_HCNT_CANCEL *((volatile unsigned int*)(0x42842024UL)) -#define bFM3_USB0_HCNT_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) -#define bFM3_USB0_HCNT0_HOST *((volatile unsigned int*)(0x42842000UL)) -#define bFM3_USB0_HCNT0_URST *((volatile unsigned int*)(0x42842004UL)) -#define bFM3_USB0_HCNT0_SOFIRE *((volatile unsigned int*)(0x42842008UL)) -#define bFM3_USB0_HCNT0_DIRE *((volatile unsigned int*)(0x4284200CUL)) -#define bFM3_USB0_HCNT0_CNNIRE *((volatile unsigned int*)(0x42842010UL)) -#define bFM3_USB0_HCNT0_CMPIRE *((volatile unsigned int*)(0x42842014UL)) -#define bFM3_USB0_HCNT0_URIRE *((volatile unsigned int*)(0x42842018UL)) -#define bFM3_USB0_HCNT0_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) -#define bFM3_USB0_HCNT1_RETRY *((volatile unsigned int*)(0x42842020UL)) -#define bFM3_USB0_HCNT1_CANCEL *((volatile unsigned int*)(0x42842024UL)) -#define bFM3_USB0_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) -#define bFM3_USB0_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42842080UL)) -#define bFM3_USB0_HIRQ_DIRQ *((volatile unsigned int*)(0x42842084UL)) -#define bFM3_USB0_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42842088UL)) -#define bFM3_USB0_HIRQ_CMPIRQ *((volatile unsigned int*)(0x4284208CUL)) -#define bFM3_USB0_HIRQ_URIRQ *((volatile unsigned int*)(0x42842090UL)) -#define bFM3_USB0_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42842094UL)) -#define bFM3_USB0_HIRQ_TCAN *((volatile unsigned int*)(0x4284209CUL)) -#define bFM3_USB0_HERR_HS0 *((volatile unsigned int*)(0x428420A0UL)) -#define bFM3_USB0_HERR_HS1 *((volatile unsigned int*)(0x428420A4UL)) -#define bFM3_USB0_HERR_STUFF *((volatile unsigned int*)(0x428420A8UL)) -#define bFM3_USB0_HERR_TGERR *((volatile unsigned int*)(0x428420ACUL)) -#define bFM3_USB0_HERR_CRC *((volatile unsigned int*)(0x428420B0UL)) -#define bFM3_USB0_HERR_TOUT *((volatile unsigned int*)(0x428420B4UL)) -#define bFM3_USB0_HERR_RERR *((volatile unsigned int*)(0x428420B8UL)) -#define bFM3_USB0_HERR_LSTOF *((volatile unsigned int*)(0x428420BCUL)) -#define bFM3_USB0_HSTATE_CSTAT *((volatile unsigned int*)(0x42842100UL)) -#define bFM3_USB0_HSTATE_TMODE *((volatile unsigned int*)(0x42842104UL)) -#define bFM3_USB0_HSTATE_SUSP *((volatile unsigned int*)(0x42842108UL)) -#define bFM3_USB0_HSTATE_SOFBUSY *((volatile unsigned int*)(0x4284210CUL)) -#define bFM3_USB0_HSTATE_CLKSEL *((volatile unsigned int*)(0x42842110UL)) -#define bFM3_USB0_HSTATE_ALIVE *((volatile unsigned int*)(0x42842114UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42842120UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42842124UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42842128UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x4284212CUL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42842130UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42842134UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42842138UL)) -#define bFM3_USB0_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x4284213CUL)) -#define bFM3_USB0_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42842180UL)) -#define bFM3_USB0_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42842184UL)) -#define bFM3_USB0_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42842188UL)) -#define bFM3_USB0_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x4284218CUL)) -#define bFM3_USB0_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42842190UL)) -#define bFM3_USB0_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42842194UL)) -#define bFM3_USB0_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42842198UL)) -#define bFM3_USB0_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x4284219CUL)) -#define bFM3_USB0_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x428421A0UL)) -#define bFM3_USB0_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x428421A4UL)) -#define bFM3_USB0_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x428421A8UL)) -#define bFM3_USB0_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x428421ACUL)) -#define bFM3_USB0_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x428421B0UL)) -#define bFM3_USB0_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x428421B4UL)) -#define bFM3_USB0_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x428421B8UL)) -#define bFM3_USB0_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x428421BCUL)) -#define bFM3_USB0_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42842180UL)) -#define bFM3_USB0_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42842184UL)) -#define bFM3_USB0_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42842188UL)) -#define bFM3_USB0_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x4284218CUL)) -#define bFM3_USB0_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42842190UL)) -#define bFM3_USB0_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42842194UL)) -#define bFM3_USB0_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42842198UL)) -#define bFM3_USB0_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x4284219CUL)) -#define bFM3_USB0_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x428421A0UL)) -#define bFM3_USB0_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x428421A4UL)) -#define bFM3_USB0_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x428421A8UL)) -#define bFM3_USB0_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x428421ACUL)) -#define bFM3_USB0_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x428421B0UL)) -#define bFM3_USB0_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x428421B4UL)) -#define bFM3_USB0_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x428421B8UL)) -#define bFM3_USB0_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x428421BCUL)) -#define bFM3_USB0_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42842200UL)) -#define bFM3_USB0_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42842204UL)) -#define bFM3_USB0_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42842208UL)) -#define bFM3_USB0_HADR_ADDRESS0 *((volatile unsigned int*)(0x42842220UL)) -#define bFM3_USB0_HADR_ADDRESS1 *((volatile unsigned int*)(0x42842224UL)) -#define bFM3_USB0_HADR_ADDRESS2 *((volatile unsigned int*)(0x42842228UL)) -#define bFM3_USB0_HADR_ADDRESS3 *((volatile unsigned int*)(0x4284222CUL)) -#define bFM3_USB0_HADR_ADDRESS4 *((volatile unsigned int*)(0x42842230UL)) -#define bFM3_USB0_HADR_ADDRESS5 *((volatile unsigned int*)(0x42842234UL)) -#define bFM3_USB0_HADR_ADDRESS6 *((volatile unsigned int*)(0x42842238UL)) -#define bFM3_USB0_HEOF_EOF0 *((volatile unsigned int*)(0x42842280UL)) -#define bFM3_USB0_HEOF_EOF1 *((volatile unsigned int*)(0x42842284UL)) -#define bFM3_USB0_HEOF_EOF2 *((volatile unsigned int*)(0x42842288UL)) -#define bFM3_USB0_HEOF_EOF3 *((volatile unsigned int*)(0x4284228CUL)) -#define bFM3_USB0_HEOF_EOF4 *((volatile unsigned int*)(0x42842290UL)) -#define bFM3_USB0_HEOF_EOF5 *((volatile unsigned int*)(0x42842294UL)) -#define bFM3_USB0_HEOF_EOF6 *((volatile unsigned int*)(0x42842298UL)) -#define bFM3_USB0_HEOF_EOF7 *((volatile unsigned int*)(0x4284229CUL)) -#define bFM3_USB0_HEOF_EOF8 *((volatile unsigned int*)(0x428422A0UL)) -#define bFM3_USB0_HEOF_EOF9 *((volatile unsigned int*)(0x428422A4UL)) -#define bFM3_USB0_HEOF_EOF10 *((volatile unsigned int*)(0x428422A8UL)) -#define bFM3_USB0_HEOF_EOF11 *((volatile unsigned int*)(0x428422ACUL)) -#define bFM3_USB0_HEOF_EOF12 *((volatile unsigned int*)(0x428422B0UL)) -#define bFM3_USB0_HEOF_EOF13 *((volatile unsigned int*)(0x428422B4UL)) -#define bFM3_USB0_HEOF_EOF14 *((volatile unsigned int*)(0x428422B8UL)) -#define bFM3_USB0_HEOF_EOF15 *((volatile unsigned int*)(0x428422BCUL)) -#define bFM3_USB0_HEOF0_EOF00 *((volatile unsigned int*)(0x42842280UL)) -#define bFM3_USB0_HEOF0_EOF01 *((volatile unsigned int*)(0x42842284UL)) -#define bFM3_USB0_HEOF0_EOF02 *((volatile unsigned int*)(0x42842288UL)) -#define bFM3_USB0_HEOF0_EOF03 *((volatile unsigned int*)(0x4284228CUL)) -#define bFM3_USB0_HEOF0_EOF04 *((volatile unsigned int*)(0x42842290UL)) -#define bFM3_USB0_HEOF0_EOF05 *((volatile unsigned int*)(0x42842294UL)) -#define bFM3_USB0_HEOF0_EOF06 *((volatile unsigned int*)(0x42842298UL)) -#define bFM3_USB0_HEOF0_EOF07 *((volatile unsigned int*)(0x4284229CUL)) -#define bFM3_USB0_HEOF1_EOF10 *((volatile unsigned int*)(0x428422A0UL)) -#define bFM3_USB0_HEOF1_EOF11 *((volatile unsigned int*)(0x428422A4UL)) -#define bFM3_USB0_HEOF1_EOF12 *((volatile unsigned int*)(0x428422A8UL)) -#define bFM3_USB0_HEOF1_EOF13 *((volatile unsigned int*)(0x428422ACUL)) -#define bFM3_USB0_HEOF1_EOF14 *((volatile unsigned int*)(0x428422B0UL)) -#define bFM3_USB0_HEOF1_EOF15 *((volatile unsigned int*)(0x428422B4UL)) -#define bFM3_USB0_HFRAME_FRAME0 *((volatile unsigned int*)(0x42842300UL)) -#define bFM3_USB0_HFRAME_FRAME1 *((volatile unsigned int*)(0x42842304UL)) -#define bFM3_USB0_HFRAME_FRAME2 *((volatile unsigned int*)(0x42842308UL)) -#define bFM3_USB0_HFRAME_FRAME3 *((volatile unsigned int*)(0x4284230CUL)) -#define bFM3_USB0_HFRAME_FRAME4 *((volatile unsigned int*)(0x42842310UL)) -#define bFM3_USB0_HFRAME_FRAME5 *((volatile unsigned int*)(0x42842314UL)) -#define bFM3_USB0_HFRAME_FRAME6 *((volatile unsigned int*)(0x42842318UL)) -#define bFM3_USB0_HFRAME_FRAME7 *((volatile unsigned int*)(0x4284231CUL)) -#define bFM3_USB0_HFRAME_FRAME8 *((volatile unsigned int*)(0x42842320UL)) -#define bFM3_USB0_HFRAME_FRAME9 *((volatile unsigned int*)(0x42842324UL)) -#define bFM3_USB0_HFRAME_FRAME10 *((volatile unsigned int*)(0x42842328UL)) -#define bFM3_USB0_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42842300UL)) -#define bFM3_USB0_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42842304UL)) -#define bFM3_USB0_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42842308UL)) -#define bFM3_USB0_HFRAME0_FRAME03 *((volatile unsigned int*)(0x4284230CUL)) -#define bFM3_USB0_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42842310UL)) -#define bFM3_USB0_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42842314UL)) -#define bFM3_USB0_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42842318UL)) -#define bFM3_USB0_HFRAME0_FRAME07 *((volatile unsigned int*)(0x4284231CUL)) -#define bFM3_USB0_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42842320UL)) -#define bFM3_USB0_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42842324UL)) -#define bFM3_USB0_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42842328UL)) -#define bFM3_USB0_HFRAME1_FRAME13 *((volatile unsigned int*)(0x4284232CUL)) -#define bFM3_USB0_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42842380UL)) -#define bFM3_USB0_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42842384UL)) -#define bFM3_USB0_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42842388UL)) -#define bFM3_USB0_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x4284238CUL)) -#define bFM3_USB0_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42842390UL)) -#define bFM3_USB0_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42842394UL)) -#define bFM3_USB0_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42842398UL)) -#define bFM3_USB0_HTOKEN_TGGL *((volatile unsigned int*)(0x4284239CUL)) -#define bFM3_USB0_UDCC_PWC *((volatile unsigned int*)(0x42842400UL)) -#define bFM3_USB0_UDCC_RFBK *((volatile unsigned int*)(0x42842404UL)) -#define bFM3_USB0_UDCC_STALCLREN *((volatile unsigned int*)(0x4284240CUL)) -#define bFM3_USB0_UDCC_USTP *((volatile unsigned int*)(0x42842410UL)) -#define bFM3_USB0_UDCC_HCONX *((volatile unsigned int*)(0x42842414UL)) -#define bFM3_USB0_UDCC_RESUM *((volatile unsigned int*)(0x42842418UL)) -#define bFM3_USB0_UDCC_RST *((volatile unsigned int*)(0x4284241CUL)) -#define bFM3_USB0_EP0C_PKS00 *((volatile unsigned int*)(0x42842480UL)) -#define bFM3_USB0_EP0C_PKS01 *((volatile unsigned int*)(0x42842484UL)) -#define bFM3_USB0_EP0C_PKS02 *((volatile unsigned int*)(0x42842488UL)) -#define bFM3_USB0_EP0C_PKS03 *((volatile unsigned int*)(0x4284248CUL)) -#define bFM3_USB0_EP0C_PKS04 *((volatile unsigned int*)(0x42842490UL)) -#define bFM3_USB0_EP0C_PKS05 *((volatile unsigned int*)(0x42842494UL)) -#define bFM3_USB0_EP0C_PKS06 *((volatile unsigned int*)(0x42842498UL)) -#define bFM3_USB0_EP0C_STAL *((volatile unsigned int*)(0x428424A4UL)) -#define bFM3_USB0_EP1C_PKS10 *((volatile unsigned int*)(0x42842500UL)) -#define bFM3_USB0_EP1C_PKS11 *((volatile unsigned int*)(0x42842504UL)) -#define bFM3_USB0_EP1C_PKS12 *((volatile unsigned int*)(0x42842508UL)) -#define bFM3_USB0_EP1C_PKS13 *((volatile unsigned int*)(0x4284250CUL)) -#define bFM3_USB0_EP1C_PKS14 *((volatile unsigned int*)(0x42842510UL)) -#define bFM3_USB0_EP1C_PKS15 *((volatile unsigned int*)(0x42842514UL)) -#define bFM3_USB0_EP1C_PKS16 *((volatile unsigned int*)(0x42842518UL)) -#define bFM3_USB0_EP1C_PKS17 *((volatile unsigned int*)(0x4284251CUL)) -#define bFM3_USB0_EP1C_PSK18 *((volatile unsigned int*)(0x42842520UL)) -#define bFM3_USB0_EP1C_STAL *((volatile unsigned int*)(0x42842524UL)) -#define bFM3_USB0_EP1C_NULE *((volatile unsigned int*)(0x42842528UL)) -#define bFM3_USB0_EP1C_DMAE *((volatile unsigned int*)(0x4284252CUL)) -#define bFM3_USB0_EP1C_DIR *((volatile unsigned int*)(0x42842530UL)) -#define bFM3_USB0_EP1C_TYPE0 *((volatile unsigned int*)(0x42842534UL)) -#define bFM3_USB0_EP1C_TYPE1 *((volatile unsigned int*)(0x42842538UL)) -#define bFM3_USB0_EP1C_EPEN *((volatile unsigned int*)(0x4284253CUL)) -#define bFM3_USB0_EP2C_PKS20 *((volatile unsigned int*)(0x42842580UL)) -#define bFM3_USB0_EP2C_PKS21 *((volatile unsigned int*)(0x42842584UL)) -#define bFM3_USB0_EP2C_PKS22 *((volatile unsigned int*)(0x42842588UL)) -#define bFM3_USB0_EP2C_PKS23 *((volatile unsigned int*)(0x4284258CUL)) -#define bFM3_USB0_EP2C_PKS24 *((volatile unsigned int*)(0x42842590UL)) -#define bFM3_USB0_EP2C_PKS25 *((volatile unsigned int*)(0x42842594UL)) -#define bFM3_USB0_EP2C_PKS26 *((volatile unsigned int*)(0x42842598UL)) -#define bFM3_USB0_EP2C_STAL *((volatile unsigned int*)(0x428425A4UL)) -#define bFM3_USB0_EP2C_NULE *((volatile unsigned int*)(0x428425A8UL)) -#define bFM3_USB0_EP2C_DMAE *((volatile unsigned int*)(0x428425ACUL)) -#define bFM3_USB0_EP2C_DIR *((volatile unsigned int*)(0x428425B0UL)) -#define bFM3_USB0_EP2C_TYPE0 *((volatile unsigned int*)(0x428425B4UL)) -#define bFM3_USB0_EP2C_TYPE1 *((volatile unsigned int*)(0x428425B8UL)) -#define bFM3_USB0_EP2C_EPEN *((volatile unsigned int*)(0x428425BCUL)) -#define bFM3_USB0_EP3C_PKS30 *((volatile unsigned int*)(0x42842600UL)) -#define bFM3_USB0_EP3C_PKS31 *((volatile unsigned int*)(0x42842604UL)) -#define bFM3_USB0_EP3C_PKS32 *((volatile unsigned int*)(0x42842608UL)) -#define bFM3_USB0_EP3C_PKS33 *((volatile unsigned int*)(0x4284260CUL)) -#define bFM3_USB0_EP3C_PKS34 *((volatile unsigned int*)(0x42842610UL)) -#define bFM3_USB0_EP3C_PKS35 *((volatile unsigned int*)(0x42842614UL)) -#define bFM3_USB0_EP3C_PKS36 *((volatile unsigned int*)(0x42842618UL)) -#define bFM3_USB0_EP3C_STAL *((volatile unsigned int*)(0x42842624UL)) -#define bFM3_USB0_EP3C_NULE *((volatile unsigned int*)(0x42842628UL)) -#define bFM3_USB0_EP3C_DMAE *((volatile unsigned int*)(0x4284262CUL)) -#define bFM3_USB0_EP3C_DIR *((volatile unsigned int*)(0x42842630UL)) -#define bFM3_USB0_EP3C_TYPE0 *((volatile unsigned int*)(0x42842634UL)) -#define bFM3_USB0_EP3C_TYPE1 *((volatile unsigned int*)(0x42842638UL)) -#define bFM3_USB0_EP3C_EPEN *((volatile unsigned int*)(0x4284263CUL)) -#define bFM3_USB0_EP4C_PKS40 *((volatile unsigned int*)(0x42842680UL)) -#define bFM3_USB0_EP4C_PKS41 *((volatile unsigned int*)(0x42842684UL)) -#define bFM3_USB0_EP4C_PKS42 *((volatile unsigned int*)(0x42842688UL)) -#define bFM3_USB0_EP4C_PKS43 *((volatile unsigned int*)(0x4284268CUL)) -#define bFM3_USB0_EP4C_PKS44 *((volatile unsigned int*)(0x42842690UL)) -#define bFM3_USB0_EP4C_PKS45 *((volatile unsigned int*)(0x42842694UL)) -#define bFM3_USB0_EP4C_PKS46 *((volatile unsigned int*)(0x42842698UL)) -#define bFM3_USB0_EP4C_STAL *((volatile unsigned int*)(0x428426A4UL)) -#define bFM3_USB0_EP4C_NULE *((volatile unsigned int*)(0x428426A8UL)) -#define bFM3_USB0_EP4C_DMAE *((volatile unsigned int*)(0x428426ACUL)) -#define bFM3_USB0_EP4C_DIR *((volatile unsigned int*)(0x428426B0UL)) -#define bFM3_USB0_EP4C_TYPE0 *((volatile unsigned int*)(0x428426B4UL)) -#define bFM3_USB0_EP4C_TYPE1 *((volatile unsigned int*)(0x428426B8UL)) -#define bFM3_USB0_EP4C_EPEN *((volatile unsigned int*)(0x428426BCUL)) -#define bFM3_USB0_EP5C_PKS50 *((volatile unsigned int*)(0x42842700UL)) -#define bFM3_USB0_EP5C_PKS51 *((volatile unsigned int*)(0x42842704UL)) -#define bFM3_USB0_EP5C_PKS52 *((volatile unsigned int*)(0x42842708UL)) -#define bFM3_USB0_EP5C_PKS53 *((volatile unsigned int*)(0x4284270CUL)) -#define bFM3_USB0_EP5C_PKS54 *((volatile unsigned int*)(0x42842710UL)) -#define bFM3_USB0_EP5C_PKS55 *((volatile unsigned int*)(0x42842714UL)) -#define bFM3_USB0_EP5C_PKS56 *((volatile unsigned int*)(0x42842718UL)) -#define bFM3_USB0_EP5C_STAL *((volatile unsigned int*)(0x42842724UL)) -#define bFM3_USB0_EP5C_NULE *((volatile unsigned int*)(0x42842728UL)) -#define bFM3_USB0_EP5C_DMAE *((volatile unsigned int*)(0x4284272CUL)) -#define bFM3_USB0_EP5C_DIR *((volatile unsigned int*)(0x42842730UL)) -#define bFM3_USB0_EP5C_TYPE0 *((volatile unsigned int*)(0x42842734UL)) -#define bFM3_USB0_EP5C_TYPE1 *((volatile unsigned int*)(0x42842738UL)) -#define bFM3_USB0_EP5C_EPEN *((volatile unsigned int*)(0x4284273CUL)) -#define bFM3_USB0_TMSP_TMSP0 *((volatile unsigned int*)(0x42842780UL)) -#define bFM3_USB0_TMSP_TMSP1 *((volatile unsigned int*)(0x42842784UL)) -#define bFM3_USB0_TMSP_TMSP2 *((volatile unsigned int*)(0x42842788UL)) -#define bFM3_USB0_TMSP_TMSP3 *((volatile unsigned int*)(0x4284278CUL)) -#define bFM3_USB0_TMSP_TMSP4 *((volatile unsigned int*)(0x42842790UL)) -#define bFM3_USB0_TMSP_TMSP5 *((volatile unsigned int*)(0x42842794UL)) -#define bFM3_USB0_TMSP_TMSP6 *((volatile unsigned int*)(0x42842798UL)) -#define bFM3_USB0_TMSP_TMSP7 *((volatile unsigned int*)(0x4284279CUL)) -#define bFM3_USB0_TMSP_TMSP8 *((volatile unsigned int*)(0x428427A0UL)) -#define bFM3_USB0_TMSP_TMSP9 *((volatile unsigned int*)(0x428427A4UL)) -#define bFM3_USB0_TMSP_TMSP10 *((volatile unsigned int*)(0x428427A8UL)) -#define bFM3_USB0_UDCS_CONF *((volatile unsigned int*)(0x42842800UL)) -#define bFM3_USB0_UDCS_SETP *((volatile unsigned int*)(0x42842804UL)) -#define bFM3_USB0_UDCS_WKUP *((volatile unsigned int*)(0x42842808UL)) -#define bFM3_USB0_UDCS_BRST *((volatile unsigned int*)(0x4284280CUL)) -#define bFM3_USB0_UDCS_SOF *((volatile unsigned int*)(0x42842810UL)) -#define bFM3_USB0_UDCS_SUSP *((volatile unsigned int*)(0x42842814UL)) -#define bFM3_USB0_UDCIE_CONFIE *((volatile unsigned int*)(0x42842820UL)) -#define bFM3_USB0_UDCIE_CONFN *((volatile unsigned int*)(0x42842824UL)) -#define bFM3_USB0_UDCIE_WKUPIE *((volatile unsigned int*)(0x42842828UL)) -#define bFM3_USB0_UDCIE_BRSTIE *((volatile unsigned int*)(0x4284282CUL)) -#define bFM3_USB0_UDCIE_SOFIE *((volatile unsigned int*)(0x42842830UL)) -#define bFM3_USB0_UDCIE_SUSPIE *((volatile unsigned int*)(0x42842834UL)) -#define bFM3_USB0_EP0IS_DRQI *((volatile unsigned int*)(0x428428A8UL)) -#define bFM3_USB0_EP0IS_DRQIIE *((volatile unsigned int*)(0x428428B8UL)) -#define bFM3_USB0_EP0IS_BFINI *((volatile unsigned int*)(0x428428BCUL)) -#define bFM3_USB0_EP0OS_SIZE0 *((volatile unsigned int*)(0x42842900UL)) -#define bFM3_USB0_EP0OS_SIZE1 *((volatile unsigned int*)(0x42842904UL)) -#define bFM3_USB0_EP0OS_SIZE2 *((volatile unsigned int*)(0x42842908UL)) -#define bFM3_USB0_EP0OS_SIZE3 *((volatile unsigned int*)(0x4284290CUL)) -#define bFM3_USB0_EP0OS_SIZE4 *((volatile unsigned int*)(0x42842910UL)) -#define bFM3_USB0_EP0OS_SIZE5 *((volatile unsigned int*)(0x42842914UL)) -#define bFM3_USB0_EP0OS_SIZE6 *((volatile unsigned int*)(0x42842918UL)) -#define bFM3_USB0_EP0OS_SPK *((volatile unsigned int*)(0x42842924UL)) -#define bFM3_USB0_EP0OS_DRQO *((volatile unsigned int*)(0x42842928UL)) -#define bFM3_USB0_EP0OS_SPKIE *((volatile unsigned int*)(0x42842934UL)) -#define bFM3_USB0_EP0OS_DRQOIE *((volatile unsigned int*)(0x42842938UL)) -#define bFM3_USB0_EP0OS_BFINI *((volatile unsigned int*)(0x4284293CUL)) -#define bFM3_USB0_EP1S_SIZE10 *((volatile unsigned int*)(0x42842980UL)) -#define bFM3_USB0_EP1S_SIZE11 *((volatile unsigned int*)(0x42842984UL)) -#define bFM3_USB0_EP1S_SIZE12 *((volatile unsigned int*)(0x42842988UL)) -#define bFM3_USB0_EP1S_SIZE13 *((volatile unsigned int*)(0x4284298CUL)) -#define bFM3_USB0_EP1S_SIZE14 *((volatile unsigned int*)(0x42842990UL)) -#define bFM3_USB0_EP1S_SIZE15 *((volatile unsigned int*)(0x42842994UL)) -#define bFM3_USB0_EP1S_SIZE16 *((volatile unsigned int*)(0x42842998UL)) -#define bFM3_USB0_EP1S_SIZE17 *((volatile unsigned int*)(0x4284299CUL)) -#define bFM3_USB0_EP1S_SPK *((volatile unsigned int*)(0x428429A4UL)) -#define bFM3_USB0_EP1S_DRQ *((volatile unsigned int*)(0x428429A8UL)) -#define bFM3_USB0_EP1S_BUSY *((volatile unsigned int*)(0x428429ACUL)) -#define bFM3_USB0_EP1S_SPKIE *((volatile unsigned int*)(0x428429B4UL)) -#define bFM3_USB0_EP1S_DRQIE *((volatile unsigned int*)(0x428429B8UL)) -#define bFM3_USB0_EP1S_BFINI *((volatile unsigned int*)(0x428429BCUL)) -#define bFM3_USB0_EP2S_SIZE20 *((volatile unsigned int*)(0x42842A00UL)) -#define bFM3_USB0_EP2S_SIZE21 *((volatile unsigned int*)(0x42842A04UL)) -#define bFM3_USB0_EP2S_SIZE22 *((volatile unsigned int*)(0x42842A08UL)) -#define bFM3_USB0_EP2S_SIZE23 *((volatile unsigned int*)(0x42842A0CUL)) -#define bFM3_USB0_EP2S_SIZE24 *((volatile unsigned int*)(0x42842A10UL)) -#define bFM3_USB0_EP2S_SIZE25 *((volatile unsigned int*)(0x42842A14UL)) -#define bFM3_USB0_EP2S_SIZE26 *((volatile unsigned int*)(0x42842A18UL)) -#define bFM3_USB0_EP2S_SPK *((volatile unsigned int*)(0x42842A24UL)) -#define bFM3_USB0_EP2S_DRQ *((volatile unsigned int*)(0x42842A28UL)) -#define bFM3_USB0_EP2S_BUSY *((volatile unsigned int*)(0x42842A2CUL)) -#define bFM3_USB0_EP2S_SPKIE *((volatile unsigned int*)(0x42842A34UL)) -#define bFM3_USB0_EP2S_DRQIE *((volatile unsigned int*)(0x42842A38UL)) -#define bFM3_USB0_EP2S_BFINI *((volatile unsigned int*)(0x42842A3CUL)) -#define bFM3_USB0_EP3S_SIZE30 *((volatile unsigned int*)(0x42842A80UL)) -#define bFM3_USB0_EP3S_SIZE31 *((volatile unsigned int*)(0x42842A84UL)) -#define bFM3_USB0_EP3S_SIZE32 *((volatile unsigned int*)(0x42842A88UL)) -#define bFM3_USB0_EP3S_SIZE33 *((volatile unsigned int*)(0x42842A8CUL)) -#define bFM3_USB0_EP3S_SIZE34 *((volatile unsigned int*)(0x42842A90UL)) -#define bFM3_USB0_EP3S_SIZE35 *((volatile unsigned int*)(0x42842A94UL)) -#define bFM3_USB0_EP3S_SIZE36 *((volatile unsigned int*)(0x42842A98UL)) -#define bFM3_USB0_EP3S_SPK *((volatile unsigned int*)(0x42842AA4UL)) -#define bFM3_USB0_EP3S_DRQ *((volatile unsigned int*)(0x42842AA8UL)) -#define bFM3_USB0_EP3S_BUSY *((volatile unsigned int*)(0x42842AACUL)) -#define bFM3_USB0_EP3S_SPKIE *((volatile unsigned int*)(0x42842AB4UL)) -#define bFM3_USB0_EP3S_DRQIE *((volatile unsigned int*)(0x42842AB8UL)) -#define bFM3_USB0_EP3S_BFINI *((volatile unsigned int*)(0x42842ABCUL)) -#define bFM3_USB0_EP4S_SIZE40 *((volatile unsigned int*)(0x42842B00UL)) -#define bFM3_USB0_EP4S_SIZE41 *((volatile unsigned int*)(0x42842B04UL)) -#define bFM3_USB0_EP4S_SIZE42 *((volatile unsigned int*)(0x42842B08UL)) -#define bFM3_USB0_EP4S_SIZE43 *((volatile unsigned int*)(0x42842B0CUL)) -#define bFM3_USB0_EP4S_SIZE44 *((volatile unsigned int*)(0x42842B10UL)) -#define bFM3_USB0_EP4S_SIZE45 *((volatile unsigned int*)(0x42842B14UL)) -#define bFM3_USB0_EP4S_SIZE46 *((volatile unsigned int*)(0x42842B18UL)) -#define bFM3_USB0_EP4S_SPK *((volatile unsigned int*)(0x42842B24UL)) -#define bFM3_USB0_EP4S_DRQ *((volatile unsigned int*)(0x42842B28UL)) -#define bFM3_USB0_EP4S_BUSY *((volatile unsigned int*)(0x42842B2CUL)) -#define bFM3_USB0_EP4S_SPKIE *((volatile unsigned int*)(0x42842B34UL)) -#define bFM3_USB0_EP4S_DRQIE *((volatile unsigned int*)(0x42842B38UL)) -#define bFM3_USB0_EP4S_BFINI *((volatile unsigned int*)(0x42842B3CUL)) -#define bFM3_USB0_EP5S_SIZE50 *((volatile unsigned int*)(0x42842B80UL)) -#define bFM3_USB0_EP5S_SIZE51 *((volatile unsigned int*)(0x42842B84UL)) -#define bFM3_USB0_EP5S_SIZE52 *((volatile unsigned int*)(0x42842B88UL)) -#define bFM3_USB0_EP5S_SIZE53 *((volatile unsigned int*)(0x42842B8CUL)) -#define bFM3_USB0_EP5S_SIZE54 *((volatile unsigned int*)(0x42842B90UL)) -#define bFM3_USB0_EP5S_SIZE55 *((volatile unsigned int*)(0x42842B94UL)) -#define bFM3_USB0_EP5S_SIZE56 *((volatile unsigned int*)(0x42842B98UL)) -#define bFM3_USB0_EP5S_SPK *((volatile unsigned int*)(0x42842BA4UL)) -#define bFM3_USB0_EP5S_DRQ *((volatile unsigned int*)(0x42842BA8UL)) -#define bFM3_USB0_EP5S_BUSY *((volatile unsigned int*)(0x42842BACUL)) -#define bFM3_USB0_EP5S_SPKIE *((volatile unsigned int*)(0x42842BB4UL)) -#define bFM3_USB0_EP5S_DRQIE *((volatile unsigned int*)(0x42842BB8UL)) -#define bFM3_USB0_EP5S_BFINI *((volatile unsigned int*)(0x42842BBCUL)) - -/* DMA controller */ -#define bFM3_DMAC_DMACR_DH0 *((volatile unsigned int*)(0x42C00060UL)) -#define bFM3_DMAC_DMACR_DH1 *((volatile unsigned int*)(0x42C00064UL)) -#define bFM3_DMAC_DMACR_DH2 *((volatile unsigned int*)(0x42C00068UL)) -#define bFM3_DMAC_DMACR_DH3 *((volatile unsigned int*)(0x42C0006CUL)) -#define bFM3_DMAC_DMACR_PR *((volatile unsigned int*)(0x42C00070UL)) -#define bFM3_DMAC_DMACR_DS *((volatile unsigned int*)(0x42C00078UL)) -#define bFM3_DMAC_DMACR_DE *((volatile unsigned int*)(0x42C0007CUL)) -#define bFM3_DMAC_DMACA0_TC0 *((volatile unsigned int*)(0x42C00200UL)) -#define bFM3_DMAC_DMACA0_TC1 *((volatile unsigned int*)(0x42C00204UL)) -#define bFM3_DMAC_DMACA0_TC2 *((volatile unsigned int*)(0x42C00208UL)) -#define bFM3_DMAC_DMACA0_TC3 *((volatile unsigned int*)(0x42C0020CUL)) -#define bFM3_DMAC_DMACA0_TC4 *((volatile unsigned int*)(0x42C00210UL)) -#define bFM3_DMAC_DMACA0_TC5 *((volatile unsigned int*)(0x42C00214UL)) -#define bFM3_DMAC_DMACA0_TC6 *((volatile unsigned int*)(0x42C00218UL)) -#define bFM3_DMAC_DMACA0_TC7 *((volatile unsigned int*)(0x42C0021CUL)) -#define bFM3_DMAC_DMACA0_TC8 *((volatile unsigned int*)(0x42C00220UL)) -#define bFM3_DMAC_DMACA0_TC9 *((volatile unsigned int*)(0x42C00224UL)) -#define bFM3_DMAC_DMACA0_TC10 *((volatile unsigned int*)(0x42C00228UL)) -#define bFM3_DMAC_DMACA0_TC11 *((volatile unsigned int*)(0x42C0022CUL)) -#define bFM3_DMAC_DMACA0_TC12 *((volatile unsigned int*)(0x42C00230UL)) -#define bFM3_DMAC_DMACA0_TC13 *((volatile unsigned int*)(0x42C00234UL)) -#define bFM3_DMAC_DMACA0_TC14 *((volatile unsigned int*)(0x42C00238UL)) -#define bFM3_DMAC_DMACA0_TC15 *((volatile unsigned int*)(0x42C0023CUL)) -#define bFM3_DMAC_DMACA0_BC0 *((volatile unsigned int*)(0x42C00240UL)) -#define bFM3_DMAC_DMACA0_BC1 *((volatile unsigned int*)(0x42C00244UL)) -#define bFM3_DMAC_DMACA0_BC2 *((volatile unsigned int*)(0x42C00248UL)) -#define bFM3_DMAC_DMACA0_BC3 *((volatile unsigned int*)(0x42C0024CUL)) -#define bFM3_DMAC_DMACA0_IS0 *((volatile unsigned int*)(0x42C0025CUL)) -#define bFM3_DMAC_DMACA0_IS1 *((volatile unsigned int*)(0x42C00260UL)) -#define bFM3_DMAC_DMACA0_IS2 *((volatile unsigned int*)(0x42C00264UL)) -#define bFM3_DMAC_DMACA0_IS3 *((volatile unsigned int*)(0x42C00268UL)) -#define bFM3_DMAC_DMACA0_IS4 *((volatile unsigned int*)(0x42C0026CUL)) -#define bFM3_DMAC_DMACA0_IS5 *((volatile unsigned int*)(0x42C00270UL)) -#define bFM3_DMAC_DMACA0_ST *((volatile unsigned int*)(0x42C00274UL)) -#define bFM3_DMAC_DMACA0_PB *((volatile unsigned int*)(0x42C00278UL)) -#define bFM3_DMAC_DMACA0_EB *((volatile unsigned int*)(0x42C0027CUL)) -#define bFM3_DMAC_DMACB0_EM *((volatile unsigned int*)(0x42C00280UL)) -#define bFM3_DMAC_DMACB0_SS0 *((volatile unsigned int*)(0x42C002C0UL)) -#define bFM3_DMAC_DMACB0_SS1 *((volatile unsigned int*)(0x42C002C4UL)) -#define bFM3_DMAC_DMACB0_SS2 *((volatile unsigned int*)(0x42C002C8UL)) -#define bFM3_DMAC_DMACB0_CI *((volatile unsigned int*)(0x42C002CCUL)) -#define bFM3_DMAC_DMACB0_EI *((volatile unsigned int*)(0x42C002D0UL)) -#define bFM3_DMAC_DMACB0_RD *((volatile unsigned int*)(0x42C002D4UL)) -#define bFM3_DMAC_DMACB0_RS *((volatile unsigned int*)(0x42C002D8UL)) -#define bFM3_DMAC_DMACB0_RC *((volatile unsigned int*)(0x42C002DCUL)) -#define bFM3_DMAC_DMACB0_FD *((volatile unsigned int*)(0x42C002E0UL)) -#define bFM3_DMAC_DMACB0_FS *((volatile unsigned int*)(0x42C002E4UL)) -#define bFM3_DMAC_DMACB0_TW0 *((volatile unsigned int*)(0x42C002E8UL)) -#define bFM3_DMAC_DMACB0_TW1 *((volatile unsigned int*)(0x42C002ECUL)) -#define bFM3_DMAC_DMACB0_MS0 *((volatile unsigned int*)(0x42C002F0UL)) -#define bFM3_DMAC_DMACB0_MS1 *((volatile unsigned int*)(0x42C002F4UL)) -#define bFM3_DMAC_DMACA1_TC0 *((volatile unsigned int*)(0x42C00400UL)) -#define bFM3_DMAC_DMACA1_TC1 *((volatile unsigned int*)(0x42C00404UL)) -#define bFM3_DMAC_DMACA1_TC2 *((volatile unsigned int*)(0x42C00408UL)) -#define bFM3_DMAC_DMACA1_TC3 *((volatile unsigned int*)(0x42C0040CUL)) -#define bFM3_DMAC_DMACA1_TC4 *((volatile unsigned int*)(0x42C00410UL)) -#define bFM3_DMAC_DMACA1_TC5 *((volatile unsigned int*)(0x42C00414UL)) -#define bFM3_DMAC_DMACA1_TC6 *((volatile unsigned int*)(0x42C00418UL)) -#define bFM3_DMAC_DMACA1_TC7 *((volatile unsigned int*)(0x42C0041CUL)) -#define bFM3_DMAC_DMACA1_TC8 *((volatile unsigned int*)(0x42C00420UL)) -#define bFM3_DMAC_DMACA1_TC9 *((volatile unsigned int*)(0x42C00424UL)) -#define bFM3_DMAC_DMACA1_TC10 *((volatile unsigned int*)(0x42C00428UL)) -#define bFM3_DMAC_DMACA1_TC11 *((volatile unsigned int*)(0x42C0042CUL)) -#define bFM3_DMAC_DMACA1_TC12 *((volatile unsigned int*)(0x42C00430UL)) -#define bFM3_DMAC_DMACA1_TC13 *((volatile unsigned int*)(0x42C00434UL)) -#define bFM3_DMAC_DMACA1_TC14 *((volatile unsigned int*)(0x42C00438UL)) -#define bFM3_DMAC_DMACA1_TC15 *((volatile unsigned int*)(0x42C0043CUL)) -#define bFM3_DMAC_DMACA1_BC0 *((volatile unsigned int*)(0x42C00440UL)) -#define bFM3_DMAC_DMACA1_BC1 *((volatile unsigned int*)(0x42C00444UL)) -#define bFM3_DMAC_DMACA1_BC2 *((volatile unsigned int*)(0x42C00448UL)) -#define bFM3_DMAC_DMACA1_BC3 *((volatile unsigned int*)(0x42C0044CUL)) -#define bFM3_DMAC_DMACA1_IS0 *((volatile unsigned int*)(0x42C0045CUL)) -#define bFM3_DMAC_DMACA1_IS1 *((volatile unsigned int*)(0x42C00460UL)) -#define bFM3_DMAC_DMACA1_IS2 *((volatile unsigned int*)(0x42C00464UL)) -#define bFM3_DMAC_DMACA1_IS3 *((volatile unsigned int*)(0x42C00468UL)) -#define bFM3_DMAC_DMACA1_IS4 *((volatile unsigned int*)(0x42C0046CUL)) -#define bFM3_DMAC_DMACA1_IS5 *((volatile unsigned int*)(0x42C00470UL)) -#define bFM3_DMAC_DMACA1_ST *((volatile unsigned int*)(0x42C00474UL)) -#define bFM3_DMAC_DMACA1_PB *((volatile unsigned int*)(0x42C00478UL)) -#define bFM3_DMAC_DMACA1_EB *((volatile unsigned int*)(0x42C0047CUL)) -#define bFM3_DMAC_DMACB1_EM *((volatile unsigned int*)(0x42C00480UL)) -#define bFM3_DMAC_DMACB1_SS0 *((volatile unsigned int*)(0x42C004C0UL)) -#define bFM3_DMAC_DMACB1_SS1 *((volatile unsigned int*)(0x42C004C4UL)) -#define bFM3_DMAC_DMACB1_SS2 *((volatile unsigned int*)(0x42C004C8UL)) -#define bFM3_DMAC_DMACB1_CI *((volatile unsigned int*)(0x42C004CCUL)) -#define bFM3_DMAC_DMACB1_EI *((volatile unsigned int*)(0x42C004D0UL)) -#define bFM3_DMAC_DMACB1_RD *((volatile unsigned int*)(0x42C004D4UL)) -#define bFM3_DMAC_DMACB1_RS *((volatile unsigned int*)(0x42C004D8UL)) -#define bFM3_DMAC_DMACB1_RC *((volatile unsigned int*)(0x42C004DCUL)) -#define bFM3_DMAC_DMACB1_FD *((volatile unsigned int*)(0x42C004E0UL)) -#define bFM3_DMAC_DMACB1_FS *((volatile unsigned int*)(0x42C004E4UL)) -#define bFM3_DMAC_DMACB1_TW0 *((volatile unsigned int*)(0x42C004E8UL)) -#define bFM3_DMAC_DMACB1_TW1 *((volatile unsigned int*)(0x42C004ECUL)) -#define bFM3_DMAC_DMACB1_MS0 *((volatile unsigned int*)(0x42C004F0UL)) -#define bFM3_DMAC_DMACB1_MS1 *((volatile unsigned int*)(0x42C004F4UL)) -#define bFM3_DMAC_DMACA2_TC0 *((volatile unsigned int*)(0x42C00600UL)) -#define bFM3_DMAC_DMACA2_TC1 *((volatile unsigned int*)(0x42C00604UL)) -#define bFM3_DMAC_DMACA2_TC2 *((volatile unsigned int*)(0x42C00608UL)) -#define bFM3_DMAC_DMACA2_TC3 *((volatile unsigned int*)(0x42C0060CUL)) -#define bFM3_DMAC_DMACA2_TC4 *((volatile unsigned int*)(0x42C00610UL)) -#define bFM3_DMAC_DMACA2_TC5 *((volatile unsigned int*)(0x42C00614UL)) -#define bFM3_DMAC_DMACA2_TC6 *((volatile unsigned int*)(0x42C00618UL)) -#define bFM3_DMAC_DMACA2_TC7 *((volatile unsigned int*)(0x42C0061CUL)) -#define bFM3_DMAC_DMACA2_TC8 *((volatile unsigned int*)(0x42C00620UL)) -#define bFM3_DMAC_DMACA2_TC9 *((volatile unsigned int*)(0x42C00624UL)) -#define bFM3_DMAC_DMACA2_TC10 *((volatile unsigned int*)(0x42C00628UL)) -#define bFM3_DMAC_DMACA2_TC11 *((volatile unsigned int*)(0x42C0062CUL)) -#define bFM3_DMAC_DMACA2_TC12 *((volatile unsigned int*)(0x42C00630UL)) -#define bFM3_DMAC_DMACA2_TC13 *((volatile unsigned int*)(0x42C00634UL)) -#define bFM3_DMAC_DMACA2_TC14 *((volatile unsigned int*)(0x42C00638UL)) -#define bFM3_DMAC_DMACA2_TC15 *((volatile unsigned int*)(0x42C0063CUL)) -#define bFM3_DMAC_DMACA2_BC0 *((volatile unsigned int*)(0x42C00640UL)) -#define bFM3_DMAC_DMACA2_BC1 *((volatile unsigned int*)(0x42C00644UL)) -#define bFM3_DMAC_DMACA2_BC2 *((volatile unsigned int*)(0x42C00648UL)) -#define bFM3_DMAC_DMACA2_BC3 *((volatile unsigned int*)(0x42C0064CUL)) -#define bFM3_DMAC_DMACA2_IS0 *((volatile unsigned int*)(0x42C0065CUL)) -#define bFM3_DMAC_DMACA2_IS1 *((volatile unsigned int*)(0x42C00660UL)) -#define bFM3_DMAC_DMACA2_IS2 *((volatile unsigned int*)(0x42C00664UL)) -#define bFM3_DMAC_DMACA2_IS3 *((volatile unsigned int*)(0x42C00668UL)) -#define bFM3_DMAC_DMACA2_IS4 *((volatile unsigned int*)(0x42C0066CUL)) -#define bFM3_DMAC_DMACA2_IS5 *((volatile unsigned int*)(0x42C00670UL)) -#define bFM3_DMAC_DMACA2_ST *((volatile unsigned int*)(0x42C00674UL)) -#define bFM3_DMAC_DMACA2_PB *((volatile unsigned int*)(0x42C00678UL)) -#define bFM3_DMAC_DMACA2_EB *((volatile unsigned int*)(0x42C0067CUL)) -#define bFM3_DMAC_DMACB2_EM *((volatile unsigned int*)(0x42C00680UL)) -#define bFM3_DMAC_DMACB2_SS0 *((volatile unsigned int*)(0x42C006C0UL)) -#define bFM3_DMAC_DMACB2_SS1 *((volatile unsigned int*)(0x42C006C4UL)) -#define bFM3_DMAC_DMACB2_SS2 *((volatile unsigned int*)(0x42C006C8UL)) -#define bFM3_DMAC_DMACB2_CI *((volatile unsigned int*)(0x42C006CCUL)) -#define bFM3_DMAC_DMACB2_EI *((volatile unsigned int*)(0x42C006D0UL)) -#define bFM3_DMAC_DMACB2_RD *((volatile unsigned int*)(0x42C006D4UL)) -#define bFM3_DMAC_DMACB2_RS *((volatile unsigned int*)(0x42C006D8UL)) -#define bFM3_DMAC_DMACB2_RC *((volatile unsigned int*)(0x42C006DCUL)) -#define bFM3_DMAC_DMACB2_FD *((volatile unsigned int*)(0x42C006E0UL)) -#define bFM3_DMAC_DMACB2_FS *((volatile unsigned int*)(0x42C006E4UL)) -#define bFM3_DMAC_DMACB2_TW0 *((volatile unsigned int*)(0x42C006E8UL)) -#define bFM3_DMAC_DMACB2_TW1 *((volatile unsigned int*)(0x42C006ECUL)) -#define bFM3_DMAC_DMACB2_MS0 *((volatile unsigned int*)(0x42C006F0UL)) -#define bFM3_DMAC_DMACB2_MS1 *((volatile unsigned int*)(0x42C006F4UL)) -#define bFM3_DMAC_DMACA3_TC0 *((volatile unsigned int*)(0x42C00800UL)) -#define bFM3_DMAC_DMACA3_TC1 *((volatile unsigned int*)(0x42C00804UL)) -#define bFM3_DMAC_DMACA3_TC2 *((volatile unsigned int*)(0x42C00808UL)) -#define bFM3_DMAC_DMACA3_TC3 *((volatile unsigned int*)(0x42C0080CUL)) -#define bFM3_DMAC_DMACA3_TC4 *((volatile unsigned int*)(0x42C00810UL)) -#define bFM3_DMAC_DMACA3_TC5 *((volatile unsigned int*)(0x42C00814UL)) -#define bFM3_DMAC_DMACA3_TC6 *((volatile unsigned int*)(0x42C00818UL)) -#define bFM3_DMAC_DMACA3_TC7 *((volatile unsigned int*)(0x42C0081CUL)) -#define bFM3_DMAC_DMACA3_TC8 *((volatile unsigned int*)(0x42C00820UL)) -#define bFM3_DMAC_DMACA3_TC9 *((volatile unsigned int*)(0x42C00824UL)) -#define bFM3_DMAC_DMACA3_TC10 *((volatile unsigned int*)(0x42C00828UL)) -#define bFM3_DMAC_DMACA3_TC11 *((volatile unsigned int*)(0x42C0082CUL)) -#define bFM3_DMAC_DMACA3_TC12 *((volatile unsigned int*)(0x42C00830UL)) -#define bFM3_DMAC_DMACA3_TC13 *((volatile unsigned int*)(0x42C00834UL)) -#define bFM3_DMAC_DMACA3_TC14 *((volatile unsigned int*)(0x42C00838UL)) -#define bFM3_DMAC_DMACA3_TC15 *((volatile unsigned int*)(0x42C0083CUL)) -#define bFM3_DMAC_DMACA3_BC0 *((volatile unsigned int*)(0x42C00840UL)) -#define bFM3_DMAC_DMACA3_BC1 *((volatile unsigned int*)(0x42C00844UL)) -#define bFM3_DMAC_DMACA3_BC2 *((volatile unsigned int*)(0x42C00848UL)) -#define bFM3_DMAC_DMACA3_BC3 *((volatile unsigned int*)(0x42C0084CUL)) -#define bFM3_DMAC_DMACA3_IS0 *((volatile unsigned int*)(0x42C0085CUL)) -#define bFM3_DMAC_DMACA3_IS1 *((volatile unsigned int*)(0x42C00860UL)) -#define bFM3_DMAC_DMACA3_IS2 *((volatile unsigned int*)(0x42C00864UL)) -#define bFM3_DMAC_DMACA3_IS3 *((volatile unsigned int*)(0x42C00868UL)) -#define bFM3_DMAC_DMACA3_IS4 *((volatile unsigned int*)(0x42C0086CUL)) -#define bFM3_DMAC_DMACA3_IS5 *((volatile unsigned int*)(0x42C00870UL)) -#define bFM3_DMAC_DMACA3_ST *((volatile unsigned int*)(0x42C00874UL)) -#define bFM3_DMAC_DMACA3_PB *((volatile unsigned int*)(0x42C00878UL)) -#define bFM3_DMAC_DMACA3_EB *((volatile unsigned int*)(0x42C0087CUL)) -#define bFM3_DMAC_DMACB3_EM *((volatile unsigned int*)(0x42C00880UL)) -#define bFM3_DMAC_DMACB3_SS0 *((volatile unsigned int*)(0x42C008C0UL)) -#define bFM3_DMAC_DMACB3_SS1 *((volatile unsigned int*)(0x42C008C4UL)) -#define bFM3_DMAC_DMACB3_SS2 *((volatile unsigned int*)(0x42C008C8UL)) -#define bFM3_DMAC_DMACB3_CI *((volatile unsigned int*)(0x42C008CCUL)) -#define bFM3_DMAC_DMACB3_EI *((volatile unsigned int*)(0x42C008D0UL)) -#define bFM3_DMAC_DMACB3_RD *((volatile unsigned int*)(0x42C008D4UL)) -#define bFM3_DMAC_DMACB3_RS *((volatile unsigned int*)(0x42C008D8UL)) -#define bFM3_DMAC_DMACB3_RC *((volatile unsigned int*)(0x42C008DCUL)) -#define bFM3_DMAC_DMACB3_FD *((volatile unsigned int*)(0x42C008E0UL)) -#define bFM3_DMAC_DMACB3_FS *((volatile unsigned int*)(0x42C008E4UL)) -#define bFM3_DMAC_DMACB3_TW0 *((volatile unsigned int*)(0x42C008E8UL)) -#define bFM3_DMAC_DMACB3_TW1 *((volatile unsigned int*)(0x42C008ECUL)) -#define bFM3_DMAC_DMACB3_MS0 *((volatile unsigned int*)(0x42C008F0UL)) -#define bFM3_DMAC_DMACB3_MS1 *((volatile unsigned int*)(0x42C008F4UL)) -#define bFM3_DMAC_DMACA4_TC0 *((volatile unsigned int*)(0x42C00A00UL)) -#define bFM3_DMAC_DMACA4_TC1 *((volatile unsigned int*)(0x42C00A04UL)) -#define bFM3_DMAC_DMACA4_TC2 *((volatile unsigned int*)(0x42C00A08UL)) -#define bFM3_DMAC_DMACA4_TC3 *((volatile unsigned int*)(0x42C00A0CUL)) -#define bFM3_DMAC_DMACA4_TC4 *((volatile unsigned int*)(0x42C00A10UL)) -#define bFM3_DMAC_DMACA4_TC5 *((volatile unsigned int*)(0x42C00A14UL)) -#define bFM3_DMAC_DMACA4_TC6 *((volatile unsigned int*)(0x42C00A18UL)) -#define bFM3_DMAC_DMACA4_TC7 *((volatile unsigned int*)(0x42C00A1CUL)) -#define bFM3_DMAC_DMACA4_TC8 *((volatile unsigned int*)(0x42C00A20UL)) -#define bFM3_DMAC_DMACA4_TC9 *((volatile unsigned int*)(0x42C00A24UL)) -#define bFM3_DMAC_DMACA4_TC10 *((volatile unsigned int*)(0x42C00A28UL)) -#define bFM3_DMAC_DMACA4_TC11 *((volatile unsigned int*)(0x42C00A2CUL)) -#define bFM3_DMAC_DMACA4_TC12 *((volatile unsigned int*)(0x42C00A30UL)) -#define bFM3_DMAC_DMACA4_TC13 *((volatile unsigned int*)(0x42C00A34UL)) -#define bFM3_DMAC_DMACA4_TC14 *((volatile unsigned int*)(0x42C00A38UL)) -#define bFM3_DMAC_DMACA4_TC15 *((volatile unsigned int*)(0x42C00A3CUL)) -#define bFM3_DMAC_DMACA4_BC0 *((volatile unsigned int*)(0x42C00A40UL)) -#define bFM3_DMAC_DMACA4_BC1 *((volatile unsigned int*)(0x42C00A44UL)) -#define bFM3_DMAC_DMACA4_BC2 *((volatile unsigned int*)(0x42C00A48UL)) -#define bFM3_DMAC_DMACA4_BC3 *((volatile unsigned int*)(0x42C00A4CUL)) -#define bFM3_DMAC_DMACA4_IS0 *((volatile unsigned int*)(0x42C00A5CUL)) -#define bFM3_DMAC_DMACA4_IS1 *((volatile unsigned int*)(0x42C00A60UL)) -#define bFM3_DMAC_DMACA4_IS2 *((volatile unsigned int*)(0x42C00A64UL)) -#define bFM3_DMAC_DMACA4_IS3 *((volatile unsigned int*)(0x42C00A68UL)) -#define bFM3_DMAC_DMACA4_IS4 *((volatile unsigned int*)(0x42C00A6CUL)) -#define bFM3_DMAC_DMACA4_IS5 *((volatile unsigned int*)(0x42C00A70UL)) -#define bFM3_DMAC_DMACA4_ST *((volatile unsigned int*)(0x42C00A74UL)) -#define bFM3_DMAC_DMACA4_PB *((volatile unsigned int*)(0x42C00A78UL)) -#define bFM3_DMAC_DMACA4_EB *((volatile unsigned int*)(0x42C00A7CUL)) -#define bFM3_DMAC_DMACB4_EM *((volatile unsigned int*)(0x42C00A80UL)) -#define bFM3_DMAC_DMACB4_SS0 *((volatile unsigned int*)(0x42C00AC0UL)) -#define bFM3_DMAC_DMACB4_SS1 *((volatile unsigned int*)(0x42C00AC4UL)) -#define bFM3_DMAC_DMACB4_SS2 *((volatile unsigned int*)(0x42C00AC8UL)) -#define bFM3_DMAC_DMACB4_CI *((volatile unsigned int*)(0x42C00ACCUL)) -#define bFM3_DMAC_DMACB4_EI *((volatile unsigned int*)(0x42C00AD0UL)) -#define bFM3_DMAC_DMACB4_RD *((volatile unsigned int*)(0x42C00AD4UL)) -#define bFM3_DMAC_DMACB4_RS *((volatile unsigned int*)(0x42C00AD8UL)) -#define bFM3_DMAC_DMACB4_RC *((volatile unsigned int*)(0x42C00ADCUL)) -#define bFM3_DMAC_DMACB4_FD *((volatile unsigned int*)(0x42C00AE0UL)) -#define bFM3_DMAC_DMACB4_FS *((volatile unsigned int*)(0x42C00AE4UL)) -#define bFM3_DMAC_DMACB4_TW0 *((volatile unsigned int*)(0x42C00AE8UL)) -#define bFM3_DMAC_DMACB4_TW1 *((volatile unsigned int*)(0x42C00AECUL)) -#define bFM3_DMAC_DMACB4_MS0 *((volatile unsigned int*)(0x42C00AF0UL)) -#define bFM3_DMAC_DMACB4_MS1 *((volatile unsigned int*)(0x42C00AF4UL)) -#define bFM3_DMAC_DMACA5_TC0 *((volatile unsigned int*)(0x42C00C00UL)) -#define bFM3_DMAC_DMACA5_TC1 *((volatile unsigned int*)(0x42C00C04UL)) -#define bFM3_DMAC_DMACA5_TC2 *((volatile unsigned int*)(0x42C00C08UL)) -#define bFM3_DMAC_DMACA5_TC3 *((volatile unsigned int*)(0x42C00C0CUL)) -#define bFM3_DMAC_DMACA5_TC4 *((volatile unsigned int*)(0x42C00C10UL)) -#define bFM3_DMAC_DMACA5_TC5 *((volatile unsigned int*)(0x42C00C14UL)) -#define bFM3_DMAC_DMACA5_TC6 *((volatile unsigned int*)(0x42C00C18UL)) -#define bFM3_DMAC_DMACA5_TC7 *((volatile unsigned int*)(0x42C00C1CUL)) -#define bFM3_DMAC_DMACA5_TC8 *((volatile unsigned int*)(0x42C00C20UL)) -#define bFM3_DMAC_DMACA5_TC9 *((volatile unsigned int*)(0x42C00C24UL)) -#define bFM3_DMAC_DMACA5_TC10 *((volatile unsigned int*)(0x42C00C28UL)) -#define bFM3_DMAC_DMACA5_TC11 *((volatile unsigned int*)(0x42C00C2CUL)) -#define bFM3_DMAC_DMACA5_TC12 *((volatile unsigned int*)(0x42C00C30UL)) -#define bFM3_DMAC_DMACA5_TC13 *((volatile unsigned int*)(0x42C00C34UL)) -#define bFM3_DMAC_DMACA5_TC14 *((volatile unsigned int*)(0x42C00C38UL)) -#define bFM3_DMAC_DMACA5_TC15 *((volatile unsigned int*)(0x42C00C3CUL)) -#define bFM3_DMAC_DMACA5_BC0 *((volatile unsigned int*)(0x42C00C40UL)) -#define bFM3_DMAC_DMACA5_BC1 *((volatile unsigned int*)(0x42C00C44UL)) -#define bFM3_DMAC_DMACA5_BC2 *((volatile unsigned int*)(0x42C00C48UL)) -#define bFM3_DMAC_DMACA5_BC3 *((volatile unsigned int*)(0x42C00C4CUL)) -#define bFM3_DMAC_DMACA5_IS0 *((volatile unsigned int*)(0x42C00C5CUL)) -#define bFM3_DMAC_DMACA5_IS1 *((volatile unsigned int*)(0x42C00C60UL)) -#define bFM3_DMAC_DMACA5_IS2 *((volatile unsigned int*)(0x42C00C64UL)) -#define bFM3_DMAC_DMACA5_IS3 *((volatile unsigned int*)(0x42C00C68UL)) -#define bFM3_DMAC_DMACA5_IS4 *((volatile unsigned int*)(0x42C00C6CUL)) -#define bFM3_DMAC_DMACA5_IS5 *((volatile unsigned int*)(0x42C00C70UL)) -#define bFM3_DMAC_DMACA5_ST *((volatile unsigned int*)(0x42C00C74UL)) -#define bFM3_DMAC_DMACA5_PB *((volatile unsigned int*)(0x42C00C78UL)) -#define bFM3_DMAC_DMACA5_EB *((volatile unsigned int*)(0x42C00C7CUL)) -#define bFM3_DMAC_DMACB5_EM *((volatile unsigned int*)(0x42C00C80UL)) -#define bFM3_DMAC_DMACB5_SS0 *((volatile unsigned int*)(0x42C00CC0UL)) -#define bFM3_DMAC_DMACB5_SS1 *((volatile unsigned int*)(0x42C00CC4UL)) -#define bFM3_DMAC_DMACB5_SS2 *((volatile unsigned int*)(0x42C00CC8UL)) -#define bFM3_DMAC_DMACB5_CI *((volatile unsigned int*)(0x42C00CCCUL)) -#define bFM3_DMAC_DMACB5_EI *((volatile unsigned int*)(0x42C00CD0UL)) -#define bFM3_DMAC_DMACB5_RD *((volatile unsigned int*)(0x42C00CD4UL)) -#define bFM3_DMAC_DMACB5_RS *((volatile unsigned int*)(0x42C00CD8UL)) -#define bFM3_DMAC_DMACB5_RC *((volatile unsigned int*)(0x42C00CDCUL)) -#define bFM3_DMAC_DMACB5_FD *((volatile unsigned int*)(0x42C00CE0UL)) -#define bFM3_DMAC_DMACB5_FS *((volatile unsigned int*)(0x42C00CE4UL)) -#define bFM3_DMAC_DMACB5_TW0 *((volatile unsigned int*)(0x42C00CE8UL)) -#define bFM3_DMAC_DMACB5_TW1 *((volatile unsigned int*)(0x42C00CECUL)) -#define bFM3_DMAC_DMACB5_MS0 *((volatile unsigned int*)(0x42C00CF0UL)) -#define bFM3_DMAC_DMACB5_MS1 *((volatile unsigned int*)(0x42C00CF4UL)) -#define bFM3_DMAC_DMACA6_TC0 *((volatile unsigned int*)(0x42C00E00UL)) -#define bFM3_DMAC_DMACA6_TC1 *((volatile unsigned int*)(0x42C00E04UL)) -#define bFM3_DMAC_DMACA6_TC2 *((volatile unsigned int*)(0x42C00E08UL)) -#define bFM3_DMAC_DMACA6_TC3 *((volatile unsigned int*)(0x42C00E0CUL)) -#define bFM3_DMAC_DMACA6_TC4 *((volatile unsigned int*)(0x42C00E10UL)) -#define bFM3_DMAC_DMACA6_TC5 *((volatile unsigned int*)(0x42C00E14UL)) -#define bFM3_DMAC_DMACA6_TC6 *((volatile unsigned int*)(0x42C00E18UL)) -#define bFM3_DMAC_DMACA6_TC7 *((volatile unsigned int*)(0x42C00E1CUL)) -#define bFM3_DMAC_DMACA6_TC8 *((volatile unsigned int*)(0x42C00E20UL)) -#define bFM3_DMAC_DMACA6_TC9 *((volatile unsigned int*)(0x42C00E24UL)) -#define bFM3_DMAC_DMACA6_TC10 *((volatile unsigned int*)(0x42C00E28UL)) -#define bFM3_DMAC_DMACA6_TC11 *((volatile unsigned int*)(0x42C00E2CUL)) -#define bFM3_DMAC_DMACA6_TC12 *((volatile unsigned int*)(0x42C00E30UL)) -#define bFM3_DMAC_DMACA6_TC13 *((volatile unsigned int*)(0x42C00E34UL)) -#define bFM3_DMAC_DMACA6_TC14 *((volatile unsigned int*)(0x42C00E38UL)) -#define bFM3_DMAC_DMACA6_TC15 *((volatile unsigned int*)(0x42C00E3CUL)) -#define bFM3_DMAC_DMACA6_BC0 *((volatile unsigned int*)(0x42C00E40UL)) -#define bFM3_DMAC_DMACA6_BC1 *((volatile unsigned int*)(0x42C00E44UL)) -#define bFM3_DMAC_DMACA6_BC2 *((volatile unsigned int*)(0x42C00E48UL)) -#define bFM3_DMAC_DMACA6_BC3 *((volatile unsigned int*)(0x42C00E4CUL)) -#define bFM3_DMAC_DMACA6_IS0 *((volatile unsigned int*)(0x42C00E5CUL)) -#define bFM3_DMAC_DMACA6_IS1 *((volatile unsigned int*)(0x42C00E60UL)) -#define bFM3_DMAC_DMACA6_IS2 *((volatile unsigned int*)(0x42C00E64UL)) -#define bFM3_DMAC_DMACA6_IS3 *((volatile unsigned int*)(0x42C00E68UL)) -#define bFM3_DMAC_DMACA6_IS4 *((volatile unsigned int*)(0x42C00E6CUL)) -#define bFM3_DMAC_DMACA6_IS5 *((volatile unsigned int*)(0x42C00E70UL)) -#define bFM3_DMAC_DMACA6_ST *((volatile unsigned int*)(0x42C00E74UL)) -#define bFM3_DMAC_DMACA6_PB *((volatile unsigned int*)(0x42C00E78UL)) -#define bFM3_DMAC_DMACA6_EB *((volatile unsigned int*)(0x42C00E7CUL)) -#define bFM3_DMAC_DMACB6_EM *((volatile unsigned int*)(0x42C00E80UL)) -#define bFM3_DMAC_DMACB6_SS0 *((volatile unsigned int*)(0x42C00EC0UL)) -#define bFM3_DMAC_DMACB6_SS1 *((volatile unsigned int*)(0x42C00EC4UL)) -#define bFM3_DMAC_DMACB6_SS2 *((volatile unsigned int*)(0x42C00EC8UL)) -#define bFM3_DMAC_DMACB6_CI *((volatile unsigned int*)(0x42C00ECCUL)) -#define bFM3_DMAC_DMACB6_EI *((volatile unsigned int*)(0x42C00ED0UL)) -#define bFM3_DMAC_DMACB6_RD *((volatile unsigned int*)(0x42C00ED4UL)) -#define bFM3_DMAC_DMACB6_RS *((volatile unsigned int*)(0x42C00ED8UL)) -#define bFM3_DMAC_DMACB6_RC *((volatile unsigned int*)(0x42C00EDCUL)) -#define bFM3_DMAC_DMACB6_FD *((volatile unsigned int*)(0x42C00EE0UL)) -#define bFM3_DMAC_DMACB6_FS *((volatile unsigned int*)(0x42C00EE4UL)) -#define bFM3_DMAC_DMACB6_TW0 *((volatile unsigned int*)(0x42C00EE8UL)) -#define bFM3_DMAC_DMACB6_TW1 *((volatile unsigned int*)(0x42C00EECUL)) -#define bFM3_DMAC_DMACB6_MS0 *((volatile unsigned int*)(0x42C00EF0UL)) -#define bFM3_DMAC_DMACB6_MS1 *((volatile unsigned int*)(0x42C00EF4UL)) -#define bFM3_DMAC_DMACA7_TC0 *((volatile unsigned int*)(0x42C01000UL)) -#define bFM3_DMAC_DMACA7_TC1 *((volatile unsigned int*)(0x42C01004UL)) -#define bFM3_DMAC_DMACA7_TC2 *((volatile unsigned int*)(0x42C01008UL)) -#define bFM3_DMAC_DMACA7_TC3 *((volatile unsigned int*)(0x42C0100CUL)) -#define bFM3_DMAC_DMACA7_TC4 *((volatile unsigned int*)(0x42C01010UL)) -#define bFM3_DMAC_DMACA7_TC5 *((volatile unsigned int*)(0x42C01014UL)) -#define bFM3_DMAC_DMACA7_TC6 *((volatile unsigned int*)(0x42C01018UL)) -#define bFM3_DMAC_DMACA7_TC7 *((volatile unsigned int*)(0x42C0101CUL)) -#define bFM3_DMAC_DMACA7_TC8 *((volatile unsigned int*)(0x42C01020UL)) -#define bFM3_DMAC_DMACA7_TC9 *((volatile unsigned int*)(0x42C01024UL)) -#define bFM3_DMAC_DMACA7_TC10 *((volatile unsigned int*)(0x42C01028UL)) -#define bFM3_DMAC_DMACA7_TC11 *((volatile unsigned int*)(0x42C0102CUL)) -#define bFM3_DMAC_DMACA7_TC12 *((volatile unsigned int*)(0x42C01030UL)) -#define bFM3_DMAC_DMACA7_TC13 *((volatile unsigned int*)(0x42C01034UL)) -#define bFM3_DMAC_DMACA7_TC14 *((volatile unsigned int*)(0x42C01038UL)) -#define bFM3_DMAC_DMACA7_TC15 *((volatile unsigned int*)(0x42C0103CUL)) -#define bFM3_DMAC_DMACA7_BC0 *((volatile unsigned int*)(0x42C01040UL)) -#define bFM3_DMAC_DMACA7_BC1 *((volatile unsigned int*)(0x42C01044UL)) -#define bFM3_DMAC_DMACA7_BC2 *((volatile unsigned int*)(0x42C01048UL)) -#define bFM3_DMAC_DMACA7_BC3 *((volatile unsigned int*)(0x42C0104CUL)) -#define bFM3_DMAC_DMACA7_IS0 *((volatile unsigned int*)(0x42C0105CUL)) -#define bFM3_DMAC_DMACA7_IS1 *((volatile unsigned int*)(0x42C01060UL)) -#define bFM3_DMAC_DMACA7_IS2 *((volatile unsigned int*)(0x42C01064UL)) -#define bFM3_DMAC_DMACA7_IS3 *((volatile unsigned int*)(0x42C01068UL)) -#define bFM3_DMAC_DMACA7_IS4 *((volatile unsigned int*)(0x42C0106CUL)) -#define bFM3_DMAC_DMACA7_IS5 *((volatile unsigned int*)(0x42C01070UL)) -#define bFM3_DMAC_DMACA7_ST *((volatile unsigned int*)(0x42C01074UL)) -#define bFM3_DMAC_DMACA7_PB *((volatile unsigned int*)(0x42C01078UL)) -#define bFM3_DMAC_DMACA7_EB *((volatile unsigned int*)(0x42C0107CUL)) -#define bFM3_DMAC_DMACB7_EM *((volatile unsigned int*)(0x42C01080UL)) -#define bFM3_DMAC_DMACB7_SS0 *((volatile unsigned int*)(0x42C010C0UL)) -#define bFM3_DMAC_DMACB7_SS1 *((volatile unsigned int*)(0x42C010C4UL)) -#define bFM3_DMAC_DMACB7_SS2 *((volatile unsigned int*)(0x42C010C8UL)) -#define bFM3_DMAC_DMACB7_CI *((volatile unsigned int*)(0x42C010CCUL)) -#define bFM3_DMAC_DMACB7_EI *((volatile unsigned int*)(0x42C010D0UL)) -#define bFM3_DMAC_DMACB7_RD *((volatile unsigned int*)(0x42C010D4UL)) -#define bFM3_DMAC_DMACB7_RS *((volatile unsigned int*)(0x42C010D8UL)) -#define bFM3_DMAC_DMACB7_RC *((volatile unsigned int*)(0x42C010DCUL)) -#define bFM3_DMAC_DMACB7_FD *((volatile unsigned int*)(0x42C010E0UL)) -#define bFM3_DMAC_DMACB7_FS *((volatile unsigned int*)(0x42C010E4UL)) -#define bFM3_DMAC_DMACB7_TW0 *((volatile unsigned int*)(0x42C010E8UL)) -#define bFM3_DMAC_DMACB7_TW1 *((volatile unsigned int*)(0x42C010ECUL)) -#define bFM3_DMAC_DMACB7_MS0 *((volatile unsigned int*)(0x42C010F0UL)) -#define bFM3_DMAC_DMACB7_MS1 *((volatile unsigned int*)(0x42C010F4UL)) - -/* CAN channel 0 registers */ -#define bFM3_CAN0_CTRLR_INIT *((volatile unsigned int*)(0x42C40000UL)) -#define bFM3_CAN0_CTRLR_IE *((volatile unsigned int*)(0x42C40004UL)) -#define bFM3_CAN0_CTRLR_SIE *((volatile unsigned int*)(0x42C40008UL)) -#define bFM3_CAN0_CTRLR_EIE *((volatile unsigned int*)(0x42C4000CUL)) -#define bFM3_CAN0_CTRLR_DAR *((volatile unsigned int*)(0x42C40014UL)) -#define bFM3_CAN0_CTRLR_CCE *((volatile unsigned int*)(0x42C40018UL)) -#define bFM3_CAN0_CTRLR_TEST *((volatile unsigned int*)(0x42C4001CUL)) -#define bFM3_CAN0_STATR_LEC0 *((volatile unsigned int*)(0x42C40040UL)) -#define bFM3_CAN0_STATR_LEC1 *((volatile unsigned int*)(0x42C40044UL)) -#define bFM3_CAN0_STATR_LEC2 *((volatile unsigned int*)(0x42C40048UL)) -#define bFM3_CAN0_STATR_TXOK *((volatile unsigned int*)(0x42C4004CUL)) -#define bFM3_CAN0_STATR_RXOK *((volatile unsigned int*)(0x42C40050UL)) -#define bFM3_CAN0_STATR_EPASS *((volatile unsigned int*)(0x42C40054UL)) -#define bFM3_CAN0_STATR_EWARM *((volatile unsigned int*)(0x42C40058UL)) -#define bFM3_CAN0_STATR_BOFF *((volatile unsigned int*)(0x42C4005CUL)) -#define bFM3_CAN0_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C40080UL)) -#define bFM3_CAN0_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C40084UL)) -#define bFM3_CAN0_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C40088UL)) -#define bFM3_CAN0_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C4008CUL)) -#define bFM3_CAN0_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C40090UL)) -#define bFM3_CAN0_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C40094UL)) -#define bFM3_CAN0_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C40098UL)) -#define bFM3_CAN0_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C4009CUL)) -#define bFM3_CAN0_ERRCNT_REC0 *((volatile unsigned int*)(0x42C400A0UL)) -#define bFM3_CAN0_ERRCNT_REC1 *((volatile unsigned int*)(0x42C400A4UL)) -#define bFM3_CAN0_ERRCNT_REC2 *((volatile unsigned int*)(0x42C400A8UL)) -#define bFM3_CAN0_ERRCNT_REC3 *((volatile unsigned int*)(0x42C400ACUL)) -#define bFM3_CAN0_ERRCNT_REC4 *((volatile unsigned int*)(0x42C400B0UL)) -#define bFM3_CAN0_ERRCNT_REC5 *((volatile unsigned int*)(0x42C400B4UL)) -#define bFM3_CAN0_ERRCNT_REC6 *((volatile unsigned int*)(0x42C400B8UL)) -#define bFM3_CAN0_ERRCNT_RP *((volatile unsigned int*)(0x42C400BCUL)) -#define bFM3_CAN0_BTR_BRP0 *((volatile unsigned int*)(0x42C400C0UL)) -#define bFM3_CAN0_BTR_BRP1 *((volatile unsigned int*)(0x42C400C4UL)) -#define bFM3_CAN0_BTR_BRP2 *((volatile unsigned int*)(0x42C400C8UL)) -#define bFM3_CAN0_BTR_BRP3 *((volatile unsigned int*)(0x42C400CCUL)) -#define bFM3_CAN0_BTR_BRP4 *((volatile unsigned int*)(0x42C400D0UL)) -#define bFM3_CAN0_BTR_BRP5 *((volatile unsigned int*)(0x42C400D4UL)) -#define bFM3_CAN0_BTR_SJW0 *((volatile unsigned int*)(0x42C400D8UL)) -#define bFM3_CAN0_BTR_SJW1 *((volatile unsigned int*)(0x42C400DCUL)) -#define bFM3_CAN0_BTR_TSEG10 *((volatile unsigned int*)(0x42C400E0UL)) -#define bFM3_CAN0_BTR_TSEG11 *((volatile unsigned int*)(0x42C400E4UL)) -#define bFM3_CAN0_BTR_TSEG12 *((volatile unsigned int*)(0x42C400E8UL)) -#define bFM3_CAN0_BTR_TSEG13 *((volatile unsigned int*)(0x42C400ECUL)) -#define bFM3_CAN0_BTR_TSEG20 *((volatile unsigned int*)(0x42C400F0UL)) -#define bFM3_CAN0_BTR_TSEG21 *((volatile unsigned int*)(0x42C400F4UL)) -#define bFM3_CAN0_BTR_TSEG22 *((volatile unsigned int*)(0x42C400F8UL)) -#define bFM3_CAN0_INTR_INTID0 *((volatile unsigned int*)(0x42C40100UL)) -#define bFM3_CAN0_INTR_INTID1 *((volatile unsigned int*)(0x42C40104UL)) -#define bFM3_CAN0_INTR_INTID2 *((volatile unsigned int*)(0x42C40108UL)) -#define bFM3_CAN0_INTR_INTID3 *((volatile unsigned int*)(0x42C4010CUL)) -#define bFM3_CAN0_INTR_INTID4 *((volatile unsigned int*)(0x42C40110UL)) -#define bFM3_CAN0_INTR_INTID5 *((volatile unsigned int*)(0x42C40114UL)) -#define bFM3_CAN0_INTR_INTID6 *((volatile unsigned int*)(0x42C40118UL)) -#define bFM3_CAN0_INTR_INTID7 *((volatile unsigned int*)(0x42C4011CUL)) -#define bFM3_CAN0_INTR_INTID8 *((volatile unsigned int*)(0x42C40120UL)) -#define bFM3_CAN0_INTR_INTID9 *((volatile unsigned int*)(0x42C40124UL)) -#define bFM3_CAN0_INTR_INTID10 *((volatile unsigned int*)(0x42C40128UL)) -#define bFM3_CAN0_INTR_INTID11 *((volatile unsigned int*)(0x42C4012CUL)) -#define bFM3_CAN0_INTR_INTID12 *((volatile unsigned int*)(0x42C40130UL)) -#define bFM3_CAN0_INTR_INTID13 *((volatile unsigned int*)(0x42C40134UL)) -#define bFM3_CAN0_INTR_INTID14 *((volatile unsigned int*)(0x42C40138UL)) -#define bFM3_CAN0_INTR_INTID15 *((volatile unsigned int*)(0x42C4013CUL)) -#define bFM3_CAN0_TESTR_BASIC *((volatile unsigned int*)(0x42C40148UL)) -#define bFM3_CAN0_TESTR_SILENT *((volatile unsigned int*)(0x42C4014CUL)) -#define bFM3_CAN0_TESTR_LBACK *((volatile unsigned int*)(0x42C40150UL)) -#define bFM3_CAN0_TESTR_TX0 *((volatile unsigned int*)(0x42C40154UL)) -#define bFM3_CAN0_TESTR_TX1 *((volatile unsigned int*)(0x42C40158UL)) -#define bFM3_CAN0_TESTR_RX *((volatile unsigned int*)(0x42C4015CUL)) -#define bFM3_CAN0_BRPER_BRPE0 *((volatile unsigned int*)(0x42C40180UL)) -#define bFM3_CAN0_BRPER_BRPE1 *((volatile unsigned int*)(0x42C40184UL)) -#define bFM3_CAN0_BRPER_BRPE2 *((volatile unsigned int*)(0x42C40188UL)) -#define bFM3_CAN0_BRPER_BRPE3 *((volatile unsigned int*)(0x42C4018CUL)) -#define bFM3_CAN0_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C4023CUL)) -#define bFM3_CAN0_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C40240UL)) -#define bFM3_CAN0_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C40244UL)) -#define bFM3_CAN0_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C40248UL)) -#define bFM3_CAN0_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C40248UL)) -#define bFM3_CAN0_IF1CMSK_CIP *((volatile unsigned int*)(0x42C4024CUL)) -#define bFM3_CAN0_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C40250UL)) -#define bFM3_CAN0_IF1CMSK_ARB *((volatile unsigned int*)(0x42C40254UL)) -#define bFM3_CAN0_IF1CMSK_MASK *((volatile unsigned int*)(0x42C40258UL)) -#define bFM3_CAN0_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C4025CUL)) -#define bFM3_CAN0_IF1MSK_MDIR *((volatile unsigned int*)(0x42C402F8UL)) -#define bFM3_CAN0_IF1MSK_MXTD *((volatile unsigned int*)(0x42C402FCUL)) -#define bFM3_CAN0_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C402F8UL)) -#define bFM3_CAN0_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C402FCUL)) -#define bFM3_CAN0_IF1ARB_DIR *((volatile unsigned int*)(0x42C40374UL)) -#define bFM3_CAN0_IF1ARB_XTD *((volatile unsigned int*)(0x42C40378UL)) -#define bFM3_CAN0_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) -#define bFM3_CAN0_IF1ARB2_DIR *((volatile unsigned int*)(0x42C40374UL)) -#define bFM3_CAN0_IF1ARB2_XTD *((volatile unsigned int*)(0x42C40378UL)) -#define bFM3_CAN0_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) -#define bFM3_CAN0_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C40380UL)) -#define bFM3_CAN0_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C40384UL)) -#define bFM3_CAN0_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C40388UL)) -#define bFM3_CAN0_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C4038CUL)) -#define bFM3_CAN0_IF1MCTR_EOB *((volatile unsigned int*)(0x42C4039CUL)) -#define bFM3_CAN0_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C403A0UL)) -#define bFM3_CAN0_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C403A4UL)) -#define bFM3_CAN0_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C403A8UL)) -#define bFM3_CAN0_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C403ACUL)) -#define bFM3_CAN0_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C403B0UL)) -#define bFM3_CAN0_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C403B4UL)) -#define bFM3_CAN0_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C403B8UL)) -#define bFM3_CAN0_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C403BCUL)) -#define bFM3_CAN0_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C4083CUL)) -#define bFM3_CAN0_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C40840UL)) -#define bFM3_CAN0_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C40844UL)) -#define bFM3_CAN0_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C40848UL)) -#define bFM3_CAN0_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C40848UL)) -#define bFM3_CAN0_IF2CMSK_CIP *((volatile unsigned int*)(0x42C4084CUL)) -#define bFM3_CAN0_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C40850UL)) -#define bFM3_CAN0_IF2CMSK_ARB *((volatile unsigned int*)(0x42C40854UL)) -#define bFM3_CAN0_IF2CMSK_MASK *((volatile unsigned int*)(0x42C40858UL)) -#define bFM3_CAN0_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C4085CUL)) -#define bFM3_CAN0_IF2MSK_MDIR *((volatile unsigned int*)(0x42C408F8UL)) -#define bFM3_CAN0_IF2MSK_MXTD *((volatile unsigned int*)(0x42C408FCUL)) -#define bFM3_CAN0_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C408F8UL)) -#define bFM3_CAN0_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C408FCUL)) -#define bFM3_CAN0_IF2ARB_DIR *((volatile unsigned int*)(0x42C40974UL)) -#define bFM3_CAN0_IF2ARB_XTD *((volatile unsigned int*)(0x42C40978UL)) -#define bFM3_CAN0_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) -#define bFM3_CAN0_IF2ARB2_DIR *((volatile unsigned int*)(0x42C40974UL)) -#define bFM3_CAN0_IF2ARB2_XTD *((volatile unsigned int*)(0x42C40978UL)) -#define bFM3_CAN0_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) -#define bFM3_CAN0_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C40980UL)) -#define bFM3_CAN0_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C40984UL)) -#define bFM3_CAN0_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C40988UL)) -#define bFM3_CAN0_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C4098CUL)) -#define bFM3_CAN0_IF2MCTR_EOB *((volatile unsigned int*)(0x42C4099CUL)) -#define bFM3_CAN0_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C409A0UL)) -#define bFM3_CAN0_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C409A4UL)) -#define bFM3_CAN0_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C409A8UL)) -#define bFM3_CAN0_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C409ACUL)) -#define bFM3_CAN0_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C409B0UL)) -#define bFM3_CAN0_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C409B4UL)) -#define bFM3_CAN0_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C409B8UL)) -#define bFM3_CAN0_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C409BCUL)) -#define bFM3_CAN0_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) -#define bFM3_CAN0_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) -#define bFM3_CAN0_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) -#define bFM3_CAN0_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) -#define bFM3_CAN0_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) -#define bFM3_CAN0_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) -#define bFM3_CAN0_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) -#define bFM3_CAN0_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) -#define bFM3_CAN0_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) -#define bFM3_CAN0_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) -#define bFM3_CAN0_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) -#define bFM3_CAN0_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) -#define bFM3_CAN0_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) -#define bFM3_CAN0_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) -#define bFM3_CAN0_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) -#define bFM3_CAN0_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) -#define bFM3_CAN0_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) -#define bFM3_CAN0_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) -#define bFM3_CAN0_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) -#define bFM3_CAN0_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) -#define bFM3_CAN0_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) -#define bFM3_CAN0_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) -#define bFM3_CAN0_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) -#define bFM3_CAN0_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) -#define bFM3_CAN0_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) -#define bFM3_CAN0_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) -#define bFM3_CAN0_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) -#define bFM3_CAN0_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) -#define bFM3_CAN0_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) -#define bFM3_CAN0_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) -#define bFM3_CAN0_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) -#define bFM3_CAN0_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) -#define bFM3_CAN0_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) -#define bFM3_CAN0_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) -#define bFM3_CAN0_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) -#define bFM3_CAN0_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) -#define bFM3_CAN0_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) -#define bFM3_CAN0_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) -#define bFM3_CAN0_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) -#define bFM3_CAN0_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) -#define bFM3_CAN0_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) -#define bFM3_CAN0_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) -#define bFM3_CAN0_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) -#define bFM3_CAN0_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) -#define bFM3_CAN0_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) -#define bFM3_CAN0_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) -#define bFM3_CAN0_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) -#define bFM3_CAN0_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) -#define bFM3_CAN0_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) -#define bFM3_CAN0_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) -#define bFM3_CAN0_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) -#define bFM3_CAN0_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) -#define bFM3_CAN0_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) -#define bFM3_CAN0_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) -#define bFM3_CAN0_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) -#define bFM3_CAN0_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) -#define bFM3_CAN0_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) -#define bFM3_CAN0_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) -#define bFM3_CAN0_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) -#define bFM3_CAN0_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) -#define bFM3_CAN0_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) -#define bFM3_CAN0_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) -#define bFM3_CAN0_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) -#define bFM3_CAN0_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) -#define bFM3_CAN0_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) -#define bFM3_CAN0_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) -#define bFM3_CAN0_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) -#define bFM3_CAN0_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) -#define bFM3_CAN0_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) -#define bFM3_CAN0_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) -#define bFM3_CAN0_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) -#define bFM3_CAN0_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) -#define bFM3_CAN0_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) -#define bFM3_CAN0_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) -#define bFM3_CAN0_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) -#define bFM3_CAN0_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) -#define bFM3_CAN0_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) -#define bFM3_CAN0_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) -#define bFM3_CAN0_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) -#define bFM3_CAN0_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) -#define bFM3_CAN0_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) -#define bFM3_CAN0_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) -#define bFM3_CAN0_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) -#define bFM3_CAN0_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) -#define bFM3_CAN0_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) -#define bFM3_CAN0_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) -#define bFM3_CAN0_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) -#define bFM3_CAN0_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) -#define bFM3_CAN0_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) -#define bFM3_CAN0_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) -#define bFM3_CAN0_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) -#define bFM3_CAN0_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) -#define bFM3_CAN0_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) -#define bFM3_CAN0_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) -#define bFM3_CAN0_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) -#define bFM3_CAN0_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) -#define bFM3_CAN0_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) -#define bFM3_CAN0_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) -#define bFM3_CAN0_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) -#define bFM3_CAN0_INTPND_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) -#define bFM3_CAN0_INTPND_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) -#define bFM3_CAN0_INTPND_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) -#define bFM3_CAN0_INTPND_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) -#define bFM3_CAN0_INTPND_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) -#define bFM3_CAN0_INTPND_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) -#define bFM3_CAN0_INTPND_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) -#define bFM3_CAN0_INTPND_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) -#define bFM3_CAN0_INTPND_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) -#define bFM3_CAN0_INTPND_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) -#define bFM3_CAN0_INTPND_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) -#define bFM3_CAN0_INTPND_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) -#define bFM3_CAN0_INTPND_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) -#define bFM3_CAN0_INTPND_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) -#define bFM3_CAN0_INTPND_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) -#define bFM3_CAN0_INTPND_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) -#define bFM3_CAN0_INTPND_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) -#define bFM3_CAN0_INTPND_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) -#define bFM3_CAN0_INTPND_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) -#define bFM3_CAN0_INTPND_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) -#define bFM3_CAN0_INTPND_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) -#define bFM3_CAN0_INTPND_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) -#define bFM3_CAN0_INTPND_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) -#define bFM3_CAN0_INTPND_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) -#define bFM3_CAN0_INTPND_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) -#define bFM3_CAN0_INTPND_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) -#define bFM3_CAN0_INTPND_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) -#define bFM3_CAN0_INTPND_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) -#define bFM3_CAN0_INTPND_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) -#define bFM3_CAN0_INTPND_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) -#define bFM3_CAN0_INTPND_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) -#define bFM3_CAN0_INTPND_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) -#define bFM3_CAN0_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) -#define bFM3_CAN0_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) -#define bFM3_CAN0_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) -#define bFM3_CAN0_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) -#define bFM3_CAN0_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) -#define bFM3_CAN0_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) -#define bFM3_CAN0_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) -#define bFM3_CAN0_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) -#define bFM3_CAN0_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) -#define bFM3_CAN0_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) -#define bFM3_CAN0_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) -#define bFM3_CAN0_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) -#define bFM3_CAN0_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) -#define bFM3_CAN0_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) -#define bFM3_CAN0_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) -#define bFM3_CAN0_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) -#define bFM3_CAN0_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) -#define bFM3_CAN0_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) -#define bFM3_CAN0_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) -#define bFM3_CAN0_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) -#define bFM3_CAN0_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) -#define bFM3_CAN0_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) -#define bFM3_CAN0_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) -#define bFM3_CAN0_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) -#define bFM3_CAN0_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) -#define bFM3_CAN0_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) -#define bFM3_CAN0_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) -#define bFM3_CAN0_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) -#define bFM3_CAN0_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) -#define bFM3_CAN0_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) -#define bFM3_CAN0_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) -#define bFM3_CAN0_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) -#define bFM3_CAN0_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) -#define bFM3_CAN0_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) -#define bFM3_CAN0_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) -#define bFM3_CAN0_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) - -/* CAN channel 1 registers */ -#define bFM3_CAN1_CTRLR_INIT *((volatile unsigned int*)(0x42C60000UL)) -#define bFM3_CAN1_CTRLR_IE *((volatile unsigned int*)(0x42C60004UL)) -#define bFM3_CAN1_CTRLR_SIE *((volatile unsigned int*)(0x42C60008UL)) -#define bFM3_CAN1_CTRLR_EIE *((volatile unsigned int*)(0x42C6000CUL)) -#define bFM3_CAN1_CTRLR_DAR *((volatile unsigned int*)(0x42C60014UL)) -#define bFM3_CAN1_CTRLR_CCE *((volatile unsigned int*)(0x42C60018UL)) -#define bFM3_CAN1_CTRLR_TEST *((volatile unsigned int*)(0x42C6001CUL)) -#define bFM3_CAN1_STATR_LEC0 *((volatile unsigned int*)(0x42C60040UL)) -#define bFM3_CAN1_STATR_LEC1 *((volatile unsigned int*)(0x42C60044UL)) -#define bFM3_CAN1_STATR_LEC2 *((volatile unsigned int*)(0x42C60048UL)) -#define bFM3_CAN1_STATR_TXOK *((volatile unsigned int*)(0x42C6004CUL)) -#define bFM3_CAN1_STATR_RXOK *((volatile unsigned int*)(0x42C60050UL)) -#define bFM3_CAN1_STATR_EPASS *((volatile unsigned int*)(0x42C60054UL)) -#define bFM3_CAN1_STATR_EWARM *((volatile unsigned int*)(0x42C60058UL)) -#define bFM3_CAN1_STATR_BOFF *((volatile unsigned int*)(0x42C6005CUL)) -#define bFM3_CAN1_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C60080UL)) -#define bFM3_CAN1_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C60084UL)) -#define bFM3_CAN1_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C60088UL)) -#define bFM3_CAN1_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C6008CUL)) -#define bFM3_CAN1_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C60090UL)) -#define bFM3_CAN1_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C60094UL)) -#define bFM3_CAN1_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C60098UL)) -#define bFM3_CAN1_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C6009CUL)) -#define bFM3_CAN1_ERRCNT_REC0 *((volatile unsigned int*)(0x42C600A0UL)) -#define bFM3_CAN1_ERRCNT_REC1 *((volatile unsigned int*)(0x42C600A4UL)) -#define bFM3_CAN1_ERRCNT_REC2 *((volatile unsigned int*)(0x42C600A8UL)) -#define bFM3_CAN1_ERRCNT_REC3 *((volatile unsigned int*)(0x42C600ACUL)) -#define bFM3_CAN1_ERRCNT_REC4 *((volatile unsigned int*)(0x42C600B0UL)) -#define bFM3_CAN1_ERRCNT_REC5 *((volatile unsigned int*)(0x42C600B4UL)) -#define bFM3_CAN1_ERRCNT_REC6 *((volatile unsigned int*)(0x42C600B8UL)) -#define bFM3_CAN1_ERRCNT_RP *((volatile unsigned int*)(0x42C600BCUL)) -#define bFM3_CAN1_BTR_BRP0 *((volatile unsigned int*)(0x42C600C0UL)) -#define bFM3_CAN1_BTR_BRP1 *((volatile unsigned int*)(0x42C600C4UL)) -#define bFM3_CAN1_BTR_BRP2 *((volatile unsigned int*)(0x42C600C8UL)) -#define bFM3_CAN1_BTR_BRP3 *((volatile unsigned int*)(0x42C600CCUL)) -#define bFM3_CAN1_BTR_BRP4 *((volatile unsigned int*)(0x42C600D0UL)) -#define bFM3_CAN1_BTR_BRP5 *((volatile unsigned int*)(0x42C600D4UL)) -#define bFM3_CAN1_BTR_SJW0 *((volatile unsigned int*)(0x42C600D8UL)) -#define bFM3_CAN1_BTR_SJW1 *((volatile unsigned int*)(0x42C600DCUL)) -#define bFM3_CAN1_BTR_TSEG10 *((volatile unsigned int*)(0x42C600E0UL)) -#define bFM3_CAN1_BTR_TSEG11 *((volatile unsigned int*)(0x42C600E4UL)) -#define bFM3_CAN1_BTR_TSEG12 *((volatile unsigned int*)(0x42C600E8UL)) -#define bFM3_CAN1_BTR_TSEG13 *((volatile unsigned int*)(0x42C600ECUL)) -#define bFM3_CAN1_BTR_TSEG20 *((volatile unsigned int*)(0x42C600F0UL)) -#define bFM3_CAN1_BTR_TSEG21 *((volatile unsigned int*)(0x42C600F4UL)) -#define bFM3_CAN1_BTR_TSEG22 *((volatile unsigned int*)(0x42C600F8UL)) -#define bFM3_CAN1_INTR_INTID0 *((volatile unsigned int*)(0x42C60100UL)) -#define bFM3_CAN1_INTR_INTID1 *((volatile unsigned int*)(0x42C60104UL)) -#define bFM3_CAN1_INTR_INTID2 *((volatile unsigned int*)(0x42C60108UL)) -#define bFM3_CAN1_INTR_INTID3 *((volatile unsigned int*)(0x42C6010CUL)) -#define bFM3_CAN1_INTR_INTID4 *((volatile unsigned int*)(0x42C60110UL)) -#define bFM3_CAN1_INTR_INTID5 *((volatile unsigned int*)(0x42C60114UL)) -#define bFM3_CAN1_INTR_INTID6 *((volatile unsigned int*)(0x42C60118UL)) -#define bFM3_CAN1_INTR_INTID7 *((volatile unsigned int*)(0x42C6011CUL)) -#define bFM3_CAN1_INTR_INTID8 *((volatile unsigned int*)(0x42C60120UL)) -#define bFM3_CAN1_INTR_INTID9 *((volatile unsigned int*)(0x42C60124UL)) -#define bFM3_CAN1_INTR_INTID10 *((volatile unsigned int*)(0x42C60128UL)) -#define bFM3_CAN1_INTR_INTID11 *((volatile unsigned int*)(0x42C6012CUL)) -#define bFM3_CAN1_INTR_INTID12 *((volatile unsigned int*)(0x42C60130UL)) -#define bFM3_CAN1_INTR_INTID13 *((volatile unsigned int*)(0x42C60134UL)) -#define bFM3_CAN1_INTR_INTID14 *((volatile unsigned int*)(0x42C60138UL)) -#define bFM3_CAN1_INTR_INTID15 *((volatile unsigned int*)(0x42C6013CUL)) -#define bFM3_CAN1_TESTR_BASIC *((volatile unsigned int*)(0x42C60148UL)) -#define bFM3_CAN1_TESTR_SILENT *((volatile unsigned int*)(0x42C6014CUL)) -#define bFM3_CAN1_TESTR_LBACK *((volatile unsigned int*)(0x42C60150UL)) -#define bFM3_CAN1_TESTR_TX0 *((volatile unsigned int*)(0x42C60154UL)) -#define bFM3_CAN1_TESTR_TX1 *((volatile unsigned int*)(0x42C60158UL)) -#define bFM3_CAN1_TESTR_RX *((volatile unsigned int*)(0x42C6015CUL)) -#define bFM3_CAN1_BRPER_BRPE0 *((volatile unsigned int*)(0x42C60180UL)) -#define bFM3_CAN1_BRPER_BRPE1 *((volatile unsigned int*)(0x42C60184UL)) -#define bFM3_CAN1_BRPER_BRPE2 *((volatile unsigned int*)(0x42C60188UL)) -#define bFM3_CAN1_BRPER_BRPE3 *((volatile unsigned int*)(0x42C6018CUL)) -#define bFM3_CAN1_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C6023CUL)) -#define bFM3_CAN1_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C60240UL)) -#define bFM3_CAN1_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C60244UL)) -#define bFM3_CAN1_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C60248UL)) -#define bFM3_CAN1_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C60248UL)) -#define bFM3_CAN1_IF1CMSK_CIP *((volatile unsigned int*)(0x42C6024CUL)) -#define bFM3_CAN1_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C60250UL)) -#define bFM3_CAN1_IF1CMSK_ARB *((volatile unsigned int*)(0x42C60254UL)) -#define bFM3_CAN1_IF1CMSK_MASK *((volatile unsigned int*)(0x42C60258UL)) -#define bFM3_CAN1_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C6025CUL)) -#define bFM3_CAN1_IF1MSK_MDIR *((volatile unsigned int*)(0x42C602F8UL)) -#define bFM3_CAN1_IF1MSK_MXTD *((volatile unsigned int*)(0x42C602FCUL)) -#define bFM3_CAN1_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C602F8UL)) -#define bFM3_CAN1_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C602FCUL)) -#define bFM3_CAN1_IF1ARB_DIR *((volatile unsigned int*)(0x42C60374UL)) -#define bFM3_CAN1_IF1ARB_XTD *((volatile unsigned int*)(0x42C60378UL)) -#define bFM3_CAN1_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) -#define bFM3_CAN1_IF1ARB2_DIR *((volatile unsigned int*)(0x42C60374UL)) -#define bFM3_CAN1_IF1ARB2_XTD *((volatile unsigned int*)(0x42C60378UL)) -#define bFM3_CAN1_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) -#define bFM3_CAN1_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C60380UL)) -#define bFM3_CAN1_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C60384UL)) -#define bFM3_CAN1_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C60388UL)) -#define bFM3_CAN1_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C6038CUL)) -#define bFM3_CAN1_IF1MCTR_EOB *((volatile unsigned int*)(0x42C6039CUL)) -#define bFM3_CAN1_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C603A0UL)) -#define bFM3_CAN1_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C603A4UL)) -#define bFM3_CAN1_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C603A8UL)) -#define bFM3_CAN1_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C603ACUL)) -#define bFM3_CAN1_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C603B0UL)) -#define bFM3_CAN1_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C603B4UL)) -#define bFM3_CAN1_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C603B8UL)) -#define bFM3_CAN1_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C603BCUL)) -#define bFM3_CAN1_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C6083CUL)) -#define bFM3_CAN1_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C60840UL)) -#define bFM3_CAN1_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C60844UL)) -#define bFM3_CAN1_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C60848UL)) -#define bFM3_CAN1_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C60848UL)) -#define bFM3_CAN1_IF2CMSK_CIP *((volatile unsigned int*)(0x42C6084CUL)) -#define bFM3_CAN1_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C60850UL)) -#define bFM3_CAN1_IF2CMSK_ARB *((volatile unsigned int*)(0x42C60854UL)) -#define bFM3_CAN1_IF2CMSK_MASK *((volatile unsigned int*)(0x42C60858UL)) -#define bFM3_CAN1_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C6085CUL)) -#define bFM3_CAN1_IF2MSK_MDIR *((volatile unsigned int*)(0x42C608F8UL)) -#define bFM3_CAN1_IF2MSK_MXTD *((volatile unsigned int*)(0x42C608FCUL)) -#define bFM3_CAN1_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C608F8UL)) -#define bFM3_CAN1_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C608FCUL)) -#define bFM3_CAN1_IF2ARB_DIR *((volatile unsigned int*)(0x42C60974UL)) -#define bFM3_CAN1_IF2ARB_XTD *((volatile unsigned int*)(0x42C60978UL)) -#define bFM3_CAN1_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) -#define bFM3_CAN1_IF2ARB2_DIR *((volatile unsigned int*)(0x42C60974UL)) -#define bFM3_CAN1_IF2ARB2_XTD *((volatile unsigned int*)(0x42C60978UL)) -#define bFM3_CAN1_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) -#define bFM3_CAN1_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C60980UL)) -#define bFM3_CAN1_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C60984UL)) -#define bFM3_CAN1_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C60988UL)) -#define bFM3_CAN1_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C6098CUL)) -#define bFM3_CAN1_IF2MCTR_EOB *((volatile unsigned int*)(0x42C6099CUL)) -#define bFM3_CAN1_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C609A0UL)) -#define bFM3_CAN1_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C609A4UL)) -#define bFM3_CAN1_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C609A8UL)) -#define bFM3_CAN1_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C609ACUL)) -#define bFM3_CAN1_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C609B0UL)) -#define bFM3_CAN1_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C609B4UL)) -#define bFM3_CAN1_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C609B8UL)) -#define bFM3_CAN1_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C609BCUL)) -#define bFM3_CAN1_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) -#define bFM3_CAN1_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) -#define bFM3_CAN1_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) -#define bFM3_CAN1_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) -#define bFM3_CAN1_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) -#define bFM3_CAN1_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) -#define bFM3_CAN1_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) -#define bFM3_CAN1_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) -#define bFM3_CAN1_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) -#define bFM3_CAN1_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) -#define bFM3_CAN1_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) -#define bFM3_CAN1_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) -#define bFM3_CAN1_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) -#define bFM3_CAN1_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) -#define bFM3_CAN1_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) -#define bFM3_CAN1_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) -#define bFM3_CAN1_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) -#define bFM3_CAN1_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) -#define bFM3_CAN1_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) -#define bFM3_CAN1_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) -#define bFM3_CAN1_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) -#define bFM3_CAN1_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) -#define bFM3_CAN1_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) -#define bFM3_CAN1_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) -#define bFM3_CAN1_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) -#define bFM3_CAN1_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) -#define bFM3_CAN1_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) -#define bFM3_CAN1_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) -#define bFM3_CAN1_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) -#define bFM3_CAN1_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) -#define bFM3_CAN1_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) -#define bFM3_CAN1_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) -#define bFM3_CAN1_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) -#define bFM3_CAN1_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) -#define bFM3_CAN1_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) -#define bFM3_CAN1_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) -#define bFM3_CAN1_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) -#define bFM3_CAN1_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) -#define bFM3_CAN1_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) -#define bFM3_CAN1_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) -#define bFM3_CAN1_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) -#define bFM3_CAN1_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) -#define bFM3_CAN1_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) -#define bFM3_CAN1_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) -#define bFM3_CAN1_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) -#define bFM3_CAN1_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) -#define bFM3_CAN1_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) -#define bFM3_CAN1_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) -#define bFM3_CAN1_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) -#define bFM3_CAN1_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) -#define bFM3_CAN1_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) -#define bFM3_CAN1_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) -#define bFM3_CAN1_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) -#define bFM3_CAN1_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) -#define bFM3_CAN1_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) -#define bFM3_CAN1_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) -#define bFM3_CAN1_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) -#define bFM3_CAN1_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) -#define bFM3_CAN1_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) -#define bFM3_CAN1_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) -#define bFM3_CAN1_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) -#define bFM3_CAN1_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) -#define bFM3_CAN1_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) -#define bFM3_CAN1_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) -#define bFM3_CAN1_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) -#define bFM3_CAN1_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) -#define bFM3_CAN1_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) -#define bFM3_CAN1_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) -#define bFM3_CAN1_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) -#define bFM3_CAN1_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) -#define bFM3_CAN1_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) -#define bFM3_CAN1_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) -#define bFM3_CAN1_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) -#define bFM3_CAN1_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) -#define bFM3_CAN1_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) -#define bFM3_CAN1_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) -#define bFM3_CAN1_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) -#define bFM3_CAN1_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) -#define bFM3_CAN1_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) -#define bFM3_CAN1_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) -#define bFM3_CAN1_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) -#define bFM3_CAN1_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) -#define bFM3_CAN1_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) -#define bFM3_CAN1_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) -#define bFM3_CAN1_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) -#define bFM3_CAN1_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) -#define bFM3_CAN1_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) -#define bFM3_CAN1_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) -#define bFM3_CAN1_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) -#define bFM3_CAN1_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) -#define bFM3_CAN1_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) -#define bFM3_CAN1_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) -#define bFM3_CAN1_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) -#define bFM3_CAN1_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) -#define bFM3_CAN1_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) -#define bFM3_CAN1_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) -#define bFM3_CAN1_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) -#define bFM3_CAN1_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) -#define bFM3_CAN1_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) -#define bFM3_CAN1_INTPND_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) -#define bFM3_CAN1_INTPND_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) -#define bFM3_CAN1_INTPND_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) -#define bFM3_CAN1_INTPND_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) -#define bFM3_CAN1_INTPND_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) -#define bFM3_CAN1_INTPND_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) -#define bFM3_CAN1_INTPND_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) -#define bFM3_CAN1_INTPND_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) -#define bFM3_CAN1_INTPND_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) -#define bFM3_CAN1_INTPND_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) -#define bFM3_CAN1_INTPND_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) -#define bFM3_CAN1_INTPND_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) -#define bFM3_CAN1_INTPND_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) -#define bFM3_CAN1_INTPND_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) -#define bFM3_CAN1_INTPND_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) -#define bFM3_CAN1_INTPND_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) -#define bFM3_CAN1_INTPND_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) -#define bFM3_CAN1_INTPND_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) -#define bFM3_CAN1_INTPND_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) -#define bFM3_CAN1_INTPND_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) -#define bFM3_CAN1_INTPND_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) -#define bFM3_CAN1_INTPND_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) -#define bFM3_CAN1_INTPND_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) -#define bFM3_CAN1_INTPND_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) -#define bFM3_CAN1_INTPND_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) -#define bFM3_CAN1_INTPND_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) -#define bFM3_CAN1_INTPND_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) -#define bFM3_CAN1_INTPND_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) -#define bFM3_CAN1_INTPND_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) -#define bFM3_CAN1_INTPND_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) -#define bFM3_CAN1_INTPND_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) -#define bFM3_CAN1_INTPND_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) -#define bFM3_CAN1_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) -#define bFM3_CAN1_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) -#define bFM3_CAN1_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) -#define bFM3_CAN1_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) -#define bFM3_CAN1_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) -#define bFM3_CAN1_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) -#define bFM3_CAN1_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) -#define bFM3_CAN1_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) -#define bFM3_CAN1_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) -#define bFM3_CAN1_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) -#define bFM3_CAN1_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) -#define bFM3_CAN1_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) -#define bFM3_CAN1_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) -#define bFM3_CAN1_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) -#define bFM3_CAN1_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) -#define bFM3_CAN1_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) -#define bFM3_CAN1_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) -#define bFM3_CAN1_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) -#define bFM3_CAN1_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) -#define bFM3_CAN1_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) -#define bFM3_CAN1_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) -#define bFM3_CAN1_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) -#define bFM3_CAN1_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) -#define bFM3_CAN1_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) -#define bFM3_CAN1_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) -#define bFM3_CAN1_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) -#define bFM3_CAN1_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) -#define bFM3_CAN1_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) -#define bFM3_CAN1_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) -#define bFM3_CAN1_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) -#define bFM3_CAN1_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) -#define bFM3_CAN1_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) -#define bFM3_CAN1_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) -#define bFM3_CAN1_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) -#define bFM3_CAN1_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) -#define bFM3_CAN1_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) - -#ifdef __cplusplus -} -#endif - -#endif /* _MB9BF506R_H_ */ - diff --git a/bsp/fm3/CMSIS/start_gcc.S b/bsp/fm3/CMSIS/start_gcc.S deleted file mode 100644 index ad0f8af0c3..0000000000 --- a/bsp/fm3/CMSIS/start_gcc.S +++ /dev/null @@ -1,360 +0,0 @@ -/* - * File : start_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-07-01 lgnq first version - */ - -.section .bss.init -.equ Stack_Size, 0x00000200 -.space Stack_Size -Initial_spTop: - - .syntax unified - .cpu cortex-m3 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -// .equ Initial_spTop, 0x20000200 -.equ BootRAM, 0xF1E0F85F -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* restore original stack pointer */ - LDR r0, =Initial_spTop - MSR msp, r0 -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss -/* Call the application's entry point.*/ - bl main - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word Initial_spTop - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - .word CSV_IRQHandler - .word SWDT_IRQHandler - .word LVD_IRQHandler - .word WFG_IRQHandler - .word EXINT0_7_IRQHandler - .word EXINT8_15_IRQHandler - .word DTIM_QDU_IRQHandler - .word MFS0RX_IRQHandler - .word MFS0TX_IRQHandler - .word MFS1RX_IRQHandler - .word MFS1TX_IRQHandler - .word MFS2RX_IRQHandler - .word MFS2TX_IRQHandler - .word MFS3RX_IRQHandler - .word MFS3TX_IRQHandler - .word MFS4RX_IRQHandler - .word MFS4TX_IRQHandler - .word MFS5RX_IRQHandler - .word MFS5TX_IRQHandler - .word MFS6RX_IRQHandler - .word MFS6TX_IRQHandler - .word MFS7RX_IRQHandler - .word MFS7TX_IRQHandler - .word PPG_IRQHandler - .word OSC_PLL_WC_IRQHandler - .word ADC0_IRQHandler - .word ADC1_IRQHandler - .word ADC2_IRQHandler - .word FRTIM_IRQHandler - .word INCAP_IRQHandler - .word OUTCOMP_IRQHandler - .word BTIM_IRQHandler - .word CAN0_IRQHandler - .word CAN1_IRQHandler - .word USBF_IRQHandler - .word USBF_USBH_IRQHandler - .word RESERVED_1_IRQHandler - .word RESERVED_2_IRQHandler - .word DMAC0_IRQHandler - .word DMAC1_IRQHandler - .word DMAC2_IRQHandler - .word DMAC3_IRQHandler - .word DMAC4_IRQHandler - .word DMAC5_IRQHandler - .word DMAC6_IRQHandler - .word DMAC7_IRQHandler - .word RESERVED_3_IRQHandler - .word RESERVED_4_IRQHandler - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak CSV_IRQHandler - .thumb_set CSV_IRQHandler,Default_Handler - - .weak SWDT_IRQHandler - .thumb_set SWDT_IRQHandler,Default_Handler - - .weak LVD_IRQHandler - .thumb_set LVD_IRQHandler,Default_Handler - - .weak WFG_IRQHandler - .thumb_set WFG_IRQHandler,Default_Handler - - .weak EXINT0_7_IRQHandler - .thumb_set EXINT0_7_IRQHandler,Default_Handler - - .weak EXINT8_15_IRQHandler - .thumb_set EXINT8_15_IRQHandler,Default_Handler - - .weak DTIM_QDU_IRQHandler - .thumb_set DTIM_QDU_IRQHandler,Default_Handler - - .weak MFS0RX_IRQHandler - .thumb_set MFS0RX_IRQHandler,Default_Handler - - .weak MFS0TX_IRQHandler - .thumb_set MFS0TX_IRQHandler,Default_Handler - - .weak MFS1RX_IRQHandler - .thumb_set MFS1RX_IRQHandler,Default_Handler - - .weak MFS1TX_IRQHandler - .thumb_set MFS1TX_IRQHandler,Default_Handler - - .weak MFS2RX_IRQHandler - .thumb_set MFS2RX_IRQHandler,Default_Handler - - .weak MFS2TX_IRQHandler - .thumb_set MFS2TX_IRQHandler,Default_Handler - - .weak MFS3RX_IRQHandler - .thumb_set MFS3RX_IRQHandler,Default_Handler - - .weak MFS3TX_IRQHandler - .thumb_set MFS3TX_IRQHandler,Default_Handler - - .weak MFS4RX_IRQHandler - .thumb_set MFS4RX_IRQHandler,Default_Handler - - .weak MFS4TX_IRQHandler - .thumb_set MFS4TX_IRQHandler,Default_Handler - - .weak MFS5RX_IRQHandler - .thumb_set MFS5RX_IRQHandler,Default_Handler - - .weak MFS5TX_IRQHandler - .thumb_set MFS5TX_IRQHandler,Default_Handler - - .weak MFS6RX_IRQHandler - .thumb_set MFS6RX_IRQHandler,Default_Handler - - .weak MFS6TX_IRQHandler - .thumb_set MFS6TX_IRQHandler,Default_Handler - - .weak MFS7RX_IRQHandler - .thumb_set MFS7RX_IRQHandler,Default_Handler - - .weak MFS7TX_IRQHandler - .thumb_set MFS7TX_IRQHandler,Default_Handler - - .weak PPG_IRQHandler - .thumb_set PPG_IRQHandler,Default_Handler - - .weak OSC_PLL_WC_IRQHandler - .thumb_set OSC_PLL_WC_IRQHandler,Default_Handler - - .weak ADC0_IRQHandler - .thumb_set ADC0_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak ADC2_IRQHandler - .thumb_set ADC2_IRQHandler,Default_Handler - - .weak FRTIM_IRQHandler - .thumb_set FRTIM_IRQHandler,Default_Handler - - .weak INCAP_IRQHandler - .thumb_set INCAP_IRQHandler,Default_Handler - - .weak OUTCOMP_IRQHandler - .thumb_set OUTCOMP_IRQHandler,Default_Handler - - .weak BTIM_IRQHandler - .thumb_set BTIM_IRQHandler,Default_Handler - - .weak CAN0_IRQHandler - .thumb_set CAN0_IRQHandler,Default_Handler - - .weak CAN1_IRQHandler - .thumb_set CAN1_IRQHandler,Default_Handler - - .weak USBF_IRQHandler - .thumb_set USBF_IRQHandler,Default_Handler - - .weak USBF_USBH_IRQHandler - .thumb_set USBF_USBH_IRQHandler,Default_Handler - - .weak RESERVED_1_IRQHandler - .thumb_set RESERVED_1_IRQHandler,Default_Handler - - .weak RESERVED_2_IRQHandler - .thumb_set RESERVED_2_IRQHandler,Default_Handler - - .weak DMAC0_IRQHandler - .thumb_set DMAC0_IRQHandler,Default_Handler - - .weak DMAC1_IRQHandler - .thumb_set DMAC1_IRQHandler,Default_Handler - - .weak DMAC2_IRQHandler - .thumb_set DMAC2_IRQHandler,Default_Handler - - .weak DMAC3_IRQHandler - .thumb_set DMAC3_IRQHandler,Default_Handler - - .weak DMAC4_IRQHandler - .thumb_set DMAC4_IRQHandler,Default_Handler - - .weak DMAC5_IRQHandler - .thumb_set DMAC5_IRQHandler,Default_Handler - - .weak DMAC6_IRQHandler - .thumb_set DMAC6_IRQHandler,Default_Handler - - .weak DMAC7_IRQHandler - .thumb_set DMAC7_IRQHandler,Default_Handler - - .weak RESERVED_3_IRQHandler - .thumb_set RESERVED_3_IRQHandler,Default_Handler - - .weak RESERVED_4_IRQHandler - .thumb_set RESERVED_4_IRQHandler,Default_Handler - diff --git a/bsp/fm3/CMSIS/start_iar.S b/bsp/fm3/CMSIS/start_iar.S deleted file mode 100644 index b111ce9b43..0000000000 --- a/bsp/fm3/CMSIS/start_iar.S +++ /dev/null @@ -1,363 +0,0 @@ -;/* -; * File : context_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team -; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE -; * -; * Change Logs: -; * Date Author Notes -; * 2009-01-17 Bernard first version -; * 2009-09-27 Bernard add protect when contex switch occurs -; */ - -#include "rtconfig.h" - - MODULE ?cstartup - -;; ICODE is the same segment as cstartup. By placing __low_level_init -;; in the same segment, we make sure it can be reached with BL. */ - - SECTION CSTACK:DATA:NOROOT(3) - SECTION .icode:CODE:NOROOT(2) - -#ifdef RT_USING_UART2 - IMPORT MFS2RX_IRQHandler -#endif - PUBLIC __low_level_init - - PUBWEAK SystemInit_ExtMemCtl - SECTION .text:CODE:REORDER(2) - THUMB -SystemInit_ExtMemCtl - BX LR - -__low_level_init: - ;; Initialize hardware. - LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller - MOV R11, LR - BLX R0 - LDR R1, =sfe(CSTACK) ; restore original stack pointer - MSR MSP, R1 - MOV R0,#1 - ;; Return with BX to be independent of mode of caller - BX R11 - - ;; Forward declaration of sections. - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD __iar_program_start - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD CSV_IRQHandler ; Clock Super Visor - DCD SWDT_IRQHandler ; Software Watchdog Timer - DCD LVD_IRQHandler ; Low Voltage Detector - DCD WFG_IRQHandler ; Wave Form Generator - DCD EXINT0_7_IRQHandler ; External Interrupt Request ch.0 to ch.7 - DCD EXINT8_15_IRQHandler ; External Interrupt Request ch.8 to ch.15 - DCD DTIM_QDU_IRQHandler ; Dual Timer / Quad Decoder - DCD MFS0RX_IRQHandler ; MultiFunction Serial ch.0 - DCD MFS0TX_IRQHandler ; MultiFunction Serial ch.0 - DCD MFS1RX_IRQHandler ; MultiFunction Serial ch.1 - DCD MFS1TX_IRQHandler ; MultiFunction Serial ch.1 -#ifdef RT_USING_UART2 - DCD MFS2RX_IRQHandler ; MultiFunction Serial ch.2 -#else - DCD NULL_IRQHandler ; MultiFunction Serial ch.2 -#endif - DCD MFS2TX_IRQHandler ; MultiFunction Serial ch.2 - DCD MFS3RX_IRQHandler ; MultiFunction Serial ch.3 - DCD MFS3TX_IRQHandler ; MultiFunction Serial ch.3 - DCD MFS4RX_IRQHandler ; MultiFunction Serial ch.4 - DCD MFS4TX_IRQHandler ; MultiFunction Serial ch.4 - DCD MFS5RX_IRQHandler ; MultiFunction Serial ch.5 - DCD MFS5TX_IRQHandler ; MultiFunction Serial ch.5 - DCD MFS6RX_IRQHandler ; MultiFunction Serial ch.6 - DCD MFS6TX_IRQHandler ; MultiFunction Serial ch.6 - DCD MFS7RX_IRQHandler ; MultiFunction Serial ch.7 - DCD MFS7TX_IRQHandler ; MultiFunction Serial ch.7 - DCD PPG_IRQHandler ; PPG - DCD OSC_PLL_WC_IRQHandler ; OSC / PLL / Watch Counter - DCD ADC0_IRQHandler ; ADC0 - DCD ADC1_IRQHandler ; ADC1 - DCD ADC2_IRQHandler ; ADC2 - DCD FRTIM_IRQHandler ; Free-run Timer - DCD INCAP_IRQHandler ; Input Capture - DCD OUTCOMP_IRQHandler ; Output Compare - DCD BTIM_IRQHandler ; Base Timer ch.0 to ch.7 - DCD CAN0_IRQHandler ; CAN ch.0 - DCD CAN1_IRQHandler ; CAN ch.1 - DCD USBF_IRQHandler ; USB Function - DCD USBF_USBH_IRQHandler ; USB Function / USB HOST - DCD RESERVED_1_IRQHandler ; Reserved_1 - DCD RESERVED_2_IRQHandler ; Reserved_2 - DCD DMAC0_IRQHandler ; DMAC ch.0 - DCD DMAC1_IRQHandler ; DMAC ch.1 - DCD DMAC2_IRQHandler ; DMAC ch.2 - DCD DMAC3_IRQHandler ; DMAC ch.3 - DCD DMAC4_IRQHandler ; DMAC ch.4 - DCD DMAC5_IRQHandler ; DMAC ch.5 - DCD DMAC6_IRQHandler ; DMAC ch.6 - DCD DMAC7_IRQHandler ; DMAC ch.7 - DCD RESERVED_3_IRQHandler ; Reserved_3 - DCD RESERVED_4_IRQHandler ; Reserved_4 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER(1) -NMI_Handler - B NMI_Handler - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER(1) -HardFault_Handler - B HardFault_Handler - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER(1) -MemManage_Handler - B MemManage_Handler - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER(1) -BusFault_Handler - B BusFault_Handler - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER(1) -UsageFault_Handler - B UsageFault_Handler - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER(1) -SVC_Handler - B SVC_Handler - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER(1) -DebugMon_Handler - B DebugMon_Handler - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER(1) -PendSV_Handler - B PendSV_Handler - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER(1) -SysTick_Handler - B SysTick_Handler - PUBWEAK CSV_IRQHandler - SECTION .text:CODE:REORDER(1) -CSV_IRQHandler - B CSV_IRQHandler - PUBWEAK SWDT_IRQHandler - SECTION .text:CODE:REORDER(1) -SWDT_IRQHandler - B SWDT_IRQHandler - PUBWEAK LVD_IRQHandler - SECTION .text:CODE:REORDER(1) -LVD_IRQHandler - B LVD_IRQHandler - PUBWEAK WFG_IRQHandler - SECTION .text:CODE:REORDER(1) -WFG_IRQHandler - B WFG_IRQHandler - PUBWEAK EXINT0_7_IRQHandler - SECTION .text:CODE:REORDER(1) -EXINT0_7_IRQHandler - B EXINT0_7_IRQHandler - PUBWEAK EXINT8_15_IRQHandler - SECTION .text:CODE:REORDER(1) -EXINT8_15_IRQHandler - B EXINT8_15_IRQHandler - PUBWEAK DTIM_QDU_IRQHandler - SECTION .text:CODE:REORDER(1) -DTIM_QDU_IRQHandler - B DTIM_QDU_IRQHandler - PUBWEAK MFS0RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS0RX_IRQHandler - B MFS0RX_IRQHandler - PUBWEAK MFS0TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS0TX_IRQHandler - B MFS0TX_IRQHandler - PUBWEAK MFS1RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS1RX_IRQHandler - B MFS1RX_IRQHandler - PUBWEAK MFS1TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS1TX_IRQHandler - B MFS1TX_IRQHandler - PUBWEAK NULL_IRQHandler - SECTION .text:CODE:REORDER(1) -NULL_IRQHandler - B NULL_IRQHandler - PUBWEAK MFS2TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS2TX_IRQHandler - B MFS2TX_IRQHandler - PUBWEAK MFS3RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS3RX_IRQHandler - B MFS3RX_IRQHandler - PUBWEAK MFS3TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS3TX_IRQHandler - B MFS3TX_IRQHandler - PUBWEAK MFS4RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS4RX_IRQHandler - B MFS4RX_IRQHandler - PUBWEAK MFS4TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS4TX_IRQHandler - B MFS4TX_IRQHandler - PUBWEAK MFS5RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS5RX_IRQHandler - B MFS5RX_IRQHandler - PUBWEAK MFS5TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS5TX_IRQHandler - B MFS5TX_IRQHandler - PUBWEAK MFS6RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS6RX_IRQHandler - B MFS6RX_IRQHandler - PUBWEAK MFS6TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS6TX_IRQHandler - B MFS6TX_IRQHandler - PUBWEAK MFS7RX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS7RX_IRQHandler - B MFS7RX_IRQHandler - PUBWEAK MFS7TX_IRQHandler - SECTION .text:CODE:REORDER(1) -MFS7TX_IRQHandler - B MFS7TX_IRQHandler - PUBWEAK PPG_IRQHandler - SECTION .text:CODE:REORDER(1) -PPG_IRQHandler - B PPG_IRQHandler - PUBWEAK OSC_PLL_WC_IRQHandler - SECTION .text:CODE:REORDER(1) -OSC_PLL_WC_IRQHandler - B OSC_PLL_WC_IRQHandler - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC0_IRQHandler - B ADC0_IRQHandler - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC1_IRQHandler - B ADC1_IRQHandler - PUBWEAK ADC2_IRQHandler - SECTION .text:CODE:REORDER(1) -ADC2_IRQHandler - B ADC2_IRQHandler - PUBWEAK FRTIM_IRQHandler - SECTION .text:CODE:REORDER(1) -FRTIM_IRQHandler - B FRTIM_IRQHandler - PUBWEAK INCAP_IRQHandler - SECTION .text:CODE:REORDER(1) -INCAP_IRQHandler - B INCAP_IRQHandler - PUBWEAK OUTCOMP_IRQHandler - SECTION .text:CODE:REORDER(1) -OUTCOMP_IRQHandler - B OUTCOMP_IRQHandler - PUBWEAK BTIM_IRQHandler - SECTION .text:CODE:REORDER(1) -BTIM_IRQHandler - B BTIM_IRQHandler - PUBWEAK CAN0_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN0_IRQHandler - B CAN0_IRQHandler - PUBWEAK CAN1_IRQHandler - SECTION .text:CODE:REORDER(1) -CAN1_IRQHandler - B CAN1_IRQHandler - PUBWEAK USBF_IRQHandler - SECTION .text:CODE:REORDER(1) -USBF_IRQHandler - B USBF_IRQHandler - PUBWEAK USBF_USBH_IRQHandler - SECTION .text:CODE:REORDER(1) -USBF_USBH_IRQHandler - B USBF_USBH_IRQHandler - PUBWEAK RESERVED_1_IRQHandler - SECTION .text:CODE:REORDER(1) -RESERVED_1_IRQHandler - B RESERVED_1_IRQHandler - PUBWEAK RESERVED_2_IRQHandler - SECTION .text:CODE:REORDER(1) -RESERVED_2_IRQHandler - B RESERVED_2_IRQHandler - PUBWEAK DMAC0_IRQHandler - SECTION .text:CODE:REORDER(1) -DMAC0_IRQHandler - B DMAC0_IRQHandler - PUBWEAK DMAC1_IRQHandler - SECTION .text:CODE:REORDER(1) -DMAC1_IRQHandler - B DMAC1_IRQHandler - PUBWEAK DMAC2_IRQHandler - SECTION .text:CODE:REORDER(1) -DMAC2_IRQHandler - B DMAC2_IRQHandler - PUBWEAK DMAC3_IRQHandler - SECTION .text:CODE:REORDER(1) -DMAC3_IRQHandler - B DMAC3_IRQHandler - PUBWEAK DMAC4_IRQHandler - SECTION .text:CODE:REORDER(1) -DMAC4_IRQHandler - B DMAC4_IRQHandler - PUBWEAK DMAC5_IRQHandler - SECTION .text:CODE:REORDER(1) -DMAC5_IRQHandler - B DMAC5_IRQHandler - PUBWEAK DMAC6_IRQHandler - SECTION .text:CODE:REORDER(1) -DMAC6_IRQHandler - B DMAC6_IRQHandler - PUBWEAK DMAC7_IRQHandler - SECTION .text:CODE:REORDER(1) -DMAC7_IRQHandler - B DMAC7_IRQHandler - PUBWEAK RESERVED_3_IRQHandler - SECTION .text:CODE:REORDER(1) -RESERVED_3_IRQHandler - B RESERVED_3_IRQHandler - PUBWEAK RESERVED_4_IRQHandler - SECTION .text:CODE:REORDER(1) -RESERVED_4_IRQHandler - B RESERVED_4_IRQHandler - - END diff --git a/bsp/fm3/CMSIS/start_rvds.S b/bsp/fm3/CMSIS/start_rvds.S deleted file mode 100644 index fc755132c1..0000000000 --- a/bsp/fm3/CMSIS/start_rvds.S +++ /dev/null @@ -1,291 +0,0 @@ -; /* -; * File : start_rvds.s -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team -; * -; * The license and distribution terms for this file may be -; * found in the file LICENSE in this distribution or at -; * http://www.rt-thread.org/license/LICENSE -; * -; * Change Logs: -; * Date Author Notes -; * 2011-02-23 Bernard first implementation -; */ - -;* <<< Use Configuration Wizard in Context Menu >>> - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x00000200 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - -; Note: RT-Thread not use malloc/free in Keil MDK, therefore the heap size is 0. -Heap_Size EQU 0x00000000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - DCD CSV_Handler ; 0: Clock Super Visor - DCD SWDT_Handler ; 1: Software Watchdog Timer - DCD LVD_Handler ; 2: Low Voltage Detector - DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF - DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7 - DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15 - DCD DT_Handler ; 6: Dual Timer / Quad Decoder - DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0 - DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0 - DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1 - DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1 - DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2 - DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2 - DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3 - DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3 - DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4 - DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4 - DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5 - DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5 - DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6 - DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6 - DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7 - DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7 - DCD PPG_Handler ; 23: PPG - DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter - DCD ADC0_IRQHandler ; 25: ADC0 - DCD ADC1_IRQHandler ; 26: ADC1 - DCD ADC2_IRQHandler ; 27: ADC2 - DCD MFT_FRT_IRQHandler ; 28: Free-run Timer - DCD MFT_IPC_IRQHandler ; 29: Input Capture - DCD MFT_OPC_IRQHandler ; 30: Output Compare - DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7 - DCD CAN0_IRQHandler ; 32: CAN ch.0 - DCD CAN1_IRQHandler ; 33: CAN ch.1 - DCD USBF_Handler ; 34: USB Function - DCD USB_Handler ; 35: USB Function / USB HOST - DCD DummyHandler ; 36: Reserved - DCD DummyHandler ; 37: Reserved - DCD DMAC0_Handler ; 38: DMAC ch.0 - DCD DMAC1_Handler ; 39: DMAC ch.1 - DCD DMAC2_Handler ; 40: DMAC ch.2 - DCD DMAC3_Handler ; 41: DMAC ch.3 - DCD DMAC4_Handler ; 42: DMAC ch.4 - DCD DMAC5_Handler ; 43: DMAC ch.5 - DCD DMAC6_Handler ; 44: DMAC ch.6 - DCD DMAC7_Handler ; 45: DMAC ch.7 - DCD DummyHandler ; 46: Reserved - DCD DummyHandler ; 47: Reserved -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R1, = __initial_sp ; restore original stack pointer - MSR MSP, R1 - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT CSV_Handler [WEAK] - EXPORT SWDT_Handler [WEAK] - EXPORT LVD_Handler [WEAK] - EXPORT MFT_WG_IRQHandler [WEAK] - EXPORT INT0_7_Handler [WEAK] - EXPORT INT8_15_Handler [WEAK] - EXPORT DT_Handler [WEAK] - EXPORT MFS0RX_IRQHandler [WEAK] - EXPORT MFS0TX_IRQHandler [WEAK] - EXPORT MFS1RX_IRQHandler [WEAK] - EXPORT MFS1TX_IRQHandler [WEAK] - EXPORT MFS2RX_IRQHandler [WEAK] - EXPORT MFS2TX_IRQHandler [WEAK] - EXPORT MFS3RX_IRQHandler [WEAK] - EXPORT MFS3TX_IRQHandler [WEAK] - EXPORT MFS4RX_IRQHandler [WEAK] - EXPORT MFS4TX_IRQHandler [WEAK] - EXPORT MFS5RX_IRQHandler [WEAK] - EXPORT MFS5TX_IRQHandler [WEAK] - EXPORT MFS6RX_IRQHandler [WEAK] - EXPORT MFS6TX_IRQHandler [WEAK] - EXPORT MFS7RX_IRQHandler [WEAK] - EXPORT MFS7TX_IRQHandler [WEAK] - EXPORT PPG_Handler [WEAK] - EXPORT TIM_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT ADC2_IRQHandler [WEAK] - EXPORT MFT_FRT_IRQHandler [WEAK] - EXPORT MFT_IPC_IRQHandler [WEAK] - EXPORT MFT_OPC_IRQHandler [WEAK] - EXPORT BT_IRQHandler [WEAK] - EXPORT CAN0_IRQHandler [WEAK] - EXPORT CAN1_IRQHandler [WEAK] - EXPORT USBF_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT DMAC0_Handler [WEAK] - EXPORT DMAC1_Handler [WEAK] - EXPORT DMAC2_Handler [WEAK] - EXPORT DMAC3_Handler [WEAK] - EXPORT DMAC4_Handler [WEAK] - EXPORT DMAC5_Handler [WEAK] - EXPORT DMAC6_Handler [WEAK] - EXPORT DMAC7_Handler [WEAK] - EXPORT DummyHandler [WEAK] - -CSV_Handler -SWDT_Handler -LVD_Handler -MFT_WG_IRQHandler -INT0_7_Handler -INT8_15_Handler -DT_Handler -MFS0RX_IRQHandler -MFS0TX_IRQHandler -MFS1RX_IRQHandler -MFS1TX_IRQHandler -MFS2RX_IRQHandler -MFS2TX_IRQHandler -MFS3RX_IRQHandler -MFS3TX_IRQHandler -MFS4RX_IRQHandler -MFS4TX_IRQHandler -MFS5RX_IRQHandler -MFS5TX_IRQHandler -MFS6RX_IRQHandler -MFS6TX_IRQHandler -MFS7RX_IRQHandler -MFS7TX_IRQHandler -PPG_Handler -TIM_IRQHandler -ADC0_IRQHandler -ADC1_IRQHandler -ADC2_IRQHandler -MFT_FRT_IRQHandler -MFT_IPC_IRQHandler -MFT_OPC_IRQHandler -BT_IRQHandler -CAN0_IRQHandler -CAN1_IRQHandler -USBF_Handler -USB_Handler -DMAC0_Handler -DMAC1_Handler -DMAC2_Handler -DMAC3_Handler -DMAC4_Handler -DMAC5_Handler -DMAC6_Handler -DMAC7_Handler -DummyHandler - B . - ENDP - ALIGN - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - ELSE - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - ENDIF - - END diff --git a/bsp/fm3/CMSIS/system_mb9bf50x.c b/bsp/fm3/CMSIS/system_mb9bf50x.c deleted file mode 100644 index 21cd7a3f26..0000000000 --- a/bsp/fm3/CMSIS/system_mb9bf50x.c +++ /dev/null @@ -1,111 +0,0 @@ -/************************************************************************/ -/* (C) Fujitsu Semiconductor Europe GmbH */ -/* */ -/* The following software deliverable is intended for and must only be */ -/* used for reference and in an evaluation laboratory environment. */ -/* It is provided on an as-is basis without charge and is subject to */ -/* alterations. */ -/* It is the user’s obligation to fully test the software in its */ -/* environment and to ensure proper functionality, qualification and */ -/* compliance with component specifications. */ -/* */ -/* In the event the software deliverable includes the use of open */ -/* source components, the provisions of the governing open source */ -/* license agreement shall apply with respect to such software */ -/* deliverable. */ -/* FSEU does not warrant that the deliverables do not infringe any */ -/* third party intellectual property right (IPR). In the event that */ -/* the deliverables infringe a third party IPR it is the sole */ -/* responsibility of the customer to obtain necessary licenses to */ -/* continue the usage of the deliverable. */ -/* */ -/* To the maximum extent permitted by applicable law FSEU disclaims all */ -/* warranties, whether express or implied, in particular, but not */ -/* limited to, warranties of merchantability and fitness for a */ -/* particular purpose for which the deliverable is not designated. */ -/* */ -/* To the maximum extent permitted by applicable law, FSEU's liability */ -/* is restricted to intention and gross negligence. */ -/* FSEU is not liable for consequential damages. */ -/* */ -/* (V1.4) */ -/************************************************************************/ - -#include "mb9bf506r.h" - -/* - * 80MHz : Master Clock - */ -const uint32_t SystemFrequency = 80000000UL; - -uint32_t SysFreHCLK = 80000000UL; /* HCLK = MasterClock / 1 */ -uint32_t SysFrePCLK0 = 40000000UL; /* PCLK0 = HCLK / 2 */ -uint32_t SysFrePCLK1 = 40000000UL; /* PCLK1 = HCLK / 2 */ -uint32_t SysFrePCLK2 = 40000000UL; /* PCLK2 = HCLK / 2 */ -uint32_t SysFreTPIU = 0UL; /* TPIUCLK : Disable */ - -/* - * Prototype of internal function - */ -static void ClockInit(void); -static void HwwdtDisable(void); - - -/* - * Setup the microcontroller system - */ -void SystemInit (void) -{ - HwwdtDisable(); /* Disable Hardware Watchdog */ - ClockInit(); /* Initialize Clock */ -} -/* - * Initialize Clock - */ -static void ClockInit(void) -{ - /*set Main clock stabilization - wait time to 2ms*/ - FM3_CRG->CSW_TMR = 0x79; - /*Enable Main Oscilator*/ - FM3_CRG->SCM_CTL |= 1<<1; - /*Wait stabilization end*/ - while(!(FM3_CRG->SCM_STR & 0x02)); - - /* sub CLK enable */ - //FM3_CRG->SCM_CTL |= 0x08; - //while(!(FM3_CRG->SCM_STR & 0x08)); - - /*Set PLL stabilization - wait time to 512uS*/ - FM3_CRG->PSW_TMR |= 2; - /*Set PLL to 80MHz*/ - FM3_CRG->PLL_CTL1 = 0; /*K = 1, M=1*/ - FM3_CRG->PLL_CTL2 = 19; /*N = 20*/ - /*Enable PLL*/ - FM3_CRG->SCM_CTL |= 0x10; - /*Set bus prescalers*/ - FM3_CRG->BSC_PSR = 0; /*Base clock Prescaler 1:1*/ - FM3_CRG->APBC0_PSR |= 1; /*APB0 clock Prescaler 1:2*/ - FM3_CRG->APBC1_PSR |= 1; /*APB1 clock Prescaler 1:2*/ - FM3_CRG->APBC2_PSR |= 1; /*APB2 clock Prescaler 1:2*/ - /*Wait PLL stabilizatoin end*/ - while(!(FM3_CRG->SCM_STR & 0x10)); - /*Select PLL for main clock*/ - FM3_CRG->SCM_CTL |= 2<<5; - /*Wait PLL to be connected*/ - while((FM3_CRG->SCM_STR & 0xe0) != 0x40); - -} -/* - * Stop HW Watchdog Timer - */ -static void HwwdtDisable(void) -{ - /* UnLock (except WDG_CTL) */ - FM3_HWWDT->WDG_LCK = 0x1ACCE551; - /* UnLock (WDG_CTL) */ - FM3_HWWDT->WDG_LCK = 0xE5331AAE; - /* Disable WDG */ - FM3_HWWDT->WDG_CTL = 0x00; -} diff --git a/bsp/fm3/CMSIS/system_mb9bf50x.h b/bsp/fm3/CMSIS/system_mb9bf50x.h deleted file mode 100644 index 4b4789d5df..0000000000 --- a/bsp/fm3/CMSIS/system_mb9bf50x.h +++ /dev/null @@ -1,71 +0,0 @@ -/************************************************************************/ -/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ -/* */ -/* The following software deliverable is intended for and must only be */ -/* used for reference and in an evaluation laboratory environment. */ -/* It is provided on an as-is basis without charge and is subject to */ -/* alterations. */ -/* It is the user's obligation to fully test the software in its */ -/* environment and to ensure proper functionality, qualification and */ -/* compliance with component specifications. */ -/* */ -/* In the event the software deliverable includes the use of open */ -/* source components, the provisions of the governing open source */ -/* license agreement shall apply with respect to such software */ -/* deliverable. */ -/* FSEU does not warrant that the deliverables do not infringe any */ -/* third party intellectual property right (IPR). In the event that */ -/* the deliverables infringe a third party IPR it is the sole */ -/* responsibility of the customer to obtain necessary licenses to */ -/* continue the usage of the deliverable. */ -/* */ -/* To the maximum extent permitted by applicable law FSEU disclaims all */ -/* warranties, whether express or implied, in particular, but not */ -/* limited to, warranties of merchantability and fitness for a */ -/* particular purpose for which the deliverable is not designated. */ -/* */ -/* To the maximum extent permitted by applicable law, FSEU's liability */ -/* is restricted to intentional misconduct and gross negligence. */ -/* FSEU is not liable for consequential damages. */ -/* */ -/* (V1.5) */ -/************************************************************************/ - -#ifndef _SYSTEM_MB9BF50X_H_ -#define _SYSTEM_MB9BF50X_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_MB9BF50X_H */ diff --git a/bsp/fm3/mb9bf500r/SConscript b/bsp/fm3/mb9bf500r/SConscript deleted file mode 100644 index 703232f1b6..0000000000 --- a/bsp/fm3/mb9bf500r/SConscript +++ /dev/null @@ -1,16 +0,0 @@ -import rtconfig -Import('RTT_ROOT') -from building import * - -src_bsp = ['application.c', 'startup.c', 'board.c', 'led.c', 'cpuusage.c'] -src_drv = ['adc.c', 'lcd.c', 'key.c'] - -if GetDepend('RT_USING_RTGUI'): - src_drv += ['info.c'] - -src = src_bsp + src_drv -CPPPATH = [GetCurrentDir()] -CPPDEFINES = [] -group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) - -Return('group') diff --git a/bsp/fm3/mb9bf500r/SConstruct b/bsp/fm3/mb9bf500r/SConstruct deleted file mode 100644 index 5289674c12..0000000000 --- a/bsp/fm3/mb9bf500r/SConstruct +++ /dev/null @@ -1,39 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -from building import * - -TARGET = 'rtthread.' + rtconfig.TARGET_EXT - -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM == 'iar': - env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map']) - env.Replace(ARFLAGS = '') - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT) - -objs = objs + SConscript('../CMSIS/SConscript', variant_dir='build/bsp/Libraries', duplicate=0) - -# build program -env.Program(TARGET, objs) - -# end building -EndBuilding(TARGET) diff --git a/bsp/fm3/mb9bf500r/adc.c b/bsp/fm3/mb9bf500r/adc.c deleted file mode 100644 index 1e36d0b600..0000000000 --- a/bsp/fm3/mb9bf500r/adc.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * File : adc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-03-03 lgnq - */ - -#include -#include -#include "mb9bf506r.h" -#include "adc.h" -#include "led.h" -#include "lcd.h" - -#ifdef RT_USING_RTGUI -#include -#include -#include -#endif - -static struct rt_device adc; - -static rt_err_t rt_adc_init(rt_device_t dev) -{ - RT_ASSERT(dev != RT_NULL); - - if(!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - /* I/O setting AN08 - P18 */ - FM3_GPIO->ADE |= 0x100; - FM3_GPIO->PFR1 = 0x100; - - /* A/DC setting */ - FM3_ADC0->SCIS1 = 0x01; - FM3_ADC0->ADSS1 = 0x00; /* sampling timming ADST0 */ - FM3_ADC0->ADST1 = 0x43; - FM3_ADC0->ADCT = 0x02; - FM3_ADC0->SCCR = 0x10; /* FIFO clear,single mode */ - FM3_ADC0->CMPCR = 0x00; /* disable comparator */ - - /* starting A/DC */ - FM3_ADC0->SCCR |= 0x01; /* A/DC start */ - - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } - return RT_EOK; -} - -static rt_err_t rt_adc_control(rt_device_t dev, rt_uint8_t cmd, void *args) -{ - RT_ASSERT(dev != RT_NULL); - - switch (cmd) - { - case RT_DEVICE_CTRL_ADC_START: - FM3_ADC0->SCCR |= 0x1; - break; - - case RT_DEVICE_CTRL_ADC_RESULT: - while(FM3_ADC0->ADSR & 0x1) - ; - *((rt_uint16_t*)args) = FM3_ADC0->SCFD; - *((rt_uint16_t*)args) = *((rt_uint16_t*)args) >> 6; - *((rt_uint16_t*)args) = (*((rt_uint16_t*)args)*3300)/1024; - break; - } - return RT_EOK; -} - -extern struct rt_messagequeue mq; -extern rt_thread_t info_tid; -rt_uint16_t adc_value; -static void adc_thread_entry(void *parameter) -{ - rt_device_t device; - -#ifdef RT_USING_RTGUI - struct rtgui_event_command ecmd; - - RTGUI_EVENT_COMMAND_INIT(&ecmd); - ecmd.type = RTGUI_CMD_USER_INT; - ecmd.command_id = ADC_UPDATE; -#else - struct lcd_msg msg; -#endif - - device = rt_device_find("adc"); - - while(1) - { - rt_device_control(device, RT_DEVICE_CTRL_ADC_START, RT_NULL); - rt_device_control(device, RT_DEVICE_CTRL_ADC_RESULT, &adc_value); - pwm_update(adc_value/3); -#ifdef RT_USING_RTGUI - rtgui_thread_send(info_tid, &ecmd.parent, sizeof(ecmd)); -#else - msg.type = ADC_MSG; - msg.adc_value = adc_value; - rt_mq_send(&mq, &msg, sizeof(msg)); -#endif - rt_thread_delay(20); - } -} - -static rt_thread_t adc_thread; -void rt_hw_adc_init(void) -{ - adc.type = RT_Device_Class_Char; - adc.rx_indicate = RT_NULL; - adc.tx_complete = RT_NULL; - adc.init = rt_adc_init; - adc.open = RT_NULL; - adc.close = RT_NULL; - adc.read = RT_NULL; - adc.write = RT_NULL; - adc.control = rt_adc_control; - adc.user_data = RT_NULL; - - adc_thread = rt_thread_create("adc", adc_thread_entry, RT_NULL, 384, 26, 5); - if(adc_thread != RT_NULL) - rt_thread_startup(adc_thread); - - /* register a character device */ - rt_device_register(&adc, "adc", RT_DEVICE_FLAG_RDWR); -} - diff --git a/bsp/fm3/mb9bf500r/adc.h b/bsp/fm3/mb9bf500r/adc.h deleted file mode 100644 index 601a67619f..0000000000 --- a/bsp/fm3/mb9bf500r/adc.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * File : adc.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-03-03 lgnq - */ - -#ifndef __ADC_H__ -#define __ADC_H__ - -/* Exported constants ---------------------------------------------------------*/ -/* Exported macro -------------------------------------------------------------*/ -#define ADC_MODE_SINGLE 0x00UL -#define ADC_MODE_SCAN 0x01UL -#define ADC_MODE_TAILGATE 0x02UL - -#define RT_DEVICE_CTRL_ADC_START 0xF1 /* start ADC conversion */ -#define RT_DEVICE_CTRL_ADC_RESULT 0xF2 /* get ADC result */ - -#define ADC_UPDATE 0 - -/* Exported functions --------------------------------------------------------- */ -void rt_hw_adc_init(void); - -#endif /*__ADC_H__ */ diff --git a/bsp/fm3/mb9bf500r/application.c b/bsp/fm3/mb9bf500r/application.c deleted file mode 100644 index 2c3e4dab1c..0000000000 --- a/bsp/fm3/mb9bf500r/application.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-02-24 Bernard the first version - */ - -/** - * @addtogroup FM3 - */ -/*@{*/ - -#include -#include "board.h" -#include "led.h" -#include "key.h" -#include "adc.h" -#include "lcd.h" -#include "cpuusage.h" - -#ifdef RT_USING_RTGUI -#include -#include -extern void rtgui_startup(); -#endif - -struct rt_messagequeue mq; -static char msg_pool[2048]; - -void rt_init_thread_entry(void *parameter) -{ - rt_device_t lcd; - - rt_hw_led_init(); - rt_hw_key_init(); - rt_hw_adc_init(); - rt_hw_lcd_init(); - rt_hw_cpu_init(); - - /* re-init device driver */ - rt_device_init_all(); - -#ifdef RT_USING_RTGUI - /* find lcd device */ - lcd = rt_device_find("lcd"); - - /* set lcd device as rtgui graphic driver */ - rtgui_graphic_set_device(lcd); - - /* startup rtgui */ - rtgui_startup(); -#else - { - char buf[20] = {'\0'}; - struct lcd_msg msg; - rt_device_t device; - device = rt_device_find("lcd"); - rt_device_control(device, RT_DEVICE_CTRL_LCD_CLEAR_SCR, RT_NULL); - x = 1; - y = 1; - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "ADC"); - x = 1; - y = 20; - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "CPU"); - x = 1; - y = 40; - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "KEY"); - - while(1) - { - if (rt_mq_recv(&mq, &msg, sizeof(msg), RT_WAITING_FOREVER) == RT_EOK) - { - switch(msg.type) - { - case ADC_MSG: - x = 40; - y = 1; - rt_memset(buf, 0, sizeof(buf)); - rt_sprintf(buf, "%04d", msg.adc_value); - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); - break; - case CPU_MSG: - x = 40; - y = 20; - rt_memset(buf, 0, sizeof(buf)); - rt_sprintf(buf, "%03d %03d", msg.major, msg.minor); - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); - break; - case KEY_MSG: - x = 40; - y = 40; - rt_memset(buf, 0, sizeof(buf)); - switch(msg.key) - { - case KEY_DOWN: - rt_sprintf(buf, "DOWN KEY "); - break; - case KEY_UP: - rt_sprintf(buf, "UP KEY "); - break; - case KEY_RIGHT: - rt_sprintf(buf, "RIGHT KEY"); - break; - case KEY_LEFT: - rt_sprintf(buf, "LEFT KEY "); - break; - case KEY_ENTER: - rt_sprintf(buf, "ENTER KEY"); - break; - default: - rt_sprintf(buf, "NO KEY "); - break; - } - rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); - break; - } - } - } - } -#endif -} - -int rt_application_init() -{ - rt_thread_t init_thread; - - rt_mq_init(&mq, "mqt", &msg_pool[0], 128 - sizeof(void*), sizeof(msg_pool), RT_IPC_FLAG_FIFO); - - init_thread = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 1024, 21, 20); - if(init_thread != RT_NULL) - rt_thread_startup(init_thread); - - return 0; -} - -/*@}*/ diff --git a/bsp/fm3/mb9bf500r/board.c b/bsp/fm3/mb9bf500r/board.c deleted file mode 100644 index 896afc9ed4..0000000000 --- a/bsp/fm3/mb9bf500r/board.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-02-24 Bernard first implementation - */ - -#include -#include - -#include "board.h" -#include "mb9bf506r.h" -#include "core_cm3.h" - -extern const uint32_t SystemFrequency; - -/** - * @addtogroup FM3 - */ - -/*@{*/ - -/** - * This is the timer interrupt service routine. - * - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -/** -* This function will initial FM3 Easy Kit board. - */ -void rt_hw_board_init() -{ - /* init systick */ - SysTick_Config(SystemFrequency/RT_TICK_PER_SECOND - 1); -} - -/*@}*/ diff --git a/bsp/fm3/mb9bf500r/board.h b/bsp/fm3/mb9bf500r/board.h deleted file mode 100644 index 951db46f7d..0000000000 --- a/bsp/fm3/mb9bf500r/board.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-09-22 Bernard add board.h to this bsp - * 2011-03-04 lgnq add board.h to FM3 bsp - */ - -#ifndef __BOARD_H__ -#define __BOARD_H__ - -//Internal SRAM memory size[Kbytes] <8-64> -//MB9BF500 : 32 -//MB9BF504 : 32 -//MB9BF505 : 48 -//MB9BF506 : 64 -#define FM3_SRAM_SIZE 32 -#define FM3_SRAM_END (0x1FFFC000 + FM3_SRAM_SIZE * 1024) - -void rt_hw_board_init(void); - -#endif diff --git a/bsp/fm3/mb9bf500r/cpuusage.c b/bsp/fm3/mb9bf500r/cpuusage.c deleted file mode 100644 index 56d193b9ed..0000000000 --- a/bsp/fm3/mb9bf500r/cpuusage.c +++ /dev/null @@ -1,115 +0,0 @@ -#include -#include -#include "cpuusage.h" -#include "lcd.h" - -#ifdef RT_USING_RTGUI -#include -#include -#include -#endif - -#define CPU_USAGE_CALC_TICK 10 -#define CPU_USAGE_LOOP 100 - -static rt_uint8_t cpu_usage_major = 0, cpu_usage_minor= 0; -static rt_uint32_t total_count = 0; - -static void cpu_usage_idle_hook() -{ - rt_tick_t tick; - rt_uint32_t count; - volatile rt_uint32_t loop; - - if (total_count == 0) - { - loop = 0; - - /* get total count */ - rt_enter_critical(); - tick = rt_tick_get(); - while(rt_tick_get() - tick < CPU_USAGE_CALC_TICK) - { - total_count ++; - while (loop < CPU_USAGE_LOOP) loop ++; - } - rt_exit_critical(); - } - - count = 0; - loop = 0; - /* get CPU usage */ - tick = rt_tick_get(); - while (rt_tick_get() - tick < CPU_USAGE_CALC_TICK) - { - count ++; - while (loop < CPU_USAGE_LOOP) loop ++; - } - - /* calculate major and minor */ - if (count < total_count) - { - count = total_count - count; - cpu_usage_major = (count * 100) / total_count; - cpu_usage_minor = ((count * 100) % total_count) * 100 / total_count; - } - else - { - total_count = count; - - /* no CPU usage */ - cpu_usage_major = 0; - cpu_usage_minor = 0; - } -} - -void cpu_usage_get(rt_uint8_t *major, rt_uint8_t *minor) -{ - RT_ASSERT(major != RT_NULL); - RT_ASSERT(minor != RT_NULL); - - *major = cpu_usage_major; - *minor = cpu_usage_minor; -} - -void cpu_usage_init() -{ - /* set idle thread hook */ - rt_thread_idle_sethook(cpu_usage_idle_hook); -} -extern struct rt_messagequeue mq; -extern rt_thread_t info_tid; -static void cpu_thread_entry(void *parameter) -{ -#ifdef RT_USING_RTGUI - struct rtgui_event_command ecmd; - - RTGUI_EVENT_COMMAND_INIT(&ecmd); - ecmd.type = RTGUI_CMD_USER_INT; - ecmd.command_id = CPU_UPDATE; -#else - struct lcd_msg msg; -#endif - - while (1) - { -#ifdef RT_USING_RTGUI - rtgui_thread_send(info_tid, &ecmd.parent, sizeof(ecmd)); -#else - msg.type = CPU_MSG; - msg.major = cpu_usage_major; - msg.minor = cpu_usage_minor; - rt_mq_send(&mq, &msg, sizeof(msg)); -#endif - rt_thread_delay(20); - } -} - -static rt_thread_t cpu_thread; -void rt_hw_cpu_init(void) -{ - cpu_usage_init(); - cpu_thread = rt_thread_create("cpu", cpu_thread_entry, RT_NULL, 384, 27, 5); - if(cpu_thread != RT_NULL) - rt_thread_startup(cpu_thread); -} diff --git a/bsp/fm3/mb9bf500r/cpuusage.h b/bsp/fm3/mb9bf500r/cpuusage.h deleted file mode 100644 index e77bec0146..0000000000 --- a/bsp/fm3/mb9bf500r/cpuusage.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * File : cpuusage.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-03-03 lgnq - */ - -#ifndef __CPUUSAGE_H__ -#define __CPUUSAGE_H__ - -#define CPU_UPDATE 1 - -void cpu_usage_get(rt_uint8_t *major, rt_uint8_t *minor); -void rt_hw_cpu_init(void); - -#endif /*__ADC_H__ */ diff --git a/bsp/fm3/mb9bf500r/fm3_easy_kit.ewp b/bsp/fm3/mb9bf500r/fm3_easy_kit.ewp deleted file mode 100644 index b769dd1877..0000000000 --- a/bsp/fm3/mb9bf500r/fm3_easy_kit.ewp +++ /dev/null @@ -1,2030 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 20 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 26 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 11 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 20 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 26 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 11 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - CMSIS - - $PROJ_DIR$\..\CMSIS\core_cm3.c - - - $PROJ_DIR$\..\CMSIS\start_iar.S - - - $PROJ_DIR$\..\CMSIS\system_mb9bf50x.c - - - - FM3 - - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m3\context_iar.S - - - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m3\cpuport.c - - - - Kernel - - $PROJ_DIR$\..\..\..\src\clock.c - - - $PROJ_DIR$\..\..\..\src\device.c - - - $PROJ_DIR$\..\..\..\src\idle.c - - - $PROJ_DIR$\..\..\..\src\ipc.c - - - $PROJ_DIR$\..\..\..\src\irq.c - - - $PROJ_DIR$\..\..\..\src\kservice.c - - - $PROJ_DIR$\..\..\..\src\mem.c - - - $PROJ_DIR$\..\..\..\src\mempool.c - - - $PROJ_DIR$\..\..\..\src\module.c - - - $PROJ_DIR$\..\..\..\src\object.c - - - $PROJ_DIR$\..\..\..\src\rtm.c - - - $PROJ_DIR$\..\..\..\src\scheduler.c - - - $PROJ_DIR$\..\..\..\src\slab.c - - - $PROJ_DIR$\..\..\..\src\thread.c - - - $PROJ_DIR$\..\..\..\src\timer.c - - - - Rtgui - - $PROJ_DIR$\..\..\..\components\rtgui\widgets\about_view.c - - - $PROJ_DIR$\..\..\..\components\rtgui\common\asc12font.c - - - $PROJ_DIR$\..\..\..\components\rtgui\common\asc16font.c - - - $PROJ_DIR$\..\..\..\components\rtgui\common\blit.c - - - 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$PROJ_DIR$\..\..\..\components\rtgui\widgets\staticline.c - - - $PROJ_DIR$\..\..\..\components\rtgui\widgets\textbox.c - - - $PROJ_DIR$\..\..\..\components\rtgui\widgets\textview.c - - - $PROJ_DIR$\..\..\..\components\rtgui\widgets\title.c - - - $PROJ_DIR$\..\..\..\components\rtgui\widgets\toplevel.c - - - $PROJ_DIR$\..\..\..\components\rtgui\server\topwin.c - - - $PROJ_DIR$\..\..\..\components\rtgui\widgets\view.c - - - $PROJ_DIR$\..\..\..\components\rtgui\widgets\widget.c - - - $PROJ_DIR$\..\..\..\components\rtgui\widgets\window.c - - - $PROJ_DIR$\..\..\..\components\rtgui\widgets\workbench.c - - - - Startup - - $PROJ_DIR$\adc.c - - - $PROJ_DIR$\application.c - - - $PROJ_DIR$\board.c - - - $PROJ_DIR$\cpuusage.c - - - $PROJ_DIR$\info.c - - - $PROJ_DIR$\key.c - - - $PROJ_DIR$\lcd.c - - - $PROJ_DIR$\led.c - - - $PROJ_DIR$\startup.c - - - - - diff --git a/bsp/fm3/mb9bf500r/fm3_easy_kit.eww b/bsp/fm3/mb9bf500r/fm3_easy_kit.eww deleted file mode 100644 index bdaf802ebd..0000000000 --- a/bsp/fm3/mb9bf500r/fm3_easy_kit.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\fm3_easy_kit.ewp - - - - - diff --git a/bsp/fm3/mb9bf500r/fm3_rom.ld b/bsp/fm3/mb9bf500r/fm3_rom.ld deleted file mode 100644 index 861f94a00a..0000000000 --- a/bsp/fm3/mb9bf500r/fm3_rom.ld +++ /dev/null @@ -1,122 +0,0 @@ -/* Program Entry, set to mark it as "used" and avoid gc */ -MEMORY -{ - CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 - DATA (rw) : ORIGIN = 0x1FFFC000, LENGTH = 0x0000C000 -} -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . 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a/bsp/fm3/mb9bf500r/font.h b/bsp/fm3/mb9bf500r/font.h deleted file mode 100644 index 0819a2c22d..0000000000 --- a/bsp/fm3/mb9bf500r/font.h +++ /dev/null @@ -1,961 +0,0 @@ -#ifndef __FONT_H -#define __FONT_H - -/* Font definition */ -#define ________ 0x00 -#define _______X 0x01 -#define ______X_ 0x02 -#define ______XX 0x03 -#define _____X__ 0x04 -#define _____X_X 0x05 -#define _____XX_ 0x06 -#define _____XXX 0x07 -#define ____X___ 0x08 -#define ____X__X 0x09 -#define ____X_X_ 0x0a -#define ____X_XX 0x0b -#define ____XX__ 0x0c -#define ____XX_X 0x0d -#define ____XXX_ 0x0e -#define ____XXXX 0x0f -#define ___X____ 0x10 -#define ___X___X 0x11 -#define ___X__X_ 0x12 -#define ___X__XX 0x13 -#define ___X_X__ 0x14 -#define ___X_X_X 0x15 -#define ___X_XX_ 0x16 -#define ___X_XXX 0x17 -#define ___XX___ 0x18 -#define ___XX__X 0x19 -#define ___XX_X_ 0x1a -#define ___XX_XX 0x1b -#define ___XXX__ 0x1c -#define ___XXX_X 0x1d -#define ___XXXX_ 0x1e -#define ___XXXXX 0x1f -#define __X_____ 0x20 -#define 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X_X___XX 0xa3 -#define X_X__X__ 0xa4 -#define X_X__X_X 0xa5 -#define X_X__XX_ 0xa6 -#define X_X__XXX 0xa7 -#define X_X_X___ 0xa8 -#define X_X_X__X 0xa9 -#define X_X_X_X_ 0xaa -#define X_X_X_XX 0xab -#define X_X_XX__ 0xac -#define X_X_XX_X 0xad -#define X_X_XXX_ 0xae -#define X_X_XXXX 0xaf -#define X_XX____ 0xb0 -#define X_XX___X 0xb1 -#define X_XX__X_ 0xb2 -#define X_XX__XX 0xb3 -#define X_XX_X__ 0xb4 -#define X_XX_X_X 0xb5 -#define X_XX_XX_ 0xb6 -#define X_XX_XXX 0xb7 -#define X_XXX___ 0xb8 -#define X_XXX__X 0xb9 -#define X_XXX_X_ 0xba -#define X_XXX_XX 0xbb -#define X_XXXX__ 0xbc -#define X_XXXX_X 0xbd -#define X_XXXXX_ 0xbe -#define X_XXXXXX 0xbf -#define XX______ 0xc0 -#define XX_____X 0xc1 -#define XX____X_ 0xc2 -#define XX____XX 0xc3 -#define XX___X__ 0xc4 -#define XX___X_X 0xc5 -#define XX___XX_ 0xc6 -#define XX___XXX 0xc7 -#define XX__X___ 0xc8 -#define XX__X__X 0xc9 -#define XX__X_X_ 0xca -#define XX__X_XX 0xcb -#define XX__XX__ 0xcc -#define XX__XX_X 0xcd -#define XX__XXX_ 0xce -#define XX__XXXX 0xcf -#define XX_X____ 0xd0 -#define XX_X___X 0xd1 -#define XX_X__X_ 0xd2 -#define XX_X__XX 0xd3 -#define XX_X_X__ 0xd4 -#define XX_X_X_X 0xd5 -#define XX_X_XX_ 0xd6 -#define XX_X_XXX 0xd7 -#define XX_XX___ 0xd8 -#define XX_XX__X 0xd9 -#define XX_XX_X_ 0xda -#define XX_XX_XX 0xdb -#define XX_XXX__ 0xdc -#define XX_XXX_X 0xdd -#define XX_XXXX_ 0xde -#define XX_XXXXX 0xdf -#define XXX_____ 0xe0 -#define XXX____X 0xe1 -#define XXX___X_ 0xe2 -#define XXX___XX 0xe3 -#define XXX__X__ 0xe4 -#define XXX__X_X 0xe5 -#define XXX__XX_ 0xe6 -#define XXX__XXX 0xe7 -#define XXX_X___ 0xe8 -#define XXX_X__X 0xe9 -#define XXX_X_X_ 0xea -#define XXX_X_XX 0xeb -#define XXX_XX__ 0xec -#define XXX_XX_X 0xed -#define XXX_XXX_ 0xee -#define XXX_XXXX 0xef -#define XXXX____ 0xf0 -#define XXXX___X 0xf1 -#define XXXX__X_ 0xf2 -#define XXXX__XX 0xf3 -#define XXXX_X__ 0xf4 -#define XXXX_X_X 0xf5 -#define XXXX_XX_ 0xf6 -#define XXXX_XXX 0xf7 -#define XXXXX___ 0xf8 -#define XXXXX__X 0xf9 -#define XXXXX_X_ 0xfa -#define XXXXX_XX 0xfb -#define XXXXXX__ 0xfc -#define XXXXXX_X 0xfd -#define XXXXXXX_ 0xfe -#define XXXXXXXX 0xff - - - - -const unsigned char FONTTYPE8_8[][8] = { -/* blank */ - { - ________, - ________, - ________, - ________, - ________, - ________, - ________, - ________} - -/* 0 */ - ,{ - __XXX___, - _XX_XX__, - XX___XX_, - XX___XX_, - XX___XX_, - _XX_XX__, - __XXX___, - ________} - -/* 1 */ - ,{ - ___XX___, - __XXX___, - ___XX___, - ___XX___, - ___XX___, - ___XX___, - _XXXXXX_, - ________} - -/* 2 */ - ,{ - _XXXXX__, - XX___XX_, - _____XX_, - ___XXX__, - __XX____, - _XX__XX_, - XXXXXXX_, - ________} - -/* 3 */ - ,{ - _XXXXX__, - XX___XX_, - _____XX_, - __XXXX__, - _____XX_, - XX___XX_, - _XXXXX__, - ________} - -/* 4 */ - ,{ - ___XXX__, - __XXXX__, - _XX_XX__, - XX__XX__, - XXXXXXX_, - ____XX__, - ___XXXX_, - ________} - -/* 5 */ - ,{ - XXXXXXX_, - XX______, - XX______, - XXXXXX__, - _____XX_, - XX___XX_, - _XXXXX__, - ________} - -/* 6 */ - ,{ - __XXX___, - _XX_____, - XX______, - XXXXXX__, - XX___XX_, - XX___XX_, - _XXXXX__, - ________} - -/* 7 */ - ,{ - XXXXXXX_, - XX___XX_, - ____XX__, - ___XX___, - __XX____, - __XX____, - __XX____, - ________} - -/* 8 */ - ,{ - _XXXXX__, - XX___XX_, - XX___XX_, - _XXXXX__, - XX___XX_, - XX___XX_, - _XXXXX__, - ________} - -/* 9 */ - ,{ - _XXXXX__, - XX___XX_, - XX___XX_, - _XXXXXX_, - _____XX_, - ____XX__, - _XXXX___, - ________} - -/* A */ - ,{ - __XXX___, - _XX_XX__, - XX___XX_, - XXXXXXX_, - XX___XX_, - XX___XX_, - XX___XX_, - ________} - -/* B */ - ,{ - XXXXXX__, - _XX__XX_, - _XX__XX_, - _XXXXX__, - _XX__XX_, - _XX__XX_, - XXXXXX__, - ________} - -/* C */ - ,{ - __XXXX__, - _XX__XX_, - XX______, - XX______, - XX______, - _XX__XX_, - __XXXX__, - ________} - -/* D */ - ,{ - XXXXX___, - _XX_XX__, - _XX__XX_, - _XX__XX_, - _XX__XX_, - _XX_XX__, - XXXXX___, - ________} - -/* E */ - ,{ - XXXXXXX_, - _XX___X_, - _XX_X___, - _XXXX___, - _XX_X___, - _XX___X_, - XXXXXXX_, - ________} - -/* F */ - ,{ - XXXXXXX_, - _XX___X_, - _XX_X___, - _XXXX___, - _XX_X___, - _XX_____, - XXXX____, - ________} - -/* G */ - ,{ - __XXXX__, - _XX__XX_, - XX______, - XX______, - XX__XXX_, - _XX__XX_, - __XXX_X_, - ________} - -/* H */ - ,{ - XX___XX_, - XX___XX_, - XX___XX_, - XXXXXXX_, - XX___XX_, - XX___XX_, - XX___XX_, - ________} - -/* I */ - ,{ - __XXXX__, - ___XX___, - ___XX___, - ___XX___, - ___XX___, - ___XX___, - __XXXX__, - ________} - -/* J */ - ,{ - ___XXXX_, - ____XX__, - ____XX__, - ____XX__, - XX__XX__, - XX__XX__, - _XXXX___, - ________} - -/* K */ - ,{ - XXX__XX_, - _XX__XX_, - _XX_XX__, - _XXXX___, - _XX_XX__, - _XX__XX_, - XXX__XX_, - ________} - -/* L */ - ,{ - XXXX____, - _XX_____, - _XX_____, - _XX_____, - _XX___X_, - _XX__XX_, - XXXXXXX_, - ________} - -/* M */ - ,{ - XX___XX_, - XXX_XXX_, - XXXXXXX_, - XXXXXXX_, - XX_X_XX_, - XX___XX_, - XX___XX_, - ________} - -/* N */ - ,{ - XX___XX_, - XXX__XX_, - XXXX_XX_, - XX_XXXX_, - XX__XXX_, - XX___XX_, - XX___XX_, - ________} - -/* O */ - ,{ - _XXXXX__, - XX___XX_, - XX___XX_, - XX___XX_, - XX___XX_, - XX___XX_, - _XXXXX__, - ________} - -/* P */ - ,{ - XXXXXX__, - _XX__XX_, - _XX__XX_, - _XXXXX__, - _XX_____, - _XX_____, - XXXX____, - ________} - -/* Q */ - ,{ - _XXXXX__, - XX___XX_, - XX___XX_, - XX___XX_, - XX___XX_, - XX__XXX_, - _XXXXX__, - ____XXX_} - -/* R */ - ,{ - XXXXXX__, - _XX__XX_, - _XX__XX_, - _XXXXX__, - _XX_XX__, - _XX__XX_, - XXX__XX_, - ________} - -/* S */ - ,{ - __XXXX__, - _XX__XX_, - __XX____, - ___XX___, - ____XX__, - _XX__XX_, - __XXXX__, - ________} - -/* T */ - ,{ - _XXXXXX_, - _XXXXXX_, - _X_XX_X_, - ___XX___, - ___XX___, - ___XX___, - __XXXX__, - ________} - -/* U */ - ,{ - XX___XX_, - XX___XX_, - XX___XX_, - XX___XX_, - XX___XX_, - XX___XX_, - _XXXXX__, - ________} - -/* V */ - ,{ - XX___XX_, - XX___XX_, - XX___XX_, - XX___XX_, - XX___XX_, - _XX_XX__, - __XXX___, - ________} - -/* W */ - ,{ - XX___XX_, - XX___XX_, - XX___XX_, - XX_X_XX_, - XX_X_XX_, - XXXXXXX_, - _XX_XX__, - ________} - -/* X */ - ,{ - XX___XX_, - XX___XX_, - _XX_XX__, - __XXX___, - _XX_XX__, - XX___XX_, - XX___XX_, - ________} - -/* Y */ - ,{ - _XX__XX_, - _XX__XX_, - _XX__XX_, - __XXXX__, - ___XX___, - ___XX___, - __XXXX__, - ________} - -/* Z */ - ,{ - XXXXXXX_, - XX___XX_, - X___XX__, - ___XX___, - __XX__X_, - _XX__XX_, - XXXXXXX_, - ________} - -/* a */ - ,{ - ________, - ________, - _XXXX___, - ____XX__, - _XXXXX__, - XX__XX__, - _XXX_XX_, - ________} - -/* b */ - ,{ - XXX_____, - _XX_____, - _XXXXX__, - _XX__XX_, - _XX__XX_, - _XX__XX_, - XX_XXX__, - ________} - -/* c */ - ,{ - ________, - ________, - _XXXXX__, - XX___XX_, - XX______, - XX___XX_, - _XXXXX__, - ________} - -/* d */ - ,{ - ___XXX__, - ____XX__, - _XXXXX__, - XX__XX__, - XX__XX__, - XX__XX__, - _XXX_XX_, - ________} - -/* e */ - ,{ - ________, - ________, - _XXXXX__, - XX___XX_, - XXXXXXX_, - XX______, - _XXXXX__, - ________} - -/* f */ - ,{ - __XXXX__, - _XX__XX_, - _XX_____, - XXXXX___, - _XX_____, - _XX_____, - XXXX____, - ________} - -/* g */ - ,{ - ________, - ________, - _XXX_XX_, - XX__XX__, - XX__XX__, - _XXXXX__, - ____XX__, - XXXXX___} - -/* h */ - ,{ - XXX_____, - _XX_____, - _XX_XX__, - _XXX_XX_, - _XX__XX_, - _XX__XX_, - XXX__XX_, - ________} - -/* i */ - ,{ - ___XX___, - ________, - __XXX___, - ___XX___, - ___XX___, - ___XX___, - __XXXX__, - ________} - -/* j */ - ,{ - _____XX_, - ________, - _____XX_, - _____XX_, - _____XX_, - _XX__XX_, - _XX__XX_, - __XXXX__} - -/* k */ - ,{ - XXX_____, - _XX_____, - _XX__XX_, - _XX_XX__, - _XXXX___, - _XX_XX__, - XXX__XX_, - ________} - -/* l */ - ,{ - __XXX___, - ___XX___, - ___XX___, - ___XX___, - ___XX___, - ___XX___, - __XXXX__, - ________} - -/* m */ - ,{ - ________, - ________, - XXX_XX__, - XXXXXXX_, - XX_X_XX_, - XX_X_XX_, - XX_X_XX_, - ________} - -/* n */ - ,{ - ________, - ________, - XX_XXX__, - _XX__XX_, - _XX__XX_, - _XX__XX_, - _XX__XX_, - ________} - -/* o */ - ,{ - ________, - ________, - _XXXXX__, - XX___XX_, - XX___XX_, - XX___XX_, - _XXXXX__, - ________} - -/* p */ - ,{ - ________, - ________, - XX_XXX__, - _XX__XX_, - _XX__XX_, - _XXXXX__, - _XX_____, - XXXX____} - -/* q */ - ,{ - ________, - ________, - _XXX_XX_, - XX__XX__, - XX__XX__, - _XXXXX__, - ____XX__, - ___XXXX_} - -/* r */ - ,{ - ________, - ________, - XX_XXX__, - _XXX_XX_, - _XX_____, - _XX_____, - XXXX____, - ________} - -/* s */ - ,{ - ________, - ________, - _XXXXXX_, - XX______, - _XXXXX__, - _____XX_, - XXXXXX__, - ________} - -/* t */ - ,{ - __XX____, - __XX____, - XXXXXX__, - __XX____, - __XX____, - __XX_XX_, - ___XXX__, - ________} - -/* u */ - ,{ - ________, - ________, - XX__XX__, - XX__XX__, - XX__XX__, - XX__XX__, - _XXX_XX_, - ________} - -/* v */ - ,{ - ________, - ________, - XX___XX_, - XX___XX_, - XX___XX_, - _XX_XX__, - __XXX___, - ________} - -/* w */ - ,{ - ________, - ________, - XX___XX_, - XX_X_XX_, - XX_X_XX_, - XXXXXXX_, - _XX_XX__, - ________} - -/* x */ - ,{ - ________, - ________, - XX___XX_, - _XX_XX__, - __XXX___, - _XX_XX__, - XX___XX_, - ________} - -/* y */ - ,{ - ________, - ________, - XX___XX_, - XX___XX_, - XX___XX_, - _XXXXXX_, - _____XX_, - XXXXXX__} - -/* z */ - ,{ - ________, - ________, - _XXXXXX_, - _X__XX__, - ___XX___, - __XX__X_, - _XXXXXX_, - ________} - -}; - -#endif /* __FONT_H */ diff --git a/bsp/fm3/mb9bf500r/info.c b/bsp/fm3/mb9bf500r/info.c deleted file mode 100644 index 104d02a70f..0000000000 --- a/bsp/fm3/mb9bf500r/info.c +++ /dev/null @@ -1,214 +0,0 @@ -#include - -#ifdef RT_USING_RTGUI -#include -#include -#include - -#include -#include - -#include "adc.h" -#include "cpuusage.h" - -extern rt_uint16_t adc_value; -static rt_uint8_t index = 0 ; -static rt_bool_t view_event_handler(struct rtgui_widget* widget, struct rtgui_event* event) -{ - if (event->type == RTGUI_EVENT_PAINT) - { - struct rtgui_dc* dc; - struct rtgui_rect rect; - - dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) - return RT_FALSE; - rtgui_widget_get_rect(widget, &rect); - - rtgui_dc_fill_rect(dc, &rect); - rect.x2 -= 1; rect.y2 -= 1; - rtgui_dc_draw_hline(dc, rect.x1, rect.x2, rect.y1); - rtgui_dc_draw_vline(dc, rect.x1, rect.y1, rect.y2); - - rtgui_dc_draw_hline(dc, rect.x1, rect.x2, rect.y2); - rtgui_dc_draw_vline(dc, rect.x2, rect.y1, rect.y2 + 1); - - /* shrink border */ - rtgui_rect_inflate(&rect, -1); - - /* draw text */ - rtgui_widget_get_rect(widget, &rect); - rect.y1 += 25; - rtgui_dc_draw_text(dc, " FM3 Easy Kit Demo", &rect); - rect.y1 += 10; - rtgui_dc_draw_text(dc, " rt-thread / RTGUI", &rect); - rtgui_dc_end_drawing(dc); - - return RT_FALSE; - } - else if (event->type == RTGUI_EVENT_KBD) - { - struct rtgui_dc* dc; - struct rtgui_rect rect; - struct rtgui_event_kbd* ekbd = (struct rtgui_event_kbd*)event; - if (ekbd->type == RTGUI_KEYDOWN) - { - char key_str[16]; - switch (ekbd->key) - { - case RTGUIK_LEFT: - rt_sprintf(key_str, "%s", "L"); - break; - case RTGUIK_RIGHT: - rt_sprintf(key_str, "%s", "R"); - break; - case RTGUIK_DOWN: - rt_sprintf(key_str, "%s", "D"); - break; - case RTGUIK_UP: - rt_sprintf(key_str, "%s", "U"); - break; - default: - rt_sprintf(key_str, "%s", "S"); - break; - } - dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) - return RT_FALSE; - rect.x1 = 118; - rect.y1 = 1; - rect.x2 = 127; - rect.y2 = 10; - rtgui_dc_fill_rect(dc, &rect); - rtgui_dc_draw_text(dc, key_str, &rect); - rtgui_dc_end_drawing(dc); - } - else if (ekbd->type == RTGUI_KEYUP) - { - dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) - return RT_FALSE; - rect.x1 = 118; - rect.y1 = 1; - rect.x2 = 127; - rect.y2 = 10; - rtgui_dc_fill_rect(dc, &rect); - //rtgui_dc_draw_text(dc, key_str, &rect); - rtgui_dc_end_drawing(dc); - } - } - else if (event->type == RTGUI_EVENT_COMMAND) - { - char str[16]; - struct rtgui_dc* dc; - struct rtgui_rect rect; - struct rtgui_event_command* ecmd; - rt_uint8_t major,minor; - dc = rtgui_dc_begin_drawing(widget); - if (dc == RT_NULL) - return RT_FALSE; - - ecmd = (struct rtgui_event_command*)event; - switch (ecmd->command_id) - { - case ADC_UPDATE: - rect.x1 = 1; - rect.y1 = 1; - rect.x2 = 117; - rect.y2 = 10; - rtgui_dc_fill_rect(dc, &rect); - rt_sprintf(str, "ADC = %d mv", adc_value); - rtgui_dc_draw_text(dc, str, &rect); - break; - case CPU_UPDATE: - cpu_usage_get(&major, &minor); - rect.x1 = 1; - rect.y1 = 12; - rect.x2 = 127; - rect.y2 = 22; - rtgui_dc_fill_rect(dc, &rect); - rt_sprintf(str, "CPU : %d.%d%", major, minor); - rtgui_dc_draw_text(dc, str, &rect); - - rect.y1 = 23; - rect.y2 = 63; - index++; - if (index == 127) - { - index = 1; - rtgui_dc_fill_rect(dc, &rect); - } - if (major>40) - rtgui_dc_draw_vline(dc, index, rect.y1, rect.y2); - else - rtgui_dc_draw_vline(dc, index, rect.y2-major, rect.y2); - break; - } - rtgui_dc_end_drawing(dc); - } - - return rtgui_view_event_handler(widget, event); -} - -static void info_entry(void* parameter) -{ - rt_mq_t mq; - struct rtgui_view* view; - struct rtgui_workbench* workbench; - - mq = rt_mq_create("qInfo", 256, 4, RT_IPC_FLAG_FIFO); - rtgui_thread_register(rt_thread_self(), mq); - - workbench = rtgui_workbench_create("info", "workbench"); - if(workbench == RT_NULL) - return; - - view = rtgui_view_create("view"); - RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(view)) = white; - RTGUI_WIDGET_FOREGROUND(RTGUI_WIDGET(view)) = black; - rtgui_widget_set_event_handler(RTGUI_WIDGET(view), view_event_handler); - - rtgui_workbench_add_view(workbench, view); - /* this view can be focused */ - RTGUI_WIDGET(view)->flag |= RTGUI_WIDGET_FLAG_FOCUSABLE; - /* set widget focus */ - rtgui_widget_focus(RTGUI_WIDGET(view)); - - rtgui_view_show(view, RT_FALSE); - - rtgui_workbench_event_loop(workbench); - - rtgui_thread_deregister(rt_thread_self()); - rt_mq_delete(mq); -} - -rt_thread_t info_tid; -void info_init() -{ - info_tid = rt_thread_create("info", - info_entry, RT_NULL, - 2048, 25, 10); - - if (info_tid != RT_NULL) rt_thread_startup(info_tid); -} - -void rtgui_startup() -{ - rtgui_rect_t rect; - - /* GUIϵͳ³õʼ»¯ */ - rtgui_system_server_init(); - - /* register dock panel */ - rect.x1 = 0; - rect.y1 = 0; - rect.x2 = 128; - rect.y2 = 64; - rtgui_panel_register("info", &rect); - rtgui_panel_set_default_focused("info"); - - /* Æô¶¯info workbench */ - info_init(); -} - -#endif diff --git a/bsp/fm3/mb9bf500r/key.c b/bsp/fm3/mb9bf500r/key.c deleted file mode 100644 index a03b48366a..0000000000 --- a/bsp/fm3/mb9bf500r/key.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * File : key.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-03-03 lgnq - */ - -#include -#include "key.h" -#include "lcd.h" - -#ifdef RT_USING_RTGUI -#include -#include -#endif - -static void key_io_init(void) -{ - /*Select CPIO function*/ - KEY_PFR &= ~KEY_MASK; - /*Set CPIO Pull-Up function*/ - KEY_PCR |= KEY_MASK; - /*Make button pins inputs*/ - KEY_DDR &= ~KEY_MASK; -} - -static void key_thread_entry(void *parameter) -{ -#ifdef RT_USING_RTGUI - rt_time_t next_delay; - rt_uint8_t i; - - struct rtgui_event_kbd kbd_event; - - key_io_init(); - - /* init keyboard event */ - RTGUI_EVENT_KBD_INIT(&kbd_event); - kbd_event.mod = RTGUI_KMOD_NONE; - kbd_event.unicode = 0; - - while (1) - { - next_delay = RT_TICK_PER_SECOND/10; - kbd_event.key = RTGUIK_UNKNOWN; - kbd_event.type = RTGUI_KEYDOWN; - - if (KEY_ENTER_GETVALUE() == 0 ) - { - for(i=0; ; i++) - { - rt_thread_delay( next_delay ); - if (KEY_ENTER_GETVALUE() == 0) - { - if (i>=4) - { - /* HOME key */ - kbd_event.key = RTGUIK_HOME; - next_delay = RT_TICK_PER_SECOND/5; - break; - } - } - else - { - kbd_event.key = RTGUIK_RETURN; - break; - } - } - } - - if (KEY_DOWN_GETVALUE() == 0) - { - kbd_event.key = RTGUIK_DOWN; - } - - if (KEY_UP_GETVALUE() == 0) - { - kbd_event.key = RTGUIK_UP; - } - - if (KEY_RIGHT_GETVALUE() == 0) - { - kbd_event.key = RTGUIK_RIGHT; - } - - if (KEY_LEFT_GETVALUE() == 0) - { - kbd_event.key = RTGUIK_LEFT; - } - - if (kbd_event.key != RTGUIK_UNKNOWN) - { - /* post down event */ - rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event)); - } - else - { - kbd_event.type = RTGUI_KEYUP; - rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event)); - } - /* wait next key press */ - rt_thread_delay(next_delay); - } -#else - extern struct rt_messagequeue mq; - rt_time_t next_delay; - struct lcd_msg msg; - msg.type = KEY_MSG; - - key_io_init(); - - while (1) - { - msg.key = NO_KEY; - - next_delay = RT_TICK_PER_SECOND/10; - - if (KEY_ENTER_GETVALUE() == 0 ) - { - msg.key = KEY_ENTER; - } - - if (KEY_DOWN_GETVALUE() == 0) - { - msg.key = KEY_DOWN; - } - - if (KEY_UP_GETVALUE() == 0) - { - msg.key = KEY_UP; - } - - if (KEY_RIGHT_GETVALUE() == 0) - { - msg.key = KEY_RIGHT; - } - - if (KEY_LEFT_GETVALUE() == 0) - { - msg.key = KEY_LEFT; - } - - rt_mq_send(&mq, &msg, sizeof(msg)); - - /* wait next key press */ - rt_thread_delay(next_delay); - } -#endif -} - -static rt_thread_t key_thread; -void rt_hw_key_init(void) -{ - key_thread = rt_thread_create("key", key_thread_entry, RT_NULL, 384, 28, 5); - if (key_thread != RT_NULL) - rt_thread_startup(key_thread); -} diff --git a/bsp/fm3/mb9bf500r/key.h b/bsp/fm3/mb9bf500r/key.h deleted file mode 100644 index 3b47c7b1bb..0000000000 --- a/bsp/fm3/mb9bf500r/key.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * File : key.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-03-06 lgnq - */ -#ifndef __KEY_H__ -#define __KEY_H__ - -#include "mb9bf506r.h" - -#define KEY_DOWN (1<<0) -#define KEY_ENTER (1<<1) -#define KEY_LEFT (1<<2) -#define KEY_RIGHT (1<<3) -#define KEY_UP (1<<4) -#define NO_KEY (1<<5) - -#define KEY_MASK (KEY_DOWN | KEY_ENTER | KEY_LEFT | KEY_RIGHT | KEY_UP) -#define KEY_PFR (FM3_GPIO->PFR7) -#define KEY_PCR (FM3_GPIO->PCR7) -#define KEY_PDIR (FM3_GPIO->PDIR7) -#define KEY_DDR (FM3_GPIO->DDR7) - -#define RT_DEVICE_CTRL_KEY_SCAN 0 -#define RT_DEVICE_CTRL_KEY_STATUS 1 - -#define SET_BIT(byte, bit) ((byte) |= (1<<(bit))) -#define CLR_BIT(byte, bit) ((byte) &= ~(1<<(bit))) -#define TST_BIT(byte, bit) (((byte) & (1<<(bit)))?1:0) - -#define KEY_ENTER_GETVALUE() TST_BIT(KEY_PDIR, 1) -#define KEY_DOWN_GETVALUE() TST_BIT(KEY_PDIR, 0) -#define KEY_UP_GETVALUE() TST_BIT(KEY_PDIR, 4) -#define KEY_RIGHT_GETVALUE() TST_BIT(KEY_PDIR, 3) -#define KEY_LEFT_GETVALUE() TST_BIT(KEY_PDIR, 2) - -void rt_hw_key_init(void); - -#endif diff --git a/bsp/fm3/mb9bf500r/lcd.c b/bsp/fm3/mb9bf500r/lcd.c deleted file mode 100644 index b665a61378..0000000000 --- a/bsp/fm3/mb9bf500r/lcd.c +++ /dev/null @@ -1,481 +0,0 @@ -/* - * File : lcd.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-03-05 lgnq ZYMG12864C3 LCD driver - */ - -#include -#include "lcd.h" -#include "font.h" - -static struct rt_device_graphic_info _lcd_info; -static rt_uint8_t gui_disp_buf[GUI_LCM_YMAX/8][GUI_LCM_XMAX]; -const unsigned char BIT_MASK[8] = {0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01}; -/* simple font: ' ', '0'~'9','a'~'z','A'~'Z' */ -extern const unsigned char FONTTYPE8_8[][8]; - -rt_uint32_t x; -rt_uint32_t y; - -void power_delay(void) -{ - rt_uint32_t i = 0x4ffff; - while(i--) - ; -} - -void delay(void) -{ - rt_uint8_t i = 0x8; - while(i--) - ; -} - -void reset_delay(void) -{ - rt_uint8_t i = 0xff; - while(i--) - ; -} - -void lcd_write_cmd(unsigned char command) -{ - rt_uint8_t i; - - LCD_PS_LOW(); - LCD_CS_LOW(); - LCD_CD_LOW(); - for (i=0; i<8; i++) - { - if (command & (0x80 >> i)) - LCD_DATA_HIGH(); - else - LCD_DATA_LOW(); - - LCD_CLK_LOW(); - delay(); - LCD_CLK_HIGH(); - delay(); - } - LCD_CS_HIGH(); -} - -void lcd_write_data(unsigned char data) -{ - rt_uint8_t i; - - LCD_PS_LOW(); - LCD_CS_LOW(); - LCD_CD_HIGH(); - for (i=0; i<8; i++) - { - if (data & (0x80 >> i)) - LCD_DATA_HIGH(); - else - LCD_DATA_LOW(); - - LCD_CLK_LOW(); - delay(); - LCD_CLK_HIGH(); - delay(); - } - LCD_CS_HIGH(); -} - -#ifdef RT_USING_RTGUI -#include -#include - -static void rt_hw_lcd_update(struct rt_device_rect_info *rect_info) -{ - rt_uint8_t i,j = GUI_LCM_XMAX; - rt_uint8_t* p = (rt_uint8_t*)gui_disp_buf; - - for (i=0; i> 4; - lcd_write_cmd(SET_PAGE_ADDR_0 | page); - lcd_write_cmd(SET_COLH_ADDR_0 | colh); - lcd_write_cmd(SET_COLL_ADDR_0 | coll); - lcd_write_data(gui_disp_buf[page][i]); - } -} - -const struct rtgui_graphic_driver_ops _lcd_ops = -{ - rt_hw_lcd_set_pixel, - rt_hw_lcd_get_pixel, - rt_hw_lcd_draw_hline, - rt_hw_lcd_draw_vline, - rt_hw_lcd_draw_raw_hline -}; -#endif - -void lcd_io_init() -{ - /* Release the analog input function*/ - FM3_GPIO->ADE =0x03; - /*Select CPIO function*/ - LCD_CS_PFR &= ~LCD_CS; - /*Make pin output*/ - LCD_CS_DDR |= LCD_CS; - /*Select CPIO function*/ - LCD_CD_PFR &= ~LCD_CD; - /*Make pin output*/ - LCD_CD_DDR |= LCD_CD; - /*Select CPIO function*/ - LCD_PS_PFR &= ~LCD_PS; - /*Make pin output*/ - LCD_PS_DDR |= LCD_PS; - /*Select CPIO function*/ - LCD_CLK_PFR &= ~LCD_CLK; - /*Make pin output*/ - LCD_CLK_DDR |= LCD_CLK; - /*Select CPIO function*/ - LCD_DATA_PFR &= ~LCD_DATA; - /*Make pin output*/ - LCD_DATA_DDR |= LCD_DATA; -} - -/* RT-Thread Device Interface */ -static rt_err_t rt_lcd_init (rt_device_t dev) -{ - lcd_io_init(); - - power_delay(); - lcd_write_cmd(DISPLAY_OFF); - reset_delay(); - // Resetting circuit - lcd_write_cmd(RESET_LCD); - reset_delay(); - // LCD bias setting - lcd_write_cmd(SET_LCD_BIAS_9); - reset_delay(); - // ADC selection: display from left to right - lcd_write_cmd(SET_ADC_NORMAL); - reset_delay(); - // Common output state selection: display from up to down - lcd_write_cmd(COM_SCAN_DIR_REVERSE); - reset_delay(); - - lcd_write_cmd(POWER_BOOSTER_ON); - power_delay(); // 50ms requried - lcd_write_cmd(POWER_REGULATOR_ON); - power_delay(); // 50ms - lcd_write_cmd(POWER_FOLLOWER_ON); - power_delay(); // 50ms - - // Setting the built-in resistance radio for regulation of the V0 voltage - // Electronic volume control - // Power control setting - lcd_write_cmd(SET_ELECVOL_REG|0x05); - delay(); - lcd_write_cmd(SET_ELECVOL_MODE); - delay(); - lcd_write_cmd(SET_ELECVOL_REG); - delay(); - // LCD_Clear(); - delay(); - lcd_write_cmd(SET_PAGE_ADDR_0); - delay(); - lcd_write_cmd(SET_COLH_ADDR_0); - delay(); - lcd_write_cmd(SET_COLL_ADDR_0); - delay(); - lcd_write_cmd(DISPLAY_ON); - delay(); - - lcd_write_cmd(DISPLAY_ALL_ON); - delay(); - lcd_write_cmd(DISPLAY_OFF); - delay(); - lcd_write_cmd(DISPLAY_ON); - delay(); - lcd_write_cmd(DISPLAY_ALL_NORMAL); - delay(); - - return RT_EOK; -} - -/******************************************************************************* -* Function Name : LCD_FillAll -* Description : Fill the whole LCD. -* Input : None -* Output : None -* Return : None -*******************************************************************************/ -void LCD_FillAll(unsigned char* buffer) -{ - unsigned char i,j = GUI_LCM_XMAX; - unsigned char* p = buffer; - - for (i=0; i> 4; - - lcd_write_cmd(SET_PAGE_ADDR_0 | page); // page no. - lcd_write_cmd(SET_COLH_ADDR_0 | colh); // fixed col first addr - lcd_write_cmd(SET_COLL_ADDR_0 | coll); - lcd_write_data(gui_disp_buf[page][x]); -} - -/**************************************************************************** -* Function Name : LCD_PutChar -* Description : output a char to screen - (the char only can be ' ','0'~'9','A'~'Z','a'~'z') -* Input : x X-coordinate - y Y-coordinate - ch character -* Output : None -* Return : 1 Success - 0 Fail -****************************************************************************/ -unsigned char LCD_PutChar(unsigned long x, unsigned long y, unsigned char ch) -{ - unsigned char data; - unsigned char i, j; - - if( x >=(GUI_LCM_XMAX-8) ) return(0); - if( y >=(GUI_LCM_YMAX-8) ) return(0); - - if(ch == 0x20) - ch -= 0x20; - else if((ch >= 0x30)&&(ch <= 0x39)) - ch -= 0x2f; - else if((ch >= 0x41)&&(ch <= 0x5a)) - ch -= 0x36; - else if((ch >= 0x61)&&(ch <= 0x7a)) - ch -= 0x3C; - else - return(0); - - for(i = 0; i < 8; i++) - { - data = FONTTYPE8_8[ch][i]; - - for(j = 0; j < 8; j++) - { - if( (data&BIT_MASK[j]) == 0) - gui_disp_buf[y / 8][x] &= (~(0x01 << ( y % 8))); - else - gui_disp_buf[y / 8][x] |= (0x01 <<( y % 8)); - LCD_UpdatePoint(x, y); - x ++; - } - x -= 8; - y++; - } - - return(1); -} - -/**************************************************************************** -* Function Name : LCD_PutString -* Description : output string to screen -* Input : x X-coordinate - y Y-coordinate - str pointer to string -* Output : None -* Return : None -****************************************************************************/ -void LCD_PutString(unsigned long x, unsigned long y, char *str) -{ - while(1) - { - if( (*str)=='\0' ) break; - if( LCD_PutChar(x, y, *str++) == 0 ) break; - x += 6; - } -} - -static rt_err_t rt_lcd_control (rt_device_t dev, rt_uint8_t cmd, void *args) -{ - switch (cmd) - { -#ifdef RT_USING_RTGUI - case RTGRAPHIC_CTRL_RECT_UPDATE: - rt_hw_lcd_update(args); - break; - case RTGRAPHIC_CTRL_POWERON: - break; - case RTGRAPHIC_CTRL_POWEROFF: - break; - case RTGRAPHIC_CTRL_GET_INFO: - rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); - break; - case RTGRAPHIC_CTRL_SET_MODE: - break; -#else - case RT_DEVICE_CTRL_LCD_DISPLAY_ON: - lcd_write_cmd(DISPLAY_ON); - break; - case RT_DEVICE_CTRL_LCD_DISPLAY_OFF: - lcd_write_cmd(DISPLAY_OFF); - break; - case RT_DEVICE_CTRL_LCD_PUT_STRING: - LCD_PutString(x, y, (char*)args); - break; - case RT_DEVICE_CTRL_LCD_CLEAR_SCR: - LCD_ClearSCR(); - break; -#endif - } - - return RT_EOK; -} - -void rt_hw_lcd_init(void) -{ - rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); - if (lcd == RT_NULL) return; /* no memory yet */ - - _lcd_info.bits_per_pixel = 16; - _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; - _lcd_info.framebuffer = RT_NULL; - _lcd_info.width = LCD_WIDTH; - _lcd_info.height = LCD_HEIGHT; - - /* init device structure */ - lcd->type = RT_Device_Class_Unknown; - lcd->init = rt_lcd_init; - lcd->open = RT_NULL; - lcd->close = RT_NULL; - lcd->control = rt_lcd_control; -#ifdef RT_USING_RTGUI - lcd->user_data = (void*)&_lcd_ops; -#endif - /* register lcd device to RT-Thread */ - rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); -} diff --git a/bsp/fm3/mb9bf500r/lcd.h b/bsp/fm3/mb9bf500r/lcd.h deleted file mode 100644 index d1c9877897..0000000000 --- a/bsp/fm3/mb9bf500r/lcd.h +++ /dev/null @@ -1,189 +0,0 @@ -/* - * File : lcd.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2008-03-29 Yi.Qiu - * 2011-06-13 lgnq modified for FM3 easy kit - */ -#ifndef __LCD_H__ -#define __LCD_H__ - -#include -#include "mb9bf506r.h" - -/********* LCD Hardward Interface ************* -LCD_CS PORT1.7 -LCD_CD PORT1.6 -LCD_WR PORT1.5 -LCD_RD PORT1.4 -LCD_SCK PORT1.3 -LCD_MOSI PORT1.2 -LCD_C86 PORT1.1 -LCD_PS PORT1.0 -LCD_DATA[0..7] PORT5.[0..7] -***********************************************/ -#define LCD_CS (1UL << 7) -#define LCD_CS_DDR (FM3_GPIO->DDR1) -#define LCD_CS_PFR (FM3_GPIO->PFR1) -#define LCD_CS_PDOR (FM3_GPIO->PDOR1) - -#define LCD_CD (1UL << 6) -#define LCD_CD_DDR (FM3_GPIO->DDR1) -#define LCD_CD_PFR (FM3_GPIO->PFR1) -#define LCD_CD_PDOR (FM3_GPIO->PDOR1) - -#define LCD_PS (1UL << 0) -#define LCD_PS_DDR (FM3_GPIO->DDR1) -#define LCD_PS_PFR (FM3_GPIO->PFR1) -#define LCD_PS_PDOR (FM3_GPIO->PDOR1) - -#define LCD_CLK (1UL << 6) -#define LCD_CLK_DDR (FM3_GPIO->DDR5) -#define LCD_CLK_PFR (FM3_GPIO->PFR5) -#define LCD_CLK_PDOR (FM3_GPIO->PDOR5) - -#define LCD_DATA (1UL << 7) -#define LCD_DATA_DDR (FM3_GPIO->DDR5) -#define LCD_DATA_PFR (FM3_GPIO->PFR5) -#define LCD_DATA_PDOR (FM3_GPIO->PDOR5) - -/* LCD driver for ZYMG12864C3 */ -#define LCD_WIDTH 128 -#define LCD_HEIGHT 64 - -// Driver the LCD with Parallel or serial interface and the command/data control pin is gpio -#define LCD_CS_HIGH() LCD_CS_PDOR |= LCD_CS -#define LCD_CS_LOW() LCD_CS_PDOR &= ~LCD_CS - -#define LCD_CD_HIGH() LCD_CD_PDOR |= LCD_CD -#define LCD_CD_LOW() LCD_CD_PDOR &= ~LCD_CD - -#define LCD_PS_HIGH() LCD_PS_PDOR |= LCD_PS -#define LCD_PS_LOW() LCD_PS_PDOR &= ~LCD_PS - -#define LCD_CLK_HIGH() LCD_CLK_PDOR |= LCD_CLK -#define LCD_CLK_LOW() LCD_CLK_PDOR &= ~LCD_CLK - -#define LCD_DATA_HIGH() LCD_DATA_PDOR |= LCD_DATA -#define LCD_DATA_LOW() LCD_DATA_PDOR &= ~LCD_DATA - -// define the arrtibute of ZYMG12864(LCM) -#define GUI_LCM_XMAX 128 // defined the lcd's line-number is 128 -#define GUI_LCM_YMAX 64 // defined the lcd's column-number is 64 -#define GUI_LCM_PAGE 8 // defined the lcd's page-number is 8(GUI_LCM_YMAX/8) - -/* set LCD command */ -#define DISPLAY_ON 0xAF // A0,RD,WR:010 -#define DISPLAY_OFF 0xAE // A0,RD,WR:010 - -#define SET_START_LINE_0 0x40 // A0,RD,WR:010; line0~line63 -#define SET_PAGE_ADDR_0 0xB0 // A0,RD,WR:010; addr0~addr8 -#define SET_COLH_ADDR_0 0x10 // A0,RD,WR:010; -#define SET_COLL_ADDR_0 0x00 // A0,RD,WR:010; addr0~addr131 - -#define READ_STATUS 0x-0 // A0,RD,WR:001; BUSY | ADC | ON/OFF | RESET | 0 0 0 0 -#define STATUS_BUSY 0x80 -#define STATUS_ADC_REVERSE 0x40 // column address 131-n : SEG n, else column address n : SEG n -#define STATUS_DISPLAY_OFF 0x20 -#define STATUS_RESET 0x80 - -#define WRITE_DATA 0x-- // A0,RD,WR:110 -#define READ_DATE 0x-- // A0,RD,WR:101; spi mode is unavailable - -#define SET_ADC_NORMAL 0xA0 // A0,RD,WR:010 -#define SET_ADC_REVERSE 0xA1 // A0,RD,WR:010 -#define DISPLAY_NORMAL 0xA6 // A0,RD,WR:010 -#define DISPLAY_REVERSE 0xA7 // A0,RD,WR:010; reverse color -#define DISPLAY_ALL_ON 0xA5 // A0,RD,WR:010 -#define DISPLAY_ALL_NORMAL 0xA4 // A0,RD,WR:010 - -/************************************************************* -* bias: 1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty * -* ---------------|----------|----------|----------|--------- * -* A2: 1/9 bias | 1/8 bias | 1/6 bias | 1/8 bias | 1/8 bias * -* A3: 1/7 bias | 1/6 bias | 1/5 bias | 1/6 bias | 1/6 bias * -**************************************************************/ - -#define SET_LCD_BIAS_7 0xA3 // A0,RD,WR:010 -#define SET_LCD_BIAS_9 0xA2 // A0,RD,WR:010 - -#define RMW_MODE_ENABLE 0xE0 // A0,RD,WR:010; the column address locked when read command operating -#define RMW_MODE_END 0xEE // A0,RD,WR:010; returns to the column address when RMW was entered. -#define RESET_LCD 0xE2 // A0,RD,WR:010 - - -/************************************************************************************** -* Com Scan Dir: | 1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty * -* --------------|-------------|-------------|-------------|------------------------ * -* C0: Normal | COM0:COM63 | COM0:COM47 | COM0:COM31 | COM0:COM53 | COM0:COM51 * -* C8: Reverse | COM63:COM0 | COM47:COM0 | COM31:COM0 | COM53:COM0 | COM51:COM0 * -***************************************************************************************/ - -#define COM_SCAN_DIR_NORMAL 0xC0 // A0,RD,WR:010 -#define COM_SCAN_DIR_REVERSE 0xC8 // A0,RD,WR:010 - -// 0 0 1 0 1 | Booster On | Regulator On | Follower On -#define POWER_BOOSTER_ON 0x2C // A0,RD,WR:010 -#define POWER_REGULATOR_ON 0x2E // A0,RD,WR:010 -#define POWER_FOLLOWER_ON 0x2F // A0,RD,WR:010 - -#define SET_RESISTOR_RATIO 0x20 // A0,RD,WR:010; 20~27:small~large - -#define SET_ELECVOL_MODE 0x81 // A0,RD,WR:010; double byte command -#define SET_ELECVOL_REG 0x20 // A0,RD,WR:010; the electronic volume(64 voltage levels:00~3F) function is not used. - -#define SLEEP_MODE_ENABLE 0xAC // A0,RD,WR:010; double byte command, preceding command -#define SLEEP_MODE_DISABLE 0xAD // A0,RD,WR:010; preceding command -#define SLEEP_MODE_DELIVER 0x00 // A0,RD,WR:010; following command - -#define BOOST_RATIO_SET 0xF8 // A0,RD,WR:010; double byte command, preceding command -#define BOOST_RATIO_234 0x00 // A0,RD,WR:010; following command -#define BOOST_RATIO_5 0x01 // A0,RD,WR:010; following command -#define BOOST_RATIO_6 0x03 // A0,RD,WR:010; following command - -#define COMMAND_NOP 0xE3 // A0,RD,WR:010 -#define COMMAND_IC_TEST 0xFC // A0,RD,WR:010; don't use - -#define RT_DEVICE_CTRL_LCD_GET_WIDTH 0 -#define RT_DEVICE_CTRL_LCD_GET_HEIGHT 1 -#define RT_DEVICE_CTRL_LCD_GET_BPP 2 -#define RT_DEVICE_CTRL_LCD_GET_FRAMEBUFFER 3 -#define RT_DEVICE_CTRL_LCD_POWER_ON 4 -#define RT_DEVICE_CTRL_LCD_POWER_OFF 5 -#define RT_DEVICE_CTRL_LCD_CLEAR_SCR 6 -#define RT_DEVICE_CTRL_LCD_FILL_ALL 7 -#define RT_DEVICE_CTRL_LCD_UPDATE_POINT 8 -#define RT_DEVICE_CTRL_LCD_DISPLAY_ON 9 -#define RT_DEVICE_CTRL_LCD_DISPLAY_OFF 10 -#define RT_DEVICE_CTRL_LCD_PUT_STRING 11 - -enum -{ - ADC_MSG, - KEY_MSG, - CPU_MSG, - MAX_MSG, -}; - -struct lcd_msg -{ - rt_uint8_t type; - rt_uint16_t adc_value; - rt_uint8_t key; - rt_uint16_t major; - rt_uint16_t minor; -}; - -extern rt_uint32_t x; -extern rt_uint32_t y; - -void rt_hw_lcd_init(void); - -#endif diff --git a/bsp/fm3/mb9bf500r/led.c b/bsp/fm3/mb9bf500r/led.c deleted file mode 100644 index b72042d39e..0000000000 --- a/bsp/fm3/mb9bf500r/led.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * File : led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-03-03 lgnq - */ - -#include -#include - -#include "mb9bf506r.h" -#include "led.h" - -void rt_hw_led_on(rt_uint8_t num) -{ - RT_ASSERT(num < LEDS_MAX_NUMBER); - - switch (num) - { - case 1: - LED_PDOR &= ~LED1; - break; - case 2: - LED_PDOR &= ~LED2; - break; - case 3: - LED_PDOR &= ~LED3; - break; - default: - break; - } -} - -void rt_hw_led_off(rt_uint8_t num) -{ - RT_ASSERT(num < LEDS_MAX_NUMBER); - - switch (num) - { - case 1: - LED_PDOR |= LED1; - break; - case 2: - LED_PDOR |= LED2; - break; - case 3: - LED_PDOR |= LED3; - break; - default: - break; - } -} - -void rt_hw_led_toggle(rt_uint8_t num) -{ - RT_ASSERT(num < LEDS_MAX_NUMBER); - - switch (num) - { - case 1: - if (LED_PDOR&LED1) - LED_PDOR &= ~LED1; - else - LED_PDOR |= LED1; - break; - case 2: - if (LED_PDOR&LED2) - LED_PDOR &= ~LED2; - else - LED_PDOR |= LED2; - break; - case 3: - if (LED_PDOR&LED3) - LED_PDOR &= ~LED3; - else - LED_PDOR |= LED3; - break; - default: - break; - } -} - -static rt_err_t led_io_init(void) -{ - /*Select CPIO function*/ - LED_PFR &= ~LED_MASK; - /*Set Pin to turn off leds*/ - LED_PDOR |= LED_MASK; - /*Make led pins outputs*/ - LED_DDR |= LED_MASK; - - //LED3 is controled by PWM - FM3_GPIO->PFR3 = 0x1000; - FM3_GPIO->EPFR04 = 0x00080000; - FM3_BT2_PWM->TMCR = 0x0018; - FM3_BT2_PWM->TMCR2 = 0x01; /* cks=0b1000 count clk 1/512 */ - FM3_BT2_PWM->STC = 0x00; - FM3_BT2_PWM->PCSR = 0x61A; /* Down count = 1562 */ - FM3_BT2_PWM->PDUT = 0x0; /* Duty count = 16/1562=10% */ - - FM3_BT2_PWM->TMCR |= 0x03; /* start base timer(softwere TRG) */ - return RT_EOK; -} - -void pwm_update(rt_uint16_t value) -{ - FM3_BT2_PWM->PDUT = value; -} - -static void led1_thread_entry(void *parameter) -{ - while (1) - { - rt_hw_led_toggle(1); - rt_thread_delay(RT_TICK_PER_SECOND); - } -} - -static void led2_thread_entry(void *parameter) -{ - while (1) - { - rt_hw_led_toggle(2); - rt_thread_delay(RT_TICK_PER_SECOND/2); - } -} - -static rt_thread_t led1_thread; -static rt_thread_t led2_thread; -void rt_hw_led_init(void) -{ - led_io_init(); - - led1_thread = rt_thread_create("led1", led1_thread_entry, RT_NULL, 384, 29, 5); - if (led1_thread != RT_NULL) - rt_thread_startup(led1_thread); - - led2_thread = rt_thread_create("led2", led2_thread_entry, RT_NULL, 384, 30, 5); - if (led2_thread != RT_NULL) - rt_thread_startup(led2_thread); -} - - diff --git a/bsp/fm3/mb9bf500r/led.h b/bsp/fm3/mb9bf500r/led.h deleted file mode 100644 index 5610a09f71..0000000000 --- a/bsp/fm3/mb9bf500r/led.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-03-03 lgnq - */ - -#ifndef __LED_H__ -#define __LED_H__ - -#include "mb9bf506r.h" - -#define LEDS_MAX_NUMBER 4 - -/*LEDs*/ -#define LED1 (1UL<<10) -#define LED2 (1UL<<11) -#define LED3 (1UL<<12) -#define LED_MASK (LED1 | LED2 | LED3) - -#define LED_PFR (FM3_GPIO->PFR3) -#define LED_DDR (FM3_GPIO->DDR3) -#define LED_PDOR (FM3_GPIO->PDOR3) - -#define RT_DEVICE_CTRL_LED_ON 0 -#define RT_DEVICE_CTRL_LED_OFF 1 -#define RT_DEVICE_CTRL_LED_TOGGLE 2 - -void rt_hw_led_init(void); -void rt_hw_led_on(rt_uint8_t num); -void rt_hw_led_off(rt_uint8_t num); -void rt_hw_led_toggle(rt_uint8_t num); -void pwm_update(rt_uint16_t value); - -#endif diff --git a/bsp/fm3/mb9bf500r/mb9bf500r.icf b/bsp/fm3/mb9bf500r/mb9bf500r.icf deleted file mode 100644 index ff723823ce..0000000000 --- a/bsp/fm3/mb9bf500r/mb9bf500r.icf +++ /dev/null @@ -1,32 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x1FFFC000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x800; -define symbol __ICFEDIT_size_heap__ = 0x0; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; diff --git a/bsp/fm3/mb9bf500r/project.uvopt b/bsp/fm3/mb9bf500r/project.uvopt deleted file mode 100644 index 14f1a50e07..0000000000 --- a/bsp/fm3/mb9bf500r/project.uvopt +++ /dev/null @@ -1,586 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - - - - 0 - 0 - - - - RT-Thread FM3 - 0x4 - ARM-ADS - - 4000000 - - 1 - 1 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\obj\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM3 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM3 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 0 - 0 - 7 - - - - - - - - - - - Segger\JL2CM3.dll - - - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - Startup - 0 - 0 - 0 - - 1 - 1 - 1 - 0 - 0 - 43 - 0 - 121 - 121 - 0 - .\application.c - application.c - - - 1 - 2 - 1 - 0 - 0 - 20 - 0 - 32 - 34 - 0 - .\board.c - board.c - - - 1 - 3 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\startup.c - startup.c - - - 1 - 4 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\adc.c - adc.c - - - 1 - 5 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\cpuusage.c - cpuusage.c - - - 1 - 6 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\key.c - key.c - - - 1 - 7 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\lcd.c - lcd.c - - - 1 - 8 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\led.c - led.c - - - 1 - 9 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - .\info.c - info.c - - - - - FM3 - 0 - 0 - 0 - - 2 - 10 - 2 - 0 - 0 - 7 - 0 - 116 - 116 - 0 - ..\..\..\libcpu\arm\cortex-m3\context_rvds.S - context_rvds.S - - - 2 - 11 - 1 - 0 - 0 - 22 - 0 - 1 - 1 - 0 - ..\..\..\libcpu\arm\cortex-m3\cpuport.c - cpuport.c - - - - - CMSIS - 0 - 0 - 0 - - 3 - 12 - 1 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - ..\CMSIS\core_cm3.c - core_cm3.c - - - 3 - 13 - 1 - 0 - 0 - 0 - 0 - 1 - 1 - 0 - ..\CMSIS\system_mb9bf50x.c - system_mb9bf50x.c - - - 3 - 14 - 2 - 0 - 0 - 39 - 0 - 47 - 61 - 0 - ..\CMSIS\start_rvds.S - start_rvds.S - - - - - Kernel - 0 - 0 - 0 - - 4 - 15 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\clock.c - clock.c - - - 4 - 16 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\device.c - device.c - - - 4 - 17 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\idle.c - idle.c - - - 4 - 18 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\ipc.c - ipc.c - - - 4 - 19 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\irq.c - irq.c - - - 4 - 20 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\kservice.c - kservice.c - - - 4 - 21 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\mem.c - mem.c - - - 4 - 22 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\mempool.c - mempool.c - - - 4 - 23 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\module.c - module.c - - - 4 - 24 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\object.c - object.c - - - 4 - 25 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\rtm.c - rtm.c - - - 4 - 26 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\scheduler.c - scheduler.c - - - 4 - 27 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\slab.c - slab.c - - - 4 - 28 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\thread.c - thread.c - - - 4 - 29 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - ..\..\..\src\timer.c - timer.c - - - - diff --git a/bsp/fm3/mb9bf500r/project.uvproj b/bsp/fm3/mb9bf500r/project.uvproj deleted file mode 100644 index 50781e7cdb..0000000000 --- a/bsp/fm3/mb9bf500r/project.uvproj +++ /dev/null @@ -1,555 +0,0 @@ - - - - 1.1 - -
### uVision Project, (C) Keil Software
- - - - RT-Thread FM3 - 0x4 - ARM-ADS - - - MB9BF500R - Fujitsu Semiconductors - IRAM(0x20000000-0x20003FFF) IROM(0x00000000-0x0003FFFF) CLOCK(4000000) CPUTYPE("Cortex-M3") - - "STARTUP\FUJITSU\MB9BF50x\startup_MB9BF50x.s" ("Fujitsu MB9BF50x Startup Code") - UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BF50x_256 -FS00 -FL040000) - 5155 - MB9BF50x.h - - - - - - - - - - - 0 - - - - Fujitsu\MB9BF50x\ - Fujitsu\MB9BF50x\ - - 0 - 0 - 0 - 0 - 1 - - .\obj\ - rtthread-fm3 - 1 - 0 - 0 - 1 - 1 - .\obj\ - 1 - 0 - 0 - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - - 0 - 0 - - 0 - - - - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 3 - - - - - SARMCM3.DLL - -MPU - DCM.DLL - -pCM3 - SARMCM3.DLL - -MPU - TCM.DLL - -pCM3 - - - - 1 - 0 - 0 - 0 - 16 - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - - 0 - 7 - - - - - - - - - - - - - - Segger\JL2CM3.dll - - - - - 1 - 0 - 0 - 1 - 1 - 4099 - - Segger\JL2CM3.dll - "" () - - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - "Cortex-M3" - - 0 - 0 - 0 - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 8 - 1 - 0 - 0 - 3 - 3 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 1 - 0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x4000 - - - 1 - 0x0 - 0x40000 - - - 0 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x0 - - - 1 - 0x0 - 0x40000 - - - 1 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x0 - 0x0 - - - 0 - 0x20000000 - 0x4000 - - - 0 - 0x0 - 0x0 - - - - - - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - ..\CMSIS;.;..\..\..\libcpu\arm\fm3;..\..\..\include;..\..\..\components\rtgui\include - - - - 1 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - - - 1 - 0 - 0 - 0 - 1 - 0 - 0x00000000 - 0x10000000 - - - - - - - - - - - - Startup - - - application.c - 1 - .\application.c - - - board.c - 1 - .\board.c - - - startup.c - 1 - .\startup.c - - - adc.c - 1 - .\adc.c - - - cpuusage.c - 1 - .\cpuusage.c - - - key.c - 1 - .\key.c - - - lcd.c - 1 - .\lcd.c - - - led.c - 1 - .\led.c - - - info.c - 1 - .\info.c - - - - - FM3 - - - context_rvds.S - 2 - ..\..\..\libcpu\arm\cortex-m3\context_rvds.S - - - cpuport.c - 1 - ..\..\..\libcpu\arm\cortex-m3\cpuport.c - - - - - CMSIS - - - core_cm3.c - 1 - ..\CMSIS\core_cm3.c - - - system_mb9bf50x.c - 1 - ..\CMSIS\system_mb9bf50x.c - - - start_rvds.S - 2 - ..\CMSIS\start_rvds.S - - - - - Kernel - - - clock.c - 1 - ..\..\..\src\clock.c - - - device.c - 1 - ..\..\..\src\device.c - - - idle.c - 1 - ..\..\..\src\idle.c - - - ipc.c - 1 - ..\..\..\src\ipc.c - - - irq.c - 1 - ..\..\..\src\irq.c - - - kservice.c - 1 - ..\..\..\src\kservice.c - - - mem.c - 1 - ..\..\..\src\mem.c - - - mempool.c - 1 - ..\..\..\src\mempool.c - - - module.c - 1 - ..\..\..\src\module.c - - - object.c - 1 - ..\..\..\src\object.c - - - rtm.c - 1 - ..\..\..\src\rtm.c - - - scheduler.c - 1 - ..\..\..\src\scheduler.c - - - slab.c - 1 - ..\..\..\src\slab.c - - - thread.c - 1 - ..\..\..\src\thread.c - - - timer.c - 1 - ..\..\..\src\timer.c - - - - - - - - diff --git a/bsp/fm3/mb9bf500r/rtconfig.h b/bsp/fm3/mb9bf500r/rtconfig.h deleted file mode 100644 index d1937e3a2a..0000000000 --- a/bsp/fm3/mb9bf500r/rtconfig.h +++ /dev/null @@ -1,88 +0,0 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ - -/* RT_NAME_MAX*/ -#define RT_NAME_MAX 4 - -/* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 4 - -/* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 - -/* Tick per Second */ -#define RT_TICK_PER_SECOND 100 - -/* SECTION: RT_DEBUG */ -/* Thread Debug */ -/* #define RT_DEBUG */ -#define RT_USING_OVERFLOW_CHECK - -/* Using Hook */ -#define RT_USING_HOOK - -/* SECTION: IPC */ -/* Using Semaphore */ -#define RT_USING_SEMAPHORE - -/* Using Mutex */ -#define RT_USING_MUTEX - -/* Using Event */ -#define RT_USING_EVENT - -/* Using MailBox */ -#define RT_USING_MAILBOX - -/* Using Message Queue */ -#define RT_USING_MESSAGEQUEUE - -/* SECTION: Memory Management */ -/* Using Memory Pool Management*/ -#define RT_USING_MEMPOOL - -/* Using Dynamic Heap Management */ -#define RT_USING_HEAP - -/* Using Small MM */ -#define RT_USING_SMALL_MEM - -/* SECTION: Device System */ -/* Using Device System */ -#define RT_USING_DEVICE -/* RT_USING_UART */ -#define RT_USING_UART0 -#define RT_UART_RX_BUFFER_SIZE 64 - -/* SECTION: Console options */ -#define RT_TINY_SIZE -#define RT_USING_CONSOLE -/* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 - -/* SECTION: RTGUI support */ -/* using RTGUI support */ -/* #define RT_USING_RTGUI */ - -/* name length of RTGUI object */ -#define RTGUI_NAME_MAX 16 -/* support 16 weight font */ -//#define RTGUI_USING_FONT16 -/* support 12 weight font */ -#define RTGUI_USING_FONT12 -/* support Chinese font */ -//#define RTGUI_USING_FONTHZ -/* use DFS as file interface */ -//#define RTGUI_USING_DFS_FILERW -/* use font file as Chinese font */ -/* #define RTGUI_USING_HZ_FILE */ -/* use Chinese bitmap font */ -//#define RTGUI_USING_HZ_BMP -/* use small size in RTGUI */ -//#define RTGUI_USING_SMALL_SIZE -/* use mouse cursor */ -/* #define RTGUI_USING_MOUSE_CURSOR */ -#define RTGUI_DEFAULT_FONT_SIZE 12 - -#endif diff --git a/bsp/fm3/mb9bf500r/rtconfig.py b/bsp/fm3/mb9bf500r/rtconfig.py deleted file mode 100644 index 6446b1b0cd..0000000000 --- a/bsp/fm3/mb9bf500r/rtconfig.py +++ /dev/null @@ -1,114 +0,0 @@ -# toolchains options -ARCH='arm' -CPU='cortex-m3' -CROSS_TOOL='iar' - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR - -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = 'C:/Keil' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iar' - IAR_PATH = 'C:\Program Files\IAR Systems\Embedded Workbench 6.0 Evaluation' - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'axf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' - CFLAGS = DEVICE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-fm3.map,-cref,-u,Reset_Handler -T fm3_rom.ld' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' - -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --device DARMSTM' - CFLAGS = DEVICE + ' --apcs=interwork' - AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-fm3.map --scatter fm3_rom.sct' - - CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' - - EXEC_PATH += '/arm/bin40/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iar': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - CFLAGS = '' - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --debug' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M3' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' -Ol' - CFLAGS += ' --use_c++_inline' - - AFLAGS = '' - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M3' - AFLAGS += ' --fpu None' - AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"' - - LFLAGS = ' --config mb9bf500r.icf' - LFLAGS += ' --semihosting' - LFLAGS += ' --entry __iar_program_start' - - EXEC_PATH = IAR_PATH + '/arm/bin/' - POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' diff --git a/bsp/fm3/mb9bf500r/startup.c b/bsp/fm3/mb9bf500r/startup.c deleted file mode 100644 index f74c60bc5c..0000000000 --- a/bsp/fm3/mb9bf500r/startup.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-02-24 Bernard first implementation - */ - -#include -#include - -#include "board.h" -#include "mb9bf506r.h" -/** - * @addtogroup FM3 - */ - -/*@{*/ - -extern int rt_application_init(void); - -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#elif __ICCARM__ -#pragma section="HEAP" -#else -extern int __bss_end; -#endif - -/** - * This function will startup RT-Thread RTOS. - */ -void rtthread_startup(void) -{ - /* init board */ - rt_hw_board_init(); - - /* show version */ - rt_show_version(); - - /* init tick */ - rt_system_tick_init(); - - /* init kernel object */ - rt_system_object_init(); - - /* init timer system */ - rt_system_timer_init(); - -#ifdef RT_USING_HEAP - #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); - #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); - #else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); - #endif -#endif - - /* init scheduler system */ - rt_system_scheduler_init(); - -#ifdef RT_USING_DEVICE - /* init all device */ - rt_device_init_all(); -#endif - - /* init application */ - rt_application_init(); - - /* init timer thread */ - rt_system_timer_thread_init(); - - /* init idle thread */ - rt_thread_idle_init(); - - /* start scheduler */ - rt_system_scheduler_start(); - - /* never reach here */ - return ; -} - -int main(void) -{ - rt_uint32_t UNUSED level; - - /* disable interrupt first */ - level = rt_hw_interrupt_disable(); - - /* init system setting */ - SystemInit(); - - /* startup RT-Thread RTOS */ - rtthread_startup(); - - return 0; -} - -/*@}*/ diff --git a/bsp/fm3/mb9bf506r/SConscript b/bsp/fm3/mb9bf506r/SConscript deleted file mode 100644 index d09b858deb..0000000000 --- a/bsp/fm3/mb9bf506r/SConscript +++ /dev/null @@ -1,16 +0,0 @@ -import rtconfig -Import('RTT_ROOT') -from building import * - -src_bsp = ['application.c', 'startup.c', 'board.c', 'led.c', 'console.c'] -src_drv = ['serial.c', 'nand.c'] - -if GetDepend('RT_USING_RTGUI'): - src_drv += ['info.c'] - -src = src_bsp + src_drv -CPPPATH = [GetCurrentDir()] -CPPDEFINES = [] -group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) - -Return('group') diff --git a/bsp/fm3/mb9bf506r/SConstruct b/bsp/fm3/mb9bf506r/SConstruct deleted file mode 100644 index 1fac2c8cd8..0000000000 --- a/bsp/fm3/mb9bf506r/SConstruct +++ /dev/null @@ -1,39 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -from building import * - -TARGET = 'rtthread.' + rtconfig.TARGET_EXT - -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -if rtconfig.PLATFORM == 'iar': - env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) - env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map']) - env.Replace(ARFLAGS = '') - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT) - -objs = objs + SConscript('../CMSIS/SConscript', variant_dir='build/bsp/Libraries', duplicate=0) - -# build program -env.Program(TARGET, objs) - -# end building -EndBuilding(TARGET) diff --git a/bsp/fm3/mb9bf506r/application.c b/bsp/fm3/mb9bf506r/application.c deleted file mode 100644 index 94ffe4819d..0000000000 --- a/bsp/fm3/mb9bf506r/application.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-05-24 Bernard the first version - */ - -/** - * @addtogroup FM3 - */ -/*@{*/ - -#include -#include "board.h" -#include "led.h" - -#ifdef RT_USING_DFS -/* dfs init */ -#include -/* dfs filesystem:ELM filesystem init */ -#include -/* dfs Filesystem APIs */ -#include -#endif - -void rt_init_thread_entry(void *parameter) -{ - /* Filesystem Initialization */ -#ifdef RT_USING_DFS - { - /* init the device filesystem */ - dfs_init(); - -#ifdef RT_USING_DFS_ELMFAT - /* init the elm chan FatFs filesystam*/ - elm_init(); - - /* mount ELM FatFs on NAND flash as root directory */ - if (dfs_mount("nand", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!\n"); -#endif - } -#endif - /* LED Initialization */ - rt_hw_led_init(); -} - -int rt_application_init() -{ - rt_thread_t tid; - - tid = rt_thread_create("init", - rt_init_thread_entry, RT_NULL, - 2048, 8, 20); - if (tid != RT_NULL) rt_thread_startup(tid); - - return 0; -} - -/*@}*/ diff --git a/bsp/fm3/mb9bf506r/board.c b/bsp/fm3/mb9bf506r/board.c deleted file mode 100644 index bd2f27d1ef..0000000000 --- a/bsp/fm3/mb9bf506r/board.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-02-24 Bernard first implementation - */ - -#include -#include - -#include "board.h" -#include "mb9bf506r.h" - -#include "serial.h" -#include "nand.h" - -extern const uint32_t SystemFrequency; - -/** - * @addtogroup FM3 - */ - -/*@{*/ - -/** - * This is the timer interrupt service routine. - * - */ -void SysTick_Handler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -/** -* This function will initial FM3 Easy Kit board. - */ -void rt_hw_board_init() -{ - /* init systick */ - SysTick_Config(SystemFrequency/RT_TICK_PER_SECOND); - - /* initialize UART device */ - rt_hw_serial_init(); - /* set console as UART device */ - rt_console_set_device("uart2"); - - /* initialize nand flash device */ - rt_hw_nand_init(); -} - -/*@}*/ diff --git a/bsp/fm3/mb9bf506r/board.h b/bsp/fm3/mb9bf506r/board.h deleted file mode 100644 index b96f8a167a..0000000000 --- a/bsp/fm3/mb9bf506r/board.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2009-09-22 Bernard add board.h to this bsp - * 2011-03-04 lgnq add board.h to FM3 bsp - */ - -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include "serial.h" - -//Internal SRAM memory size[Kbytes] <8-64> -//MB9BF500 : 32 -//MB9BF504 : 32 -//MB9BF505 : 48 -//MB9BF506 : 64 -#define FM3_SRAM_SIZE 64 -#define FM3_SRAM_END (0x1FFF8000 + FM3_SRAM_SIZE * 1024) - -void rt_hw_board_init(void); - -#endif diff --git a/bsp/fm3/mb9bf506r/console.c b/bsp/fm3/mb9bf506r/console.c deleted file mode 100644 index 084a7d6a08..0000000000 --- a/bsp/fm3/mb9bf506r/console.c +++ /dev/null @@ -1,180 +0,0 @@ -#include - -#include - -#define RT_CONSOLE_WIDTH 240 -#define RT_CONSOLE_HEIGHT 320 - -#define RT_CONSOLE_FONT_WIDTH 8 -#define RT_CONSOLE_FONT_HEIGHT 16 - -#define RT_CONSOLE_COL (RT_CONSOLE_WIDTH/RT_CONSOLE_FONT_WIDTH) -#define RT_CONSOLE_ROW (RT_CONSOLE_HEIGHT/RT_CONSOLE_FONT_HEIGHT) - -#define RT_CONSOLE_TAB 4 - -#define RT_CONSOLE_FOREPIXEL (0x001f) - -extern struct serial_device uart2; - -struct rt_console -{ - rt_uint8_t* video_ptr; - rt_uint8_t* font_ptr; - - /* bpp and pixel of width */ - rt_uint8_t bpp; - rt_uint32_t pitch; - - /* current cursor */ - rt_uint8_t current_col; - rt_uint8_t current_row; -}; -struct rt_console console; - -void rt_hw_console_init(rt_uint8_t* video_ptr, rt_uint8_t* font_ptr, rt_uint8_t bpp); -void rt_hw_console_newline(void); -void rt_hw_console_putc(char c); -void rt_hw_console_clear(void); - -void rt_hw_console_init(rt_uint8_t* video_ptr, rt_uint8_t* font_ptr, rt_uint8_t bpp) -{ - rt_memset(&console, 0, sizeof(struct rt_console)); - - console.video_ptr = video_ptr; - console.font_ptr = font_ptr; - console.bpp = bpp; - console.pitch = console.bpp * RT_CONSOLE_WIDTH; - - rt_hw_console_clear(); -} - -void rt_hw_console_putc(char c) -{ - switch (c) - { - case 10: - case 11: - case 12: - case 13: - /* to next line */ - rt_hw_console_newline(); - console.current_col = 0; - break; - - case 9: - console.current_col += RT_CONSOLE_TAB; - break; - - default: - { - rt_uint8_t* font_ptr; - register rt_uint32_t cursor; - register rt_uint32_t i, j; - - if (console.current_col == RT_CONSOLE_COL) - { - rt_hw_console_newline(); - console.current_col = 0; - - rt_hw_console_putc(c); - return; - } - - font_ptr = console.font_ptr + c * RT_CONSOLE_FONT_HEIGHT; - cursor = (console.current_row * RT_CONSOLE_FONT_HEIGHT) * console.pitch - + console.current_col * RT_CONSOLE_FONT_WIDTH * console.bpp; - - for (i = 0; i < RT_CONSOLE_FONT_HEIGHT; i ++ ) - { - for (j = 0; j < RT_CONSOLE_FONT_WIDTH; j ++) - { - if ( ((font_ptr[i] >> (7-j)) & 0x01) != 0 ) - { - /* draw a pixel */ - rt_uint8_t *ptr = &(console.video_ptr[cursor + i * console.pitch + j * console.bpp]); - switch(console.bpp) - { - case 1: - *ptr = RT_CONSOLE_FOREPIXEL; - break; - case 2: - *(rt_uint16_t*)ptr = RT_CONSOLE_FOREPIXEL; - break; - case 3: - ptr[0] = RT_CONSOLE_FOREPIXEL & 0xff; - ptr[1] = (RT_CONSOLE_FOREPIXEL >> 8) & 0xff; - ptr[2] = (RT_CONSOLE_FOREPIXEL >> 16) & 0xff; - break; - case 4: - *(rt_uint32_t*)ptr = RT_CONSOLE_FOREPIXEL; - break; - } - } - } - } - - console.current_col ++; - } - break; - } -} - -void rt_hw_console_newline() -{ - console.current_row ++; - if (console.current_row >= RT_CONSOLE_ROW) - { - rt_uint32_t i; - - /* scroll to next line */ - for (i = 0; i < RT_CONSOLE_ROW - 1; i ++) - { - rt_memcpy(console.video_ptr + i * RT_CONSOLE_FONT_HEIGHT * console.pitch, - console.video_ptr + (i + 1) * RT_CONSOLE_FONT_HEIGHT * console.pitch, - RT_CONSOLE_FONT_HEIGHT * console.pitch); - } - - /* clear last line */ - rt_memset(console.video_ptr + (RT_CONSOLE_ROW - 1) * RT_CONSOLE_FONT_HEIGHT * console.pitch, - 0, - RT_CONSOLE_FONT_HEIGHT * console.pitch); - - console.current_row = RT_CONSOLE_ROW - 1; - } -} - -void rt_hw_console_clear() -{ - console.current_col = 0; - console.current_row = 0; - - rt_memset(console.video_ptr, 0, RT_CONSOLE_HEIGHT * console.pitch); -} - -/* write one character to serial, must not trigger interrupt */ -void rt_hw_serial_putc(const char c) -{ - /* - to be polite with serial console add a line feed - to the carriage return character - */ - if (c=='\n')rt_hw_serial_putc('\r'); - - while (!(uart2.uart_device->SSR & SSR_TDRE)); - uart2.uart_device->TDR = (c & 0x1FF); -} - -/** - * This function is used by rt_kprintf to display a string on console. - * - * @param str the displayed string - */ -void rt_hw_console_output(const char* str) -{ - while (*str) - { - rt_hw_serial_putc(*str++); - } -} - diff --git a/bsp/fm3/mb9bf506r/fm3_easy_kit.ewp b/bsp/fm3/mb9bf506r/fm3_easy_kit.ewp deleted file mode 100644 index c0897412c9..0000000000 --- a/bsp/fm3/mb9bf506r/fm3_easy_kit.ewp +++ /dev/null @@ -1,1897 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 20 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 26 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 11 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 20 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 26 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 8 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 11 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - CMSIS - - $PROJ_DIR$\..\CMSIS\core_cm3.c - - - $PROJ_DIR$\..\CMSIS\start_iar.S - - - $PROJ_DIR$\..\CMSIS\system_mb9bf50x.c - - - - Filesystem - - $PROJ_DIR$\..\..\..\components\dfs\src\dfs.c - - - $PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\dfs_elm.c - - - $PROJ_DIR$\..\..\..\components\dfs\src\dfs_file.c - - - $PROJ_DIR$\..\..\..\components\dfs\src\dfs_fs.c - - - $PROJ_DIR$\..\..\..\components\dfs\src\dfs_posix.c - - - $PROJ_DIR$\..\..\..\components\dfs\filesystems\elmfat\ff.c - - - - Finsh - - $PROJ_DIR$\..\..\..\components\finsh\cmd.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_compiler.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_error.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_heap.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_init.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_node.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_ops.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_parser.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_token.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_var.c - - - $PROJ_DIR$\..\..\..\components\finsh\finsh_vm.c - - - $PROJ_DIR$\..\..\..\components\finsh\shell.c - - - $PROJ_DIR$\..\..\..\components\finsh\symbol.c - - - - FM3 - - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m3\context_iar.S - - - $PROJ_DIR$\..\..\..\libcpu\arm\cortex-m3\cpuport.c - - - - Kernel - - $PROJ_DIR$\..\..\..\src\clock.c - - - $PROJ_DIR$\..\..\..\src\device.c - - - $PROJ_DIR$\..\..\..\src\idle.c - - - $PROJ_DIR$\..\..\..\src\ipc.c - - - $PROJ_DIR$\..\..\..\src\irq.c - - - $PROJ_DIR$\..\..\..\src\kservice.c - - - $PROJ_DIR$\..\..\..\src\mem.c - - - $PROJ_DIR$\..\..\..\src\mempool.c - - - $PROJ_DIR$\..\..\..\src\module.c - - - $PROJ_DIR$\..\..\..\src\object.c - - - $PROJ_DIR$\..\..\..\src\rtm.c - - - $PROJ_DIR$\..\..\..\src\scheduler.c - - - $PROJ_DIR$\..\..\..\src\slab.c - - - $PROJ_DIR$\..\..\..\src\thread.c - - - $PROJ_DIR$\..\..\..\src\timer.c - - - - Startup - - $PROJ_DIR$\application.c - - - $PROJ_DIR$\board.c - - - $PROJ_DIR$\led.c - - - $PROJ_DIR$\nand.c - - - $PROJ_DIR$\serial.c - - - $PROJ_DIR$\startup.c - - - - - diff --git a/bsp/fm3/mb9bf506r/fm3_easy_kit.eww b/bsp/fm3/mb9bf506r/fm3_easy_kit.eww deleted file mode 100644 index bdaf802ebd..0000000000 --- a/bsp/fm3/mb9bf506r/fm3_easy_kit.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\fm3_easy_kit.ewp - - - - - diff --git a/bsp/fm3/mb9bf506r/fm3_rom.ld b/bsp/fm3/mb9bf506r/fm3_rom.ld deleted file mode 100644 index dc9f4c02b6..0000000000 --- a/bsp/fm3/mb9bf506r/fm3_rom.ld +++ /dev/null @@ -1,122 +0,0 @@ -/* Program Entry, set to mark it as "used" and avoid gc */ -MEMORY -{ - CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 - DATA (rw) : ORIGIN = 0x1FFFC000, LENGTH = 0x00010000 -} -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - . = ALIGN(4); - KEEP(*(.isr_vector)) /* Startup code */ - . = ALIGN(4); - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - _etext = .; - } > CODE = 0 - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - - /* This is used by the startup in order to initialize the .data secion */ - _sidata = .; - } > CODE - __exidx_end = .; - - /* .data section which is used for initialized data */ - - .data : AT (_sidata) - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _sdata = . ; - - *(.data) - *(.data.*) - *(.gnu.linkonce.d*) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .data secion */ - _edata = . ; - } >DATA - - __bss_start = .; - .bss : - { - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _sbss = .; - - *(.bss) - *(.bss.*) - *(COMMON) - - . = ALIGN(4); - /* This is used by the startup in order to initialize the .bss secion */ - _ebss = . ; - _estack = .; - - *(.bss.init) - } > DATA - __bss_end = .; - - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/bsp/fm3/mb9bf506r/led.c b/bsp/fm3/mb9bf506r/led.c deleted file mode 100644 index a1ab6a0592..0000000000 --- a/bsp/fm3/mb9bf506r/led.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - * File : led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-03-03 lgnq - */ - -#include -#include - -#include "mb9bf506r.h" -#include "led.h" - -void rt_hw_led_on(rt_uint8_t num) -{ - RT_ASSERT(num < LEDS_MAX_NUMBER); - - switch (num) - { - case 1: - USER_LED_PDOR &= ~USER_LED1; - break; - case 2: - USER_LED_PDOR &= ~USER_LED2; - break; - case 3: - USER_LED_PDOR &= ~USER_LED3; - break; - default: - break; - } -} - -void rt_hw_led_off(rt_uint8_t num) -{ - RT_ASSERT(num < LEDS_MAX_NUMBER); - - switch (num) - { - case 1: - USER_LED_PDOR |= USER_LED1; - break; - case 2: - USER_LED_PDOR |= USER_LED2; - break; - case 3: - USER_LED_PDOR |= USER_LED3; - break; - default: - break; - } -} - -void rt_hw_led_toggle(rt_uint8_t num) -{ - RT_ASSERT(num < LEDS_MAX_NUMBER); - - switch (num) - { - case 1: - if (USER_LED_PDOR&USER_LED1) - USER_LED_PDOR &= ~USER_LED1; - else - USER_LED_PDOR |= USER_LED1; - break; - case 2: - if (USER_LED_PDOR&USER_LED2) - USER_LED_PDOR &= ~USER_LED2; - else - USER_LED_PDOR |= USER_LED2; - break; - case 3: - if (USER_LED_PDOR&USER_LED3) - USER_LED_PDOR &= ~USER_LED3; - else - USER_LED_PDOR |= USER_LED3; - break; - default: - break; - } -} - -void led_init(void) -{ - /*Select CPIO function*/ - USER_LED_PFR &= ~USER_LED_MASK; - /* disable analog input */ - FM3_GPIO->ADE &= ~USER_LED_MASK; - /*Set CPIO Pull-Up function*/ - USER_LED_PCR |= USER_LED_MASK; - /*Make led pins outputs*/ - USER_LED_DDR |= USER_LED_MASK; - USER_LED_PDOR |= USER_LED_MASK; -} - -void pwm_update(rt_uint16_t value) -{ - FM3_BT2_PWM->PDUT = value; -} - -static void led1_thread_entry(void *parameter) -{ - while (1) - { - rt_hw_led_toggle(1); - rt_thread_delay(RT_TICK_PER_SECOND); - } -} - -static void led2_thread_entry(void *parameter) -{ - while (1) - { - rt_hw_led_toggle(2); - rt_thread_delay(RT_TICK_PER_SECOND/2); - } -} - -static rt_thread_t led1_thread; -static rt_thread_t led2_thread; -void rt_hw_led_init(void) -{ - led_init(); - - led1_thread = rt_thread_create("led1", led1_thread_entry, RT_NULL, 384, 29, 5); - if (led1_thread != RT_NULL) - rt_thread_startup(led1_thread); - - led2_thread = rt_thread_create("led2", led2_thread_entry, RT_NULL, 384, 30, 5); - if (led2_thread != RT_NULL) - rt_thread_startup(led2_thread); -} - - diff --git a/bsp/fm3/mb9bf506r/led.h b/bsp/fm3/mb9bf506r/led.h deleted file mode 100644 index 5db0980520..0000000000 --- a/bsp/fm3/mb9bf506r/led.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2011, RT-Thread Develop Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-03-03 lgnq - */ - -#ifndef __LED_H__ -#define __LED_H__ - -#include "mb9bf506r.h" - -#define LEDS_MAX_NUMBER 4 - -/* LED */ -#define USER_LED1 (1UL<<0x9) -#define USER_LED2 (1UL<<0xa) -#define USER_LED3 (1UL<<0xb) - -#define USER_LED_MASK (USER_LED1 | USER_LED2 | USER_LED3) -#define USER_LED_PFR FM3_GPIO->PFR1 -#define USER_LED_PCR FM3_GPIO->PCR1 -#define USER_LED_PDOR FM3_GPIO->PDOR1 -#define USER_LED_DDR FM3_GPIO->DDR1 - -#define RT_DEVICE_CTRL_LED_ON 0 -#define RT_DEVICE_CTRL_LED_OFF 1 -#define RT_DEVICE_CTRL_LED_TOGGLE 2 - -void rt_hw_led_init(void); -void rt_hw_led_on(rt_uint8_t num); -void rt_hw_led_off(rt_uint8_t num); -void rt_hw_led_toggle(rt_uint8_t num); -void pwm_update(rt_uint16_t value); - -#endif diff --git a/bsp/fm3/mb9bf506r/mb9bf506.icf b/bsp/fm3/mb9bf506r/mb9bf506.icf deleted file mode 100644 index 63518e1ee9..0000000000 --- a/bsp/fm3/mb9bf506r/mb9bf506.icf +++ /dev/null @@ -1,33 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x1FFF8000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = 0x400; -define symbol __ICFEDIT_size_heap__ = 0; -/**** End of ICF editor section. ###ICF###*/ - - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section FSymTab }; -keep { section VSymTab }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; - -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/fm3/mb9bf506r/nand.c b/bsp/fm3/mb9bf506r/nand.c deleted file mode 100644 index ada61e3f92..0000000000 --- a/bsp/fm3/mb9bf506r/nand.c +++ /dev/null @@ -1,667 +0,0 @@ -/* - * File : nand.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-05-25 Bernard first version - */ - -#include "nand.h" -#include "mb9bf506r.h" - -/* - * NandFlash driver for SamSung K9F5608 - * 32M x 8bit - */ -#define PAGE_SIZE 512 -#define PAGE_PER_BLOCK 32 -#define BLOCK_NUM 2048 - -/* device driver debug trace */ -/* #define NAND_DEBUG */ -#ifdef NAND_DEBUG -#define trace_log rt_kprintf -#else -#define trace_log(...) -#endif - -/* - * OOB, - * when block has been erased, OOB is 0xff. - * when block has been written, OOB is 0x00. - */ -struct rt_device_nand -{ - struct rt_device parent; /* which is inherited from rt_device */ - - rt_uint16_t block_num; /* total block number in device */ - rt_uint16_t page_per_block; /* pages in one block */ - rt_uint16_t page_size; /* page size */ - - /* this buffer which used as to save data before erase block */ - rt_uint8_t block_buffer[PAGE_SIZE * PAGE_PER_BLOCK]; -}; -static struct rt_device_nand _nand; - -/* Flash operation definition */ -#define NF_CMD(cmd) {*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_CMD_OFFSET) = (unsigned char)(cmd);} -#define NF_ADDR(addr) {*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_ADDR_OFFSET)= (unsigned char)(addr);} -#define NF_RDDATA() (*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_DATA_OFFSET)) -#define NF_WRDATA(data) {*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_DATA_OFFSET)= (unsigned char)(data);} -#define NF_CLR_ALE() {*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_ALE_OFFSET) = (unsigned char)0;} - -/* Flash Control IO definition */ -#define NF_OE_H() {IO_NF_PDOR |= NF_EN;} -#define NF_OE_L() {IO_NF_PDOR &= ~NF_EN;} - -#define NF_DATA_OUT() {IO_NF_PDOR &= ~NF_DATA_DIR;} -#define NF_DATA_IN() {IO_NF_PDOR |= NF_DATA_DIR;} - -static unsigned char NF_ReadStatus(void); -static void Wait(unsigned int cnt); -static void NF_Reset(void); - -static void Wait(unsigned int cnt) -{ - while(cnt--); -} - -static void NF_Reset(void) -{ - NF_OE_L(); - NF_DATA_OUT(); - NF_CMD(NAND_CMD_RESET); - NF_OE_H(); - - Wait(10000); /* wait for Trst */ -} - -static unsigned char NF_ReadStatus(void) -{ - unsigned int timeout=0; - NF_DATA_OUT(); - NF_CMD(NAND_CMD_STATUS); - NF_DATA_IN(); - - while(!(NF_RDDATA() & 0x40)) - { - timeout++; - if(timeout == 0x00080000) - return FLASH_NG; - } - if(NF_RDDATA() & 0x01)return FLASH_NG; - - return FLASH_OK; -} - -/* - * @ Funciton: NF_Init - * Parameter: None - * Return: None - */ -static void NF_Init(void) -{ - FM3_GPIO->PFR5 |= (0x7ff); /* D0-D5, CS7, ALE, CLE, WEX, REX */ - FM3_GPIO->PFR3 |= (0x3); /* D6-D7 */ - FM3_GPIO->EPFR10 |= (1<<13 /* CS enable */ - |1<<6 /* ALE, CLE, WEX, REX enable */ - |1<<0); /* D0-D7 enable */ - FM3_EXBUS->AREA7 = 0x001f00e0; /* Select CS7 area, 32Mbyte size */ - FM3_EXBUS->MODE7 |= (1<<4); /* Nand Flash mode turn on, set 8 bit width */ - - IO_NF_PFR = IO_NF_PFR & ~(NF_EN|NF_DATA_DIR); - IO_NF_DDR = IO_NF_DDR | (NF_EN|NF_DATA_DIR); - IO_NF_PDOR = IO_NF_PDOR | (NF_EN | NF_DATA_DIR); /* disable Flash operation */ - - /*Reset NAND*/ - NF_Reset(); -} - -static void NF_UnInit(void) -{ - FM3_GPIO->PFR5 &= ~(0x7ff); /* disable D0-D5, CS7, ALE, CLE, WEX, REX */ - FM3_GPIO->PFR3 &= ~(0x3); /* disable D6-D7 */ - FM3_GPIO->EPFR10 &= ~(1<<13 /* disable CS enable */ - |1<<6 /* disable ALE, CLE, WEX, REX enable */ - |1<<0); /* disable D0-D7 enable */ - FM3_EXBUS->MODE7 &= ~(1<<4); - IO_NF_PFR = IO_NF_PFR & ~(NF_EN|NF_DATA_DIR); - IO_NF_DDR = IO_NF_DDR | (NF_EN|NF_DATA_DIR); - IO_NF_PDOR = IO_NF_PDOR | (NF_EN | NF_DATA_DIR); /* disable Flash operation */ -} - -/* - * @ Funciton: NF_ReadPage - * Parameter: block (max: 2048) - * page (max:32) - * buffer: pointer to data buffer - * Return: 0: Flash Operation OK - * 1: Flash Operation NG - */ -int NF_ReadPage(unsigned int block, unsigned int page, unsigned char *buffer, - unsigned char *oob) -{ - unsigned int blockPage,i; - - NF_Init(); - blockPage=(block<<5)+page; /* 1 block=32 page */ - NF_OE_L(); - NF_DATA_OUT(); - if (buffer != RT_NULL) - { - volatile unsigned char ch; - - NF_CMD(NAND_CMD_READ0); /* send read data */ - - NF_ADDR(0); - NF_ADDR(blockPage & 0xff); - NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ - NF_CLR_ALE(); - NF_DATA_IN(); - - Wait(500); - - for(i=0;i<512;i++) /* read 512 bytes data */ - buffer[i] = NF_RDDATA(); - for(i=0;i<16;i++) /* read 16 bytes oob */ - if (oob != RT_NULL) - oob[i] = NF_RDDATA(); - else - ch = NF_RDDATA(); - } - else - { - NF_CMD(NAND_CMD_READOOB); /* send read data */ - - NF_ADDR(0); - NF_ADDR(blockPage & 0xff); - NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ - NF_CLR_ALE(); - NF_DATA_IN(); - - Wait(500); - - for (i=0; i<16; i++) /* read 16 bytes oob */ - oob[i] = NF_RDDATA(); - } - - NF_OE_H(); - NF_UnInit(); - return 0; -} - -/* - * @ Funciton: NF_EraseBlock - * Parameter: block (max: 2048) - * Return: 0: Flash Operation OK - * 1: Flash Operation NG - */ -int NF_EraseBlock(unsigned int block) -{ - rt_uint32_t blockPage; - - trace_log("Erase block %d: ", block); - - NF_Init(); - blockPage = (block << 5); - NF_OE_L(); - NF_DATA_OUT(); - NF_CMD(NAND_CMD_ERASE1); /* send erase command */ - NF_ADDR(blockPage & 0xff); - NF_ADDR((blockPage >> 8) & 0xff); - NF_CMD(NAND_CMD_ERASE2); /* start erase */ - - if(NF_ReadStatus()) - { - NF_Reset(); - NF_OE_H(); - NF_UnInit(); - trace_log("Failed\n"); - rt_kprintf("erase block failed\n"); - - return FLASH_NG; - } - - NF_OE_H(); - NF_UnInit(); - - trace_log("OK\n"); - - return FLASH_OK; -} - -/* - * @ Funciton: NF_WritePage - * Parameter: block (max: 2048) - * page (max:32) - * buffer: pointer to data buffer - * Return: 0: Flash Operation OK - * 1: Flash Operation NG - */ -int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer) -{ - unsigned int blockPage,i; - unsigned char se[16] = {0}; - unsigned char data; - - blockPage = (block<<5)+page; - NF_Init(); - NF_OE_L(); - NF_DATA_OUT(); - NF_CMD(0x00); /* set programming area */ - NF_CMD(NAND_CMD_SEQIN); /* send write command */ - NF_ADDR(0); - NF_ADDR(blockPage & 0xff); - NF_ADDR((blockPage>>8) & 0xff); - NF_CLR_ALE(); - - for(i=0;i<512;i++) NF_WRDATA(buffer[i]); /* write data */ - for(i=0;i<16;i++) NF_WRDATA(se[i]); /* dummy write */ - - NF_CMD(NAND_CMD_PAGEPROG); /* start programming */ - - if(NF_ReadStatus()) - { - NF_Reset(); - NF_OE_H(); - NF_UnInit(); - - trace_log("write failed\n"); - return FLASH_NG; - } - - /* verify the write data */ - NF_DATA_OUT(); - NF_CMD(NAND_CMD_READ0); /* send read command */ - NF_ADDR(0); - NF_ADDR(blockPage & 0xff); - NF_ADDR((blockPage>>8) & 0xff); - NF_CLR_ALE(); - NF_DATA_IN(); - - Wait(500); - for(i=0; i<512; i++) - { - data=NF_RDDATA(); /* verify 1-512 byte */ - if(data != buffer[i]) - { - trace_log("block %d, page %d\n", block , page); - trace_log("write data failed[%d]: %02x %02x\n", i, data, buffer[i]); - - NF_Reset(); - NF_OE_H(); - NF_UnInit(); - return FLASH_NG; - } - } - - for(i=0; i<16; i++) - { - data=NF_RDDATA(); /* verify 16 byte dummy data */ - if(data != se[i]) - { - trace_log("block %d, page %d\n", block , page); - trace_log("write oob failed[%d]: %02x %02x\n", i, data, se[i]); - NF_Reset(); - NF_OE_H(); - NF_UnInit(); - return FLASH_NG; - } - } - - NF_OE_H(); - NF_UnInit(); - return FLASH_OK; -} - -/* - * @ Funciton: NF_ReadID - * Parameter: id: pointer to device ID - * Return: None - */ -void NF_ReadID(unsigned char *id) -{ - unsigned char maker_code; - NF_Init(); - NF_OE_L(); - NF_DATA_OUT(); - NF_CMD(NAND_CMD_READID); - NF_ADDR(0x00); - NF_CLR_ALE(); - Wait(10); - NF_DATA_IN(); - maker_code = NF_RDDATA(); - maker_code = maker_code; - *id = NF_RDDATA(); - NF_OE_H(); - NF_UnInit(); -} - -static rt_err_t rt_nand_init (rt_device_t dev) -{ - /* empty implementation */ - return RT_EOK; -} - -static rt_err_t rt_nand_open(rt_device_t dev, rt_uint16_t oflag) -{ - /* empty implementation */ - return RT_EOK; -} - -static rt_err_t rt_nand_close(rt_device_t dev) -{ - /* empty implementation */ - return RT_EOK; -} - -/* nand device read */ -static rt_size_t rt_nand_read (rt_device_t dev, rt_off_t pos, void* buffer, - rt_size_t size) -{ - rt_ubase_t block; /* block of position */ - rt_ubase_t page, index; /* page in block of position */ - rt_uint8_t *page_ptr, oob[16]; - struct rt_device_nand *nand; - - /* get nand device */ - nand = (struct rt_device_nand*) dev; - RT_ASSERT(nand != RT_NULL); - - /* get block and page */ - block = pos / nand->page_per_block; - page = pos % nand->page_per_block; - - trace_log("nand read: position %d, block %d, page %d, size %d\n", - pos, block, page, size); - - /* set page buffer pointer */ - page_ptr = (rt_uint8_t*) buffer; - for (index = 0; index < size; index ++) - { - NF_ReadPage(block, page + index, page_ptr, oob); - page_ptr += nand->page_size; - - if (page + index > nand->page_per_block) - { - block += 1; - page = 0; - } - } - - /* return read size (count of block) */ - return size; -} - -/* - * write pages by erase block first - * @param nand the nand device driver - * @param block the block of page - * @param page the page - * @param buffer the data buffer to be written - * @param pages the number of pages to be written - */ -static int rt_nand_eraseblock_writepage(struct rt_device_nand* nand, - rt_ubase_t block, rt_ubase_t page, - const rt_uint8_t *buffer, rt_ubase_t pages) -{ - rt_ubase_t index; - rt_uint32_t page_status; - rt_uint8_t *page_ptr, oob[16]; - - /* set page status */ - page_status = 0; - - /* read each page in block */ - page_ptr = nand->block_buffer; - for (index = 0; index < nand->page_per_block; index ++) - { - NF_ReadPage(block, index, page_ptr, oob); - if (!oob[0]) - page_status |= (1 << index); - page_ptr += nand->page_size; - } - - /* erase block */ - NF_EraseBlock(block); - - page_ptr = &(nand->block_buffer[page * nand->page_size]); - /* merge buffer to page buffer */ - for (index = 0; index < pages; index ++) - { - rt_memcpy(page_ptr, buffer, nand->page_size); - - /* set page status */ - page_status |= (1 << (page + index)); - - /* move to next page */ - page_ptr += nand->page_size; - buffer += nand->page_size; - } - - /* write to flash */ - page_ptr = nand->block_buffer; - for (index = 0; index < nand->page_per_block; index ++) - { - if (page_status & (1 << index)) - NF_WritePage(block, index, page_ptr); - - /* move to next page */ - page_ptr += nand->page_size; - } - - return 0; -} - -/* nand device write */ -static rt_size_t rt_nand_write (rt_device_t dev, rt_off_t pos, - const void* buffer, rt_size_t size) -{ - rt_ubase_t block, page; - rt_uint8_t oob[16]; - struct rt_device_nand *nand; - - nand = (struct rt_device_nand*) dev; - RT_ASSERT(nand != RT_NULL); - - /* get block and page */ - block = pos / nand->page_per_block; - page = pos % nand->page_per_block; - - trace_log("nand write: position %d, block %d, page %d, size %d\n", - pos, block, page, size); - - if (size == 1) - { - /* write one page */ - - /* read oob to get page status */ - NF_ReadPage(block, page, RT_NULL, oob); - if (oob[0]) - NF_WritePage(block, page, buffer); - else - /* erase block and then write page */ - rt_nand_eraseblock_writepage(nand, block, page, buffer, 1); - } - else if (size > 1) - { - rt_ubase_t index; - rt_ubase_t need_erase_block; - const rt_uint8_t *page_ptr; - rt_ubase_t chunk_pages, pages; - - pages = size; - page_ptr = (const rt_uint8_t*) buffer; - do - { - need_erase_block = 0; - /* calculate pages in current chunk */ - if (pages > nand->page_per_block - page) - chunk_pages = nand->page_per_block - page; - else - chunk_pages = pages; - - /* get page status in current block */ - for (index = page; index < page + chunk_pages; index ++) - { - NF_ReadPage(block, index, RT_NULL, oob); - if (!oob[0]) - { - /* this page has data, need erase this block firstly */ - need_erase_block = 1; - break; - } - } - - if (need_erase_block) - { - /* erase block and then write it */ - rt_nand_eraseblock_writepage(nand, block, page, page_ptr, chunk_pages); - page_ptr += chunk_pages * nand->page_size; - } - else - { - /* write pages directly */ - for (index = page; index < page + chunk_pages; index ++) - { - NF_WritePage(block, index, page_ptr); - page_ptr += nand->page_size; - } - } - - pages -= chunk_pages; - page = 0; block ++; /* move to next block */ - } - while (pages); - } - - return size; -} - -static rt_err_t rt_nand_control (rt_device_t dev, rt_uint8_t cmd, void *args) -{ - struct rt_device_nand *nand; - - nand = (struct rt_device_nand*) dev; - RT_ASSERT(dev != RT_NULL); - - switch (cmd) - { - case RT_DEVICE_CTRL_BLK_GETGEOME: - { - struct rt_device_blk_geometry *geometry; - - geometry = (struct rt_device_blk_geometry *)args; - if (geometry == RT_NULL) return -RT_ERROR; - - geometry->bytes_per_sector = nand->page_size; - geometry->block_size = nand->page_size * nand->page_per_block; - geometry->sector_count = nand->block_num * nand->page_per_block; - } - break; - } - - return RT_EOK; -} - -void rt_hw_nand_init(void) -{ - /* initialize nand flash structure */ - _nand.block_num = BLOCK_NUM; - _nand.page_per_block = PAGE_PER_BLOCK; - _nand.page_size = PAGE_SIZE; - - rt_memset(_nand.block_buffer, 0, sizeof(_nand.block_buffer)); - - _nand.parent.type = RT_Device_Class_MTD; - _nand.parent.rx_indicate = RT_NULL; - _nand.parent.tx_complete = RT_NULL; - _nand.parent.init = rt_nand_init; - _nand.parent.open = rt_nand_open; - _nand.parent.close = rt_nand_close; - _nand.parent.read = rt_nand_read; - _nand.parent.write = rt_nand_write; - _nand.parent.control = rt_nand_control; - - /* register a MTD device */ - rt_device_register(&(_nand.parent), "nand", RT_DEVICE_FLAG_RDWR); -} - -#ifdef NAND_DEBUG -#include -unsigned char nand_buffer[512]; -unsigned char nand_oob[16]; - -void dump_mem(unsigned char* buffer, int length) -{ - int i; - - if (length > 64) length = 64; - for (i = 0; i < length; i ++) - { - rt_kprintf("%02x ", *buffer++); - if (((i+1) % 16) == 0) - rt_kprintf("\n"); - } - rt_kprintf("\n"); -} - -void nand_read(int block, int page) -{ - rt_kprintf("read block %d, page %d\n", block, page); - - NF_ReadPage(block, page, nand_buffer, nand_oob); - rt_kprintf("page data:\n"); - dump_mem(nand_buffer, 512); - rt_kprintf("oob data:\n"); - dump_mem(nand_oob, 16); -} -FINSH_FUNCTION_EXPORT_ALIAS(nand_read, read_page, read page[block/page]); - -void nand_write(int block, int page) -{ - int i; - for (i = 0; i < 512; i ++) - nand_buffer[i] = i; - - NF_WritePage(block, page, nand_buffer); -} -FINSH_FUNCTION_EXPORT_ALIAS(nand_write, write_page, write page[block/page]); - -void nand_erase(int block) -{ - NF_EraseBlock(block); -} -FINSH_FUNCTION_EXPORT_ALIAS(nand_erase, erase_block, erase block[block]); - -void nand_readoob(int block, int page) -{ - rt_kprintf("read oob on block %d, page %d\n", block, page); - - NF_ReadPage(block, page, RT_NULL, (unsigned char*)nand_oob); - rt_kprintf("oob data:\n"); - dump_mem(nand_oob, 16); -} -FINSH_FUNCTION_EXPORT_ALIAS(nand_readoob, readoob, read oob[block/page]); - -void nand_erase_chip() -{ - int i; - unsigned char id; - - NF_ReadID(&id); - rt_kprintf("id: %02x\n", id); - - for (i = 0; i < 2048; i ++) - { - NF_EraseBlock(i); - } -} -FINSH_FUNCTION_EXPORT_ALIAS(nand_erase_chip, erase_chip, erase whole chip); -#endif diff --git a/bsp/fm3/mb9bf506r/nand.h b/bsp/fm3/mb9bf506r/nand.h deleted file mode 100644 index ffb4bae2c3..0000000000 --- a/bsp/fm3/mb9bf506r/nand.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * File : nand.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-05-25 Bernard first version - */ - -#ifndef __NAND_H__ -#define __NAND_H__ - -#include - -#define IO_NF_PFR FM3_GPIO->PFR3 -#define IO_NF_DDR FM3_GPIO->DDR3 -#define IO_NF_PDOR FM3_GPIO->PDOR3 - -#define NF_EN 0x0008 -#define NF_DATA_DIR 0x0004 - -#define EXT_BUS_BASE_ADDR 0x60000000 -#define EXT_CS7_OFFSET 0x0E000000 -#define EXT_CS7_SIZE 0x02000000 - -#define NF_FLASH_BASE_ADDR (EXT_BUS_BASE_ADDR+EXT_CS7_OFFSET) - -#define NF_ALE_OFFSET 0x00003000 -#define NF_ADDR_OFFSET 0x00002000 -#define NF_CMD_OFFSET 0x00001000 -#define NF_DATA_OFFSET 0x00000000 - -/* NAND command */ -#define NAND_CMD_READ0 0x00 -#define NAND_CMD_READ1 0x01 -#define NAND_CMD_PAGEPROG 0x10 -#define NAND_CMD_READOOB 0x50 -#define NAND_CMD_ERASE1 0x60 -#define NAND_CMD_STATUS 0x70 -#define NAND_CMD_SEQIN 0x80 -#define NAND_CMD_READID 0x90 -#define NAND_CMD_READID1 0x91 -#define NAND_CMD_ERASE2 0xd0 -#define NAND_CMD_RESET 0xff - -#define FLASH_OK 0 -#define FLASH_NG 1 - -/* nand flash device initialization */ -void rt_hw_nand_init(void); - -#endif diff --git a/bsp/fm3/mb9bf506r/rtconfig.h b/bsp/fm3/mb9bf506r/rtconfig.h deleted file mode 100644 index 78b3315a7e..0000000000 --- a/bsp/fm3/mb9bf506r/rtconfig.h +++ /dev/null @@ -1,90 +0,0 @@ -/* RT-Thread config file */ -#ifndef __RTTHREAD_CFG_H__ -#define __RTTHREAD_CFG_H__ - -/* RT_NAME_MAX*/ -#define RT_NAME_MAX 8 - -/* RT_ALIGN_SIZE*/ -#define RT_ALIGN_SIZE 8 - -/* PRIORITY_MAX */ -#define RT_THREAD_PRIORITY_MAX 32 - -/* Tick per Second */ -#define RT_TICK_PER_SECOND 100 - -/* SECTION: RT_DEBUG */ -/* Thread Debug */ -#define RT_DEBUG -#define RT_USING_OVERFLOW_CHECK - -/* Using Hook */ -#define RT_USING_HOOK - -/* SECTION: IPC */ -/* Using Semaphore */ -#define RT_USING_SEMAPHORE - -/* Using Mutex */ -#define RT_USING_MUTEX - -/* Using Event */ -#define RT_USING_EVENT - -/* Using MailBox */ -#define RT_USING_MAILBOX - -/* Using Message Queue */ -#define RT_USING_MESSAGEQUEUE - -/* SECTION: Memory Management */ -/* Using Memory Pool Management*/ -#define RT_USING_MEMPOOL - -/* Using Dynamic Heap Management */ -#define RT_USING_HEAP - -/* Using Small MM */ -#define RT_USING_SMALL_MEM - -/* SECTION: Device System */ -/* Using Device System */ -#define RT_USING_DEVICE -/* RT_USING_UART */ -#define RT_USING_UART2 -#define RT_UART_RX_BUFFER_SIZE 64 - -/* SECTION: Console options */ -/* #define RT_TINY_SIZE */ -#define RT_USING_CONSOLE -/* the buffer size of console */ -#define RT_CONSOLEBUF_SIZE 128 - -/* SECTION: finsh, a C-Express shell */ -/* Using FinSH as Shell*/ -#define RT_USING_FINSH -/* Using symbol table */ -#define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_STACK_SIZE 1024 - -/* SECTION: Device filesystem support */ -/* using DFS support */ -#define RT_USING_DFS -#define RT_USING_DFS_ELMFAT -/* use long file name feature */ -/* #define RT_DFS_ELM_USE_LFN */ -/* the max number of file length */ -#define RT_DFS_ELM_MAX_LFN 32 -/* #define RT_USING_DFS_UFFS */ -/* #define RT_USING_DFS_DEVFS */ - -/* the max number of mounted filesystem */ -#define DFS_FILESYSTEMS_MAX 2 -/* the max number of opened files */ -#define DFS_FD_MAX 8 -/* using working directory */ -#define DFS_USING_WORKDIR - -#endif diff --git a/bsp/fm3/mb9bf506r/rtconfig.py b/bsp/fm3/mb9bf506r/rtconfig.py deleted file mode 100644 index 6381070f7c..0000000000 --- a/bsp/fm3/mb9bf506r/rtconfig.py +++ /dev/null @@ -1,113 +0,0 @@ -# toolchains options -ARCH='arm' -CPU='cortex-m3' -CROSS_TOOL='gcc' - -# cross_tool provides the cross compiler -# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR - -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = '/media/workspace/arm-2011.03/bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = 'C:/Keil' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iar' - IAR_PATH = 'C:\Program Files\IAR Systems\Embedded Workbench 6.0 Evaluation' - -BUILD = 'debug' - -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'axf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' - CFLAGS = DEVICE - AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-fm3.map,-cref,-u,Reset_Handler -T fm3_rom.ld' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - - DEVICE = ' --device DARMSTM' - CFLAGS = DEVICE + ' --apcs=interwork' - AFLAGS = DEVICE - LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-stm32.map --scatter stm32_rom.sct' - - CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' - LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' - - EXEC_PATH += '/arm/bin40/' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' - -elif PLATFORM == 'iar': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - CFLAGS = '' - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - CFLAGS += ' --debug' - CFLAGS += ' --endian=little' - CFLAGS += ' --cpu=Cortex-M3' - CFLAGS += ' -e' - CFLAGS += ' --fpu=None' - CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' -Ol' - CFLAGS += ' --use_c++_inline' - - AFLAGS = '' - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --cpu Cortex-M3' - AFLAGS += ' --fpu None' - AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"' - - LFLAGS = ' --config mb9bf506.icf' - LFLAGS += ' --semihosting' - LFLAGS += ' --entry __iar_program_start' - - EXEC_PATH = IAR_PATH + '/arm/bin/' - POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' diff --git a/bsp/fm3/mb9bf506r/serial.c b/bsp/fm3/mb9bf506r/serial.c deleted file mode 100644 index a5116fc7e3..0000000000 --- a/bsp/fm3/mb9bf506r/serial.c +++ /dev/null @@ -1,348 +0,0 @@ -/* - * File : serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2011-05-15 lgnq modified according bernard's implementaion. - */ - -#include - -#include "serial.h" - -/** - * @addtogroup FM3 MB9B500 - */ -/*@{*/ - -/* RT-Thread Device Interface */ -/** - * This function initializes serial - */ -static rt_err_t rt_serial_init (rt_device_t dev) -{ - struct serial_device* uart = (struct serial_device*) dev->user_data; - - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = uart->int_rx->save_index = 0; - } - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - rt_memset(uart->int_tx->tx_buffer, 0, - sizeof(uart->int_tx->tx_buffer)); - uart->int_tx->write_index = uart->int_tx->save_index = 0; - } - - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } - - return RT_EOK; -} - -/* save a char to serial buffer */ -static void rt_serial_savechar(struct serial_device* uart, char ch) -{ - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } - - /* enable interrupt */ - rt_hw_interrupt_enable(level); -} - -static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) -{ - struct serial_device* uart; - - RT_ASSERT(dev != RT_NULL); - uart = (struct serial_device*) dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* enable interrupt */ - UART_ENABLE_IRQ(uart->rx_irq); - } - - return RT_EOK; -} - -static rt_err_t rt_serial_close(rt_device_t dev) -{ - struct serial_device* uart; - - RT_ASSERT(dev != RT_NULL); - uart = (struct serial_device*) dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable interrupt */ - UART_DISABLE_IRQ(uart->rx_irq); - } - - return RT_EOK; -} - -static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, - rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - ptr = buffer; - err_code = RT_EOK; - uart = (struct serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_base_t level; - - /* interrupt mode Rx */ - while (size) - { - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size --; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (uart->uart_device->SSR & SSR_RDRF) - { - *ptr = uart->uart_device->RDR & 0xff; - ptr ++; - } - } - } - - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; -} - -static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, - const void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct serial_device*)dev->user_data; - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx */ - while (uart->int_tx->save_index != uart->int_tx->write_index) - { - /* save on tx buffer */ - uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - - -- size; - - /* move to next position */ - uart->int_tx->save_index ++; - - /* wrap save index */ - if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) - uart->int_tx->save_index = 0; - } - - /* set error code */ - if (size > 0) - err_code = -RT_EFULL; - } - else - { - /* polling mode */ - while (size) - { - /* - * to be polite with serial console add a line feed - * to the carriage return character - */ - if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) - { - while (!(uart->uart_device->SSR & SSR_TDRE)); - uart->uart_device->TDR = '\r'; - } - - while (!(uart->uart_device->SSR & SSR_TDRE)); - uart->uart_device->TDR = (*ptr & 0x1FF); - - ++ptr; --size; - } - } - - /* set error code */ - rt_set_errno(err_code); - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; -} - -static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args) -{ - RT_ASSERT(dev != RT_NULL); - - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; - - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } - - return RT_EOK; -} - -/* - * serial register - */ -rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, - rt_uint32_t flag, struct serial_device *serial) -{ - RT_ASSERT(device != RT_NULL); - - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; - - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); -} - -/* ISR for serial interrupt */ -void rt_hw_serial_isr(rt_device_t device) -{ - struct serial_device* uart = (struct serial_device*) device->user_data; - - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); - - /* save on rx buffer */ - while (uart->uart_device->SSR & SSR_RDRF) - { - rt_serial_savechar(uart, uart->uart_device->RDR & 0xff); - } - - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; - - device->rx_indicate(device, rx_length); - } -} - -#ifdef RT_USING_UART2 -/* UART2 device driver structure */ -#define UART2 FM3_MFS2_UART -struct serial_int_rx uart2_int_rx; -struct serial_device uart2 = -{ - UART2, - MFS2RX_IRQn, - MFS2TX_IRQn, - &uart2_int_rx, - RT_NULL -}; -struct rt_device uart2_device; - -void MFS2RX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - rt_hw_serial_isr(&uart2_device); - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif - -void rt_hw_serial_init(void) -{ -#ifdef RT_USING_UART2 - /* initialize UART2 */ - /* Set Uart Ch2 Port, SIN2_1, SOT2_1 */ - FM3_GPIO->PFR2 = FM3_GPIO->PFR2 | 0x0030; - FM3_GPIO->EPFR07 = FM3_GPIO->EPFR07 | 0x000a0000; - - uart2.uart_device->SMR = SMR_MD_UART | SMR_SOE;; - uart2.uart_device->BGR = (40000000UL + (BPS/2))/BPS - 1; - uart2.uart_device->ESCR = ESCR_DATABITS_8; - uart2.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE; - - /* register UART2 device */ - rt_hw_serial_register(&uart2_device, - "uart2", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, - &uart2); -#endif -} - -/*@}*/ diff --git a/bsp/fm3/mb9bf506r/serial.h b/bsp/fm3/mb9bf506r/serial.h deleted file mode 100644 index 1fd05d429d..0000000000 --- a/bsp/fm3/mb9bf506r/serial.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * File : serial.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2006-03-13 Bernard first version - * 2011-05-15 lgnq modified according bernard's implementaion. - */ - -#ifndef __RT_HW_SERIAL_H__ -#define __RT_HW_SERIAL_H__ - -#include -#include - -#include "mb9bf506r.h" - -#define SMR_SOE 0x01U -#define SMR_BDS 0x04U -#define SMR_SBL 0x08U -#define SMR_WUCR 0x10U -#define SMR_MD_UART 0x00U -#define SMR_MD_UART_MP 0x20U -#define SMR_MD_SIO 0x40U -#define SMR_MD_LIN 0x60U -#define SMR_MD_I2C 0x80U - -#define SCR_TXE 0x01U -#define SCR_RXE 0x02U -#define SCR_TBIE 0x04U -#define SCR_TIE 0x08U -#define SCR_RIE 0x10U -#define SCR_UPGL 0x80U - -#define SSR_TBI 0x01U -#define SSR_TDRE 0x02U -#define SSR_RDRF 0x04U -#define SSR_ORE 0x08U -#define SSR_FRE 0x10U -#define SSR_PE 0x20U -#define SSR_REC 0x80U - -#define ESCR_P 0x08U -#define ESCR_PEN 0x10U -#define ESCR_INV 0x20U -#define ESCR_ESBL 0x40U -#define ESCR_FLWEN 0x80U -#define ESCR_DATABITS_8 0x00U -#define ESCR_DATABITS_5 0x01U -#define ESCR_DATABITS_6 0x02U -#define ESCR_DATABITS_7 0x03U -#define ESCR_DATABITS_9 0x04U - -#define BPS 115200 /* serial baudrate */ - -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 - -struct serial_int_rx -{ - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; -}; - -struct serial_int_tx -{ - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; -}; - -/* - * Enable/DISABLE Interrupt Controller - */ -/* deviation from MISRA-C:2004 Rule 19.7 */ -#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) -#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) - -struct serial_device -{ - FM3_MFS03_UART_TypeDef* uart_device; - /* irq number */ - IRQn_Type rx_irq, tx_irq; - - /* rx structure */ - struct serial_int_rx* int_rx; - /* tx structure */ - struct serial_int_tx* int_tx; -}; - -void rt_hw_serial_isr(rt_device_t device); -void rt_hw_serial_init(void); - -#endif diff --git a/bsp/fm3/mb9bf506r/startup.c b/bsp/fm3/mb9bf506r/startup.c deleted file mode 100644 index 073318abeb..0000000000 --- a/bsp/fm3/mb9bf506r/startup.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * File : startup.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2011-02-24 Bernard first implementation - */ - -#include -#include - -#include "board.h" -#include "mb9bf506r.h" -#ifdef RT_USING_FINSH -#include -#endif - -/** - * @addtogroup FM3 - */ - -extern struct serial_device uart0; -extern struct rt_device uart0_device; -extern struct serial_device uart2; -extern struct rt_device uart2_device; - -/*@{*/ - -extern int rt_application_init(void); -#ifdef RT_USING_FINSH -extern void finsh_system_init(void); -#endif - -#ifdef __CC_ARM -extern int Image$$RW_IRAM1$$ZI$$Limit; -#elif __ICCARM__ -#pragma section="HEAP" -#else -extern int __bss_end; -#endif - -/** - * This function will startup RT-Thread RTOS. - */ -void rtthread_startup(void) -{ - /* init board */ - rt_hw_board_init(); - - /* show version */ - rt_show_version(); - - /* init tick */ - rt_system_tick_init(); - /* init timer system */ - rt_system_timer_init(); - -#ifdef RT_USING_HEAP - #ifdef __CC_ARM - rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); - #elif __ICCARM__ - rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); - #else - /* init memory system */ - rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); - #endif -#endif - - /* init scheduler system */ - rt_system_scheduler_init(); - -#ifdef RT_USING_DFS -#ifdef RT_USING_DFS_UFFS - rt_hw_nand_init(); -#endif -#endif - - /* init application */ - rt_application_init(); - -#ifdef RT_USING_FINSH - /* init finsh */ - finsh_system_init(); -#ifdef RT_USING_DEVICE - finsh_set_device("uart2"); -#endif -#endif - - /* init timer thread */ - rt_system_timer_thread_init(); - - /* init idle thread */ - rt_thread_idle_init(); - - /* start scheduler */ - rt_system_scheduler_start(); - - /* never reach here */ - return ; -} - -int main(void) -{ - /* disable interrupt first */ - rt_hw_interrupt_disable(); - - /* init system setting */ - SystemInit(); - - /* startup RT-Thread RTOS */ - rtthread_startup(); - - return 0; -} - -/*@}*/ diff --git a/bsp/mb9bf500r/CMSIS/SConscript b/bsp/mb9bf500r/CMSIS/SConscript new file mode 100644 index 0000000000..05e39c54d8 --- /dev/null +++ b/bsp/mb9bf500r/CMSIS/SConscript @@ -0,0 +1,19 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +src = Glob('*.c') + +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['start_gcc.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['start_rvds.S'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['start_iar.S'] + +CPPPATH = [GetCurrentDir()] + +group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, LIBRARY = '') + +Return('group') diff --git a/bsp/mb9bf500r/CMSIS/core_cm3.c b/bsp/mb9bf500r/CMSIS/core_cm3.c new file mode 100644 index 0000000000..f1bfb2b8e0 --- /dev/null +++ b/bsp/mb9bf500r/CMSIS/core_cm3.c @@ -0,0 +1,359 @@ +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V1.40 + * @date 18. February 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ########################## Core Instruction Access ######################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ + +/** + * @brief Reverse byte order (16 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +#if (__ARMCC_VERSION < 400677) +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +#if (__ARMCC_VERSION < 400677) +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + /** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __CLREX(void) +{ + clrex +} +#endif /* __ARMCC_VERSION */ + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* obsolete */ +#endif + + +/* ########################### Core Function Access ########################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get IPSR Register value + * + * @return uint32_t IPSR value + * + * return the content of the IPSR register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_IPSR(void) +{ + mrs r0, ipsr + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get APSR Register value + * + * @return uint32_t APSR value + * + * return the content of the APSR register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_APSR(void) +{ + mrs r0, apsr + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get xPSR Register value + * + * @return uint32_t xPSR value + * + * return the content of the xPSR register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_xPSR(void) +{ + mrs r0, xpsr + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the FPSCR value + * + * @return FloatingPointStatusControlRegister + * + * Return the content of the FPSCR register + */ + +/** + * @brief Set the FPSCR value + * + * @param fpscr FloatingPointStatusControlRegister + * + * Set the FPSCR register + */ + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* obsolete */ +#endif diff --git a/bsp/mb9bf500r/CMSIS/core_cm3.h b/bsp/mb9bf500r/CMSIS/core_cm3.h new file mode 100644 index 0000000000..43be05e58b --- /dev/null +++ b/bsp/mb9bf500r/CMSIS/core_cm3.h @@ -0,0 +1,1166 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.40 + * @date 16. February 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CM3_H__ +#define __CORE_CM3_H__ + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - not yet checked + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x40) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + +#include /* Include standard types */ + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + +/** @addtogroup CMSIS_ARM_CORE CMSIS ARM Core + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; +#else + uint32_t _reserved0:16; + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; + uint32_t w; +} APSR_Type; + +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 00..08 Exception number */ + uint32_t _reserved0:23; + } b; + uint32_t w; +} IPSR_Type; + +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 00..08 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; +#else + uint32_t _reserved0:7; + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; + uint32_t w; +} xPSR_Type; + +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 00 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 01 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 02 FP extension active flag */ + uint32_t _reserved0:29; + } b; + uint32_t w; +} CONTROL_Type; + +/*@}*/ /* end of group CMSIS_ARM_CORE */ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/* ########################## Core Instruction Access ######################### */ +#include "core_cmInstr.h" + +/* ########################### Core Function Access ########################### */ +#include "core_cmFunc.h" + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + +#endif /* __CORE_CM3_H__ */ + +/*lint -restore */ diff --git a/bsp/mb9bf500r/CMSIS/core_cmFunc.h b/bsp/mb9bf500r/CMSIS/core_cmFunc.h new file mode 100644 index 0000000000..03c29d35dc --- /dev/null +++ b/bsp/mb9bf500r/CMSIS/core_cmFunc.h @@ -0,0 +1,912 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V1.40 + * @date 16. February 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H__ +#define __CORE_CMFUNC_H__ + +/* ########################### Core Function Access ########################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ +/* ARM armcc specific functions */ + + /** + * @brief Enable IRQ Interrupts + * + * Enables IRQ interrupts by clearing the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + /** + * @brief Disable IRQ Interrupts + * + * Disables IRQ interrupts by setting the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_CONTROL(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_CONTROL(uint32_t control); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get IPSR Register value + * + * @return uint32_t IPSR value + * + * return the content of the IPSR register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_IPSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get APSR Register value + * + * @return uint32_t APSR value + * + * return the content of the APSR register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_APSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get xPSR Register value + * + * @return uint32_t xPSR value + * + * return the content of the xPSR register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_xPSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_PSP(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_PSP(uint32_t topOfProcStack); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_MSP(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_MSP(uint32_t topOfMainStack); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_MSP(uint32_t mainStackPointer) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = mainStackPointer; +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_PRIMASK(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_PRIMASK(uint32_t priMask); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} +#endif /* __ARMCC_VERSION */ + + +#if (__CORTEX_M >= 0x03) + + /** + * @brief Enable FIQ Interrupts + * + * Enables FIQ interrupts by clearing the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + /** + * @brief Disable FIQ Interrupts + * + * Disables FIQ interrupts by setting the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_BASEPRI(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_BASEPRI(uint32_t basePri); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_FAULTMASK(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_FAULTMASK(uint32_t faultMask); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} +#endif /* __ARMCC_VERSION */ + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** + * @brief Return the FPSCR value + * + * @return FloatingPointStatusControlRegister + * + * Return the content of the FPSCR register + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + +/** + * @brief Set the FPSCR value + * + * @param fpscr FloatingPointStatusControlRegister + * + * Set the FPSCR register + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + + #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* IAR iccarm specific functions */ +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + +#pragma diag_suppress=Pe940 + + /** + * @brief Enable IRQ Interrupts + * + * Enables IRQ interrupts by clearing the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +#define __enable_irq __enable_interrupt + + /** + * @brief Disable IRQ Interrupts + * + * Disables IRQ interrupts by setting the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +#define __disable_irq __disable_interrupt + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */ + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */ + +/** + * @brief Get IPSR Register value + * + * @return uint32_t IPSR value + * + * return the content of the IPSR register + */ +static uint32_t __get_IPSR(void) +{ + __ASM("mrs r0, ipsr"); +} + +/** + * @brief Get APSR Register value + * + * @return uint32_t APSR value + * + * return the content of the APSR register + */ +/* __intrinsic unsigned long __get_APSR( void ); (see intrinsic.h) */ + +/** + * @brief Get xPSR Register value + * + * @return uint32_t xPSR value + * + * return the content of the xPSR register + */ +static uint32_t __get_xPSR(void) +{ + __ASM("mrs r0, psr"); // assembler does not know "xpsr" +} + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ + static uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +static void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +static uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +static void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */ + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */ + + +#if (__CORTEX_M >= 0x03) + + /** + * @brief Enable FIQ Interrupts + * + * Enables FIQ interrupts by clearing the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } + + /** + * @brief Disable FIQ Interrupts + * + * Disables FIQ interrupts by setting the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */ + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */ + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */ + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */ + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** + * @brief Return the FPSCR value + * + * @return FloatingPointStatusControlRegister + * + * Return the content of the FPSCR register + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + /* not yet implemented */ + return(0); +#else + return(0); +#endif +} + +/** + * @brief Set the FPSCR value + * + * @param fpscr FloatingPointStatusControlRegister + * + * Set the FPSCR register + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + /* not yet implemented */ +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + /** + * @brief Enable IRQ Interrupts + * + * Enables IRQ interrupts by clearing the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } + + /** + * @brief Disable IRQ Interrupts + * + * Disables IRQ interrupts by setting the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + +/** + * @brief Get IPSR Register value + * + * @return uint32_t IPSR value + * + * return the content of the IPSR register + */ +static __INLINE uint32_t __get_IPSR(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + +/** + * @brief Get APSR Register value + * + * @return uint32_t APSR value + * + * return the content of the APSR register + */ +static __INLINE uint32_t __get_APSR(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + +/** + * @brief Get xPSR Register value + * + * @return uint32_t xPSR value + * + * return the content of the xPSR register + */ +static __INLINE uint32_t __get_xPSR(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +static __INLINE uint32_t __get_PSP(void) __attribute__( ( naked ) ); +static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t result __ASM ("r0") = 0; + + __ASM volatile ("MRS %0, psp\n" + "BX lr \n" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" + "BX lr \n" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +static __INLINE uint32_t __get_MSP(void) __attribute__( ( naked ) ); +static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t result __ASM ("r0") = 0; + + __ASM volatile ("MRS %0, msp\n" + "BX lr \n" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +static __INLINE void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); +static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" + "BX lr \n" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + + /** + * @brief Enable FIQ Interrupts + * + * Enables FIQ interrupts by clearing the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } + + /** + * @brief Disable FIQ Interrupts + * + * Disables FIQ interrupts by setting the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + + +#if (__CORTEX_M == 0x04) + +/** + * @brief Return the FPSCR value + * + * @return FloatingPointStatusControlRegister + * + * Return the content of the FPSCR register + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result=0; + + __ASM volatile ("MRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + +/** + * @brief Set the FPSCR value + * + * @param fpscr FloatingPointStatusControlRegister + * + * Set the FPSCR register + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("MSR control, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +#endif // __CORE_CMFUNC_H__ diff --git a/bsp/mb9bf500r/CMSIS/core_cmInstr.h b/bsp/mb9bf500r/CMSIS/core_cmInstr.h new file mode 100644 index 0000000000..514cfb2385 --- /dev/null +++ b/bsp/mb9bf500r/CMSIS/core_cmInstr.h @@ -0,0 +1,684 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V1.40 + * @date 16. February 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H__ +#define __CORE_CMINSTR_H__ + +/* ########################## Core Instruction Access ######################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ +/* ARM armcc specific functions */ + + /** + * @brief No Operation + * + * No Operation does nothing. This instruction can be used for code alignment + * purposes. + */ +#define __NOP __nop + + /** + * @brief Wait For Interrupt + * + * Wait For Interrupt is a hint instruction that suspends execution until + * one of a number of events occurs. + */ +#define __WFI __wfi + + /** + * @brief Wait For Event + * + * Wait For Event is a hint instruction that permits the processor to enter + * a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + /** + * @brief Send Event + * + * Send Event is a hint instruction. It causes an event to be signaled + * to the CPU. + */ +#define __SEV __sev + + /** + * @brief Instruction Synchronization Barrier + * + * Instruction Synchronization Barrier flushes the pipeline in the processor, + * so that all instructions following the ISB are fetched from cache or + * memory, after the instruction has been completed + */ +#define __ISB() __isb(0xF) + + /** + * @brief Data Synchronization Barrier + * + * The DSB instruction operation acts as a special kind of Data Memory Barrier. + * The DSB operation completes when all explicit memory accesses before this + * instruction complete. + */ +#define __DSB() __dsb(0xF) + + /** + * @brief Data Memory Barrier + * + * DMB ensures the apparent order of the explicit memory operations before + * and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + +/** + * @brief Reverse byte order (32 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +#define __REV __rev + +/** + * @brief Reverse byte order (16 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +#if (__ARMCC_VERSION < 400677) +extern uint32_t __REV16(uint16_t value); +#else /* (__ARMCC_VERSION >= 400677) */ +static __INLINE __ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +#if (__ARMCC_VERSION < 400677) +extern int32_t __REVSH(int16_t value); +#else /* (__ARMCC_VERSION >= 400677) */ +static __INLINE __ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +#if (__CORTEX_M >= 0x03) + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +#define __RBIT __rbit + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +#define __STREXB(value, ptr) __strex(value, ptr) + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +#define __STREXH(value, ptr) __strex(value, ptr) + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + /** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#if (__ARMCC_VERSION < 400000) +extern void __CLREX(void); +#else /* (__ARMCC_VERSION >= 400000) */ +#define __CLREX __clrex +#endif /* __ARMCC_VERSION */ + +#endif /* (__CORTEX_M >= 0x03) */ + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* IAR iccarm specific functions */ +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + +#pragma diag_suppress=Pe940 + + /** + * @brief No Operation + * + * No Operation does nothing. This instruction can be used for code alignment + * purposes. + */ +#define __NOP __no_operation + + /** + * @brief Wait For Interrupt + * + * Wait For Interrupt is a hint instruction that suspends execution until + * one of a number of events occurs. + */ +static __INLINE void __WFI() { __ASM ("wfi"); } + + /** + * @brief Wait For Event + * + * Wait For Event is a hint instruction that permits the processor to enter + * a low-power state until one of a number of events occurs. + */ +static __INLINE void __WFE() { __ASM ("wfe"); } + + /** + * @brief Send Event + * + * Send Event is a hint instruction. It causes an event to be signaled + * to the CPU. + */ +static __INLINE void __SEV() { __ASM ("sev"); } + + /** + * @brief Instruction Synchronization Barrier + * + * Instruction Synchronization Barrier flushes the pipeline in the processor, + * so that all instructions following the ISB are fetched from cache or + * memory, after the instruction has been completed + */ +/* intrinsic void __ISB(void) (see intrinsics.h */ + + /** + * @brief Data Synchronization Barrier + * + * The DSB instruction operation acts as a special kind of Data Memory Barrier. + * The DSB operation completes when all explicit memory accesses before this + * instruction complete. + */ +/* intrinsic void __DSB(void) (see intrinsics.h */ + + /** + * @brief Data Memory Barrier + * + * DMB ensures the apparent order of the explicit memory operations before + * and after the instruction, without ensuring their completion. + */ +/* intrinsic void __DMB(void) (see intrinsics.h */ + +/** + * @brief Reverse byte order (32 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h */ + +/** + * @brief Reverse byte order (16 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +static uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */ + + +#if (__CORTEX_M >= 0x03) + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +static uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +static uint8_t __LDREXB(uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +static uint16_t __LDREXH(uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h */ +static uint32_t __LDREXW(uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +static uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +static uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h */ +static uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); +} + + /** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +static __INLINE void __CLREX() { __ASM ("clrex"); } + +#endif /* (__CORTEX_M >= 0x03) */ + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + + /** + * @brief No Operation + * + * No Operation does nothing. This instruction can be used for code alignment + * purposes. + */ +static __INLINE void __NOP() { __ASM volatile ("nop"); } + + /** + * @brief Wait For Interrupt + * + * Wait For Interrupt is a hint instruction that suspends execution until + * one of a number of events occurs. + */ +static __INLINE void __WFI() { __ASM volatile ("wfi"); } + + /** + * @brief Wait For Event + * + * Wait For Event is a hint instruction that permits the processor to enter + * a low-power state until one of a number of events occurs. + */ +static __INLINE void __WFE() { __ASM volatile ("wfe"); } + + /** + * @brief Send Event + * + * Send Event is a hint instruction. It causes an event to be signaled + * to the CPU. + */ +static __INLINE void __SEV() { __ASM volatile ("sev"); } + + /** + * @brief Instruction Synchronization Barrier + * + * Instruction Synchronization Barrier flushes the pipeline in the processor, + * so that all instructions following the ISB are fetched from cache or + * memory, after the instruction has been completed + */ +static __INLINE void __ISB() { __ASM volatile ("isb"); } + + /** + * @brief Data Synchronization Barrier + * + * The DSB instruction operation acts as a special kind of Data Memory Barrier. + * The DSB operation completes when all explicit memory accesses before this + * instruction complete. + */ +static __INLINE void __DSB() { __ASM volatile ("dsb"); } + + /** + * @brief Data Memory Barrier + * + * DMB ensures the apparent order of the explicit memory operations before + * and after the instruction, without ensuring their completion. + */ +static __INLINE void __DMB() { __ASM volatile ("dmb"); } + +/** + * @brief Reverse byte order (32 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +static __INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order (16 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +static __INLINE uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +static __INLINE int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +#if (__CORTEX_M >= 0x03) + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +static __INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +static __INLINE uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +static __INLINE uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +static __INLINE uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +static __INLINE uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +static __INLINE uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +static __INLINE uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + /** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +static __INLINE void __CLREX() { __ASM volatile ("clrex"); } + +#endif /* (__CORTEX_M >= 0x03) */ + + +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +#endif // __CORE_CMINSTR_H__ diff --git a/bsp/mb9bf500r/CMSIS/mb9bf506r.h b/bsp/mb9bf500r/CMSIS/mb9bf506r.h new file mode 100644 index 0000000000..3f0a9481c3 --- /dev/null +++ b/bsp/mb9bf500r/CMSIS/mb9bf506r.h @@ -0,0 +1,9739 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user's obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intentional misconduct and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.5) */ +/************************************************************************/ +/* */ +/* Header File for Device MB9BF506R */ +/* Version V1.00 */ +/* Date 2011-01-21 */ +/* */ +/************************************************************************/ + +#ifndef _MB9BF506R_H_ +#define _MB9BF506R_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +/****************************************************************************** + * Configuration of the Cortex-M3 Processor and Core Peripherals + ******************************************************************************/ +#define __MPU_PRESENT 1 /* FM3 provide an MPU */ +#define __NVIC_PRIO_BITS 4 /* FM3 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + + +/****************************************************************************** + * Interrupt Number Definition + ******************************************************************************/ +typedef enum IRQn +{ + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + MemManage_IRQn = -12, /* 4 Memory Management */ + BusFault_IRQn = -11, /* 5 Bus Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault */ + SVC_IRQn = -5, /* 11 SV Call */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSVC_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + + CSV_IRQn = 0, /* Clock Super Visor */ + SWDT_IRQn = 1, /* Software Watchdog Timer */ + LVD_IRQn = 2, /* Low Voltage Detector */ + WFG_IRQn = 3, /* Wave Form Generator */ + EXINT0_7_IRQn = 4, /* External Interrupt Request ch.0 to ch.7 */ + EXINT8_15_IRQn = 5, /* External Interrupt Request ch.8 to ch.15 */ + DTIM_QDU_IRQn = 6, /* Dual Timer / Quad Decoder */ + MFS0RX_IRQn = 7, /* MultiFunction Serial ch.0 */ + MFS0TX_IRQn = 8, /* MultiFunction Serial ch.0 */ + MFS1RX_IRQn = 9, /* MultiFunction Serial ch.1 */ + MFS1TX_IRQn = 10, /* MultiFunction Serial ch.1 */ + MFS2RX_IRQn = 11, /* MultiFunction Serial ch.2 */ + MFS2TX_IRQn = 12, /* MultiFunction Serial ch.2 */ + MFS3RX_IRQn = 13, /* MultiFunction Serial ch.3 */ + MFS3TX_IRQn = 14, /* MultiFunction Serial ch.3 */ + MFS4RX_IRQn = 15, /* MultiFunction Serial ch.4 */ + MFS4TX_IRQn = 16, /* MultiFunction Serial ch.4 */ + MFS5RX_IRQn = 17, /* MultiFunction Serial ch.5 */ + MFS5TX_IRQn = 18, /* MultiFunction Serial ch.5 */ + MFS6RX_IRQn = 19, /* MultiFunction Serial ch.6 */ + MFS6TX_IRQn = 20, /* MultiFunction Serial ch.6 */ + MFS7RX_IRQn = 21, /* MultiFunction Serial ch.7 */ + MFS7TX_IRQn = 22, /* MultiFunction Serial ch.7 */ + PPG_IRQn = 23, /* PPG */ + OSC_PLL_WC_IRQn = 24, /* OSC / PLL / Watch Counter */ + ADC0_IRQn = 25, /* ADC0 */ + ADC1_IRQn = 26, /* ADC1 */ + ADC2_IRQn = 27, /* ADC2 */ + FRTIM_IRQn = 28, /* Free-run Timer */ + INCAP_IRQn = 29, /* Input Capture */ + OUTCOMP_IRQn = 30, /* Output Compare */ + BTIM_IRQn = 31, /* Base Timer ch.0 to ch.7 */ + CAN0_IRQn = 32, /* CAN ch.0 */ + CAN1_IRQn = 33, /* CAN ch.1 */ + USBF_IRQn = 34, /* USB Function */ + USBF_USBH_IRQn = 35, /* USB Function / USB HOST */ + /* Reserved = 36, */ + /* Reserved = 37, */ + DMAC0_IRQn = 38, /* DMAC ch.0 */ + DMAC1_IRQn = 39, /* DMAC ch.1 */ + DMAC2_IRQn = 40, /* DMAC ch.2 */ + DMAC3_IRQn = 41, /* DMAC ch.3 */ + DMAC4_IRQn = 42, /* DMAC ch.4 */ + DMAC5_IRQn = 43, /* DMAC ch.5 */ + DMAC6_IRQn = 44, /* DMAC ch.6 */ + DMAC7_IRQn = 45, /* DMAC ch.7 */ + /* Reserved = 46, */ + /* Reserved = 47, */ +} IRQn_Type; + + +#include "core_cm3.h" +#include "system_mb9bf50x.h" +#include + +#define SUCCESS 0 +#define ERROR -1 + +#ifndef NULL +#define NULL 0 +#endif + + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** + * Flash_IF_MODULE + ******************************************************************************/ +/* Flash interface registers */ +typedef struct +{ + __IO uint32_t FASZR; + __IO uint32_t FRWTR; + __IO uint32_t FSTR; + uint8_t RESERVED0[4]; + __IO uint32_t FSYNDN; + uint8_t RESERVED1[236]; + __IO uint32_t CRTRMM; +}FM3_FIF_TypeDef; + +/****************************************************************************** + * Clock_Reset_MODULE + ******************************************************************************/ +/* Clock and reset registers */ +typedef struct +{ + __IO uint8_t SCM_CTL; + uint8_t RESERVED0[3]; + __IO uint8_t SCM_STR; + uint8_t RESERVED1[3]; + __IO uint32_t STB_CTL; + __IO uint16_t RST_STR; + uint8_t RESERVED2[2]; + __IO uint8_t BSC_PSR; + uint8_t RESERVED3[3]; + __IO uint8_t APBC0_PSR; + uint8_t RESERVED4[3]; + __IO uint8_t APBC1_PSR; + uint8_t RESERVED5[3]; + __IO uint8_t APBC2_PSR; + uint8_t RESERVED6[3]; + __IO uint8_t SWC_PSR; + uint8_t RESERVED7[7]; + __IO uint8_t TTC_PSR; + uint8_t RESERVED8[7]; + __IO uint8_t CSW_TMR; + uint8_t RESERVED9[3]; + __IO uint8_t PSW_TMR; + uint8_t RESERVED10[3]; + __IO uint8_t PLL_CTL1; + uint8_t RESERVED11[3]; + __IO uint8_t PLL_CTL2; + uint8_t RESERVED12[3]; + __IO uint16_t CSV_CTL; + uint8_t RESERVED13[2]; + __IO uint8_t CSV_STR; + uint8_t RESERVED14[3]; + __IO uint16_t FCSWH_CTL; + uint8_t RESERVED15[2]; + __IO uint16_t FCSWL_CTL; + uint8_t RESERVED16[2]; + __IO uint16_t FCSWD_CTL; + uint8_t RESERVED17[2]; + __IO uint8_t DBWDT_CTL; + uint8_t RESERVED18[11]; + __IO uint8_t INT_ENR; + uint8_t RESERVED19[3]; + __IO uint8_t INT_STR; + uint8_t RESERVED20[3]; + __IO uint8_t INT_CLR; +}FM3_CRG_TypeDef; + +/****************************************************************************** + * HWWDT_MODULE + ******************************************************************************/ +/* Hardware watchdog registers */ +typedef struct +{ + __IO uint32_t WDG_LDR; + __IO uint32_t WDG_VLR; + __IO uint8_t WDG_CTL; + uint8_t RESERVED0[3]; + __IO uint8_t WDG_ICL; + uint8_t RESERVED1[3]; + __IO uint8_t WDG_RIS; + uint8_t RESERVED2[3055]; + __IO uint32_t WDG_LCK; +}FM3_HWWDT_TypeDef; + +/****************************************************************************** + * SWWDT_MODULE + ******************************************************************************/ +/* Software watchdog registers */ +typedef struct +{ + __IO uint32_t WDOGLOAD; + __IO uint32_t WDOGVALUE; + __IO uint8_t WDOGCONTROL; + uint8_t RESERVED0[3]; + __IO uint32_t WDOGINTCLR; + __IO uint8_t WDOGRIS; + uint8_t RESERVED1[3055]; + __IO uint32_t WDOGLOCK; +}FM3_SWWDT_TypeDef; + +/****************************************************************************** + * DTIM_MODULE + ******************************************************************************/ +/* Dual timer 1/2 registers */ +typedef struct +{ + __IO uint32_t TIMER1LOAD; + __IO uint32_t TIMER1VALUE; + __IO uint32_t TIMER1CONTROL; + __IO uint32_t TIMER1INTCLR; + __IO uint32_t TIMER1RIS; + __IO uint32_t TIMER1MIS; + __IO uint32_t TIMER1BGLOAD; + uint8_t RESERVED0[4]; + __IO uint32_t TIMER2LOAD; + __IO uint32_t TIMER2VALUE; + __IO uint32_t TIMER2CONTROL; + __IO uint32_t TIMER2INTCLR; + __IO uint32_t TIMER2RIS; + __IO uint32_t TIMER2MIS; + __IO uint32_t TIMER2BGLOAD; +}FM3_DTIM_TypeDef; + +/****************************************************************************** + * MFT_FRT_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Free Running Timer registers */ +typedef struct +{ + uint8_t RESERVED0[40]; + __IO uint16_t TCCP0; + uint8_t RESERVED1[2]; + __IO uint16_t TCDT0; + uint8_t RESERVED2[2]; + __IO uint16_t TCSA0; + uint8_t RESERVED3[2]; + __IO uint16_t TCSB0; + uint8_t RESERVED4[2]; + __IO uint16_t TCCP1; + uint8_t RESERVED5[2]; + __IO uint16_t TCDT1; + uint8_t RESERVED6[2]; + __IO uint16_t TCSA1; + uint8_t RESERVED7[2]; + __IO uint16_t TCSB1; + uint8_t RESERVED8[2]; + __IO uint16_t TCCP2; + uint8_t RESERVED9[2]; + __IO uint16_t TCDT2; + uint8_t RESERVED10[2]; + __IO uint16_t TCSA2; + uint8_t RESERVED11[2]; + __IO uint16_t TCSB2; +}FM3_MFT_FRT_TypeDef; + +/****************************************************************************** + * MFT_OCU_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Output Compare Unit registers */ +typedef struct +{ + __IO uint16_t OCCP0; + uint8_t RESERVED0[2]; + __IO uint16_t OCCP1; + uint8_t RESERVED1[2]; + __IO uint16_t OCCP2; + uint8_t RESERVED2[2]; + __IO uint16_t OCCP3; + uint8_t RESERVED3[2]; + __IO uint16_t OCCP4; + uint8_t RESERVED4[2]; + __IO uint16_t OCCP5; + uint8_t RESERVED5[2]; + __IO uint8_t OCSA10; + __IO uint8_t OCSB10; + uint8_t RESERVED6[2]; + __IO uint8_t OCSA32; + __IO uint8_t OCSB32; + uint8_t RESERVED7[2]; + __IO uint8_t OCSA54; + __IO uint8_t OCSB54; + uint8_t RESERVED8[3]; + __IO uint8_t OCSC; + uint8_t RESERVED9[50]; + __IO uint8_t OCFS10; + __IO uint8_t OCFS32; + uint8_t RESERVED10[2]; + __IO uint8_t OCFS54; +}FM3_MFT_OCU_TypeDef; + +/****************************************************************************** + * MFT_WFG_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +typedef struct +{ + uint8_t RESERVED0[128]; + __IO uint16_t WFTM10; + uint8_t RESERVED1[2]; + __IO uint16_t WFTM32; + uint8_t RESERVED2[2]; + __IO uint16_t WFTM54; + uint8_t RESERVED3[2]; + __IO uint16_t WFSA10; + uint8_t RESERVED4[2]; + __IO uint16_t WFSA32; + uint8_t RESERVED5[2]; + __IO uint16_t WFSA54; + uint8_t RESERVED6[2]; + __IO uint16_t WFIR; + uint8_t RESERVED7[2]; + __IO uint16_t NZCL; +}FM3_MFT_WFG_TypeDef; + +/****************************************************************************** + * MFT_ICU_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Input Capture Unit registers */ +typedef struct +{ + uint8_t RESERVED0[96]; + __IO uint8_t ICFS10; + __IO uint8_t ICFS32; + uint8_t RESERVED1[6]; + __IO uint16_t ICCP0; + uint8_t RESERVED2[2]; + __IO uint16_t ICCP1; + uint8_t RESERVED3[2]; + __IO uint16_t ICCP2; + uint8_t RESERVED4[2]; + __IO uint16_t ICCP3; + uint8_t RESERVED5[2]; + __IO uint8_t ICSA10; + __IO uint8_t ICSB10; + uint8_t RESERVED6[2]; + __IO uint8_t ICSA32; + __IO uint8_t ICSB32; +}FM3_MFT_ICU_TypeDef; + +/****************************************************************************** + * MFT_ADCMP_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +typedef struct +{ + uint8_t RESERVED0[160]; + __IO uint16_t ACCP0; + uint8_t RESERVED1[2]; + __IO uint16_t ACCPDN0; + uint8_t RESERVED2[2]; + __IO uint16_t ACCP1; + uint8_t RESERVED3[2]; + __IO uint16_t ACCPDN1; + uint8_t RESERVED4[2]; + __IO uint16_t ACCP2; + uint8_t RESERVED5[2]; + __IO uint16_t ACCPDN2; + uint8_t RESERVED6[2]; + __IO uint8_t ACSB; + uint8_t RESERVED7[3]; + __IO uint16_t ACSA; + uint8_t RESERVED8[2]; + __IO uint16_t ATSA; +}FM3_MFT_ADCMP_TypeDef; + +/****************************************************************************** + * MFT_PPG_MODULE + ******************************************************************************/ +/* Multifunction Timer PPG registers */ +typedef struct +{ + uint8_t RESERVED0; + __IO uint8_t TTCR0; + uint8_t RESERVED1[7]; + __IO uint8_t COMP0; + uint8_t RESERVED2[2]; + __IO uint8_t COMP2; + uint8_t RESERVED3[4]; + __IO uint8_t COMP4; + uint8_t RESERVED4[2]; + __IO uint8_t COMP6; + uint8_t RESERVED5[12]; + __IO uint8_t TTCR1; + uint8_t RESERVED6[7]; + __IO uint8_t COMP1; + uint8_t RESERVED7[2]; + __IO uint8_t COMP3; + uint8_t RESERVED8[4]; + __IO uint8_t COMP5; + uint8_t RESERVED9[2]; + __IO uint8_t COMP7; + uint8_t RESERVED10[203]; + __IO uint16_t TRG; + uint8_t RESERVED11[2]; + __IO uint16_t REVC; + uint8_t RESERVED12[250]; + __IO uint8_t PPGC1; + __IO uint8_t PPGC0; + uint8_t RESERVED13[2]; + __IO uint8_t PPGC3; + __IO uint8_t PPGC2; + uint8_t RESERVED14[2]; + union { + __IO uint16_t PRL0; + struct { + __IO uint8_t PRLL0; + __IO uint8_t PRLH0; + }; + }; + uint8_t RESERVED15[2]; + union { + __IO uint16_t PRL1; + struct { + __IO uint8_t PRLL1; + __IO uint8_t PRLH1; + }; + }; + uint8_t RESERVED16[2]; + union { + __IO uint16_t PRL2; + struct { + __IO uint8_t PRLL2; + __IO uint8_t PRLH2; + }; + }; + uint8_t RESERVED17[2]; + union { + __IO uint16_t PRL3; + struct { + __IO uint8_t PRLL3; + __IO uint8_t PRLH3; + }; + }; + uint8_t RESERVED18[2]; + __IO uint8_t GATEC0; + uint8_t RESERVED19[39]; + __IO uint8_t PPGC5; + __IO uint8_t PPGC4; + uint8_t RESERVED20[2]; + __IO uint8_t PPGC7; + __IO uint8_t PPGC6; + uint8_t RESERVED21[2]; + union { + __IO uint16_t PRL4; + struct { + __IO uint8_t PRLL4; + __IO uint8_t PRLH4; + }; + }; + uint8_t RESERVED22[2]; + union { + __IO uint16_t PRL5; + struct { + __IO uint8_t PRLL5; + __IO uint8_t PRLH5; + }; + }; + uint8_t RESERVED23[2]; + union { + __IO uint16_t PRL6; + struct { + __IO uint8_t PRLL6; + __IO uint8_t PRLH6; + }; + }; + uint8_t RESERVED24[2]; + union { + __IO uint16_t PRL7; + struct { + __IO uint8_t PRLL7; + __IO uint8_t PRLH7; + }; + }; + uint8_t RESERVED25[2]; + __IO uint8_t GATEC4; + uint8_t RESERVED26[39]; + __IO uint8_t PPGC9; + __IO uint8_t PPGC8; + uint8_t RESERVED27[2]; + __IO uint8_t PPGC11; + __IO uint8_t PPGC10; + uint8_t RESERVED28[2]; + union { + __IO uint16_t PRL8; + struct { + __IO uint8_t PRLL8; + __IO uint8_t PRLH8; + }; + }; + uint8_t RESERVED29[2]; + union { + __IO uint16_t PRL9; + struct { + __IO uint8_t PRLL9; + __IO uint8_t PRLH9; + }; + }; + uint8_t RESERVED30[2]; + union { + __IO uint16_t PRL10; + struct { + __IO uint8_t PRLL10; + __IO uint8_t PRLH10; + }; + }; + uint8_t RESERVED31[2]; + union { + __IO uint16_t PRL11; + struct { + __IO uint8_t PRLL11; + __IO uint8_t PRLH11; + }; + }; + uint8_t RESERVED32[2]; + __IO uint8_t GATEC8; + uint8_t RESERVED33[39]; + __IO uint8_t PPGC13; + __IO uint8_t PPGC12; + uint8_t RESERVED34[2]; + __IO uint8_t PPGC15; + __IO uint8_t PPGC14; + uint8_t RESERVED35[2]; + union { + __IO uint16_t PRL12; + struct { + __IO uint8_t PRLL12; + __IO uint8_t PRLH12; + }; + }; + uint8_t RESERVED36[2]; + union { + __IO uint16_t PRL13; + struct { + __IO uint8_t PRLL13; + __IO uint8_t PRLH13; + }; + }; + uint8_t RESERVED37[2]; + union { + __IO uint16_t PRL14; + struct { + __IO uint8_t PRLL14; + __IO uint8_t PRLH14; + }; + }; + uint8_t RESERVED38[2]; + union { + __IO uint16_t PRL15; + struct { + __IO uint8_t PRLL15; + __IO uint8_t PRLH15; + }; + }; + uint8_t RESERVED39[2]; + __IO uint8_t GATEC12; +}FM3_MFT_PPG_TypeDef; + +/****************************************************************************** + * BT_PPG_MODULE + ******************************************************************************/ +/* Base Timer 0 PPG registers */ +typedef struct +{ + __IO uint16_t PRLL; + uint8_t RESERVED0[2]; + __IO uint16_t PRLH; + uint8_t RESERVED1[2]; + __IO uint16_t TMR; + uint8_t RESERVED2[2]; + __IO uint16_t TMCR; + uint8_t RESERVED3[2]; + __IO uint8_t STC; + __IO uint8_t TMCR2; +}FM3_BT_PPG_TypeDef; + +/****************************************************************************** + * BT_PWM_MODULE + ******************************************************************************/ +/* Base Timer 0 PWM registers */ +typedef struct +{ + __IO uint16_t PCSR; + uint8_t RESERVED0[2]; + __IO uint16_t PDUT; + uint8_t RESERVED1[2]; + __IO uint16_t TMR; + uint8_t RESERVED2[2]; + __IO uint16_t TMCR; + uint8_t RESERVED3[2]; + __IO uint8_t STC; + __IO uint8_t TMCR2; +}FM3_BT_PWM_TypeDef; + +/****************************************************************************** + * BT_RT_MODULE + ******************************************************************************/ +/* Base Timer 0 RT registers */ +typedef struct +{ + __IO uint16_t PCSR; + uint8_t RESERVED0[6]; + __IO uint16_t TMR; + uint8_t RESERVED1[2]; + __IO uint16_t TMCR; + uint8_t RESERVED2[2]; + __IO uint8_t STC; + __IO uint8_t TMCR2; +}FM3_BT_RT_TypeDef; + +/****************************************************************************** + * BT_PWC_MODULE + ******************************************************************************/ +/* Base Timer 0 PWC registers */ +typedef struct +{ + uint8_t RESERVED0[4]; + __IO uint16_t DTBF; + uint8_t RESERVED1[6]; + __IO uint16_t TMCR; + uint8_t RESERVED2[2]; + __IO uint8_t STC; + __IO uint8_t TMCR2; +}FM3_BT_PWC_TypeDef; + +/****************************************************************************** + * BTIOSEL03_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 0 - channel 3 registers */ +typedef struct +{ + uint8_t RESERVED0; + __IO uint8_t BTSEL0123; +}FM3_BTIOSEL03_TypeDef; + +/****************************************************************************** + * BTIOSEL47_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 4 - channel 7 registers */ +typedef struct +{ + uint8_t RESERVED0; + __IO uint8_t BTSEL4567; +}FM3_BTIOSEL47_TypeDef; + +/****************************************************************************** + * SBSSR_MODULE + ******************************************************************************/ +/* Software based Simulation Startup (Base Timer) register */ +typedef struct +{ + __IO uint16_t BTSSSR; +}FM3_SBSSR_TypeDef; + +/****************************************************************************** + * QPRC_MODULE + ******************************************************************************/ +/* Quad position and revolution counter channel 0 registers */ +typedef struct +{ + __IO uint16_t QPCR; + uint8_t RESERVED0[2]; + __IO uint16_t QRCR; + uint8_t RESERVED1[2]; + __IO uint16_t QPCCR; + uint8_t RESERVED2[2]; + __IO uint16_t QPRCR; + uint8_t RESERVED3[2]; + __IO uint16_t QMPR; + uint8_t RESERVED4[2]; + union { + __IO uint16_t QICR; + struct { + __IO uint8_t QICRL; + __IO uint8_t QICRH; + }; + }; + uint8_t RESERVED5[2]; + union { + __IO uint16_t QCR; + struct { + __IO uint8_t QCRL; + __IO uint8_t QCRH; + }; + }; + uint8_t RESERVED6[2]; + __IO uint16_t QECR; +}FM3_QPRC_TypeDef; + +/****************************************************************************** + * ADC12_MODULE + ******************************************************************************/ +/* 12-bit ADC unit 0 registers */ +typedef struct +{ + __IO uint8_t ADSR; + __IO uint8_t ADCR; + uint8_t RESERVED0[6]; + __IO uint8_t SFNS; + __IO uint8_t SCCR; + uint8_t RESERVED1[2]; + union { + __IO uint32_t SCFD; + struct { + __IO uint16_t SCFDL; + __IO uint16_t SCFDH; + }; + }; + union { + __IO uint16_t SCIS23; + struct { + __IO uint8_t SCIS2; + __IO uint8_t SCIS3; + }; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t SCIS01; + struct { + __IO uint8_t SCIS0; + __IO uint8_t SCIS1; + }; + }; + uint8_t RESERVED3[2]; + __IO uint8_t PFNS; + __IO uint8_t PCCR; + uint8_t RESERVED4[2]; + union { + __IO uint32_t PCFD; + struct { + __IO uint16_t PCFDL; + __IO uint16_t PCFDH; + }; + }; + __IO uint8_t PCIS; + uint8_t RESERVED5[3]; + __IO uint8_t CMPCR; + uint8_t RESERVED6; + __IO uint16_t CMPD; + union { + __IO uint16_t ADSS23; + struct { + __IO uint8_t ADSS2; + __IO uint8_t ADSS3; + }; + }; + uint8_t RESERVED7[2]; + union { + __IO uint16_t ADSS01; + struct { + __IO uint8_t ADSS0; + __IO uint8_t ADSS1; + }; + }; + uint8_t RESERVED8[2]; + union { + __IO uint16_t ADST01; + struct { + __IO uint8_t ADST1; + __IO uint8_t ADST0; + }; + }; + uint8_t RESERVED9[2]; + __IO uint8_t ADCT; + uint8_t RESERVED10[3]; + __IO uint8_t PRTSL; + __IO uint8_t SCTSL; + uint8_t RESERVED11[2]; + __IO uint8_t ADCEN; +}FM3_ADC_TypeDef; + +/****************************************************************************** + * CRTRIM_MODULE + ******************************************************************************/ +/* CR trimming registers */ +typedef struct +{ + __IO uint8_t MCR_PSR; + uint8_t RESERVED0[3]; + __IO uint16_t MCR_FTRM; + uint8_t RESERVED1[6]; + __IO uint32_t MCR_RLR; +}FM3_CRTRIM_TypeDef; + +/****************************************************************************** + * EXTI_MODULE + ******************************************************************************/ +/* External interrupt registers */ +typedef struct +{ + __IO uint16_t ENIR; + uint8_t RESERVED0[2]; + __IO uint16_t EIRR; + uint8_t RESERVED1[2]; + __IO uint16_t EICL; + uint8_t RESERVED2[2]; + __IO uint32_t ELVR; + uint8_t RESERVED3[4]; + __IO uint8_t NMIRR; + uint8_t RESERVED4[3]; + __IO uint8_t NMICL; +}FM3_EXTI_TypeDef; + +/****************************************************************************** + * INTREQ_MODULE + ******************************************************************************/ +/* Interrupt request read registers */ +typedef struct +{ + __IO uint32_t DRQSEL; + uint8_t RESERVED0[12]; + __IO uint32_t EXC02MON; + __IO uint32_t IRQ00MON; + __IO uint32_t IRQ01MON; + __IO uint32_t IRQ02MON; + __IO uint32_t IRQ03MON; + __IO uint32_t IRQ04MON; + __IO uint32_t IRQ05MON; + __IO uint32_t IRQ06MON; + __IO uint32_t IRQ07MON; + __IO uint32_t IRQ08MON; + __IO uint32_t IRQ09MON; + __IO uint32_t IRQ10MON; + __IO uint32_t IRQ11MON; + __IO uint32_t IRQ12MON; + __IO uint32_t IRQ13MON; + __IO uint32_t IRQ14MON; + __IO uint32_t IRQ15MON; + __IO uint32_t IRQ16MON; + __IO uint32_t IRQ17MON; + __IO uint32_t IRQ18MON; + __IO uint32_t IRQ19MON; + __IO uint32_t IRQ20MON; + __IO uint32_t IRQ21MON; + __IO uint32_t IRQ22MON; + __IO uint32_t IRQ23MON; + __IO uint32_t IRQ24MON; + __IO uint32_t IRQ25MON; + __IO uint32_t IRQ26MON; + __IO uint32_t IRQ27MON; + __IO uint32_t IRQ28MON; + __IO uint32_t IRQ29MON; + __IO uint32_t IRQ30MON; + __IO uint32_t IRQ31MON; + __IO uint32_t IRQ32MON; + __IO uint32_t IRQ33MON; + __IO uint32_t IRQ34MON; + __IO uint32_t IRQ35MON; + __IO uint32_t IRQ36MON; + __IO uint32_t IRQ37MON; + __IO uint32_t IRQ38MON; + __IO uint32_t IRQ39MON; + __IO uint32_t IRQ40MON; + __IO uint32_t IRQ41MON; + __IO uint32_t IRQ42MON; + __IO uint32_t IRQ43MON; + __IO uint32_t IRQ44MON; + __IO uint32_t IRQ45MON; + __IO uint32_t IRQ46MON; + __IO uint32_t IRQ47MON; +}FM3_INTREQ_TypeDef; + +/****************************************************************************** + * GPIO_MODULE + ******************************************************************************/ +/* General purpose I/O registers */ +typedef struct +{ + __IO uint32_t PFR0; + __IO uint32_t PFR1; + __IO uint32_t PFR2; + __IO uint32_t PFR3; + __IO uint32_t PFR4; + __IO uint32_t PFR5; + __IO uint32_t PFR6; + __IO uint32_t PFR7; + __IO uint32_t PFR8; + uint8_t RESERVED0[220]; + __IO uint32_t PCR0; + __IO uint32_t PCR1; + __IO uint32_t PCR2; + __IO uint32_t PCR3; + __IO uint32_t PCR4; + __IO uint32_t PCR5; + __IO uint32_t PCR6; + __IO uint32_t PCR7; + uint8_t RESERVED1[224]; + __IO uint32_t DDR0; + __IO uint32_t DDR1; + __IO uint32_t DDR2; + __IO uint32_t DDR3; + __IO uint32_t DDR4; + __IO uint32_t DDR5; + __IO uint32_t DDR6; + __IO uint32_t DDR7; + __IO uint32_t DDR8; + uint8_t RESERVED2[220]; + __IO uint32_t PDIR0; + __IO uint32_t PDIR1; + __IO uint32_t PDIR2; + __IO uint32_t PDIR3; + __IO uint32_t PDIR4; + __IO uint32_t PDIR5; + __IO uint32_t PDIR6; + __IO uint32_t PDIR7; + __IO uint32_t PDIR8; + uint8_t RESERVED3[220]; + __IO uint32_t PDOR0; + __IO uint32_t PDOR1; + __IO uint32_t PDOR2; + __IO uint32_t PDOR3; + __IO uint32_t PDOR4; + __IO uint32_t PDOR5; + __IO uint32_t PDOR6; + __IO uint32_t PDOR7; + __IO uint32_t PDOR8; + uint8_t RESERVED4[220]; + __IO uint32_t ADE; + uint8_t RESERVED5[124]; + __IO uint32_t SPSR; + uint8_t RESERVED6[124]; + __IO uint32_t EPFR00; + __IO uint32_t EPFR01; + __IO uint32_t EPFR02; + uint8_t RESERVED7[4]; + __IO uint32_t EPFR04; + __IO uint32_t EPFR05; + __IO uint32_t EPFR06; + __IO uint32_t EPFR07; + __IO uint32_t EPFR08; + __IO uint32_t EPFR09; + __IO uint32_t EPFR10; +}FM3_GPIO_TypeDef; + +/****************************************************************************** + * LVD_MODULE + ******************************************************************************/ +/* Low voltage detection registers */ +typedef struct +{ + __IO uint8_t LVD_CTL; + uint8_t RESERVED0[3]; + __IO uint8_t LVD_STR; + uint8_t RESERVED1[3]; + __IO uint8_t LVD_CLR; + uint8_t RESERVED2[3]; + __IO uint32_t LVD_RLR; + __IO uint8_t LVD_STR2; +}FM3_LVD_TypeDef; + +/****************************************************************************** + * USBCLK + ******************************************************************************/ +/* USB clock registers */ +typedef struct +{ + __IO uint8_t UCCR; + uint8_t RESERVED0[3]; + __IO uint8_t UPCR1; + uint8_t RESERVED1[3]; + __IO uint8_t UPCR2; + uint8_t RESERVED2[3]; + __IO uint8_t UPCR3; + uint8_t RESERVED3[3]; + __IO uint8_t UPCR4; + uint8_t RESERVED4[3]; + __IO uint8_t UP_STR; + uint8_t RESERVED5[3]; + __IO uint8_t UPINT_ENR; + uint8_t RESERVED6[3]; + __IO uint8_t UPINT_CLR; + uint8_t RESERVED7[3]; + __IO uint8_t UPINT_STR; + uint8_t RESERVED8[15]; + __IO uint8_t USBEN; +}FM3_USBCLK_TypeDef; + +/****************************************************************************** + * CANPRE_MODULE + ******************************************************************************/ +/* CAN prescaler register */ +typedef struct +{ + __IO uint8_t CANPRE; +}FM3_CANPRE_TypeDef; + +/****************************************************************************** + * MFS03_UART_MODULE + ******************************************************************************/ +/* UART asynchronous channel 0 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; +}FM3_MFS03_UART_TypeDef; + +/****************************************************************************** + * MFS03_CSIO_MODULE + ******************************************************************************/ +/* UART synchronous channel 0 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; +}FM3_MFS03_CSIO_TypeDef; + +/****************************************************************************** + * MFS03_LIN_MODULE + ******************************************************************************/ +/* UART LIN channel 0 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; +}FM3_MFS03_LIN_TypeDef; + +/****************************************************************************** + * MFS03_I2C_MODULE + ******************************************************************************/ +/* I2C channel 0 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t IBCR; + uint8_t RESERVED0[2]; + __IO uint8_t IBSR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[2]; + __IO uint8_t ISBA; + __IO uint8_t ISMK; +}FM3_MFS03_I2C_TypeDef; + +/****************************************************************************** + * MFS47_UART_MODULE + ******************************************************************************/ +/* UART asynchronous channel 4 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[6]; + union { + __IO uint16_t FCR; + struct { + __IO uint8_t FCR0; + __IO uint8_t FCR1; + }; + }; + uint8_t RESERVED4[2]; + union { + __IO uint16_t FBYTE; + struct { + __IO uint8_t FBYTE1; + __IO uint8_t FBYTE2; + }; + }; +}FM3_MFS47_UART_TypeDef; + +/****************************************************************************** + * MFS47_CSIO_MODULE + ******************************************************************************/ +/* UART synchronous channel 4 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[6]; + union { + __IO uint16_t FCR; + struct { + __IO uint8_t FCR0; + __IO uint8_t FCR1; + }; + }; + uint8_t RESERVED4[2]; + union { + __IO uint16_t FBYTE; + struct { + __IO uint8_t FBYTE1; + __IO uint8_t FBYTE2; + }; + }; +}FM3_MFS47_CSIO_TypeDef; + +/****************************************************************************** + * MFS47_LIN_MODULE + ******************************************************************************/ +/* UART LIN channel 4 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[6]; + union { + __IO uint16_t FCR; + struct { + __IO uint8_t FCR0; + __IO uint8_t FCR1; + }; + }; + uint8_t RESERVED4[2]; + union { + __IO uint16_t FBYTE; + struct { + __IO uint8_t FBYTE1; + __IO uint8_t FBYTE2; + }; + }; +}FM3_MFS47_LIN_TypeDef; + +/****************************************************************************** + * MFS47_I2C_MODULE + ******************************************************************************/ +/* I2C channel 4 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t IBCR; + uint8_t RESERVED0[2]; + __IO uint8_t IBSR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[2]; + __IO uint8_t ISBA; + __IO uint8_t ISMK; + uint8_t RESERVED4[2]; + union { + __IO uint16_t FCR; + struct { + __IO uint8_t FCR0; + __IO uint8_t FCR1; + }; + }; + uint8_t RESERVED5[2]; + union { + __IO uint16_t FBYTE; + struct { + __IO uint8_t FBYTE1; + __IO uint8_t FBYTE2; + }; + }; +}FM3_MFS47_I2C_TypeDef; + +/****************************************************************************** + * CRC_MODULE + ******************************************************************************/ +/* CRC registers */ +typedef struct +{ + __IO uint8_t CRCCR; + uint8_t RESERVED0[3]; + __IO uint32_t CRCINIT; + union { + __IO uint32_t CRCIN; + struct { + union { + __IO uint16_t CRCINL; + struct { + __IO uint8_t CRCINLL; + __IO uint8_t CRCINLH; + }; + }; + union { + __IO uint16_t CRCINH; + struct { + __IO uint8_t CRCINHL; + __IO uint8_t CRCINHH; + }; + }; + }; + }; + __IO uint32_t CRCR; +}FM3_CRC_TypeDef; + +/****************************************************************************** + * WC_MODULE + ******************************************************************************/ +/* Watch counter registers */ +typedef struct +{ + __IO uint8_t WCRD; + __IO uint8_t WCRL; + __IO uint8_t WCCR; + uint8_t RESERVED0[13]; + __IO uint16_t CLK_SEL; + uint8_t RESERVED1[2]; + __IO uint8_t CLK_EN; +}FM3_WC_TypeDef; + +/****************************************************************************** + * EXBUS_MODULE + ******************************************************************************/ +/* External bus interface registers */ +typedef struct +{ + __IO uint32_t MODE0; + __IO uint32_t MODE1; + __IO uint32_t MODE2; + __IO uint32_t MODE3; + __IO uint32_t MODE4; + __IO uint32_t MODE5; + __IO uint32_t MODE6; + __IO uint32_t MODE7; + __IO uint32_t TIM0; + __IO uint32_t TIM1; + __IO uint32_t TIM2; + __IO uint32_t TIM3; + __IO uint32_t TIM4; + __IO uint32_t TIM5; + __IO uint32_t TIM6; + __IO uint32_t TIM7; + __IO uint32_t AREA0; + __IO uint32_t AREA1; + __IO uint32_t AREA2; + __IO uint32_t AREA3; + __IO uint32_t AREA4; + __IO uint32_t AREA5; + __IO uint32_t AREA6; + __IO uint32_t AREA7; +}FM3_EXBUS_TypeDef; + +/****************************************************************************** + * USB_MODULE + ******************************************************************************/ +/* USB channel 0 registers */ +typedef struct +{ + union { + __IO uint16_t HCNT; + struct { + __IO uint8_t HCNT0; + __IO uint8_t HCNT1; + }; + }; + uint8_t RESERVED0[2]; + __IO uint8_t HIRQ; + __IO uint8_t HERR; + uint8_t RESERVED1[2]; + __IO uint8_t HSTATE; + __IO uint8_t HFCOMP; + uint8_t RESERVED2[2]; + union { + __IO uint16_t HRTIMER; + struct { + __IO uint8_t HRTIMER0; + __IO uint8_t HRTIMER1; + }; + }; + uint8_t RESERVED3[2]; + __IO uint8_t HRTIMER2; + __IO uint8_t HADR; + uint8_t RESERVED4[2]; + union { + __IO uint16_t HEOF; + struct { + __IO uint8_t HEOF0; + __IO uint8_t HEOF1; + }; + }; + uint8_t RESERVED5[2]; + union { + __IO uint16_t HFRAME; + struct { + __IO uint8_t HFRAME0; + __IO uint8_t HFRAME1; + }; + }; + uint8_t RESERVED6[2]; + __IO uint8_t HTOKEN; + uint8_t RESERVED7[3]; + __IO uint16_t UDCC; + uint8_t RESERVED8[2]; + __IO uint16_t EP0C; + uint8_t RESERVED9[2]; + __IO uint16_t EP1C; + uint8_t RESERVED10[2]; + __IO uint16_t EP2C; + uint8_t RESERVED11[2]; + __IO uint16_t EP3C; + uint8_t RESERVED12[2]; + __IO uint16_t EP4C; + uint8_t RESERVED13[2]; + __IO uint16_t EP5C; + uint8_t RESERVED14[2]; + __IO uint16_t TMSP; + uint8_t RESERVED15[2]; + __IO uint8_t UDCS; + __IO uint8_t UDCIE; + uint8_t RESERVED16[2]; + __IO uint16_t EP0IS; + uint8_t RESERVED17[2]; + __IO uint16_t EP0OS; + uint8_t RESERVED18[2]; + __IO uint16_t EP1S; + uint8_t RESERVED19[2]; + __IO uint16_t EP2S; + uint8_t RESERVED20[2]; + __IO uint16_t EP3S; + uint8_t RESERVED21[2]; + __IO uint16_t EP4S; + uint8_t RESERVED22[2]; + __IO uint16_t EP5S; + uint8_t RESERVED23[2]; + union { + __IO uint16_t EP0DT; + struct { + __IO uint8_t EP0DTL; + __IO uint8_t EP0DTH; + }; + }; + uint8_t RESERVED24[2]; + union { + __IO uint16_t EP1DT; + struct { + __IO uint8_t EP1DTL; + __IO uint8_t EP1DTH; + }; + }; + uint8_t RESERVED25[2]; + union { + __IO uint16_t EP2DT; + struct { + __IO uint8_t EP2DTL; + __IO uint8_t EP2DTH; + }; + }; + uint8_t RESERVED26[2]; + union { + __IO uint16_t EP3DT; + struct { + __IO uint8_t EP3DTL; + __IO uint8_t EP3DTH; + }; + }; + uint8_t RESERVED27[2]; + union { + __IO uint16_t EP4DT; + struct { + __IO uint8_t EP4DTL; + __IO uint8_t EP4DTH; + }; + }; + uint8_t RESERVED28[2]; + union { + __IO uint16_t EP5DT; + struct { + __IO uint8_t EP5DTL; + __IO uint8_t EP5DTH; + }; + }; +}FM3_USB_TypeDef; + +/****************************************************************************** + * DMAC_MODULE + ******************************************************************************/ +/* DMA controller */ +typedef struct +{ + __IO uint32_t DMACR; + uint8_t RESERVED0[12]; + __IO uint32_t DMACA0; + __IO uint32_t DMACB0; + __IO uint32_t DMACSA0; + __IO uint32_t DMACDA0; + __IO uint32_t DMACA1; + __IO uint32_t DMACB1; + __IO uint32_t DMACSA1; + __IO uint32_t DMACDA1; + __IO uint32_t DMACA2; + __IO uint32_t DMACB2; + __IO uint32_t DMACSA2; + __IO uint32_t DMACDA2; + __IO uint32_t DMACA3; + __IO uint32_t DMACB3; + __IO uint32_t DMACSA3; + __IO uint32_t DMACDA3; + __IO uint32_t DMACA4; + __IO uint32_t DMACB4; + __IO uint32_t DMACSA4; + __IO uint32_t DMACDA4; + __IO uint32_t DMACA5; + __IO uint32_t DMACB5; + __IO uint32_t DMACSA5; + __IO uint32_t DMACDA5; + __IO uint32_t DMACA6; + __IO uint32_t DMACB6; + __IO uint32_t DMACSA6; + __IO uint32_t DMACDA6; + __IO uint32_t DMACA7; + __IO uint32_t DMACB7; + __IO uint32_t DMACSA7; + __IO uint32_t DMACDA7; +}FM3_DMAC_TypeDef; + +/****************************************************************************** + * CAN_MODULE + ******************************************************************************/ +/* CAN channel 0 registers */ +typedef struct +{ + __IO uint16_t CTRLR; + __IO uint16_t STATR; + __IO uint16_t ERRCNT; + __IO uint16_t BTR; + __IO uint16_t INTR; + __IO uint16_t TESTR; + __IO uint16_t BRPER; + uint8_t RESERVED0[2]; + __IO uint16_t IF1CREQ; + __IO uint16_t IF1CMSK; + union { + __IO uint32_t IF1MSK; + struct { + __IO uint16_t IF1MSK1; + __IO uint16_t IF1MSK2; + }; + }; + union { + __IO uint32_t IF1ARB; + struct { + __IO uint16_t IF1ARB1; + __IO uint16_t IF1ARB2; + }; + }; + __IO uint16_t IF1MCTR; + uint8_t RESERVED1[2]; + union { + __IO uint32_t IF1DTA_L; + struct { + __IO uint16_t IF1DTA1_L; + __IO uint16_t IF1DTA2_L; + }; + }; + union { + __IO uint32_t IF1DTB_L; + struct { + __IO uint16_t IF1DTB1_L; + __IO uint16_t IF1DTB2_L; + }; + }; + uint8_t RESERVED2[8]; + union { + __IO uint32_t IF1DTA_B; + struct { + __IO uint16_t IF1DTA2_B; + __IO uint16_t IF1DTA1_B; + }; + }; + union { + __IO uint32_t IF1DTB_B; + struct { + __IO uint16_t IF1DTB2_B; + __IO uint16_t IF1DTB1_B; + }; + }; + uint8_t RESERVED3[8]; + __IO uint16_t IF2CREQ; + __IO uint16_t IF2CMSK; + union { + __IO uint32_t IF2MSK; + struct { + __IO uint16_t IF2MSK1; + __IO uint16_t IF2MSK2; + }; + }; + union { + __IO uint32_t IF2ARB; + struct { + __IO uint16_t IF2ARB1; + __IO uint16_t IF2ARB2; + }; + }; + __IO uint16_t IF2MCTR; + uint8_t RESERVED4[2]; + union { + __IO uint32_t IF2DTA_L; + struct { + __IO uint16_t IF2DTA1_L; + __IO uint16_t IF2DTA2_L; + }; + }; + union { + __IO uint32_t IF2DTB_L; + struct { + __IO uint16_t IF2DTB1_L; + __IO uint16_t IF2DTB2_L; + }; + }; + uint8_t RESERVED5[8]; + union { + __IO uint32_t IF2DTA_B; + struct { + __IO uint16_t IF2DTA2_B; + __IO uint16_t IF2DTA1_B; + }; + }; + union { + __IO uint32_t IF2DTB_B; + struct { + __IO uint16_t IF2DTB2_B; + __IO uint16_t IF2DTB1_B; + }; + }; + uint8_t RESERVED6[24]; + union { + __IO uint32_t TREQR; + struct { + __IO uint16_t TREQR1; + __IO uint16_t TREQR2; + }; + }; + uint8_t RESERVED7[12]; + union { + __IO uint32_t NEWDT; + struct { + __IO uint16_t NEWDT1; + __IO uint16_t NEWDT2; + }; + }; + uint8_t RESERVED8[12]; + union { + __IO uint32_t INTPND; + struct { + __IO uint16_t INTPND1; + __IO uint16_t INTPND2; + }; + }; + uint8_t RESERVED9[12]; + union { + __IO uint32_t MSGVAL; + struct { + __IO uint16_t MSGVAL1; + __IO uint16_t MSGVAL2; + }; + }; +}FM3_CAN_TypeDef; + + +/****************************************************************************** + * Peripheral memory map + ******************************************************************************/ +#define FM3_FLASH_BASE (0x00000000UL) /* Flash Base */ +#define FM3_PERIPH_BASE (0x40000000UL) /* Peripheral Base */ +#define FM3_CM3_BASE (0xE0100000UL) /* CM3 Private */ + +#define FM3_FLASH_IF_BASE (FM3_PERIPH_BASE + 0x00000UL) /* Flash interface registers */ +#define FM3_CRG_BASE (FM3_PERIPH_BASE + 0x10000UL) /* Clock and reset registers */ +#define FM3_HWWDT_BASE (FM3_PERIPH_BASE + 0x11000UL) /* Hardware watchdog registers */ +#define FM3_SWWDT_BASE (FM3_PERIPH_BASE + 0x12000UL) /* Software watchdog registers */ +#define FM3_DTIM_BASE (FM3_PERIPH_BASE + 0x15000UL) /* Dual timer 1/2 registers */ +#define FM3_MFT0_FRT_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Free Running Timer registers */ +#define FM3_MFT0_OCU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Output Compare Unit registers */ +#define FM3_MFT0_WFG_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +#define FM3_MFT0_ICU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Input Capture Unit registers */ +#define FM3_MFT0_ADCMP_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +#define FM3_MFT1_FRT_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Free Running Timer registers */ +#define FM3_MFT1_OCU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Output Compare Unit registers */ +#define FM3_MFT1_WFG_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ +#define FM3_MFT1_ICU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Input Capture Unit registers */ +#define FM3_MFT1_ADCMP_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 ADC Start Compare Unit registers */ +#define FM3_MFT_PPG_BASE (FM3_PERIPH_BASE + 0x24000UL) /* Multifunction Timer PPG registers */ +#define FM3_BT0_PPG_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PPG registers */ +#define FM3_BT0_PWM_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWM registers */ +#define FM3_BT0_RT_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 RT registers */ +#define FM3_BT0_PWC_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWC registers */ +#define FM3_BT1_PPG_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PPG registers */ +#define FM3_BT1_PWM_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWM registers */ +#define FM3_BT1_RT_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 RT registers */ +#define FM3_BT1_PWC_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWC registers */ +#define FM3_BT2_PPG_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PPG registers */ +#define FM3_BT2_PWM_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWM registers */ +#define FM3_BT2_RT_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 RT registers */ +#define FM3_BT2_PWC_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWC registers */ +#define FM3_BT3_PPG_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PPG registers */ +#define FM3_BT3_PWM_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWM registers */ +#define FM3_BT3_RT_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 RT registers */ +#define FM3_BT3_PWC_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWC registers */ +#define FM3_BT4_PPG_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PPG registers */ +#define FM3_BT4_PWM_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWM registers */ +#define FM3_BT4_RT_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 RT registers */ +#define FM3_BT4_PWC_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWC registers */ +#define FM3_BT5_PPG_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PPG registers */ +#define FM3_BT5_PWM_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWM registers */ +#define FM3_BT5_RT_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 RT registers */ +#define FM3_BT5_PWC_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWC registers */ +#define FM3_BT6_PPG_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PPG registers */ +#define FM3_BT6_PWM_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWM registers */ +#define FM3_BT6_RT_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 RT registers */ +#define FM3_BT6_PWC_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWC registers */ +#define FM3_BT7_PPG_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PPG registers */ +#define FM3_BT7_PWM_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWM registers */ +#define FM3_BT7_RT_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 RT registers */ +#define FM3_BT7_PWC_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWC registers */ +#define FM3_BTIOSEL03_BASE (FM3_PERIPH_BASE + 0x25100UL) /* Base Timer I/O selector channel 0 - channel 3 registers */ +#define FM3_BTIOSEL47_BASE (FM3_PERIPH_BASE + 0x25300UL) /* Base Timer I/O selector channel 4 - channel 7 registers */ +#define FM3_SBSSR_BASE (FM3_PERIPH_BASE + 0x25FFCUL) /* Software based Simulation Startup (Base Timer) register */ +#define FM3_QPRC0_BASE (FM3_PERIPH_BASE + 0x26000UL) /* Quad position and revolution counter channel 0 registers */ +#define FM3_QPRC1_BASE (FM3_PERIPH_BASE + 0x26040UL) /* Quad position and revolution counter channel 1 registers */ +#define FM3_ADC0_BASE (FM3_PERIPH_BASE + 0x27000UL) /* 12-bit ADC unit 0 registers */ +#define FM3_ADC1_BASE (FM3_PERIPH_BASE + 0x27100UL) /* 12-bit ADC unit 1 registers */ +#define FM3_ADC2_BASE (FM3_PERIPH_BASE + 0x27200UL) /* 12-bit ADC unit 2 registers */ +#define FM3_CRTRIM_BASE (FM3_PERIPH_BASE + 0x2E000UL) /* CR trimming registers */ +#define FM3_EXTI_BASE (FM3_PERIPH_BASE + 0x30000UL) /* External interrupt registers */ +#define FM3_INTREQ_BASE (FM3_PERIPH_BASE + 0x31000UL) /* Interrupt request read registers */ +#define FM3_GPIO_BASE (FM3_PERIPH_BASE + 0x33000UL) /* General purpose I/O registers */ +#define FM3_LVD_BASE (FM3_PERIPH_BASE + 0x35000UL) /* Low voltage detection registers */ +#define FM3_USBCLK_BASE (FM3_PERIPH_BASE + 0x36000UL) /* USB clock registers */ +#define FM3_CANPRES_BASE (FM3_PERIPH_BASE + 0x37000UL) /* CAN prescaler register */ +#define FM3_MFS0_UART_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART asynchronous channel 0 registers */ +#define FM3_MFS0_CSIO_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART synchronous channel 0 registers */ +#define FM3_MFS0_LIN_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART LIN channel 0 registers */ +#define FM3_MFS0_I2C_BASE (FM3_PERIPH_BASE + 0x38000UL) /* I2C channel 0 registers */ +#define FM3_MFS1_UART_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART asynchronous channel 1 registers */ +#define FM3_MFS1_CSIO_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART synchronous channel 1 registers */ +#define FM3_MFS1_LIN_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART LIN channel 1 registers */ +#define FM3_MFS1_I2C_BASE (FM3_PERIPH_BASE + 0x38100UL) /* I2C channel 1 registers */ +#define FM3_MFS2_UART_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART asynchronous channel 2 registers */ +#define FM3_MFS2_CSIO_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART synchronous channel 2 registers */ +#define FM3_MFS2_LIN_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART LIN channel 2 registers */ +#define FM3_MFS2_I2C_BASE (FM3_PERIPH_BASE + 0x38200UL) /* I2C channel 2 registers */ +#define FM3_MFS3_UART_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART asynchronous channel 3 registers */ +#define FM3_MFS3_CSIO_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART synchronous channel 3 registers */ +#define FM3_MFS3_LIN_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART LIN channel 3 registers */ +#define FM3_MFS3_I2C_BASE (FM3_PERIPH_BASE + 0x38300UL) /* I2C channel 3 registers */ +#define FM3_MFS4_UART_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART asynchronous channel 4 registers */ +#define FM3_MFS4_CSIO_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART synchronous channel 4 registers */ +#define FM3_MFS4_LIN_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART LIN channel 4 registers */ +#define FM3_MFS4_I2C_BASE (FM3_PERIPH_BASE + 0x38400UL) /* I2C channel 4 registers */ +#define FM3_MFS5_UART_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART asynchronous channel 5 registers */ +#define FM3_MFS5_CSIO_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART synchronous channel 5 registers */ +#define FM3_MFS5_LIN_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART LIN channel 5 registers */ +#define FM3_MFS5_I2C_BASE (FM3_PERIPH_BASE + 0x38500UL) /* I2C channel 5 registers */ +#define FM3_MFS6_UART_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART asynchronous channel 6 registers */ +#define FM3_MFS6_CSIO_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART synchronous channel 6 registers */ +#define FM3_MFS6_LIN_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART LIN channel 6 registers */ +#define FM3_MFS6_I2C_BASE (FM3_PERIPH_BASE + 0x38600UL) /* I2C channel 6 registers */ +#define FM3_MFS7_UART_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART asynchronous channel 7 registers */ +#define FM3_MFS7_CSIO_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART synchronous channel 7 registers */ +#define FM3_MFS7_LIN_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART LIN channel 7 registers */ +#define FM3_MFS7_I2C_BASE (FM3_PERIPH_BASE + 0x38700UL) /* I2C channel 7 registers */ +#define FM3_CRC_BASE (FM3_PERIPH_BASE + 0x39000UL) /* CRC registers */ +#define FM3_WC_BASE (FM3_PERIPH_BASE + 0x3A000UL) /* Watch counter registers */ +#define FM3_EXBUS_BASE (FM3_PERIPH_BASE + 0x3F000UL) /* External bus interface registers */ +#define FM3_USB0_BASE (FM3_PERIPH_BASE + 0x42100UL) /* USB channel 0 registers */ +#define FM3_DMAC_BASE (FM3_PERIPH_BASE + 0x60000UL) /* DMA controller */ +#define FM3_CAN0_BASE (FM3_PERIPH_BASE + 0x62000UL) /* CAN channel 0 registers */ +#define FM3_CAN1_BASE (FM3_PERIPH_BASE + 0x63000UL) /* CAN channel 1 registers */ + +/****************************************************************************** + * Peripheral declaration + ******************************************************************************/ +#define FM3_FLASH_IF ((FM3_FIF_TypeDef *)FM3_FLASH_IF_BASE) +#define FM3_CRG ((FM3_CRG_TypeDef *)FM3_CRG_BASE) +#define FM3_HWWDT ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE) +#define FM3_SWWDT ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE) +#define FM3_DTIM ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE) +#define FM3_MFT0_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE) +#define FM3_MFT0_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE) +#define FM3_MFT0_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE) +#define FM3_MFT0_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE) +#define FM3_MFT0_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE) +#define FM3_MFT1_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE) +#define FM3_MFT1_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE) +#define FM3_MFT1_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE) +#define FM3_MFT1_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE) +#define FM3_MFT1_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE) +#define FM3_MFT_PPG ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE) +#define FM3_BT0_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE) +#define FM3_BT0_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE) +#define FM3_BT0_RT ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE) +#define FM3_BT0_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE) +#define FM3_BT1_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE) +#define FM3_BT1_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE) +#define FM3_BT1_RT ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE) +#define FM3_BT1_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE) +#define FM3_BT2_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE) +#define FM3_BT2_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE) +#define FM3_BT2_RT ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE) +#define FM3_BT2_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE) +#define FM3_BT3_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE) +#define FM3_BT3_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE) +#define FM3_BT3_RT ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE) +#define FM3_BT3_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE) +#define FM3_BT4_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE) +#define FM3_BT4_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE) +#define FM3_BT4_RT ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE) +#define FM3_BT4_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE) +#define FM3_BT5_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE) +#define FM3_BT5_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE) +#define FM3_BT5_RT ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE) +#define FM3_BT5_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE) +#define FM3_BT6_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE) +#define FM3_BT6_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE) +#define FM3_BT6_RT ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE) +#define FM3_BT6_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE) +#define FM3_BT7_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE) +#define FM3_BT7_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE) +#define FM3_BT7_RT ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE) +#define FM3_BT7_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE) +#define FM3_BTIOSEL03 ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE) +#define FM3_BTIOSEL47 ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE) +#define FM3_SBSSR ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE) +#define FM3_QPRC0 ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE) +#define FM3_QPRC1 ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE) +#define FM3_ADC0 ((FM3_ADC_TypeDef *)FM3_ADC0_BASE) +#define FM3_ADC1 ((FM3_ADC_TypeDef *)FM3_ADC1_BASE) +#define FM3_ADC2 ((FM3_ADC_TypeDef *)FM3_ADC2_BASE) +#define FM3_CRTRIM ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE) +#define FM3_EXTI ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE) +#define FM3_INTREQ ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE) +#define FM3_GPIO ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE) +#define FM3_LVD ((FM3_LVD_TypeDef *)FM3_LVD_BASE) +#define FM3_USBCLK ((FM3_USBCLK_TypeDef *)FM3_USBCLK_BASE) +#define FM3_CANPRES ((FM3_CANPRE_TypeDef *)FM3_CANPRES_BASE) +#define FM3_MFS0_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE) +#define FM3_MFS0_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE) +#define FM3_MFS0_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE) +#define FM3_MFS0_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE) +#define FM3_MFS1_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE) +#define FM3_MFS1_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE) +#define FM3_MFS1_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE) +#define FM3_MFS1_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE) +#define FM3_MFS2_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE) +#define FM3_MFS2_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE) +#define FM3_MFS2_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE) +#define FM3_MFS2_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE) +#define FM3_MFS3_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE) +#define FM3_MFS3_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE) +#define FM3_MFS3_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE) +#define FM3_MFS3_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE) +#define FM3_MFS4_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE) +#define FM3_MFS4_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE) +#define FM3_MFS4_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE) +#define FM3_MFS4_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE) +#define FM3_MFS5_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE) +#define FM3_MFS5_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE) +#define FM3_MFS5_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE) +#define FM3_MFS5_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE) +#define FM3_MFS6_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE) +#define FM3_MFS6_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE) +#define FM3_MFS6_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE) +#define FM3_MFS6_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE) +#define FM3_MFS7_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE) +#define FM3_MFS7_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE) +#define FM3_MFS7_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE) +#define FM3_MFS7_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE) +#define FM3_CRC ((FM3_CRC_TypeDef *)FM3_CRC_BASE) +#define FM3_WC ((FM3_WC_TypeDef *)FM3_WC_BASE) +#define FM3_EXBUS ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE) +#define FM3_USB0 ((FM3_USB_TypeDef *)FM3_USB0_BASE) +#define FM3_DMAC ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE) +#define FM3_CAN0 ((FM3_CAN_TypeDef *)FM3_CAN0_BASE) +#define FM3_CAN1 ((FM3_CAN_TypeDef *)FM3_CAN1_BASE) + +/****************************************************************************** + * Peripheral Bit Band Alias declaration + ******************************************************************************/ + +/* Flash interface registers */ +#define bFM3_FLASH_IF_FASZR_ASZ0 *((volatile unsigned int*)(0x42000000UL)) +#define bFM3_FLASH_IF_FASZR_ASZ1 *((volatile unsigned int*)(0x42000004UL)) +#define bFM3_FLASH_IF_FRWTR_RWT0 *((volatile unsigned int*)(0x42000080UL)) +#define bFM3_FLASH_IF_FRWTR_RWT1 *((volatile unsigned int*)(0x42000084UL)) +#define bFM3_FLASH_IF_FSTR_RDY *((volatile unsigned int*)(0x42000100UL)) +#define bFM3_FLASH_IF_FSTR_HNG *((volatile unsigned int*)(0x42000104UL)) +#define bFM3_FLASH_IF_FSYNDN_SD0 *((volatile unsigned int*)(0x42000200UL)) +#define bFM3_FLASH_IF_FSYNDN_SD1 *((volatile unsigned int*)(0x42000204UL)) +#define bFM3_FLASH_IF_FSYNDN_SD2 *((volatile unsigned int*)(0x42000208UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM0 *((volatile unsigned int*)(0x42002000UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM1 *((volatile unsigned int*)(0x42002004UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM2 *((volatile unsigned int*)(0x42002008UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM3 *((volatile unsigned int*)(0x4200200CUL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM4 *((volatile unsigned int*)(0x42002010UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM5 *((volatile unsigned int*)(0x42002014UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM6 *((volatile unsigned int*)(0x42002018UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM7 *((volatile unsigned int*)(0x4200201CUL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM8 *((volatile unsigned int*)(0x42002020UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM9 *((volatile unsigned int*)(0x42002024UL)) + +/* Clock and reset registers */ +#define bFM3_CRG_SCM_CTL_MOSCE *((volatile unsigned int*)(0x42200004UL)) +#define bFM3_CRG_SCM_CTL_SOSCE *((volatile unsigned int*)(0x4220000CUL)) +#define bFM3_CRG_SCM_CTL_PLLE *((volatile unsigned int*)(0x42200010UL)) +#define bFM3_CRG_SCM_CTL_RCS0 *((volatile unsigned int*)(0x42200014UL)) +#define bFM3_CRG_SCM_CTL_RCS1 *((volatile unsigned int*)(0x42200018UL)) +#define bFM3_CRG_SCM_CTL_RCS2 *((volatile unsigned int*)(0x4220001CUL)) +#define bFM3_CRG_SCM_STR_MORDY *((volatile unsigned int*)(0x42200084UL)) +#define bFM3_CRG_SCM_STR_SORDY *((volatile unsigned int*)(0x4220008CUL)) +#define bFM3_CRG_SCM_STR_PLRDY *((volatile unsigned int*)(0x42200090UL)) +#define bFM3_CRG_SCM_STR_RCM0 *((volatile unsigned int*)(0x42200094UL)) +#define bFM3_CRG_SCM_STR_RCM1 *((volatile unsigned int*)(0x42200098UL)) +#define bFM3_CRG_SCM_STR_RCM2 *((volatile unsigned int*)(0x4220009CUL)) +#define bFM3_CRG_RST_STR_PONR *((volatile unsigned int*)(0x42200180UL)) +#define bFM3_CRG_RST_STR_INITX *((volatile unsigned int*)(0x42200184UL)) +#define bFM3_CRG_RST_STR_SWDT *((volatile unsigned int*)(0x42200190UL)) +#define bFM3_CRG_RST_STR_HWDT *((volatile unsigned int*)(0x42200194UL)) +#define bFM3_CRG_RST_STR_CSVR *((volatile unsigned int*)(0x42200198UL)) +#define bFM3_CRG_RST_STR_FCSR *((volatile unsigned int*)(0x4220019CUL)) +#define bFM3_CRG_RST_STR_SRST *((volatile unsigned int*)(0x422001A0UL)) +#define bFM3_CRG_BSC_PSR_BSR0 *((volatile unsigned int*)(0x42200200UL)) +#define bFM3_CRG_BSC_PSR_BSR1 *((volatile unsigned int*)(0x42200204UL)) +#define bFM3_CRG_BSC_PSR_BSR2 *((volatile unsigned int*)(0x42200208UL)) +#define bFM3_CRG_APBC0_PSR_APBC00 *((volatile unsigned int*)(0x42200280UL)) +#define bFM3_CRG_APBC0_PSR_APBC01 *((volatile unsigned int*)(0x42200284UL)) +#define bFM3_CRG_APBC1_PSR_APBC10 *((volatile unsigned int*)(0x42200300UL)) +#define bFM3_CRG_APBC1_PSR_APBC11 *((volatile unsigned int*)(0x42200304UL)) +#define bFM3_CRG_APBC1_PSR_APBC1RST *((volatile unsigned int*)(0x42200310UL)) +#define bFM3_CRG_APBC1_PSR_APBC1EN *((volatile unsigned int*)(0x4220031CUL)) +#define bFM3_CRG_APBC2_PSR_APBC20 *((volatile unsigned int*)(0x42200380UL)) +#define bFM3_CRG_APBC2_PSR_APBC21 *((volatile unsigned int*)(0x42200384UL)) +#define bFM3_CRG_APBC2_PSR_APBC2RST *((volatile unsigned int*)(0x42200390UL)) +#define bFM3_CRG_APBC2_PSR_APBC2EN *((volatile unsigned int*)(0x4220039CUL)) +#define bFM3_CRG_SWC_PSR_SWDS0 *((volatile unsigned int*)(0x42200400UL)) +#define bFM3_CRG_SWC_PSR_SWDS1 *((volatile unsigned int*)(0x42200404UL)) +#define bFM3_CRG_SWC_PSR_TESTB *((volatile unsigned int*)(0x4220041CUL)) +#define bFM3_CRG_TTC_PSR_TTC *((volatile unsigned int*)(0x42200500UL)) +#define bFM3_CRG_CSW_TMR_MOWT0 *((volatile unsigned int*)(0x42200600UL)) +#define bFM3_CRG_CSW_TMR_MOWT1 *((volatile unsigned int*)(0x42200604UL)) +#define bFM3_CRG_CSW_TMR_MOWT2 *((volatile unsigned int*)(0x42200608UL)) +#define bFM3_CRG_CSW_TMR_MOWT3 *((volatile unsigned int*)(0x4220060CUL)) +#define bFM3_CRG_CSW_TMR_SOWT0 *((volatile unsigned int*)(0x42200610UL)) +#define bFM3_CRG_CSW_TMR_SOWT1 *((volatile unsigned int*)(0x42200614UL)) +#define bFM3_CRG_CSW_TMR_SOWT2 *((volatile unsigned int*)(0x42200618UL)) +#define bFM3_CRG_PSW_TMR_POWT0 *((volatile unsigned int*)(0x42200680UL)) +#define bFM3_CRG_PSW_TMR_POWT1 *((volatile unsigned int*)(0x42200684UL)) +#define bFM3_CRG_PSW_TMR_POWT2 *((volatile unsigned int*)(0x42200688UL)) +#define bFM3_CRG_PSW_TMR_PINC *((volatile unsigned int*)(0x42200690UL)) +#define bFM3_CRG_PLL_CTL1_PLLM0 *((volatile unsigned int*)(0x42200700UL)) +#define bFM3_CRG_PLL_CTL1_PLLM1 *((volatile unsigned int*)(0x42200704UL)) +#define bFM3_CRG_PLL_CTL1_PLLM2 *((volatile unsigned int*)(0x42200708UL)) +#define bFM3_CRG_PLL_CTL1_PLLM3 *((volatile unsigned int*)(0x4220070CUL)) +#define bFM3_CRG_PLL_CTL1_PLLK0 *((volatile unsigned int*)(0x42200710UL)) +#define bFM3_CRG_PLL_CTL1_PLLK1 *((volatile unsigned int*)(0x42200714UL)) +#define bFM3_CRG_PLL_CTL1_PLLK2 *((volatile unsigned int*)(0x42200718UL)) +#define bFM3_CRG_PLL_CTL1_PLLK3 *((volatile unsigned int*)(0x4220071CUL)) +#define bFM3_CRG_PLL_CTL2_PLLN0 *((volatile unsigned int*)(0x42200780UL)) +#define bFM3_CRG_PLL_CTL2_PLLN1 *((volatile unsigned int*)(0x42200784UL)) +#define bFM3_CRG_PLL_CTL2_PLLN2 *((volatile unsigned int*)(0x42200788UL)) +#define bFM3_CRG_PLL_CTL2_PLLN3 *((volatile unsigned int*)(0x4220078CUL)) +#define bFM3_CRG_PLL_CTL2_PLLN4 *((volatile unsigned int*)(0x42200790UL)) +#define bFM3_CRG_CSV_CTL_MCSVE *((volatile unsigned int*)(0x42200800UL)) +#define bFM3_CRG_CSV_CTL_SCSVE *((volatile unsigned int*)(0x42200804UL)) +#define bFM3_CRG_CSV_CTL_FCSDE *((volatile unsigned int*)(0x42200820UL)) +#define bFM3_CRG_CSV_CTL_FCSRE *((volatile unsigned int*)(0x42200824UL)) +#define bFM3_CRG_CSV_CTL_FCD0 *((volatile unsigned int*)(0x42200830UL)) +#define bFM3_CRG_CSV_CTL_FCD1 *((volatile unsigned int*)(0x42200834UL)) +#define bFM3_CRG_CSV_CTL_FCD2 *((volatile unsigned int*)(0x42200838UL)) +#define bFM3_CRG_CSV_STR_MCMF *((volatile unsigned int*)(0x42200880UL)) +#define bFM3_CRG_CSV_STR_SCMF *((volatile unsigned int*)(0x42200884UL)) +#define bFM3_CRG_DBWDT_CTL_DPSWBE *((volatile unsigned int*)(0x42200A94UL)) +#define bFM3_CRG_DBWDT_CTL_DPHWBE *((volatile unsigned int*)(0x42200A9CUL)) +#define bFM3_CRG_INT_ENR_MCSE *((volatile unsigned int*)(0x42200C00UL)) +#define bFM3_CRG_INT_ENR_SCSE *((volatile unsigned int*)(0x42200C04UL)) +#define bFM3_CRG_INT_ENR_PCSE *((volatile unsigned int*)(0x42200C08UL)) +#define bFM3_CRG_INT_ENR_FCSE *((volatile unsigned int*)(0x42200C14UL)) +#define bFM3_CRG_INT_STR_MCSI *((volatile unsigned int*)(0x42200C80UL)) +#define bFM3_CRG_INT_STR_SCSI *((volatile unsigned int*)(0x42200C84UL)) +#define bFM3_CRG_INT_STR_PCSI *((volatile unsigned int*)(0x42200C88UL)) +#define bFM3_CRG_INT_STR_FCSI *((volatile unsigned int*)(0x42200C94UL)) +#define bFM3_CRG_INT_CLR_MCSC *((volatile unsigned int*)(0x42200D00UL)) +#define bFM3_CRG_INT_CLR_SCSC *((volatile unsigned int*)(0x42200D04UL)) +#define bFM3_CRG_INT_CLR_PCSC *((volatile unsigned int*)(0x42200D08UL)) +#define bFM3_CRG_INT_CLR_FCSC *((volatile unsigned int*)(0x42200D14UL)) + +/* Hardware watchdog registers */ +#define bFM3_HWWDT_WDG_CTL_INTEN *((volatile unsigned int*)(0x42220100UL)) +#define bFM3_HWWDT_WDG_CTL_RESEN *((volatile unsigned int*)(0x42220104UL)) +#define bFM3_HWWDT_WDG_RIS_RIS *((volatile unsigned int*)(0x42220200UL)) + +/* Software watchdog registers */ +#define bFM3_SWWDT_WDOGCONTROL_INTEN *((volatile unsigned int*)(0x42240100UL)) +#define bFM3_SWWDT_WDOGCONTROL_RESEN *((volatile unsigned int*)(0x42240104UL)) +#define bFM3_SWWDT_WDOGRIS_RIS *((volatile unsigned int*)(0x42240200UL)) + +/* Dual timer 1/2 registers */ +#define bFM3_DTIM_TIMER1CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0100UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0104UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0108UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A010CUL)) +#define bFM3_DTIM_TIMER1CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0114UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0118UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMEREN *((volatile unsigned int*)(0x422A011CUL)) +#define bFM3_DTIM_TIMER1RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0200UL)) +#define bFM3_DTIM_TIMER1MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0280UL)) +#define bFM3_DTIM_TIMER2CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0500UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0504UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0508UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A050CUL)) +#define bFM3_DTIM_TIMER2CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0514UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0518UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMEREN *((volatile unsigned int*)(0x422A051CUL)) +#define bFM3_DTIM_TIMER2RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0600UL)) +#define bFM3_DTIM_TIMER2MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0680UL)) + +/* Multifunction Timer unit 0 Free Running Timer registers */ +#define bFM3_MFT0_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42400600UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42400604UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42400608UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4240060CUL)) +#define bFM3_MFT0_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42400610UL)) +#define bFM3_MFT0_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42400614UL)) +#define bFM3_MFT0_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42400618UL)) +#define bFM3_MFT0_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4240061CUL)) +#define bFM3_MFT0_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42400620UL)) +#define bFM3_MFT0_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42400624UL)) +#define bFM3_MFT0_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42400634UL)) +#define bFM3_MFT0_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42400638UL)) +#define bFM3_MFT0_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4240063CUL)) +#define bFM3_MFT0_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42400680UL)) +#define bFM3_MFT0_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42400684UL)) +#define bFM3_MFT0_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42400688UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42400800UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42400804UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42400808UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4240080CUL)) +#define bFM3_MFT0_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42400810UL)) +#define bFM3_MFT0_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42400814UL)) +#define bFM3_MFT0_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42400818UL)) +#define bFM3_MFT0_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4240081CUL)) +#define bFM3_MFT0_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42400820UL)) +#define bFM3_MFT0_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42400824UL)) +#define bFM3_MFT0_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42400834UL)) +#define bFM3_MFT0_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42400838UL)) +#define bFM3_MFT0_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4240083CUL)) +#define bFM3_MFT0_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42400880UL)) +#define bFM3_MFT0_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42400884UL)) +#define bFM3_MFT0_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42400888UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42400A00UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42400A04UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42400A08UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42400A0CUL)) +#define bFM3_MFT0_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42400A10UL)) +#define bFM3_MFT0_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42400A14UL)) +#define bFM3_MFT0_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42400A18UL)) +#define bFM3_MFT0_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42400A1CUL)) +#define bFM3_MFT0_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42400A20UL)) +#define bFM3_MFT0_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42400A24UL)) +#define bFM3_MFT0_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42400A34UL)) +#define bFM3_MFT0_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42400A38UL)) +#define bFM3_MFT0_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42400A3CUL)) +#define bFM3_MFT0_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42400A80UL)) +#define bFM3_MFT0_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42400A84UL)) +#define bFM3_MFT0_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42400A88UL)) + +/* Multifunction Timer unit 0 Output Compare Unit registers */ +#define bFM3_MFT0_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42400300UL)) +#define bFM3_MFT0_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42400304UL)) +#define bFM3_MFT0_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42400308UL)) +#define bFM3_MFT0_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4240030CUL)) +#define bFM3_MFT0_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42400310UL)) +#define bFM3_MFT0_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42400314UL)) +#define bFM3_MFT0_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42400318UL)) +#define bFM3_MFT0_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4240031CUL)) +#define bFM3_MFT0_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42400320UL)) +#define bFM3_MFT0_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42400324UL)) +#define bFM3_MFT0_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42400330UL)) +#define bFM3_MFT0_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42400334UL)) +#define bFM3_MFT0_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42400338UL)) +#define bFM3_MFT0_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42400380UL)) +#define bFM3_MFT0_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42400384UL)) +#define bFM3_MFT0_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42400388UL)) +#define bFM3_MFT0_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4240038CUL)) +#define bFM3_MFT0_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42400390UL)) +#define bFM3_MFT0_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42400394UL)) +#define bFM3_MFT0_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42400398UL)) +#define bFM3_MFT0_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4240039CUL)) +#define bFM3_MFT0_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424003A0UL)) +#define bFM3_MFT0_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424003A4UL)) +#define bFM3_MFT0_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424003B0UL)) +#define bFM3_MFT0_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424003B4UL)) +#define bFM3_MFT0_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424003B8UL)) +#define bFM3_MFT0_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42400400UL)) +#define bFM3_MFT0_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42400404UL)) +#define bFM3_MFT0_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42400408UL)) +#define bFM3_MFT0_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4240040CUL)) +#define bFM3_MFT0_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42400410UL)) +#define bFM3_MFT0_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42400414UL)) +#define bFM3_MFT0_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42400418UL)) +#define bFM3_MFT0_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4240041CUL)) +#define bFM3_MFT0_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42400420UL)) +#define bFM3_MFT0_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42400424UL)) +#define bFM3_MFT0_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42400430UL)) +#define bFM3_MFT0_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42400434UL)) +#define bFM3_MFT0_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42400438UL)) +#define bFM3_MFT0_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424004A0UL)) +#define bFM3_MFT0_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424004A4UL)) +#define bFM3_MFT0_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424004A8UL)) +#define bFM3_MFT0_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424004ACUL)) +#define bFM3_MFT0_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424004B0UL)) +#define bFM3_MFT0_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424004B4UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42400B00UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42400B04UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42400B08UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42400B0CUL)) +#define bFM3_MFT0_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42400B10UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42400B14UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42400B18UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42400B1CUL)) +#define bFM3_MFT0_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42400B20UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42400B24UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42400B28UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42400B2CUL)) +#define bFM3_MFT0_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42400B30UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42400B34UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42400B38UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42400B3CUL)) +#define bFM3_MFT0_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42400B80UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42400B84UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42400B88UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42400B8CUL)) +#define bFM3_MFT0_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42400B90UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42400B94UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42400B98UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42400B9CUL)) + +/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +#define bFM3_MFT0_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42401180UL)) +#define bFM3_MFT0_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42401184UL)) +#define bFM3_MFT0_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42401188UL)) +#define bFM3_MFT0_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4240118CUL)) +#define bFM3_MFT0_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42401190UL)) +#define bFM3_MFT0_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42401194UL)) +#define bFM3_MFT0_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42401198UL)) +#define bFM3_MFT0_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4240119CUL)) +#define bFM3_MFT0_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424011A0UL)) +#define bFM3_MFT0_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424011A4UL)) +#define bFM3_MFT0_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424011A8UL)) +#define bFM3_MFT0_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424011ACUL)) +#define bFM3_MFT0_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424011B0UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42401200UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42401204UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42401208UL)) +#define bFM3_MFT0_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4240120CUL)) +#define bFM3_MFT0_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42401210UL)) +#define bFM3_MFT0_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42401214UL)) +#define bFM3_MFT0_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42401218UL)) +#define bFM3_MFT0_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4240121CUL)) +#define bFM3_MFT0_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42401220UL)) +#define bFM3_MFT0_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42401224UL)) +#define bFM3_MFT0_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42401228UL)) +#define bFM3_MFT0_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4240122CUL)) +#define bFM3_MFT0_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42401230UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42401280UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42401284UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42401288UL)) +#define bFM3_MFT0_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4240128CUL)) +#define bFM3_MFT0_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42401290UL)) +#define bFM3_MFT0_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42401294UL)) +#define bFM3_MFT0_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42401298UL)) +#define bFM3_MFT0_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4240129CUL)) +#define bFM3_MFT0_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424012A0UL)) +#define bFM3_MFT0_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424012A4UL)) +#define bFM3_MFT0_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424012A8UL)) +#define bFM3_MFT0_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424012ACUL)) +#define bFM3_MFT0_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424012B0UL)) +#define bFM3_MFT0_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42401300UL)) +#define bFM3_MFT0_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42401304UL)) +#define bFM3_MFT0_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42401310UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42401314UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42401318UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4240131CUL)) +#define bFM3_MFT0_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42401320UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42401324UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42401328UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4240132CUL)) +#define bFM3_MFT0_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42401330UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42401334UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42401338UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4240133CUL)) +#define bFM3_MFT0_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42401380UL)) +#define bFM3_MFT0_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42401384UL)) +#define bFM3_MFT0_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42401388UL)) +#define bFM3_MFT0_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4240138CUL)) +#define bFM3_MFT0_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42401390UL)) + +/* Multifunction Timer unit 0 Input Capture Unit registers */ +#define bFM3_MFT0_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42400C00UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42400C04UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42400C08UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42400C0CUL)) +#define bFM3_MFT0_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42400C10UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42400C14UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42400C18UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42400C1CUL)) +#define bFM3_MFT0_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42400C20UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42400C24UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42400C28UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42400C2CUL)) +#define bFM3_MFT0_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42400C30UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42400C34UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42400C38UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42400C3CUL)) +#define bFM3_MFT0_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42400F00UL)) +#define bFM3_MFT0_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42400F04UL)) +#define bFM3_MFT0_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42400F08UL)) +#define bFM3_MFT0_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42400F0CUL)) +#define bFM3_MFT0_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42400F10UL)) +#define bFM3_MFT0_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42400F14UL)) +#define bFM3_MFT0_ICU_ICSA10_IPC0 *((volatile unsigned int*)(0x42400F18UL)) +#define bFM3_MFT0_ICU_ICSA10_IPC1 *((volatile unsigned int*)(0x42400F1CUL)) +#define bFM3_MFT0_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42400F20UL)) +#define bFM3_MFT0_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42400F24UL)) +#define bFM3_MFT0_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42400F80UL)) +#define bFM3_MFT0_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42400F84UL)) +#define bFM3_MFT0_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42400F88UL)) +#define bFM3_MFT0_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42400F8CUL)) +#define bFM3_MFT0_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42400F90UL)) +#define bFM3_MFT0_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42400F94UL)) +#define bFM3_MFT0_ICU_ICSA32_IPC2 *((volatile unsigned int*)(0x42400F98UL)) +#define bFM3_MFT0_ICU_ICSA32_IPC3 *((volatile unsigned int*)(0x42400F9CUL)) +#define bFM3_MFT0_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42400FA0UL)) +#define bFM3_MFT0_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42400FA4UL)) + +/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +#define bFM3_MFT0_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42401700UL)) +#define bFM3_MFT0_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42401704UL)) +#define bFM3_MFT0_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42401708UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42401710UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42401714UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42401718UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42401780UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42401784UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42401788UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4240178CUL)) +#define bFM3_MFT0_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42401790UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42401794UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424017A0UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424017A4UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424017A8UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424017ACUL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424017B0UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424017B4UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42401800UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42401804UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42401808UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4240180CUL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42401810UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42401814UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42401820UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42401824UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42401828UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4240182CUL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42401830UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42401834UL)) + +/* Multifunction Timer unit 1 Free Running Timer registers */ +#define bFM3_MFT1_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42420600UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42420604UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42420608UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4242060CUL)) +#define bFM3_MFT1_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42420610UL)) +#define bFM3_MFT1_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42420614UL)) +#define bFM3_MFT1_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42420618UL)) +#define bFM3_MFT1_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4242061CUL)) +#define bFM3_MFT1_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42420620UL)) +#define bFM3_MFT1_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42420624UL)) +#define bFM3_MFT1_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42420634UL)) +#define bFM3_MFT1_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42420638UL)) +#define bFM3_MFT1_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4242063CUL)) +#define bFM3_MFT1_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42420680UL)) +#define bFM3_MFT1_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42420684UL)) +#define bFM3_MFT1_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42420688UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42420800UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42420804UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42420808UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4242080CUL)) +#define bFM3_MFT1_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42420810UL)) +#define bFM3_MFT1_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42420814UL)) +#define bFM3_MFT1_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42420818UL)) +#define bFM3_MFT1_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4242081CUL)) +#define bFM3_MFT1_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42420820UL)) +#define bFM3_MFT1_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42420824UL)) +#define bFM3_MFT1_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42420834UL)) +#define bFM3_MFT1_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42420838UL)) +#define bFM3_MFT1_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4242083CUL)) +#define bFM3_MFT1_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42420880UL)) +#define bFM3_MFT1_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42420884UL)) +#define bFM3_MFT1_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42420888UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42420A00UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42420A04UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42420A08UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42420A0CUL)) +#define bFM3_MFT1_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42420A10UL)) +#define bFM3_MFT1_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42420A14UL)) +#define bFM3_MFT1_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42420A18UL)) +#define bFM3_MFT1_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42420A1CUL)) +#define bFM3_MFT1_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42420A20UL)) +#define bFM3_MFT1_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42420A24UL)) +#define bFM3_MFT1_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42420A34UL)) +#define bFM3_MFT1_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42420A38UL)) +#define bFM3_MFT1_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42420A3CUL)) +#define bFM3_MFT1_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42420A80UL)) +#define bFM3_MFT1_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42420A84UL)) +#define bFM3_MFT1_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42420A88UL)) + +/* Multifunction Timer unit 1 Output Compare Unit registers */ +#define bFM3_MFT1_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42420300UL)) +#define bFM3_MFT1_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42420304UL)) +#define bFM3_MFT1_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42420308UL)) +#define bFM3_MFT1_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4242030CUL)) +#define bFM3_MFT1_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42420310UL)) +#define bFM3_MFT1_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42420314UL)) +#define bFM3_MFT1_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42420318UL)) +#define bFM3_MFT1_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4242031CUL)) +#define bFM3_MFT1_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42420320UL)) +#define bFM3_MFT1_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42420324UL)) +#define bFM3_MFT1_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42420330UL)) +#define bFM3_MFT1_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42420334UL)) +#define bFM3_MFT1_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42420338UL)) +#define bFM3_MFT1_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42420380UL)) +#define bFM3_MFT1_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42420384UL)) +#define bFM3_MFT1_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42420388UL)) +#define bFM3_MFT1_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4242038CUL)) +#define bFM3_MFT1_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42420390UL)) +#define bFM3_MFT1_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42420394UL)) +#define bFM3_MFT1_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42420398UL)) +#define bFM3_MFT1_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4242039CUL)) +#define bFM3_MFT1_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424203A0UL)) +#define bFM3_MFT1_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424203A4UL)) +#define bFM3_MFT1_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424203B0UL)) +#define bFM3_MFT1_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424203B4UL)) +#define bFM3_MFT1_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424203B8UL)) +#define bFM3_MFT1_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42420400UL)) +#define bFM3_MFT1_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42420404UL)) +#define bFM3_MFT1_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42420408UL)) +#define bFM3_MFT1_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4242040CUL)) +#define bFM3_MFT1_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42420410UL)) +#define bFM3_MFT1_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42420414UL)) +#define bFM3_MFT1_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42420418UL)) +#define bFM3_MFT1_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4242041CUL)) +#define bFM3_MFT1_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42420420UL)) +#define bFM3_MFT1_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42420424UL)) +#define bFM3_MFT1_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42420430UL)) +#define bFM3_MFT1_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42420434UL)) +#define bFM3_MFT1_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42420438UL)) +#define bFM3_MFT1_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424204A0UL)) +#define bFM3_MFT1_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424204A4UL)) +#define bFM3_MFT1_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424204A8UL)) +#define bFM3_MFT1_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424204ACUL)) +#define bFM3_MFT1_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424204B0UL)) +#define bFM3_MFT1_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424204B4UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42420B00UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42420B04UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42420B08UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42420B0CUL)) +#define bFM3_MFT1_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42420B10UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42420B14UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42420B18UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42420B1CUL)) +#define bFM3_MFT1_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42420B20UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42420B24UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42420B28UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42420B2CUL)) +#define bFM3_MFT1_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42420B30UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42420B34UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42420B38UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42420B3CUL)) +#define bFM3_MFT1_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42420B80UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42420B84UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42420B88UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42420B8CUL)) +#define bFM3_MFT1_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42420B90UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42420B94UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42420B98UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42420B9CUL)) + +/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ +#define bFM3_MFT1_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42421180UL)) +#define bFM3_MFT1_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42421184UL)) +#define bFM3_MFT1_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42421188UL)) +#define bFM3_MFT1_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4242118CUL)) +#define bFM3_MFT1_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42421190UL)) +#define bFM3_MFT1_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42421194UL)) +#define bFM3_MFT1_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42421198UL)) +#define bFM3_MFT1_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4242119CUL)) +#define bFM3_MFT1_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424211A0UL)) +#define bFM3_MFT1_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424211A4UL)) +#define bFM3_MFT1_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424211A8UL)) +#define bFM3_MFT1_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424211ACUL)) +#define bFM3_MFT1_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424211B0UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42421200UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42421204UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42421208UL)) +#define bFM3_MFT1_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4242120CUL)) +#define bFM3_MFT1_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42421210UL)) +#define bFM3_MFT1_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42421214UL)) +#define bFM3_MFT1_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42421218UL)) +#define bFM3_MFT1_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4242121CUL)) +#define bFM3_MFT1_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42421220UL)) +#define bFM3_MFT1_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42421224UL)) +#define bFM3_MFT1_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42421228UL)) +#define bFM3_MFT1_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4242122CUL)) +#define bFM3_MFT1_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42421230UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42421280UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42421284UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42421288UL)) +#define bFM3_MFT1_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4242128CUL)) +#define bFM3_MFT1_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42421290UL)) +#define bFM3_MFT1_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42421294UL)) +#define bFM3_MFT1_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42421298UL)) +#define bFM3_MFT1_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4242129CUL)) +#define bFM3_MFT1_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424212A0UL)) +#define bFM3_MFT1_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424212A4UL)) +#define bFM3_MFT1_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424212A8UL)) +#define bFM3_MFT1_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424212ACUL)) +#define bFM3_MFT1_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424212B0UL)) +#define bFM3_MFT1_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42421300UL)) +#define bFM3_MFT1_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42421304UL)) +#define bFM3_MFT1_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42421310UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42421314UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42421318UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4242131CUL)) +#define bFM3_MFT1_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42421320UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42421324UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42421328UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4242132CUL)) +#define bFM3_MFT1_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42421330UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42421334UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42421338UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4242133CUL)) +#define bFM3_MFT1_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42421380UL)) +#define bFM3_MFT1_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42421384UL)) +#define bFM3_MFT1_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42421388UL)) +#define bFM3_MFT1_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4242138CUL)) +#define bFM3_MFT1_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42421390UL)) + +/* Multifunction Timer unit 1 Input Capture Unit registers */ +#define bFM3_MFT1_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42420C00UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42420C04UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42420C08UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42420C0CUL)) +#define bFM3_MFT1_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42420C10UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42420C14UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42420C18UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42420C1CUL)) +#define bFM3_MFT1_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42420C20UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42420C24UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42420C28UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42420C2CUL)) +#define bFM3_MFT1_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42420C30UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42420C34UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42420C38UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42420C3CUL)) +#define bFM3_MFT1_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42420F00UL)) +#define bFM3_MFT1_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42420F04UL)) +#define bFM3_MFT1_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42420F08UL)) +#define bFM3_MFT1_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42420F0CUL)) +#define bFM3_MFT1_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42420F10UL)) +#define bFM3_MFT1_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42420F14UL)) +#define bFM3_MFT1_ICU_ICSA10_IPC0 *((volatile unsigned int*)(0x42420F18UL)) +#define bFM3_MFT1_ICU_ICSA10_IPC1 *((volatile unsigned int*)(0x42420F1CUL)) +#define bFM3_MFT1_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42420F20UL)) +#define bFM3_MFT1_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42420F24UL)) +#define bFM3_MFT1_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42420F80UL)) +#define bFM3_MFT1_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42420F84UL)) +#define bFM3_MFT1_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42420F88UL)) +#define bFM3_MFT1_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42420F8CUL)) +#define bFM3_MFT1_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42420F90UL)) +#define bFM3_MFT1_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42420F94UL)) +#define bFM3_MFT1_ICU_ICSA32_IPC2 *((volatile unsigned int*)(0x42420F98UL)) +#define bFM3_MFT1_ICU_ICSA32_IPC3 *((volatile unsigned int*)(0x42420F9CUL)) +#define bFM3_MFT1_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42420FA0UL)) +#define bFM3_MFT1_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42420FA4UL)) + +/* Multifunction Timer unit 1 ADC Start Compare Unit registers */ +#define bFM3_MFT1_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42421700UL)) +#define bFM3_MFT1_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42421704UL)) +#define bFM3_MFT1_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42421708UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42421710UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42421714UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42421718UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42421780UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42421784UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42421788UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4242178CUL)) +#define bFM3_MFT1_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42421790UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42421794UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424217A0UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424217A4UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424217A8UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424217ACUL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424217B0UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424217B4UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42421800UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42421804UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42421808UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4242180CUL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42421810UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42421814UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42421820UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42421824UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42421828UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4242182CUL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42421830UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42421834UL)) + +/* Multifunction Timer PPG registers */ +#define bFM3_MFT_PPG_TTCR0_STR0 *((volatile unsigned int*)(0x42480020UL)) +#define bFM3_MFT_PPG_TTCR0_MONI0 *((volatile unsigned int*)(0x42480024UL)) +#define bFM3_MFT_PPG_TTCR0_CS00 *((volatile unsigned int*)(0x42480028UL)) +#define bFM3_MFT_PPG_TTCR0_CS01 *((volatile unsigned int*)(0x4248002CUL)) +#define bFM3_MFT_PPG_TTCR0_TRG0O *((volatile unsigned int*)(0x42480030UL)) +#define bFM3_MFT_PPG_TTCR0_TRG2O *((volatile unsigned int*)(0x42480034UL)) +#define bFM3_MFT_PPG_TTCR0_TRG4O *((volatile unsigned int*)(0x42480038UL)) +#define bFM3_MFT_PPG_TTCR0_TRG6O *((volatile unsigned int*)(0x4248003CUL)) +#define bFM3_MFT_PPG_TTCR1_STR1 *((volatile unsigned int*)(0x42480420UL)) +#define bFM3_MFT_PPG_TTCR1_MONI1 *((volatile unsigned int*)(0x42480424UL)) +#define bFM3_MFT_PPG_TTCR1_CS10 *((volatile unsigned int*)(0x42480428UL)) +#define bFM3_MFT_PPG_TTCR1_CS11 *((volatile unsigned int*)(0x4248042CUL)) +#define bFM3_MFT_PPG_TTCR1_TRG1O *((volatile unsigned int*)(0x42480430UL)) +#define bFM3_MFT_PPG_TTCR1_TRG3O *((volatile unsigned int*)(0x42480434UL)) +#define bFM3_MFT_PPG_TTCR1_TRG5O *((volatile unsigned int*)(0x42480438UL)) +#define bFM3_MFT_PPG_TTCR1_TRG7O *((volatile unsigned int*)(0x4248043CUL)) +#define bFM3_MFT_PPG_TRG_PEN00 *((volatile unsigned int*)(0x42482000UL)) +#define bFM3_MFT_PPG_TRG_PEN01 *((volatile unsigned int*)(0x42482004UL)) +#define bFM3_MFT_PPG_TRG_PEN02 *((volatile unsigned int*)(0x42482008UL)) +#define bFM3_MFT_PPG_TRG_PEN03 *((volatile unsigned int*)(0x4248200CUL)) +#define bFM3_MFT_PPG_TRG_PEN04 *((volatile unsigned int*)(0x42482010UL)) +#define bFM3_MFT_PPG_TRG_PEN05 *((volatile unsigned int*)(0x42482014UL)) +#define bFM3_MFT_PPG_TRG_PEN06 *((volatile unsigned int*)(0x42482018UL)) +#define bFM3_MFT_PPG_TRG_PEN07 *((volatile unsigned int*)(0x4248201CUL)) +#define bFM3_MFT_PPG_TRG_PEN08 *((volatile unsigned int*)(0x42482020UL)) +#define bFM3_MFT_PPG_TRG_PEN09 *((volatile unsigned int*)(0x42482024UL)) +#define bFM3_MFT_PPG_TRG_PEN10 *((volatile unsigned int*)(0x42482028UL)) +#define bFM3_MFT_PPG_TRG_PEN11 *((volatile unsigned int*)(0x4248202CUL)) +#define bFM3_MFT_PPG_TRG_PEN12 *((volatile unsigned int*)(0x42482030UL)) +#define bFM3_MFT_PPG_TRG_PEN13 *((volatile unsigned int*)(0x42482034UL)) +#define bFM3_MFT_PPG_TRG_PEN14 *((volatile unsigned int*)(0x42482038UL)) +#define bFM3_MFT_PPG_TRG_PEN15 *((volatile unsigned int*)(0x4248203CUL)) +#define bFM3_MFT_PPG_REVC_REV00 *((volatile unsigned int*)(0x42482080UL)) +#define bFM3_MFT_PPG_REVC_REV01 *((volatile unsigned int*)(0x42482084UL)) +#define bFM3_MFT_PPG_REVC_REV02 *((volatile unsigned int*)(0x42482088UL)) +#define bFM3_MFT_PPG_REVC_REV03 *((volatile unsigned int*)(0x4248208CUL)) +#define bFM3_MFT_PPG_REVC_REV04 *((volatile unsigned int*)(0x42482090UL)) +#define bFM3_MFT_PPG_REVC_REV05 *((volatile unsigned int*)(0x42482094UL)) +#define bFM3_MFT_PPG_REVC_REV06 *((volatile unsigned int*)(0x42482098UL)) +#define bFM3_MFT_PPG_REVC_REV07 *((volatile unsigned int*)(0x4248209CUL)) +#define bFM3_MFT_PPG_REVC_REV08 *((volatile unsigned int*)(0x424820A0UL)) +#define bFM3_MFT_PPG_REVC_REV09 *((volatile unsigned int*)(0x424820A4UL)) +#define bFM3_MFT_PPG_REVC_REV10 *((volatile unsigned int*)(0x424820A8UL)) +#define bFM3_MFT_PPG_REVC_REV11 *((volatile unsigned int*)(0x424820ACUL)) +#define bFM3_MFT_PPG_REVC_REV12 *((volatile unsigned int*)(0x424820B0UL)) +#define bFM3_MFT_PPG_REVC_REV13 *((volatile unsigned int*)(0x424820B4UL)) +#define bFM3_MFT_PPG_REVC_REV14 *((volatile unsigned int*)(0x424820B8UL)) +#define bFM3_MFT_PPG_REVC_REV15 *((volatile unsigned int*)(0x424820BCUL)) +#define bFM3_MFT_PPG_PPGC1_TTRG *((volatile unsigned int*)(0x42484000UL)) +#define bFM3_MFT_PPG_PPGC1_MD0 *((volatile unsigned int*)(0x42484004UL)) +#define bFM3_MFT_PPG_PPGC1_MD1 *((volatile unsigned int*)(0x42484008UL)) +#define bFM3_MFT_PPG_PPGC1_PCS0 *((volatile unsigned int*)(0x4248400CUL)) +#define bFM3_MFT_PPG_PPGC1_PCS1 *((volatile unsigned int*)(0x42484010UL)) +#define bFM3_MFT_PPG_PPGC1_INTM *((volatile unsigned int*)(0x42484014UL)) +#define bFM3_MFT_PPG_PPGC1_PUF *((volatile unsigned int*)(0x42484018UL)) +#define bFM3_MFT_PPG_PPGC1_PIE *((volatile unsigned int*)(0x4248401CUL)) +#define bFM3_MFT_PPG_PPGC0_TTRG *((volatile unsigned int*)(0x42484020UL)) +#define bFM3_MFT_PPG_PPGC0_MD0 *((volatile unsigned int*)(0x42484024UL)) +#define bFM3_MFT_PPG_PPGC0_MD1 *((volatile unsigned int*)(0x42484028UL)) +#define bFM3_MFT_PPG_PPGC0_PCS0 *((volatile unsigned int*)(0x4248402CUL)) +#define bFM3_MFT_PPG_PPGC0_PCS1 *((volatile unsigned int*)(0x42484030UL)) +#define bFM3_MFT_PPG_PPGC0_INTM *((volatile unsigned int*)(0x42484034UL)) +#define bFM3_MFT_PPG_PPGC0_PUF *((volatile unsigned int*)(0x42484038UL)) +#define bFM3_MFT_PPG_PPGC0_PIE *((volatile unsigned int*)(0x4248403CUL)) +#define bFM3_MFT_PPG_PPGC3_TTRG *((volatile unsigned int*)(0x42484080UL)) +#define bFM3_MFT_PPG_PPGC3_MD0 *((volatile unsigned int*)(0x42484084UL)) +#define bFM3_MFT_PPG_PPGC3_MD1 *((volatile unsigned int*)(0x42484088UL)) +#define bFM3_MFT_PPG_PPGC3_PCS0 *((volatile unsigned int*)(0x4248408CUL)) +#define bFM3_MFT_PPG_PPGC3_PCS1 *((volatile unsigned int*)(0x42484090UL)) +#define bFM3_MFT_PPG_PPGC3_INTM *((volatile unsigned int*)(0x42484094UL)) +#define bFM3_MFT_PPG_PPGC3_PUF *((volatile unsigned int*)(0x42484098UL)) +#define bFM3_MFT_PPG_PPGC3_PIE *((volatile unsigned int*)(0x4248409CUL)) +#define bFM3_MFT_PPG_PPGC2_TTRG *((volatile unsigned int*)(0x424840A0UL)) +#define bFM3_MFT_PPG_PPGC2_MD0 *((volatile unsigned int*)(0x424840A4UL)) +#define bFM3_MFT_PPG_PPGC2_MD1 *((volatile unsigned int*)(0x424840A8UL)) +#define bFM3_MFT_PPG_PPGC2_PCS0 *((volatile unsigned int*)(0x424840ACUL)) +#define bFM3_MFT_PPG_PPGC2_PCS1 *((volatile unsigned int*)(0x424840B0UL)) +#define bFM3_MFT_PPG_PPGC2_INTM *((volatile unsigned int*)(0x424840B4UL)) +#define bFM3_MFT_PPG_PPGC2_PUF *((volatile unsigned int*)(0x424840B8UL)) +#define bFM3_MFT_PPG_PPGC2_PIE *((volatile unsigned int*)(0x424840BCUL)) +#define bFM3_MFT_PPG_GATEC0_EDGE0 *((volatile unsigned int*)(0x42484300UL)) +#define bFM3_MFT_PPG_GATEC0_STRG0 *((volatile unsigned int*)(0x42484304UL)) +#define bFM3_MFT_PPG_GATEC0_EDGE2 *((volatile unsigned int*)(0x42484310UL)) +#define bFM3_MFT_PPG_GATEC0_STRG2 *((volatile unsigned int*)(0x42484314UL)) +#define bFM3_MFT_PPG_PPGC5_TTRG *((volatile unsigned int*)(0x42484800UL)) +#define bFM3_MFT_PPG_PPGC5_MD0 *((volatile unsigned int*)(0x42484804UL)) +#define bFM3_MFT_PPG_PPGC5_MD1 *((volatile unsigned int*)(0x42484808UL)) +#define bFM3_MFT_PPG_PPGC5_PCS0 *((volatile unsigned int*)(0x4248480CUL)) +#define bFM3_MFT_PPG_PPGC5_PCS1 *((volatile unsigned int*)(0x42484810UL)) +#define bFM3_MFT_PPG_PPGC5_INTM *((volatile unsigned int*)(0x42484814UL)) +#define bFM3_MFT_PPG_PPGC5_PUF *((volatile unsigned int*)(0x42484818UL)) +#define bFM3_MFT_PPG_PPGC5_PIE *((volatile unsigned int*)(0x4248481CUL)) +#define bFM3_MFT_PPG_PPGC4_TTRG *((volatile unsigned int*)(0x42484820UL)) +#define bFM3_MFT_PPG_PPGC4_MD0 *((volatile unsigned int*)(0x42484824UL)) +#define bFM3_MFT_PPG_PPGC4_MD1 *((volatile unsigned int*)(0x42484828UL)) +#define bFM3_MFT_PPG_PPGC4_PCS0 *((volatile unsigned int*)(0x4248482CUL)) +#define bFM3_MFT_PPG_PPGC4_PCS1 *((volatile unsigned int*)(0x42484830UL)) +#define bFM3_MFT_PPG_PPGC4_INTM *((volatile unsigned int*)(0x42484834UL)) +#define bFM3_MFT_PPG_PPGC4_PUF *((volatile unsigned int*)(0x42484838UL)) +#define bFM3_MFT_PPG_PPGC4_PIE *((volatile unsigned int*)(0x4248483CUL)) +#define bFM3_MFT_PPG_PPGC7_TTRG *((volatile unsigned int*)(0x42484880UL)) +#define bFM3_MFT_PPG_PPGC7_MD0 *((volatile unsigned int*)(0x42484884UL)) +#define bFM3_MFT_PPG_PPGC7_MD1 *((volatile unsigned int*)(0x42484888UL)) +#define bFM3_MFT_PPG_PPGC7_PCS0 *((volatile unsigned int*)(0x4248488CUL)) +#define bFM3_MFT_PPG_PPGC7_PCS1 *((volatile unsigned int*)(0x42484890UL)) +#define bFM3_MFT_PPG_PPGC7_INTM *((volatile unsigned int*)(0x42484894UL)) +#define bFM3_MFT_PPG_PPGC7_PUF *((volatile unsigned int*)(0x42484898UL)) +#define bFM3_MFT_PPG_PPGC7_PIE *((volatile unsigned int*)(0x4248489CUL)) +#define bFM3_MFT_PPG_PPGC6_TTRG *((volatile unsigned int*)(0x424848A0UL)) +#define bFM3_MFT_PPG_PPGC6_MD0 *((volatile unsigned int*)(0x424848A4UL)) +#define bFM3_MFT_PPG_PPGC6_MD1 *((volatile unsigned int*)(0x424848A8UL)) +#define bFM3_MFT_PPG_PPGC6_PCS0 *((volatile unsigned int*)(0x424848ACUL)) +#define bFM3_MFT_PPG_PPGC6_PCS1 *((volatile unsigned int*)(0x424848B0UL)) +#define bFM3_MFT_PPG_PPGC6_INTM *((volatile unsigned int*)(0x424848B4UL)) +#define bFM3_MFT_PPG_PPGC6_PUF *((volatile unsigned int*)(0x424848B8UL)) +#define bFM3_MFT_PPG_PPGC6_PIE *((volatile unsigned int*)(0x424848BCUL)) +#define bFM3_MFT_PPG_GATEC4_EDGE4 *((volatile unsigned int*)(0x42484B00UL)) +#define bFM3_MFT_PPG_GATEC4_STRG4 *((volatile unsigned int*)(0x42484B04UL)) +#define bFM3_MFT_PPG_GATEC4_EDGE6 *((volatile unsigned int*)(0x42484B10UL)) +#define bFM3_MFT_PPG_GATEC4_STRG6 *((volatile unsigned int*)(0x42484B14UL)) +#define bFM3_MFT_PPG_PPGC9_TTRG *((volatile unsigned int*)(0x42485000UL)) +#define bFM3_MFT_PPG_PPGC9_MD0 *((volatile unsigned int*)(0x42485004UL)) +#define bFM3_MFT_PPG_PPGC9_MD1 *((volatile unsigned int*)(0x42485008UL)) +#define bFM3_MFT_PPG_PPGC9_PCS0 *((volatile unsigned int*)(0x4248500CUL)) +#define bFM3_MFT_PPG_PPGC9_PCS1 *((volatile unsigned int*)(0x42485010UL)) +#define bFM3_MFT_PPG_PPGC9_INTM *((volatile unsigned int*)(0x42485014UL)) +#define bFM3_MFT_PPG_PPGC9_PUF *((volatile unsigned int*)(0x42485018UL)) +#define bFM3_MFT_PPG_PPGC9_PIE *((volatile unsigned int*)(0x4248501CUL)) +#define bFM3_MFT_PPG_PPGC8_TTRG *((volatile unsigned int*)(0x42485020UL)) +#define bFM3_MFT_PPG_PPGC8_MD0 *((volatile unsigned int*)(0x42485024UL)) +#define bFM3_MFT_PPG_PPGC8_MD1 *((volatile unsigned int*)(0x42485028UL)) +#define bFM3_MFT_PPG_PPGC8_PCS0 *((volatile unsigned int*)(0x4248502CUL)) +#define bFM3_MFT_PPG_PPGC8_PCS1 *((volatile unsigned int*)(0x42485030UL)) +#define bFM3_MFT_PPG_PPGC8_INTM *((volatile unsigned int*)(0x42485034UL)) +#define bFM3_MFT_PPG_PPGC8_PUF *((volatile unsigned int*)(0x42485038UL)) +#define bFM3_MFT_PPG_PPGC8_PIE *((volatile unsigned int*)(0x4248503CUL)) +#define bFM3_MFT_PPG_PPGC11_TTRG *((volatile unsigned int*)(0x42485080UL)) +#define bFM3_MFT_PPG_PPGC11_MD0 *((volatile unsigned int*)(0x42485084UL)) +#define bFM3_MFT_PPG_PPGC11_MD1 *((volatile unsigned int*)(0x42485088UL)) +#define bFM3_MFT_PPG_PPGC11_PCS0 *((volatile unsigned int*)(0x4248508CUL)) +#define bFM3_MFT_PPG_PPGC11_PCS1 *((volatile unsigned int*)(0x42485090UL)) +#define bFM3_MFT_PPG_PPGC11_INTM *((volatile unsigned int*)(0x42485094UL)) +#define bFM3_MFT_PPG_PPGC11_PUF *((volatile unsigned int*)(0x42485098UL)) +#define bFM3_MFT_PPG_PPGC11_PIE *((volatile unsigned int*)(0x4248509CUL)) +#define bFM3_MFT_PPG_PPGC10_TTRG *((volatile unsigned int*)(0x424850A0UL)) +#define bFM3_MFT_PPG_PPGC10_MD0 *((volatile unsigned int*)(0x424850A4UL)) +#define bFM3_MFT_PPG_PPGC10_MD1 *((volatile unsigned int*)(0x424850A8UL)) +#define bFM3_MFT_PPG_PPGC10_PCS0 *((volatile unsigned int*)(0x424850ACUL)) +#define bFM3_MFT_PPG_PPGC10_PCS1 *((volatile unsigned int*)(0x424850B0UL)) +#define bFM3_MFT_PPG_PPGC10_INTM *((volatile unsigned int*)(0x424850B4UL)) +#define bFM3_MFT_PPG_PPGC10_PUF *((volatile unsigned int*)(0x424850B8UL)) +#define bFM3_MFT_PPG_PPGC10_PIE *((volatile unsigned int*)(0x424850BCUL)) +#define bFM3_MFT_PPG_GATEC8_EDGE8 *((volatile unsigned int*)(0x42485300UL)) +#define bFM3_MFT_PPG_GATEC8_STRG8 *((volatile unsigned int*)(0x42485304UL)) +#define bFM3_MFT_PPG_GATEC8_EDGE10 *((volatile unsigned int*)(0x42485310UL)) +#define bFM3_MFT_PPG_GATEC8_STRG10 *((volatile unsigned int*)(0x42485314UL)) +#define bFM3_MFT_PPG_PPGC13_TTRG *((volatile unsigned int*)(0x42485800UL)) +#define bFM3_MFT_PPG_PPGC13_MD0 *((volatile unsigned int*)(0x42485804UL)) +#define bFM3_MFT_PPG_PPGC13_MD1 *((volatile unsigned int*)(0x42485808UL)) +#define bFM3_MFT_PPG_PPGC13_PCS0 *((volatile unsigned int*)(0x4248580CUL)) +#define bFM3_MFT_PPG_PPGC13_PCS1 *((volatile unsigned int*)(0x42485810UL)) +#define bFM3_MFT_PPG_PPGC13_INTM *((volatile unsigned int*)(0x42485814UL)) +#define bFM3_MFT_PPG_PPGC13_PUF *((volatile unsigned int*)(0x42485818UL)) +#define bFM3_MFT_PPG_PPGC13_PIE *((volatile unsigned int*)(0x4248581CUL)) +#define bFM3_MFT_PPG_PPGC12_TTRG *((volatile unsigned int*)(0x42485820UL)) +#define bFM3_MFT_PPG_PPGC12_MD0 *((volatile unsigned int*)(0x42485824UL)) +#define bFM3_MFT_PPG_PPGC12_MD1 *((volatile unsigned int*)(0x42485828UL)) +#define bFM3_MFT_PPG_PPGC12_PCS0 *((volatile unsigned int*)(0x4248582CUL)) +#define bFM3_MFT_PPG_PPGC12_PCS1 *((volatile unsigned int*)(0x42485830UL)) +#define bFM3_MFT_PPG_PPGC12_INTM *((volatile unsigned int*)(0x42485834UL)) +#define bFM3_MFT_PPG_PPGC12_PUF *((volatile unsigned int*)(0x42485838UL)) +#define bFM3_MFT_PPG_PPGC12_PIE *((volatile unsigned int*)(0x4248583CUL)) +#define bFM3_MFT_PPG_PPGC15_TTRG *((volatile unsigned int*)(0x42485880UL)) +#define bFM3_MFT_PPG_PPGC15_MD0 *((volatile unsigned int*)(0x42485884UL)) +#define bFM3_MFT_PPG_PPGC15_MD1 *((volatile unsigned int*)(0x42485888UL)) +#define bFM3_MFT_PPG_PPGC15_PCS0 *((volatile unsigned int*)(0x4248588CUL)) +#define bFM3_MFT_PPG_PPGC15_PCS1 *((volatile unsigned int*)(0x42485890UL)) +#define bFM3_MFT_PPG_PPGC15_INTM *((volatile unsigned int*)(0x42485894UL)) +#define bFM3_MFT_PPG_PPGC15_PUF *((volatile unsigned int*)(0x42485898UL)) +#define bFM3_MFT_PPG_PPGC15_PIE *((volatile unsigned int*)(0x4248589CUL)) +#define bFM3_MFT_PPG_PPGC14_TTRG *((volatile unsigned int*)(0x424858A0UL)) +#define bFM3_MFT_PPG_PPGC14_MD0 *((volatile unsigned int*)(0x424858A4UL)) +#define bFM3_MFT_PPG_PPGC14_MD1 *((volatile unsigned int*)(0x424858A8UL)) +#define bFM3_MFT_PPG_PPGC14_PCS0 *((volatile unsigned int*)(0x424858ACUL)) +#define bFM3_MFT_PPG_PPGC14_PCS1 *((volatile unsigned int*)(0x424858B0UL)) +#define bFM3_MFT_PPG_PPGC14_INTM *((volatile unsigned int*)(0x424858B4UL)) +#define bFM3_MFT_PPG_PPGC14_PUF *((volatile unsigned int*)(0x424858B8UL)) +#define bFM3_MFT_PPG_PPGC14_PIE *((volatile unsigned int*)(0x424858BCUL)) +#define bFM3_MFT_PPG_GATEC12_EDGE12 *((volatile unsigned int*)(0x42485B00UL)) +#define bFM3_MFT_PPG_GATEC12_STRG12 *((volatile unsigned int*)(0x42485B04UL)) +#define bFM3_MFT_PPG_GATEC12_EDGE14 *((volatile unsigned int*)(0x42485B10UL)) +#define bFM3_MFT_PPG_GATEC12_STRG14 *((volatile unsigned int*)(0x42485B14UL)) + +/* Base Timer 0 PPG registers */ +#define bFM3_BT0_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) +#define bFM3_BT0_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 PWM registers */ +#define bFM3_BT0_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) +#define bFM3_BT0_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0204UL)) +#define bFM3_BT0_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0214UL)) +#define bFM3_BT0_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 RT registers */ +#define bFM3_BT0_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_RT_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) +#define bFM3_BT0_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_RT_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_RT_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_RT_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_RT_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 PWC registers */ +#define bFM3_BT0_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) +#define bFM3_BT0_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PWC_STC_ERR *((volatile unsigned int*)(0x424A021CUL)) +#define bFM3_BT0_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 1 PPG registers */ +#define bFM3_BT1_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) +#define bFM3_BT1_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 PWM registers */ +#define bFM3_BT1_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) +#define bFM3_BT1_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0A04UL)) +#define bFM3_BT1_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0A14UL)) +#define bFM3_BT1_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 RT registers */ +#define bFM3_BT1_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_RT_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) +#define bFM3_BT1_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_RT_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_RT_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_RT_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_RT_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 PWC registers */ +#define bFM3_BT1_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) +#define bFM3_BT1_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PWC_STC_ERR *((volatile unsigned int*)(0x424A0A1CUL)) +#define bFM3_BT1_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 2 PPG registers */ +#define bFM3_BT2_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) +#define bFM3_BT2_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 PWM registers */ +#define bFM3_BT2_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) +#define bFM3_BT2_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1204UL)) +#define bFM3_BT2_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1214UL)) +#define bFM3_BT2_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 RT registers */ +#define bFM3_BT2_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_RT_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) +#define bFM3_BT2_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_RT_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_RT_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_RT_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_RT_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 PWC registers */ +#define bFM3_BT2_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) +#define bFM3_BT2_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PWC_STC_ERR *((volatile unsigned int*)(0x424A121CUL)) +#define bFM3_BT2_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 3 PPG registers */ +#define bFM3_BT3_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) +#define bFM3_BT3_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 PWM registers */ +#define bFM3_BT3_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) +#define bFM3_BT3_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1A04UL)) +#define bFM3_BT3_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1A14UL)) +#define bFM3_BT3_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 RT registers */ +#define bFM3_BT3_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_RT_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) +#define bFM3_BT3_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_RT_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_RT_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_RT_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_RT_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 PWC registers */ +#define bFM3_BT3_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) +#define bFM3_BT3_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PWC_STC_ERR *((volatile unsigned int*)(0x424A1A1CUL)) +#define bFM3_BT3_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 4 PPG registers */ +#define bFM3_BT4_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) +#define bFM3_BT4_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 PWM registers */ +#define bFM3_BT4_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) +#define bFM3_BT4_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4204UL)) +#define bFM3_BT4_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4214UL)) +#define bFM3_BT4_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 RT registers */ +#define bFM3_BT4_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_RT_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) +#define bFM3_BT4_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_RT_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_RT_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_RT_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_RT_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 PWC registers */ +#define bFM3_BT4_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) +#define bFM3_BT4_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PWC_STC_ERR *((volatile unsigned int*)(0x424A421CUL)) +#define bFM3_BT4_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 5 PPG registers */ +#define bFM3_BT5_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) +#define bFM3_BT5_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 PWM registers */ +#define bFM3_BT5_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) +#define bFM3_BT5_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4A04UL)) +#define bFM3_BT5_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4A14UL)) +#define bFM3_BT5_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 RT registers */ +#define bFM3_BT5_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_RT_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) +#define bFM3_BT5_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_RT_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_RT_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_RT_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_RT_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 PWC registers */ +#define bFM3_BT5_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) +#define bFM3_BT5_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PWC_STC_ERR *((volatile unsigned int*)(0x424A4A1CUL)) +#define bFM3_BT5_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 6 PPG registers */ +#define bFM3_BT6_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) +#define bFM3_BT6_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 PWM registers */ +#define bFM3_BT6_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) +#define bFM3_BT6_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5204UL)) +#define bFM3_BT6_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5214UL)) +#define bFM3_BT6_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 RT registers */ +#define bFM3_BT6_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_RT_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) +#define bFM3_BT6_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_RT_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_RT_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_RT_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_RT_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 PWC registers */ +#define bFM3_BT6_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) +#define bFM3_BT6_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PWC_STC_ERR *((volatile unsigned int*)(0x424A521CUL)) +#define bFM3_BT6_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 7 PPG registers */ +#define bFM3_BT7_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) +#define bFM3_BT7_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 PWM registers */ +#define bFM3_BT7_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) +#define bFM3_BT7_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5A04UL)) +#define bFM3_BT7_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5A14UL)) +#define bFM3_BT7_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 RT registers */ +#define bFM3_BT7_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_RT_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) +#define bFM3_BT7_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_RT_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_RT_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_RT_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_RT_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 PWC registers */ +#define bFM3_BT7_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) +#define bFM3_BT7_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PWC_STC_ERR *((volatile unsigned int*)(0x424A5A1CUL)) +#define bFM3_BT7_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer I/O selector channel 0 - channel 3 registers */ +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0 *((volatile unsigned int*)(0x424A2020UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1 *((volatile unsigned int*)(0x424A2024UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2 *((volatile unsigned int*)(0x424A2028UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3 *((volatile unsigned int*)(0x424A202CUL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0 *((volatile unsigned int*)(0x424A2030UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1 *((volatile unsigned int*)(0x424A2034UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2 *((volatile unsigned int*)(0x424A2038UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3 *((volatile unsigned int*)(0x424A203CUL)) + +/* Base Timer I/O selector channel 4 - channel 7 registers */ +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0 *((volatile unsigned int*)(0x424A6020UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1 *((volatile unsigned int*)(0x424A6024UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2 *((volatile unsigned int*)(0x424A6028UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3 *((volatile unsigned int*)(0x424A602CUL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0 *((volatile unsigned int*)(0x424A6030UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1 *((volatile unsigned int*)(0x424A6034UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2 *((volatile unsigned int*)(0x424A6038UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3 *((volatile unsigned int*)(0x424A603CUL)) + +/* Software based Simulation Startup (Base Timer) register */ +#define bFM3_SBSSR_BTSSSR_SSR0 *((volatile unsigned int*)(0x424BFF80UL)) +#define bFM3_SBSSR_BTSSSR_SSR1 *((volatile unsigned int*)(0x424BFF84UL)) +#define bFM3_SBSSR_BTSSSR_SSR2 *((volatile unsigned int*)(0x424BFF88UL)) +#define bFM3_SBSSR_BTSSSR_SSR3 *((volatile unsigned int*)(0x424BFF8CUL)) +#define bFM3_SBSSR_BTSSSR_SSR4 *((volatile unsigned int*)(0x424BFF90UL)) +#define bFM3_SBSSR_BTSSSR_SSR5 *((volatile unsigned int*)(0x424BFF94UL)) +#define bFM3_SBSSR_BTSSSR_SSR6 *((volatile unsigned int*)(0x424BFF98UL)) +#define bFM3_SBSSR_BTSSSR_SSR7 *((volatile unsigned int*)(0x424BFF9CUL)) +#define bFM3_SBSSR_BTSSSR_SSR8 *((volatile unsigned int*)(0x424BFFA0UL)) +#define bFM3_SBSSR_BTSSSR_SSR9 *((volatile unsigned int*)(0x424BFFA4UL)) +#define bFM3_SBSSR_BTSSSR_SSR10 *((volatile unsigned int*)(0x424BFFA8UL)) +#define bFM3_SBSSR_BTSSSR_SSR11 *((volatile unsigned int*)(0x424BFFACUL)) +#define bFM3_SBSSR_BTSSSR_SSR12 *((volatile unsigned int*)(0x424BFFB0UL)) +#define bFM3_SBSSR_BTSSSR_SSR13 *((volatile unsigned int*)(0x424BFFB4UL)) +#define bFM3_SBSSR_BTSSSR_SSR14 *((volatile unsigned int*)(0x424BFFB8UL)) +#define bFM3_SBSSR_BTSSSR_SSR15 *((volatile unsigned int*)(0x424BFFBCUL)) + +/* Quad position and revolution counter channel 0 registers */ +#define bFM3_QPRC0_QICR_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) +#define bFM3_QPRC0_QICR_QPCMF *((volatile unsigned int*)(0x424C0284UL)) +#define bFM3_QPRC0_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) +#define bFM3_QPRC0_QICR_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) +#define bFM3_QPRC0_QICR_OUZIE *((volatile unsigned int*)(0x424C0290UL)) +#define bFM3_QPRC0_QICR_UFDF *((volatile unsigned int*)(0x424C0294UL)) +#define bFM3_QPRC0_QICR_OFDF *((volatile unsigned int*)(0x424C0298UL)) +#define bFM3_QPRC0_QICR_ZIIF *((volatile unsigned int*)(0x424C029CUL)) +#define bFM3_QPRC0_QICR_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) +#define bFM3_QPRC0_QICR_CDCF *((volatile unsigned int*)(0x424C02A4UL)) +#define bFM3_QPRC0_QICR_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) +#define bFM3_QPRC0_QICR_DIROU *((volatile unsigned int*)(0x424C02ACUL)) +#define bFM3_QPRC0_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) +#define bFM3_QPRC0_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) +#define bFM3_QPRC0_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) +#define bFM3_QPRC0_QICRL_QPCMF *((volatile unsigned int*)(0x424C0284UL)) +#define bFM3_QPRC0_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) +#define bFM3_QPRC0_QICRL_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) +#define bFM3_QPRC0_QICRL_OUZIE *((volatile unsigned int*)(0x424C0290UL)) +#define bFM3_QPRC0_QICRL_UFDF *((volatile unsigned int*)(0x424C0294UL)) +#define bFM3_QPRC0_QICRL_OFDF *((volatile unsigned int*)(0x424C0298UL)) +#define bFM3_QPRC0_QICRL_ZIIF *((volatile unsigned int*)(0x424C029CUL)) +#define bFM3_QPRC0_QICRH_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) +#define bFM3_QPRC0_QICRH_CDCF *((volatile unsigned int*)(0x424C02A4UL)) +#define bFM3_QPRC0_QICRH_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) +#define bFM3_QPRC0_QICRH_DIROU *((volatile unsigned int*)(0x424C02ACUL)) +#define bFM3_QPRC0_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) +#define bFM3_QPRC0_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) +#define bFM3_QPRC0_QCR_PCM0 *((volatile unsigned int*)(0x424C0300UL)) +#define bFM3_QPRC0_QCR_PCM1 *((volatile unsigned int*)(0x424C0304UL)) +#define bFM3_QPRC0_QCR_RCM0 *((volatile unsigned int*)(0x424C0308UL)) +#define bFM3_QPRC0_QCR_RCM1 *((volatile unsigned int*)(0x424C030CUL)) +#define bFM3_QPRC0_QCR_PSTP *((volatile unsigned int*)(0x424C0310UL)) +#define bFM3_QPRC0_QCR_CGSC *((volatile unsigned int*)(0x424C0314UL)) +#define bFM3_QPRC0_QCR_RSEL *((volatile unsigned int*)(0x424C0318UL)) +#define bFM3_QPRC0_QCR_SWAP *((volatile unsigned int*)(0x424C031CUL)) +#define bFM3_QPRC0_QCR_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) +#define bFM3_QPRC0_QCR_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) +#define bFM3_QPRC0_QCR_AES0 *((volatile unsigned int*)(0x424C0328UL)) +#define bFM3_QPRC0_QCR_AES1 *((volatile unsigned int*)(0x424C032CUL)) +#define bFM3_QPRC0_QCR_BES0 *((volatile unsigned int*)(0x424C0330UL)) +#define bFM3_QPRC0_QCR_BES1 *((volatile unsigned int*)(0x424C0334UL)) +#define bFM3_QPRC0_QCR_CGE0 *((volatile unsigned int*)(0x424C0338UL)) +#define bFM3_QPRC0_QCR_CGE1 *((volatile unsigned int*)(0x424C033CUL)) +#define bFM3_QPRC0_QCRL_PCM0 *((volatile unsigned int*)(0x424C0300UL)) +#define bFM3_QPRC0_QCRL_PCM1 *((volatile unsigned int*)(0x424C0304UL)) +#define bFM3_QPRC0_QCRL_RCM0 *((volatile unsigned int*)(0x424C0308UL)) +#define bFM3_QPRC0_QCRL_RCM1 *((volatile unsigned int*)(0x424C030CUL)) +#define bFM3_QPRC0_QCRL_PSTP *((volatile unsigned int*)(0x424C0310UL)) +#define bFM3_QPRC0_QCRL_CGSC *((volatile unsigned int*)(0x424C0314UL)) +#define bFM3_QPRC0_QCRL_RSEL *((volatile unsigned int*)(0x424C0318UL)) +#define bFM3_QPRC0_QCRL_SWAP *((volatile unsigned int*)(0x424C031CUL)) +#define bFM3_QPRC0_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) +#define bFM3_QPRC0_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) +#define bFM3_QPRC0_QCRH_AES0 *((volatile unsigned int*)(0x424C0328UL)) +#define bFM3_QPRC0_QCRH_AES1 *((volatile unsigned int*)(0x424C032CUL)) +#define bFM3_QPRC0_QCRH_BES0 *((volatile unsigned int*)(0x424C0330UL)) +#define bFM3_QPRC0_QCRH_BES1 *((volatile unsigned int*)(0x424C0334UL)) +#define bFM3_QPRC0_QCRH_CGE0 *((volatile unsigned int*)(0x424C0338UL)) +#define bFM3_QPRC0_QCRH_CGE1 *((volatile unsigned int*)(0x424C033CUL)) +#define bFM3_QPRC0_QECR_ORNGMD *((volatile unsigned int*)(0x424C0380UL)) +#define bFM3_QPRC0_QECR_ORNGF *((volatile unsigned int*)(0x424C0384UL)) +#define bFM3_QPRC0_QECR_ORNGIE *((volatile unsigned int*)(0x424C0388UL)) + +/* Quad position and revolution counter channel 1 registers */ +#define bFM3_QPRC1_QICR_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) +#define bFM3_QPRC1_QICR_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) +#define bFM3_QPRC1_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) +#define bFM3_QPRC1_QICR_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) +#define bFM3_QPRC1_QICR_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) +#define bFM3_QPRC1_QICR_UFDF *((volatile unsigned int*)(0x424C0A94UL)) +#define bFM3_QPRC1_QICR_OFDF *((volatile unsigned int*)(0x424C0A98UL)) +#define bFM3_QPRC1_QICR_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) +#define bFM3_QPRC1_QICR_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) +#define bFM3_QPRC1_QICR_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) +#define bFM3_QPRC1_QICR_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) +#define bFM3_QPRC1_QICR_DIROU *((volatile unsigned int*)(0x424C0AACUL)) +#define bFM3_QPRC1_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) +#define bFM3_QPRC1_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) +#define bFM3_QPRC1_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) +#define bFM3_QPRC1_QICRL_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) +#define bFM3_QPRC1_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) +#define bFM3_QPRC1_QICRL_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) +#define bFM3_QPRC1_QICRL_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) +#define bFM3_QPRC1_QICRL_UFDF *((volatile unsigned int*)(0x424C0A94UL)) +#define bFM3_QPRC1_QICRL_OFDF *((volatile unsigned int*)(0x424C0A98UL)) +#define bFM3_QPRC1_QICRL_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) +#define bFM3_QPRC1_QICRH_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) +#define bFM3_QPRC1_QICRH_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) +#define bFM3_QPRC1_QICRH_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) +#define bFM3_QPRC1_QICRH_DIROU *((volatile unsigned int*)(0x424C0AACUL)) +#define bFM3_QPRC1_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) +#define bFM3_QPRC1_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) +#define bFM3_QPRC1_QCR_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) +#define bFM3_QPRC1_QCR_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) +#define bFM3_QPRC1_QCR_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) +#define bFM3_QPRC1_QCR_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) +#define bFM3_QPRC1_QCR_PSTP *((volatile unsigned int*)(0x424C0B10UL)) +#define bFM3_QPRC1_QCR_CGSC *((volatile unsigned int*)(0x424C0B14UL)) +#define bFM3_QPRC1_QCR_RSEL *((volatile unsigned int*)(0x424C0B18UL)) +#define bFM3_QPRC1_QCR_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) +#define bFM3_QPRC1_QCR_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) +#define bFM3_QPRC1_QCR_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) +#define bFM3_QPRC1_QCR_AES0 *((volatile unsigned int*)(0x424C0B28UL)) +#define bFM3_QPRC1_QCR_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) +#define bFM3_QPRC1_QCR_BES0 *((volatile unsigned int*)(0x424C0B30UL)) +#define bFM3_QPRC1_QCR_BES1 *((volatile unsigned int*)(0x424C0B34UL)) +#define bFM3_QPRC1_QCR_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) +#define bFM3_QPRC1_QCR_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) +#define bFM3_QPRC1_QCRL_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) +#define bFM3_QPRC1_QCRL_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) +#define bFM3_QPRC1_QCRL_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) +#define bFM3_QPRC1_QCRL_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) +#define bFM3_QPRC1_QCRL_PSTP *((volatile unsigned int*)(0x424C0B10UL)) +#define bFM3_QPRC1_QCRL_CGSC *((volatile unsigned int*)(0x424C0B14UL)) +#define bFM3_QPRC1_QCRL_RSEL *((volatile unsigned int*)(0x424C0B18UL)) +#define bFM3_QPRC1_QCRL_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) +#define bFM3_QPRC1_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) +#define bFM3_QPRC1_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) +#define bFM3_QPRC1_QCRH_AES0 *((volatile unsigned int*)(0x424C0B28UL)) +#define bFM3_QPRC1_QCRH_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) +#define bFM3_QPRC1_QCRH_BES0 *((volatile unsigned int*)(0x424C0B30UL)) +#define bFM3_QPRC1_QCRH_BES1 *((volatile unsigned int*)(0x424C0B34UL)) +#define bFM3_QPRC1_QCRH_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) +#define bFM3_QPRC1_QCRH_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) +#define bFM3_QPRC1_QECR_ORNGMD *((volatile unsigned int*)(0x424C0B80UL)) +#define bFM3_QPRC1_QECR_ORNGF *((volatile unsigned int*)(0x424C0B84UL)) +#define bFM3_QPRC1_QECR_ORNGIE *((volatile unsigned int*)(0x424C0B88UL)) + +/* 12-bit ADC unit 0 registers */ +#define bFM3_ADC0_ADSR_SCS *((volatile unsigned int*)(0x424E0000UL)) +#define bFM3_ADC0_ADSR_PCS *((volatile unsigned int*)(0x424E0004UL)) +#define bFM3_ADC0_ADSR_PCNS *((volatile unsigned int*)(0x424E0008UL)) +#define bFM3_ADC0_ADSR_FDAS *((volatile unsigned int*)(0x424E0018UL)) +#define bFM3_ADC0_ADSR_ADSTP *((volatile unsigned int*)(0x424E001CUL)) +#define bFM3_ADC0_ADCR_OVRIE *((volatile unsigned int*)(0x424E0020UL)) +#define bFM3_ADC0_ADCR_CMPIE *((volatile unsigned int*)(0x424E0024UL)) +#define bFM3_ADC0_ADCR_PCIE *((volatile unsigned int*)(0x424E0028UL)) +#define bFM3_ADC0_ADCR_SCIE *((volatile unsigned int*)(0x424E002CUL)) +#define bFM3_ADC0_ADCR_CMPIF *((volatile unsigned int*)(0x424E0034UL)) +#define bFM3_ADC0_ADCR_PCIF *((volatile unsigned int*)(0x424E0038UL)) +#define bFM3_ADC0_ADCR_SCIF *((volatile unsigned int*)(0x424E003CUL)) +#define bFM3_ADC0_SFNS_SFS0 *((volatile unsigned int*)(0x424E0100UL)) +#define bFM3_ADC0_SFNS_SFS1 *((volatile unsigned int*)(0x424E0104UL)) +#define bFM3_ADC0_SFNS_SFS2 *((volatile unsigned int*)(0x424E0108UL)) +#define bFM3_ADC0_SFNS_SFS3 *((volatile unsigned int*)(0x424E010CUL)) +#define bFM3_ADC0_SCCR_SSTR *((volatile unsigned int*)(0x424E0120UL)) +#define bFM3_ADC0_SCCR_SHEN *((volatile unsigned int*)(0x424E0124UL)) +#define bFM3_ADC0_SCCR_RPT *((volatile unsigned int*)(0x424E0128UL)) +#define bFM3_ADC0_SCCR_SFCLR *((volatile unsigned int*)(0x424E0130UL)) +#define bFM3_ADC0_SCCR_SOVR *((volatile unsigned int*)(0x424E0134UL)) +#define bFM3_ADC0_SCCR_SFUL *((volatile unsigned int*)(0x424E0138UL)) +#define bFM3_ADC0_SCCR_SEMP *((volatile unsigned int*)(0x424E013CUL)) +#define bFM3_ADC0_SCFD_SC0 *((volatile unsigned int*)(0x424E0180UL)) +#define bFM3_ADC0_SCFD_SC1 *((volatile unsigned int*)(0x424E0184UL)) +#define bFM3_ADC0_SCFD_SC2 *((volatile unsigned int*)(0x424E0188UL)) +#define bFM3_ADC0_SCFD_SC3 *((volatile unsigned int*)(0x424E018CUL)) +#define bFM3_ADC0_SCFD_SC4 *((volatile unsigned int*)(0x424E0190UL)) +#define bFM3_ADC0_SCFD_RS0 *((volatile unsigned int*)(0x424E01A0UL)) +#define bFM3_ADC0_SCFD_RS1 *((volatile unsigned int*)(0x424E01A4UL)) +#define bFM3_ADC0_SCFD_INVL *((volatile unsigned int*)(0x424E01B0UL)) +#define bFM3_ADC0_SCFD_SD0 *((volatile unsigned int*)(0x424E01D0UL)) +#define bFM3_ADC0_SCFD_SD1 *((volatile unsigned int*)(0x424E01D4UL)) +#define bFM3_ADC0_SCFD_SD2 *((volatile unsigned int*)(0x424E01D8UL)) +#define bFM3_ADC0_SCFD_SD3 *((volatile unsigned int*)(0x424E01DCUL)) +#define bFM3_ADC0_SCFD_SD4 *((volatile unsigned int*)(0x424E01E0UL)) +#define bFM3_ADC0_SCFD_SD5 *((volatile unsigned int*)(0x424E01E4UL)) +#define bFM3_ADC0_SCFD_SD6 *((volatile unsigned int*)(0x424E01E8UL)) +#define bFM3_ADC0_SCFD_SD7 *((volatile unsigned int*)(0x424E01ECUL)) +#define bFM3_ADC0_SCFD_SD8 *((volatile unsigned int*)(0x424E01F0UL)) +#define bFM3_ADC0_SCFD_SD9 *((volatile unsigned int*)(0x424E01F4UL)) +#define bFM3_ADC0_SCFD_SD10 *((volatile unsigned int*)(0x424E01F8UL)) +#define bFM3_ADC0_SCFD_SD11 *((volatile unsigned int*)(0x424E01FCUL)) +#define bFM3_ADC0_SCFDL_SC0 *((volatile unsigned int*)(0x424E0180UL)) +#define bFM3_ADC0_SCFDL_SC1 *((volatile unsigned int*)(0x424E0184UL)) +#define bFM3_ADC0_SCFDL_SC2 *((volatile unsigned int*)(0x424E0188UL)) +#define bFM3_ADC0_SCFDL_SC3 *((volatile unsigned int*)(0x424E018CUL)) +#define bFM3_ADC0_SCFDL_SC4 *((volatile unsigned int*)(0x424E0190UL)) +#define bFM3_ADC0_SCFDL_RS0 *((volatile unsigned int*)(0x424E01A0UL)) +#define bFM3_ADC0_SCFDL_RS1 *((volatile unsigned int*)(0x424E01A4UL)) +#define bFM3_ADC0_SCFDL_INVL *((volatile unsigned int*)(0x424E01B0UL)) +#define bFM3_ADC0_SCFDH_SD0 *((volatile unsigned int*)(0x424E01D0UL)) +#define bFM3_ADC0_SCFDH_SD1 *((volatile unsigned int*)(0x424E01D4UL)) +#define bFM3_ADC0_SCFDH_SD2 *((volatile unsigned int*)(0x424E01D8UL)) +#define bFM3_ADC0_SCFDH_SD3 *((volatile unsigned int*)(0x424E01DCUL)) +#define bFM3_ADC0_SCFDH_SD4 *((volatile unsigned int*)(0x424E01E0UL)) +#define bFM3_ADC0_SCFDH_SD5 *((volatile unsigned int*)(0x424E01E4UL)) +#define bFM3_ADC0_SCFDH_SD6 *((volatile unsigned int*)(0x424E01E8UL)) +#define bFM3_ADC0_SCFDH_SD7 *((volatile unsigned int*)(0x424E01ECUL)) +#define bFM3_ADC0_SCFDH_SD8 *((volatile unsigned int*)(0x424E01F0UL)) +#define bFM3_ADC0_SCFDH_SD9 *((volatile unsigned int*)(0x424E01F4UL)) +#define bFM3_ADC0_SCFDH_SD10 *((volatile unsigned int*)(0x424E01F8UL)) +#define bFM3_ADC0_SCFDH_SD11 *((volatile unsigned int*)(0x424E01FCUL)) +#define bFM3_ADC0_SCIS23_AN16 *((volatile unsigned int*)(0x424E0200UL)) +#define bFM3_ADC0_SCIS23_AN17 *((volatile unsigned int*)(0x424E0204UL)) +#define bFM3_ADC0_SCIS23_AN18 *((volatile unsigned int*)(0x424E0208UL)) +#define bFM3_ADC0_SCIS23_AN19 *((volatile unsigned int*)(0x424E020CUL)) +#define bFM3_ADC0_SCIS23_AN20 *((volatile unsigned int*)(0x424E0210UL)) +#define bFM3_ADC0_SCIS23_AN21 *((volatile unsigned int*)(0x424E0214UL)) +#define bFM3_ADC0_SCIS23_AN22 *((volatile unsigned int*)(0x424E0218UL)) +#define bFM3_ADC0_SCIS23_AN23 *((volatile unsigned int*)(0x424E021CUL)) +#define bFM3_ADC0_SCIS23_AN24 *((volatile unsigned int*)(0x424E0220UL)) +#define bFM3_ADC0_SCIS23_AN25 *((volatile unsigned int*)(0x424E0224UL)) +#define bFM3_ADC0_SCIS23_AN26 *((volatile unsigned int*)(0x424E0228UL)) +#define bFM3_ADC0_SCIS23_AN27 *((volatile unsigned int*)(0x424E022CUL)) +#define bFM3_ADC0_SCIS23_AN28 *((volatile unsigned int*)(0x424E0230UL)) +#define bFM3_ADC0_SCIS23_AN29 *((volatile unsigned int*)(0x424E0234UL)) +#define bFM3_ADC0_SCIS23_AN30 *((volatile unsigned int*)(0x424E0238UL)) +#define bFM3_ADC0_SCIS23_AN31 *((volatile unsigned int*)(0x424E023CUL)) +#define bFM3_ADC0_SCIS2_AN16 *((volatile unsigned int*)(0x424E0200UL)) +#define bFM3_ADC0_SCIS2_AN17 *((volatile unsigned int*)(0x424E0204UL)) +#define bFM3_ADC0_SCIS2_AN18 *((volatile unsigned int*)(0x424E0208UL)) +#define bFM3_ADC0_SCIS2_AN19 *((volatile unsigned int*)(0x424E020CUL)) +#define bFM3_ADC0_SCIS2_AN20 *((volatile unsigned int*)(0x424E0210UL)) +#define bFM3_ADC0_SCIS2_AN21 *((volatile unsigned int*)(0x424E0214UL)) +#define bFM3_ADC0_SCIS2_AN22 *((volatile unsigned int*)(0x424E0218UL)) +#define bFM3_ADC0_SCIS2_AN23 *((volatile unsigned int*)(0x424E021CUL)) +#define bFM3_ADC0_SCIS3_AN24 *((volatile unsigned int*)(0x424E0220UL)) +#define bFM3_ADC0_SCIS3_AN25 *((volatile unsigned int*)(0x424E0224UL)) +#define bFM3_ADC0_SCIS3_AN26 *((volatile unsigned int*)(0x424E0228UL)) +#define bFM3_ADC0_SCIS3_AN27 *((volatile unsigned int*)(0x424E022CUL)) +#define bFM3_ADC0_SCIS3_AN28 *((volatile unsigned int*)(0x424E0230UL)) +#define bFM3_ADC0_SCIS3_AN29 *((volatile unsigned int*)(0x424E0234UL)) +#define bFM3_ADC0_SCIS3_AN30 *((volatile unsigned int*)(0x424E0238UL)) +#define bFM3_ADC0_SCIS3_AN31 *((volatile unsigned int*)(0x424E023CUL)) +#define bFM3_ADC0_SCIS01_AN0 *((volatile unsigned int*)(0x424E0280UL)) +#define bFM3_ADC0_SCIS01_AN1 *((volatile unsigned int*)(0x424E0284UL)) +#define bFM3_ADC0_SCIS01_AN2 *((volatile unsigned int*)(0x424E0288UL)) +#define bFM3_ADC0_SCIS01_AN3 *((volatile unsigned int*)(0x424E028CUL)) +#define bFM3_ADC0_SCIS01_AN4 *((volatile unsigned int*)(0x424E0290UL)) +#define bFM3_ADC0_SCIS01_AN5 *((volatile unsigned int*)(0x424E0294UL)) +#define bFM3_ADC0_SCIS01_AN6 *((volatile unsigned int*)(0x424E0298UL)) +#define bFM3_ADC0_SCIS01_AN7 *((volatile unsigned int*)(0x424E029CUL)) +#define bFM3_ADC0_SCIS01_AN8 *((volatile unsigned int*)(0x424E02A0UL)) +#define bFM3_ADC0_SCIS01_AN9 *((volatile unsigned int*)(0x424E02A4UL)) +#define bFM3_ADC0_SCIS01_AN10 *((volatile unsigned int*)(0x424E02A8UL)) +#define bFM3_ADC0_SCIS01_AN11 *((volatile unsigned int*)(0x424E02ACUL)) +#define bFM3_ADC0_SCIS01_AN12 *((volatile unsigned int*)(0x424E02B0UL)) +#define bFM3_ADC0_SCIS01_AN13 *((volatile unsigned int*)(0x424E02B4UL)) +#define bFM3_ADC0_SCIS01_AN14 *((volatile unsigned int*)(0x424E02B8UL)) +#define bFM3_ADC0_SCIS01_AN15 *((volatile unsigned int*)(0x424E02BCUL)) +#define bFM3_ADC0_SCIS0_AN0 *((volatile unsigned int*)(0x424E0280UL)) +#define bFM3_ADC0_SCIS0_AN1 *((volatile unsigned int*)(0x424E0284UL)) +#define bFM3_ADC0_SCIS0_AN2 *((volatile unsigned int*)(0x424E0288UL)) +#define bFM3_ADC0_SCIS0_AN3 *((volatile unsigned int*)(0x424E028CUL)) +#define bFM3_ADC0_SCIS0_AN4 *((volatile unsigned int*)(0x424E0290UL)) +#define bFM3_ADC0_SCIS0_AN5 *((volatile unsigned int*)(0x424E0294UL)) +#define bFM3_ADC0_SCIS0_AN6 *((volatile unsigned int*)(0x424E0298UL)) +#define bFM3_ADC0_SCIS0_AN7 *((volatile unsigned int*)(0x424E029CUL)) +#define bFM3_ADC0_SCIS1_AN8 *((volatile unsigned int*)(0x424E02A0UL)) +#define bFM3_ADC0_SCIS1_AN9 *((volatile unsigned int*)(0x424E02A4UL)) +#define bFM3_ADC0_SCIS1_AN10 *((volatile unsigned int*)(0x424E02A8UL)) +#define bFM3_ADC0_SCIS1_AN11 *((volatile unsigned int*)(0x424E02ACUL)) +#define bFM3_ADC0_SCIS1_AN12 *((volatile unsigned int*)(0x424E02B0UL)) +#define bFM3_ADC0_SCIS1_AN13 *((volatile unsigned int*)(0x424E02B4UL)) +#define bFM3_ADC0_SCIS1_AN14 *((volatile unsigned int*)(0x424E02B8UL)) +#define bFM3_ADC0_SCIS1_AN15 *((volatile unsigned int*)(0x424E02BCUL)) +#define bFM3_ADC0_PFNS_PFS0 *((volatile unsigned int*)(0x424E0300UL)) +#define bFM3_ADC0_PFNS_PFS1 *((volatile unsigned int*)(0x424E0304UL)) +#define bFM3_ADC0_PFNS_TEST0 *((volatile unsigned int*)(0x424E0310UL)) +#define bFM3_ADC0_PFNS_TEST1 *((volatile unsigned int*)(0x424E0314UL)) +#define bFM3_ADC0_PCCR_PSTR *((volatile unsigned int*)(0x424E0320UL)) +#define bFM3_ADC0_PCCR_PHEN *((volatile unsigned int*)(0x424E0324UL)) +#define bFM3_ADC0_PCCR_PEEN *((volatile unsigned int*)(0x424E0328UL)) +#define bFM3_ADC0_PCCR_ESCE *((volatile unsigned int*)(0x424E032CUL)) +#define bFM3_ADC0_PCCR_PFCLR *((volatile unsigned int*)(0x424E0330UL)) +#define bFM3_ADC0_PCCR_POVR *((volatile unsigned int*)(0x424E0334UL)) +#define bFM3_ADC0_PCCR_PFUL *((volatile unsigned int*)(0x424E0338UL)) +#define bFM3_ADC0_PCCR_PEMP *((volatile unsigned int*)(0x424E033CUL)) +#define bFM3_ADC0_PCFD_PC0 *((volatile unsigned int*)(0x424E0380UL)) +#define bFM3_ADC0_PCFD_PC1 *((volatile unsigned int*)(0x424E0384UL)) +#define bFM3_ADC0_PCFD_PC2 *((volatile unsigned int*)(0x424E0388UL)) +#define bFM3_ADC0_PCFD_PC3 *((volatile unsigned int*)(0x424E038CUL)) +#define bFM3_ADC0_PCFD_PC4 *((volatile unsigned int*)(0x424E0390UL)) +#define bFM3_ADC0_PCFD_RS0 *((volatile unsigned int*)(0x424E03A0UL)) +#define bFM3_ADC0_PCFD_RS1 *((volatile unsigned int*)(0x424E03A4UL)) +#define bFM3_ADC0_PCFD_RS2 *((volatile unsigned int*)(0x424E03A8UL)) +#define bFM3_ADC0_PCFD_INVL *((volatile unsigned int*)(0x424E03B0UL)) +#define bFM3_ADC0_PCFD_PD0 *((volatile unsigned int*)(0x424E03D0UL)) +#define bFM3_ADC0_PCFD_PD1 *((volatile unsigned int*)(0x424E03D4UL)) +#define bFM3_ADC0_PCFD_PD2 *((volatile unsigned int*)(0x424E03D8UL)) +#define bFM3_ADC0_PCFD_PD3 *((volatile unsigned int*)(0x424E03DCUL)) +#define bFM3_ADC0_PCFD_PD4 *((volatile unsigned int*)(0x424E03E0UL)) +#define bFM3_ADC0_PCFD_PD5 *((volatile unsigned int*)(0x424E03E4UL)) +#define bFM3_ADC0_PCFD_PD6 *((volatile unsigned int*)(0x424E03E8UL)) +#define bFM3_ADC0_PCFD_PD7 *((volatile unsigned int*)(0x424E03ECUL)) +#define bFM3_ADC0_PCFD_PD8 *((volatile unsigned int*)(0x424E03F0UL)) +#define bFM3_ADC0_PCFD_PD9 *((volatile unsigned int*)(0x424E03F4UL)) +#define bFM3_ADC0_PCFD_PD10 *((volatile unsigned int*)(0x424E03F8UL)) +#define bFM3_ADC0_PCFD_PD11 *((volatile unsigned int*)(0x424E03FCUL)) +#define bFM3_ADC0_PCFDL_PC0 *((volatile unsigned int*)(0x424E0380UL)) +#define bFM3_ADC0_PCFDL_PC1 *((volatile unsigned int*)(0x424E0384UL)) +#define bFM3_ADC0_PCFDL_PC2 *((volatile unsigned int*)(0x424E0388UL)) +#define bFM3_ADC0_PCFDL_PC3 *((volatile unsigned int*)(0x424E038CUL)) +#define bFM3_ADC0_PCFDL_PC4 *((volatile unsigned int*)(0x424E0390UL)) +#define bFM3_ADC0_PCFDL_RS0 *((volatile unsigned int*)(0x424E03A0UL)) +#define bFM3_ADC0_PCFDL_RS1 *((volatile unsigned int*)(0x424E03A4UL)) +#define bFM3_ADC0_PCFDL_RS2 *((volatile unsigned int*)(0x424E03A8UL)) +#define bFM3_ADC0_PCFDL_INVL *((volatile unsigned int*)(0x424E03B0UL)) +#define bFM3_ADC0_PCFDH_PD0 *((volatile unsigned int*)(0x424E03D0UL)) +#define bFM3_ADC0_PCFDH_PD1 *((volatile unsigned int*)(0x424E03D4UL)) +#define bFM3_ADC0_PCFDH_PD2 *((volatile unsigned int*)(0x424E03D8UL)) +#define bFM3_ADC0_PCFDH_PD3 *((volatile unsigned int*)(0x424E03DCUL)) +#define bFM3_ADC0_PCFDH_PD4 *((volatile unsigned int*)(0x424E03E0UL)) +#define bFM3_ADC0_PCFDH_PD5 *((volatile unsigned int*)(0x424E03E4UL)) +#define bFM3_ADC0_PCFDH_PD6 *((volatile unsigned int*)(0x424E03E8UL)) +#define bFM3_ADC0_PCFDH_PD7 *((volatile unsigned int*)(0x424E03ECUL)) +#define bFM3_ADC0_PCFDH_PD8 *((volatile unsigned int*)(0x424E03F0UL)) +#define bFM3_ADC0_PCFDH_PD9 *((volatile unsigned int*)(0x424E03F4UL)) +#define bFM3_ADC0_PCFDH_PD10 *((volatile unsigned int*)(0x424E03F8UL)) +#define bFM3_ADC0_PCFDH_PD11 *((volatile unsigned int*)(0x424E03FCUL)) +#define bFM3_ADC0_PCIS_P1A0 *((volatile unsigned int*)(0x424E0400UL)) +#define bFM3_ADC0_PCIS_P1A1 *((volatile unsigned int*)(0x424E0404UL)) +#define bFM3_ADC0_PCIS_P1A2 *((volatile unsigned int*)(0x424E0408UL)) +#define bFM3_ADC0_PCIS_P2A0 *((volatile unsigned int*)(0x424E040CUL)) +#define bFM3_ADC0_PCIS_P2A1 *((volatile unsigned int*)(0x424E0410UL)) +#define bFM3_ADC0_PCIS_P2A2 *((volatile unsigned int*)(0x424E0414UL)) +#define bFM3_ADC0_PCIS_P2A3 *((volatile unsigned int*)(0x424E0418UL)) +#define bFM3_ADC0_PCIS_P2A4 *((volatile unsigned int*)(0x424E041CUL)) +#define bFM3_ADC0_CMPCR_CCH0 *((volatile unsigned int*)(0x424E0480UL)) +#define bFM3_ADC0_CMPCR_CCH1 *((volatile unsigned int*)(0x424E0484UL)) +#define bFM3_ADC0_CMPCR_CCH2 *((volatile unsigned int*)(0x424E0488UL)) +#define bFM3_ADC0_CMPCR_CCH3 *((volatile unsigned int*)(0x424E048CUL)) +#define bFM3_ADC0_CMPCR_CCH4 *((volatile unsigned int*)(0x424E0490UL)) +#define bFM3_ADC0_CMPCR_CMD0 *((volatile unsigned int*)(0x424E0494UL)) +#define bFM3_ADC0_CMPCR_CMD1 *((volatile unsigned int*)(0x424E0498UL)) +#define bFM3_ADC0_CMPCR_CMPEN *((volatile unsigned int*)(0x424E049CUL)) +#define bFM3_ADC0_CMPD_CMAD2 *((volatile unsigned int*)(0x424E04D8UL)) +#define bFM3_ADC0_CMPD_CMAD3 *((volatile unsigned int*)(0x424E04DCUL)) +#define bFM3_ADC0_CMPD_CMAD4 *((volatile unsigned int*)(0x424E04E0UL)) +#define bFM3_ADC0_CMPD_CMAD5 *((volatile unsigned int*)(0x424E04E4UL)) +#define bFM3_ADC0_CMPD_CMAD6 *((volatile unsigned int*)(0x424E04E8UL)) +#define bFM3_ADC0_CMPD_CMAD7 *((volatile unsigned int*)(0x424E04ECUL)) +#define bFM3_ADC0_CMPD_CMAD8 *((volatile unsigned int*)(0x424E04F0UL)) +#define bFM3_ADC0_CMPD_CMAD9 *((volatile unsigned int*)(0x424E04F4UL)) +#define bFM3_ADC0_CMPD_CMAD10 *((volatile unsigned int*)(0x424E04F8UL)) +#define bFM3_ADC0_CMPD_CMAD11 *((volatile unsigned int*)(0x424E04FCUL)) +#define bFM3_ADC0_ADSS23_TS16 *((volatile unsigned int*)(0x424E0500UL)) +#define bFM3_ADC0_ADSS23_TS17 *((volatile unsigned int*)(0x424E0504UL)) +#define bFM3_ADC0_ADSS23_TS18 *((volatile unsigned int*)(0x424E0508UL)) +#define bFM3_ADC0_ADSS23_TS19 *((volatile unsigned int*)(0x424E050CUL)) +#define bFM3_ADC0_ADSS23_TS20 *((volatile unsigned int*)(0x424E0510UL)) +#define bFM3_ADC0_ADSS23_TS21 *((volatile unsigned int*)(0x424E0514UL)) +#define bFM3_ADC0_ADSS23_TS22 *((volatile unsigned int*)(0x424E0518UL)) +#define bFM3_ADC0_ADSS23_TS23 *((volatile unsigned int*)(0x424E051CUL)) +#define bFM3_ADC0_ADSS23_TS24 *((volatile unsigned int*)(0x424E0520UL)) +#define bFM3_ADC0_ADSS23_TS25 *((volatile unsigned int*)(0x424E0524UL)) +#define bFM3_ADC0_ADSS23_TS26 *((volatile unsigned int*)(0x424E0528UL)) +#define bFM3_ADC0_ADSS23_TS27 *((volatile unsigned int*)(0x424E052CUL)) +#define bFM3_ADC0_ADSS23_TS28 *((volatile unsigned int*)(0x424E0530UL)) +#define bFM3_ADC0_ADSS23_TS29 *((volatile unsigned int*)(0x424E0534UL)) +#define bFM3_ADC0_ADSS23_TS30 *((volatile unsigned int*)(0x424E0538UL)) +#define bFM3_ADC0_ADSS23_TS31 *((volatile unsigned int*)(0x424E053CUL)) +#define bFM3_ADC0_ADSS2_TS16 *((volatile unsigned int*)(0x424E0500UL)) +#define bFM3_ADC0_ADSS2_TS17 *((volatile unsigned int*)(0x424E0504UL)) +#define bFM3_ADC0_ADSS2_TS18 *((volatile unsigned int*)(0x424E0508UL)) +#define bFM3_ADC0_ADSS2_TS19 *((volatile unsigned int*)(0x424E050CUL)) +#define bFM3_ADC0_ADSS2_TS20 *((volatile unsigned int*)(0x424E0510UL)) +#define bFM3_ADC0_ADSS2_TS21 *((volatile unsigned int*)(0x424E0514UL)) +#define bFM3_ADC0_ADSS2_TS22 *((volatile unsigned int*)(0x424E0518UL)) +#define bFM3_ADC0_ADSS2_TS23 *((volatile unsigned int*)(0x424E051CUL)) +#define bFM3_ADC0_ADSS3_TS24 *((volatile unsigned int*)(0x424E0520UL)) +#define bFM3_ADC0_ADSS3_TS25 *((volatile unsigned int*)(0x424E0524UL)) +#define bFM3_ADC0_ADSS3_TS26 *((volatile unsigned int*)(0x424E0528UL)) +#define bFM3_ADC0_ADSS3_TS27 *((volatile unsigned int*)(0x424E052CUL)) +#define bFM3_ADC0_ADSS3_TS28 *((volatile unsigned int*)(0x424E0530UL)) +#define bFM3_ADC0_ADSS3_TS29 *((volatile unsigned int*)(0x424E0534UL)) +#define bFM3_ADC0_ADSS3_TS30 *((volatile unsigned int*)(0x424E0538UL)) +#define bFM3_ADC0_ADSS3_TS31 *((volatile unsigned int*)(0x424E053CUL)) +#define bFM3_ADC0_ADSS01_TS0 *((volatile unsigned int*)(0x424E0580UL)) +#define bFM3_ADC0_ADSS01_TS1 *((volatile unsigned int*)(0x424E0584UL)) +#define bFM3_ADC0_ADSS01_TS2 *((volatile unsigned int*)(0x424E0588UL)) +#define bFM3_ADC0_ADSS01_TS3 *((volatile unsigned int*)(0x424E058CUL)) +#define bFM3_ADC0_ADSS01_TS4 *((volatile unsigned int*)(0x424E0590UL)) +#define bFM3_ADC0_ADSS01_TS5 *((volatile unsigned int*)(0x424E0594UL)) +#define bFM3_ADC0_ADSS01_TS6 *((volatile unsigned int*)(0x424E0598UL)) +#define bFM3_ADC0_ADSS01_TS7 *((volatile unsigned int*)(0x424E059CUL)) +#define bFM3_ADC0_ADSS01_TS8 *((volatile unsigned int*)(0x424E05A0UL)) +#define bFM3_ADC0_ADSS01_TS9 *((volatile unsigned int*)(0x424E05A4UL)) +#define bFM3_ADC0_ADSS01_TS10 *((volatile unsigned int*)(0x424E05A8UL)) +#define bFM3_ADC0_ADSS01_TS11 *((volatile unsigned int*)(0x424E05ACUL)) +#define bFM3_ADC0_ADSS01_TS12 *((volatile unsigned int*)(0x424E05B0UL)) +#define bFM3_ADC0_ADSS01_TS13 *((volatile unsigned int*)(0x424E05B4UL)) +#define bFM3_ADC0_ADSS01_TS14 *((volatile unsigned int*)(0x424E05B8UL)) +#define bFM3_ADC0_ADSS01_TS15 *((volatile unsigned int*)(0x424E05BCUL)) +#define bFM3_ADC0_ADSS0_TS0 *((volatile unsigned int*)(0x424E0580UL)) +#define bFM3_ADC0_ADSS0_TS1 *((volatile unsigned int*)(0x424E0584UL)) +#define bFM3_ADC0_ADSS0_TS2 *((volatile unsigned int*)(0x424E0588UL)) +#define bFM3_ADC0_ADSS0_TS3 *((volatile unsigned int*)(0x424E058CUL)) +#define bFM3_ADC0_ADSS0_TS4 *((volatile unsigned int*)(0x424E0590UL)) +#define bFM3_ADC0_ADSS0_TS5 *((volatile unsigned int*)(0x424E0594UL)) +#define bFM3_ADC0_ADSS0_TS6 *((volatile unsigned int*)(0x424E0598UL)) +#define bFM3_ADC0_ADSS0_TS7 *((volatile unsigned int*)(0x424E059CUL)) +#define bFM3_ADC0_ADSS1_TS8 *((volatile unsigned int*)(0x424E05A0UL)) +#define bFM3_ADC0_ADSS1_TS9 *((volatile unsigned int*)(0x424E05A4UL)) +#define bFM3_ADC0_ADSS1_TS10 *((volatile unsigned int*)(0x424E05A8UL)) +#define bFM3_ADC0_ADSS1_TS11 *((volatile unsigned int*)(0x424E05ACUL)) +#define bFM3_ADC0_ADSS1_TS12 *((volatile unsigned int*)(0x424E05B0UL)) +#define bFM3_ADC0_ADSS1_TS13 *((volatile unsigned int*)(0x424E05B4UL)) +#define bFM3_ADC0_ADSS1_TS14 *((volatile unsigned int*)(0x424E05B8UL)) +#define bFM3_ADC0_ADSS1_TS15 *((volatile unsigned int*)(0x424E05BCUL)) +#define bFM3_ADC0_ADST01_ST10 *((volatile unsigned int*)(0x424E0600UL)) +#define bFM3_ADC0_ADST01_ST11 *((volatile unsigned int*)(0x424E0604UL)) +#define bFM3_ADC0_ADST01_ST12 *((volatile unsigned int*)(0x424E0608UL)) +#define bFM3_ADC0_ADST01_ST13 *((volatile unsigned int*)(0x424E060CUL)) +#define bFM3_ADC0_ADST01_ST14 *((volatile unsigned int*)(0x424E0610UL)) +#define bFM3_ADC0_ADST01_STX10 *((volatile unsigned int*)(0x424E0614UL)) +#define bFM3_ADC0_ADST01_STX11 *((volatile unsigned int*)(0x424E0618UL)) +#define bFM3_ADC0_ADST01_STX12 *((volatile unsigned int*)(0x424E061CUL)) +#define bFM3_ADC0_ADST01_ST00 *((volatile unsigned int*)(0x424E0620UL)) +#define bFM3_ADC0_ADST01_ST01 *((volatile unsigned int*)(0x424E0624UL)) +#define bFM3_ADC0_ADST01_ST02 *((volatile unsigned int*)(0x424E0628UL)) +#define bFM3_ADC0_ADST01_ST03 *((volatile unsigned int*)(0x424E062CUL)) +#define bFM3_ADC0_ADST01_ST04 *((volatile unsigned int*)(0x424E0630UL)) +#define bFM3_ADC0_ADST01_STX00 *((volatile unsigned int*)(0x424E0634UL)) +#define bFM3_ADC0_ADST01_STX01 *((volatile unsigned int*)(0x424E0638UL)) +#define bFM3_ADC0_ADST01_STX02 *((volatile unsigned int*)(0x424E063CUL)) +#define bFM3_ADC0_ADST1_ST10 *((volatile unsigned int*)(0x424E0600UL)) +#define bFM3_ADC0_ADST1_ST11 *((volatile unsigned int*)(0x424E0604UL)) +#define bFM3_ADC0_ADST1_ST12 *((volatile unsigned int*)(0x424E0608UL)) +#define bFM3_ADC0_ADST1_ST13 *((volatile unsigned int*)(0x424E060CUL)) +#define bFM3_ADC0_ADST1_ST14 *((volatile unsigned int*)(0x424E0610UL)) +#define bFM3_ADC0_ADST1_STX10 *((volatile unsigned int*)(0x424E0614UL)) +#define bFM3_ADC0_ADST1_STX11 *((volatile unsigned int*)(0x424E0618UL)) +#define bFM3_ADC0_ADST1_STX12 *((volatile unsigned int*)(0x424E061CUL)) +#define bFM3_ADC0_ADST0_ST00 *((volatile unsigned int*)(0x424E0620UL)) +#define bFM3_ADC0_ADST0_ST01 *((volatile unsigned int*)(0x424E0624UL)) +#define bFM3_ADC0_ADST0_ST02 *((volatile unsigned int*)(0x424E0628UL)) +#define bFM3_ADC0_ADST0_ST03 *((volatile unsigned int*)(0x424E062CUL)) +#define bFM3_ADC0_ADST0_ST04 *((volatile unsigned int*)(0x424E0630UL)) +#define bFM3_ADC0_ADST0_STX00 *((volatile unsigned int*)(0x424E0634UL)) +#define bFM3_ADC0_ADST0_STX01 *((volatile unsigned int*)(0x424E0638UL)) +#define bFM3_ADC0_ADST0_STX02 *((volatile unsigned int*)(0x424E063CUL)) +#define bFM3_ADC0_ADCT_CT0 *((volatile unsigned int*)(0x424E0680UL)) +#define bFM3_ADC0_ADCT_CT1 *((volatile unsigned int*)(0x424E0684UL)) +#define bFM3_ADC0_ADCT_CT2 *((volatile unsigned int*)(0x424E0688UL)) +#define bFM3_ADC0_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E0700UL)) +#define bFM3_ADC0_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E0704UL)) +#define bFM3_ADC0_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E0708UL)) +#define bFM3_ADC0_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E070CUL)) +#define bFM3_ADC0_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E0720UL)) +#define bFM3_ADC0_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E0724UL)) +#define bFM3_ADC0_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E0728UL)) +#define bFM3_ADC0_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E072CUL)) +#define bFM3_ADC0_ADCEN_ENBL *((volatile unsigned int*)(0x424E0780UL)) +#define bFM3_ADC0_ADCEN_READY *((volatile unsigned int*)(0x424E0784UL)) + +/* 12-bit ADC unit 1 registers */ +#define bFM3_ADC1_ADSR_SCS *((volatile unsigned int*)(0x424E2000UL)) +#define bFM3_ADC1_ADSR_PCS *((volatile unsigned int*)(0x424E2004UL)) +#define bFM3_ADC1_ADSR_PCNS *((volatile unsigned int*)(0x424E2008UL)) +#define bFM3_ADC1_ADSR_FDAS *((volatile unsigned int*)(0x424E2018UL)) +#define bFM3_ADC1_ADSR_ADSTP *((volatile unsigned int*)(0x424E201CUL)) +#define bFM3_ADC1_ADCR_OVRIE *((volatile unsigned int*)(0x424E2020UL)) +#define bFM3_ADC1_ADCR_CMPIE *((volatile unsigned int*)(0x424E2024UL)) +#define bFM3_ADC1_ADCR_PCIE *((volatile unsigned int*)(0x424E2028UL)) +#define bFM3_ADC1_ADCR_SCIE *((volatile unsigned int*)(0x424E202CUL)) +#define bFM3_ADC1_ADCR_CMPIF *((volatile unsigned int*)(0x424E2034UL)) +#define bFM3_ADC1_ADCR_PCIF *((volatile unsigned int*)(0x424E2038UL)) +#define bFM3_ADC1_ADCR_SCIF *((volatile unsigned int*)(0x424E203CUL)) +#define bFM3_ADC1_SFNS_SFS0 *((volatile unsigned int*)(0x424E2100UL)) +#define bFM3_ADC1_SFNS_SFS1 *((volatile unsigned int*)(0x424E2104UL)) +#define bFM3_ADC1_SFNS_SFS2 *((volatile unsigned int*)(0x424E2108UL)) +#define bFM3_ADC1_SFNS_SFS3 *((volatile unsigned int*)(0x424E210CUL)) +#define bFM3_ADC1_SCCR_SSTR *((volatile unsigned int*)(0x424E2120UL)) +#define bFM3_ADC1_SCCR_SHEN *((volatile unsigned int*)(0x424E2124UL)) +#define bFM3_ADC1_SCCR_RPT *((volatile unsigned int*)(0x424E2128UL)) +#define bFM3_ADC1_SCCR_SFCLR *((volatile unsigned int*)(0x424E2130UL)) +#define bFM3_ADC1_SCCR_SOVR *((volatile unsigned int*)(0x424E2134UL)) +#define bFM3_ADC1_SCCR_SFUL *((volatile unsigned int*)(0x424E2138UL)) +#define bFM3_ADC1_SCCR_SEMP *((volatile unsigned int*)(0x424E213CUL)) +#define bFM3_ADC1_SCFD_SC0 *((volatile unsigned int*)(0x424E2180UL)) +#define bFM3_ADC1_SCFD_SC1 *((volatile unsigned int*)(0x424E2184UL)) +#define bFM3_ADC1_SCFD_SC2 *((volatile unsigned int*)(0x424E2188UL)) +#define bFM3_ADC1_SCFD_SC3 *((volatile unsigned int*)(0x424E218CUL)) +#define bFM3_ADC1_SCFD_SC4 *((volatile unsigned int*)(0x424E2190UL)) +#define bFM3_ADC1_SCFD_RS0 *((volatile unsigned int*)(0x424E21A0UL)) +#define bFM3_ADC1_SCFD_RS1 *((volatile unsigned int*)(0x424E21A4UL)) +#define bFM3_ADC1_SCFD_INVL *((volatile unsigned int*)(0x424E21B0UL)) +#define bFM3_ADC1_SCFD_SD0 *((volatile unsigned int*)(0x424E21D0UL)) +#define bFM3_ADC1_SCFD_SD1 *((volatile unsigned int*)(0x424E21D4UL)) +#define bFM3_ADC1_SCFD_SD2 *((volatile unsigned int*)(0x424E21D8UL)) +#define bFM3_ADC1_SCFD_SD3 *((volatile unsigned int*)(0x424E21DCUL)) +#define bFM3_ADC1_SCFD_SD4 *((volatile unsigned int*)(0x424E21E0UL)) +#define bFM3_ADC1_SCFD_SD5 *((volatile unsigned int*)(0x424E21E4UL)) +#define bFM3_ADC1_SCFD_SD6 *((volatile unsigned int*)(0x424E21E8UL)) +#define bFM3_ADC1_SCFD_SD7 *((volatile unsigned int*)(0x424E21ECUL)) +#define bFM3_ADC1_SCFD_SD8 *((volatile unsigned int*)(0x424E21F0UL)) +#define bFM3_ADC1_SCFD_SD9 *((volatile unsigned int*)(0x424E21F4UL)) +#define bFM3_ADC1_SCFD_SD10 *((volatile unsigned int*)(0x424E21F8UL)) +#define bFM3_ADC1_SCFD_SD11 *((volatile unsigned int*)(0x424E21FCUL)) +#define bFM3_ADC1_SCFDL_SC0 *((volatile unsigned int*)(0x424E2180UL)) +#define bFM3_ADC1_SCFDL_SC1 *((volatile unsigned int*)(0x424E2184UL)) +#define bFM3_ADC1_SCFDL_SC2 *((volatile unsigned int*)(0x424E2188UL)) +#define bFM3_ADC1_SCFDL_SC3 *((volatile unsigned int*)(0x424E218CUL)) +#define bFM3_ADC1_SCFDL_SC4 *((volatile unsigned int*)(0x424E2190UL)) +#define bFM3_ADC1_SCFDL_RS0 *((volatile unsigned int*)(0x424E21A0UL)) +#define bFM3_ADC1_SCFDL_RS1 *((volatile unsigned int*)(0x424E21A4UL)) +#define bFM3_ADC1_SCFDL_INVL *((volatile unsigned int*)(0x424E21B0UL)) +#define bFM3_ADC1_SCFDH_SD0 *((volatile unsigned int*)(0x424E21D0UL)) +#define bFM3_ADC1_SCFDH_SD1 *((volatile unsigned int*)(0x424E21D4UL)) +#define bFM3_ADC1_SCFDH_SD2 *((volatile unsigned int*)(0x424E21D8UL)) +#define bFM3_ADC1_SCFDH_SD3 *((volatile unsigned int*)(0x424E21DCUL)) +#define bFM3_ADC1_SCFDH_SD4 *((volatile unsigned int*)(0x424E21E0UL)) +#define bFM3_ADC1_SCFDH_SD5 *((volatile unsigned int*)(0x424E21E4UL)) +#define bFM3_ADC1_SCFDH_SD6 *((volatile unsigned int*)(0x424E21E8UL)) +#define bFM3_ADC1_SCFDH_SD7 *((volatile unsigned int*)(0x424E21ECUL)) +#define bFM3_ADC1_SCFDH_SD8 *((volatile unsigned int*)(0x424E21F0UL)) +#define bFM3_ADC1_SCFDH_SD9 *((volatile unsigned int*)(0x424E21F4UL)) +#define bFM3_ADC1_SCFDH_SD10 *((volatile unsigned int*)(0x424E21F8UL)) +#define bFM3_ADC1_SCFDH_SD11 *((volatile unsigned int*)(0x424E21FCUL)) +#define bFM3_ADC1_SCIS23_AN16 *((volatile unsigned int*)(0x424E2200UL)) +#define bFM3_ADC1_SCIS23_AN17 *((volatile unsigned int*)(0x424E2204UL)) +#define bFM3_ADC1_SCIS23_AN18 *((volatile unsigned int*)(0x424E2208UL)) +#define bFM3_ADC1_SCIS23_AN19 *((volatile unsigned int*)(0x424E220CUL)) +#define bFM3_ADC1_SCIS23_AN20 *((volatile unsigned int*)(0x424E2210UL)) +#define bFM3_ADC1_SCIS23_AN21 *((volatile unsigned int*)(0x424E2214UL)) +#define bFM3_ADC1_SCIS23_AN22 *((volatile unsigned int*)(0x424E2218UL)) +#define bFM3_ADC1_SCIS23_AN23 *((volatile unsigned int*)(0x424E221CUL)) +#define bFM3_ADC1_SCIS23_AN24 *((volatile unsigned int*)(0x424E2220UL)) +#define bFM3_ADC1_SCIS23_AN25 *((volatile unsigned int*)(0x424E2224UL)) +#define bFM3_ADC1_SCIS23_AN26 *((volatile unsigned int*)(0x424E2228UL)) +#define bFM3_ADC1_SCIS23_AN27 *((volatile unsigned int*)(0x424E222CUL)) +#define bFM3_ADC1_SCIS23_AN28 *((volatile unsigned int*)(0x424E2230UL)) +#define bFM3_ADC1_SCIS23_AN29 *((volatile unsigned int*)(0x424E2234UL)) +#define bFM3_ADC1_SCIS23_AN30 *((volatile unsigned int*)(0x424E2238UL)) +#define bFM3_ADC1_SCIS23_AN31 *((volatile unsigned int*)(0x424E223CUL)) +#define bFM3_ADC1_SCIS2_AN16 *((volatile unsigned int*)(0x424E2200UL)) +#define bFM3_ADC1_SCIS2_AN17 *((volatile unsigned int*)(0x424E2204UL)) +#define bFM3_ADC1_SCIS2_AN18 *((volatile unsigned int*)(0x424E2208UL)) +#define bFM3_ADC1_SCIS2_AN19 *((volatile unsigned int*)(0x424E220CUL)) +#define bFM3_ADC1_SCIS2_AN20 *((volatile unsigned int*)(0x424E2210UL)) +#define bFM3_ADC1_SCIS2_AN21 *((volatile unsigned int*)(0x424E2214UL)) +#define bFM3_ADC1_SCIS2_AN22 *((volatile unsigned int*)(0x424E2218UL)) +#define bFM3_ADC1_SCIS2_AN23 *((volatile unsigned int*)(0x424E221CUL)) +#define bFM3_ADC1_SCIS3_AN24 *((volatile unsigned int*)(0x424E2220UL)) +#define bFM3_ADC1_SCIS3_AN25 *((volatile unsigned int*)(0x424E2224UL)) +#define bFM3_ADC1_SCIS3_AN26 *((volatile unsigned int*)(0x424E2228UL)) +#define bFM3_ADC1_SCIS3_AN27 *((volatile unsigned int*)(0x424E222CUL)) +#define bFM3_ADC1_SCIS3_AN28 *((volatile unsigned int*)(0x424E2230UL)) +#define bFM3_ADC1_SCIS3_AN29 *((volatile unsigned int*)(0x424E2234UL)) +#define bFM3_ADC1_SCIS3_AN30 *((volatile unsigned int*)(0x424E2238UL)) +#define bFM3_ADC1_SCIS3_AN31 *((volatile unsigned int*)(0x424E223CUL)) +#define bFM3_ADC1_SCIS01_AN0 *((volatile unsigned int*)(0x424E2280UL)) +#define bFM3_ADC1_SCIS01_AN1 *((volatile unsigned int*)(0x424E2284UL)) +#define bFM3_ADC1_SCIS01_AN2 *((volatile unsigned int*)(0x424E2288UL)) +#define bFM3_ADC1_SCIS01_AN3 *((volatile unsigned int*)(0x424E228CUL)) +#define bFM3_ADC1_SCIS01_AN4 *((volatile unsigned int*)(0x424E2290UL)) +#define bFM3_ADC1_SCIS01_AN5 *((volatile unsigned int*)(0x424E2294UL)) +#define bFM3_ADC1_SCIS01_AN6 *((volatile unsigned int*)(0x424E2298UL)) +#define bFM3_ADC1_SCIS01_AN7 *((volatile unsigned int*)(0x424E229CUL)) +#define bFM3_ADC1_SCIS01_AN8 *((volatile unsigned int*)(0x424E22A0UL)) +#define bFM3_ADC1_SCIS01_AN9 *((volatile unsigned int*)(0x424E22A4UL)) +#define bFM3_ADC1_SCIS01_AN10 *((volatile unsigned int*)(0x424E22A8UL)) +#define bFM3_ADC1_SCIS01_AN11 *((volatile unsigned int*)(0x424E22ACUL)) +#define bFM3_ADC1_SCIS01_AN12 *((volatile unsigned int*)(0x424E22B0UL)) +#define bFM3_ADC1_SCIS01_AN13 *((volatile unsigned int*)(0x424E22B4UL)) +#define bFM3_ADC1_SCIS01_AN14 *((volatile unsigned int*)(0x424E22B8UL)) +#define bFM3_ADC1_SCIS01_AN15 *((volatile unsigned int*)(0x424E22BCUL)) +#define bFM3_ADC1_SCIS0_AN0 *((volatile unsigned int*)(0x424E2280UL)) +#define bFM3_ADC1_SCIS0_AN1 *((volatile unsigned int*)(0x424E2284UL)) +#define bFM3_ADC1_SCIS0_AN2 *((volatile unsigned int*)(0x424E2288UL)) +#define bFM3_ADC1_SCIS0_AN3 *((volatile unsigned int*)(0x424E228CUL)) +#define bFM3_ADC1_SCIS0_AN4 *((volatile unsigned int*)(0x424E2290UL)) +#define bFM3_ADC1_SCIS0_AN5 *((volatile unsigned int*)(0x424E2294UL)) +#define bFM3_ADC1_SCIS0_AN6 *((volatile unsigned int*)(0x424E2298UL)) +#define bFM3_ADC1_SCIS0_AN7 *((volatile unsigned int*)(0x424E229CUL)) +#define bFM3_ADC1_SCIS1_AN8 *((volatile unsigned int*)(0x424E22A0UL)) +#define bFM3_ADC1_SCIS1_AN9 *((volatile unsigned int*)(0x424E22A4UL)) +#define bFM3_ADC1_SCIS1_AN10 *((volatile unsigned int*)(0x424E22A8UL)) +#define bFM3_ADC1_SCIS1_AN11 *((volatile unsigned int*)(0x424E22ACUL)) +#define bFM3_ADC1_SCIS1_AN12 *((volatile unsigned int*)(0x424E22B0UL)) +#define bFM3_ADC1_SCIS1_AN13 *((volatile unsigned int*)(0x424E22B4UL)) +#define bFM3_ADC1_SCIS1_AN14 *((volatile unsigned int*)(0x424E22B8UL)) +#define bFM3_ADC1_SCIS1_AN15 *((volatile unsigned int*)(0x424E22BCUL)) +#define bFM3_ADC1_PFNS_PFS0 *((volatile unsigned int*)(0x424E2300UL)) +#define bFM3_ADC1_PFNS_PFS1 *((volatile unsigned int*)(0x424E2304UL)) +#define bFM3_ADC1_PFNS_TEST0 *((volatile unsigned int*)(0x424E2310UL)) +#define bFM3_ADC1_PFNS_TEST1 *((volatile unsigned int*)(0x424E2314UL)) +#define bFM3_ADC1_PCCR_PSTR *((volatile unsigned int*)(0x424E2320UL)) +#define bFM3_ADC1_PCCR_PHEN *((volatile unsigned int*)(0x424E2324UL)) +#define bFM3_ADC1_PCCR_PEEN *((volatile unsigned int*)(0x424E2328UL)) +#define bFM3_ADC1_PCCR_ESCE *((volatile unsigned int*)(0x424E232CUL)) +#define bFM3_ADC1_PCCR_PFCLR *((volatile unsigned int*)(0x424E2330UL)) +#define bFM3_ADC1_PCCR_POVR *((volatile unsigned int*)(0x424E2334UL)) +#define bFM3_ADC1_PCCR_PFUL *((volatile unsigned int*)(0x424E2338UL)) +#define bFM3_ADC1_PCCR_PEMP *((volatile unsigned int*)(0x424E233CUL)) +#define bFM3_ADC1_PCFD_PC0 *((volatile unsigned int*)(0x424E2380UL)) +#define bFM3_ADC1_PCFD_PC1 *((volatile unsigned int*)(0x424E2384UL)) +#define bFM3_ADC1_PCFD_PC2 *((volatile unsigned int*)(0x424E2388UL)) +#define bFM3_ADC1_PCFD_PC3 *((volatile unsigned int*)(0x424E238CUL)) +#define bFM3_ADC1_PCFD_PC4 *((volatile unsigned int*)(0x424E2390UL)) +#define bFM3_ADC1_PCFD_RS0 *((volatile unsigned int*)(0x424E23A0UL)) +#define bFM3_ADC1_PCFD_RS1 *((volatile unsigned int*)(0x424E23A4UL)) +#define bFM3_ADC1_PCFD_RS2 *((volatile unsigned int*)(0x424E23A8UL)) +#define bFM3_ADC1_PCFD_INVL *((volatile unsigned int*)(0x424E23B0UL)) +#define bFM3_ADC1_PCFD_PD0 *((volatile unsigned int*)(0x424E23D0UL)) +#define bFM3_ADC1_PCFD_PD1 *((volatile unsigned int*)(0x424E23D4UL)) +#define bFM3_ADC1_PCFD_PD2 *((volatile unsigned int*)(0x424E23D8UL)) +#define bFM3_ADC1_PCFD_PD3 *((volatile unsigned int*)(0x424E23DCUL)) +#define bFM3_ADC1_PCFD_PD4 *((volatile unsigned int*)(0x424E23E0UL)) +#define bFM3_ADC1_PCFD_PD5 *((volatile unsigned int*)(0x424E23E4UL)) +#define bFM3_ADC1_PCFD_PD6 *((volatile unsigned int*)(0x424E23E8UL)) +#define bFM3_ADC1_PCFD_PD7 *((volatile unsigned int*)(0x424E23ECUL)) +#define bFM3_ADC1_PCFD_PD8 *((volatile unsigned int*)(0x424E23F0UL)) +#define bFM3_ADC1_PCFD_PD9 *((volatile unsigned int*)(0x424E23F4UL)) +#define bFM3_ADC1_PCFD_PD10 *((volatile unsigned int*)(0x424E23F8UL)) +#define bFM3_ADC1_PCFD_PD11 *((volatile unsigned int*)(0x424E23FCUL)) +#define bFM3_ADC1_PCFDL_PC0 *((volatile unsigned int*)(0x424E2380UL)) +#define bFM3_ADC1_PCFDL_PC1 *((volatile unsigned int*)(0x424E2384UL)) +#define bFM3_ADC1_PCFDL_PC2 *((volatile unsigned int*)(0x424E2388UL)) +#define bFM3_ADC1_PCFDL_PC3 *((volatile unsigned int*)(0x424E238CUL)) +#define bFM3_ADC1_PCFDL_PC4 *((volatile unsigned int*)(0x424E2390UL)) +#define bFM3_ADC1_PCFDL_RS0 *((volatile unsigned int*)(0x424E23A0UL)) +#define bFM3_ADC1_PCFDL_RS1 *((volatile unsigned int*)(0x424E23A4UL)) +#define bFM3_ADC1_PCFDL_RS2 *((volatile unsigned int*)(0x424E23A8UL)) +#define bFM3_ADC1_PCFDL_INVL *((volatile unsigned int*)(0x424E23B0UL)) +#define bFM3_ADC1_PCFDH_PD0 *((volatile unsigned int*)(0x424E23D0UL)) +#define bFM3_ADC1_PCFDH_PD1 *((volatile unsigned int*)(0x424E23D4UL)) +#define bFM3_ADC1_PCFDH_PD2 *((volatile unsigned int*)(0x424E23D8UL)) +#define bFM3_ADC1_PCFDH_PD3 *((volatile unsigned int*)(0x424E23DCUL)) +#define bFM3_ADC1_PCFDH_PD4 *((volatile unsigned int*)(0x424E23E0UL)) +#define bFM3_ADC1_PCFDH_PD5 *((volatile unsigned int*)(0x424E23E4UL)) +#define bFM3_ADC1_PCFDH_PD6 *((volatile unsigned int*)(0x424E23E8UL)) +#define bFM3_ADC1_PCFDH_PD7 *((volatile unsigned int*)(0x424E23ECUL)) +#define bFM3_ADC1_PCFDH_PD8 *((volatile unsigned int*)(0x424E23F0UL)) +#define bFM3_ADC1_PCFDH_PD9 *((volatile unsigned int*)(0x424E23F4UL)) +#define bFM3_ADC1_PCFDH_PD10 *((volatile unsigned int*)(0x424E23F8UL)) +#define bFM3_ADC1_PCFDH_PD11 *((volatile unsigned int*)(0x424E23FCUL)) +#define bFM3_ADC1_PCIS_P1A0 *((volatile unsigned int*)(0x424E2400UL)) +#define bFM3_ADC1_PCIS_P1A1 *((volatile unsigned int*)(0x424E2404UL)) +#define bFM3_ADC1_PCIS_P1A2 *((volatile unsigned int*)(0x424E2408UL)) +#define bFM3_ADC1_PCIS_P2A0 *((volatile unsigned int*)(0x424E240CUL)) +#define bFM3_ADC1_PCIS_P2A1 *((volatile unsigned int*)(0x424E2410UL)) +#define bFM3_ADC1_PCIS_P2A2 *((volatile unsigned int*)(0x424E2414UL)) +#define bFM3_ADC1_PCIS_P2A3 *((volatile unsigned int*)(0x424E2418UL)) +#define bFM3_ADC1_PCIS_P2A4 *((volatile unsigned int*)(0x424E241CUL)) +#define bFM3_ADC1_CMPCR_CCH0 *((volatile unsigned int*)(0x424E2480UL)) +#define bFM3_ADC1_CMPCR_CCH1 *((volatile unsigned int*)(0x424E2484UL)) +#define bFM3_ADC1_CMPCR_CCH2 *((volatile unsigned int*)(0x424E2488UL)) +#define bFM3_ADC1_CMPCR_CCH3 *((volatile unsigned int*)(0x424E248CUL)) +#define bFM3_ADC1_CMPCR_CCH4 *((volatile unsigned int*)(0x424E2490UL)) +#define bFM3_ADC1_CMPCR_CMD0 *((volatile unsigned int*)(0x424E2494UL)) +#define bFM3_ADC1_CMPCR_CMD1 *((volatile unsigned int*)(0x424E2498UL)) +#define bFM3_ADC1_CMPCR_CMPEN *((volatile unsigned int*)(0x424E249CUL)) +#define bFM3_ADC1_CMPD_CMAD2 *((volatile unsigned int*)(0x424E24D8UL)) +#define bFM3_ADC1_CMPD_CMAD3 *((volatile unsigned int*)(0x424E24DCUL)) +#define bFM3_ADC1_CMPD_CMAD4 *((volatile unsigned int*)(0x424E24E0UL)) +#define bFM3_ADC1_CMPD_CMAD5 *((volatile unsigned int*)(0x424E24E4UL)) +#define bFM3_ADC1_CMPD_CMAD6 *((volatile unsigned int*)(0x424E24E8UL)) +#define bFM3_ADC1_CMPD_CMAD7 *((volatile unsigned int*)(0x424E24ECUL)) +#define bFM3_ADC1_CMPD_CMAD8 *((volatile unsigned int*)(0x424E24F0UL)) +#define bFM3_ADC1_CMPD_CMAD9 *((volatile unsigned int*)(0x424E24F4UL)) +#define bFM3_ADC1_CMPD_CMAD10 *((volatile unsigned int*)(0x424E24F8UL)) +#define bFM3_ADC1_CMPD_CMAD11 *((volatile unsigned int*)(0x424E24FCUL)) +#define bFM3_ADC1_ADSS23_TS16 *((volatile unsigned int*)(0x424E2500UL)) +#define bFM3_ADC1_ADSS23_TS17 *((volatile unsigned int*)(0x424E2504UL)) +#define bFM3_ADC1_ADSS23_TS18 *((volatile unsigned int*)(0x424E2508UL)) +#define bFM3_ADC1_ADSS23_TS19 *((volatile unsigned int*)(0x424E250CUL)) +#define bFM3_ADC1_ADSS23_TS20 *((volatile unsigned int*)(0x424E2510UL)) +#define bFM3_ADC1_ADSS23_TS21 *((volatile unsigned int*)(0x424E2514UL)) +#define bFM3_ADC1_ADSS23_TS22 *((volatile unsigned int*)(0x424E2518UL)) +#define bFM3_ADC1_ADSS23_TS23 *((volatile unsigned int*)(0x424E251CUL)) +#define bFM3_ADC1_ADSS23_TS24 *((volatile unsigned int*)(0x424E2520UL)) +#define bFM3_ADC1_ADSS23_TS25 *((volatile unsigned int*)(0x424E2524UL)) +#define bFM3_ADC1_ADSS23_TS26 *((volatile unsigned int*)(0x424E2528UL)) +#define bFM3_ADC1_ADSS23_TS27 *((volatile unsigned int*)(0x424E252CUL)) +#define bFM3_ADC1_ADSS23_TS28 *((volatile unsigned int*)(0x424E2530UL)) +#define bFM3_ADC1_ADSS23_TS29 *((volatile unsigned int*)(0x424E2534UL)) +#define bFM3_ADC1_ADSS23_TS30 *((volatile unsigned int*)(0x424E2538UL)) +#define bFM3_ADC1_ADSS23_TS31 *((volatile unsigned int*)(0x424E253CUL)) +#define bFM3_ADC1_ADSS2_TS16 *((volatile unsigned int*)(0x424E2500UL)) +#define bFM3_ADC1_ADSS2_TS17 *((volatile unsigned int*)(0x424E2504UL)) +#define bFM3_ADC1_ADSS2_TS18 *((volatile unsigned int*)(0x424E2508UL)) +#define bFM3_ADC1_ADSS2_TS19 *((volatile unsigned int*)(0x424E250CUL)) +#define bFM3_ADC1_ADSS2_TS20 *((volatile unsigned int*)(0x424E2510UL)) +#define bFM3_ADC1_ADSS2_TS21 *((volatile unsigned int*)(0x424E2514UL)) +#define bFM3_ADC1_ADSS2_TS22 *((volatile unsigned int*)(0x424E2518UL)) +#define bFM3_ADC1_ADSS2_TS23 *((volatile unsigned int*)(0x424E251CUL)) +#define bFM3_ADC1_ADSS3_TS24 *((volatile unsigned int*)(0x424E2520UL)) +#define bFM3_ADC1_ADSS3_TS25 *((volatile unsigned int*)(0x424E2524UL)) +#define bFM3_ADC1_ADSS3_TS26 *((volatile unsigned int*)(0x424E2528UL)) +#define bFM3_ADC1_ADSS3_TS27 *((volatile unsigned int*)(0x424E252CUL)) +#define bFM3_ADC1_ADSS3_TS28 *((volatile unsigned int*)(0x424E2530UL)) +#define bFM3_ADC1_ADSS3_TS29 *((volatile unsigned int*)(0x424E2534UL)) +#define bFM3_ADC1_ADSS3_TS30 *((volatile unsigned int*)(0x424E2538UL)) +#define bFM3_ADC1_ADSS3_TS31 *((volatile unsigned int*)(0x424E253CUL)) +#define bFM3_ADC1_ADSS01_TS0 *((volatile unsigned int*)(0x424E2580UL)) +#define bFM3_ADC1_ADSS01_TS1 *((volatile unsigned int*)(0x424E2584UL)) +#define bFM3_ADC1_ADSS01_TS2 *((volatile unsigned int*)(0x424E2588UL)) +#define bFM3_ADC1_ADSS01_TS3 *((volatile unsigned int*)(0x424E258CUL)) +#define bFM3_ADC1_ADSS01_TS4 *((volatile unsigned int*)(0x424E2590UL)) +#define bFM3_ADC1_ADSS01_TS5 *((volatile unsigned int*)(0x424E2594UL)) +#define bFM3_ADC1_ADSS01_TS6 *((volatile unsigned int*)(0x424E2598UL)) +#define bFM3_ADC1_ADSS01_TS7 *((volatile unsigned int*)(0x424E259CUL)) +#define bFM3_ADC1_ADSS01_TS8 *((volatile unsigned int*)(0x424E25A0UL)) +#define bFM3_ADC1_ADSS01_TS9 *((volatile unsigned int*)(0x424E25A4UL)) +#define bFM3_ADC1_ADSS01_TS10 *((volatile unsigned int*)(0x424E25A8UL)) +#define bFM3_ADC1_ADSS01_TS11 *((volatile unsigned int*)(0x424E25ACUL)) +#define bFM3_ADC1_ADSS01_TS12 *((volatile unsigned int*)(0x424E25B0UL)) +#define bFM3_ADC1_ADSS01_TS13 *((volatile unsigned int*)(0x424E25B4UL)) +#define bFM3_ADC1_ADSS01_TS14 *((volatile unsigned int*)(0x424E25B8UL)) +#define bFM3_ADC1_ADSS01_TS15 *((volatile unsigned int*)(0x424E25BCUL)) +#define bFM3_ADC1_ADSS0_TS0 *((volatile unsigned int*)(0x424E2580UL)) +#define bFM3_ADC1_ADSS0_TS1 *((volatile unsigned int*)(0x424E2584UL)) +#define bFM3_ADC1_ADSS0_TS2 *((volatile unsigned int*)(0x424E2588UL)) +#define bFM3_ADC1_ADSS0_TS3 *((volatile unsigned int*)(0x424E258CUL)) +#define bFM3_ADC1_ADSS0_TS4 *((volatile unsigned int*)(0x424E2590UL)) +#define bFM3_ADC1_ADSS0_TS5 *((volatile unsigned int*)(0x424E2594UL)) +#define bFM3_ADC1_ADSS0_TS6 *((volatile unsigned int*)(0x424E2598UL)) +#define bFM3_ADC1_ADSS0_TS7 *((volatile unsigned int*)(0x424E259CUL)) +#define bFM3_ADC1_ADSS1_TS8 *((volatile unsigned int*)(0x424E25A0UL)) +#define bFM3_ADC1_ADSS1_TS9 *((volatile unsigned int*)(0x424E25A4UL)) +#define bFM3_ADC1_ADSS1_TS10 *((volatile unsigned int*)(0x424E25A8UL)) +#define bFM3_ADC1_ADSS1_TS11 *((volatile unsigned int*)(0x424E25ACUL)) +#define bFM3_ADC1_ADSS1_TS12 *((volatile unsigned int*)(0x424E25B0UL)) +#define bFM3_ADC1_ADSS1_TS13 *((volatile unsigned int*)(0x424E25B4UL)) +#define bFM3_ADC1_ADSS1_TS14 *((volatile unsigned int*)(0x424E25B8UL)) +#define bFM3_ADC1_ADSS1_TS15 *((volatile unsigned int*)(0x424E25BCUL)) +#define bFM3_ADC1_ADST01_ST10 *((volatile unsigned int*)(0x424E2600UL)) +#define bFM3_ADC1_ADST01_ST11 *((volatile unsigned int*)(0x424E2604UL)) +#define bFM3_ADC1_ADST01_ST12 *((volatile unsigned int*)(0x424E2608UL)) +#define bFM3_ADC1_ADST01_ST13 *((volatile unsigned int*)(0x424E260CUL)) +#define bFM3_ADC1_ADST01_ST14 *((volatile unsigned int*)(0x424E2610UL)) +#define bFM3_ADC1_ADST01_STX10 *((volatile unsigned int*)(0x424E2614UL)) +#define bFM3_ADC1_ADST01_STX11 *((volatile unsigned int*)(0x424E2618UL)) +#define bFM3_ADC1_ADST01_STX12 *((volatile unsigned int*)(0x424E261CUL)) +#define bFM3_ADC1_ADST01_ST00 *((volatile unsigned int*)(0x424E2620UL)) +#define bFM3_ADC1_ADST01_ST01 *((volatile unsigned int*)(0x424E2624UL)) +#define bFM3_ADC1_ADST01_ST02 *((volatile unsigned int*)(0x424E2628UL)) +#define bFM3_ADC1_ADST01_ST03 *((volatile unsigned int*)(0x424E262CUL)) +#define bFM3_ADC1_ADST01_ST04 *((volatile unsigned int*)(0x424E2630UL)) +#define bFM3_ADC1_ADST01_STX00 *((volatile unsigned int*)(0x424E2634UL)) +#define bFM3_ADC1_ADST01_STX01 *((volatile unsigned int*)(0x424E2638UL)) +#define bFM3_ADC1_ADST01_STX02 *((volatile unsigned int*)(0x424E263CUL)) +#define bFM3_ADC1_ADST1_ST10 *((volatile unsigned int*)(0x424E2600UL)) +#define bFM3_ADC1_ADST1_ST11 *((volatile unsigned int*)(0x424E2604UL)) +#define bFM3_ADC1_ADST1_ST12 *((volatile unsigned int*)(0x424E2608UL)) +#define bFM3_ADC1_ADST1_ST13 *((volatile unsigned int*)(0x424E260CUL)) +#define bFM3_ADC1_ADST1_ST14 *((volatile unsigned int*)(0x424E2610UL)) +#define bFM3_ADC1_ADST1_STX10 *((volatile unsigned int*)(0x424E2614UL)) +#define bFM3_ADC1_ADST1_STX11 *((volatile unsigned int*)(0x424E2618UL)) +#define bFM3_ADC1_ADST1_STX12 *((volatile unsigned int*)(0x424E261CUL)) +#define bFM3_ADC1_ADST0_ST00 *((volatile unsigned int*)(0x424E2620UL)) +#define bFM3_ADC1_ADST0_ST01 *((volatile unsigned int*)(0x424E2624UL)) +#define bFM3_ADC1_ADST0_ST02 *((volatile unsigned int*)(0x424E2628UL)) +#define bFM3_ADC1_ADST0_ST03 *((volatile unsigned int*)(0x424E262CUL)) +#define bFM3_ADC1_ADST0_ST04 *((volatile unsigned int*)(0x424E2630UL)) +#define bFM3_ADC1_ADST0_STX00 *((volatile unsigned int*)(0x424E2634UL)) +#define bFM3_ADC1_ADST0_STX01 *((volatile unsigned int*)(0x424E2638UL)) +#define bFM3_ADC1_ADST0_STX02 *((volatile unsigned int*)(0x424E263CUL)) +#define bFM3_ADC1_ADCT_CT0 *((volatile unsigned int*)(0x424E2680UL)) +#define bFM3_ADC1_ADCT_CT1 *((volatile unsigned int*)(0x424E2684UL)) +#define bFM3_ADC1_ADCT_CT2 *((volatile unsigned int*)(0x424E2688UL)) +#define bFM3_ADC1_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E2700UL)) +#define bFM3_ADC1_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E2704UL)) +#define bFM3_ADC1_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E2708UL)) +#define bFM3_ADC1_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E270CUL)) +#define bFM3_ADC1_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E2720UL)) +#define bFM3_ADC1_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E2724UL)) +#define bFM3_ADC1_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E2728UL)) +#define bFM3_ADC1_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E272CUL)) +#define bFM3_ADC1_ADCEN_ENBL *((volatile unsigned int*)(0x424E2780UL)) +#define bFM3_ADC1_ADCEN_READY *((volatile unsigned int*)(0x424E2784UL)) + +/* 12-bit ADC unit 2 registers */ +#define bFM3_ADC2_ADSR_SCS *((volatile unsigned int*)(0x424E4000UL)) +#define bFM3_ADC2_ADSR_PCS *((volatile unsigned int*)(0x424E4004UL)) +#define bFM3_ADC2_ADSR_PCNS *((volatile unsigned int*)(0x424E4008UL)) +#define bFM3_ADC2_ADSR_FDAS *((volatile unsigned int*)(0x424E4018UL)) +#define bFM3_ADC2_ADSR_ADSTP *((volatile unsigned int*)(0x424E401CUL)) +#define bFM3_ADC2_ADCR_OVRIE *((volatile unsigned int*)(0x424E4020UL)) +#define bFM3_ADC2_ADCR_CMPIE *((volatile unsigned int*)(0x424E4024UL)) +#define bFM3_ADC2_ADCR_PCIE *((volatile unsigned int*)(0x424E4028UL)) +#define bFM3_ADC2_ADCR_SCIE *((volatile unsigned int*)(0x424E402CUL)) +#define bFM3_ADC2_ADCR_CMPIF *((volatile unsigned int*)(0x424E4034UL)) +#define bFM3_ADC2_ADCR_PCIF *((volatile unsigned int*)(0x424E4038UL)) +#define bFM3_ADC2_ADCR_SCIF *((volatile unsigned int*)(0x424E403CUL)) +#define bFM3_ADC2_SFNS_SFS0 *((volatile unsigned int*)(0x424E4100UL)) +#define bFM3_ADC2_SFNS_SFS1 *((volatile unsigned int*)(0x424E4104UL)) +#define bFM3_ADC2_SFNS_SFS2 *((volatile unsigned int*)(0x424E4108UL)) +#define bFM3_ADC2_SFNS_SFS3 *((volatile unsigned int*)(0x424E410CUL)) +#define bFM3_ADC2_SCCR_SSTR *((volatile unsigned int*)(0x424E4120UL)) +#define bFM3_ADC2_SCCR_SHEN *((volatile unsigned int*)(0x424E4124UL)) +#define bFM3_ADC2_SCCR_RPT *((volatile unsigned int*)(0x424E4128UL)) +#define bFM3_ADC2_SCCR_SFCLR *((volatile unsigned int*)(0x424E4130UL)) +#define bFM3_ADC2_SCCR_SOVR *((volatile unsigned int*)(0x424E4134UL)) +#define bFM3_ADC2_SCCR_SFUL *((volatile unsigned int*)(0x424E4138UL)) +#define bFM3_ADC2_SCCR_SEMP *((volatile unsigned int*)(0x424E413CUL)) +#define bFM3_ADC2_SCFD_SC0 *((volatile unsigned int*)(0x424E4180UL)) +#define bFM3_ADC2_SCFD_SC1 *((volatile unsigned int*)(0x424E4184UL)) +#define bFM3_ADC2_SCFD_SC2 *((volatile unsigned int*)(0x424E4188UL)) +#define bFM3_ADC2_SCFD_SC3 *((volatile unsigned int*)(0x424E418CUL)) +#define bFM3_ADC2_SCFD_SC4 *((volatile unsigned int*)(0x424E4190UL)) +#define bFM3_ADC2_SCFD_RS0 *((volatile unsigned int*)(0x424E41A0UL)) +#define bFM3_ADC2_SCFD_RS1 *((volatile unsigned int*)(0x424E41A4UL)) +#define bFM3_ADC2_SCFD_INVL *((volatile unsigned int*)(0x424E41B0UL)) +#define bFM3_ADC2_SCFD_SD0 *((volatile unsigned int*)(0x424E41D0UL)) +#define bFM3_ADC2_SCFD_SD1 *((volatile unsigned int*)(0x424E41D4UL)) +#define bFM3_ADC2_SCFD_SD2 *((volatile unsigned int*)(0x424E41D8UL)) +#define bFM3_ADC2_SCFD_SD3 *((volatile unsigned int*)(0x424E41DCUL)) +#define bFM3_ADC2_SCFD_SD4 *((volatile unsigned int*)(0x424E41E0UL)) +#define bFM3_ADC2_SCFD_SD5 *((volatile unsigned int*)(0x424E41E4UL)) +#define bFM3_ADC2_SCFD_SD6 *((volatile unsigned int*)(0x424E41E8UL)) +#define bFM3_ADC2_SCFD_SD7 *((volatile unsigned int*)(0x424E41ECUL)) +#define bFM3_ADC2_SCFD_SD8 *((volatile unsigned int*)(0x424E41F0UL)) +#define bFM3_ADC2_SCFD_SD9 *((volatile unsigned int*)(0x424E41F4UL)) +#define bFM3_ADC2_SCFD_SD10 *((volatile unsigned int*)(0x424E41F8UL)) +#define bFM3_ADC2_SCFD_SD11 *((volatile unsigned int*)(0x424E41FCUL)) +#define bFM3_ADC2_SCFDL_SC0 *((volatile unsigned int*)(0x424E4180UL)) +#define bFM3_ADC2_SCFDL_SC1 *((volatile unsigned int*)(0x424E4184UL)) +#define bFM3_ADC2_SCFDL_SC2 *((volatile unsigned int*)(0x424E4188UL)) +#define bFM3_ADC2_SCFDL_SC3 *((volatile unsigned int*)(0x424E418CUL)) +#define bFM3_ADC2_SCFDL_SC4 *((volatile unsigned int*)(0x424E4190UL)) +#define bFM3_ADC2_SCFDL_RS0 *((volatile unsigned int*)(0x424E41A0UL)) +#define bFM3_ADC2_SCFDL_RS1 *((volatile unsigned int*)(0x424E41A4UL)) +#define bFM3_ADC2_SCFDL_INVL *((volatile unsigned int*)(0x424E41B0UL)) +#define bFM3_ADC2_SCFDH_SD0 *((volatile unsigned int*)(0x424E41D0UL)) +#define bFM3_ADC2_SCFDH_SD1 *((volatile unsigned int*)(0x424E41D4UL)) +#define bFM3_ADC2_SCFDH_SD2 *((volatile unsigned int*)(0x424E41D8UL)) +#define bFM3_ADC2_SCFDH_SD3 *((volatile unsigned int*)(0x424E41DCUL)) +#define bFM3_ADC2_SCFDH_SD4 *((volatile unsigned int*)(0x424E41E0UL)) +#define bFM3_ADC2_SCFDH_SD5 *((volatile unsigned int*)(0x424E41E4UL)) +#define bFM3_ADC2_SCFDH_SD6 *((volatile unsigned int*)(0x424E41E8UL)) +#define bFM3_ADC2_SCFDH_SD7 *((volatile unsigned int*)(0x424E41ECUL)) +#define bFM3_ADC2_SCFDH_SD8 *((volatile unsigned int*)(0x424E41F0UL)) +#define bFM3_ADC2_SCFDH_SD9 *((volatile unsigned int*)(0x424E41F4UL)) +#define bFM3_ADC2_SCFDH_SD10 *((volatile unsigned int*)(0x424E41F8UL)) +#define bFM3_ADC2_SCFDH_SD11 *((volatile unsigned int*)(0x424E41FCUL)) +#define bFM3_ADC2_SCIS23_AN16 *((volatile unsigned int*)(0x424E4200UL)) +#define bFM3_ADC2_SCIS23_AN17 *((volatile unsigned int*)(0x424E4204UL)) +#define bFM3_ADC2_SCIS23_AN18 *((volatile unsigned int*)(0x424E4208UL)) +#define bFM3_ADC2_SCIS23_AN19 *((volatile unsigned int*)(0x424E420CUL)) +#define bFM3_ADC2_SCIS23_AN20 *((volatile unsigned int*)(0x424E4210UL)) +#define bFM3_ADC2_SCIS23_AN21 *((volatile unsigned int*)(0x424E4214UL)) +#define bFM3_ADC2_SCIS23_AN22 *((volatile unsigned int*)(0x424E4218UL)) +#define bFM3_ADC2_SCIS23_AN23 *((volatile unsigned int*)(0x424E421CUL)) +#define bFM3_ADC2_SCIS23_AN24 *((volatile unsigned int*)(0x424E4220UL)) +#define bFM3_ADC2_SCIS23_AN25 *((volatile unsigned int*)(0x424E4224UL)) +#define bFM3_ADC2_SCIS23_AN26 *((volatile unsigned int*)(0x424E4228UL)) +#define bFM3_ADC2_SCIS23_AN27 *((volatile unsigned int*)(0x424E422CUL)) +#define bFM3_ADC2_SCIS23_AN28 *((volatile unsigned int*)(0x424E4230UL)) +#define bFM3_ADC2_SCIS23_AN29 *((volatile unsigned int*)(0x424E4234UL)) +#define bFM3_ADC2_SCIS23_AN30 *((volatile unsigned int*)(0x424E4238UL)) +#define bFM3_ADC2_SCIS23_AN31 *((volatile unsigned int*)(0x424E423CUL)) +#define bFM3_ADC2_SCIS2_AN16 *((volatile unsigned int*)(0x424E4200UL)) +#define bFM3_ADC2_SCIS2_AN17 *((volatile unsigned int*)(0x424E4204UL)) +#define bFM3_ADC2_SCIS2_AN18 *((volatile unsigned int*)(0x424E4208UL)) +#define bFM3_ADC2_SCIS2_AN19 *((volatile unsigned int*)(0x424E420CUL)) +#define bFM3_ADC2_SCIS2_AN20 *((volatile unsigned int*)(0x424E4210UL)) +#define bFM3_ADC2_SCIS2_AN21 *((volatile unsigned int*)(0x424E4214UL)) +#define bFM3_ADC2_SCIS2_AN22 *((volatile unsigned int*)(0x424E4218UL)) +#define bFM3_ADC2_SCIS2_AN23 *((volatile unsigned int*)(0x424E421CUL)) +#define bFM3_ADC2_SCIS3_AN24 *((volatile unsigned int*)(0x424E4220UL)) +#define bFM3_ADC2_SCIS3_AN25 *((volatile unsigned int*)(0x424E4224UL)) +#define bFM3_ADC2_SCIS3_AN26 *((volatile unsigned int*)(0x424E4228UL)) +#define bFM3_ADC2_SCIS3_AN27 *((volatile unsigned int*)(0x424E422CUL)) +#define bFM3_ADC2_SCIS3_AN28 *((volatile unsigned int*)(0x424E4230UL)) +#define bFM3_ADC2_SCIS3_AN29 *((volatile unsigned int*)(0x424E4234UL)) +#define bFM3_ADC2_SCIS3_AN30 *((volatile unsigned int*)(0x424E4238UL)) +#define bFM3_ADC2_SCIS3_AN31 *((volatile unsigned int*)(0x424E423CUL)) +#define bFM3_ADC2_SCIS01_AN0 *((volatile unsigned int*)(0x424E4280UL)) +#define bFM3_ADC2_SCIS01_AN1 *((volatile unsigned int*)(0x424E4284UL)) +#define bFM3_ADC2_SCIS01_AN2 *((volatile unsigned int*)(0x424E4288UL)) +#define bFM3_ADC2_SCIS01_AN3 *((volatile unsigned int*)(0x424E428CUL)) +#define bFM3_ADC2_SCIS01_AN4 *((volatile unsigned int*)(0x424E4290UL)) +#define bFM3_ADC2_SCIS01_AN5 *((volatile unsigned int*)(0x424E4294UL)) +#define bFM3_ADC2_SCIS01_AN6 *((volatile unsigned int*)(0x424E4298UL)) +#define bFM3_ADC2_SCIS01_AN7 *((volatile unsigned int*)(0x424E429CUL)) +#define bFM3_ADC2_SCIS01_AN8 *((volatile unsigned int*)(0x424E42A0UL)) +#define bFM3_ADC2_SCIS01_AN9 *((volatile unsigned int*)(0x424E42A4UL)) +#define bFM3_ADC2_SCIS01_AN10 *((volatile unsigned int*)(0x424E42A8UL)) +#define bFM3_ADC2_SCIS01_AN11 *((volatile unsigned int*)(0x424E42ACUL)) +#define bFM3_ADC2_SCIS01_AN12 *((volatile unsigned int*)(0x424E42B0UL)) +#define bFM3_ADC2_SCIS01_AN13 *((volatile unsigned int*)(0x424E42B4UL)) +#define bFM3_ADC2_SCIS01_AN14 *((volatile unsigned int*)(0x424E42B8UL)) +#define bFM3_ADC2_SCIS01_AN15 *((volatile unsigned int*)(0x424E42BCUL)) +#define bFM3_ADC2_SCIS0_AN0 *((volatile unsigned int*)(0x424E4280UL)) +#define bFM3_ADC2_SCIS0_AN1 *((volatile unsigned int*)(0x424E4284UL)) +#define bFM3_ADC2_SCIS0_AN2 *((volatile unsigned int*)(0x424E4288UL)) +#define bFM3_ADC2_SCIS0_AN3 *((volatile unsigned int*)(0x424E428CUL)) +#define bFM3_ADC2_SCIS0_AN4 *((volatile unsigned int*)(0x424E4290UL)) +#define bFM3_ADC2_SCIS0_AN5 *((volatile unsigned int*)(0x424E4294UL)) +#define bFM3_ADC2_SCIS0_AN6 *((volatile unsigned int*)(0x424E4298UL)) +#define bFM3_ADC2_SCIS0_AN7 *((volatile unsigned int*)(0x424E429CUL)) +#define bFM3_ADC2_SCIS1_AN8 *((volatile unsigned int*)(0x424E42A0UL)) +#define bFM3_ADC2_SCIS1_AN9 *((volatile unsigned int*)(0x424E42A4UL)) +#define bFM3_ADC2_SCIS1_AN10 *((volatile unsigned int*)(0x424E42A8UL)) +#define bFM3_ADC2_SCIS1_AN11 *((volatile unsigned int*)(0x424E42ACUL)) +#define bFM3_ADC2_SCIS1_AN12 *((volatile unsigned int*)(0x424E42B0UL)) +#define bFM3_ADC2_SCIS1_AN13 *((volatile unsigned int*)(0x424E42B4UL)) +#define bFM3_ADC2_SCIS1_AN14 *((volatile unsigned int*)(0x424E42B8UL)) +#define bFM3_ADC2_SCIS1_AN15 *((volatile unsigned int*)(0x424E42BCUL)) +#define bFM3_ADC2_PFNS_PFS0 *((volatile unsigned int*)(0x424E4300UL)) +#define bFM3_ADC2_PFNS_PFS1 *((volatile unsigned int*)(0x424E4304UL)) +#define bFM3_ADC2_PFNS_TEST0 *((volatile unsigned int*)(0x424E4310UL)) +#define bFM3_ADC2_PFNS_TEST1 *((volatile unsigned int*)(0x424E4314UL)) +#define bFM3_ADC2_PCCR_PSTR *((volatile unsigned int*)(0x424E4320UL)) +#define bFM3_ADC2_PCCR_PHEN *((volatile unsigned int*)(0x424E4324UL)) +#define bFM3_ADC2_PCCR_PEEN *((volatile unsigned int*)(0x424E4328UL)) +#define bFM3_ADC2_PCCR_ESCE *((volatile unsigned int*)(0x424E432CUL)) +#define bFM3_ADC2_PCCR_PFCLR *((volatile unsigned int*)(0x424E4330UL)) +#define bFM3_ADC2_PCCR_POVR *((volatile unsigned int*)(0x424E4334UL)) +#define bFM3_ADC2_PCCR_PFUL *((volatile unsigned int*)(0x424E4338UL)) +#define bFM3_ADC2_PCCR_PEMP *((volatile unsigned int*)(0x424E433CUL)) +#define bFM3_ADC2_PCFD_PC0 *((volatile unsigned int*)(0x424E4380UL)) +#define bFM3_ADC2_PCFD_PC1 *((volatile unsigned int*)(0x424E4384UL)) +#define bFM3_ADC2_PCFD_PC2 *((volatile unsigned int*)(0x424E4388UL)) +#define bFM3_ADC2_PCFD_PC3 *((volatile unsigned int*)(0x424E438CUL)) +#define bFM3_ADC2_PCFD_PC4 *((volatile unsigned int*)(0x424E4390UL)) +#define bFM3_ADC2_PCFD_RS0 *((volatile unsigned int*)(0x424E43A0UL)) +#define bFM3_ADC2_PCFD_RS1 *((volatile unsigned int*)(0x424E43A4UL)) +#define bFM3_ADC2_PCFD_RS2 *((volatile unsigned int*)(0x424E43A8UL)) +#define bFM3_ADC2_PCFD_INVL *((volatile unsigned int*)(0x424E43B0UL)) +#define bFM3_ADC2_PCFD_PD0 *((volatile unsigned int*)(0x424E43D0UL)) +#define bFM3_ADC2_PCFD_PD1 *((volatile unsigned int*)(0x424E43D4UL)) +#define bFM3_ADC2_PCFD_PD2 *((volatile unsigned int*)(0x424E43D8UL)) +#define bFM3_ADC2_PCFD_PD3 *((volatile unsigned int*)(0x424E43DCUL)) +#define bFM3_ADC2_PCFD_PD4 *((volatile unsigned int*)(0x424E43E0UL)) +#define bFM3_ADC2_PCFD_PD5 *((volatile unsigned int*)(0x424E43E4UL)) +#define bFM3_ADC2_PCFD_PD6 *((volatile unsigned int*)(0x424E43E8UL)) +#define bFM3_ADC2_PCFD_PD7 *((volatile unsigned int*)(0x424E43ECUL)) +#define bFM3_ADC2_PCFD_PD8 *((volatile unsigned int*)(0x424E43F0UL)) +#define bFM3_ADC2_PCFD_PD9 *((volatile unsigned int*)(0x424E43F4UL)) +#define bFM3_ADC2_PCFD_PD10 *((volatile unsigned int*)(0x424E43F8UL)) +#define bFM3_ADC2_PCFD_PD11 *((volatile unsigned int*)(0x424E43FCUL)) +#define bFM3_ADC2_PCFDL_PC0 *((volatile unsigned int*)(0x424E4380UL)) +#define bFM3_ADC2_PCFDL_PC1 *((volatile unsigned int*)(0x424E4384UL)) +#define bFM3_ADC2_PCFDL_PC2 *((volatile unsigned int*)(0x424E4388UL)) +#define bFM3_ADC2_PCFDL_PC3 *((volatile unsigned int*)(0x424E438CUL)) +#define bFM3_ADC2_PCFDL_PC4 *((volatile unsigned int*)(0x424E4390UL)) +#define bFM3_ADC2_PCFDL_RS0 *((volatile unsigned int*)(0x424E43A0UL)) +#define bFM3_ADC2_PCFDL_RS1 *((volatile unsigned int*)(0x424E43A4UL)) +#define bFM3_ADC2_PCFDL_RS2 *((volatile unsigned int*)(0x424E43A8UL)) +#define bFM3_ADC2_PCFDL_INVL *((volatile unsigned int*)(0x424E43B0UL)) +#define bFM3_ADC2_PCFDH_PD0 *((volatile unsigned int*)(0x424E43D0UL)) +#define bFM3_ADC2_PCFDH_PD1 *((volatile unsigned int*)(0x424E43D4UL)) +#define bFM3_ADC2_PCFDH_PD2 *((volatile unsigned int*)(0x424E43D8UL)) +#define bFM3_ADC2_PCFDH_PD3 *((volatile unsigned int*)(0x424E43DCUL)) +#define bFM3_ADC2_PCFDH_PD4 *((volatile unsigned int*)(0x424E43E0UL)) +#define bFM3_ADC2_PCFDH_PD5 *((volatile unsigned int*)(0x424E43E4UL)) +#define bFM3_ADC2_PCFDH_PD6 *((volatile unsigned int*)(0x424E43E8UL)) +#define bFM3_ADC2_PCFDH_PD7 *((volatile unsigned int*)(0x424E43ECUL)) +#define bFM3_ADC2_PCFDH_PD8 *((volatile unsigned int*)(0x424E43F0UL)) +#define bFM3_ADC2_PCFDH_PD9 *((volatile unsigned int*)(0x424E43F4UL)) +#define bFM3_ADC2_PCFDH_PD10 *((volatile unsigned int*)(0x424E43F8UL)) +#define bFM3_ADC2_PCFDH_PD11 *((volatile unsigned int*)(0x424E43FCUL)) +#define bFM3_ADC2_PCIS_P1A0 *((volatile unsigned int*)(0x424E4400UL)) +#define bFM3_ADC2_PCIS_P1A1 *((volatile unsigned int*)(0x424E4404UL)) +#define bFM3_ADC2_PCIS_P1A2 *((volatile unsigned int*)(0x424E4408UL)) +#define bFM3_ADC2_PCIS_P2A0 *((volatile unsigned int*)(0x424E440CUL)) +#define bFM3_ADC2_PCIS_P2A1 *((volatile unsigned int*)(0x424E4410UL)) +#define bFM3_ADC2_PCIS_P2A2 *((volatile unsigned int*)(0x424E4414UL)) +#define bFM3_ADC2_PCIS_P2A3 *((volatile unsigned int*)(0x424E4418UL)) +#define bFM3_ADC2_PCIS_P2A4 *((volatile unsigned int*)(0x424E441CUL)) +#define bFM3_ADC2_CMPCR_CCH0 *((volatile unsigned int*)(0x424E4480UL)) +#define bFM3_ADC2_CMPCR_CCH1 *((volatile unsigned int*)(0x424E4484UL)) +#define bFM3_ADC2_CMPCR_CCH2 *((volatile unsigned int*)(0x424E4488UL)) +#define bFM3_ADC2_CMPCR_CCH3 *((volatile unsigned int*)(0x424E448CUL)) +#define bFM3_ADC2_CMPCR_CCH4 *((volatile unsigned int*)(0x424E4490UL)) +#define bFM3_ADC2_CMPCR_CMD0 *((volatile unsigned int*)(0x424E4494UL)) +#define bFM3_ADC2_CMPCR_CMD1 *((volatile unsigned int*)(0x424E4498UL)) +#define bFM3_ADC2_CMPCR_CMPEN *((volatile unsigned int*)(0x424E449CUL)) +#define bFM3_ADC2_CMPD_CMAD2 *((volatile unsigned int*)(0x424E44D8UL)) +#define bFM3_ADC2_CMPD_CMAD3 *((volatile unsigned int*)(0x424E44DCUL)) +#define bFM3_ADC2_CMPD_CMAD4 *((volatile unsigned int*)(0x424E44E0UL)) +#define bFM3_ADC2_CMPD_CMAD5 *((volatile unsigned int*)(0x424E44E4UL)) +#define bFM3_ADC2_CMPD_CMAD6 *((volatile unsigned int*)(0x424E44E8UL)) +#define bFM3_ADC2_CMPD_CMAD7 *((volatile unsigned int*)(0x424E44ECUL)) +#define bFM3_ADC2_CMPD_CMAD8 *((volatile unsigned int*)(0x424E44F0UL)) +#define bFM3_ADC2_CMPD_CMAD9 *((volatile unsigned int*)(0x424E44F4UL)) +#define bFM3_ADC2_CMPD_CMAD10 *((volatile unsigned int*)(0x424E44F8UL)) +#define bFM3_ADC2_CMPD_CMAD11 *((volatile unsigned int*)(0x424E44FCUL)) +#define bFM3_ADC2_ADSS23_TS16 *((volatile unsigned int*)(0x424E4500UL)) +#define bFM3_ADC2_ADSS23_TS17 *((volatile unsigned int*)(0x424E4504UL)) +#define bFM3_ADC2_ADSS23_TS18 *((volatile unsigned int*)(0x424E4508UL)) +#define bFM3_ADC2_ADSS23_TS19 *((volatile unsigned int*)(0x424E450CUL)) +#define bFM3_ADC2_ADSS23_TS20 *((volatile unsigned int*)(0x424E4510UL)) +#define bFM3_ADC2_ADSS23_TS21 *((volatile unsigned int*)(0x424E4514UL)) +#define bFM3_ADC2_ADSS23_TS22 *((volatile unsigned int*)(0x424E4518UL)) +#define bFM3_ADC2_ADSS23_TS23 *((volatile unsigned int*)(0x424E451CUL)) +#define bFM3_ADC2_ADSS23_TS24 *((volatile unsigned int*)(0x424E4520UL)) +#define bFM3_ADC2_ADSS23_TS25 *((volatile unsigned int*)(0x424E4524UL)) +#define bFM3_ADC2_ADSS23_TS26 *((volatile unsigned int*)(0x424E4528UL)) +#define bFM3_ADC2_ADSS23_TS27 *((volatile unsigned int*)(0x424E452CUL)) +#define bFM3_ADC2_ADSS23_TS28 *((volatile unsigned int*)(0x424E4530UL)) +#define bFM3_ADC2_ADSS23_TS29 *((volatile unsigned int*)(0x424E4534UL)) +#define bFM3_ADC2_ADSS23_TS30 *((volatile unsigned int*)(0x424E4538UL)) +#define bFM3_ADC2_ADSS23_TS31 *((volatile unsigned int*)(0x424E453CUL)) +#define bFM3_ADC2_ADSS2_TS16 *((volatile unsigned int*)(0x424E4500UL)) +#define bFM3_ADC2_ADSS2_TS17 *((volatile unsigned int*)(0x424E4504UL)) +#define bFM3_ADC2_ADSS2_TS18 *((volatile unsigned int*)(0x424E4508UL)) +#define bFM3_ADC2_ADSS2_TS19 *((volatile unsigned int*)(0x424E450CUL)) +#define bFM3_ADC2_ADSS2_TS20 *((volatile unsigned int*)(0x424E4510UL)) +#define bFM3_ADC2_ADSS2_TS21 *((volatile unsigned int*)(0x424E4514UL)) +#define bFM3_ADC2_ADSS2_TS22 *((volatile unsigned int*)(0x424E4518UL)) +#define bFM3_ADC2_ADSS2_TS23 *((volatile unsigned int*)(0x424E451CUL)) +#define bFM3_ADC2_ADSS3_TS24 *((volatile unsigned int*)(0x424E4520UL)) +#define bFM3_ADC2_ADSS3_TS25 *((volatile unsigned int*)(0x424E4524UL)) +#define bFM3_ADC2_ADSS3_TS26 *((volatile unsigned int*)(0x424E4528UL)) +#define bFM3_ADC2_ADSS3_TS27 *((volatile unsigned int*)(0x424E452CUL)) +#define bFM3_ADC2_ADSS3_TS28 *((volatile unsigned int*)(0x424E4530UL)) +#define bFM3_ADC2_ADSS3_TS29 *((volatile unsigned int*)(0x424E4534UL)) +#define bFM3_ADC2_ADSS3_TS30 *((volatile unsigned int*)(0x424E4538UL)) +#define bFM3_ADC2_ADSS3_TS31 *((volatile unsigned int*)(0x424E453CUL)) +#define bFM3_ADC2_ADSS01_TS0 *((volatile unsigned int*)(0x424E4580UL)) +#define bFM3_ADC2_ADSS01_TS1 *((volatile unsigned int*)(0x424E4584UL)) +#define bFM3_ADC2_ADSS01_TS2 *((volatile unsigned int*)(0x424E4588UL)) +#define bFM3_ADC2_ADSS01_TS3 *((volatile unsigned int*)(0x424E458CUL)) +#define bFM3_ADC2_ADSS01_TS4 *((volatile unsigned int*)(0x424E4590UL)) +#define bFM3_ADC2_ADSS01_TS5 *((volatile unsigned int*)(0x424E4594UL)) +#define bFM3_ADC2_ADSS01_TS6 *((volatile unsigned int*)(0x424E4598UL)) +#define bFM3_ADC2_ADSS01_TS7 *((volatile unsigned int*)(0x424E459CUL)) +#define bFM3_ADC2_ADSS01_TS8 *((volatile unsigned int*)(0x424E45A0UL)) +#define bFM3_ADC2_ADSS01_TS9 *((volatile unsigned int*)(0x424E45A4UL)) +#define bFM3_ADC2_ADSS01_TS10 *((volatile unsigned int*)(0x424E45A8UL)) +#define bFM3_ADC2_ADSS01_TS11 *((volatile unsigned int*)(0x424E45ACUL)) +#define bFM3_ADC2_ADSS01_TS12 *((volatile unsigned int*)(0x424E45B0UL)) +#define bFM3_ADC2_ADSS01_TS13 *((volatile unsigned int*)(0x424E45B4UL)) +#define bFM3_ADC2_ADSS01_TS14 *((volatile unsigned int*)(0x424E45B8UL)) +#define bFM3_ADC2_ADSS01_TS15 *((volatile unsigned int*)(0x424E45BCUL)) +#define bFM3_ADC2_ADSS0_TS0 *((volatile unsigned int*)(0x424E4580UL)) +#define bFM3_ADC2_ADSS0_TS1 *((volatile unsigned int*)(0x424E4584UL)) +#define bFM3_ADC2_ADSS0_TS2 *((volatile unsigned int*)(0x424E4588UL)) +#define bFM3_ADC2_ADSS0_TS3 *((volatile unsigned int*)(0x424E458CUL)) +#define bFM3_ADC2_ADSS0_TS4 *((volatile unsigned int*)(0x424E4590UL)) +#define bFM3_ADC2_ADSS0_TS5 *((volatile unsigned int*)(0x424E4594UL)) +#define bFM3_ADC2_ADSS0_TS6 *((volatile unsigned int*)(0x424E4598UL)) +#define bFM3_ADC2_ADSS0_TS7 *((volatile unsigned int*)(0x424E459CUL)) +#define bFM3_ADC2_ADSS1_TS8 *((volatile unsigned int*)(0x424E45A0UL)) +#define bFM3_ADC2_ADSS1_TS9 *((volatile unsigned int*)(0x424E45A4UL)) +#define bFM3_ADC2_ADSS1_TS10 *((volatile unsigned int*)(0x424E45A8UL)) +#define bFM3_ADC2_ADSS1_TS11 *((volatile unsigned int*)(0x424E45ACUL)) +#define bFM3_ADC2_ADSS1_TS12 *((volatile unsigned int*)(0x424E45B0UL)) +#define bFM3_ADC2_ADSS1_TS13 *((volatile unsigned int*)(0x424E45B4UL)) +#define bFM3_ADC2_ADSS1_TS14 *((volatile unsigned int*)(0x424E45B8UL)) +#define bFM3_ADC2_ADSS1_TS15 *((volatile unsigned int*)(0x424E45BCUL)) +#define bFM3_ADC2_ADST01_ST10 *((volatile unsigned int*)(0x424E4600UL)) +#define bFM3_ADC2_ADST01_ST11 *((volatile unsigned int*)(0x424E4604UL)) +#define bFM3_ADC2_ADST01_ST12 *((volatile unsigned int*)(0x424E4608UL)) +#define bFM3_ADC2_ADST01_ST13 *((volatile unsigned int*)(0x424E460CUL)) +#define bFM3_ADC2_ADST01_ST14 *((volatile unsigned int*)(0x424E4610UL)) +#define bFM3_ADC2_ADST01_STX10 *((volatile unsigned int*)(0x424E4614UL)) +#define bFM3_ADC2_ADST01_STX11 *((volatile unsigned int*)(0x424E4618UL)) +#define bFM3_ADC2_ADST01_STX12 *((volatile unsigned int*)(0x424E461CUL)) +#define bFM3_ADC2_ADST01_ST00 *((volatile unsigned int*)(0x424E4620UL)) +#define bFM3_ADC2_ADST01_ST01 *((volatile unsigned int*)(0x424E4624UL)) +#define bFM3_ADC2_ADST01_ST02 *((volatile unsigned int*)(0x424E4628UL)) +#define bFM3_ADC2_ADST01_ST03 *((volatile unsigned int*)(0x424E462CUL)) +#define bFM3_ADC2_ADST01_ST04 *((volatile unsigned int*)(0x424E4630UL)) +#define bFM3_ADC2_ADST01_STX00 *((volatile unsigned int*)(0x424E4634UL)) +#define bFM3_ADC2_ADST01_STX01 *((volatile unsigned int*)(0x424E4638UL)) +#define bFM3_ADC2_ADST01_STX02 *((volatile unsigned int*)(0x424E463CUL)) +#define bFM3_ADC2_ADST1_ST10 *((volatile unsigned int*)(0x424E4600UL)) +#define bFM3_ADC2_ADST1_ST11 *((volatile unsigned int*)(0x424E4604UL)) +#define bFM3_ADC2_ADST1_ST12 *((volatile unsigned int*)(0x424E4608UL)) +#define bFM3_ADC2_ADST1_ST13 *((volatile unsigned int*)(0x424E460CUL)) +#define bFM3_ADC2_ADST1_ST14 *((volatile unsigned int*)(0x424E4610UL)) +#define bFM3_ADC2_ADST1_STX10 *((volatile unsigned int*)(0x424E4614UL)) +#define bFM3_ADC2_ADST1_STX11 *((volatile unsigned int*)(0x424E4618UL)) +#define bFM3_ADC2_ADST1_STX12 *((volatile unsigned int*)(0x424E461CUL)) +#define bFM3_ADC2_ADST0_ST00 *((volatile unsigned int*)(0x424E4620UL)) +#define bFM3_ADC2_ADST0_ST01 *((volatile unsigned int*)(0x424E4624UL)) +#define bFM3_ADC2_ADST0_ST02 *((volatile unsigned int*)(0x424E4628UL)) +#define bFM3_ADC2_ADST0_ST03 *((volatile unsigned int*)(0x424E462CUL)) +#define bFM3_ADC2_ADST0_ST04 *((volatile unsigned int*)(0x424E4630UL)) +#define bFM3_ADC2_ADST0_STX00 *((volatile unsigned int*)(0x424E4634UL)) +#define bFM3_ADC2_ADST0_STX01 *((volatile unsigned int*)(0x424E4638UL)) +#define bFM3_ADC2_ADST0_STX02 *((volatile unsigned int*)(0x424E463CUL)) +#define bFM3_ADC2_ADCT_CT0 *((volatile unsigned int*)(0x424E4680UL)) +#define bFM3_ADC2_ADCT_CT1 *((volatile unsigned int*)(0x424E4684UL)) +#define bFM3_ADC2_ADCT_CT2 *((volatile unsigned int*)(0x424E4688UL)) +#define bFM3_ADC2_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E4700UL)) +#define bFM3_ADC2_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E4704UL)) +#define bFM3_ADC2_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E4708UL)) +#define bFM3_ADC2_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E470CUL)) +#define bFM3_ADC2_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E4720UL)) +#define bFM3_ADC2_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E4724UL)) +#define bFM3_ADC2_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E4728UL)) +#define bFM3_ADC2_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E472CUL)) +#define bFM3_ADC2_ADCEN_ENBL *((volatile unsigned int*)(0x424E4780UL)) +#define bFM3_ADC2_ADCEN_READY *((volatile unsigned int*)(0x424E4784UL)) + +/* CR trimming registers */ +#define bFM3_CRTRIM_MCR_PSR_CSR0 *((volatile unsigned int*)(0x425C0000UL)) +#define bFM3_CRTRIM_MCR_PSR_CSR1 *((volatile unsigned int*)(0x425C0004UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD0 *((volatile unsigned int*)(0x425C0080UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD1 *((volatile unsigned int*)(0x425C0084UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD2 *((volatile unsigned int*)(0x425C0088UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD3 *((volatile unsigned int*)(0x425C008CUL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD4 *((volatile unsigned int*)(0x425C0090UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD5 *((volatile unsigned int*)(0x425C0094UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD6 *((volatile unsigned int*)(0x425C0098UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD7 *((volatile unsigned int*)(0x425C009CUL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD8 *((volatile unsigned int*)(0x425C00A0UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD9 *((volatile unsigned int*)(0x425C00A4UL)) + +/* External interrupt registers */ +#define bFM3_EXTI_ENIR_EN0 *((volatile unsigned int*)(0x42600000UL)) +#define bFM3_EXTI_ENIR_EN1 *((volatile unsigned int*)(0x42600004UL)) +#define bFM3_EXTI_ENIR_EN2 *((volatile unsigned int*)(0x42600008UL)) +#define bFM3_EXTI_ENIR_EN3 *((volatile unsigned int*)(0x4260000CUL)) +#define bFM3_EXTI_ENIR_EN4 *((volatile unsigned int*)(0x42600010UL)) +#define bFM3_EXTI_ENIR_EN5 *((volatile unsigned int*)(0x42600014UL)) +#define bFM3_EXTI_ENIR_EN6 *((volatile unsigned int*)(0x42600018UL)) +#define bFM3_EXTI_ENIR_EN7 *((volatile unsigned int*)(0x4260001CUL)) +#define bFM3_EXTI_ENIR_EN8 *((volatile unsigned int*)(0x42600020UL)) +#define bFM3_EXTI_ENIR_EN9 *((volatile unsigned int*)(0x42600024UL)) +#define bFM3_EXTI_ENIR_EN10 *((volatile unsigned int*)(0x42600028UL)) +#define bFM3_EXTI_ENIR_EN11 *((volatile unsigned int*)(0x4260002CUL)) +#define bFM3_EXTI_ENIR_EN12 *((volatile unsigned int*)(0x42600030UL)) +#define bFM3_EXTI_ENIR_EN13 *((volatile unsigned int*)(0x42600034UL)) +#define bFM3_EXTI_ENIR_EN14 *((volatile unsigned int*)(0x42600038UL)) +#define bFM3_EXTI_ENIR_EN15 *((volatile unsigned int*)(0x4260003CUL)) +#define bFM3_EXTI_EIRR_ER0 *((volatile unsigned int*)(0x42600080UL)) +#define bFM3_EXTI_EIRR_ER1 *((volatile unsigned int*)(0x42600084UL)) +#define bFM3_EXTI_EIRR_ER2 *((volatile unsigned int*)(0x42600088UL)) +#define bFM3_EXTI_EIRR_ER3 *((volatile unsigned int*)(0x4260008CUL)) +#define bFM3_EXTI_EIRR_ER4 *((volatile unsigned int*)(0x42600090UL)) +#define bFM3_EXTI_EIRR_ER5 *((volatile unsigned int*)(0x42600094UL)) +#define bFM3_EXTI_EIRR_ER6 *((volatile unsigned int*)(0x42600098UL)) +#define bFM3_EXTI_EIRR_ER7 *((volatile unsigned int*)(0x4260009CUL)) +#define bFM3_EXTI_EIRR_ER8 *((volatile unsigned int*)(0x426000A0UL)) +#define bFM3_EXTI_EIRR_ER9 *((volatile unsigned int*)(0x426000A4UL)) +#define bFM3_EXTI_EIRR_ER10 *((volatile unsigned int*)(0x426000A8UL)) +#define bFM3_EXTI_EIRR_ER11 *((volatile unsigned int*)(0x426000ACUL)) +#define bFM3_EXTI_EIRR_ER12 *((volatile unsigned int*)(0x426000B0UL)) +#define bFM3_EXTI_EIRR_ER13 *((volatile unsigned int*)(0x426000B4UL)) +#define bFM3_EXTI_EIRR_ER14 *((volatile unsigned int*)(0x426000B8UL)) +#define bFM3_EXTI_EIRR_ER15 *((volatile unsigned int*)(0x426000BCUL)) +#define bFM3_EXTI_EICL_ECL0 *((volatile unsigned int*)(0x42600100UL)) +#define bFM3_EXTI_EICL_ECL1 *((volatile unsigned int*)(0x42600104UL)) +#define bFM3_EXTI_EICL_ECL2 *((volatile unsigned int*)(0x42600108UL)) +#define bFM3_EXTI_EICL_ECL3 *((volatile unsigned int*)(0x4260010CUL)) +#define bFM3_EXTI_EICL_ECL4 *((volatile unsigned int*)(0x42600110UL)) +#define bFM3_EXTI_EICL_ECL5 *((volatile unsigned int*)(0x42600114UL)) +#define bFM3_EXTI_EICL_ECL6 *((volatile unsigned int*)(0x42600118UL)) +#define bFM3_EXTI_EICL_ECL7 *((volatile unsigned int*)(0x4260011CUL)) +#define bFM3_EXTI_EICL_ECL8 *((volatile unsigned int*)(0x42600120UL)) +#define bFM3_EXTI_EICL_ECL9 *((volatile unsigned int*)(0x42600124UL)) +#define bFM3_EXTI_EICL_ECL10 *((volatile unsigned int*)(0x42600128UL)) +#define bFM3_EXTI_EICL_ECL11 *((volatile unsigned int*)(0x4260012CUL)) +#define bFM3_EXTI_EICL_ECL12 *((volatile unsigned int*)(0x42600130UL)) +#define bFM3_EXTI_EICL_ECL13 *((volatile unsigned int*)(0x42600134UL)) +#define bFM3_EXTI_EICL_ECL14 *((volatile unsigned int*)(0x42600138UL)) +#define bFM3_EXTI_EICL_ECL15 *((volatile unsigned int*)(0x4260013CUL)) +#define bFM3_EXTI_ELVR_LA0 *((volatile unsigned int*)(0x42600180UL)) +#define bFM3_EXTI_ELVR_LB0 *((volatile unsigned int*)(0x42600184UL)) +#define bFM3_EXTI_ELVR_LA1 *((volatile unsigned int*)(0x42600188UL)) +#define bFM3_EXTI_ELVR_LB1 *((volatile unsigned int*)(0x4260018CUL)) +#define bFM3_EXTI_ELVR_LA2 *((volatile unsigned int*)(0x42600190UL)) +#define bFM3_EXTI_ELVR_LB2 *((volatile unsigned int*)(0x42600194UL)) +#define bFM3_EXTI_ELVR_LA3 *((volatile unsigned int*)(0x42600198UL)) +#define bFM3_EXTI_ELVR_LB3 *((volatile unsigned int*)(0x4260019CUL)) +#define bFM3_EXTI_ELVR_LA4 *((volatile unsigned int*)(0x426001A0UL)) +#define bFM3_EXTI_ELVR_LB4 *((volatile unsigned int*)(0x426001A4UL)) +#define bFM3_EXTI_ELVR_LA5 *((volatile unsigned int*)(0x426001A8UL)) +#define bFM3_EXTI_ELVR_LB5 *((volatile unsigned int*)(0x426001ACUL)) +#define bFM3_EXTI_ELVR_LA6 *((volatile unsigned int*)(0x426001B0UL)) +#define bFM3_EXTI_ELVR_LB6 *((volatile unsigned int*)(0x426001B4UL)) +#define bFM3_EXTI_ELVR_LA7 *((volatile unsigned int*)(0x426001B8UL)) +#define bFM3_EXTI_ELVR_LB7 *((volatile unsigned int*)(0x426001BCUL)) +#define bFM3_EXTI_ELVR_LA8 *((volatile unsigned int*)(0x426001C0UL)) +#define bFM3_EXTI_ELVR_LB8 *((volatile unsigned int*)(0x426001C4UL)) +#define bFM3_EXTI_ELVR_LA9 *((volatile unsigned int*)(0x426001C8UL)) +#define bFM3_EXTI_ELVR_LB9 *((volatile unsigned int*)(0x426001CCUL)) +#define bFM3_EXTI_ELVR_LA10 *((volatile unsigned int*)(0x426001D0UL)) +#define bFM3_EXTI_ELVR_LB10 *((volatile unsigned int*)(0x426001D4UL)) +#define bFM3_EXTI_ELVR_LA11 *((volatile unsigned int*)(0x426001D8UL)) +#define bFM3_EXTI_ELVR_LB11 *((volatile unsigned int*)(0x426001DCUL)) +#define bFM3_EXTI_ELVR_LA12 *((volatile unsigned int*)(0x426001E0UL)) +#define bFM3_EXTI_ELVR_LB12 *((volatile unsigned int*)(0x426001E4UL)) +#define bFM3_EXTI_ELVR_LA13 *((volatile unsigned int*)(0x426001E8UL)) +#define bFM3_EXTI_ELVR_LB13 *((volatile unsigned int*)(0x426001ECUL)) +#define bFM3_EXTI_ELVR_LA14 *((volatile unsigned int*)(0x426001F0UL)) +#define bFM3_EXTI_ELVR_LB14 *((volatile unsigned int*)(0x426001F4UL)) +#define bFM3_EXTI_ELVR_LA15 *((volatile unsigned int*)(0x426001F8UL)) +#define bFM3_EXTI_ELVR_LB15 *((volatile unsigned int*)(0x426001FCUL)) +#define bFM3_EXTI_NMIRR_NR0 *((volatile unsigned int*)(0x42600280UL)) +#define bFM3_EXTI_NMICL_NCL0 *((volatile unsigned int*)(0x42600300UL)) + +/* Interrupt request read registers */ +#define bFM3_INTREQ_DRQSEL_DRQSEL0 *((volatile unsigned int*)(0x42620000UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL1 *((volatile unsigned int*)(0x42620004UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL2 *((volatile unsigned int*)(0x42620008UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL3 *((volatile unsigned int*)(0x4262000CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL4 *((volatile unsigned int*)(0x42620010UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL5 *((volatile unsigned int*)(0x42620014UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL6 *((volatile unsigned int*)(0x42620018UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL7 *((volatile unsigned int*)(0x4262001CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL8 *((volatile unsigned int*)(0x42620020UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL9 *((volatile unsigned int*)(0x42620024UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL10 *((volatile unsigned int*)(0x42620028UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL11 *((volatile unsigned int*)(0x4262002CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL12 *((volatile unsigned int*)(0x42620030UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL13 *((volatile unsigned int*)(0x42620034UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL14 *((volatile unsigned int*)(0x42620038UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL15 *((volatile unsigned int*)(0x4262003CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL16 *((volatile unsigned int*)(0x42620040UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL17 *((volatile unsigned int*)(0x42620044UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL18 *((volatile unsigned int*)(0x42620048UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL19 *((volatile unsigned int*)(0x4262004CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL20 *((volatile unsigned int*)(0x42620050UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL21 *((volatile unsigned int*)(0x42620054UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL22 *((volatile unsigned int*)(0x42620058UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL23 *((volatile unsigned int*)(0x4262005CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL24 *((volatile unsigned int*)(0x42620060UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL25 *((volatile unsigned int*)(0x42620064UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL26 *((volatile unsigned int*)(0x42620068UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL27 *((volatile unsigned int*)(0x4262006CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL28 *((volatile unsigned int*)(0x42620070UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL29 *((volatile unsigned int*)(0x42620074UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL30 *((volatile unsigned int*)(0x42620078UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL31 *((volatile unsigned int*)(0x4262007CUL)) +#define bFM3_INTREQ_EXC02MON_NMI *((volatile unsigned int*)(0x42620200UL)) +#define bFM3_INTREQ_EXC02MON_HWINT *((volatile unsigned int*)(0x42620204UL)) +#define bFM3_INTREQ_IRQ00MON_FCSINT *((volatile unsigned int*)(0x42620280UL)) +#define bFM3_INTREQ_IRQ01MON_SWWDTINT *((volatile unsigned int*)(0x42620300UL)) +#define bFM3_INTREQ_IRQ02MON_LVDINT *((volatile unsigned int*)(0x42620380UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT0 *((volatile unsigned int*)(0x42620400UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT1 *((volatile unsigned int*)(0x42620404UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT2 *((volatile unsigned int*)(0x42620408UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT3 *((volatile unsigned int*)(0x4262040CUL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT0 *((volatile unsigned int*)(0x42620410UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT1 *((volatile unsigned int*)(0x42620414UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT2 *((volatile unsigned int*)(0x42620418UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT3 *((volatile unsigned int*)(0x4262041CUL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT0 *((volatile unsigned int*)(0x42620480UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT1 *((volatile unsigned int*)(0x42620484UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT2 *((volatile unsigned int*)(0x42620488UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT3 *((volatile unsigned int*)(0x4262048CUL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT4 *((volatile unsigned int*)(0x42620490UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT5 *((volatile unsigned int*)(0x42620494UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT6 *((volatile unsigned int*)(0x42620498UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT7 *((volatile unsigned int*)(0x4262049CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT0 *((volatile unsigned int*)(0x42620500UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT1 *((volatile unsigned int*)(0x42620504UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT2 *((volatile unsigned int*)(0x42620508UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT3 *((volatile unsigned int*)(0x4262050CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT4 *((volatile unsigned int*)(0x42620510UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT5 *((volatile unsigned int*)(0x42620514UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT6 *((volatile unsigned int*)(0x42620518UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT7 *((volatile unsigned int*)(0x4262051CUL)) +#define bFM3_INTREQ_IRQ06MON_TIMINT0 *((volatile unsigned int*)(0x42620580UL)) +#define bFM3_INTREQ_IRQ06MON_TIMINT1 *((volatile unsigned int*)(0x42620584UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT0 *((volatile unsigned int*)(0x42620588UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT1 *((volatile unsigned int*)(0x4262058CUL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT2 *((volatile unsigned int*)(0x42620590UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT3 *((volatile unsigned int*)(0x42620594UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT4 *((volatile unsigned int*)(0x42620598UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT5 *((volatile unsigned int*)(0x4262059CUL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT0 *((volatile unsigned int*)(0x426205A0UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT1 *((volatile unsigned int*)(0x426205A4UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT2 *((volatile unsigned int*)(0x426205A8UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT3 *((volatile unsigned int*)(0x426205ACUL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT4 *((volatile unsigned int*)(0x426205B0UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT5 *((volatile unsigned int*)(0x426205B4UL)) +#define bFM3_INTREQ_IRQ07MON_FMSINT *((volatile unsigned int*)(0x42620600UL)) +#define bFM3_INTREQ_IRQ08MON_MFSINT0 *((volatile unsigned int*)(0x42620680UL)) +#define bFM3_INTREQ_IRQ08MON_MFSINT1 *((volatile unsigned int*)(0x42620684UL)) +#define bFM3_INTREQ_IRQ09MON_FMSINT *((volatile unsigned int*)(0x42620700UL)) +#define bFM3_INTREQ_IRQ10MON_MFSINT0 *((volatile unsigned int*)(0x42620780UL)) +#define bFM3_INTREQ_IRQ10MON_MFSINT1 *((volatile unsigned int*)(0x42620784UL)) +#define bFM3_INTREQ_IRQ11MON_FMSINT *((volatile unsigned int*)(0x42620800UL)) +#define bFM3_INTREQ_IRQ12MON_MFSINT0 *((volatile unsigned int*)(0x42620880UL)) +#define bFM3_INTREQ_IRQ12MON_MFSINT1 *((volatile unsigned int*)(0x42620884UL)) +#define bFM3_INTREQ_IRQ13MON_FMSINT *((volatile unsigned int*)(0x42620900UL)) +#define bFM3_INTREQ_IRQ14MON_MFSINT0 *((volatile unsigned int*)(0x42620980UL)) +#define bFM3_INTREQ_IRQ14MON_MFSINT1 *((volatile unsigned int*)(0x42620984UL)) +#define bFM3_INTREQ_IRQ15MON_FMSINT *((volatile unsigned int*)(0x42620A00UL)) +#define bFM3_INTREQ_IRQ16MON_MFSINT0 *((volatile unsigned int*)(0x42620A80UL)) +#define bFM3_INTREQ_IRQ16MON_MFSINT1 *((volatile unsigned int*)(0x42620A84UL)) +#define bFM3_INTREQ_IRQ17MON_FMSINT *((volatile unsigned int*)(0x42620B00UL)) +#define bFM3_INTREQ_IRQ18MON_MFSINT0 *((volatile unsigned int*)(0x42620B80UL)) +#define bFM3_INTREQ_IRQ18MON_MFSINT1 *((volatile unsigned int*)(0x42620B84UL)) +#define bFM3_INTREQ_IRQ19MON_FMSINT *((volatile unsigned int*)(0x42620C00UL)) +#define bFM3_INTREQ_IRQ20MON_MFSINT0 *((volatile unsigned int*)(0x42620C80UL)) +#define bFM3_INTREQ_IRQ20MON_MFSINT1 *((volatile unsigned int*)(0x42620C84UL)) +#define bFM3_INTREQ_IRQ21MON_FMSINT *((volatile unsigned int*)(0x42620D00UL)) +#define bFM3_INTREQ_IRQ22MON_MFSINT0 *((volatile unsigned int*)(0x42620D80UL)) +#define bFM3_INTREQ_IRQ22MON_MFSINT1 *((volatile unsigned int*)(0x42620D84UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT0 *((volatile unsigned int*)(0x42620E00UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT1 *((volatile unsigned int*)(0x42620E04UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT2 *((volatile unsigned int*)(0x42620E08UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT3 *((volatile unsigned int*)(0x42620E0CUL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT4 *((volatile unsigned int*)(0x42620E10UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT5 *((volatile unsigned int*)(0x42620E14UL)) +#define bFM3_INTREQ_IRQ24MON_MOSCINT *((volatile unsigned int*)(0x42620E80UL)) +#define bFM3_INTREQ_IRQ24MON_SOSCINT *((volatile unsigned int*)(0x42620E84UL)) +#define bFM3_INTREQ_IRQ24MON_MPLLINT *((volatile unsigned int*)(0x42620E88UL)) +#define bFM3_INTREQ_IRQ24MON_UPLLINT *((volatile unsigned int*)(0x42620E8CUL)) +#define bFM3_INTREQ_IRQ24MON_WCINT *((volatile unsigned int*)(0x42620E90UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT0 *((volatile unsigned int*)(0x42620F00UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT1 *((volatile unsigned int*)(0x42620F04UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT2 *((volatile unsigned int*)(0x42620F08UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT3 *((volatile unsigned int*)(0x42620F0CUL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT0 *((volatile unsigned int*)(0x42620F80UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT1 *((volatile unsigned int*)(0x42620F84UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT2 *((volatile unsigned int*)(0x42620F88UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT3 *((volatile unsigned int*)(0x42620F8CUL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT0 *((volatile unsigned int*)(0x42621000UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT1 *((volatile unsigned int*)(0x42621004UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT2 *((volatile unsigned int*)(0x42621008UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT3 *((volatile unsigned int*)(0x4262100CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT0 *((volatile unsigned int*)(0x42621080UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT1 *((volatile unsigned int*)(0x42621084UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT2 *((volatile unsigned int*)(0x42621088UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT3 *((volatile unsigned int*)(0x4262108CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT4 *((volatile unsigned int*)(0x42621090UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT5 *((volatile unsigned int*)(0x42621094UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT0 *((volatile unsigned int*)(0x42621098UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT1 *((volatile unsigned int*)(0x4262109CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT2 *((volatile unsigned int*)(0x426210A0UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT3 *((volatile unsigned int*)(0x426210A4UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT4 *((volatile unsigned int*)(0x426210A8UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT5 *((volatile unsigned int*)(0x426210ACUL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT0 *((volatile unsigned int*)(0x42621100UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT1 *((volatile unsigned int*)(0x42621104UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT2 *((volatile unsigned int*)(0x42621108UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT3 *((volatile unsigned int*)(0x4262110CUL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT0 *((volatile unsigned int*)(0x42621110UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT1 *((volatile unsigned int*)(0x42621114UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT2 *((volatile unsigned int*)(0x42621118UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT3 *((volatile unsigned int*)(0x4262111CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT0 *((volatile unsigned int*)(0x42621180UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT1 *((volatile unsigned int*)(0x42621184UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT2 *((volatile unsigned int*)(0x42621188UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT3 *((volatile unsigned int*)(0x4262118CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT4 *((volatile unsigned int*)(0x42621190UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT5 *((volatile unsigned int*)(0x42621194UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT0 *((volatile unsigned int*)(0x42621198UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT1 *((volatile unsigned int*)(0x4262119CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT2 *((volatile unsigned int*)(0x426211A0UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT3 *((volatile unsigned int*)(0x426211A4UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT4 *((volatile unsigned int*)(0x426211A8UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT5 *((volatile unsigned int*)(0x426211ACUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT0 *((volatile unsigned int*)(0x42621200UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT1 *((volatile unsigned int*)(0x42621204UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT2 *((volatile unsigned int*)(0x42621208UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT3 *((volatile unsigned int*)(0x4262120CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT4 *((volatile unsigned int*)(0x42621210UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT5 *((volatile unsigned int*)(0x42621214UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT6 *((volatile unsigned int*)(0x42621218UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT7 *((volatile unsigned int*)(0x4262121CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT8 *((volatile unsigned int*)(0x42621220UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT9 *((volatile unsigned int*)(0x42621224UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT10 *((volatile unsigned int*)(0x42621228UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT11 *((volatile unsigned int*)(0x4262122CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT12 *((volatile unsigned int*)(0x42621230UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT13 *((volatile unsigned int*)(0x42621234UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT14 *((volatile unsigned int*)(0x42621238UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT15 *((volatile unsigned int*)(0x4262123CUL)) +#define bFM3_INTREQ_IRQ32MON_CANINT *((volatile unsigned int*)(0x42621280UL)) +#define bFM3_INTREQ_IRQ33MON_CANINT *((volatile unsigned int*)(0x42621300UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT0 *((volatile unsigned int*)(0x42621380UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT1 *((volatile unsigned int*)(0x42621384UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT2 *((volatile unsigned int*)(0x42621388UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT3 *((volatile unsigned int*)(0x4262138CUL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT4 *((volatile unsigned int*)(0x42621390UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT0 *((volatile unsigned int*)(0x42621400UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT1 *((volatile unsigned int*)(0x42621404UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT2 *((volatile unsigned int*)(0x42621408UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT3 *((volatile unsigned int*)(0x4262140CUL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT4 *((volatile unsigned int*)(0x42621410UL)) +#define bFM3_INTREQ_IRQ38MON_DMAINT *((volatile unsigned int*)(0x42621580UL)) +#define bFM3_INTREQ_IRQ39MON_DMAINT *((volatile unsigned int*)(0x42621600UL)) +#define bFM3_INTREQ_IRQ40MON_DMAINT *((volatile unsigned int*)(0x42621680UL)) +#define bFM3_INTREQ_IRQ41MON_DMAINT *((volatile unsigned int*)(0x42621700UL)) +#define bFM3_INTREQ_IRQ42MON_DMAINT *((volatile unsigned int*)(0x42621780UL)) +#define bFM3_INTREQ_IRQ43MON_DMAINT *((volatile unsigned int*)(0x42621800UL)) +#define bFM3_INTREQ_IRQ44MON_DMAINT *((volatile unsigned int*)(0x42621880UL)) +#define bFM3_INTREQ_IRQ45MON_DMAINT *((volatile unsigned int*)(0x42621900UL)) + +/* General purpose I/O registers */ +#define bFM3_GPIO_PFR0_P0 *((volatile unsigned int*)(0x42660000UL)) +#define bFM3_GPIO_PFR0_P1 *((volatile unsigned int*)(0x42660004UL)) +#define bFM3_GPIO_PFR0_P2 *((volatile unsigned int*)(0x42660008UL)) +#define bFM3_GPIO_PFR0_P3 *((volatile unsigned int*)(0x4266000CUL)) +#define bFM3_GPIO_PFR0_P4 *((volatile unsigned int*)(0x42660010UL)) +#define bFM3_GPIO_PFR0_P5 *((volatile unsigned int*)(0x42660014UL)) +#define bFM3_GPIO_PFR0_P6 *((volatile unsigned int*)(0x42660018UL)) +#define bFM3_GPIO_PFR0_P7 *((volatile unsigned int*)(0x4266001CUL)) +#define bFM3_GPIO_PFR0_P8 *((volatile unsigned int*)(0x42660020UL)) +#define bFM3_GPIO_PFR0_P9 *((volatile unsigned int*)(0x42660024UL)) +#define bFM3_GPIO_PFR0_PA *((volatile unsigned int*)(0x42660028UL)) +#define bFM3_GPIO_PFR0_PB *((volatile unsigned int*)(0x4266002CUL)) +#define bFM3_GPIO_PFR0_PC *((volatile unsigned int*)(0x42660030UL)) +#define bFM3_GPIO_PFR0_PD *((volatile unsigned int*)(0x42660034UL)) +#define bFM3_GPIO_PFR0_PE *((volatile unsigned int*)(0x42660038UL)) +#define bFM3_GPIO_PFR0_PF *((volatile unsigned int*)(0x4266003CUL)) +#define bFM3_GPIO_PFR1_P0 *((volatile unsigned int*)(0x42660080UL)) +#define bFM3_GPIO_PFR1_P1 *((volatile unsigned int*)(0x42660084UL)) +#define bFM3_GPIO_PFR1_P2 *((volatile unsigned int*)(0x42660088UL)) +#define bFM3_GPIO_PFR1_P3 *((volatile unsigned int*)(0x4266008CUL)) +#define bFM3_GPIO_PFR1_P4 *((volatile unsigned int*)(0x42660090UL)) +#define bFM3_GPIO_PFR1_P5 *((volatile unsigned int*)(0x42660094UL)) +#define bFM3_GPIO_PFR1_P6 *((volatile unsigned int*)(0x42660098UL)) +#define bFM3_GPIO_PFR1_P7 *((volatile unsigned int*)(0x4266009CUL)) +#define bFM3_GPIO_PFR1_P8 *((volatile unsigned int*)(0x426600A0UL)) +#define bFM3_GPIO_PFR1_P9 *((volatile unsigned int*)(0x426600A4UL)) +#define bFM3_GPIO_PFR1_PA *((volatile unsigned int*)(0x426600A8UL)) +#define bFM3_GPIO_PFR1_PB *((volatile unsigned int*)(0x426600ACUL)) +#define bFM3_GPIO_PFR1_PC *((volatile unsigned int*)(0x426600B0UL)) +#define bFM3_GPIO_PFR1_PD *((volatile unsigned int*)(0x426600B4UL)) +#define bFM3_GPIO_PFR1_PE *((volatile unsigned int*)(0x426600B8UL)) +#define bFM3_GPIO_PFR1_PF *((volatile unsigned int*)(0x426600BCUL)) +#define bFM3_GPIO_PFR2_P0 *((volatile unsigned int*)(0x42660100UL)) +#define bFM3_GPIO_PFR2_P1 *((volatile unsigned int*)(0x42660104UL)) +#define bFM3_GPIO_PFR2_P2 *((volatile unsigned int*)(0x42660108UL)) +#define bFM3_GPIO_PFR2_P3 *((volatile unsigned int*)(0x4266010CUL)) +#define bFM3_GPIO_PFR2_P4 *((volatile unsigned int*)(0x42660110UL)) +#define bFM3_GPIO_PFR2_P5 *((volatile unsigned int*)(0x42660114UL)) +#define bFM3_GPIO_PFR2_P6 *((volatile unsigned int*)(0x42660118UL)) +#define bFM3_GPIO_PFR2_P7 *((volatile unsigned int*)(0x4266011CUL)) +#define bFM3_GPIO_PFR2_P8 *((volatile unsigned int*)(0x42660120UL)) +#define bFM3_GPIO_PFR3_P0 *((volatile unsigned int*)(0x42660180UL)) +#define bFM3_GPIO_PFR3_P1 *((volatile unsigned int*)(0x42660184UL)) +#define bFM3_GPIO_PFR3_P2 *((volatile unsigned int*)(0x42660188UL)) +#define bFM3_GPIO_PFR3_P3 *((volatile unsigned int*)(0x4266018CUL)) +#define bFM3_GPIO_PFR3_P4 *((volatile unsigned int*)(0x42660190UL)) +#define bFM3_GPIO_PFR3_P5 *((volatile unsigned int*)(0x42660194UL)) +#define bFM3_GPIO_PFR3_P6 *((volatile unsigned int*)(0x42660198UL)) +#define bFM3_GPIO_PFR3_P7 *((volatile unsigned int*)(0x4266019CUL)) +#define bFM3_GPIO_PFR3_P8 *((volatile unsigned int*)(0x426601A0UL)) +#define bFM3_GPIO_PFR3_P9 *((volatile unsigned int*)(0x426601A4UL)) +#define bFM3_GPIO_PFR3_PA *((volatile unsigned int*)(0x426601A8UL)) +#define bFM3_GPIO_PFR3_PB *((volatile unsigned int*)(0x426601ACUL)) +#define bFM3_GPIO_PFR3_PC *((volatile unsigned int*)(0x426601B0UL)) +#define bFM3_GPIO_PFR3_PD *((volatile unsigned int*)(0x426601B4UL)) +#define bFM3_GPIO_PFR3_PE *((volatile unsigned int*)(0x426601B8UL)) +#define bFM3_GPIO_PFR3_PF *((volatile unsigned int*)(0x426601BCUL)) +#define bFM3_GPIO_PFR4_P0 *((volatile unsigned int*)(0x42660200UL)) +#define bFM3_GPIO_PFR4_P1 *((volatile unsigned int*)(0x42660204UL)) +#define bFM3_GPIO_PFR4_P2 *((volatile unsigned int*)(0x42660208UL)) +#define bFM3_GPIO_PFR4_P3 *((volatile unsigned int*)(0x4266020CUL)) +#define bFM3_GPIO_PFR4_P4 *((volatile unsigned int*)(0x42660210UL)) +#define bFM3_GPIO_PFR4_P5 *((volatile unsigned int*)(0x42660214UL)) +#define bFM3_GPIO_PFR4_P6 *((volatile unsigned int*)(0x42660218UL)) +#define bFM3_GPIO_PFR4_P7 *((volatile unsigned int*)(0x4266021CUL)) +#define bFM3_GPIO_PFR4_P8 *((volatile unsigned int*)(0x42660220UL)) +#define bFM3_GPIO_PFR4_P9 *((volatile unsigned int*)(0x42660224UL)) +#define bFM3_GPIO_PFR4_PA *((volatile unsigned int*)(0x42660228UL)) +#define bFM3_GPIO_PFR4_PB *((volatile unsigned int*)(0x4266022CUL)) +#define bFM3_GPIO_PFR4_PC *((volatile unsigned int*)(0x42660230UL)) +#define bFM3_GPIO_PFR4_PD *((volatile unsigned int*)(0x42660234UL)) +#define bFM3_GPIO_PFR4_PE *((volatile unsigned int*)(0x42660238UL)) +#define bFM3_GPIO_PFR5_P0 *((volatile unsigned int*)(0x42660280UL)) +#define bFM3_GPIO_PFR5_P1 *((volatile unsigned int*)(0x42660284UL)) +#define bFM3_GPIO_PFR5_P2 *((volatile unsigned int*)(0x42660288UL)) +#define bFM3_GPIO_PFR5_P3 *((volatile unsigned int*)(0x4266028CUL)) +#define bFM3_GPIO_PFR5_P4 *((volatile unsigned int*)(0x42660290UL)) +#define bFM3_GPIO_PFR5_P5 *((volatile unsigned int*)(0x42660294UL)) +#define bFM3_GPIO_PFR5_P6 *((volatile unsigned int*)(0x42660298UL)) +#define bFM3_GPIO_PFR5_P7 *((volatile unsigned int*)(0x4266029CUL)) +#define bFM3_GPIO_PFR5_P8 *((volatile unsigned int*)(0x426602A0UL)) +#define bFM3_GPIO_PFR5_P9 *((volatile unsigned int*)(0x426602A4UL)) +#define bFM3_GPIO_PFR5_PA *((volatile unsigned int*)(0x426602A8UL)) +#define bFM3_GPIO_PFR5_PB *((volatile unsigned int*)(0x426602ACUL)) +#define bFM3_GPIO_PFR6_P0 *((volatile unsigned int*)(0x42660300UL)) +#define bFM3_GPIO_PFR6_P1 *((volatile unsigned int*)(0x42660304UL)) +#define bFM3_GPIO_PFR6_P2 *((volatile unsigned int*)(0x42660308UL)) +#define bFM3_GPIO_PFR6_P3 *((volatile unsigned int*)(0x4266030CUL)) +#define bFM3_GPIO_PFR6_P4 *((volatile unsigned int*)(0x42660310UL)) +#define bFM3_GPIO_PFR6_P5 *((volatile unsigned int*)(0x42660314UL)) +#define bFM3_GPIO_PFR6_P6 *((volatile unsigned int*)(0x42660318UL)) +#define bFM3_GPIO_PFR6_P7 *((volatile unsigned int*)(0x4266031CUL)) +#define bFM3_GPIO_PFR6_P8 *((volatile unsigned int*)(0x42660320UL)) +#define bFM3_GPIO_PFR7_P0 *((volatile unsigned int*)(0x42660380UL)) +#define bFM3_GPIO_PFR7_P1 *((volatile unsigned int*)(0x42660384UL)) +#define bFM3_GPIO_PFR7_P2 *((volatile unsigned int*)(0x42660388UL)) +#define bFM3_GPIO_PFR7_P3 *((volatile unsigned int*)(0x4266038CUL)) +#define bFM3_GPIO_PFR7_P4 *((volatile unsigned int*)(0x42660390UL)) +#define bFM3_GPIO_PFR8_P0 *((volatile unsigned int*)(0x42660400UL)) +#define bFM3_GPIO_PFR8_P1 *((volatile unsigned int*)(0x42660404UL)) +#define bFM3_GPIO_PCR0_P0 *((volatile unsigned int*)(0x42662000UL)) +#define bFM3_GPIO_PCR0_P1 *((volatile unsigned int*)(0x42662004UL)) +#define bFM3_GPIO_PCR0_P2 *((volatile unsigned int*)(0x42662008UL)) +#define bFM3_GPIO_PCR0_P3 *((volatile unsigned int*)(0x4266200CUL)) +#define bFM3_GPIO_PCR0_P4 *((volatile unsigned int*)(0x42662010UL)) +#define bFM3_GPIO_PCR0_P5 *((volatile unsigned int*)(0x42662014UL)) +#define bFM3_GPIO_PCR0_P6 *((volatile unsigned int*)(0x42662018UL)) +#define bFM3_GPIO_PCR0_P7 *((volatile unsigned int*)(0x4266201CUL)) +#define bFM3_GPIO_PCR0_P8 *((volatile unsigned int*)(0x42662020UL)) +#define bFM3_GPIO_PCR0_P9 *((volatile unsigned int*)(0x42662024UL)) +#define bFM3_GPIO_PCR0_PA *((volatile unsigned int*)(0x42662028UL)) +#define bFM3_GPIO_PCR0_PB *((volatile unsigned int*)(0x4266202CUL)) +#define bFM3_GPIO_PCR0_PC *((volatile unsigned int*)(0x42662030UL)) +#define bFM3_GPIO_PCR0_PD *((volatile unsigned int*)(0x42662034UL)) +#define bFM3_GPIO_PCR0_PE *((volatile unsigned int*)(0x42662038UL)) +#define bFM3_GPIO_PCR0_PF *((volatile unsigned int*)(0x4266203CUL)) +#define bFM3_GPIO_PCR1_P0 *((volatile unsigned int*)(0x42662080UL)) +#define bFM3_GPIO_PCR1_P1 *((volatile unsigned int*)(0x42662084UL)) +#define bFM3_GPIO_PCR1_P2 *((volatile unsigned int*)(0x42662088UL)) +#define bFM3_GPIO_PCR1_P3 *((volatile unsigned int*)(0x4266208CUL)) +#define bFM3_GPIO_PCR1_P4 *((volatile unsigned int*)(0x42662090UL)) +#define bFM3_GPIO_PCR1_P5 *((volatile unsigned int*)(0x42662094UL)) +#define bFM3_GPIO_PCR1_P6 *((volatile unsigned int*)(0x42662098UL)) +#define bFM3_GPIO_PCR1_P7 *((volatile unsigned int*)(0x4266209CUL)) +#define bFM3_GPIO_PCR1_P8 *((volatile unsigned int*)(0x426620A0UL)) +#define bFM3_GPIO_PCR1_P9 *((volatile unsigned int*)(0x426620A4UL)) +#define bFM3_GPIO_PCR1_PA *((volatile unsigned int*)(0x426620A8UL)) +#define bFM3_GPIO_PCR1_PB *((volatile unsigned int*)(0x426620ACUL)) +#define bFM3_GPIO_PCR1_PC *((volatile unsigned int*)(0x426620B0UL)) +#define bFM3_GPIO_PCR1_PD *((volatile unsigned int*)(0x426620B4UL)) +#define bFM3_GPIO_PCR1_PE *((volatile unsigned int*)(0x426620B8UL)) +#define bFM3_GPIO_PCR1_PF *((volatile unsigned int*)(0x426620BCUL)) +#define bFM3_GPIO_PCR2_P0 *((volatile unsigned int*)(0x42662100UL)) +#define bFM3_GPIO_PCR2_P1 *((volatile unsigned int*)(0x42662104UL)) +#define bFM3_GPIO_PCR2_P2 *((volatile unsigned int*)(0x42662108UL)) +#define bFM3_GPIO_PCR2_P3 *((volatile unsigned int*)(0x4266210CUL)) +#define bFM3_GPIO_PCR2_P4 *((volatile unsigned int*)(0x42662110UL)) +#define bFM3_GPIO_PCR2_P5 *((volatile unsigned int*)(0x42662114UL)) +#define bFM3_GPIO_PCR2_P6 *((volatile unsigned int*)(0x42662118UL)) +#define bFM3_GPIO_PCR2_P7 *((volatile unsigned int*)(0x4266211CUL)) +#define bFM3_GPIO_PCR2_P8 *((volatile unsigned int*)(0x42662120UL)) +#define bFM3_GPIO_PCR3_P0 *((volatile unsigned int*)(0x42662180UL)) +#define bFM3_GPIO_PCR3_P1 *((volatile unsigned int*)(0x42662184UL)) +#define bFM3_GPIO_PCR3_P2 *((volatile unsigned int*)(0x42662188UL)) +#define bFM3_GPIO_PCR3_P3 *((volatile unsigned int*)(0x4266218CUL)) +#define bFM3_GPIO_PCR3_P4 *((volatile unsigned int*)(0x42662190UL)) +#define bFM3_GPIO_PCR3_P5 *((volatile unsigned int*)(0x42662194UL)) +#define bFM3_GPIO_PCR3_P6 *((volatile unsigned int*)(0x42662198UL)) +#define bFM3_GPIO_PCR3_P7 *((volatile unsigned int*)(0x4266219CUL)) +#define bFM3_GPIO_PCR3_P8 *((volatile unsigned int*)(0x426621A0UL)) +#define bFM3_GPIO_PCR3_P9 *((volatile unsigned int*)(0x426621A4UL)) +#define bFM3_GPIO_PCR3_PA *((volatile unsigned int*)(0x426621A8UL)) +#define bFM3_GPIO_PCR3_PB *((volatile unsigned int*)(0x426621ACUL)) +#define bFM3_GPIO_PCR3_PC *((volatile unsigned int*)(0x426621B0UL)) +#define bFM3_GPIO_PCR3_PD *((volatile unsigned int*)(0x426621B4UL)) +#define bFM3_GPIO_PCR3_PE *((volatile unsigned int*)(0x426621B8UL)) +#define bFM3_GPIO_PCR3_PF *((volatile unsigned int*)(0x426621BCUL)) +#define bFM3_GPIO_PCR4_P0 *((volatile unsigned int*)(0x42662200UL)) +#define bFM3_GPIO_PCR4_P1 *((volatile unsigned int*)(0x42662204UL)) +#define bFM3_GPIO_PCR4_P2 *((volatile unsigned int*)(0x42662208UL)) +#define bFM3_GPIO_PCR4_P3 *((volatile unsigned int*)(0x4266220CUL)) +#define bFM3_GPIO_PCR4_P4 *((volatile unsigned int*)(0x42662210UL)) +#define bFM3_GPIO_PCR4_P5 *((volatile unsigned int*)(0x42662214UL)) +#define bFM3_GPIO_PCR4_P6 *((volatile unsigned int*)(0x42662218UL)) +#define bFM3_GPIO_PCR4_P7 *((volatile unsigned int*)(0x4266221CUL)) +#define bFM3_GPIO_PCR4_P8 *((volatile unsigned int*)(0x42662220UL)) +#define bFM3_GPIO_PCR4_P9 *((volatile unsigned int*)(0x42662224UL)) +#define bFM3_GPIO_PCR4_PA *((volatile unsigned int*)(0x42662228UL)) +#define bFM3_GPIO_PCR4_PB *((volatile unsigned int*)(0x4266222CUL)) +#define bFM3_GPIO_PCR4_PC *((volatile unsigned int*)(0x42662230UL)) +#define bFM3_GPIO_PCR4_PD *((volatile unsigned int*)(0x42662234UL)) +#define bFM3_GPIO_PCR4_PE *((volatile unsigned int*)(0x42662238UL)) +#define bFM3_GPIO_PCR5_P0 *((volatile unsigned int*)(0x42662280UL)) +#define bFM3_GPIO_PCR5_P1 *((volatile unsigned int*)(0x42662284UL)) +#define bFM3_GPIO_PCR5_P2 *((volatile unsigned int*)(0x42662288UL)) +#define bFM3_GPIO_PCR5_P3 *((volatile unsigned int*)(0x4266228CUL)) +#define bFM3_GPIO_PCR5_P4 *((volatile unsigned int*)(0x42662290UL)) +#define bFM3_GPIO_PCR5_P5 *((volatile unsigned int*)(0x42662294UL)) +#define bFM3_GPIO_PCR5_P6 *((volatile unsigned int*)(0x42662298UL)) +#define bFM3_GPIO_PCR5_P7 *((volatile unsigned int*)(0x4266229CUL)) +#define bFM3_GPIO_PCR5_P8 *((volatile unsigned int*)(0x426622A0UL)) +#define bFM3_GPIO_PCR5_P9 *((volatile unsigned int*)(0x426622A4UL)) +#define bFM3_GPIO_PCR5_PA *((volatile unsigned int*)(0x426622A8UL)) +#define bFM3_GPIO_PCR5_PB *((volatile unsigned int*)(0x426622ACUL)) +#define bFM3_GPIO_PCR6_P0 *((volatile unsigned int*)(0x42662300UL)) +#define bFM3_GPIO_PCR6_P1 *((volatile unsigned int*)(0x42662304UL)) +#define bFM3_GPIO_PCR6_P2 *((volatile unsigned int*)(0x42662308UL)) +#define bFM3_GPIO_PCR6_P3 *((volatile unsigned int*)(0x4266230CUL)) +#define bFM3_GPIO_PCR6_P4 *((volatile unsigned int*)(0x42662310UL)) +#define bFM3_GPIO_PCR6_P5 *((volatile unsigned int*)(0x42662314UL)) +#define bFM3_GPIO_PCR6_P6 *((volatile unsigned int*)(0x42662318UL)) +#define bFM3_GPIO_PCR6_P7 *((volatile unsigned int*)(0x4266231CUL)) +#define bFM3_GPIO_PCR6_P8 *((volatile unsigned int*)(0x42662320UL)) +#define bFM3_GPIO_PCR7_P0 *((volatile unsigned int*)(0x42662380UL)) +#define bFM3_GPIO_PCR7_P1 *((volatile unsigned int*)(0x42662384UL)) +#define bFM3_GPIO_PCR7_P2 *((volatile unsigned int*)(0x42662388UL)) +#define bFM3_GPIO_PCR7_P3 *((volatile unsigned int*)(0x4266238CUL)) +#define bFM3_GPIO_PCR7_P4 *((volatile unsigned int*)(0x42662390UL)) +#define bFM3_GPIO_DDR0_P0 *((volatile unsigned int*)(0x42664000UL)) +#define bFM3_GPIO_DDR0_P1 *((volatile unsigned int*)(0x42664004UL)) +#define bFM3_GPIO_DDR0_P2 *((volatile unsigned int*)(0x42664008UL)) +#define bFM3_GPIO_DDR0_P3 *((volatile unsigned int*)(0x4266400CUL)) +#define bFM3_GPIO_DDR0_P4 *((volatile unsigned int*)(0x42664010UL)) +#define bFM3_GPIO_DDR0_P5 *((volatile unsigned int*)(0x42664014UL)) +#define bFM3_GPIO_DDR0_P6 *((volatile unsigned int*)(0x42664018UL)) +#define bFM3_GPIO_DDR0_P7 *((volatile unsigned int*)(0x4266401CUL)) +#define bFM3_GPIO_DDR0_P8 *((volatile unsigned int*)(0x42664020UL)) +#define bFM3_GPIO_DDR0_P9 *((volatile unsigned int*)(0x42664024UL)) +#define bFM3_GPIO_DDR0_PA *((volatile unsigned int*)(0x42664028UL)) +#define bFM3_GPIO_DDR0_PB *((volatile unsigned int*)(0x4266402CUL)) +#define bFM3_GPIO_DDR0_PC *((volatile unsigned int*)(0x42664030UL)) +#define bFM3_GPIO_DDR0_PD *((volatile unsigned int*)(0x42664034UL)) +#define bFM3_GPIO_DDR0_PE *((volatile unsigned int*)(0x42664038UL)) +#define bFM3_GPIO_DDR0_PF *((volatile unsigned int*)(0x4266403CUL)) +#define bFM3_GPIO_DDR1_P0 *((volatile unsigned int*)(0x42664080UL)) +#define bFM3_GPIO_DDR1_P1 *((volatile unsigned int*)(0x42664084UL)) +#define bFM3_GPIO_DDR1_P2 *((volatile unsigned int*)(0x42664088UL)) +#define bFM3_GPIO_DDR1_P3 *((volatile unsigned int*)(0x4266408CUL)) +#define bFM3_GPIO_DDR1_P4 *((volatile unsigned int*)(0x42664090UL)) +#define bFM3_GPIO_DDR1_P5 *((volatile unsigned int*)(0x42664094UL)) +#define bFM3_GPIO_DDR1_P6 *((volatile unsigned int*)(0x42664098UL)) +#define bFM3_GPIO_DDR1_P7 *((volatile unsigned int*)(0x4266409CUL)) +#define bFM3_GPIO_DDR1_P8 *((volatile unsigned int*)(0x426640A0UL)) +#define bFM3_GPIO_DDR1_P9 *((volatile unsigned int*)(0x426640A4UL)) +#define bFM3_GPIO_DDR1_PA *((volatile unsigned int*)(0x426640A8UL)) +#define bFM3_GPIO_DDR1_PB *((volatile unsigned int*)(0x426640ACUL)) +#define bFM3_GPIO_DDR1_PC *((volatile unsigned int*)(0x426640B0UL)) +#define bFM3_GPIO_DDR1_PD *((volatile unsigned int*)(0x426640B4UL)) +#define bFM3_GPIO_DDR1_PE *((volatile unsigned int*)(0x426640B8UL)) +#define bFM3_GPIO_DDR1_PF *((volatile unsigned int*)(0x426640BCUL)) +#define bFM3_GPIO_DDR2_P0 *((volatile unsigned int*)(0x42664100UL)) +#define bFM3_GPIO_DDR2_P1 *((volatile unsigned int*)(0x42664104UL)) +#define bFM3_GPIO_DDR2_P2 *((volatile unsigned int*)(0x42664108UL)) +#define bFM3_GPIO_DDR2_P3 *((volatile unsigned int*)(0x4266410CUL)) +#define bFM3_GPIO_DDR2_P4 *((volatile unsigned int*)(0x42664110UL)) +#define bFM3_GPIO_DDR2_P5 *((volatile unsigned int*)(0x42664114UL)) +#define bFM3_GPIO_DDR2_P6 *((volatile unsigned int*)(0x42664118UL)) +#define bFM3_GPIO_DDR2_P7 *((volatile unsigned int*)(0x4266411CUL)) +#define bFM3_GPIO_DDR2_P8 *((volatile unsigned int*)(0x42664120UL)) +#define bFM3_GPIO_DDR3_P0 *((volatile unsigned int*)(0x42664180UL)) +#define bFM3_GPIO_DDR3_P1 *((volatile unsigned int*)(0x42664184UL)) +#define bFM3_GPIO_DDR3_P2 *((volatile unsigned int*)(0x42664188UL)) +#define bFM3_GPIO_DDR3_P3 *((volatile unsigned int*)(0x4266418CUL)) +#define bFM3_GPIO_DDR3_P4 *((volatile unsigned int*)(0x42664190UL)) +#define bFM3_GPIO_DDR3_P5 *((volatile unsigned int*)(0x42664194UL)) +#define bFM3_GPIO_DDR3_P6 *((volatile unsigned int*)(0x42664198UL)) +#define bFM3_GPIO_DDR3_P7 *((volatile unsigned int*)(0x4266419CUL)) +#define bFM3_GPIO_DDR3_P8 *((volatile unsigned int*)(0x426641A0UL)) +#define bFM3_GPIO_DDR3_P9 *((volatile unsigned int*)(0x426641A4UL)) +#define bFM3_GPIO_DDR3_PA *((volatile unsigned int*)(0x426641A8UL)) +#define bFM3_GPIO_DDR3_PB *((volatile unsigned int*)(0x426641ACUL)) +#define bFM3_GPIO_DDR3_PC *((volatile unsigned int*)(0x426641B0UL)) +#define bFM3_GPIO_DDR3_PD *((volatile unsigned int*)(0x426641B4UL)) +#define bFM3_GPIO_DDR3_PE *((volatile unsigned int*)(0x426641B8UL)) +#define bFM3_GPIO_DDR3_PF *((volatile unsigned int*)(0x426641BCUL)) +#define bFM3_GPIO_DDR4_P0 *((volatile unsigned int*)(0x42664200UL)) +#define bFM3_GPIO_DDR4_P1 *((volatile unsigned int*)(0x42664204UL)) +#define bFM3_GPIO_DDR4_P2 *((volatile unsigned int*)(0x42664208UL)) +#define bFM3_GPIO_DDR4_P3 *((volatile unsigned int*)(0x4266420CUL)) +#define bFM3_GPIO_DDR4_P4 *((volatile unsigned int*)(0x42664210UL)) +#define bFM3_GPIO_DDR4_P5 *((volatile unsigned int*)(0x42664214UL)) +#define bFM3_GPIO_DDR4_P6 *((volatile unsigned int*)(0x42664218UL)) +#define bFM3_GPIO_DDR4_P7 *((volatile unsigned int*)(0x4266421CUL)) +#define bFM3_GPIO_DDR4_P8 *((volatile unsigned int*)(0x42664220UL)) +#define bFM3_GPIO_DDR4_P9 *((volatile unsigned int*)(0x42664224UL)) +#define bFM3_GPIO_DDR4_PA *((volatile unsigned int*)(0x42664228UL)) +#define bFM3_GPIO_DDR4_PB *((volatile unsigned int*)(0x4266422CUL)) +#define bFM3_GPIO_DDR4_PC *((volatile unsigned int*)(0x42664230UL)) +#define bFM3_GPIO_DDR4_PD *((volatile unsigned int*)(0x42664234UL)) +#define bFM3_GPIO_DDR4_PE *((volatile unsigned int*)(0x42664238UL)) +#define bFM3_GPIO_DDR5_P0 *((volatile unsigned int*)(0x42664280UL)) +#define bFM3_GPIO_DDR5_P1 *((volatile unsigned int*)(0x42664284UL)) +#define bFM3_GPIO_DDR5_P2 *((volatile unsigned int*)(0x42664288UL)) +#define bFM3_GPIO_DDR5_P3 *((volatile unsigned int*)(0x4266428CUL)) +#define bFM3_GPIO_DDR5_P4 *((volatile unsigned int*)(0x42664290UL)) +#define bFM3_GPIO_DDR5_P5 *((volatile unsigned int*)(0x42664294UL)) +#define bFM3_GPIO_DDR5_P6 *((volatile unsigned int*)(0x42664298UL)) +#define bFM3_GPIO_DDR5_P7 *((volatile unsigned int*)(0x4266429CUL)) +#define bFM3_GPIO_DDR5_P8 *((volatile unsigned int*)(0x426642A0UL)) +#define bFM3_GPIO_DDR5_P9 *((volatile unsigned int*)(0x426642A4UL)) +#define bFM3_GPIO_DDR5_PA *((volatile unsigned int*)(0x426642A8UL)) +#define bFM3_GPIO_DDR5_PB *((volatile unsigned int*)(0x426642ACUL)) +#define bFM3_GPIO_DDR6_P0 *((volatile unsigned int*)(0x42664300UL)) +#define bFM3_GPIO_DDR6_P1 *((volatile unsigned int*)(0x42664304UL)) +#define bFM3_GPIO_DDR6_P2 *((volatile unsigned int*)(0x42664308UL)) +#define bFM3_GPIO_DDR6_P3 *((volatile unsigned int*)(0x4266430CUL)) +#define bFM3_GPIO_DDR6_P4 *((volatile unsigned int*)(0x42664310UL)) +#define bFM3_GPIO_DDR6_P5 *((volatile unsigned int*)(0x42664314UL)) +#define bFM3_GPIO_DDR6_P6 *((volatile unsigned int*)(0x42664318UL)) +#define bFM3_GPIO_DDR6_P7 *((volatile unsigned int*)(0x4266431CUL)) +#define bFM3_GPIO_DDR6_P8 *((volatile unsigned int*)(0x42664320UL)) +#define bFM3_GPIO_DDR7_P0 *((volatile unsigned int*)(0x42664380UL)) +#define bFM3_GPIO_DDR7_P1 *((volatile unsigned int*)(0x42664384UL)) +#define bFM3_GPIO_DDR7_P2 *((volatile unsigned int*)(0x42664388UL)) +#define bFM3_GPIO_DDR7_P3 *((volatile unsigned int*)(0x4266438CUL)) +#define bFM3_GPIO_DDR7_P4 *((volatile unsigned int*)(0x42664390UL)) +#define bFM3_GPIO_DDR8_P0 *((volatile unsigned int*)(0x42664400UL)) +#define bFM3_GPIO_DDR8_P1 *((volatile unsigned int*)(0x42664404UL)) +#define bFM3_GPIO_PDIR0_P0 *((volatile unsigned int*)(0x42666000UL)) +#define bFM3_GPIO_PDIR0_P1 *((volatile unsigned int*)(0x42666004UL)) +#define bFM3_GPIO_PDIR0_P2 *((volatile unsigned int*)(0x42666008UL)) +#define bFM3_GPIO_PDIR0_P3 *((volatile unsigned int*)(0x4266600CUL)) +#define bFM3_GPIO_PDIR0_P4 *((volatile unsigned int*)(0x42666010UL)) +#define bFM3_GPIO_PDIR0_P5 *((volatile unsigned int*)(0x42666014UL)) +#define bFM3_GPIO_PDIR0_P6 *((volatile unsigned int*)(0x42666018UL)) +#define bFM3_GPIO_PDIR0_P7 *((volatile unsigned int*)(0x4266601CUL)) +#define bFM3_GPIO_PDIR0_P8 *((volatile unsigned int*)(0x42666020UL)) +#define bFM3_GPIO_PDIR0_P9 *((volatile unsigned int*)(0x42666024UL)) +#define bFM3_GPIO_PDIR0_PA *((volatile unsigned int*)(0x42666028UL)) +#define bFM3_GPIO_PDIR0_PB *((volatile unsigned int*)(0x4266602CUL)) +#define bFM3_GPIO_PDIR0_PC *((volatile unsigned int*)(0x42666030UL)) +#define bFM3_GPIO_PDIR0_PD *((volatile unsigned int*)(0x42666034UL)) +#define bFM3_GPIO_PDIR0_PE *((volatile unsigned int*)(0x42666038UL)) +#define bFM3_GPIO_PDIR0_PF *((volatile unsigned int*)(0x4266603CUL)) +#define bFM3_GPIO_PDIR1_P0 *((volatile unsigned int*)(0x42666080UL)) +#define bFM3_GPIO_PDIR1_P1 *((volatile unsigned int*)(0x42666084UL)) +#define bFM3_GPIO_PDIR1_P2 *((volatile unsigned int*)(0x42666088UL)) +#define bFM3_GPIO_PDIR1_P3 *((volatile unsigned int*)(0x4266608CUL)) +#define bFM3_GPIO_PDIR1_P4 *((volatile unsigned int*)(0x42666090UL)) +#define bFM3_GPIO_PDIR1_P5 *((volatile unsigned int*)(0x42666094UL)) +#define bFM3_GPIO_PDIR1_P6 *((volatile unsigned int*)(0x42666098UL)) +#define bFM3_GPIO_PDIR1_P7 *((volatile unsigned int*)(0x4266609CUL)) +#define bFM3_GPIO_PDIR1_P8 *((volatile unsigned int*)(0x426660A0UL)) +#define bFM3_GPIO_PDIR1_P9 *((volatile unsigned int*)(0x426660A4UL)) +#define bFM3_GPIO_PDIR1_PA *((volatile unsigned int*)(0x426660A8UL)) +#define bFM3_GPIO_PDIR1_PB *((volatile unsigned int*)(0x426660ACUL)) +#define bFM3_GPIO_PDIR1_PC *((volatile unsigned int*)(0x426660B0UL)) +#define bFM3_GPIO_PDIR1_PD *((volatile unsigned int*)(0x426660B4UL)) +#define bFM3_GPIO_PDIR1_PE *((volatile unsigned int*)(0x426660B8UL)) +#define bFM3_GPIO_PDIR1_PF *((volatile unsigned int*)(0x426660BCUL)) +#define bFM3_GPIO_PDIR2_P0 *((volatile unsigned int*)(0x42666100UL)) +#define bFM3_GPIO_PDIR2_P1 *((volatile unsigned int*)(0x42666104UL)) +#define bFM3_GPIO_PDIR2_P2 *((volatile unsigned int*)(0x42666108UL)) +#define bFM3_GPIO_PDIR2_P3 *((volatile unsigned int*)(0x4266610CUL)) +#define bFM3_GPIO_PDIR2_P4 *((volatile unsigned int*)(0x42666110UL)) +#define bFM3_GPIO_PDIR2_P5 *((volatile unsigned int*)(0x42666114UL)) +#define bFM3_GPIO_PDIR2_P6 *((volatile unsigned int*)(0x42666118UL)) +#define bFM3_GPIO_PDIR2_P7 *((volatile unsigned int*)(0x4266611CUL)) +#define bFM3_GPIO_PDIR2_P8 *((volatile unsigned int*)(0x42666120UL)) +#define bFM3_GPIO_PDIR3_P0 *((volatile unsigned int*)(0x42666180UL)) +#define bFM3_GPIO_PDIR3_P1 *((volatile unsigned int*)(0x42666184UL)) +#define bFM3_GPIO_PDIR3_P2 *((volatile unsigned int*)(0x42666188UL)) +#define bFM3_GPIO_PDIR3_P3 *((volatile unsigned int*)(0x4266618CUL)) +#define bFM3_GPIO_PDIR3_P4 *((volatile unsigned int*)(0x42666190UL)) +#define bFM3_GPIO_PDIR3_P5 *((volatile unsigned int*)(0x42666194UL)) +#define bFM3_GPIO_PDIR3_P6 *((volatile unsigned int*)(0x42666198UL)) +#define bFM3_GPIO_PDIR3_P7 *((volatile unsigned int*)(0x4266619CUL)) +#define bFM3_GPIO_PDIR3_P8 *((volatile unsigned int*)(0x426661A0UL)) +#define bFM3_GPIO_PDIR3_P9 *((volatile unsigned int*)(0x426661A4UL)) +#define bFM3_GPIO_PDIR3_PA *((volatile unsigned int*)(0x426661A8UL)) +#define bFM3_GPIO_PDIR3_PB *((volatile unsigned int*)(0x426661ACUL)) +#define bFM3_GPIO_PDIR3_PC *((volatile unsigned int*)(0x426661B0UL)) +#define bFM3_GPIO_PDIR3_PD *((volatile unsigned int*)(0x426661B4UL)) +#define bFM3_GPIO_PDIR3_PE *((volatile unsigned int*)(0x426661B8UL)) +#define bFM3_GPIO_PDIR3_PF *((volatile unsigned int*)(0x426661BCUL)) +#define bFM3_GPIO_PDIR4_P0 *((volatile unsigned int*)(0x42666200UL)) +#define bFM3_GPIO_PDIR4_P1 *((volatile unsigned int*)(0x42666204UL)) +#define bFM3_GPIO_PDIR4_P2 *((volatile unsigned int*)(0x42666208UL)) +#define bFM3_GPIO_PDIR4_P3 *((volatile unsigned int*)(0x4266620CUL)) +#define bFM3_GPIO_PDIR4_P4 *((volatile unsigned int*)(0x42666210UL)) +#define bFM3_GPIO_PDIR4_P5 *((volatile unsigned int*)(0x42666214UL)) +#define bFM3_GPIO_PDIR4_P6 *((volatile unsigned int*)(0x42666218UL)) +#define bFM3_GPIO_PDIR4_P7 *((volatile unsigned int*)(0x4266621CUL)) +#define bFM3_GPIO_PDIR4_P8 *((volatile unsigned int*)(0x42666220UL)) +#define bFM3_GPIO_PDIR4_P9 *((volatile unsigned int*)(0x42666224UL)) +#define bFM3_GPIO_PDIR4_PA *((volatile unsigned int*)(0x42666228UL)) +#define bFM3_GPIO_PDIR4_PB *((volatile unsigned int*)(0x4266622CUL)) +#define bFM3_GPIO_PDIR4_PC *((volatile unsigned int*)(0x42666230UL)) +#define bFM3_GPIO_PDIR4_PD *((volatile unsigned int*)(0x42666234UL)) +#define bFM3_GPIO_PDIR4_PE *((volatile unsigned int*)(0x42666238UL)) +#define bFM3_GPIO_PDIR5_P0 *((volatile unsigned int*)(0x42666280UL)) +#define bFM3_GPIO_PDIR5_P1 *((volatile unsigned int*)(0x42666284UL)) +#define bFM3_GPIO_PDIR5_P2 *((volatile unsigned int*)(0x42666288UL)) +#define bFM3_GPIO_PDIR5_P3 *((volatile unsigned int*)(0x4266628CUL)) +#define bFM3_GPIO_PDIR5_P4 *((volatile unsigned int*)(0x42666290UL)) +#define bFM3_GPIO_PDIR5_P5 *((volatile unsigned int*)(0x42666294UL)) +#define bFM3_GPIO_PDIR5_P6 *((volatile unsigned int*)(0x42666298UL)) +#define bFM3_GPIO_PDIR5_P7 *((volatile unsigned int*)(0x4266629CUL)) +#define bFM3_GPIO_PDIR5_P8 *((volatile unsigned int*)(0x426662A0UL)) +#define bFM3_GPIO_PDIR5_P9 *((volatile unsigned int*)(0x426662A4UL)) +#define bFM3_GPIO_PDIR5_PA *((volatile unsigned int*)(0x426662A8UL)) +#define bFM3_GPIO_PDIR5_PB *((volatile unsigned int*)(0x426662ACUL)) +#define bFM3_GPIO_PDIR6_P0 *((volatile unsigned int*)(0x42666300UL)) +#define bFM3_GPIO_PDIR6_P1 *((volatile unsigned int*)(0x42666304UL)) +#define bFM3_GPIO_PDIR6_P2 *((volatile unsigned int*)(0x42666308UL)) +#define bFM3_GPIO_PDIR6_P3 *((volatile unsigned int*)(0x4266630CUL)) +#define bFM3_GPIO_PDIR6_P4 *((volatile unsigned int*)(0x42666310UL)) +#define bFM3_GPIO_PDIR6_P5 *((volatile unsigned int*)(0x42666314UL)) +#define bFM3_GPIO_PDIR6_P6 *((volatile unsigned int*)(0x42666318UL)) +#define bFM3_GPIO_PDIR6_P7 *((volatile unsigned int*)(0x4266631CUL)) +#define bFM3_GPIO_PDIR6_P8 *((volatile unsigned int*)(0x42666320UL)) +#define bFM3_GPIO_PDIR7_P0 *((volatile unsigned int*)(0x42666380UL)) +#define bFM3_GPIO_PDIR7_P1 *((volatile unsigned int*)(0x42666384UL)) +#define bFM3_GPIO_PDIR7_P2 *((volatile unsigned int*)(0x42666388UL)) +#define bFM3_GPIO_PDIR7_P3 *((volatile unsigned int*)(0x4266638CUL)) +#define bFM3_GPIO_PDIR7_P4 *((volatile unsigned int*)(0x42666390UL)) +#define bFM3_GPIO_PDIR8_P0 *((volatile unsigned int*)(0x42666400UL)) +#define bFM3_GPIO_PDIR8_P1 *((volatile unsigned int*)(0x42666404UL)) +#define bFM3_GPIO_PDOR0_P0 *((volatile unsigned int*)(0x42668000UL)) +#define bFM3_GPIO_PDOR0_P1 *((volatile unsigned int*)(0x42668004UL)) +#define bFM3_GPIO_PDOR0_P2 *((volatile unsigned int*)(0x42668008UL)) +#define bFM3_GPIO_PDOR0_P3 *((volatile unsigned int*)(0x4266800CUL)) +#define bFM3_GPIO_PDOR0_P4 *((volatile unsigned int*)(0x42668010UL)) +#define bFM3_GPIO_PDOR0_P5 *((volatile unsigned int*)(0x42668014UL)) +#define bFM3_GPIO_PDOR0_P6 *((volatile unsigned int*)(0x42668018UL)) +#define bFM3_GPIO_PDOR0_P7 *((volatile unsigned int*)(0x4266801CUL)) +#define bFM3_GPIO_PDOR0_P8 *((volatile unsigned int*)(0x42668020UL)) +#define bFM3_GPIO_PDOR0_P9 *((volatile unsigned int*)(0x42668024UL)) +#define bFM3_GPIO_PDOR0_PA *((volatile unsigned int*)(0x42668028UL)) +#define bFM3_GPIO_PDOR0_PB *((volatile unsigned int*)(0x4266802CUL)) +#define bFM3_GPIO_PDOR0_PC *((volatile unsigned int*)(0x42668030UL)) +#define bFM3_GPIO_PDOR0_PD *((volatile unsigned int*)(0x42668034UL)) +#define bFM3_GPIO_PDOR0_PE *((volatile unsigned int*)(0x42668038UL)) +#define bFM3_GPIO_PDOR0_PF *((volatile unsigned int*)(0x4266803CUL)) +#define bFM3_GPIO_PDOR1_P0 *((volatile unsigned int*)(0x42668080UL)) +#define bFM3_GPIO_PDOR1_P1 *((volatile unsigned int*)(0x42668084UL)) +#define bFM3_GPIO_PDOR1_P2 *((volatile unsigned int*)(0x42668088UL)) +#define bFM3_GPIO_PDOR1_P3 *((volatile unsigned int*)(0x4266808CUL)) +#define bFM3_GPIO_PDOR1_P4 *((volatile unsigned int*)(0x42668090UL)) +#define bFM3_GPIO_PDOR1_P5 *((volatile unsigned int*)(0x42668094UL)) +#define bFM3_GPIO_PDOR1_P6 *((volatile unsigned int*)(0x42668098UL)) +#define bFM3_GPIO_PDOR1_P7 *((volatile unsigned int*)(0x4266809CUL)) +#define bFM3_GPIO_PDOR1_P8 *((volatile unsigned int*)(0x426680A0UL)) +#define bFM3_GPIO_PDOR1_P9 *((volatile unsigned int*)(0x426680A4UL)) +#define bFM3_GPIO_PDOR1_PA *((volatile unsigned int*)(0x426680A8UL)) +#define bFM3_GPIO_PDOR1_PB *((volatile unsigned int*)(0x426680ACUL)) +#define bFM3_GPIO_PDOR1_PC *((volatile unsigned int*)(0x426680B0UL)) +#define bFM3_GPIO_PDOR1_PD *((volatile unsigned int*)(0x426680B4UL)) +#define bFM3_GPIO_PDOR1_PE *((volatile unsigned int*)(0x426680B8UL)) +#define bFM3_GPIO_PDOR1_PF *((volatile unsigned int*)(0x426680BCUL)) +#define bFM3_GPIO_PDOR2_P0 *((volatile unsigned int*)(0x42668100UL)) +#define bFM3_GPIO_PDOR2_P1 *((volatile unsigned int*)(0x42668104UL)) +#define bFM3_GPIO_PDOR2_P2 *((volatile unsigned int*)(0x42668108UL)) +#define bFM3_GPIO_PDOR2_P3 *((volatile unsigned int*)(0x4266810CUL)) +#define bFM3_GPIO_PDOR2_P4 *((volatile unsigned int*)(0x42668110UL)) +#define bFM3_GPIO_PDOR2_P5 *((volatile unsigned int*)(0x42668114UL)) +#define bFM3_GPIO_PDOR2_P6 *((volatile unsigned int*)(0x42668118UL)) +#define bFM3_GPIO_PDOR2_P7 *((volatile unsigned int*)(0x4266811CUL)) +#define bFM3_GPIO_PDOR2_P8 *((volatile unsigned int*)(0x42668120UL)) +#define bFM3_GPIO_PDOR3_P0 *((volatile unsigned int*)(0x42668180UL)) +#define bFM3_GPIO_PDOR3_P1 *((volatile unsigned int*)(0x42668184UL)) +#define bFM3_GPIO_PDOR3_P2 *((volatile unsigned int*)(0x42668188UL)) +#define bFM3_GPIO_PDOR3_P3 *((volatile unsigned int*)(0x4266818CUL)) +#define bFM3_GPIO_PDOR3_P4 *((volatile unsigned int*)(0x42668190UL)) +#define bFM3_GPIO_PDOR3_P5 *((volatile unsigned int*)(0x42668194UL)) +#define bFM3_GPIO_PDOR3_P6 *((volatile unsigned int*)(0x42668198UL)) +#define bFM3_GPIO_PDOR3_P7 *((volatile unsigned int*)(0x4266819CUL)) +#define bFM3_GPIO_PDOR3_P8 *((volatile unsigned int*)(0x426681A0UL)) +#define bFM3_GPIO_PDOR3_P9 *((volatile unsigned int*)(0x426681A4UL)) +#define bFM3_GPIO_PDOR3_PA *((volatile unsigned int*)(0x426681A8UL)) +#define bFM3_GPIO_PDOR3_PB *((volatile unsigned int*)(0x426681ACUL)) +#define bFM3_GPIO_PDOR3_PC *((volatile unsigned int*)(0x426681B0UL)) +#define bFM3_GPIO_PDOR3_PD *((volatile unsigned int*)(0x426681B4UL)) +#define bFM3_GPIO_PDOR3_PE *((volatile unsigned int*)(0x426681B8UL)) +#define bFM3_GPIO_PDOR3_PF *((volatile unsigned int*)(0x426681BCUL)) +#define bFM3_GPIO_PDOR4_P0 *((volatile unsigned int*)(0x42668200UL)) +#define bFM3_GPIO_PDOR4_P1 *((volatile unsigned int*)(0x42668204UL)) +#define bFM3_GPIO_PDOR4_P2 *((volatile unsigned int*)(0x42668208UL)) +#define bFM3_GPIO_PDOR4_P3 *((volatile unsigned int*)(0x4266820CUL)) +#define bFM3_GPIO_PDOR4_P4 *((volatile unsigned int*)(0x42668210UL)) +#define bFM3_GPIO_PDOR4_P5 *((volatile unsigned int*)(0x42668214UL)) +#define bFM3_GPIO_PDOR4_P6 *((volatile unsigned int*)(0x42668218UL)) +#define bFM3_GPIO_PDOR4_P7 *((volatile unsigned int*)(0x4266821CUL)) +#define bFM3_GPIO_PDOR4_P8 *((volatile unsigned int*)(0x42668220UL)) +#define bFM3_GPIO_PDOR4_P9 *((volatile unsigned int*)(0x42668224UL)) +#define bFM3_GPIO_PDOR4_PA *((volatile unsigned int*)(0x42668228UL)) +#define bFM3_GPIO_PDOR4_PB *((volatile unsigned int*)(0x4266822CUL)) +#define bFM3_GPIO_PDOR4_PC *((volatile unsigned int*)(0x42668230UL)) +#define bFM3_GPIO_PDOR4_PD *((volatile unsigned int*)(0x42668234UL)) +#define bFM3_GPIO_PDOR4_PE *((volatile unsigned int*)(0x42668238UL)) +#define bFM3_GPIO_PDOR5_P0 *((volatile unsigned int*)(0x42668280UL)) +#define bFM3_GPIO_PDOR5_P1 *((volatile unsigned int*)(0x42668284UL)) +#define bFM3_GPIO_PDOR5_P2 *((volatile unsigned int*)(0x42668288UL)) +#define bFM3_GPIO_PDOR5_P3 *((volatile unsigned int*)(0x4266828CUL)) +#define bFM3_GPIO_PDOR5_P4 *((volatile unsigned int*)(0x42668290UL)) +#define bFM3_GPIO_PDOR5_P5 *((volatile unsigned int*)(0x42668294UL)) +#define bFM3_GPIO_PDOR5_P6 *((volatile unsigned int*)(0x42668298UL)) +#define bFM3_GPIO_PDOR5_P7 *((volatile unsigned int*)(0x4266829CUL)) +#define bFM3_GPIO_PDOR5_P8 *((volatile unsigned int*)(0x426682A0UL)) +#define bFM3_GPIO_PDOR5_P9 *((volatile unsigned int*)(0x426682A4UL)) +#define bFM3_GPIO_PDOR5_PA *((volatile unsigned int*)(0x426682A8UL)) +#define bFM3_GPIO_PDOR5_PB *((volatile unsigned int*)(0x426682ACUL)) +#define bFM3_GPIO_PDOR6_P0 *((volatile unsigned int*)(0x42668300UL)) +#define bFM3_GPIO_PDOR6_P1 *((volatile unsigned int*)(0x42668304UL)) +#define bFM3_GPIO_PDOR6_P2 *((volatile unsigned int*)(0x42668308UL)) +#define bFM3_GPIO_PDOR6_P3 *((volatile unsigned int*)(0x4266830CUL)) +#define bFM3_GPIO_PDOR6_P4 *((volatile unsigned int*)(0x42668310UL)) +#define bFM3_GPIO_PDOR6_P5 *((volatile unsigned int*)(0x42668314UL)) +#define bFM3_GPIO_PDOR6_P6 *((volatile unsigned int*)(0x42668318UL)) +#define bFM3_GPIO_PDOR6_P7 *((volatile unsigned int*)(0x4266831CUL)) +#define bFM3_GPIO_PDOR6_P8 *((volatile unsigned int*)(0x42668320UL)) +#define bFM3_GPIO_PDOR7_P0 *((volatile unsigned int*)(0x42668380UL)) +#define bFM3_GPIO_PDOR7_P1 *((volatile unsigned int*)(0x42668384UL)) +#define bFM3_GPIO_PDOR7_P2 *((volatile unsigned int*)(0x42668388UL)) +#define bFM3_GPIO_PDOR7_P3 *((volatile unsigned int*)(0x4266838CUL)) +#define bFM3_GPIO_PDOR7_P4 *((volatile unsigned int*)(0x42668390UL)) +#define bFM3_GPIO_PDOR8_P0 *((volatile unsigned int*)(0x42668400UL)) +#define bFM3_GPIO_PDOR8_P1 *((volatile unsigned int*)(0x42668404UL)) +#define bFM3_GPIO_ADE_AN0 *((volatile unsigned int*)(0x4266A000UL)) +#define bFM3_GPIO_ADE_AN1 *((volatile unsigned int*)(0x4266A004UL)) +#define bFM3_GPIO_ADE_AN2 *((volatile unsigned int*)(0x4266A008UL)) +#define bFM3_GPIO_ADE_AN3 *((volatile unsigned int*)(0x4266A00CUL)) +#define bFM3_GPIO_ADE_AN4 *((volatile unsigned int*)(0x4266A010UL)) +#define bFM3_GPIO_ADE_AN5 *((volatile unsigned int*)(0x4266A014UL)) +#define bFM3_GPIO_ADE_AN6 *((volatile unsigned int*)(0x4266A018UL)) +#define bFM3_GPIO_ADE_AN7 *((volatile unsigned int*)(0x4266A01CUL)) +#define bFM3_GPIO_ADE_AN8 *((volatile unsigned int*)(0x4266A020UL)) +#define bFM3_GPIO_ADE_AN9 *((volatile unsigned int*)(0x4266A024UL)) +#define bFM3_GPIO_ADE_ANA *((volatile unsigned int*)(0x4266A028UL)) +#define bFM3_GPIO_ADE_ANB *((volatile unsigned int*)(0x4266A02CUL)) +#define bFM3_GPIO_ADE_ANC *((volatile unsigned int*)(0x4266A030UL)) +#define bFM3_GPIO_ADE_AND *((volatile unsigned int*)(0x4266A034UL)) +#define bFM3_GPIO_ADE_ANE *((volatile unsigned int*)(0x4266A038UL)) +#define bFM3_GPIO_ADE_ANF *((volatile unsigned int*)(0x4266A03CUL)) +#define bFM3_GPIO_SPSR_SUBXC *((volatile unsigned int*)(0x4266B000UL)) +#define bFM3_GPIO_SPSR_USB0C *((volatile unsigned int*)(0x4266B010UL)) +#define bFM3_GPIO_EPFR00_NMIS *((volatile unsigned int*)(0x4266C000UL)) +#define bFM3_GPIO_EPFR00_CROUTE *((volatile unsigned int*)(0x4266C004UL)) +#define bFM3_GPIO_EPFR00_USB0PE *((volatile unsigned int*)(0x4266C024UL)) +#define bFM3_GPIO_EPFR00_JTAGEN0B *((volatile unsigned int*)(0x4266C040UL)) +#define bFM3_GPIO_EPFR00_JTAGEN1S *((volatile unsigned int*)(0x4266C044UL)) +#define bFM3_GPIO_EPFR00_TRC0E *((volatile unsigned int*)(0x4266C060UL)) +#define bFM3_GPIO_EPFR00_TRC1E *((volatile unsigned int*)(0x4266C064UL)) +#define bFM3_GPIO_EPFR01_RTO00E0 *((volatile unsigned int*)(0x4266C080UL)) +#define bFM3_GPIO_EPFR01_RTO00E1 *((volatile unsigned int*)(0x4266C084UL)) +#define bFM3_GPIO_EPFR01_RTO01E0 *((volatile unsigned int*)(0x4266C088UL)) +#define bFM3_GPIO_EPFR01_RTO01E1 *((volatile unsigned int*)(0x4266C08CUL)) +#define bFM3_GPIO_EPFR01_RTO02E0 *((volatile unsigned int*)(0x4266C090UL)) +#define bFM3_GPIO_EPFR01_RTO02E1 *((volatile unsigned int*)(0x4266C094UL)) +#define bFM3_GPIO_EPFR01_RTO03E0 *((volatile unsigned int*)(0x4266C098UL)) +#define bFM3_GPIO_EPFR01_RTO03E1 *((volatile unsigned int*)(0x4266C09CUL)) +#define bFM3_GPIO_EPFR01_RTO04E0 *((volatile unsigned int*)(0x4266C0A0UL)) +#define bFM3_GPIO_EPFR01_RTO04E1 *((volatile unsigned int*)(0x4266C0A4UL)) +#define bFM3_GPIO_EPFR01_RTO05E0 *((volatile unsigned int*)(0x4266C0A8UL)) +#define bFM3_GPIO_EPFR01_RTO05E1 *((volatile unsigned int*)(0x4266C0ACUL)) +#define bFM3_GPIO_EPFR01_DTTI0C *((volatile unsigned int*)(0x4266C0B0UL)) +#define bFM3_GPIO_EPFR01_DTTI0S0 *((volatile unsigned int*)(0x4266C0C0UL)) +#define bFM3_GPIO_EPFR01_DTTI0S1 *((volatile unsigned int*)(0x4266C0C4UL)) +#define bFM3_GPIO_EPFR01_FRCK0S0 *((volatile unsigned int*)(0x4266C0C8UL)) +#define bFM3_GPIO_EPFR01_FRCK0S1 *((volatile unsigned int*)(0x4266C0CCUL)) +#define bFM3_GPIO_EPFR01_IC00S0 *((volatile unsigned int*)(0x4266C0D0UL)) +#define bFM3_GPIO_EPFR01_IC00S1 *((volatile unsigned int*)(0x4266C0D4UL)) +#define bFM3_GPIO_EPFR01_IC00S2 *((volatile unsigned int*)(0x4266C0D8UL)) +#define bFM3_GPIO_EPFR01_IC01S0 *((volatile unsigned int*)(0x4266C0DCUL)) +#define bFM3_GPIO_EPFR01_IC01S1 *((volatile unsigned int*)(0x4266C0E0UL)) +#define bFM3_GPIO_EPFR01_IC01S2 *((volatile unsigned int*)(0x4266C0E4UL)) +#define bFM3_GPIO_EPFR01_IC02S0 *((volatile unsigned int*)(0x4266C0E8UL)) +#define bFM3_GPIO_EPFR01_IC02S1 *((volatile unsigned int*)(0x4266C0ECUL)) +#define bFM3_GPIO_EPFR01_IC02S2 *((volatile unsigned int*)(0x4266C0F0UL)) +#define bFM3_GPIO_EPFR01_IC03S0 *((volatile unsigned int*)(0x4266C0F4UL)) +#define bFM3_GPIO_EPFR01_IC03S1 *((volatile unsigned int*)(0x4266C0F8UL)) +#define bFM3_GPIO_EPFR01_IC03S2 *((volatile unsigned int*)(0x4266C0FCUL)) +#define bFM3_GPIO_EPFR02_RTO10E0 *((volatile unsigned int*)(0x4266C100UL)) +#define bFM3_GPIO_EPFR02_RTO10E1 *((volatile unsigned int*)(0x4266C104UL)) +#define bFM3_GPIO_EPFR02_RTO11E0 *((volatile unsigned int*)(0x4266C108UL)) +#define bFM3_GPIO_EPFR02_RTO11E1 *((volatile unsigned int*)(0x4266C10CUL)) +#define bFM3_GPIO_EPFR02_RTO12E0 *((volatile unsigned int*)(0x4266C110UL)) +#define bFM3_GPIO_EPFR02_RTO12E1 *((volatile unsigned int*)(0x4266C114UL)) +#define bFM3_GPIO_EPFR02_RTO13E0 *((volatile unsigned int*)(0x4266C118UL)) +#define bFM3_GPIO_EPFR02_RTO13E1 *((volatile unsigned int*)(0x4266C11CUL)) +#define bFM3_GPIO_EPFR02_RTO14E0 *((volatile unsigned int*)(0x4266C120UL)) +#define bFM3_GPIO_EPFR02_RTO14E1 *((volatile unsigned int*)(0x4266C124UL)) +#define bFM3_GPIO_EPFR02_RTO15E0 *((volatile unsigned int*)(0x4266C128UL)) +#define bFM3_GPIO_EPFR02_RTO15E1 *((volatile unsigned int*)(0x4266C12CUL)) +#define bFM3_GPIO_EPFR02_DTTI1C *((volatile unsigned int*)(0x4266C130UL)) +#define bFM3_GPIO_EPFR02_DTTI1S0 *((volatile unsigned int*)(0x4266C140UL)) +#define bFM3_GPIO_EPFR02_DTTI1S1 *((volatile unsigned int*)(0x4266C144UL)) +#define bFM3_GPIO_EPFR02_FRCK1S0 *((volatile unsigned int*)(0x4266C148UL)) +#define bFM3_GPIO_EPFR02_FRCK1S1 *((volatile unsigned int*)(0x4266C14CUL)) +#define bFM3_GPIO_EPFR02_IC10S0 *((volatile unsigned int*)(0x4266C150UL)) +#define bFM3_GPIO_EPFR02_IC10S1 *((volatile unsigned int*)(0x4266C154UL)) +#define bFM3_GPIO_EPFR02_IC10S2 *((volatile unsigned int*)(0x4266C158UL)) +#define bFM3_GPIO_EPFR02_IC11S0 *((volatile unsigned int*)(0x4266C15CUL)) +#define bFM3_GPIO_EPFR02_IC11S1 *((volatile unsigned int*)(0x4266C160UL)) +#define bFM3_GPIO_EPFR02_IC11S2 *((volatile unsigned int*)(0x4266C164UL)) +#define bFM3_GPIO_EPFR02_IC12S0 *((volatile unsigned int*)(0x4266C168UL)) +#define bFM3_GPIO_EPFR02_IC12S1 *((volatile unsigned int*)(0x4266C16CUL)) +#define bFM3_GPIO_EPFR02_IC12S2 *((volatile unsigned int*)(0x4266C170UL)) +#define bFM3_GPIO_EPFR02_IC13S0 *((volatile unsigned int*)(0x4266C174UL)) +#define bFM3_GPIO_EPFR02_IC13S1 *((volatile unsigned int*)(0x4266C178UL)) +#define bFM3_GPIO_EPFR02_IC13S2 *((volatile unsigned int*)(0x4266C17CUL)) +#define bFM3_GPIO_EPFR04_TIOA0E0 *((volatile unsigned int*)(0x4266C208UL)) +#define bFM3_GPIO_EPFR04_TIOA0E1 *((volatile unsigned int*)(0x4266C20CUL)) +#define bFM3_GPIO_EPFR04_TIOB0S0 *((volatile unsigned int*)(0x4266C210UL)) +#define bFM3_GPIO_EPFR04_TIOB0S1 *((volatile unsigned int*)(0x4266C214UL)) +#define bFM3_GPIO_EPFR04_TIOA1S0 *((volatile unsigned int*)(0x4266C220UL)) +#define bFM3_GPIO_EPFR04_TIOA1S1 *((volatile unsigned int*)(0x4266C224UL)) +#define bFM3_GPIO_EPFR04_TIOA1E0 *((volatile unsigned int*)(0x4266C228UL)) +#define bFM3_GPIO_EPFR04_TIOA1E1 *((volatile unsigned int*)(0x4266C22CUL)) +#define bFM3_GPIO_EPFR04_TIOB1S0 *((volatile unsigned int*)(0x4266C230UL)) +#define bFM3_GPIO_EPFR04_TIOB1S1 *((volatile unsigned int*)(0x4266C234UL)) +#define bFM3_GPIO_EPFR04_TIOA2E0 *((volatile unsigned int*)(0x4266C248UL)) +#define bFM3_GPIO_EPFR04_TIOA2E1 *((volatile unsigned int*)(0x4266C24CUL)) +#define bFM3_GPIO_EPFR04_TIOB2S0 *((volatile unsigned int*)(0x4266C250UL)) +#define bFM3_GPIO_EPFR04_TIOB2S1 *((volatile unsigned int*)(0x4266C254UL)) +#define bFM3_GPIO_EPFR04_TIOA3S0 *((volatile unsigned int*)(0x4266C260UL)) +#define bFM3_GPIO_EPFR04_TIOA3S1 *((volatile unsigned int*)(0x4266C264UL)) +#define bFM3_GPIO_EPFR04_TIOA3E0 *((volatile unsigned int*)(0x4266C268UL)) +#define bFM3_GPIO_EPFR04_TIOA3E1 *((volatile unsigned int*)(0x4266C26CUL)) +#define bFM3_GPIO_EPFR04_TIOB3S0 *((volatile unsigned int*)(0x4266C270UL)) +#define bFM3_GPIO_EPFR04_TIOB3S1 *((volatile unsigned int*)(0x4266C274UL)) +#define bFM3_GPIO_EPFR05_TIOA4E0 *((volatile unsigned int*)(0x4266C288UL)) +#define bFM3_GPIO_EPFR05_TIOA4E1 *((volatile unsigned int*)(0x4266C28CUL)) +#define bFM3_GPIO_EPFR05_TIOB4S0 *((volatile unsigned int*)(0x4266C290UL)) +#define bFM3_GPIO_EPFR05_TIOB4S1 *((volatile unsigned int*)(0x4266C294UL)) +#define bFM3_GPIO_EPFR05_TIOA5S0 *((volatile unsigned int*)(0x4266C2A0UL)) +#define bFM3_GPIO_EPFR05_TIOA5S1 *((volatile unsigned int*)(0x4266C2A4UL)) +#define bFM3_GPIO_EPFR05_TIOA5E0 *((volatile unsigned int*)(0x4266C2A8UL)) +#define bFM3_GPIO_EPFR05_TIOA5E1 *((volatile unsigned int*)(0x4266C2ACUL)) +#define bFM3_GPIO_EPFR05_TIOB5S0 *((volatile unsigned int*)(0x4266C2B0UL)) +#define bFM3_GPIO_EPFR05_TIOB5S1 *((volatile unsigned int*)(0x4266C2B4UL)) +#define bFM3_GPIO_EPFR05_TIOA6E0 *((volatile unsigned int*)(0x4266C2C8UL)) +#define bFM3_GPIO_EPFR05_TIOA6E1 *((volatile unsigned int*)(0x4266C2CCUL)) +#define bFM3_GPIO_EPFR05_TIOB6S0 *((volatile unsigned int*)(0x4266C2D0UL)) +#define bFM3_GPIO_EPFR05_TIOB6S1 *((volatile unsigned int*)(0x4266C2D4UL)) +#define bFM3_GPIO_EPFR05_TIOA7S0 *((volatile unsigned int*)(0x4266C2E0UL)) +#define bFM3_GPIO_EPFR05_TIOA7S1 *((volatile unsigned int*)(0x4266C2E4UL)) +#define bFM3_GPIO_EPFR05_TIOA7E0 *((volatile unsigned int*)(0x4266C2E8UL)) +#define bFM3_GPIO_EPFR05_TIOA7E1 *((volatile unsigned int*)(0x4266C2ECUL)) +#define bFM3_GPIO_EPFR05_TIOB7S0 *((volatile unsigned int*)(0x4266C2F0UL)) +#define bFM3_GPIO_EPFR05_TIOB7S1 *((volatile unsigned int*)(0x4266C2F4UL)) +#define bFM3_GPIO_EPFR06_EINT00S0 *((volatile unsigned int*)(0x4266C300UL)) +#define bFM3_GPIO_EPFR06_EINT00S1 *((volatile unsigned int*)(0x4266C304UL)) +#define bFM3_GPIO_EPFR06_EINT01S0 *((volatile unsigned int*)(0x4266C308UL)) +#define bFM3_GPIO_EPFR06_EINT01S1 *((volatile unsigned int*)(0x4266C30CUL)) +#define bFM3_GPIO_EPFR06_EINT02S0 *((volatile unsigned int*)(0x4266C310UL)) +#define bFM3_GPIO_EPFR06_EINT02S1 *((volatile unsigned int*)(0x4266C314UL)) +#define bFM3_GPIO_EPFR06_EINT03S0 *((volatile unsigned int*)(0x4266C318UL)) +#define bFM3_GPIO_EPFR06_EINT03S1 *((volatile unsigned int*)(0x4266C31CUL)) +#define bFM3_GPIO_EPFR06_EINT04S0 *((volatile unsigned int*)(0x4266C320UL)) +#define bFM3_GPIO_EPFR06_EINT04S1 *((volatile unsigned int*)(0x4266C324UL)) +#define bFM3_GPIO_EPFR06_EINT05S0 *((volatile unsigned int*)(0x4266C328UL)) +#define bFM3_GPIO_EPFR06_EINT05S1 *((volatile unsigned int*)(0x4266C32CUL)) +#define bFM3_GPIO_EPFR06_EINT06S0 *((volatile unsigned int*)(0x4266C330UL)) +#define bFM3_GPIO_EPFR06_EINT06S1 *((volatile unsigned int*)(0x4266C334UL)) +#define bFM3_GPIO_EPFR06_EINT07S0 *((volatile unsigned int*)(0x4266C338UL)) +#define bFM3_GPIO_EPFR06_EINT07S1 *((volatile unsigned int*)(0x4266C33CUL)) +#define bFM3_GPIO_EPFR06_EINT08S0 *((volatile unsigned int*)(0x4266C340UL)) +#define bFM3_GPIO_EPFR06_EINT08S1 *((volatile unsigned int*)(0x4266C344UL)) +#define bFM3_GPIO_EPFR06_EINT09S0 *((volatile unsigned int*)(0x4266C348UL)) +#define bFM3_GPIO_EPFR06_EINT09S1 *((volatile unsigned int*)(0x4266C34CUL)) +#define bFM3_GPIO_EPFR06_EINT10S0 *((volatile unsigned int*)(0x4266C350UL)) +#define bFM3_GPIO_EPFR06_EINT10S1 *((volatile unsigned int*)(0x4266C354UL)) +#define bFM3_GPIO_EPFR06_EINT11S0 *((volatile unsigned int*)(0x4266C358UL)) +#define bFM3_GPIO_EPFR06_EINT11S1 *((volatile unsigned int*)(0x4266C35CUL)) +#define bFM3_GPIO_EPFR06_EINT12S0 *((volatile unsigned int*)(0x4266C360UL)) +#define bFM3_GPIO_EPFR06_EINT12S1 *((volatile unsigned int*)(0x4266C364UL)) +#define bFM3_GPIO_EPFR06_EINT13S0 *((volatile unsigned int*)(0x4266C368UL)) +#define bFM3_GPIO_EPFR06_EINT13S1 *((volatile unsigned int*)(0x4266C36CUL)) +#define bFM3_GPIO_EPFR06_EINT14S0 *((volatile unsigned int*)(0x4266C370UL)) +#define bFM3_GPIO_EPFR06_EINT14S1 *((volatile unsigned int*)(0x4266C374UL)) +#define bFM3_GPIO_EPFR06_EINT15S0 *((volatile unsigned int*)(0x4266C378UL)) +#define bFM3_GPIO_EPFR06_EINT15S1 *((volatile unsigned int*)(0x4266C37CUL)) +#define bFM3_GPIO_EPFR07_SIN0S0 *((volatile unsigned int*)(0x4266C390UL)) +#define bFM3_GPIO_EPFR07_SIN0S1 *((volatile unsigned int*)(0x4266C394UL)) +#define bFM3_GPIO_EPFR07_SOT0B0 *((volatile unsigned int*)(0x4266C398UL)) +#define bFM3_GPIO_EPFR07_SOT0B1 *((volatile unsigned int*)(0x4266C39CUL)) +#define bFM3_GPIO_EPFR07_SCK0B0 *((volatile unsigned int*)(0x4266C3A0UL)) +#define bFM3_GPIO_EPFR07_SCK0B1 *((volatile unsigned int*)(0x4266C3A4UL)) +#define bFM3_GPIO_EPFR07_SIN1S0 *((volatile unsigned int*)(0x4266C3A8UL)) +#define bFM3_GPIO_EPFR07_SIN1S1 *((volatile unsigned int*)(0x4266C3ACUL)) +#define bFM3_GPIO_EPFR07_SOT1B0 *((volatile unsigned int*)(0x4266C3B0UL)) +#define bFM3_GPIO_EPFR07_SOT1B1 *((volatile unsigned int*)(0x4266C3B4UL)) +#define bFM3_GPIO_EPFR07_SCK1B0 *((volatile unsigned int*)(0x4266C3B8UL)) +#define bFM3_GPIO_EPFR07_SCK1B1 *((volatile unsigned int*)(0x4266C3BCUL)) +#define bFM3_GPIO_EPFR07_SIN2S0 *((volatile unsigned int*)(0x4266C3C0UL)) +#define bFM3_GPIO_EPFR07_SIN2S1 *((volatile unsigned int*)(0x4266C3C4UL)) +#define bFM3_GPIO_EPFR07_SOT2B0 *((volatile unsigned int*)(0x4266C3C8UL)) +#define bFM3_GPIO_EPFR07_SOT2B1 *((volatile unsigned int*)(0x4266C3CCUL)) +#define bFM3_GPIO_EPFR07_SCK2B0 *((volatile unsigned int*)(0x4266C3D0UL)) +#define bFM3_GPIO_EPFR07_SCK2B1 *((volatile unsigned int*)(0x4266C3D4UL)) +#define bFM3_GPIO_EPFR07_SIN3S0 *((volatile unsigned int*)(0x4266C3D8UL)) +#define bFM3_GPIO_EPFR07_SIN3S1 *((volatile unsigned int*)(0x4266C3DCUL)) +#define bFM3_GPIO_EPFR07_SOT3B0 *((volatile unsigned int*)(0x4266C3E0UL)) +#define bFM3_GPIO_EPFR07_SOT3B1 *((volatile unsigned int*)(0x4266C3E4UL)) +#define bFM3_GPIO_EPFR07_SCK3B0 *((volatile unsigned int*)(0x4266C3E8UL)) +#define bFM3_GPIO_EPFR07_SCK3B1 *((volatile unsigned int*)(0x4266C3ECUL)) +#define bFM3_GPIO_EPFR08_RTS4E0 *((volatile unsigned int*)(0x4266C400UL)) +#define bFM3_GPIO_EPFR08_RTS4E1 *((volatile unsigned int*)(0x4266C404UL)) +#define bFM3_GPIO_EPFR08_CTS4S0 *((volatile unsigned int*)(0x4266C408UL)) +#define bFM3_GPIO_EPFR08_CTS4S1 *((volatile unsigned int*)(0x4266C40CUL)) +#define bFM3_GPIO_EPFR08_SIN4S0 *((volatile unsigned int*)(0x4266C410UL)) +#define bFM3_GPIO_EPFR08_SIN4S1 *((volatile unsigned int*)(0x4266C414UL)) +#define bFM3_GPIO_EPFR08_SOT4B0 *((volatile unsigned int*)(0x4266C418UL)) +#define bFM3_GPIO_EPFR08_SOT4B1 *((volatile unsigned int*)(0x4266C41CUL)) +#define bFM3_GPIO_EPFR08_SCK4B0 *((volatile unsigned int*)(0x4266C420UL)) +#define bFM3_GPIO_EPFR08_SCK4B1 *((volatile unsigned int*)(0x4266C424UL)) +#define bFM3_GPIO_EPFR08_SIN5S0 *((volatile unsigned int*)(0x4266C428UL)) +#define bFM3_GPIO_EPFR08_SIN5S1 *((volatile unsigned int*)(0x4266C42CUL)) +#define bFM3_GPIO_EPFR08_SOT5B0 *((volatile unsigned int*)(0x4266C430UL)) +#define bFM3_GPIO_EPFR08_SOT5B1 *((volatile unsigned int*)(0x4266C434UL)) +#define bFM3_GPIO_EPFR08_SCK5B0 *((volatile unsigned int*)(0x4266C438UL)) +#define bFM3_GPIO_EPFR08_SCK5B1 *((volatile unsigned int*)(0x4266C43CUL)) +#define bFM3_GPIO_EPFR08_SIN6S0 *((volatile unsigned int*)(0x4266C440UL)) +#define bFM3_GPIO_EPFR08_SIN6S1 *((volatile unsigned int*)(0x4266C444UL)) +#define bFM3_GPIO_EPFR08_SOT6B0 *((volatile unsigned int*)(0x4266C448UL)) +#define bFM3_GPIO_EPFR08_SOT6B1 *((volatile unsigned int*)(0x4266C44CUL)) +#define bFM3_GPIO_EPFR08_SCK6B0 *((volatile unsigned int*)(0x4266C450UL)) +#define bFM3_GPIO_EPFR08_SCK6B1 *((volatile unsigned int*)(0x4266C454UL)) +#define bFM3_GPIO_EPFR08_SIN7S0 *((volatile unsigned int*)(0x4266C458UL)) +#define bFM3_GPIO_EPFR08_SIN7S1 *((volatile unsigned int*)(0x4266C45CUL)) +#define bFM3_GPIO_EPFR08_SOT7B0 *((volatile unsigned int*)(0x4266C460UL)) +#define bFM3_GPIO_EPFR08_SOT7B1 *((volatile unsigned int*)(0x4266C464UL)) +#define bFM3_GPIO_EPFR08_SCK7B0 *((volatile unsigned int*)(0x4266C468UL)) +#define bFM3_GPIO_EPFR08_SCK7B1 *((volatile unsigned int*)(0x4266C46CUL)) +#define bFM3_GPIO_EPFR09_QAIN0S0 *((volatile unsigned int*)(0x4266C480UL)) +#define bFM3_GPIO_EPFR09_QAIN0S1 *((volatile unsigned int*)(0x4266C484UL)) +#define bFM3_GPIO_EPFR09_QBIN0S0 *((volatile unsigned int*)(0x4266C488UL)) +#define bFM3_GPIO_EPFR09_QBIN0S1 *((volatile unsigned int*)(0x4266C48CUL)) +#define bFM3_GPIO_EPFR09_QZIN0S0 *((volatile unsigned int*)(0x4266C490UL)) +#define bFM3_GPIO_EPFR09_QZIN0S1 *((volatile unsigned int*)(0x4266C494UL)) +#define bFM3_GPIO_EPFR09_QAIN1S0 *((volatile unsigned int*)(0x4266C498UL)) +#define bFM3_GPIO_EPFR09_QAIN1S1 *((volatile unsigned int*)(0x4266C49CUL)) +#define bFM3_GPIO_EPFR09_QBIN1S0 *((volatile unsigned int*)(0x4266C4A0UL)) +#define bFM3_GPIO_EPFR09_QBIN1S1 *((volatile unsigned int*)(0x4266C4A4UL)) +#define bFM3_GPIO_EPFR09_QZIN1S0 *((volatile unsigned int*)(0x4266C4A8UL)) +#define bFM3_GPIO_EPFR09_QZIN1S1 *((volatile unsigned int*)(0x4266C4ACUL)) +#define bFM3_GPIO_EPFR09_ADTRG0S0 *((volatile unsigned int*)(0x4266C4B0UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S1 *((volatile unsigned int*)(0x4266C4B4UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S2 *((volatile unsigned int*)(0x4266C4B8UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S3 *((volatile unsigned int*)(0x4266C4BCUL)) +#define bFM3_GPIO_EPFR09_ADTRG1S0 *((volatile unsigned int*)(0x4266C4C0UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S1 *((volatile unsigned int*)(0x4266C4C4UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S2 *((volatile unsigned int*)(0x4266C4C8UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S3 *((volatile unsigned int*)(0x4266C4CCUL)) +#define bFM3_GPIO_EPFR09_ADTRG2S0 *((volatile unsigned int*)(0x4266C4D0UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S1 *((volatile unsigned int*)(0x4266C4D4UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S2 *((volatile unsigned int*)(0x4266C4D8UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S3 *((volatile unsigned int*)(0x4266C4DCUL)) +#define bFM3_GPIO_EPFR09_CRX0S0 *((volatile unsigned int*)(0x4266C4E0UL)) +#define bFM3_GPIO_EPFR09_CRX0S1 *((volatile unsigned int*)(0x4266C4E4UL)) +#define bFM3_GPIO_EPFR09_CTX0E0 *((volatile unsigned int*)(0x4266C4E8UL)) +#define bFM3_GPIO_EPFR09_CTX0E1 *((volatile unsigned int*)(0x4266C4ECUL)) +#define bFM3_GPIO_EPFR09_CRX1S0 *((volatile unsigned int*)(0x4266C4F0UL)) +#define bFM3_GPIO_EPFR09_CRX1S1 *((volatile unsigned int*)(0x4266C4F4UL)) +#define bFM3_GPIO_EPFR09_CTX1E0 *((volatile unsigned int*)(0x4266C4F8UL)) +#define bFM3_GPIO_EPFR09_CTX1E1 *((volatile unsigned int*)(0x4266C4FCUL)) +#define bFM3_GPIO_EPFR10_UEDEFB *((volatile unsigned int*)(0x4266C500UL)) +#define bFM3_GPIO_EPFR10_UEDTHB *((volatile unsigned int*)(0x4266C504UL)) +#define bFM3_GPIO_EPFR10_TESTB *((volatile unsigned int*)(0x4266C508UL)) +#define bFM3_GPIO_EPFR10_UEWEXE *((volatile unsigned int*)(0x4266C50CUL)) +#define bFM3_GPIO_EPFR10_UEDQME *((volatile unsigned int*)(0x4266C510UL)) +#define bFM3_GPIO_EPFR10_UEOEXE *((volatile unsigned int*)(0x4266C514UL)) +#define bFM3_GPIO_EPFR10_UEFLSE *((volatile unsigned int*)(0x4266C518UL)) +#define bFM3_GPIO_EPFR10_UECS1E *((volatile unsigned int*)(0x4266C51CUL)) +#define bFM3_GPIO_EPFR10_UECS2E *((volatile unsigned int*)(0x4266C520UL)) +#define bFM3_GPIO_EPFR10_UECS3E *((volatile unsigned int*)(0x4266C524UL)) +#define bFM3_GPIO_EPFR10_UECS4E *((volatile unsigned int*)(0x4266C528UL)) +#define bFM3_GPIO_EPFR10_UECS5E *((volatile unsigned int*)(0x4266C52CUL)) +#define bFM3_GPIO_EPFR10_UECS6E *((volatile unsigned int*)(0x4266C530UL)) +#define bFM3_GPIO_EPFR10_UECS7E *((volatile unsigned int*)(0x4266C534UL)) +#define bFM3_GPIO_EPFR10_UEAOOE *((volatile unsigned int*)(0x4266C538UL)) +#define bFM3_GPIO_EPFR10_UEA08E *((volatile unsigned int*)(0x4266C53CUL)) +#define bFM3_GPIO_EPFR10_UEA09E *((volatile unsigned int*)(0x4266C540UL)) +#define bFM3_GPIO_EPFR10_UEA10E *((volatile unsigned int*)(0x4266C544UL)) +#define bFM3_GPIO_EPFR10_UEA11E *((volatile unsigned int*)(0x4266C548UL)) +#define bFM3_GPIO_EPFR10_UEA12E *((volatile unsigned int*)(0x4266C54CUL)) +#define bFM3_GPIO_EPFR10_UEA13E *((volatile unsigned int*)(0x4266C550UL)) +#define bFM3_GPIO_EPFR10_UEA14E *((volatile unsigned int*)(0x4266C554UL)) +#define bFM3_GPIO_EPFR10_UEA15E *((volatile unsigned int*)(0x4266C558UL)) +#define bFM3_GPIO_EPFR10_UEA16E *((volatile unsigned int*)(0x4266C55CUL)) +#define bFM3_GPIO_EPFR10_UEA17E *((volatile unsigned int*)(0x4266C560UL)) +#define bFM3_GPIO_EPFR10_UEA18E *((volatile unsigned int*)(0x4266C564UL)) +#define bFM3_GPIO_EPFR10_UEA19E *((volatile unsigned int*)(0x4266C568UL)) +#define bFM3_GPIO_EPFR10_UEA20E *((volatile unsigned int*)(0x4266C56CUL)) +#define bFM3_GPIO_EPFR10_UEA21E *((volatile unsigned int*)(0x4266C570UL)) +#define bFM3_GPIO_EPFR10_UEA22E *((volatile unsigned int*)(0x4266C574UL)) +#define bFM3_GPIO_EPFR10_UEA23E *((volatile unsigned int*)(0x4266C578UL)) +#define bFM3_GPIO_EPFR10_UEA24E *((volatile unsigned int*)(0x4266C57CUL)) + +/* Low voltage detection registers */ +#define bFM3_LVD_LVD_CTL_SVHI0 *((volatile unsigned int*)(0x426A0008UL)) +#define bFM3_LVD_LVD_CTL_SVHI1 *((volatile unsigned int*)(0x426A000CUL)) +#define bFM3_LVD_LVD_CTL_SVHI2 *((volatile unsigned int*)(0x426A0010UL)) +#define bFM3_LVD_LVD_CTL_SVHI3 *((volatile unsigned int*)(0x426A0014UL)) +#define bFM3_LVD_LVD_CTL_LVDIE *((volatile unsigned int*)(0x426A001CUL)) +#define bFM3_LVD_LVD_STR_LVDIR *((volatile unsigned int*)(0x426A009CUL)) +#define bFM3_LVD_LVD_CLR_LVDCL *((volatile unsigned int*)(0x426A011CUL)) +#define bFM3_LVD_LVD_STR2_LVDIRDY *((volatile unsigned int*)(0x426A021CUL)) + +/* USB clock registers */ +#define bFM3_USBCLK_UCCR_UCEN *((volatile unsigned int*)(0x426C0000UL)) +#define bFM3_USBCLK_UCCR_UCSEL *((volatile unsigned int*)(0x426C0004UL)) +#define bFM3_USBCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) +#define bFM3_USBCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) +#define bFM3_USBCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) +#define bFM3_USBCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) +#define bFM3_USBCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) +#define bFM3_USBCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) +#define bFM3_USBCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) +#define bFM3_USBCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) +#define bFM3_USBCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) +#define bFM3_USBCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) +#define bFM3_USBCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) +#define bFM3_USBCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) +#define bFM3_USBCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) +#define bFM3_USBCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) +#define bFM3_USBCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) +#define bFM3_USBCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) +#define bFM3_USBCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) +#define bFM3_USBCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) +#define bFM3_USBCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) +#define bFM3_USBCLK_USBEN_USBEN *((volatile unsigned int*)(0x426C0600UL)) + +/* CAN prescaler register */ +#define bFM3_CANPRES_CANPRE_CANPRE0 *((volatile unsigned int*)(0x426E0000UL)) +#define bFM3_CANPRES_CANPRE_CANPRE1 *((volatile unsigned int*)(0x426E0004UL)) +#define bFM3_CANPRES_CANPRE_CANPRE2 *((volatile unsigned int*)(0x426E0008UL)) +#define bFM3_CANPRES_CANPRE_CANPRE3 *((volatile unsigned int*)(0x426E000CUL)) + +/* UART asynchronous channel 0 registers */ +#define bFM3_MFS0_UART_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_UART_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_UART_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_UART_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_UART_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_UART_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_UART_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_UART_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_UART_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_UART_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_UART_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_UART_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_UART_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_UART_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_UART_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_UART_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_UART_ESCR_P *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_UART_ESCR_PEN *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_UART_ESCR_INV *((volatile unsigned int*)(0x42700094UL)) +#define bFM3_MFS0_UART_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_UART_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_UART_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_UART_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_UART_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_UART_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_UART_SSR_PE *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_UART_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_UART_RDR_AD *((volatile unsigned int*)(0x42700120UL)) +#define bFM3_MFS0_UART_TDR_AD *((volatile unsigned int*)(0x42700120UL)) +#define bFM3_MFS0_UART_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) +#define bFM3_MFS0_UART_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) + +/* UART synchronous channel 0 registers */ +#define bFM3_MFS0_CSIO_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42700004UL)) +#define bFM3_MFS0_CSIO_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_CSIO_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_CSIO_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_CSIO_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_CSIO_SCR_SPI *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_CSIO_SCR_MS *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_CSIO_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_CSIO_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_CSIO_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) + +/* UART LIN channel 0 registers */ +#define bFM3_MFS0_LIN_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_LIN_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_LIN_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_LIN_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_LIN_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_LIN_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_LIN_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_LIN_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_LIN_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_LIN_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_LIN_SCR_LBR *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_LIN_SCR_MS *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_LIN_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_LIN_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_LIN_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_LIN_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_LIN_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_LIN_SSR_LBD *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_LIN_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_LIN_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) +#define bFM3_MFS0_LIN_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) + +/* I2C channel 0 registers */ +#define bFM3_MFS0_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42700004UL)) +#define bFM3_MFS0_I2C_SMR_TIE *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_I2C_SMR_RIE *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_I2C_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_I2C_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_I2C_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_I2C_IBCR_INT *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_I2C_IBCR_BER *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_I2C_IBCR_INTE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_I2C_IBCR_ACT *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_I2C_IBCR_SCC *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_I2C_IBSR_BB *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_I2C_IBSR_SPC *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_I2C_IBSR_RSC *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_I2C_IBSR_AL *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_I2C_IBSR_TRX *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_I2C_IBSR_RSA *((volatile unsigned int*)(0x42700094UL)) +#define bFM3_MFS0_I2C_IBSR_RACK *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_I2C_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_I2C_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_I2C_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_I2C_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_I2C_SSR_TBIE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_I2C_SSR_DMA *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_I2C_SSR_TSET *((volatile unsigned int*)(0x427000B8UL)) +#define bFM3_MFS0_I2C_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42700200UL)) +#define bFM3_MFS0_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42700204UL)) +#define bFM3_MFS0_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42700208UL)) +#define bFM3_MFS0_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270020CUL)) +#define bFM3_MFS0_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42700210UL)) +#define bFM3_MFS0_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42700214UL)) +#define bFM3_MFS0_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42700218UL)) +#define bFM3_MFS0_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270021CUL)) +#define bFM3_MFS0_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42700220UL)) +#define bFM3_MFS0_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42700224UL)) +#define bFM3_MFS0_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42700228UL)) +#define bFM3_MFS0_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270022CUL)) +#define bFM3_MFS0_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42700230UL)) +#define bFM3_MFS0_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42700234UL)) +#define bFM3_MFS0_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42700238UL)) +#define bFM3_MFS0_I2C_ISMK_EN *((volatile unsigned int*)(0x4270023CUL)) + +/* UART asynchronous channel 1 registers */ +#define bFM3_MFS1_UART_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_UART_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_UART_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_UART_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_UART_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_UART_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_UART_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_UART_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_UART_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_UART_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_UART_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_UART_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_UART_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_UART_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_UART_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_UART_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_UART_ESCR_P *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_UART_ESCR_PEN *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_UART_ESCR_INV *((volatile unsigned int*)(0x42702094UL)) +#define bFM3_MFS1_UART_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_UART_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_UART_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_UART_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_UART_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_UART_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_UART_SSR_PE *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_UART_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_UART_RDR_AD *((volatile unsigned int*)(0x42702120UL)) +#define bFM3_MFS1_UART_TDR_AD *((volatile unsigned int*)(0x42702120UL)) +#define bFM3_MFS1_UART_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) +#define bFM3_MFS1_UART_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) + +/* UART synchronous channel 1 registers */ +#define bFM3_MFS1_CSIO_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42702004UL)) +#define bFM3_MFS1_CSIO_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_CSIO_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_CSIO_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_CSIO_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_CSIO_SCR_SPI *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_CSIO_SCR_MS *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_CSIO_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_CSIO_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_CSIO_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) + +/* UART LIN channel 1 registers */ +#define bFM3_MFS1_LIN_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_LIN_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_LIN_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_LIN_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_LIN_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_LIN_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_LIN_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_LIN_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_LIN_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_LIN_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_LIN_SCR_LBR *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_LIN_SCR_MS *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_LIN_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_LIN_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_LIN_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_LIN_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_LIN_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_LIN_SSR_LBD *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_LIN_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_LIN_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) +#define bFM3_MFS1_LIN_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) + +/* I2C channel 1 registers */ +#define bFM3_MFS1_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42702004UL)) +#define bFM3_MFS1_I2C_SMR_TIE *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_I2C_SMR_RIE *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_I2C_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_I2C_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_I2C_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_I2C_IBCR_INT *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_I2C_IBCR_BER *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_I2C_IBCR_INTE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_I2C_IBCR_ACT *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_I2C_IBCR_SCC *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_I2C_IBSR_BB *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_I2C_IBSR_SPC *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_I2C_IBSR_RSC *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_I2C_IBSR_AL *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_I2C_IBSR_TRX *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_I2C_IBSR_RSA *((volatile unsigned int*)(0x42702094UL)) +#define bFM3_MFS1_I2C_IBSR_RACK *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_I2C_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_I2C_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_I2C_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_I2C_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_I2C_SSR_TBIE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_I2C_SSR_DMA *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_I2C_SSR_TSET *((volatile unsigned int*)(0x427020B8UL)) +#define bFM3_MFS1_I2C_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42702200UL)) +#define bFM3_MFS1_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42702204UL)) +#define bFM3_MFS1_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42702208UL)) +#define bFM3_MFS1_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270220CUL)) +#define bFM3_MFS1_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42702210UL)) +#define bFM3_MFS1_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42702214UL)) +#define bFM3_MFS1_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42702218UL)) +#define bFM3_MFS1_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270221CUL)) +#define bFM3_MFS1_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42702220UL)) +#define bFM3_MFS1_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42702224UL)) +#define bFM3_MFS1_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42702228UL)) +#define bFM3_MFS1_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270222CUL)) +#define bFM3_MFS1_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42702230UL)) +#define bFM3_MFS1_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42702234UL)) +#define bFM3_MFS1_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42702238UL)) +#define bFM3_MFS1_I2C_ISMK_EN *((volatile unsigned int*)(0x4270223CUL)) + +/* UART asynchronous channel 2 registers */ +#define bFM3_MFS2_UART_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_UART_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_UART_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_UART_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_UART_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_UART_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_UART_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_UART_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_UART_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_UART_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_UART_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_UART_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_UART_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_UART_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_UART_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_UART_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_UART_ESCR_P *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_UART_ESCR_PEN *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_UART_ESCR_INV *((volatile unsigned int*)(0x42704094UL)) +#define bFM3_MFS2_UART_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_UART_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_UART_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_UART_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_UART_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_UART_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_UART_SSR_PE *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_UART_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_UART_RDR_AD *((volatile unsigned int*)(0x42704120UL)) +#define bFM3_MFS2_UART_TDR_AD *((volatile unsigned int*)(0x42704120UL)) +#define bFM3_MFS2_UART_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) +#define bFM3_MFS2_UART_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) + +/* UART synchronous channel 2 registers */ +#define bFM3_MFS2_CSIO_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42704004UL)) +#define bFM3_MFS2_CSIO_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_CSIO_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_CSIO_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_CSIO_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_CSIO_SCR_SPI *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_CSIO_SCR_MS *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_CSIO_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_CSIO_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_CSIO_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) + +/* UART LIN channel 2 registers */ +#define bFM3_MFS2_LIN_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_LIN_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_LIN_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_LIN_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_LIN_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_LIN_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_LIN_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_LIN_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_LIN_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_LIN_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_LIN_SCR_LBR *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_LIN_SCR_MS *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_LIN_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_LIN_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_LIN_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_LIN_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_LIN_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_LIN_SSR_LBD *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_LIN_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_LIN_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) +#define bFM3_MFS2_LIN_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) + +/* I2C channel 2 registers */ +#define bFM3_MFS2_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42704004UL)) +#define bFM3_MFS2_I2C_SMR_TIE *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_I2C_SMR_RIE *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_I2C_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_I2C_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_I2C_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_I2C_IBCR_INT *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_I2C_IBCR_BER *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_I2C_IBCR_INTE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_I2C_IBCR_ACT *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_I2C_IBCR_SCC *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_I2C_IBSR_BB *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_I2C_IBSR_SPC *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_I2C_IBSR_RSC *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_I2C_IBSR_AL *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_I2C_IBSR_TRX *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_I2C_IBSR_RSA *((volatile unsigned int*)(0x42704094UL)) +#define bFM3_MFS2_I2C_IBSR_RACK *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_I2C_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_I2C_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_I2C_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_I2C_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_I2C_SSR_TBIE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_I2C_SSR_DMA *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_I2C_SSR_TSET *((volatile unsigned int*)(0x427040B8UL)) +#define bFM3_MFS2_I2C_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42704200UL)) +#define bFM3_MFS2_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42704204UL)) +#define bFM3_MFS2_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42704208UL)) +#define bFM3_MFS2_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270420CUL)) +#define bFM3_MFS2_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42704210UL)) +#define bFM3_MFS2_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42704214UL)) +#define bFM3_MFS2_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42704218UL)) +#define bFM3_MFS2_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270421CUL)) +#define bFM3_MFS2_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42704220UL)) +#define bFM3_MFS2_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42704224UL)) +#define bFM3_MFS2_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42704228UL)) +#define bFM3_MFS2_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270422CUL)) +#define bFM3_MFS2_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42704230UL)) +#define bFM3_MFS2_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42704234UL)) +#define bFM3_MFS2_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42704238UL)) +#define bFM3_MFS2_I2C_ISMK_EN *((volatile unsigned int*)(0x4270423CUL)) + +/* UART asynchronous channel 3 registers */ +#define bFM3_MFS3_UART_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_UART_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_UART_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_UART_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_UART_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_UART_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_UART_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_UART_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_UART_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_UART_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_UART_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_UART_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_UART_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_UART_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_UART_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_UART_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_UART_ESCR_P *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_UART_ESCR_PEN *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_UART_ESCR_INV *((volatile unsigned int*)(0x42706094UL)) +#define bFM3_MFS3_UART_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_UART_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_UART_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_UART_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_UART_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_UART_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_UART_SSR_PE *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_UART_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_UART_RDR_AD *((volatile unsigned int*)(0x42706120UL)) +#define bFM3_MFS3_UART_TDR_AD *((volatile unsigned int*)(0x42706120UL)) +#define bFM3_MFS3_UART_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) +#define bFM3_MFS3_UART_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) + +/* UART synchronous channel 3 registers */ +#define bFM3_MFS3_CSIO_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42706004UL)) +#define bFM3_MFS3_CSIO_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_CSIO_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_CSIO_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_CSIO_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_CSIO_SCR_SPI *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_CSIO_SCR_MS *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_CSIO_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_CSIO_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_CSIO_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) + +/* UART LIN channel 3 registers */ +#define bFM3_MFS3_LIN_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_LIN_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_LIN_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_LIN_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_LIN_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_LIN_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_LIN_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_LIN_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_LIN_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_LIN_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_LIN_SCR_LBR *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_LIN_SCR_MS *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_LIN_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_LIN_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_LIN_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_LIN_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_LIN_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_LIN_SSR_LBD *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_LIN_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_LIN_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) +#define bFM3_MFS3_LIN_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) + +/* I2C channel 3 registers */ +#define bFM3_MFS3_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42706004UL)) +#define bFM3_MFS3_I2C_SMR_TIE *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_I2C_SMR_RIE *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_I2C_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_I2C_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_I2C_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_I2C_IBCR_INT *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_I2C_IBCR_BER *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_I2C_IBCR_INTE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_I2C_IBCR_ACT *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_I2C_IBCR_SCC *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_I2C_IBSR_BB *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_I2C_IBSR_SPC *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_I2C_IBSR_RSC *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_I2C_IBSR_AL *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_I2C_IBSR_TRX *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_I2C_IBSR_RSA *((volatile unsigned int*)(0x42706094UL)) +#define bFM3_MFS3_I2C_IBSR_RACK *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_I2C_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_I2C_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_I2C_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_I2C_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_I2C_SSR_TBIE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_I2C_SSR_DMA *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_I2C_SSR_TSET *((volatile unsigned int*)(0x427060B8UL)) +#define bFM3_MFS3_I2C_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42706200UL)) +#define bFM3_MFS3_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42706204UL)) +#define bFM3_MFS3_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42706208UL)) +#define bFM3_MFS3_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270620CUL)) +#define bFM3_MFS3_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42706210UL)) +#define bFM3_MFS3_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42706214UL)) +#define bFM3_MFS3_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42706218UL)) +#define bFM3_MFS3_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270621CUL)) +#define bFM3_MFS3_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42706220UL)) +#define bFM3_MFS3_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42706224UL)) +#define bFM3_MFS3_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42706228UL)) +#define bFM3_MFS3_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270622CUL)) +#define bFM3_MFS3_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42706230UL)) +#define bFM3_MFS3_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42706234UL)) +#define bFM3_MFS3_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42706238UL)) +#define bFM3_MFS3_I2C_ISMK_EN *((volatile unsigned int*)(0x4270623CUL)) + +/* UART asynchronous channel 4 registers */ +#define bFM3_MFS4_UART_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_UART_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_UART_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_UART_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_UART_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_UART_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_UART_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_UART_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_UART_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_UART_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_UART_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_UART_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_UART_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_UART_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_UART_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_UART_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_UART_ESCR_P *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_UART_ESCR_PEN *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_UART_ESCR_INV *((volatile unsigned int*)(0x42708094UL)) +#define bFM3_MFS4_UART_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_UART_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_UART_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_UART_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_UART_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_UART_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_UART_SSR_PE *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_UART_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_UART_RDR_AD *((volatile unsigned int*)(0x42708120UL)) +#define bFM3_MFS4_UART_TDR_AD *((volatile unsigned int*)(0x42708120UL)) +#define bFM3_MFS4_UART_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_UART_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_UART_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_UART_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_UART_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_UART_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_UART_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_UART_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_UART_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_UART_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_UART_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_UART_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_UART_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_UART_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_UART_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_UART_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_UART_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_UART_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_UART_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_UART_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_UART_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_UART_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_UART_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_UART_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_UART_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* UART synchronous channel 4 registers */ +#define bFM3_MFS4_CSIO_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42708004UL)) +#define bFM3_MFS4_CSIO_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_CSIO_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_CSIO_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_CSIO_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_CSIO_SCR_SPI *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_CSIO_SCR_MS *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_CSIO_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_CSIO_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_CSIO_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_CSIO_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_CSIO_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_CSIO_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_CSIO_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL)) + +/* UART LIN channel 4 registers */ +#define bFM3_MFS4_LIN_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_LIN_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_LIN_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_LIN_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_LIN_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_LIN_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_LIN_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_LIN_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_LIN_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_LIN_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_LIN_SCR_LBR *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_LIN_SCR_MS *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_LIN_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_LIN_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_LIN_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_LIN_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_LIN_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_LIN_SSR_LBD *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_LIN_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_LIN_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_LIN_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_LIN_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_LIN_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_LIN_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_LIN_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_LIN_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_LIN_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_LIN_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_LIN_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_LIN_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_LIN_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_LIN_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_LIN_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_LIN_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_LIN_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL)) +#define bFM3_MFS4_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL)) + +/* I2C channel 4 registers */ +#define bFM3_MFS4_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42708004UL)) +#define bFM3_MFS4_I2C_SMR_TIE *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_I2C_SMR_RIE *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_I2C_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_I2C_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_I2C_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_I2C_IBCR_INT *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_I2C_IBCR_BER *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_I2C_IBCR_INTE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_I2C_IBCR_ACT *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_I2C_IBCR_SCC *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_I2C_IBSR_BB *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_I2C_IBSR_SPC *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_I2C_IBSR_RSC *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_I2C_IBSR_AL *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_I2C_IBSR_TRX *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_I2C_IBSR_RSA *((volatile unsigned int*)(0x42708094UL)) +#define bFM3_MFS4_I2C_IBSR_RACK *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_I2C_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_I2C_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_I2C_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_I2C_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_I2C_SSR_TBIE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_I2C_SSR_DMA *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_I2C_SSR_TSET *((volatile unsigned int*)(0x427080B8UL)) +#define bFM3_MFS4_I2C_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42708200UL)) +#define bFM3_MFS4_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42708204UL)) +#define bFM3_MFS4_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42708208UL)) +#define bFM3_MFS4_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270820CUL)) +#define bFM3_MFS4_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42708210UL)) +#define bFM3_MFS4_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42708214UL)) +#define bFM3_MFS4_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42708218UL)) +#define bFM3_MFS4_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270821CUL)) +#define bFM3_MFS4_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42708220UL)) +#define bFM3_MFS4_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42708224UL)) +#define bFM3_MFS4_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42708228UL)) +#define bFM3_MFS4_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270822CUL)) +#define bFM3_MFS4_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42708230UL)) +#define bFM3_MFS4_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42708234UL)) +#define bFM3_MFS4_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42708238UL)) +#define bFM3_MFS4_I2C_ISMK_EN *((volatile unsigned int*)(0x4270823CUL)) +#define bFM3_MFS4_I2C_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_I2C_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_I2C_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_I2C_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_I2C_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_I2C_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_I2C_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_I2C_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_I2C_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_I2C_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_I2C_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_I2C_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_I2C_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_I2C_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL)) +#define bFM3_MFS4_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL)) + +/* UART asynchronous channel 5 registers */ +#define bFM3_MFS5_UART_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_UART_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_UART_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_UART_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_UART_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_UART_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_UART_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_UART_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_UART_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_UART_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_UART_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_UART_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_UART_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_UART_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_UART_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_UART_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_UART_ESCR_P *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_UART_ESCR_PEN *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_UART_ESCR_INV *((volatile unsigned int*)(0x4270A094UL)) +#define bFM3_MFS5_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_UART_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_UART_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_UART_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_UART_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_UART_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_UART_SSR_PE *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_UART_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_UART_RDR_AD *((volatile unsigned int*)(0x4270A120UL)) +#define bFM3_MFS5_UART_TDR_AD *((volatile unsigned int*)(0x4270A120UL)) +#define bFM3_MFS5_UART_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_UART_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_UART_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_UART_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_UART_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_UART_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_UART_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_UART_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_UART_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_UART_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_UART_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_UART_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_UART_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* UART synchronous channel 5 registers */ +#define bFM3_MFS5_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270A004UL)) +#define bFM3_MFS5_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_CSIO_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_CSIO_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL)) + +/* UART LIN channel 5 registers */ +#define bFM3_MFS5_LIN_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_LIN_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_LIN_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_LIN_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_LIN_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_LIN_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_LIN_SCR_LBR *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_LIN_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_LIN_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_LIN_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_LIN_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_LIN_SSR_LBD *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_LIN_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_LIN_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_LIN_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_LIN_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_LIN_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL)) +#define bFM3_MFS5_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL)) + +/* I2C channel 5 registers */ +#define bFM3_MFS5_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270A004UL)) +#define bFM3_MFS5_I2C_SMR_TIE *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_I2C_SMR_RIE *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_I2C_IBCR_INT *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_I2C_IBCR_BER *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_I2C_IBSR_BB *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_I2C_IBSR_AL *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270A094UL)) +#define bFM3_MFS5_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_I2C_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_I2C_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_I2C_SSR_DMA *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_I2C_SSR_TSET *((volatile unsigned int*)(0x4270A0B8UL)) +#define bFM3_MFS5_I2C_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270A200UL)) +#define bFM3_MFS5_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270A204UL)) +#define bFM3_MFS5_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270A208UL)) +#define bFM3_MFS5_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270A20CUL)) +#define bFM3_MFS5_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270A210UL)) +#define bFM3_MFS5_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270A214UL)) +#define bFM3_MFS5_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270A218UL)) +#define bFM3_MFS5_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270A21CUL)) +#define bFM3_MFS5_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270A220UL)) +#define bFM3_MFS5_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270A224UL)) +#define bFM3_MFS5_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270A228UL)) +#define bFM3_MFS5_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270A22CUL)) +#define bFM3_MFS5_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270A230UL)) +#define bFM3_MFS5_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270A234UL)) +#define bFM3_MFS5_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270A238UL)) +#define bFM3_MFS5_I2C_ISMK_EN *((volatile unsigned int*)(0x4270A23CUL)) +#define bFM3_MFS5_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_I2C_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_I2C_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_I2C_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL)) +#define bFM3_MFS5_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL)) + +/* UART asynchronous channel 6 registers */ +#define bFM3_MFS6_UART_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_UART_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_UART_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_UART_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_UART_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_UART_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_UART_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_UART_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_UART_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_UART_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_UART_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_UART_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_UART_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_UART_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_UART_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_UART_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_UART_ESCR_P *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_UART_ESCR_PEN *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_UART_ESCR_INV *((volatile unsigned int*)(0x4270C094UL)) +#define bFM3_MFS6_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_UART_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_UART_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_UART_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_UART_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_UART_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_UART_SSR_PE *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_UART_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_UART_RDR_AD *((volatile unsigned int*)(0x4270C120UL)) +#define bFM3_MFS6_UART_TDR_AD *((volatile unsigned int*)(0x4270C120UL)) +#define bFM3_MFS6_UART_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_UART_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_UART_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_UART_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_UART_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_UART_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_UART_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_UART_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_UART_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_UART_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_UART_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_UART_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_UART_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* UART synchronous channel 6 registers */ +#define bFM3_MFS6_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270C004UL)) +#define bFM3_MFS6_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_CSIO_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_CSIO_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL)) + +/* UART LIN channel 6 registers */ +#define bFM3_MFS6_LIN_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_LIN_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_LIN_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_LIN_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_LIN_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_LIN_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_LIN_SCR_LBR *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_LIN_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_LIN_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_LIN_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_LIN_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_LIN_SSR_LBD *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_LIN_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_LIN_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_LIN_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_LIN_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_LIN_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL)) +#define bFM3_MFS6_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL)) + +/* I2C channel 6 registers */ +#define bFM3_MFS6_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270C004UL)) +#define bFM3_MFS6_I2C_SMR_TIE *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_I2C_SMR_RIE *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_I2C_IBCR_INT *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_I2C_IBCR_BER *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_I2C_IBSR_BB *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_I2C_IBSR_AL *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270C094UL)) +#define bFM3_MFS6_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_I2C_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_I2C_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_I2C_SSR_DMA *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_I2C_SSR_TSET *((volatile unsigned int*)(0x4270C0B8UL)) +#define bFM3_MFS6_I2C_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270C200UL)) +#define bFM3_MFS6_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270C204UL)) +#define bFM3_MFS6_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270C208UL)) +#define bFM3_MFS6_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270C20CUL)) +#define bFM3_MFS6_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270C210UL)) +#define bFM3_MFS6_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270C214UL)) +#define bFM3_MFS6_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270C218UL)) +#define bFM3_MFS6_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270C21CUL)) +#define bFM3_MFS6_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270C220UL)) +#define bFM3_MFS6_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270C224UL)) +#define bFM3_MFS6_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270C228UL)) +#define bFM3_MFS6_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270C22CUL)) +#define bFM3_MFS6_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270C230UL)) +#define bFM3_MFS6_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270C234UL)) +#define bFM3_MFS6_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270C238UL)) +#define bFM3_MFS6_I2C_ISMK_EN *((volatile unsigned int*)(0x4270C23CUL)) +#define bFM3_MFS6_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_I2C_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_I2C_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_I2C_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL)) +#define bFM3_MFS6_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL)) + +/* UART asynchronous channel 7 registers */ +#define bFM3_MFS7_UART_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_UART_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_UART_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_UART_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_UART_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_UART_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_UART_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_UART_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_UART_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_UART_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_UART_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_UART_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_UART_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_UART_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_UART_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_UART_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_UART_ESCR_P *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_UART_ESCR_PEN *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_UART_ESCR_INV *((volatile unsigned int*)(0x4270E094UL)) +#define bFM3_MFS7_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_UART_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_UART_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_UART_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_UART_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_UART_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_UART_SSR_PE *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_UART_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_UART_RDR_AD *((volatile unsigned int*)(0x4270E120UL)) +#define bFM3_MFS7_UART_TDR_AD *((volatile unsigned int*)(0x4270E120UL)) +#define bFM3_MFS7_UART_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_UART_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_UART_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_UART_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_UART_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_UART_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_UART_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_UART_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_UART_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_UART_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_UART_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_UART_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_UART_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* UART synchronous channel 7 registers */ +#define bFM3_MFS7_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270E004UL)) +#define bFM3_MFS7_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_CSIO_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_CSIO_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL)) + +/* UART LIN channel 7 registers */ +#define bFM3_MFS7_LIN_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_LIN_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_LIN_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_LIN_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_LIN_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_LIN_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_LIN_SCR_LBR *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_LIN_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_LIN_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_LIN_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_LIN_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_LIN_SSR_LBD *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_LIN_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_LIN_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_LIN_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_LIN_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_LIN_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL)) +#define bFM3_MFS7_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL)) + +/* I2C channel 7 registers */ +#define bFM3_MFS7_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270E004UL)) +#define bFM3_MFS7_I2C_SMR_TIE *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_I2C_SMR_RIE *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_I2C_IBCR_INT *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_I2C_IBCR_BER *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_I2C_IBSR_BB *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_I2C_IBSR_AL *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270E094UL)) +#define bFM3_MFS7_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_I2C_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_I2C_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_I2C_SSR_DMA *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_I2C_SSR_TSET *((volatile unsigned int*)(0x4270E0B8UL)) +#define bFM3_MFS7_I2C_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270E200UL)) +#define bFM3_MFS7_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270E204UL)) +#define bFM3_MFS7_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270E208UL)) +#define bFM3_MFS7_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270E20CUL)) +#define bFM3_MFS7_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270E210UL)) +#define bFM3_MFS7_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270E214UL)) +#define bFM3_MFS7_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270E218UL)) +#define bFM3_MFS7_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270E21CUL)) +#define bFM3_MFS7_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270E220UL)) +#define bFM3_MFS7_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270E224UL)) +#define bFM3_MFS7_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270E228UL)) +#define bFM3_MFS7_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270E22CUL)) +#define bFM3_MFS7_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270E230UL)) +#define bFM3_MFS7_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270E234UL)) +#define bFM3_MFS7_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270E238UL)) +#define bFM3_MFS7_I2C_ISMK_EN *((volatile unsigned int*)(0x4270E23CUL)) +#define bFM3_MFS7_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_I2C_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_I2C_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_I2C_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL)) +#define bFM3_MFS7_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL)) + +/* CRC registers */ +#define bFM3_CRC_CRCCR_INIT *((volatile unsigned int*)(0x42720000UL)) +#define bFM3_CRC_CRCCR_CRC32 *((volatile unsigned int*)(0x42720004UL)) +#define bFM3_CRC_CRCCR_LTLEND *((volatile unsigned int*)(0x42720008UL)) +#define bFM3_CRC_CRCCR_LSBFST *((volatile unsigned int*)(0x4272000CUL)) +#define bFM3_CRC_CRCCR_CRCLTE *((volatile unsigned int*)(0x42720010UL)) +#define bFM3_CRC_CRCCR_CRCLSF *((volatile unsigned int*)(0x42720014UL)) +#define bFM3_CRC_CRCCR_FXOR *((volatile unsigned int*)(0x42720018UL)) + +/* Watch counter registers */ +#define bFM3_WC_WCRD_CTR0 *((volatile unsigned int*)(0x42740000UL)) +#define bFM3_WC_WCRD_CTR1 *((volatile unsigned int*)(0x42740004UL)) +#define bFM3_WC_WCRD_CTR2 *((volatile unsigned int*)(0x42740008UL)) +#define bFM3_WC_WCRD_CTR3 *((volatile unsigned int*)(0x4274000CUL)) +#define bFM3_WC_WCRD_CTR4 *((volatile unsigned int*)(0x42740010UL)) +#define bFM3_WC_WCRD_CTR5 *((volatile unsigned int*)(0x42740014UL)) +#define bFM3_WC_WCRL_RLC0 *((volatile unsigned int*)(0x42740020UL)) +#define bFM3_WC_WCRL_RLC1 *((volatile unsigned int*)(0x42740024UL)) +#define bFM3_WC_WCRL_RLC2 *((volatile unsigned int*)(0x42740028UL)) +#define bFM3_WC_WCRL_RLC3 *((volatile unsigned int*)(0x4274002CUL)) +#define bFM3_WC_WCRL_RLC4 *((volatile unsigned int*)(0x42740030UL)) +#define bFM3_WC_WCRL_RLC5 *((volatile unsigned int*)(0x42740034UL)) +#define bFM3_WC_WCCR_WCIF *((volatile unsigned int*)(0x42740040UL)) +#define bFM3_WC_WCCR_WCIE *((volatile unsigned int*)(0x42740044UL)) +#define bFM3_WC_WCCR_CS0 *((volatile unsigned int*)(0x42740048UL)) +#define bFM3_WC_WCCR_CS1 *((volatile unsigned int*)(0x4274004CUL)) +#define bFM3_WC_WCCR_WCOP *((volatile unsigned int*)(0x42740058UL)) +#define bFM3_WC_WCCR_WCEN *((volatile unsigned int*)(0x4274005CUL)) +#define bFM3_WC_CLK_SEL_SEL_IN *((volatile unsigned int*)(0x42740200UL)) +#define bFM3_WC_CLK_SEL_SEL_OUT *((volatile unsigned int*)(0x42740220UL)) +#define bFM3_WC_CLK_EN_CLK_EN *((volatile unsigned int*)(0x42740280UL)) +#define bFM3_WC_CLK_EN_CLK_EN_R *((volatile unsigned int*)(0x42740284UL)) + +/* External bus interface registers */ +#define bFM3_EXBUS_MODE0_WDTH0 *((volatile unsigned int*)(0x427E0000UL)) +#define bFM3_EXBUS_MODE0_WDTH1 *((volatile unsigned int*)(0x427E0004UL)) +#define bFM3_EXBUS_MODE0_RBMON *((volatile unsigned int*)(0x427E0008UL)) +#define bFM3_EXBUS_MODE0_WEOFF *((volatile unsigned int*)(0x427E000CUL)) +#define bFM3_EXBUS_MODE0_NAND *((volatile unsigned int*)(0x427E0010UL)) +#define bFM3_EXBUS_MODE0_PAGE *((volatile unsigned int*)(0x427E0014UL)) +#define bFM3_EXBUS_MODE0_TEST *((volatile unsigned int*)(0x427E0018UL)) +#define bFM3_EXBUS_MODE1_WDTH0 *((volatile unsigned int*)(0x427E0080UL)) +#define bFM3_EXBUS_MODE1_WDTH1 *((volatile unsigned int*)(0x427E0084UL)) +#define bFM3_EXBUS_MODE1_RBMON *((volatile unsigned int*)(0x427E0088UL)) +#define bFM3_EXBUS_MODE1_WEOFF *((volatile unsigned int*)(0x427E008CUL)) +#define bFM3_EXBUS_MODE1_NAND *((volatile unsigned int*)(0x427E0090UL)) +#define bFM3_EXBUS_MODE1_PAGE *((volatile unsigned int*)(0x427E0094UL)) +#define bFM3_EXBUS_MODE1_TEST *((volatile unsigned int*)(0x427E0098UL)) +#define bFM3_EXBUS_MODE2_WDTH0 *((volatile unsigned int*)(0x427E0100UL)) +#define bFM3_EXBUS_MODE2_WDTH1 *((volatile unsigned int*)(0x427E0104UL)) +#define bFM3_EXBUS_MODE2_RBMON *((volatile unsigned int*)(0x427E0108UL)) +#define bFM3_EXBUS_MODE2_WEOFF *((volatile unsigned int*)(0x427E010CUL)) +#define bFM3_EXBUS_MODE2_NAND *((volatile unsigned int*)(0x427E0110UL)) +#define bFM3_EXBUS_MODE2_PAGE *((volatile unsigned int*)(0x427E0114UL)) +#define bFM3_EXBUS_MODE2_TEST *((volatile unsigned int*)(0x427E0118UL)) +#define bFM3_EXBUS_MODE3_WDTH0 *((volatile unsigned int*)(0x427E0180UL)) +#define bFM3_EXBUS_MODE3_WDTH1 *((volatile unsigned int*)(0x427E0184UL)) +#define bFM3_EXBUS_MODE3_RBMON *((volatile unsigned int*)(0x427E0188UL)) +#define bFM3_EXBUS_MODE3_WEOFF *((volatile unsigned int*)(0x427E018CUL)) +#define bFM3_EXBUS_MODE3_NAND *((volatile unsigned int*)(0x427E0190UL)) +#define bFM3_EXBUS_MODE3_PAGE *((volatile unsigned int*)(0x427E0194UL)) +#define bFM3_EXBUS_MODE3_TEST *((volatile unsigned int*)(0x427E0198UL)) +#define bFM3_EXBUS_MODE4_WDTH0 *((volatile unsigned int*)(0x427E0200UL)) +#define bFM3_EXBUS_MODE4_WDTH1 *((volatile unsigned int*)(0x427E0204UL)) +#define bFM3_EXBUS_MODE4_RBMON *((volatile unsigned int*)(0x427E0208UL)) +#define bFM3_EXBUS_MODE4_WEOFF *((volatile unsigned int*)(0x427E020CUL)) +#define bFM3_EXBUS_MODE4_NAND *((volatile unsigned int*)(0x427E0210UL)) +#define bFM3_EXBUS_MODE4_PAGE *((volatile unsigned int*)(0x427E0214UL)) +#define bFM3_EXBUS_MODE4_TEST *((volatile unsigned int*)(0x427E0218UL)) +#define bFM3_EXBUS_MODE5_WDTH0 *((volatile unsigned int*)(0x427E0280UL)) +#define bFM3_EXBUS_MODE5_WDTH1 *((volatile unsigned int*)(0x427E0284UL)) +#define bFM3_EXBUS_MODE5_RBMON *((volatile unsigned int*)(0x427E0288UL)) +#define bFM3_EXBUS_MODE5_WEOFF *((volatile unsigned int*)(0x427E028CUL)) +#define bFM3_EXBUS_MODE5_NAND *((volatile unsigned int*)(0x427E0290UL)) +#define bFM3_EXBUS_MODE5_PAGE *((volatile unsigned int*)(0x427E0294UL)) +#define bFM3_EXBUS_MODE5_TEST *((volatile unsigned int*)(0x427E0298UL)) +#define bFM3_EXBUS_MODE6_WDTH0 *((volatile unsigned int*)(0x427E0300UL)) +#define bFM3_EXBUS_MODE6_WDTH1 *((volatile unsigned int*)(0x427E0304UL)) +#define bFM3_EXBUS_MODE6_RBMON *((volatile unsigned int*)(0x427E0308UL)) +#define bFM3_EXBUS_MODE6_WEOFF *((volatile unsigned int*)(0x427E030CUL)) +#define bFM3_EXBUS_MODE6_NAND *((volatile unsigned int*)(0x427E0310UL)) +#define bFM3_EXBUS_MODE6_PAGE *((volatile unsigned int*)(0x427E0314UL)) +#define bFM3_EXBUS_MODE6_TEST *((volatile unsigned int*)(0x427E0318UL)) +#define bFM3_EXBUS_MODE7_WDTH0 *((volatile unsigned int*)(0x427E0380UL)) +#define bFM3_EXBUS_MODE7_WDTH1 *((volatile unsigned int*)(0x427E0384UL)) +#define bFM3_EXBUS_MODE7_RBMON *((volatile unsigned int*)(0x427E0388UL)) +#define bFM3_EXBUS_MODE7_WEOFF *((volatile unsigned int*)(0x427E038CUL)) +#define bFM3_EXBUS_MODE7_NAND *((volatile unsigned int*)(0x427E0390UL)) +#define bFM3_EXBUS_MODE7_PAGE *((volatile unsigned int*)(0x427E0394UL)) +#define bFM3_EXBUS_MODE7_TEST *((volatile unsigned int*)(0x427E0398UL)) +#define bFM3_EXBUS_TIM0_RACC0 *((volatile unsigned int*)(0x427E0400UL)) +#define bFM3_EXBUS_TIM0_RACC1 *((volatile unsigned int*)(0x427E0404UL)) +#define bFM3_EXBUS_TIM0_RACC2 *((volatile unsigned int*)(0x427E0408UL)) +#define bFM3_EXBUS_TIM0_RACC3 *((volatile unsigned int*)(0x427E040CUL)) +#define bFM3_EXBUS_TIM0_RADC0 *((volatile unsigned int*)(0x427E0410UL)) +#define bFM3_EXBUS_TIM0_RADC1 *((volatile unsigned int*)(0x427E0414UL)) +#define bFM3_EXBUS_TIM0_RADC2 *((volatile unsigned int*)(0x427E0418UL)) +#define bFM3_EXBUS_TIM0_RADC3 *((volatile unsigned int*)(0x427E041CUL)) +#define bFM3_EXBUS_TIM0_FRADC0 *((volatile unsigned int*)(0x427E0420UL)) +#define bFM3_EXBUS_TIM0_FRADC1 *((volatile unsigned int*)(0x427E0424UL)) +#define bFM3_EXBUS_TIM0_FRADC2 *((volatile unsigned int*)(0x427E0428UL)) +#define bFM3_EXBUS_TIM0_FRADC3 *((volatile unsigned int*)(0x427E042CUL)) +#define bFM3_EXBUS_TIM0_RIDLC0 *((volatile unsigned int*)(0x427E0430UL)) +#define bFM3_EXBUS_TIM0_RIDLC1 *((volatile unsigned int*)(0x427E0434UL)) +#define bFM3_EXBUS_TIM0_RIDLC2 *((volatile unsigned int*)(0x427E0438UL)) +#define bFM3_EXBUS_TIM0_RIDLC3 *((volatile unsigned int*)(0x427E043CUL)) +#define bFM3_EXBUS_TIM0_WACC0 *((volatile unsigned int*)(0x427E0440UL)) +#define bFM3_EXBUS_TIM0_WACC1 *((volatile unsigned int*)(0x427E0444UL)) +#define bFM3_EXBUS_TIM0_WACC2 *((volatile unsigned int*)(0x427E0448UL)) +#define bFM3_EXBUS_TIM0_WACC3 *((volatile unsigned int*)(0x427E044CUL)) +#define bFM3_EXBUS_TIM0_WADC0 *((volatile unsigned int*)(0x427E0450UL)) +#define bFM3_EXBUS_TIM0_WADC1 *((volatile unsigned int*)(0x427E0454UL)) +#define bFM3_EXBUS_TIM0_WADC2 *((volatile unsigned int*)(0x427E0458UL)) +#define bFM3_EXBUS_TIM0_WADC3 *((volatile unsigned int*)(0x427E045CUL)) +#define bFM3_EXBUS_TIM0_WWEC0 *((volatile unsigned int*)(0x427E0460UL)) +#define bFM3_EXBUS_TIM0_WWEC1 *((volatile unsigned int*)(0x427E0464UL)) +#define bFM3_EXBUS_TIM0_WWEC2 *((volatile unsigned int*)(0x427E0468UL)) +#define bFM3_EXBUS_TIM0_WWEC3 *((volatile unsigned int*)(0x427E046CUL)) +#define bFM3_EXBUS_TIM0_WIDLC0 *((volatile unsigned int*)(0x427E0470UL)) +#define bFM3_EXBUS_TIM0_WIDLC1 *((volatile unsigned int*)(0x427E0474UL)) +#define bFM3_EXBUS_TIM0_WIDLC2 *((volatile unsigned int*)(0x427E0478UL)) +#define bFM3_EXBUS_TIM0_WIDLC3 *((volatile unsigned int*)(0x427E047CUL)) +#define bFM3_EXBUS_TIM1_RACC0 *((volatile unsigned int*)(0x427E0480UL)) +#define bFM3_EXBUS_TIM1_RACC1 *((volatile unsigned int*)(0x427E0484UL)) +#define bFM3_EXBUS_TIM1_RACC2 *((volatile unsigned int*)(0x427E0488UL)) +#define bFM3_EXBUS_TIM1_RACC3 *((volatile unsigned int*)(0x427E048CUL)) +#define bFM3_EXBUS_TIM1_RADC0 *((volatile unsigned int*)(0x427E0490UL)) +#define bFM3_EXBUS_TIM1_RADC1 *((volatile unsigned int*)(0x427E0494UL)) +#define bFM3_EXBUS_TIM1_RADC2 *((volatile unsigned int*)(0x427E0498UL)) +#define bFM3_EXBUS_TIM1_RADC3 *((volatile unsigned int*)(0x427E049CUL)) +#define bFM3_EXBUS_TIM1_FRADC0 *((volatile unsigned int*)(0x427E04A0UL)) +#define bFM3_EXBUS_TIM1_FRADC1 *((volatile unsigned int*)(0x427E04A4UL)) +#define bFM3_EXBUS_TIM1_FRADC2 *((volatile unsigned int*)(0x427E04A8UL)) +#define bFM3_EXBUS_TIM1_FRADC3 *((volatile unsigned int*)(0x427E04ACUL)) +#define bFM3_EXBUS_TIM1_RIDLC0 *((volatile unsigned int*)(0x427E04B0UL)) +#define bFM3_EXBUS_TIM1_RIDLC1 *((volatile unsigned int*)(0x427E04B4UL)) +#define bFM3_EXBUS_TIM1_RIDLC2 *((volatile unsigned int*)(0x427E04B8UL)) +#define bFM3_EXBUS_TIM1_RIDLC3 *((volatile unsigned int*)(0x427E04BCUL)) +#define bFM3_EXBUS_TIM1_WACC0 *((volatile unsigned int*)(0x427E04C0UL)) +#define bFM3_EXBUS_TIM1_WACC1 *((volatile unsigned int*)(0x427E04C4UL)) +#define bFM3_EXBUS_TIM1_WACC2 *((volatile unsigned int*)(0x427E04C8UL)) +#define bFM3_EXBUS_TIM1_WACC3 *((volatile unsigned int*)(0x427E04CCUL)) +#define bFM3_EXBUS_TIM1_WADC0 *((volatile unsigned int*)(0x427E04D0UL)) +#define bFM3_EXBUS_TIM1_WADC1 *((volatile unsigned int*)(0x427E04D4UL)) +#define bFM3_EXBUS_TIM1_WADC2 *((volatile unsigned int*)(0x427E04D8UL)) +#define bFM3_EXBUS_TIM1_WADC3 *((volatile unsigned int*)(0x427E04DCUL)) +#define bFM3_EXBUS_TIM1_WWEC0 *((volatile unsigned int*)(0x427E04E0UL)) +#define bFM3_EXBUS_TIM1_WWEC1 *((volatile unsigned int*)(0x427E04E4UL)) +#define bFM3_EXBUS_TIM1_WWEC2 *((volatile unsigned int*)(0x427E04E8UL)) +#define bFM3_EXBUS_TIM1_WWEC3 *((volatile unsigned int*)(0x427E04ECUL)) +#define bFM3_EXBUS_TIM1_WIDLC0 *((volatile unsigned int*)(0x427E04F0UL)) +#define bFM3_EXBUS_TIM1_WIDLC1 *((volatile unsigned int*)(0x427E04F4UL)) +#define bFM3_EXBUS_TIM1_WIDLC2 *((volatile unsigned int*)(0x427E04F8UL)) +#define bFM3_EXBUS_TIM1_WIDLC3 *((volatile unsigned int*)(0x427E04FCUL)) +#define bFM3_EXBUS_TIM2_RACC0 *((volatile unsigned int*)(0x427E0500UL)) +#define bFM3_EXBUS_TIM2_RACC1 *((volatile unsigned int*)(0x427E0504UL)) +#define bFM3_EXBUS_TIM2_RACC2 *((volatile unsigned int*)(0x427E0508UL)) +#define bFM3_EXBUS_TIM2_RACC3 *((volatile unsigned int*)(0x427E050CUL)) +#define bFM3_EXBUS_TIM2_RADC0 *((volatile unsigned int*)(0x427E0510UL)) +#define bFM3_EXBUS_TIM2_RADC1 *((volatile unsigned int*)(0x427E0514UL)) +#define bFM3_EXBUS_TIM2_RADC2 *((volatile unsigned int*)(0x427E0518UL)) +#define bFM3_EXBUS_TIM2_RADC3 *((volatile unsigned int*)(0x427E051CUL)) +#define bFM3_EXBUS_TIM2_FRADC0 *((volatile unsigned int*)(0x427E0520UL)) +#define bFM3_EXBUS_TIM2_FRADC1 *((volatile unsigned int*)(0x427E0524UL)) +#define bFM3_EXBUS_TIM2_FRADC2 *((volatile unsigned int*)(0x427E0528UL)) +#define bFM3_EXBUS_TIM2_FRADC3 *((volatile unsigned int*)(0x427E052CUL)) +#define bFM3_EXBUS_TIM2_RIDLC0 *((volatile unsigned int*)(0x427E0530UL)) +#define bFM3_EXBUS_TIM2_RIDLC1 *((volatile unsigned int*)(0x427E0534UL)) +#define bFM3_EXBUS_TIM2_RIDLC2 *((volatile unsigned int*)(0x427E0538UL)) +#define bFM3_EXBUS_TIM2_RIDLC3 *((volatile unsigned int*)(0x427E053CUL)) +#define bFM3_EXBUS_TIM2_WACC0 *((volatile unsigned int*)(0x427E0540UL)) +#define bFM3_EXBUS_TIM2_WACC1 *((volatile unsigned int*)(0x427E0544UL)) +#define bFM3_EXBUS_TIM2_WACC2 *((volatile unsigned int*)(0x427E0548UL)) +#define bFM3_EXBUS_TIM2_WACC3 *((volatile unsigned int*)(0x427E054CUL)) +#define bFM3_EXBUS_TIM2_WADC0 *((volatile unsigned int*)(0x427E0550UL)) +#define bFM3_EXBUS_TIM2_WADC1 *((volatile unsigned int*)(0x427E0554UL)) +#define bFM3_EXBUS_TIM2_WADC2 *((volatile unsigned int*)(0x427E0558UL)) +#define bFM3_EXBUS_TIM2_WADC3 *((volatile unsigned int*)(0x427E055CUL)) +#define bFM3_EXBUS_TIM2_WWEC0 *((volatile unsigned int*)(0x427E0560UL)) +#define bFM3_EXBUS_TIM2_WWEC1 *((volatile unsigned int*)(0x427E0564UL)) +#define bFM3_EXBUS_TIM2_WWEC2 *((volatile unsigned int*)(0x427E0568UL)) +#define bFM3_EXBUS_TIM2_WWEC3 *((volatile unsigned int*)(0x427E056CUL)) +#define bFM3_EXBUS_TIM2_WIDLC0 *((volatile unsigned int*)(0x427E0570UL)) +#define bFM3_EXBUS_TIM2_WIDLC1 *((volatile unsigned int*)(0x427E0574UL)) +#define bFM3_EXBUS_TIM2_WIDLC2 *((volatile unsigned int*)(0x427E0578UL)) +#define bFM3_EXBUS_TIM2_WIDLC3 *((volatile unsigned int*)(0x427E057CUL)) +#define bFM3_EXBUS_TIM3_RACC0 *((volatile unsigned int*)(0x427E0580UL)) +#define bFM3_EXBUS_TIM3_RACC1 *((volatile unsigned int*)(0x427E0584UL)) +#define bFM3_EXBUS_TIM3_RACC2 *((volatile unsigned int*)(0x427E0588UL)) +#define bFM3_EXBUS_TIM3_RACC3 *((volatile unsigned int*)(0x427E058CUL)) +#define bFM3_EXBUS_TIM3_RADC0 *((volatile unsigned int*)(0x427E0590UL)) +#define bFM3_EXBUS_TIM3_RADC1 *((volatile unsigned int*)(0x427E0594UL)) +#define bFM3_EXBUS_TIM3_RADC2 *((volatile unsigned int*)(0x427E0598UL)) +#define bFM3_EXBUS_TIM3_RADC3 *((volatile unsigned int*)(0x427E059CUL)) +#define bFM3_EXBUS_TIM3_FRADC0 *((volatile unsigned int*)(0x427E05A0UL)) +#define bFM3_EXBUS_TIM3_FRADC1 *((volatile unsigned int*)(0x427E05A4UL)) +#define bFM3_EXBUS_TIM3_FRADC2 *((volatile unsigned int*)(0x427E05A8UL)) +#define bFM3_EXBUS_TIM3_FRADC3 *((volatile unsigned int*)(0x427E05ACUL)) +#define bFM3_EXBUS_TIM3_RIDLC0 *((volatile unsigned int*)(0x427E05B0UL)) +#define bFM3_EXBUS_TIM3_RIDLC1 *((volatile unsigned int*)(0x427E05B4UL)) +#define bFM3_EXBUS_TIM3_RIDLC2 *((volatile unsigned int*)(0x427E05B8UL)) +#define bFM3_EXBUS_TIM3_RIDLC3 *((volatile unsigned int*)(0x427E05BCUL)) +#define bFM3_EXBUS_TIM3_WACC0 *((volatile unsigned int*)(0x427E05C0UL)) +#define bFM3_EXBUS_TIM3_WACC1 *((volatile unsigned int*)(0x427E05C4UL)) +#define bFM3_EXBUS_TIM3_WACC2 *((volatile unsigned int*)(0x427E05C8UL)) +#define bFM3_EXBUS_TIM3_WACC3 *((volatile unsigned int*)(0x427E05CCUL)) +#define bFM3_EXBUS_TIM3_WADC0 *((volatile unsigned int*)(0x427E05D0UL)) +#define bFM3_EXBUS_TIM3_WADC1 *((volatile unsigned int*)(0x427E05D4UL)) +#define bFM3_EXBUS_TIM3_WADC2 *((volatile unsigned int*)(0x427E05D8UL)) +#define bFM3_EXBUS_TIM3_WADC3 *((volatile unsigned int*)(0x427E05DCUL)) +#define bFM3_EXBUS_TIM3_WWEC0 *((volatile unsigned int*)(0x427E05E0UL)) +#define bFM3_EXBUS_TIM3_WWEC1 *((volatile unsigned int*)(0x427E05E4UL)) +#define bFM3_EXBUS_TIM3_WWEC2 *((volatile unsigned int*)(0x427E05E8UL)) +#define bFM3_EXBUS_TIM3_WWEC3 *((volatile unsigned int*)(0x427E05ECUL)) +#define bFM3_EXBUS_TIM3_WIDLC0 *((volatile unsigned int*)(0x427E05F0UL)) +#define bFM3_EXBUS_TIM3_WIDLC1 *((volatile unsigned int*)(0x427E05F4UL)) +#define bFM3_EXBUS_TIM3_WIDLC2 *((volatile unsigned int*)(0x427E05F8UL)) +#define bFM3_EXBUS_TIM3_WIDLC3 *((volatile unsigned int*)(0x427E05FCUL)) +#define bFM3_EXBUS_TIM4_RACC0 *((volatile unsigned int*)(0x427E0600UL)) +#define bFM3_EXBUS_TIM4_RACC1 *((volatile unsigned int*)(0x427E0604UL)) +#define bFM3_EXBUS_TIM4_RACC2 *((volatile unsigned int*)(0x427E0608UL)) +#define bFM3_EXBUS_TIM4_RACC3 *((volatile unsigned int*)(0x427E060CUL)) +#define bFM3_EXBUS_TIM4_RADC0 *((volatile unsigned int*)(0x427E0610UL)) +#define bFM3_EXBUS_TIM4_RADC1 *((volatile unsigned int*)(0x427E0614UL)) +#define bFM3_EXBUS_TIM4_RADC2 *((volatile unsigned int*)(0x427E0618UL)) +#define bFM3_EXBUS_TIM4_RADC3 *((volatile unsigned int*)(0x427E061CUL)) +#define bFM3_EXBUS_TIM4_FRADC0 *((volatile unsigned int*)(0x427E0620UL)) +#define bFM3_EXBUS_TIM4_FRADC1 *((volatile unsigned int*)(0x427E0624UL)) +#define bFM3_EXBUS_TIM4_FRADC2 *((volatile unsigned int*)(0x427E0628UL)) +#define bFM3_EXBUS_TIM4_FRADC3 *((volatile unsigned int*)(0x427E062CUL)) +#define bFM3_EXBUS_TIM4_RIDLC0 *((volatile unsigned int*)(0x427E0630UL)) +#define bFM3_EXBUS_TIM4_RIDLC1 *((volatile unsigned int*)(0x427E0634UL)) +#define bFM3_EXBUS_TIM4_RIDLC2 *((volatile unsigned int*)(0x427E0638UL)) +#define bFM3_EXBUS_TIM4_RIDLC3 *((volatile unsigned int*)(0x427E063CUL)) +#define bFM3_EXBUS_TIM4_WACC0 *((volatile unsigned int*)(0x427E0640UL)) +#define bFM3_EXBUS_TIM4_WACC1 *((volatile unsigned int*)(0x427E0644UL)) +#define bFM3_EXBUS_TIM4_WACC2 *((volatile unsigned int*)(0x427E0648UL)) +#define bFM3_EXBUS_TIM4_WACC3 *((volatile unsigned int*)(0x427E064CUL)) +#define bFM3_EXBUS_TIM4_WADC0 *((volatile unsigned int*)(0x427E0650UL)) +#define bFM3_EXBUS_TIM4_WADC1 *((volatile unsigned int*)(0x427E0654UL)) +#define bFM3_EXBUS_TIM4_WADC2 *((volatile unsigned int*)(0x427E0658UL)) +#define bFM3_EXBUS_TIM4_WADC3 *((volatile unsigned int*)(0x427E065CUL)) +#define bFM3_EXBUS_TIM4_WWEC0 *((volatile unsigned int*)(0x427E0660UL)) +#define bFM3_EXBUS_TIM4_WWEC1 *((volatile unsigned int*)(0x427E0664UL)) +#define bFM3_EXBUS_TIM4_WWEC2 *((volatile unsigned int*)(0x427E0668UL)) +#define bFM3_EXBUS_TIM4_WWEC3 *((volatile unsigned int*)(0x427E066CUL)) +#define bFM3_EXBUS_TIM4_WIDLC0 *((volatile unsigned int*)(0x427E0670UL)) +#define bFM3_EXBUS_TIM4_WIDLC1 *((volatile unsigned int*)(0x427E0674UL)) +#define bFM3_EXBUS_TIM4_WIDLC2 *((volatile unsigned int*)(0x427E0678UL)) +#define bFM3_EXBUS_TIM4_WIDLC3 *((volatile unsigned int*)(0x427E067CUL)) +#define bFM3_EXBUS_TIM5_RACC0 *((volatile unsigned int*)(0x427E0680UL)) +#define bFM3_EXBUS_TIM5_RACC1 *((volatile unsigned int*)(0x427E0684UL)) +#define bFM3_EXBUS_TIM5_RACC2 *((volatile unsigned int*)(0x427E0688UL)) +#define bFM3_EXBUS_TIM5_RACC3 *((volatile unsigned int*)(0x427E068CUL)) +#define bFM3_EXBUS_TIM5_RADC0 *((volatile unsigned int*)(0x427E0690UL)) +#define bFM3_EXBUS_TIM5_RADC1 *((volatile unsigned int*)(0x427E0694UL)) +#define bFM3_EXBUS_TIM5_RADC2 *((volatile unsigned int*)(0x427E0698UL)) +#define bFM3_EXBUS_TIM5_RADC3 *((volatile unsigned int*)(0x427E069CUL)) +#define bFM3_EXBUS_TIM5_FRADC0 *((volatile unsigned int*)(0x427E06A0UL)) +#define bFM3_EXBUS_TIM5_FRADC1 *((volatile unsigned int*)(0x427E06A4UL)) +#define bFM3_EXBUS_TIM5_FRADC2 *((volatile unsigned int*)(0x427E06A8UL)) +#define bFM3_EXBUS_TIM5_FRADC3 *((volatile unsigned int*)(0x427E06ACUL)) +#define bFM3_EXBUS_TIM5_RIDLC0 *((volatile unsigned int*)(0x427E06B0UL)) +#define bFM3_EXBUS_TIM5_RIDLC1 *((volatile unsigned int*)(0x427E06B4UL)) +#define bFM3_EXBUS_TIM5_RIDLC2 *((volatile unsigned int*)(0x427E06B8UL)) +#define bFM3_EXBUS_TIM5_RIDLC3 *((volatile unsigned int*)(0x427E06BCUL)) +#define bFM3_EXBUS_TIM5_WACC0 *((volatile unsigned int*)(0x427E06C0UL)) +#define bFM3_EXBUS_TIM5_WACC1 *((volatile unsigned int*)(0x427E06C4UL)) +#define bFM3_EXBUS_TIM5_WACC2 *((volatile unsigned int*)(0x427E06C8UL)) +#define bFM3_EXBUS_TIM5_WACC3 *((volatile unsigned int*)(0x427E06CCUL)) +#define bFM3_EXBUS_TIM5_WADC0 *((volatile unsigned int*)(0x427E06D0UL)) +#define bFM3_EXBUS_TIM5_WADC1 *((volatile unsigned int*)(0x427E06D4UL)) +#define bFM3_EXBUS_TIM5_WADC2 *((volatile unsigned int*)(0x427E06D8UL)) +#define bFM3_EXBUS_TIM5_WADC3 *((volatile unsigned int*)(0x427E06DCUL)) +#define bFM3_EXBUS_TIM5_WWEC0 *((volatile unsigned int*)(0x427E06E0UL)) +#define bFM3_EXBUS_TIM5_WWEC1 *((volatile unsigned int*)(0x427E06E4UL)) +#define bFM3_EXBUS_TIM5_WWEC2 *((volatile unsigned int*)(0x427E06E8UL)) +#define bFM3_EXBUS_TIM5_WWEC3 *((volatile unsigned int*)(0x427E06ECUL)) +#define bFM3_EXBUS_TIM5_WIDLC0 *((volatile unsigned int*)(0x427E06F0UL)) +#define bFM3_EXBUS_TIM5_WIDLC1 *((volatile unsigned int*)(0x427E06F4UL)) +#define bFM3_EXBUS_TIM5_WIDLC2 *((volatile unsigned int*)(0x427E06F8UL)) +#define bFM3_EXBUS_TIM5_WIDLC3 *((volatile unsigned int*)(0x427E06FCUL)) +#define bFM3_EXBUS_TIM6_RACC0 *((volatile unsigned int*)(0x427E0700UL)) +#define bFM3_EXBUS_TIM6_RACC1 *((volatile unsigned int*)(0x427E0704UL)) +#define bFM3_EXBUS_TIM6_RACC2 *((volatile unsigned int*)(0x427E0708UL)) +#define bFM3_EXBUS_TIM6_RACC3 *((volatile unsigned int*)(0x427E070CUL)) +#define bFM3_EXBUS_TIM6_RADC0 *((volatile unsigned int*)(0x427E0710UL)) +#define bFM3_EXBUS_TIM6_RADC1 *((volatile unsigned int*)(0x427E0714UL)) +#define bFM3_EXBUS_TIM6_RADC2 *((volatile unsigned int*)(0x427E0718UL)) +#define bFM3_EXBUS_TIM6_RADC3 *((volatile unsigned int*)(0x427E071CUL)) +#define bFM3_EXBUS_TIM6_FRADC0 *((volatile unsigned int*)(0x427E0720UL)) +#define bFM3_EXBUS_TIM6_FRADC1 *((volatile unsigned int*)(0x427E0724UL)) +#define bFM3_EXBUS_TIM6_FRADC2 *((volatile unsigned int*)(0x427E0728UL)) +#define bFM3_EXBUS_TIM6_FRADC3 *((volatile unsigned int*)(0x427E072CUL)) +#define bFM3_EXBUS_TIM6_RIDLC0 *((volatile unsigned int*)(0x427E0730UL)) +#define bFM3_EXBUS_TIM6_RIDLC1 *((volatile unsigned int*)(0x427E0734UL)) +#define bFM3_EXBUS_TIM6_RIDLC2 *((volatile unsigned int*)(0x427E0738UL)) +#define bFM3_EXBUS_TIM6_RIDLC3 *((volatile unsigned int*)(0x427E073CUL)) +#define bFM3_EXBUS_TIM6_WACC0 *((volatile unsigned int*)(0x427E0740UL)) +#define bFM3_EXBUS_TIM6_WACC1 *((volatile unsigned int*)(0x427E0744UL)) +#define bFM3_EXBUS_TIM6_WACC2 *((volatile unsigned int*)(0x427E0748UL)) +#define bFM3_EXBUS_TIM6_WACC3 *((volatile unsigned int*)(0x427E074CUL)) +#define bFM3_EXBUS_TIM6_WADC0 *((volatile unsigned int*)(0x427E0750UL)) +#define bFM3_EXBUS_TIM6_WADC1 *((volatile unsigned int*)(0x427E0754UL)) +#define bFM3_EXBUS_TIM6_WADC2 *((volatile unsigned int*)(0x427E0758UL)) +#define bFM3_EXBUS_TIM6_WADC3 *((volatile unsigned int*)(0x427E075CUL)) +#define bFM3_EXBUS_TIM6_WWEC0 *((volatile unsigned int*)(0x427E0760UL)) +#define bFM3_EXBUS_TIM6_WWEC1 *((volatile unsigned int*)(0x427E0764UL)) +#define bFM3_EXBUS_TIM6_WWEC2 *((volatile unsigned int*)(0x427E0768UL)) +#define bFM3_EXBUS_TIM6_WWEC3 *((volatile unsigned int*)(0x427E076CUL)) +#define bFM3_EXBUS_TIM6_WIDLC0 *((volatile unsigned int*)(0x427E0770UL)) +#define bFM3_EXBUS_TIM6_WIDLC1 *((volatile unsigned int*)(0x427E0774UL)) +#define bFM3_EXBUS_TIM6_WIDLC2 *((volatile unsigned int*)(0x427E0778UL)) +#define bFM3_EXBUS_TIM6_WIDLC3 *((volatile unsigned int*)(0x427E077CUL)) +#define bFM3_EXBUS_TIM7_RACC0 *((volatile unsigned int*)(0x427E0780UL)) +#define bFM3_EXBUS_TIM7_RACC1 *((volatile unsigned int*)(0x427E0784UL)) +#define bFM3_EXBUS_TIM7_RACC2 *((volatile unsigned int*)(0x427E0788UL)) +#define bFM3_EXBUS_TIM7_RACC3 *((volatile unsigned int*)(0x427E078CUL)) +#define bFM3_EXBUS_TIM7_RADC0 *((volatile unsigned int*)(0x427E0790UL)) +#define bFM3_EXBUS_TIM7_RADC1 *((volatile unsigned int*)(0x427E0794UL)) +#define bFM3_EXBUS_TIM7_RADC2 *((volatile unsigned int*)(0x427E0798UL)) +#define bFM3_EXBUS_TIM7_RADC3 *((volatile unsigned int*)(0x427E079CUL)) +#define bFM3_EXBUS_TIM7_FRADC0 *((volatile unsigned int*)(0x427E07A0UL)) +#define bFM3_EXBUS_TIM7_FRADC1 *((volatile unsigned int*)(0x427E07A4UL)) +#define bFM3_EXBUS_TIM7_FRADC2 *((volatile unsigned int*)(0x427E07A8UL)) +#define bFM3_EXBUS_TIM7_FRADC3 *((volatile unsigned int*)(0x427E07ACUL)) +#define bFM3_EXBUS_TIM7_RIDLC0 *((volatile unsigned int*)(0x427E07B0UL)) +#define bFM3_EXBUS_TIM7_RIDLC1 *((volatile unsigned int*)(0x427E07B4UL)) +#define bFM3_EXBUS_TIM7_RIDLC2 *((volatile unsigned int*)(0x427E07B8UL)) +#define bFM3_EXBUS_TIM7_RIDLC3 *((volatile unsigned int*)(0x427E07BCUL)) +#define bFM3_EXBUS_TIM7_WACC0 *((volatile unsigned int*)(0x427E07C0UL)) +#define bFM3_EXBUS_TIM7_WACC1 *((volatile unsigned int*)(0x427E07C4UL)) +#define bFM3_EXBUS_TIM7_WACC2 *((volatile unsigned int*)(0x427E07C8UL)) +#define bFM3_EXBUS_TIM7_WACC3 *((volatile unsigned int*)(0x427E07CCUL)) +#define bFM3_EXBUS_TIM7_WADC0 *((volatile unsigned int*)(0x427E07D0UL)) +#define bFM3_EXBUS_TIM7_WADC1 *((volatile unsigned int*)(0x427E07D4UL)) +#define bFM3_EXBUS_TIM7_WADC2 *((volatile unsigned int*)(0x427E07D8UL)) +#define bFM3_EXBUS_TIM7_WADC3 *((volatile unsigned int*)(0x427E07DCUL)) +#define bFM3_EXBUS_TIM7_WWEC0 *((volatile unsigned int*)(0x427E07E0UL)) +#define bFM3_EXBUS_TIM7_WWEC1 *((volatile unsigned int*)(0x427E07E4UL)) +#define bFM3_EXBUS_TIM7_WWEC2 *((volatile unsigned int*)(0x427E07E8UL)) +#define bFM3_EXBUS_TIM7_WWEC3 *((volatile unsigned int*)(0x427E07ECUL)) +#define bFM3_EXBUS_TIM7_WIDLC0 *((volatile unsigned int*)(0x427E07F0UL)) +#define bFM3_EXBUS_TIM7_WIDLC1 *((volatile unsigned int*)(0x427E07F4UL)) +#define bFM3_EXBUS_TIM7_WIDLC2 *((volatile unsigned int*)(0x427E07F8UL)) +#define bFM3_EXBUS_TIM7_WIDLC3 *((volatile unsigned int*)(0x427E07FCUL)) +#define bFM3_EXBUS_AREA0_ADDR0 *((volatile unsigned int*)(0x427E0800UL)) +#define bFM3_EXBUS_AREA0_ADDR1 *((volatile unsigned int*)(0x427E0804UL)) +#define bFM3_EXBUS_AREA0_ADDR2 *((volatile unsigned int*)(0x427E0808UL)) +#define bFM3_EXBUS_AREA0_ADDR3 *((volatile unsigned int*)(0x427E080CUL)) +#define bFM3_EXBUS_AREA0_ADDR4 *((volatile unsigned int*)(0x427E0810UL)) +#define bFM3_EXBUS_AREA0_ADDR5 *((volatile unsigned int*)(0x427E0814UL)) +#define bFM3_EXBUS_AREA0_ADDR6 *((volatile unsigned int*)(0x427E0818UL)) +#define bFM3_EXBUS_AREA0_ADDR7 *((volatile unsigned int*)(0x427E081CUL)) +#define bFM3_EXBUS_AREA0_MASK0 *((volatile unsigned int*)(0x427E0840UL)) +#define bFM3_EXBUS_AREA0_MASK1 *((volatile unsigned int*)(0x427E0844UL)) +#define bFM3_EXBUS_AREA0_MASK2 *((volatile unsigned int*)(0x427E0848UL)) +#define bFM3_EXBUS_AREA0_MASK3 *((volatile unsigned int*)(0x427E084CUL)) +#define bFM3_EXBUS_AREA0_MASK4 *((volatile unsigned int*)(0x427E0850UL)) +#define bFM3_EXBUS_AREA0_MASK5 *((volatile unsigned int*)(0x427E0854UL)) +#define bFM3_EXBUS_AREA0_MASK6 *((volatile unsigned int*)(0x427E0858UL)) +#define bFM3_EXBUS_AREA1_ADDR0 *((volatile unsigned int*)(0x427E0880UL)) +#define bFM3_EXBUS_AREA1_ADDR1 *((volatile unsigned int*)(0x427E0884UL)) +#define bFM3_EXBUS_AREA1_ADDR2 *((volatile unsigned int*)(0x427E0888UL)) +#define bFM3_EXBUS_AREA1_ADDR3 *((volatile unsigned int*)(0x427E088CUL)) +#define bFM3_EXBUS_AREA1_ADDR4 *((volatile unsigned int*)(0x427E0890UL)) +#define bFM3_EXBUS_AREA1_ADDR5 *((volatile unsigned int*)(0x427E0894UL)) +#define bFM3_EXBUS_AREA1_ADDR6 *((volatile unsigned int*)(0x427E0898UL)) +#define bFM3_EXBUS_AREA1_ADDR7 *((volatile unsigned int*)(0x427E089CUL)) +#define bFM3_EXBUS_AREA1_MASK0 *((volatile unsigned int*)(0x427E08C0UL)) +#define bFM3_EXBUS_AREA1_MASK1 *((volatile unsigned int*)(0x427E08C4UL)) +#define bFM3_EXBUS_AREA1_MASK2 *((volatile unsigned int*)(0x427E08C8UL)) +#define bFM3_EXBUS_AREA1_MASK3 *((volatile unsigned int*)(0x427E08CCUL)) +#define bFM3_EXBUS_AREA1_MASK4 *((volatile unsigned int*)(0x427E08D0UL)) +#define bFM3_EXBUS_AREA1_MASK5 *((volatile unsigned int*)(0x427E08D4UL)) +#define bFM3_EXBUS_AREA1_MASK6 *((volatile unsigned int*)(0x427E08D8UL)) +#define bFM3_EXBUS_AREA2_ADDR0 *((volatile unsigned int*)(0x427E0900UL)) +#define bFM3_EXBUS_AREA2_ADDR1 *((volatile unsigned int*)(0x427E0904UL)) +#define bFM3_EXBUS_AREA2_ADDR2 *((volatile unsigned int*)(0x427E0908UL)) +#define bFM3_EXBUS_AREA2_ADDR3 *((volatile unsigned int*)(0x427E090CUL)) +#define bFM3_EXBUS_AREA2_ADDR4 *((volatile unsigned int*)(0x427E0910UL)) +#define bFM3_EXBUS_AREA2_ADDR5 *((volatile unsigned int*)(0x427E0914UL)) +#define bFM3_EXBUS_AREA2_ADDR6 *((volatile unsigned int*)(0x427E0918UL)) +#define bFM3_EXBUS_AREA2_ADDR7 *((volatile unsigned int*)(0x427E091CUL)) +#define bFM3_EXBUS_AREA2_MASK0 *((volatile unsigned int*)(0x427E0940UL)) +#define bFM3_EXBUS_AREA2_MASK1 *((volatile unsigned int*)(0x427E0944UL)) +#define bFM3_EXBUS_AREA2_MASK2 *((volatile unsigned int*)(0x427E0948UL)) +#define bFM3_EXBUS_AREA2_MASK3 *((volatile unsigned int*)(0x427E094CUL)) +#define bFM3_EXBUS_AREA2_MASK4 *((volatile unsigned int*)(0x427E0950UL)) +#define bFM3_EXBUS_AREA2_MASK5 *((volatile unsigned int*)(0x427E0954UL)) +#define bFM3_EXBUS_AREA2_MASK6 *((volatile unsigned int*)(0x427E0958UL)) +#define bFM3_EXBUS_AREA3_ADDR0 *((volatile unsigned int*)(0x427E0980UL)) +#define bFM3_EXBUS_AREA3_ADDR1 *((volatile unsigned int*)(0x427E0984UL)) +#define bFM3_EXBUS_AREA3_ADDR2 *((volatile unsigned int*)(0x427E0988UL)) +#define bFM3_EXBUS_AREA3_ADDR3 *((volatile unsigned int*)(0x427E098CUL)) +#define bFM3_EXBUS_AREA3_ADDR4 *((volatile unsigned int*)(0x427E0990UL)) +#define bFM3_EXBUS_AREA3_ADDR5 *((volatile unsigned int*)(0x427E0994UL)) +#define bFM3_EXBUS_AREA3_ADDR6 *((volatile unsigned int*)(0x427E0998UL)) +#define bFM3_EXBUS_AREA3_ADDR7 *((volatile unsigned int*)(0x427E099CUL)) +#define bFM3_EXBUS_AREA3_MASK0 *((volatile unsigned int*)(0x427E09C0UL)) +#define bFM3_EXBUS_AREA3_MASK1 *((volatile unsigned int*)(0x427E09C4UL)) +#define bFM3_EXBUS_AREA3_MASK2 *((volatile unsigned int*)(0x427E09C8UL)) +#define bFM3_EXBUS_AREA3_MASK3 *((volatile unsigned int*)(0x427E09CCUL)) +#define bFM3_EXBUS_AREA3_MASK4 *((volatile unsigned int*)(0x427E09D0UL)) +#define bFM3_EXBUS_AREA3_MASK5 *((volatile unsigned int*)(0x427E09D4UL)) +#define bFM3_EXBUS_AREA3_MASK6 *((volatile unsigned int*)(0x427E09D8UL)) +#define bFM3_EXBUS_AREA4_ADDR0 *((volatile unsigned int*)(0x427E0A00UL)) +#define bFM3_EXBUS_AREA4_ADDR1 *((volatile unsigned int*)(0x427E0A04UL)) +#define bFM3_EXBUS_AREA4_ADDR2 *((volatile unsigned int*)(0x427E0A08UL)) +#define bFM3_EXBUS_AREA4_ADDR3 *((volatile unsigned int*)(0x427E0A0CUL)) +#define bFM3_EXBUS_AREA4_ADDR4 *((volatile unsigned int*)(0x427E0A10UL)) +#define bFM3_EXBUS_AREA4_ADDR5 *((volatile unsigned int*)(0x427E0A14UL)) +#define bFM3_EXBUS_AREA4_ADDR6 *((volatile unsigned int*)(0x427E0A18UL)) +#define bFM3_EXBUS_AREA4_ADDR7 *((volatile unsigned int*)(0x427E0A1CUL)) +#define bFM3_EXBUS_AREA4_MASK0 *((volatile unsigned int*)(0x427E0A40UL)) +#define bFM3_EXBUS_AREA4_MASK1 *((volatile unsigned int*)(0x427E0A44UL)) +#define bFM3_EXBUS_AREA4_MASK2 *((volatile unsigned int*)(0x427E0A48UL)) +#define bFM3_EXBUS_AREA4_MASK3 *((volatile unsigned int*)(0x427E0A4CUL)) +#define bFM3_EXBUS_AREA4_MASK4 *((volatile unsigned int*)(0x427E0A50UL)) +#define bFM3_EXBUS_AREA4_MASK5 *((volatile unsigned int*)(0x427E0A54UL)) +#define bFM3_EXBUS_AREA4_MASK6 *((volatile unsigned int*)(0x427E0A58UL)) +#define bFM3_EXBUS_AREA5_ADDR0 *((volatile unsigned int*)(0x427E0A80UL)) +#define bFM3_EXBUS_AREA5_ADDR1 *((volatile unsigned int*)(0x427E0A84UL)) +#define bFM3_EXBUS_AREA5_ADDR2 *((volatile unsigned int*)(0x427E0A88UL)) +#define bFM3_EXBUS_AREA5_ADDR3 *((volatile unsigned int*)(0x427E0A8CUL)) +#define bFM3_EXBUS_AREA5_ADDR4 *((volatile unsigned int*)(0x427E0A90UL)) +#define bFM3_EXBUS_AREA5_ADDR5 *((volatile unsigned int*)(0x427E0A94UL)) +#define bFM3_EXBUS_AREA5_ADDR6 *((volatile unsigned int*)(0x427E0A98UL)) +#define bFM3_EXBUS_AREA5_ADDR7 *((volatile unsigned int*)(0x427E0A9CUL)) +#define bFM3_EXBUS_AREA5_MASK0 *((volatile unsigned int*)(0x427E0AC0UL)) +#define bFM3_EXBUS_AREA5_MASK1 *((volatile unsigned int*)(0x427E0AC4UL)) +#define bFM3_EXBUS_AREA5_MASK2 *((volatile unsigned int*)(0x427E0AC8UL)) +#define bFM3_EXBUS_AREA5_MASK3 *((volatile unsigned int*)(0x427E0ACCUL)) +#define bFM3_EXBUS_AREA5_MASK4 *((volatile unsigned int*)(0x427E0AD0UL)) +#define bFM3_EXBUS_AREA5_MASK5 *((volatile unsigned int*)(0x427E0AD4UL)) +#define bFM3_EXBUS_AREA5_MASK6 *((volatile unsigned int*)(0x427E0AD8UL)) +#define bFM3_EXBUS_AREA6_ADDR0 *((volatile unsigned int*)(0x427E0B00UL)) +#define bFM3_EXBUS_AREA6_ADDR1 *((volatile unsigned int*)(0x427E0B04UL)) +#define bFM3_EXBUS_AREA6_ADDR2 *((volatile unsigned int*)(0x427E0B08UL)) +#define bFM3_EXBUS_AREA6_ADDR3 *((volatile unsigned int*)(0x427E0B0CUL)) +#define bFM3_EXBUS_AREA6_ADDR4 *((volatile unsigned int*)(0x427E0B10UL)) +#define bFM3_EXBUS_AREA6_ADDR5 *((volatile unsigned int*)(0x427E0B14UL)) +#define bFM3_EXBUS_AREA6_ADDR6 *((volatile unsigned int*)(0x427E0B18UL)) +#define bFM3_EXBUS_AREA6_ADDR7 *((volatile unsigned int*)(0x427E0B1CUL)) +#define bFM3_EXBUS_AREA6_MASK0 *((volatile unsigned int*)(0x427E0B40UL)) +#define bFM3_EXBUS_AREA6_MASK1 *((volatile unsigned int*)(0x427E0B44UL)) +#define bFM3_EXBUS_AREA6_MASK2 *((volatile unsigned int*)(0x427E0B48UL)) +#define bFM3_EXBUS_AREA6_MASK3 *((volatile unsigned int*)(0x427E0B4CUL)) +#define bFM3_EXBUS_AREA6_MASK4 *((volatile unsigned int*)(0x427E0B50UL)) +#define bFM3_EXBUS_AREA6_MASK5 *((volatile unsigned int*)(0x427E0B54UL)) +#define bFM3_EXBUS_AREA6_MASK6 *((volatile unsigned int*)(0x427E0B58UL)) +#define bFM3_EXBUS_AREA7_ADDR0 *((volatile unsigned int*)(0x427E0B80UL)) +#define bFM3_EXBUS_AREA7_ADDR1 *((volatile unsigned int*)(0x427E0B84UL)) +#define bFM3_EXBUS_AREA7_ADDR2 *((volatile unsigned int*)(0x427E0B88UL)) +#define bFM3_EXBUS_AREA7_ADDR3 *((volatile unsigned int*)(0x427E0B8CUL)) +#define bFM3_EXBUS_AREA7_ADDR4 *((volatile unsigned int*)(0x427E0B90UL)) +#define bFM3_EXBUS_AREA7_ADDR5 *((volatile unsigned int*)(0x427E0B94UL)) +#define bFM3_EXBUS_AREA7_ADDR6 *((volatile unsigned int*)(0x427E0B98UL)) +#define bFM3_EXBUS_AREA7_ADDR7 *((volatile unsigned int*)(0x427E0B9CUL)) +#define bFM3_EXBUS_AREA7_MASK0 *((volatile unsigned int*)(0x427E0BC0UL)) +#define bFM3_EXBUS_AREA7_MASK1 *((volatile unsigned int*)(0x427E0BC4UL)) +#define bFM3_EXBUS_AREA7_MASK2 *((volatile unsigned int*)(0x427E0BC8UL)) +#define bFM3_EXBUS_AREA7_MASK3 *((volatile unsigned int*)(0x427E0BCCUL)) +#define bFM3_EXBUS_AREA7_MASK4 *((volatile unsigned int*)(0x427E0BD0UL)) +#define bFM3_EXBUS_AREA7_MASK5 *((volatile unsigned int*)(0x427E0BD4UL)) +#define bFM3_EXBUS_AREA7_MASK6 *((volatile unsigned int*)(0x427E0BD8UL)) + +/* USB channel 0 registers */ +#define bFM3_USB0_HCNT_HOST *((volatile unsigned int*)(0x42842000UL)) +#define bFM3_USB0_HCNT_URST *((volatile unsigned int*)(0x42842004UL)) +#define bFM3_USB0_HCNT_SOFIRE *((volatile unsigned int*)(0x42842008UL)) +#define bFM3_USB0_HCNT_DIRE *((volatile unsigned int*)(0x4284200CUL)) +#define bFM3_USB0_HCNT_CNNIRE *((volatile unsigned int*)(0x42842010UL)) +#define bFM3_USB0_HCNT_CMPIRE *((volatile unsigned int*)(0x42842014UL)) +#define bFM3_USB0_HCNT_URIRE *((volatile unsigned int*)(0x42842018UL)) +#define bFM3_USB0_HCNT_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) +#define bFM3_USB0_HCNT_RETRY *((volatile unsigned int*)(0x42842020UL)) +#define bFM3_USB0_HCNT_CANCEL *((volatile unsigned int*)(0x42842024UL)) +#define bFM3_USB0_HCNT_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) +#define bFM3_USB0_HCNT0_HOST *((volatile unsigned int*)(0x42842000UL)) +#define bFM3_USB0_HCNT0_URST *((volatile unsigned int*)(0x42842004UL)) +#define bFM3_USB0_HCNT0_SOFIRE *((volatile unsigned int*)(0x42842008UL)) +#define bFM3_USB0_HCNT0_DIRE *((volatile unsigned int*)(0x4284200CUL)) +#define bFM3_USB0_HCNT0_CNNIRE *((volatile unsigned int*)(0x42842010UL)) +#define bFM3_USB0_HCNT0_CMPIRE *((volatile unsigned int*)(0x42842014UL)) +#define bFM3_USB0_HCNT0_URIRE *((volatile unsigned int*)(0x42842018UL)) +#define bFM3_USB0_HCNT0_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) +#define bFM3_USB0_HCNT1_RETRY *((volatile unsigned int*)(0x42842020UL)) +#define bFM3_USB0_HCNT1_CANCEL *((volatile unsigned int*)(0x42842024UL)) +#define bFM3_USB0_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) +#define bFM3_USB0_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42842080UL)) +#define bFM3_USB0_HIRQ_DIRQ *((volatile unsigned int*)(0x42842084UL)) +#define bFM3_USB0_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42842088UL)) +#define bFM3_USB0_HIRQ_CMPIRQ *((volatile unsigned int*)(0x4284208CUL)) +#define bFM3_USB0_HIRQ_URIRQ *((volatile unsigned int*)(0x42842090UL)) +#define bFM3_USB0_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42842094UL)) +#define bFM3_USB0_HIRQ_TCAN *((volatile unsigned int*)(0x4284209CUL)) +#define bFM3_USB0_HERR_HS0 *((volatile unsigned int*)(0x428420A0UL)) +#define bFM3_USB0_HERR_HS1 *((volatile unsigned int*)(0x428420A4UL)) +#define bFM3_USB0_HERR_STUFF *((volatile unsigned int*)(0x428420A8UL)) +#define bFM3_USB0_HERR_TGERR *((volatile unsigned int*)(0x428420ACUL)) +#define bFM3_USB0_HERR_CRC *((volatile unsigned int*)(0x428420B0UL)) +#define bFM3_USB0_HERR_TOUT *((volatile unsigned int*)(0x428420B4UL)) +#define bFM3_USB0_HERR_RERR *((volatile unsigned int*)(0x428420B8UL)) +#define bFM3_USB0_HERR_LSTOF *((volatile unsigned int*)(0x428420BCUL)) +#define bFM3_USB0_HSTATE_CSTAT *((volatile unsigned int*)(0x42842100UL)) +#define bFM3_USB0_HSTATE_TMODE *((volatile unsigned int*)(0x42842104UL)) +#define bFM3_USB0_HSTATE_SUSP *((volatile unsigned int*)(0x42842108UL)) +#define bFM3_USB0_HSTATE_SOFBUSY *((volatile unsigned int*)(0x4284210CUL)) +#define bFM3_USB0_HSTATE_CLKSEL *((volatile unsigned int*)(0x42842110UL)) +#define bFM3_USB0_HSTATE_ALIVE *((volatile unsigned int*)(0x42842114UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42842120UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42842124UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42842128UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x4284212CUL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42842130UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42842134UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42842138UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x4284213CUL)) +#define bFM3_USB0_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42842180UL)) +#define bFM3_USB0_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42842184UL)) +#define bFM3_USB0_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42842188UL)) +#define bFM3_USB0_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x4284218CUL)) +#define bFM3_USB0_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42842190UL)) +#define bFM3_USB0_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42842194UL)) +#define bFM3_USB0_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42842198UL)) +#define bFM3_USB0_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x4284219CUL)) +#define bFM3_USB0_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x428421A0UL)) +#define bFM3_USB0_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x428421A4UL)) +#define bFM3_USB0_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x428421A8UL)) +#define bFM3_USB0_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x428421ACUL)) +#define bFM3_USB0_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x428421B0UL)) +#define bFM3_USB0_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x428421B4UL)) +#define bFM3_USB0_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x428421B8UL)) +#define bFM3_USB0_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x428421BCUL)) +#define bFM3_USB0_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42842180UL)) +#define bFM3_USB0_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42842184UL)) +#define bFM3_USB0_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42842188UL)) +#define bFM3_USB0_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x4284218CUL)) +#define bFM3_USB0_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42842190UL)) +#define bFM3_USB0_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42842194UL)) +#define bFM3_USB0_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42842198UL)) +#define bFM3_USB0_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x4284219CUL)) +#define bFM3_USB0_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x428421A0UL)) +#define bFM3_USB0_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x428421A4UL)) +#define bFM3_USB0_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x428421A8UL)) +#define bFM3_USB0_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x428421ACUL)) +#define bFM3_USB0_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x428421B0UL)) +#define bFM3_USB0_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x428421B4UL)) +#define bFM3_USB0_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x428421B8UL)) +#define bFM3_USB0_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x428421BCUL)) +#define bFM3_USB0_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42842200UL)) +#define bFM3_USB0_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42842204UL)) +#define bFM3_USB0_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42842208UL)) +#define bFM3_USB0_HADR_ADDRESS0 *((volatile unsigned int*)(0x42842220UL)) +#define bFM3_USB0_HADR_ADDRESS1 *((volatile unsigned int*)(0x42842224UL)) +#define bFM3_USB0_HADR_ADDRESS2 *((volatile unsigned int*)(0x42842228UL)) +#define bFM3_USB0_HADR_ADDRESS3 *((volatile unsigned int*)(0x4284222CUL)) +#define bFM3_USB0_HADR_ADDRESS4 *((volatile unsigned int*)(0x42842230UL)) +#define bFM3_USB0_HADR_ADDRESS5 *((volatile unsigned int*)(0x42842234UL)) +#define bFM3_USB0_HADR_ADDRESS6 *((volatile unsigned int*)(0x42842238UL)) +#define bFM3_USB0_HEOF_EOF0 *((volatile unsigned int*)(0x42842280UL)) +#define bFM3_USB0_HEOF_EOF1 *((volatile unsigned int*)(0x42842284UL)) +#define bFM3_USB0_HEOF_EOF2 *((volatile unsigned int*)(0x42842288UL)) +#define bFM3_USB0_HEOF_EOF3 *((volatile unsigned int*)(0x4284228CUL)) +#define bFM3_USB0_HEOF_EOF4 *((volatile unsigned int*)(0x42842290UL)) +#define bFM3_USB0_HEOF_EOF5 *((volatile unsigned int*)(0x42842294UL)) +#define bFM3_USB0_HEOF_EOF6 *((volatile unsigned int*)(0x42842298UL)) +#define bFM3_USB0_HEOF_EOF7 *((volatile unsigned int*)(0x4284229CUL)) +#define bFM3_USB0_HEOF_EOF8 *((volatile unsigned int*)(0x428422A0UL)) +#define bFM3_USB0_HEOF_EOF9 *((volatile unsigned int*)(0x428422A4UL)) +#define bFM3_USB0_HEOF_EOF10 *((volatile unsigned int*)(0x428422A8UL)) +#define bFM3_USB0_HEOF_EOF11 *((volatile unsigned int*)(0x428422ACUL)) +#define bFM3_USB0_HEOF_EOF12 *((volatile unsigned int*)(0x428422B0UL)) +#define bFM3_USB0_HEOF_EOF13 *((volatile unsigned int*)(0x428422B4UL)) +#define bFM3_USB0_HEOF_EOF14 *((volatile unsigned int*)(0x428422B8UL)) +#define bFM3_USB0_HEOF_EOF15 *((volatile unsigned int*)(0x428422BCUL)) +#define bFM3_USB0_HEOF0_EOF00 *((volatile unsigned int*)(0x42842280UL)) +#define bFM3_USB0_HEOF0_EOF01 *((volatile unsigned int*)(0x42842284UL)) +#define bFM3_USB0_HEOF0_EOF02 *((volatile unsigned int*)(0x42842288UL)) +#define bFM3_USB0_HEOF0_EOF03 *((volatile unsigned int*)(0x4284228CUL)) +#define bFM3_USB0_HEOF0_EOF04 *((volatile unsigned int*)(0x42842290UL)) +#define bFM3_USB0_HEOF0_EOF05 *((volatile unsigned int*)(0x42842294UL)) +#define bFM3_USB0_HEOF0_EOF06 *((volatile unsigned int*)(0x42842298UL)) +#define bFM3_USB0_HEOF0_EOF07 *((volatile unsigned int*)(0x4284229CUL)) +#define bFM3_USB0_HEOF1_EOF10 *((volatile unsigned int*)(0x428422A0UL)) +#define bFM3_USB0_HEOF1_EOF11 *((volatile unsigned int*)(0x428422A4UL)) +#define bFM3_USB0_HEOF1_EOF12 *((volatile unsigned int*)(0x428422A8UL)) +#define bFM3_USB0_HEOF1_EOF13 *((volatile unsigned int*)(0x428422ACUL)) +#define bFM3_USB0_HEOF1_EOF14 *((volatile unsigned int*)(0x428422B0UL)) +#define bFM3_USB0_HEOF1_EOF15 *((volatile unsigned int*)(0x428422B4UL)) +#define bFM3_USB0_HFRAME_FRAME0 *((volatile unsigned int*)(0x42842300UL)) +#define bFM3_USB0_HFRAME_FRAME1 *((volatile unsigned int*)(0x42842304UL)) +#define bFM3_USB0_HFRAME_FRAME2 *((volatile unsigned int*)(0x42842308UL)) +#define bFM3_USB0_HFRAME_FRAME3 *((volatile unsigned int*)(0x4284230CUL)) +#define bFM3_USB0_HFRAME_FRAME4 *((volatile unsigned int*)(0x42842310UL)) +#define bFM3_USB0_HFRAME_FRAME5 *((volatile unsigned int*)(0x42842314UL)) +#define bFM3_USB0_HFRAME_FRAME6 *((volatile unsigned int*)(0x42842318UL)) +#define bFM3_USB0_HFRAME_FRAME7 *((volatile unsigned int*)(0x4284231CUL)) +#define bFM3_USB0_HFRAME_FRAME8 *((volatile unsigned int*)(0x42842320UL)) +#define bFM3_USB0_HFRAME_FRAME9 *((volatile unsigned int*)(0x42842324UL)) +#define bFM3_USB0_HFRAME_FRAME10 *((volatile unsigned int*)(0x42842328UL)) +#define bFM3_USB0_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42842300UL)) +#define bFM3_USB0_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42842304UL)) +#define bFM3_USB0_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42842308UL)) +#define bFM3_USB0_HFRAME0_FRAME03 *((volatile unsigned int*)(0x4284230CUL)) +#define bFM3_USB0_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42842310UL)) +#define bFM3_USB0_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42842314UL)) +#define bFM3_USB0_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42842318UL)) +#define bFM3_USB0_HFRAME0_FRAME07 *((volatile unsigned int*)(0x4284231CUL)) +#define bFM3_USB0_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42842320UL)) +#define bFM3_USB0_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42842324UL)) +#define bFM3_USB0_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42842328UL)) +#define bFM3_USB0_HFRAME1_FRAME13 *((volatile unsigned int*)(0x4284232CUL)) +#define bFM3_USB0_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42842380UL)) +#define bFM3_USB0_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42842384UL)) +#define bFM3_USB0_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42842388UL)) +#define bFM3_USB0_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x4284238CUL)) +#define bFM3_USB0_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42842390UL)) +#define bFM3_USB0_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42842394UL)) +#define bFM3_USB0_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42842398UL)) +#define bFM3_USB0_HTOKEN_TGGL *((volatile unsigned int*)(0x4284239CUL)) +#define bFM3_USB0_UDCC_PWC *((volatile unsigned int*)(0x42842400UL)) +#define bFM3_USB0_UDCC_RFBK *((volatile unsigned int*)(0x42842404UL)) +#define bFM3_USB0_UDCC_STALCLREN *((volatile unsigned int*)(0x4284240CUL)) +#define bFM3_USB0_UDCC_USTP *((volatile unsigned int*)(0x42842410UL)) +#define bFM3_USB0_UDCC_HCONX *((volatile unsigned int*)(0x42842414UL)) +#define bFM3_USB0_UDCC_RESUM *((volatile unsigned int*)(0x42842418UL)) +#define bFM3_USB0_UDCC_RST *((volatile unsigned int*)(0x4284241CUL)) +#define bFM3_USB0_EP0C_PKS00 *((volatile unsigned int*)(0x42842480UL)) +#define bFM3_USB0_EP0C_PKS01 *((volatile unsigned int*)(0x42842484UL)) +#define bFM3_USB0_EP0C_PKS02 *((volatile unsigned int*)(0x42842488UL)) +#define bFM3_USB0_EP0C_PKS03 *((volatile unsigned int*)(0x4284248CUL)) +#define bFM3_USB0_EP0C_PKS04 *((volatile unsigned int*)(0x42842490UL)) +#define bFM3_USB0_EP0C_PKS05 *((volatile unsigned int*)(0x42842494UL)) +#define bFM3_USB0_EP0C_PKS06 *((volatile unsigned int*)(0x42842498UL)) +#define bFM3_USB0_EP0C_STAL *((volatile unsigned int*)(0x428424A4UL)) +#define bFM3_USB0_EP1C_PKS10 *((volatile unsigned int*)(0x42842500UL)) +#define bFM3_USB0_EP1C_PKS11 *((volatile unsigned int*)(0x42842504UL)) +#define bFM3_USB0_EP1C_PKS12 *((volatile unsigned int*)(0x42842508UL)) +#define bFM3_USB0_EP1C_PKS13 *((volatile unsigned int*)(0x4284250CUL)) +#define bFM3_USB0_EP1C_PKS14 *((volatile unsigned int*)(0x42842510UL)) +#define bFM3_USB0_EP1C_PKS15 *((volatile unsigned int*)(0x42842514UL)) +#define bFM3_USB0_EP1C_PKS16 *((volatile unsigned int*)(0x42842518UL)) +#define bFM3_USB0_EP1C_PKS17 *((volatile unsigned int*)(0x4284251CUL)) +#define bFM3_USB0_EP1C_PSK18 *((volatile unsigned int*)(0x42842520UL)) +#define bFM3_USB0_EP1C_STAL *((volatile unsigned int*)(0x42842524UL)) +#define bFM3_USB0_EP1C_NULE *((volatile unsigned int*)(0x42842528UL)) +#define bFM3_USB0_EP1C_DMAE *((volatile unsigned int*)(0x4284252CUL)) +#define bFM3_USB0_EP1C_DIR *((volatile unsigned int*)(0x42842530UL)) +#define bFM3_USB0_EP1C_TYPE0 *((volatile unsigned int*)(0x42842534UL)) +#define bFM3_USB0_EP1C_TYPE1 *((volatile unsigned int*)(0x42842538UL)) +#define bFM3_USB0_EP1C_EPEN *((volatile unsigned int*)(0x4284253CUL)) +#define bFM3_USB0_EP2C_PKS20 *((volatile unsigned int*)(0x42842580UL)) +#define bFM3_USB0_EP2C_PKS21 *((volatile unsigned int*)(0x42842584UL)) +#define bFM3_USB0_EP2C_PKS22 *((volatile unsigned int*)(0x42842588UL)) +#define bFM3_USB0_EP2C_PKS23 *((volatile unsigned int*)(0x4284258CUL)) +#define bFM3_USB0_EP2C_PKS24 *((volatile unsigned int*)(0x42842590UL)) +#define bFM3_USB0_EP2C_PKS25 *((volatile unsigned int*)(0x42842594UL)) +#define bFM3_USB0_EP2C_PKS26 *((volatile unsigned int*)(0x42842598UL)) +#define bFM3_USB0_EP2C_STAL *((volatile unsigned int*)(0x428425A4UL)) +#define bFM3_USB0_EP2C_NULE *((volatile unsigned int*)(0x428425A8UL)) +#define bFM3_USB0_EP2C_DMAE *((volatile unsigned int*)(0x428425ACUL)) +#define bFM3_USB0_EP2C_DIR *((volatile unsigned int*)(0x428425B0UL)) +#define bFM3_USB0_EP2C_TYPE0 *((volatile unsigned int*)(0x428425B4UL)) +#define bFM3_USB0_EP2C_TYPE1 *((volatile unsigned int*)(0x428425B8UL)) +#define bFM3_USB0_EP2C_EPEN *((volatile unsigned int*)(0x428425BCUL)) +#define bFM3_USB0_EP3C_PKS30 *((volatile unsigned int*)(0x42842600UL)) +#define bFM3_USB0_EP3C_PKS31 *((volatile unsigned int*)(0x42842604UL)) +#define bFM3_USB0_EP3C_PKS32 *((volatile unsigned int*)(0x42842608UL)) +#define bFM3_USB0_EP3C_PKS33 *((volatile unsigned int*)(0x4284260CUL)) +#define bFM3_USB0_EP3C_PKS34 *((volatile unsigned int*)(0x42842610UL)) +#define bFM3_USB0_EP3C_PKS35 *((volatile unsigned int*)(0x42842614UL)) +#define bFM3_USB0_EP3C_PKS36 *((volatile unsigned int*)(0x42842618UL)) +#define bFM3_USB0_EP3C_STAL *((volatile unsigned int*)(0x42842624UL)) +#define bFM3_USB0_EP3C_NULE *((volatile unsigned int*)(0x42842628UL)) +#define bFM3_USB0_EP3C_DMAE *((volatile unsigned int*)(0x4284262CUL)) +#define bFM3_USB0_EP3C_DIR *((volatile unsigned int*)(0x42842630UL)) +#define bFM3_USB0_EP3C_TYPE0 *((volatile unsigned int*)(0x42842634UL)) +#define bFM3_USB0_EP3C_TYPE1 *((volatile unsigned int*)(0x42842638UL)) +#define bFM3_USB0_EP3C_EPEN *((volatile unsigned int*)(0x4284263CUL)) +#define bFM3_USB0_EP4C_PKS40 *((volatile unsigned int*)(0x42842680UL)) +#define bFM3_USB0_EP4C_PKS41 *((volatile unsigned int*)(0x42842684UL)) +#define bFM3_USB0_EP4C_PKS42 *((volatile unsigned int*)(0x42842688UL)) +#define bFM3_USB0_EP4C_PKS43 *((volatile unsigned int*)(0x4284268CUL)) +#define bFM3_USB0_EP4C_PKS44 *((volatile unsigned int*)(0x42842690UL)) +#define bFM3_USB0_EP4C_PKS45 *((volatile unsigned int*)(0x42842694UL)) +#define bFM3_USB0_EP4C_PKS46 *((volatile unsigned int*)(0x42842698UL)) +#define bFM3_USB0_EP4C_STAL *((volatile unsigned int*)(0x428426A4UL)) +#define bFM3_USB0_EP4C_NULE *((volatile unsigned int*)(0x428426A8UL)) +#define bFM3_USB0_EP4C_DMAE *((volatile unsigned int*)(0x428426ACUL)) +#define bFM3_USB0_EP4C_DIR *((volatile unsigned int*)(0x428426B0UL)) +#define bFM3_USB0_EP4C_TYPE0 *((volatile unsigned int*)(0x428426B4UL)) +#define bFM3_USB0_EP4C_TYPE1 *((volatile unsigned int*)(0x428426B8UL)) +#define bFM3_USB0_EP4C_EPEN *((volatile unsigned int*)(0x428426BCUL)) +#define bFM3_USB0_EP5C_PKS50 *((volatile unsigned int*)(0x42842700UL)) +#define bFM3_USB0_EP5C_PKS51 *((volatile unsigned int*)(0x42842704UL)) +#define bFM3_USB0_EP5C_PKS52 *((volatile unsigned int*)(0x42842708UL)) +#define bFM3_USB0_EP5C_PKS53 *((volatile unsigned int*)(0x4284270CUL)) +#define bFM3_USB0_EP5C_PKS54 *((volatile unsigned int*)(0x42842710UL)) +#define bFM3_USB0_EP5C_PKS55 *((volatile unsigned int*)(0x42842714UL)) +#define bFM3_USB0_EP5C_PKS56 *((volatile unsigned int*)(0x42842718UL)) +#define bFM3_USB0_EP5C_STAL *((volatile unsigned int*)(0x42842724UL)) +#define bFM3_USB0_EP5C_NULE *((volatile unsigned int*)(0x42842728UL)) +#define bFM3_USB0_EP5C_DMAE *((volatile unsigned int*)(0x4284272CUL)) +#define bFM3_USB0_EP5C_DIR *((volatile unsigned int*)(0x42842730UL)) +#define bFM3_USB0_EP5C_TYPE0 *((volatile unsigned int*)(0x42842734UL)) +#define bFM3_USB0_EP5C_TYPE1 *((volatile unsigned int*)(0x42842738UL)) +#define bFM3_USB0_EP5C_EPEN *((volatile unsigned int*)(0x4284273CUL)) +#define bFM3_USB0_TMSP_TMSP0 *((volatile unsigned int*)(0x42842780UL)) +#define bFM3_USB0_TMSP_TMSP1 *((volatile unsigned int*)(0x42842784UL)) +#define bFM3_USB0_TMSP_TMSP2 *((volatile unsigned int*)(0x42842788UL)) +#define bFM3_USB0_TMSP_TMSP3 *((volatile unsigned int*)(0x4284278CUL)) +#define bFM3_USB0_TMSP_TMSP4 *((volatile unsigned int*)(0x42842790UL)) +#define bFM3_USB0_TMSP_TMSP5 *((volatile unsigned int*)(0x42842794UL)) +#define bFM3_USB0_TMSP_TMSP6 *((volatile unsigned int*)(0x42842798UL)) +#define bFM3_USB0_TMSP_TMSP7 *((volatile unsigned int*)(0x4284279CUL)) +#define bFM3_USB0_TMSP_TMSP8 *((volatile unsigned int*)(0x428427A0UL)) +#define bFM3_USB0_TMSP_TMSP9 *((volatile unsigned int*)(0x428427A4UL)) +#define bFM3_USB0_TMSP_TMSP10 *((volatile unsigned int*)(0x428427A8UL)) +#define bFM3_USB0_UDCS_CONF *((volatile unsigned int*)(0x42842800UL)) +#define bFM3_USB0_UDCS_SETP *((volatile unsigned int*)(0x42842804UL)) +#define bFM3_USB0_UDCS_WKUP *((volatile unsigned int*)(0x42842808UL)) +#define bFM3_USB0_UDCS_BRST *((volatile unsigned int*)(0x4284280CUL)) +#define bFM3_USB0_UDCS_SOF *((volatile unsigned int*)(0x42842810UL)) +#define bFM3_USB0_UDCS_SUSP *((volatile unsigned int*)(0x42842814UL)) +#define bFM3_USB0_UDCIE_CONFIE *((volatile unsigned int*)(0x42842820UL)) +#define bFM3_USB0_UDCIE_CONFN *((volatile unsigned int*)(0x42842824UL)) +#define bFM3_USB0_UDCIE_WKUPIE *((volatile unsigned int*)(0x42842828UL)) +#define bFM3_USB0_UDCIE_BRSTIE *((volatile unsigned int*)(0x4284282CUL)) +#define bFM3_USB0_UDCIE_SOFIE *((volatile unsigned int*)(0x42842830UL)) +#define bFM3_USB0_UDCIE_SUSPIE *((volatile unsigned int*)(0x42842834UL)) +#define bFM3_USB0_EP0IS_DRQI *((volatile unsigned int*)(0x428428A8UL)) +#define bFM3_USB0_EP0IS_DRQIIE *((volatile unsigned int*)(0x428428B8UL)) +#define bFM3_USB0_EP0IS_BFINI *((volatile unsigned int*)(0x428428BCUL)) +#define bFM3_USB0_EP0OS_SIZE0 *((volatile unsigned int*)(0x42842900UL)) +#define bFM3_USB0_EP0OS_SIZE1 *((volatile unsigned int*)(0x42842904UL)) +#define bFM3_USB0_EP0OS_SIZE2 *((volatile unsigned int*)(0x42842908UL)) +#define bFM3_USB0_EP0OS_SIZE3 *((volatile unsigned int*)(0x4284290CUL)) +#define bFM3_USB0_EP0OS_SIZE4 *((volatile unsigned int*)(0x42842910UL)) +#define bFM3_USB0_EP0OS_SIZE5 *((volatile unsigned int*)(0x42842914UL)) +#define bFM3_USB0_EP0OS_SIZE6 *((volatile unsigned int*)(0x42842918UL)) +#define bFM3_USB0_EP0OS_SPK *((volatile unsigned int*)(0x42842924UL)) +#define bFM3_USB0_EP0OS_DRQO *((volatile unsigned int*)(0x42842928UL)) +#define bFM3_USB0_EP0OS_SPKIE *((volatile unsigned int*)(0x42842934UL)) +#define bFM3_USB0_EP0OS_DRQOIE *((volatile unsigned int*)(0x42842938UL)) +#define bFM3_USB0_EP0OS_BFINI *((volatile unsigned int*)(0x4284293CUL)) +#define bFM3_USB0_EP1S_SIZE10 *((volatile unsigned int*)(0x42842980UL)) +#define bFM3_USB0_EP1S_SIZE11 *((volatile unsigned int*)(0x42842984UL)) +#define bFM3_USB0_EP1S_SIZE12 *((volatile unsigned int*)(0x42842988UL)) +#define bFM3_USB0_EP1S_SIZE13 *((volatile unsigned int*)(0x4284298CUL)) +#define bFM3_USB0_EP1S_SIZE14 *((volatile unsigned int*)(0x42842990UL)) +#define bFM3_USB0_EP1S_SIZE15 *((volatile unsigned int*)(0x42842994UL)) +#define bFM3_USB0_EP1S_SIZE16 *((volatile unsigned int*)(0x42842998UL)) +#define bFM3_USB0_EP1S_SIZE17 *((volatile unsigned int*)(0x4284299CUL)) +#define bFM3_USB0_EP1S_SPK *((volatile unsigned int*)(0x428429A4UL)) +#define bFM3_USB0_EP1S_DRQ *((volatile unsigned int*)(0x428429A8UL)) +#define bFM3_USB0_EP1S_BUSY *((volatile unsigned int*)(0x428429ACUL)) +#define bFM3_USB0_EP1S_SPKIE *((volatile unsigned int*)(0x428429B4UL)) +#define bFM3_USB0_EP1S_DRQIE *((volatile unsigned int*)(0x428429B8UL)) +#define bFM3_USB0_EP1S_BFINI *((volatile unsigned int*)(0x428429BCUL)) +#define bFM3_USB0_EP2S_SIZE20 *((volatile unsigned int*)(0x42842A00UL)) +#define bFM3_USB0_EP2S_SIZE21 *((volatile unsigned int*)(0x42842A04UL)) +#define bFM3_USB0_EP2S_SIZE22 *((volatile unsigned int*)(0x42842A08UL)) +#define bFM3_USB0_EP2S_SIZE23 *((volatile unsigned int*)(0x42842A0CUL)) +#define bFM3_USB0_EP2S_SIZE24 *((volatile unsigned int*)(0x42842A10UL)) +#define bFM3_USB0_EP2S_SIZE25 *((volatile unsigned int*)(0x42842A14UL)) +#define bFM3_USB0_EP2S_SIZE26 *((volatile unsigned int*)(0x42842A18UL)) +#define bFM3_USB0_EP2S_SPK *((volatile unsigned int*)(0x42842A24UL)) +#define bFM3_USB0_EP2S_DRQ *((volatile unsigned int*)(0x42842A28UL)) +#define bFM3_USB0_EP2S_BUSY *((volatile unsigned int*)(0x42842A2CUL)) +#define bFM3_USB0_EP2S_SPKIE *((volatile unsigned int*)(0x42842A34UL)) +#define bFM3_USB0_EP2S_DRQIE *((volatile unsigned int*)(0x42842A38UL)) +#define bFM3_USB0_EP2S_BFINI *((volatile unsigned int*)(0x42842A3CUL)) +#define bFM3_USB0_EP3S_SIZE30 *((volatile unsigned int*)(0x42842A80UL)) +#define bFM3_USB0_EP3S_SIZE31 *((volatile unsigned int*)(0x42842A84UL)) +#define bFM3_USB0_EP3S_SIZE32 *((volatile unsigned int*)(0x42842A88UL)) +#define bFM3_USB0_EP3S_SIZE33 *((volatile unsigned int*)(0x42842A8CUL)) +#define bFM3_USB0_EP3S_SIZE34 *((volatile unsigned int*)(0x42842A90UL)) +#define bFM3_USB0_EP3S_SIZE35 *((volatile unsigned int*)(0x42842A94UL)) +#define bFM3_USB0_EP3S_SIZE36 *((volatile unsigned int*)(0x42842A98UL)) +#define bFM3_USB0_EP3S_SPK *((volatile unsigned int*)(0x42842AA4UL)) +#define bFM3_USB0_EP3S_DRQ *((volatile unsigned int*)(0x42842AA8UL)) +#define bFM3_USB0_EP3S_BUSY *((volatile unsigned int*)(0x42842AACUL)) +#define bFM3_USB0_EP3S_SPKIE *((volatile unsigned int*)(0x42842AB4UL)) +#define bFM3_USB0_EP3S_DRQIE *((volatile unsigned int*)(0x42842AB8UL)) +#define bFM3_USB0_EP3S_BFINI *((volatile unsigned int*)(0x42842ABCUL)) +#define bFM3_USB0_EP4S_SIZE40 *((volatile unsigned int*)(0x42842B00UL)) +#define bFM3_USB0_EP4S_SIZE41 *((volatile unsigned int*)(0x42842B04UL)) +#define bFM3_USB0_EP4S_SIZE42 *((volatile unsigned int*)(0x42842B08UL)) +#define bFM3_USB0_EP4S_SIZE43 *((volatile unsigned int*)(0x42842B0CUL)) +#define bFM3_USB0_EP4S_SIZE44 *((volatile unsigned int*)(0x42842B10UL)) +#define bFM3_USB0_EP4S_SIZE45 *((volatile unsigned int*)(0x42842B14UL)) +#define bFM3_USB0_EP4S_SIZE46 *((volatile unsigned int*)(0x42842B18UL)) +#define bFM3_USB0_EP4S_SPK *((volatile unsigned int*)(0x42842B24UL)) +#define bFM3_USB0_EP4S_DRQ *((volatile unsigned int*)(0x42842B28UL)) +#define bFM3_USB0_EP4S_BUSY *((volatile unsigned int*)(0x42842B2CUL)) +#define bFM3_USB0_EP4S_SPKIE *((volatile unsigned int*)(0x42842B34UL)) +#define bFM3_USB0_EP4S_DRQIE *((volatile unsigned int*)(0x42842B38UL)) +#define bFM3_USB0_EP4S_BFINI *((volatile unsigned int*)(0x42842B3CUL)) +#define bFM3_USB0_EP5S_SIZE50 *((volatile unsigned int*)(0x42842B80UL)) +#define bFM3_USB0_EP5S_SIZE51 *((volatile unsigned int*)(0x42842B84UL)) +#define bFM3_USB0_EP5S_SIZE52 *((volatile unsigned int*)(0x42842B88UL)) +#define bFM3_USB0_EP5S_SIZE53 *((volatile unsigned int*)(0x42842B8CUL)) +#define bFM3_USB0_EP5S_SIZE54 *((volatile unsigned int*)(0x42842B90UL)) +#define bFM3_USB0_EP5S_SIZE55 *((volatile unsigned int*)(0x42842B94UL)) +#define bFM3_USB0_EP5S_SIZE56 *((volatile unsigned int*)(0x42842B98UL)) +#define bFM3_USB0_EP5S_SPK *((volatile unsigned int*)(0x42842BA4UL)) +#define bFM3_USB0_EP5S_DRQ *((volatile unsigned int*)(0x42842BA8UL)) +#define bFM3_USB0_EP5S_BUSY *((volatile unsigned int*)(0x42842BACUL)) +#define bFM3_USB0_EP5S_SPKIE *((volatile unsigned int*)(0x42842BB4UL)) +#define bFM3_USB0_EP5S_DRQIE *((volatile unsigned int*)(0x42842BB8UL)) +#define bFM3_USB0_EP5S_BFINI *((volatile unsigned int*)(0x42842BBCUL)) + +/* DMA controller */ +#define bFM3_DMAC_DMACR_DH0 *((volatile unsigned int*)(0x42C00060UL)) +#define bFM3_DMAC_DMACR_DH1 *((volatile unsigned int*)(0x42C00064UL)) +#define bFM3_DMAC_DMACR_DH2 *((volatile unsigned int*)(0x42C00068UL)) +#define bFM3_DMAC_DMACR_DH3 *((volatile unsigned int*)(0x42C0006CUL)) +#define bFM3_DMAC_DMACR_PR *((volatile unsigned int*)(0x42C00070UL)) +#define bFM3_DMAC_DMACR_DS *((volatile unsigned int*)(0x42C00078UL)) +#define bFM3_DMAC_DMACR_DE *((volatile unsigned int*)(0x42C0007CUL)) +#define bFM3_DMAC_DMACA0_TC0 *((volatile unsigned int*)(0x42C00200UL)) +#define bFM3_DMAC_DMACA0_TC1 *((volatile unsigned int*)(0x42C00204UL)) +#define bFM3_DMAC_DMACA0_TC2 *((volatile unsigned int*)(0x42C00208UL)) +#define bFM3_DMAC_DMACA0_TC3 *((volatile unsigned int*)(0x42C0020CUL)) +#define bFM3_DMAC_DMACA0_TC4 *((volatile unsigned int*)(0x42C00210UL)) +#define bFM3_DMAC_DMACA0_TC5 *((volatile unsigned int*)(0x42C00214UL)) +#define bFM3_DMAC_DMACA0_TC6 *((volatile unsigned int*)(0x42C00218UL)) +#define bFM3_DMAC_DMACA0_TC7 *((volatile unsigned int*)(0x42C0021CUL)) +#define bFM3_DMAC_DMACA0_TC8 *((volatile unsigned int*)(0x42C00220UL)) +#define bFM3_DMAC_DMACA0_TC9 *((volatile unsigned int*)(0x42C00224UL)) +#define bFM3_DMAC_DMACA0_TC10 *((volatile unsigned int*)(0x42C00228UL)) +#define bFM3_DMAC_DMACA0_TC11 *((volatile unsigned int*)(0x42C0022CUL)) +#define bFM3_DMAC_DMACA0_TC12 *((volatile unsigned int*)(0x42C00230UL)) +#define bFM3_DMAC_DMACA0_TC13 *((volatile unsigned int*)(0x42C00234UL)) +#define bFM3_DMAC_DMACA0_TC14 *((volatile unsigned int*)(0x42C00238UL)) +#define bFM3_DMAC_DMACA0_TC15 *((volatile unsigned int*)(0x42C0023CUL)) +#define bFM3_DMAC_DMACA0_BC0 *((volatile unsigned int*)(0x42C00240UL)) +#define bFM3_DMAC_DMACA0_BC1 *((volatile unsigned int*)(0x42C00244UL)) +#define bFM3_DMAC_DMACA0_BC2 *((volatile unsigned int*)(0x42C00248UL)) +#define bFM3_DMAC_DMACA0_BC3 *((volatile unsigned int*)(0x42C0024CUL)) +#define bFM3_DMAC_DMACA0_IS0 *((volatile unsigned int*)(0x42C0025CUL)) +#define bFM3_DMAC_DMACA0_IS1 *((volatile unsigned int*)(0x42C00260UL)) +#define bFM3_DMAC_DMACA0_IS2 *((volatile unsigned int*)(0x42C00264UL)) +#define bFM3_DMAC_DMACA0_IS3 *((volatile unsigned int*)(0x42C00268UL)) +#define bFM3_DMAC_DMACA0_IS4 *((volatile unsigned int*)(0x42C0026CUL)) +#define bFM3_DMAC_DMACA0_IS5 *((volatile unsigned int*)(0x42C00270UL)) +#define bFM3_DMAC_DMACA0_ST *((volatile unsigned int*)(0x42C00274UL)) +#define bFM3_DMAC_DMACA0_PB *((volatile unsigned int*)(0x42C00278UL)) +#define bFM3_DMAC_DMACA0_EB *((volatile unsigned int*)(0x42C0027CUL)) +#define bFM3_DMAC_DMACB0_EM *((volatile unsigned int*)(0x42C00280UL)) +#define bFM3_DMAC_DMACB0_SS0 *((volatile unsigned int*)(0x42C002C0UL)) +#define bFM3_DMAC_DMACB0_SS1 *((volatile unsigned int*)(0x42C002C4UL)) +#define bFM3_DMAC_DMACB0_SS2 *((volatile unsigned int*)(0x42C002C8UL)) +#define bFM3_DMAC_DMACB0_CI *((volatile unsigned int*)(0x42C002CCUL)) +#define bFM3_DMAC_DMACB0_EI *((volatile unsigned int*)(0x42C002D0UL)) +#define bFM3_DMAC_DMACB0_RD *((volatile unsigned int*)(0x42C002D4UL)) +#define bFM3_DMAC_DMACB0_RS *((volatile unsigned int*)(0x42C002D8UL)) +#define bFM3_DMAC_DMACB0_RC *((volatile unsigned int*)(0x42C002DCUL)) +#define bFM3_DMAC_DMACB0_FD *((volatile unsigned int*)(0x42C002E0UL)) +#define bFM3_DMAC_DMACB0_FS *((volatile unsigned int*)(0x42C002E4UL)) +#define bFM3_DMAC_DMACB0_TW0 *((volatile unsigned int*)(0x42C002E8UL)) +#define bFM3_DMAC_DMACB0_TW1 *((volatile unsigned int*)(0x42C002ECUL)) +#define bFM3_DMAC_DMACB0_MS0 *((volatile unsigned int*)(0x42C002F0UL)) +#define bFM3_DMAC_DMACB0_MS1 *((volatile unsigned int*)(0x42C002F4UL)) +#define bFM3_DMAC_DMACA1_TC0 *((volatile unsigned int*)(0x42C00400UL)) +#define bFM3_DMAC_DMACA1_TC1 *((volatile unsigned int*)(0x42C00404UL)) +#define bFM3_DMAC_DMACA1_TC2 *((volatile unsigned int*)(0x42C00408UL)) +#define bFM3_DMAC_DMACA1_TC3 *((volatile unsigned int*)(0x42C0040CUL)) +#define bFM3_DMAC_DMACA1_TC4 *((volatile unsigned int*)(0x42C00410UL)) +#define bFM3_DMAC_DMACA1_TC5 *((volatile unsigned int*)(0x42C00414UL)) +#define bFM3_DMAC_DMACA1_TC6 *((volatile unsigned int*)(0x42C00418UL)) +#define bFM3_DMAC_DMACA1_TC7 *((volatile unsigned int*)(0x42C0041CUL)) +#define bFM3_DMAC_DMACA1_TC8 *((volatile unsigned int*)(0x42C00420UL)) +#define bFM3_DMAC_DMACA1_TC9 *((volatile unsigned int*)(0x42C00424UL)) +#define bFM3_DMAC_DMACA1_TC10 *((volatile unsigned int*)(0x42C00428UL)) +#define bFM3_DMAC_DMACA1_TC11 *((volatile unsigned int*)(0x42C0042CUL)) +#define bFM3_DMAC_DMACA1_TC12 *((volatile unsigned int*)(0x42C00430UL)) +#define bFM3_DMAC_DMACA1_TC13 *((volatile unsigned int*)(0x42C00434UL)) +#define bFM3_DMAC_DMACA1_TC14 *((volatile unsigned int*)(0x42C00438UL)) +#define bFM3_DMAC_DMACA1_TC15 *((volatile unsigned int*)(0x42C0043CUL)) +#define bFM3_DMAC_DMACA1_BC0 *((volatile unsigned int*)(0x42C00440UL)) +#define bFM3_DMAC_DMACA1_BC1 *((volatile unsigned int*)(0x42C00444UL)) +#define bFM3_DMAC_DMACA1_BC2 *((volatile unsigned int*)(0x42C00448UL)) +#define bFM3_DMAC_DMACA1_BC3 *((volatile unsigned int*)(0x42C0044CUL)) +#define bFM3_DMAC_DMACA1_IS0 *((volatile unsigned int*)(0x42C0045CUL)) +#define bFM3_DMAC_DMACA1_IS1 *((volatile unsigned int*)(0x42C00460UL)) +#define bFM3_DMAC_DMACA1_IS2 *((volatile unsigned int*)(0x42C00464UL)) +#define bFM3_DMAC_DMACA1_IS3 *((volatile unsigned int*)(0x42C00468UL)) +#define bFM3_DMAC_DMACA1_IS4 *((volatile unsigned int*)(0x42C0046CUL)) +#define bFM3_DMAC_DMACA1_IS5 *((volatile unsigned int*)(0x42C00470UL)) +#define bFM3_DMAC_DMACA1_ST *((volatile unsigned int*)(0x42C00474UL)) +#define bFM3_DMAC_DMACA1_PB *((volatile unsigned int*)(0x42C00478UL)) +#define bFM3_DMAC_DMACA1_EB *((volatile unsigned int*)(0x42C0047CUL)) +#define bFM3_DMAC_DMACB1_EM *((volatile unsigned int*)(0x42C00480UL)) +#define bFM3_DMAC_DMACB1_SS0 *((volatile unsigned int*)(0x42C004C0UL)) +#define bFM3_DMAC_DMACB1_SS1 *((volatile unsigned int*)(0x42C004C4UL)) +#define bFM3_DMAC_DMACB1_SS2 *((volatile unsigned int*)(0x42C004C8UL)) +#define bFM3_DMAC_DMACB1_CI *((volatile unsigned int*)(0x42C004CCUL)) +#define bFM3_DMAC_DMACB1_EI *((volatile unsigned int*)(0x42C004D0UL)) +#define bFM3_DMAC_DMACB1_RD *((volatile unsigned int*)(0x42C004D4UL)) +#define bFM3_DMAC_DMACB1_RS *((volatile unsigned int*)(0x42C004D8UL)) +#define bFM3_DMAC_DMACB1_RC *((volatile unsigned int*)(0x42C004DCUL)) +#define bFM3_DMAC_DMACB1_FD *((volatile unsigned int*)(0x42C004E0UL)) +#define bFM3_DMAC_DMACB1_FS *((volatile unsigned int*)(0x42C004E4UL)) +#define bFM3_DMAC_DMACB1_TW0 *((volatile unsigned int*)(0x42C004E8UL)) +#define bFM3_DMAC_DMACB1_TW1 *((volatile unsigned int*)(0x42C004ECUL)) +#define bFM3_DMAC_DMACB1_MS0 *((volatile unsigned int*)(0x42C004F0UL)) +#define bFM3_DMAC_DMACB1_MS1 *((volatile unsigned int*)(0x42C004F4UL)) +#define bFM3_DMAC_DMACA2_TC0 *((volatile unsigned int*)(0x42C00600UL)) +#define bFM3_DMAC_DMACA2_TC1 *((volatile unsigned int*)(0x42C00604UL)) +#define bFM3_DMAC_DMACA2_TC2 *((volatile unsigned int*)(0x42C00608UL)) +#define bFM3_DMAC_DMACA2_TC3 *((volatile unsigned int*)(0x42C0060CUL)) +#define bFM3_DMAC_DMACA2_TC4 *((volatile unsigned int*)(0x42C00610UL)) +#define bFM3_DMAC_DMACA2_TC5 *((volatile unsigned int*)(0x42C00614UL)) +#define bFM3_DMAC_DMACA2_TC6 *((volatile unsigned int*)(0x42C00618UL)) +#define bFM3_DMAC_DMACA2_TC7 *((volatile unsigned int*)(0x42C0061CUL)) +#define bFM3_DMAC_DMACA2_TC8 *((volatile unsigned int*)(0x42C00620UL)) +#define bFM3_DMAC_DMACA2_TC9 *((volatile unsigned int*)(0x42C00624UL)) +#define bFM3_DMAC_DMACA2_TC10 *((volatile unsigned int*)(0x42C00628UL)) +#define bFM3_DMAC_DMACA2_TC11 *((volatile unsigned int*)(0x42C0062CUL)) +#define bFM3_DMAC_DMACA2_TC12 *((volatile unsigned int*)(0x42C00630UL)) +#define bFM3_DMAC_DMACA2_TC13 *((volatile unsigned int*)(0x42C00634UL)) +#define bFM3_DMAC_DMACA2_TC14 *((volatile unsigned int*)(0x42C00638UL)) +#define bFM3_DMAC_DMACA2_TC15 *((volatile unsigned int*)(0x42C0063CUL)) +#define bFM3_DMAC_DMACA2_BC0 *((volatile unsigned int*)(0x42C00640UL)) +#define bFM3_DMAC_DMACA2_BC1 *((volatile unsigned int*)(0x42C00644UL)) +#define bFM3_DMAC_DMACA2_BC2 *((volatile unsigned int*)(0x42C00648UL)) +#define bFM3_DMAC_DMACA2_BC3 *((volatile unsigned int*)(0x42C0064CUL)) +#define bFM3_DMAC_DMACA2_IS0 *((volatile unsigned int*)(0x42C0065CUL)) +#define bFM3_DMAC_DMACA2_IS1 *((volatile unsigned int*)(0x42C00660UL)) +#define bFM3_DMAC_DMACA2_IS2 *((volatile unsigned int*)(0x42C00664UL)) +#define bFM3_DMAC_DMACA2_IS3 *((volatile unsigned int*)(0x42C00668UL)) +#define bFM3_DMAC_DMACA2_IS4 *((volatile unsigned int*)(0x42C0066CUL)) +#define bFM3_DMAC_DMACA2_IS5 *((volatile unsigned int*)(0x42C00670UL)) +#define bFM3_DMAC_DMACA2_ST *((volatile unsigned int*)(0x42C00674UL)) +#define bFM3_DMAC_DMACA2_PB *((volatile unsigned int*)(0x42C00678UL)) +#define bFM3_DMAC_DMACA2_EB *((volatile unsigned int*)(0x42C0067CUL)) +#define bFM3_DMAC_DMACB2_EM *((volatile unsigned int*)(0x42C00680UL)) +#define bFM3_DMAC_DMACB2_SS0 *((volatile unsigned int*)(0x42C006C0UL)) +#define bFM3_DMAC_DMACB2_SS1 *((volatile unsigned int*)(0x42C006C4UL)) +#define bFM3_DMAC_DMACB2_SS2 *((volatile unsigned int*)(0x42C006C8UL)) +#define bFM3_DMAC_DMACB2_CI *((volatile unsigned int*)(0x42C006CCUL)) +#define bFM3_DMAC_DMACB2_EI *((volatile unsigned int*)(0x42C006D0UL)) +#define bFM3_DMAC_DMACB2_RD *((volatile unsigned int*)(0x42C006D4UL)) +#define bFM3_DMAC_DMACB2_RS *((volatile unsigned int*)(0x42C006D8UL)) +#define bFM3_DMAC_DMACB2_RC *((volatile unsigned int*)(0x42C006DCUL)) +#define bFM3_DMAC_DMACB2_FD *((volatile unsigned int*)(0x42C006E0UL)) +#define bFM3_DMAC_DMACB2_FS *((volatile unsigned int*)(0x42C006E4UL)) +#define bFM3_DMAC_DMACB2_TW0 *((volatile unsigned int*)(0x42C006E8UL)) +#define bFM3_DMAC_DMACB2_TW1 *((volatile unsigned int*)(0x42C006ECUL)) +#define bFM3_DMAC_DMACB2_MS0 *((volatile unsigned int*)(0x42C006F0UL)) +#define bFM3_DMAC_DMACB2_MS1 *((volatile unsigned int*)(0x42C006F4UL)) +#define bFM3_DMAC_DMACA3_TC0 *((volatile unsigned int*)(0x42C00800UL)) +#define bFM3_DMAC_DMACA3_TC1 *((volatile unsigned int*)(0x42C00804UL)) +#define bFM3_DMAC_DMACA3_TC2 *((volatile unsigned int*)(0x42C00808UL)) +#define bFM3_DMAC_DMACA3_TC3 *((volatile unsigned int*)(0x42C0080CUL)) +#define bFM3_DMAC_DMACA3_TC4 *((volatile unsigned int*)(0x42C00810UL)) +#define bFM3_DMAC_DMACA3_TC5 *((volatile unsigned int*)(0x42C00814UL)) +#define bFM3_DMAC_DMACA3_TC6 *((volatile unsigned int*)(0x42C00818UL)) +#define bFM3_DMAC_DMACA3_TC7 *((volatile unsigned int*)(0x42C0081CUL)) +#define bFM3_DMAC_DMACA3_TC8 *((volatile unsigned int*)(0x42C00820UL)) +#define bFM3_DMAC_DMACA3_TC9 *((volatile unsigned int*)(0x42C00824UL)) +#define bFM3_DMAC_DMACA3_TC10 *((volatile unsigned int*)(0x42C00828UL)) +#define bFM3_DMAC_DMACA3_TC11 *((volatile unsigned int*)(0x42C0082CUL)) +#define bFM3_DMAC_DMACA3_TC12 *((volatile unsigned int*)(0x42C00830UL)) +#define bFM3_DMAC_DMACA3_TC13 *((volatile unsigned int*)(0x42C00834UL)) +#define bFM3_DMAC_DMACA3_TC14 *((volatile unsigned int*)(0x42C00838UL)) +#define bFM3_DMAC_DMACA3_TC15 *((volatile unsigned int*)(0x42C0083CUL)) +#define bFM3_DMAC_DMACA3_BC0 *((volatile unsigned int*)(0x42C00840UL)) +#define bFM3_DMAC_DMACA3_BC1 *((volatile unsigned int*)(0x42C00844UL)) +#define bFM3_DMAC_DMACA3_BC2 *((volatile unsigned int*)(0x42C00848UL)) +#define bFM3_DMAC_DMACA3_BC3 *((volatile unsigned int*)(0x42C0084CUL)) +#define bFM3_DMAC_DMACA3_IS0 *((volatile unsigned int*)(0x42C0085CUL)) +#define bFM3_DMAC_DMACA3_IS1 *((volatile unsigned int*)(0x42C00860UL)) +#define bFM3_DMAC_DMACA3_IS2 *((volatile unsigned int*)(0x42C00864UL)) +#define bFM3_DMAC_DMACA3_IS3 *((volatile unsigned int*)(0x42C00868UL)) +#define bFM3_DMAC_DMACA3_IS4 *((volatile unsigned int*)(0x42C0086CUL)) +#define bFM3_DMAC_DMACA3_IS5 *((volatile unsigned int*)(0x42C00870UL)) +#define bFM3_DMAC_DMACA3_ST *((volatile unsigned int*)(0x42C00874UL)) +#define bFM3_DMAC_DMACA3_PB *((volatile unsigned int*)(0x42C00878UL)) +#define bFM3_DMAC_DMACA3_EB *((volatile unsigned int*)(0x42C0087CUL)) +#define bFM3_DMAC_DMACB3_EM *((volatile unsigned int*)(0x42C00880UL)) +#define bFM3_DMAC_DMACB3_SS0 *((volatile unsigned int*)(0x42C008C0UL)) +#define bFM3_DMAC_DMACB3_SS1 *((volatile unsigned int*)(0x42C008C4UL)) +#define bFM3_DMAC_DMACB3_SS2 *((volatile unsigned int*)(0x42C008C8UL)) +#define bFM3_DMAC_DMACB3_CI *((volatile unsigned int*)(0x42C008CCUL)) +#define bFM3_DMAC_DMACB3_EI *((volatile unsigned int*)(0x42C008D0UL)) +#define bFM3_DMAC_DMACB3_RD *((volatile unsigned int*)(0x42C008D4UL)) +#define bFM3_DMAC_DMACB3_RS *((volatile unsigned int*)(0x42C008D8UL)) +#define bFM3_DMAC_DMACB3_RC *((volatile unsigned int*)(0x42C008DCUL)) +#define bFM3_DMAC_DMACB3_FD *((volatile unsigned int*)(0x42C008E0UL)) +#define bFM3_DMAC_DMACB3_FS *((volatile unsigned int*)(0x42C008E4UL)) +#define bFM3_DMAC_DMACB3_TW0 *((volatile unsigned int*)(0x42C008E8UL)) +#define bFM3_DMAC_DMACB3_TW1 *((volatile unsigned int*)(0x42C008ECUL)) +#define bFM3_DMAC_DMACB3_MS0 *((volatile unsigned int*)(0x42C008F0UL)) +#define bFM3_DMAC_DMACB3_MS1 *((volatile unsigned int*)(0x42C008F4UL)) +#define bFM3_DMAC_DMACA4_TC0 *((volatile unsigned int*)(0x42C00A00UL)) +#define bFM3_DMAC_DMACA4_TC1 *((volatile unsigned int*)(0x42C00A04UL)) +#define bFM3_DMAC_DMACA4_TC2 *((volatile unsigned int*)(0x42C00A08UL)) +#define bFM3_DMAC_DMACA4_TC3 *((volatile unsigned int*)(0x42C00A0CUL)) +#define bFM3_DMAC_DMACA4_TC4 *((volatile unsigned int*)(0x42C00A10UL)) +#define bFM3_DMAC_DMACA4_TC5 *((volatile unsigned int*)(0x42C00A14UL)) +#define bFM3_DMAC_DMACA4_TC6 *((volatile unsigned int*)(0x42C00A18UL)) +#define bFM3_DMAC_DMACA4_TC7 *((volatile unsigned int*)(0x42C00A1CUL)) +#define bFM3_DMAC_DMACA4_TC8 *((volatile unsigned int*)(0x42C00A20UL)) +#define bFM3_DMAC_DMACA4_TC9 *((volatile unsigned int*)(0x42C00A24UL)) +#define bFM3_DMAC_DMACA4_TC10 *((volatile unsigned int*)(0x42C00A28UL)) +#define bFM3_DMAC_DMACA4_TC11 *((volatile unsigned int*)(0x42C00A2CUL)) +#define bFM3_DMAC_DMACA4_TC12 *((volatile unsigned int*)(0x42C00A30UL)) +#define bFM3_DMAC_DMACA4_TC13 *((volatile unsigned int*)(0x42C00A34UL)) +#define bFM3_DMAC_DMACA4_TC14 *((volatile unsigned int*)(0x42C00A38UL)) +#define bFM3_DMAC_DMACA4_TC15 *((volatile unsigned int*)(0x42C00A3CUL)) +#define bFM3_DMAC_DMACA4_BC0 *((volatile unsigned int*)(0x42C00A40UL)) +#define bFM3_DMAC_DMACA4_BC1 *((volatile unsigned int*)(0x42C00A44UL)) +#define bFM3_DMAC_DMACA4_BC2 *((volatile unsigned int*)(0x42C00A48UL)) +#define bFM3_DMAC_DMACA4_BC3 *((volatile unsigned int*)(0x42C00A4CUL)) +#define bFM3_DMAC_DMACA4_IS0 *((volatile unsigned int*)(0x42C00A5CUL)) +#define bFM3_DMAC_DMACA4_IS1 *((volatile unsigned int*)(0x42C00A60UL)) +#define bFM3_DMAC_DMACA4_IS2 *((volatile unsigned int*)(0x42C00A64UL)) +#define bFM3_DMAC_DMACA4_IS3 *((volatile unsigned int*)(0x42C00A68UL)) +#define bFM3_DMAC_DMACA4_IS4 *((volatile unsigned int*)(0x42C00A6CUL)) +#define bFM3_DMAC_DMACA4_IS5 *((volatile unsigned int*)(0x42C00A70UL)) +#define bFM3_DMAC_DMACA4_ST *((volatile unsigned int*)(0x42C00A74UL)) +#define bFM3_DMAC_DMACA4_PB *((volatile unsigned int*)(0x42C00A78UL)) +#define bFM3_DMAC_DMACA4_EB *((volatile unsigned int*)(0x42C00A7CUL)) +#define bFM3_DMAC_DMACB4_EM *((volatile unsigned int*)(0x42C00A80UL)) +#define bFM3_DMAC_DMACB4_SS0 *((volatile unsigned int*)(0x42C00AC0UL)) +#define bFM3_DMAC_DMACB4_SS1 *((volatile unsigned int*)(0x42C00AC4UL)) +#define bFM3_DMAC_DMACB4_SS2 *((volatile unsigned int*)(0x42C00AC8UL)) +#define bFM3_DMAC_DMACB4_CI *((volatile unsigned int*)(0x42C00ACCUL)) +#define bFM3_DMAC_DMACB4_EI *((volatile unsigned int*)(0x42C00AD0UL)) +#define bFM3_DMAC_DMACB4_RD *((volatile unsigned int*)(0x42C00AD4UL)) +#define bFM3_DMAC_DMACB4_RS *((volatile unsigned int*)(0x42C00AD8UL)) +#define bFM3_DMAC_DMACB4_RC *((volatile unsigned int*)(0x42C00ADCUL)) +#define bFM3_DMAC_DMACB4_FD *((volatile unsigned int*)(0x42C00AE0UL)) +#define bFM3_DMAC_DMACB4_FS *((volatile unsigned int*)(0x42C00AE4UL)) +#define bFM3_DMAC_DMACB4_TW0 *((volatile unsigned int*)(0x42C00AE8UL)) +#define bFM3_DMAC_DMACB4_TW1 *((volatile unsigned int*)(0x42C00AECUL)) +#define bFM3_DMAC_DMACB4_MS0 *((volatile unsigned int*)(0x42C00AF0UL)) +#define bFM3_DMAC_DMACB4_MS1 *((volatile unsigned int*)(0x42C00AF4UL)) +#define bFM3_DMAC_DMACA5_TC0 *((volatile unsigned int*)(0x42C00C00UL)) +#define bFM3_DMAC_DMACA5_TC1 *((volatile unsigned int*)(0x42C00C04UL)) +#define bFM3_DMAC_DMACA5_TC2 *((volatile unsigned int*)(0x42C00C08UL)) +#define bFM3_DMAC_DMACA5_TC3 *((volatile unsigned int*)(0x42C00C0CUL)) +#define bFM3_DMAC_DMACA5_TC4 *((volatile unsigned int*)(0x42C00C10UL)) +#define bFM3_DMAC_DMACA5_TC5 *((volatile unsigned int*)(0x42C00C14UL)) +#define bFM3_DMAC_DMACA5_TC6 *((volatile unsigned int*)(0x42C00C18UL)) +#define bFM3_DMAC_DMACA5_TC7 *((volatile unsigned int*)(0x42C00C1CUL)) +#define bFM3_DMAC_DMACA5_TC8 *((volatile unsigned int*)(0x42C00C20UL)) +#define bFM3_DMAC_DMACA5_TC9 *((volatile unsigned int*)(0x42C00C24UL)) +#define bFM3_DMAC_DMACA5_TC10 *((volatile unsigned int*)(0x42C00C28UL)) +#define bFM3_DMAC_DMACA5_TC11 *((volatile unsigned int*)(0x42C00C2CUL)) +#define bFM3_DMAC_DMACA5_TC12 *((volatile unsigned int*)(0x42C00C30UL)) +#define bFM3_DMAC_DMACA5_TC13 *((volatile unsigned int*)(0x42C00C34UL)) +#define bFM3_DMAC_DMACA5_TC14 *((volatile unsigned int*)(0x42C00C38UL)) +#define bFM3_DMAC_DMACA5_TC15 *((volatile unsigned int*)(0x42C00C3CUL)) +#define bFM3_DMAC_DMACA5_BC0 *((volatile unsigned int*)(0x42C00C40UL)) +#define bFM3_DMAC_DMACA5_BC1 *((volatile unsigned int*)(0x42C00C44UL)) +#define bFM3_DMAC_DMACA5_BC2 *((volatile unsigned int*)(0x42C00C48UL)) +#define bFM3_DMAC_DMACA5_BC3 *((volatile unsigned int*)(0x42C00C4CUL)) +#define bFM3_DMAC_DMACA5_IS0 *((volatile unsigned int*)(0x42C00C5CUL)) +#define bFM3_DMAC_DMACA5_IS1 *((volatile unsigned int*)(0x42C00C60UL)) +#define bFM3_DMAC_DMACA5_IS2 *((volatile unsigned int*)(0x42C00C64UL)) +#define bFM3_DMAC_DMACA5_IS3 *((volatile unsigned int*)(0x42C00C68UL)) +#define bFM3_DMAC_DMACA5_IS4 *((volatile unsigned int*)(0x42C00C6CUL)) +#define bFM3_DMAC_DMACA5_IS5 *((volatile unsigned int*)(0x42C00C70UL)) +#define bFM3_DMAC_DMACA5_ST *((volatile unsigned int*)(0x42C00C74UL)) +#define bFM3_DMAC_DMACA5_PB *((volatile unsigned int*)(0x42C00C78UL)) +#define bFM3_DMAC_DMACA5_EB *((volatile unsigned int*)(0x42C00C7CUL)) +#define bFM3_DMAC_DMACB5_EM *((volatile unsigned int*)(0x42C00C80UL)) +#define bFM3_DMAC_DMACB5_SS0 *((volatile unsigned int*)(0x42C00CC0UL)) +#define bFM3_DMAC_DMACB5_SS1 *((volatile unsigned int*)(0x42C00CC4UL)) +#define bFM3_DMAC_DMACB5_SS2 *((volatile unsigned int*)(0x42C00CC8UL)) +#define bFM3_DMAC_DMACB5_CI *((volatile unsigned int*)(0x42C00CCCUL)) +#define bFM3_DMAC_DMACB5_EI *((volatile unsigned int*)(0x42C00CD0UL)) +#define bFM3_DMAC_DMACB5_RD *((volatile unsigned int*)(0x42C00CD4UL)) +#define bFM3_DMAC_DMACB5_RS *((volatile unsigned int*)(0x42C00CD8UL)) +#define bFM3_DMAC_DMACB5_RC *((volatile unsigned int*)(0x42C00CDCUL)) +#define bFM3_DMAC_DMACB5_FD *((volatile unsigned int*)(0x42C00CE0UL)) +#define bFM3_DMAC_DMACB5_FS *((volatile unsigned int*)(0x42C00CE4UL)) +#define bFM3_DMAC_DMACB5_TW0 *((volatile unsigned int*)(0x42C00CE8UL)) +#define bFM3_DMAC_DMACB5_TW1 *((volatile unsigned int*)(0x42C00CECUL)) +#define bFM3_DMAC_DMACB5_MS0 *((volatile unsigned int*)(0x42C00CF0UL)) +#define bFM3_DMAC_DMACB5_MS1 *((volatile unsigned int*)(0x42C00CF4UL)) +#define bFM3_DMAC_DMACA6_TC0 *((volatile unsigned int*)(0x42C00E00UL)) +#define bFM3_DMAC_DMACA6_TC1 *((volatile unsigned int*)(0x42C00E04UL)) +#define bFM3_DMAC_DMACA6_TC2 *((volatile unsigned int*)(0x42C00E08UL)) +#define bFM3_DMAC_DMACA6_TC3 *((volatile unsigned int*)(0x42C00E0CUL)) +#define bFM3_DMAC_DMACA6_TC4 *((volatile unsigned int*)(0x42C00E10UL)) +#define bFM3_DMAC_DMACA6_TC5 *((volatile unsigned int*)(0x42C00E14UL)) +#define bFM3_DMAC_DMACA6_TC6 *((volatile unsigned int*)(0x42C00E18UL)) +#define bFM3_DMAC_DMACA6_TC7 *((volatile unsigned int*)(0x42C00E1CUL)) +#define bFM3_DMAC_DMACA6_TC8 *((volatile unsigned int*)(0x42C00E20UL)) +#define bFM3_DMAC_DMACA6_TC9 *((volatile unsigned int*)(0x42C00E24UL)) +#define bFM3_DMAC_DMACA6_TC10 *((volatile unsigned int*)(0x42C00E28UL)) +#define bFM3_DMAC_DMACA6_TC11 *((volatile unsigned int*)(0x42C00E2CUL)) +#define bFM3_DMAC_DMACA6_TC12 *((volatile unsigned int*)(0x42C00E30UL)) +#define bFM3_DMAC_DMACA6_TC13 *((volatile unsigned int*)(0x42C00E34UL)) +#define bFM3_DMAC_DMACA6_TC14 *((volatile unsigned int*)(0x42C00E38UL)) +#define bFM3_DMAC_DMACA6_TC15 *((volatile unsigned int*)(0x42C00E3CUL)) +#define bFM3_DMAC_DMACA6_BC0 *((volatile unsigned int*)(0x42C00E40UL)) +#define bFM3_DMAC_DMACA6_BC1 *((volatile unsigned int*)(0x42C00E44UL)) +#define bFM3_DMAC_DMACA6_BC2 *((volatile unsigned int*)(0x42C00E48UL)) +#define bFM3_DMAC_DMACA6_BC3 *((volatile unsigned int*)(0x42C00E4CUL)) +#define bFM3_DMAC_DMACA6_IS0 *((volatile unsigned int*)(0x42C00E5CUL)) +#define bFM3_DMAC_DMACA6_IS1 *((volatile unsigned int*)(0x42C00E60UL)) +#define bFM3_DMAC_DMACA6_IS2 *((volatile unsigned int*)(0x42C00E64UL)) +#define bFM3_DMAC_DMACA6_IS3 *((volatile unsigned int*)(0x42C00E68UL)) +#define bFM3_DMAC_DMACA6_IS4 *((volatile unsigned int*)(0x42C00E6CUL)) +#define bFM3_DMAC_DMACA6_IS5 *((volatile unsigned int*)(0x42C00E70UL)) +#define bFM3_DMAC_DMACA6_ST *((volatile unsigned int*)(0x42C00E74UL)) +#define bFM3_DMAC_DMACA6_PB *((volatile unsigned int*)(0x42C00E78UL)) +#define bFM3_DMAC_DMACA6_EB *((volatile unsigned int*)(0x42C00E7CUL)) +#define bFM3_DMAC_DMACB6_EM *((volatile unsigned int*)(0x42C00E80UL)) +#define bFM3_DMAC_DMACB6_SS0 *((volatile unsigned int*)(0x42C00EC0UL)) +#define bFM3_DMAC_DMACB6_SS1 *((volatile unsigned int*)(0x42C00EC4UL)) +#define bFM3_DMAC_DMACB6_SS2 *((volatile unsigned int*)(0x42C00EC8UL)) +#define bFM3_DMAC_DMACB6_CI *((volatile unsigned int*)(0x42C00ECCUL)) +#define bFM3_DMAC_DMACB6_EI *((volatile unsigned int*)(0x42C00ED0UL)) +#define bFM3_DMAC_DMACB6_RD *((volatile unsigned int*)(0x42C00ED4UL)) +#define bFM3_DMAC_DMACB6_RS *((volatile unsigned int*)(0x42C00ED8UL)) +#define bFM3_DMAC_DMACB6_RC *((volatile unsigned int*)(0x42C00EDCUL)) +#define bFM3_DMAC_DMACB6_FD *((volatile unsigned int*)(0x42C00EE0UL)) +#define bFM3_DMAC_DMACB6_FS *((volatile unsigned int*)(0x42C00EE4UL)) +#define bFM3_DMAC_DMACB6_TW0 *((volatile unsigned int*)(0x42C00EE8UL)) +#define bFM3_DMAC_DMACB6_TW1 *((volatile unsigned int*)(0x42C00EECUL)) +#define bFM3_DMAC_DMACB6_MS0 *((volatile unsigned int*)(0x42C00EF0UL)) +#define bFM3_DMAC_DMACB6_MS1 *((volatile unsigned int*)(0x42C00EF4UL)) +#define bFM3_DMAC_DMACA7_TC0 *((volatile unsigned int*)(0x42C01000UL)) +#define bFM3_DMAC_DMACA7_TC1 *((volatile unsigned int*)(0x42C01004UL)) +#define bFM3_DMAC_DMACA7_TC2 *((volatile unsigned int*)(0x42C01008UL)) +#define bFM3_DMAC_DMACA7_TC3 *((volatile unsigned int*)(0x42C0100CUL)) +#define bFM3_DMAC_DMACA7_TC4 *((volatile unsigned int*)(0x42C01010UL)) +#define bFM3_DMAC_DMACA7_TC5 *((volatile unsigned int*)(0x42C01014UL)) +#define bFM3_DMAC_DMACA7_TC6 *((volatile unsigned int*)(0x42C01018UL)) +#define bFM3_DMAC_DMACA7_TC7 *((volatile unsigned int*)(0x42C0101CUL)) +#define bFM3_DMAC_DMACA7_TC8 *((volatile unsigned int*)(0x42C01020UL)) +#define bFM3_DMAC_DMACA7_TC9 *((volatile unsigned int*)(0x42C01024UL)) +#define bFM3_DMAC_DMACA7_TC10 *((volatile unsigned int*)(0x42C01028UL)) +#define bFM3_DMAC_DMACA7_TC11 *((volatile unsigned int*)(0x42C0102CUL)) +#define bFM3_DMAC_DMACA7_TC12 *((volatile unsigned int*)(0x42C01030UL)) +#define bFM3_DMAC_DMACA7_TC13 *((volatile unsigned int*)(0x42C01034UL)) +#define bFM3_DMAC_DMACA7_TC14 *((volatile unsigned int*)(0x42C01038UL)) +#define bFM3_DMAC_DMACA7_TC15 *((volatile unsigned int*)(0x42C0103CUL)) +#define bFM3_DMAC_DMACA7_BC0 *((volatile unsigned int*)(0x42C01040UL)) +#define bFM3_DMAC_DMACA7_BC1 *((volatile unsigned int*)(0x42C01044UL)) +#define bFM3_DMAC_DMACA7_BC2 *((volatile unsigned int*)(0x42C01048UL)) +#define bFM3_DMAC_DMACA7_BC3 *((volatile unsigned int*)(0x42C0104CUL)) +#define bFM3_DMAC_DMACA7_IS0 *((volatile unsigned int*)(0x42C0105CUL)) +#define bFM3_DMAC_DMACA7_IS1 *((volatile unsigned int*)(0x42C01060UL)) +#define bFM3_DMAC_DMACA7_IS2 *((volatile unsigned int*)(0x42C01064UL)) +#define bFM3_DMAC_DMACA7_IS3 *((volatile unsigned int*)(0x42C01068UL)) +#define bFM3_DMAC_DMACA7_IS4 *((volatile unsigned int*)(0x42C0106CUL)) +#define bFM3_DMAC_DMACA7_IS5 *((volatile unsigned int*)(0x42C01070UL)) +#define bFM3_DMAC_DMACA7_ST *((volatile unsigned int*)(0x42C01074UL)) +#define bFM3_DMAC_DMACA7_PB *((volatile unsigned int*)(0x42C01078UL)) +#define bFM3_DMAC_DMACA7_EB *((volatile unsigned int*)(0x42C0107CUL)) +#define bFM3_DMAC_DMACB7_EM *((volatile unsigned int*)(0x42C01080UL)) +#define bFM3_DMAC_DMACB7_SS0 *((volatile unsigned int*)(0x42C010C0UL)) +#define bFM3_DMAC_DMACB7_SS1 *((volatile unsigned int*)(0x42C010C4UL)) +#define bFM3_DMAC_DMACB7_SS2 *((volatile unsigned int*)(0x42C010C8UL)) +#define bFM3_DMAC_DMACB7_CI *((volatile unsigned int*)(0x42C010CCUL)) +#define bFM3_DMAC_DMACB7_EI *((volatile unsigned int*)(0x42C010D0UL)) +#define bFM3_DMAC_DMACB7_RD *((volatile unsigned int*)(0x42C010D4UL)) +#define bFM3_DMAC_DMACB7_RS *((volatile unsigned int*)(0x42C010D8UL)) +#define bFM3_DMAC_DMACB7_RC *((volatile unsigned int*)(0x42C010DCUL)) +#define bFM3_DMAC_DMACB7_FD *((volatile unsigned int*)(0x42C010E0UL)) +#define bFM3_DMAC_DMACB7_FS *((volatile unsigned int*)(0x42C010E4UL)) +#define bFM3_DMAC_DMACB7_TW0 *((volatile unsigned int*)(0x42C010E8UL)) +#define bFM3_DMAC_DMACB7_TW1 *((volatile unsigned int*)(0x42C010ECUL)) +#define bFM3_DMAC_DMACB7_MS0 *((volatile unsigned int*)(0x42C010F0UL)) +#define bFM3_DMAC_DMACB7_MS1 *((volatile unsigned int*)(0x42C010F4UL)) + +/* CAN channel 0 registers */ +#define bFM3_CAN0_CTRLR_INIT *((volatile unsigned int*)(0x42C40000UL)) +#define bFM3_CAN0_CTRLR_IE *((volatile unsigned int*)(0x42C40004UL)) +#define bFM3_CAN0_CTRLR_SIE *((volatile unsigned int*)(0x42C40008UL)) +#define bFM3_CAN0_CTRLR_EIE *((volatile unsigned int*)(0x42C4000CUL)) +#define bFM3_CAN0_CTRLR_DAR *((volatile unsigned int*)(0x42C40014UL)) +#define bFM3_CAN0_CTRLR_CCE *((volatile unsigned int*)(0x42C40018UL)) +#define bFM3_CAN0_CTRLR_TEST *((volatile unsigned int*)(0x42C4001CUL)) +#define bFM3_CAN0_STATR_LEC0 *((volatile unsigned int*)(0x42C40040UL)) +#define bFM3_CAN0_STATR_LEC1 *((volatile unsigned int*)(0x42C40044UL)) +#define bFM3_CAN0_STATR_LEC2 *((volatile unsigned int*)(0x42C40048UL)) +#define bFM3_CAN0_STATR_TXOK *((volatile unsigned int*)(0x42C4004CUL)) +#define bFM3_CAN0_STATR_RXOK *((volatile unsigned int*)(0x42C40050UL)) +#define bFM3_CAN0_STATR_EPASS *((volatile unsigned int*)(0x42C40054UL)) +#define bFM3_CAN0_STATR_EWARM *((volatile unsigned int*)(0x42C40058UL)) +#define bFM3_CAN0_STATR_BOFF *((volatile unsigned int*)(0x42C4005CUL)) +#define bFM3_CAN0_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C40080UL)) +#define bFM3_CAN0_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C40084UL)) +#define bFM3_CAN0_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C40088UL)) +#define bFM3_CAN0_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C4008CUL)) +#define bFM3_CAN0_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C40090UL)) +#define bFM3_CAN0_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C40094UL)) +#define bFM3_CAN0_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C40098UL)) +#define bFM3_CAN0_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C4009CUL)) +#define bFM3_CAN0_ERRCNT_REC0 *((volatile unsigned int*)(0x42C400A0UL)) +#define bFM3_CAN0_ERRCNT_REC1 *((volatile unsigned int*)(0x42C400A4UL)) +#define bFM3_CAN0_ERRCNT_REC2 *((volatile unsigned int*)(0x42C400A8UL)) +#define bFM3_CAN0_ERRCNT_REC3 *((volatile unsigned int*)(0x42C400ACUL)) +#define bFM3_CAN0_ERRCNT_REC4 *((volatile unsigned int*)(0x42C400B0UL)) +#define bFM3_CAN0_ERRCNT_REC5 *((volatile unsigned int*)(0x42C400B4UL)) +#define bFM3_CAN0_ERRCNT_REC6 *((volatile unsigned int*)(0x42C400B8UL)) +#define bFM3_CAN0_ERRCNT_RP *((volatile unsigned int*)(0x42C400BCUL)) +#define bFM3_CAN0_BTR_BRP0 *((volatile unsigned int*)(0x42C400C0UL)) +#define bFM3_CAN0_BTR_BRP1 *((volatile unsigned int*)(0x42C400C4UL)) +#define bFM3_CAN0_BTR_BRP2 *((volatile unsigned int*)(0x42C400C8UL)) +#define bFM3_CAN0_BTR_BRP3 *((volatile unsigned int*)(0x42C400CCUL)) +#define bFM3_CAN0_BTR_BRP4 *((volatile unsigned int*)(0x42C400D0UL)) +#define bFM3_CAN0_BTR_BRP5 *((volatile unsigned int*)(0x42C400D4UL)) +#define bFM3_CAN0_BTR_SJW0 *((volatile unsigned int*)(0x42C400D8UL)) +#define bFM3_CAN0_BTR_SJW1 *((volatile unsigned int*)(0x42C400DCUL)) +#define bFM3_CAN0_BTR_TSEG10 *((volatile unsigned int*)(0x42C400E0UL)) +#define bFM3_CAN0_BTR_TSEG11 *((volatile unsigned int*)(0x42C400E4UL)) +#define bFM3_CAN0_BTR_TSEG12 *((volatile unsigned int*)(0x42C400E8UL)) +#define bFM3_CAN0_BTR_TSEG13 *((volatile unsigned int*)(0x42C400ECUL)) +#define bFM3_CAN0_BTR_TSEG20 *((volatile unsigned int*)(0x42C400F0UL)) +#define bFM3_CAN0_BTR_TSEG21 *((volatile unsigned int*)(0x42C400F4UL)) +#define bFM3_CAN0_BTR_TSEG22 *((volatile unsigned int*)(0x42C400F8UL)) +#define bFM3_CAN0_INTR_INTID0 *((volatile unsigned int*)(0x42C40100UL)) +#define bFM3_CAN0_INTR_INTID1 *((volatile unsigned int*)(0x42C40104UL)) +#define bFM3_CAN0_INTR_INTID2 *((volatile unsigned int*)(0x42C40108UL)) +#define bFM3_CAN0_INTR_INTID3 *((volatile unsigned int*)(0x42C4010CUL)) +#define bFM3_CAN0_INTR_INTID4 *((volatile unsigned int*)(0x42C40110UL)) +#define bFM3_CAN0_INTR_INTID5 *((volatile unsigned int*)(0x42C40114UL)) +#define bFM3_CAN0_INTR_INTID6 *((volatile unsigned int*)(0x42C40118UL)) +#define bFM3_CAN0_INTR_INTID7 *((volatile unsigned int*)(0x42C4011CUL)) +#define bFM3_CAN0_INTR_INTID8 *((volatile unsigned int*)(0x42C40120UL)) +#define bFM3_CAN0_INTR_INTID9 *((volatile unsigned int*)(0x42C40124UL)) +#define bFM3_CAN0_INTR_INTID10 *((volatile unsigned int*)(0x42C40128UL)) +#define bFM3_CAN0_INTR_INTID11 *((volatile unsigned int*)(0x42C4012CUL)) +#define bFM3_CAN0_INTR_INTID12 *((volatile unsigned int*)(0x42C40130UL)) +#define bFM3_CAN0_INTR_INTID13 *((volatile unsigned int*)(0x42C40134UL)) +#define bFM3_CAN0_INTR_INTID14 *((volatile unsigned int*)(0x42C40138UL)) +#define bFM3_CAN0_INTR_INTID15 *((volatile unsigned int*)(0x42C4013CUL)) +#define bFM3_CAN0_TESTR_BASIC *((volatile unsigned int*)(0x42C40148UL)) +#define bFM3_CAN0_TESTR_SILENT *((volatile unsigned int*)(0x42C4014CUL)) +#define bFM3_CAN0_TESTR_LBACK *((volatile unsigned int*)(0x42C40150UL)) +#define bFM3_CAN0_TESTR_TX0 *((volatile unsigned int*)(0x42C40154UL)) +#define bFM3_CAN0_TESTR_TX1 *((volatile unsigned int*)(0x42C40158UL)) +#define bFM3_CAN0_TESTR_RX *((volatile unsigned int*)(0x42C4015CUL)) +#define bFM3_CAN0_BRPER_BRPE0 *((volatile unsigned int*)(0x42C40180UL)) +#define bFM3_CAN0_BRPER_BRPE1 *((volatile unsigned int*)(0x42C40184UL)) +#define bFM3_CAN0_BRPER_BRPE2 *((volatile unsigned int*)(0x42C40188UL)) +#define bFM3_CAN0_BRPER_BRPE3 *((volatile unsigned int*)(0x42C4018CUL)) +#define bFM3_CAN0_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C4023CUL)) +#define bFM3_CAN0_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C40240UL)) +#define bFM3_CAN0_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C40244UL)) +#define bFM3_CAN0_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C40248UL)) +#define bFM3_CAN0_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C40248UL)) +#define bFM3_CAN0_IF1CMSK_CIP *((volatile unsigned int*)(0x42C4024CUL)) +#define bFM3_CAN0_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C40250UL)) +#define bFM3_CAN0_IF1CMSK_ARB *((volatile unsigned int*)(0x42C40254UL)) +#define bFM3_CAN0_IF1CMSK_MASK *((volatile unsigned int*)(0x42C40258UL)) +#define bFM3_CAN0_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C4025CUL)) +#define bFM3_CAN0_IF1MSK_MDIR *((volatile unsigned int*)(0x42C402F8UL)) +#define bFM3_CAN0_IF1MSK_MXTD *((volatile unsigned int*)(0x42C402FCUL)) +#define bFM3_CAN0_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C402F8UL)) +#define bFM3_CAN0_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C402FCUL)) +#define bFM3_CAN0_IF1ARB_DIR *((volatile unsigned int*)(0x42C40374UL)) +#define bFM3_CAN0_IF1ARB_XTD *((volatile unsigned int*)(0x42C40378UL)) +#define bFM3_CAN0_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) +#define bFM3_CAN0_IF1ARB2_DIR *((volatile unsigned int*)(0x42C40374UL)) +#define bFM3_CAN0_IF1ARB2_XTD *((volatile unsigned int*)(0x42C40378UL)) +#define bFM3_CAN0_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) +#define bFM3_CAN0_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C40380UL)) +#define bFM3_CAN0_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C40384UL)) +#define bFM3_CAN0_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C40388UL)) +#define bFM3_CAN0_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C4038CUL)) +#define bFM3_CAN0_IF1MCTR_EOB *((volatile unsigned int*)(0x42C4039CUL)) +#define bFM3_CAN0_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C403A0UL)) +#define bFM3_CAN0_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C403A4UL)) +#define bFM3_CAN0_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C403A8UL)) +#define bFM3_CAN0_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C403ACUL)) +#define bFM3_CAN0_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C403B0UL)) +#define bFM3_CAN0_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C403B4UL)) +#define bFM3_CAN0_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C403B8UL)) +#define bFM3_CAN0_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C403BCUL)) +#define bFM3_CAN0_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C4083CUL)) +#define bFM3_CAN0_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C40840UL)) +#define bFM3_CAN0_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C40844UL)) +#define bFM3_CAN0_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C40848UL)) +#define bFM3_CAN0_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C40848UL)) +#define bFM3_CAN0_IF2CMSK_CIP *((volatile unsigned int*)(0x42C4084CUL)) +#define bFM3_CAN0_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C40850UL)) +#define bFM3_CAN0_IF2CMSK_ARB *((volatile unsigned int*)(0x42C40854UL)) +#define bFM3_CAN0_IF2CMSK_MASK *((volatile unsigned int*)(0x42C40858UL)) +#define bFM3_CAN0_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C4085CUL)) +#define bFM3_CAN0_IF2MSK_MDIR *((volatile unsigned int*)(0x42C408F8UL)) +#define bFM3_CAN0_IF2MSK_MXTD *((volatile unsigned int*)(0x42C408FCUL)) +#define bFM3_CAN0_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C408F8UL)) +#define bFM3_CAN0_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C408FCUL)) +#define bFM3_CAN0_IF2ARB_DIR *((volatile unsigned int*)(0x42C40974UL)) +#define bFM3_CAN0_IF2ARB_XTD *((volatile unsigned int*)(0x42C40978UL)) +#define bFM3_CAN0_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) +#define bFM3_CAN0_IF2ARB2_DIR *((volatile unsigned int*)(0x42C40974UL)) +#define bFM3_CAN0_IF2ARB2_XTD *((volatile unsigned int*)(0x42C40978UL)) +#define bFM3_CAN0_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) +#define bFM3_CAN0_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C40980UL)) +#define bFM3_CAN0_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C40984UL)) +#define bFM3_CAN0_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C40988UL)) +#define bFM3_CAN0_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C4098CUL)) +#define bFM3_CAN0_IF2MCTR_EOB *((volatile unsigned int*)(0x42C4099CUL)) +#define bFM3_CAN0_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C409A0UL)) +#define bFM3_CAN0_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C409A4UL)) +#define bFM3_CAN0_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C409A8UL)) +#define bFM3_CAN0_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C409ACUL)) +#define bFM3_CAN0_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C409B0UL)) +#define bFM3_CAN0_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C409B4UL)) +#define bFM3_CAN0_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C409B8UL)) +#define bFM3_CAN0_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C409BCUL)) +#define bFM3_CAN0_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) +#define bFM3_CAN0_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) +#define bFM3_CAN0_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) +#define bFM3_CAN0_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) +#define bFM3_CAN0_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) +#define bFM3_CAN0_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) +#define bFM3_CAN0_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) +#define bFM3_CAN0_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) +#define bFM3_CAN0_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) +#define bFM3_CAN0_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) +#define bFM3_CAN0_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) +#define bFM3_CAN0_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) +#define bFM3_CAN0_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) +#define bFM3_CAN0_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) +#define bFM3_CAN0_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) +#define bFM3_CAN0_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) +#define bFM3_CAN0_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) +#define bFM3_CAN0_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) +#define bFM3_CAN0_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) +#define bFM3_CAN0_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) +#define bFM3_CAN0_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) +#define bFM3_CAN0_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) +#define bFM3_CAN0_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) +#define bFM3_CAN0_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) +#define bFM3_CAN0_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) +#define bFM3_CAN0_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) +#define bFM3_CAN0_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) +#define bFM3_CAN0_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) +#define bFM3_CAN0_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) +#define bFM3_CAN0_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) +#define bFM3_CAN0_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) +#define bFM3_CAN0_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) +#define bFM3_CAN0_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) +#define bFM3_CAN0_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) +#define bFM3_CAN0_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) +#define bFM3_CAN0_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) +#define bFM3_CAN0_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) +#define bFM3_CAN0_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) +#define bFM3_CAN0_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) +#define bFM3_CAN0_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) +#define bFM3_CAN0_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) +#define bFM3_CAN0_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) +#define bFM3_CAN0_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) +#define bFM3_CAN0_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) +#define bFM3_CAN0_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) +#define bFM3_CAN0_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) +#define bFM3_CAN0_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) +#define bFM3_CAN0_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) +#define bFM3_CAN0_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) +#define bFM3_CAN0_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) +#define bFM3_CAN0_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) +#define bFM3_CAN0_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) +#define bFM3_CAN0_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) +#define bFM3_CAN0_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) +#define bFM3_CAN0_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) +#define bFM3_CAN0_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) +#define bFM3_CAN0_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) +#define bFM3_CAN0_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) +#define bFM3_CAN0_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) +#define bFM3_CAN0_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) +#define bFM3_CAN0_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) +#define bFM3_CAN0_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) +#define bFM3_CAN0_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) +#define bFM3_CAN0_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) +#define bFM3_CAN0_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) +#define bFM3_CAN0_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) +#define bFM3_CAN0_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) +#define bFM3_CAN0_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) +#define bFM3_CAN0_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) +#define bFM3_CAN0_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) +#define bFM3_CAN0_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) +#define bFM3_CAN0_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) +#define bFM3_CAN0_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) +#define bFM3_CAN0_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) +#define bFM3_CAN0_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) +#define bFM3_CAN0_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) +#define bFM3_CAN0_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) +#define bFM3_CAN0_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) +#define bFM3_CAN0_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) +#define bFM3_CAN0_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) +#define bFM3_CAN0_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) +#define bFM3_CAN0_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) +#define bFM3_CAN0_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) +#define bFM3_CAN0_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) +#define bFM3_CAN0_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) +#define bFM3_CAN0_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) +#define bFM3_CAN0_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) +#define bFM3_CAN0_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) +#define bFM3_CAN0_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) +#define bFM3_CAN0_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) +#define bFM3_CAN0_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) +#define bFM3_CAN0_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) +#define bFM3_CAN0_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) +#define bFM3_CAN0_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) +#define bFM3_CAN0_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) +#define bFM3_CAN0_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) +#define bFM3_CAN0_INTPND_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) +#define bFM3_CAN0_INTPND_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) +#define bFM3_CAN0_INTPND_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) +#define bFM3_CAN0_INTPND_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) +#define bFM3_CAN0_INTPND_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) +#define bFM3_CAN0_INTPND_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) +#define bFM3_CAN0_INTPND_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) +#define bFM3_CAN0_INTPND_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) +#define bFM3_CAN0_INTPND_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) +#define bFM3_CAN0_INTPND_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) +#define bFM3_CAN0_INTPND_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) +#define bFM3_CAN0_INTPND_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) +#define bFM3_CAN0_INTPND_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) +#define bFM3_CAN0_INTPND_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) +#define bFM3_CAN0_INTPND_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) +#define bFM3_CAN0_INTPND_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) +#define bFM3_CAN0_INTPND_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) +#define bFM3_CAN0_INTPND_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) +#define bFM3_CAN0_INTPND_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) +#define bFM3_CAN0_INTPND_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) +#define bFM3_CAN0_INTPND_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) +#define bFM3_CAN0_INTPND_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) +#define bFM3_CAN0_INTPND_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) +#define bFM3_CAN0_INTPND_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) +#define bFM3_CAN0_INTPND_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) +#define bFM3_CAN0_INTPND_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) +#define bFM3_CAN0_INTPND_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) +#define bFM3_CAN0_INTPND_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) +#define bFM3_CAN0_INTPND_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) +#define bFM3_CAN0_INTPND_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) +#define bFM3_CAN0_INTPND_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) +#define bFM3_CAN0_INTPND_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) +#define bFM3_CAN0_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) +#define bFM3_CAN0_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) +#define bFM3_CAN0_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) +#define bFM3_CAN0_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) +#define bFM3_CAN0_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) +#define bFM3_CAN0_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) +#define bFM3_CAN0_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) +#define bFM3_CAN0_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) +#define bFM3_CAN0_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) +#define bFM3_CAN0_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) +#define bFM3_CAN0_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) +#define bFM3_CAN0_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) +#define bFM3_CAN0_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) +#define bFM3_CAN0_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) +#define bFM3_CAN0_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) +#define bFM3_CAN0_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) +#define bFM3_CAN0_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) +#define bFM3_CAN0_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) +#define bFM3_CAN0_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) +#define bFM3_CAN0_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) +#define bFM3_CAN0_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) +#define bFM3_CAN0_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) +#define bFM3_CAN0_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) +#define bFM3_CAN0_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) +#define bFM3_CAN0_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) +#define bFM3_CAN0_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) +#define bFM3_CAN0_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) +#define bFM3_CAN0_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) +#define bFM3_CAN0_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) +#define bFM3_CAN0_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) +#define bFM3_CAN0_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) +#define bFM3_CAN0_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) + +/* CAN channel 1 registers */ +#define bFM3_CAN1_CTRLR_INIT *((volatile unsigned int*)(0x42C60000UL)) +#define bFM3_CAN1_CTRLR_IE *((volatile unsigned int*)(0x42C60004UL)) +#define bFM3_CAN1_CTRLR_SIE *((volatile unsigned int*)(0x42C60008UL)) +#define bFM3_CAN1_CTRLR_EIE *((volatile unsigned int*)(0x42C6000CUL)) +#define bFM3_CAN1_CTRLR_DAR *((volatile unsigned int*)(0x42C60014UL)) +#define bFM3_CAN1_CTRLR_CCE *((volatile unsigned int*)(0x42C60018UL)) +#define bFM3_CAN1_CTRLR_TEST *((volatile unsigned int*)(0x42C6001CUL)) +#define bFM3_CAN1_STATR_LEC0 *((volatile unsigned int*)(0x42C60040UL)) +#define bFM3_CAN1_STATR_LEC1 *((volatile unsigned int*)(0x42C60044UL)) +#define bFM3_CAN1_STATR_LEC2 *((volatile unsigned int*)(0x42C60048UL)) +#define bFM3_CAN1_STATR_TXOK *((volatile unsigned int*)(0x42C6004CUL)) +#define bFM3_CAN1_STATR_RXOK *((volatile unsigned int*)(0x42C60050UL)) +#define bFM3_CAN1_STATR_EPASS *((volatile unsigned int*)(0x42C60054UL)) +#define bFM3_CAN1_STATR_EWARM *((volatile unsigned int*)(0x42C60058UL)) +#define bFM3_CAN1_STATR_BOFF *((volatile unsigned int*)(0x42C6005CUL)) +#define bFM3_CAN1_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C60080UL)) +#define bFM3_CAN1_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C60084UL)) +#define bFM3_CAN1_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C60088UL)) +#define bFM3_CAN1_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C6008CUL)) +#define bFM3_CAN1_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C60090UL)) +#define bFM3_CAN1_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C60094UL)) +#define bFM3_CAN1_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C60098UL)) +#define bFM3_CAN1_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C6009CUL)) +#define bFM3_CAN1_ERRCNT_REC0 *((volatile unsigned int*)(0x42C600A0UL)) +#define bFM3_CAN1_ERRCNT_REC1 *((volatile unsigned int*)(0x42C600A4UL)) +#define bFM3_CAN1_ERRCNT_REC2 *((volatile unsigned int*)(0x42C600A8UL)) +#define bFM3_CAN1_ERRCNT_REC3 *((volatile unsigned int*)(0x42C600ACUL)) +#define bFM3_CAN1_ERRCNT_REC4 *((volatile unsigned int*)(0x42C600B0UL)) +#define bFM3_CAN1_ERRCNT_REC5 *((volatile unsigned int*)(0x42C600B4UL)) +#define bFM3_CAN1_ERRCNT_REC6 *((volatile unsigned int*)(0x42C600B8UL)) +#define bFM3_CAN1_ERRCNT_RP *((volatile unsigned int*)(0x42C600BCUL)) +#define bFM3_CAN1_BTR_BRP0 *((volatile unsigned int*)(0x42C600C0UL)) +#define bFM3_CAN1_BTR_BRP1 *((volatile unsigned int*)(0x42C600C4UL)) +#define bFM3_CAN1_BTR_BRP2 *((volatile unsigned int*)(0x42C600C8UL)) +#define bFM3_CAN1_BTR_BRP3 *((volatile unsigned int*)(0x42C600CCUL)) +#define bFM3_CAN1_BTR_BRP4 *((volatile unsigned int*)(0x42C600D0UL)) +#define bFM3_CAN1_BTR_BRP5 *((volatile unsigned int*)(0x42C600D4UL)) +#define bFM3_CAN1_BTR_SJW0 *((volatile unsigned int*)(0x42C600D8UL)) +#define bFM3_CAN1_BTR_SJW1 *((volatile unsigned int*)(0x42C600DCUL)) +#define bFM3_CAN1_BTR_TSEG10 *((volatile unsigned int*)(0x42C600E0UL)) +#define bFM3_CAN1_BTR_TSEG11 *((volatile unsigned int*)(0x42C600E4UL)) +#define bFM3_CAN1_BTR_TSEG12 *((volatile unsigned int*)(0x42C600E8UL)) +#define bFM3_CAN1_BTR_TSEG13 *((volatile unsigned int*)(0x42C600ECUL)) +#define bFM3_CAN1_BTR_TSEG20 *((volatile unsigned int*)(0x42C600F0UL)) +#define bFM3_CAN1_BTR_TSEG21 *((volatile unsigned int*)(0x42C600F4UL)) +#define bFM3_CAN1_BTR_TSEG22 *((volatile unsigned int*)(0x42C600F8UL)) +#define bFM3_CAN1_INTR_INTID0 *((volatile unsigned int*)(0x42C60100UL)) +#define bFM3_CAN1_INTR_INTID1 *((volatile unsigned int*)(0x42C60104UL)) +#define bFM3_CAN1_INTR_INTID2 *((volatile unsigned int*)(0x42C60108UL)) +#define bFM3_CAN1_INTR_INTID3 *((volatile unsigned int*)(0x42C6010CUL)) +#define bFM3_CAN1_INTR_INTID4 *((volatile unsigned int*)(0x42C60110UL)) +#define bFM3_CAN1_INTR_INTID5 *((volatile unsigned int*)(0x42C60114UL)) +#define bFM3_CAN1_INTR_INTID6 *((volatile unsigned int*)(0x42C60118UL)) +#define bFM3_CAN1_INTR_INTID7 *((volatile unsigned int*)(0x42C6011CUL)) +#define bFM3_CAN1_INTR_INTID8 *((volatile unsigned int*)(0x42C60120UL)) +#define bFM3_CAN1_INTR_INTID9 *((volatile unsigned int*)(0x42C60124UL)) +#define bFM3_CAN1_INTR_INTID10 *((volatile unsigned int*)(0x42C60128UL)) +#define bFM3_CAN1_INTR_INTID11 *((volatile unsigned int*)(0x42C6012CUL)) +#define bFM3_CAN1_INTR_INTID12 *((volatile unsigned int*)(0x42C60130UL)) +#define bFM3_CAN1_INTR_INTID13 *((volatile unsigned int*)(0x42C60134UL)) +#define bFM3_CAN1_INTR_INTID14 *((volatile unsigned int*)(0x42C60138UL)) +#define bFM3_CAN1_INTR_INTID15 *((volatile unsigned int*)(0x42C6013CUL)) +#define bFM3_CAN1_TESTR_BASIC *((volatile unsigned int*)(0x42C60148UL)) +#define bFM3_CAN1_TESTR_SILENT *((volatile unsigned int*)(0x42C6014CUL)) +#define bFM3_CAN1_TESTR_LBACK *((volatile unsigned int*)(0x42C60150UL)) +#define bFM3_CAN1_TESTR_TX0 *((volatile unsigned int*)(0x42C60154UL)) +#define bFM3_CAN1_TESTR_TX1 *((volatile unsigned int*)(0x42C60158UL)) +#define bFM3_CAN1_TESTR_RX *((volatile unsigned int*)(0x42C6015CUL)) +#define bFM3_CAN1_BRPER_BRPE0 *((volatile unsigned int*)(0x42C60180UL)) +#define bFM3_CAN1_BRPER_BRPE1 *((volatile unsigned int*)(0x42C60184UL)) +#define bFM3_CAN1_BRPER_BRPE2 *((volatile unsigned int*)(0x42C60188UL)) +#define bFM3_CAN1_BRPER_BRPE3 *((volatile unsigned int*)(0x42C6018CUL)) +#define bFM3_CAN1_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C6023CUL)) +#define bFM3_CAN1_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C60240UL)) +#define bFM3_CAN1_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C60244UL)) +#define bFM3_CAN1_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C60248UL)) +#define bFM3_CAN1_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C60248UL)) +#define bFM3_CAN1_IF1CMSK_CIP *((volatile unsigned int*)(0x42C6024CUL)) +#define bFM3_CAN1_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C60250UL)) +#define bFM3_CAN1_IF1CMSK_ARB *((volatile unsigned int*)(0x42C60254UL)) +#define bFM3_CAN1_IF1CMSK_MASK *((volatile unsigned int*)(0x42C60258UL)) +#define bFM3_CAN1_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C6025CUL)) +#define bFM3_CAN1_IF1MSK_MDIR *((volatile unsigned int*)(0x42C602F8UL)) +#define bFM3_CAN1_IF1MSK_MXTD *((volatile unsigned int*)(0x42C602FCUL)) +#define bFM3_CAN1_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C602F8UL)) +#define bFM3_CAN1_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C602FCUL)) +#define bFM3_CAN1_IF1ARB_DIR *((volatile unsigned int*)(0x42C60374UL)) +#define bFM3_CAN1_IF1ARB_XTD *((volatile unsigned int*)(0x42C60378UL)) +#define bFM3_CAN1_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) +#define bFM3_CAN1_IF1ARB2_DIR *((volatile unsigned int*)(0x42C60374UL)) +#define bFM3_CAN1_IF1ARB2_XTD *((volatile unsigned int*)(0x42C60378UL)) +#define bFM3_CAN1_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) +#define bFM3_CAN1_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C60380UL)) +#define bFM3_CAN1_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C60384UL)) +#define bFM3_CAN1_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C60388UL)) +#define bFM3_CAN1_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C6038CUL)) +#define bFM3_CAN1_IF1MCTR_EOB *((volatile unsigned int*)(0x42C6039CUL)) +#define bFM3_CAN1_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C603A0UL)) +#define bFM3_CAN1_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C603A4UL)) +#define bFM3_CAN1_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C603A8UL)) +#define bFM3_CAN1_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C603ACUL)) +#define bFM3_CAN1_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C603B0UL)) +#define bFM3_CAN1_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C603B4UL)) +#define bFM3_CAN1_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C603B8UL)) +#define bFM3_CAN1_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C603BCUL)) +#define bFM3_CAN1_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C6083CUL)) +#define bFM3_CAN1_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C60840UL)) +#define bFM3_CAN1_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C60844UL)) +#define bFM3_CAN1_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C60848UL)) +#define bFM3_CAN1_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C60848UL)) +#define bFM3_CAN1_IF2CMSK_CIP *((volatile unsigned int*)(0x42C6084CUL)) +#define bFM3_CAN1_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C60850UL)) +#define bFM3_CAN1_IF2CMSK_ARB *((volatile unsigned int*)(0x42C60854UL)) +#define bFM3_CAN1_IF2CMSK_MASK *((volatile unsigned int*)(0x42C60858UL)) +#define bFM3_CAN1_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C6085CUL)) +#define bFM3_CAN1_IF2MSK_MDIR *((volatile unsigned int*)(0x42C608F8UL)) +#define bFM3_CAN1_IF2MSK_MXTD *((volatile unsigned int*)(0x42C608FCUL)) +#define bFM3_CAN1_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C608F8UL)) +#define bFM3_CAN1_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C608FCUL)) +#define bFM3_CAN1_IF2ARB_DIR *((volatile unsigned int*)(0x42C60974UL)) +#define bFM3_CAN1_IF2ARB_XTD *((volatile unsigned int*)(0x42C60978UL)) +#define bFM3_CAN1_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) +#define bFM3_CAN1_IF2ARB2_DIR *((volatile unsigned int*)(0x42C60974UL)) +#define bFM3_CAN1_IF2ARB2_XTD *((volatile unsigned int*)(0x42C60978UL)) +#define bFM3_CAN1_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) +#define bFM3_CAN1_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C60980UL)) +#define bFM3_CAN1_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C60984UL)) +#define bFM3_CAN1_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C60988UL)) +#define bFM3_CAN1_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C6098CUL)) +#define bFM3_CAN1_IF2MCTR_EOB *((volatile unsigned int*)(0x42C6099CUL)) +#define bFM3_CAN1_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C609A0UL)) +#define bFM3_CAN1_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C609A4UL)) +#define bFM3_CAN1_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C609A8UL)) +#define bFM3_CAN1_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C609ACUL)) +#define bFM3_CAN1_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C609B0UL)) +#define bFM3_CAN1_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C609B4UL)) +#define bFM3_CAN1_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C609B8UL)) +#define bFM3_CAN1_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C609BCUL)) +#define bFM3_CAN1_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) +#define bFM3_CAN1_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) +#define bFM3_CAN1_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) +#define bFM3_CAN1_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) +#define bFM3_CAN1_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) +#define bFM3_CAN1_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) +#define bFM3_CAN1_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) +#define bFM3_CAN1_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) +#define bFM3_CAN1_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) +#define bFM3_CAN1_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) +#define bFM3_CAN1_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) +#define bFM3_CAN1_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) +#define bFM3_CAN1_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) +#define bFM3_CAN1_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) +#define bFM3_CAN1_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) +#define bFM3_CAN1_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) +#define bFM3_CAN1_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) +#define bFM3_CAN1_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) +#define bFM3_CAN1_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) +#define bFM3_CAN1_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) +#define bFM3_CAN1_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) +#define bFM3_CAN1_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) +#define bFM3_CAN1_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) +#define bFM3_CAN1_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) +#define bFM3_CAN1_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) +#define bFM3_CAN1_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) +#define bFM3_CAN1_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) +#define bFM3_CAN1_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) +#define bFM3_CAN1_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) +#define bFM3_CAN1_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) +#define bFM3_CAN1_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) +#define bFM3_CAN1_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) +#define bFM3_CAN1_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) +#define bFM3_CAN1_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) +#define bFM3_CAN1_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) +#define bFM3_CAN1_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) +#define bFM3_CAN1_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) +#define bFM3_CAN1_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) +#define bFM3_CAN1_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) +#define bFM3_CAN1_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) +#define bFM3_CAN1_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) +#define bFM3_CAN1_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) +#define bFM3_CAN1_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) +#define bFM3_CAN1_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) +#define bFM3_CAN1_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) +#define bFM3_CAN1_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) +#define bFM3_CAN1_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) +#define bFM3_CAN1_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) +#define bFM3_CAN1_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) +#define bFM3_CAN1_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) +#define bFM3_CAN1_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) +#define bFM3_CAN1_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) +#define bFM3_CAN1_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) +#define bFM3_CAN1_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) +#define bFM3_CAN1_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) +#define bFM3_CAN1_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) +#define bFM3_CAN1_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) +#define bFM3_CAN1_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) +#define bFM3_CAN1_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) +#define bFM3_CAN1_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) +#define bFM3_CAN1_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) +#define bFM3_CAN1_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) +#define bFM3_CAN1_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) +#define bFM3_CAN1_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) +#define bFM3_CAN1_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) +#define bFM3_CAN1_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) +#define bFM3_CAN1_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) +#define bFM3_CAN1_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) +#define bFM3_CAN1_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) +#define bFM3_CAN1_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) +#define bFM3_CAN1_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) +#define bFM3_CAN1_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) +#define bFM3_CAN1_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) +#define bFM3_CAN1_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) +#define bFM3_CAN1_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) +#define bFM3_CAN1_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) +#define bFM3_CAN1_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) +#define bFM3_CAN1_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) +#define bFM3_CAN1_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) +#define bFM3_CAN1_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) +#define bFM3_CAN1_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) +#define bFM3_CAN1_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) +#define bFM3_CAN1_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) +#define bFM3_CAN1_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) +#define bFM3_CAN1_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) +#define bFM3_CAN1_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) +#define bFM3_CAN1_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) +#define bFM3_CAN1_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) +#define bFM3_CAN1_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) +#define bFM3_CAN1_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) +#define bFM3_CAN1_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) +#define bFM3_CAN1_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) +#define bFM3_CAN1_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) +#define bFM3_CAN1_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) +#define bFM3_CAN1_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) +#define bFM3_CAN1_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) +#define bFM3_CAN1_INTPND_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) +#define bFM3_CAN1_INTPND_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) +#define bFM3_CAN1_INTPND_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) +#define bFM3_CAN1_INTPND_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) +#define bFM3_CAN1_INTPND_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) +#define bFM3_CAN1_INTPND_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) +#define bFM3_CAN1_INTPND_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) +#define bFM3_CAN1_INTPND_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) +#define bFM3_CAN1_INTPND_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) +#define bFM3_CAN1_INTPND_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) +#define bFM3_CAN1_INTPND_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) +#define bFM3_CAN1_INTPND_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) +#define bFM3_CAN1_INTPND_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) +#define bFM3_CAN1_INTPND_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) +#define bFM3_CAN1_INTPND_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) +#define bFM3_CAN1_INTPND_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) +#define bFM3_CAN1_INTPND_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) +#define bFM3_CAN1_INTPND_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) +#define bFM3_CAN1_INTPND_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) +#define bFM3_CAN1_INTPND_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) +#define bFM3_CAN1_INTPND_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) +#define bFM3_CAN1_INTPND_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) +#define bFM3_CAN1_INTPND_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) +#define bFM3_CAN1_INTPND_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) +#define bFM3_CAN1_INTPND_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) +#define bFM3_CAN1_INTPND_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) +#define bFM3_CAN1_INTPND_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) +#define bFM3_CAN1_INTPND_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) +#define bFM3_CAN1_INTPND_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) +#define bFM3_CAN1_INTPND_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) +#define bFM3_CAN1_INTPND_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) +#define bFM3_CAN1_INTPND_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) +#define bFM3_CAN1_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) +#define bFM3_CAN1_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) +#define bFM3_CAN1_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) +#define bFM3_CAN1_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) +#define bFM3_CAN1_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) +#define bFM3_CAN1_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) +#define bFM3_CAN1_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) +#define bFM3_CAN1_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) +#define bFM3_CAN1_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) +#define bFM3_CAN1_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) +#define bFM3_CAN1_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) +#define bFM3_CAN1_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) +#define bFM3_CAN1_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) +#define bFM3_CAN1_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) +#define bFM3_CAN1_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) +#define bFM3_CAN1_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) +#define bFM3_CAN1_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) +#define bFM3_CAN1_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) +#define bFM3_CAN1_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) +#define bFM3_CAN1_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) +#define bFM3_CAN1_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) +#define bFM3_CAN1_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) +#define bFM3_CAN1_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) +#define bFM3_CAN1_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) +#define bFM3_CAN1_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) +#define bFM3_CAN1_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) +#define bFM3_CAN1_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) +#define bFM3_CAN1_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) +#define bFM3_CAN1_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) +#define bFM3_CAN1_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) +#define bFM3_CAN1_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) +#define bFM3_CAN1_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) + +#ifdef __cplusplus +} +#endif + +#endif /* _MB9BF506R_H_ */ + diff --git a/bsp/mb9bf500r/CMSIS/start_gcc.S b/bsp/mb9bf500r/CMSIS/start_gcc.S new file mode 100644 index 0000000000..ad0f8af0c3 --- /dev/null +++ b/bsp/mb9bf500r/CMSIS/start_gcc.S @@ -0,0 +1,360 @@ +/* + * File : start_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-07-01 lgnq first version + */ + +.section .bss.init +.equ Stack_Size, 0x00000200 +.space Stack_Size +Initial_spTop: + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +// .equ Initial_spTop, 0x20000200 +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* restore original stack pointer */ + LDR r0, =Initial_spTop + MSR msp, r0 +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word Initial_spTop + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + .word CSV_IRQHandler + .word SWDT_IRQHandler + .word LVD_IRQHandler + .word WFG_IRQHandler + .word EXINT0_7_IRQHandler + .word EXINT8_15_IRQHandler + .word DTIM_QDU_IRQHandler + .word MFS0RX_IRQHandler + .word MFS0TX_IRQHandler + .word MFS1RX_IRQHandler + .word MFS1TX_IRQHandler + .word MFS2RX_IRQHandler + .word MFS2TX_IRQHandler + .word MFS3RX_IRQHandler + .word MFS3TX_IRQHandler + .word MFS4RX_IRQHandler + .word MFS4TX_IRQHandler + .word MFS5RX_IRQHandler + .word MFS5TX_IRQHandler + .word MFS6RX_IRQHandler + .word MFS6TX_IRQHandler + .word MFS7RX_IRQHandler + .word MFS7TX_IRQHandler + .word PPG_IRQHandler + .word OSC_PLL_WC_IRQHandler + .word ADC0_IRQHandler + .word ADC1_IRQHandler + .word ADC2_IRQHandler + .word FRTIM_IRQHandler + .word INCAP_IRQHandler + .word OUTCOMP_IRQHandler + .word BTIM_IRQHandler + .word CAN0_IRQHandler + .word CAN1_IRQHandler + .word USBF_IRQHandler + .word USBF_USBH_IRQHandler + .word RESERVED_1_IRQHandler + .word RESERVED_2_IRQHandler + .word DMAC0_IRQHandler + .word DMAC1_IRQHandler + .word DMAC2_IRQHandler + .word DMAC3_IRQHandler + .word DMAC4_IRQHandler + .word DMAC5_IRQHandler + .word DMAC6_IRQHandler + .word DMAC7_IRQHandler + .word RESERVED_3_IRQHandler + .word RESERVED_4_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak CSV_IRQHandler + .thumb_set CSV_IRQHandler,Default_Handler + + .weak SWDT_IRQHandler + .thumb_set SWDT_IRQHandler,Default_Handler + + .weak LVD_IRQHandler + .thumb_set LVD_IRQHandler,Default_Handler + + .weak WFG_IRQHandler + .thumb_set WFG_IRQHandler,Default_Handler + + .weak EXINT0_7_IRQHandler + .thumb_set EXINT0_7_IRQHandler,Default_Handler + + .weak EXINT8_15_IRQHandler + .thumb_set EXINT8_15_IRQHandler,Default_Handler + + .weak DTIM_QDU_IRQHandler + .thumb_set DTIM_QDU_IRQHandler,Default_Handler + + .weak MFS0RX_IRQHandler + .thumb_set MFS0RX_IRQHandler,Default_Handler + + .weak MFS0TX_IRQHandler + .thumb_set MFS0TX_IRQHandler,Default_Handler + + .weak MFS1RX_IRQHandler + .thumb_set MFS1RX_IRQHandler,Default_Handler + + .weak MFS1TX_IRQHandler + .thumb_set MFS1TX_IRQHandler,Default_Handler + + .weak MFS2RX_IRQHandler + .thumb_set MFS2RX_IRQHandler,Default_Handler + + .weak MFS2TX_IRQHandler + .thumb_set MFS2TX_IRQHandler,Default_Handler + + .weak MFS3RX_IRQHandler + .thumb_set MFS3RX_IRQHandler,Default_Handler + + .weak MFS3TX_IRQHandler + .thumb_set MFS3TX_IRQHandler,Default_Handler + + .weak MFS4RX_IRQHandler + .thumb_set MFS4RX_IRQHandler,Default_Handler + + .weak MFS4TX_IRQHandler + .thumb_set MFS4TX_IRQHandler,Default_Handler + + .weak MFS5RX_IRQHandler + .thumb_set MFS5RX_IRQHandler,Default_Handler + + .weak MFS5TX_IRQHandler + .thumb_set MFS5TX_IRQHandler,Default_Handler + + .weak MFS6RX_IRQHandler + .thumb_set MFS6RX_IRQHandler,Default_Handler + + .weak MFS6TX_IRQHandler + .thumb_set MFS6TX_IRQHandler,Default_Handler + + .weak MFS7RX_IRQHandler + .thumb_set MFS7RX_IRQHandler,Default_Handler + + .weak MFS7TX_IRQHandler + .thumb_set MFS7TX_IRQHandler,Default_Handler + + .weak PPG_IRQHandler + .thumb_set PPG_IRQHandler,Default_Handler + + .weak OSC_PLL_WC_IRQHandler + .thumb_set OSC_PLL_WC_IRQHandler,Default_Handler + + .weak ADC0_IRQHandler + .thumb_set ADC0_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak ADC2_IRQHandler + .thumb_set ADC2_IRQHandler,Default_Handler + + .weak FRTIM_IRQHandler + .thumb_set FRTIM_IRQHandler,Default_Handler + + .weak INCAP_IRQHandler + .thumb_set INCAP_IRQHandler,Default_Handler + + .weak OUTCOMP_IRQHandler + .thumb_set OUTCOMP_IRQHandler,Default_Handler + + .weak BTIM_IRQHandler + .thumb_set BTIM_IRQHandler,Default_Handler + + .weak CAN0_IRQHandler + .thumb_set CAN0_IRQHandler,Default_Handler + + .weak CAN1_IRQHandler + .thumb_set CAN1_IRQHandler,Default_Handler + + .weak USBF_IRQHandler + .thumb_set USBF_IRQHandler,Default_Handler + + .weak USBF_USBH_IRQHandler + .thumb_set USBF_USBH_IRQHandler,Default_Handler + + .weak RESERVED_1_IRQHandler + .thumb_set RESERVED_1_IRQHandler,Default_Handler + + .weak RESERVED_2_IRQHandler + .thumb_set RESERVED_2_IRQHandler,Default_Handler + + .weak DMAC0_IRQHandler + .thumb_set DMAC0_IRQHandler,Default_Handler + + .weak DMAC1_IRQHandler + .thumb_set DMAC1_IRQHandler,Default_Handler + + .weak DMAC2_IRQHandler + .thumb_set DMAC2_IRQHandler,Default_Handler + + .weak DMAC3_IRQHandler + .thumb_set DMAC3_IRQHandler,Default_Handler + + .weak DMAC4_IRQHandler + .thumb_set DMAC4_IRQHandler,Default_Handler + + .weak DMAC5_IRQHandler + .thumb_set DMAC5_IRQHandler,Default_Handler + + .weak DMAC6_IRQHandler + .thumb_set DMAC6_IRQHandler,Default_Handler + + .weak DMAC7_IRQHandler + .thumb_set DMAC7_IRQHandler,Default_Handler + + .weak RESERVED_3_IRQHandler + .thumb_set RESERVED_3_IRQHandler,Default_Handler + + .weak RESERVED_4_IRQHandler + .thumb_set RESERVED_4_IRQHandler,Default_Handler + diff --git a/bsp/mb9bf500r/CMSIS/start_iar.S b/bsp/mb9bf500r/CMSIS/start_iar.S new file mode 100644 index 0000000000..b111ce9b43 --- /dev/null +++ b/bsp/mb9bf500r/CMSIS/start_iar.S @@ -0,0 +1,363 @@ +;/* +; * File : context_iar.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version +; * 2009-09-27 Bernard add protect when contex switch occurs +; */ + +#include "rtconfig.h" + + MODULE ?cstartup + +;; ICODE is the same segment as cstartup. By placing __low_level_init +;; in the same segment, we make sure it can be reached with BL. */ + + SECTION CSTACK:DATA:NOROOT(3) + SECTION .icode:CODE:NOROOT(2) + +#ifdef RT_USING_UART2 + IMPORT MFS2RX_IRQHandler +#endif + PUBLIC __low_level_init + + PUBWEAK SystemInit_ExtMemCtl + SECTION .text:CODE:REORDER(2) + THUMB +SystemInit_ExtMemCtl + BX LR + +__low_level_init: + ;; Initialize hardware. + LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller + MOV R11, LR + BLX R0 + LDR R1, =sfe(CSTACK) ; restore original stack pointer + MSR MSP, R1 + MOV R0,#1 + ;; Return with BX to be independent of mode of caller + BX R11 + + ;; Forward declaration of sections. + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD __iar_program_start + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD CSV_IRQHandler ; Clock Super Visor + DCD SWDT_IRQHandler ; Software Watchdog Timer + DCD LVD_IRQHandler ; Low Voltage Detector + DCD WFG_IRQHandler ; Wave Form Generator + DCD EXINT0_7_IRQHandler ; External Interrupt Request ch.0 to ch.7 + DCD EXINT8_15_IRQHandler ; External Interrupt Request ch.8 to ch.15 + DCD DTIM_QDU_IRQHandler ; Dual Timer / Quad Decoder + DCD MFS0RX_IRQHandler ; MultiFunction Serial ch.0 + DCD MFS0TX_IRQHandler ; MultiFunction Serial ch.0 + DCD MFS1RX_IRQHandler ; MultiFunction Serial ch.1 + DCD MFS1TX_IRQHandler ; MultiFunction Serial ch.1 +#ifdef RT_USING_UART2 + DCD MFS2RX_IRQHandler ; MultiFunction Serial ch.2 +#else + DCD NULL_IRQHandler ; MultiFunction Serial ch.2 +#endif + DCD MFS2TX_IRQHandler ; MultiFunction Serial ch.2 + DCD MFS3RX_IRQHandler ; MultiFunction Serial ch.3 + DCD MFS3TX_IRQHandler ; MultiFunction Serial ch.3 + DCD MFS4RX_IRQHandler ; MultiFunction Serial ch.4 + DCD MFS4TX_IRQHandler ; MultiFunction Serial ch.4 + DCD MFS5RX_IRQHandler ; MultiFunction Serial ch.5 + DCD MFS5TX_IRQHandler ; MultiFunction Serial ch.5 + DCD MFS6RX_IRQHandler ; MultiFunction Serial ch.6 + DCD MFS6TX_IRQHandler ; MultiFunction Serial ch.6 + DCD MFS7RX_IRQHandler ; MultiFunction Serial ch.7 + DCD MFS7TX_IRQHandler ; MultiFunction Serial ch.7 + DCD PPG_IRQHandler ; PPG + DCD OSC_PLL_WC_IRQHandler ; OSC / PLL / Watch Counter + DCD ADC0_IRQHandler ; ADC0 + DCD ADC1_IRQHandler ; ADC1 + DCD ADC2_IRQHandler ; ADC2 + DCD FRTIM_IRQHandler ; Free-run Timer + DCD INCAP_IRQHandler ; Input Capture + DCD OUTCOMP_IRQHandler ; Output Compare + DCD BTIM_IRQHandler ; Base Timer ch.0 to ch.7 + DCD CAN0_IRQHandler ; CAN ch.0 + DCD CAN1_IRQHandler ; CAN ch.1 + DCD USBF_IRQHandler ; USB Function + DCD USBF_USBH_IRQHandler ; USB Function / USB HOST + DCD RESERVED_1_IRQHandler ; Reserved_1 + DCD RESERVED_2_IRQHandler ; Reserved_2 + DCD DMAC0_IRQHandler ; DMAC ch.0 + DCD DMAC1_IRQHandler ; DMAC ch.1 + DCD DMAC2_IRQHandler ; DMAC ch.2 + DCD DMAC3_IRQHandler ; DMAC ch.3 + DCD DMAC4_IRQHandler ; DMAC ch.4 + DCD DMAC5_IRQHandler ; DMAC ch.5 + DCD DMAC6_IRQHandler ; DMAC ch.6 + DCD DMAC7_IRQHandler ; DMAC ch.7 + DCD RESERVED_3_IRQHandler ; Reserved_3 + DCD RESERVED_4_IRQHandler ; Reserved_4 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + PUBWEAK CSV_IRQHandler + SECTION .text:CODE:REORDER(1) +CSV_IRQHandler + B CSV_IRQHandler + PUBWEAK SWDT_IRQHandler + SECTION .text:CODE:REORDER(1) +SWDT_IRQHandler + B SWDT_IRQHandler + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + PUBWEAK WFG_IRQHandler + SECTION .text:CODE:REORDER(1) +WFG_IRQHandler + B WFG_IRQHandler + PUBWEAK EXINT0_7_IRQHandler + SECTION .text:CODE:REORDER(1) +EXINT0_7_IRQHandler + B EXINT0_7_IRQHandler + PUBWEAK EXINT8_15_IRQHandler + SECTION .text:CODE:REORDER(1) +EXINT8_15_IRQHandler + B EXINT8_15_IRQHandler + PUBWEAK DTIM_QDU_IRQHandler + SECTION .text:CODE:REORDER(1) +DTIM_QDU_IRQHandler + B DTIM_QDU_IRQHandler + PUBWEAK MFS0RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS0RX_IRQHandler + B MFS0RX_IRQHandler + PUBWEAK MFS0TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS0TX_IRQHandler + B MFS0TX_IRQHandler + PUBWEAK MFS1RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS1RX_IRQHandler + B MFS1RX_IRQHandler + PUBWEAK MFS1TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS1TX_IRQHandler + B MFS1TX_IRQHandler + PUBWEAK NULL_IRQHandler + SECTION .text:CODE:REORDER(1) +NULL_IRQHandler + B NULL_IRQHandler + PUBWEAK MFS2TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS2TX_IRQHandler + B MFS2TX_IRQHandler + PUBWEAK MFS3RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS3RX_IRQHandler + B MFS3RX_IRQHandler + PUBWEAK MFS3TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS3TX_IRQHandler + B MFS3TX_IRQHandler + PUBWEAK MFS4RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS4RX_IRQHandler + B MFS4RX_IRQHandler + PUBWEAK MFS4TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS4TX_IRQHandler + B MFS4TX_IRQHandler + PUBWEAK MFS5RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS5RX_IRQHandler + B MFS5RX_IRQHandler + PUBWEAK MFS5TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS5TX_IRQHandler + B MFS5TX_IRQHandler + PUBWEAK MFS6RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS6RX_IRQHandler + B MFS6RX_IRQHandler + PUBWEAK MFS6TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS6TX_IRQHandler + B MFS6TX_IRQHandler + PUBWEAK MFS7RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS7RX_IRQHandler + B MFS7RX_IRQHandler + PUBWEAK MFS7TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS7TX_IRQHandler + B MFS7TX_IRQHandler + PUBWEAK PPG_IRQHandler + SECTION .text:CODE:REORDER(1) +PPG_IRQHandler + B PPG_IRQHandler + PUBWEAK OSC_PLL_WC_IRQHandler + SECTION .text:CODE:REORDER(1) +OSC_PLL_WC_IRQHandler + B OSC_PLL_WC_IRQHandler + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC0_IRQHandler + B ADC0_IRQHandler + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + PUBWEAK ADC2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC2_IRQHandler + B ADC2_IRQHandler + PUBWEAK FRTIM_IRQHandler + SECTION .text:CODE:REORDER(1) +FRTIM_IRQHandler + B FRTIM_IRQHandler + PUBWEAK INCAP_IRQHandler + SECTION .text:CODE:REORDER(1) +INCAP_IRQHandler + B INCAP_IRQHandler + PUBWEAK OUTCOMP_IRQHandler + SECTION .text:CODE:REORDER(1) +OUTCOMP_IRQHandler + B OUTCOMP_IRQHandler + PUBWEAK BTIM_IRQHandler + SECTION .text:CODE:REORDER(1) +BTIM_IRQHandler + B BTIM_IRQHandler + PUBWEAK CAN0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN0_IRQHandler + B CAN0_IRQHandler + PUBWEAK CAN1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_IRQHandler + B CAN1_IRQHandler + PUBWEAK USBF_IRQHandler + SECTION .text:CODE:REORDER(1) +USBF_IRQHandler + B USBF_IRQHandler + PUBWEAK USBF_USBH_IRQHandler + SECTION .text:CODE:REORDER(1) +USBF_USBH_IRQHandler + B USBF_USBH_IRQHandler + PUBWEAK RESERVED_1_IRQHandler + SECTION .text:CODE:REORDER(1) +RESERVED_1_IRQHandler + B RESERVED_1_IRQHandler + PUBWEAK RESERVED_2_IRQHandler + SECTION .text:CODE:REORDER(1) +RESERVED_2_IRQHandler + B RESERVED_2_IRQHandler + PUBWEAK DMAC0_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC0_IRQHandler + B DMAC0_IRQHandler + PUBWEAK DMAC1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC1_IRQHandler + B DMAC1_IRQHandler + PUBWEAK DMAC2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC2_IRQHandler + B DMAC2_IRQHandler + PUBWEAK DMAC3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC3_IRQHandler + B DMAC3_IRQHandler + PUBWEAK DMAC4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC4_IRQHandler + B DMAC4_IRQHandler + PUBWEAK DMAC5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC5_IRQHandler + B DMAC5_IRQHandler + PUBWEAK DMAC6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC6_IRQHandler + B DMAC6_IRQHandler + PUBWEAK DMAC7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC7_IRQHandler + B DMAC7_IRQHandler + PUBWEAK RESERVED_3_IRQHandler + SECTION .text:CODE:REORDER(1) +RESERVED_3_IRQHandler + B RESERVED_3_IRQHandler + PUBWEAK RESERVED_4_IRQHandler + SECTION .text:CODE:REORDER(1) +RESERVED_4_IRQHandler + B RESERVED_4_IRQHandler + + END diff --git a/bsp/mb9bf500r/CMSIS/start_rvds.S b/bsp/mb9bf500r/CMSIS/start_rvds.S new file mode 100644 index 0000000000..fc755132c1 --- /dev/null +++ b/bsp/mb9bf500r/CMSIS/start_rvds.S @@ -0,0 +1,291 @@ +; /* +; * File : start_rvds.s +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2011-02-23 Bernard first implementation +; */ + +;* <<< Use Configuration Wizard in Context Menu >>> + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Note: RT-Thread not use malloc/free in Keil MDK, therefore the heap size is 0. +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + DCD CSV_Handler ; 0: Clock Super Visor + DCD SWDT_Handler ; 1: Software Watchdog Timer + DCD LVD_Handler ; 2: Low Voltage Detector + DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF + DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7 + DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15 + DCD DT_Handler ; 6: Dual Timer / Quad Decoder + DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0 + DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0 + DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1 + DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1 + DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2 + DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2 + DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3 + DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3 + DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4 + DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4 + DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5 + DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5 + DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6 + DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6 + DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7 + DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7 + DCD PPG_Handler ; 23: PPG + DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter + DCD ADC0_IRQHandler ; 25: ADC0 + DCD ADC1_IRQHandler ; 26: ADC1 + DCD ADC2_IRQHandler ; 27: ADC2 + DCD MFT_FRT_IRQHandler ; 28: Free-run Timer + DCD MFT_IPC_IRQHandler ; 29: Input Capture + DCD MFT_OPC_IRQHandler ; 30: Output Compare + DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7 + DCD CAN0_IRQHandler ; 32: CAN ch.0 + DCD CAN1_IRQHandler ; 33: CAN ch.1 + DCD USBF_Handler ; 34: USB Function + DCD USB_Handler ; 35: USB Function / USB HOST + DCD DummyHandler ; 36: Reserved + DCD DummyHandler ; 37: Reserved + DCD DMAC0_Handler ; 38: DMAC ch.0 + DCD DMAC1_Handler ; 39: DMAC ch.1 + DCD DMAC2_Handler ; 40: DMAC ch.2 + DCD DMAC3_Handler ; 41: DMAC ch.3 + DCD DMAC4_Handler ; 42: DMAC ch.4 + DCD DMAC5_Handler ; 43: DMAC ch.5 + DCD DMAC6_Handler ; 44: DMAC ch.6 + DCD DMAC7_Handler ; 45: DMAC ch.7 + DCD DummyHandler ; 46: Reserved + DCD DummyHandler ; 47: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R1, = __initial_sp ; restore original stack pointer + MSR MSP, R1 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT CSV_Handler [WEAK] + EXPORT SWDT_Handler [WEAK] + EXPORT LVD_Handler [WEAK] + EXPORT MFT_WG_IRQHandler [WEAK] + EXPORT INT0_7_Handler [WEAK] + EXPORT INT8_15_Handler [WEAK] + EXPORT DT_Handler [WEAK] + EXPORT MFS0RX_IRQHandler [WEAK] + EXPORT MFS0TX_IRQHandler [WEAK] + EXPORT MFS1RX_IRQHandler [WEAK] + EXPORT MFS1TX_IRQHandler [WEAK] + EXPORT MFS2RX_IRQHandler [WEAK] + EXPORT MFS2TX_IRQHandler [WEAK] + EXPORT MFS3RX_IRQHandler [WEAK] + EXPORT MFS3TX_IRQHandler [WEAK] + EXPORT MFS4RX_IRQHandler [WEAK] + EXPORT MFS4TX_IRQHandler [WEAK] + EXPORT MFS5RX_IRQHandler [WEAK] + EXPORT MFS5TX_IRQHandler [WEAK] + EXPORT MFS6RX_IRQHandler [WEAK] + EXPORT MFS6TX_IRQHandler [WEAK] + EXPORT MFS7RX_IRQHandler [WEAK] + EXPORT MFS7TX_IRQHandler [WEAK] + EXPORT PPG_Handler [WEAK] + EXPORT TIM_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT MFT_FRT_IRQHandler [WEAK] + EXPORT MFT_IPC_IRQHandler [WEAK] + EXPORT MFT_OPC_IRQHandler [WEAK] + EXPORT BT_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT USBF_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT DMAC0_Handler [WEAK] + EXPORT DMAC1_Handler [WEAK] + EXPORT DMAC2_Handler [WEAK] + EXPORT DMAC3_Handler [WEAK] + EXPORT DMAC4_Handler [WEAK] + EXPORT DMAC5_Handler [WEAK] + EXPORT DMAC6_Handler [WEAK] + EXPORT DMAC7_Handler [WEAK] + EXPORT DummyHandler [WEAK] + +CSV_Handler +SWDT_Handler +LVD_Handler +MFT_WG_IRQHandler +INT0_7_Handler +INT8_15_Handler +DT_Handler +MFS0RX_IRQHandler +MFS0TX_IRQHandler +MFS1RX_IRQHandler +MFS1TX_IRQHandler +MFS2RX_IRQHandler +MFS2TX_IRQHandler +MFS3RX_IRQHandler +MFS3TX_IRQHandler +MFS4RX_IRQHandler +MFS4TX_IRQHandler +MFS5RX_IRQHandler +MFS5TX_IRQHandler +MFS6RX_IRQHandler +MFS6TX_IRQHandler +MFS7RX_IRQHandler +MFS7TX_IRQHandler +PPG_Handler +TIM_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +ADC2_IRQHandler +MFT_FRT_IRQHandler +MFT_IPC_IRQHandler +MFT_OPC_IRQHandler +BT_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +USBF_Handler +USB_Handler +DMAC0_Handler +DMAC1_Handler +DMAC2_Handler +DMAC3_Handler +DMAC4_Handler +DMAC5_Handler +DMAC6_Handler +DMAC7_Handler +DummyHandler + B . + ENDP + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + ELSE + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + ENDIF + + END diff --git a/bsp/mb9bf500r/CMSIS/system_mb9bf50x.c b/bsp/mb9bf500r/CMSIS/system_mb9bf50x.c new file mode 100644 index 0000000000..21cd7a3f26 --- /dev/null +++ b/bsp/mb9bf500r/CMSIS/system_mb9bf50x.c @@ -0,0 +1,111 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user’s obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intention and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.4) */ +/************************************************************************/ + +#include "mb9bf506r.h" + +/* + * 80MHz : Master Clock + */ +const uint32_t SystemFrequency = 80000000UL; + +uint32_t SysFreHCLK = 80000000UL; /* HCLK = MasterClock / 1 */ +uint32_t SysFrePCLK0 = 40000000UL; /* PCLK0 = HCLK / 2 */ +uint32_t SysFrePCLK1 = 40000000UL; /* PCLK1 = HCLK / 2 */ +uint32_t SysFrePCLK2 = 40000000UL; /* PCLK2 = HCLK / 2 */ +uint32_t SysFreTPIU = 0UL; /* TPIUCLK : Disable */ + +/* + * Prototype of internal function + */ +static void ClockInit(void); +static void HwwdtDisable(void); + + +/* + * Setup the microcontroller system + */ +void SystemInit (void) +{ + HwwdtDisable(); /* Disable Hardware Watchdog */ + ClockInit(); /* Initialize Clock */ +} +/* + * Initialize Clock + */ +static void ClockInit(void) +{ + /*set Main clock stabilization + wait time to 2ms*/ + FM3_CRG->CSW_TMR = 0x79; + /*Enable Main Oscilator*/ + FM3_CRG->SCM_CTL |= 1<<1; + /*Wait stabilization end*/ + while(!(FM3_CRG->SCM_STR & 0x02)); + + /* sub CLK enable */ + //FM3_CRG->SCM_CTL |= 0x08; + //while(!(FM3_CRG->SCM_STR & 0x08)); + + /*Set PLL stabilization + wait time to 512uS*/ + FM3_CRG->PSW_TMR |= 2; + /*Set PLL to 80MHz*/ + FM3_CRG->PLL_CTL1 = 0; /*K = 1, M=1*/ + FM3_CRG->PLL_CTL2 = 19; /*N = 20*/ + /*Enable PLL*/ + FM3_CRG->SCM_CTL |= 0x10; + /*Set bus prescalers*/ + FM3_CRG->BSC_PSR = 0; /*Base clock Prescaler 1:1*/ + FM3_CRG->APBC0_PSR |= 1; /*APB0 clock Prescaler 1:2*/ + FM3_CRG->APBC1_PSR |= 1; /*APB1 clock Prescaler 1:2*/ + FM3_CRG->APBC2_PSR |= 1; /*APB2 clock Prescaler 1:2*/ + /*Wait PLL stabilizatoin end*/ + while(!(FM3_CRG->SCM_STR & 0x10)); + /*Select PLL for main clock*/ + FM3_CRG->SCM_CTL |= 2<<5; + /*Wait PLL to be connected*/ + while((FM3_CRG->SCM_STR & 0xe0) != 0x40); + +} +/* + * Stop HW Watchdog Timer + */ +static void HwwdtDisable(void) +{ + /* UnLock (except WDG_CTL) */ + FM3_HWWDT->WDG_LCK = 0x1ACCE551; + /* UnLock (WDG_CTL) */ + FM3_HWWDT->WDG_LCK = 0xE5331AAE; + /* Disable WDG */ + FM3_HWWDT->WDG_CTL = 0x00; +} diff --git a/bsp/mb9bf500r/CMSIS/system_mb9bf50x.h b/bsp/mb9bf500r/CMSIS/system_mb9bf50x.h new file mode 100644 index 0000000000..4b4789d5df --- /dev/null +++ b/bsp/mb9bf500r/CMSIS/system_mb9bf50x.h @@ -0,0 +1,71 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user's obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intentional misconduct and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.5) */ +/************************************************************************/ + +#ifndef _SYSTEM_MB9BF50X_H_ +#define _SYSTEM_MB9BF50X_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_MB9BF50X_H */ diff --git a/bsp/mb9bf500r/SConscript b/bsp/mb9bf500r/SConscript new file mode 100644 index 0000000000..703232f1b6 --- /dev/null +++ b/bsp/mb9bf500r/SConscript @@ -0,0 +1,16 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +src_bsp = ['application.c', 'startup.c', 'board.c', 'led.c', 'cpuusage.c'] +src_drv = ['adc.c', 'lcd.c', 'key.c'] + +if GetDepend('RT_USING_RTGUI'): + src_drv += ['info.c'] + +src = src_bsp + src_drv +CPPPATH = [GetCurrentDir()] +CPPDEFINES = [] +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/mb9bf500r/SConstruct b/bsp/mb9bf500r/SConstruct new file mode 100644 index 0000000000..b297c2cd74 --- /dev/null +++ b/bsp/mb9bf500r/SConstruct @@ -0,0 +1,39 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map']) + env.Replace(ARFLAGS = '') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +objs = objs + SConscript('CMSIS/SConscript', variant_dir='build/bsp/CMSIS', duplicate=0) + +# build program +env.Program(TARGET, objs) + +# end building +EndBuilding(TARGET) diff --git a/bsp/mb9bf500r/adc.c b/bsp/mb9bf500r/adc.c new file mode 100644 index 0000000000..1e36d0b600 --- /dev/null +++ b/bsp/mb9bf500r/adc.c @@ -0,0 +1,133 @@ +/* + * File : adc.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-03-03 lgnq + */ + +#include +#include +#include "mb9bf506r.h" +#include "adc.h" +#include "led.h" +#include "lcd.h" + +#ifdef RT_USING_RTGUI +#include +#include +#include +#endif + +static struct rt_device adc; + +static rt_err_t rt_adc_init(rt_device_t dev) +{ + RT_ASSERT(dev != RT_NULL); + + if(!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + /* I/O setting AN08 - P18 */ + FM3_GPIO->ADE |= 0x100; + FM3_GPIO->PFR1 = 0x100; + + /* A/DC setting */ + FM3_ADC0->SCIS1 = 0x01; + FM3_ADC0->ADSS1 = 0x00; /* sampling timming ADST0 */ + FM3_ADC0->ADST1 = 0x43; + FM3_ADC0->ADCT = 0x02; + FM3_ADC0->SCCR = 0x10; /* FIFO clear,single mode */ + FM3_ADC0->CMPCR = 0x00; /* disable comparator */ + + /* starting A/DC */ + FM3_ADC0->SCCR |= 0x01; /* A/DC start */ + + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + return RT_EOK; +} + +static rt_err_t rt_adc_control(rt_device_t dev, rt_uint8_t cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_ADC_START: + FM3_ADC0->SCCR |= 0x1; + break; + + case RT_DEVICE_CTRL_ADC_RESULT: + while(FM3_ADC0->ADSR & 0x1) + ; + *((rt_uint16_t*)args) = FM3_ADC0->SCFD; + *((rt_uint16_t*)args) = *((rt_uint16_t*)args) >> 6; + *((rt_uint16_t*)args) = (*((rt_uint16_t*)args)*3300)/1024; + break; + } + return RT_EOK; +} + +extern struct rt_messagequeue mq; +extern rt_thread_t info_tid; +rt_uint16_t adc_value; +static void adc_thread_entry(void *parameter) +{ + rt_device_t device; + +#ifdef RT_USING_RTGUI + struct rtgui_event_command ecmd; + + RTGUI_EVENT_COMMAND_INIT(&ecmd); + ecmd.type = RTGUI_CMD_USER_INT; + ecmd.command_id = ADC_UPDATE; +#else + struct lcd_msg msg; +#endif + + device = rt_device_find("adc"); + + while(1) + { + rt_device_control(device, RT_DEVICE_CTRL_ADC_START, RT_NULL); + rt_device_control(device, RT_DEVICE_CTRL_ADC_RESULT, &adc_value); + pwm_update(adc_value/3); +#ifdef RT_USING_RTGUI + rtgui_thread_send(info_tid, &ecmd.parent, sizeof(ecmd)); +#else + msg.type = ADC_MSG; + msg.adc_value = adc_value; + rt_mq_send(&mq, &msg, sizeof(msg)); +#endif + rt_thread_delay(20); + } +} + +static rt_thread_t adc_thread; +void rt_hw_adc_init(void) +{ + adc.type = RT_Device_Class_Char; + adc.rx_indicate = RT_NULL; + adc.tx_complete = RT_NULL; + adc.init = rt_adc_init; + adc.open = RT_NULL; + adc.close = RT_NULL; + adc.read = RT_NULL; + adc.write = RT_NULL; + adc.control = rt_adc_control; + adc.user_data = RT_NULL; + + adc_thread = rt_thread_create("adc", adc_thread_entry, RT_NULL, 384, 26, 5); + if(adc_thread != RT_NULL) + rt_thread_startup(adc_thread); + + /* register a character device */ + rt_device_register(&adc, "adc", RT_DEVICE_FLAG_RDWR); +} + diff --git a/bsp/mb9bf500r/adc.h b/bsp/mb9bf500r/adc.h new file mode 100644 index 0000000000..601a67619f --- /dev/null +++ b/bsp/mb9bf500r/adc.h @@ -0,0 +1,32 @@ +/* + * File : adc.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-03-03 lgnq + */ + +#ifndef __ADC_H__ +#define __ADC_H__ + +/* Exported constants ---------------------------------------------------------*/ +/* Exported macro -------------------------------------------------------------*/ +#define ADC_MODE_SINGLE 0x00UL +#define ADC_MODE_SCAN 0x01UL +#define ADC_MODE_TAILGATE 0x02UL + +#define RT_DEVICE_CTRL_ADC_START 0xF1 /* start ADC conversion */ +#define RT_DEVICE_CTRL_ADC_RESULT 0xF2 /* get ADC result */ + +#define ADC_UPDATE 0 + +/* Exported functions --------------------------------------------------------- */ +void rt_hw_adc_init(void); + +#endif /*__ADC_H__ */ diff --git a/bsp/mb9bf500r/application.c b/bsp/mb9bf500r/application.c new file mode 100644 index 0000000000..2c3e4dab1c --- /dev/null +++ b/bsp/mb9bf500r/application.c @@ -0,0 +1,143 @@ +/* + * File : application.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-24 Bernard the first version + */ + +/** + * @addtogroup FM3 + */ +/*@{*/ + +#include +#include "board.h" +#include "led.h" +#include "key.h" +#include "adc.h" +#include "lcd.h" +#include "cpuusage.h" + +#ifdef RT_USING_RTGUI +#include +#include +extern void rtgui_startup(); +#endif + +struct rt_messagequeue mq; +static char msg_pool[2048]; + +void rt_init_thread_entry(void *parameter) +{ + rt_device_t lcd; + + rt_hw_led_init(); + rt_hw_key_init(); + rt_hw_adc_init(); + rt_hw_lcd_init(); + rt_hw_cpu_init(); + + /* re-init device driver */ + rt_device_init_all(); + +#ifdef RT_USING_RTGUI + /* find lcd device */ + lcd = rt_device_find("lcd"); + + /* set lcd device as rtgui graphic driver */ + rtgui_graphic_set_device(lcd); + + /* startup rtgui */ + rtgui_startup(); +#else + { + char buf[20] = {'\0'}; + struct lcd_msg msg; + rt_device_t device; + device = rt_device_find("lcd"); + rt_device_control(device, RT_DEVICE_CTRL_LCD_CLEAR_SCR, RT_NULL); + x = 1; + y = 1; + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "ADC"); + x = 1; + y = 20; + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "CPU"); + x = 1; + y = 40; + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, "KEY"); + + while(1) + { + if (rt_mq_recv(&mq, &msg, sizeof(msg), RT_WAITING_FOREVER) == RT_EOK) + { + switch(msg.type) + { + case ADC_MSG: + x = 40; + y = 1; + rt_memset(buf, 0, sizeof(buf)); + rt_sprintf(buf, "%04d", msg.adc_value); + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); + break; + case CPU_MSG: + x = 40; + y = 20; + rt_memset(buf, 0, sizeof(buf)); + rt_sprintf(buf, "%03d %03d", msg.major, msg.minor); + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); + break; + case KEY_MSG: + x = 40; + y = 40; + rt_memset(buf, 0, sizeof(buf)); + switch(msg.key) + { + case KEY_DOWN: + rt_sprintf(buf, "DOWN KEY "); + break; + case KEY_UP: + rt_sprintf(buf, "UP KEY "); + break; + case KEY_RIGHT: + rt_sprintf(buf, "RIGHT KEY"); + break; + case KEY_LEFT: + rt_sprintf(buf, "LEFT KEY "); + break; + case KEY_ENTER: + rt_sprintf(buf, "ENTER KEY"); + break; + default: + rt_sprintf(buf, "NO KEY "); + break; + } + rt_device_control(device, RT_DEVICE_CTRL_LCD_PUT_STRING, buf); + break; + } + } + } + } +#endif +} + +int rt_application_init() +{ + rt_thread_t init_thread; + + rt_mq_init(&mq, "mqt", &msg_pool[0], 128 - sizeof(void*), sizeof(msg_pool), RT_IPC_FLAG_FIFO); + + init_thread = rt_thread_create("init", rt_init_thread_entry, RT_NULL, 1024, 21, 20); + if(init_thread != RT_NULL) + rt_thread_startup(init_thread); + + return 0; +} + +/*@}*/ diff --git a/bsp/mb9bf500r/board.c b/bsp/mb9bf500r/board.c new file mode 100644 index 0000000000..896afc9ed4 --- /dev/null +++ b/bsp/mb9bf500r/board.c @@ -0,0 +1,54 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-24 Bernard first implementation + */ + +#include +#include + +#include "board.h" +#include "mb9bf506r.h" +#include "core_cm3.h" + +extern const uint32_t SystemFrequency; + +/** + * @addtogroup FM3 + */ + +/*@{*/ + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** +* This function will initial FM3 Easy Kit board. + */ +void rt_hw_board_init() +{ + /* init systick */ + SysTick_Config(SystemFrequency/RT_TICK_PER_SECOND - 1); +} + +/*@}*/ diff --git a/bsp/mb9bf500r/board.h b/bsp/mb9bf500r/board.h new file mode 100644 index 0000000000..951db46f7d --- /dev/null +++ b/bsp/mb9bf500r/board.h @@ -0,0 +1,29 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2011-03-04 lgnq add board.h to FM3 bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +//Internal SRAM memory size[Kbytes] <8-64> +//MB9BF500 : 32 +//MB9BF504 : 32 +//MB9BF505 : 48 +//MB9BF506 : 64 +#define FM3_SRAM_SIZE 32 +#define FM3_SRAM_END (0x1FFFC000 + FM3_SRAM_SIZE * 1024) + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/mb9bf500r/cpuusage.c b/bsp/mb9bf500r/cpuusage.c new file mode 100644 index 0000000000..56d193b9ed --- /dev/null +++ b/bsp/mb9bf500r/cpuusage.c @@ -0,0 +1,115 @@ +#include +#include +#include "cpuusage.h" +#include "lcd.h" + +#ifdef RT_USING_RTGUI +#include +#include +#include +#endif + +#define CPU_USAGE_CALC_TICK 10 +#define CPU_USAGE_LOOP 100 + +static rt_uint8_t cpu_usage_major = 0, cpu_usage_minor= 0; +static rt_uint32_t total_count = 0; + +static void cpu_usage_idle_hook() +{ + rt_tick_t tick; + rt_uint32_t count; + volatile rt_uint32_t loop; + + if (total_count == 0) + { + loop = 0; + + /* get total count */ + rt_enter_critical(); + tick = rt_tick_get(); + while(rt_tick_get() - tick < CPU_USAGE_CALC_TICK) + { + total_count ++; + while (loop < CPU_USAGE_LOOP) loop ++; + } + rt_exit_critical(); + } + + count = 0; + loop = 0; + /* get CPU usage */ + tick = rt_tick_get(); + while (rt_tick_get() - tick < CPU_USAGE_CALC_TICK) + { + count ++; + while (loop < CPU_USAGE_LOOP) loop ++; + } + + /* calculate major and minor */ + if (count < total_count) + { + count = total_count - count; + cpu_usage_major = (count * 100) / total_count; + cpu_usage_minor = ((count * 100) % total_count) * 100 / total_count; + } + else + { + total_count = count; + + /* no CPU usage */ + cpu_usage_major = 0; + cpu_usage_minor = 0; + } +} + +void cpu_usage_get(rt_uint8_t *major, rt_uint8_t *minor) +{ + RT_ASSERT(major != RT_NULL); + RT_ASSERT(minor != RT_NULL); + + *major = cpu_usage_major; + *minor = cpu_usage_minor; +} + +void cpu_usage_init() +{ + /* set idle thread hook */ + rt_thread_idle_sethook(cpu_usage_idle_hook); +} +extern struct rt_messagequeue mq; +extern rt_thread_t info_tid; +static void cpu_thread_entry(void *parameter) +{ +#ifdef RT_USING_RTGUI + struct rtgui_event_command ecmd; + + RTGUI_EVENT_COMMAND_INIT(&ecmd); + ecmd.type = RTGUI_CMD_USER_INT; + ecmd.command_id = CPU_UPDATE; +#else + struct lcd_msg msg; +#endif + + while (1) + { +#ifdef RT_USING_RTGUI + rtgui_thread_send(info_tid, &ecmd.parent, sizeof(ecmd)); +#else + msg.type = CPU_MSG; + msg.major = cpu_usage_major; + msg.minor = cpu_usage_minor; + rt_mq_send(&mq, &msg, sizeof(msg)); +#endif + rt_thread_delay(20); + } +} + +static rt_thread_t cpu_thread; +void rt_hw_cpu_init(void) +{ + cpu_usage_init(); + cpu_thread = rt_thread_create("cpu", cpu_thread_entry, RT_NULL, 384, 27, 5); + if(cpu_thread != RT_NULL) + rt_thread_startup(cpu_thread); +} diff --git a/bsp/mb9bf500r/cpuusage.h b/bsp/mb9bf500r/cpuusage.h new file mode 100644 index 0000000000..e77bec0146 --- /dev/null +++ b/bsp/mb9bf500r/cpuusage.h @@ -0,0 +1,23 @@ +/* + * File : cpuusage.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-03-03 lgnq + */ + +#ifndef __CPUUSAGE_H__ +#define __CPUUSAGE_H__ + +#define CPU_UPDATE 1 + +void cpu_usage_get(rt_uint8_t *major, rt_uint8_t *minor); +void rt_hw_cpu_init(void); + +#endif /*__ADC_H__ */ diff --git a/bsp/mb9bf500r/fm3_easy_kit.ewp b/bsp/mb9bf500r/fm3_easy_kit.ewp new file mode 100644 index 0000000000..413df3c022 --- /dev/null +++ b/bsp/mb9bf500r/fm3_easy_kit.ewp @@ -0,0 +1,2030 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + CMSIS + + $PROJ_DIR$\CMSIS\core_cm3.c + + + $PROJ_DIR$\CMSIS\start_iar.S + + + $PROJ_DIR$\CMSIS\system_mb9bf50x.c + + + + FM3 + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c + + + + Kernel + + $PROJ_DIR$\..\..\src\clock.c + + + $PROJ_DIR$\..\..\src\device.c + + + $PROJ_DIR$\..\..\src\idle.c + + + $PROJ_DIR$\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\src\irq.c + + + $PROJ_DIR$\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\src\mem.c + + + $PROJ_DIR$\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\src\module.c + + + $PROJ_DIR$\..\..\src\object.c + + + $PROJ_DIR$\..\..\src\rtm.c + + + $PROJ_DIR$\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\src\slab.c + + + $PROJ_DIR$\..\..\src\thread.c + + + $PROJ_DIR$\..\..\src\timer.c + + + + Rtgui + + $PROJ_DIR$\..\..\components\rtgui\widgets\about_view.c + + + $PROJ_DIR$\..\..\components\rtgui\common\asc12font.c + + + $PROJ_DIR$\..\..\components\rtgui\common\asc16font.c + + + $PROJ_DIR$\..\..\components\rtgui\common\blit.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\box.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\button.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\checkbox.c + + + $PROJ_DIR$\..\..\components\rtgui\common\color.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\combobox.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\container.c + + + $PROJ_DIR$\..\..\components\rtgui\common\dc.c + + + $PROJ_DIR$\..\..\components\rtgui\common\dc_buffer.c + + + $PROJ_DIR$\..\..\components\rtgui\common\dc_client.c + + + $PROJ_DIR$\..\..\components\rtgui\common\dc_hw.c + + + $PROJ_DIR$\..\..\components\rtgui\server\driver.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\filelist_view.c + + + $PROJ_DIR$\..\..\components\rtgui\common\filerw.c + + + $PROJ_DIR$\..\..\components\rtgui\common\font.c + + + $PROJ_DIR$\..\..\components\rtgui\common\font_bmp.c + + + $PROJ_DIR$\..\..\components\rtgui\common\font_freetype.c + + + $PROJ_DIR$\..\..\components\rtgui\common\font_hz_bmp.c + + + $PROJ_DIR$\..\..\components\rtgui\common\font_hz_file.c + + + $PROJ_DIR$\..\..\components\rtgui\common\framebuffer_driver.c + + + $PROJ_DIR$\..\..\components\rtgui\common\hz12font.c + + + $PROJ_DIR$\..\..\components\rtgui\common\hz16font.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\iconbox.c + + + $PROJ_DIR$\..\..\components\rtgui\common\image.c + + + $PROJ_DIR$\..\..\components\rtgui\common\image_bmp.c + + + $PROJ_DIR$\..\..\components\rtgui\common\image_container.c + + + $PROJ_DIR$\..\..\components\rtgui\common\image_hdc.c + + + $PROJ_DIR$\..\..\components\rtgui\common\image_jpg.c + + + $PROJ_DIR$\..\..\components\rtgui\common\image_png.c + + + $PROJ_DIR$\..\..\components\rtgui\common\image_xpm.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\label.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\list_view.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\listbox.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\listctrl.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\menu.c + + + $PROJ_DIR$\..\..\components\rtgui\server\mouse.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\notebook.c + + + $PROJ_DIR$\..\..\components\rtgui\server\panel.c + + + $PROJ_DIR$\..\..\components\rtgui\common\pixel_driver.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\progressbar.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\radiobox.c + + + $PROJ_DIR$\..\..\components\rtgui\common\region.c + + + $PROJ_DIR$\..\..\components\rtgui\common\rtgui_object.c + + + $PROJ_DIR$\..\..\components\rtgui\common\rtgui_system.c + + + $PROJ_DIR$\..\..\components\rtgui\common\rtgui_theme.c + + + $PROJ_DIR$\..\..\components\rtgui\common\rtgui_xml.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\scrollbar.c + + + $PROJ_DIR$\..\..\components\rtgui\server\server.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\slider.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\staticline.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\textbox.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\textview.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\title.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\toplevel.c + + + $PROJ_DIR$\..\..\components\rtgui\server\topwin.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\view.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\widget.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\window.c + + + $PROJ_DIR$\..\..\components\rtgui\widgets\workbench.c + + + + Startup + + $PROJ_DIR$\adc.c + + + $PROJ_DIR$\application.c + + + $PROJ_DIR$\board.c + + + $PROJ_DIR$\cpuusage.c + + + $PROJ_DIR$\info.c + + + $PROJ_DIR$\key.c + + + $PROJ_DIR$\lcd.c + + + $PROJ_DIR$\led.c + + + $PROJ_DIR$\startup.c + + + + + diff --git a/bsp/mb9bf500r/fm3_easy_kit.eww b/bsp/mb9bf500r/fm3_easy_kit.eww new file mode 100644 index 0000000000..bdaf802ebd --- /dev/null +++ b/bsp/mb9bf500r/fm3_easy_kit.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\fm3_easy_kit.ewp + + + + + diff --git a/bsp/mb9bf500r/fm3_rom.ld b/bsp/mb9bf500r/fm3_rom.ld new file mode 100644 index 0000000000..861f94a00a --- /dev/null +++ b/bsp/mb9bf500r/fm3_rom.ld @@ -0,0 +1,122 @@ +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 + DATA (rw) : ORIGIN = 0x1FFFC000, LENGTH = 0x0000C000 +} +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + _estack = .; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/mb9bf500r/fm3_rom.sct b/bsp/mb9bf500r/fm3_rom.sct new file mode 100644 index 0000000000..f1a09f4900 --- /dev/null +++ b/bsp/mb9bf500r/fm3_rom.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00040000 { ; load region size_region + ER_IROM1 0x00000000 0x00040000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00004000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/mb9bf500r/font.h b/bsp/mb9bf500r/font.h new file mode 100644 index 0000000000..0819a2c22d --- /dev/null +++ b/bsp/mb9bf500r/font.h @@ -0,0 +1,961 @@ +#ifndef __FONT_H +#define __FONT_H + +/* Font definition */ +#define ________ 0x00 +#define _______X 0x01 +#define ______X_ 0x02 +#define ______XX 0x03 +#define _____X__ 0x04 +#define _____X_X 0x05 +#define _____XX_ 0x06 +#define _____XXX 0x07 +#define ____X___ 0x08 +#define ____X__X 0x09 +#define ____X_X_ 0x0a +#define ____X_XX 0x0b +#define ____XX__ 0x0c +#define ____XX_X 0x0d +#define ____XXX_ 0x0e +#define ____XXXX 0x0f +#define ___X____ 0x10 +#define ___X___X 0x11 +#define ___X__X_ 0x12 +#define ___X__XX 0x13 +#define ___X_X__ 0x14 +#define ___X_X_X 0x15 +#define ___X_XX_ 0x16 +#define ___X_XXX 0x17 +#define ___XX___ 0x18 +#define ___XX__X 0x19 +#define ___XX_X_ 0x1a +#define ___XX_XX 0x1b +#define ___XXX__ 0x1c +#define ___XXX_X 0x1d +#define ___XXXX_ 0x1e +#define ___XXXXX 0x1f +#define __X_____ 0x20 +#define __X____X 0x21 +#define __X___X_ 0x22 +#define __X___XX 0x23 +#define __X__X__ 0x24 +#define __X__X_X 0x25 +#define __X__XX_ 0x26 +#define __X__XXX 0x27 +#define __X_X___ 0x28 +#define __X_X__X 0x29 +#define __X_X_X_ 0x2a +#define __X_X_XX 0x2b +#define __X_XX__ 0x2c +#define __X_XX_X 0x2d +#define __X_XXX_ 0x2e +#define __X_XXXX 0x2f +#define __XX____ 0x30 +#define __XX___X 0x31 +#define __XX__X_ 0x32 +#define __XX__XX 0x33 +#define __XX_X__ 0x34 +#define __XX_X_X 0x35 +#define __XX_XX_ 0x36 +#define __XX_XXX 0x37 +#define __XXX___ 0x38 +#define __XXX__X 0x39 +#define __XXX_X_ 0x3a +#define __XXX_XX 0x3b +#define __XXXX__ 0x3c +#define __XXXX_X 0x3d +#define __XXXXX_ 0x3e +#define __XXXXXX 0x3f +#define _X______ 0x40 +#define _X_____X 0x41 +#define _X____X_ 0x42 +#define _X____XX 0x43 +#define _X___X__ 0x44 +#define _X___X_X 0x45 +#define _X___XX_ 0x46 +#define _X___XXX 0x47 +#define _X__X___ 0x48 +#define _X__X__X 0x49 +#define _X__X_X_ 0x4a +#define _X__X_XX 0x4b +#define _X__XX__ 0x4c +#define _X__XX_X 0x4d +#define _X__XXX_ 0x4e +#define _X__XXXX 0x4f +#define _X_X____ 0x50 +#define _X_X___X 0x51 +#define _X_X__X_ 0x52 +#define _X_X__XX 0x53 +#define _X_X_X__ 0x54 +#define _X_X_X_X 0x55 +#define _X_X_XX_ 0x56 +#define _X_X_XXX 0x57 +#define _X_XX___ 0x58 +#define _X_XX__X 0x59 +#define _X_XX_X_ 0x5a +#define _X_XX_XX 0x5b +#define _X_XXX__ 0x5c +#define _X_XXX_X 0x5d +#define _X_XXXX_ 0x5e +#define _X_XXXXX 0x5f +#define _XX_____ 0x60 +#define _XX____X 0x61 +#define _XX___X_ 0x62 +#define _XX___XX 0x63 +#define _XX__X__ 0x64 +#define _XX__X_X 0x65 +#define _XX__XX_ 0x66 +#define _XX__XXX 0x67 +#define _XX_X___ 0x68 +#define _XX_X__X 0x69 +#define _XX_X_X_ 0x6a +#define _XX_X_XX 0x6b +#define _XX_XX__ 0x6c +#define _XX_XX_X 0x6d +#define _XX_XXX_ 0x6e +#define _XX_XXXX 0x6f +#define _XXX____ 0x70 +#define _XXX___X 0x71 +#define _XXX__X_ 0x72 +#define _XXX__XX 0x73 +#define _XXX_X__ 0x74 +#define _XXX_X_X 0x75 +#define _XXX_XX_ 0x76 +#define _XXX_XXX 0x77 +#define _XXXX___ 0x78 +#define _XXXX__X 0x79 +#define _XXXX_X_ 0x7a +#define _XXXX_XX 0x7b +#define _XXXXX__ 0x7c +#define _XXXXX_X 0x7d +#define _XXXXXX_ 0x7e +#define _XXXXXXX 0x7f +#define X_______ 0x80 +#define X______X 0x81 +#define X_____X_ 0x82 +#define X_____XX 0x83 +#define X____X__ 0x84 +#define X____X_X 0x85 +#define X____XX_ 0x86 +#define X____XXX 0x87 +#define X___X___ 0x88 +#define X___X__X 0x89 +#define X___X_X_ 0x8a +#define X___X_XX 0x8b +#define X___XX__ 0x8c +#define X___XX_X 0x8d +#define X___XXX_ 0x8e +#define X___XXXX 0x8f +#define X__X____ 0x90 +#define X__X___X 0x91 +#define X__X__X_ 0x92 +#define X__X__XX 0x93 +#define X__X_X__ 0x94 +#define X__X_X_X 0x95 +#define X__X_XX_ 0x96 +#define X__X_XXX 0x97 +#define X__XX___ 0x98 +#define X__XX__X 0x99 +#define X__XX_X_ 0x9a +#define X__XX_XX 0x9b +#define X__XXX__ 0x9c +#define X__XXX_X 0x9d +#define X__XXXX_ 0x9e +#define X__XXXXX 0x9f +#define X_X_____ 0xa0 +#define X_X____X 0xa1 +#define X_X___X_ 0xa2 +#define X_X___XX 0xa3 +#define X_X__X__ 0xa4 +#define X_X__X_X 0xa5 +#define X_X__XX_ 0xa6 +#define X_X__XXX 0xa7 +#define X_X_X___ 0xa8 +#define X_X_X__X 0xa9 +#define X_X_X_X_ 0xaa +#define X_X_X_XX 0xab +#define X_X_XX__ 0xac +#define X_X_XX_X 0xad +#define X_X_XXX_ 0xae +#define X_X_XXXX 0xaf +#define X_XX____ 0xb0 +#define X_XX___X 0xb1 +#define X_XX__X_ 0xb2 +#define X_XX__XX 0xb3 +#define X_XX_X__ 0xb4 +#define X_XX_X_X 0xb5 +#define X_XX_XX_ 0xb6 +#define X_XX_XXX 0xb7 +#define X_XXX___ 0xb8 +#define X_XXX__X 0xb9 +#define X_XXX_X_ 0xba +#define X_XXX_XX 0xbb +#define X_XXXX__ 0xbc +#define X_XXXX_X 0xbd +#define X_XXXXX_ 0xbe +#define X_XXXXXX 0xbf +#define XX______ 0xc0 +#define XX_____X 0xc1 +#define XX____X_ 0xc2 +#define XX____XX 0xc3 +#define XX___X__ 0xc4 +#define XX___X_X 0xc5 +#define XX___XX_ 0xc6 +#define XX___XXX 0xc7 +#define XX__X___ 0xc8 +#define XX__X__X 0xc9 +#define XX__X_X_ 0xca +#define XX__X_XX 0xcb +#define XX__XX__ 0xcc +#define XX__XX_X 0xcd +#define XX__XXX_ 0xce +#define XX__XXXX 0xcf +#define XX_X____ 0xd0 +#define XX_X___X 0xd1 +#define XX_X__X_ 0xd2 +#define XX_X__XX 0xd3 +#define XX_X_X__ 0xd4 +#define XX_X_X_X 0xd5 +#define XX_X_XX_ 0xd6 +#define XX_X_XXX 0xd7 +#define XX_XX___ 0xd8 +#define XX_XX__X 0xd9 +#define XX_XX_X_ 0xda +#define XX_XX_XX 0xdb +#define XX_XXX__ 0xdc +#define XX_XXX_X 0xdd +#define XX_XXXX_ 0xde +#define XX_XXXXX 0xdf +#define XXX_____ 0xe0 +#define XXX____X 0xe1 +#define XXX___X_ 0xe2 +#define XXX___XX 0xe3 +#define XXX__X__ 0xe4 +#define XXX__X_X 0xe5 +#define XXX__XX_ 0xe6 +#define XXX__XXX 0xe7 +#define XXX_X___ 0xe8 +#define XXX_X__X 0xe9 +#define XXX_X_X_ 0xea +#define XXX_X_XX 0xeb +#define XXX_XX__ 0xec +#define XXX_XX_X 0xed +#define XXX_XXX_ 0xee +#define XXX_XXXX 0xef +#define XXXX____ 0xf0 +#define XXXX___X 0xf1 +#define XXXX__X_ 0xf2 +#define XXXX__XX 0xf3 +#define XXXX_X__ 0xf4 +#define XXXX_X_X 0xf5 +#define XXXX_XX_ 0xf6 +#define XXXX_XXX 0xf7 +#define XXXXX___ 0xf8 +#define XXXXX__X 0xf9 +#define XXXXX_X_ 0xfa +#define XXXXX_XX 0xfb +#define XXXXXX__ 0xfc +#define XXXXXX_X 0xfd +#define XXXXXXX_ 0xfe +#define XXXXXXXX 0xff + + + + +const unsigned char FONTTYPE8_8[][8] = { +/* blank */ + { + ________, + ________, + ________, + ________, + ________, + ________, + ________, + ________} + +/* 0 */ + ,{ + __XXX___, + _XX_XX__, + XX___XX_, + XX___XX_, + XX___XX_, + _XX_XX__, + __XXX___, + ________} + +/* 1 */ + ,{ + ___XX___, + __XXX___, + ___XX___, + ___XX___, + ___XX___, + ___XX___, + _XXXXXX_, + ________} + +/* 2 */ + ,{ + _XXXXX__, + XX___XX_, + _____XX_, + ___XXX__, + __XX____, + _XX__XX_, + XXXXXXX_, + ________} + +/* 3 */ + ,{ + _XXXXX__, + XX___XX_, + _____XX_, + __XXXX__, + _____XX_, + XX___XX_, + _XXXXX__, + ________} + +/* 4 */ + ,{ + ___XXX__, + __XXXX__, + _XX_XX__, + XX__XX__, + XXXXXXX_, + ____XX__, + ___XXXX_, + ________} + +/* 5 */ + ,{ + XXXXXXX_, + XX______, + XX______, + XXXXXX__, + _____XX_, + XX___XX_, + _XXXXX__, + ________} + +/* 6 */ + ,{ + __XXX___, + _XX_____, + XX______, + XXXXXX__, + XX___XX_, + XX___XX_, + _XXXXX__, + ________} + +/* 7 */ + ,{ + XXXXXXX_, + XX___XX_, + ____XX__, + ___XX___, + __XX____, + __XX____, + __XX____, + ________} + +/* 8 */ + ,{ + _XXXXX__, + XX___XX_, + XX___XX_, + _XXXXX__, + XX___XX_, + XX___XX_, + _XXXXX__, + ________} + +/* 9 */ + ,{ + _XXXXX__, + XX___XX_, + XX___XX_, + _XXXXXX_, + _____XX_, + ____XX__, + _XXXX___, + ________} + +/* A */ + ,{ + __XXX___, + _XX_XX__, + XX___XX_, + XXXXXXX_, + XX___XX_, + XX___XX_, + XX___XX_, + ________} + +/* B */ + ,{ + XXXXXX__, + _XX__XX_, + _XX__XX_, + _XXXXX__, + _XX__XX_, + _XX__XX_, + XXXXXX__, + ________} + +/* C */ + ,{ + __XXXX__, + _XX__XX_, + XX______, + XX______, + XX______, + _XX__XX_, + __XXXX__, + ________} + +/* D */ + ,{ + XXXXX___, + _XX_XX__, + _XX__XX_, + _XX__XX_, + _XX__XX_, + _XX_XX__, + XXXXX___, + ________} + +/* E */ + ,{ + XXXXXXX_, + _XX___X_, + _XX_X___, + _XXXX___, + _XX_X___, + _XX___X_, + XXXXXXX_, + ________} + +/* F */ + ,{ + XXXXXXX_, + _XX___X_, + _XX_X___, + _XXXX___, + _XX_X___, + _XX_____, + XXXX____, + ________} + +/* G */ + ,{ + __XXXX__, + _XX__XX_, + XX______, + XX______, + XX__XXX_, + _XX__XX_, + __XXX_X_, + ________} + +/* H */ + ,{ + XX___XX_, + XX___XX_, + XX___XX_, + XXXXXXX_, + XX___XX_, + XX___XX_, + XX___XX_, + ________} + +/* I */ + ,{ + __XXXX__, + ___XX___, + ___XX___, + ___XX___, + ___XX___, + ___XX___, + __XXXX__, + ________} + +/* J */ + ,{ + ___XXXX_, + ____XX__, + ____XX__, + ____XX__, + XX__XX__, + XX__XX__, + _XXXX___, + ________} + +/* K */ + ,{ + XXX__XX_, + _XX__XX_, + _XX_XX__, + _XXXX___, + _XX_XX__, + _XX__XX_, + XXX__XX_, + ________} + +/* L */ + ,{ + XXXX____, + _XX_____, + _XX_____, + _XX_____, + _XX___X_, + _XX__XX_, + XXXXXXX_, + ________} + +/* M */ + ,{ + XX___XX_, + XXX_XXX_, + XXXXXXX_, + XXXXXXX_, + XX_X_XX_, + XX___XX_, + XX___XX_, + ________} + +/* N */ + ,{ + XX___XX_, + XXX__XX_, + XXXX_XX_, + XX_XXXX_, + XX__XXX_, + XX___XX_, + XX___XX_, + ________} + +/* O */ + ,{ + _XXXXX__, + XX___XX_, + XX___XX_, + XX___XX_, + XX___XX_, + XX___XX_, + _XXXXX__, + ________} + +/* P */ + ,{ + XXXXXX__, + _XX__XX_, + _XX__XX_, + _XXXXX__, + _XX_____, + _XX_____, + XXXX____, + ________} + +/* Q */ + ,{ + _XXXXX__, + XX___XX_, + XX___XX_, + XX___XX_, + XX___XX_, + XX__XXX_, + _XXXXX__, + ____XXX_} + +/* R */ + ,{ + XXXXXX__, + _XX__XX_, + _XX__XX_, + _XXXXX__, + _XX_XX__, + _XX__XX_, + XXX__XX_, + ________} + +/* S */ + ,{ + __XXXX__, + _XX__XX_, + __XX____, + ___XX___, + ____XX__, + _XX__XX_, + __XXXX__, + ________} + +/* T */ + ,{ + _XXXXXX_, + _XXXXXX_, + _X_XX_X_, + ___XX___, + ___XX___, + ___XX___, + __XXXX__, + ________} + +/* U */ + ,{ + XX___XX_, + XX___XX_, + XX___XX_, + XX___XX_, + XX___XX_, + XX___XX_, + _XXXXX__, + ________} + +/* V */ + ,{ + XX___XX_, + XX___XX_, + XX___XX_, + XX___XX_, + XX___XX_, + _XX_XX__, + __XXX___, + ________} + +/* W */ + ,{ + XX___XX_, + XX___XX_, + XX___XX_, + XX_X_XX_, + XX_X_XX_, + XXXXXXX_, + _XX_XX__, + ________} + +/* X */ + ,{ + XX___XX_, + XX___XX_, + _XX_XX__, + __XXX___, + _XX_XX__, + XX___XX_, + XX___XX_, + ________} + +/* Y */ + ,{ + _XX__XX_, + _XX__XX_, + _XX__XX_, + __XXXX__, + ___XX___, + ___XX___, + __XXXX__, + ________} + +/* Z */ + ,{ + XXXXXXX_, + XX___XX_, + X___XX__, + ___XX___, + __XX__X_, + _XX__XX_, + XXXXXXX_, + ________} + +/* a */ + ,{ + ________, + ________, + _XXXX___, + ____XX__, + _XXXXX__, + XX__XX__, + _XXX_XX_, + ________} + +/* b */ + ,{ + XXX_____, + _XX_____, + _XXXXX__, + _XX__XX_, + _XX__XX_, + _XX__XX_, + XX_XXX__, + ________} + +/* c */ + ,{ + ________, + ________, + _XXXXX__, + XX___XX_, + XX______, + XX___XX_, + _XXXXX__, + ________} + +/* d */ + ,{ + ___XXX__, + ____XX__, + _XXXXX__, + XX__XX__, + XX__XX__, + XX__XX__, + _XXX_XX_, + ________} + +/* e */ + ,{ + ________, + ________, + _XXXXX__, + XX___XX_, + XXXXXXX_, + XX______, + _XXXXX__, + ________} + +/* f */ + ,{ + __XXXX__, + _XX__XX_, + _XX_____, + XXXXX___, + _XX_____, + _XX_____, + XXXX____, + ________} + +/* g */ + ,{ + ________, + ________, + _XXX_XX_, + XX__XX__, + XX__XX__, + _XXXXX__, + ____XX__, + XXXXX___} + +/* h */ + ,{ + XXX_____, + _XX_____, + _XX_XX__, + _XXX_XX_, + _XX__XX_, + _XX__XX_, + XXX__XX_, + ________} + +/* i */ + ,{ + ___XX___, + ________, + __XXX___, + ___XX___, + ___XX___, + ___XX___, + __XXXX__, + ________} + +/* j */ + ,{ + _____XX_, + ________, + _____XX_, + _____XX_, + _____XX_, + _XX__XX_, + _XX__XX_, + __XXXX__} + +/* k */ + ,{ + XXX_____, + _XX_____, + _XX__XX_, + _XX_XX__, + _XXXX___, + _XX_XX__, + XXX__XX_, + ________} + +/* l */ + ,{ + __XXX___, + ___XX___, + ___XX___, + ___XX___, + ___XX___, + ___XX___, + __XXXX__, + ________} + +/* m */ + ,{ + ________, + ________, + XXX_XX__, + XXXXXXX_, + XX_X_XX_, + XX_X_XX_, + XX_X_XX_, + ________} + +/* n */ + ,{ + ________, + ________, + XX_XXX__, + _XX__XX_, + _XX__XX_, + _XX__XX_, + _XX__XX_, + ________} + +/* o */ + ,{ + ________, + ________, + _XXXXX__, + XX___XX_, + XX___XX_, + XX___XX_, + _XXXXX__, + ________} + +/* p */ + ,{ + ________, + ________, + XX_XXX__, + _XX__XX_, + _XX__XX_, + _XXXXX__, + _XX_____, + XXXX____} + +/* q */ + ,{ + ________, + ________, + _XXX_XX_, + XX__XX__, + XX__XX__, + _XXXXX__, + ____XX__, + ___XXXX_} + +/* r */ + ,{ + ________, + ________, + XX_XXX__, + _XXX_XX_, + _XX_____, + _XX_____, + XXXX____, + ________} + +/* s */ + ,{ + ________, + ________, + _XXXXXX_, + XX______, + _XXXXX__, + _____XX_, + XXXXXX__, + ________} + +/* t */ + ,{ + __XX____, + __XX____, + XXXXXX__, + __XX____, + __XX____, + __XX_XX_, + ___XXX__, + ________} + +/* u */ + ,{ + ________, + ________, + XX__XX__, + XX__XX__, + XX__XX__, + XX__XX__, + _XXX_XX_, + ________} + +/* v */ + ,{ + ________, + ________, + XX___XX_, + XX___XX_, + XX___XX_, + _XX_XX__, + __XXX___, + ________} + +/* w */ + ,{ + ________, + ________, + XX___XX_, + XX_X_XX_, + XX_X_XX_, + XXXXXXX_, + _XX_XX__, + ________} + +/* x */ + ,{ + ________, + ________, + XX___XX_, + _XX_XX__, + __XXX___, + _XX_XX__, + XX___XX_, + ________} + +/* y */ + ,{ + ________, + ________, + XX___XX_, + XX___XX_, + XX___XX_, + _XXXXXX_, + _____XX_, + XXXXXX__} + +/* z */ + ,{ + ________, + ________, + _XXXXXX_, + _X__XX__, + ___XX___, + __XX__X_, + _XXXXXX_, + ________} + +}; + +#endif /* __FONT_H */ diff --git a/bsp/mb9bf500r/info.c b/bsp/mb9bf500r/info.c new file mode 100644 index 0000000000..104d02a70f --- /dev/null +++ b/bsp/mb9bf500r/info.c @@ -0,0 +1,214 @@ +#include + +#ifdef RT_USING_RTGUI +#include +#include +#include + +#include +#include + +#include "adc.h" +#include "cpuusage.h" + +extern rt_uint16_t adc_value; +static rt_uint8_t index = 0 ; +static rt_bool_t view_event_handler(struct rtgui_widget* widget, struct rtgui_event* event) +{ + if (event->type == RTGUI_EVENT_PAINT) + { + struct rtgui_dc* dc; + struct rtgui_rect rect; + + dc = rtgui_dc_begin_drawing(widget); + if (dc == RT_NULL) + return RT_FALSE; + rtgui_widget_get_rect(widget, &rect); + + rtgui_dc_fill_rect(dc, &rect); + rect.x2 -= 1; rect.y2 -= 1; + rtgui_dc_draw_hline(dc, rect.x1, rect.x2, rect.y1); + rtgui_dc_draw_vline(dc, rect.x1, rect.y1, rect.y2); + + rtgui_dc_draw_hline(dc, rect.x1, rect.x2, rect.y2); + rtgui_dc_draw_vline(dc, rect.x2, rect.y1, rect.y2 + 1); + + /* shrink border */ + rtgui_rect_inflate(&rect, -1); + + /* draw text */ + rtgui_widget_get_rect(widget, &rect); + rect.y1 += 25; + rtgui_dc_draw_text(dc, " FM3 Easy Kit Demo", &rect); + rect.y1 += 10; + rtgui_dc_draw_text(dc, " rt-thread / RTGUI", &rect); + rtgui_dc_end_drawing(dc); + + return RT_FALSE; + } + else if (event->type == RTGUI_EVENT_KBD) + { + struct rtgui_dc* dc; + struct rtgui_rect rect; + struct rtgui_event_kbd* ekbd = (struct rtgui_event_kbd*)event; + if (ekbd->type == RTGUI_KEYDOWN) + { + char key_str[16]; + switch (ekbd->key) + { + case RTGUIK_LEFT: + rt_sprintf(key_str, "%s", "L"); + break; + case RTGUIK_RIGHT: + rt_sprintf(key_str, "%s", "R"); + break; + case RTGUIK_DOWN: + rt_sprintf(key_str, "%s", "D"); + break; + case RTGUIK_UP: + rt_sprintf(key_str, "%s", "U"); + break; + default: + rt_sprintf(key_str, "%s", "S"); + break; + } + dc = rtgui_dc_begin_drawing(widget); + if (dc == RT_NULL) + return RT_FALSE; + rect.x1 = 118; + rect.y1 = 1; + rect.x2 = 127; + rect.y2 = 10; + rtgui_dc_fill_rect(dc, &rect); + rtgui_dc_draw_text(dc, key_str, &rect); + rtgui_dc_end_drawing(dc); + } + else if (ekbd->type == RTGUI_KEYUP) + { + dc = rtgui_dc_begin_drawing(widget); + if (dc == RT_NULL) + return RT_FALSE; + rect.x1 = 118; + rect.y1 = 1; + rect.x2 = 127; + rect.y2 = 10; + rtgui_dc_fill_rect(dc, &rect); + //rtgui_dc_draw_text(dc, key_str, &rect); + rtgui_dc_end_drawing(dc); + } + } + else if (event->type == RTGUI_EVENT_COMMAND) + { + char str[16]; + struct rtgui_dc* dc; + struct rtgui_rect rect; + struct rtgui_event_command* ecmd; + rt_uint8_t major,minor; + dc = rtgui_dc_begin_drawing(widget); + if (dc == RT_NULL) + return RT_FALSE; + + ecmd = (struct rtgui_event_command*)event; + switch (ecmd->command_id) + { + case ADC_UPDATE: + rect.x1 = 1; + rect.y1 = 1; + rect.x2 = 117; + rect.y2 = 10; + rtgui_dc_fill_rect(dc, &rect); + rt_sprintf(str, "ADC = %d mv", adc_value); + rtgui_dc_draw_text(dc, str, &rect); + break; + case CPU_UPDATE: + cpu_usage_get(&major, &minor); + rect.x1 = 1; + rect.y1 = 12; + rect.x2 = 127; + rect.y2 = 22; + rtgui_dc_fill_rect(dc, &rect); + rt_sprintf(str, "CPU : %d.%d%", major, minor); + rtgui_dc_draw_text(dc, str, &rect); + + rect.y1 = 23; + rect.y2 = 63; + index++; + if (index == 127) + { + index = 1; + rtgui_dc_fill_rect(dc, &rect); + } + if (major>40) + rtgui_dc_draw_vline(dc, index, rect.y1, rect.y2); + else + rtgui_dc_draw_vline(dc, index, rect.y2-major, rect.y2); + break; + } + rtgui_dc_end_drawing(dc); + } + + return rtgui_view_event_handler(widget, event); +} + +static void info_entry(void* parameter) +{ + rt_mq_t mq; + struct rtgui_view* view; + struct rtgui_workbench* workbench; + + mq = rt_mq_create("qInfo", 256, 4, RT_IPC_FLAG_FIFO); + rtgui_thread_register(rt_thread_self(), mq); + + workbench = rtgui_workbench_create("info", "workbench"); + if(workbench == RT_NULL) + return; + + view = rtgui_view_create("view"); + RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(view)) = white; + RTGUI_WIDGET_FOREGROUND(RTGUI_WIDGET(view)) = black; + rtgui_widget_set_event_handler(RTGUI_WIDGET(view), view_event_handler); + + rtgui_workbench_add_view(workbench, view); + /* this view can be focused */ + RTGUI_WIDGET(view)->flag |= RTGUI_WIDGET_FLAG_FOCUSABLE; + /* set widget focus */ + rtgui_widget_focus(RTGUI_WIDGET(view)); + + rtgui_view_show(view, RT_FALSE); + + rtgui_workbench_event_loop(workbench); + + rtgui_thread_deregister(rt_thread_self()); + rt_mq_delete(mq); +} + +rt_thread_t info_tid; +void info_init() +{ + info_tid = rt_thread_create("info", + info_entry, RT_NULL, + 2048, 25, 10); + + if (info_tid != RT_NULL) rt_thread_startup(info_tid); +} + +void rtgui_startup() +{ + rtgui_rect_t rect; + + /* GUIϵͳ³õʼ»¯ */ + rtgui_system_server_init(); + + /* register dock panel */ + rect.x1 = 0; + rect.y1 = 0; + rect.x2 = 128; + rect.y2 = 64; + rtgui_panel_register("info", &rect); + rtgui_panel_set_default_focused("info"); + + /* Æô¶¯info workbench */ + info_init(); +} + +#endif diff --git a/bsp/mb9bf500r/key.c b/bsp/mb9bf500r/key.c new file mode 100644 index 0000000000..a03b48366a --- /dev/null +++ b/bsp/mb9bf500r/key.c @@ -0,0 +1,164 @@ +/* + * File : key.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-03-03 lgnq + */ + +#include +#include "key.h" +#include "lcd.h" + +#ifdef RT_USING_RTGUI +#include +#include +#endif + +static void key_io_init(void) +{ + /*Select CPIO function*/ + KEY_PFR &= ~KEY_MASK; + /*Set CPIO Pull-Up function*/ + KEY_PCR |= KEY_MASK; + /*Make button pins inputs*/ + KEY_DDR &= ~KEY_MASK; +} + +static void key_thread_entry(void *parameter) +{ +#ifdef RT_USING_RTGUI + rt_time_t next_delay; + rt_uint8_t i; + + struct rtgui_event_kbd kbd_event; + + key_io_init(); + + /* init keyboard event */ + RTGUI_EVENT_KBD_INIT(&kbd_event); + kbd_event.mod = RTGUI_KMOD_NONE; + kbd_event.unicode = 0; + + while (1) + { + next_delay = RT_TICK_PER_SECOND/10; + kbd_event.key = RTGUIK_UNKNOWN; + kbd_event.type = RTGUI_KEYDOWN; + + if (KEY_ENTER_GETVALUE() == 0 ) + { + for(i=0; ; i++) + { + rt_thread_delay( next_delay ); + if (KEY_ENTER_GETVALUE() == 0) + { + if (i>=4) + { + /* HOME key */ + kbd_event.key = RTGUIK_HOME; + next_delay = RT_TICK_PER_SECOND/5; + break; + } + } + else + { + kbd_event.key = RTGUIK_RETURN; + break; + } + } + } + + if (KEY_DOWN_GETVALUE() == 0) + { + kbd_event.key = RTGUIK_DOWN; + } + + if (KEY_UP_GETVALUE() == 0) + { + kbd_event.key = RTGUIK_UP; + } + + if (KEY_RIGHT_GETVALUE() == 0) + { + kbd_event.key = RTGUIK_RIGHT; + } + + if (KEY_LEFT_GETVALUE() == 0) + { + kbd_event.key = RTGUIK_LEFT; + } + + if (kbd_event.key != RTGUIK_UNKNOWN) + { + /* post down event */ + rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event)); + } + else + { + kbd_event.type = RTGUI_KEYUP; + rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event)); + } + /* wait next key press */ + rt_thread_delay(next_delay); + } +#else + extern struct rt_messagequeue mq; + rt_time_t next_delay; + struct lcd_msg msg; + msg.type = KEY_MSG; + + key_io_init(); + + while (1) + { + msg.key = NO_KEY; + + next_delay = RT_TICK_PER_SECOND/10; + + if (KEY_ENTER_GETVALUE() == 0 ) + { + msg.key = KEY_ENTER; + } + + if (KEY_DOWN_GETVALUE() == 0) + { + msg.key = KEY_DOWN; + } + + if (KEY_UP_GETVALUE() == 0) + { + msg.key = KEY_UP; + } + + if (KEY_RIGHT_GETVALUE() == 0) + { + msg.key = KEY_RIGHT; + } + + if (KEY_LEFT_GETVALUE() == 0) + { + msg.key = KEY_LEFT; + } + + rt_mq_send(&mq, &msg, sizeof(msg)); + + /* wait next key press */ + rt_thread_delay(next_delay); + } +#endif +} + +static rt_thread_t key_thread; +void rt_hw_key_init(void) +{ + key_thread = rt_thread_create("key", key_thread_entry, RT_NULL, 384, 28, 5); + if (key_thread != RT_NULL) + rt_thread_startup(key_thread); +} diff --git a/bsp/mb9bf500r/key.h b/bsp/mb9bf500r/key.h new file mode 100644 index 0000000000..3b47c7b1bb --- /dev/null +++ b/bsp/mb9bf500r/key.h @@ -0,0 +1,47 @@ +/* + * File : key.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-03-06 lgnq + */ +#ifndef __KEY_H__ +#define __KEY_H__ + +#include "mb9bf506r.h" + +#define KEY_DOWN (1<<0) +#define KEY_ENTER (1<<1) +#define KEY_LEFT (1<<2) +#define KEY_RIGHT (1<<3) +#define KEY_UP (1<<4) +#define NO_KEY (1<<5) + +#define KEY_MASK (KEY_DOWN | KEY_ENTER | KEY_LEFT | KEY_RIGHT | KEY_UP) +#define KEY_PFR (FM3_GPIO->PFR7) +#define KEY_PCR (FM3_GPIO->PCR7) +#define KEY_PDIR (FM3_GPIO->PDIR7) +#define KEY_DDR (FM3_GPIO->DDR7) + +#define RT_DEVICE_CTRL_KEY_SCAN 0 +#define RT_DEVICE_CTRL_KEY_STATUS 1 + +#define SET_BIT(byte, bit) ((byte) |= (1<<(bit))) +#define CLR_BIT(byte, bit) ((byte) &= ~(1<<(bit))) +#define TST_BIT(byte, bit) (((byte) & (1<<(bit)))?1:0) + +#define KEY_ENTER_GETVALUE() TST_BIT(KEY_PDIR, 1) +#define KEY_DOWN_GETVALUE() TST_BIT(KEY_PDIR, 0) +#define KEY_UP_GETVALUE() TST_BIT(KEY_PDIR, 4) +#define KEY_RIGHT_GETVALUE() TST_BIT(KEY_PDIR, 3) +#define KEY_LEFT_GETVALUE() TST_BIT(KEY_PDIR, 2) + +void rt_hw_key_init(void); + +#endif diff --git a/bsp/mb9bf500r/lcd.c b/bsp/mb9bf500r/lcd.c new file mode 100644 index 0000000000..b665a61378 --- /dev/null +++ b/bsp/mb9bf500r/lcd.c @@ -0,0 +1,481 @@ +/* + * File : lcd.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-03-05 lgnq ZYMG12864C3 LCD driver + */ + +#include +#include "lcd.h" +#include "font.h" + +static struct rt_device_graphic_info _lcd_info; +static rt_uint8_t gui_disp_buf[GUI_LCM_YMAX/8][GUI_LCM_XMAX]; +const unsigned char BIT_MASK[8] = {0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01}; +/* simple font: ' ', '0'~'9','a'~'z','A'~'Z' */ +extern const unsigned char FONTTYPE8_8[][8]; + +rt_uint32_t x; +rt_uint32_t y; + +void power_delay(void) +{ + rt_uint32_t i = 0x4ffff; + while(i--) + ; +} + +void delay(void) +{ + rt_uint8_t i = 0x8; + while(i--) + ; +} + +void reset_delay(void) +{ + rt_uint8_t i = 0xff; + while(i--) + ; +} + +void lcd_write_cmd(unsigned char command) +{ + rt_uint8_t i; + + LCD_PS_LOW(); + LCD_CS_LOW(); + LCD_CD_LOW(); + for (i=0; i<8; i++) + { + if (command & (0x80 >> i)) + LCD_DATA_HIGH(); + else + LCD_DATA_LOW(); + + LCD_CLK_LOW(); + delay(); + LCD_CLK_HIGH(); + delay(); + } + LCD_CS_HIGH(); +} + +void lcd_write_data(unsigned char data) +{ + rt_uint8_t i; + + LCD_PS_LOW(); + LCD_CS_LOW(); + LCD_CD_HIGH(); + for (i=0; i<8; i++) + { + if (data & (0x80 >> i)) + LCD_DATA_HIGH(); + else + LCD_DATA_LOW(); + + LCD_CLK_LOW(); + delay(); + LCD_CLK_HIGH(); + delay(); + } + LCD_CS_HIGH(); +} + +#ifdef RT_USING_RTGUI +#include +#include + +static void rt_hw_lcd_update(struct rt_device_rect_info *rect_info) +{ + rt_uint8_t i,j = GUI_LCM_XMAX; + rt_uint8_t* p = (rt_uint8_t*)gui_disp_buf; + + for (i=0; i> 4; + lcd_write_cmd(SET_PAGE_ADDR_0 | page); + lcd_write_cmd(SET_COLH_ADDR_0 | colh); + lcd_write_cmd(SET_COLL_ADDR_0 | coll); + lcd_write_data(gui_disp_buf[page][i]); + } +} + +const struct rtgui_graphic_driver_ops _lcd_ops = +{ + rt_hw_lcd_set_pixel, + rt_hw_lcd_get_pixel, + rt_hw_lcd_draw_hline, + rt_hw_lcd_draw_vline, + rt_hw_lcd_draw_raw_hline +}; +#endif + +void lcd_io_init() +{ + /* Release the analog input function*/ + FM3_GPIO->ADE =0x03; + /*Select CPIO function*/ + LCD_CS_PFR &= ~LCD_CS; + /*Make pin output*/ + LCD_CS_DDR |= LCD_CS; + /*Select CPIO function*/ + LCD_CD_PFR &= ~LCD_CD; + /*Make pin output*/ + LCD_CD_DDR |= LCD_CD; + /*Select CPIO function*/ + LCD_PS_PFR &= ~LCD_PS; + /*Make pin output*/ + LCD_PS_DDR |= LCD_PS; + /*Select CPIO function*/ + LCD_CLK_PFR &= ~LCD_CLK; + /*Make pin output*/ + LCD_CLK_DDR |= LCD_CLK; + /*Select CPIO function*/ + LCD_DATA_PFR &= ~LCD_DATA; + /*Make pin output*/ + LCD_DATA_DDR |= LCD_DATA; +} + +/* RT-Thread Device Interface */ +static rt_err_t rt_lcd_init (rt_device_t dev) +{ + lcd_io_init(); + + power_delay(); + lcd_write_cmd(DISPLAY_OFF); + reset_delay(); + // Resetting circuit + lcd_write_cmd(RESET_LCD); + reset_delay(); + // LCD bias setting + lcd_write_cmd(SET_LCD_BIAS_9); + reset_delay(); + // ADC selection: display from left to right + lcd_write_cmd(SET_ADC_NORMAL); + reset_delay(); + // Common output state selection: display from up to down + lcd_write_cmd(COM_SCAN_DIR_REVERSE); + reset_delay(); + + lcd_write_cmd(POWER_BOOSTER_ON); + power_delay(); // 50ms requried + lcd_write_cmd(POWER_REGULATOR_ON); + power_delay(); // 50ms + lcd_write_cmd(POWER_FOLLOWER_ON); + power_delay(); // 50ms + + // Setting the built-in resistance radio for regulation of the V0 voltage + // Electronic volume control + // Power control setting + lcd_write_cmd(SET_ELECVOL_REG|0x05); + delay(); + lcd_write_cmd(SET_ELECVOL_MODE); + delay(); + lcd_write_cmd(SET_ELECVOL_REG); + delay(); + // LCD_Clear(); + delay(); + lcd_write_cmd(SET_PAGE_ADDR_0); + delay(); + lcd_write_cmd(SET_COLH_ADDR_0); + delay(); + lcd_write_cmd(SET_COLL_ADDR_0); + delay(); + lcd_write_cmd(DISPLAY_ON); + delay(); + + lcd_write_cmd(DISPLAY_ALL_ON); + delay(); + lcd_write_cmd(DISPLAY_OFF); + delay(); + lcd_write_cmd(DISPLAY_ON); + delay(); + lcd_write_cmd(DISPLAY_ALL_NORMAL); + delay(); + + return RT_EOK; +} + +/******************************************************************************* +* Function Name : LCD_FillAll +* Description : Fill the whole LCD. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void LCD_FillAll(unsigned char* buffer) +{ + unsigned char i,j = GUI_LCM_XMAX; + unsigned char* p = buffer; + + for (i=0; i> 4; + + lcd_write_cmd(SET_PAGE_ADDR_0 | page); // page no. + lcd_write_cmd(SET_COLH_ADDR_0 | colh); // fixed col first addr + lcd_write_cmd(SET_COLL_ADDR_0 | coll); + lcd_write_data(gui_disp_buf[page][x]); +} + +/**************************************************************************** +* Function Name : LCD_PutChar +* Description : output a char to screen + (the char only can be ' ','0'~'9','A'~'Z','a'~'z') +* Input : x X-coordinate + y Y-coordinate + ch character +* Output : None +* Return : 1 Success + 0 Fail +****************************************************************************/ +unsigned char LCD_PutChar(unsigned long x, unsigned long y, unsigned char ch) +{ + unsigned char data; + unsigned char i, j; + + if( x >=(GUI_LCM_XMAX-8) ) return(0); + if( y >=(GUI_LCM_YMAX-8) ) return(0); + + if(ch == 0x20) + ch -= 0x20; + else if((ch >= 0x30)&&(ch <= 0x39)) + ch -= 0x2f; + else if((ch >= 0x41)&&(ch <= 0x5a)) + ch -= 0x36; + else if((ch >= 0x61)&&(ch <= 0x7a)) + ch -= 0x3C; + else + return(0); + + for(i = 0; i < 8; i++) + { + data = FONTTYPE8_8[ch][i]; + + for(j = 0; j < 8; j++) + { + if( (data&BIT_MASK[j]) == 0) + gui_disp_buf[y / 8][x] &= (~(0x01 << ( y % 8))); + else + gui_disp_buf[y / 8][x] |= (0x01 <<( y % 8)); + LCD_UpdatePoint(x, y); + x ++; + } + x -= 8; + y++; + } + + return(1); +} + +/**************************************************************************** +* Function Name : LCD_PutString +* Description : output string to screen +* Input : x X-coordinate + y Y-coordinate + str pointer to string +* Output : None +* Return : None +****************************************************************************/ +void LCD_PutString(unsigned long x, unsigned long y, char *str) +{ + while(1) + { + if( (*str)=='\0' ) break; + if( LCD_PutChar(x, y, *str++) == 0 ) break; + x += 6; + } +} + +static rt_err_t rt_lcd_control (rt_device_t dev, rt_uint8_t cmd, void *args) +{ + switch (cmd) + { +#ifdef RT_USING_RTGUI + case RTGRAPHIC_CTRL_RECT_UPDATE: + rt_hw_lcd_update(args); + break; + case RTGRAPHIC_CTRL_POWERON: + break; + case RTGRAPHIC_CTRL_POWEROFF: + break; + case RTGRAPHIC_CTRL_GET_INFO: + rt_memcpy(args, &_lcd_info, sizeof(_lcd_info)); + break; + case RTGRAPHIC_CTRL_SET_MODE: + break; +#else + case RT_DEVICE_CTRL_LCD_DISPLAY_ON: + lcd_write_cmd(DISPLAY_ON); + break; + case RT_DEVICE_CTRL_LCD_DISPLAY_OFF: + lcd_write_cmd(DISPLAY_OFF); + break; + case RT_DEVICE_CTRL_LCD_PUT_STRING: + LCD_PutString(x, y, (char*)args); + break; + case RT_DEVICE_CTRL_LCD_CLEAR_SCR: + LCD_ClearSCR(); + break; +#endif + } + + return RT_EOK; +} + +void rt_hw_lcd_init(void) +{ + rt_device_t lcd = rt_malloc(sizeof(struct rt_device)); + if (lcd == RT_NULL) return; /* no memory yet */ + + _lcd_info.bits_per_pixel = 16; + _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565; + _lcd_info.framebuffer = RT_NULL; + _lcd_info.width = LCD_WIDTH; + _lcd_info.height = LCD_HEIGHT; + + /* init device structure */ + lcd->type = RT_Device_Class_Unknown; + lcd->init = rt_lcd_init; + lcd->open = RT_NULL; + lcd->close = RT_NULL; + lcd->control = rt_lcd_control; +#ifdef RT_USING_RTGUI + lcd->user_data = (void*)&_lcd_ops; +#endif + /* register lcd device to RT-Thread */ + rt_device_register(lcd, "lcd", RT_DEVICE_FLAG_RDWR); +} diff --git a/bsp/mb9bf500r/lcd.h b/bsp/mb9bf500r/lcd.h new file mode 100644 index 0000000000..d1c9877897 --- /dev/null +++ b/bsp/mb9bf500r/lcd.h @@ -0,0 +1,189 @@ +/* + * File : lcd.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2008-03-29 Yi.Qiu + * 2011-06-13 lgnq modified for FM3 easy kit + */ +#ifndef __LCD_H__ +#define __LCD_H__ + +#include +#include "mb9bf506r.h" + +/********* LCD Hardward Interface ************* +LCD_CS PORT1.7 +LCD_CD PORT1.6 +LCD_WR PORT1.5 +LCD_RD PORT1.4 +LCD_SCK PORT1.3 +LCD_MOSI PORT1.2 +LCD_C86 PORT1.1 +LCD_PS PORT1.0 +LCD_DATA[0..7] PORT5.[0..7] +***********************************************/ +#define LCD_CS (1UL << 7) +#define LCD_CS_DDR (FM3_GPIO->DDR1) +#define LCD_CS_PFR (FM3_GPIO->PFR1) +#define LCD_CS_PDOR (FM3_GPIO->PDOR1) + +#define LCD_CD (1UL << 6) +#define LCD_CD_DDR (FM3_GPIO->DDR1) +#define LCD_CD_PFR (FM3_GPIO->PFR1) +#define LCD_CD_PDOR (FM3_GPIO->PDOR1) + +#define LCD_PS (1UL << 0) +#define LCD_PS_DDR (FM3_GPIO->DDR1) +#define LCD_PS_PFR (FM3_GPIO->PFR1) +#define LCD_PS_PDOR (FM3_GPIO->PDOR1) + +#define LCD_CLK (1UL << 6) +#define LCD_CLK_DDR (FM3_GPIO->DDR5) +#define LCD_CLK_PFR (FM3_GPIO->PFR5) +#define LCD_CLK_PDOR (FM3_GPIO->PDOR5) + +#define LCD_DATA (1UL << 7) +#define LCD_DATA_DDR (FM3_GPIO->DDR5) +#define LCD_DATA_PFR (FM3_GPIO->PFR5) +#define LCD_DATA_PDOR (FM3_GPIO->PDOR5) + +/* LCD driver for ZYMG12864C3 */ +#define LCD_WIDTH 128 +#define LCD_HEIGHT 64 + +// Driver the LCD with Parallel or serial interface and the command/data control pin is gpio +#define LCD_CS_HIGH() LCD_CS_PDOR |= LCD_CS +#define LCD_CS_LOW() LCD_CS_PDOR &= ~LCD_CS + +#define LCD_CD_HIGH() LCD_CD_PDOR |= LCD_CD +#define LCD_CD_LOW() LCD_CD_PDOR &= ~LCD_CD + +#define LCD_PS_HIGH() LCD_PS_PDOR |= LCD_PS +#define LCD_PS_LOW() LCD_PS_PDOR &= ~LCD_PS + +#define LCD_CLK_HIGH() LCD_CLK_PDOR |= LCD_CLK +#define LCD_CLK_LOW() LCD_CLK_PDOR &= ~LCD_CLK + +#define LCD_DATA_HIGH() LCD_DATA_PDOR |= LCD_DATA +#define LCD_DATA_LOW() LCD_DATA_PDOR &= ~LCD_DATA + +// define the arrtibute of ZYMG12864(LCM) +#define GUI_LCM_XMAX 128 // defined the lcd's line-number is 128 +#define GUI_LCM_YMAX 64 // defined the lcd's column-number is 64 +#define GUI_LCM_PAGE 8 // defined the lcd's page-number is 8(GUI_LCM_YMAX/8) + +/* set LCD command */ +#define DISPLAY_ON 0xAF // A0,RD,WR:010 +#define DISPLAY_OFF 0xAE // A0,RD,WR:010 + +#define SET_START_LINE_0 0x40 // A0,RD,WR:010; line0~line63 +#define SET_PAGE_ADDR_0 0xB0 // A0,RD,WR:010; addr0~addr8 +#define SET_COLH_ADDR_0 0x10 // A0,RD,WR:010; +#define SET_COLL_ADDR_0 0x00 // A0,RD,WR:010; addr0~addr131 + +#define READ_STATUS 0x-0 // A0,RD,WR:001; BUSY | ADC | ON/OFF | RESET | 0 0 0 0 +#define STATUS_BUSY 0x80 +#define STATUS_ADC_REVERSE 0x40 // column address 131-n : SEG n, else column address n : SEG n +#define STATUS_DISPLAY_OFF 0x20 +#define STATUS_RESET 0x80 + +#define WRITE_DATA 0x-- // A0,RD,WR:110 +#define READ_DATE 0x-- // A0,RD,WR:101; spi mode is unavailable + +#define SET_ADC_NORMAL 0xA0 // A0,RD,WR:010 +#define SET_ADC_REVERSE 0xA1 // A0,RD,WR:010 +#define DISPLAY_NORMAL 0xA6 // A0,RD,WR:010 +#define DISPLAY_REVERSE 0xA7 // A0,RD,WR:010; reverse color +#define DISPLAY_ALL_ON 0xA5 // A0,RD,WR:010 +#define DISPLAY_ALL_NORMAL 0xA4 // A0,RD,WR:010 + +/************************************************************* +* bias: 1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty * +* ---------------|----------|----------|----------|--------- * +* A2: 1/9 bias | 1/8 bias | 1/6 bias | 1/8 bias | 1/8 bias * +* A3: 1/7 bias | 1/6 bias | 1/5 bias | 1/6 bias | 1/6 bias * +**************************************************************/ + +#define SET_LCD_BIAS_7 0xA3 // A0,RD,WR:010 +#define SET_LCD_BIAS_9 0xA2 // A0,RD,WR:010 + +#define RMW_MODE_ENABLE 0xE0 // A0,RD,WR:010; the column address locked when read command operating +#define RMW_MODE_END 0xEE // A0,RD,WR:010; returns to the column address when RMW was entered. +#define RESET_LCD 0xE2 // A0,RD,WR:010 + + +/************************************************************************************** +* Com Scan Dir: | 1/65duty | 1/49duty | 1/33duty | 1/55duty | 1/53duty * +* --------------|-------------|-------------|-------------|------------------------ * +* C0: Normal | COM0:COM63 | COM0:COM47 | COM0:COM31 | COM0:COM53 | COM0:COM51 * +* C8: Reverse | COM63:COM0 | COM47:COM0 | COM31:COM0 | COM53:COM0 | COM51:COM0 * +***************************************************************************************/ + +#define COM_SCAN_DIR_NORMAL 0xC0 // A0,RD,WR:010 +#define COM_SCAN_DIR_REVERSE 0xC8 // A0,RD,WR:010 + +// 0 0 1 0 1 | Booster On | Regulator On | Follower On +#define POWER_BOOSTER_ON 0x2C // A0,RD,WR:010 +#define POWER_REGULATOR_ON 0x2E // A0,RD,WR:010 +#define POWER_FOLLOWER_ON 0x2F // A0,RD,WR:010 + +#define SET_RESISTOR_RATIO 0x20 // A0,RD,WR:010; 20~27:small~large + +#define SET_ELECVOL_MODE 0x81 // A0,RD,WR:010; double byte command +#define SET_ELECVOL_REG 0x20 // A0,RD,WR:010; the electronic volume(64 voltage levels:00~3F) function is not used. + +#define SLEEP_MODE_ENABLE 0xAC // A0,RD,WR:010; double byte command, preceding command +#define SLEEP_MODE_DISABLE 0xAD // A0,RD,WR:010; preceding command +#define SLEEP_MODE_DELIVER 0x00 // A0,RD,WR:010; following command + +#define BOOST_RATIO_SET 0xF8 // A0,RD,WR:010; double byte command, preceding command +#define BOOST_RATIO_234 0x00 // A0,RD,WR:010; following command +#define BOOST_RATIO_5 0x01 // A0,RD,WR:010; following command +#define BOOST_RATIO_6 0x03 // A0,RD,WR:010; following command + +#define COMMAND_NOP 0xE3 // A0,RD,WR:010 +#define COMMAND_IC_TEST 0xFC // A0,RD,WR:010; don't use + +#define RT_DEVICE_CTRL_LCD_GET_WIDTH 0 +#define RT_DEVICE_CTRL_LCD_GET_HEIGHT 1 +#define RT_DEVICE_CTRL_LCD_GET_BPP 2 +#define RT_DEVICE_CTRL_LCD_GET_FRAMEBUFFER 3 +#define RT_DEVICE_CTRL_LCD_POWER_ON 4 +#define RT_DEVICE_CTRL_LCD_POWER_OFF 5 +#define RT_DEVICE_CTRL_LCD_CLEAR_SCR 6 +#define RT_DEVICE_CTRL_LCD_FILL_ALL 7 +#define RT_DEVICE_CTRL_LCD_UPDATE_POINT 8 +#define RT_DEVICE_CTRL_LCD_DISPLAY_ON 9 +#define RT_DEVICE_CTRL_LCD_DISPLAY_OFF 10 +#define RT_DEVICE_CTRL_LCD_PUT_STRING 11 + +enum +{ + ADC_MSG, + KEY_MSG, + CPU_MSG, + MAX_MSG, +}; + +struct lcd_msg +{ + rt_uint8_t type; + rt_uint16_t adc_value; + rt_uint8_t key; + rt_uint16_t major; + rt_uint16_t minor; +}; + +extern rt_uint32_t x; +extern rt_uint32_t y; + +void rt_hw_lcd_init(void); + +#endif diff --git a/bsp/mb9bf500r/led.c b/bsp/mb9bf500r/led.c new file mode 100644 index 0000000000..b72042d39e --- /dev/null +++ b/bsp/mb9bf500r/led.c @@ -0,0 +1,150 @@ +/* + * File : led.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-03-03 lgnq + */ + +#include +#include + +#include "mb9bf506r.h" +#include "led.h" + +void rt_hw_led_on(rt_uint8_t num) +{ + RT_ASSERT(num < LEDS_MAX_NUMBER); + + switch (num) + { + case 1: + LED_PDOR &= ~LED1; + break; + case 2: + LED_PDOR &= ~LED2; + break; + case 3: + LED_PDOR &= ~LED3; + break; + default: + break; + } +} + +void rt_hw_led_off(rt_uint8_t num) +{ + RT_ASSERT(num < LEDS_MAX_NUMBER); + + switch (num) + { + case 1: + LED_PDOR |= LED1; + break; + case 2: + LED_PDOR |= LED2; + break; + case 3: + LED_PDOR |= LED3; + break; + default: + break; + } +} + +void rt_hw_led_toggle(rt_uint8_t num) +{ + RT_ASSERT(num < LEDS_MAX_NUMBER); + + switch (num) + { + case 1: + if (LED_PDOR&LED1) + LED_PDOR &= ~LED1; + else + LED_PDOR |= LED1; + break; + case 2: + if (LED_PDOR&LED2) + LED_PDOR &= ~LED2; + else + LED_PDOR |= LED2; + break; + case 3: + if (LED_PDOR&LED3) + LED_PDOR &= ~LED3; + else + LED_PDOR |= LED3; + break; + default: + break; + } +} + +static rt_err_t led_io_init(void) +{ + /*Select CPIO function*/ + LED_PFR &= ~LED_MASK; + /*Set Pin to turn off leds*/ + LED_PDOR |= LED_MASK; + /*Make led pins outputs*/ + LED_DDR |= LED_MASK; + + //LED3 is controled by PWM + FM3_GPIO->PFR3 = 0x1000; + FM3_GPIO->EPFR04 = 0x00080000; + FM3_BT2_PWM->TMCR = 0x0018; + FM3_BT2_PWM->TMCR2 = 0x01; /* cks=0b1000 count clk 1/512 */ + FM3_BT2_PWM->STC = 0x00; + FM3_BT2_PWM->PCSR = 0x61A; /* Down count = 1562 */ + FM3_BT2_PWM->PDUT = 0x0; /* Duty count = 16/1562=10% */ + + FM3_BT2_PWM->TMCR |= 0x03; /* start base timer(softwere TRG) */ + return RT_EOK; +} + +void pwm_update(rt_uint16_t value) +{ + FM3_BT2_PWM->PDUT = value; +} + +static void led1_thread_entry(void *parameter) +{ + while (1) + { + rt_hw_led_toggle(1); + rt_thread_delay(RT_TICK_PER_SECOND); + } +} + +static void led2_thread_entry(void *parameter) +{ + while (1) + { + rt_hw_led_toggle(2); + rt_thread_delay(RT_TICK_PER_SECOND/2); + } +} + +static rt_thread_t led1_thread; +static rt_thread_t led2_thread; +void rt_hw_led_init(void) +{ + led_io_init(); + + led1_thread = rt_thread_create("led1", led1_thread_entry, RT_NULL, 384, 29, 5); + if (led1_thread != RT_NULL) + rt_thread_startup(led1_thread); + + led2_thread = rt_thread_create("led2", led2_thread_entry, RT_NULL, 384, 30, 5); + if (led2_thread != RT_NULL) + rt_thread_startup(led2_thread); +} + + diff --git a/bsp/mb9bf500r/led.h b/bsp/mb9bf500r/led.h new file mode 100644 index 0000000000..5610a09f71 --- /dev/null +++ b/bsp/mb9bf500r/led.h @@ -0,0 +1,42 @@ +/* + * File : led.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-03-03 lgnq + */ + +#ifndef __LED_H__ +#define __LED_H__ + +#include "mb9bf506r.h" + +#define LEDS_MAX_NUMBER 4 + +/*LEDs*/ +#define LED1 (1UL<<10) +#define LED2 (1UL<<11) +#define LED3 (1UL<<12) +#define LED_MASK (LED1 | LED2 | LED3) + +#define LED_PFR (FM3_GPIO->PFR3) +#define LED_DDR (FM3_GPIO->DDR3) +#define LED_PDOR (FM3_GPIO->PDOR3) + +#define RT_DEVICE_CTRL_LED_ON 0 +#define RT_DEVICE_CTRL_LED_OFF 1 +#define RT_DEVICE_CTRL_LED_TOGGLE 2 + +void rt_hw_led_init(void); +void rt_hw_led_on(rt_uint8_t num); +void rt_hw_led_off(rt_uint8_t num); +void rt_hw_led_toggle(rt_uint8_t num); +void pwm_update(rt_uint16_t value); + +#endif diff --git a/bsp/mb9bf500r/mb9bf500r.icf b/bsp/mb9bf500r/mb9bf500r.icf new file mode 100644 index 0000000000..ff723823ce --- /dev/null +++ b/bsp/mb9bf500r/mb9bf500r.icf @@ -0,0 +1,32 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x1FFFC000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x800; +define symbol __ICFEDIT_size_heap__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +//initialize by copy with packing = none { section __DLIB_PERTHREAD }; // Required in a multi-threaded application +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/mb9bf500r/project.uvopt b/bsp/mb9bf500r/project.uvopt new file mode 100644 index 0000000000..9605f929c6 --- /dev/null +++ b/bsp/mb9bf500r/project.uvopt @@ -0,0 +1,586 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + + + + 0 + 0 + + + + RT-Thread FM3 + 0x4 + ARM-ADS + + 4000000 + + 1 + 1 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\obj\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM3 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 0 + 0 + 7 + + + + + + + + + + + Segger\JL2CM3.dll + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + Startup + 1 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 43 + 0 + 121 + 121 + 0 + .\application.c + application.c + + + 1 + 2 + 1 + 0 + 0 + 20 + 0 + 32 + 34 + 0 + .\board.c + board.c + + + 1 + 3 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\startup.c + startup.c + + + 1 + 4 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\adc.c + adc.c + + + 1 + 5 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\cpuusage.c + cpuusage.c + + + 1 + 6 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\key.c + key.c + + + 1 + 7 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\lcd.c + lcd.c + + + 1 + 8 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\led.c + led.c + + + 1 + 9 + 1 + 0 + 0 + 39 + 0 + 14 + 25 + 0 + .\info.c + info.c + + + + + FM3 + 1 + 0 + 0 + + 2 + 10 + 2 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + ..\..\libcpu\arm\cortex-m3\context_rvds.S + context_rvds.S + + + 2 + 11 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\libcpu\arm\cortex-m3\cpuport.c + cpuport.c + + + + + CMSIS + 1 + 0 + 0 + + 3 + 12 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\CMSIS\core_cm3.c + core_cm3.c + + + 3 + 13 + 2 + 0 + 0 + 0 + 0 + 1 + 1 + 0 + .\CMSIS\start_rvds.S + start_rvds.S + + + 3 + 14 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + .\CMSIS\system_mb9bf50x.c + system_mb9bf50x.c + + + + + Kernel + 1 + 0 + 0 + + 4 + 15 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\clock.c + clock.c + + + 4 + 16 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\device.c + device.c + + + 4 + 17 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\idle.c + idle.c + + + 4 + 18 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\ipc.c + ipc.c + + + 4 + 19 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\irq.c + irq.c + + + 4 + 20 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\kservice.c + kservice.c + + + 4 + 21 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\mem.c + mem.c + + + 4 + 22 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\mempool.c + mempool.c + + + 4 + 23 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\module.c + module.c + + + 4 + 24 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\object.c + object.c + + + 4 + 25 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\rtm.c + rtm.c + + + 4 + 26 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\scheduler.c + scheduler.c + + + 4 + 27 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\slab.c + slab.c + + + 4 + 28 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\thread.c + thread.c + + + 4 + 29 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ..\..\src\timer.c + timer.c + + + + diff --git a/bsp/mb9bf500r/project.uvproj b/bsp/mb9bf500r/project.uvproj new file mode 100644 index 0000000000..ec6c7f4b64 --- /dev/null +++ b/bsp/mb9bf500r/project.uvproj @@ -0,0 +1,555 @@ + + + + 1.1 + +
### uVision Project, (C) Keil Software
+ + + + RT-Thread FM3 + 0x4 + ARM-ADS + + + MB9BF500R + Fujitsu Semiconductors + IRAM(0x20000000-0x20003FFF) IROM(0x00000000-0x0003FFFF) CLOCK(4000000) CPUTYPE("Cortex-M3") + + "STARTUP\FUJITSU\MB9BF50x\startup_MB9BF50x.s" ("Fujitsu MB9BF50x Startup Code") + UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0MB9BF50x_256 -FS00 -FL040000) + 5155 + MB9BF50x.h + + + + + + + + + + + 0 + + + + Fujitsu\MB9BF50x\ + Fujitsu\MB9BF50x\ + + 0 + 0 + 0 + 0 + 1 + + .\obj\ + rtthread-fm3 + 1 + 0 + 0 + 1 + 1 + .\obj\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM3 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + 0 + 7 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + Segger\JL2CM3.dll + "" () + + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x40000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x4000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + CMSIS;.;..\..\include;..\..\components\rtgui\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x10000000 + + + + + + + + + + + + Startup + + + application.c + 1 + .\application.c + + + board.c + 1 + .\board.c + + + startup.c + 1 + .\startup.c + + + adc.c + 1 + .\adc.c + + + cpuusage.c + 1 + .\cpuusage.c + + + key.c + 1 + .\key.c + + + lcd.c + 1 + .\lcd.c + + + led.c + 1 + .\led.c + + + info.c + 1 + .\info.c + + + + + FM3 + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m3\context_rvds.S + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m3\cpuport.c + + + + + CMSIS + + + core_cm3.c + 1 + .\CMSIS\core_cm3.c + + + start_rvds.S + 2 + .\CMSIS\start_rvds.S + + + system_mb9bf50x.c + 1 + .\CMSIS\system_mb9bf50x.c + + + + + Kernel + + + clock.c + 1 + ..\..\src\clock.c + + + device.c + 1 + ..\..\src\device.c + + + idle.c + 1 + ..\..\src\idle.c + + + ipc.c + 1 + ..\..\src\ipc.c + + + irq.c + 1 + ..\..\src\irq.c + + + kservice.c + 1 + ..\..\src\kservice.c + + + mem.c + 1 + ..\..\src\mem.c + + + mempool.c + 1 + ..\..\src\mempool.c + + + module.c + 1 + ..\..\src\module.c + + + object.c + 1 + ..\..\src\object.c + + + rtm.c + 1 + ..\..\src\rtm.c + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + slab.c + 1 + ..\..\src\slab.c + + + thread.c + 1 + ..\..\src\thread.c + + + timer.c + 1 + ..\..\src\timer.c + + + + + + + + diff --git a/bsp/mb9bf500r/rtconfig.h b/bsp/mb9bf500r/rtconfig.h new file mode 100644 index 0000000000..3e32c40962 --- /dev/null +++ b/bsp/mb9bf500r/rtconfig.h @@ -0,0 +1,88 @@ +/* RT-Thread config file */ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +/* RT_NAME_MAX*/ +#define RT_NAME_MAX 8 + +/* RT_ALIGN_SIZE*/ +#define RT_ALIGN_SIZE 4 + +/* PRIORITY_MAX */ +#define RT_THREAD_PRIORITY_MAX 32 + +/* Tick per Second */ +#define RT_TICK_PER_SECOND 100 + +/* SECTION: RT_DEBUG */ +/* Thread Debug */ +/* #define RT_DEBUG */ +#define RT_USING_OVERFLOW_CHECK + +/* Using Hook */ +#define RT_USING_HOOK + +/* SECTION: IPC */ +/* Using Semaphore */ +#define RT_USING_SEMAPHORE + +/* Using Mutex */ +#define RT_USING_MUTEX + +/* Using Event */ +#define RT_USING_EVENT + +/* Using MailBox */ +#define RT_USING_MAILBOX + +/* Using Message Queue */ +#define RT_USING_MESSAGEQUEUE + +/* SECTION: Memory Management */ +/* Using Memory Pool Management*/ +#define RT_USING_MEMPOOL + +/* Using Dynamic Heap Management */ +#define RT_USING_HEAP + +/* Using Small MM */ +#define RT_USING_SMALL_MEM + +/* SECTION: Device System */ +/* Using Device System */ +#define RT_USING_DEVICE +/* RT_USING_UART */ +#define RT_USING_UART0 +#define RT_UART_RX_BUFFER_SIZE 64 + +/* SECTION: Console options */ +#define RT_TINY_SIZE +#define RT_USING_CONSOLE +/* the buffer size of console */ +#define RT_CONSOLEBUF_SIZE 128 + +/* SECTION: RTGUI support */ +/* using RTGUI support */ +/* #define RT_USING_RTGUI */ + +/* name length of RTGUI object */ +#define RTGUI_NAME_MAX 16 +/* support 16 weight font */ +//#define RTGUI_USING_FONT16 +/* support 12 weight font */ +#define RTGUI_USING_FONT12 +/* support Chinese font */ +//#define RTGUI_USING_FONTHZ +/* use DFS as file interface */ +//#define RTGUI_USING_DFS_FILERW +/* use font file as Chinese font */ +/* #define RTGUI_USING_HZ_FILE */ +/* use Chinese bitmap font */ +//#define RTGUI_USING_HZ_BMP +/* use small size in RTGUI */ +//#define RTGUI_USING_SMALL_SIZE +/* use mouse cursor */ +/* #define RTGUI_USING_MOUSE_CURSOR */ +#define RTGUI_DEFAULT_FONT_SIZE 12 + +#endif diff --git a/bsp/mb9bf500r/rtconfig.py b/bsp/mb9bf500r/rtconfig.py new file mode 100644 index 0000000000..5b3885ebad --- /dev/null +++ b/bsp/mb9bf500r/rtconfig.py @@ -0,0 +1,114 @@ +# toolchains options +ARCH='arm' +CPU='cortex-m3' +CROSS_TOOL='gcc' + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'axf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-fm3.map,-cref,-u,Reset_Handler -T fm3_rom.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --device DARMSTM' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-fm3.map --scatter fm3_rom.sct' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + CFLAGS = '' + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M3' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M3' + AFLAGS += ' --fpu None' + AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"' + + LFLAGS = ' --config mb9bf500r.icf' + LFLAGS += ' --semihosting' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = IAR_PATH + '/arm/bin/' + POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' diff --git a/bsp/mb9bf500r/startup.c b/bsp/mb9bf500r/startup.c new file mode 100644 index 0000000000..f74c60bc5c --- /dev/null +++ b/bsp/mb9bf500r/startup.c @@ -0,0 +1,107 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-24 Bernard first implementation + */ + +#include +#include + +#include "board.h" +#include "mb9bf506r.h" +/** + * @addtogroup FM3 + */ + +/*@{*/ + +extern int rt_application_init(void); + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ +#pragma section="HEAP" +#else +extern int __bss_end; +#endif + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + + /* init tick */ + rt_system_tick_init(); + + /* init kernel object */ + rt_system_object_init(); + + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP + #ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); + #elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); + #else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); + #endif +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + +#ifdef RT_USING_DEVICE + /* init all device */ + rt_device_init_all(); +#endif + + /* init application */ + rt_application_init(); + + /* init timer thread */ + rt_system_timer_thread_init(); + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + rt_uint32_t UNUSED level; + + /* disable interrupt first */ + level = rt_hw_interrupt_disable(); + + /* init system setting */ + SystemInit(); + + /* startup RT-Thread RTOS */ + rtthread_startup(); + + return 0; +} + +/*@}*/ diff --git a/bsp/mb9bf506r/CMSIS/SConscript b/bsp/mb9bf506r/CMSIS/SConscript new file mode 100644 index 0000000000..e058a7aad1 --- /dev/null +++ b/bsp/mb9bf506r/CMSIS/SConscript @@ -0,0 +1,19 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +src = Glob('*.c') + +# add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['start_gcc.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['start_rvds.S'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['start_iar.S'] + +CPPPATH = [GetCurrentDir()] + +group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH, LIBRARY = '') + +Return('group') diff --git a/bsp/mb9bf506r/CMSIS/core_cm3.c b/bsp/mb9bf506r/CMSIS/core_cm3.c new file mode 100644 index 0000000000..f1bfb2b8e0 --- /dev/null +++ b/bsp/mb9bf506r/CMSIS/core_cm3.c @@ -0,0 +1,359 @@ +/**************************************************************************//** + * @file core_cm3.c + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File + * @version V1.40 + * @date 18. February 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/* ########################## Core Instruction Access ######################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ + +/** + * @brief Reverse byte order (16 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +#if (__ARMCC_VERSION < 400677) +__ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +#if (__ARMCC_VERSION < 400677) +__ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + /** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __CLREX(void) +{ + clrex +} +#endif /* __ARMCC_VERSION */ + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* obsolete */ +#endif + + +/* ########################### Core Function Access ########################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_CONTROL(void) +{ + mrs r0, control + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_CONTROL(uint32_t control) +{ + msr control, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get IPSR Register value + * + * @return uint32_t IPSR value + * + * return the content of the IPSR register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_IPSR(void) +{ + mrs r0, ipsr + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get APSR Register value + * + * @return uint32_t APSR value + * + * return the content of the APSR register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_APSR(void) +{ + mrs r0, apsr + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get xPSR Register value + * + * @return uint32_t xPSR value + * + * return the content of the xPSR register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_xPSR(void) +{ + mrs r0, xpsr + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_PSP(void) +{ + mrs r0, psp + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_PSP(uint32_t topOfProcStack) +{ + msr psp, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_MSP(void) +{ + mrs r0, msp + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_MSP(uint32_t mainStackPointer) +{ + msr msp, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_BASEPRI(void) +{ + mrs r0, basepri + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_BASEPRI(uint32_t basePri) +{ + msr basepri, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_PRIMASK(void) +{ + mrs r0, primask + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_PRIMASK(uint32_t priMask) +{ + msr primask, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +#if (__ARMCC_VERSION < 400000) +__ASM uint32_t __get_FAULTMASK(void) +{ + mrs r0, faultmask + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +#if (__ARMCC_VERSION < 400000) +__ASM void __set_FAULTMASK(uint32_t faultMask) +{ + msr faultmask, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the FPSCR value + * + * @return FloatingPointStatusControlRegister + * + * Return the content of the FPSCR register + */ + +/** + * @brief Set the FPSCR value + * + * @param fpscr FloatingPointStatusControlRegister + * + * Set the FPSCR register + */ + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* obsolete */ +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* obsolete */ +#endif diff --git a/bsp/mb9bf506r/CMSIS/core_cm3.h b/bsp/mb9bf506r/CMSIS/core_cm3.h new file mode 100644 index 0000000000..43be05e58b --- /dev/null +++ b/bsp/mb9bf506r/CMSIS/core_cm3.h @@ -0,0 +1,1166 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V1.40 + * @date 16. February 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CM3_H__ +#define __CORE_CM3_H__ + +/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration + * + * List of Lint messages which will be suppressed and not shown: + * - not yet checked + * . + * Note: To re-enable a Message, insert a space before 'lint' * + * + */ + + +/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core registers and bitfields + - Cortex-M core peripheral base address + @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x40) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex core */ + +#ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */ +#endif + + +#include /* Include standard types */ + + + +/** + * IO definitions + * + * define access restrictions to peripheral registers + */ + +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register + @{ +*/ + +/** @addtogroup CMSIS_ARM_CORE CMSIS ARM Core + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; +#else + uint32_t _reserved0:16; + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; + uint32_t w; +} APSR_Type; + +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 00..08 Exception number */ + uint32_t _reserved0:23; + } b; + uint32_t w; +} IPSR_Type; + +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 00..08 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; +#else + uint32_t _reserved0:7; + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; + uint32_t w; +} xPSR_Type; + +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 00 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 01 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 02 FP extension active flag */ + uint32_t _reserved0:29; + } b; + uint32_t w; +} CONTROL_Type; + +/*@}*/ /* end of group CMSIS_ARM_CORE */ + + +/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC + memory mapped structure for Nested Vectored Interrupt Controller (NVIC) + @{ + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */ +} NVIC_Type; +/*@}*/ /* end of group CMSIS_CM3_NVIC */ + + +/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB + memory mapped structure for System Control Block (SCB) + @{ + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +/*@}*/ /* end of group CMSIS_CM3_SCB */ + + +/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick + memory mapped structure for SysTick + @{ + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ +/*@}*/ /* end of group CMSIS_CM3_SysTick */ + + +/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM + memory mapped structure for Instrumentation Trace Macrocell (ITM) + @{ + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */ + __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */ + __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +/*@}*/ /* end of group CMSIS_CM3_ITM */ + + +/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type + memory mapped structure for Interrupt Type + @{ + */ +typedef struct +{ + uint32_t RESERVED0; + __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */ +} InterruptType_Type; + +/* Interrupt Controller Type Register Definitions */ +#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */ +#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */ +#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */ + +#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */ +#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */ + +#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */ +#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */ +/*@}*/ /* end of group CMSIS_CM3_InterruptType */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) +/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU + memory mapped structure for Memory Protection Unit (MPU) + @{ + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */ +#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */ +#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */ +#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */ +#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */ +#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */ +#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@}*/ /* end of group CMSIS_CM3_MPU */ +#endif + + +/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug + memory mapped structure for Core Debug Register + @{ + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +/*@}*/ /* end of group CMSIS_CM3_CoreDebug */ + + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000) /*!< ITM Base Address */ +#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */ + +#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */ +#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_register */ + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/* ########################## Core Instruction Access ######################### */ +#include "core_cmInstr.h" + +/* ########################### Core Function Access ########################### */ +#include "core_cmFunc.h" + + +/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface + Core Function Interface containing: + - Core NVIC Functions + - Core SysTick Functions + - Core Reset Functions +*/ +/*@{*/ + +/* ########################## NVIC functions #################################### */ + +/** + * @brief Set the Priority Grouping in NVIC Interrupt Controller + * + * @param PriorityGroup is priority grouping field + * + * Set the priority grouping field using the required unlock sequence. + * The parameter priority_grouping is assigned to the field + * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + */ +static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + (0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** + * @brief Get the Priority Grouping from NVIC Interrupt Controller + * + * @return priority grouping field + * + * Get the priority grouping from NVIC Interrupt Controller. + * priority grouping is SCB->AIRCR [10:8] PRIGROUP field. + */ +static __INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** + * @brief Enable Interrupt in NVIC Interrupt Controller + * + * @param IRQn The positive number of the external interrupt to enable + * + * Enable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + +/** + * @brief Disable the interrupt line for external interrupt specified + * + * @param IRQn The positive number of the external interrupt to disable + * + * Disable a device specific interupt in the NVIC interrupt controller. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + +/** + * @brief Read the interrupt pending bit for a device specific interrupt source + * + * @param IRQn The number of the device specifc interrupt + * @return 1 = interrupt pending, 0 = interrupt not pending + * + * Read the pending register in NVIC and return 1 if its status is pending, + * otherwise it returns 0 + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + +/** + * @brief Set the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for set pending + * + * Set the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + +/** + * @brief Clear the pending bit for an external interrupt + * + * @param IRQn The number of the interrupt for clear pending + * + * Clear the pending bit for the specified interrupt. + * The interrupt number cannot be a negative value. + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + +/** + * @brief Read the active bit for an external interrupt + * + * @param IRQn The number of the interrupt for read active bit + * @return 1 = interrupt active, 0 = interrupt not active + * + * Read the active register in NVIC and returns 1 if its status is active, + * otherwise it returns 0. + */ +static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + +/** + * @brief Set the priority for an interrupt + * + * @param IRQn The number of the interrupt for set priority + * @param priority The priority to set + * + * Set the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + +/** + * @brief Read the priority for an interrupt + * + * @param IRQn The number of the interrupt for get priority + * @return The priority for the interrupt + * + * Read the priority for the specified interrupt. The interrupt + * number can be positive to specify an external (device specific) + * interrupt, or negative to specify an internal (core) interrupt. + * + * The returned priority value is automatically aligned to the implemented + * priority bits of the microcontroller. + * + * Note: The priority cannot be set for every core interrupt. + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** + * @brief Encode the priority for an interrupt + * + * @param PriorityGroup The used priority group + * @param PreemptPriority The preemptive priority value (starting from 0) + * @param SubPriority The sub priority value (starting from 0) + * @return The encoded priority for the interrupt + * + * Encode the priority for an interrupt with the given priority group, + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The returned priority value can be used for NVIC_SetPriority(...) function + */ +static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** + * @brief Decode the priority of an interrupt + * + * @param Priority The priority for the interrupt + * @param PriorityGroup The used priority group + * @param pPreemptPriority The preemptive priority value (starting from 0) + * @param pSubPriority The sub priority value (starting from 0) + * + * Decode an interrupt priority value with the given priority group to + * preemptive priority value and sub priority value. + * In case of a conflict between priority grouping and available + * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + * + * The priority value can be retrieved with NVIC_GetPriority(...) function + */ +static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + + +/* ################################## SysTick function ############################################ */ + +#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0) + +/** + * @brief Initialize and start the SysTick counter and its interrupt. + * + * @param ticks number of ticks between two interrupts + * @return 1 = failed, 0 = successful + * + * Initialise the system tick timer and its interrupt and start the + * system tick timer / counter in free running mode to generate + * periodical interrupts. + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + + + + +/* ################################## Reset function ############################################ */ + +/** + * @brief Initiate a system reset request. + * + * Initiate a system reset request to reset the MCU + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */ + + + +/* ##################################### Debug In/Output function ########################################### */ + +/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface + Core Debug Interface containing: + - Core Debug Receive / Transmit Functions + - Core Debug Defines + - Core Debug Variables +*/ +/*@{*/ + +extern volatile int ITM_RxBuffer; /*!< variable to receive characters */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */ + + +/** + * @brief Outputs a character via the ITM channel 0 + * + * @param ch character to output + * @return character to output + * + * The function outputs a character via the ITM channel 0. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */ + (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** + * @brief Inputs a character via variable ITM_RxBuffer + * + * @return received character, -1 = no character received + * + * The function inputs a character via variable ITM_RxBuffer. + * The function returns when no debugger is connected that has booked the output. + * It is blocking when a debugger is connected, but the previous character send is not transmitted. + */ +static __INLINE int ITM_ReceiveChar (void) { + int ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + * @brief Check if a character via variable ITM_RxBuffer is available + * + * @return 1 = character available, 0 = no character available + * + * The function checks variable ITM_RxBuffer whether a character is available or not. + * The function returns '1' if a character is available and '0' if no character is available. + */ +static __INLINE int ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ /* end of group CMSIS_CM3_core_definitions */ + +#endif /* __CORE_CM3_H__ */ + +/*lint -restore */ diff --git a/bsp/mb9bf506r/CMSIS/core_cmFunc.h b/bsp/mb9bf506r/CMSIS/core_cmFunc.h new file mode 100644 index 0000000000..03c29d35dc --- /dev/null +++ b/bsp/mb9bf506r/CMSIS/core_cmFunc.h @@ -0,0 +1,912 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V1.40 + * @date 16. February 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H__ +#define __CORE_CMFUNC_H__ + +/* ########################### Core Function Access ########################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ +/* ARM armcc specific functions */ + + /** + * @brief Enable IRQ Interrupts + * + * Enables IRQ interrupts by clearing the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + /** + * @brief Disable IRQ Interrupts + * + * Disables IRQ interrupts by setting the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_CONTROL(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_CONTROL(uint32_t control); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get IPSR Register value + * + * @return uint32_t IPSR value + * + * return the content of the IPSR register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_IPSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get APSR Register value + * + * @return uint32_t APSR value + * + * return the content of the APSR register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_APSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Get xPSR Register value + * + * @return uint32_t xPSR value + * + * return the content of the xPSR register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_xPSR(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_PSP(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_PSP(uint32_t topOfProcStack); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_MSP(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_MSP(uint32_t topOfMainStack); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_MSP(uint32_t mainStackPointer) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = mainStackPointer; +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_PRIMASK(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_PRIMASK(uint32_t priMask); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} +#endif /* __ARMCC_VERSION */ + + +#if (__CORTEX_M >= 0x03) + + /** + * @brief Enable FIQ Interrupts + * + * Enables FIQ interrupts by clearing the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + /** + * @brief Disable FIQ Interrupts + * + * Disables FIQ interrupts by setting the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_BASEPRI(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_BASEPRI(uint32_t basePri); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +#if (__ARMCC_VERSION < 400000) +extern uint32_t __get_FAULTMASK(void); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +#if (__ARMCC_VERSION < 400000) +extern void __set_FAULTMASK(uint32_t faultMask); +#else /* (__ARMCC_VERSION >= 400000) */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & 1); +} +#endif /* __ARMCC_VERSION */ + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** + * @brief Return the FPSCR value + * + * @return FloatingPointStatusControlRegister + * + * Return the content of the FPSCR register + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + +/** + * @brief Set the FPSCR value + * + * @param fpscr FloatingPointStatusControlRegister + * + * Set the FPSCR register + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + + #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* IAR iccarm specific functions */ +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + +#pragma diag_suppress=Pe940 + + /** + * @brief Enable IRQ Interrupts + * + * Enables IRQ interrupts by clearing the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +#define __enable_irq __enable_interrupt + + /** + * @brief Disable IRQ Interrupts + * + * Disables IRQ interrupts by setting the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +#define __disable_irq __disable_interrupt + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */ + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */ + +/** + * @brief Get IPSR Register value + * + * @return uint32_t IPSR value + * + * return the content of the IPSR register + */ +static uint32_t __get_IPSR(void) +{ + __ASM("mrs r0, ipsr"); +} + +/** + * @brief Get APSR Register value + * + * @return uint32_t APSR value + * + * return the content of the APSR register + */ +/* __intrinsic unsigned long __get_APSR( void ); (see intrinsic.h) */ + +/** + * @brief Get xPSR Register value + * + * @return uint32_t xPSR value + * + * return the content of the xPSR register + */ +static uint32_t __get_xPSR(void) +{ + __ASM("mrs r0, psr"); // assembler does not know "xpsr" +} + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ + static uint32_t __get_PSP(void) +{ + __ASM("mrs r0, psp"); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +static void __set_PSP(uint32_t topOfProcStack) +{ + __ASM("msr psp, r0"); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +static uint32_t __get_MSP(void) +{ + __ASM("mrs r0, msp"); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +static void __set_MSP(uint32_t topOfMainStack) +{ + __ASM("msr msp, r0"); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */ + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */ + + +#if (__CORTEX_M >= 0x03) + + /** + * @brief Enable FIQ Interrupts + * + * Enables FIQ interrupts by clearing the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); } + + /** + * @brief Disable FIQ Interrupts + * + * Disables FIQ interrupts by setting the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); } + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */ + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */ + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */ + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */ + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** + * @brief Return the FPSCR value + * + * @return FloatingPointStatusControlRegister + * + * Return the content of the FPSCR register + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + /* not yet implemented */ + return(0); +#else + return(0); +#endif +} + +/** + * @brief Set the FPSCR value + * + * @param fpscr FloatingPointStatusControlRegister + * + * Set the FPSCR register + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + /* not yet implemented */ +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + /** + * @brief Enable IRQ Interrupts + * + * Enables IRQ interrupts by clearing the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); } + + /** + * @brief Disable IRQ Interrupts + * + * Disables IRQ interrupts by setting the I-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); } + +/** + * @brief Return the Control Register value +* +* @return Control value + * + * Return the content of the control register + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Control Register value + * + * @param control Control value + * + * Set the control register + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + +/** + * @brief Get IPSR Register value + * + * @return uint32_t IPSR value + * + * return the content of the IPSR register + */ +static __INLINE uint32_t __get_IPSR(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + +/** + * @brief Get APSR Register value + * + * @return uint32_t APSR value + * + * return the content of the APSR register + */ +static __INLINE uint32_t __get_APSR(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + +/** + * @brief Get xPSR Register value + * + * @return uint32_t xPSR value + * + * return the content of the xPSR register + */ +static __INLINE uint32_t __get_xPSR(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + +/** + * @brief Return the Process Stack Pointer + * + * @return ProcessStackPointer + * + * Return the actual process stack pointer + */ +static __INLINE uint32_t __get_PSP(void) __attribute__( ( naked ) ); +static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t result __ASM ("r0") = 0; + + __ASM volatile ("MRS %0, psp\n" + "BX lr \n" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Process Stack Pointer + * + * @param topOfProcStack Process Stack Pointer + * + * Assign the value ProcessStackPointer to the MSP + * (process stack pointer) Cortex processor register + */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) ); +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" + "BX lr \n" : : "r" (topOfProcStack) ); +} + +/** + * @brief Return the Main Stack Pointer + * + * @return Main Stack Pointer + * + * Return the current value of the MSP (main stack pointer) + * Cortex processor register + */ +static __INLINE uint32_t __get_MSP(void) __attribute__( ( naked ) ); +static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t result __ASM ("r0") = 0; + + __ASM volatile ("MRS %0, msp\n" + "BX lr \n" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Main Stack Pointer + * + * @param topOfMainStack Main Stack Pointer + * + * Assign the value mainStackPointer to the MSP + * (main stack pointer) Cortex processor register + */ +static __INLINE void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) ); +static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" + "BX lr \n" : : "r" (topOfMainStack) ); +} + +/** + * @brief Return the Priority Mask value + * + * @return PriMask + * + * Return state of the priority mask bit from the priority mask register + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Priority Mask value + * + * @param priMask PriMask + * + * Set the priority mask bit in the priority mask register + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + + /** + * @brief Enable FIQ Interrupts + * + * Enables FIQ interrupts by clearing the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); } + + /** + * @brief Disable FIQ Interrupts + * + * Disables FIQ interrupts by setting the F-bit in the CPSR. + * Can only be executed in Privileged modes. + */ +static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); } + +/** + * @brief Return the Base Priority value + * + * @return BasePriority + * + * Return the content of the base priority register + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + +/** + * @brief Set the Base Priority value + * + * @param basePri BasePriority + * + * Set the base priority register + */ +static __INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + +/** + * @brief Return the Fault Mask value + * + * @return FaultMask + * + * Return the content of the fault mask register + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result=0; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + +/** + * @brief Set the Fault Mask value + * + * @param faultMask faultMask value + * + * Set the fault mask register + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + + +#if (__CORTEX_M == 0x04) + +/** + * @brief Return the FPSCR value + * + * @return FloatingPointStatusControlRegister + * + * Return the content of the FPSCR register + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) + uint32_t result=0; + + __ASM volatile ("MRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + +/** + * @brief Set the FPSCR value + * + * @param fpscr FloatingPointStatusControlRegister + * + * Set the FPSCR register + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) + __ASM volatile ("MSR control, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +#endif // __CORE_CMFUNC_H__ diff --git a/bsp/mb9bf506r/CMSIS/core_cmInstr.h b/bsp/mb9bf506r/CMSIS/core_cmInstr.h new file mode 100644 index 0000000000..514cfb2385 --- /dev/null +++ b/bsp/mb9bf506r/CMSIS/core_cmInstr.h @@ -0,0 +1,684 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V1.40 + * @date 16. February 2010 + * + * @note + * Copyright (C) 2009-2010 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H__ +#define __CORE_CMINSTR_H__ + +/* ########################## Core Instruction Access ######################### */ + +#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/ +/* ARM armcc specific functions */ + + /** + * @brief No Operation + * + * No Operation does nothing. This instruction can be used for code alignment + * purposes. + */ +#define __NOP __nop + + /** + * @brief Wait For Interrupt + * + * Wait For Interrupt is a hint instruction that suspends execution until + * one of a number of events occurs. + */ +#define __WFI __wfi + + /** + * @brief Wait For Event + * + * Wait For Event is a hint instruction that permits the processor to enter + * a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + /** + * @brief Send Event + * + * Send Event is a hint instruction. It causes an event to be signaled + * to the CPU. + */ +#define __SEV __sev + + /** + * @brief Instruction Synchronization Barrier + * + * Instruction Synchronization Barrier flushes the pipeline in the processor, + * so that all instructions following the ISB are fetched from cache or + * memory, after the instruction has been completed + */ +#define __ISB() __isb(0xF) + + /** + * @brief Data Synchronization Barrier + * + * The DSB instruction operation acts as a special kind of Data Memory Barrier. + * The DSB operation completes when all explicit memory accesses before this + * instruction complete. + */ +#define __DSB() __dsb(0xF) + + /** + * @brief Data Memory Barrier + * + * DMB ensures the apparent order of the explicit memory operations before + * and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + +/** + * @brief Reverse byte order (32 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +#define __REV __rev + +/** + * @brief Reverse byte order (16 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +#if (__ARMCC_VERSION < 400677) +extern uint32_t __REV16(uint16_t value); +#else /* (__ARMCC_VERSION >= 400677) */ +static __INLINE __ASM uint32_t __REV16(uint16_t value) +{ + rev16 r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +#if (__ARMCC_VERSION < 400677) +extern int32_t __REVSH(int16_t value); +#else /* (__ARMCC_VERSION >= 400677) */ +static __INLINE __ASM int32_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif /* __ARMCC_VERSION */ + + +#if (__CORTEX_M >= 0x03) + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +#define __RBIT __rbit + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr)) + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr)) + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr)) + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +#define __STREXB(value, ptr) __strex(value, ptr) + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +#define __STREXH(value, ptr) __strex(value, ptr) + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + /** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +#if (__ARMCC_VERSION < 400000) +extern void __CLREX(void); +#else /* (__ARMCC_VERSION >= 400000) */ +#define __CLREX __clrex +#endif /* __ARMCC_VERSION */ + +#endif /* (__CORTEX_M >= 0x03) */ + + +#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/ +/* IAR iccarm specific functions */ +#if defined (__ICCARM__) + #include /* IAR Intrinsics */ +#endif + +#pragma diag_suppress=Pe940 + + /** + * @brief No Operation + * + * No Operation does nothing. This instruction can be used for code alignment + * purposes. + */ +#define __NOP __no_operation + + /** + * @brief Wait For Interrupt + * + * Wait For Interrupt is a hint instruction that suspends execution until + * one of a number of events occurs. + */ +static __INLINE void __WFI() { __ASM ("wfi"); } + + /** + * @brief Wait For Event + * + * Wait For Event is a hint instruction that permits the processor to enter + * a low-power state until one of a number of events occurs. + */ +static __INLINE void __WFE() { __ASM ("wfe"); } + + /** + * @brief Send Event + * + * Send Event is a hint instruction. It causes an event to be signaled + * to the CPU. + */ +static __INLINE void __SEV() { __ASM ("sev"); } + + /** + * @brief Instruction Synchronization Barrier + * + * Instruction Synchronization Barrier flushes the pipeline in the processor, + * so that all instructions following the ISB are fetched from cache or + * memory, after the instruction has been completed + */ +/* intrinsic void __ISB(void) (see intrinsics.h */ + + /** + * @brief Data Synchronization Barrier + * + * The DSB instruction operation acts as a special kind of Data Memory Barrier. + * The DSB operation completes when all explicit memory accesses before this + * instruction complete. + */ +/* intrinsic void __DSB(void) (see intrinsics.h */ + + /** + * @brief Data Memory Barrier + * + * DMB ensures the apparent order of the explicit memory operations before + * and after the instruction, without ensuring their completion. + */ +/* intrinsic void __DMB(void) (see intrinsics.h */ + +/** + * @brief Reverse byte order (32 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h */ + +/** + * @brief Reverse byte order (16 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +static uint32_t __REV16(uint16_t value) +{ + __ASM("rev16 r0, r0"); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */ + + +#if (__CORTEX_M >= 0x03) + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +static uint32_t __RBIT(uint32_t value) +{ + __ASM("rbit r0, r0"); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +static uint8_t __LDREXB(uint8_t *addr) +{ + __ASM("ldrexb r0, [r0]"); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +static uint16_t __LDREXH(uint16_t *addr) +{ + __ASM("ldrexh r0, [r0]"); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h */ +static uint32_t __LDREXW(uint32_t *addr) +{ + __ASM("ldrex r0, [r0]"); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +static uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + __ASM("strexb r0, r0, [r1]"); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +static uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + __ASM("strexh r0, r0, [r1]"); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h */ +static uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + __ASM("strex r0, r0, [r1]"); +} + + /** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +static __INLINE void __CLREX() { __ASM ("clrex"); } + +#endif /* (__CORTEX_M >= 0x03) */ + +#pragma diag_default=Pe940 + + +#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + + /** + * @brief No Operation + * + * No Operation does nothing. This instruction can be used for code alignment + * purposes. + */ +static __INLINE void __NOP() { __ASM volatile ("nop"); } + + /** + * @brief Wait For Interrupt + * + * Wait For Interrupt is a hint instruction that suspends execution until + * one of a number of events occurs. + */ +static __INLINE void __WFI() { __ASM volatile ("wfi"); } + + /** + * @brief Wait For Event + * + * Wait For Event is a hint instruction that permits the processor to enter + * a low-power state until one of a number of events occurs. + */ +static __INLINE void __WFE() { __ASM volatile ("wfe"); } + + /** + * @brief Send Event + * + * Send Event is a hint instruction. It causes an event to be signaled + * to the CPU. + */ +static __INLINE void __SEV() { __ASM volatile ("sev"); } + + /** + * @brief Instruction Synchronization Barrier + * + * Instruction Synchronization Barrier flushes the pipeline in the processor, + * so that all instructions following the ISB are fetched from cache or + * memory, after the instruction has been completed + */ +static __INLINE void __ISB() { __ASM volatile ("isb"); } + + /** + * @brief Data Synchronization Barrier + * + * The DSB instruction operation acts as a special kind of Data Memory Barrier. + * The DSB operation completes when all explicit memory accesses before this + * instruction complete. + */ +static __INLINE void __DSB() { __ASM volatile ("dsb"); } + + /** + * @brief Data Memory Barrier + * + * DMB ensures the apparent order of the explicit memory operations before + * and after the instruction, without ensuring their completion. + */ +static __INLINE void __DMB() { __ASM volatile ("dmb"); } + +/** + * @brief Reverse byte order (32 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in integer value + */ +static __INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order (16 bit) + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in unsigned short value + */ +static __INLINE uint32_t __REV16(uint16_t value) +{ + uint32_t result=0; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief Reverse byte order in signed short value with sign extension to integer + * + * @param value value to reverse + * @return reversed value + * + * Reverse byte order in signed short value with sign extension to integer + */ +static __INLINE int32_t __REVSH(int16_t value) +{ + uint32_t result=0; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +#if (__CORTEX_M >= 0x03) + +/** + * @brief Reverse bit order of value + * + * @param value value to reverse + * @return reversed value + * + * Reverse bit order of value + */ +static __INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result=0; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +/** + * @brief LDR Exclusive (8 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 8 bit value + */ +static __INLINE uint8_t __LDREXB(uint8_t *addr) +{ + uint8_t result=0; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (16 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 16 bit values + */ +static __INLINE uint16_t __LDREXH(uint16_t *addr) +{ + uint16_t result=0; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief LDR Exclusive (32 bit) + * + * @param *addr address pointer + * @return value of (*address) + * + * Exclusive LDR command for 32 bit values + */ +static __INLINE uint32_t __LDREXW(uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + +/** + * @brief STR Exclusive (8 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 8 bit values + */ +static __INLINE uint32_t __STREXB(uint8_t value, uint8_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (16 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 16 bit values + */ +static __INLINE uint32_t __STREXH(uint16_t value, uint16_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + +/** + * @brief STR Exclusive (32 bit) + * + * @param value value to store + * @param *addr address pointer + * @return successful / failed + * + * Exclusive STR command for 32 bit values + */ +static __INLINE uint32_t __STREXW(uint32_t value, uint32_t *addr) +{ + uint32_t result=0; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + /** + * @brief Remove the exclusive lock created by ldrex + * + * Removes the exclusive lock which is created by ldrex. + */ +static __INLINE void __CLREX() { __ASM volatile ("clrex"); } + +#endif /* (__CORTEX_M >= 0x03) */ + + +#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +#endif // __CORE_CMINSTR_H__ diff --git a/bsp/mb9bf506r/CMSIS/mb9bf506r.h b/bsp/mb9bf506r/CMSIS/mb9bf506r.h new file mode 100644 index 0000000000..3f0a9481c3 --- /dev/null +++ b/bsp/mb9bf506r/CMSIS/mb9bf506r.h @@ -0,0 +1,9739 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user's obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intentional misconduct and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.5) */ +/************************************************************************/ +/* */ +/* Header File for Device MB9BF506R */ +/* Version V1.00 */ +/* Date 2011-01-21 */ +/* */ +/************************************************************************/ + +#ifndef _MB9BF506R_H_ +#define _MB9BF506R_H_ + +#ifdef __cplusplus +extern "C" { +#endif + + +/****************************************************************************** + * Configuration of the Cortex-M3 Processor and Core Peripherals + ******************************************************************************/ +#define __MPU_PRESENT 1 /* FM3 provide an MPU */ +#define __NVIC_PRIO_BITS 4 /* FM3 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + + +/****************************************************************************** + * Interrupt Number Definition + ******************************************************************************/ +typedef enum IRQn +{ + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + MemManage_IRQn = -12, /* 4 Memory Management */ + BusFault_IRQn = -11, /* 5 Bus Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault */ + SVC_IRQn = -5, /* 11 SV Call */ + DebugMonitor_IRQn = -4, /* 12 Debug Monitor */ + PendSVC_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + + CSV_IRQn = 0, /* Clock Super Visor */ + SWDT_IRQn = 1, /* Software Watchdog Timer */ + LVD_IRQn = 2, /* Low Voltage Detector */ + WFG_IRQn = 3, /* Wave Form Generator */ + EXINT0_7_IRQn = 4, /* External Interrupt Request ch.0 to ch.7 */ + EXINT8_15_IRQn = 5, /* External Interrupt Request ch.8 to ch.15 */ + DTIM_QDU_IRQn = 6, /* Dual Timer / Quad Decoder */ + MFS0RX_IRQn = 7, /* MultiFunction Serial ch.0 */ + MFS0TX_IRQn = 8, /* MultiFunction Serial ch.0 */ + MFS1RX_IRQn = 9, /* MultiFunction Serial ch.1 */ + MFS1TX_IRQn = 10, /* MultiFunction Serial ch.1 */ + MFS2RX_IRQn = 11, /* MultiFunction Serial ch.2 */ + MFS2TX_IRQn = 12, /* MultiFunction Serial ch.2 */ + MFS3RX_IRQn = 13, /* MultiFunction Serial ch.3 */ + MFS3TX_IRQn = 14, /* MultiFunction Serial ch.3 */ + MFS4RX_IRQn = 15, /* MultiFunction Serial ch.4 */ + MFS4TX_IRQn = 16, /* MultiFunction Serial ch.4 */ + MFS5RX_IRQn = 17, /* MultiFunction Serial ch.5 */ + MFS5TX_IRQn = 18, /* MultiFunction Serial ch.5 */ + MFS6RX_IRQn = 19, /* MultiFunction Serial ch.6 */ + MFS6TX_IRQn = 20, /* MultiFunction Serial ch.6 */ + MFS7RX_IRQn = 21, /* MultiFunction Serial ch.7 */ + MFS7TX_IRQn = 22, /* MultiFunction Serial ch.7 */ + PPG_IRQn = 23, /* PPG */ + OSC_PLL_WC_IRQn = 24, /* OSC / PLL / Watch Counter */ + ADC0_IRQn = 25, /* ADC0 */ + ADC1_IRQn = 26, /* ADC1 */ + ADC2_IRQn = 27, /* ADC2 */ + FRTIM_IRQn = 28, /* Free-run Timer */ + INCAP_IRQn = 29, /* Input Capture */ + OUTCOMP_IRQn = 30, /* Output Compare */ + BTIM_IRQn = 31, /* Base Timer ch.0 to ch.7 */ + CAN0_IRQn = 32, /* CAN ch.0 */ + CAN1_IRQn = 33, /* CAN ch.1 */ + USBF_IRQn = 34, /* USB Function */ + USBF_USBH_IRQn = 35, /* USB Function / USB HOST */ + /* Reserved = 36, */ + /* Reserved = 37, */ + DMAC0_IRQn = 38, /* DMAC ch.0 */ + DMAC1_IRQn = 39, /* DMAC ch.1 */ + DMAC2_IRQn = 40, /* DMAC ch.2 */ + DMAC3_IRQn = 41, /* DMAC ch.3 */ + DMAC4_IRQn = 42, /* DMAC ch.4 */ + DMAC5_IRQn = 43, /* DMAC ch.5 */ + DMAC6_IRQn = 44, /* DMAC ch.6 */ + DMAC7_IRQn = 45, /* DMAC ch.7 */ + /* Reserved = 46, */ + /* Reserved = 47, */ +} IRQn_Type; + + +#include "core_cm3.h" +#include "system_mb9bf50x.h" +#include + +#define SUCCESS 0 +#define ERROR -1 + +#ifndef NULL +#define NULL 0 +#endif + + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/****************************************************************************** + * Flash_IF_MODULE + ******************************************************************************/ +/* Flash interface registers */ +typedef struct +{ + __IO uint32_t FASZR; + __IO uint32_t FRWTR; + __IO uint32_t FSTR; + uint8_t RESERVED0[4]; + __IO uint32_t FSYNDN; + uint8_t RESERVED1[236]; + __IO uint32_t CRTRMM; +}FM3_FIF_TypeDef; + +/****************************************************************************** + * Clock_Reset_MODULE + ******************************************************************************/ +/* Clock and reset registers */ +typedef struct +{ + __IO uint8_t SCM_CTL; + uint8_t RESERVED0[3]; + __IO uint8_t SCM_STR; + uint8_t RESERVED1[3]; + __IO uint32_t STB_CTL; + __IO uint16_t RST_STR; + uint8_t RESERVED2[2]; + __IO uint8_t BSC_PSR; + uint8_t RESERVED3[3]; + __IO uint8_t APBC0_PSR; + uint8_t RESERVED4[3]; + __IO uint8_t APBC1_PSR; + uint8_t RESERVED5[3]; + __IO uint8_t APBC2_PSR; + uint8_t RESERVED6[3]; + __IO uint8_t SWC_PSR; + uint8_t RESERVED7[7]; + __IO uint8_t TTC_PSR; + uint8_t RESERVED8[7]; + __IO uint8_t CSW_TMR; + uint8_t RESERVED9[3]; + __IO uint8_t PSW_TMR; + uint8_t RESERVED10[3]; + __IO uint8_t PLL_CTL1; + uint8_t RESERVED11[3]; + __IO uint8_t PLL_CTL2; + uint8_t RESERVED12[3]; + __IO uint16_t CSV_CTL; + uint8_t RESERVED13[2]; + __IO uint8_t CSV_STR; + uint8_t RESERVED14[3]; + __IO uint16_t FCSWH_CTL; + uint8_t RESERVED15[2]; + __IO uint16_t FCSWL_CTL; + uint8_t RESERVED16[2]; + __IO uint16_t FCSWD_CTL; + uint8_t RESERVED17[2]; + __IO uint8_t DBWDT_CTL; + uint8_t RESERVED18[11]; + __IO uint8_t INT_ENR; + uint8_t RESERVED19[3]; + __IO uint8_t INT_STR; + uint8_t RESERVED20[3]; + __IO uint8_t INT_CLR; +}FM3_CRG_TypeDef; + +/****************************************************************************** + * HWWDT_MODULE + ******************************************************************************/ +/* Hardware watchdog registers */ +typedef struct +{ + __IO uint32_t WDG_LDR; + __IO uint32_t WDG_VLR; + __IO uint8_t WDG_CTL; + uint8_t RESERVED0[3]; + __IO uint8_t WDG_ICL; + uint8_t RESERVED1[3]; + __IO uint8_t WDG_RIS; + uint8_t RESERVED2[3055]; + __IO uint32_t WDG_LCK; +}FM3_HWWDT_TypeDef; + +/****************************************************************************** + * SWWDT_MODULE + ******************************************************************************/ +/* Software watchdog registers */ +typedef struct +{ + __IO uint32_t WDOGLOAD; + __IO uint32_t WDOGVALUE; + __IO uint8_t WDOGCONTROL; + uint8_t RESERVED0[3]; + __IO uint32_t WDOGINTCLR; + __IO uint8_t WDOGRIS; + uint8_t RESERVED1[3055]; + __IO uint32_t WDOGLOCK; +}FM3_SWWDT_TypeDef; + +/****************************************************************************** + * DTIM_MODULE + ******************************************************************************/ +/* Dual timer 1/2 registers */ +typedef struct +{ + __IO uint32_t TIMER1LOAD; + __IO uint32_t TIMER1VALUE; + __IO uint32_t TIMER1CONTROL; + __IO uint32_t TIMER1INTCLR; + __IO uint32_t TIMER1RIS; + __IO uint32_t TIMER1MIS; + __IO uint32_t TIMER1BGLOAD; + uint8_t RESERVED0[4]; + __IO uint32_t TIMER2LOAD; + __IO uint32_t TIMER2VALUE; + __IO uint32_t TIMER2CONTROL; + __IO uint32_t TIMER2INTCLR; + __IO uint32_t TIMER2RIS; + __IO uint32_t TIMER2MIS; + __IO uint32_t TIMER2BGLOAD; +}FM3_DTIM_TypeDef; + +/****************************************************************************** + * MFT_FRT_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Free Running Timer registers */ +typedef struct +{ + uint8_t RESERVED0[40]; + __IO uint16_t TCCP0; + uint8_t RESERVED1[2]; + __IO uint16_t TCDT0; + uint8_t RESERVED2[2]; + __IO uint16_t TCSA0; + uint8_t RESERVED3[2]; + __IO uint16_t TCSB0; + uint8_t RESERVED4[2]; + __IO uint16_t TCCP1; + uint8_t RESERVED5[2]; + __IO uint16_t TCDT1; + uint8_t RESERVED6[2]; + __IO uint16_t TCSA1; + uint8_t RESERVED7[2]; + __IO uint16_t TCSB1; + uint8_t RESERVED8[2]; + __IO uint16_t TCCP2; + uint8_t RESERVED9[2]; + __IO uint16_t TCDT2; + uint8_t RESERVED10[2]; + __IO uint16_t TCSA2; + uint8_t RESERVED11[2]; + __IO uint16_t TCSB2; +}FM3_MFT_FRT_TypeDef; + +/****************************************************************************** + * MFT_OCU_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Output Compare Unit registers */ +typedef struct +{ + __IO uint16_t OCCP0; + uint8_t RESERVED0[2]; + __IO uint16_t OCCP1; + uint8_t RESERVED1[2]; + __IO uint16_t OCCP2; + uint8_t RESERVED2[2]; + __IO uint16_t OCCP3; + uint8_t RESERVED3[2]; + __IO uint16_t OCCP4; + uint8_t RESERVED4[2]; + __IO uint16_t OCCP5; + uint8_t RESERVED5[2]; + __IO uint8_t OCSA10; + __IO uint8_t OCSB10; + uint8_t RESERVED6[2]; + __IO uint8_t OCSA32; + __IO uint8_t OCSB32; + uint8_t RESERVED7[2]; + __IO uint8_t OCSA54; + __IO uint8_t OCSB54; + uint8_t RESERVED8[3]; + __IO uint8_t OCSC; + uint8_t RESERVED9[50]; + __IO uint8_t OCFS10; + __IO uint8_t OCFS32; + uint8_t RESERVED10[2]; + __IO uint8_t OCFS54; +}FM3_MFT_OCU_TypeDef; + +/****************************************************************************** + * MFT_WFG_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +typedef struct +{ + uint8_t RESERVED0[128]; + __IO uint16_t WFTM10; + uint8_t RESERVED1[2]; + __IO uint16_t WFTM32; + uint8_t RESERVED2[2]; + __IO uint16_t WFTM54; + uint8_t RESERVED3[2]; + __IO uint16_t WFSA10; + uint8_t RESERVED4[2]; + __IO uint16_t WFSA32; + uint8_t RESERVED5[2]; + __IO uint16_t WFSA54; + uint8_t RESERVED6[2]; + __IO uint16_t WFIR; + uint8_t RESERVED7[2]; + __IO uint16_t NZCL; +}FM3_MFT_WFG_TypeDef; + +/****************************************************************************** + * MFT_ICU_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 Input Capture Unit registers */ +typedef struct +{ + uint8_t RESERVED0[96]; + __IO uint8_t ICFS10; + __IO uint8_t ICFS32; + uint8_t RESERVED1[6]; + __IO uint16_t ICCP0; + uint8_t RESERVED2[2]; + __IO uint16_t ICCP1; + uint8_t RESERVED3[2]; + __IO uint16_t ICCP2; + uint8_t RESERVED4[2]; + __IO uint16_t ICCP3; + uint8_t RESERVED5[2]; + __IO uint8_t ICSA10; + __IO uint8_t ICSB10; + uint8_t RESERVED6[2]; + __IO uint8_t ICSA32; + __IO uint8_t ICSB32; +}FM3_MFT_ICU_TypeDef; + +/****************************************************************************** + * MFT_ADCMP_MODULE + ******************************************************************************/ +/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +typedef struct +{ + uint8_t RESERVED0[160]; + __IO uint16_t ACCP0; + uint8_t RESERVED1[2]; + __IO uint16_t ACCPDN0; + uint8_t RESERVED2[2]; + __IO uint16_t ACCP1; + uint8_t RESERVED3[2]; + __IO uint16_t ACCPDN1; + uint8_t RESERVED4[2]; + __IO uint16_t ACCP2; + uint8_t RESERVED5[2]; + __IO uint16_t ACCPDN2; + uint8_t RESERVED6[2]; + __IO uint8_t ACSB; + uint8_t RESERVED7[3]; + __IO uint16_t ACSA; + uint8_t RESERVED8[2]; + __IO uint16_t ATSA; +}FM3_MFT_ADCMP_TypeDef; + +/****************************************************************************** + * MFT_PPG_MODULE + ******************************************************************************/ +/* Multifunction Timer PPG registers */ +typedef struct +{ + uint8_t RESERVED0; + __IO uint8_t TTCR0; + uint8_t RESERVED1[7]; + __IO uint8_t COMP0; + uint8_t RESERVED2[2]; + __IO uint8_t COMP2; + uint8_t RESERVED3[4]; + __IO uint8_t COMP4; + uint8_t RESERVED4[2]; + __IO uint8_t COMP6; + uint8_t RESERVED5[12]; + __IO uint8_t TTCR1; + uint8_t RESERVED6[7]; + __IO uint8_t COMP1; + uint8_t RESERVED7[2]; + __IO uint8_t COMP3; + uint8_t RESERVED8[4]; + __IO uint8_t COMP5; + uint8_t RESERVED9[2]; + __IO uint8_t COMP7; + uint8_t RESERVED10[203]; + __IO uint16_t TRG; + uint8_t RESERVED11[2]; + __IO uint16_t REVC; + uint8_t RESERVED12[250]; + __IO uint8_t PPGC1; + __IO uint8_t PPGC0; + uint8_t RESERVED13[2]; + __IO uint8_t PPGC3; + __IO uint8_t PPGC2; + uint8_t RESERVED14[2]; + union { + __IO uint16_t PRL0; + struct { + __IO uint8_t PRLL0; + __IO uint8_t PRLH0; + }; + }; + uint8_t RESERVED15[2]; + union { + __IO uint16_t PRL1; + struct { + __IO uint8_t PRLL1; + __IO uint8_t PRLH1; + }; + }; + uint8_t RESERVED16[2]; + union { + __IO uint16_t PRL2; + struct { + __IO uint8_t PRLL2; + __IO uint8_t PRLH2; + }; + }; + uint8_t RESERVED17[2]; + union { + __IO uint16_t PRL3; + struct { + __IO uint8_t PRLL3; + __IO uint8_t PRLH3; + }; + }; + uint8_t RESERVED18[2]; + __IO uint8_t GATEC0; + uint8_t RESERVED19[39]; + __IO uint8_t PPGC5; + __IO uint8_t PPGC4; + uint8_t RESERVED20[2]; + __IO uint8_t PPGC7; + __IO uint8_t PPGC6; + uint8_t RESERVED21[2]; + union { + __IO uint16_t PRL4; + struct { + __IO uint8_t PRLL4; + __IO uint8_t PRLH4; + }; + }; + uint8_t RESERVED22[2]; + union { + __IO uint16_t PRL5; + struct { + __IO uint8_t PRLL5; + __IO uint8_t PRLH5; + }; + }; + uint8_t RESERVED23[2]; + union { + __IO uint16_t PRL6; + struct { + __IO uint8_t PRLL6; + __IO uint8_t PRLH6; + }; + }; + uint8_t RESERVED24[2]; + union { + __IO uint16_t PRL7; + struct { + __IO uint8_t PRLL7; + __IO uint8_t PRLH7; + }; + }; + uint8_t RESERVED25[2]; + __IO uint8_t GATEC4; + uint8_t RESERVED26[39]; + __IO uint8_t PPGC9; + __IO uint8_t PPGC8; + uint8_t RESERVED27[2]; + __IO uint8_t PPGC11; + __IO uint8_t PPGC10; + uint8_t RESERVED28[2]; + union { + __IO uint16_t PRL8; + struct { + __IO uint8_t PRLL8; + __IO uint8_t PRLH8; + }; + }; + uint8_t RESERVED29[2]; + union { + __IO uint16_t PRL9; + struct { + __IO uint8_t PRLL9; + __IO uint8_t PRLH9; + }; + }; + uint8_t RESERVED30[2]; + union { + __IO uint16_t PRL10; + struct { + __IO uint8_t PRLL10; + __IO uint8_t PRLH10; + }; + }; + uint8_t RESERVED31[2]; + union { + __IO uint16_t PRL11; + struct { + __IO uint8_t PRLL11; + __IO uint8_t PRLH11; + }; + }; + uint8_t RESERVED32[2]; + __IO uint8_t GATEC8; + uint8_t RESERVED33[39]; + __IO uint8_t PPGC13; + __IO uint8_t PPGC12; + uint8_t RESERVED34[2]; + __IO uint8_t PPGC15; + __IO uint8_t PPGC14; + uint8_t RESERVED35[2]; + union { + __IO uint16_t PRL12; + struct { + __IO uint8_t PRLL12; + __IO uint8_t PRLH12; + }; + }; + uint8_t RESERVED36[2]; + union { + __IO uint16_t PRL13; + struct { + __IO uint8_t PRLL13; + __IO uint8_t PRLH13; + }; + }; + uint8_t RESERVED37[2]; + union { + __IO uint16_t PRL14; + struct { + __IO uint8_t PRLL14; + __IO uint8_t PRLH14; + }; + }; + uint8_t RESERVED38[2]; + union { + __IO uint16_t PRL15; + struct { + __IO uint8_t PRLL15; + __IO uint8_t PRLH15; + }; + }; + uint8_t RESERVED39[2]; + __IO uint8_t GATEC12; +}FM3_MFT_PPG_TypeDef; + +/****************************************************************************** + * BT_PPG_MODULE + ******************************************************************************/ +/* Base Timer 0 PPG registers */ +typedef struct +{ + __IO uint16_t PRLL; + uint8_t RESERVED0[2]; + __IO uint16_t PRLH; + uint8_t RESERVED1[2]; + __IO uint16_t TMR; + uint8_t RESERVED2[2]; + __IO uint16_t TMCR; + uint8_t RESERVED3[2]; + __IO uint8_t STC; + __IO uint8_t TMCR2; +}FM3_BT_PPG_TypeDef; + +/****************************************************************************** + * BT_PWM_MODULE + ******************************************************************************/ +/* Base Timer 0 PWM registers */ +typedef struct +{ + __IO uint16_t PCSR; + uint8_t RESERVED0[2]; + __IO uint16_t PDUT; + uint8_t RESERVED1[2]; + __IO uint16_t TMR; + uint8_t RESERVED2[2]; + __IO uint16_t TMCR; + uint8_t RESERVED3[2]; + __IO uint8_t STC; + __IO uint8_t TMCR2; +}FM3_BT_PWM_TypeDef; + +/****************************************************************************** + * BT_RT_MODULE + ******************************************************************************/ +/* Base Timer 0 RT registers */ +typedef struct +{ + __IO uint16_t PCSR; + uint8_t RESERVED0[6]; + __IO uint16_t TMR; + uint8_t RESERVED1[2]; + __IO uint16_t TMCR; + uint8_t RESERVED2[2]; + __IO uint8_t STC; + __IO uint8_t TMCR2; +}FM3_BT_RT_TypeDef; + +/****************************************************************************** + * BT_PWC_MODULE + ******************************************************************************/ +/* Base Timer 0 PWC registers */ +typedef struct +{ + uint8_t RESERVED0[4]; + __IO uint16_t DTBF; + uint8_t RESERVED1[6]; + __IO uint16_t TMCR; + uint8_t RESERVED2[2]; + __IO uint8_t STC; + __IO uint8_t TMCR2; +}FM3_BT_PWC_TypeDef; + +/****************************************************************************** + * BTIOSEL03_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 0 - channel 3 registers */ +typedef struct +{ + uint8_t RESERVED0; + __IO uint8_t BTSEL0123; +}FM3_BTIOSEL03_TypeDef; + +/****************************************************************************** + * BTIOSEL47_MODULE + ******************************************************************************/ +/* Base Timer I/O selector channel 4 - channel 7 registers */ +typedef struct +{ + uint8_t RESERVED0; + __IO uint8_t BTSEL4567; +}FM3_BTIOSEL47_TypeDef; + +/****************************************************************************** + * SBSSR_MODULE + ******************************************************************************/ +/* Software based Simulation Startup (Base Timer) register */ +typedef struct +{ + __IO uint16_t BTSSSR; +}FM3_SBSSR_TypeDef; + +/****************************************************************************** + * QPRC_MODULE + ******************************************************************************/ +/* Quad position and revolution counter channel 0 registers */ +typedef struct +{ + __IO uint16_t QPCR; + uint8_t RESERVED0[2]; + __IO uint16_t QRCR; + uint8_t RESERVED1[2]; + __IO uint16_t QPCCR; + uint8_t RESERVED2[2]; + __IO uint16_t QPRCR; + uint8_t RESERVED3[2]; + __IO uint16_t QMPR; + uint8_t RESERVED4[2]; + union { + __IO uint16_t QICR; + struct { + __IO uint8_t QICRL; + __IO uint8_t QICRH; + }; + }; + uint8_t RESERVED5[2]; + union { + __IO uint16_t QCR; + struct { + __IO uint8_t QCRL; + __IO uint8_t QCRH; + }; + }; + uint8_t RESERVED6[2]; + __IO uint16_t QECR; +}FM3_QPRC_TypeDef; + +/****************************************************************************** + * ADC12_MODULE + ******************************************************************************/ +/* 12-bit ADC unit 0 registers */ +typedef struct +{ + __IO uint8_t ADSR; + __IO uint8_t ADCR; + uint8_t RESERVED0[6]; + __IO uint8_t SFNS; + __IO uint8_t SCCR; + uint8_t RESERVED1[2]; + union { + __IO uint32_t SCFD; + struct { + __IO uint16_t SCFDL; + __IO uint16_t SCFDH; + }; + }; + union { + __IO uint16_t SCIS23; + struct { + __IO uint8_t SCIS2; + __IO uint8_t SCIS3; + }; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t SCIS01; + struct { + __IO uint8_t SCIS0; + __IO uint8_t SCIS1; + }; + }; + uint8_t RESERVED3[2]; + __IO uint8_t PFNS; + __IO uint8_t PCCR; + uint8_t RESERVED4[2]; + union { + __IO uint32_t PCFD; + struct { + __IO uint16_t PCFDL; + __IO uint16_t PCFDH; + }; + }; + __IO uint8_t PCIS; + uint8_t RESERVED5[3]; + __IO uint8_t CMPCR; + uint8_t RESERVED6; + __IO uint16_t CMPD; + union { + __IO uint16_t ADSS23; + struct { + __IO uint8_t ADSS2; + __IO uint8_t ADSS3; + }; + }; + uint8_t RESERVED7[2]; + union { + __IO uint16_t ADSS01; + struct { + __IO uint8_t ADSS0; + __IO uint8_t ADSS1; + }; + }; + uint8_t RESERVED8[2]; + union { + __IO uint16_t ADST01; + struct { + __IO uint8_t ADST1; + __IO uint8_t ADST0; + }; + }; + uint8_t RESERVED9[2]; + __IO uint8_t ADCT; + uint8_t RESERVED10[3]; + __IO uint8_t PRTSL; + __IO uint8_t SCTSL; + uint8_t RESERVED11[2]; + __IO uint8_t ADCEN; +}FM3_ADC_TypeDef; + +/****************************************************************************** + * CRTRIM_MODULE + ******************************************************************************/ +/* CR trimming registers */ +typedef struct +{ + __IO uint8_t MCR_PSR; + uint8_t RESERVED0[3]; + __IO uint16_t MCR_FTRM; + uint8_t RESERVED1[6]; + __IO uint32_t MCR_RLR; +}FM3_CRTRIM_TypeDef; + +/****************************************************************************** + * EXTI_MODULE + ******************************************************************************/ +/* External interrupt registers */ +typedef struct +{ + __IO uint16_t ENIR; + uint8_t RESERVED0[2]; + __IO uint16_t EIRR; + uint8_t RESERVED1[2]; + __IO uint16_t EICL; + uint8_t RESERVED2[2]; + __IO uint32_t ELVR; + uint8_t RESERVED3[4]; + __IO uint8_t NMIRR; + uint8_t RESERVED4[3]; + __IO uint8_t NMICL; +}FM3_EXTI_TypeDef; + +/****************************************************************************** + * INTREQ_MODULE + ******************************************************************************/ +/* Interrupt request read registers */ +typedef struct +{ + __IO uint32_t DRQSEL; + uint8_t RESERVED0[12]; + __IO uint32_t EXC02MON; + __IO uint32_t IRQ00MON; + __IO uint32_t IRQ01MON; + __IO uint32_t IRQ02MON; + __IO uint32_t IRQ03MON; + __IO uint32_t IRQ04MON; + __IO uint32_t IRQ05MON; + __IO uint32_t IRQ06MON; + __IO uint32_t IRQ07MON; + __IO uint32_t IRQ08MON; + __IO uint32_t IRQ09MON; + __IO uint32_t IRQ10MON; + __IO uint32_t IRQ11MON; + __IO uint32_t IRQ12MON; + __IO uint32_t IRQ13MON; + __IO uint32_t IRQ14MON; + __IO uint32_t IRQ15MON; + __IO uint32_t IRQ16MON; + __IO uint32_t IRQ17MON; + __IO uint32_t IRQ18MON; + __IO uint32_t IRQ19MON; + __IO uint32_t IRQ20MON; + __IO uint32_t IRQ21MON; + __IO uint32_t IRQ22MON; + __IO uint32_t IRQ23MON; + __IO uint32_t IRQ24MON; + __IO uint32_t IRQ25MON; + __IO uint32_t IRQ26MON; + __IO uint32_t IRQ27MON; + __IO uint32_t IRQ28MON; + __IO uint32_t IRQ29MON; + __IO uint32_t IRQ30MON; + __IO uint32_t IRQ31MON; + __IO uint32_t IRQ32MON; + __IO uint32_t IRQ33MON; + __IO uint32_t IRQ34MON; + __IO uint32_t IRQ35MON; + __IO uint32_t IRQ36MON; + __IO uint32_t IRQ37MON; + __IO uint32_t IRQ38MON; + __IO uint32_t IRQ39MON; + __IO uint32_t IRQ40MON; + __IO uint32_t IRQ41MON; + __IO uint32_t IRQ42MON; + __IO uint32_t IRQ43MON; + __IO uint32_t IRQ44MON; + __IO uint32_t IRQ45MON; + __IO uint32_t IRQ46MON; + __IO uint32_t IRQ47MON; +}FM3_INTREQ_TypeDef; + +/****************************************************************************** + * GPIO_MODULE + ******************************************************************************/ +/* General purpose I/O registers */ +typedef struct +{ + __IO uint32_t PFR0; + __IO uint32_t PFR1; + __IO uint32_t PFR2; + __IO uint32_t PFR3; + __IO uint32_t PFR4; + __IO uint32_t PFR5; + __IO uint32_t PFR6; + __IO uint32_t PFR7; + __IO uint32_t PFR8; + uint8_t RESERVED0[220]; + __IO uint32_t PCR0; + __IO uint32_t PCR1; + __IO uint32_t PCR2; + __IO uint32_t PCR3; + __IO uint32_t PCR4; + __IO uint32_t PCR5; + __IO uint32_t PCR6; + __IO uint32_t PCR7; + uint8_t RESERVED1[224]; + __IO uint32_t DDR0; + __IO uint32_t DDR1; + __IO uint32_t DDR2; + __IO uint32_t DDR3; + __IO uint32_t DDR4; + __IO uint32_t DDR5; + __IO uint32_t DDR6; + __IO uint32_t DDR7; + __IO uint32_t DDR8; + uint8_t RESERVED2[220]; + __IO uint32_t PDIR0; + __IO uint32_t PDIR1; + __IO uint32_t PDIR2; + __IO uint32_t PDIR3; + __IO uint32_t PDIR4; + __IO uint32_t PDIR5; + __IO uint32_t PDIR6; + __IO uint32_t PDIR7; + __IO uint32_t PDIR8; + uint8_t RESERVED3[220]; + __IO uint32_t PDOR0; + __IO uint32_t PDOR1; + __IO uint32_t PDOR2; + __IO uint32_t PDOR3; + __IO uint32_t PDOR4; + __IO uint32_t PDOR5; + __IO uint32_t PDOR6; + __IO uint32_t PDOR7; + __IO uint32_t PDOR8; + uint8_t RESERVED4[220]; + __IO uint32_t ADE; + uint8_t RESERVED5[124]; + __IO uint32_t SPSR; + uint8_t RESERVED6[124]; + __IO uint32_t EPFR00; + __IO uint32_t EPFR01; + __IO uint32_t EPFR02; + uint8_t RESERVED7[4]; + __IO uint32_t EPFR04; + __IO uint32_t EPFR05; + __IO uint32_t EPFR06; + __IO uint32_t EPFR07; + __IO uint32_t EPFR08; + __IO uint32_t EPFR09; + __IO uint32_t EPFR10; +}FM3_GPIO_TypeDef; + +/****************************************************************************** + * LVD_MODULE + ******************************************************************************/ +/* Low voltage detection registers */ +typedef struct +{ + __IO uint8_t LVD_CTL; + uint8_t RESERVED0[3]; + __IO uint8_t LVD_STR; + uint8_t RESERVED1[3]; + __IO uint8_t LVD_CLR; + uint8_t RESERVED2[3]; + __IO uint32_t LVD_RLR; + __IO uint8_t LVD_STR2; +}FM3_LVD_TypeDef; + +/****************************************************************************** + * USBCLK + ******************************************************************************/ +/* USB clock registers */ +typedef struct +{ + __IO uint8_t UCCR; + uint8_t RESERVED0[3]; + __IO uint8_t UPCR1; + uint8_t RESERVED1[3]; + __IO uint8_t UPCR2; + uint8_t RESERVED2[3]; + __IO uint8_t UPCR3; + uint8_t RESERVED3[3]; + __IO uint8_t UPCR4; + uint8_t RESERVED4[3]; + __IO uint8_t UP_STR; + uint8_t RESERVED5[3]; + __IO uint8_t UPINT_ENR; + uint8_t RESERVED6[3]; + __IO uint8_t UPINT_CLR; + uint8_t RESERVED7[3]; + __IO uint8_t UPINT_STR; + uint8_t RESERVED8[15]; + __IO uint8_t USBEN; +}FM3_USBCLK_TypeDef; + +/****************************************************************************** + * CANPRE_MODULE + ******************************************************************************/ +/* CAN prescaler register */ +typedef struct +{ + __IO uint8_t CANPRE; +}FM3_CANPRE_TypeDef; + +/****************************************************************************** + * MFS03_UART_MODULE + ******************************************************************************/ +/* UART asynchronous channel 0 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; +}FM3_MFS03_UART_TypeDef; + +/****************************************************************************** + * MFS03_CSIO_MODULE + ******************************************************************************/ +/* UART synchronous channel 0 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; +}FM3_MFS03_CSIO_TypeDef; + +/****************************************************************************** + * MFS03_LIN_MODULE + ******************************************************************************/ +/* UART LIN channel 0 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; +}FM3_MFS03_LIN_TypeDef; + +/****************************************************************************** + * MFS03_I2C_MODULE + ******************************************************************************/ +/* I2C channel 0 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t IBCR; + uint8_t RESERVED0[2]; + __IO uint8_t IBSR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[2]; + __IO uint8_t ISBA; + __IO uint8_t ISMK; +}FM3_MFS03_I2C_TypeDef; + +/****************************************************************************** + * MFS47_UART_MODULE + ******************************************************************************/ +/* UART asynchronous channel 4 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[6]; + union { + __IO uint16_t FCR; + struct { + __IO uint8_t FCR0; + __IO uint8_t FCR1; + }; + }; + uint8_t RESERVED4[2]; + union { + __IO uint16_t FBYTE; + struct { + __IO uint8_t FBYTE1; + __IO uint8_t FBYTE2; + }; + }; +}FM3_MFS47_UART_TypeDef; + +/****************************************************************************** + * MFS47_CSIO_MODULE + ******************************************************************************/ +/* UART synchronous channel 4 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[6]; + union { + __IO uint16_t FCR; + struct { + __IO uint8_t FCR0; + __IO uint8_t FCR1; + }; + }; + uint8_t RESERVED4[2]; + union { + __IO uint16_t FBYTE; + struct { + __IO uint8_t FBYTE1; + __IO uint8_t FBYTE2; + }; + }; +}FM3_MFS47_CSIO_TypeDef; + +/****************************************************************************** + * MFS47_LIN_MODULE + ******************************************************************************/ +/* UART LIN channel 4 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t SCR; + uint8_t RESERVED0[2]; + __IO uint8_t ESCR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[6]; + union { + __IO uint16_t FCR; + struct { + __IO uint8_t FCR0; + __IO uint8_t FCR1; + }; + }; + uint8_t RESERVED4[2]; + union { + __IO uint16_t FBYTE; + struct { + __IO uint8_t FBYTE1; + __IO uint8_t FBYTE2; + }; + }; +}FM3_MFS47_LIN_TypeDef; + +/****************************************************************************** + * MFS47_I2C_MODULE + ******************************************************************************/ +/* I2C channel 4 registers */ +typedef struct +{ + __IO uint8_t SMR; + __IO uint8_t IBCR; + uint8_t RESERVED0[2]; + __IO uint8_t IBSR; + __IO uint8_t SSR; + uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + __IO uint16_t TDR; + }; + uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + struct { + __IO uint8_t BGR0; + __IO uint8_t BGR1; + }; + }; + uint8_t RESERVED3[2]; + __IO uint8_t ISBA; + __IO uint8_t ISMK; + uint8_t RESERVED4[2]; + union { + __IO uint16_t FCR; + struct { + __IO uint8_t FCR0; + __IO uint8_t FCR1; + }; + }; + uint8_t RESERVED5[2]; + union { + __IO uint16_t FBYTE; + struct { + __IO uint8_t FBYTE1; + __IO uint8_t FBYTE2; + }; + }; +}FM3_MFS47_I2C_TypeDef; + +/****************************************************************************** + * CRC_MODULE + ******************************************************************************/ +/* CRC registers */ +typedef struct +{ + __IO uint8_t CRCCR; + uint8_t RESERVED0[3]; + __IO uint32_t CRCINIT; + union { + __IO uint32_t CRCIN; + struct { + union { + __IO uint16_t CRCINL; + struct { + __IO uint8_t CRCINLL; + __IO uint8_t CRCINLH; + }; + }; + union { + __IO uint16_t CRCINH; + struct { + __IO uint8_t CRCINHL; + __IO uint8_t CRCINHH; + }; + }; + }; + }; + __IO uint32_t CRCR; +}FM3_CRC_TypeDef; + +/****************************************************************************** + * WC_MODULE + ******************************************************************************/ +/* Watch counter registers */ +typedef struct +{ + __IO uint8_t WCRD; + __IO uint8_t WCRL; + __IO uint8_t WCCR; + uint8_t RESERVED0[13]; + __IO uint16_t CLK_SEL; + uint8_t RESERVED1[2]; + __IO uint8_t CLK_EN; +}FM3_WC_TypeDef; + +/****************************************************************************** + * EXBUS_MODULE + ******************************************************************************/ +/* External bus interface registers */ +typedef struct +{ + __IO uint32_t MODE0; + __IO uint32_t MODE1; + __IO uint32_t MODE2; + __IO uint32_t MODE3; + __IO uint32_t MODE4; + __IO uint32_t MODE5; + __IO uint32_t MODE6; + __IO uint32_t MODE7; + __IO uint32_t TIM0; + __IO uint32_t TIM1; + __IO uint32_t TIM2; + __IO uint32_t TIM3; + __IO uint32_t TIM4; + __IO uint32_t TIM5; + __IO uint32_t TIM6; + __IO uint32_t TIM7; + __IO uint32_t AREA0; + __IO uint32_t AREA1; + __IO uint32_t AREA2; + __IO uint32_t AREA3; + __IO uint32_t AREA4; + __IO uint32_t AREA5; + __IO uint32_t AREA6; + __IO uint32_t AREA7; +}FM3_EXBUS_TypeDef; + +/****************************************************************************** + * USB_MODULE + ******************************************************************************/ +/* USB channel 0 registers */ +typedef struct +{ + union { + __IO uint16_t HCNT; + struct { + __IO uint8_t HCNT0; + __IO uint8_t HCNT1; + }; + }; + uint8_t RESERVED0[2]; + __IO uint8_t HIRQ; + __IO uint8_t HERR; + uint8_t RESERVED1[2]; + __IO uint8_t HSTATE; + __IO uint8_t HFCOMP; + uint8_t RESERVED2[2]; + union { + __IO uint16_t HRTIMER; + struct { + __IO uint8_t HRTIMER0; + __IO uint8_t HRTIMER1; + }; + }; + uint8_t RESERVED3[2]; + __IO uint8_t HRTIMER2; + __IO uint8_t HADR; + uint8_t RESERVED4[2]; + union { + __IO uint16_t HEOF; + struct { + __IO uint8_t HEOF0; + __IO uint8_t HEOF1; + }; + }; + uint8_t RESERVED5[2]; + union { + __IO uint16_t HFRAME; + struct { + __IO uint8_t HFRAME0; + __IO uint8_t HFRAME1; + }; + }; + uint8_t RESERVED6[2]; + __IO uint8_t HTOKEN; + uint8_t RESERVED7[3]; + __IO uint16_t UDCC; + uint8_t RESERVED8[2]; + __IO uint16_t EP0C; + uint8_t RESERVED9[2]; + __IO uint16_t EP1C; + uint8_t RESERVED10[2]; + __IO uint16_t EP2C; + uint8_t RESERVED11[2]; + __IO uint16_t EP3C; + uint8_t RESERVED12[2]; + __IO uint16_t EP4C; + uint8_t RESERVED13[2]; + __IO uint16_t EP5C; + uint8_t RESERVED14[2]; + __IO uint16_t TMSP; + uint8_t RESERVED15[2]; + __IO uint8_t UDCS; + __IO uint8_t UDCIE; + uint8_t RESERVED16[2]; + __IO uint16_t EP0IS; + uint8_t RESERVED17[2]; + __IO uint16_t EP0OS; + uint8_t RESERVED18[2]; + __IO uint16_t EP1S; + uint8_t RESERVED19[2]; + __IO uint16_t EP2S; + uint8_t RESERVED20[2]; + __IO uint16_t EP3S; + uint8_t RESERVED21[2]; + __IO uint16_t EP4S; + uint8_t RESERVED22[2]; + __IO uint16_t EP5S; + uint8_t RESERVED23[2]; + union { + __IO uint16_t EP0DT; + struct { + __IO uint8_t EP0DTL; + __IO uint8_t EP0DTH; + }; + }; + uint8_t RESERVED24[2]; + union { + __IO uint16_t EP1DT; + struct { + __IO uint8_t EP1DTL; + __IO uint8_t EP1DTH; + }; + }; + uint8_t RESERVED25[2]; + union { + __IO uint16_t EP2DT; + struct { + __IO uint8_t EP2DTL; + __IO uint8_t EP2DTH; + }; + }; + uint8_t RESERVED26[2]; + union { + __IO uint16_t EP3DT; + struct { + __IO uint8_t EP3DTL; + __IO uint8_t EP3DTH; + }; + }; + uint8_t RESERVED27[2]; + union { + __IO uint16_t EP4DT; + struct { + __IO uint8_t EP4DTL; + __IO uint8_t EP4DTH; + }; + }; + uint8_t RESERVED28[2]; + union { + __IO uint16_t EP5DT; + struct { + __IO uint8_t EP5DTL; + __IO uint8_t EP5DTH; + }; + }; +}FM3_USB_TypeDef; + +/****************************************************************************** + * DMAC_MODULE + ******************************************************************************/ +/* DMA controller */ +typedef struct +{ + __IO uint32_t DMACR; + uint8_t RESERVED0[12]; + __IO uint32_t DMACA0; + __IO uint32_t DMACB0; + __IO uint32_t DMACSA0; + __IO uint32_t DMACDA0; + __IO uint32_t DMACA1; + __IO uint32_t DMACB1; + __IO uint32_t DMACSA1; + __IO uint32_t DMACDA1; + __IO uint32_t DMACA2; + __IO uint32_t DMACB2; + __IO uint32_t DMACSA2; + __IO uint32_t DMACDA2; + __IO uint32_t DMACA3; + __IO uint32_t DMACB3; + __IO uint32_t DMACSA3; + __IO uint32_t DMACDA3; + __IO uint32_t DMACA4; + __IO uint32_t DMACB4; + __IO uint32_t DMACSA4; + __IO uint32_t DMACDA4; + __IO uint32_t DMACA5; + __IO uint32_t DMACB5; + __IO uint32_t DMACSA5; + __IO uint32_t DMACDA5; + __IO uint32_t DMACA6; + __IO uint32_t DMACB6; + __IO uint32_t DMACSA6; + __IO uint32_t DMACDA6; + __IO uint32_t DMACA7; + __IO uint32_t DMACB7; + __IO uint32_t DMACSA7; + __IO uint32_t DMACDA7; +}FM3_DMAC_TypeDef; + +/****************************************************************************** + * CAN_MODULE + ******************************************************************************/ +/* CAN channel 0 registers */ +typedef struct +{ + __IO uint16_t CTRLR; + __IO uint16_t STATR; + __IO uint16_t ERRCNT; + __IO uint16_t BTR; + __IO uint16_t INTR; + __IO uint16_t TESTR; + __IO uint16_t BRPER; + uint8_t RESERVED0[2]; + __IO uint16_t IF1CREQ; + __IO uint16_t IF1CMSK; + union { + __IO uint32_t IF1MSK; + struct { + __IO uint16_t IF1MSK1; + __IO uint16_t IF1MSK2; + }; + }; + union { + __IO uint32_t IF1ARB; + struct { + __IO uint16_t IF1ARB1; + __IO uint16_t IF1ARB2; + }; + }; + __IO uint16_t IF1MCTR; + uint8_t RESERVED1[2]; + union { + __IO uint32_t IF1DTA_L; + struct { + __IO uint16_t IF1DTA1_L; + __IO uint16_t IF1DTA2_L; + }; + }; + union { + __IO uint32_t IF1DTB_L; + struct { + __IO uint16_t IF1DTB1_L; + __IO uint16_t IF1DTB2_L; + }; + }; + uint8_t RESERVED2[8]; + union { + __IO uint32_t IF1DTA_B; + struct { + __IO uint16_t IF1DTA2_B; + __IO uint16_t IF1DTA1_B; + }; + }; + union { + __IO uint32_t IF1DTB_B; + struct { + __IO uint16_t IF1DTB2_B; + __IO uint16_t IF1DTB1_B; + }; + }; + uint8_t RESERVED3[8]; + __IO uint16_t IF2CREQ; + __IO uint16_t IF2CMSK; + union { + __IO uint32_t IF2MSK; + struct { + __IO uint16_t IF2MSK1; + __IO uint16_t IF2MSK2; + }; + }; + union { + __IO uint32_t IF2ARB; + struct { + __IO uint16_t IF2ARB1; + __IO uint16_t IF2ARB2; + }; + }; + __IO uint16_t IF2MCTR; + uint8_t RESERVED4[2]; + union { + __IO uint32_t IF2DTA_L; + struct { + __IO uint16_t IF2DTA1_L; + __IO uint16_t IF2DTA2_L; + }; + }; + union { + __IO uint32_t IF2DTB_L; + struct { + __IO uint16_t IF2DTB1_L; + __IO uint16_t IF2DTB2_L; + }; + }; + uint8_t RESERVED5[8]; + union { + __IO uint32_t IF2DTA_B; + struct { + __IO uint16_t IF2DTA2_B; + __IO uint16_t IF2DTA1_B; + }; + }; + union { + __IO uint32_t IF2DTB_B; + struct { + __IO uint16_t IF2DTB2_B; + __IO uint16_t IF2DTB1_B; + }; + }; + uint8_t RESERVED6[24]; + union { + __IO uint32_t TREQR; + struct { + __IO uint16_t TREQR1; + __IO uint16_t TREQR2; + }; + }; + uint8_t RESERVED7[12]; + union { + __IO uint32_t NEWDT; + struct { + __IO uint16_t NEWDT1; + __IO uint16_t NEWDT2; + }; + }; + uint8_t RESERVED8[12]; + union { + __IO uint32_t INTPND; + struct { + __IO uint16_t INTPND1; + __IO uint16_t INTPND2; + }; + }; + uint8_t RESERVED9[12]; + union { + __IO uint32_t MSGVAL; + struct { + __IO uint16_t MSGVAL1; + __IO uint16_t MSGVAL2; + }; + }; +}FM3_CAN_TypeDef; + + +/****************************************************************************** + * Peripheral memory map + ******************************************************************************/ +#define FM3_FLASH_BASE (0x00000000UL) /* Flash Base */ +#define FM3_PERIPH_BASE (0x40000000UL) /* Peripheral Base */ +#define FM3_CM3_BASE (0xE0100000UL) /* CM3 Private */ + +#define FM3_FLASH_IF_BASE (FM3_PERIPH_BASE + 0x00000UL) /* Flash interface registers */ +#define FM3_CRG_BASE (FM3_PERIPH_BASE + 0x10000UL) /* Clock and reset registers */ +#define FM3_HWWDT_BASE (FM3_PERIPH_BASE + 0x11000UL) /* Hardware watchdog registers */ +#define FM3_SWWDT_BASE (FM3_PERIPH_BASE + 0x12000UL) /* Software watchdog registers */ +#define FM3_DTIM_BASE (FM3_PERIPH_BASE + 0x15000UL) /* Dual timer 1/2 registers */ +#define FM3_MFT0_FRT_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Free Running Timer registers */ +#define FM3_MFT0_OCU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Output Compare Unit registers */ +#define FM3_MFT0_WFG_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +#define FM3_MFT0_ICU_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 Input Capture Unit registers */ +#define FM3_MFT0_ADCMP_BASE (FM3_PERIPH_BASE + 0x20000UL) /* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +#define FM3_MFT1_FRT_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Free Running Timer registers */ +#define FM3_MFT1_OCU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Output Compare Unit registers */ +#define FM3_MFT1_WFG_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ +#define FM3_MFT1_ICU_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 Input Capture Unit registers */ +#define FM3_MFT1_ADCMP_BASE (FM3_PERIPH_BASE + 0x21000UL) /* Multifunction Timer unit 1 ADC Start Compare Unit registers */ +#define FM3_MFT_PPG_BASE (FM3_PERIPH_BASE + 0x24000UL) /* Multifunction Timer PPG registers */ +#define FM3_BT0_PPG_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PPG registers */ +#define FM3_BT0_PWM_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWM registers */ +#define FM3_BT0_RT_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 RT registers */ +#define FM3_BT0_PWC_BASE (FM3_PERIPH_BASE + 0x25000UL) /* Base Timer 0 PWC registers */ +#define FM3_BT1_PPG_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PPG registers */ +#define FM3_BT1_PWM_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWM registers */ +#define FM3_BT1_RT_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 RT registers */ +#define FM3_BT1_PWC_BASE (FM3_PERIPH_BASE + 0x25040UL) /* Base Timer 1 PWC registers */ +#define FM3_BT2_PPG_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PPG registers */ +#define FM3_BT2_PWM_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWM registers */ +#define FM3_BT2_RT_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 RT registers */ +#define FM3_BT2_PWC_BASE (FM3_PERIPH_BASE + 0x25080UL) /* Base Timer 2 PWC registers */ +#define FM3_BT3_PPG_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PPG registers */ +#define FM3_BT3_PWM_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWM registers */ +#define FM3_BT3_RT_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 RT registers */ +#define FM3_BT3_PWC_BASE (FM3_PERIPH_BASE + 0x250C0UL) /* Base Timer 3 PWC registers */ +#define FM3_BT4_PPG_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PPG registers */ +#define FM3_BT4_PWM_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWM registers */ +#define FM3_BT4_RT_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 RT registers */ +#define FM3_BT4_PWC_BASE (FM3_PERIPH_BASE + 0x25200UL) /* Base Timer 4 PWC registers */ +#define FM3_BT5_PPG_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PPG registers */ +#define FM3_BT5_PWM_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWM registers */ +#define FM3_BT5_RT_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 RT registers */ +#define FM3_BT5_PWC_BASE (FM3_PERIPH_BASE + 0x25240UL) /* Base Timer 5 PWC registers */ +#define FM3_BT6_PPG_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PPG registers */ +#define FM3_BT6_PWM_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWM registers */ +#define FM3_BT6_RT_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 RT registers */ +#define FM3_BT6_PWC_BASE (FM3_PERIPH_BASE + 0x25280UL) /* Base Timer 6 PWC registers */ +#define FM3_BT7_PPG_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PPG registers */ +#define FM3_BT7_PWM_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWM registers */ +#define FM3_BT7_RT_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 RT registers */ +#define FM3_BT7_PWC_BASE (FM3_PERIPH_BASE + 0x252C0UL) /* Base Timer 7 PWC registers */ +#define FM3_BTIOSEL03_BASE (FM3_PERIPH_BASE + 0x25100UL) /* Base Timer I/O selector channel 0 - channel 3 registers */ +#define FM3_BTIOSEL47_BASE (FM3_PERIPH_BASE + 0x25300UL) /* Base Timer I/O selector channel 4 - channel 7 registers */ +#define FM3_SBSSR_BASE (FM3_PERIPH_BASE + 0x25FFCUL) /* Software based Simulation Startup (Base Timer) register */ +#define FM3_QPRC0_BASE (FM3_PERIPH_BASE + 0x26000UL) /* Quad position and revolution counter channel 0 registers */ +#define FM3_QPRC1_BASE (FM3_PERIPH_BASE + 0x26040UL) /* Quad position and revolution counter channel 1 registers */ +#define FM3_ADC0_BASE (FM3_PERIPH_BASE + 0x27000UL) /* 12-bit ADC unit 0 registers */ +#define FM3_ADC1_BASE (FM3_PERIPH_BASE + 0x27100UL) /* 12-bit ADC unit 1 registers */ +#define FM3_ADC2_BASE (FM3_PERIPH_BASE + 0x27200UL) /* 12-bit ADC unit 2 registers */ +#define FM3_CRTRIM_BASE (FM3_PERIPH_BASE + 0x2E000UL) /* CR trimming registers */ +#define FM3_EXTI_BASE (FM3_PERIPH_BASE + 0x30000UL) /* External interrupt registers */ +#define FM3_INTREQ_BASE (FM3_PERIPH_BASE + 0x31000UL) /* Interrupt request read registers */ +#define FM3_GPIO_BASE (FM3_PERIPH_BASE + 0x33000UL) /* General purpose I/O registers */ +#define FM3_LVD_BASE (FM3_PERIPH_BASE + 0x35000UL) /* Low voltage detection registers */ +#define FM3_USBCLK_BASE (FM3_PERIPH_BASE + 0x36000UL) /* USB clock registers */ +#define FM3_CANPRES_BASE (FM3_PERIPH_BASE + 0x37000UL) /* CAN prescaler register */ +#define FM3_MFS0_UART_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART asynchronous channel 0 registers */ +#define FM3_MFS0_CSIO_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART synchronous channel 0 registers */ +#define FM3_MFS0_LIN_BASE (FM3_PERIPH_BASE + 0x38000UL) /* UART LIN channel 0 registers */ +#define FM3_MFS0_I2C_BASE (FM3_PERIPH_BASE + 0x38000UL) /* I2C channel 0 registers */ +#define FM3_MFS1_UART_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART asynchronous channel 1 registers */ +#define FM3_MFS1_CSIO_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART synchronous channel 1 registers */ +#define FM3_MFS1_LIN_BASE (FM3_PERIPH_BASE + 0x38100UL) /* UART LIN channel 1 registers */ +#define FM3_MFS1_I2C_BASE (FM3_PERIPH_BASE + 0x38100UL) /* I2C channel 1 registers */ +#define FM3_MFS2_UART_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART asynchronous channel 2 registers */ +#define FM3_MFS2_CSIO_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART synchronous channel 2 registers */ +#define FM3_MFS2_LIN_BASE (FM3_PERIPH_BASE + 0x38200UL) /* UART LIN channel 2 registers */ +#define FM3_MFS2_I2C_BASE (FM3_PERIPH_BASE + 0x38200UL) /* I2C channel 2 registers */ +#define FM3_MFS3_UART_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART asynchronous channel 3 registers */ +#define FM3_MFS3_CSIO_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART synchronous channel 3 registers */ +#define FM3_MFS3_LIN_BASE (FM3_PERIPH_BASE + 0x38300UL) /* UART LIN channel 3 registers */ +#define FM3_MFS3_I2C_BASE (FM3_PERIPH_BASE + 0x38300UL) /* I2C channel 3 registers */ +#define FM3_MFS4_UART_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART asynchronous channel 4 registers */ +#define FM3_MFS4_CSIO_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART synchronous channel 4 registers */ +#define FM3_MFS4_LIN_BASE (FM3_PERIPH_BASE + 0x38400UL) /* UART LIN channel 4 registers */ +#define FM3_MFS4_I2C_BASE (FM3_PERIPH_BASE + 0x38400UL) /* I2C channel 4 registers */ +#define FM3_MFS5_UART_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART asynchronous channel 5 registers */ +#define FM3_MFS5_CSIO_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART synchronous channel 5 registers */ +#define FM3_MFS5_LIN_BASE (FM3_PERIPH_BASE + 0x38500UL) /* UART LIN channel 5 registers */ +#define FM3_MFS5_I2C_BASE (FM3_PERIPH_BASE + 0x38500UL) /* I2C channel 5 registers */ +#define FM3_MFS6_UART_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART asynchronous channel 6 registers */ +#define FM3_MFS6_CSIO_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART synchronous channel 6 registers */ +#define FM3_MFS6_LIN_BASE (FM3_PERIPH_BASE + 0x38600UL) /* UART LIN channel 6 registers */ +#define FM3_MFS6_I2C_BASE (FM3_PERIPH_BASE + 0x38600UL) /* I2C channel 6 registers */ +#define FM3_MFS7_UART_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART asynchronous channel 7 registers */ +#define FM3_MFS7_CSIO_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART synchronous channel 7 registers */ +#define FM3_MFS7_LIN_BASE (FM3_PERIPH_BASE + 0x38700UL) /* UART LIN channel 7 registers */ +#define FM3_MFS7_I2C_BASE (FM3_PERIPH_BASE + 0x38700UL) /* I2C channel 7 registers */ +#define FM3_CRC_BASE (FM3_PERIPH_BASE + 0x39000UL) /* CRC registers */ +#define FM3_WC_BASE (FM3_PERIPH_BASE + 0x3A000UL) /* Watch counter registers */ +#define FM3_EXBUS_BASE (FM3_PERIPH_BASE + 0x3F000UL) /* External bus interface registers */ +#define FM3_USB0_BASE (FM3_PERIPH_BASE + 0x42100UL) /* USB channel 0 registers */ +#define FM3_DMAC_BASE (FM3_PERIPH_BASE + 0x60000UL) /* DMA controller */ +#define FM3_CAN0_BASE (FM3_PERIPH_BASE + 0x62000UL) /* CAN channel 0 registers */ +#define FM3_CAN1_BASE (FM3_PERIPH_BASE + 0x63000UL) /* CAN channel 1 registers */ + +/****************************************************************************** + * Peripheral declaration + ******************************************************************************/ +#define FM3_FLASH_IF ((FM3_FIF_TypeDef *)FM3_FLASH_IF_BASE) +#define FM3_CRG ((FM3_CRG_TypeDef *)FM3_CRG_BASE) +#define FM3_HWWDT ((FM3_HWWDT_TypeDef *)FM3_HWWDT_BASE) +#define FM3_SWWDT ((FM3_SWWDT_TypeDef *)FM3_SWWDT_BASE) +#define FM3_DTIM ((FM3_DTIM_TypeDef *)FM3_DTIM_BASE) +#define FM3_MFT0_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT0_FRT_BASE) +#define FM3_MFT0_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT0_OCU_BASE) +#define FM3_MFT0_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT0_WFG_BASE) +#define FM3_MFT0_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT0_ICU_BASE) +#define FM3_MFT0_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT0_ADCMP_BASE) +#define FM3_MFT1_FRT ((FM3_MFT_FRT_TypeDef *)FM3_MFT1_FRT_BASE) +#define FM3_MFT1_OCU ((FM3_MFT_OCU_TypeDef *)FM3_MFT1_OCU_BASE) +#define FM3_MFT1_WFG ((FM3_MFT_WFG_TypeDef *)FM3_MFT1_WFG_BASE) +#define FM3_MFT1_ICU ((FM3_MFT_ICU_TypeDef *)FM3_MFT1_ICU_BASE) +#define FM3_MFT1_ADCMP ((FM3_MFT_ADCMP_TypeDef *)FM3_MFT1_ADCMP_BASE) +#define FM3_MFT_PPG ((FM3_MFT_PPG_TypeDef *)FM3_MFT_PPG_BASE) +#define FM3_BT0_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT0_PPG_BASE) +#define FM3_BT0_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT0_PWM_BASE) +#define FM3_BT0_RT ((FM3_BT_RT_TypeDef *)FM3_BT0_RT_BASE) +#define FM3_BT0_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT0_PWC_BASE) +#define FM3_BT1_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT1_PPG_BASE) +#define FM3_BT1_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT1_PWM_BASE) +#define FM3_BT1_RT ((FM3_BT_RT_TypeDef *)FM3_BT1_RT_BASE) +#define FM3_BT1_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT1_PWC_BASE) +#define FM3_BT2_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT2_PPG_BASE) +#define FM3_BT2_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT2_PWM_BASE) +#define FM3_BT2_RT ((FM3_BT_RT_TypeDef *)FM3_BT2_RT_BASE) +#define FM3_BT2_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT2_PWC_BASE) +#define FM3_BT3_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT3_PPG_BASE) +#define FM3_BT3_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT3_PWM_BASE) +#define FM3_BT3_RT ((FM3_BT_RT_TypeDef *)FM3_BT3_RT_BASE) +#define FM3_BT3_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT3_PWC_BASE) +#define FM3_BT4_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT4_PPG_BASE) +#define FM3_BT4_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT4_PWM_BASE) +#define FM3_BT4_RT ((FM3_BT_RT_TypeDef *)FM3_BT4_RT_BASE) +#define FM3_BT4_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT4_PWC_BASE) +#define FM3_BT5_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT5_PPG_BASE) +#define FM3_BT5_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT5_PWM_BASE) +#define FM3_BT5_RT ((FM3_BT_RT_TypeDef *)FM3_BT5_RT_BASE) +#define FM3_BT5_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT5_PWC_BASE) +#define FM3_BT6_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT6_PPG_BASE) +#define FM3_BT6_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT6_PWM_BASE) +#define FM3_BT6_RT ((FM3_BT_RT_TypeDef *)FM3_BT6_RT_BASE) +#define FM3_BT6_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT6_PWC_BASE) +#define FM3_BT7_PPG ((FM3_BT_PPG_TypeDef *)FM3_BT7_PPG_BASE) +#define FM3_BT7_PWM ((FM3_BT_PWM_TypeDef *)FM3_BT7_PWM_BASE) +#define FM3_BT7_RT ((FM3_BT_RT_TypeDef *)FM3_BT7_RT_BASE) +#define FM3_BT7_PWC ((FM3_BT_PWC_TypeDef *)FM3_BT7_PWC_BASE) +#define FM3_BTIOSEL03 ((FM3_BTIOSEL03_TypeDef *)FM3_BTIOSEL03_BASE) +#define FM3_BTIOSEL47 ((FM3_BTIOSEL47_TypeDef *)FM3_BTIOSEL47_BASE) +#define FM3_SBSSR ((FM3_SBSSR_TypeDef *)FM3_SBSSR_BASE) +#define FM3_QPRC0 ((FM3_QPRC_TypeDef *)FM3_QPRC0_BASE) +#define FM3_QPRC1 ((FM3_QPRC_TypeDef *)FM3_QPRC1_BASE) +#define FM3_ADC0 ((FM3_ADC_TypeDef *)FM3_ADC0_BASE) +#define FM3_ADC1 ((FM3_ADC_TypeDef *)FM3_ADC1_BASE) +#define FM3_ADC2 ((FM3_ADC_TypeDef *)FM3_ADC2_BASE) +#define FM3_CRTRIM ((FM3_CRTRIM_TypeDef *)FM3_CRTRIM_BASE) +#define FM3_EXTI ((FM3_EXTI_TypeDef *)FM3_EXTI_BASE) +#define FM3_INTREQ ((FM3_INTREQ_TypeDef *)FM3_INTREQ_BASE) +#define FM3_GPIO ((FM3_GPIO_TypeDef *)FM3_GPIO_BASE) +#define FM3_LVD ((FM3_LVD_TypeDef *)FM3_LVD_BASE) +#define FM3_USBCLK ((FM3_USBCLK_TypeDef *)FM3_USBCLK_BASE) +#define FM3_CANPRES ((FM3_CANPRE_TypeDef *)FM3_CANPRES_BASE) +#define FM3_MFS0_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS0_UART_BASE) +#define FM3_MFS0_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS0_CSIO_BASE) +#define FM3_MFS0_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS0_LIN_BASE) +#define FM3_MFS0_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS0_I2C_BASE) +#define FM3_MFS1_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS1_UART_BASE) +#define FM3_MFS1_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS1_CSIO_BASE) +#define FM3_MFS1_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS1_LIN_BASE) +#define FM3_MFS1_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS1_I2C_BASE) +#define FM3_MFS2_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS2_UART_BASE) +#define FM3_MFS2_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS2_CSIO_BASE) +#define FM3_MFS2_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS2_LIN_BASE) +#define FM3_MFS2_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS2_I2C_BASE) +#define FM3_MFS3_UART ((FM3_MFS03_UART_TypeDef *)FM3_MFS3_UART_BASE) +#define FM3_MFS3_CSIO ((FM3_MFS03_CSIO_TypeDef *)FM3_MFS3_CSIO_BASE) +#define FM3_MFS3_LIN ((FM3_MFS03_LIN_TypeDef *)FM3_MFS3_LIN_BASE) +#define FM3_MFS3_I2C ((FM3_MFS03_I2C_TypeDef *)FM3_MFS3_I2C_BASE) +#define FM3_MFS4_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS4_UART_BASE) +#define FM3_MFS4_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS4_CSIO_BASE) +#define FM3_MFS4_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS4_LIN_BASE) +#define FM3_MFS4_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS4_I2C_BASE) +#define FM3_MFS5_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS5_UART_BASE) +#define FM3_MFS5_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS5_CSIO_BASE) +#define FM3_MFS5_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS5_LIN_BASE) +#define FM3_MFS5_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS5_I2C_BASE) +#define FM3_MFS6_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS6_UART_BASE) +#define FM3_MFS6_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS6_CSIO_BASE) +#define FM3_MFS6_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS6_LIN_BASE) +#define FM3_MFS6_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS6_I2C_BASE) +#define FM3_MFS7_UART ((FM3_MFS47_UART_TypeDef *)FM3_MFS7_UART_BASE) +#define FM3_MFS7_CSIO ((FM3_MFS47_CSIO_TypeDef *)FM3_MFS7_CSIO_BASE) +#define FM3_MFS7_LIN ((FM3_MFS47_LIN_TypeDef *)FM3_MFS7_LIN_BASE) +#define FM3_MFS7_I2C ((FM3_MFS47_I2C_TypeDef *)FM3_MFS7_I2C_BASE) +#define FM3_CRC ((FM3_CRC_TypeDef *)FM3_CRC_BASE) +#define FM3_WC ((FM3_WC_TypeDef *)FM3_WC_BASE) +#define FM3_EXBUS ((FM3_EXBUS_TypeDef *)FM3_EXBUS_BASE) +#define FM3_USB0 ((FM3_USB_TypeDef *)FM3_USB0_BASE) +#define FM3_DMAC ((FM3_DMAC_TypeDef *)FM3_DMAC_BASE) +#define FM3_CAN0 ((FM3_CAN_TypeDef *)FM3_CAN0_BASE) +#define FM3_CAN1 ((FM3_CAN_TypeDef *)FM3_CAN1_BASE) + +/****************************************************************************** + * Peripheral Bit Band Alias declaration + ******************************************************************************/ + +/* Flash interface registers */ +#define bFM3_FLASH_IF_FASZR_ASZ0 *((volatile unsigned int*)(0x42000000UL)) +#define bFM3_FLASH_IF_FASZR_ASZ1 *((volatile unsigned int*)(0x42000004UL)) +#define bFM3_FLASH_IF_FRWTR_RWT0 *((volatile unsigned int*)(0x42000080UL)) +#define bFM3_FLASH_IF_FRWTR_RWT1 *((volatile unsigned int*)(0x42000084UL)) +#define bFM3_FLASH_IF_FSTR_RDY *((volatile unsigned int*)(0x42000100UL)) +#define bFM3_FLASH_IF_FSTR_HNG *((volatile unsigned int*)(0x42000104UL)) +#define bFM3_FLASH_IF_FSYNDN_SD0 *((volatile unsigned int*)(0x42000200UL)) +#define bFM3_FLASH_IF_FSYNDN_SD1 *((volatile unsigned int*)(0x42000204UL)) +#define bFM3_FLASH_IF_FSYNDN_SD2 *((volatile unsigned int*)(0x42000208UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM0 *((volatile unsigned int*)(0x42002000UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM1 *((volatile unsigned int*)(0x42002004UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM2 *((volatile unsigned int*)(0x42002008UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM3 *((volatile unsigned int*)(0x4200200CUL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM4 *((volatile unsigned int*)(0x42002010UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM5 *((volatile unsigned int*)(0x42002014UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM6 *((volatile unsigned int*)(0x42002018UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM7 *((volatile unsigned int*)(0x4200201CUL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM8 *((volatile unsigned int*)(0x42002020UL)) +#define bFM3_FLASH_IF_CRTRMM_TRMM9 *((volatile unsigned int*)(0x42002024UL)) + +/* Clock and reset registers */ +#define bFM3_CRG_SCM_CTL_MOSCE *((volatile unsigned int*)(0x42200004UL)) +#define bFM3_CRG_SCM_CTL_SOSCE *((volatile unsigned int*)(0x4220000CUL)) +#define bFM3_CRG_SCM_CTL_PLLE *((volatile unsigned int*)(0x42200010UL)) +#define bFM3_CRG_SCM_CTL_RCS0 *((volatile unsigned int*)(0x42200014UL)) +#define bFM3_CRG_SCM_CTL_RCS1 *((volatile unsigned int*)(0x42200018UL)) +#define bFM3_CRG_SCM_CTL_RCS2 *((volatile unsigned int*)(0x4220001CUL)) +#define bFM3_CRG_SCM_STR_MORDY *((volatile unsigned int*)(0x42200084UL)) +#define bFM3_CRG_SCM_STR_SORDY *((volatile unsigned int*)(0x4220008CUL)) +#define bFM3_CRG_SCM_STR_PLRDY *((volatile unsigned int*)(0x42200090UL)) +#define bFM3_CRG_SCM_STR_RCM0 *((volatile unsigned int*)(0x42200094UL)) +#define bFM3_CRG_SCM_STR_RCM1 *((volatile unsigned int*)(0x42200098UL)) +#define bFM3_CRG_SCM_STR_RCM2 *((volatile unsigned int*)(0x4220009CUL)) +#define bFM3_CRG_RST_STR_PONR *((volatile unsigned int*)(0x42200180UL)) +#define bFM3_CRG_RST_STR_INITX *((volatile unsigned int*)(0x42200184UL)) +#define bFM3_CRG_RST_STR_SWDT *((volatile unsigned int*)(0x42200190UL)) +#define bFM3_CRG_RST_STR_HWDT *((volatile unsigned int*)(0x42200194UL)) +#define bFM3_CRG_RST_STR_CSVR *((volatile unsigned int*)(0x42200198UL)) +#define bFM3_CRG_RST_STR_FCSR *((volatile unsigned int*)(0x4220019CUL)) +#define bFM3_CRG_RST_STR_SRST *((volatile unsigned int*)(0x422001A0UL)) +#define bFM3_CRG_BSC_PSR_BSR0 *((volatile unsigned int*)(0x42200200UL)) +#define bFM3_CRG_BSC_PSR_BSR1 *((volatile unsigned int*)(0x42200204UL)) +#define bFM3_CRG_BSC_PSR_BSR2 *((volatile unsigned int*)(0x42200208UL)) +#define bFM3_CRG_APBC0_PSR_APBC00 *((volatile unsigned int*)(0x42200280UL)) +#define bFM3_CRG_APBC0_PSR_APBC01 *((volatile unsigned int*)(0x42200284UL)) +#define bFM3_CRG_APBC1_PSR_APBC10 *((volatile unsigned int*)(0x42200300UL)) +#define bFM3_CRG_APBC1_PSR_APBC11 *((volatile unsigned int*)(0x42200304UL)) +#define bFM3_CRG_APBC1_PSR_APBC1RST *((volatile unsigned int*)(0x42200310UL)) +#define bFM3_CRG_APBC1_PSR_APBC1EN *((volatile unsigned int*)(0x4220031CUL)) +#define bFM3_CRG_APBC2_PSR_APBC20 *((volatile unsigned int*)(0x42200380UL)) +#define bFM3_CRG_APBC2_PSR_APBC21 *((volatile unsigned int*)(0x42200384UL)) +#define bFM3_CRG_APBC2_PSR_APBC2RST *((volatile unsigned int*)(0x42200390UL)) +#define bFM3_CRG_APBC2_PSR_APBC2EN *((volatile unsigned int*)(0x4220039CUL)) +#define bFM3_CRG_SWC_PSR_SWDS0 *((volatile unsigned int*)(0x42200400UL)) +#define bFM3_CRG_SWC_PSR_SWDS1 *((volatile unsigned int*)(0x42200404UL)) +#define bFM3_CRG_SWC_PSR_TESTB *((volatile unsigned int*)(0x4220041CUL)) +#define bFM3_CRG_TTC_PSR_TTC *((volatile unsigned int*)(0x42200500UL)) +#define bFM3_CRG_CSW_TMR_MOWT0 *((volatile unsigned int*)(0x42200600UL)) +#define bFM3_CRG_CSW_TMR_MOWT1 *((volatile unsigned int*)(0x42200604UL)) +#define bFM3_CRG_CSW_TMR_MOWT2 *((volatile unsigned int*)(0x42200608UL)) +#define bFM3_CRG_CSW_TMR_MOWT3 *((volatile unsigned int*)(0x4220060CUL)) +#define bFM3_CRG_CSW_TMR_SOWT0 *((volatile unsigned int*)(0x42200610UL)) +#define bFM3_CRG_CSW_TMR_SOWT1 *((volatile unsigned int*)(0x42200614UL)) +#define bFM3_CRG_CSW_TMR_SOWT2 *((volatile unsigned int*)(0x42200618UL)) +#define bFM3_CRG_PSW_TMR_POWT0 *((volatile unsigned int*)(0x42200680UL)) +#define bFM3_CRG_PSW_TMR_POWT1 *((volatile unsigned int*)(0x42200684UL)) +#define bFM3_CRG_PSW_TMR_POWT2 *((volatile unsigned int*)(0x42200688UL)) +#define bFM3_CRG_PSW_TMR_PINC *((volatile unsigned int*)(0x42200690UL)) +#define bFM3_CRG_PLL_CTL1_PLLM0 *((volatile unsigned int*)(0x42200700UL)) +#define bFM3_CRG_PLL_CTL1_PLLM1 *((volatile unsigned int*)(0x42200704UL)) +#define bFM3_CRG_PLL_CTL1_PLLM2 *((volatile unsigned int*)(0x42200708UL)) +#define bFM3_CRG_PLL_CTL1_PLLM3 *((volatile unsigned int*)(0x4220070CUL)) +#define bFM3_CRG_PLL_CTL1_PLLK0 *((volatile unsigned int*)(0x42200710UL)) +#define bFM3_CRG_PLL_CTL1_PLLK1 *((volatile unsigned int*)(0x42200714UL)) +#define bFM3_CRG_PLL_CTL1_PLLK2 *((volatile unsigned int*)(0x42200718UL)) +#define bFM3_CRG_PLL_CTL1_PLLK3 *((volatile unsigned int*)(0x4220071CUL)) +#define bFM3_CRG_PLL_CTL2_PLLN0 *((volatile unsigned int*)(0x42200780UL)) +#define bFM3_CRG_PLL_CTL2_PLLN1 *((volatile unsigned int*)(0x42200784UL)) +#define bFM3_CRG_PLL_CTL2_PLLN2 *((volatile unsigned int*)(0x42200788UL)) +#define bFM3_CRG_PLL_CTL2_PLLN3 *((volatile unsigned int*)(0x4220078CUL)) +#define bFM3_CRG_PLL_CTL2_PLLN4 *((volatile unsigned int*)(0x42200790UL)) +#define bFM3_CRG_CSV_CTL_MCSVE *((volatile unsigned int*)(0x42200800UL)) +#define bFM3_CRG_CSV_CTL_SCSVE *((volatile unsigned int*)(0x42200804UL)) +#define bFM3_CRG_CSV_CTL_FCSDE *((volatile unsigned int*)(0x42200820UL)) +#define bFM3_CRG_CSV_CTL_FCSRE *((volatile unsigned int*)(0x42200824UL)) +#define bFM3_CRG_CSV_CTL_FCD0 *((volatile unsigned int*)(0x42200830UL)) +#define bFM3_CRG_CSV_CTL_FCD1 *((volatile unsigned int*)(0x42200834UL)) +#define bFM3_CRG_CSV_CTL_FCD2 *((volatile unsigned int*)(0x42200838UL)) +#define bFM3_CRG_CSV_STR_MCMF *((volatile unsigned int*)(0x42200880UL)) +#define bFM3_CRG_CSV_STR_SCMF *((volatile unsigned int*)(0x42200884UL)) +#define bFM3_CRG_DBWDT_CTL_DPSWBE *((volatile unsigned int*)(0x42200A94UL)) +#define bFM3_CRG_DBWDT_CTL_DPHWBE *((volatile unsigned int*)(0x42200A9CUL)) +#define bFM3_CRG_INT_ENR_MCSE *((volatile unsigned int*)(0x42200C00UL)) +#define bFM3_CRG_INT_ENR_SCSE *((volatile unsigned int*)(0x42200C04UL)) +#define bFM3_CRG_INT_ENR_PCSE *((volatile unsigned int*)(0x42200C08UL)) +#define bFM3_CRG_INT_ENR_FCSE *((volatile unsigned int*)(0x42200C14UL)) +#define bFM3_CRG_INT_STR_MCSI *((volatile unsigned int*)(0x42200C80UL)) +#define bFM3_CRG_INT_STR_SCSI *((volatile unsigned int*)(0x42200C84UL)) +#define bFM3_CRG_INT_STR_PCSI *((volatile unsigned int*)(0x42200C88UL)) +#define bFM3_CRG_INT_STR_FCSI *((volatile unsigned int*)(0x42200C94UL)) +#define bFM3_CRG_INT_CLR_MCSC *((volatile unsigned int*)(0x42200D00UL)) +#define bFM3_CRG_INT_CLR_SCSC *((volatile unsigned int*)(0x42200D04UL)) +#define bFM3_CRG_INT_CLR_PCSC *((volatile unsigned int*)(0x42200D08UL)) +#define bFM3_CRG_INT_CLR_FCSC *((volatile unsigned int*)(0x42200D14UL)) + +/* Hardware watchdog registers */ +#define bFM3_HWWDT_WDG_CTL_INTEN *((volatile unsigned int*)(0x42220100UL)) +#define bFM3_HWWDT_WDG_CTL_RESEN *((volatile unsigned int*)(0x42220104UL)) +#define bFM3_HWWDT_WDG_RIS_RIS *((volatile unsigned int*)(0x42220200UL)) + +/* Software watchdog registers */ +#define bFM3_SWWDT_WDOGCONTROL_INTEN *((volatile unsigned int*)(0x42240100UL)) +#define bFM3_SWWDT_WDOGCONTROL_RESEN *((volatile unsigned int*)(0x42240104UL)) +#define bFM3_SWWDT_WDOGRIS_RIS *((volatile unsigned int*)(0x42240200UL)) + +/* Dual timer 1/2 registers */ +#define bFM3_DTIM_TIMER1CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0100UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0104UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0108UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A010CUL)) +#define bFM3_DTIM_TIMER1CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0114UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0118UL)) +#define bFM3_DTIM_TIMER1CONTROL_TIMEREN *((volatile unsigned int*)(0x422A011CUL)) +#define bFM3_DTIM_TIMER1RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0200UL)) +#define bFM3_DTIM_TIMER1MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0280UL)) +#define bFM3_DTIM_TIMER2CONTROL_ONESHOT *((volatile unsigned int*)(0x422A0500UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERSIZE *((volatile unsigned int*)(0x422A0504UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE0 *((volatile unsigned int*)(0x422A0508UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERPRE1 *((volatile unsigned int*)(0x422A050CUL)) +#define bFM3_DTIM_TIMER2CONTROL_INTENABLE *((volatile unsigned int*)(0x422A0514UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMERMODE *((volatile unsigned int*)(0x422A0518UL)) +#define bFM3_DTIM_TIMER2CONTROL_TIMEREN *((volatile unsigned int*)(0x422A051CUL)) +#define bFM3_DTIM_TIMER2RIS_TIMERXRIS *((volatile unsigned int*)(0x422A0600UL)) +#define bFM3_DTIM_TIMER2MIS_TIMERXRIS *((volatile unsigned int*)(0x422A0680UL)) + +/* Multifunction Timer unit 0 Free Running Timer registers */ +#define bFM3_MFT0_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42400600UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42400604UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42400608UL)) +#define bFM3_MFT0_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4240060CUL)) +#define bFM3_MFT0_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42400610UL)) +#define bFM3_MFT0_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42400614UL)) +#define bFM3_MFT0_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42400618UL)) +#define bFM3_MFT0_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4240061CUL)) +#define bFM3_MFT0_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42400620UL)) +#define bFM3_MFT0_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42400624UL)) +#define bFM3_MFT0_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42400634UL)) +#define bFM3_MFT0_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42400638UL)) +#define bFM3_MFT0_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4240063CUL)) +#define bFM3_MFT0_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42400680UL)) +#define bFM3_MFT0_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42400684UL)) +#define bFM3_MFT0_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42400688UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42400800UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42400804UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42400808UL)) +#define bFM3_MFT0_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4240080CUL)) +#define bFM3_MFT0_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42400810UL)) +#define bFM3_MFT0_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42400814UL)) +#define bFM3_MFT0_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42400818UL)) +#define bFM3_MFT0_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4240081CUL)) +#define bFM3_MFT0_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42400820UL)) +#define bFM3_MFT0_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42400824UL)) +#define bFM3_MFT0_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42400834UL)) +#define bFM3_MFT0_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42400838UL)) +#define bFM3_MFT0_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4240083CUL)) +#define bFM3_MFT0_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42400880UL)) +#define bFM3_MFT0_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42400884UL)) +#define bFM3_MFT0_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42400888UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42400A00UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42400A04UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42400A08UL)) +#define bFM3_MFT0_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42400A0CUL)) +#define bFM3_MFT0_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42400A10UL)) +#define bFM3_MFT0_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42400A14UL)) +#define bFM3_MFT0_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42400A18UL)) +#define bFM3_MFT0_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42400A1CUL)) +#define bFM3_MFT0_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42400A20UL)) +#define bFM3_MFT0_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42400A24UL)) +#define bFM3_MFT0_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42400A34UL)) +#define bFM3_MFT0_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42400A38UL)) +#define bFM3_MFT0_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42400A3CUL)) +#define bFM3_MFT0_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42400A80UL)) +#define bFM3_MFT0_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42400A84UL)) +#define bFM3_MFT0_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42400A88UL)) + +/* Multifunction Timer unit 0 Output Compare Unit registers */ +#define bFM3_MFT0_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42400300UL)) +#define bFM3_MFT0_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42400304UL)) +#define bFM3_MFT0_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42400308UL)) +#define bFM3_MFT0_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4240030CUL)) +#define bFM3_MFT0_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42400310UL)) +#define bFM3_MFT0_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42400314UL)) +#define bFM3_MFT0_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42400318UL)) +#define bFM3_MFT0_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4240031CUL)) +#define bFM3_MFT0_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42400320UL)) +#define bFM3_MFT0_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42400324UL)) +#define bFM3_MFT0_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42400330UL)) +#define bFM3_MFT0_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42400334UL)) +#define bFM3_MFT0_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42400338UL)) +#define bFM3_MFT0_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42400380UL)) +#define bFM3_MFT0_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42400384UL)) +#define bFM3_MFT0_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42400388UL)) +#define bFM3_MFT0_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4240038CUL)) +#define bFM3_MFT0_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42400390UL)) +#define bFM3_MFT0_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42400394UL)) +#define bFM3_MFT0_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42400398UL)) +#define bFM3_MFT0_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4240039CUL)) +#define bFM3_MFT0_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424003A0UL)) +#define bFM3_MFT0_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424003A4UL)) +#define bFM3_MFT0_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424003B0UL)) +#define bFM3_MFT0_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424003B4UL)) +#define bFM3_MFT0_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424003B8UL)) +#define bFM3_MFT0_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42400400UL)) +#define bFM3_MFT0_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42400404UL)) +#define bFM3_MFT0_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42400408UL)) +#define bFM3_MFT0_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4240040CUL)) +#define bFM3_MFT0_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42400410UL)) +#define bFM3_MFT0_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42400414UL)) +#define bFM3_MFT0_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42400418UL)) +#define bFM3_MFT0_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4240041CUL)) +#define bFM3_MFT0_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42400420UL)) +#define bFM3_MFT0_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42400424UL)) +#define bFM3_MFT0_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42400430UL)) +#define bFM3_MFT0_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42400434UL)) +#define bFM3_MFT0_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42400438UL)) +#define bFM3_MFT0_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424004A0UL)) +#define bFM3_MFT0_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424004A4UL)) +#define bFM3_MFT0_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424004A8UL)) +#define bFM3_MFT0_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424004ACUL)) +#define bFM3_MFT0_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424004B0UL)) +#define bFM3_MFT0_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424004B4UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42400B00UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42400B04UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42400B08UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42400B0CUL)) +#define bFM3_MFT0_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42400B10UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42400B14UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42400B18UL)) +#define bFM3_MFT0_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42400B1CUL)) +#define bFM3_MFT0_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42400B20UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42400B24UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42400B28UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42400B2CUL)) +#define bFM3_MFT0_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42400B30UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42400B34UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42400B38UL)) +#define bFM3_MFT0_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42400B3CUL)) +#define bFM3_MFT0_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42400B80UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42400B84UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42400B88UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42400B8CUL)) +#define bFM3_MFT0_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42400B90UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42400B94UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42400B98UL)) +#define bFM3_MFT0_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42400B9CUL)) + +/* Multifunction Timer unit 0 Waveform Generator and Noise Canceler registers */ +#define bFM3_MFT0_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42401180UL)) +#define bFM3_MFT0_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42401184UL)) +#define bFM3_MFT0_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42401188UL)) +#define bFM3_MFT0_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4240118CUL)) +#define bFM3_MFT0_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42401190UL)) +#define bFM3_MFT0_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42401194UL)) +#define bFM3_MFT0_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42401198UL)) +#define bFM3_MFT0_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4240119CUL)) +#define bFM3_MFT0_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424011A0UL)) +#define bFM3_MFT0_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424011A4UL)) +#define bFM3_MFT0_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424011A8UL)) +#define bFM3_MFT0_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424011ACUL)) +#define bFM3_MFT0_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424011B0UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42401200UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42401204UL)) +#define bFM3_MFT0_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42401208UL)) +#define bFM3_MFT0_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4240120CUL)) +#define bFM3_MFT0_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42401210UL)) +#define bFM3_MFT0_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42401214UL)) +#define bFM3_MFT0_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42401218UL)) +#define bFM3_MFT0_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4240121CUL)) +#define bFM3_MFT0_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42401220UL)) +#define bFM3_MFT0_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42401224UL)) +#define bFM3_MFT0_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42401228UL)) +#define bFM3_MFT0_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4240122CUL)) +#define bFM3_MFT0_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42401230UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42401280UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42401284UL)) +#define bFM3_MFT0_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42401288UL)) +#define bFM3_MFT0_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4240128CUL)) +#define bFM3_MFT0_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42401290UL)) +#define bFM3_MFT0_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42401294UL)) +#define bFM3_MFT0_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42401298UL)) +#define bFM3_MFT0_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4240129CUL)) +#define bFM3_MFT0_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424012A0UL)) +#define bFM3_MFT0_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424012A4UL)) +#define bFM3_MFT0_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424012A8UL)) +#define bFM3_MFT0_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424012ACUL)) +#define bFM3_MFT0_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424012B0UL)) +#define bFM3_MFT0_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42401300UL)) +#define bFM3_MFT0_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42401304UL)) +#define bFM3_MFT0_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42401310UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42401314UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42401318UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4240131CUL)) +#define bFM3_MFT0_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42401320UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42401324UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42401328UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4240132CUL)) +#define bFM3_MFT0_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42401330UL)) +#define bFM3_MFT0_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42401334UL)) +#define bFM3_MFT0_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42401338UL)) +#define bFM3_MFT0_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4240133CUL)) +#define bFM3_MFT0_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42401380UL)) +#define bFM3_MFT0_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42401384UL)) +#define bFM3_MFT0_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42401388UL)) +#define bFM3_MFT0_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4240138CUL)) +#define bFM3_MFT0_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42401390UL)) + +/* Multifunction Timer unit 0 Input Capture Unit registers */ +#define bFM3_MFT0_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42400C00UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42400C04UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42400C08UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42400C0CUL)) +#define bFM3_MFT0_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42400C10UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42400C14UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42400C18UL)) +#define bFM3_MFT0_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42400C1CUL)) +#define bFM3_MFT0_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42400C20UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42400C24UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42400C28UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42400C2CUL)) +#define bFM3_MFT0_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42400C30UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42400C34UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42400C38UL)) +#define bFM3_MFT0_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42400C3CUL)) +#define bFM3_MFT0_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42400F00UL)) +#define bFM3_MFT0_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42400F04UL)) +#define bFM3_MFT0_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42400F08UL)) +#define bFM3_MFT0_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42400F0CUL)) +#define bFM3_MFT0_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42400F10UL)) +#define bFM3_MFT0_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42400F14UL)) +#define bFM3_MFT0_ICU_ICSA10_IPC0 *((volatile unsigned int*)(0x42400F18UL)) +#define bFM3_MFT0_ICU_ICSA10_IPC1 *((volatile unsigned int*)(0x42400F1CUL)) +#define bFM3_MFT0_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42400F20UL)) +#define bFM3_MFT0_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42400F24UL)) +#define bFM3_MFT0_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42400F80UL)) +#define bFM3_MFT0_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42400F84UL)) +#define bFM3_MFT0_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42400F88UL)) +#define bFM3_MFT0_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42400F8CUL)) +#define bFM3_MFT0_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42400F90UL)) +#define bFM3_MFT0_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42400F94UL)) +#define bFM3_MFT0_ICU_ICSA32_IPC2 *((volatile unsigned int*)(0x42400F98UL)) +#define bFM3_MFT0_ICU_ICSA32_IPC3 *((volatile unsigned int*)(0x42400F9CUL)) +#define bFM3_MFT0_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42400FA0UL)) +#define bFM3_MFT0_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42400FA4UL)) + +/* Multifunction Timer unit 0 ADC Start Compare Unit registers */ +#define bFM3_MFT0_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42401700UL)) +#define bFM3_MFT0_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42401704UL)) +#define bFM3_MFT0_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42401708UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42401710UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42401714UL)) +#define bFM3_MFT0_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42401718UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42401780UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42401784UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42401788UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4240178CUL)) +#define bFM3_MFT0_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42401790UL)) +#define bFM3_MFT0_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42401794UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424017A0UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424017A4UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424017A8UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424017ACUL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424017B0UL)) +#define bFM3_MFT0_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424017B4UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42401800UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42401804UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42401808UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4240180CUL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42401810UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42401814UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42401820UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42401824UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42401828UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4240182CUL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42401830UL)) +#define bFM3_MFT0_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42401834UL)) + +/* Multifunction Timer unit 1 Free Running Timer registers */ +#define bFM3_MFT1_FRT_TCSA0_CLK0 *((volatile unsigned int*)(0x42420600UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK1 *((volatile unsigned int*)(0x42420604UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK2 *((volatile unsigned int*)(0x42420608UL)) +#define bFM3_MFT1_FRT_TCSA0_CLK3 *((volatile unsigned int*)(0x4242060CUL)) +#define bFM3_MFT1_FRT_TCSA0_SCLR *((volatile unsigned int*)(0x42420610UL)) +#define bFM3_MFT1_FRT_TCSA0_MODE *((volatile unsigned int*)(0x42420614UL)) +#define bFM3_MFT1_FRT_TCSA0_STOP *((volatile unsigned int*)(0x42420618UL)) +#define bFM3_MFT1_FRT_TCSA0_BFE *((volatile unsigned int*)(0x4242061CUL)) +#define bFM3_MFT1_FRT_TCSA0_ICRE *((volatile unsigned int*)(0x42420620UL)) +#define bFM3_MFT1_FRT_TCSA0_ICLR *((volatile unsigned int*)(0x42420624UL)) +#define bFM3_MFT1_FRT_TCSA0_IRQZE *((volatile unsigned int*)(0x42420634UL)) +#define bFM3_MFT1_FRT_TCSA0_IRQZF *((volatile unsigned int*)(0x42420638UL)) +#define bFM3_MFT1_FRT_TCSA0_ECKE *((volatile unsigned int*)(0x4242063CUL)) +#define bFM3_MFT1_FRT_TCSB0_AD0E *((volatile unsigned int*)(0x42420680UL)) +#define bFM3_MFT1_FRT_TCSB0_AD1E *((volatile unsigned int*)(0x42420684UL)) +#define bFM3_MFT1_FRT_TCSB0_AD2E *((volatile unsigned int*)(0x42420688UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK0 *((volatile unsigned int*)(0x42420800UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK1 *((volatile unsigned int*)(0x42420804UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK2 *((volatile unsigned int*)(0x42420808UL)) +#define bFM3_MFT1_FRT_TCSA1_CLK3 *((volatile unsigned int*)(0x4242080CUL)) +#define bFM3_MFT1_FRT_TCSA1_SCLR *((volatile unsigned int*)(0x42420810UL)) +#define bFM3_MFT1_FRT_TCSA1_MODE *((volatile unsigned int*)(0x42420814UL)) +#define bFM3_MFT1_FRT_TCSA1_STOP *((volatile unsigned int*)(0x42420818UL)) +#define bFM3_MFT1_FRT_TCSA1_BFE *((volatile unsigned int*)(0x4242081CUL)) +#define bFM3_MFT1_FRT_TCSA1_ICRE *((volatile unsigned int*)(0x42420820UL)) +#define bFM3_MFT1_FRT_TCSA1_ICLR *((volatile unsigned int*)(0x42420824UL)) +#define bFM3_MFT1_FRT_TCSA1_IRQZE *((volatile unsigned int*)(0x42420834UL)) +#define bFM3_MFT1_FRT_TCSA1_IRQZF *((volatile unsigned int*)(0x42420838UL)) +#define bFM3_MFT1_FRT_TCSA1_ECKE *((volatile unsigned int*)(0x4242083CUL)) +#define bFM3_MFT1_FRT_TCSB1_AD0E *((volatile unsigned int*)(0x42420880UL)) +#define bFM3_MFT1_FRT_TCSB1_AD1E *((volatile unsigned int*)(0x42420884UL)) +#define bFM3_MFT1_FRT_TCSB1_AD2E *((volatile unsigned int*)(0x42420888UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK0 *((volatile unsigned int*)(0x42420A00UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK1 *((volatile unsigned int*)(0x42420A04UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK2 *((volatile unsigned int*)(0x42420A08UL)) +#define bFM3_MFT1_FRT_TCSA2_CLK3 *((volatile unsigned int*)(0x42420A0CUL)) +#define bFM3_MFT1_FRT_TCSA2_SCLR *((volatile unsigned int*)(0x42420A10UL)) +#define bFM3_MFT1_FRT_TCSA2_MODE *((volatile unsigned int*)(0x42420A14UL)) +#define bFM3_MFT1_FRT_TCSA2_STOP *((volatile unsigned int*)(0x42420A18UL)) +#define bFM3_MFT1_FRT_TCSA2_BFE *((volatile unsigned int*)(0x42420A1CUL)) +#define bFM3_MFT1_FRT_TCSA2_ICRE *((volatile unsigned int*)(0x42420A20UL)) +#define bFM3_MFT1_FRT_TCSA2_ICLR *((volatile unsigned int*)(0x42420A24UL)) +#define bFM3_MFT1_FRT_TCSA2_IRQZE *((volatile unsigned int*)(0x42420A34UL)) +#define bFM3_MFT1_FRT_TCSA2_IRQZF *((volatile unsigned int*)(0x42420A38UL)) +#define bFM3_MFT1_FRT_TCSA2_ECKE *((volatile unsigned int*)(0x42420A3CUL)) +#define bFM3_MFT1_FRT_TCSB2_AD0E *((volatile unsigned int*)(0x42420A80UL)) +#define bFM3_MFT1_FRT_TCSB2_AD1E *((volatile unsigned int*)(0x42420A84UL)) +#define bFM3_MFT1_FRT_TCSB2_AD2E *((volatile unsigned int*)(0x42420A88UL)) + +/* Multifunction Timer unit 1 Output Compare Unit registers */ +#define bFM3_MFT1_OCU_OCSA10_CST0 *((volatile unsigned int*)(0x42420300UL)) +#define bFM3_MFT1_OCU_OCSA10_CST1 *((volatile unsigned int*)(0x42420304UL)) +#define bFM3_MFT1_OCU_OCSA10_BDIS0 *((volatile unsigned int*)(0x42420308UL)) +#define bFM3_MFT1_OCU_OCSA10_BDIS1 *((volatile unsigned int*)(0x4242030CUL)) +#define bFM3_MFT1_OCU_OCSA10_IOE0 *((volatile unsigned int*)(0x42420310UL)) +#define bFM3_MFT1_OCU_OCSA10_IOE1 *((volatile unsigned int*)(0x42420314UL)) +#define bFM3_MFT1_OCU_OCSA10_IOP0 *((volatile unsigned int*)(0x42420318UL)) +#define bFM3_MFT1_OCU_OCSA10_IOP1 *((volatile unsigned int*)(0x4242031CUL)) +#define bFM3_MFT1_OCU_OCSB10_OTD0 *((volatile unsigned int*)(0x42420320UL)) +#define bFM3_MFT1_OCU_OCSB10_OTD1 *((volatile unsigned int*)(0x42420324UL)) +#define bFM3_MFT1_OCU_OCSB10_CMOD *((volatile unsigned int*)(0x42420330UL)) +#define bFM3_MFT1_OCU_OCSB10_BTS0 *((volatile unsigned int*)(0x42420334UL)) +#define bFM3_MFT1_OCU_OCSB10_BTS1 *((volatile unsigned int*)(0x42420338UL)) +#define bFM3_MFT1_OCU_OCSA32_CST2 *((volatile unsigned int*)(0x42420380UL)) +#define bFM3_MFT1_OCU_OCSA32_CST3 *((volatile unsigned int*)(0x42420384UL)) +#define bFM3_MFT1_OCU_OCSA32_BDIS2 *((volatile unsigned int*)(0x42420388UL)) +#define bFM3_MFT1_OCU_OCSA32_BDIS3 *((volatile unsigned int*)(0x4242038CUL)) +#define bFM3_MFT1_OCU_OCSA32_IOE2 *((volatile unsigned int*)(0x42420390UL)) +#define bFM3_MFT1_OCU_OCSA32_IOE3 *((volatile unsigned int*)(0x42420394UL)) +#define bFM3_MFT1_OCU_OCSA32_IOP2 *((volatile unsigned int*)(0x42420398UL)) +#define bFM3_MFT1_OCU_OCSA32_IOP3 *((volatile unsigned int*)(0x4242039CUL)) +#define bFM3_MFT1_OCU_OCSB32_OTD2 *((volatile unsigned int*)(0x424203A0UL)) +#define bFM3_MFT1_OCU_OCSB32_OTD3 *((volatile unsigned int*)(0x424203A4UL)) +#define bFM3_MFT1_OCU_OCSB32_CMOD *((volatile unsigned int*)(0x424203B0UL)) +#define bFM3_MFT1_OCU_OCSB32_BTS2 *((volatile unsigned int*)(0x424203B4UL)) +#define bFM3_MFT1_OCU_OCSB32_BTS3 *((volatile unsigned int*)(0x424203B8UL)) +#define bFM3_MFT1_OCU_OCSA54_CST4 *((volatile unsigned int*)(0x42420400UL)) +#define bFM3_MFT1_OCU_OCSA54_CST5 *((volatile unsigned int*)(0x42420404UL)) +#define bFM3_MFT1_OCU_OCSA54_BDIS4 *((volatile unsigned int*)(0x42420408UL)) +#define bFM3_MFT1_OCU_OCSA54_BDIS5 *((volatile unsigned int*)(0x4242040CUL)) +#define bFM3_MFT1_OCU_OCSA54_IOE4 *((volatile unsigned int*)(0x42420410UL)) +#define bFM3_MFT1_OCU_OCSA54_IOE5 *((volatile unsigned int*)(0x42420414UL)) +#define bFM3_MFT1_OCU_OCSA54_IOP4 *((volatile unsigned int*)(0x42420418UL)) +#define bFM3_MFT1_OCU_OCSA54_IOP5 *((volatile unsigned int*)(0x4242041CUL)) +#define bFM3_MFT1_OCU_OCSB54_OTD4 *((volatile unsigned int*)(0x42420420UL)) +#define bFM3_MFT1_OCU_OCSB54_OTD5 *((volatile unsigned int*)(0x42420424UL)) +#define bFM3_MFT1_OCU_OCSB54_CMOD *((volatile unsigned int*)(0x42420430UL)) +#define bFM3_MFT1_OCU_OCSB54_BTS4 *((volatile unsigned int*)(0x42420434UL)) +#define bFM3_MFT1_OCU_OCSB54_BTS5 *((volatile unsigned int*)(0x42420438UL)) +#define bFM3_MFT1_OCU_OCSC_MOD0 *((volatile unsigned int*)(0x424204A0UL)) +#define bFM3_MFT1_OCU_OCSC_MOD1 *((volatile unsigned int*)(0x424204A4UL)) +#define bFM3_MFT1_OCU_OCSC_MOD2 *((volatile unsigned int*)(0x424204A8UL)) +#define bFM3_MFT1_OCU_OCSC_MOD3 *((volatile unsigned int*)(0x424204ACUL)) +#define bFM3_MFT1_OCU_OCSC_MOD4 *((volatile unsigned int*)(0x424204B0UL)) +#define bFM3_MFT1_OCU_OCSC_MOD5 *((volatile unsigned int*)(0x424204B4UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO00 *((volatile unsigned int*)(0x42420B00UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO01 *((volatile unsigned int*)(0x42420B04UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO02 *((volatile unsigned int*)(0x42420B08UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO03 *((volatile unsigned int*)(0x42420B0CUL)) +#define bFM3_MFT1_OCU_OCFS10_FSO10 *((volatile unsigned int*)(0x42420B10UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO11 *((volatile unsigned int*)(0x42420B14UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO12 *((volatile unsigned int*)(0x42420B18UL)) +#define bFM3_MFT1_OCU_OCFS10_FSO13 *((volatile unsigned int*)(0x42420B1CUL)) +#define bFM3_MFT1_OCU_OCFS32_FSO20 *((volatile unsigned int*)(0x42420B20UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO21 *((volatile unsigned int*)(0x42420B24UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO22 *((volatile unsigned int*)(0x42420B28UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO23 *((volatile unsigned int*)(0x42420B2CUL)) +#define bFM3_MFT1_OCU_OCFS32_FSO30 *((volatile unsigned int*)(0x42420B30UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO31 *((volatile unsigned int*)(0x42420B34UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO32 *((volatile unsigned int*)(0x42420B38UL)) +#define bFM3_MFT1_OCU_OCFS32_FSO33 *((volatile unsigned int*)(0x42420B3CUL)) +#define bFM3_MFT1_OCU_OCFS54_FSO40 *((volatile unsigned int*)(0x42420B80UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO41 *((volatile unsigned int*)(0x42420B84UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO42 *((volatile unsigned int*)(0x42420B88UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO43 *((volatile unsigned int*)(0x42420B8CUL)) +#define bFM3_MFT1_OCU_OCFS54_FSO50 *((volatile unsigned int*)(0x42420B90UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO51 *((volatile unsigned int*)(0x42420B94UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO52 *((volatile unsigned int*)(0x42420B98UL)) +#define bFM3_MFT1_OCU_OCFS54_FSO53 *((volatile unsigned int*)(0x42420B9CUL)) + +/* Multifunction Timer unit 1 Waveform Generator and Noise Canceler registers */ +#define bFM3_MFT1_WFG_WFSA10_DCK0 *((volatile unsigned int*)(0x42421180UL)) +#define bFM3_MFT1_WFG_WFSA10_DCK1 *((volatile unsigned int*)(0x42421184UL)) +#define bFM3_MFT1_WFG_WFSA10_DCK2 *((volatile unsigned int*)(0x42421188UL)) +#define bFM3_MFT1_WFG_WFSA10_TMD0 *((volatile unsigned int*)(0x4242118CUL)) +#define bFM3_MFT1_WFG_WFSA10_TMD1 *((volatile unsigned int*)(0x42421190UL)) +#define bFM3_MFT1_WFG_WFSA10_TMD2 *((volatile unsigned int*)(0x42421194UL)) +#define bFM3_MFT1_WFG_WFSA10_GTEN0 *((volatile unsigned int*)(0x42421198UL)) +#define bFM3_MFT1_WFG_WFSA10_GTEN1 *((volatile unsigned int*)(0x4242119CUL)) +#define bFM3_MFT1_WFG_WFSA10_PSEL0 *((volatile unsigned int*)(0x424211A0UL)) +#define bFM3_MFT1_WFG_WFSA10_PSEL1 *((volatile unsigned int*)(0x424211A4UL)) +#define bFM3_MFT1_WFG_WFSA10_PGEN0 *((volatile unsigned int*)(0x424211A8UL)) +#define bFM3_MFT1_WFG_WFSA10_PGEN1 *((volatile unsigned int*)(0x424211ACUL)) +#define bFM3_MFT1_WFG_WFSA10_DMOD *((volatile unsigned int*)(0x424211B0UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK0 *((volatile unsigned int*)(0x42421200UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK1 *((volatile unsigned int*)(0x42421204UL)) +#define bFM3_MFT1_WFG_WFSA32_DCK2 *((volatile unsigned int*)(0x42421208UL)) +#define bFM3_MFT1_WFG_WFSA32_TMD0 *((volatile unsigned int*)(0x4242120CUL)) +#define bFM3_MFT1_WFG_WFSA32_TMD1 *((volatile unsigned int*)(0x42421210UL)) +#define bFM3_MFT1_WFG_WFSA32_TMD2 *((volatile unsigned int*)(0x42421214UL)) +#define bFM3_MFT1_WFG_WFSA32_GTEN0 *((volatile unsigned int*)(0x42421218UL)) +#define bFM3_MFT1_WFG_WFSA32_GTEN1 *((volatile unsigned int*)(0x4242121CUL)) +#define bFM3_MFT1_WFG_WFSA32_PSEL0 *((volatile unsigned int*)(0x42421220UL)) +#define bFM3_MFT1_WFG_WFSA32_PSEL1 *((volatile unsigned int*)(0x42421224UL)) +#define bFM3_MFT1_WFG_WFSA32_PGEN0 *((volatile unsigned int*)(0x42421228UL)) +#define bFM3_MFT1_WFG_WFSA32_PGEN1 *((volatile unsigned int*)(0x4242122CUL)) +#define bFM3_MFT1_WFG_WFSA32_DMOD *((volatile unsigned int*)(0x42421230UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK0 *((volatile unsigned int*)(0x42421280UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK1 *((volatile unsigned int*)(0x42421284UL)) +#define bFM3_MFT1_WFG_WFSA54_DCK2 *((volatile unsigned int*)(0x42421288UL)) +#define bFM3_MFT1_WFG_WFSA54_TMD0 *((volatile unsigned int*)(0x4242128CUL)) +#define bFM3_MFT1_WFG_WFSA54_TMD1 *((volatile unsigned int*)(0x42421290UL)) +#define bFM3_MFT1_WFG_WFSA54_TMD2 *((volatile unsigned int*)(0x42421294UL)) +#define bFM3_MFT1_WFG_WFSA54_GTEN0 *((volatile unsigned int*)(0x42421298UL)) +#define bFM3_MFT1_WFG_WFSA54_GTEN1 *((volatile unsigned int*)(0x4242129CUL)) +#define bFM3_MFT1_WFG_WFSA54_PSEL0 *((volatile unsigned int*)(0x424212A0UL)) +#define bFM3_MFT1_WFG_WFSA54_PSEL1 *((volatile unsigned int*)(0x424212A4UL)) +#define bFM3_MFT1_WFG_WFSA54_PGEN0 *((volatile unsigned int*)(0x424212A8UL)) +#define bFM3_MFT1_WFG_WFSA54_PGEN1 *((volatile unsigned int*)(0x424212ACUL)) +#define bFM3_MFT1_WFG_WFSA54_DMOD *((volatile unsigned int*)(0x424212B0UL)) +#define bFM3_MFT1_WFG_WFIR_DTIF *((volatile unsigned int*)(0x42421300UL)) +#define bFM3_MFT1_WFG_WFIR_DTIC *((volatile unsigned int*)(0x42421304UL)) +#define bFM3_MFT1_WFG_WFIR_TMIF10 *((volatile unsigned int*)(0x42421310UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC10 *((volatile unsigned int*)(0x42421314UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE10 *((volatile unsigned int*)(0x42421318UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS10 *((volatile unsigned int*)(0x4242131CUL)) +#define bFM3_MFT1_WFG_WFIR_TMIF32 *((volatile unsigned int*)(0x42421320UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC32 *((volatile unsigned int*)(0x42421324UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE32 *((volatile unsigned int*)(0x42421328UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS32 *((volatile unsigned int*)(0x4242132CUL)) +#define bFM3_MFT1_WFG_WFIR_TMIF54 *((volatile unsigned int*)(0x42421330UL)) +#define bFM3_MFT1_WFG_WFIR_TMIC54 *((volatile unsigned int*)(0x42421334UL)) +#define bFM3_MFT1_WFG_WFIR_TMIE54 *((volatile unsigned int*)(0x42421338UL)) +#define bFM3_MFT1_WFG_WFIR_TMIS54 *((volatile unsigned int*)(0x4242133CUL)) +#define bFM3_MFT1_WFG_NZCL_DTIE *((volatile unsigned int*)(0x42421380UL)) +#define bFM3_MFT1_WFG_NZCL_NWS0 *((volatile unsigned int*)(0x42421384UL)) +#define bFM3_MFT1_WFG_NZCL_NWS1 *((volatile unsigned int*)(0x42421388UL)) +#define bFM3_MFT1_WFG_NZCL_NWS2 *((volatile unsigned int*)(0x4242138CUL)) +#define bFM3_MFT1_WFG_NZCL_SDTI *((volatile unsigned int*)(0x42421390UL)) + +/* Multifunction Timer unit 1 Input Capture Unit registers */ +#define bFM3_MFT1_ICU_ICFS10_FSI00 *((volatile unsigned int*)(0x42420C00UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI01 *((volatile unsigned int*)(0x42420C04UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI02 *((volatile unsigned int*)(0x42420C08UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI03 *((volatile unsigned int*)(0x42420C0CUL)) +#define bFM3_MFT1_ICU_ICFS10_FSI10 *((volatile unsigned int*)(0x42420C10UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI11 *((volatile unsigned int*)(0x42420C14UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI12 *((volatile unsigned int*)(0x42420C18UL)) +#define bFM3_MFT1_ICU_ICFS10_FSI13 *((volatile unsigned int*)(0x42420C1CUL)) +#define bFM3_MFT1_ICU_ICFS32_FSI20 *((volatile unsigned int*)(0x42420C20UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI21 *((volatile unsigned int*)(0x42420C24UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI22 *((volatile unsigned int*)(0x42420C28UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI23 *((volatile unsigned int*)(0x42420C2CUL)) +#define bFM3_MFT1_ICU_ICFS32_FSI30 *((volatile unsigned int*)(0x42420C30UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI31 *((volatile unsigned int*)(0x42420C34UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI32 *((volatile unsigned int*)(0x42420C38UL)) +#define bFM3_MFT1_ICU_ICFS32_FSI33 *((volatile unsigned int*)(0x42420C3CUL)) +#define bFM3_MFT1_ICU_ICSA10_EG00 *((volatile unsigned int*)(0x42420F00UL)) +#define bFM3_MFT1_ICU_ICSA10_EG01 *((volatile unsigned int*)(0x42420F04UL)) +#define bFM3_MFT1_ICU_ICSA10_EG10 *((volatile unsigned int*)(0x42420F08UL)) +#define bFM3_MFT1_ICU_ICSA10_EG11 *((volatile unsigned int*)(0x42420F0CUL)) +#define bFM3_MFT1_ICU_ICSA10_ICE0 *((volatile unsigned int*)(0x42420F10UL)) +#define bFM3_MFT1_ICU_ICSA10_ICE1 *((volatile unsigned int*)(0x42420F14UL)) +#define bFM3_MFT1_ICU_ICSA10_IPC0 *((volatile unsigned int*)(0x42420F18UL)) +#define bFM3_MFT1_ICU_ICSA10_IPC1 *((volatile unsigned int*)(0x42420F1CUL)) +#define bFM3_MFT1_ICU_ICSB10_IEI0 *((volatile unsigned int*)(0x42420F20UL)) +#define bFM3_MFT1_ICU_ICSB10_IEI1 *((volatile unsigned int*)(0x42420F24UL)) +#define bFM3_MFT1_ICU_ICSA32_EG20 *((volatile unsigned int*)(0x42420F80UL)) +#define bFM3_MFT1_ICU_ICSA32_EG21 *((volatile unsigned int*)(0x42420F84UL)) +#define bFM3_MFT1_ICU_ICSA32_EG30 *((volatile unsigned int*)(0x42420F88UL)) +#define bFM3_MFT1_ICU_ICSA32_EG31 *((volatile unsigned int*)(0x42420F8CUL)) +#define bFM3_MFT1_ICU_ICSA32_ICE2 *((volatile unsigned int*)(0x42420F90UL)) +#define bFM3_MFT1_ICU_ICSA32_ICE3 *((volatile unsigned int*)(0x42420F94UL)) +#define bFM3_MFT1_ICU_ICSA32_IPC2 *((volatile unsigned int*)(0x42420F98UL)) +#define bFM3_MFT1_ICU_ICSA32_IPC3 *((volatile unsigned int*)(0x42420F9CUL)) +#define bFM3_MFT1_ICU_ICSB32_IEI2 *((volatile unsigned int*)(0x42420FA0UL)) +#define bFM3_MFT1_ICU_ICSB32_IEI3 *((volatile unsigned int*)(0x42420FA4UL)) + +/* Multifunction Timer unit 1 ADC Start Compare Unit registers */ +#define bFM3_MFT1_ADCMP_ACSB_BDIS0 *((volatile unsigned int*)(0x42421700UL)) +#define bFM3_MFT1_ADCMP_ACSB_BDIS1 *((volatile unsigned int*)(0x42421704UL)) +#define bFM3_MFT1_ADCMP_ACSB_BDIS2 *((volatile unsigned int*)(0x42421708UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS0 *((volatile unsigned int*)(0x42421710UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS1 *((volatile unsigned int*)(0x42421714UL)) +#define bFM3_MFT1_ADCMP_ACSB_BTS2 *((volatile unsigned int*)(0x42421718UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE00 *((volatile unsigned int*)(0x42421780UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE01 *((volatile unsigned int*)(0x42421784UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE10 *((volatile unsigned int*)(0x42421788UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE11 *((volatile unsigned int*)(0x4242178CUL)) +#define bFM3_MFT1_ADCMP_ACSA_CE20 *((volatile unsigned int*)(0x42421790UL)) +#define bFM3_MFT1_ADCMP_ACSA_CE21 *((volatile unsigned int*)(0x42421794UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL00 *((volatile unsigned int*)(0x424217A0UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL01 *((volatile unsigned int*)(0x424217A4UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL10 *((volatile unsigned int*)(0x424217A8UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL11 *((volatile unsigned int*)(0x424217ACUL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL20 *((volatile unsigned int*)(0x424217B0UL)) +#define bFM3_MFT1_ADCMP_ACSA_SEL21 *((volatile unsigned int*)(0x424217B4UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0S0 *((volatile unsigned int*)(0x42421800UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0S1 *((volatile unsigned int*)(0x42421804UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1S0 *((volatile unsigned int*)(0x42421808UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1S1 *((volatile unsigned int*)(0x4242180CUL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2S0 *((volatile unsigned int*)(0x42421810UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2S1 *((volatile unsigned int*)(0x42421814UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0P0 *((volatile unsigned int*)(0x42421820UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD0P1 *((volatile unsigned int*)(0x42421824UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1P0 *((volatile unsigned int*)(0x42421828UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD1P1 *((volatile unsigned int*)(0x4242182CUL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2P0 *((volatile unsigned int*)(0x42421830UL)) +#define bFM3_MFT1_ADCMP_ATSA_AD2P1 *((volatile unsigned int*)(0x42421834UL)) + +/* Multifunction Timer PPG registers */ +#define bFM3_MFT_PPG_TTCR0_STR0 *((volatile unsigned int*)(0x42480020UL)) +#define bFM3_MFT_PPG_TTCR0_MONI0 *((volatile unsigned int*)(0x42480024UL)) +#define bFM3_MFT_PPG_TTCR0_CS00 *((volatile unsigned int*)(0x42480028UL)) +#define bFM3_MFT_PPG_TTCR0_CS01 *((volatile unsigned int*)(0x4248002CUL)) +#define bFM3_MFT_PPG_TTCR0_TRG0O *((volatile unsigned int*)(0x42480030UL)) +#define bFM3_MFT_PPG_TTCR0_TRG2O *((volatile unsigned int*)(0x42480034UL)) +#define bFM3_MFT_PPG_TTCR0_TRG4O *((volatile unsigned int*)(0x42480038UL)) +#define bFM3_MFT_PPG_TTCR0_TRG6O *((volatile unsigned int*)(0x4248003CUL)) +#define bFM3_MFT_PPG_TTCR1_STR1 *((volatile unsigned int*)(0x42480420UL)) +#define bFM3_MFT_PPG_TTCR1_MONI1 *((volatile unsigned int*)(0x42480424UL)) +#define bFM3_MFT_PPG_TTCR1_CS10 *((volatile unsigned int*)(0x42480428UL)) +#define bFM3_MFT_PPG_TTCR1_CS11 *((volatile unsigned int*)(0x4248042CUL)) +#define bFM3_MFT_PPG_TTCR1_TRG1O *((volatile unsigned int*)(0x42480430UL)) +#define bFM3_MFT_PPG_TTCR1_TRG3O *((volatile unsigned int*)(0x42480434UL)) +#define bFM3_MFT_PPG_TTCR1_TRG5O *((volatile unsigned int*)(0x42480438UL)) +#define bFM3_MFT_PPG_TTCR1_TRG7O *((volatile unsigned int*)(0x4248043CUL)) +#define bFM3_MFT_PPG_TRG_PEN00 *((volatile unsigned int*)(0x42482000UL)) +#define bFM3_MFT_PPG_TRG_PEN01 *((volatile unsigned int*)(0x42482004UL)) +#define bFM3_MFT_PPG_TRG_PEN02 *((volatile unsigned int*)(0x42482008UL)) +#define bFM3_MFT_PPG_TRG_PEN03 *((volatile unsigned int*)(0x4248200CUL)) +#define bFM3_MFT_PPG_TRG_PEN04 *((volatile unsigned int*)(0x42482010UL)) +#define bFM3_MFT_PPG_TRG_PEN05 *((volatile unsigned int*)(0x42482014UL)) +#define bFM3_MFT_PPG_TRG_PEN06 *((volatile unsigned int*)(0x42482018UL)) +#define bFM3_MFT_PPG_TRG_PEN07 *((volatile unsigned int*)(0x4248201CUL)) +#define bFM3_MFT_PPG_TRG_PEN08 *((volatile unsigned int*)(0x42482020UL)) +#define bFM3_MFT_PPG_TRG_PEN09 *((volatile unsigned int*)(0x42482024UL)) +#define bFM3_MFT_PPG_TRG_PEN10 *((volatile unsigned int*)(0x42482028UL)) +#define bFM3_MFT_PPG_TRG_PEN11 *((volatile unsigned int*)(0x4248202CUL)) +#define bFM3_MFT_PPG_TRG_PEN12 *((volatile unsigned int*)(0x42482030UL)) +#define bFM3_MFT_PPG_TRG_PEN13 *((volatile unsigned int*)(0x42482034UL)) +#define bFM3_MFT_PPG_TRG_PEN14 *((volatile unsigned int*)(0x42482038UL)) +#define bFM3_MFT_PPG_TRG_PEN15 *((volatile unsigned int*)(0x4248203CUL)) +#define bFM3_MFT_PPG_REVC_REV00 *((volatile unsigned int*)(0x42482080UL)) +#define bFM3_MFT_PPG_REVC_REV01 *((volatile unsigned int*)(0x42482084UL)) +#define bFM3_MFT_PPG_REVC_REV02 *((volatile unsigned int*)(0x42482088UL)) +#define bFM3_MFT_PPG_REVC_REV03 *((volatile unsigned int*)(0x4248208CUL)) +#define bFM3_MFT_PPG_REVC_REV04 *((volatile unsigned int*)(0x42482090UL)) +#define bFM3_MFT_PPG_REVC_REV05 *((volatile unsigned int*)(0x42482094UL)) +#define bFM3_MFT_PPG_REVC_REV06 *((volatile unsigned int*)(0x42482098UL)) +#define bFM3_MFT_PPG_REVC_REV07 *((volatile unsigned int*)(0x4248209CUL)) +#define bFM3_MFT_PPG_REVC_REV08 *((volatile unsigned int*)(0x424820A0UL)) +#define bFM3_MFT_PPG_REVC_REV09 *((volatile unsigned int*)(0x424820A4UL)) +#define bFM3_MFT_PPG_REVC_REV10 *((volatile unsigned int*)(0x424820A8UL)) +#define bFM3_MFT_PPG_REVC_REV11 *((volatile unsigned int*)(0x424820ACUL)) +#define bFM3_MFT_PPG_REVC_REV12 *((volatile unsigned int*)(0x424820B0UL)) +#define bFM3_MFT_PPG_REVC_REV13 *((volatile unsigned int*)(0x424820B4UL)) +#define bFM3_MFT_PPG_REVC_REV14 *((volatile unsigned int*)(0x424820B8UL)) +#define bFM3_MFT_PPG_REVC_REV15 *((volatile unsigned int*)(0x424820BCUL)) +#define bFM3_MFT_PPG_PPGC1_TTRG *((volatile unsigned int*)(0x42484000UL)) +#define bFM3_MFT_PPG_PPGC1_MD0 *((volatile unsigned int*)(0x42484004UL)) +#define bFM3_MFT_PPG_PPGC1_MD1 *((volatile unsigned int*)(0x42484008UL)) +#define bFM3_MFT_PPG_PPGC1_PCS0 *((volatile unsigned int*)(0x4248400CUL)) +#define bFM3_MFT_PPG_PPGC1_PCS1 *((volatile unsigned int*)(0x42484010UL)) +#define bFM3_MFT_PPG_PPGC1_INTM *((volatile unsigned int*)(0x42484014UL)) +#define bFM3_MFT_PPG_PPGC1_PUF *((volatile unsigned int*)(0x42484018UL)) +#define bFM3_MFT_PPG_PPGC1_PIE *((volatile unsigned int*)(0x4248401CUL)) +#define bFM3_MFT_PPG_PPGC0_TTRG *((volatile unsigned int*)(0x42484020UL)) +#define bFM3_MFT_PPG_PPGC0_MD0 *((volatile unsigned int*)(0x42484024UL)) +#define bFM3_MFT_PPG_PPGC0_MD1 *((volatile unsigned int*)(0x42484028UL)) +#define bFM3_MFT_PPG_PPGC0_PCS0 *((volatile unsigned int*)(0x4248402CUL)) +#define bFM3_MFT_PPG_PPGC0_PCS1 *((volatile unsigned int*)(0x42484030UL)) +#define bFM3_MFT_PPG_PPGC0_INTM *((volatile unsigned int*)(0x42484034UL)) +#define bFM3_MFT_PPG_PPGC0_PUF *((volatile unsigned int*)(0x42484038UL)) +#define bFM3_MFT_PPG_PPGC0_PIE *((volatile unsigned int*)(0x4248403CUL)) +#define bFM3_MFT_PPG_PPGC3_TTRG *((volatile unsigned int*)(0x42484080UL)) +#define bFM3_MFT_PPG_PPGC3_MD0 *((volatile unsigned int*)(0x42484084UL)) +#define bFM3_MFT_PPG_PPGC3_MD1 *((volatile unsigned int*)(0x42484088UL)) +#define bFM3_MFT_PPG_PPGC3_PCS0 *((volatile unsigned int*)(0x4248408CUL)) +#define bFM3_MFT_PPG_PPGC3_PCS1 *((volatile unsigned int*)(0x42484090UL)) +#define bFM3_MFT_PPG_PPGC3_INTM *((volatile unsigned int*)(0x42484094UL)) +#define bFM3_MFT_PPG_PPGC3_PUF *((volatile unsigned int*)(0x42484098UL)) +#define bFM3_MFT_PPG_PPGC3_PIE *((volatile unsigned int*)(0x4248409CUL)) +#define bFM3_MFT_PPG_PPGC2_TTRG *((volatile unsigned int*)(0x424840A0UL)) +#define bFM3_MFT_PPG_PPGC2_MD0 *((volatile unsigned int*)(0x424840A4UL)) +#define bFM3_MFT_PPG_PPGC2_MD1 *((volatile unsigned int*)(0x424840A8UL)) +#define bFM3_MFT_PPG_PPGC2_PCS0 *((volatile unsigned int*)(0x424840ACUL)) +#define bFM3_MFT_PPG_PPGC2_PCS1 *((volatile unsigned int*)(0x424840B0UL)) +#define bFM3_MFT_PPG_PPGC2_INTM *((volatile unsigned int*)(0x424840B4UL)) +#define bFM3_MFT_PPG_PPGC2_PUF *((volatile unsigned int*)(0x424840B8UL)) +#define bFM3_MFT_PPG_PPGC2_PIE *((volatile unsigned int*)(0x424840BCUL)) +#define bFM3_MFT_PPG_GATEC0_EDGE0 *((volatile unsigned int*)(0x42484300UL)) +#define bFM3_MFT_PPG_GATEC0_STRG0 *((volatile unsigned int*)(0x42484304UL)) +#define bFM3_MFT_PPG_GATEC0_EDGE2 *((volatile unsigned int*)(0x42484310UL)) +#define bFM3_MFT_PPG_GATEC0_STRG2 *((volatile unsigned int*)(0x42484314UL)) +#define bFM3_MFT_PPG_PPGC5_TTRG *((volatile unsigned int*)(0x42484800UL)) +#define bFM3_MFT_PPG_PPGC5_MD0 *((volatile unsigned int*)(0x42484804UL)) +#define bFM3_MFT_PPG_PPGC5_MD1 *((volatile unsigned int*)(0x42484808UL)) +#define bFM3_MFT_PPG_PPGC5_PCS0 *((volatile unsigned int*)(0x4248480CUL)) +#define bFM3_MFT_PPG_PPGC5_PCS1 *((volatile unsigned int*)(0x42484810UL)) +#define bFM3_MFT_PPG_PPGC5_INTM *((volatile unsigned int*)(0x42484814UL)) +#define bFM3_MFT_PPG_PPGC5_PUF *((volatile unsigned int*)(0x42484818UL)) +#define bFM3_MFT_PPG_PPGC5_PIE *((volatile unsigned int*)(0x4248481CUL)) +#define bFM3_MFT_PPG_PPGC4_TTRG *((volatile unsigned int*)(0x42484820UL)) +#define bFM3_MFT_PPG_PPGC4_MD0 *((volatile unsigned int*)(0x42484824UL)) +#define bFM3_MFT_PPG_PPGC4_MD1 *((volatile unsigned int*)(0x42484828UL)) +#define bFM3_MFT_PPG_PPGC4_PCS0 *((volatile unsigned int*)(0x4248482CUL)) +#define bFM3_MFT_PPG_PPGC4_PCS1 *((volatile unsigned int*)(0x42484830UL)) +#define bFM3_MFT_PPG_PPGC4_INTM *((volatile unsigned int*)(0x42484834UL)) +#define bFM3_MFT_PPG_PPGC4_PUF *((volatile unsigned int*)(0x42484838UL)) +#define bFM3_MFT_PPG_PPGC4_PIE *((volatile unsigned int*)(0x4248483CUL)) +#define bFM3_MFT_PPG_PPGC7_TTRG *((volatile unsigned int*)(0x42484880UL)) +#define bFM3_MFT_PPG_PPGC7_MD0 *((volatile unsigned int*)(0x42484884UL)) +#define bFM3_MFT_PPG_PPGC7_MD1 *((volatile unsigned int*)(0x42484888UL)) +#define bFM3_MFT_PPG_PPGC7_PCS0 *((volatile unsigned int*)(0x4248488CUL)) +#define bFM3_MFT_PPG_PPGC7_PCS1 *((volatile unsigned int*)(0x42484890UL)) +#define bFM3_MFT_PPG_PPGC7_INTM *((volatile unsigned int*)(0x42484894UL)) +#define bFM3_MFT_PPG_PPGC7_PUF *((volatile unsigned int*)(0x42484898UL)) +#define bFM3_MFT_PPG_PPGC7_PIE *((volatile unsigned int*)(0x4248489CUL)) +#define bFM3_MFT_PPG_PPGC6_TTRG *((volatile unsigned int*)(0x424848A0UL)) +#define bFM3_MFT_PPG_PPGC6_MD0 *((volatile unsigned int*)(0x424848A4UL)) +#define bFM3_MFT_PPG_PPGC6_MD1 *((volatile unsigned int*)(0x424848A8UL)) +#define bFM3_MFT_PPG_PPGC6_PCS0 *((volatile unsigned int*)(0x424848ACUL)) +#define bFM3_MFT_PPG_PPGC6_PCS1 *((volatile unsigned int*)(0x424848B0UL)) +#define bFM3_MFT_PPG_PPGC6_INTM *((volatile unsigned int*)(0x424848B4UL)) +#define bFM3_MFT_PPG_PPGC6_PUF *((volatile unsigned int*)(0x424848B8UL)) +#define bFM3_MFT_PPG_PPGC6_PIE *((volatile unsigned int*)(0x424848BCUL)) +#define bFM3_MFT_PPG_GATEC4_EDGE4 *((volatile unsigned int*)(0x42484B00UL)) +#define bFM3_MFT_PPG_GATEC4_STRG4 *((volatile unsigned int*)(0x42484B04UL)) +#define bFM3_MFT_PPG_GATEC4_EDGE6 *((volatile unsigned int*)(0x42484B10UL)) +#define bFM3_MFT_PPG_GATEC4_STRG6 *((volatile unsigned int*)(0x42484B14UL)) +#define bFM3_MFT_PPG_PPGC9_TTRG *((volatile unsigned int*)(0x42485000UL)) +#define bFM3_MFT_PPG_PPGC9_MD0 *((volatile unsigned int*)(0x42485004UL)) +#define bFM3_MFT_PPG_PPGC9_MD1 *((volatile unsigned int*)(0x42485008UL)) +#define bFM3_MFT_PPG_PPGC9_PCS0 *((volatile unsigned int*)(0x4248500CUL)) +#define bFM3_MFT_PPG_PPGC9_PCS1 *((volatile unsigned int*)(0x42485010UL)) +#define bFM3_MFT_PPG_PPGC9_INTM *((volatile unsigned int*)(0x42485014UL)) +#define bFM3_MFT_PPG_PPGC9_PUF *((volatile unsigned int*)(0x42485018UL)) +#define bFM3_MFT_PPG_PPGC9_PIE *((volatile unsigned int*)(0x4248501CUL)) +#define bFM3_MFT_PPG_PPGC8_TTRG *((volatile unsigned int*)(0x42485020UL)) +#define bFM3_MFT_PPG_PPGC8_MD0 *((volatile unsigned int*)(0x42485024UL)) +#define bFM3_MFT_PPG_PPGC8_MD1 *((volatile unsigned int*)(0x42485028UL)) +#define bFM3_MFT_PPG_PPGC8_PCS0 *((volatile unsigned int*)(0x4248502CUL)) +#define bFM3_MFT_PPG_PPGC8_PCS1 *((volatile unsigned int*)(0x42485030UL)) +#define bFM3_MFT_PPG_PPGC8_INTM *((volatile unsigned int*)(0x42485034UL)) +#define bFM3_MFT_PPG_PPGC8_PUF *((volatile unsigned int*)(0x42485038UL)) +#define bFM3_MFT_PPG_PPGC8_PIE *((volatile unsigned int*)(0x4248503CUL)) +#define bFM3_MFT_PPG_PPGC11_TTRG *((volatile unsigned int*)(0x42485080UL)) +#define bFM3_MFT_PPG_PPGC11_MD0 *((volatile unsigned int*)(0x42485084UL)) +#define bFM3_MFT_PPG_PPGC11_MD1 *((volatile unsigned int*)(0x42485088UL)) +#define bFM3_MFT_PPG_PPGC11_PCS0 *((volatile unsigned int*)(0x4248508CUL)) +#define bFM3_MFT_PPG_PPGC11_PCS1 *((volatile unsigned int*)(0x42485090UL)) +#define bFM3_MFT_PPG_PPGC11_INTM *((volatile unsigned int*)(0x42485094UL)) +#define bFM3_MFT_PPG_PPGC11_PUF *((volatile unsigned int*)(0x42485098UL)) +#define bFM3_MFT_PPG_PPGC11_PIE *((volatile unsigned int*)(0x4248509CUL)) +#define bFM3_MFT_PPG_PPGC10_TTRG *((volatile unsigned int*)(0x424850A0UL)) +#define bFM3_MFT_PPG_PPGC10_MD0 *((volatile unsigned int*)(0x424850A4UL)) +#define bFM3_MFT_PPG_PPGC10_MD1 *((volatile unsigned int*)(0x424850A8UL)) +#define bFM3_MFT_PPG_PPGC10_PCS0 *((volatile unsigned int*)(0x424850ACUL)) +#define bFM3_MFT_PPG_PPGC10_PCS1 *((volatile unsigned int*)(0x424850B0UL)) +#define bFM3_MFT_PPG_PPGC10_INTM *((volatile unsigned int*)(0x424850B4UL)) +#define bFM3_MFT_PPG_PPGC10_PUF *((volatile unsigned int*)(0x424850B8UL)) +#define bFM3_MFT_PPG_PPGC10_PIE *((volatile unsigned int*)(0x424850BCUL)) +#define bFM3_MFT_PPG_GATEC8_EDGE8 *((volatile unsigned int*)(0x42485300UL)) +#define bFM3_MFT_PPG_GATEC8_STRG8 *((volatile unsigned int*)(0x42485304UL)) +#define bFM3_MFT_PPG_GATEC8_EDGE10 *((volatile unsigned int*)(0x42485310UL)) +#define bFM3_MFT_PPG_GATEC8_STRG10 *((volatile unsigned int*)(0x42485314UL)) +#define bFM3_MFT_PPG_PPGC13_TTRG *((volatile unsigned int*)(0x42485800UL)) +#define bFM3_MFT_PPG_PPGC13_MD0 *((volatile unsigned int*)(0x42485804UL)) +#define bFM3_MFT_PPG_PPGC13_MD1 *((volatile unsigned int*)(0x42485808UL)) +#define bFM3_MFT_PPG_PPGC13_PCS0 *((volatile unsigned int*)(0x4248580CUL)) +#define bFM3_MFT_PPG_PPGC13_PCS1 *((volatile unsigned int*)(0x42485810UL)) +#define bFM3_MFT_PPG_PPGC13_INTM *((volatile unsigned int*)(0x42485814UL)) +#define bFM3_MFT_PPG_PPGC13_PUF *((volatile unsigned int*)(0x42485818UL)) +#define bFM3_MFT_PPG_PPGC13_PIE *((volatile unsigned int*)(0x4248581CUL)) +#define bFM3_MFT_PPG_PPGC12_TTRG *((volatile unsigned int*)(0x42485820UL)) +#define bFM3_MFT_PPG_PPGC12_MD0 *((volatile unsigned int*)(0x42485824UL)) +#define bFM3_MFT_PPG_PPGC12_MD1 *((volatile unsigned int*)(0x42485828UL)) +#define bFM3_MFT_PPG_PPGC12_PCS0 *((volatile unsigned int*)(0x4248582CUL)) +#define bFM3_MFT_PPG_PPGC12_PCS1 *((volatile unsigned int*)(0x42485830UL)) +#define bFM3_MFT_PPG_PPGC12_INTM *((volatile unsigned int*)(0x42485834UL)) +#define bFM3_MFT_PPG_PPGC12_PUF *((volatile unsigned int*)(0x42485838UL)) +#define bFM3_MFT_PPG_PPGC12_PIE *((volatile unsigned int*)(0x4248583CUL)) +#define bFM3_MFT_PPG_PPGC15_TTRG *((volatile unsigned int*)(0x42485880UL)) +#define bFM3_MFT_PPG_PPGC15_MD0 *((volatile unsigned int*)(0x42485884UL)) +#define bFM3_MFT_PPG_PPGC15_MD1 *((volatile unsigned int*)(0x42485888UL)) +#define bFM3_MFT_PPG_PPGC15_PCS0 *((volatile unsigned int*)(0x4248588CUL)) +#define bFM3_MFT_PPG_PPGC15_PCS1 *((volatile unsigned int*)(0x42485890UL)) +#define bFM3_MFT_PPG_PPGC15_INTM *((volatile unsigned int*)(0x42485894UL)) +#define bFM3_MFT_PPG_PPGC15_PUF *((volatile unsigned int*)(0x42485898UL)) +#define bFM3_MFT_PPG_PPGC15_PIE *((volatile unsigned int*)(0x4248589CUL)) +#define bFM3_MFT_PPG_PPGC14_TTRG *((volatile unsigned int*)(0x424858A0UL)) +#define bFM3_MFT_PPG_PPGC14_MD0 *((volatile unsigned int*)(0x424858A4UL)) +#define bFM3_MFT_PPG_PPGC14_MD1 *((volatile unsigned int*)(0x424858A8UL)) +#define bFM3_MFT_PPG_PPGC14_PCS0 *((volatile unsigned int*)(0x424858ACUL)) +#define bFM3_MFT_PPG_PPGC14_PCS1 *((volatile unsigned int*)(0x424858B0UL)) +#define bFM3_MFT_PPG_PPGC14_INTM *((volatile unsigned int*)(0x424858B4UL)) +#define bFM3_MFT_PPG_PPGC14_PUF *((volatile unsigned int*)(0x424858B8UL)) +#define bFM3_MFT_PPG_PPGC14_PIE *((volatile unsigned int*)(0x424858BCUL)) +#define bFM3_MFT_PPG_GATEC12_EDGE12 *((volatile unsigned int*)(0x42485B00UL)) +#define bFM3_MFT_PPG_GATEC12_STRG12 *((volatile unsigned int*)(0x42485B04UL)) +#define bFM3_MFT_PPG_GATEC12_EDGE14 *((volatile unsigned int*)(0x42485B10UL)) +#define bFM3_MFT_PPG_GATEC12_STRG14 *((volatile unsigned int*)(0x42485B14UL)) + +/* Base Timer 0 PPG registers */ +#define bFM3_BT0_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) +#define bFM3_BT0_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 PWM registers */ +#define bFM3_BT0_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A01ACUL)) +#define bFM3_BT0_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0204UL)) +#define bFM3_BT0_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0214UL)) +#define bFM3_BT0_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 RT registers */ +#define bFM3_BT0_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0180UL)) +#define bFM3_BT0_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A018CUL)) +#define bFM3_BT0_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_RT_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) +#define bFM3_BT0_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_RT_STC_UDIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_RT_STC_TGIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_RT_STC_UDIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_RT_STC_TGIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 0 PWC registers */ +#define bFM3_BT0_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0184UL)) +#define bFM3_BT0_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0188UL)) +#define bFM3_BT0_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0190UL)) +#define bFM3_BT0_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0194UL)) +#define bFM3_BT0_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0198UL)) +#define bFM3_BT0_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A019CUL)) +#define bFM3_BT0_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A01A0UL)) +#define bFM3_BT0_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A01A4UL)) +#define bFM3_BT0_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A01A8UL)) +#define bFM3_BT0_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A01B0UL)) +#define bFM3_BT0_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A01B4UL)) +#define bFM3_BT0_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A01B8UL)) +#define bFM3_BT0_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0200UL)) +#define bFM3_BT0_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0208UL)) +#define bFM3_BT0_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0210UL)) +#define bFM3_BT0_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0218UL)) +#define bFM3_BT0_PWC_STC_ERR *((volatile unsigned int*)(0x424A021CUL)) +#define bFM3_BT0_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0220UL)) + +/* Base Timer 1 PPG registers */ +#define bFM3_BT1_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) +#define bFM3_BT1_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PPG_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PPG_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PPG_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PPG_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 PWM registers */ +#define bFM3_BT1_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A09ACUL)) +#define bFM3_BT1_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PWM_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PWM_STC_DTIR *((volatile unsigned int*)(0x424A0A04UL)) +#define bFM3_BT1_PWM_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PWM_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PWM_STC_DTIE *((volatile unsigned int*)(0x424A0A14UL)) +#define bFM3_BT1_PWM_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 RT registers */ +#define bFM3_BT1_RT_TMCR_STRG *((volatile unsigned int*)(0x424A0980UL)) +#define bFM3_BT1_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A098CUL)) +#define bFM3_BT1_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_RT_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) +#define bFM3_BT1_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_RT_STC_UDIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_RT_STC_TGIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_RT_STC_UDIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_RT_STC_TGIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 1 PWC registers */ +#define bFM3_BT1_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A0984UL)) +#define bFM3_BT1_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A0988UL)) +#define bFM3_BT1_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A0990UL)) +#define bFM3_BT1_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A0994UL)) +#define bFM3_BT1_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A0998UL)) +#define bFM3_BT1_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A099CUL)) +#define bFM3_BT1_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A09A0UL)) +#define bFM3_BT1_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A09A4UL)) +#define bFM3_BT1_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A09A8UL)) +#define bFM3_BT1_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A09B0UL)) +#define bFM3_BT1_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A09B4UL)) +#define bFM3_BT1_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A09B8UL)) +#define bFM3_BT1_PWC_STC_OVIR *((volatile unsigned int*)(0x424A0A00UL)) +#define bFM3_BT1_PWC_STC_EDIR *((volatile unsigned int*)(0x424A0A08UL)) +#define bFM3_BT1_PWC_STC_OVIE *((volatile unsigned int*)(0x424A0A10UL)) +#define bFM3_BT1_PWC_STC_EDIE *((volatile unsigned int*)(0x424A0A18UL)) +#define bFM3_BT1_PWC_STC_ERR *((volatile unsigned int*)(0x424A0A1CUL)) +#define bFM3_BT1_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A0A20UL)) + +/* Base Timer 2 PPG registers */ +#define bFM3_BT2_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) +#define bFM3_BT2_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 PWM registers */ +#define bFM3_BT2_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A11ACUL)) +#define bFM3_BT2_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1204UL)) +#define bFM3_BT2_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1214UL)) +#define bFM3_BT2_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 RT registers */ +#define bFM3_BT2_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1180UL)) +#define bFM3_BT2_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A118CUL)) +#define bFM3_BT2_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_RT_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) +#define bFM3_BT2_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_RT_STC_UDIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_RT_STC_TGIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_RT_STC_UDIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_RT_STC_TGIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 2 PWC registers */ +#define bFM3_BT2_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1184UL)) +#define bFM3_BT2_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1188UL)) +#define bFM3_BT2_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1190UL)) +#define bFM3_BT2_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1194UL)) +#define bFM3_BT2_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1198UL)) +#define bFM3_BT2_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A119CUL)) +#define bFM3_BT2_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A11A0UL)) +#define bFM3_BT2_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A11A4UL)) +#define bFM3_BT2_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A11A8UL)) +#define bFM3_BT2_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A11B0UL)) +#define bFM3_BT2_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A11B4UL)) +#define bFM3_BT2_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A11B8UL)) +#define bFM3_BT2_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1200UL)) +#define bFM3_BT2_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1208UL)) +#define bFM3_BT2_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1210UL)) +#define bFM3_BT2_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1218UL)) +#define bFM3_BT2_PWC_STC_ERR *((volatile unsigned int*)(0x424A121CUL)) +#define bFM3_BT2_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1220UL)) + +/* Base Timer 3 PPG registers */ +#define bFM3_BT3_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) +#define bFM3_BT3_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PPG_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PPG_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PPG_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PPG_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 PWM registers */ +#define bFM3_BT3_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A19ACUL)) +#define bFM3_BT3_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PWM_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PWM_STC_DTIR *((volatile unsigned int*)(0x424A1A04UL)) +#define bFM3_BT3_PWM_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PWM_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PWM_STC_DTIE *((volatile unsigned int*)(0x424A1A14UL)) +#define bFM3_BT3_PWM_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 RT registers */ +#define bFM3_BT3_RT_TMCR_STRG *((volatile unsigned int*)(0x424A1980UL)) +#define bFM3_BT3_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A198CUL)) +#define bFM3_BT3_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_RT_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) +#define bFM3_BT3_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_RT_STC_UDIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_RT_STC_TGIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_RT_STC_UDIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_RT_STC_TGIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 3 PWC registers */ +#define bFM3_BT3_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A1984UL)) +#define bFM3_BT3_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A1988UL)) +#define bFM3_BT3_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A1990UL)) +#define bFM3_BT3_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A1994UL)) +#define bFM3_BT3_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A1998UL)) +#define bFM3_BT3_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A199CUL)) +#define bFM3_BT3_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A19A0UL)) +#define bFM3_BT3_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A19A4UL)) +#define bFM3_BT3_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A19A8UL)) +#define bFM3_BT3_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A19B0UL)) +#define bFM3_BT3_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A19B4UL)) +#define bFM3_BT3_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A19B8UL)) +#define bFM3_BT3_PWC_STC_OVIR *((volatile unsigned int*)(0x424A1A00UL)) +#define bFM3_BT3_PWC_STC_EDIR *((volatile unsigned int*)(0x424A1A08UL)) +#define bFM3_BT3_PWC_STC_OVIE *((volatile unsigned int*)(0x424A1A10UL)) +#define bFM3_BT3_PWC_STC_EDIE *((volatile unsigned int*)(0x424A1A18UL)) +#define bFM3_BT3_PWC_STC_ERR *((volatile unsigned int*)(0x424A1A1CUL)) +#define bFM3_BT3_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A1A20UL)) + +/* Base Timer 4 PPG registers */ +#define bFM3_BT4_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) +#define bFM3_BT4_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 PWM registers */ +#define bFM3_BT4_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A41ACUL)) +#define bFM3_BT4_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4204UL)) +#define bFM3_BT4_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4214UL)) +#define bFM3_BT4_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 RT registers */ +#define bFM3_BT4_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4180UL)) +#define bFM3_BT4_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A418CUL)) +#define bFM3_BT4_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_RT_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) +#define bFM3_BT4_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_RT_STC_UDIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_RT_STC_TGIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_RT_STC_UDIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_RT_STC_TGIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 4 PWC registers */ +#define bFM3_BT4_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4184UL)) +#define bFM3_BT4_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4188UL)) +#define bFM3_BT4_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4190UL)) +#define bFM3_BT4_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4194UL)) +#define bFM3_BT4_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4198UL)) +#define bFM3_BT4_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A419CUL)) +#define bFM3_BT4_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A41A0UL)) +#define bFM3_BT4_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A41A4UL)) +#define bFM3_BT4_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A41A8UL)) +#define bFM3_BT4_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A41B0UL)) +#define bFM3_BT4_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A41B4UL)) +#define bFM3_BT4_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A41B8UL)) +#define bFM3_BT4_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4200UL)) +#define bFM3_BT4_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4208UL)) +#define bFM3_BT4_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4210UL)) +#define bFM3_BT4_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4218UL)) +#define bFM3_BT4_PWC_STC_ERR *((volatile unsigned int*)(0x424A421CUL)) +#define bFM3_BT4_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4220UL)) + +/* Base Timer 5 PPG registers */ +#define bFM3_BT5_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) +#define bFM3_BT5_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PPG_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PPG_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PPG_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PPG_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 PWM registers */ +#define bFM3_BT5_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A49ACUL)) +#define bFM3_BT5_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PWM_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PWM_STC_DTIR *((volatile unsigned int*)(0x424A4A04UL)) +#define bFM3_BT5_PWM_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PWM_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PWM_STC_DTIE *((volatile unsigned int*)(0x424A4A14UL)) +#define bFM3_BT5_PWM_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 RT registers */ +#define bFM3_BT5_RT_TMCR_STRG *((volatile unsigned int*)(0x424A4980UL)) +#define bFM3_BT5_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A498CUL)) +#define bFM3_BT5_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_RT_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) +#define bFM3_BT5_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_RT_STC_UDIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_RT_STC_TGIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_RT_STC_UDIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_RT_STC_TGIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 5 PWC registers */ +#define bFM3_BT5_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A4984UL)) +#define bFM3_BT5_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A4988UL)) +#define bFM3_BT5_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A4990UL)) +#define bFM3_BT5_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A4994UL)) +#define bFM3_BT5_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A4998UL)) +#define bFM3_BT5_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A499CUL)) +#define bFM3_BT5_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A49A0UL)) +#define bFM3_BT5_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A49A4UL)) +#define bFM3_BT5_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A49A8UL)) +#define bFM3_BT5_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A49B0UL)) +#define bFM3_BT5_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A49B4UL)) +#define bFM3_BT5_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A49B8UL)) +#define bFM3_BT5_PWC_STC_OVIR *((volatile unsigned int*)(0x424A4A00UL)) +#define bFM3_BT5_PWC_STC_EDIR *((volatile unsigned int*)(0x424A4A08UL)) +#define bFM3_BT5_PWC_STC_OVIE *((volatile unsigned int*)(0x424A4A10UL)) +#define bFM3_BT5_PWC_STC_EDIE *((volatile unsigned int*)(0x424A4A18UL)) +#define bFM3_BT5_PWC_STC_ERR *((volatile unsigned int*)(0x424A4A1CUL)) +#define bFM3_BT5_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A4A20UL)) + +/* Base Timer 6 PPG registers */ +#define bFM3_BT6_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) +#define bFM3_BT6_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 PWM registers */ +#define bFM3_BT6_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A51ACUL)) +#define bFM3_BT6_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5204UL)) +#define bFM3_BT6_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5214UL)) +#define bFM3_BT6_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 RT registers */ +#define bFM3_BT6_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5180UL)) +#define bFM3_BT6_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A518CUL)) +#define bFM3_BT6_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_RT_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) +#define bFM3_BT6_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_RT_STC_UDIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_RT_STC_TGIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_RT_STC_UDIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_RT_STC_TGIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 6 PWC registers */ +#define bFM3_BT6_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5184UL)) +#define bFM3_BT6_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5188UL)) +#define bFM3_BT6_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5190UL)) +#define bFM3_BT6_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5194UL)) +#define bFM3_BT6_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5198UL)) +#define bFM3_BT6_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A519CUL)) +#define bFM3_BT6_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A51A0UL)) +#define bFM3_BT6_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A51A4UL)) +#define bFM3_BT6_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A51A8UL)) +#define bFM3_BT6_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A51B0UL)) +#define bFM3_BT6_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A51B4UL)) +#define bFM3_BT6_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A51B8UL)) +#define bFM3_BT6_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5200UL)) +#define bFM3_BT6_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5208UL)) +#define bFM3_BT6_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5210UL)) +#define bFM3_BT6_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5218UL)) +#define bFM3_BT6_PWC_STC_ERR *((volatile unsigned int*)(0x424A521CUL)) +#define bFM3_BT6_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5220UL)) + +/* Base Timer 7 PPG registers */ +#define bFM3_BT7_PPG_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_PPG_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PPG_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PPG_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_PPG_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_PPG_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_PPG_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_PPG_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PPG_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PPG_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PPG_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) +#define bFM3_BT7_PPG_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PPG_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PPG_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PPG_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PPG_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PPG_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PPG_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PPG_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 PWM registers */ +#define bFM3_BT7_PWM_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_PWM_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PWM_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PWM_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_PWM_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_PWM_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_PWM_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_PWM_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PWM_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PWM_TMCR_PMSK *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PWM_TMCR_RTGEN *((volatile unsigned int*)(0x424A59ACUL)) +#define bFM3_BT7_PWM_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PWM_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PWM_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PWM_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PWM_STC_DTIR *((volatile unsigned int*)(0x424A5A04UL)) +#define bFM3_BT7_PWM_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PWM_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PWM_STC_DTIE *((volatile unsigned int*)(0x424A5A14UL)) +#define bFM3_BT7_PWM_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PWM_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 RT registers */ +#define bFM3_BT7_RT_TMCR_STRG *((volatile unsigned int*)(0x424A5980UL)) +#define bFM3_BT7_RT_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_RT_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_RT_TMCR_OSEL *((volatile unsigned int*)(0x424A598CUL)) +#define bFM3_BT7_RT_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_RT_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_RT_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_RT_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) +#define bFM3_BT7_RT_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_RT_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_RT_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_RT_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_RT_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_RT_STC_UDIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_RT_STC_TGIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_RT_STC_UDIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_RT_STC_TGIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_RT_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer 7 PWC registers */ +#define bFM3_BT7_PWC_TMCR_CTEN *((volatile unsigned int*)(0x424A5984UL)) +#define bFM3_BT7_PWC_TMCR_MDSE *((volatile unsigned int*)(0x424A5988UL)) +#define bFM3_BT7_PWC_TMCR_FMD0 *((volatile unsigned int*)(0x424A5990UL)) +#define bFM3_BT7_PWC_TMCR_FMD1 *((volatile unsigned int*)(0x424A5994UL)) +#define bFM3_BT7_PWC_TMCR_FMD2 *((volatile unsigned int*)(0x424A5998UL)) +#define bFM3_BT7_PWC_TMCR_T32 *((volatile unsigned int*)(0x424A599CUL)) +#define bFM3_BT7_PWC_TMCR_EGS0 *((volatile unsigned int*)(0x424A59A0UL)) +#define bFM3_BT7_PWC_TMCR_EGS1 *((volatile unsigned int*)(0x424A59A4UL)) +#define bFM3_BT7_PWC_TMCR_EGS2 *((volatile unsigned int*)(0x424A59A8UL)) +#define bFM3_BT7_PWC_TMCR_CKS0 *((volatile unsigned int*)(0x424A59B0UL)) +#define bFM3_BT7_PWC_TMCR_CKS1 *((volatile unsigned int*)(0x424A59B4UL)) +#define bFM3_BT7_PWC_TMCR_CKS2 *((volatile unsigned int*)(0x424A59B8UL)) +#define bFM3_BT7_PWC_STC_OVIR *((volatile unsigned int*)(0x424A5A00UL)) +#define bFM3_BT7_PWC_STC_EDIR *((volatile unsigned int*)(0x424A5A08UL)) +#define bFM3_BT7_PWC_STC_OVIE *((volatile unsigned int*)(0x424A5A10UL)) +#define bFM3_BT7_PWC_STC_EDIE *((volatile unsigned int*)(0x424A5A18UL)) +#define bFM3_BT7_PWC_STC_ERR *((volatile unsigned int*)(0x424A5A1CUL)) +#define bFM3_BT7_PWC_TMCR2_CKS3 *((volatile unsigned int*)(0x424A5A20UL)) + +/* Base Timer I/O selector channel 0 - channel 3 registers */ +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_0 *((volatile unsigned int*)(0x424A2020UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_1 *((volatile unsigned int*)(0x424A2024UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_2 *((volatile unsigned int*)(0x424A2028UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL01_3 *((volatile unsigned int*)(0x424A202CUL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_0 *((volatile unsigned int*)(0x424A2030UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_1 *((volatile unsigned int*)(0x424A2034UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_2 *((volatile unsigned int*)(0x424A2038UL)) +#define bFM3_BTIOSEL03_BTSEL0123_SEL23_3 *((volatile unsigned int*)(0x424A203CUL)) + +/* Base Timer I/O selector channel 4 - channel 7 registers */ +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_0 *((volatile unsigned int*)(0x424A6020UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_1 *((volatile unsigned int*)(0x424A6024UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_2 *((volatile unsigned int*)(0x424A6028UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL45_3 *((volatile unsigned int*)(0x424A602CUL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_0 *((volatile unsigned int*)(0x424A6030UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_1 *((volatile unsigned int*)(0x424A6034UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_2 *((volatile unsigned int*)(0x424A6038UL)) +#define bFM3_BTIOSEL47_BTSEL4567_SEL67_3 *((volatile unsigned int*)(0x424A603CUL)) + +/* Software based Simulation Startup (Base Timer) register */ +#define bFM3_SBSSR_BTSSSR_SSR0 *((volatile unsigned int*)(0x424BFF80UL)) +#define bFM3_SBSSR_BTSSSR_SSR1 *((volatile unsigned int*)(0x424BFF84UL)) +#define bFM3_SBSSR_BTSSSR_SSR2 *((volatile unsigned int*)(0x424BFF88UL)) +#define bFM3_SBSSR_BTSSSR_SSR3 *((volatile unsigned int*)(0x424BFF8CUL)) +#define bFM3_SBSSR_BTSSSR_SSR4 *((volatile unsigned int*)(0x424BFF90UL)) +#define bFM3_SBSSR_BTSSSR_SSR5 *((volatile unsigned int*)(0x424BFF94UL)) +#define bFM3_SBSSR_BTSSSR_SSR6 *((volatile unsigned int*)(0x424BFF98UL)) +#define bFM3_SBSSR_BTSSSR_SSR7 *((volatile unsigned int*)(0x424BFF9CUL)) +#define bFM3_SBSSR_BTSSSR_SSR8 *((volatile unsigned int*)(0x424BFFA0UL)) +#define bFM3_SBSSR_BTSSSR_SSR9 *((volatile unsigned int*)(0x424BFFA4UL)) +#define bFM3_SBSSR_BTSSSR_SSR10 *((volatile unsigned int*)(0x424BFFA8UL)) +#define bFM3_SBSSR_BTSSSR_SSR11 *((volatile unsigned int*)(0x424BFFACUL)) +#define bFM3_SBSSR_BTSSSR_SSR12 *((volatile unsigned int*)(0x424BFFB0UL)) +#define bFM3_SBSSR_BTSSSR_SSR13 *((volatile unsigned int*)(0x424BFFB4UL)) +#define bFM3_SBSSR_BTSSSR_SSR14 *((volatile unsigned int*)(0x424BFFB8UL)) +#define bFM3_SBSSR_BTSSSR_SSR15 *((volatile unsigned int*)(0x424BFFBCUL)) + +/* Quad position and revolution counter channel 0 registers */ +#define bFM3_QPRC0_QICR_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) +#define bFM3_QPRC0_QICR_QPCMF *((volatile unsigned int*)(0x424C0284UL)) +#define bFM3_QPRC0_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) +#define bFM3_QPRC0_QICR_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) +#define bFM3_QPRC0_QICR_OUZIE *((volatile unsigned int*)(0x424C0290UL)) +#define bFM3_QPRC0_QICR_UFDF *((volatile unsigned int*)(0x424C0294UL)) +#define bFM3_QPRC0_QICR_OFDF *((volatile unsigned int*)(0x424C0298UL)) +#define bFM3_QPRC0_QICR_ZIIF *((volatile unsigned int*)(0x424C029CUL)) +#define bFM3_QPRC0_QICR_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) +#define bFM3_QPRC0_QICR_CDCF *((volatile unsigned int*)(0x424C02A4UL)) +#define bFM3_QPRC0_QICR_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) +#define bFM3_QPRC0_QICR_DIROU *((volatile unsigned int*)(0x424C02ACUL)) +#define bFM3_QPRC0_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) +#define bFM3_QPRC0_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) +#define bFM3_QPRC0_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0280UL)) +#define bFM3_QPRC0_QICRL_QPCMF *((volatile unsigned int*)(0x424C0284UL)) +#define bFM3_QPRC0_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0288UL)) +#define bFM3_QPRC0_QICRL_QPRCMF *((volatile unsigned int*)(0x424C028CUL)) +#define bFM3_QPRC0_QICRL_OUZIE *((volatile unsigned int*)(0x424C0290UL)) +#define bFM3_QPRC0_QICRL_UFDF *((volatile unsigned int*)(0x424C0294UL)) +#define bFM3_QPRC0_QICRL_OFDF *((volatile unsigned int*)(0x424C0298UL)) +#define bFM3_QPRC0_QICRL_ZIIF *((volatile unsigned int*)(0x424C029CUL)) +#define bFM3_QPRC0_QICRH_CDCIE *((volatile unsigned int*)(0x424C02A0UL)) +#define bFM3_QPRC0_QICRH_CDCF *((volatile unsigned int*)(0x424C02A4UL)) +#define bFM3_QPRC0_QICRH_DIRPC *((volatile unsigned int*)(0x424C02A8UL)) +#define bFM3_QPRC0_QICRH_DIROU *((volatile unsigned int*)(0x424C02ACUL)) +#define bFM3_QPRC0_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C02B0UL)) +#define bFM3_QPRC0_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C02B4UL)) +#define bFM3_QPRC0_QCR_PCM0 *((volatile unsigned int*)(0x424C0300UL)) +#define bFM3_QPRC0_QCR_PCM1 *((volatile unsigned int*)(0x424C0304UL)) +#define bFM3_QPRC0_QCR_RCM0 *((volatile unsigned int*)(0x424C0308UL)) +#define bFM3_QPRC0_QCR_RCM1 *((volatile unsigned int*)(0x424C030CUL)) +#define bFM3_QPRC0_QCR_PSTP *((volatile unsigned int*)(0x424C0310UL)) +#define bFM3_QPRC0_QCR_CGSC *((volatile unsigned int*)(0x424C0314UL)) +#define bFM3_QPRC0_QCR_RSEL *((volatile unsigned int*)(0x424C0318UL)) +#define bFM3_QPRC0_QCR_SWAP *((volatile unsigned int*)(0x424C031CUL)) +#define bFM3_QPRC0_QCR_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) +#define bFM3_QPRC0_QCR_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) +#define bFM3_QPRC0_QCR_AES0 *((volatile unsigned int*)(0x424C0328UL)) +#define bFM3_QPRC0_QCR_AES1 *((volatile unsigned int*)(0x424C032CUL)) +#define bFM3_QPRC0_QCR_BES0 *((volatile unsigned int*)(0x424C0330UL)) +#define bFM3_QPRC0_QCR_BES1 *((volatile unsigned int*)(0x424C0334UL)) +#define bFM3_QPRC0_QCR_CGE0 *((volatile unsigned int*)(0x424C0338UL)) +#define bFM3_QPRC0_QCR_CGE1 *((volatile unsigned int*)(0x424C033CUL)) +#define bFM3_QPRC0_QCRL_PCM0 *((volatile unsigned int*)(0x424C0300UL)) +#define bFM3_QPRC0_QCRL_PCM1 *((volatile unsigned int*)(0x424C0304UL)) +#define bFM3_QPRC0_QCRL_RCM0 *((volatile unsigned int*)(0x424C0308UL)) +#define bFM3_QPRC0_QCRL_RCM1 *((volatile unsigned int*)(0x424C030CUL)) +#define bFM3_QPRC0_QCRL_PSTP *((volatile unsigned int*)(0x424C0310UL)) +#define bFM3_QPRC0_QCRL_CGSC *((volatile unsigned int*)(0x424C0314UL)) +#define bFM3_QPRC0_QCRL_RSEL *((volatile unsigned int*)(0x424C0318UL)) +#define bFM3_QPRC0_QCRL_SWAP *((volatile unsigned int*)(0x424C031CUL)) +#define bFM3_QPRC0_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0320UL)) +#define bFM3_QPRC0_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0324UL)) +#define bFM3_QPRC0_QCRH_AES0 *((volatile unsigned int*)(0x424C0328UL)) +#define bFM3_QPRC0_QCRH_AES1 *((volatile unsigned int*)(0x424C032CUL)) +#define bFM3_QPRC0_QCRH_BES0 *((volatile unsigned int*)(0x424C0330UL)) +#define bFM3_QPRC0_QCRH_BES1 *((volatile unsigned int*)(0x424C0334UL)) +#define bFM3_QPRC0_QCRH_CGE0 *((volatile unsigned int*)(0x424C0338UL)) +#define bFM3_QPRC0_QCRH_CGE1 *((volatile unsigned int*)(0x424C033CUL)) +#define bFM3_QPRC0_QECR_ORNGMD *((volatile unsigned int*)(0x424C0380UL)) +#define bFM3_QPRC0_QECR_ORNGF *((volatile unsigned int*)(0x424C0384UL)) +#define bFM3_QPRC0_QECR_ORNGIE *((volatile unsigned int*)(0x424C0388UL)) + +/* Quad position and revolution counter channel 1 registers */ +#define bFM3_QPRC1_QICR_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) +#define bFM3_QPRC1_QICR_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) +#define bFM3_QPRC1_QICR_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) +#define bFM3_QPRC1_QICR_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) +#define bFM3_QPRC1_QICR_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) +#define bFM3_QPRC1_QICR_UFDF *((volatile unsigned int*)(0x424C0A94UL)) +#define bFM3_QPRC1_QICR_OFDF *((volatile unsigned int*)(0x424C0A98UL)) +#define bFM3_QPRC1_QICR_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) +#define bFM3_QPRC1_QICR_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) +#define bFM3_QPRC1_QICR_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) +#define bFM3_QPRC1_QICR_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) +#define bFM3_QPRC1_QICR_DIROU *((volatile unsigned int*)(0x424C0AACUL)) +#define bFM3_QPRC1_QICR_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) +#define bFM3_QPRC1_QICR_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) +#define bFM3_QPRC1_QICRL_QPCMIE *((volatile unsigned int*)(0x424C0A80UL)) +#define bFM3_QPRC1_QICRL_QPCMF *((volatile unsigned int*)(0x424C0A84UL)) +#define bFM3_QPRC1_QICRL_QPRCMIE *((volatile unsigned int*)(0x424C0A88UL)) +#define bFM3_QPRC1_QICRL_QPRCMF *((volatile unsigned int*)(0x424C0A8CUL)) +#define bFM3_QPRC1_QICRL_OUZIE *((volatile unsigned int*)(0x424C0A90UL)) +#define bFM3_QPRC1_QICRL_UFDF *((volatile unsigned int*)(0x424C0A94UL)) +#define bFM3_QPRC1_QICRL_OFDF *((volatile unsigned int*)(0x424C0A98UL)) +#define bFM3_QPRC1_QICRL_ZIIF *((volatile unsigned int*)(0x424C0A9CUL)) +#define bFM3_QPRC1_QICRH_CDCIE *((volatile unsigned int*)(0x424C0AA0UL)) +#define bFM3_QPRC1_QICRH_CDCF *((volatile unsigned int*)(0x424C0AA4UL)) +#define bFM3_QPRC1_QICRH_DIRPC *((volatile unsigned int*)(0x424C0AA8UL)) +#define bFM3_QPRC1_QICRH_DIROU *((volatile unsigned int*)(0x424C0AACUL)) +#define bFM3_QPRC1_QICRH_QPCNRCMIE *((volatile unsigned int*)(0x424C0AB0UL)) +#define bFM3_QPRC1_QICRH_QPCNRCMF *((volatile unsigned int*)(0x424C0AB4UL)) +#define bFM3_QPRC1_QCR_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) +#define bFM3_QPRC1_QCR_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) +#define bFM3_QPRC1_QCR_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) +#define bFM3_QPRC1_QCR_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) +#define bFM3_QPRC1_QCR_PSTP *((volatile unsigned int*)(0x424C0B10UL)) +#define bFM3_QPRC1_QCR_CGSC *((volatile unsigned int*)(0x424C0B14UL)) +#define bFM3_QPRC1_QCR_RSEL *((volatile unsigned int*)(0x424C0B18UL)) +#define bFM3_QPRC1_QCR_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) +#define bFM3_QPRC1_QCR_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) +#define bFM3_QPRC1_QCR_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) +#define bFM3_QPRC1_QCR_AES0 *((volatile unsigned int*)(0x424C0B28UL)) +#define bFM3_QPRC1_QCR_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) +#define bFM3_QPRC1_QCR_BES0 *((volatile unsigned int*)(0x424C0B30UL)) +#define bFM3_QPRC1_QCR_BES1 *((volatile unsigned int*)(0x424C0B34UL)) +#define bFM3_QPRC1_QCR_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) +#define bFM3_QPRC1_QCR_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) +#define bFM3_QPRC1_QCRL_PCM0 *((volatile unsigned int*)(0x424C0B00UL)) +#define bFM3_QPRC1_QCRL_PCM1 *((volatile unsigned int*)(0x424C0B04UL)) +#define bFM3_QPRC1_QCRL_RCM0 *((volatile unsigned int*)(0x424C0B08UL)) +#define bFM3_QPRC1_QCRL_RCM1 *((volatile unsigned int*)(0x424C0B0CUL)) +#define bFM3_QPRC1_QCRL_PSTP *((volatile unsigned int*)(0x424C0B10UL)) +#define bFM3_QPRC1_QCRL_CGSC *((volatile unsigned int*)(0x424C0B14UL)) +#define bFM3_QPRC1_QCRL_RSEL *((volatile unsigned int*)(0x424C0B18UL)) +#define bFM3_QPRC1_QCRL_SWAP *((volatile unsigned int*)(0x424C0B1CUL)) +#define bFM3_QPRC1_QCRH_PCRM0 *((volatile unsigned int*)(0x424C0B20UL)) +#define bFM3_QPRC1_QCRH_PCRM1 *((volatile unsigned int*)(0x424C0B24UL)) +#define bFM3_QPRC1_QCRH_AES0 *((volatile unsigned int*)(0x424C0B28UL)) +#define bFM3_QPRC1_QCRH_AES1 *((volatile unsigned int*)(0x424C0B2CUL)) +#define bFM3_QPRC1_QCRH_BES0 *((volatile unsigned int*)(0x424C0B30UL)) +#define bFM3_QPRC1_QCRH_BES1 *((volatile unsigned int*)(0x424C0B34UL)) +#define bFM3_QPRC1_QCRH_CGE0 *((volatile unsigned int*)(0x424C0B38UL)) +#define bFM3_QPRC1_QCRH_CGE1 *((volatile unsigned int*)(0x424C0B3CUL)) +#define bFM3_QPRC1_QECR_ORNGMD *((volatile unsigned int*)(0x424C0B80UL)) +#define bFM3_QPRC1_QECR_ORNGF *((volatile unsigned int*)(0x424C0B84UL)) +#define bFM3_QPRC1_QECR_ORNGIE *((volatile unsigned int*)(0x424C0B88UL)) + +/* 12-bit ADC unit 0 registers */ +#define bFM3_ADC0_ADSR_SCS *((volatile unsigned int*)(0x424E0000UL)) +#define bFM3_ADC0_ADSR_PCS *((volatile unsigned int*)(0x424E0004UL)) +#define bFM3_ADC0_ADSR_PCNS *((volatile unsigned int*)(0x424E0008UL)) +#define bFM3_ADC0_ADSR_FDAS *((volatile unsigned int*)(0x424E0018UL)) +#define bFM3_ADC0_ADSR_ADSTP *((volatile unsigned int*)(0x424E001CUL)) +#define bFM3_ADC0_ADCR_OVRIE *((volatile unsigned int*)(0x424E0020UL)) +#define bFM3_ADC0_ADCR_CMPIE *((volatile unsigned int*)(0x424E0024UL)) +#define bFM3_ADC0_ADCR_PCIE *((volatile unsigned int*)(0x424E0028UL)) +#define bFM3_ADC0_ADCR_SCIE *((volatile unsigned int*)(0x424E002CUL)) +#define bFM3_ADC0_ADCR_CMPIF *((volatile unsigned int*)(0x424E0034UL)) +#define bFM3_ADC0_ADCR_PCIF *((volatile unsigned int*)(0x424E0038UL)) +#define bFM3_ADC0_ADCR_SCIF *((volatile unsigned int*)(0x424E003CUL)) +#define bFM3_ADC0_SFNS_SFS0 *((volatile unsigned int*)(0x424E0100UL)) +#define bFM3_ADC0_SFNS_SFS1 *((volatile unsigned int*)(0x424E0104UL)) +#define bFM3_ADC0_SFNS_SFS2 *((volatile unsigned int*)(0x424E0108UL)) +#define bFM3_ADC0_SFNS_SFS3 *((volatile unsigned int*)(0x424E010CUL)) +#define bFM3_ADC0_SCCR_SSTR *((volatile unsigned int*)(0x424E0120UL)) +#define bFM3_ADC0_SCCR_SHEN *((volatile unsigned int*)(0x424E0124UL)) +#define bFM3_ADC0_SCCR_RPT *((volatile unsigned int*)(0x424E0128UL)) +#define bFM3_ADC0_SCCR_SFCLR *((volatile unsigned int*)(0x424E0130UL)) +#define bFM3_ADC0_SCCR_SOVR *((volatile unsigned int*)(0x424E0134UL)) +#define bFM3_ADC0_SCCR_SFUL *((volatile unsigned int*)(0x424E0138UL)) +#define bFM3_ADC0_SCCR_SEMP *((volatile unsigned int*)(0x424E013CUL)) +#define bFM3_ADC0_SCFD_SC0 *((volatile unsigned int*)(0x424E0180UL)) +#define bFM3_ADC0_SCFD_SC1 *((volatile unsigned int*)(0x424E0184UL)) +#define bFM3_ADC0_SCFD_SC2 *((volatile unsigned int*)(0x424E0188UL)) +#define bFM3_ADC0_SCFD_SC3 *((volatile unsigned int*)(0x424E018CUL)) +#define bFM3_ADC0_SCFD_SC4 *((volatile unsigned int*)(0x424E0190UL)) +#define bFM3_ADC0_SCFD_RS0 *((volatile unsigned int*)(0x424E01A0UL)) +#define bFM3_ADC0_SCFD_RS1 *((volatile unsigned int*)(0x424E01A4UL)) +#define bFM3_ADC0_SCFD_INVL *((volatile unsigned int*)(0x424E01B0UL)) +#define bFM3_ADC0_SCFD_SD0 *((volatile unsigned int*)(0x424E01D0UL)) +#define bFM3_ADC0_SCFD_SD1 *((volatile unsigned int*)(0x424E01D4UL)) +#define bFM3_ADC0_SCFD_SD2 *((volatile unsigned int*)(0x424E01D8UL)) +#define bFM3_ADC0_SCFD_SD3 *((volatile unsigned int*)(0x424E01DCUL)) +#define bFM3_ADC0_SCFD_SD4 *((volatile unsigned int*)(0x424E01E0UL)) +#define bFM3_ADC0_SCFD_SD5 *((volatile unsigned int*)(0x424E01E4UL)) +#define bFM3_ADC0_SCFD_SD6 *((volatile unsigned int*)(0x424E01E8UL)) +#define bFM3_ADC0_SCFD_SD7 *((volatile unsigned int*)(0x424E01ECUL)) +#define bFM3_ADC0_SCFD_SD8 *((volatile unsigned int*)(0x424E01F0UL)) +#define bFM3_ADC0_SCFD_SD9 *((volatile unsigned int*)(0x424E01F4UL)) +#define bFM3_ADC0_SCFD_SD10 *((volatile unsigned int*)(0x424E01F8UL)) +#define bFM3_ADC0_SCFD_SD11 *((volatile unsigned int*)(0x424E01FCUL)) +#define bFM3_ADC0_SCFDL_SC0 *((volatile unsigned int*)(0x424E0180UL)) +#define bFM3_ADC0_SCFDL_SC1 *((volatile unsigned int*)(0x424E0184UL)) +#define bFM3_ADC0_SCFDL_SC2 *((volatile unsigned int*)(0x424E0188UL)) +#define bFM3_ADC0_SCFDL_SC3 *((volatile unsigned int*)(0x424E018CUL)) +#define bFM3_ADC0_SCFDL_SC4 *((volatile unsigned int*)(0x424E0190UL)) +#define bFM3_ADC0_SCFDL_RS0 *((volatile unsigned int*)(0x424E01A0UL)) +#define bFM3_ADC0_SCFDL_RS1 *((volatile unsigned int*)(0x424E01A4UL)) +#define bFM3_ADC0_SCFDL_INVL *((volatile unsigned int*)(0x424E01B0UL)) +#define bFM3_ADC0_SCFDH_SD0 *((volatile unsigned int*)(0x424E01D0UL)) +#define bFM3_ADC0_SCFDH_SD1 *((volatile unsigned int*)(0x424E01D4UL)) +#define bFM3_ADC0_SCFDH_SD2 *((volatile unsigned int*)(0x424E01D8UL)) +#define bFM3_ADC0_SCFDH_SD3 *((volatile unsigned int*)(0x424E01DCUL)) +#define bFM3_ADC0_SCFDH_SD4 *((volatile unsigned int*)(0x424E01E0UL)) +#define bFM3_ADC0_SCFDH_SD5 *((volatile unsigned int*)(0x424E01E4UL)) +#define bFM3_ADC0_SCFDH_SD6 *((volatile unsigned int*)(0x424E01E8UL)) +#define bFM3_ADC0_SCFDH_SD7 *((volatile unsigned int*)(0x424E01ECUL)) +#define bFM3_ADC0_SCFDH_SD8 *((volatile unsigned int*)(0x424E01F0UL)) +#define bFM3_ADC0_SCFDH_SD9 *((volatile unsigned int*)(0x424E01F4UL)) +#define bFM3_ADC0_SCFDH_SD10 *((volatile unsigned int*)(0x424E01F8UL)) +#define bFM3_ADC0_SCFDH_SD11 *((volatile unsigned int*)(0x424E01FCUL)) +#define bFM3_ADC0_SCIS23_AN16 *((volatile unsigned int*)(0x424E0200UL)) +#define bFM3_ADC0_SCIS23_AN17 *((volatile unsigned int*)(0x424E0204UL)) +#define bFM3_ADC0_SCIS23_AN18 *((volatile unsigned int*)(0x424E0208UL)) +#define bFM3_ADC0_SCIS23_AN19 *((volatile unsigned int*)(0x424E020CUL)) +#define bFM3_ADC0_SCIS23_AN20 *((volatile unsigned int*)(0x424E0210UL)) +#define bFM3_ADC0_SCIS23_AN21 *((volatile unsigned int*)(0x424E0214UL)) +#define bFM3_ADC0_SCIS23_AN22 *((volatile unsigned int*)(0x424E0218UL)) +#define bFM3_ADC0_SCIS23_AN23 *((volatile unsigned int*)(0x424E021CUL)) +#define bFM3_ADC0_SCIS23_AN24 *((volatile unsigned int*)(0x424E0220UL)) +#define bFM3_ADC0_SCIS23_AN25 *((volatile unsigned int*)(0x424E0224UL)) +#define bFM3_ADC0_SCIS23_AN26 *((volatile unsigned int*)(0x424E0228UL)) +#define bFM3_ADC0_SCIS23_AN27 *((volatile unsigned int*)(0x424E022CUL)) +#define bFM3_ADC0_SCIS23_AN28 *((volatile unsigned int*)(0x424E0230UL)) +#define bFM3_ADC0_SCIS23_AN29 *((volatile unsigned int*)(0x424E0234UL)) +#define bFM3_ADC0_SCIS23_AN30 *((volatile unsigned int*)(0x424E0238UL)) +#define bFM3_ADC0_SCIS23_AN31 *((volatile unsigned int*)(0x424E023CUL)) +#define bFM3_ADC0_SCIS2_AN16 *((volatile unsigned int*)(0x424E0200UL)) +#define bFM3_ADC0_SCIS2_AN17 *((volatile unsigned int*)(0x424E0204UL)) +#define bFM3_ADC0_SCIS2_AN18 *((volatile unsigned int*)(0x424E0208UL)) +#define bFM3_ADC0_SCIS2_AN19 *((volatile unsigned int*)(0x424E020CUL)) +#define bFM3_ADC0_SCIS2_AN20 *((volatile unsigned int*)(0x424E0210UL)) +#define bFM3_ADC0_SCIS2_AN21 *((volatile unsigned int*)(0x424E0214UL)) +#define bFM3_ADC0_SCIS2_AN22 *((volatile unsigned int*)(0x424E0218UL)) +#define bFM3_ADC0_SCIS2_AN23 *((volatile unsigned int*)(0x424E021CUL)) +#define bFM3_ADC0_SCIS3_AN24 *((volatile unsigned int*)(0x424E0220UL)) +#define bFM3_ADC0_SCIS3_AN25 *((volatile unsigned int*)(0x424E0224UL)) +#define bFM3_ADC0_SCIS3_AN26 *((volatile unsigned int*)(0x424E0228UL)) +#define bFM3_ADC0_SCIS3_AN27 *((volatile unsigned int*)(0x424E022CUL)) +#define bFM3_ADC0_SCIS3_AN28 *((volatile unsigned int*)(0x424E0230UL)) +#define bFM3_ADC0_SCIS3_AN29 *((volatile unsigned int*)(0x424E0234UL)) +#define bFM3_ADC0_SCIS3_AN30 *((volatile unsigned int*)(0x424E0238UL)) +#define bFM3_ADC0_SCIS3_AN31 *((volatile unsigned int*)(0x424E023CUL)) +#define bFM3_ADC0_SCIS01_AN0 *((volatile unsigned int*)(0x424E0280UL)) +#define bFM3_ADC0_SCIS01_AN1 *((volatile unsigned int*)(0x424E0284UL)) +#define bFM3_ADC0_SCIS01_AN2 *((volatile unsigned int*)(0x424E0288UL)) +#define bFM3_ADC0_SCIS01_AN3 *((volatile unsigned int*)(0x424E028CUL)) +#define bFM3_ADC0_SCIS01_AN4 *((volatile unsigned int*)(0x424E0290UL)) +#define bFM3_ADC0_SCIS01_AN5 *((volatile unsigned int*)(0x424E0294UL)) +#define bFM3_ADC0_SCIS01_AN6 *((volatile unsigned int*)(0x424E0298UL)) +#define bFM3_ADC0_SCIS01_AN7 *((volatile unsigned int*)(0x424E029CUL)) +#define bFM3_ADC0_SCIS01_AN8 *((volatile unsigned int*)(0x424E02A0UL)) +#define bFM3_ADC0_SCIS01_AN9 *((volatile unsigned int*)(0x424E02A4UL)) +#define bFM3_ADC0_SCIS01_AN10 *((volatile unsigned int*)(0x424E02A8UL)) +#define bFM3_ADC0_SCIS01_AN11 *((volatile unsigned int*)(0x424E02ACUL)) +#define bFM3_ADC0_SCIS01_AN12 *((volatile unsigned int*)(0x424E02B0UL)) +#define bFM3_ADC0_SCIS01_AN13 *((volatile unsigned int*)(0x424E02B4UL)) +#define bFM3_ADC0_SCIS01_AN14 *((volatile unsigned int*)(0x424E02B8UL)) +#define bFM3_ADC0_SCIS01_AN15 *((volatile unsigned int*)(0x424E02BCUL)) +#define bFM3_ADC0_SCIS0_AN0 *((volatile unsigned int*)(0x424E0280UL)) +#define bFM3_ADC0_SCIS0_AN1 *((volatile unsigned int*)(0x424E0284UL)) +#define bFM3_ADC0_SCIS0_AN2 *((volatile unsigned int*)(0x424E0288UL)) +#define bFM3_ADC0_SCIS0_AN3 *((volatile unsigned int*)(0x424E028CUL)) +#define bFM3_ADC0_SCIS0_AN4 *((volatile unsigned int*)(0x424E0290UL)) +#define bFM3_ADC0_SCIS0_AN5 *((volatile unsigned int*)(0x424E0294UL)) +#define bFM3_ADC0_SCIS0_AN6 *((volatile unsigned int*)(0x424E0298UL)) +#define bFM3_ADC0_SCIS0_AN7 *((volatile unsigned int*)(0x424E029CUL)) +#define bFM3_ADC0_SCIS1_AN8 *((volatile unsigned int*)(0x424E02A0UL)) +#define bFM3_ADC0_SCIS1_AN9 *((volatile unsigned int*)(0x424E02A4UL)) +#define bFM3_ADC0_SCIS1_AN10 *((volatile unsigned int*)(0x424E02A8UL)) +#define bFM3_ADC0_SCIS1_AN11 *((volatile unsigned int*)(0x424E02ACUL)) +#define bFM3_ADC0_SCIS1_AN12 *((volatile unsigned int*)(0x424E02B0UL)) +#define bFM3_ADC0_SCIS1_AN13 *((volatile unsigned int*)(0x424E02B4UL)) +#define bFM3_ADC0_SCIS1_AN14 *((volatile unsigned int*)(0x424E02B8UL)) +#define bFM3_ADC0_SCIS1_AN15 *((volatile unsigned int*)(0x424E02BCUL)) +#define bFM3_ADC0_PFNS_PFS0 *((volatile unsigned int*)(0x424E0300UL)) +#define bFM3_ADC0_PFNS_PFS1 *((volatile unsigned int*)(0x424E0304UL)) +#define bFM3_ADC0_PFNS_TEST0 *((volatile unsigned int*)(0x424E0310UL)) +#define bFM3_ADC0_PFNS_TEST1 *((volatile unsigned int*)(0x424E0314UL)) +#define bFM3_ADC0_PCCR_PSTR *((volatile unsigned int*)(0x424E0320UL)) +#define bFM3_ADC0_PCCR_PHEN *((volatile unsigned int*)(0x424E0324UL)) +#define bFM3_ADC0_PCCR_PEEN *((volatile unsigned int*)(0x424E0328UL)) +#define bFM3_ADC0_PCCR_ESCE *((volatile unsigned int*)(0x424E032CUL)) +#define bFM3_ADC0_PCCR_PFCLR *((volatile unsigned int*)(0x424E0330UL)) +#define bFM3_ADC0_PCCR_POVR *((volatile unsigned int*)(0x424E0334UL)) +#define bFM3_ADC0_PCCR_PFUL *((volatile unsigned int*)(0x424E0338UL)) +#define bFM3_ADC0_PCCR_PEMP *((volatile unsigned int*)(0x424E033CUL)) +#define bFM3_ADC0_PCFD_PC0 *((volatile unsigned int*)(0x424E0380UL)) +#define bFM3_ADC0_PCFD_PC1 *((volatile unsigned int*)(0x424E0384UL)) +#define bFM3_ADC0_PCFD_PC2 *((volatile unsigned int*)(0x424E0388UL)) +#define bFM3_ADC0_PCFD_PC3 *((volatile unsigned int*)(0x424E038CUL)) +#define bFM3_ADC0_PCFD_PC4 *((volatile unsigned int*)(0x424E0390UL)) +#define bFM3_ADC0_PCFD_RS0 *((volatile unsigned int*)(0x424E03A0UL)) +#define bFM3_ADC0_PCFD_RS1 *((volatile unsigned int*)(0x424E03A4UL)) +#define bFM3_ADC0_PCFD_RS2 *((volatile unsigned int*)(0x424E03A8UL)) +#define bFM3_ADC0_PCFD_INVL *((volatile unsigned int*)(0x424E03B0UL)) +#define bFM3_ADC0_PCFD_PD0 *((volatile unsigned int*)(0x424E03D0UL)) +#define bFM3_ADC0_PCFD_PD1 *((volatile unsigned int*)(0x424E03D4UL)) +#define bFM3_ADC0_PCFD_PD2 *((volatile unsigned int*)(0x424E03D8UL)) +#define bFM3_ADC0_PCFD_PD3 *((volatile unsigned int*)(0x424E03DCUL)) +#define bFM3_ADC0_PCFD_PD4 *((volatile unsigned int*)(0x424E03E0UL)) +#define bFM3_ADC0_PCFD_PD5 *((volatile unsigned int*)(0x424E03E4UL)) +#define bFM3_ADC0_PCFD_PD6 *((volatile unsigned int*)(0x424E03E8UL)) +#define bFM3_ADC0_PCFD_PD7 *((volatile unsigned int*)(0x424E03ECUL)) +#define bFM3_ADC0_PCFD_PD8 *((volatile unsigned int*)(0x424E03F0UL)) +#define bFM3_ADC0_PCFD_PD9 *((volatile unsigned int*)(0x424E03F4UL)) +#define bFM3_ADC0_PCFD_PD10 *((volatile unsigned int*)(0x424E03F8UL)) +#define bFM3_ADC0_PCFD_PD11 *((volatile unsigned int*)(0x424E03FCUL)) +#define bFM3_ADC0_PCFDL_PC0 *((volatile unsigned int*)(0x424E0380UL)) +#define bFM3_ADC0_PCFDL_PC1 *((volatile unsigned int*)(0x424E0384UL)) +#define bFM3_ADC0_PCFDL_PC2 *((volatile unsigned int*)(0x424E0388UL)) +#define bFM3_ADC0_PCFDL_PC3 *((volatile unsigned int*)(0x424E038CUL)) +#define bFM3_ADC0_PCFDL_PC4 *((volatile unsigned int*)(0x424E0390UL)) +#define bFM3_ADC0_PCFDL_RS0 *((volatile unsigned int*)(0x424E03A0UL)) +#define bFM3_ADC0_PCFDL_RS1 *((volatile unsigned int*)(0x424E03A4UL)) +#define bFM3_ADC0_PCFDL_RS2 *((volatile unsigned int*)(0x424E03A8UL)) +#define bFM3_ADC0_PCFDL_INVL *((volatile unsigned int*)(0x424E03B0UL)) +#define bFM3_ADC0_PCFDH_PD0 *((volatile unsigned int*)(0x424E03D0UL)) +#define bFM3_ADC0_PCFDH_PD1 *((volatile unsigned int*)(0x424E03D4UL)) +#define bFM3_ADC0_PCFDH_PD2 *((volatile unsigned int*)(0x424E03D8UL)) +#define bFM3_ADC0_PCFDH_PD3 *((volatile unsigned int*)(0x424E03DCUL)) +#define bFM3_ADC0_PCFDH_PD4 *((volatile unsigned int*)(0x424E03E0UL)) +#define bFM3_ADC0_PCFDH_PD5 *((volatile unsigned int*)(0x424E03E4UL)) +#define bFM3_ADC0_PCFDH_PD6 *((volatile unsigned int*)(0x424E03E8UL)) +#define bFM3_ADC0_PCFDH_PD7 *((volatile unsigned int*)(0x424E03ECUL)) +#define bFM3_ADC0_PCFDH_PD8 *((volatile unsigned int*)(0x424E03F0UL)) +#define bFM3_ADC0_PCFDH_PD9 *((volatile unsigned int*)(0x424E03F4UL)) +#define bFM3_ADC0_PCFDH_PD10 *((volatile unsigned int*)(0x424E03F8UL)) +#define bFM3_ADC0_PCFDH_PD11 *((volatile unsigned int*)(0x424E03FCUL)) +#define bFM3_ADC0_PCIS_P1A0 *((volatile unsigned int*)(0x424E0400UL)) +#define bFM3_ADC0_PCIS_P1A1 *((volatile unsigned int*)(0x424E0404UL)) +#define bFM3_ADC0_PCIS_P1A2 *((volatile unsigned int*)(0x424E0408UL)) +#define bFM3_ADC0_PCIS_P2A0 *((volatile unsigned int*)(0x424E040CUL)) +#define bFM3_ADC0_PCIS_P2A1 *((volatile unsigned int*)(0x424E0410UL)) +#define bFM3_ADC0_PCIS_P2A2 *((volatile unsigned int*)(0x424E0414UL)) +#define bFM3_ADC0_PCIS_P2A3 *((volatile unsigned int*)(0x424E0418UL)) +#define bFM3_ADC0_PCIS_P2A4 *((volatile unsigned int*)(0x424E041CUL)) +#define bFM3_ADC0_CMPCR_CCH0 *((volatile unsigned int*)(0x424E0480UL)) +#define bFM3_ADC0_CMPCR_CCH1 *((volatile unsigned int*)(0x424E0484UL)) +#define bFM3_ADC0_CMPCR_CCH2 *((volatile unsigned int*)(0x424E0488UL)) +#define bFM3_ADC0_CMPCR_CCH3 *((volatile unsigned int*)(0x424E048CUL)) +#define bFM3_ADC0_CMPCR_CCH4 *((volatile unsigned int*)(0x424E0490UL)) +#define bFM3_ADC0_CMPCR_CMD0 *((volatile unsigned int*)(0x424E0494UL)) +#define bFM3_ADC0_CMPCR_CMD1 *((volatile unsigned int*)(0x424E0498UL)) +#define bFM3_ADC0_CMPCR_CMPEN *((volatile unsigned int*)(0x424E049CUL)) +#define bFM3_ADC0_CMPD_CMAD2 *((volatile unsigned int*)(0x424E04D8UL)) +#define bFM3_ADC0_CMPD_CMAD3 *((volatile unsigned int*)(0x424E04DCUL)) +#define bFM3_ADC0_CMPD_CMAD4 *((volatile unsigned int*)(0x424E04E0UL)) +#define bFM3_ADC0_CMPD_CMAD5 *((volatile unsigned int*)(0x424E04E4UL)) +#define bFM3_ADC0_CMPD_CMAD6 *((volatile unsigned int*)(0x424E04E8UL)) +#define bFM3_ADC0_CMPD_CMAD7 *((volatile unsigned int*)(0x424E04ECUL)) +#define bFM3_ADC0_CMPD_CMAD8 *((volatile unsigned int*)(0x424E04F0UL)) +#define bFM3_ADC0_CMPD_CMAD9 *((volatile unsigned int*)(0x424E04F4UL)) +#define bFM3_ADC0_CMPD_CMAD10 *((volatile unsigned int*)(0x424E04F8UL)) +#define bFM3_ADC0_CMPD_CMAD11 *((volatile unsigned int*)(0x424E04FCUL)) +#define bFM3_ADC0_ADSS23_TS16 *((volatile unsigned int*)(0x424E0500UL)) +#define bFM3_ADC0_ADSS23_TS17 *((volatile unsigned int*)(0x424E0504UL)) +#define bFM3_ADC0_ADSS23_TS18 *((volatile unsigned int*)(0x424E0508UL)) +#define bFM3_ADC0_ADSS23_TS19 *((volatile unsigned int*)(0x424E050CUL)) +#define bFM3_ADC0_ADSS23_TS20 *((volatile unsigned int*)(0x424E0510UL)) +#define bFM3_ADC0_ADSS23_TS21 *((volatile unsigned int*)(0x424E0514UL)) +#define bFM3_ADC0_ADSS23_TS22 *((volatile unsigned int*)(0x424E0518UL)) +#define bFM3_ADC0_ADSS23_TS23 *((volatile unsigned int*)(0x424E051CUL)) +#define bFM3_ADC0_ADSS23_TS24 *((volatile unsigned int*)(0x424E0520UL)) +#define bFM3_ADC0_ADSS23_TS25 *((volatile unsigned int*)(0x424E0524UL)) +#define bFM3_ADC0_ADSS23_TS26 *((volatile unsigned int*)(0x424E0528UL)) +#define bFM3_ADC0_ADSS23_TS27 *((volatile unsigned int*)(0x424E052CUL)) +#define bFM3_ADC0_ADSS23_TS28 *((volatile unsigned int*)(0x424E0530UL)) +#define bFM3_ADC0_ADSS23_TS29 *((volatile unsigned int*)(0x424E0534UL)) +#define bFM3_ADC0_ADSS23_TS30 *((volatile unsigned int*)(0x424E0538UL)) +#define bFM3_ADC0_ADSS23_TS31 *((volatile unsigned int*)(0x424E053CUL)) +#define bFM3_ADC0_ADSS2_TS16 *((volatile unsigned int*)(0x424E0500UL)) +#define bFM3_ADC0_ADSS2_TS17 *((volatile unsigned int*)(0x424E0504UL)) +#define bFM3_ADC0_ADSS2_TS18 *((volatile unsigned int*)(0x424E0508UL)) +#define bFM3_ADC0_ADSS2_TS19 *((volatile unsigned int*)(0x424E050CUL)) +#define bFM3_ADC0_ADSS2_TS20 *((volatile unsigned int*)(0x424E0510UL)) +#define bFM3_ADC0_ADSS2_TS21 *((volatile unsigned int*)(0x424E0514UL)) +#define bFM3_ADC0_ADSS2_TS22 *((volatile unsigned int*)(0x424E0518UL)) +#define bFM3_ADC0_ADSS2_TS23 *((volatile unsigned int*)(0x424E051CUL)) +#define bFM3_ADC0_ADSS3_TS24 *((volatile unsigned int*)(0x424E0520UL)) +#define bFM3_ADC0_ADSS3_TS25 *((volatile unsigned int*)(0x424E0524UL)) +#define bFM3_ADC0_ADSS3_TS26 *((volatile unsigned int*)(0x424E0528UL)) +#define bFM3_ADC0_ADSS3_TS27 *((volatile unsigned int*)(0x424E052CUL)) +#define bFM3_ADC0_ADSS3_TS28 *((volatile unsigned int*)(0x424E0530UL)) +#define bFM3_ADC0_ADSS3_TS29 *((volatile unsigned int*)(0x424E0534UL)) +#define bFM3_ADC0_ADSS3_TS30 *((volatile unsigned int*)(0x424E0538UL)) +#define bFM3_ADC0_ADSS3_TS31 *((volatile unsigned int*)(0x424E053CUL)) +#define bFM3_ADC0_ADSS01_TS0 *((volatile unsigned int*)(0x424E0580UL)) +#define bFM3_ADC0_ADSS01_TS1 *((volatile unsigned int*)(0x424E0584UL)) +#define bFM3_ADC0_ADSS01_TS2 *((volatile unsigned int*)(0x424E0588UL)) +#define bFM3_ADC0_ADSS01_TS3 *((volatile unsigned int*)(0x424E058CUL)) +#define bFM3_ADC0_ADSS01_TS4 *((volatile unsigned int*)(0x424E0590UL)) +#define bFM3_ADC0_ADSS01_TS5 *((volatile unsigned int*)(0x424E0594UL)) +#define bFM3_ADC0_ADSS01_TS6 *((volatile unsigned int*)(0x424E0598UL)) +#define bFM3_ADC0_ADSS01_TS7 *((volatile unsigned int*)(0x424E059CUL)) +#define bFM3_ADC0_ADSS01_TS8 *((volatile unsigned int*)(0x424E05A0UL)) +#define bFM3_ADC0_ADSS01_TS9 *((volatile unsigned int*)(0x424E05A4UL)) +#define bFM3_ADC0_ADSS01_TS10 *((volatile unsigned int*)(0x424E05A8UL)) +#define bFM3_ADC0_ADSS01_TS11 *((volatile unsigned int*)(0x424E05ACUL)) +#define bFM3_ADC0_ADSS01_TS12 *((volatile unsigned int*)(0x424E05B0UL)) +#define bFM3_ADC0_ADSS01_TS13 *((volatile unsigned int*)(0x424E05B4UL)) +#define bFM3_ADC0_ADSS01_TS14 *((volatile unsigned int*)(0x424E05B8UL)) +#define bFM3_ADC0_ADSS01_TS15 *((volatile unsigned int*)(0x424E05BCUL)) +#define bFM3_ADC0_ADSS0_TS0 *((volatile unsigned int*)(0x424E0580UL)) +#define bFM3_ADC0_ADSS0_TS1 *((volatile unsigned int*)(0x424E0584UL)) +#define bFM3_ADC0_ADSS0_TS2 *((volatile unsigned int*)(0x424E0588UL)) +#define bFM3_ADC0_ADSS0_TS3 *((volatile unsigned int*)(0x424E058CUL)) +#define bFM3_ADC0_ADSS0_TS4 *((volatile unsigned int*)(0x424E0590UL)) +#define bFM3_ADC0_ADSS0_TS5 *((volatile unsigned int*)(0x424E0594UL)) +#define bFM3_ADC0_ADSS0_TS6 *((volatile unsigned int*)(0x424E0598UL)) +#define bFM3_ADC0_ADSS0_TS7 *((volatile unsigned int*)(0x424E059CUL)) +#define bFM3_ADC0_ADSS1_TS8 *((volatile unsigned int*)(0x424E05A0UL)) +#define bFM3_ADC0_ADSS1_TS9 *((volatile unsigned int*)(0x424E05A4UL)) +#define bFM3_ADC0_ADSS1_TS10 *((volatile unsigned int*)(0x424E05A8UL)) +#define bFM3_ADC0_ADSS1_TS11 *((volatile unsigned int*)(0x424E05ACUL)) +#define bFM3_ADC0_ADSS1_TS12 *((volatile unsigned int*)(0x424E05B0UL)) +#define bFM3_ADC0_ADSS1_TS13 *((volatile unsigned int*)(0x424E05B4UL)) +#define bFM3_ADC0_ADSS1_TS14 *((volatile unsigned int*)(0x424E05B8UL)) +#define bFM3_ADC0_ADSS1_TS15 *((volatile unsigned int*)(0x424E05BCUL)) +#define bFM3_ADC0_ADST01_ST10 *((volatile unsigned int*)(0x424E0600UL)) +#define bFM3_ADC0_ADST01_ST11 *((volatile unsigned int*)(0x424E0604UL)) +#define bFM3_ADC0_ADST01_ST12 *((volatile unsigned int*)(0x424E0608UL)) +#define bFM3_ADC0_ADST01_ST13 *((volatile unsigned int*)(0x424E060CUL)) +#define bFM3_ADC0_ADST01_ST14 *((volatile unsigned int*)(0x424E0610UL)) +#define bFM3_ADC0_ADST01_STX10 *((volatile unsigned int*)(0x424E0614UL)) +#define bFM3_ADC0_ADST01_STX11 *((volatile unsigned int*)(0x424E0618UL)) +#define bFM3_ADC0_ADST01_STX12 *((volatile unsigned int*)(0x424E061CUL)) +#define bFM3_ADC0_ADST01_ST00 *((volatile unsigned int*)(0x424E0620UL)) +#define bFM3_ADC0_ADST01_ST01 *((volatile unsigned int*)(0x424E0624UL)) +#define bFM3_ADC0_ADST01_ST02 *((volatile unsigned int*)(0x424E0628UL)) +#define bFM3_ADC0_ADST01_ST03 *((volatile unsigned int*)(0x424E062CUL)) +#define bFM3_ADC0_ADST01_ST04 *((volatile unsigned int*)(0x424E0630UL)) +#define bFM3_ADC0_ADST01_STX00 *((volatile unsigned int*)(0x424E0634UL)) +#define bFM3_ADC0_ADST01_STX01 *((volatile unsigned int*)(0x424E0638UL)) +#define bFM3_ADC0_ADST01_STX02 *((volatile unsigned int*)(0x424E063CUL)) +#define bFM3_ADC0_ADST1_ST10 *((volatile unsigned int*)(0x424E0600UL)) +#define bFM3_ADC0_ADST1_ST11 *((volatile unsigned int*)(0x424E0604UL)) +#define bFM3_ADC0_ADST1_ST12 *((volatile unsigned int*)(0x424E0608UL)) +#define bFM3_ADC0_ADST1_ST13 *((volatile unsigned int*)(0x424E060CUL)) +#define bFM3_ADC0_ADST1_ST14 *((volatile unsigned int*)(0x424E0610UL)) +#define bFM3_ADC0_ADST1_STX10 *((volatile unsigned int*)(0x424E0614UL)) +#define bFM3_ADC0_ADST1_STX11 *((volatile unsigned int*)(0x424E0618UL)) +#define bFM3_ADC0_ADST1_STX12 *((volatile unsigned int*)(0x424E061CUL)) +#define bFM3_ADC0_ADST0_ST00 *((volatile unsigned int*)(0x424E0620UL)) +#define bFM3_ADC0_ADST0_ST01 *((volatile unsigned int*)(0x424E0624UL)) +#define bFM3_ADC0_ADST0_ST02 *((volatile unsigned int*)(0x424E0628UL)) +#define bFM3_ADC0_ADST0_ST03 *((volatile unsigned int*)(0x424E062CUL)) +#define bFM3_ADC0_ADST0_ST04 *((volatile unsigned int*)(0x424E0630UL)) +#define bFM3_ADC0_ADST0_STX00 *((volatile unsigned int*)(0x424E0634UL)) +#define bFM3_ADC0_ADST0_STX01 *((volatile unsigned int*)(0x424E0638UL)) +#define bFM3_ADC0_ADST0_STX02 *((volatile unsigned int*)(0x424E063CUL)) +#define bFM3_ADC0_ADCT_CT0 *((volatile unsigned int*)(0x424E0680UL)) +#define bFM3_ADC0_ADCT_CT1 *((volatile unsigned int*)(0x424E0684UL)) +#define bFM3_ADC0_ADCT_CT2 *((volatile unsigned int*)(0x424E0688UL)) +#define bFM3_ADC0_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E0700UL)) +#define bFM3_ADC0_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E0704UL)) +#define bFM3_ADC0_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E0708UL)) +#define bFM3_ADC0_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E070CUL)) +#define bFM3_ADC0_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E0720UL)) +#define bFM3_ADC0_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E0724UL)) +#define bFM3_ADC0_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E0728UL)) +#define bFM3_ADC0_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E072CUL)) +#define bFM3_ADC0_ADCEN_ENBL *((volatile unsigned int*)(0x424E0780UL)) +#define bFM3_ADC0_ADCEN_READY *((volatile unsigned int*)(0x424E0784UL)) + +/* 12-bit ADC unit 1 registers */ +#define bFM3_ADC1_ADSR_SCS *((volatile unsigned int*)(0x424E2000UL)) +#define bFM3_ADC1_ADSR_PCS *((volatile unsigned int*)(0x424E2004UL)) +#define bFM3_ADC1_ADSR_PCNS *((volatile unsigned int*)(0x424E2008UL)) +#define bFM3_ADC1_ADSR_FDAS *((volatile unsigned int*)(0x424E2018UL)) +#define bFM3_ADC1_ADSR_ADSTP *((volatile unsigned int*)(0x424E201CUL)) +#define bFM3_ADC1_ADCR_OVRIE *((volatile unsigned int*)(0x424E2020UL)) +#define bFM3_ADC1_ADCR_CMPIE *((volatile unsigned int*)(0x424E2024UL)) +#define bFM3_ADC1_ADCR_PCIE *((volatile unsigned int*)(0x424E2028UL)) +#define bFM3_ADC1_ADCR_SCIE *((volatile unsigned int*)(0x424E202CUL)) +#define bFM3_ADC1_ADCR_CMPIF *((volatile unsigned int*)(0x424E2034UL)) +#define bFM3_ADC1_ADCR_PCIF *((volatile unsigned int*)(0x424E2038UL)) +#define bFM3_ADC1_ADCR_SCIF *((volatile unsigned int*)(0x424E203CUL)) +#define bFM3_ADC1_SFNS_SFS0 *((volatile unsigned int*)(0x424E2100UL)) +#define bFM3_ADC1_SFNS_SFS1 *((volatile unsigned int*)(0x424E2104UL)) +#define bFM3_ADC1_SFNS_SFS2 *((volatile unsigned int*)(0x424E2108UL)) +#define bFM3_ADC1_SFNS_SFS3 *((volatile unsigned int*)(0x424E210CUL)) +#define bFM3_ADC1_SCCR_SSTR *((volatile unsigned int*)(0x424E2120UL)) +#define bFM3_ADC1_SCCR_SHEN *((volatile unsigned int*)(0x424E2124UL)) +#define bFM3_ADC1_SCCR_RPT *((volatile unsigned int*)(0x424E2128UL)) +#define bFM3_ADC1_SCCR_SFCLR *((volatile unsigned int*)(0x424E2130UL)) +#define bFM3_ADC1_SCCR_SOVR *((volatile unsigned int*)(0x424E2134UL)) +#define bFM3_ADC1_SCCR_SFUL *((volatile unsigned int*)(0x424E2138UL)) +#define bFM3_ADC1_SCCR_SEMP *((volatile unsigned int*)(0x424E213CUL)) +#define bFM3_ADC1_SCFD_SC0 *((volatile unsigned int*)(0x424E2180UL)) +#define bFM3_ADC1_SCFD_SC1 *((volatile unsigned int*)(0x424E2184UL)) +#define bFM3_ADC1_SCFD_SC2 *((volatile unsigned int*)(0x424E2188UL)) +#define bFM3_ADC1_SCFD_SC3 *((volatile unsigned int*)(0x424E218CUL)) +#define bFM3_ADC1_SCFD_SC4 *((volatile unsigned int*)(0x424E2190UL)) +#define bFM3_ADC1_SCFD_RS0 *((volatile unsigned int*)(0x424E21A0UL)) +#define bFM3_ADC1_SCFD_RS1 *((volatile unsigned int*)(0x424E21A4UL)) +#define bFM3_ADC1_SCFD_INVL *((volatile unsigned int*)(0x424E21B0UL)) +#define bFM3_ADC1_SCFD_SD0 *((volatile unsigned int*)(0x424E21D0UL)) +#define bFM3_ADC1_SCFD_SD1 *((volatile unsigned int*)(0x424E21D4UL)) +#define bFM3_ADC1_SCFD_SD2 *((volatile unsigned int*)(0x424E21D8UL)) +#define bFM3_ADC1_SCFD_SD3 *((volatile unsigned int*)(0x424E21DCUL)) +#define bFM3_ADC1_SCFD_SD4 *((volatile unsigned int*)(0x424E21E0UL)) +#define bFM3_ADC1_SCFD_SD5 *((volatile unsigned int*)(0x424E21E4UL)) +#define bFM3_ADC1_SCFD_SD6 *((volatile unsigned int*)(0x424E21E8UL)) +#define bFM3_ADC1_SCFD_SD7 *((volatile unsigned int*)(0x424E21ECUL)) +#define bFM3_ADC1_SCFD_SD8 *((volatile unsigned int*)(0x424E21F0UL)) +#define bFM3_ADC1_SCFD_SD9 *((volatile unsigned int*)(0x424E21F4UL)) +#define bFM3_ADC1_SCFD_SD10 *((volatile unsigned int*)(0x424E21F8UL)) +#define bFM3_ADC1_SCFD_SD11 *((volatile unsigned int*)(0x424E21FCUL)) +#define bFM3_ADC1_SCFDL_SC0 *((volatile unsigned int*)(0x424E2180UL)) +#define bFM3_ADC1_SCFDL_SC1 *((volatile unsigned int*)(0x424E2184UL)) +#define bFM3_ADC1_SCFDL_SC2 *((volatile unsigned int*)(0x424E2188UL)) +#define bFM3_ADC1_SCFDL_SC3 *((volatile unsigned int*)(0x424E218CUL)) +#define bFM3_ADC1_SCFDL_SC4 *((volatile unsigned int*)(0x424E2190UL)) +#define bFM3_ADC1_SCFDL_RS0 *((volatile unsigned int*)(0x424E21A0UL)) +#define bFM3_ADC1_SCFDL_RS1 *((volatile unsigned int*)(0x424E21A4UL)) +#define bFM3_ADC1_SCFDL_INVL *((volatile unsigned int*)(0x424E21B0UL)) +#define bFM3_ADC1_SCFDH_SD0 *((volatile unsigned int*)(0x424E21D0UL)) +#define bFM3_ADC1_SCFDH_SD1 *((volatile unsigned int*)(0x424E21D4UL)) +#define bFM3_ADC1_SCFDH_SD2 *((volatile unsigned int*)(0x424E21D8UL)) +#define bFM3_ADC1_SCFDH_SD3 *((volatile unsigned int*)(0x424E21DCUL)) +#define bFM3_ADC1_SCFDH_SD4 *((volatile unsigned int*)(0x424E21E0UL)) +#define bFM3_ADC1_SCFDH_SD5 *((volatile unsigned int*)(0x424E21E4UL)) +#define bFM3_ADC1_SCFDH_SD6 *((volatile unsigned int*)(0x424E21E8UL)) +#define bFM3_ADC1_SCFDH_SD7 *((volatile unsigned int*)(0x424E21ECUL)) +#define bFM3_ADC1_SCFDH_SD8 *((volatile unsigned int*)(0x424E21F0UL)) +#define bFM3_ADC1_SCFDH_SD9 *((volatile unsigned int*)(0x424E21F4UL)) +#define bFM3_ADC1_SCFDH_SD10 *((volatile unsigned int*)(0x424E21F8UL)) +#define bFM3_ADC1_SCFDH_SD11 *((volatile unsigned int*)(0x424E21FCUL)) +#define bFM3_ADC1_SCIS23_AN16 *((volatile unsigned int*)(0x424E2200UL)) +#define bFM3_ADC1_SCIS23_AN17 *((volatile unsigned int*)(0x424E2204UL)) +#define bFM3_ADC1_SCIS23_AN18 *((volatile unsigned int*)(0x424E2208UL)) +#define bFM3_ADC1_SCIS23_AN19 *((volatile unsigned int*)(0x424E220CUL)) +#define bFM3_ADC1_SCIS23_AN20 *((volatile unsigned int*)(0x424E2210UL)) +#define bFM3_ADC1_SCIS23_AN21 *((volatile unsigned int*)(0x424E2214UL)) +#define bFM3_ADC1_SCIS23_AN22 *((volatile unsigned int*)(0x424E2218UL)) +#define bFM3_ADC1_SCIS23_AN23 *((volatile unsigned int*)(0x424E221CUL)) +#define bFM3_ADC1_SCIS23_AN24 *((volatile unsigned int*)(0x424E2220UL)) +#define bFM3_ADC1_SCIS23_AN25 *((volatile unsigned int*)(0x424E2224UL)) +#define bFM3_ADC1_SCIS23_AN26 *((volatile unsigned int*)(0x424E2228UL)) +#define bFM3_ADC1_SCIS23_AN27 *((volatile unsigned int*)(0x424E222CUL)) +#define bFM3_ADC1_SCIS23_AN28 *((volatile unsigned int*)(0x424E2230UL)) +#define bFM3_ADC1_SCIS23_AN29 *((volatile unsigned int*)(0x424E2234UL)) +#define bFM3_ADC1_SCIS23_AN30 *((volatile unsigned int*)(0x424E2238UL)) +#define bFM3_ADC1_SCIS23_AN31 *((volatile unsigned int*)(0x424E223CUL)) +#define bFM3_ADC1_SCIS2_AN16 *((volatile unsigned int*)(0x424E2200UL)) +#define bFM3_ADC1_SCIS2_AN17 *((volatile unsigned int*)(0x424E2204UL)) +#define bFM3_ADC1_SCIS2_AN18 *((volatile unsigned int*)(0x424E2208UL)) +#define bFM3_ADC1_SCIS2_AN19 *((volatile unsigned int*)(0x424E220CUL)) +#define bFM3_ADC1_SCIS2_AN20 *((volatile unsigned int*)(0x424E2210UL)) +#define bFM3_ADC1_SCIS2_AN21 *((volatile unsigned int*)(0x424E2214UL)) +#define bFM3_ADC1_SCIS2_AN22 *((volatile unsigned int*)(0x424E2218UL)) +#define bFM3_ADC1_SCIS2_AN23 *((volatile unsigned int*)(0x424E221CUL)) +#define bFM3_ADC1_SCIS3_AN24 *((volatile unsigned int*)(0x424E2220UL)) +#define bFM3_ADC1_SCIS3_AN25 *((volatile unsigned int*)(0x424E2224UL)) +#define bFM3_ADC1_SCIS3_AN26 *((volatile unsigned int*)(0x424E2228UL)) +#define bFM3_ADC1_SCIS3_AN27 *((volatile unsigned int*)(0x424E222CUL)) +#define bFM3_ADC1_SCIS3_AN28 *((volatile unsigned int*)(0x424E2230UL)) +#define bFM3_ADC1_SCIS3_AN29 *((volatile unsigned int*)(0x424E2234UL)) +#define bFM3_ADC1_SCIS3_AN30 *((volatile unsigned int*)(0x424E2238UL)) +#define bFM3_ADC1_SCIS3_AN31 *((volatile unsigned int*)(0x424E223CUL)) +#define bFM3_ADC1_SCIS01_AN0 *((volatile unsigned int*)(0x424E2280UL)) +#define bFM3_ADC1_SCIS01_AN1 *((volatile unsigned int*)(0x424E2284UL)) +#define bFM3_ADC1_SCIS01_AN2 *((volatile unsigned int*)(0x424E2288UL)) +#define bFM3_ADC1_SCIS01_AN3 *((volatile unsigned int*)(0x424E228CUL)) +#define bFM3_ADC1_SCIS01_AN4 *((volatile unsigned int*)(0x424E2290UL)) +#define bFM3_ADC1_SCIS01_AN5 *((volatile unsigned int*)(0x424E2294UL)) +#define bFM3_ADC1_SCIS01_AN6 *((volatile unsigned int*)(0x424E2298UL)) +#define bFM3_ADC1_SCIS01_AN7 *((volatile unsigned int*)(0x424E229CUL)) +#define bFM3_ADC1_SCIS01_AN8 *((volatile unsigned int*)(0x424E22A0UL)) +#define bFM3_ADC1_SCIS01_AN9 *((volatile unsigned int*)(0x424E22A4UL)) +#define bFM3_ADC1_SCIS01_AN10 *((volatile unsigned int*)(0x424E22A8UL)) +#define bFM3_ADC1_SCIS01_AN11 *((volatile unsigned int*)(0x424E22ACUL)) +#define bFM3_ADC1_SCIS01_AN12 *((volatile unsigned int*)(0x424E22B0UL)) +#define bFM3_ADC1_SCIS01_AN13 *((volatile unsigned int*)(0x424E22B4UL)) +#define bFM3_ADC1_SCIS01_AN14 *((volatile unsigned int*)(0x424E22B8UL)) +#define bFM3_ADC1_SCIS01_AN15 *((volatile unsigned int*)(0x424E22BCUL)) +#define bFM3_ADC1_SCIS0_AN0 *((volatile unsigned int*)(0x424E2280UL)) +#define bFM3_ADC1_SCIS0_AN1 *((volatile unsigned int*)(0x424E2284UL)) +#define bFM3_ADC1_SCIS0_AN2 *((volatile unsigned int*)(0x424E2288UL)) +#define bFM3_ADC1_SCIS0_AN3 *((volatile unsigned int*)(0x424E228CUL)) +#define bFM3_ADC1_SCIS0_AN4 *((volatile unsigned int*)(0x424E2290UL)) +#define bFM3_ADC1_SCIS0_AN5 *((volatile unsigned int*)(0x424E2294UL)) +#define bFM3_ADC1_SCIS0_AN6 *((volatile unsigned int*)(0x424E2298UL)) +#define bFM3_ADC1_SCIS0_AN7 *((volatile unsigned int*)(0x424E229CUL)) +#define bFM3_ADC1_SCIS1_AN8 *((volatile unsigned int*)(0x424E22A0UL)) +#define bFM3_ADC1_SCIS1_AN9 *((volatile unsigned int*)(0x424E22A4UL)) +#define bFM3_ADC1_SCIS1_AN10 *((volatile unsigned int*)(0x424E22A8UL)) +#define bFM3_ADC1_SCIS1_AN11 *((volatile unsigned int*)(0x424E22ACUL)) +#define bFM3_ADC1_SCIS1_AN12 *((volatile unsigned int*)(0x424E22B0UL)) +#define bFM3_ADC1_SCIS1_AN13 *((volatile unsigned int*)(0x424E22B4UL)) +#define bFM3_ADC1_SCIS1_AN14 *((volatile unsigned int*)(0x424E22B8UL)) +#define bFM3_ADC1_SCIS1_AN15 *((volatile unsigned int*)(0x424E22BCUL)) +#define bFM3_ADC1_PFNS_PFS0 *((volatile unsigned int*)(0x424E2300UL)) +#define bFM3_ADC1_PFNS_PFS1 *((volatile unsigned int*)(0x424E2304UL)) +#define bFM3_ADC1_PFNS_TEST0 *((volatile unsigned int*)(0x424E2310UL)) +#define bFM3_ADC1_PFNS_TEST1 *((volatile unsigned int*)(0x424E2314UL)) +#define bFM3_ADC1_PCCR_PSTR *((volatile unsigned int*)(0x424E2320UL)) +#define bFM3_ADC1_PCCR_PHEN *((volatile unsigned int*)(0x424E2324UL)) +#define bFM3_ADC1_PCCR_PEEN *((volatile unsigned int*)(0x424E2328UL)) +#define bFM3_ADC1_PCCR_ESCE *((volatile unsigned int*)(0x424E232CUL)) +#define bFM3_ADC1_PCCR_PFCLR *((volatile unsigned int*)(0x424E2330UL)) +#define bFM3_ADC1_PCCR_POVR *((volatile unsigned int*)(0x424E2334UL)) +#define bFM3_ADC1_PCCR_PFUL *((volatile unsigned int*)(0x424E2338UL)) +#define bFM3_ADC1_PCCR_PEMP *((volatile unsigned int*)(0x424E233CUL)) +#define bFM3_ADC1_PCFD_PC0 *((volatile unsigned int*)(0x424E2380UL)) +#define bFM3_ADC1_PCFD_PC1 *((volatile unsigned int*)(0x424E2384UL)) +#define bFM3_ADC1_PCFD_PC2 *((volatile unsigned int*)(0x424E2388UL)) +#define bFM3_ADC1_PCFD_PC3 *((volatile unsigned int*)(0x424E238CUL)) +#define bFM3_ADC1_PCFD_PC4 *((volatile unsigned int*)(0x424E2390UL)) +#define bFM3_ADC1_PCFD_RS0 *((volatile unsigned int*)(0x424E23A0UL)) +#define bFM3_ADC1_PCFD_RS1 *((volatile unsigned int*)(0x424E23A4UL)) +#define bFM3_ADC1_PCFD_RS2 *((volatile unsigned int*)(0x424E23A8UL)) +#define bFM3_ADC1_PCFD_INVL *((volatile unsigned int*)(0x424E23B0UL)) +#define bFM3_ADC1_PCFD_PD0 *((volatile unsigned int*)(0x424E23D0UL)) +#define bFM3_ADC1_PCFD_PD1 *((volatile unsigned int*)(0x424E23D4UL)) +#define bFM3_ADC1_PCFD_PD2 *((volatile unsigned int*)(0x424E23D8UL)) +#define bFM3_ADC1_PCFD_PD3 *((volatile unsigned int*)(0x424E23DCUL)) +#define bFM3_ADC1_PCFD_PD4 *((volatile unsigned int*)(0x424E23E0UL)) +#define bFM3_ADC1_PCFD_PD5 *((volatile unsigned int*)(0x424E23E4UL)) +#define bFM3_ADC1_PCFD_PD6 *((volatile unsigned int*)(0x424E23E8UL)) +#define bFM3_ADC1_PCFD_PD7 *((volatile unsigned int*)(0x424E23ECUL)) +#define bFM3_ADC1_PCFD_PD8 *((volatile unsigned int*)(0x424E23F0UL)) +#define bFM3_ADC1_PCFD_PD9 *((volatile unsigned int*)(0x424E23F4UL)) +#define bFM3_ADC1_PCFD_PD10 *((volatile unsigned int*)(0x424E23F8UL)) +#define bFM3_ADC1_PCFD_PD11 *((volatile unsigned int*)(0x424E23FCUL)) +#define bFM3_ADC1_PCFDL_PC0 *((volatile unsigned int*)(0x424E2380UL)) +#define bFM3_ADC1_PCFDL_PC1 *((volatile unsigned int*)(0x424E2384UL)) +#define bFM3_ADC1_PCFDL_PC2 *((volatile unsigned int*)(0x424E2388UL)) +#define bFM3_ADC1_PCFDL_PC3 *((volatile unsigned int*)(0x424E238CUL)) +#define bFM3_ADC1_PCFDL_PC4 *((volatile unsigned int*)(0x424E2390UL)) +#define bFM3_ADC1_PCFDL_RS0 *((volatile unsigned int*)(0x424E23A0UL)) +#define bFM3_ADC1_PCFDL_RS1 *((volatile unsigned int*)(0x424E23A4UL)) +#define bFM3_ADC1_PCFDL_RS2 *((volatile unsigned int*)(0x424E23A8UL)) +#define bFM3_ADC1_PCFDL_INVL *((volatile unsigned int*)(0x424E23B0UL)) +#define bFM3_ADC1_PCFDH_PD0 *((volatile unsigned int*)(0x424E23D0UL)) +#define bFM3_ADC1_PCFDH_PD1 *((volatile unsigned int*)(0x424E23D4UL)) +#define bFM3_ADC1_PCFDH_PD2 *((volatile unsigned int*)(0x424E23D8UL)) +#define bFM3_ADC1_PCFDH_PD3 *((volatile unsigned int*)(0x424E23DCUL)) +#define bFM3_ADC1_PCFDH_PD4 *((volatile unsigned int*)(0x424E23E0UL)) +#define bFM3_ADC1_PCFDH_PD5 *((volatile unsigned int*)(0x424E23E4UL)) +#define bFM3_ADC1_PCFDH_PD6 *((volatile unsigned int*)(0x424E23E8UL)) +#define bFM3_ADC1_PCFDH_PD7 *((volatile unsigned int*)(0x424E23ECUL)) +#define bFM3_ADC1_PCFDH_PD8 *((volatile unsigned int*)(0x424E23F0UL)) +#define bFM3_ADC1_PCFDH_PD9 *((volatile unsigned int*)(0x424E23F4UL)) +#define bFM3_ADC1_PCFDH_PD10 *((volatile unsigned int*)(0x424E23F8UL)) +#define bFM3_ADC1_PCFDH_PD11 *((volatile unsigned int*)(0x424E23FCUL)) +#define bFM3_ADC1_PCIS_P1A0 *((volatile unsigned int*)(0x424E2400UL)) +#define bFM3_ADC1_PCIS_P1A1 *((volatile unsigned int*)(0x424E2404UL)) +#define bFM3_ADC1_PCIS_P1A2 *((volatile unsigned int*)(0x424E2408UL)) +#define bFM3_ADC1_PCIS_P2A0 *((volatile unsigned int*)(0x424E240CUL)) +#define bFM3_ADC1_PCIS_P2A1 *((volatile unsigned int*)(0x424E2410UL)) +#define bFM3_ADC1_PCIS_P2A2 *((volatile unsigned int*)(0x424E2414UL)) +#define bFM3_ADC1_PCIS_P2A3 *((volatile unsigned int*)(0x424E2418UL)) +#define bFM3_ADC1_PCIS_P2A4 *((volatile unsigned int*)(0x424E241CUL)) +#define bFM3_ADC1_CMPCR_CCH0 *((volatile unsigned int*)(0x424E2480UL)) +#define bFM3_ADC1_CMPCR_CCH1 *((volatile unsigned int*)(0x424E2484UL)) +#define bFM3_ADC1_CMPCR_CCH2 *((volatile unsigned int*)(0x424E2488UL)) +#define bFM3_ADC1_CMPCR_CCH3 *((volatile unsigned int*)(0x424E248CUL)) +#define bFM3_ADC1_CMPCR_CCH4 *((volatile unsigned int*)(0x424E2490UL)) +#define bFM3_ADC1_CMPCR_CMD0 *((volatile unsigned int*)(0x424E2494UL)) +#define bFM3_ADC1_CMPCR_CMD1 *((volatile unsigned int*)(0x424E2498UL)) +#define bFM3_ADC1_CMPCR_CMPEN *((volatile unsigned int*)(0x424E249CUL)) +#define bFM3_ADC1_CMPD_CMAD2 *((volatile unsigned int*)(0x424E24D8UL)) +#define bFM3_ADC1_CMPD_CMAD3 *((volatile unsigned int*)(0x424E24DCUL)) +#define bFM3_ADC1_CMPD_CMAD4 *((volatile unsigned int*)(0x424E24E0UL)) +#define bFM3_ADC1_CMPD_CMAD5 *((volatile unsigned int*)(0x424E24E4UL)) +#define bFM3_ADC1_CMPD_CMAD6 *((volatile unsigned int*)(0x424E24E8UL)) +#define bFM3_ADC1_CMPD_CMAD7 *((volatile unsigned int*)(0x424E24ECUL)) +#define bFM3_ADC1_CMPD_CMAD8 *((volatile unsigned int*)(0x424E24F0UL)) +#define bFM3_ADC1_CMPD_CMAD9 *((volatile unsigned int*)(0x424E24F4UL)) +#define bFM3_ADC1_CMPD_CMAD10 *((volatile unsigned int*)(0x424E24F8UL)) +#define bFM3_ADC1_CMPD_CMAD11 *((volatile unsigned int*)(0x424E24FCUL)) +#define bFM3_ADC1_ADSS23_TS16 *((volatile unsigned int*)(0x424E2500UL)) +#define bFM3_ADC1_ADSS23_TS17 *((volatile unsigned int*)(0x424E2504UL)) +#define bFM3_ADC1_ADSS23_TS18 *((volatile unsigned int*)(0x424E2508UL)) +#define bFM3_ADC1_ADSS23_TS19 *((volatile unsigned int*)(0x424E250CUL)) +#define bFM3_ADC1_ADSS23_TS20 *((volatile unsigned int*)(0x424E2510UL)) +#define bFM3_ADC1_ADSS23_TS21 *((volatile unsigned int*)(0x424E2514UL)) +#define bFM3_ADC1_ADSS23_TS22 *((volatile unsigned int*)(0x424E2518UL)) +#define bFM3_ADC1_ADSS23_TS23 *((volatile unsigned int*)(0x424E251CUL)) +#define bFM3_ADC1_ADSS23_TS24 *((volatile unsigned int*)(0x424E2520UL)) +#define bFM3_ADC1_ADSS23_TS25 *((volatile unsigned int*)(0x424E2524UL)) +#define bFM3_ADC1_ADSS23_TS26 *((volatile unsigned int*)(0x424E2528UL)) +#define bFM3_ADC1_ADSS23_TS27 *((volatile unsigned int*)(0x424E252CUL)) +#define bFM3_ADC1_ADSS23_TS28 *((volatile unsigned int*)(0x424E2530UL)) +#define bFM3_ADC1_ADSS23_TS29 *((volatile unsigned int*)(0x424E2534UL)) +#define bFM3_ADC1_ADSS23_TS30 *((volatile unsigned int*)(0x424E2538UL)) +#define bFM3_ADC1_ADSS23_TS31 *((volatile unsigned int*)(0x424E253CUL)) +#define bFM3_ADC1_ADSS2_TS16 *((volatile unsigned int*)(0x424E2500UL)) +#define bFM3_ADC1_ADSS2_TS17 *((volatile unsigned int*)(0x424E2504UL)) +#define bFM3_ADC1_ADSS2_TS18 *((volatile unsigned int*)(0x424E2508UL)) +#define bFM3_ADC1_ADSS2_TS19 *((volatile unsigned int*)(0x424E250CUL)) +#define bFM3_ADC1_ADSS2_TS20 *((volatile unsigned int*)(0x424E2510UL)) +#define bFM3_ADC1_ADSS2_TS21 *((volatile unsigned int*)(0x424E2514UL)) +#define bFM3_ADC1_ADSS2_TS22 *((volatile unsigned int*)(0x424E2518UL)) +#define bFM3_ADC1_ADSS2_TS23 *((volatile unsigned int*)(0x424E251CUL)) +#define bFM3_ADC1_ADSS3_TS24 *((volatile unsigned int*)(0x424E2520UL)) +#define bFM3_ADC1_ADSS3_TS25 *((volatile unsigned int*)(0x424E2524UL)) +#define bFM3_ADC1_ADSS3_TS26 *((volatile unsigned int*)(0x424E2528UL)) +#define bFM3_ADC1_ADSS3_TS27 *((volatile unsigned int*)(0x424E252CUL)) +#define bFM3_ADC1_ADSS3_TS28 *((volatile unsigned int*)(0x424E2530UL)) +#define bFM3_ADC1_ADSS3_TS29 *((volatile unsigned int*)(0x424E2534UL)) +#define bFM3_ADC1_ADSS3_TS30 *((volatile unsigned int*)(0x424E2538UL)) +#define bFM3_ADC1_ADSS3_TS31 *((volatile unsigned int*)(0x424E253CUL)) +#define bFM3_ADC1_ADSS01_TS0 *((volatile unsigned int*)(0x424E2580UL)) +#define bFM3_ADC1_ADSS01_TS1 *((volatile unsigned int*)(0x424E2584UL)) +#define bFM3_ADC1_ADSS01_TS2 *((volatile unsigned int*)(0x424E2588UL)) +#define bFM3_ADC1_ADSS01_TS3 *((volatile unsigned int*)(0x424E258CUL)) +#define bFM3_ADC1_ADSS01_TS4 *((volatile unsigned int*)(0x424E2590UL)) +#define bFM3_ADC1_ADSS01_TS5 *((volatile unsigned int*)(0x424E2594UL)) +#define bFM3_ADC1_ADSS01_TS6 *((volatile unsigned int*)(0x424E2598UL)) +#define bFM3_ADC1_ADSS01_TS7 *((volatile unsigned int*)(0x424E259CUL)) +#define bFM3_ADC1_ADSS01_TS8 *((volatile unsigned int*)(0x424E25A0UL)) +#define bFM3_ADC1_ADSS01_TS9 *((volatile unsigned int*)(0x424E25A4UL)) +#define bFM3_ADC1_ADSS01_TS10 *((volatile unsigned int*)(0x424E25A8UL)) +#define bFM3_ADC1_ADSS01_TS11 *((volatile unsigned int*)(0x424E25ACUL)) +#define bFM3_ADC1_ADSS01_TS12 *((volatile unsigned int*)(0x424E25B0UL)) +#define bFM3_ADC1_ADSS01_TS13 *((volatile unsigned int*)(0x424E25B4UL)) +#define bFM3_ADC1_ADSS01_TS14 *((volatile unsigned int*)(0x424E25B8UL)) +#define bFM3_ADC1_ADSS01_TS15 *((volatile unsigned int*)(0x424E25BCUL)) +#define bFM3_ADC1_ADSS0_TS0 *((volatile unsigned int*)(0x424E2580UL)) +#define bFM3_ADC1_ADSS0_TS1 *((volatile unsigned int*)(0x424E2584UL)) +#define bFM3_ADC1_ADSS0_TS2 *((volatile unsigned int*)(0x424E2588UL)) +#define bFM3_ADC1_ADSS0_TS3 *((volatile unsigned int*)(0x424E258CUL)) +#define bFM3_ADC1_ADSS0_TS4 *((volatile unsigned int*)(0x424E2590UL)) +#define bFM3_ADC1_ADSS0_TS5 *((volatile unsigned int*)(0x424E2594UL)) +#define bFM3_ADC1_ADSS0_TS6 *((volatile unsigned int*)(0x424E2598UL)) +#define bFM3_ADC1_ADSS0_TS7 *((volatile unsigned int*)(0x424E259CUL)) +#define bFM3_ADC1_ADSS1_TS8 *((volatile unsigned int*)(0x424E25A0UL)) +#define bFM3_ADC1_ADSS1_TS9 *((volatile unsigned int*)(0x424E25A4UL)) +#define bFM3_ADC1_ADSS1_TS10 *((volatile unsigned int*)(0x424E25A8UL)) +#define bFM3_ADC1_ADSS1_TS11 *((volatile unsigned int*)(0x424E25ACUL)) +#define bFM3_ADC1_ADSS1_TS12 *((volatile unsigned int*)(0x424E25B0UL)) +#define bFM3_ADC1_ADSS1_TS13 *((volatile unsigned int*)(0x424E25B4UL)) +#define bFM3_ADC1_ADSS1_TS14 *((volatile unsigned int*)(0x424E25B8UL)) +#define bFM3_ADC1_ADSS1_TS15 *((volatile unsigned int*)(0x424E25BCUL)) +#define bFM3_ADC1_ADST01_ST10 *((volatile unsigned int*)(0x424E2600UL)) +#define bFM3_ADC1_ADST01_ST11 *((volatile unsigned int*)(0x424E2604UL)) +#define bFM3_ADC1_ADST01_ST12 *((volatile unsigned int*)(0x424E2608UL)) +#define bFM3_ADC1_ADST01_ST13 *((volatile unsigned int*)(0x424E260CUL)) +#define bFM3_ADC1_ADST01_ST14 *((volatile unsigned int*)(0x424E2610UL)) +#define bFM3_ADC1_ADST01_STX10 *((volatile unsigned int*)(0x424E2614UL)) +#define bFM3_ADC1_ADST01_STX11 *((volatile unsigned int*)(0x424E2618UL)) +#define bFM3_ADC1_ADST01_STX12 *((volatile unsigned int*)(0x424E261CUL)) +#define bFM3_ADC1_ADST01_ST00 *((volatile unsigned int*)(0x424E2620UL)) +#define bFM3_ADC1_ADST01_ST01 *((volatile unsigned int*)(0x424E2624UL)) +#define bFM3_ADC1_ADST01_ST02 *((volatile unsigned int*)(0x424E2628UL)) +#define bFM3_ADC1_ADST01_ST03 *((volatile unsigned int*)(0x424E262CUL)) +#define bFM3_ADC1_ADST01_ST04 *((volatile unsigned int*)(0x424E2630UL)) +#define bFM3_ADC1_ADST01_STX00 *((volatile unsigned int*)(0x424E2634UL)) +#define bFM3_ADC1_ADST01_STX01 *((volatile unsigned int*)(0x424E2638UL)) +#define bFM3_ADC1_ADST01_STX02 *((volatile unsigned int*)(0x424E263CUL)) +#define bFM3_ADC1_ADST1_ST10 *((volatile unsigned int*)(0x424E2600UL)) +#define bFM3_ADC1_ADST1_ST11 *((volatile unsigned int*)(0x424E2604UL)) +#define bFM3_ADC1_ADST1_ST12 *((volatile unsigned int*)(0x424E2608UL)) +#define bFM3_ADC1_ADST1_ST13 *((volatile unsigned int*)(0x424E260CUL)) +#define bFM3_ADC1_ADST1_ST14 *((volatile unsigned int*)(0x424E2610UL)) +#define bFM3_ADC1_ADST1_STX10 *((volatile unsigned int*)(0x424E2614UL)) +#define bFM3_ADC1_ADST1_STX11 *((volatile unsigned int*)(0x424E2618UL)) +#define bFM3_ADC1_ADST1_STX12 *((volatile unsigned int*)(0x424E261CUL)) +#define bFM3_ADC1_ADST0_ST00 *((volatile unsigned int*)(0x424E2620UL)) +#define bFM3_ADC1_ADST0_ST01 *((volatile unsigned int*)(0x424E2624UL)) +#define bFM3_ADC1_ADST0_ST02 *((volatile unsigned int*)(0x424E2628UL)) +#define bFM3_ADC1_ADST0_ST03 *((volatile unsigned int*)(0x424E262CUL)) +#define bFM3_ADC1_ADST0_ST04 *((volatile unsigned int*)(0x424E2630UL)) +#define bFM3_ADC1_ADST0_STX00 *((volatile unsigned int*)(0x424E2634UL)) +#define bFM3_ADC1_ADST0_STX01 *((volatile unsigned int*)(0x424E2638UL)) +#define bFM3_ADC1_ADST0_STX02 *((volatile unsigned int*)(0x424E263CUL)) +#define bFM3_ADC1_ADCT_CT0 *((volatile unsigned int*)(0x424E2680UL)) +#define bFM3_ADC1_ADCT_CT1 *((volatile unsigned int*)(0x424E2684UL)) +#define bFM3_ADC1_ADCT_CT2 *((volatile unsigned int*)(0x424E2688UL)) +#define bFM3_ADC1_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E2700UL)) +#define bFM3_ADC1_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E2704UL)) +#define bFM3_ADC1_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E2708UL)) +#define bFM3_ADC1_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E270CUL)) +#define bFM3_ADC1_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E2720UL)) +#define bFM3_ADC1_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E2724UL)) +#define bFM3_ADC1_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E2728UL)) +#define bFM3_ADC1_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E272CUL)) +#define bFM3_ADC1_ADCEN_ENBL *((volatile unsigned int*)(0x424E2780UL)) +#define bFM3_ADC1_ADCEN_READY *((volatile unsigned int*)(0x424E2784UL)) + +/* 12-bit ADC unit 2 registers */ +#define bFM3_ADC2_ADSR_SCS *((volatile unsigned int*)(0x424E4000UL)) +#define bFM3_ADC2_ADSR_PCS *((volatile unsigned int*)(0x424E4004UL)) +#define bFM3_ADC2_ADSR_PCNS *((volatile unsigned int*)(0x424E4008UL)) +#define bFM3_ADC2_ADSR_FDAS *((volatile unsigned int*)(0x424E4018UL)) +#define bFM3_ADC2_ADSR_ADSTP *((volatile unsigned int*)(0x424E401CUL)) +#define bFM3_ADC2_ADCR_OVRIE *((volatile unsigned int*)(0x424E4020UL)) +#define bFM3_ADC2_ADCR_CMPIE *((volatile unsigned int*)(0x424E4024UL)) +#define bFM3_ADC2_ADCR_PCIE *((volatile unsigned int*)(0x424E4028UL)) +#define bFM3_ADC2_ADCR_SCIE *((volatile unsigned int*)(0x424E402CUL)) +#define bFM3_ADC2_ADCR_CMPIF *((volatile unsigned int*)(0x424E4034UL)) +#define bFM3_ADC2_ADCR_PCIF *((volatile unsigned int*)(0x424E4038UL)) +#define bFM3_ADC2_ADCR_SCIF *((volatile unsigned int*)(0x424E403CUL)) +#define bFM3_ADC2_SFNS_SFS0 *((volatile unsigned int*)(0x424E4100UL)) +#define bFM3_ADC2_SFNS_SFS1 *((volatile unsigned int*)(0x424E4104UL)) +#define bFM3_ADC2_SFNS_SFS2 *((volatile unsigned int*)(0x424E4108UL)) +#define bFM3_ADC2_SFNS_SFS3 *((volatile unsigned int*)(0x424E410CUL)) +#define bFM3_ADC2_SCCR_SSTR *((volatile unsigned int*)(0x424E4120UL)) +#define bFM3_ADC2_SCCR_SHEN *((volatile unsigned int*)(0x424E4124UL)) +#define bFM3_ADC2_SCCR_RPT *((volatile unsigned int*)(0x424E4128UL)) +#define bFM3_ADC2_SCCR_SFCLR *((volatile unsigned int*)(0x424E4130UL)) +#define bFM3_ADC2_SCCR_SOVR *((volatile unsigned int*)(0x424E4134UL)) +#define bFM3_ADC2_SCCR_SFUL *((volatile unsigned int*)(0x424E4138UL)) +#define bFM3_ADC2_SCCR_SEMP *((volatile unsigned int*)(0x424E413CUL)) +#define bFM3_ADC2_SCFD_SC0 *((volatile unsigned int*)(0x424E4180UL)) +#define bFM3_ADC2_SCFD_SC1 *((volatile unsigned int*)(0x424E4184UL)) +#define bFM3_ADC2_SCFD_SC2 *((volatile unsigned int*)(0x424E4188UL)) +#define bFM3_ADC2_SCFD_SC3 *((volatile unsigned int*)(0x424E418CUL)) +#define bFM3_ADC2_SCFD_SC4 *((volatile unsigned int*)(0x424E4190UL)) +#define bFM3_ADC2_SCFD_RS0 *((volatile unsigned int*)(0x424E41A0UL)) +#define bFM3_ADC2_SCFD_RS1 *((volatile unsigned int*)(0x424E41A4UL)) +#define bFM3_ADC2_SCFD_INVL *((volatile unsigned int*)(0x424E41B0UL)) +#define bFM3_ADC2_SCFD_SD0 *((volatile unsigned int*)(0x424E41D0UL)) +#define bFM3_ADC2_SCFD_SD1 *((volatile unsigned int*)(0x424E41D4UL)) +#define bFM3_ADC2_SCFD_SD2 *((volatile unsigned int*)(0x424E41D8UL)) +#define bFM3_ADC2_SCFD_SD3 *((volatile unsigned int*)(0x424E41DCUL)) +#define bFM3_ADC2_SCFD_SD4 *((volatile unsigned int*)(0x424E41E0UL)) +#define bFM3_ADC2_SCFD_SD5 *((volatile unsigned int*)(0x424E41E4UL)) +#define bFM3_ADC2_SCFD_SD6 *((volatile unsigned int*)(0x424E41E8UL)) +#define bFM3_ADC2_SCFD_SD7 *((volatile unsigned int*)(0x424E41ECUL)) +#define bFM3_ADC2_SCFD_SD8 *((volatile unsigned int*)(0x424E41F0UL)) +#define bFM3_ADC2_SCFD_SD9 *((volatile unsigned int*)(0x424E41F4UL)) +#define bFM3_ADC2_SCFD_SD10 *((volatile unsigned int*)(0x424E41F8UL)) +#define bFM3_ADC2_SCFD_SD11 *((volatile unsigned int*)(0x424E41FCUL)) +#define bFM3_ADC2_SCFDL_SC0 *((volatile unsigned int*)(0x424E4180UL)) +#define bFM3_ADC2_SCFDL_SC1 *((volatile unsigned int*)(0x424E4184UL)) +#define bFM3_ADC2_SCFDL_SC2 *((volatile unsigned int*)(0x424E4188UL)) +#define bFM3_ADC2_SCFDL_SC3 *((volatile unsigned int*)(0x424E418CUL)) +#define bFM3_ADC2_SCFDL_SC4 *((volatile unsigned int*)(0x424E4190UL)) +#define bFM3_ADC2_SCFDL_RS0 *((volatile unsigned int*)(0x424E41A0UL)) +#define bFM3_ADC2_SCFDL_RS1 *((volatile unsigned int*)(0x424E41A4UL)) +#define bFM3_ADC2_SCFDL_INVL *((volatile unsigned int*)(0x424E41B0UL)) +#define bFM3_ADC2_SCFDH_SD0 *((volatile unsigned int*)(0x424E41D0UL)) +#define bFM3_ADC2_SCFDH_SD1 *((volatile unsigned int*)(0x424E41D4UL)) +#define bFM3_ADC2_SCFDH_SD2 *((volatile unsigned int*)(0x424E41D8UL)) +#define bFM3_ADC2_SCFDH_SD3 *((volatile unsigned int*)(0x424E41DCUL)) +#define bFM3_ADC2_SCFDH_SD4 *((volatile unsigned int*)(0x424E41E0UL)) +#define bFM3_ADC2_SCFDH_SD5 *((volatile unsigned int*)(0x424E41E4UL)) +#define bFM3_ADC2_SCFDH_SD6 *((volatile unsigned int*)(0x424E41E8UL)) +#define bFM3_ADC2_SCFDH_SD7 *((volatile unsigned int*)(0x424E41ECUL)) +#define bFM3_ADC2_SCFDH_SD8 *((volatile unsigned int*)(0x424E41F0UL)) +#define bFM3_ADC2_SCFDH_SD9 *((volatile unsigned int*)(0x424E41F4UL)) +#define bFM3_ADC2_SCFDH_SD10 *((volatile unsigned int*)(0x424E41F8UL)) +#define bFM3_ADC2_SCFDH_SD11 *((volatile unsigned int*)(0x424E41FCUL)) +#define bFM3_ADC2_SCIS23_AN16 *((volatile unsigned int*)(0x424E4200UL)) +#define bFM3_ADC2_SCIS23_AN17 *((volatile unsigned int*)(0x424E4204UL)) +#define bFM3_ADC2_SCIS23_AN18 *((volatile unsigned int*)(0x424E4208UL)) +#define bFM3_ADC2_SCIS23_AN19 *((volatile unsigned int*)(0x424E420CUL)) +#define bFM3_ADC2_SCIS23_AN20 *((volatile unsigned int*)(0x424E4210UL)) +#define bFM3_ADC2_SCIS23_AN21 *((volatile unsigned int*)(0x424E4214UL)) +#define bFM3_ADC2_SCIS23_AN22 *((volatile unsigned int*)(0x424E4218UL)) +#define bFM3_ADC2_SCIS23_AN23 *((volatile unsigned int*)(0x424E421CUL)) +#define bFM3_ADC2_SCIS23_AN24 *((volatile unsigned int*)(0x424E4220UL)) +#define bFM3_ADC2_SCIS23_AN25 *((volatile unsigned int*)(0x424E4224UL)) +#define bFM3_ADC2_SCIS23_AN26 *((volatile unsigned int*)(0x424E4228UL)) +#define bFM3_ADC2_SCIS23_AN27 *((volatile unsigned int*)(0x424E422CUL)) +#define bFM3_ADC2_SCIS23_AN28 *((volatile unsigned int*)(0x424E4230UL)) +#define bFM3_ADC2_SCIS23_AN29 *((volatile unsigned int*)(0x424E4234UL)) +#define bFM3_ADC2_SCIS23_AN30 *((volatile unsigned int*)(0x424E4238UL)) +#define bFM3_ADC2_SCIS23_AN31 *((volatile unsigned int*)(0x424E423CUL)) +#define bFM3_ADC2_SCIS2_AN16 *((volatile unsigned int*)(0x424E4200UL)) +#define bFM3_ADC2_SCIS2_AN17 *((volatile unsigned int*)(0x424E4204UL)) +#define bFM3_ADC2_SCIS2_AN18 *((volatile unsigned int*)(0x424E4208UL)) +#define bFM3_ADC2_SCIS2_AN19 *((volatile unsigned int*)(0x424E420CUL)) +#define bFM3_ADC2_SCIS2_AN20 *((volatile unsigned int*)(0x424E4210UL)) +#define bFM3_ADC2_SCIS2_AN21 *((volatile unsigned int*)(0x424E4214UL)) +#define bFM3_ADC2_SCIS2_AN22 *((volatile unsigned int*)(0x424E4218UL)) +#define bFM3_ADC2_SCIS2_AN23 *((volatile unsigned int*)(0x424E421CUL)) +#define bFM3_ADC2_SCIS3_AN24 *((volatile unsigned int*)(0x424E4220UL)) +#define bFM3_ADC2_SCIS3_AN25 *((volatile unsigned int*)(0x424E4224UL)) +#define bFM3_ADC2_SCIS3_AN26 *((volatile unsigned int*)(0x424E4228UL)) +#define bFM3_ADC2_SCIS3_AN27 *((volatile unsigned int*)(0x424E422CUL)) +#define bFM3_ADC2_SCIS3_AN28 *((volatile unsigned int*)(0x424E4230UL)) +#define bFM3_ADC2_SCIS3_AN29 *((volatile unsigned int*)(0x424E4234UL)) +#define bFM3_ADC2_SCIS3_AN30 *((volatile unsigned int*)(0x424E4238UL)) +#define bFM3_ADC2_SCIS3_AN31 *((volatile unsigned int*)(0x424E423CUL)) +#define bFM3_ADC2_SCIS01_AN0 *((volatile unsigned int*)(0x424E4280UL)) +#define bFM3_ADC2_SCIS01_AN1 *((volatile unsigned int*)(0x424E4284UL)) +#define bFM3_ADC2_SCIS01_AN2 *((volatile unsigned int*)(0x424E4288UL)) +#define bFM3_ADC2_SCIS01_AN3 *((volatile unsigned int*)(0x424E428CUL)) +#define bFM3_ADC2_SCIS01_AN4 *((volatile unsigned int*)(0x424E4290UL)) +#define bFM3_ADC2_SCIS01_AN5 *((volatile unsigned int*)(0x424E4294UL)) +#define bFM3_ADC2_SCIS01_AN6 *((volatile unsigned int*)(0x424E4298UL)) +#define bFM3_ADC2_SCIS01_AN7 *((volatile unsigned int*)(0x424E429CUL)) +#define bFM3_ADC2_SCIS01_AN8 *((volatile unsigned int*)(0x424E42A0UL)) +#define bFM3_ADC2_SCIS01_AN9 *((volatile unsigned int*)(0x424E42A4UL)) +#define bFM3_ADC2_SCIS01_AN10 *((volatile unsigned int*)(0x424E42A8UL)) +#define bFM3_ADC2_SCIS01_AN11 *((volatile unsigned int*)(0x424E42ACUL)) +#define bFM3_ADC2_SCIS01_AN12 *((volatile unsigned int*)(0x424E42B0UL)) +#define bFM3_ADC2_SCIS01_AN13 *((volatile unsigned int*)(0x424E42B4UL)) +#define bFM3_ADC2_SCIS01_AN14 *((volatile unsigned int*)(0x424E42B8UL)) +#define bFM3_ADC2_SCIS01_AN15 *((volatile unsigned int*)(0x424E42BCUL)) +#define bFM3_ADC2_SCIS0_AN0 *((volatile unsigned int*)(0x424E4280UL)) +#define bFM3_ADC2_SCIS0_AN1 *((volatile unsigned int*)(0x424E4284UL)) +#define bFM3_ADC2_SCIS0_AN2 *((volatile unsigned int*)(0x424E4288UL)) +#define bFM3_ADC2_SCIS0_AN3 *((volatile unsigned int*)(0x424E428CUL)) +#define bFM3_ADC2_SCIS0_AN4 *((volatile unsigned int*)(0x424E4290UL)) +#define bFM3_ADC2_SCIS0_AN5 *((volatile unsigned int*)(0x424E4294UL)) +#define bFM3_ADC2_SCIS0_AN6 *((volatile unsigned int*)(0x424E4298UL)) +#define bFM3_ADC2_SCIS0_AN7 *((volatile unsigned int*)(0x424E429CUL)) +#define bFM3_ADC2_SCIS1_AN8 *((volatile unsigned int*)(0x424E42A0UL)) +#define bFM3_ADC2_SCIS1_AN9 *((volatile unsigned int*)(0x424E42A4UL)) +#define bFM3_ADC2_SCIS1_AN10 *((volatile unsigned int*)(0x424E42A8UL)) +#define bFM3_ADC2_SCIS1_AN11 *((volatile unsigned int*)(0x424E42ACUL)) +#define bFM3_ADC2_SCIS1_AN12 *((volatile unsigned int*)(0x424E42B0UL)) +#define bFM3_ADC2_SCIS1_AN13 *((volatile unsigned int*)(0x424E42B4UL)) +#define bFM3_ADC2_SCIS1_AN14 *((volatile unsigned int*)(0x424E42B8UL)) +#define bFM3_ADC2_SCIS1_AN15 *((volatile unsigned int*)(0x424E42BCUL)) +#define bFM3_ADC2_PFNS_PFS0 *((volatile unsigned int*)(0x424E4300UL)) +#define bFM3_ADC2_PFNS_PFS1 *((volatile unsigned int*)(0x424E4304UL)) +#define bFM3_ADC2_PFNS_TEST0 *((volatile unsigned int*)(0x424E4310UL)) +#define bFM3_ADC2_PFNS_TEST1 *((volatile unsigned int*)(0x424E4314UL)) +#define bFM3_ADC2_PCCR_PSTR *((volatile unsigned int*)(0x424E4320UL)) +#define bFM3_ADC2_PCCR_PHEN *((volatile unsigned int*)(0x424E4324UL)) +#define bFM3_ADC2_PCCR_PEEN *((volatile unsigned int*)(0x424E4328UL)) +#define bFM3_ADC2_PCCR_ESCE *((volatile unsigned int*)(0x424E432CUL)) +#define bFM3_ADC2_PCCR_PFCLR *((volatile unsigned int*)(0x424E4330UL)) +#define bFM3_ADC2_PCCR_POVR *((volatile unsigned int*)(0x424E4334UL)) +#define bFM3_ADC2_PCCR_PFUL *((volatile unsigned int*)(0x424E4338UL)) +#define bFM3_ADC2_PCCR_PEMP *((volatile unsigned int*)(0x424E433CUL)) +#define bFM3_ADC2_PCFD_PC0 *((volatile unsigned int*)(0x424E4380UL)) +#define bFM3_ADC2_PCFD_PC1 *((volatile unsigned int*)(0x424E4384UL)) +#define bFM3_ADC2_PCFD_PC2 *((volatile unsigned int*)(0x424E4388UL)) +#define bFM3_ADC2_PCFD_PC3 *((volatile unsigned int*)(0x424E438CUL)) +#define bFM3_ADC2_PCFD_PC4 *((volatile unsigned int*)(0x424E4390UL)) +#define bFM3_ADC2_PCFD_RS0 *((volatile unsigned int*)(0x424E43A0UL)) +#define bFM3_ADC2_PCFD_RS1 *((volatile unsigned int*)(0x424E43A4UL)) +#define bFM3_ADC2_PCFD_RS2 *((volatile unsigned int*)(0x424E43A8UL)) +#define bFM3_ADC2_PCFD_INVL *((volatile unsigned int*)(0x424E43B0UL)) +#define bFM3_ADC2_PCFD_PD0 *((volatile unsigned int*)(0x424E43D0UL)) +#define bFM3_ADC2_PCFD_PD1 *((volatile unsigned int*)(0x424E43D4UL)) +#define bFM3_ADC2_PCFD_PD2 *((volatile unsigned int*)(0x424E43D8UL)) +#define bFM3_ADC2_PCFD_PD3 *((volatile unsigned int*)(0x424E43DCUL)) +#define bFM3_ADC2_PCFD_PD4 *((volatile unsigned int*)(0x424E43E0UL)) +#define bFM3_ADC2_PCFD_PD5 *((volatile unsigned int*)(0x424E43E4UL)) +#define bFM3_ADC2_PCFD_PD6 *((volatile unsigned int*)(0x424E43E8UL)) +#define bFM3_ADC2_PCFD_PD7 *((volatile unsigned int*)(0x424E43ECUL)) +#define bFM3_ADC2_PCFD_PD8 *((volatile unsigned int*)(0x424E43F0UL)) +#define bFM3_ADC2_PCFD_PD9 *((volatile unsigned int*)(0x424E43F4UL)) +#define bFM3_ADC2_PCFD_PD10 *((volatile unsigned int*)(0x424E43F8UL)) +#define bFM3_ADC2_PCFD_PD11 *((volatile unsigned int*)(0x424E43FCUL)) +#define bFM3_ADC2_PCFDL_PC0 *((volatile unsigned int*)(0x424E4380UL)) +#define bFM3_ADC2_PCFDL_PC1 *((volatile unsigned int*)(0x424E4384UL)) +#define bFM3_ADC2_PCFDL_PC2 *((volatile unsigned int*)(0x424E4388UL)) +#define bFM3_ADC2_PCFDL_PC3 *((volatile unsigned int*)(0x424E438CUL)) +#define bFM3_ADC2_PCFDL_PC4 *((volatile unsigned int*)(0x424E4390UL)) +#define bFM3_ADC2_PCFDL_RS0 *((volatile unsigned int*)(0x424E43A0UL)) +#define bFM3_ADC2_PCFDL_RS1 *((volatile unsigned int*)(0x424E43A4UL)) +#define bFM3_ADC2_PCFDL_RS2 *((volatile unsigned int*)(0x424E43A8UL)) +#define bFM3_ADC2_PCFDL_INVL *((volatile unsigned int*)(0x424E43B0UL)) +#define bFM3_ADC2_PCFDH_PD0 *((volatile unsigned int*)(0x424E43D0UL)) +#define bFM3_ADC2_PCFDH_PD1 *((volatile unsigned int*)(0x424E43D4UL)) +#define bFM3_ADC2_PCFDH_PD2 *((volatile unsigned int*)(0x424E43D8UL)) +#define bFM3_ADC2_PCFDH_PD3 *((volatile unsigned int*)(0x424E43DCUL)) +#define bFM3_ADC2_PCFDH_PD4 *((volatile unsigned int*)(0x424E43E0UL)) +#define bFM3_ADC2_PCFDH_PD5 *((volatile unsigned int*)(0x424E43E4UL)) +#define bFM3_ADC2_PCFDH_PD6 *((volatile unsigned int*)(0x424E43E8UL)) +#define bFM3_ADC2_PCFDH_PD7 *((volatile unsigned int*)(0x424E43ECUL)) +#define bFM3_ADC2_PCFDH_PD8 *((volatile unsigned int*)(0x424E43F0UL)) +#define bFM3_ADC2_PCFDH_PD9 *((volatile unsigned int*)(0x424E43F4UL)) +#define bFM3_ADC2_PCFDH_PD10 *((volatile unsigned int*)(0x424E43F8UL)) +#define bFM3_ADC2_PCFDH_PD11 *((volatile unsigned int*)(0x424E43FCUL)) +#define bFM3_ADC2_PCIS_P1A0 *((volatile unsigned int*)(0x424E4400UL)) +#define bFM3_ADC2_PCIS_P1A1 *((volatile unsigned int*)(0x424E4404UL)) +#define bFM3_ADC2_PCIS_P1A2 *((volatile unsigned int*)(0x424E4408UL)) +#define bFM3_ADC2_PCIS_P2A0 *((volatile unsigned int*)(0x424E440CUL)) +#define bFM3_ADC2_PCIS_P2A1 *((volatile unsigned int*)(0x424E4410UL)) +#define bFM3_ADC2_PCIS_P2A2 *((volatile unsigned int*)(0x424E4414UL)) +#define bFM3_ADC2_PCIS_P2A3 *((volatile unsigned int*)(0x424E4418UL)) +#define bFM3_ADC2_PCIS_P2A4 *((volatile unsigned int*)(0x424E441CUL)) +#define bFM3_ADC2_CMPCR_CCH0 *((volatile unsigned int*)(0x424E4480UL)) +#define bFM3_ADC2_CMPCR_CCH1 *((volatile unsigned int*)(0x424E4484UL)) +#define bFM3_ADC2_CMPCR_CCH2 *((volatile unsigned int*)(0x424E4488UL)) +#define bFM3_ADC2_CMPCR_CCH3 *((volatile unsigned int*)(0x424E448CUL)) +#define bFM3_ADC2_CMPCR_CCH4 *((volatile unsigned int*)(0x424E4490UL)) +#define bFM3_ADC2_CMPCR_CMD0 *((volatile unsigned int*)(0x424E4494UL)) +#define bFM3_ADC2_CMPCR_CMD1 *((volatile unsigned int*)(0x424E4498UL)) +#define bFM3_ADC2_CMPCR_CMPEN *((volatile unsigned int*)(0x424E449CUL)) +#define bFM3_ADC2_CMPD_CMAD2 *((volatile unsigned int*)(0x424E44D8UL)) +#define bFM3_ADC2_CMPD_CMAD3 *((volatile unsigned int*)(0x424E44DCUL)) +#define bFM3_ADC2_CMPD_CMAD4 *((volatile unsigned int*)(0x424E44E0UL)) +#define bFM3_ADC2_CMPD_CMAD5 *((volatile unsigned int*)(0x424E44E4UL)) +#define bFM3_ADC2_CMPD_CMAD6 *((volatile unsigned int*)(0x424E44E8UL)) +#define bFM3_ADC2_CMPD_CMAD7 *((volatile unsigned int*)(0x424E44ECUL)) +#define bFM3_ADC2_CMPD_CMAD8 *((volatile unsigned int*)(0x424E44F0UL)) +#define bFM3_ADC2_CMPD_CMAD9 *((volatile unsigned int*)(0x424E44F4UL)) +#define bFM3_ADC2_CMPD_CMAD10 *((volatile unsigned int*)(0x424E44F8UL)) +#define bFM3_ADC2_CMPD_CMAD11 *((volatile unsigned int*)(0x424E44FCUL)) +#define bFM3_ADC2_ADSS23_TS16 *((volatile unsigned int*)(0x424E4500UL)) +#define bFM3_ADC2_ADSS23_TS17 *((volatile unsigned int*)(0x424E4504UL)) +#define bFM3_ADC2_ADSS23_TS18 *((volatile unsigned int*)(0x424E4508UL)) +#define bFM3_ADC2_ADSS23_TS19 *((volatile unsigned int*)(0x424E450CUL)) +#define bFM3_ADC2_ADSS23_TS20 *((volatile unsigned int*)(0x424E4510UL)) +#define bFM3_ADC2_ADSS23_TS21 *((volatile unsigned int*)(0x424E4514UL)) +#define bFM3_ADC2_ADSS23_TS22 *((volatile unsigned int*)(0x424E4518UL)) +#define bFM3_ADC2_ADSS23_TS23 *((volatile unsigned int*)(0x424E451CUL)) +#define bFM3_ADC2_ADSS23_TS24 *((volatile unsigned int*)(0x424E4520UL)) +#define bFM3_ADC2_ADSS23_TS25 *((volatile unsigned int*)(0x424E4524UL)) +#define bFM3_ADC2_ADSS23_TS26 *((volatile unsigned int*)(0x424E4528UL)) +#define bFM3_ADC2_ADSS23_TS27 *((volatile unsigned int*)(0x424E452CUL)) +#define bFM3_ADC2_ADSS23_TS28 *((volatile unsigned int*)(0x424E4530UL)) +#define bFM3_ADC2_ADSS23_TS29 *((volatile unsigned int*)(0x424E4534UL)) +#define bFM3_ADC2_ADSS23_TS30 *((volatile unsigned int*)(0x424E4538UL)) +#define bFM3_ADC2_ADSS23_TS31 *((volatile unsigned int*)(0x424E453CUL)) +#define bFM3_ADC2_ADSS2_TS16 *((volatile unsigned int*)(0x424E4500UL)) +#define bFM3_ADC2_ADSS2_TS17 *((volatile unsigned int*)(0x424E4504UL)) +#define bFM3_ADC2_ADSS2_TS18 *((volatile unsigned int*)(0x424E4508UL)) +#define bFM3_ADC2_ADSS2_TS19 *((volatile unsigned int*)(0x424E450CUL)) +#define bFM3_ADC2_ADSS2_TS20 *((volatile unsigned int*)(0x424E4510UL)) +#define bFM3_ADC2_ADSS2_TS21 *((volatile unsigned int*)(0x424E4514UL)) +#define bFM3_ADC2_ADSS2_TS22 *((volatile unsigned int*)(0x424E4518UL)) +#define bFM3_ADC2_ADSS2_TS23 *((volatile unsigned int*)(0x424E451CUL)) +#define bFM3_ADC2_ADSS3_TS24 *((volatile unsigned int*)(0x424E4520UL)) +#define bFM3_ADC2_ADSS3_TS25 *((volatile unsigned int*)(0x424E4524UL)) +#define bFM3_ADC2_ADSS3_TS26 *((volatile unsigned int*)(0x424E4528UL)) +#define bFM3_ADC2_ADSS3_TS27 *((volatile unsigned int*)(0x424E452CUL)) +#define bFM3_ADC2_ADSS3_TS28 *((volatile unsigned int*)(0x424E4530UL)) +#define bFM3_ADC2_ADSS3_TS29 *((volatile unsigned int*)(0x424E4534UL)) +#define bFM3_ADC2_ADSS3_TS30 *((volatile unsigned int*)(0x424E4538UL)) +#define bFM3_ADC2_ADSS3_TS31 *((volatile unsigned int*)(0x424E453CUL)) +#define bFM3_ADC2_ADSS01_TS0 *((volatile unsigned int*)(0x424E4580UL)) +#define bFM3_ADC2_ADSS01_TS1 *((volatile unsigned int*)(0x424E4584UL)) +#define bFM3_ADC2_ADSS01_TS2 *((volatile unsigned int*)(0x424E4588UL)) +#define bFM3_ADC2_ADSS01_TS3 *((volatile unsigned int*)(0x424E458CUL)) +#define bFM3_ADC2_ADSS01_TS4 *((volatile unsigned int*)(0x424E4590UL)) +#define bFM3_ADC2_ADSS01_TS5 *((volatile unsigned int*)(0x424E4594UL)) +#define bFM3_ADC2_ADSS01_TS6 *((volatile unsigned int*)(0x424E4598UL)) +#define bFM3_ADC2_ADSS01_TS7 *((volatile unsigned int*)(0x424E459CUL)) +#define bFM3_ADC2_ADSS01_TS8 *((volatile unsigned int*)(0x424E45A0UL)) +#define bFM3_ADC2_ADSS01_TS9 *((volatile unsigned int*)(0x424E45A4UL)) +#define bFM3_ADC2_ADSS01_TS10 *((volatile unsigned int*)(0x424E45A8UL)) +#define bFM3_ADC2_ADSS01_TS11 *((volatile unsigned int*)(0x424E45ACUL)) +#define bFM3_ADC2_ADSS01_TS12 *((volatile unsigned int*)(0x424E45B0UL)) +#define bFM3_ADC2_ADSS01_TS13 *((volatile unsigned int*)(0x424E45B4UL)) +#define bFM3_ADC2_ADSS01_TS14 *((volatile unsigned int*)(0x424E45B8UL)) +#define bFM3_ADC2_ADSS01_TS15 *((volatile unsigned int*)(0x424E45BCUL)) +#define bFM3_ADC2_ADSS0_TS0 *((volatile unsigned int*)(0x424E4580UL)) +#define bFM3_ADC2_ADSS0_TS1 *((volatile unsigned int*)(0x424E4584UL)) +#define bFM3_ADC2_ADSS0_TS2 *((volatile unsigned int*)(0x424E4588UL)) +#define bFM3_ADC2_ADSS0_TS3 *((volatile unsigned int*)(0x424E458CUL)) +#define bFM3_ADC2_ADSS0_TS4 *((volatile unsigned int*)(0x424E4590UL)) +#define bFM3_ADC2_ADSS0_TS5 *((volatile unsigned int*)(0x424E4594UL)) +#define bFM3_ADC2_ADSS0_TS6 *((volatile unsigned int*)(0x424E4598UL)) +#define bFM3_ADC2_ADSS0_TS7 *((volatile unsigned int*)(0x424E459CUL)) +#define bFM3_ADC2_ADSS1_TS8 *((volatile unsigned int*)(0x424E45A0UL)) +#define bFM3_ADC2_ADSS1_TS9 *((volatile unsigned int*)(0x424E45A4UL)) +#define bFM3_ADC2_ADSS1_TS10 *((volatile unsigned int*)(0x424E45A8UL)) +#define bFM3_ADC2_ADSS1_TS11 *((volatile unsigned int*)(0x424E45ACUL)) +#define bFM3_ADC2_ADSS1_TS12 *((volatile unsigned int*)(0x424E45B0UL)) +#define bFM3_ADC2_ADSS1_TS13 *((volatile unsigned int*)(0x424E45B4UL)) +#define bFM3_ADC2_ADSS1_TS14 *((volatile unsigned int*)(0x424E45B8UL)) +#define bFM3_ADC2_ADSS1_TS15 *((volatile unsigned int*)(0x424E45BCUL)) +#define bFM3_ADC2_ADST01_ST10 *((volatile unsigned int*)(0x424E4600UL)) +#define bFM3_ADC2_ADST01_ST11 *((volatile unsigned int*)(0x424E4604UL)) +#define bFM3_ADC2_ADST01_ST12 *((volatile unsigned int*)(0x424E4608UL)) +#define bFM3_ADC2_ADST01_ST13 *((volatile unsigned int*)(0x424E460CUL)) +#define bFM3_ADC2_ADST01_ST14 *((volatile unsigned int*)(0x424E4610UL)) +#define bFM3_ADC2_ADST01_STX10 *((volatile unsigned int*)(0x424E4614UL)) +#define bFM3_ADC2_ADST01_STX11 *((volatile unsigned int*)(0x424E4618UL)) +#define bFM3_ADC2_ADST01_STX12 *((volatile unsigned int*)(0x424E461CUL)) +#define bFM3_ADC2_ADST01_ST00 *((volatile unsigned int*)(0x424E4620UL)) +#define bFM3_ADC2_ADST01_ST01 *((volatile unsigned int*)(0x424E4624UL)) +#define bFM3_ADC2_ADST01_ST02 *((volatile unsigned int*)(0x424E4628UL)) +#define bFM3_ADC2_ADST01_ST03 *((volatile unsigned int*)(0x424E462CUL)) +#define bFM3_ADC2_ADST01_ST04 *((volatile unsigned int*)(0x424E4630UL)) +#define bFM3_ADC2_ADST01_STX00 *((volatile unsigned int*)(0x424E4634UL)) +#define bFM3_ADC2_ADST01_STX01 *((volatile unsigned int*)(0x424E4638UL)) +#define bFM3_ADC2_ADST01_STX02 *((volatile unsigned int*)(0x424E463CUL)) +#define bFM3_ADC2_ADST1_ST10 *((volatile unsigned int*)(0x424E4600UL)) +#define bFM3_ADC2_ADST1_ST11 *((volatile unsigned int*)(0x424E4604UL)) +#define bFM3_ADC2_ADST1_ST12 *((volatile unsigned int*)(0x424E4608UL)) +#define bFM3_ADC2_ADST1_ST13 *((volatile unsigned int*)(0x424E460CUL)) +#define bFM3_ADC2_ADST1_ST14 *((volatile unsigned int*)(0x424E4610UL)) +#define bFM3_ADC2_ADST1_STX10 *((volatile unsigned int*)(0x424E4614UL)) +#define bFM3_ADC2_ADST1_STX11 *((volatile unsigned int*)(0x424E4618UL)) +#define bFM3_ADC2_ADST1_STX12 *((volatile unsigned int*)(0x424E461CUL)) +#define bFM3_ADC2_ADST0_ST00 *((volatile unsigned int*)(0x424E4620UL)) +#define bFM3_ADC2_ADST0_ST01 *((volatile unsigned int*)(0x424E4624UL)) +#define bFM3_ADC2_ADST0_ST02 *((volatile unsigned int*)(0x424E4628UL)) +#define bFM3_ADC2_ADST0_ST03 *((volatile unsigned int*)(0x424E462CUL)) +#define bFM3_ADC2_ADST0_ST04 *((volatile unsigned int*)(0x424E4630UL)) +#define bFM3_ADC2_ADST0_STX00 *((volatile unsigned int*)(0x424E4634UL)) +#define bFM3_ADC2_ADST0_STX01 *((volatile unsigned int*)(0x424E4638UL)) +#define bFM3_ADC2_ADST0_STX02 *((volatile unsigned int*)(0x424E463CUL)) +#define bFM3_ADC2_ADCT_CT0 *((volatile unsigned int*)(0x424E4680UL)) +#define bFM3_ADC2_ADCT_CT1 *((volatile unsigned int*)(0x424E4684UL)) +#define bFM3_ADC2_ADCT_CT2 *((volatile unsigned int*)(0x424E4688UL)) +#define bFM3_ADC2_PRTSL_PRTSL0 *((volatile unsigned int*)(0x424E4700UL)) +#define bFM3_ADC2_PRTSL_PRTSL1 *((volatile unsigned int*)(0x424E4704UL)) +#define bFM3_ADC2_PRTSL_PRTSL2 *((volatile unsigned int*)(0x424E4708UL)) +#define bFM3_ADC2_PRTSL_PRTSL3 *((volatile unsigned int*)(0x424E470CUL)) +#define bFM3_ADC2_SCTSL_SCTSL0 *((volatile unsigned int*)(0x424E4720UL)) +#define bFM3_ADC2_SCTSL_SCTSL1 *((volatile unsigned int*)(0x424E4724UL)) +#define bFM3_ADC2_SCTSL_SCTSL2 *((volatile unsigned int*)(0x424E4728UL)) +#define bFM3_ADC2_SCTSL_SCTSL3 *((volatile unsigned int*)(0x424E472CUL)) +#define bFM3_ADC2_ADCEN_ENBL *((volatile unsigned int*)(0x424E4780UL)) +#define bFM3_ADC2_ADCEN_READY *((volatile unsigned int*)(0x424E4784UL)) + +/* CR trimming registers */ +#define bFM3_CRTRIM_MCR_PSR_CSR0 *((volatile unsigned int*)(0x425C0000UL)) +#define bFM3_CRTRIM_MCR_PSR_CSR1 *((volatile unsigned int*)(0x425C0004UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD0 *((volatile unsigned int*)(0x425C0080UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD1 *((volatile unsigned int*)(0x425C0084UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD2 *((volatile unsigned int*)(0x425C0088UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD3 *((volatile unsigned int*)(0x425C008CUL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD4 *((volatile unsigned int*)(0x425C0090UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD5 *((volatile unsigned int*)(0x425C0094UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD6 *((volatile unsigned int*)(0x425C0098UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD7 *((volatile unsigned int*)(0x425C009CUL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD8 *((volatile unsigned int*)(0x425C00A0UL)) +#define bFM3_CRTRIM_MCR_FTRM_TRD9 *((volatile unsigned int*)(0x425C00A4UL)) + +/* External interrupt registers */ +#define bFM3_EXTI_ENIR_EN0 *((volatile unsigned int*)(0x42600000UL)) +#define bFM3_EXTI_ENIR_EN1 *((volatile unsigned int*)(0x42600004UL)) +#define bFM3_EXTI_ENIR_EN2 *((volatile unsigned int*)(0x42600008UL)) +#define bFM3_EXTI_ENIR_EN3 *((volatile unsigned int*)(0x4260000CUL)) +#define bFM3_EXTI_ENIR_EN4 *((volatile unsigned int*)(0x42600010UL)) +#define bFM3_EXTI_ENIR_EN5 *((volatile unsigned int*)(0x42600014UL)) +#define bFM3_EXTI_ENIR_EN6 *((volatile unsigned int*)(0x42600018UL)) +#define bFM3_EXTI_ENIR_EN7 *((volatile unsigned int*)(0x4260001CUL)) +#define bFM3_EXTI_ENIR_EN8 *((volatile unsigned int*)(0x42600020UL)) +#define bFM3_EXTI_ENIR_EN9 *((volatile unsigned int*)(0x42600024UL)) +#define bFM3_EXTI_ENIR_EN10 *((volatile unsigned int*)(0x42600028UL)) +#define bFM3_EXTI_ENIR_EN11 *((volatile unsigned int*)(0x4260002CUL)) +#define bFM3_EXTI_ENIR_EN12 *((volatile unsigned int*)(0x42600030UL)) +#define bFM3_EXTI_ENIR_EN13 *((volatile unsigned int*)(0x42600034UL)) +#define bFM3_EXTI_ENIR_EN14 *((volatile unsigned int*)(0x42600038UL)) +#define bFM3_EXTI_ENIR_EN15 *((volatile unsigned int*)(0x4260003CUL)) +#define bFM3_EXTI_EIRR_ER0 *((volatile unsigned int*)(0x42600080UL)) +#define bFM3_EXTI_EIRR_ER1 *((volatile unsigned int*)(0x42600084UL)) +#define bFM3_EXTI_EIRR_ER2 *((volatile unsigned int*)(0x42600088UL)) +#define bFM3_EXTI_EIRR_ER3 *((volatile unsigned int*)(0x4260008CUL)) +#define bFM3_EXTI_EIRR_ER4 *((volatile unsigned int*)(0x42600090UL)) +#define bFM3_EXTI_EIRR_ER5 *((volatile unsigned int*)(0x42600094UL)) +#define bFM3_EXTI_EIRR_ER6 *((volatile unsigned int*)(0x42600098UL)) +#define bFM3_EXTI_EIRR_ER7 *((volatile unsigned int*)(0x4260009CUL)) +#define bFM3_EXTI_EIRR_ER8 *((volatile unsigned int*)(0x426000A0UL)) +#define bFM3_EXTI_EIRR_ER9 *((volatile unsigned int*)(0x426000A4UL)) +#define bFM3_EXTI_EIRR_ER10 *((volatile unsigned int*)(0x426000A8UL)) +#define bFM3_EXTI_EIRR_ER11 *((volatile unsigned int*)(0x426000ACUL)) +#define bFM3_EXTI_EIRR_ER12 *((volatile unsigned int*)(0x426000B0UL)) +#define bFM3_EXTI_EIRR_ER13 *((volatile unsigned int*)(0x426000B4UL)) +#define bFM3_EXTI_EIRR_ER14 *((volatile unsigned int*)(0x426000B8UL)) +#define bFM3_EXTI_EIRR_ER15 *((volatile unsigned int*)(0x426000BCUL)) +#define bFM3_EXTI_EICL_ECL0 *((volatile unsigned int*)(0x42600100UL)) +#define bFM3_EXTI_EICL_ECL1 *((volatile unsigned int*)(0x42600104UL)) +#define bFM3_EXTI_EICL_ECL2 *((volatile unsigned int*)(0x42600108UL)) +#define bFM3_EXTI_EICL_ECL3 *((volatile unsigned int*)(0x4260010CUL)) +#define bFM3_EXTI_EICL_ECL4 *((volatile unsigned int*)(0x42600110UL)) +#define bFM3_EXTI_EICL_ECL5 *((volatile unsigned int*)(0x42600114UL)) +#define bFM3_EXTI_EICL_ECL6 *((volatile unsigned int*)(0x42600118UL)) +#define bFM3_EXTI_EICL_ECL7 *((volatile unsigned int*)(0x4260011CUL)) +#define bFM3_EXTI_EICL_ECL8 *((volatile unsigned int*)(0x42600120UL)) +#define bFM3_EXTI_EICL_ECL9 *((volatile unsigned int*)(0x42600124UL)) +#define bFM3_EXTI_EICL_ECL10 *((volatile unsigned int*)(0x42600128UL)) +#define bFM3_EXTI_EICL_ECL11 *((volatile unsigned int*)(0x4260012CUL)) +#define bFM3_EXTI_EICL_ECL12 *((volatile unsigned int*)(0x42600130UL)) +#define bFM3_EXTI_EICL_ECL13 *((volatile unsigned int*)(0x42600134UL)) +#define bFM3_EXTI_EICL_ECL14 *((volatile unsigned int*)(0x42600138UL)) +#define bFM3_EXTI_EICL_ECL15 *((volatile unsigned int*)(0x4260013CUL)) +#define bFM3_EXTI_ELVR_LA0 *((volatile unsigned int*)(0x42600180UL)) +#define bFM3_EXTI_ELVR_LB0 *((volatile unsigned int*)(0x42600184UL)) +#define bFM3_EXTI_ELVR_LA1 *((volatile unsigned int*)(0x42600188UL)) +#define bFM3_EXTI_ELVR_LB1 *((volatile unsigned int*)(0x4260018CUL)) +#define bFM3_EXTI_ELVR_LA2 *((volatile unsigned int*)(0x42600190UL)) +#define bFM3_EXTI_ELVR_LB2 *((volatile unsigned int*)(0x42600194UL)) +#define bFM3_EXTI_ELVR_LA3 *((volatile unsigned int*)(0x42600198UL)) +#define bFM3_EXTI_ELVR_LB3 *((volatile unsigned int*)(0x4260019CUL)) +#define bFM3_EXTI_ELVR_LA4 *((volatile unsigned int*)(0x426001A0UL)) +#define bFM3_EXTI_ELVR_LB4 *((volatile unsigned int*)(0x426001A4UL)) +#define bFM3_EXTI_ELVR_LA5 *((volatile unsigned int*)(0x426001A8UL)) +#define bFM3_EXTI_ELVR_LB5 *((volatile unsigned int*)(0x426001ACUL)) +#define bFM3_EXTI_ELVR_LA6 *((volatile unsigned int*)(0x426001B0UL)) +#define bFM3_EXTI_ELVR_LB6 *((volatile unsigned int*)(0x426001B4UL)) +#define bFM3_EXTI_ELVR_LA7 *((volatile unsigned int*)(0x426001B8UL)) +#define bFM3_EXTI_ELVR_LB7 *((volatile unsigned int*)(0x426001BCUL)) +#define bFM3_EXTI_ELVR_LA8 *((volatile unsigned int*)(0x426001C0UL)) +#define bFM3_EXTI_ELVR_LB8 *((volatile unsigned int*)(0x426001C4UL)) +#define bFM3_EXTI_ELVR_LA9 *((volatile unsigned int*)(0x426001C8UL)) +#define bFM3_EXTI_ELVR_LB9 *((volatile unsigned int*)(0x426001CCUL)) +#define bFM3_EXTI_ELVR_LA10 *((volatile unsigned int*)(0x426001D0UL)) +#define bFM3_EXTI_ELVR_LB10 *((volatile unsigned int*)(0x426001D4UL)) +#define bFM3_EXTI_ELVR_LA11 *((volatile unsigned int*)(0x426001D8UL)) +#define bFM3_EXTI_ELVR_LB11 *((volatile unsigned int*)(0x426001DCUL)) +#define bFM3_EXTI_ELVR_LA12 *((volatile unsigned int*)(0x426001E0UL)) +#define bFM3_EXTI_ELVR_LB12 *((volatile unsigned int*)(0x426001E4UL)) +#define bFM3_EXTI_ELVR_LA13 *((volatile unsigned int*)(0x426001E8UL)) +#define bFM3_EXTI_ELVR_LB13 *((volatile unsigned int*)(0x426001ECUL)) +#define bFM3_EXTI_ELVR_LA14 *((volatile unsigned int*)(0x426001F0UL)) +#define bFM3_EXTI_ELVR_LB14 *((volatile unsigned int*)(0x426001F4UL)) +#define bFM3_EXTI_ELVR_LA15 *((volatile unsigned int*)(0x426001F8UL)) +#define bFM3_EXTI_ELVR_LB15 *((volatile unsigned int*)(0x426001FCUL)) +#define bFM3_EXTI_NMIRR_NR0 *((volatile unsigned int*)(0x42600280UL)) +#define bFM3_EXTI_NMICL_NCL0 *((volatile unsigned int*)(0x42600300UL)) + +/* Interrupt request read registers */ +#define bFM3_INTREQ_DRQSEL_DRQSEL0 *((volatile unsigned int*)(0x42620000UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL1 *((volatile unsigned int*)(0x42620004UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL2 *((volatile unsigned int*)(0x42620008UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL3 *((volatile unsigned int*)(0x4262000CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL4 *((volatile unsigned int*)(0x42620010UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL5 *((volatile unsigned int*)(0x42620014UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL6 *((volatile unsigned int*)(0x42620018UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL7 *((volatile unsigned int*)(0x4262001CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL8 *((volatile unsigned int*)(0x42620020UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL9 *((volatile unsigned int*)(0x42620024UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL10 *((volatile unsigned int*)(0x42620028UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL11 *((volatile unsigned int*)(0x4262002CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL12 *((volatile unsigned int*)(0x42620030UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL13 *((volatile unsigned int*)(0x42620034UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL14 *((volatile unsigned int*)(0x42620038UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL15 *((volatile unsigned int*)(0x4262003CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL16 *((volatile unsigned int*)(0x42620040UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL17 *((volatile unsigned int*)(0x42620044UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL18 *((volatile unsigned int*)(0x42620048UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL19 *((volatile unsigned int*)(0x4262004CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL20 *((volatile unsigned int*)(0x42620050UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL21 *((volatile unsigned int*)(0x42620054UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL22 *((volatile unsigned int*)(0x42620058UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL23 *((volatile unsigned int*)(0x4262005CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL24 *((volatile unsigned int*)(0x42620060UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL25 *((volatile unsigned int*)(0x42620064UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL26 *((volatile unsigned int*)(0x42620068UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL27 *((volatile unsigned int*)(0x4262006CUL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL28 *((volatile unsigned int*)(0x42620070UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL29 *((volatile unsigned int*)(0x42620074UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL30 *((volatile unsigned int*)(0x42620078UL)) +#define bFM3_INTREQ_DRQSEL_DRQSEL31 *((volatile unsigned int*)(0x4262007CUL)) +#define bFM3_INTREQ_EXC02MON_NMI *((volatile unsigned int*)(0x42620200UL)) +#define bFM3_INTREQ_EXC02MON_HWINT *((volatile unsigned int*)(0x42620204UL)) +#define bFM3_INTREQ_IRQ00MON_FCSINT *((volatile unsigned int*)(0x42620280UL)) +#define bFM3_INTREQ_IRQ01MON_SWWDTINT *((volatile unsigned int*)(0x42620300UL)) +#define bFM3_INTREQ_IRQ02MON_LVDINT *((volatile unsigned int*)(0x42620380UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT0 *((volatile unsigned int*)(0x42620400UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT1 *((volatile unsigned int*)(0x42620404UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT2 *((volatile unsigned int*)(0x42620408UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE0INT3 *((volatile unsigned int*)(0x4262040CUL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT0 *((volatile unsigned int*)(0x42620410UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT1 *((volatile unsigned int*)(0x42620414UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT2 *((volatile unsigned int*)(0x42620418UL)) +#define bFM3_INTREQ_IRQ03MON_WAVE1INT3 *((volatile unsigned int*)(0x4262041CUL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT0 *((volatile unsigned int*)(0x42620480UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT1 *((volatile unsigned int*)(0x42620484UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT2 *((volatile unsigned int*)(0x42620488UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT3 *((volatile unsigned int*)(0x4262048CUL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT4 *((volatile unsigned int*)(0x42620490UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT5 *((volatile unsigned int*)(0x42620494UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT6 *((volatile unsigned int*)(0x42620498UL)) +#define bFM3_INTREQ_IRQ04MON_EXTINT7 *((volatile unsigned int*)(0x4262049CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT0 *((volatile unsigned int*)(0x42620500UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT1 *((volatile unsigned int*)(0x42620504UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT2 *((volatile unsigned int*)(0x42620508UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT3 *((volatile unsigned int*)(0x4262050CUL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT4 *((volatile unsigned int*)(0x42620510UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT5 *((volatile unsigned int*)(0x42620514UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT6 *((volatile unsigned int*)(0x42620518UL)) +#define bFM3_INTREQ_IRQ05MON_EXTINT7 *((volatile unsigned int*)(0x4262051CUL)) +#define bFM3_INTREQ_IRQ06MON_TIMINT0 *((volatile unsigned int*)(0x42620580UL)) +#define bFM3_INTREQ_IRQ06MON_TIMINT1 *((volatile unsigned int*)(0x42620584UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT0 *((volatile unsigned int*)(0x42620588UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT1 *((volatile unsigned int*)(0x4262058CUL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT2 *((volatile unsigned int*)(0x42620590UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT3 *((volatile unsigned int*)(0x42620594UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT4 *((volatile unsigned int*)(0x42620598UL)) +#define bFM3_INTREQ_IRQ06MON_QUD0INT5 *((volatile unsigned int*)(0x4262059CUL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT0 *((volatile unsigned int*)(0x426205A0UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT1 *((volatile unsigned int*)(0x426205A4UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT2 *((volatile unsigned int*)(0x426205A8UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT3 *((volatile unsigned int*)(0x426205ACUL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT4 *((volatile unsigned int*)(0x426205B0UL)) +#define bFM3_INTREQ_IRQ06MON_QUD1INT5 *((volatile unsigned int*)(0x426205B4UL)) +#define bFM3_INTREQ_IRQ07MON_FMSINT *((volatile unsigned int*)(0x42620600UL)) +#define bFM3_INTREQ_IRQ08MON_MFSINT0 *((volatile unsigned int*)(0x42620680UL)) +#define bFM3_INTREQ_IRQ08MON_MFSINT1 *((volatile unsigned int*)(0x42620684UL)) +#define bFM3_INTREQ_IRQ09MON_FMSINT *((volatile unsigned int*)(0x42620700UL)) +#define bFM3_INTREQ_IRQ10MON_MFSINT0 *((volatile unsigned int*)(0x42620780UL)) +#define bFM3_INTREQ_IRQ10MON_MFSINT1 *((volatile unsigned int*)(0x42620784UL)) +#define bFM3_INTREQ_IRQ11MON_FMSINT *((volatile unsigned int*)(0x42620800UL)) +#define bFM3_INTREQ_IRQ12MON_MFSINT0 *((volatile unsigned int*)(0x42620880UL)) +#define bFM3_INTREQ_IRQ12MON_MFSINT1 *((volatile unsigned int*)(0x42620884UL)) +#define bFM3_INTREQ_IRQ13MON_FMSINT *((volatile unsigned int*)(0x42620900UL)) +#define bFM3_INTREQ_IRQ14MON_MFSINT0 *((volatile unsigned int*)(0x42620980UL)) +#define bFM3_INTREQ_IRQ14MON_MFSINT1 *((volatile unsigned int*)(0x42620984UL)) +#define bFM3_INTREQ_IRQ15MON_FMSINT *((volatile unsigned int*)(0x42620A00UL)) +#define bFM3_INTREQ_IRQ16MON_MFSINT0 *((volatile unsigned int*)(0x42620A80UL)) +#define bFM3_INTREQ_IRQ16MON_MFSINT1 *((volatile unsigned int*)(0x42620A84UL)) +#define bFM3_INTREQ_IRQ17MON_FMSINT *((volatile unsigned int*)(0x42620B00UL)) +#define bFM3_INTREQ_IRQ18MON_MFSINT0 *((volatile unsigned int*)(0x42620B80UL)) +#define bFM3_INTREQ_IRQ18MON_MFSINT1 *((volatile unsigned int*)(0x42620B84UL)) +#define bFM3_INTREQ_IRQ19MON_FMSINT *((volatile unsigned int*)(0x42620C00UL)) +#define bFM3_INTREQ_IRQ20MON_MFSINT0 *((volatile unsigned int*)(0x42620C80UL)) +#define bFM3_INTREQ_IRQ20MON_MFSINT1 *((volatile unsigned int*)(0x42620C84UL)) +#define bFM3_INTREQ_IRQ21MON_FMSINT *((volatile unsigned int*)(0x42620D00UL)) +#define bFM3_INTREQ_IRQ22MON_MFSINT0 *((volatile unsigned int*)(0x42620D80UL)) +#define bFM3_INTREQ_IRQ22MON_MFSINT1 *((volatile unsigned int*)(0x42620D84UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT0 *((volatile unsigned int*)(0x42620E00UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT1 *((volatile unsigned int*)(0x42620E04UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT2 *((volatile unsigned int*)(0x42620E08UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT3 *((volatile unsigned int*)(0x42620E0CUL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT4 *((volatile unsigned int*)(0x42620E10UL)) +#define bFM3_INTREQ_IRQ23MON_PPGINT5 *((volatile unsigned int*)(0x42620E14UL)) +#define bFM3_INTREQ_IRQ24MON_MOSCINT *((volatile unsigned int*)(0x42620E80UL)) +#define bFM3_INTREQ_IRQ24MON_SOSCINT *((volatile unsigned int*)(0x42620E84UL)) +#define bFM3_INTREQ_IRQ24MON_MPLLINT *((volatile unsigned int*)(0x42620E88UL)) +#define bFM3_INTREQ_IRQ24MON_UPLLINT *((volatile unsigned int*)(0x42620E8CUL)) +#define bFM3_INTREQ_IRQ24MON_WCINT *((volatile unsigned int*)(0x42620E90UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT0 *((volatile unsigned int*)(0x42620F00UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT1 *((volatile unsigned int*)(0x42620F04UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT2 *((volatile unsigned int*)(0x42620F08UL)) +#define bFM3_INTREQ_IRQ25MON_ADCINT3 *((volatile unsigned int*)(0x42620F0CUL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT0 *((volatile unsigned int*)(0x42620F80UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT1 *((volatile unsigned int*)(0x42620F84UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT2 *((volatile unsigned int*)(0x42620F88UL)) +#define bFM3_INTREQ_IRQ26MON_ADCINT3 *((volatile unsigned int*)(0x42620F8CUL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT0 *((volatile unsigned int*)(0x42621000UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT1 *((volatile unsigned int*)(0x42621004UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT2 *((volatile unsigned int*)(0x42621008UL)) +#define bFM3_INTREQ_IRQ27MON_ADCINT3 *((volatile unsigned int*)(0x4262100CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT0 *((volatile unsigned int*)(0x42621080UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT1 *((volatile unsigned int*)(0x42621084UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT2 *((volatile unsigned int*)(0x42621088UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT3 *((volatile unsigned int*)(0x4262108CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT4 *((volatile unsigned int*)(0x42621090UL)) +#define bFM3_INTREQ_IRQ28MON_FRT0INT5 *((volatile unsigned int*)(0x42621094UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT0 *((volatile unsigned int*)(0x42621098UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT1 *((volatile unsigned int*)(0x4262109CUL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT2 *((volatile unsigned int*)(0x426210A0UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT3 *((volatile unsigned int*)(0x426210A4UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT4 *((volatile unsigned int*)(0x426210A8UL)) +#define bFM3_INTREQ_IRQ28MON_FRT1INT5 *((volatile unsigned int*)(0x426210ACUL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT0 *((volatile unsigned int*)(0x42621100UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT1 *((volatile unsigned int*)(0x42621104UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT2 *((volatile unsigned int*)(0x42621108UL)) +#define bFM3_INTREQ_IRQ29MON_ICU0INT3 *((volatile unsigned int*)(0x4262110CUL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT0 *((volatile unsigned int*)(0x42621110UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT1 *((volatile unsigned int*)(0x42621114UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT2 *((volatile unsigned int*)(0x42621118UL)) +#define bFM3_INTREQ_IRQ29MON_ICU1INT3 *((volatile unsigned int*)(0x4262111CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT0 *((volatile unsigned int*)(0x42621180UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT1 *((volatile unsigned int*)(0x42621184UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT2 *((volatile unsigned int*)(0x42621188UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT3 *((volatile unsigned int*)(0x4262118CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT4 *((volatile unsigned int*)(0x42621190UL)) +#define bFM3_INTREQ_IRQ30MON_OCU0INT5 *((volatile unsigned int*)(0x42621194UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT0 *((volatile unsigned int*)(0x42621198UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT1 *((volatile unsigned int*)(0x4262119CUL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT2 *((volatile unsigned int*)(0x426211A0UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT3 *((volatile unsigned int*)(0x426211A4UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT4 *((volatile unsigned int*)(0x426211A8UL)) +#define bFM3_INTREQ_IRQ30MON_OCU1INT5 *((volatile unsigned int*)(0x426211ACUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT0 *((volatile unsigned int*)(0x42621200UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT1 *((volatile unsigned int*)(0x42621204UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT2 *((volatile unsigned int*)(0x42621208UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT3 *((volatile unsigned int*)(0x4262120CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT4 *((volatile unsigned int*)(0x42621210UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT5 *((volatile unsigned int*)(0x42621214UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT6 *((volatile unsigned int*)(0x42621218UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT7 *((volatile unsigned int*)(0x4262121CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT8 *((volatile unsigned int*)(0x42621220UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT9 *((volatile unsigned int*)(0x42621224UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT10 *((volatile unsigned int*)(0x42621228UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT11 *((volatile unsigned int*)(0x4262122CUL)) +#define bFM3_INTREQ_IRQ31MON_BTINT12 *((volatile unsigned int*)(0x42621230UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT13 *((volatile unsigned int*)(0x42621234UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT14 *((volatile unsigned int*)(0x42621238UL)) +#define bFM3_INTREQ_IRQ31MON_BTINT15 *((volatile unsigned int*)(0x4262123CUL)) +#define bFM3_INTREQ_IRQ32MON_CANINT *((volatile unsigned int*)(0x42621280UL)) +#define bFM3_INTREQ_IRQ33MON_CANINT *((volatile unsigned int*)(0x42621300UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT0 *((volatile unsigned int*)(0x42621380UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT1 *((volatile unsigned int*)(0x42621384UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT2 *((volatile unsigned int*)(0x42621388UL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT3 *((volatile unsigned int*)(0x4262138CUL)) +#define bFM3_INTREQ_IRQ34MON_USB0INT4 *((volatile unsigned int*)(0x42621390UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT0 *((volatile unsigned int*)(0x42621400UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT1 *((volatile unsigned int*)(0x42621404UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT2 *((volatile unsigned int*)(0x42621408UL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT3 *((volatile unsigned int*)(0x4262140CUL)) +#define bFM3_INTREQ_IRQ35MON_USB0INT4 *((volatile unsigned int*)(0x42621410UL)) +#define bFM3_INTREQ_IRQ38MON_DMAINT *((volatile unsigned int*)(0x42621580UL)) +#define bFM3_INTREQ_IRQ39MON_DMAINT *((volatile unsigned int*)(0x42621600UL)) +#define bFM3_INTREQ_IRQ40MON_DMAINT *((volatile unsigned int*)(0x42621680UL)) +#define bFM3_INTREQ_IRQ41MON_DMAINT *((volatile unsigned int*)(0x42621700UL)) +#define bFM3_INTREQ_IRQ42MON_DMAINT *((volatile unsigned int*)(0x42621780UL)) +#define bFM3_INTREQ_IRQ43MON_DMAINT *((volatile unsigned int*)(0x42621800UL)) +#define bFM3_INTREQ_IRQ44MON_DMAINT *((volatile unsigned int*)(0x42621880UL)) +#define bFM3_INTREQ_IRQ45MON_DMAINT *((volatile unsigned int*)(0x42621900UL)) + +/* General purpose I/O registers */ +#define bFM3_GPIO_PFR0_P0 *((volatile unsigned int*)(0x42660000UL)) +#define bFM3_GPIO_PFR0_P1 *((volatile unsigned int*)(0x42660004UL)) +#define bFM3_GPIO_PFR0_P2 *((volatile unsigned int*)(0x42660008UL)) +#define bFM3_GPIO_PFR0_P3 *((volatile unsigned int*)(0x4266000CUL)) +#define bFM3_GPIO_PFR0_P4 *((volatile unsigned int*)(0x42660010UL)) +#define bFM3_GPIO_PFR0_P5 *((volatile unsigned int*)(0x42660014UL)) +#define bFM3_GPIO_PFR0_P6 *((volatile unsigned int*)(0x42660018UL)) +#define bFM3_GPIO_PFR0_P7 *((volatile unsigned int*)(0x4266001CUL)) +#define bFM3_GPIO_PFR0_P8 *((volatile unsigned int*)(0x42660020UL)) +#define bFM3_GPIO_PFR0_P9 *((volatile unsigned int*)(0x42660024UL)) +#define bFM3_GPIO_PFR0_PA *((volatile unsigned int*)(0x42660028UL)) +#define bFM3_GPIO_PFR0_PB *((volatile unsigned int*)(0x4266002CUL)) +#define bFM3_GPIO_PFR0_PC *((volatile unsigned int*)(0x42660030UL)) +#define bFM3_GPIO_PFR0_PD *((volatile unsigned int*)(0x42660034UL)) +#define bFM3_GPIO_PFR0_PE *((volatile unsigned int*)(0x42660038UL)) +#define bFM3_GPIO_PFR0_PF *((volatile unsigned int*)(0x4266003CUL)) +#define bFM3_GPIO_PFR1_P0 *((volatile unsigned int*)(0x42660080UL)) +#define bFM3_GPIO_PFR1_P1 *((volatile unsigned int*)(0x42660084UL)) +#define bFM3_GPIO_PFR1_P2 *((volatile unsigned int*)(0x42660088UL)) +#define bFM3_GPIO_PFR1_P3 *((volatile unsigned int*)(0x4266008CUL)) +#define bFM3_GPIO_PFR1_P4 *((volatile unsigned int*)(0x42660090UL)) +#define bFM3_GPIO_PFR1_P5 *((volatile unsigned int*)(0x42660094UL)) +#define bFM3_GPIO_PFR1_P6 *((volatile unsigned int*)(0x42660098UL)) +#define bFM3_GPIO_PFR1_P7 *((volatile unsigned int*)(0x4266009CUL)) +#define bFM3_GPIO_PFR1_P8 *((volatile unsigned int*)(0x426600A0UL)) +#define bFM3_GPIO_PFR1_P9 *((volatile unsigned int*)(0x426600A4UL)) +#define bFM3_GPIO_PFR1_PA *((volatile unsigned int*)(0x426600A8UL)) +#define bFM3_GPIO_PFR1_PB *((volatile unsigned int*)(0x426600ACUL)) +#define bFM3_GPIO_PFR1_PC *((volatile unsigned int*)(0x426600B0UL)) +#define bFM3_GPIO_PFR1_PD *((volatile unsigned int*)(0x426600B4UL)) +#define bFM3_GPIO_PFR1_PE *((volatile unsigned int*)(0x426600B8UL)) +#define bFM3_GPIO_PFR1_PF *((volatile unsigned int*)(0x426600BCUL)) +#define bFM3_GPIO_PFR2_P0 *((volatile unsigned int*)(0x42660100UL)) +#define bFM3_GPIO_PFR2_P1 *((volatile unsigned int*)(0x42660104UL)) +#define bFM3_GPIO_PFR2_P2 *((volatile unsigned int*)(0x42660108UL)) +#define bFM3_GPIO_PFR2_P3 *((volatile unsigned int*)(0x4266010CUL)) +#define bFM3_GPIO_PFR2_P4 *((volatile unsigned int*)(0x42660110UL)) +#define bFM3_GPIO_PFR2_P5 *((volatile unsigned int*)(0x42660114UL)) +#define bFM3_GPIO_PFR2_P6 *((volatile unsigned int*)(0x42660118UL)) +#define bFM3_GPIO_PFR2_P7 *((volatile unsigned int*)(0x4266011CUL)) +#define bFM3_GPIO_PFR2_P8 *((volatile unsigned int*)(0x42660120UL)) +#define bFM3_GPIO_PFR3_P0 *((volatile unsigned int*)(0x42660180UL)) +#define bFM3_GPIO_PFR3_P1 *((volatile unsigned int*)(0x42660184UL)) +#define bFM3_GPIO_PFR3_P2 *((volatile unsigned int*)(0x42660188UL)) +#define bFM3_GPIO_PFR3_P3 *((volatile unsigned int*)(0x4266018CUL)) +#define bFM3_GPIO_PFR3_P4 *((volatile unsigned int*)(0x42660190UL)) +#define bFM3_GPIO_PFR3_P5 *((volatile unsigned int*)(0x42660194UL)) +#define bFM3_GPIO_PFR3_P6 *((volatile unsigned int*)(0x42660198UL)) +#define bFM3_GPIO_PFR3_P7 *((volatile unsigned int*)(0x4266019CUL)) +#define bFM3_GPIO_PFR3_P8 *((volatile unsigned int*)(0x426601A0UL)) +#define bFM3_GPIO_PFR3_P9 *((volatile unsigned int*)(0x426601A4UL)) +#define bFM3_GPIO_PFR3_PA *((volatile unsigned int*)(0x426601A8UL)) +#define bFM3_GPIO_PFR3_PB *((volatile unsigned int*)(0x426601ACUL)) +#define bFM3_GPIO_PFR3_PC *((volatile unsigned int*)(0x426601B0UL)) +#define bFM3_GPIO_PFR3_PD *((volatile unsigned int*)(0x426601B4UL)) +#define bFM3_GPIO_PFR3_PE *((volatile unsigned int*)(0x426601B8UL)) +#define bFM3_GPIO_PFR3_PF *((volatile unsigned int*)(0x426601BCUL)) +#define bFM3_GPIO_PFR4_P0 *((volatile unsigned int*)(0x42660200UL)) +#define bFM3_GPIO_PFR4_P1 *((volatile unsigned int*)(0x42660204UL)) +#define bFM3_GPIO_PFR4_P2 *((volatile unsigned int*)(0x42660208UL)) +#define bFM3_GPIO_PFR4_P3 *((volatile unsigned int*)(0x4266020CUL)) +#define bFM3_GPIO_PFR4_P4 *((volatile unsigned int*)(0x42660210UL)) +#define bFM3_GPIO_PFR4_P5 *((volatile unsigned int*)(0x42660214UL)) +#define bFM3_GPIO_PFR4_P6 *((volatile unsigned int*)(0x42660218UL)) +#define bFM3_GPIO_PFR4_P7 *((volatile unsigned int*)(0x4266021CUL)) +#define bFM3_GPIO_PFR4_P8 *((volatile unsigned int*)(0x42660220UL)) +#define bFM3_GPIO_PFR4_P9 *((volatile unsigned int*)(0x42660224UL)) +#define bFM3_GPIO_PFR4_PA *((volatile unsigned int*)(0x42660228UL)) +#define bFM3_GPIO_PFR4_PB *((volatile unsigned int*)(0x4266022CUL)) +#define bFM3_GPIO_PFR4_PC *((volatile unsigned int*)(0x42660230UL)) +#define bFM3_GPIO_PFR4_PD *((volatile unsigned int*)(0x42660234UL)) +#define bFM3_GPIO_PFR4_PE *((volatile unsigned int*)(0x42660238UL)) +#define bFM3_GPIO_PFR5_P0 *((volatile unsigned int*)(0x42660280UL)) +#define bFM3_GPIO_PFR5_P1 *((volatile unsigned int*)(0x42660284UL)) +#define bFM3_GPIO_PFR5_P2 *((volatile unsigned int*)(0x42660288UL)) +#define bFM3_GPIO_PFR5_P3 *((volatile unsigned int*)(0x4266028CUL)) +#define bFM3_GPIO_PFR5_P4 *((volatile unsigned int*)(0x42660290UL)) +#define bFM3_GPIO_PFR5_P5 *((volatile unsigned int*)(0x42660294UL)) +#define bFM3_GPIO_PFR5_P6 *((volatile unsigned int*)(0x42660298UL)) +#define bFM3_GPIO_PFR5_P7 *((volatile unsigned int*)(0x4266029CUL)) +#define bFM3_GPIO_PFR5_P8 *((volatile unsigned int*)(0x426602A0UL)) +#define bFM3_GPIO_PFR5_P9 *((volatile unsigned int*)(0x426602A4UL)) +#define bFM3_GPIO_PFR5_PA *((volatile unsigned int*)(0x426602A8UL)) +#define bFM3_GPIO_PFR5_PB *((volatile unsigned int*)(0x426602ACUL)) +#define bFM3_GPIO_PFR6_P0 *((volatile unsigned int*)(0x42660300UL)) +#define bFM3_GPIO_PFR6_P1 *((volatile unsigned int*)(0x42660304UL)) +#define bFM3_GPIO_PFR6_P2 *((volatile unsigned int*)(0x42660308UL)) +#define bFM3_GPIO_PFR6_P3 *((volatile unsigned int*)(0x4266030CUL)) +#define bFM3_GPIO_PFR6_P4 *((volatile unsigned int*)(0x42660310UL)) +#define bFM3_GPIO_PFR6_P5 *((volatile unsigned int*)(0x42660314UL)) +#define bFM3_GPIO_PFR6_P6 *((volatile unsigned int*)(0x42660318UL)) +#define bFM3_GPIO_PFR6_P7 *((volatile unsigned int*)(0x4266031CUL)) +#define bFM3_GPIO_PFR6_P8 *((volatile unsigned int*)(0x42660320UL)) +#define bFM3_GPIO_PFR7_P0 *((volatile unsigned int*)(0x42660380UL)) +#define bFM3_GPIO_PFR7_P1 *((volatile unsigned int*)(0x42660384UL)) +#define bFM3_GPIO_PFR7_P2 *((volatile unsigned int*)(0x42660388UL)) +#define bFM3_GPIO_PFR7_P3 *((volatile unsigned int*)(0x4266038CUL)) +#define bFM3_GPIO_PFR7_P4 *((volatile unsigned int*)(0x42660390UL)) +#define bFM3_GPIO_PFR8_P0 *((volatile unsigned int*)(0x42660400UL)) +#define bFM3_GPIO_PFR8_P1 *((volatile unsigned int*)(0x42660404UL)) +#define bFM3_GPIO_PCR0_P0 *((volatile unsigned int*)(0x42662000UL)) +#define bFM3_GPIO_PCR0_P1 *((volatile unsigned int*)(0x42662004UL)) +#define bFM3_GPIO_PCR0_P2 *((volatile unsigned int*)(0x42662008UL)) +#define bFM3_GPIO_PCR0_P3 *((volatile unsigned int*)(0x4266200CUL)) +#define bFM3_GPIO_PCR0_P4 *((volatile unsigned int*)(0x42662010UL)) +#define bFM3_GPIO_PCR0_P5 *((volatile unsigned int*)(0x42662014UL)) +#define bFM3_GPIO_PCR0_P6 *((volatile unsigned int*)(0x42662018UL)) +#define bFM3_GPIO_PCR0_P7 *((volatile unsigned int*)(0x4266201CUL)) +#define bFM3_GPIO_PCR0_P8 *((volatile unsigned int*)(0x42662020UL)) +#define bFM3_GPIO_PCR0_P9 *((volatile unsigned int*)(0x42662024UL)) +#define bFM3_GPIO_PCR0_PA *((volatile unsigned int*)(0x42662028UL)) +#define bFM3_GPIO_PCR0_PB *((volatile unsigned int*)(0x4266202CUL)) +#define bFM3_GPIO_PCR0_PC *((volatile unsigned int*)(0x42662030UL)) +#define bFM3_GPIO_PCR0_PD *((volatile unsigned int*)(0x42662034UL)) +#define bFM3_GPIO_PCR0_PE *((volatile unsigned int*)(0x42662038UL)) +#define bFM3_GPIO_PCR0_PF *((volatile unsigned int*)(0x4266203CUL)) +#define bFM3_GPIO_PCR1_P0 *((volatile unsigned int*)(0x42662080UL)) +#define bFM3_GPIO_PCR1_P1 *((volatile unsigned int*)(0x42662084UL)) +#define bFM3_GPIO_PCR1_P2 *((volatile unsigned int*)(0x42662088UL)) +#define bFM3_GPIO_PCR1_P3 *((volatile unsigned int*)(0x4266208CUL)) +#define bFM3_GPIO_PCR1_P4 *((volatile unsigned int*)(0x42662090UL)) +#define bFM3_GPIO_PCR1_P5 *((volatile unsigned int*)(0x42662094UL)) +#define bFM3_GPIO_PCR1_P6 *((volatile unsigned int*)(0x42662098UL)) +#define bFM3_GPIO_PCR1_P7 *((volatile unsigned int*)(0x4266209CUL)) +#define bFM3_GPIO_PCR1_P8 *((volatile unsigned int*)(0x426620A0UL)) +#define bFM3_GPIO_PCR1_P9 *((volatile unsigned int*)(0x426620A4UL)) +#define bFM3_GPIO_PCR1_PA *((volatile unsigned int*)(0x426620A8UL)) +#define bFM3_GPIO_PCR1_PB *((volatile unsigned int*)(0x426620ACUL)) +#define bFM3_GPIO_PCR1_PC *((volatile unsigned int*)(0x426620B0UL)) +#define bFM3_GPIO_PCR1_PD *((volatile unsigned int*)(0x426620B4UL)) +#define bFM3_GPIO_PCR1_PE *((volatile unsigned int*)(0x426620B8UL)) +#define bFM3_GPIO_PCR1_PF *((volatile unsigned int*)(0x426620BCUL)) +#define bFM3_GPIO_PCR2_P0 *((volatile unsigned int*)(0x42662100UL)) +#define bFM3_GPIO_PCR2_P1 *((volatile unsigned int*)(0x42662104UL)) +#define bFM3_GPIO_PCR2_P2 *((volatile unsigned int*)(0x42662108UL)) +#define bFM3_GPIO_PCR2_P3 *((volatile unsigned int*)(0x4266210CUL)) +#define bFM3_GPIO_PCR2_P4 *((volatile unsigned int*)(0x42662110UL)) +#define bFM3_GPIO_PCR2_P5 *((volatile unsigned int*)(0x42662114UL)) +#define bFM3_GPIO_PCR2_P6 *((volatile unsigned int*)(0x42662118UL)) +#define bFM3_GPIO_PCR2_P7 *((volatile unsigned int*)(0x4266211CUL)) +#define bFM3_GPIO_PCR2_P8 *((volatile unsigned int*)(0x42662120UL)) +#define bFM3_GPIO_PCR3_P0 *((volatile unsigned int*)(0x42662180UL)) +#define bFM3_GPIO_PCR3_P1 *((volatile unsigned int*)(0x42662184UL)) +#define bFM3_GPIO_PCR3_P2 *((volatile unsigned int*)(0x42662188UL)) +#define bFM3_GPIO_PCR3_P3 *((volatile unsigned int*)(0x4266218CUL)) +#define bFM3_GPIO_PCR3_P4 *((volatile unsigned int*)(0x42662190UL)) +#define bFM3_GPIO_PCR3_P5 *((volatile unsigned int*)(0x42662194UL)) +#define bFM3_GPIO_PCR3_P6 *((volatile unsigned int*)(0x42662198UL)) +#define bFM3_GPIO_PCR3_P7 *((volatile unsigned int*)(0x4266219CUL)) +#define bFM3_GPIO_PCR3_P8 *((volatile unsigned int*)(0x426621A0UL)) +#define bFM3_GPIO_PCR3_P9 *((volatile unsigned int*)(0x426621A4UL)) +#define bFM3_GPIO_PCR3_PA *((volatile unsigned int*)(0x426621A8UL)) +#define bFM3_GPIO_PCR3_PB *((volatile unsigned int*)(0x426621ACUL)) +#define bFM3_GPIO_PCR3_PC *((volatile unsigned int*)(0x426621B0UL)) +#define bFM3_GPIO_PCR3_PD *((volatile unsigned int*)(0x426621B4UL)) +#define bFM3_GPIO_PCR3_PE *((volatile unsigned int*)(0x426621B8UL)) +#define bFM3_GPIO_PCR3_PF *((volatile unsigned int*)(0x426621BCUL)) +#define bFM3_GPIO_PCR4_P0 *((volatile unsigned int*)(0x42662200UL)) +#define bFM3_GPIO_PCR4_P1 *((volatile unsigned int*)(0x42662204UL)) +#define bFM3_GPIO_PCR4_P2 *((volatile unsigned int*)(0x42662208UL)) +#define bFM3_GPIO_PCR4_P3 *((volatile unsigned int*)(0x4266220CUL)) +#define bFM3_GPIO_PCR4_P4 *((volatile unsigned int*)(0x42662210UL)) +#define bFM3_GPIO_PCR4_P5 *((volatile unsigned int*)(0x42662214UL)) +#define bFM3_GPIO_PCR4_P6 *((volatile unsigned int*)(0x42662218UL)) +#define bFM3_GPIO_PCR4_P7 *((volatile unsigned int*)(0x4266221CUL)) +#define bFM3_GPIO_PCR4_P8 *((volatile unsigned int*)(0x42662220UL)) +#define bFM3_GPIO_PCR4_P9 *((volatile unsigned int*)(0x42662224UL)) +#define bFM3_GPIO_PCR4_PA *((volatile unsigned int*)(0x42662228UL)) +#define bFM3_GPIO_PCR4_PB *((volatile unsigned int*)(0x4266222CUL)) +#define bFM3_GPIO_PCR4_PC *((volatile unsigned int*)(0x42662230UL)) +#define bFM3_GPIO_PCR4_PD *((volatile unsigned int*)(0x42662234UL)) +#define bFM3_GPIO_PCR4_PE *((volatile unsigned int*)(0x42662238UL)) +#define bFM3_GPIO_PCR5_P0 *((volatile unsigned int*)(0x42662280UL)) +#define bFM3_GPIO_PCR5_P1 *((volatile unsigned int*)(0x42662284UL)) +#define bFM3_GPIO_PCR5_P2 *((volatile unsigned int*)(0x42662288UL)) +#define bFM3_GPIO_PCR5_P3 *((volatile unsigned int*)(0x4266228CUL)) +#define bFM3_GPIO_PCR5_P4 *((volatile unsigned int*)(0x42662290UL)) +#define bFM3_GPIO_PCR5_P5 *((volatile unsigned int*)(0x42662294UL)) +#define bFM3_GPIO_PCR5_P6 *((volatile unsigned int*)(0x42662298UL)) +#define bFM3_GPIO_PCR5_P7 *((volatile unsigned int*)(0x4266229CUL)) +#define bFM3_GPIO_PCR5_P8 *((volatile unsigned int*)(0x426622A0UL)) +#define bFM3_GPIO_PCR5_P9 *((volatile unsigned int*)(0x426622A4UL)) +#define bFM3_GPIO_PCR5_PA *((volatile unsigned int*)(0x426622A8UL)) +#define bFM3_GPIO_PCR5_PB *((volatile unsigned int*)(0x426622ACUL)) +#define bFM3_GPIO_PCR6_P0 *((volatile unsigned int*)(0x42662300UL)) +#define bFM3_GPIO_PCR6_P1 *((volatile unsigned int*)(0x42662304UL)) +#define bFM3_GPIO_PCR6_P2 *((volatile unsigned int*)(0x42662308UL)) +#define bFM3_GPIO_PCR6_P3 *((volatile unsigned int*)(0x4266230CUL)) +#define bFM3_GPIO_PCR6_P4 *((volatile unsigned int*)(0x42662310UL)) +#define bFM3_GPIO_PCR6_P5 *((volatile unsigned int*)(0x42662314UL)) +#define bFM3_GPIO_PCR6_P6 *((volatile unsigned int*)(0x42662318UL)) +#define bFM3_GPIO_PCR6_P7 *((volatile unsigned int*)(0x4266231CUL)) +#define bFM3_GPIO_PCR6_P8 *((volatile unsigned int*)(0x42662320UL)) +#define bFM3_GPIO_PCR7_P0 *((volatile unsigned int*)(0x42662380UL)) +#define bFM3_GPIO_PCR7_P1 *((volatile unsigned int*)(0x42662384UL)) +#define bFM3_GPIO_PCR7_P2 *((volatile unsigned int*)(0x42662388UL)) +#define bFM3_GPIO_PCR7_P3 *((volatile unsigned int*)(0x4266238CUL)) +#define bFM3_GPIO_PCR7_P4 *((volatile unsigned int*)(0x42662390UL)) +#define bFM3_GPIO_DDR0_P0 *((volatile unsigned int*)(0x42664000UL)) +#define bFM3_GPIO_DDR0_P1 *((volatile unsigned int*)(0x42664004UL)) +#define bFM3_GPIO_DDR0_P2 *((volatile unsigned int*)(0x42664008UL)) +#define bFM3_GPIO_DDR0_P3 *((volatile unsigned int*)(0x4266400CUL)) +#define bFM3_GPIO_DDR0_P4 *((volatile unsigned int*)(0x42664010UL)) +#define bFM3_GPIO_DDR0_P5 *((volatile unsigned int*)(0x42664014UL)) +#define bFM3_GPIO_DDR0_P6 *((volatile unsigned int*)(0x42664018UL)) +#define bFM3_GPIO_DDR0_P7 *((volatile unsigned int*)(0x4266401CUL)) +#define bFM3_GPIO_DDR0_P8 *((volatile unsigned int*)(0x42664020UL)) +#define bFM3_GPIO_DDR0_P9 *((volatile unsigned int*)(0x42664024UL)) +#define bFM3_GPIO_DDR0_PA *((volatile unsigned int*)(0x42664028UL)) +#define bFM3_GPIO_DDR0_PB *((volatile unsigned int*)(0x4266402CUL)) +#define bFM3_GPIO_DDR0_PC *((volatile unsigned int*)(0x42664030UL)) +#define bFM3_GPIO_DDR0_PD *((volatile unsigned int*)(0x42664034UL)) +#define bFM3_GPIO_DDR0_PE *((volatile unsigned int*)(0x42664038UL)) +#define bFM3_GPIO_DDR0_PF *((volatile unsigned int*)(0x4266403CUL)) +#define bFM3_GPIO_DDR1_P0 *((volatile unsigned int*)(0x42664080UL)) +#define bFM3_GPIO_DDR1_P1 *((volatile unsigned int*)(0x42664084UL)) +#define bFM3_GPIO_DDR1_P2 *((volatile unsigned int*)(0x42664088UL)) +#define bFM3_GPIO_DDR1_P3 *((volatile unsigned int*)(0x4266408CUL)) +#define bFM3_GPIO_DDR1_P4 *((volatile unsigned int*)(0x42664090UL)) +#define bFM3_GPIO_DDR1_P5 *((volatile unsigned int*)(0x42664094UL)) +#define bFM3_GPIO_DDR1_P6 *((volatile unsigned int*)(0x42664098UL)) +#define bFM3_GPIO_DDR1_P7 *((volatile unsigned int*)(0x4266409CUL)) +#define bFM3_GPIO_DDR1_P8 *((volatile unsigned int*)(0x426640A0UL)) +#define bFM3_GPIO_DDR1_P9 *((volatile unsigned int*)(0x426640A4UL)) +#define bFM3_GPIO_DDR1_PA *((volatile unsigned int*)(0x426640A8UL)) +#define bFM3_GPIO_DDR1_PB *((volatile unsigned int*)(0x426640ACUL)) +#define bFM3_GPIO_DDR1_PC *((volatile unsigned int*)(0x426640B0UL)) +#define bFM3_GPIO_DDR1_PD *((volatile unsigned int*)(0x426640B4UL)) +#define bFM3_GPIO_DDR1_PE *((volatile unsigned int*)(0x426640B8UL)) +#define bFM3_GPIO_DDR1_PF *((volatile unsigned int*)(0x426640BCUL)) +#define bFM3_GPIO_DDR2_P0 *((volatile unsigned int*)(0x42664100UL)) +#define bFM3_GPIO_DDR2_P1 *((volatile unsigned int*)(0x42664104UL)) +#define bFM3_GPIO_DDR2_P2 *((volatile unsigned int*)(0x42664108UL)) +#define bFM3_GPIO_DDR2_P3 *((volatile unsigned int*)(0x4266410CUL)) +#define bFM3_GPIO_DDR2_P4 *((volatile unsigned int*)(0x42664110UL)) +#define bFM3_GPIO_DDR2_P5 *((volatile unsigned int*)(0x42664114UL)) +#define bFM3_GPIO_DDR2_P6 *((volatile unsigned int*)(0x42664118UL)) +#define bFM3_GPIO_DDR2_P7 *((volatile unsigned int*)(0x4266411CUL)) +#define bFM3_GPIO_DDR2_P8 *((volatile unsigned int*)(0x42664120UL)) +#define bFM3_GPIO_DDR3_P0 *((volatile unsigned int*)(0x42664180UL)) +#define bFM3_GPIO_DDR3_P1 *((volatile unsigned int*)(0x42664184UL)) +#define bFM3_GPIO_DDR3_P2 *((volatile unsigned int*)(0x42664188UL)) +#define bFM3_GPIO_DDR3_P3 *((volatile unsigned int*)(0x4266418CUL)) +#define bFM3_GPIO_DDR3_P4 *((volatile unsigned int*)(0x42664190UL)) +#define bFM3_GPIO_DDR3_P5 *((volatile unsigned int*)(0x42664194UL)) +#define bFM3_GPIO_DDR3_P6 *((volatile unsigned int*)(0x42664198UL)) +#define bFM3_GPIO_DDR3_P7 *((volatile unsigned int*)(0x4266419CUL)) +#define bFM3_GPIO_DDR3_P8 *((volatile unsigned int*)(0x426641A0UL)) +#define bFM3_GPIO_DDR3_P9 *((volatile unsigned int*)(0x426641A4UL)) +#define bFM3_GPIO_DDR3_PA *((volatile unsigned int*)(0x426641A8UL)) +#define bFM3_GPIO_DDR3_PB *((volatile unsigned int*)(0x426641ACUL)) +#define bFM3_GPIO_DDR3_PC *((volatile unsigned int*)(0x426641B0UL)) +#define bFM3_GPIO_DDR3_PD *((volatile unsigned int*)(0x426641B4UL)) +#define bFM3_GPIO_DDR3_PE *((volatile unsigned int*)(0x426641B8UL)) +#define bFM3_GPIO_DDR3_PF *((volatile unsigned int*)(0x426641BCUL)) +#define bFM3_GPIO_DDR4_P0 *((volatile unsigned int*)(0x42664200UL)) +#define bFM3_GPIO_DDR4_P1 *((volatile unsigned int*)(0x42664204UL)) +#define bFM3_GPIO_DDR4_P2 *((volatile unsigned int*)(0x42664208UL)) +#define bFM3_GPIO_DDR4_P3 *((volatile unsigned int*)(0x4266420CUL)) +#define bFM3_GPIO_DDR4_P4 *((volatile unsigned int*)(0x42664210UL)) +#define bFM3_GPIO_DDR4_P5 *((volatile unsigned int*)(0x42664214UL)) +#define bFM3_GPIO_DDR4_P6 *((volatile unsigned int*)(0x42664218UL)) +#define bFM3_GPIO_DDR4_P7 *((volatile unsigned int*)(0x4266421CUL)) +#define bFM3_GPIO_DDR4_P8 *((volatile unsigned int*)(0x42664220UL)) +#define bFM3_GPIO_DDR4_P9 *((volatile unsigned int*)(0x42664224UL)) +#define bFM3_GPIO_DDR4_PA *((volatile unsigned int*)(0x42664228UL)) +#define bFM3_GPIO_DDR4_PB *((volatile unsigned int*)(0x4266422CUL)) +#define bFM3_GPIO_DDR4_PC *((volatile unsigned int*)(0x42664230UL)) +#define bFM3_GPIO_DDR4_PD *((volatile unsigned int*)(0x42664234UL)) +#define bFM3_GPIO_DDR4_PE *((volatile unsigned int*)(0x42664238UL)) +#define bFM3_GPIO_DDR5_P0 *((volatile unsigned int*)(0x42664280UL)) +#define bFM3_GPIO_DDR5_P1 *((volatile unsigned int*)(0x42664284UL)) +#define bFM3_GPIO_DDR5_P2 *((volatile unsigned int*)(0x42664288UL)) +#define bFM3_GPIO_DDR5_P3 *((volatile unsigned int*)(0x4266428CUL)) +#define bFM3_GPIO_DDR5_P4 *((volatile unsigned int*)(0x42664290UL)) +#define bFM3_GPIO_DDR5_P5 *((volatile unsigned int*)(0x42664294UL)) +#define bFM3_GPIO_DDR5_P6 *((volatile unsigned int*)(0x42664298UL)) +#define bFM3_GPIO_DDR5_P7 *((volatile unsigned int*)(0x4266429CUL)) +#define bFM3_GPIO_DDR5_P8 *((volatile unsigned int*)(0x426642A0UL)) +#define bFM3_GPIO_DDR5_P9 *((volatile unsigned int*)(0x426642A4UL)) +#define bFM3_GPIO_DDR5_PA *((volatile unsigned int*)(0x426642A8UL)) +#define bFM3_GPIO_DDR5_PB *((volatile unsigned int*)(0x426642ACUL)) +#define bFM3_GPIO_DDR6_P0 *((volatile unsigned int*)(0x42664300UL)) +#define bFM3_GPIO_DDR6_P1 *((volatile unsigned int*)(0x42664304UL)) +#define bFM3_GPIO_DDR6_P2 *((volatile unsigned int*)(0x42664308UL)) +#define bFM3_GPIO_DDR6_P3 *((volatile unsigned int*)(0x4266430CUL)) +#define bFM3_GPIO_DDR6_P4 *((volatile unsigned int*)(0x42664310UL)) +#define bFM3_GPIO_DDR6_P5 *((volatile unsigned int*)(0x42664314UL)) +#define bFM3_GPIO_DDR6_P6 *((volatile unsigned int*)(0x42664318UL)) +#define bFM3_GPIO_DDR6_P7 *((volatile unsigned int*)(0x4266431CUL)) +#define bFM3_GPIO_DDR6_P8 *((volatile unsigned int*)(0x42664320UL)) +#define bFM3_GPIO_DDR7_P0 *((volatile unsigned int*)(0x42664380UL)) +#define bFM3_GPIO_DDR7_P1 *((volatile unsigned int*)(0x42664384UL)) +#define bFM3_GPIO_DDR7_P2 *((volatile unsigned int*)(0x42664388UL)) +#define bFM3_GPIO_DDR7_P3 *((volatile unsigned int*)(0x4266438CUL)) +#define bFM3_GPIO_DDR7_P4 *((volatile unsigned int*)(0x42664390UL)) +#define bFM3_GPIO_DDR8_P0 *((volatile unsigned int*)(0x42664400UL)) +#define bFM3_GPIO_DDR8_P1 *((volatile unsigned int*)(0x42664404UL)) +#define bFM3_GPIO_PDIR0_P0 *((volatile unsigned int*)(0x42666000UL)) +#define bFM3_GPIO_PDIR0_P1 *((volatile unsigned int*)(0x42666004UL)) +#define bFM3_GPIO_PDIR0_P2 *((volatile unsigned int*)(0x42666008UL)) +#define bFM3_GPIO_PDIR0_P3 *((volatile unsigned int*)(0x4266600CUL)) +#define bFM3_GPIO_PDIR0_P4 *((volatile unsigned int*)(0x42666010UL)) +#define bFM3_GPIO_PDIR0_P5 *((volatile unsigned int*)(0x42666014UL)) +#define bFM3_GPIO_PDIR0_P6 *((volatile unsigned int*)(0x42666018UL)) +#define bFM3_GPIO_PDIR0_P7 *((volatile unsigned int*)(0x4266601CUL)) +#define bFM3_GPIO_PDIR0_P8 *((volatile unsigned int*)(0x42666020UL)) +#define bFM3_GPIO_PDIR0_P9 *((volatile unsigned int*)(0x42666024UL)) +#define bFM3_GPIO_PDIR0_PA *((volatile unsigned int*)(0x42666028UL)) +#define bFM3_GPIO_PDIR0_PB *((volatile unsigned int*)(0x4266602CUL)) +#define bFM3_GPIO_PDIR0_PC *((volatile unsigned int*)(0x42666030UL)) +#define bFM3_GPIO_PDIR0_PD *((volatile unsigned int*)(0x42666034UL)) +#define bFM3_GPIO_PDIR0_PE *((volatile unsigned int*)(0x42666038UL)) +#define bFM3_GPIO_PDIR0_PF *((volatile unsigned int*)(0x4266603CUL)) +#define bFM3_GPIO_PDIR1_P0 *((volatile unsigned int*)(0x42666080UL)) +#define bFM3_GPIO_PDIR1_P1 *((volatile unsigned int*)(0x42666084UL)) +#define bFM3_GPIO_PDIR1_P2 *((volatile unsigned int*)(0x42666088UL)) +#define bFM3_GPIO_PDIR1_P3 *((volatile unsigned int*)(0x4266608CUL)) +#define bFM3_GPIO_PDIR1_P4 *((volatile unsigned int*)(0x42666090UL)) +#define bFM3_GPIO_PDIR1_P5 *((volatile unsigned int*)(0x42666094UL)) +#define bFM3_GPIO_PDIR1_P6 *((volatile unsigned int*)(0x42666098UL)) +#define bFM3_GPIO_PDIR1_P7 *((volatile unsigned int*)(0x4266609CUL)) +#define bFM3_GPIO_PDIR1_P8 *((volatile unsigned int*)(0x426660A0UL)) +#define bFM3_GPIO_PDIR1_P9 *((volatile unsigned int*)(0x426660A4UL)) +#define bFM3_GPIO_PDIR1_PA *((volatile unsigned int*)(0x426660A8UL)) +#define bFM3_GPIO_PDIR1_PB *((volatile unsigned int*)(0x426660ACUL)) +#define bFM3_GPIO_PDIR1_PC *((volatile unsigned int*)(0x426660B0UL)) +#define bFM3_GPIO_PDIR1_PD *((volatile unsigned int*)(0x426660B4UL)) +#define bFM3_GPIO_PDIR1_PE *((volatile unsigned int*)(0x426660B8UL)) +#define bFM3_GPIO_PDIR1_PF *((volatile unsigned int*)(0x426660BCUL)) +#define bFM3_GPIO_PDIR2_P0 *((volatile unsigned int*)(0x42666100UL)) +#define bFM3_GPIO_PDIR2_P1 *((volatile unsigned int*)(0x42666104UL)) +#define bFM3_GPIO_PDIR2_P2 *((volatile unsigned int*)(0x42666108UL)) +#define bFM3_GPIO_PDIR2_P3 *((volatile unsigned int*)(0x4266610CUL)) +#define bFM3_GPIO_PDIR2_P4 *((volatile unsigned int*)(0x42666110UL)) +#define bFM3_GPIO_PDIR2_P5 *((volatile unsigned int*)(0x42666114UL)) +#define bFM3_GPIO_PDIR2_P6 *((volatile unsigned int*)(0x42666118UL)) +#define bFM3_GPIO_PDIR2_P7 *((volatile unsigned int*)(0x4266611CUL)) +#define bFM3_GPIO_PDIR2_P8 *((volatile unsigned int*)(0x42666120UL)) +#define bFM3_GPIO_PDIR3_P0 *((volatile unsigned int*)(0x42666180UL)) +#define bFM3_GPIO_PDIR3_P1 *((volatile unsigned int*)(0x42666184UL)) +#define bFM3_GPIO_PDIR3_P2 *((volatile unsigned int*)(0x42666188UL)) +#define bFM3_GPIO_PDIR3_P3 *((volatile unsigned int*)(0x4266618CUL)) +#define bFM3_GPIO_PDIR3_P4 *((volatile unsigned int*)(0x42666190UL)) +#define bFM3_GPIO_PDIR3_P5 *((volatile unsigned int*)(0x42666194UL)) +#define bFM3_GPIO_PDIR3_P6 *((volatile unsigned int*)(0x42666198UL)) +#define bFM3_GPIO_PDIR3_P7 *((volatile unsigned int*)(0x4266619CUL)) +#define bFM3_GPIO_PDIR3_P8 *((volatile unsigned int*)(0x426661A0UL)) +#define bFM3_GPIO_PDIR3_P9 *((volatile unsigned int*)(0x426661A4UL)) +#define bFM3_GPIO_PDIR3_PA *((volatile unsigned int*)(0x426661A8UL)) +#define bFM3_GPIO_PDIR3_PB *((volatile unsigned int*)(0x426661ACUL)) +#define bFM3_GPIO_PDIR3_PC *((volatile unsigned int*)(0x426661B0UL)) +#define bFM3_GPIO_PDIR3_PD *((volatile unsigned int*)(0x426661B4UL)) +#define bFM3_GPIO_PDIR3_PE *((volatile unsigned int*)(0x426661B8UL)) +#define bFM3_GPIO_PDIR3_PF *((volatile unsigned int*)(0x426661BCUL)) +#define bFM3_GPIO_PDIR4_P0 *((volatile unsigned int*)(0x42666200UL)) +#define bFM3_GPIO_PDIR4_P1 *((volatile unsigned int*)(0x42666204UL)) +#define bFM3_GPIO_PDIR4_P2 *((volatile unsigned int*)(0x42666208UL)) +#define bFM3_GPIO_PDIR4_P3 *((volatile unsigned int*)(0x4266620CUL)) +#define bFM3_GPIO_PDIR4_P4 *((volatile unsigned int*)(0x42666210UL)) +#define bFM3_GPIO_PDIR4_P5 *((volatile unsigned int*)(0x42666214UL)) +#define bFM3_GPIO_PDIR4_P6 *((volatile unsigned int*)(0x42666218UL)) +#define bFM3_GPIO_PDIR4_P7 *((volatile unsigned int*)(0x4266621CUL)) +#define bFM3_GPIO_PDIR4_P8 *((volatile unsigned int*)(0x42666220UL)) +#define bFM3_GPIO_PDIR4_P9 *((volatile unsigned int*)(0x42666224UL)) +#define bFM3_GPIO_PDIR4_PA *((volatile unsigned int*)(0x42666228UL)) +#define bFM3_GPIO_PDIR4_PB *((volatile unsigned int*)(0x4266622CUL)) +#define bFM3_GPIO_PDIR4_PC *((volatile unsigned int*)(0x42666230UL)) +#define bFM3_GPIO_PDIR4_PD *((volatile unsigned int*)(0x42666234UL)) +#define bFM3_GPIO_PDIR4_PE *((volatile unsigned int*)(0x42666238UL)) +#define bFM3_GPIO_PDIR5_P0 *((volatile unsigned int*)(0x42666280UL)) +#define bFM3_GPIO_PDIR5_P1 *((volatile unsigned int*)(0x42666284UL)) +#define bFM3_GPIO_PDIR5_P2 *((volatile unsigned int*)(0x42666288UL)) +#define bFM3_GPIO_PDIR5_P3 *((volatile unsigned int*)(0x4266628CUL)) +#define bFM3_GPIO_PDIR5_P4 *((volatile unsigned int*)(0x42666290UL)) +#define bFM3_GPIO_PDIR5_P5 *((volatile unsigned int*)(0x42666294UL)) +#define bFM3_GPIO_PDIR5_P6 *((volatile unsigned int*)(0x42666298UL)) +#define bFM3_GPIO_PDIR5_P7 *((volatile unsigned int*)(0x4266629CUL)) +#define bFM3_GPIO_PDIR5_P8 *((volatile unsigned int*)(0x426662A0UL)) +#define bFM3_GPIO_PDIR5_P9 *((volatile unsigned int*)(0x426662A4UL)) +#define bFM3_GPIO_PDIR5_PA *((volatile unsigned int*)(0x426662A8UL)) +#define bFM3_GPIO_PDIR5_PB *((volatile unsigned int*)(0x426662ACUL)) +#define bFM3_GPIO_PDIR6_P0 *((volatile unsigned int*)(0x42666300UL)) +#define bFM3_GPIO_PDIR6_P1 *((volatile unsigned int*)(0x42666304UL)) +#define bFM3_GPIO_PDIR6_P2 *((volatile unsigned int*)(0x42666308UL)) +#define bFM3_GPIO_PDIR6_P3 *((volatile unsigned int*)(0x4266630CUL)) +#define bFM3_GPIO_PDIR6_P4 *((volatile unsigned int*)(0x42666310UL)) +#define bFM3_GPIO_PDIR6_P5 *((volatile unsigned int*)(0x42666314UL)) +#define bFM3_GPIO_PDIR6_P6 *((volatile unsigned int*)(0x42666318UL)) +#define bFM3_GPIO_PDIR6_P7 *((volatile unsigned int*)(0x4266631CUL)) +#define bFM3_GPIO_PDIR6_P8 *((volatile unsigned int*)(0x42666320UL)) +#define bFM3_GPIO_PDIR7_P0 *((volatile unsigned int*)(0x42666380UL)) +#define bFM3_GPIO_PDIR7_P1 *((volatile unsigned int*)(0x42666384UL)) +#define bFM3_GPIO_PDIR7_P2 *((volatile unsigned int*)(0x42666388UL)) +#define bFM3_GPIO_PDIR7_P3 *((volatile unsigned int*)(0x4266638CUL)) +#define bFM3_GPIO_PDIR7_P4 *((volatile unsigned int*)(0x42666390UL)) +#define bFM3_GPIO_PDIR8_P0 *((volatile unsigned int*)(0x42666400UL)) +#define bFM3_GPIO_PDIR8_P1 *((volatile unsigned int*)(0x42666404UL)) +#define bFM3_GPIO_PDOR0_P0 *((volatile unsigned int*)(0x42668000UL)) +#define bFM3_GPIO_PDOR0_P1 *((volatile unsigned int*)(0x42668004UL)) +#define bFM3_GPIO_PDOR0_P2 *((volatile unsigned int*)(0x42668008UL)) +#define bFM3_GPIO_PDOR0_P3 *((volatile unsigned int*)(0x4266800CUL)) +#define bFM3_GPIO_PDOR0_P4 *((volatile unsigned int*)(0x42668010UL)) +#define bFM3_GPIO_PDOR0_P5 *((volatile unsigned int*)(0x42668014UL)) +#define bFM3_GPIO_PDOR0_P6 *((volatile unsigned int*)(0x42668018UL)) +#define bFM3_GPIO_PDOR0_P7 *((volatile unsigned int*)(0x4266801CUL)) +#define bFM3_GPIO_PDOR0_P8 *((volatile unsigned int*)(0x42668020UL)) +#define bFM3_GPIO_PDOR0_P9 *((volatile unsigned int*)(0x42668024UL)) +#define bFM3_GPIO_PDOR0_PA *((volatile unsigned int*)(0x42668028UL)) +#define bFM3_GPIO_PDOR0_PB *((volatile unsigned int*)(0x4266802CUL)) +#define bFM3_GPIO_PDOR0_PC *((volatile unsigned int*)(0x42668030UL)) +#define bFM3_GPIO_PDOR0_PD *((volatile unsigned int*)(0x42668034UL)) +#define bFM3_GPIO_PDOR0_PE *((volatile unsigned int*)(0x42668038UL)) +#define bFM3_GPIO_PDOR0_PF *((volatile unsigned int*)(0x4266803CUL)) +#define bFM3_GPIO_PDOR1_P0 *((volatile unsigned int*)(0x42668080UL)) +#define bFM3_GPIO_PDOR1_P1 *((volatile unsigned int*)(0x42668084UL)) +#define bFM3_GPIO_PDOR1_P2 *((volatile unsigned int*)(0x42668088UL)) +#define bFM3_GPIO_PDOR1_P3 *((volatile unsigned int*)(0x4266808CUL)) +#define bFM3_GPIO_PDOR1_P4 *((volatile unsigned int*)(0x42668090UL)) +#define bFM3_GPIO_PDOR1_P5 *((volatile unsigned int*)(0x42668094UL)) +#define bFM3_GPIO_PDOR1_P6 *((volatile unsigned int*)(0x42668098UL)) +#define bFM3_GPIO_PDOR1_P7 *((volatile unsigned int*)(0x4266809CUL)) +#define bFM3_GPIO_PDOR1_P8 *((volatile unsigned int*)(0x426680A0UL)) +#define bFM3_GPIO_PDOR1_P9 *((volatile unsigned int*)(0x426680A4UL)) +#define bFM3_GPIO_PDOR1_PA *((volatile unsigned int*)(0x426680A8UL)) +#define bFM3_GPIO_PDOR1_PB *((volatile unsigned int*)(0x426680ACUL)) +#define bFM3_GPIO_PDOR1_PC *((volatile unsigned int*)(0x426680B0UL)) +#define bFM3_GPIO_PDOR1_PD *((volatile unsigned int*)(0x426680B4UL)) +#define bFM3_GPIO_PDOR1_PE *((volatile unsigned int*)(0x426680B8UL)) +#define bFM3_GPIO_PDOR1_PF *((volatile unsigned int*)(0x426680BCUL)) +#define bFM3_GPIO_PDOR2_P0 *((volatile unsigned int*)(0x42668100UL)) +#define bFM3_GPIO_PDOR2_P1 *((volatile unsigned int*)(0x42668104UL)) +#define bFM3_GPIO_PDOR2_P2 *((volatile unsigned int*)(0x42668108UL)) +#define bFM3_GPIO_PDOR2_P3 *((volatile unsigned int*)(0x4266810CUL)) +#define bFM3_GPIO_PDOR2_P4 *((volatile unsigned int*)(0x42668110UL)) +#define bFM3_GPIO_PDOR2_P5 *((volatile unsigned int*)(0x42668114UL)) +#define bFM3_GPIO_PDOR2_P6 *((volatile unsigned int*)(0x42668118UL)) +#define bFM3_GPIO_PDOR2_P7 *((volatile unsigned int*)(0x4266811CUL)) +#define bFM3_GPIO_PDOR2_P8 *((volatile unsigned int*)(0x42668120UL)) +#define bFM3_GPIO_PDOR3_P0 *((volatile unsigned int*)(0x42668180UL)) +#define bFM3_GPIO_PDOR3_P1 *((volatile unsigned int*)(0x42668184UL)) +#define bFM3_GPIO_PDOR3_P2 *((volatile unsigned int*)(0x42668188UL)) +#define bFM3_GPIO_PDOR3_P3 *((volatile unsigned int*)(0x4266818CUL)) +#define bFM3_GPIO_PDOR3_P4 *((volatile unsigned int*)(0x42668190UL)) +#define bFM3_GPIO_PDOR3_P5 *((volatile unsigned int*)(0x42668194UL)) +#define bFM3_GPIO_PDOR3_P6 *((volatile unsigned int*)(0x42668198UL)) +#define bFM3_GPIO_PDOR3_P7 *((volatile unsigned int*)(0x4266819CUL)) +#define bFM3_GPIO_PDOR3_P8 *((volatile unsigned int*)(0x426681A0UL)) +#define bFM3_GPIO_PDOR3_P9 *((volatile unsigned int*)(0x426681A4UL)) +#define bFM3_GPIO_PDOR3_PA *((volatile unsigned int*)(0x426681A8UL)) +#define bFM3_GPIO_PDOR3_PB *((volatile unsigned int*)(0x426681ACUL)) +#define bFM3_GPIO_PDOR3_PC *((volatile unsigned int*)(0x426681B0UL)) +#define bFM3_GPIO_PDOR3_PD *((volatile unsigned int*)(0x426681B4UL)) +#define bFM3_GPIO_PDOR3_PE *((volatile unsigned int*)(0x426681B8UL)) +#define bFM3_GPIO_PDOR3_PF *((volatile unsigned int*)(0x426681BCUL)) +#define bFM3_GPIO_PDOR4_P0 *((volatile unsigned int*)(0x42668200UL)) +#define bFM3_GPIO_PDOR4_P1 *((volatile unsigned int*)(0x42668204UL)) +#define bFM3_GPIO_PDOR4_P2 *((volatile unsigned int*)(0x42668208UL)) +#define bFM3_GPIO_PDOR4_P3 *((volatile unsigned int*)(0x4266820CUL)) +#define bFM3_GPIO_PDOR4_P4 *((volatile unsigned int*)(0x42668210UL)) +#define bFM3_GPIO_PDOR4_P5 *((volatile unsigned int*)(0x42668214UL)) +#define bFM3_GPIO_PDOR4_P6 *((volatile unsigned int*)(0x42668218UL)) +#define bFM3_GPIO_PDOR4_P7 *((volatile unsigned int*)(0x4266821CUL)) +#define bFM3_GPIO_PDOR4_P8 *((volatile unsigned int*)(0x42668220UL)) +#define bFM3_GPIO_PDOR4_P9 *((volatile unsigned int*)(0x42668224UL)) +#define bFM3_GPIO_PDOR4_PA *((volatile unsigned int*)(0x42668228UL)) +#define bFM3_GPIO_PDOR4_PB *((volatile unsigned int*)(0x4266822CUL)) +#define bFM3_GPIO_PDOR4_PC *((volatile unsigned int*)(0x42668230UL)) +#define bFM3_GPIO_PDOR4_PD *((volatile unsigned int*)(0x42668234UL)) +#define bFM3_GPIO_PDOR4_PE *((volatile unsigned int*)(0x42668238UL)) +#define bFM3_GPIO_PDOR5_P0 *((volatile unsigned int*)(0x42668280UL)) +#define bFM3_GPIO_PDOR5_P1 *((volatile unsigned int*)(0x42668284UL)) +#define bFM3_GPIO_PDOR5_P2 *((volatile unsigned int*)(0x42668288UL)) +#define bFM3_GPIO_PDOR5_P3 *((volatile unsigned int*)(0x4266828CUL)) +#define bFM3_GPIO_PDOR5_P4 *((volatile unsigned int*)(0x42668290UL)) +#define bFM3_GPIO_PDOR5_P5 *((volatile unsigned int*)(0x42668294UL)) +#define bFM3_GPIO_PDOR5_P6 *((volatile unsigned int*)(0x42668298UL)) +#define bFM3_GPIO_PDOR5_P7 *((volatile unsigned int*)(0x4266829CUL)) +#define bFM3_GPIO_PDOR5_P8 *((volatile unsigned int*)(0x426682A0UL)) +#define bFM3_GPIO_PDOR5_P9 *((volatile unsigned int*)(0x426682A4UL)) +#define bFM3_GPIO_PDOR5_PA *((volatile unsigned int*)(0x426682A8UL)) +#define bFM3_GPIO_PDOR5_PB *((volatile unsigned int*)(0x426682ACUL)) +#define bFM3_GPIO_PDOR6_P0 *((volatile unsigned int*)(0x42668300UL)) +#define bFM3_GPIO_PDOR6_P1 *((volatile unsigned int*)(0x42668304UL)) +#define bFM3_GPIO_PDOR6_P2 *((volatile unsigned int*)(0x42668308UL)) +#define bFM3_GPIO_PDOR6_P3 *((volatile unsigned int*)(0x4266830CUL)) +#define bFM3_GPIO_PDOR6_P4 *((volatile unsigned int*)(0x42668310UL)) +#define bFM3_GPIO_PDOR6_P5 *((volatile unsigned int*)(0x42668314UL)) +#define bFM3_GPIO_PDOR6_P6 *((volatile unsigned int*)(0x42668318UL)) +#define bFM3_GPIO_PDOR6_P7 *((volatile unsigned int*)(0x4266831CUL)) +#define bFM3_GPIO_PDOR6_P8 *((volatile unsigned int*)(0x42668320UL)) +#define bFM3_GPIO_PDOR7_P0 *((volatile unsigned int*)(0x42668380UL)) +#define bFM3_GPIO_PDOR7_P1 *((volatile unsigned int*)(0x42668384UL)) +#define bFM3_GPIO_PDOR7_P2 *((volatile unsigned int*)(0x42668388UL)) +#define bFM3_GPIO_PDOR7_P3 *((volatile unsigned int*)(0x4266838CUL)) +#define bFM3_GPIO_PDOR7_P4 *((volatile unsigned int*)(0x42668390UL)) +#define bFM3_GPIO_PDOR8_P0 *((volatile unsigned int*)(0x42668400UL)) +#define bFM3_GPIO_PDOR8_P1 *((volatile unsigned int*)(0x42668404UL)) +#define bFM3_GPIO_ADE_AN0 *((volatile unsigned int*)(0x4266A000UL)) +#define bFM3_GPIO_ADE_AN1 *((volatile unsigned int*)(0x4266A004UL)) +#define bFM3_GPIO_ADE_AN2 *((volatile unsigned int*)(0x4266A008UL)) +#define bFM3_GPIO_ADE_AN3 *((volatile unsigned int*)(0x4266A00CUL)) +#define bFM3_GPIO_ADE_AN4 *((volatile unsigned int*)(0x4266A010UL)) +#define bFM3_GPIO_ADE_AN5 *((volatile unsigned int*)(0x4266A014UL)) +#define bFM3_GPIO_ADE_AN6 *((volatile unsigned int*)(0x4266A018UL)) +#define bFM3_GPIO_ADE_AN7 *((volatile unsigned int*)(0x4266A01CUL)) +#define bFM3_GPIO_ADE_AN8 *((volatile unsigned int*)(0x4266A020UL)) +#define bFM3_GPIO_ADE_AN9 *((volatile unsigned int*)(0x4266A024UL)) +#define bFM3_GPIO_ADE_ANA *((volatile unsigned int*)(0x4266A028UL)) +#define bFM3_GPIO_ADE_ANB *((volatile unsigned int*)(0x4266A02CUL)) +#define bFM3_GPIO_ADE_ANC *((volatile unsigned int*)(0x4266A030UL)) +#define bFM3_GPIO_ADE_AND *((volatile unsigned int*)(0x4266A034UL)) +#define bFM3_GPIO_ADE_ANE *((volatile unsigned int*)(0x4266A038UL)) +#define bFM3_GPIO_ADE_ANF *((volatile unsigned int*)(0x4266A03CUL)) +#define bFM3_GPIO_SPSR_SUBXC *((volatile unsigned int*)(0x4266B000UL)) +#define bFM3_GPIO_SPSR_USB0C *((volatile unsigned int*)(0x4266B010UL)) +#define bFM3_GPIO_EPFR00_NMIS *((volatile unsigned int*)(0x4266C000UL)) +#define bFM3_GPIO_EPFR00_CROUTE *((volatile unsigned int*)(0x4266C004UL)) +#define bFM3_GPIO_EPFR00_USB0PE *((volatile unsigned int*)(0x4266C024UL)) +#define bFM3_GPIO_EPFR00_JTAGEN0B *((volatile unsigned int*)(0x4266C040UL)) +#define bFM3_GPIO_EPFR00_JTAGEN1S *((volatile unsigned int*)(0x4266C044UL)) +#define bFM3_GPIO_EPFR00_TRC0E *((volatile unsigned int*)(0x4266C060UL)) +#define bFM3_GPIO_EPFR00_TRC1E *((volatile unsigned int*)(0x4266C064UL)) +#define bFM3_GPIO_EPFR01_RTO00E0 *((volatile unsigned int*)(0x4266C080UL)) +#define bFM3_GPIO_EPFR01_RTO00E1 *((volatile unsigned int*)(0x4266C084UL)) +#define bFM3_GPIO_EPFR01_RTO01E0 *((volatile unsigned int*)(0x4266C088UL)) +#define bFM3_GPIO_EPFR01_RTO01E1 *((volatile unsigned int*)(0x4266C08CUL)) +#define bFM3_GPIO_EPFR01_RTO02E0 *((volatile unsigned int*)(0x4266C090UL)) +#define bFM3_GPIO_EPFR01_RTO02E1 *((volatile unsigned int*)(0x4266C094UL)) +#define bFM3_GPIO_EPFR01_RTO03E0 *((volatile unsigned int*)(0x4266C098UL)) +#define bFM3_GPIO_EPFR01_RTO03E1 *((volatile unsigned int*)(0x4266C09CUL)) +#define bFM3_GPIO_EPFR01_RTO04E0 *((volatile unsigned int*)(0x4266C0A0UL)) +#define bFM3_GPIO_EPFR01_RTO04E1 *((volatile unsigned int*)(0x4266C0A4UL)) +#define bFM3_GPIO_EPFR01_RTO05E0 *((volatile unsigned int*)(0x4266C0A8UL)) +#define bFM3_GPIO_EPFR01_RTO05E1 *((volatile unsigned int*)(0x4266C0ACUL)) +#define bFM3_GPIO_EPFR01_DTTI0C *((volatile unsigned int*)(0x4266C0B0UL)) +#define bFM3_GPIO_EPFR01_DTTI0S0 *((volatile unsigned int*)(0x4266C0C0UL)) +#define bFM3_GPIO_EPFR01_DTTI0S1 *((volatile unsigned int*)(0x4266C0C4UL)) +#define bFM3_GPIO_EPFR01_FRCK0S0 *((volatile unsigned int*)(0x4266C0C8UL)) +#define bFM3_GPIO_EPFR01_FRCK0S1 *((volatile unsigned int*)(0x4266C0CCUL)) +#define bFM3_GPIO_EPFR01_IC00S0 *((volatile unsigned int*)(0x4266C0D0UL)) +#define bFM3_GPIO_EPFR01_IC00S1 *((volatile unsigned int*)(0x4266C0D4UL)) +#define bFM3_GPIO_EPFR01_IC00S2 *((volatile unsigned int*)(0x4266C0D8UL)) +#define bFM3_GPIO_EPFR01_IC01S0 *((volatile unsigned int*)(0x4266C0DCUL)) +#define bFM3_GPIO_EPFR01_IC01S1 *((volatile unsigned int*)(0x4266C0E0UL)) +#define bFM3_GPIO_EPFR01_IC01S2 *((volatile unsigned int*)(0x4266C0E4UL)) +#define bFM3_GPIO_EPFR01_IC02S0 *((volatile unsigned int*)(0x4266C0E8UL)) +#define bFM3_GPIO_EPFR01_IC02S1 *((volatile unsigned int*)(0x4266C0ECUL)) +#define bFM3_GPIO_EPFR01_IC02S2 *((volatile unsigned int*)(0x4266C0F0UL)) +#define bFM3_GPIO_EPFR01_IC03S0 *((volatile unsigned int*)(0x4266C0F4UL)) +#define bFM3_GPIO_EPFR01_IC03S1 *((volatile unsigned int*)(0x4266C0F8UL)) +#define bFM3_GPIO_EPFR01_IC03S2 *((volatile unsigned int*)(0x4266C0FCUL)) +#define bFM3_GPIO_EPFR02_RTO10E0 *((volatile unsigned int*)(0x4266C100UL)) +#define bFM3_GPIO_EPFR02_RTO10E1 *((volatile unsigned int*)(0x4266C104UL)) +#define bFM3_GPIO_EPFR02_RTO11E0 *((volatile unsigned int*)(0x4266C108UL)) +#define bFM3_GPIO_EPFR02_RTO11E1 *((volatile unsigned int*)(0x4266C10CUL)) +#define bFM3_GPIO_EPFR02_RTO12E0 *((volatile unsigned int*)(0x4266C110UL)) +#define bFM3_GPIO_EPFR02_RTO12E1 *((volatile unsigned int*)(0x4266C114UL)) +#define bFM3_GPIO_EPFR02_RTO13E0 *((volatile unsigned int*)(0x4266C118UL)) +#define bFM3_GPIO_EPFR02_RTO13E1 *((volatile unsigned int*)(0x4266C11CUL)) +#define bFM3_GPIO_EPFR02_RTO14E0 *((volatile unsigned int*)(0x4266C120UL)) +#define bFM3_GPIO_EPFR02_RTO14E1 *((volatile unsigned int*)(0x4266C124UL)) +#define bFM3_GPIO_EPFR02_RTO15E0 *((volatile unsigned int*)(0x4266C128UL)) +#define bFM3_GPIO_EPFR02_RTO15E1 *((volatile unsigned int*)(0x4266C12CUL)) +#define bFM3_GPIO_EPFR02_DTTI1C *((volatile unsigned int*)(0x4266C130UL)) +#define bFM3_GPIO_EPFR02_DTTI1S0 *((volatile unsigned int*)(0x4266C140UL)) +#define bFM3_GPIO_EPFR02_DTTI1S1 *((volatile unsigned int*)(0x4266C144UL)) +#define bFM3_GPIO_EPFR02_FRCK1S0 *((volatile unsigned int*)(0x4266C148UL)) +#define bFM3_GPIO_EPFR02_FRCK1S1 *((volatile unsigned int*)(0x4266C14CUL)) +#define bFM3_GPIO_EPFR02_IC10S0 *((volatile unsigned int*)(0x4266C150UL)) +#define bFM3_GPIO_EPFR02_IC10S1 *((volatile unsigned int*)(0x4266C154UL)) +#define bFM3_GPIO_EPFR02_IC10S2 *((volatile unsigned int*)(0x4266C158UL)) +#define bFM3_GPIO_EPFR02_IC11S0 *((volatile unsigned int*)(0x4266C15CUL)) +#define bFM3_GPIO_EPFR02_IC11S1 *((volatile unsigned int*)(0x4266C160UL)) +#define bFM3_GPIO_EPFR02_IC11S2 *((volatile unsigned int*)(0x4266C164UL)) +#define bFM3_GPIO_EPFR02_IC12S0 *((volatile unsigned int*)(0x4266C168UL)) +#define bFM3_GPIO_EPFR02_IC12S1 *((volatile unsigned int*)(0x4266C16CUL)) +#define bFM3_GPIO_EPFR02_IC12S2 *((volatile unsigned int*)(0x4266C170UL)) +#define bFM3_GPIO_EPFR02_IC13S0 *((volatile unsigned int*)(0x4266C174UL)) +#define bFM3_GPIO_EPFR02_IC13S1 *((volatile unsigned int*)(0x4266C178UL)) +#define bFM3_GPIO_EPFR02_IC13S2 *((volatile unsigned int*)(0x4266C17CUL)) +#define bFM3_GPIO_EPFR04_TIOA0E0 *((volatile unsigned int*)(0x4266C208UL)) +#define bFM3_GPIO_EPFR04_TIOA0E1 *((volatile unsigned int*)(0x4266C20CUL)) +#define bFM3_GPIO_EPFR04_TIOB0S0 *((volatile unsigned int*)(0x4266C210UL)) +#define bFM3_GPIO_EPFR04_TIOB0S1 *((volatile unsigned int*)(0x4266C214UL)) +#define bFM3_GPIO_EPFR04_TIOA1S0 *((volatile unsigned int*)(0x4266C220UL)) +#define bFM3_GPIO_EPFR04_TIOA1S1 *((volatile unsigned int*)(0x4266C224UL)) +#define bFM3_GPIO_EPFR04_TIOA1E0 *((volatile unsigned int*)(0x4266C228UL)) +#define bFM3_GPIO_EPFR04_TIOA1E1 *((volatile unsigned int*)(0x4266C22CUL)) +#define bFM3_GPIO_EPFR04_TIOB1S0 *((volatile unsigned int*)(0x4266C230UL)) +#define bFM3_GPIO_EPFR04_TIOB1S1 *((volatile unsigned int*)(0x4266C234UL)) +#define bFM3_GPIO_EPFR04_TIOA2E0 *((volatile unsigned int*)(0x4266C248UL)) +#define bFM3_GPIO_EPFR04_TIOA2E1 *((volatile unsigned int*)(0x4266C24CUL)) +#define bFM3_GPIO_EPFR04_TIOB2S0 *((volatile unsigned int*)(0x4266C250UL)) +#define bFM3_GPIO_EPFR04_TIOB2S1 *((volatile unsigned int*)(0x4266C254UL)) +#define bFM3_GPIO_EPFR04_TIOA3S0 *((volatile unsigned int*)(0x4266C260UL)) +#define bFM3_GPIO_EPFR04_TIOA3S1 *((volatile unsigned int*)(0x4266C264UL)) +#define bFM3_GPIO_EPFR04_TIOA3E0 *((volatile unsigned int*)(0x4266C268UL)) +#define bFM3_GPIO_EPFR04_TIOA3E1 *((volatile unsigned int*)(0x4266C26CUL)) +#define bFM3_GPIO_EPFR04_TIOB3S0 *((volatile unsigned int*)(0x4266C270UL)) +#define bFM3_GPIO_EPFR04_TIOB3S1 *((volatile unsigned int*)(0x4266C274UL)) +#define bFM3_GPIO_EPFR05_TIOA4E0 *((volatile unsigned int*)(0x4266C288UL)) +#define bFM3_GPIO_EPFR05_TIOA4E1 *((volatile unsigned int*)(0x4266C28CUL)) +#define bFM3_GPIO_EPFR05_TIOB4S0 *((volatile unsigned int*)(0x4266C290UL)) +#define bFM3_GPIO_EPFR05_TIOB4S1 *((volatile unsigned int*)(0x4266C294UL)) +#define bFM3_GPIO_EPFR05_TIOA5S0 *((volatile unsigned int*)(0x4266C2A0UL)) +#define bFM3_GPIO_EPFR05_TIOA5S1 *((volatile unsigned int*)(0x4266C2A4UL)) +#define bFM3_GPIO_EPFR05_TIOA5E0 *((volatile unsigned int*)(0x4266C2A8UL)) +#define bFM3_GPIO_EPFR05_TIOA5E1 *((volatile unsigned int*)(0x4266C2ACUL)) +#define bFM3_GPIO_EPFR05_TIOB5S0 *((volatile unsigned int*)(0x4266C2B0UL)) +#define bFM3_GPIO_EPFR05_TIOB5S1 *((volatile unsigned int*)(0x4266C2B4UL)) +#define bFM3_GPIO_EPFR05_TIOA6E0 *((volatile unsigned int*)(0x4266C2C8UL)) +#define bFM3_GPIO_EPFR05_TIOA6E1 *((volatile unsigned int*)(0x4266C2CCUL)) +#define bFM3_GPIO_EPFR05_TIOB6S0 *((volatile unsigned int*)(0x4266C2D0UL)) +#define bFM3_GPIO_EPFR05_TIOB6S1 *((volatile unsigned int*)(0x4266C2D4UL)) +#define bFM3_GPIO_EPFR05_TIOA7S0 *((volatile unsigned int*)(0x4266C2E0UL)) +#define bFM3_GPIO_EPFR05_TIOA7S1 *((volatile unsigned int*)(0x4266C2E4UL)) +#define bFM3_GPIO_EPFR05_TIOA7E0 *((volatile unsigned int*)(0x4266C2E8UL)) +#define bFM3_GPIO_EPFR05_TIOA7E1 *((volatile unsigned int*)(0x4266C2ECUL)) +#define bFM3_GPIO_EPFR05_TIOB7S0 *((volatile unsigned int*)(0x4266C2F0UL)) +#define bFM3_GPIO_EPFR05_TIOB7S1 *((volatile unsigned int*)(0x4266C2F4UL)) +#define bFM3_GPIO_EPFR06_EINT00S0 *((volatile unsigned int*)(0x4266C300UL)) +#define bFM3_GPIO_EPFR06_EINT00S1 *((volatile unsigned int*)(0x4266C304UL)) +#define bFM3_GPIO_EPFR06_EINT01S0 *((volatile unsigned int*)(0x4266C308UL)) +#define bFM3_GPIO_EPFR06_EINT01S1 *((volatile unsigned int*)(0x4266C30CUL)) +#define bFM3_GPIO_EPFR06_EINT02S0 *((volatile unsigned int*)(0x4266C310UL)) +#define bFM3_GPIO_EPFR06_EINT02S1 *((volatile unsigned int*)(0x4266C314UL)) +#define bFM3_GPIO_EPFR06_EINT03S0 *((volatile unsigned int*)(0x4266C318UL)) +#define bFM3_GPIO_EPFR06_EINT03S1 *((volatile unsigned int*)(0x4266C31CUL)) +#define bFM3_GPIO_EPFR06_EINT04S0 *((volatile unsigned int*)(0x4266C320UL)) +#define bFM3_GPIO_EPFR06_EINT04S1 *((volatile unsigned int*)(0x4266C324UL)) +#define bFM3_GPIO_EPFR06_EINT05S0 *((volatile unsigned int*)(0x4266C328UL)) +#define bFM3_GPIO_EPFR06_EINT05S1 *((volatile unsigned int*)(0x4266C32CUL)) +#define bFM3_GPIO_EPFR06_EINT06S0 *((volatile unsigned int*)(0x4266C330UL)) +#define bFM3_GPIO_EPFR06_EINT06S1 *((volatile unsigned int*)(0x4266C334UL)) +#define bFM3_GPIO_EPFR06_EINT07S0 *((volatile unsigned int*)(0x4266C338UL)) +#define bFM3_GPIO_EPFR06_EINT07S1 *((volatile unsigned int*)(0x4266C33CUL)) +#define bFM3_GPIO_EPFR06_EINT08S0 *((volatile unsigned int*)(0x4266C340UL)) +#define bFM3_GPIO_EPFR06_EINT08S1 *((volatile unsigned int*)(0x4266C344UL)) +#define bFM3_GPIO_EPFR06_EINT09S0 *((volatile unsigned int*)(0x4266C348UL)) +#define bFM3_GPIO_EPFR06_EINT09S1 *((volatile unsigned int*)(0x4266C34CUL)) +#define bFM3_GPIO_EPFR06_EINT10S0 *((volatile unsigned int*)(0x4266C350UL)) +#define bFM3_GPIO_EPFR06_EINT10S1 *((volatile unsigned int*)(0x4266C354UL)) +#define bFM3_GPIO_EPFR06_EINT11S0 *((volatile unsigned int*)(0x4266C358UL)) +#define bFM3_GPIO_EPFR06_EINT11S1 *((volatile unsigned int*)(0x4266C35CUL)) +#define bFM3_GPIO_EPFR06_EINT12S0 *((volatile unsigned int*)(0x4266C360UL)) +#define bFM3_GPIO_EPFR06_EINT12S1 *((volatile unsigned int*)(0x4266C364UL)) +#define bFM3_GPIO_EPFR06_EINT13S0 *((volatile unsigned int*)(0x4266C368UL)) +#define bFM3_GPIO_EPFR06_EINT13S1 *((volatile unsigned int*)(0x4266C36CUL)) +#define bFM3_GPIO_EPFR06_EINT14S0 *((volatile unsigned int*)(0x4266C370UL)) +#define bFM3_GPIO_EPFR06_EINT14S1 *((volatile unsigned int*)(0x4266C374UL)) +#define bFM3_GPIO_EPFR06_EINT15S0 *((volatile unsigned int*)(0x4266C378UL)) +#define bFM3_GPIO_EPFR06_EINT15S1 *((volatile unsigned int*)(0x4266C37CUL)) +#define bFM3_GPIO_EPFR07_SIN0S0 *((volatile unsigned int*)(0x4266C390UL)) +#define bFM3_GPIO_EPFR07_SIN0S1 *((volatile unsigned int*)(0x4266C394UL)) +#define bFM3_GPIO_EPFR07_SOT0B0 *((volatile unsigned int*)(0x4266C398UL)) +#define bFM3_GPIO_EPFR07_SOT0B1 *((volatile unsigned int*)(0x4266C39CUL)) +#define bFM3_GPIO_EPFR07_SCK0B0 *((volatile unsigned int*)(0x4266C3A0UL)) +#define bFM3_GPIO_EPFR07_SCK0B1 *((volatile unsigned int*)(0x4266C3A4UL)) +#define bFM3_GPIO_EPFR07_SIN1S0 *((volatile unsigned int*)(0x4266C3A8UL)) +#define bFM3_GPIO_EPFR07_SIN1S1 *((volatile unsigned int*)(0x4266C3ACUL)) +#define bFM3_GPIO_EPFR07_SOT1B0 *((volatile unsigned int*)(0x4266C3B0UL)) +#define bFM3_GPIO_EPFR07_SOT1B1 *((volatile unsigned int*)(0x4266C3B4UL)) +#define bFM3_GPIO_EPFR07_SCK1B0 *((volatile unsigned int*)(0x4266C3B8UL)) +#define bFM3_GPIO_EPFR07_SCK1B1 *((volatile unsigned int*)(0x4266C3BCUL)) +#define bFM3_GPIO_EPFR07_SIN2S0 *((volatile unsigned int*)(0x4266C3C0UL)) +#define bFM3_GPIO_EPFR07_SIN2S1 *((volatile unsigned int*)(0x4266C3C4UL)) +#define bFM3_GPIO_EPFR07_SOT2B0 *((volatile unsigned int*)(0x4266C3C8UL)) +#define bFM3_GPIO_EPFR07_SOT2B1 *((volatile unsigned int*)(0x4266C3CCUL)) +#define bFM3_GPIO_EPFR07_SCK2B0 *((volatile unsigned int*)(0x4266C3D0UL)) +#define bFM3_GPIO_EPFR07_SCK2B1 *((volatile unsigned int*)(0x4266C3D4UL)) +#define bFM3_GPIO_EPFR07_SIN3S0 *((volatile unsigned int*)(0x4266C3D8UL)) +#define bFM3_GPIO_EPFR07_SIN3S1 *((volatile unsigned int*)(0x4266C3DCUL)) +#define bFM3_GPIO_EPFR07_SOT3B0 *((volatile unsigned int*)(0x4266C3E0UL)) +#define bFM3_GPIO_EPFR07_SOT3B1 *((volatile unsigned int*)(0x4266C3E4UL)) +#define bFM3_GPIO_EPFR07_SCK3B0 *((volatile unsigned int*)(0x4266C3E8UL)) +#define bFM3_GPIO_EPFR07_SCK3B1 *((volatile unsigned int*)(0x4266C3ECUL)) +#define bFM3_GPIO_EPFR08_RTS4E0 *((volatile unsigned int*)(0x4266C400UL)) +#define bFM3_GPIO_EPFR08_RTS4E1 *((volatile unsigned int*)(0x4266C404UL)) +#define bFM3_GPIO_EPFR08_CTS4S0 *((volatile unsigned int*)(0x4266C408UL)) +#define bFM3_GPIO_EPFR08_CTS4S1 *((volatile unsigned int*)(0x4266C40CUL)) +#define bFM3_GPIO_EPFR08_SIN4S0 *((volatile unsigned int*)(0x4266C410UL)) +#define bFM3_GPIO_EPFR08_SIN4S1 *((volatile unsigned int*)(0x4266C414UL)) +#define bFM3_GPIO_EPFR08_SOT4B0 *((volatile unsigned int*)(0x4266C418UL)) +#define bFM3_GPIO_EPFR08_SOT4B1 *((volatile unsigned int*)(0x4266C41CUL)) +#define bFM3_GPIO_EPFR08_SCK4B0 *((volatile unsigned int*)(0x4266C420UL)) +#define bFM3_GPIO_EPFR08_SCK4B1 *((volatile unsigned int*)(0x4266C424UL)) +#define bFM3_GPIO_EPFR08_SIN5S0 *((volatile unsigned int*)(0x4266C428UL)) +#define bFM3_GPIO_EPFR08_SIN5S1 *((volatile unsigned int*)(0x4266C42CUL)) +#define bFM3_GPIO_EPFR08_SOT5B0 *((volatile unsigned int*)(0x4266C430UL)) +#define bFM3_GPIO_EPFR08_SOT5B1 *((volatile unsigned int*)(0x4266C434UL)) +#define bFM3_GPIO_EPFR08_SCK5B0 *((volatile unsigned int*)(0x4266C438UL)) +#define bFM3_GPIO_EPFR08_SCK5B1 *((volatile unsigned int*)(0x4266C43CUL)) +#define bFM3_GPIO_EPFR08_SIN6S0 *((volatile unsigned int*)(0x4266C440UL)) +#define bFM3_GPIO_EPFR08_SIN6S1 *((volatile unsigned int*)(0x4266C444UL)) +#define bFM3_GPIO_EPFR08_SOT6B0 *((volatile unsigned int*)(0x4266C448UL)) +#define bFM3_GPIO_EPFR08_SOT6B1 *((volatile unsigned int*)(0x4266C44CUL)) +#define bFM3_GPIO_EPFR08_SCK6B0 *((volatile unsigned int*)(0x4266C450UL)) +#define bFM3_GPIO_EPFR08_SCK6B1 *((volatile unsigned int*)(0x4266C454UL)) +#define bFM3_GPIO_EPFR08_SIN7S0 *((volatile unsigned int*)(0x4266C458UL)) +#define bFM3_GPIO_EPFR08_SIN7S1 *((volatile unsigned int*)(0x4266C45CUL)) +#define bFM3_GPIO_EPFR08_SOT7B0 *((volatile unsigned int*)(0x4266C460UL)) +#define bFM3_GPIO_EPFR08_SOT7B1 *((volatile unsigned int*)(0x4266C464UL)) +#define bFM3_GPIO_EPFR08_SCK7B0 *((volatile unsigned int*)(0x4266C468UL)) +#define bFM3_GPIO_EPFR08_SCK7B1 *((volatile unsigned int*)(0x4266C46CUL)) +#define bFM3_GPIO_EPFR09_QAIN0S0 *((volatile unsigned int*)(0x4266C480UL)) +#define bFM3_GPIO_EPFR09_QAIN0S1 *((volatile unsigned int*)(0x4266C484UL)) +#define bFM3_GPIO_EPFR09_QBIN0S0 *((volatile unsigned int*)(0x4266C488UL)) +#define bFM3_GPIO_EPFR09_QBIN0S1 *((volatile unsigned int*)(0x4266C48CUL)) +#define bFM3_GPIO_EPFR09_QZIN0S0 *((volatile unsigned int*)(0x4266C490UL)) +#define bFM3_GPIO_EPFR09_QZIN0S1 *((volatile unsigned int*)(0x4266C494UL)) +#define bFM3_GPIO_EPFR09_QAIN1S0 *((volatile unsigned int*)(0x4266C498UL)) +#define bFM3_GPIO_EPFR09_QAIN1S1 *((volatile unsigned int*)(0x4266C49CUL)) +#define bFM3_GPIO_EPFR09_QBIN1S0 *((volatile unsigned int*)(0x4266C4A0UL)) +#define bFM3_GPIO_EPFR09_QBIN1S1 *((volatile unsigned int*)(0x4266C4A4UL)) +#define bFM3_GPIO_EPFR09_QZIN1S0 *((volatile unsigned int*)(0x4266C4A8UL)) +#define bFM3_GPIO_EPFR09_QZIN1S1 *((volatile unsigned int*)(0x4266C4ACUL)) +#define bFM3_GPIO_EPFR09_ADTRG0S0 *((volatile unsigned int*)(0x4266C4B0UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S1 *((volatile unsigned int*)(0x4266C4B4UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S2 *((volatile unsigned int*)(0x4266C4B8UL)) +#define bFM3_GPIO_EPFR09_ADTRG0S3 *((volatile unsigned int*)(0x4266C4BCUL)) +#define bFM3_GPIO_EPFR09_ADTRG1S0 *((volatile unsigned int*)(0x4266C4C0UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S1 *((volatile unsigned int*)(0x4266C4C4UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S2 *((volatile unsigned int*)(0x4266C4C8UL)) +#define bFM3_GPIO_EPFR09_ADTRG1S3 *((volatile unsigned int*)(0x4266C4CCUL)) +#define bFM3_GPIO_EPFR09_ADTRG2S0 *((volatile unsigned int*)(0x4266C4D0UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S1 *((volatile unsigned int*)(0x4266C4D4UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S2 *((volatile unsigned int*)(0x4266C4D8UL)) +#define bFM3_GPIO_EPFR09_ADTRG2S3 *((volatile unsigned int*)(0x4266C4DCUL)) +#define bFM3_GPIO_EPFR09_CRX0S0 *((volatile unsigned int*)(0x4266C4E0UL)) +#define bFM3_GPIO_EPFR09_CRX0S1 *((volatile unsigned int*)(0x4266C4E4UL)) +#define bFM3_GPIO_EPFR09_CTX0E0 *((volatile unsigned int*)(0x4266C4E8UL)) +#define bFM3_GPIO_EPFR09_CTX0E1 *((volatile unsigned int*)(0x4266C4ECUL)) +#define bFM3_GPIO_EPFR09_CRX1S0 *((volatile unsigned int*)(0x4266C4F0UL)) +#define bFM3_GPIO_EPFR09_CRX1S1 *((volatile unsigned int*)(0x4266C4F4UL)) +#define bFM3_GPIO_EPFR09_CTX1E0 *((volatile unsigned int*)(0x4266C4F8UL)) +#define bFM3_GPIO_EPFR09_CTX1E1 *((volatile unsigned int*)(0x4266C4FCUL)) +#define bFM3_GPIO_EPFR10_UEDEFB *((volatile unsigned int*)(0x4266C500UL)) +#define bFM3_GPIO_EPFR10_UEDTHB *((volatile unsigned int*)(0x4266C504UL)) +#define bFM3_GPIO_EPFR10_TESTB *((volatile unsigned int*)(0x4266C508UL)) +#define bFM3_GPIO_EPFR10_UEWEXE *((volatile unsigned int*)(0x4266C50CUL)) +#define bFM3_GPIO_EPFR10_UEDQME *((volatile unsigned int*)(0x4266C510UL)) +#define bFM3_GPIO_EPFR10_UEOEXE *((volatile unsigned int*)(0x4266C514UL)) +#define bFM3_GPIO_EPFR10_UEFLSE *((volatile unsigned int*)(0x4266C518UL)) +#define bFM3_GPIO_EPFR10_UECS1E *((volatile unsigned int*)(0x4266C51CUL)) +#define bFM3_GPIO_EPFR10_UECS2E *((volatile unsigned int*)(0x4266C520UL)) +#define bFM3_GPIO_EPFR10_UECS3E *((volatile unsigned int*)(0x4266C524UL)) +#define bFM3_GPIO_EPFR10_UECS4E *((volatile unsigned int*)(0x4266C528UL)) +#define bFM3_GPIO_EPFR10_UECS5E *((volatile unsigned int*)(0x4266C52CUL)) +#define bFM3_GPIO_EPFR10_UECS6E *((volatile unsigned int*)(0x4266C530UL)) +#define bFM3_GPIO_EPFR10_UECS7E *((volatile unsigned int*)(0x4266C534UL)) +#define bFM3_GPIO_EPFR10_UEAOOE *((volatile unsigned int*)(0x4266C538UL)) +#define bFM3_GPIO_EPFR10_UEA08E *((volatile unsigned int*)(0x4266C53CUL)) +#define bFM3_GPIO_EPFR10_UEA09E *((volatile unsigned int*)(0x4266C540UL)) +#define bFM3_GPIO_EPFR10_UEA10E *((volatile unsigned int*)(0x4266C544UL)) +#define bFM3_GPIO_EPFR10_UEA11E *((volatile unsigned int*)(0x4266C548UL)) +#define bFM3_GPIO_EPFR10_UEA12E *((volatile unsigned int*)(0x4266C54CUL)) +#define bFM3_GPIO_EPFR10_UEA13E *((volatile unsigned int*)(0x4266C550UL)) +#define bFM3_GPIO_EPFR10_UEA14E *((volatile unsigned int*)(0x4266C554UL)) +#define bFM3_GPIO_EPFR10_UEA15E *((volatile unsigned int*)(0x4266C558UL)) +#define bFM3_GPIO_EPFR10_UEA16E *((volatile unsigned int*)(0x4266C55CUL)) +#define bFM3_GPIO_EPFR10_UEA17E *((volatile unsigned int*)(0x4266C560UL)) +#define bFM3_GPIO_EPFR10_UEA18E *((volatile unsigned int*)(0x4266C564UL)) +#define bFM3_GPIO_EPFR10_UEA19E *((volatile unsigned int*)(0x4266C568UL)) +#define bFM3_GPIO_EPFR10_UEA20E *((volatile unsigned int*)(0x4266C56CUL)) +#define bFM3_GPIO_EPFR10_UEA21E *((volatile unsigned int*)(0x4266C570UL)) +#define bFM3_GPIO_EPFR10_UEA22E *((volatile unsigned int*)(0x4266C574UL)) +#define bFM3_GPIO_EPFR10_UEA23E *((volatile unsigned int*)(0x4266C578UL)) +#define bFM3_GPIO_EPFR10_UEA24E *((volatile unsigned int*)(0x4266C57CUL)) + +/* Low voltage detection registers */ +#define bFM3_LVD_LVD_CTL_SVHI0 *((volatile unsigned int*)(0x426A0008UL)) +#define bFM3_LVD_LVD_CTL_SVHI1 *((volatile unsigned int*)(0x426A000CUL)) +#define bFM3_LVD_LVD_CTL_SVHI2 *((volatile unsigned int*)(0x426A0010UL)) +#define bFM3_LVD_LVD_CTL_SVHI3 *((volatile unsigned int*)(0x426A0014UL)) +#define bFM3_LVD_LVD_CTL_LVDIE *((volatile unsigned int*)(0x426A001CUL)) +#define bFM3_LVD_LVD_STR_LVDIR *((volatile unsigned int*)(0x426A009CUL)) +#define bFM3_LVD_LVD_CLR_LVDCL *((volatile unsigned int*)(0x426A011CUL)) +#define bFM3_LVD_LVD_STR2_LVDIRDY *((volatile unsigned int*)(0x426A021CUL)) + +/* USB clock registers */ +#define bFM3_USBCLK_UCCR_UCEN *((volatile unsigned int*)(0x426C0000UL)) +#define bFM3_USBCLK_UCCR_UCSEL *((volatile unsigned int*)(0x426C0004UL)) +#define bFM3_USBCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) +#define bFM3_USBCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) +#define bFM3_USBCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) +#define bFM3_USBCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) +#define bFM3_USBCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) +#define bFM3_USBCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) +#define bFM3_USBCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) +#define bFM3_USBCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) +#define bFM3_USBCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) +#define bFM3_USBCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) +#define bFM3_USBCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) +#define bFM3_USBCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) +#define bFM3_USBCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) +#define bFM3_USBCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) +#define bFM3_USBCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) +#define bFM3_USBCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) +#define bFM3_USBCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) +#define bFM3_USBCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) +#define bFM3_USBCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) +#define bFM3_USBCLK_USBEN_USBEN *((volatile unsigned int*)(0x426C0600UL)) + +/* CAN prescaler register */ +#define bFM3_CANPRES_CANPRE_CANPRE0 *((volatile unsigned int*)(0x426E0000UL)) +#define bFM3_CANPRES_CANPRE_CANPRE1 *((volatile unsigned int*)(0x426E0004UL)) +#define bFM3_CANPRES_CANPRE_CANPRE2 *((volatile unsigned int*)(0x426E0008UL)) +#define bFM3_CANPRES_CANPRE_CANPRE3 *((volatile unsigned int*)(0x426E000CUL)) + +/* UART asynchronous channel 0 registers */ +#define bFM3_MFS0_UART_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_UART_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_UART_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_UART_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_UART_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_UART_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_UART_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_UART_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_UART_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_UART_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_UART_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_UART_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_UART_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_UART_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_UART_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_UART_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_UART_ESCR_P *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_UART_ESCR_PEN *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_UART_ESCR_INV *((volatile unsigned int*)(0x42700094UL)) +#define bFM3_MFS0_UART_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_UART_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_UART_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_UART_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_UART_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_UART_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_UART_SSR_PE *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_UART_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_UART_RDR_AD *((volatile unsigned int*)(0x42700120UL)) +#define bFM3_MFS0_UART_TDR_AD *((volatile unsigned int*)(0x42700120UL)) +#define bFM3_MFS0_UART_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) +#define bFM3_MFS0_UART_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) + +/* UART synchronous channel 0 registers */ +#define bFM3_MFS0_CSIO_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42700004UL)) +#define bFM3_MFS0_CSIO_SMR_BDS *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_CSIO_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_CSIO_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_CSIO_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_CSIO_SCR_SPI *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_CSIO_SCR_MS *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_CSIO_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_CSIO_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_CSIO_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) + +/* UART LIN channel 0 registers */ +#define bFM3_MFS0_LIN_SMR_SOE *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_LIN_SMR_SBL *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_LIN_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_LIN_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_LIN_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_LIN_SCR_TXE *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_LIN_SCR_RXE *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_LIN_SCR_TBIE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_LIN_SCR_TIE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_LIN_SCR_RIE *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_LIN_SCR_LBR *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_LIN_SCR_MS *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_LIN_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_LIN_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_LIN_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_LIN_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_LIN_SSR_FRE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_LIN_SSR_LBD *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_LIN_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_LIN_BGR_EXT *((volatile unsigned int*)(0x427001BCUL)) +#define bFM3_MFS0_LIN_BGR1_EXT *((volatile unsigned int*)(0x427001BCUL)) + +/* I2C channel 0 registers */ +#define bFM3_MFS0_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42700000UL)) +#define bFM3_MFS0_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42700004UL)) +#define bFM3_MFS0_I2C_SMR_TIE *((volatile unsigned int*)(0x42700008UL)) +#define bFM3_MFS0_I2C_SMR_RIE *((volatile unsigned int*)(0x4270000CUL)) +#define bFM3_MFS0_I2C_SMR_WUCR *((volatile unsigned int*)(0x42700010UL)) +#define bFM3_MFS0_I2C_SMR_MD0 *((volatile unsigned int*)(0x42700014UL)) +#define bFM3_MFS0_I2C_SMR_MD1 *((volatile unsigned int*)(0x42700018UL)) +#define bFM3_MFS0_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270001CUL)) +#define bFM3_MFS0_I2C_IBCR_INT *((volatile unsigned int*)(0x42700020UL)) +#define bFM3_MFS0_I2C_IBCR_BER *((volatile unsigned int*)(0x42700024UL)) +#define bFM3_MFS0_I2C_IBCR_INTE *((volatile unsigned int*)(0x42700028UL)) +#define bFM3_MFS0_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270002CUL)) +#define bFM3_MFS0_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42700030UL)) +#define bFM3_MFS0_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42700034UL)) +#define bFM3_MFS0_I2C_IBCR_ACT *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_I2C_IBCR_SCC *((volatile unsigned int*)(0x42700038UL)) +#define bFM3_MFS0_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270003CUL)) +#define bFM3_MFS0_I2C_IBSR_BB *((volatile unsigned int*)(0x42700080UL)) +#define bFM3_MFS0_I2C_IBSR_SPC *((volatile unsigned int*)(0x42700084UL)) +#define bFM3_MFS0_I2C_IBSR_RSC *((volatile unsigned int*)(0x42700088UL)) +#define bFM3_MFS0_I2C_IBSR_AL *((volatile unsigned int*)(0x4270008CUL)) +#define bFM3_MFS0_I2C_IBSR_TRX *((volatile unsigned int*)(0x42700090UL)) +#define bFM3_MFS0_I2C_IBSR_RSA *((volatile unsigned int*)(0x42700094UL)) +#define bFM3_MFS0_I2C_IBSR_RACK *((volatile unsigned int*)(0x42700098UL)) +#define bFM3_MFS0_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270009CUL)) +#define bFM3_MFS0_I2C_SSR_TBI *((volatile unsigned int*)(0x427000A0UL)) +#define bFM3_MFS0_I2C_SSR_TDRE *((volatile unsigned int*)(0x427000A4UL)) +#define bFM3_MFS0_I2C_SSR_RDRF *((volatile unsigned int*)(0x427000A8UL)) +#define bFM3_MFS0_I2C_SSR_ORE *((volatile unsigned int*)(0x427000ACUL)) +#define bFM3_MFS0_I2C_SSR_TBIE *((volatile unsigned int*)(0x427000B0UL)) +#define bFM3_MFS0_I2C_SSR_DMA *((volatile unsigned int*)(0x427000B4UL)) +#define bFM3_MFS0_I2C_SSR_TSET *((volatile unsigned int*)(0x427000B8UL)) +#define bFM3_MFS0_I2C_SSR_REC *((volatile unsigned int*)(0x427000BCUL)) +#define bFM3_MFS0_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42700200UL)) +#define bFM3_MFS0_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42700204UL)) +#define bFM3_MFS0_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42700208UL)) +#define bFM3_MFS0_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270020CUL)) +#define bFM3_MFS0_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42700210UL)) +#define bFM3_MFS0_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42700214UL)) +#define bFM3_MFS0_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42700218UL)) +#define bFM3_MFS0_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270021CUL)) +#define bFM3_MFS0_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42700220UL)) +#define bFM3_MFS0_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42700224UL)) +#define bFM3_MFS0_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42700228UL)) +#define bFM3_MFS0_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270022CUL)) +#define bFM3_MFS0_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42700230UL)) +#define bFM3_MFS0_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42700234UL)) +#define bFM3_MFS0_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42700238UL)) +#define bFM3_MFS0_I2C_ISMK_EN *((volatile unsigned int*)(0x4270023CUL)) + +/* UART asynchronous channel 1 registers */ +#define bFM3_MFS1_UART_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_UART_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_UART_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_UART_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_UART_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_UART_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_UART_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_UART_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_UART_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_UART_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_UART_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_UART_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_UART_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_UART_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_UART_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_UART_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_UART_ESCR_P *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_UART_ESCR_PEN *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_UART_ESCR_INV *((volatile unsigned int*)(0x42702094UL)) +#define bFM3_MFS1_UART_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_UART_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_UART_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_UART_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_UART_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_UART_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_UART_SSR_PE *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_UART_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_UART_RDR_AD *((volatile unsigned int*)(0x42702120UL)) +#define bFM3_MFS1_UART_TDR_AD *((volatile unsigned int*)(0x42702120UL)) +#define bFM3_MFS1_UART_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) +#define bFM3_MFS1_UART_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) + +/* UART synchronous channel 1 registers */ +#define bFM3_MFS1_CSIO_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42702004UL)) +#define bFM3_MFS1_CSIO_SMR_BDS *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_CSIO_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_CSIO_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_CSIO_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_CSIO_SCR_SPI *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_CSIO_SCR_MS *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_CSIO_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_CSIO_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_CSIO_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) + +/* UART LIN channel 1 registers */ +#define bFM3_MFS1_LIN_SMR_SOE *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_LIN_SMR_SBL *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_LIN_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_LIN_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_LIN_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_LIN_SCR_TXE *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_LIN_SCR_RXE *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_LIN_SCR_TBIE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_LIN_SCR_TIE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_LIN_SCR_RIE *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_LIN_SCR_LBR *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_LIN_SCR_MS *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_LIN_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_LIN_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_LIN_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_LIN_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_LIN_SSR_FRE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_LIN_SSR_LBD *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_LIN_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_LIN_BGR_EXT *((volatile unsigned int*)(0x427021BCUL)) +#define bFM3_MFS1_LIN_BGR1_EXT *((volatile unsigned int*)(0x427021BCUL)) + +/* I2C channel 1 registers */ +#define bFM3_MFS1_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42702000UL)) +#define bFM3_MFS1_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42702004UL)) +#define bFM3_MFS1_I2C_SMR_TIE *((volatile unsigned int*)(0x42702008UL)) +#define bFM3_MFS1_I2C_SMR_RIE *((volatile unsigned int*)(0x4270200CUL)) +#define bFM3_MFS1_I2C_SMR_WUCR *((volatile unsigned int*)(0x42702010UL)) +#define bFM3_MFS1_I2C_SMR_MD0 *((volatile unsigned int*)(0x42702014UL)) +#define bFM3_MFS1_I2C_SMR_MD1 *((volatile unsigned int*)(0x42702018UL)) +#define bFM3_MFS1_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270201CUL)) +#define bFM3_MFS1_I2C_IBCR_INT *((volatile unsigned int*)(0x42702020UL)) +#define bFM3_MFS1_I2C_IBCR_BER *((volatile unsigned int*)(0x42702024UL)) +#define bFM3_MFS1_I2C_IBCR_INTE *((volatile unsigned int*)(0x42702028UL)) +#define bFM3_MFS1_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270202CUL)) +#define bFM3_MFS1_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42702030UL)) +#define bFM3_MFS1_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42702034UL)) +#define bFM3_MFS1_I2C_IBCR_ACT *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_I2C_IBCR_SCC *((volatile unsigned int*)(0x42702038UL)) +#define bFM3_MFS1_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270203CUL)) +#define bFM3_MFS1_I2C_IBSR_BB *((volatile unsigned int*)(0x42702080UL)) +#define bFM3_MFS1_I2C_IBSR_SPC *((volatile unsigned int*)(0x42702084UL)) +#define bFM3_MFS1_I2C_IBSR_RSC *((volatile unsigned int*)(0x42702088UL)) +#define bFM3_MFS1_I2C_IBSR_AL *((volatile unsigned int*)(0x4270208CUL)) +#define bFM3_MFS1_I2C_IBSR_TRX *((volatile unsigned int*)(0x42702090UL)) +#define bFM3_MFS1_I2C_IBSR_RSA *((volatile unsigned int*)(0x42702094UL)) +#define bFM3_MFS1_I2C_IBSR_RACK *((volatile unsigned int*)(0x42702098UL)) +#define bFM3_MFS1_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270209CUL)) +#define bFM3_MFS1_I2C_SSR_TBI *((volatile unsigned int*)(0x427020A0UL)) +#define bFM3_MFS1_I2C_SSR_TDRE *((volatile unsigned int*)(0x427020A4UL)) +#define bFM3_MFS1_I2C_SSR_RDRF *((volatile unsigned int*)(0x427020A8UL)) +#define bFM3_MFS1_I2C_SSR_ORE *((volatile unsigned int*)(0x427020ACUL)) +#define bFM3_MFS1_I2C_SSR_TBIE *((volatile unsigned int*)(0x427020B0UL)) +#define bFM3_MFS1_I2C_SSR_DMA *((volatile unsigned int*)(0x427020B4UL)) +#define bFM3_MFS1_I2C_SSR_TSET *((volatile unsigned int*)(0x427020B8UL)) +#define bFM3_MFS1_I2C_SSR_REC *((volatile unsigned int*)(0x427020BCUL)) +#define bFM3_MFS1_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42702200UL)) +#define bFM3_MFS1_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42702204UL)) +#define bFM3_MFS1_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42702208UL)) +#define bFM3_MFS1_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270220CUL)) +#define bFM3_MFS1_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42702210UL)) +#define bFM3_MFS1_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42702214UL)) +#define bFM3_MFS1_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42702218UL)) +#define bFM3_MFS1_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270221CUL)) +#define bFM3_MFS1_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42702220UL)) +#define bFM3_MFS1_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42702224UL)) +#define bFM3_MFS1_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42702228UL)) +#define bFM3_MFS1_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270222CUL)) +#define bFM3_MFS1_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42702230UL)) +#define bFM3_MFS1_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42702234UL)) +#define bFM3_MFS1_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42702238UL)) +#define bFM3_MFS1_I2C_ISMK_EN *((volatile unsigned int*)(0x4270223CUL)) + +/* UART asynchronous channel 2 registers */ +#define bFM3_MFS2_UART_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_UART_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_UART_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_UART_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_UART_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_UART_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_UART_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_UART_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_UART_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_UART_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_UART_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_UART_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_UART_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_UART_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_UART_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_UART_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_UART_ESCR_P *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_UART_ESCR_PEN *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_UART_ESCR_INV *((volatile unsigned int*)(0x42704094UL)) +#define bFM3_MFS2_UART_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_UART_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_UART_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_UART_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_UART_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_UART_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_UART_SSR_PE *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_UART_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_UART_RDR_AD *((volatile unsigned int*)(0x42704120UL)) +#define bFM3_MFS2_UART_TDR_AD *((volatile unsigned int*)(0x42704120UL)) +#define bFM3_MFS2_UART_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) +#define bFM3_MFS2_UART_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) + +/* UART synchronous channel 2 registers */ +#define bFM3_MFS2_CSIO_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42704004UL)) +#define bFM3_MFS2_CSIO_SMR_BDS *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_CSIO_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_CSIO_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_CSIO_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_CSIO_SCR_SPI *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_CSIO_SCR_MS *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_CSIO_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_CSIO_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_CSIO_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) + +/* UART LIN channel 2 registers */ +#define bFM3_MFS2_LIN_SMR_SOE *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_LIN_SMR_SBL *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_LIN_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_LIN_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_LIN_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_LIN_SCR_TXE *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_LIN_SCR_RXE *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_LIN_SCR_TBIE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_LIN_SCR_TIE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_LIN_SCR_RIE *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_LIN_SCR_LBR *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_LIN_SCR_MS *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_LIN_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_LIN_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_LIN_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_LIN_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_LIN_SSR_FRE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_LIN_SSR_LBD *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_LIN_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_LIN_BGR_EXT *((volatile unsigned int*)(0x427041BCUL)) +#define bFM3_MFS2_LIN_BGR1_EXT *((volatile unsigned int*)(0x427041BCUL)) + +/* I2C channel 2 registers */ +#define bFM3_MFS2_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42704000UL)) +#define bFM3_MFS2_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42704004UL)) +#define bFM3_MFS2_I2C_SMR_TIE *((volatile unsigned int*)(0x42704008UL)) +#define bFM3_MFS2_I2C_SMR_RIE *((volatile unsigned int*)(0x4270400CUL)) +#define bFM3_MFS2_I2C_SMR_WUCR *((volatile unsigned int*)(0x42704010UL)) +#define bFM3_MFS2_I2C_SMR_MD0 *((volatile unsigned int*)(0x42704014UL)) +#define bFM3_MFS2_I2C_SMR_MD1 *((volatile unsigned int*)(0x42704018UL)) +#define bFM3_MFS2_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270401CUL)) +#define bFM3_MFS2_I2C_IBCR_INT *((volatile unsigned int*)(0x42704020UL)) +#define bFM3_MFS2_I2C_IBCR_BER *((volatile unsigned int*)(0x42704024UL)) +#define bFM3_MFS2_I2C_IBCR_INTE *((volatile unsigned int*)(0x42704028UL)) +#define bFM3_MFS2_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270402CUL)) +#define bFM3_MFS2_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42704030UL)) +#define bFM3_MFS2_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42704034UL)) +#define bFM3_MFS2_I2C_IBCR_ACT *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_I2C_IBCR_SCC *((volatile unsigned int*)(0x42704038UL)) +#define bFM3_MFS2_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270403CUL)) +#define bFM3_MFS2_I2C_IBSR_BB *((volatile unsigned int*)(0x42704080UL)) +#define bFM3_MFS2_I2C_IBSR_SPC *((volatile unsigned int*)(0x42704084UL)) +#define bFM3_MFS2_I2C_IBSR_RSC *((volatile unsigned int*)(0x42704088UL)) +#define bFM3_MFS2_I2C_IBSR_AL *((volatile unsigned int*)(0x4270408CUL)) +#define bFM3_MFS2_I2C_IBSR_TRX *((volatile unsigned int*)(0x42704090UL)) +#define bFM3_MFS2_I2C_IBSR_RSA *((volatile unsigned int*)(0x42704094UL)) +#define bFM3_MFS2_I2C_IBSR_RACK *((volatile unsigned int*)(0x42704098UL)) +#define bFM3_MFS2_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270409CUL)) +#define bFM3_MFS2_I2C_SSR_TBI *((volatile unsigned int*)(0x427040A0UL)) +#define bFM3_MFS2_I2C_SSR_TDRE *((volatile unsigned int*)(0x427040A4UL)) +#define bFM3_MFS2_I2C_SSR_RDRF *((volatile unsigned int*)(0x427040A8UL)) +#define bFM3_MFS2_I2C_SSR_ORE *((volatile unsigned int*)(0x427040ACUL)) +#define bFM3_MFS2_I2C_SSR_TBIE *((volatile unsigned int*)(0x427040B0UL)) +#define bFM3_MFS2_I2C_SSR_DMA *((volatile unsigned int*)(0x427040B4UL)) +#define bFM3_MFS2_I2C_SSR_TSET *((volatile unsigned int*)(0x427040B8UL)) +#define bFM3_MFS2_I2C_SSR_REC *((volatile unsigned int*)(0x427040BCUL)) +#define bFM3_MFS2_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42704200UL)) +#define bFM3_MFS2_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42704204UL)) +#define bFM3_MFS2_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42704208UL)) +#define bFM3_MFS2_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270420CUL)) +#define bFM3_MFS2_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42704210UL)) +#define bFM3_MFS2_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42704214UL)) +#define bFM3_MFS2_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42704218UL)) +#define bFM3_MFS2_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270421CUL)) +#define bFM3_MFS2_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42704220UL)) +#define bFM3_MFS2_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42704224UL)) +#define bFM3_MFS2_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42704228UL)) +#define bFM3_MFS2_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270422CUL)) +#define bFM3_MFS2_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42704230UL)) +#define bFM3_MFS2_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42704234UL)) +#define bFM3_MFS2_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42704238UL)) +#define bFM3_MFS2_I2C_ISMK_EN *((volatile unsigned int*)(0x4270423CUL)) + +/* UART asynchronous channel 3 registers */ +#define bFM3_MFS3_UART_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_UART_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_UART_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_UART_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_UART_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_UART_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_UART_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_UART_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_UART_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_UART_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_UART_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_UART_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_UART_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_UART_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_UART_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_UART_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_UART_ESCR_P *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_UART_ESCR_PEN *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_UART_ESCR_INV *((volatile unsigned int*)(0x42706094UL)) +#define bFM3_MFS3_UART_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_UART_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_UART_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_UART_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_UART_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_UART_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_UART_SSR_PE *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_UART_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_UART_RDR_AD *((volatile unsigned int*)(0x42706120UL)) +#define bFM3_MFS3_UART_TDR_AD *((volatile unsigned int*)(0x42706120UL)) +#define bFM3_MFS3_UART_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) +#define bFM3_MFS3_UART_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) + +/* UART synchronous channel 3 registers */ +#define bFM3_MFS3_CSIO_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42706004UL)) +#define bFM3_MFS3_CSIO_SMR_BDS *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_CSIO_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_CSIO_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_CSIO_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_CSIO_SCR_SPI *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_CSIO_SCR_MS *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_CSIO_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_CSIO_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_CSIO_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) + +/* UART LIN channel 3 registers */ +#define bFM3_MFS3_LIN_SMR_SOE *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_LIN_SMR_SBL *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_LIN_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_LIN_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_LIN_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_LIN_SCR_TXE *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_LIN_SCR_RXE *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_LIN_SCR_TBIE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_LIN_SCR_TIE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_LIN_SCR_RIE *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_LIN_SCR_LBR *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_LIN_SCR_MS *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_LIN_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_LIN_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_LIN_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_LIN_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_LIN_SSR_FRE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_LIN_SSR_LBD *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_LIN_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_LIN_BGR_EXT *((volatile unsigned int*)(0x427061BCUL)) +#define bFM3_MFS3_LIN_BGR1_EXT *((volatile unsigned int*)(0x427061BCUL)) + +/* I2C channel 3 registers */ +#define bFM3_MFS3_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42706000UL)) +#define bFM3_MFS3_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42706004UL)) +#define bFM3_MFS3_I2C_SMR_TIE *((volatile unsigned int*)(0x42706008UL)) +#define bFM3_MFS3_I2C_SMR_RIE *((volatile unsigned int*)(0x4270600CUL)) +#define bFM3_MFS3_I2C_SMR_WUCR *((volatile unsigned int*)(0x42706010UL)) +#define bFM3_MFS3_I2C_SMR_MD0 *((volatile unsigned int*)(0x42706014UL)) +#define bFM3_MFS3_I2C_SMR_MD1 *((volatile unsigned int*)(0x42706018UL)) +#define bFM3_MFS3_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270601CUL)) +#define bFM3_MFS3_I2C_IBCR_INT *((volatile unsigned int*)(0x42706020UL)) +#define bFM3_MFS3_I2C_IBCR_BER *((volatile unsigned int*)(0x42706024UL)) +#define bFM3_MFS3_I2C_IBCR_INTE *((volatile unsigned int*)(0x42706028UL)) +#define bFM3_MFS3_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270602CUL)) +#define bFM3_MFS3_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42706030UL)) +#define bFM3_MFS3_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42706034UL)) +#define bFM3_MFS3_I2C_IBCR_ACT *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_I2C_IBCR_SCC *((volatile unsigned int*)(0x42706038UL)) +#define bFM3_MFS3_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270603CUL)) +#define bFM3_MFS3_I2C_IBSR_BB *((volatile unsigned int*)(0x42706080UL)) +#define bFM3_MFS3_I2C_IBSR_SPC *((volatile unsigned int*)(0x42706084UL)) +#define bFM3_MFS3_I2C_IBSR_RSC *((volatile unsigned int*)(0x42706088UL)) +#define bFM3_MFS3_I2C_IBSR_AL *((volatile unsigned int*)(0x4270608CUL)) +#define bFM3_MFS3_I2C_IBSR_TRX *((volatile unsigned int*)(0x42706090UL)) +#define bFM3_MFS3_I2C_IBSR_RSA *((volatile unsigned int*)(0x42706094UL)) +#define bFM3_MFS3_I2C_IBSR_RACK *((volatile unsigned int*)(0x42706098UL)) +#define bFM3_MFS3_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270609CUL)) +#define bFM3_MFS3_I2C_SSR_TBI *((volatile unsigned int*)(0x427060A0UL)) +#define bFM3_MFS3_I2C_SSR_TDRE *((volatile unsigned int*)(0x427060A4UL)) +#define bFM3_MFS3_I2C_SSR_RDRF *((volatile unsigned int*)(0x427060A8UL)) +#define bFM3_MFS3_I2C_SSR_ORE *((volatile unsigned int*)(0x427060ACUL)) +#define bFM3_MFS3_I2C_SSR_TBIE *((volatile unsigned int*)(0x427060B0UL)) +#define bFM3_MFS3_I2C_SSR_DMA *((volatile unsigned int*)(0x427060B4UL)) +#define bFM3_MFS3_I2C_SSR_TSET *((volatile unsigned int*)(0x427060B8UL)) +#define bFM3_MFS3_I2C_SSR_REC *((volatile unsigned int*)(0x427060BCUL)) +#define bFM3_MFS3_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42706200UL)) +#define bFM3_MFS3_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42706204UL)) +#define bFM3_MFS3_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42706208UL)) +#define bFM3_MFS3_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270620CUL)) +#define bFM3_MFS3_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42706210UL)) +#define bFM3_MFS3_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42706214UL)) +#define bFM3_MFS3_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42706218UL)) +#define bFM3_MFS3_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270621CUL)) +#define bFM3_MFS3_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42706220UL)) +#define bFM3_MFS3_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42706224UL)) +#define bFM3_MFS3_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42706228UL)) +#define bFM3_MFS3_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270622CUL)) +#define bFM3_MFS3_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42706230UL)) +#define bFM3_MFS3_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42706234UL)) +#define bFM3_MFS3_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42706238UL)) +#define bFM3_MFS3_I2C_ISMK_EN *((volatile unsigned int*)(0x4270623CUL)) + +/* UART asynchronous channel 4 registers */ +#define bFM3_MFS4_UART_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_UART_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_UART_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_UART_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_UART_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_UART_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_UART_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_UART_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_UART_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_UART_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_UART_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_UART_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_UART_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_UART_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_UART_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_UART_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_UART_ESCR_P *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_UART_ESCR_PEN *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_UART_ESCR_INV *((volatile unsigned int*)(0x42708094UL)) +#define bFM3_MFS4_UART_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_UART_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_UART_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_UART_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_UART_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_UART_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_UART_SSR_PE *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_UART_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_UART_RDR_AD *((volatile unsigned int*)(0x42708120UL)) +#define bFM3_MFS4_UART_TDR_AD *((volatile unsigned int*)(0x42708120UL)) +#define bFM3_MFS4_UART_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_UART_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_UART_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_UART_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_UART_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_UART_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_UART_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_UART_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_UART_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_UART_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_UART_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_UART_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_UART_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_UART_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_UART_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_UART_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_UART_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_UART_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_UART_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_UART_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_UART_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_UART_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_UART_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_UART_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_UART_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_UART_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_UART_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_UART_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_UART_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_UART_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_UART_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_UART_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_UART_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_UART_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_UART_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_UART_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_UART_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_UART_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_UART_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_UART_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270833CUL)) + +/* UART synchronous channel 4 registers */ +#define bFM3_MFS4_CSIO_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_CSIO_SMR_SCKE *((volatile unsigned int*)(0x42708004UL)) +#define bFM3_MFS4_CSIO_SMR_BDS *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_CSIO_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_CSIO_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_CSIO_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_CSIO_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_CSIO_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_CSIO_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_CSIO_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_CSIO_SCR_SPI *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_CSIO_SCR_MS *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_CSIO_ESCR_L0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_CSIO_ESCR_L1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_CSIO_ESCR_L2 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_CSIO_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_CSIO_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_CSIO_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_CSIO_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_CSIO_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_CSIO_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_CSIO_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_CSIO_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_CSIO_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_CSIO_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_CSIO_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_CSIO_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_CSIO_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_CSIO_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_CSIO_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_CSIO_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL)) +#define bFM3_MFS4_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL)) + +/* UART LIN channel 4 registers */ +#define bFM3_MFS4_LIN_SMR_SOE *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_LIN_SMR_SBL *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_LIN_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_LIN_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_LIN_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_LIN_SCR_TXE *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_LIN_SCR_RXE *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_LIN_SCR_TBIE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_LIN_SCR_TIE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_LIN_SCR_RIE *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_LIN_SCR_LBR *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_LIN_SCR_MS *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_LIN_ESCR_LBIE *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_LIN_ESCR_ESBL *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_LIN_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_LIN_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_LIN_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_LIN_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_LIN_SSR_FRE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_LIN_SSR_LBD *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_LIN_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_LIN_BGR_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_LIN_BGR1_EXT *((volatile unsigned int*)(0x427081BCUL)) +#define bFM3_MFS4_LIN_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_LIN_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_LIN_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_LIN_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_LIN_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_LIN_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_LIN_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_LIN_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_LIN_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_LIN_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_LIN_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_LIN_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_LIN_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_LIN_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_LIN_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_LIN_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_LIN_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_LIN_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_LIN_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_LIN_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_LIN_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL)) +#define bFM3_MFS4_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL)) +#define bFM3_MFS4_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL)) + +/* I2C channel 4 registers */ +#define bFM3_MFS4_I2C_SMR_ITST0 *((volatile unsigned int*)(0x42708000UL)) +#define bFM3_MFS4_I2C_SMR_ITST1 *((volatile unsigned int*)(0x42708004UL)) +#define bFM3_MFS4_I2C_SMR_TIE *((volatile unsigned int*)(0x42708008UL)) +#define bFM3_MFS4_I2C_SMR_RIE *((volatile unsigned int*)(0x4270800CUL)) +#define bFM3_MFS4_I2C_SMR_WUCR *((volatile unsigned int*)(0x42708010UL)) +#define bFM3_MFS4_I2C_SMR_MD0 *((volatile unsigned int*)(0x42708014UL)) +#define bFM3_MFS4_I2C_SMR_MD1 *((volatile unsigned int*)(0x42708018UL)) +#define bFM3_MFS4_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270801CUL)) +#define bFM3_MFS4_I2C_IBCR_INT *((volatile unsigned int*)(0x42708020UL)) +#define bFM3_MFS4_I2C_IBCR_BER *((volatile unsigned int*)(0x42708024UL)) +#define bFM3_MFS4_I2C_IBCR_INTE *((volatile unsigned int*)(0x42708028UL)) +#define bFM3_MFS4_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270802CUL)) +#define bFM3_MFS4_I2C_IBCR_WSEL *((volatile unsigned int*)(0x42708030UL)) +#define bFM3_MFS4_I2C_IBCR_ACKE *((volatile unsigned int*)(0x42708034UL)) +#define bFM3_MFS4_I2C_IBCR_ACT *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_I2C_IBCR_SCC *((volatile unsigned int*)(0x42708038UL)) +#define bFM3_MFS4_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270803CUL)) +#define bFM3_MFS4_I2C_IBSR_BB *((volatile unsigned int*)(0x42708080UL)) +#define bFM3_MFS4_I2C_IBSR_SPC *((volatile unsigned int*)(0x42708084UL)) +#define bFM3_MFS4_I2C_IBSR_RSC *((volatile unsigned int*)(0x42708088UL)) +#define bFM3_MFS4_I2C_IBSR_AL *((volatile unsigned int*)(0x4270808CUL)) +#define bFM3_MFS4_I2C_IBSR_TRX *((volatile unsigned int*)(0x42708090UL)) +#define bFM3_MFS4_I2C_IBSR_RSA *((volatile unsigned int*)(0x42708094UL)) +#define bFM3_MFS4_I2C_IBSR_RACK *((volatile unsigned int*)(0x42708098UL)) +#define bFM3_MFS4_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270809CUL)) +#define bFM3_MFS4_I2C_SSR_TBI *((volatile unsigned int*)(0x427080A0UL)) +#define bFM3_MFS4_I2C_SSR_TDRE *((volatile unsigned int*)(0x427080A4UL)) +#define bFM3_MFS4_I2C_SSR_RDRF *((volatile unsigned int*)(0x427080A8UL)) +#define bFM3_MFS4_I2C_SSR_ORE *((volatile unsigned int*)(0x427080ACUL)) +#define bFM3_MFS4_I2C_SSR_TBIE *((volatile unsigned int*)(0x427080B0UL)) +#define bFM3_MFS4_I2C_SSR_DMA *((volatile unsigned int*)(0x427080B4UL)) +#define bFM3_MFS4_I2C_SSR_TSET *((volatile unsigned int*)(0x427080B8UL)) +#define bFM3_MFS4_I2C_SSR_REC *((volatile unsigned int*)(0x427080BCUL)) +#define bFM3_MFS4_I2C_ISBA_SA0 *((volatile unsigned int*)(0x42708200UL)) +#define bFM3_MFS4_I2C_ISBA_SA1 *((volatile unsigned int*)(0x42708204UL)) +#define bFM3_MFS4_I2C_ISBA_SA2 *((volatile unsigned int*)(0x42708208UL)) +#define bFM3_MFS4_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270820CUL)) +#define bFM3_MFS4_I2C_ISBA_SA4 *((volatile unsigned int*)(0x42708210UL)) +#define bFM3_MFS4_I2C_ISBA_SA5 *((volatile unsigned int*)(0x42708214UL)) +#define bFM3_MFS4_I2C_ISBA_SA6 *((volatile unsigned int*)(0x42708218UL)) +#define bFM3_MFS4_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270821CUL)) +#define bFM3_MFS4_I2C_ISMK_SM0 *((volatile unsigned int*)(0x42708220UL)) +#define bFM3_MFS4_I2C_ISMK_SM1 *((volatile unsigned int*)(0x42708224UL)) +#define bFM3_MFS4_I2C_ISMK_SM2 *((volatile unsigned int*)(0x42708228UL)) +#define bFM3_MFS4_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270822CUL)) +#define bFM3_MFS4_I2C_ISMK_SM4 *((volatile unsigned int*)(0x42708230UL)) +#define bFM3_MFS4_I2C_ISMK_SM5 *((volatile unsigned int*)(0x42708234UL)) +#define bFM3_MFS4_I2C_ISMK_SM6 *((volatile unsigned int*)(0x42708238UL)) +#define bFM3_MFS4_I2C_ISMK_EN *((volatile unsigned int*)(0x4270823CUL)) +#define bFM3_MFS4_I2C_FCR_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_I2C_FCR_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_I2C_FCR_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_I2C_FCR_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_I2C_FCR_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_I2C_FCR_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_I2C_FCR_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_I2C_FCR_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_I2C_FCR_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_I2C_FCR_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_I2C_FCR_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_I2C_FCR_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_I2C_FCR_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_I2C_FCR0_FE1 *((volatile unsigned int*)(0x42708280UL)) +#define bFM3_MFS4_I2C_FCR0_FE2 *((volatile unsigned int*)(0x42708284UL)) +#define bFM3_MFS4_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x42708288UL)) +#define bFM3_MFS4_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270828CUL)) +#define bFM3_MFS4_I2C_FCR0_FSET *((volatile unsigned int*)(0x42708290UL)) +#define bFM3_MFS4_I2C_FCR0_FLD *((volatile unsigned int*)(0x42708294UL)) +#define bFM3_MFS4_I2C_FCR0_FLST *((volatile unsigned int*)(0x42708298UL)) +#define bFM3_MFS4_I2C_FCR1_FSEL *((volatile unsigned int*)(0x427082A0UL)) +#define bFM3_MFS4_I2C_FCR1_FTIE *((volatile unsigned int*)(0x427082A4UL)) +#define bFM3_MFS4_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x427082A8UL)) +#define bFM3_MFS4_I2C_FCR1_FRIE *((volatile unsigned int*)(0x427082ACUL)) +#define bFM3_MFS4_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x427082B0UL)) +#define bFM3_MFS4_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x427082B8UL)) +#define bFM3_MFS4_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x427082BCUL)) +#define bFM3_MFS4_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x42708320UL)) +#define bFM3_MFS4_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x42708324UL)) +#define bFM3_MFS4_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x42708328UL)) +#define bFM3_MFS4_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270832CUL)) +#define bFM3_MFS4_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x42708330UL)) +#define bFM3_MFS4_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x42708334UL)) +#define bFM3_MFS4_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x42708338UL)) +#define bFM3_MFS4_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270833CUL)) +#define bFM3_MFS4_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x42708300UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x42708304UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x42708308UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270830CUL)) +#define bFM3_MFS4_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x42708310UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x42708314UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x42708318UL)) +#define bFM3_MFS4_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270831CUL)) +#define bFM3_MFS4_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x42708340UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x42708344UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x42708348UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270834CUL)) +#define bFM3_MFS4_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x42708350UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x42708354UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x42708358UL)) +#define bFM3_MFS4_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270835CUL)) + +/* UART asynchronous channel 5 registers */ +#define bFM3_MFS5_UART_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_UART_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_UART_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_UART_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_UART_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_UART_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_UART_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_UART_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_UART_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_UART_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_UART_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_UART_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_UART_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_UART_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_UART_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_UART_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_UART_ESCR_P *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_UART_ESCR_PEN *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_UART_ESCR_INV *((volatile unsigned int*)(0x4270A094UL)) +#define bFM3_MFS5_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_UART_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_UART_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_UART_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_UART_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_UART_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_UART_SSR_PE *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_UART_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_UART_RDR_AD *((volatile unsigned int*)(0x4270A120UL)) +#define bFM3_MFS5_UART_TDR_AD *((volatile unsigned int*)(0x4270A120UL)) +#define bFM3_MFS5_UART_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_UART_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_UART_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_UART_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_UART_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_UART_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_UART_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_UART_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_UART_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_UART_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_UART_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_UART_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_UART_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A33CUL)) + +/* UART synchronous channel 5 registers */ +#define bFM3_MFS5_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270A004UL)) +#define bFM3_MFS5_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_CSIO_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_CSIO_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL)) +#define bFM3_MFS5_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL)) + +/* UART LIN channel 5 registers */ +#define bFM3_MFS5_LIN_SMR_SOE *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_LIN_SMR_SBL *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_LIN_SCR_TXE *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_LIN_SCR_RXE *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_LIN_SCR_TIE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_LIN_SCR_RIE *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_LIN_SCR_LBR *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_LIN_SCR_MS *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_LIN_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_LIN_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_LIN_SSR_FRE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_LIN_SSR_LBD *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_LIN_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_LIN_BGR_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270A1BCUL)) +#define bFM3_MFS5_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_LIN_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_LIN_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_LIN_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL)) +#define bFM3_MFS5_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL)) +#define bFM3_MFS5_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL)) + +/* I2C channel 5 registers */ +#define bFM3_MFS5_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270A000UL)) +#define bFM3_MFS5_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270A004UL)) +#define bFM3_MFS5_I2C_SMR_TIE *((volatile unsigned int*)(0x4270A008UL)) +#define bFM3_MFS5_I2C_SMR_RIE *((volatile unsigned int*)(0x4270A00CUL)) +#define bFM3_MFS5_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270A010UL)) +#define bFM3_MFS5_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270A014UL)) +#define bFM3_MFS5_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270A018UL)) +#define bFM3_MFS5_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270A01CUL)) +#define bFM3_MFS5_I2C_IBCR_INT *((volatile unsigned int*)(0x4270A020UL)) +#define bFM3_MFS5_I2C_IBCR_BER *((volatile unsigned int*)(0x4270A024UL)) +#define bFM3_MFS5_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270A028UL)) +#define bFM3_MFS5_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270A02CUL)) +#define bFM3_MFS5_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270A030UL)) +#define bFM3_MFS5_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270A034UL)) +#define bFM3_MFS5_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270A038UL)) +#define bFM3_MFS5_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270A03CUL)) +#define bFM3_MFS5_I2C_IBSR_BB *((volatile unsigned int*)(0x4270A080UL)) +#define bFM3_MFS5_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270A084UL)) +#define bFM3_MFS5_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270A088UL)) +#define bFM3_MFS5_I2C_IBSR_AL *((volatile unsigned int*)(0x4270A08CUL)) +#define bFM3_MFS5_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270A090UL)) +#define bFM3_MFS5_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270A094UL)) +#define bFM3_MFS5_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270A098UL)) +#define bFM3_MFS5_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270A09CUL)) +#define bFM3_MFS5_I2C_SSR_TBI *((volatile unsigned int*)(0x4270A0A0UL)) +#define bFM3_MFS5_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270A0A4UL)) +#define bFM3_MFS5_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270A0A8UL)) +#define bFM3_MFS5_I2C_SSR_ORE *((volatile unsigned int*)(0x4270A0ACUL)) +#define bFM3_MFS5_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270A0B0UL)) +#define bFM3_MFS5_I2C_SSR_DMA *((volatile unsigned int*)(0x4270A0B4UL)) +#define bFM3_MFS5_I2C_SSR_TSET *((volatile unsigned int*)(0x4270A0B8UL)) +#define bFM3_MFS5_I2C_SSR_REC *((volatile unsigned int*)(0x4270A0BCUL)) +#define bFM3_MFS5_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270A200UL)) +#define bFM3_MFS5_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270A204UL)) +#define bFM3_MFS5_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270A208UL)) +#define bFM3_MFS5_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270A20CUL)) +#define bFM3_MFS5_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270A210UL)) +#define bFM3_MFS5_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270A214UL)) +#define bFM3_MFS5_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270A218UL)) +#define bFM3_MFS5_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270A21CUL)) +#define bFM3_MFS5_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270A220UL)) +#define bFM3_MFS5_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270A224UL)) +#define bFM3_MFS5_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270A228UL)) +#define bFM3_MFS5_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270A22CUL)) +#define bFM3_MFS5_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270A230UL)) +#define bFM3_MFS5_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270A234UL)) +#define bFM3_MFS5_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270A238UL)) +#define bFM3_MFS5_I2C_ISMK_EN *((volatile unsigned int*)(0x4270A23CUL)) +#define bFM3_MFS5_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_I2C_FCR_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_I2C_FCR_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_I2C_FCR_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270A280UL)) +#define bFM3_MFS5_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270A284UL)) +#define bFM3_MFS5_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270A288UL)) +#define bFM3_MFS5_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270A28CUL)) +#define bFM3_MFS5_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270A290UL)) +#define bFM3_MFS5_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270A294UL)) +#define bFM3_MFS5_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270A298UL)) +#define bFM3_MFS5_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270A2A0UL)) +#define bFM3_MFS5_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270A2A4UL)) +#define bFM3_MFS5_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270A2A8UL)) +#define bFM3_MFS5_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270A2ACUL)) +#define bFM3_MFS5_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270A2B0UL)) +#define bFM3_MFS5_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270A2B8UL)) +#define bFM3_MFS5_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270A2BCUL)) +#define bFM3_MFS5_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270A320UL)) +#define bFM3_MFS5_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270A324UL)) +#define bFM3_MFS5_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270A328UL)) +#define bFM3_MFS5_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270A32CUL)) +#define bFM3_MFS5_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270A330UL)) +#define bFM3_MFS5_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270A334UL)) +#define bFM3_MFS5_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270A338UL)) +#define bFM3_MFS5_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270A33CUL)) +#define bFM3_MFS5_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270A300UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270A304UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270A308UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270A30CUL)) +#define bFM3_MFS5_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270A310UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270A314UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270A318UL)) +#define bFM3_MFS5_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270A31CUL)) +#define bFM3_MFS5_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270A340UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270A344UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270A348UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270A34CUL)) +#define bFM3_MFS5_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270A350UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270A354UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270A358UL)) +#define bFM3_MFS5_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270A35CUL)) + +/* UART asynchronous channel 6 registers */ +#define bFM3_MFS6_UART_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_UART_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_UART_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_UART_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_UART_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_UART_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_UART_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_UART_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_UART_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_UART_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_UART_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_UART_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_UART_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_UART_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_UART_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_UART_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_UART_ESCR_P *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_UART_ESCR_PEN *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_UART_ESCR_INV *((volatile unsigned int*)(0x4270C094UL)) +#define bFM3_MFS6_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_UART_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_UART_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_UART_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_UART_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_UART_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_UART_SSR_PE *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_UART_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_UART_RDR_AD *((volatile unsigned int*)(0x4270C120UL)) +#define bFM3_MFS6_UART_TDR_AD *((volatile unsigned int*)(0x4270C120UL)) +#define bFM3_MFS6_UART_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_UART_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_UART_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_UART_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_UART_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_UART_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_UART_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_UART_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_UART_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_UART_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_UART_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_UART_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_UART_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C33CUL)) + +/* UART synchronous channel 6 registers */ +#define bFM3_MFS6_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270C004UL)) +#define bFM3_MFS6_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_CSIO_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_CSIO_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL)) +#define bFM3_MFS6_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL)) + +/* UART LIN channel 6 registers */ +#define bFM3_MFS6_LIN_SMR_SOE *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_LIN_SMR_SBL *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_LIN_SCR_TXE *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_LIN_SCR_RXE *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_LIN_SCR_TIE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_LIN_SCR_RIE *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_LIN_SCR_LBR *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_LIN_SCR_MS *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_LIN_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_LIN_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_LIN_SSR_FRE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_LIN_SSR_LBD *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_LIN_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_LIN_BGR_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270C1BCUL)) +#define bFM3_MFS6_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_LIN_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_LIN_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_LIN_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL)) +#define bFM3_MFS6_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL)) +#define bFM3_MFS6_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL)) + +/* I2C channel 6 registers */ +#define bFM3_MFS6_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270C000UL)) +#define bFM3_MFS6_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270C004UL)) +#define bFM3_MFS6_I2C_SMR_TIE *((volatile unsigned int*)(0x4270C008UL)) +#define bFM3_MFS6_I2C_SMR_RIE *((volatile unsigned int*)(0x4270C00CUL)) +#define bFM3_MFS6_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270C010UL)) +#define bFM3_MFS6_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270C014UL)) +#define bFM3_MFS6_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270C018UL)) +#define bFM3_MFS6_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270C01CUL)) +#define bFM3_MFS6_I2C_IBCR_INT *((volatile unsigned int*)(0x4270C020UL)) +#define bFM3_MFS6_I2C_IBCR_BER *((volatile unsigned int*)(0x4270C024UL)) +#define bFM3_MFS6_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270C028UL)) +#define bFM3_MFS6_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270C02CUL)) +#define bFM3_MFS6_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270C030UL)) +#define bFM3_MFS6_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270C034UL)) +#define bFM3_MFS6_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270C038UL)) +#define bFM3_MFS6_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270C03CUL)) +#define bFM3_MFS6_I2C_IBSR_BB *((volatile unsigned int*)(0x4270C080UL)) +#define bFM3_MFS6_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270C084UL)) +#define bFM3_MFS6_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270C088UL)) +#define bFM3_MFS6_I2C_IBSR_AL *((volatile unsigned int*)(0x4270C08CUL)) +#define bFM3_MFS6_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270C090UL)) +#define bFM3_MFS6_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270C094UL)) +#define bFM3_MFS6_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270C098UL)) +#define bFM3_MFS6_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270C09CUL)) +#define bFM3_MFS6_I2C_SSR_TBI *((volatile unsigned int*)(0x4270C0A0UL)) +#define bFM3_MFS6_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270C0A4UL)) +#define bFM3_MFS6_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270C0A8UL)) +#define bFM3_MFS6_I2C_SSR_ORE *((volatile unsigned int*)(0x4270C0ACUL)) +#define bFM3_MFS6_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270C0B0UL)) +#define bFM3_MFS6_I2C_SSR_DMA *((volatile unsigned int*)(0x4270C0B4UL)) +#define bFM3_MFS6_I2C_SSR_TSET *((volatile unsigned int*)(0x4270C0B8UL)) +#define bFM3_MFS6_I2C_SSR_REC *((volatile unsigned int*)(0x4270C0BCUL)) +#define bFM3_MFS6_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270C200UL)) +#define bFM3_MFS6_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270C204UL)) +#define bFM3_MFS6_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270C208UL)) +#define bFM3_MFS6_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270C20CUL)) +#define bFM3_MFS6_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270C210UL)) +#define bFM3_MFS6_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270C214UL)) +#define bFM3_MFS6_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270C218UL)) +#define bFM3_MFS6_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270C21CUL)) +#define bFM3_MFS6_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270C220UL)) +#define bFM3_MFS6_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270C224UL)) +#define bFM3_MFS6_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270C228UL)) +#define bFM3_MFS6_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270C22CUL)) +#define bFM3_MFS6_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270C230UL)) +#define bFM3_MFS6_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270C234UL)) +#define bFM3_MFS6_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270C238UL)) +#define bFM3_MFS6_I2C_ISMK_EN *((volatile unsigned int*)(0x4270C23CUL)) +#define bFM3_MFS6_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_I2C_FCR_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_I2C_FCR_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_I2C_FCR_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270C280UL)) +#define bFM3_MFS6_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270C284UL)) +#define bFM3_MFS6_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270C288UL)) +#define bFM3_MFS6_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270C28CUL)) +#define bFM3_MFS6_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270C290UL)) +#define bFM3_MFS6_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270C294UL)) +#define bFM3_MFS6_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270C298UL)) +#define bFM3_MFS6_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270C2A0UL)) +#define bFM3_MFS6_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270C2A4UL)) +#define bFM3_MFS6_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270C2A8UL)) +#define bFM3_MFS6_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270C2ACUL)) +#define bFM3_MFS6_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270C2B0UL)) +#define bFM3_MFS6_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270C2B8UL)) +#define bFM3_MFS6_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270C2BCUL)) +#define bFM3_MFS6_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270C320UL)) +#define bFM3_MFS6_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270C324UL)) +#define bFM3_MFS6_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270C328UL)) +#define bFM3_MFS6_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270C32CUL)) +#define bFM3_MFS6_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270C330UL)) +#define bFM3_MFS6_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270C334UL)) +#define bFM3_MFS6_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270C338UL)) +#define bFM3_MFS6_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270C33CUL)) +#define bFM3_MFS6_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270C300UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270C304UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270C308UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270C30CUL)) +#define bFM3_MFS6_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270C310UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270C314UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270C318UL)) +#define bFM3_MFS6_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270C31CUL)) +#define bFM3_MFS6_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270C340UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270C344UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270C348UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270C34CUL)) +#define bFM3_MFS6_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270C350UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270C354UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270C358UL)) +#define bFM3_MFS6_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270C35CUL)) + +/* UART asynchronous channel 7 registers */ +#define bFM3_MFS7_UART_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_UART_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_UART_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_UART_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_UART_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_UART_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_UART_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_UART_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_UART_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_UART_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_UART_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_UART_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_UART_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_UART_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_UART_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_UART_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_UART_ESCR_P *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_UART_ESCR_PEN *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_UART_ESCR_INV *((volatile unsigned int*)(0x4270E094UL)) +#define bFM3_MFS7_UART_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_UART_ESCR_FLWEN *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_UART_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_UART_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_UART_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_UART_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_UART_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_UART_SSR_PE *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_UART_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_UART_RDR_AD *((volatile unsigned int*)(0x4270E120UL)) +#define bFM3_MFS7_UART_TDR_AD *((volatile unsigned int*)(0x4270E120UL)) +#define bFM3_MFS7_UART_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_UART_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_UART_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_UART_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_UART_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_UART_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_UART_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_UART_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_UART_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_UART_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_UART_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_UART_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_UART_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_UART_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_UART_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_UART_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_UART_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_UART_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_UART_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_UART_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_UART_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_UART_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_UART_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_UART_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_UART_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_UART_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_UART_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_UART_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_UART_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_UART_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_UART_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_UART_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_UART_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_UART_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_UART_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_UART_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_UART_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_UART_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_UART_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_UART_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_UART_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_UART_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_UART_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_UART_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_UART_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_UART_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_UART_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_UART_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_UART_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_UART_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_UART_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_UART_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_UART_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_UART_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_UART_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_UART_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_UART_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_UART_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_UART_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_UART_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_UART_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_UART_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E33CUL)) + +/* UART synchronous channel 7 registers */ +#define bFM3_MFS7_CSIO_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_CSIO_SMR_SCKE *((volatile unsigned int*)(0x4270E004UL)) +#define bFM3_MFS7_CSIO_SMR_BDS *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_CSIO_SMR_SCINV *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_CSIO_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_CSIO_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_CSIO_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_CSIO_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_CSIO_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_CSIO_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_CSIO_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_CSIO_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_CSIO_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_CSIO_SCR_SPI *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_CSIO_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_CSIO_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_CSIO_ESCR_L0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_CSIO_ESCR_L1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_CSIO_ESCR_L2 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_CSIO_ESCR_WT0 *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_CSIO_ESCR_WT1 *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_CSIO_ESCR_SOP *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_CSIO_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_CSIO_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_CSIO_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_CSIO_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_CSIO_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_CSIO_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_CSIO_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_CSIO_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_CSIO_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_CSIO_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_CSIO_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_CSIO_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_CSIO_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_CSIO_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_CSIO_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_CSIO_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_CSIO_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_CSIO_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_CSIO_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_CSIO_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_CSIO_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_CSIO_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_CSIO_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_CSIO_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_CSIO_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_CSIO_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_CSIO_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_CSIO_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_CSIO_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_CSIO_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_CSIO_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_CSIO_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_CSIO_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_CSIO_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_CSIO_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_CSIO_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL)) +#define bFM3_MFS7_CSIO_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL)) + +/* UART LIN channel 7 registers */ +#define bFM3_MFS7_LIN_SMR_SOE *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_LIN_SMR_SBL *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_LIN_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_LIN_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_LIN_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_LIN_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_LIN_SCR_TXE *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_LIN_SCR_RXE *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_LIN_SCR_TBIE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_LIN_SCR_TIE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_LIN_SCR_RIE *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_LIN_SCR_LBR *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_LIN_SCR_MS *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_LIN_SCR_UPCL *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_LIN_ESCR_DEL0 *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_LIN_ESCR_DEL1 *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_LIN_ESCR_LBL0 *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_LIN_ESCR_LBL1 *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_LIN_ESCR_LBIE *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_LIN_ESCR_ESBL *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_LIN_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_LIN_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_LIN_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_LIN_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_LIN_SSR_FRE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_LIN_SSR_LBD *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_LIN_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_LIN_BGR_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_LIN_BGR1_EXT *((volatile unsigned int*)(0x4270E1BCUL)) +#define bFM3_MFS7_LIN_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_LIN_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_LIN_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_LIN_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_LIN_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_LIN_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_LIN_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_LIN_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_LIN_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_LIN_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_LIN_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_LIN_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_LIN_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_LIN_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_LIN_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_LIN_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_LIN_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_LIN_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_LIN_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_LIN_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_LIN_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_LIN_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_LIN_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_LIN_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_LIN_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_LIN_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_LIN_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_LIN_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_LIN_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_LIN_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_LIN_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_LIN_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_LIN_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_LIN_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_LIN_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_LIN_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_LIN_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_LIN_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_LIN_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_LIN_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_LIN_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_LIN_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_LIN_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_LIN_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_LIN_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_LIN_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL)) +#define bFM3_MFS7_LIN_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL)) +#define bFM3_MFS7_LIN_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL)) + +/* I2C channel 7 registers */ +#define bFM3_MFS7_I2C_SMR_ITST0 *((volatile unsigned int*)(0x4270E000UL)) +#define bFM3_MFS7_I2C_SMR_ITST1 *((volatile unsigned int*)(0x4270E004UL)) +#define bFM3_MFS7_I2C_SMR_TIE *((volatile unsigned int*)(0x4270E008UL)) +#define bFM3_MFS7_I2C_SMR_RIE *((volatile unsigned int*)(0x4270E00CUL)) +#define bFM3_MFS7_I2C_SMR_WUCR *((volatile unsigned int*)(0x4270E010UL)) +#define bFM3_MFS7_I2C_SMR_MD0 *((volatile unsigned int*)(0x4270E014UL)) +#define bFM3_MFS7_I2C_SMR_MD1 *((volatile unsigned int*)(0x4270E018UL)) +#define bFM3_MFS7_I2C_SMR_MD2 *((volatile unsigned int*)(0x4270E01CUL)) +#define bFM3_MFS7_I2C_IBCR_INT *((volatile unsigned int*)(0x4270E020UL)) +#define bFM3_MFS7_I2C_IBCR_BER *((volatile unsigned int*)(0x4270E024UL)) +#define bFM3_MFS7_I2C_IBCR_INTE *((volatile unsigned int*)(0x4270E028UL)) +#define bFM3_MFS7_I2C_IBCR_CNDE *((volatile unsigned int*)(0x4270E02CUL)) +#define bFM3_MFS7_I2C_IBCR_WSEL *((volatile unsigned int*)(0x4270E030UL)) +#define bFM3_MFS7_I2C_IBCR_ACKE *((volatile unsigned int*)(0x4270E034UL)) +#define bFM3_MFS7_I2C_IBCR_ACT *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_I2C_IBCR_SCC *((volatile unsigned int*)(0x4270E038UL)) +#define bFM3_MFS7_I2C_IBCR_MSS *((volatile unsigned int*)(0x4270E03CUL)) +#define bFM3_MFS7_I2C_IBSR_BB *((volatile unsigned int*)(0x4270E080UL)) +#define bFM3_MFS7_I2C_IBSR_SPC *((volatile unsigned int*)(0x4270E084UL)) +#define bFM3_MFS7_I2C_IBSR_RSC *((volatile unsigned int*)(0x4270E088UL)) +#define bFM3_MFS7_I2C_IBSR_AL *((volatile unsigned int*)(0x4270E08CUL)) +#define bFM3_MFS7_I2C_IBSR_TRX *((volatile unsigned int*)(0x4270E090UL)) +#define bFM3_MFS7_I2C_IBSR_RSA *((volatile unsigned int*)(0x4270E094UL)) +#define bFM3_MFS7_I2C_IBSR_RACK *((volatile unsigned int*)(0x4270E098UL)) +#define bFM3_MFS7_I2C_IBSR_FBT *((volatile unsigned int*)(0x4270E09CUL)) +#define bFM3_MFS7_I2C_SSR_TBI *((volatile unsigned int*)(0x4270E0A0UL)) +#define bFM3_MFS7_I2C_SSR_TDRE *((volatile unsigned int*)(0x4270E0A4UL)) +#define bFM3_MFS7_I2C_SSR_RDRF *((volatile unsigned int*)(0x4270E0A8UL)) +#define bFM3_MFS7_I2C_SSR_ORE *((volatile unsigned int*)(0x4270E0ACUL)) +#define bFM3_MFS7_I2C_SSR_TBIE *((volatile unsigned int*)(0x4270E0B0UL)) +#define bFM3_MFS7_I2C_SSR_DMA *((volatile unsigned int*)(0x4270E0B4UL)) +#define bFM3_MFS7_I2C_SSR_TSET *((volatile unsigned int*)(0x4270E0B8UL)) +#define bFM3_MFS7_I2C_SSR_REC *((volatile unsigned int*)(0x4270E0BCUL)) +#define bFM3_MFS7_I2C_ISBA_SA0 *((volatile unsigned int*)(0x4270E200UL)) +#define bFM3_MFS7_I2C_ISBA_SA1 *((volatile unsigned int*)(0x4270E204UL)) +#define bFM3_MFS7_I2C_ISBA_SA2 *((volatile unsigned int*)(0x4270E208UL)) +#define bFM3_MFS7_I2C_ISBA_SA3 *((volatile unsigned int*)(0x4270E20CUL)) +#define bFM3_MFS7_I2C_ISBA_SA4 *((volatile unsigned int*)(0x4270E210UL)) +#define bFM3_MFS7_I2C_ISBA_SA5 *((volatile unsigned int*)(0x4270E214UL)) +#define bFM3_MFS7_I2C_ISBA_SA6 *((volatile unsigned int*)(0x4270E218UL)) +#define bFM3_MFS7_I2C_ISBA_SAEN *((volatile unsigned int*)(0x4270E21CUL)) +#define bFM3_MFS7_I2C_ISMK_SM0 *((volatile unsigned int*)(0x4270E220UL)) +#define bFM3_MFS7_I2C_ISMK_SM1 *((volatile unsigned int*)(0x4270E224UL)) +#define bFM3_MFS7_I2C_ISMK_SM2 *((volatile unsigned int*)(0x4270E228UL)) +#define bFM3_MFS7_I2C_ISMK_SM3 *((volatile unsigned int*)(0x4270E22CUL)) +#define bFM3_MFS7_I2C_ISMK_SM4 *((volatile unsigned int*)(0x4270E230UL)) +#define bFM3_MFS7_I2C_ISMK_SM5 *((volatile unsigned int*)(0x4270E234UL)) +#define bFM3_MFS7_I2C_ISMK_SM6 *((volatile unsigned int*)(0x4270E238UL)) +#define bFM3_MFS7_I2C_ISMK_EN *((volatile unsigned int*)(0x4270E23CUL)) +#define bFM3_MFS7_I2C_FCR_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_I2C_FCR_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_I2C_FCR_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_I2C_FCR_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_I2C_FCR_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_I2C_FCR_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_I2C_FCR_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_I2C_FCR_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_I2C_FCR_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_I2C_FCR_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_I2C_FCR_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_I2C_FCR_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_I2C_FCR_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_I2C_FCR_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_I2C_FCR0_FE1 *((volatile unsigned int*)(0x4270E280UL)) +#define bFM3_MFS7_I2C_FCR0_FE2 *((volatile unsigned int*)(0x4270E284UL)) +#define bFM3_MFS7_I2C_FCR0_FCL1 *((volatile unsigned int*)(0x4270E288UL)) +#define bFM3_MFS7_I2C_FCR0_FCL2 *((volatile unsigned int*)(0x4270E28CUL)) +#define bFM3_MFS7_I2C_FCR0_FSET *((volatile unsigned int*)(0x4270E290UL)) +#define bFM3_MFS7_I2C_FCR0_FLD *((volatile unsigned int*)(0x4270E294UL)) +#define bFM3_MFS7_I2C_FCR0_FLST *((volatile unsigned int*)(0x4270E298UL)) +#define bFM3_MFS7_I2C_FCR1_FSEL *((volatile unsigned int*)(0x4270E2A0UL)) +#define bFM3_MFS7_I2C_FCR1_FTIE *((volatile unsigned int*)(0x4270E2A4UL)) +#define bFM3_MFS7_I2C_FCR1_FDRQ *((volatile unsigned int*)(0x4270E2A8UL)) +#define bFM3_MFS7_I2C_FCR1_FRIE *((volatile unsigned int*)(0x4270E2ACUL)) +#define bFM3_MFS7_I2C_FCR1_FLSTE *((volatile unsigned int*)(0x4270E2B0UL)) +#define bFM3_MFS7_I2C_FCR1_FTST0 *((volatile unsigned int*)(0x4270E2B8UL)) +#define bFM3_MFS7_I2C_FCR1_FTST1 *((volatile unsigned int*)(0x4270E2BCUL)) +#define bFM3_MFS7_I2C_FBYTE_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_I2C_FBYTE_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_I2C_FBYTE_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_I2C_FBYTE_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_I2C_FBYTE_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_I2C_FBYTE_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_I2C_FBYTE_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD8 *((volatile unsigned int*)(0x4270E320UL)) +#define bFM3_MFS7_I2C_FBYTE_FD9 *((volatile unsigned int*)(0x4270E324UL)) +#define bFM3_MFS7_I2C_FBYTE_FD10 *((volatile unsigned int*)(0x4270E328UL)) +#define bFM3_MFS7_I2C_FBYTE_FD11 *((volatile unsigned int*)(0x4270E32CUL)) +#define bFM3_MFS7_I2C_FBYTE_FD12 *((volatile unsigned int*)(0x4270E330UL)) +#define bFM3_MFS7_I2C_FBYTE_FD13 *((volatile unsigned int*)(0x4270E334UL)) +#define bFM3_MFS7_I2C_FBYTE_FD14 *((volatile unsigned int*)(0x4270E338UL)) +#define bFM3_MFS7_I2C_FBYTE_FD15 *((volatile unsigned int*)(0x4270E33CUL)) +#define bFM3_MFS7_I2C_FBYTE1_FD0 *((volatile unsigned int*)(0x4270E300UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD1 *((volatile unsigned int*)(0x4270E304UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD2 *((volatile unsigned int*)(0x4270E308UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD3 *((volatile unsigned int*)(0x4270E30CUL)) +#define bFM3_MFS7_I2C_FBYTE1_FD4 *((volatile unsigned int*)(0x4270E310UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD5 *((volatile unsigned int*)(0x4270E314UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD6 *((volatile unsigned int*)(0x4270E318UL)) +#define bFM3_MFS7_I2C_FBYTE1_FD7 *((volatile unsigned int*)(0x4270E31CUL)) +#define bFM3_MFS7_I2C_FBYTE2_FD8 *((volatile unsigned int*)(0x4270E340UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD9 *((volatile unsigned int*)(0x4270E344UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD10 *((volatile unsigned int*)(0x4270E348UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD11 *((volatile unsigned int*)(0x4270E34CUL)) +#define bFM3_MFS7_I2C_FBYTE2_FD12 *((volatile unsigned int*)(0x4270E350UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD13 *((volatile unsigned int*)(0x4270E354UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD14 *((volatile unsigned int*)(0x4270E358UL)) +#define bFM3_MFS7_I2C_FBYTE2_FD15 *((volatile unsigned int*)(0x4270E35CUL)) + +/* CRC registers */ +#define bFM3_CRC_CRCCR_INIT *((volatile unsigned int*)(0x42720000UL)) +#define bFM3_CRC_CRCCR_CRC32 *((volatile unsigned int*)(0x42720004UL)) +#define bFM3_CRC_CRCCR_LTLEND *((volatile unsigned int*)(0x42720008UL)) +#define bFM3_CRC_CRCCR_LSBFST *((volatile unsigned int*)(0x4272000CUL)) +#define bFM3_CRC_CRCCR_CRCLTE *((volatile unsigned int*)(0x42720010UL)) +#define bFM3_CRC_CRCCR_CRCLSF *((volatile unsigned int*)(0x42720014UL)) +#define bFM3_CRC_CRCCR_FXOR *((volatile unsigned int*)(0x42720018UL)) + +/* Watch counter registers */ +#define bFM3_WC_WCRD_CTR0 *((volatile unsigned int*)(0x42740000UL)) +#define bFM3_WC_WCRD_CTR1 *((volatile unsigned int*)(0x42740004UL)) +#define bFM3_WC_WCRD_CTR2 *((volatile unsigned int*)(0x42740008UL)) +#define bFM3_WC_WCRD_CTR3 *((volatile unsigned int*)(0x4274000CUL)) +#define bFM3_WC_WCRD_CTR4 *((volatile unsigned int*)(0x42740010UL)) +#define bFM3_WC_WCRD_CTR5 *((volatile unsigned int*)(0x42740014UL)) +#define bFM3_WC_WCRL_RLC0 *((volatile unsigned int*)(0x42740020UL)) +#define bFM3_WC_WCRL_RLC1 *((volatile unsigned int*)(0x42740024UL)) +#define bFM3_WC_WCRL_RLC2 *((volatile unsigned int*)(0x42740028UL)) +#define bFM3_WC_WCRL_RLC3 *((volatile unsigned int*)(0x4274002CUL)) +#define bFM3_WC_WCRL_RLC4 *((volatile unsigned int*)(0x42740030UL)) +#define bFM3_WC_WCRL_RLC5 *((volatile unsigned int*)(0x42740034UL)) +#define bFM3_WC_WCCR_WCIF *((volatile unsigned int*)(0x42740040UL)) +#define bFM3_WC_WCCR_WCIE *((volatile unsigned int*)(0x42740044UL)) +#define bFM3_WC_WCCR_CS0 *((volatile unsigned int*)(0x42740048UL)) +#define bFM3_WC_WCCR_CS1 *((volatile unsigned int*)(0x4274004CUL)) +#define bFM3_WC_WCCR_WCOP *((volatile unsigned int*)(0x42740058UL)) +#define bFM3_WC_WCCR_WCEN *((volatile unsigned int*)(0x4274005CUL)) +#define bFM3_WC_CLK_SEL_SEL_IN *((volatile unsigned int*)(0x42740200UL)) +#define bFM3_WC_CLK_SEL_SEL_OUT *((volatile unsigned int*)(0x42740220UL)) +#define bFM3_WC_CLK_EN_CLK_EN *((volatile unsigned int*)(0x42740280UL)) +#define bFM3_WC_CLK_EN_CLK_EN_R *((volatile unsigned int*)(0x42740284UL)) + +/* External bus interface registers */ +#define bFM3_EXBUS_MODE0_WDTH0 *((volatile unsigned int*)(0x427E0000UL)) +#define bFM3_EXBUS_MODE0_WDTH1 *((volatile unsigned int*)(0x427E0004UL)) +#define bFM3_EXBUS_MODE0_RBMON *((volatile unsigned int*)(0x427E0008UL)) +#define bFM3_EXBUS_MODE0_WEOFF *((volatile unsigned int*)(0x427E000CUL)) +#define bFM3_EXBUS_MODE0_NAND *((volatile unsigned int*)(0x427E0010UL)) +#define bFM3_EXBUS_MODE0_PAGE *((volatile unsigned int*)(0x427E0014UL)) +#define bFM3_EXBUS_MODE0_TEST *((volatile unsigned int*)(0x427E0018UL)) +#define bFM3_EXBUS_MODE1_WDTH0 *((volatile unsigned int*)(0x427E0080UL)) +#define bFM3_EXBUS_MODE1_WDTH1 *((volatile unsigned int*)(0x427E0084UL)) +#define bFM3_EXBUS_MODE1_RBMON *((volatile unsigned int*)(0x427E0088UL)) +#define bFM3_EXBUS_MODE1_WEOFF *((volatile unsigned int*)(0x427E008CUL)) +#define bFM3_EXBUS_MODE1_NAND *((volatile unsigned int*)(0x427E0090UL)) +#define bFM3_EXBUS_MODE1_PAGE *((volatile unsigned int*)(0x427E0094UL)) +#define bFM3_EXBUS_MODE1_TEST *((volatile unsigned int*)(0x427E0098UL)) +#define bFM3_EXBUS_MODE2_WDTH0 *((volatile unsigned int*)(0x427E0100UL)) +#define bFM3_EXBUS_MODE2_WDTH1 *((volatile unsigned int*)(0x427E0104UL)) +#define bFM3_EXBUS_MODE2_RBMON *((volatile unsigned int*)(0x427E0108UL)) +#define bFM3_EXBUS_MODE2_WEOFF *((volatile unsigned int*)(0x427E010CUL)) +#define bFM3_EXBUS_MODE2_NAND *((volatile unsigned int*)(0x427E0110UL)) +#define bFM3_EXBUS_MODE2_PAGE *((volatile unsigned int*)(0x427E0114UL)) +#define bFM3_EXBUS_MODE2_TEST *((volatile unsigned int*)(0x427E0118UL)) +#define bFM3_EXBUS_MODE3_WDTH0 *((volatile unsigned int*)(0x427E0180UL)) +#define bFM3_EXBUS_MODE3_WDTH1 *((volatile unsigned int*)(0x427E0184UL)) +#define bFM3_EXBUS_MODE3_RBMON *((volatile unsigned int*)(0x427E0188UL)) +#define bFM3_EXBUS_MODE3_WEOFF *((volatile unsigned int*)(0x427E018CUL)) +#define bFM3_EXBUS_MODE3_NAND *((volatile unsigned int*)(0x427E0190UL)) +#define bFM3_EXBUS_MODE3_PAGE *((volatile unsigned int*)(0x427E0194UL)) +#define bFM3_EXBUS_MODE3_TEST *((volatile unsigned int*)(0x427E0198UL)) +#define bFM3_EXBUS_MODE4_WDTH0 *((volatile unsigned int*)(0x427E0200UL)) +#define bFM3_EXBUS_MODE4_WDTH1 *((volatile unsigned int*)(0x427E0204UL)) +#define bFM3_EXBUS_MODE4_RBMON *((volatile unsigned int*)(0x427E0208UL)) +#define bFM3_EXBUS_MODE4_WEOFF *((volatile unsigned int*)(0x427E020CUL)) +#define bFM3_EXBUS_MODE4_NAND *((volatile unsigned int*)(0x427E0210UL)) +#define bFM3_EXBUS_MODE4_PAGE *((volatile unsigned int*)(0x427E0214UL)) +#define bFM3_EXBUS_MODE4_TEST *((volatile unsigned int*)(0x427E0218UL)) +#define bFM3_EXBUS_MODE5_WDTH0 *((volatile unsigned int*)(0x427E0280UL)) +#define bFM3_EXBUS_MODE5_WDTH1 *((volatile unsigned int*)(0x427E0284UL)) +#define bFM3_EXBUS_MODE5_RBMON *((volatile unsigned int*)(0x427E0288UL)) +#define bFM3_EXBUS_MODE5_WEOFF *((volatile unsigned int*)(0x427E028CUL)) +#define bFM3_EXBUS_MODE5_NAND *((volatile unsigned int*)(0x427E0290UL)) +#define bFM3_EXBUS_MODE5_PAGE *((volatile unsigned int*)(0x427E0294UL)) +#define bFM3_EXBUS_MODE5_TEST *((volatile unsigned int*)(0x427E0298UL)) +#define bFM3_EXBUS_MODE6_WDTH0 *((volatile unsigned int*)(0x427E0300UL)) +#define bFM3_EXBUS_MODE6_WDTH1 *((volatile unsigned int*)(0x427E0304UL)) +#define bFM3_EXBUS_MODE6_RBMON *((volatile unsigned int*)(0x427E0308UL)) +#define bFM3_EXBUS_MODE6_WEOFF *((volatile unsigned int*)(0x427E030CUL)) +#define bFM3_EXBUS_MODE6_NAND *((volatile unsigned int*)(0x427E0310UL)) +#define bFM3_EXBUS_MODE6_PAGE *((volatile unsigned int*)(0x427E0314UL)) +#define bFM3_EXBUS_MODE6_TEST *((volatile unsigned int*)(0x427E0318UL)) +#define bFM3_EXBUS_MODE7_WDTH0 *((volatile unsigned int*)(0x427E0380UL)) +#define bFM3_EXBUS_MODE7_WDTH1 *((volatile unsigned int*)(0x427E0384UL)) +#define bFM3_EXBUS_MODE7_RBMON *((volatile unsigned int*)(0x427E0388UL)) +#define bFM3_EXBUS_MODE7_WEOFF *((volatile unsigned int*)(0x427E038CUL)) +#define bFM3_EXBUS_MODE7_NAND *((volatile unsigned int*)(0x427E0390UL)) +#define bFM3_EXBUS_MODE7_PAGE *((volatile unsigned int*)(0x427E0394UL)) +#define bFM3_EXBUS_MODE7_TEST *((volatile unsigned int*)(0x427E0398UL)) +#define bFM3_EXBUS_TIM0_RACC0 *((volatile unsigned int*)(0x427E0400UL)) +#define bFM3_EXBUS_TIM0_RACC1 *((volatile unsigned int*)(0x427E0404UL)) +#define bFM3_EXBUS_TIM0_RACC2 *((volatile unsigned int*)(0x427E0408UL)) +#define bFM3_EXBUS_TIM0_RACC3 *((volatile unsigned int*)(0x427E040CUL)) +#define bFM3_EXBUS_TIM0_RADC0 *((volatile unsigned int*)(0x427E0410UL)) +#define bFM3_EXBUS_TIM0_RADC1 *((volatile unsigned int*)(0x427E0414UL)) +#define bFM3_EXBUS_TIM0_RADC2 *((volatile unsigned int*)(0x427E0418UL)) +#define bFM3_EXBUS_TIM0_RADC3 *((volatile unsigned int*)(0x427E041CUL)) +#define bFM3_EXBUS_TIM0_FRADC0 *((volatile unsigned int*)(0x427E0420UL)) +#define bFM3_EXBUS_TIM0_FRADC1 *((volatile unsigned int*)(0x427E0424UL)) +#define bFM3_EXBUS_TIM0_FRADC2 *((volatile unsigned int*)(0x427E0428UL)) +#define bFM3_EXBUS_TIM0_FRADC3 *((volatile unsigned int*)(0x427E042CUL)) +#define bFM3_EXBUS_TIM0_RIDLC0 *((volatile unsigned int*)(0x427E0430UL)) +#define bFM3_EXBUS_TIM0_RIDLC1 *((volatile unsigned int*)(0x427E0434UL)) +#define bFM3_EXBUS_TIM0_RIDLC2 *((volatile unsigned int*)(0x427E0438UL)) +#define bFM3_EXBUS_TIM0_RIDLC3 *((volatile unsigned int*)(0x427E043CUL)) +#define bFM3_EXBUS_TIM0_WACC0 *((volatile unsigned int*)(0x427E0440UL)) +#define bFM3_EXBUS_TIM0_WACC1 *((volatile unsigned int*)(0x427E0444UL)) +#define bFM3_EXBUS_TIM0_WACC2 *((volatile unsigned int*)(0x427E0448UL)) +#define bFM3_EXBUS_TIM0_WACC3 *((volatile unsigned int*)(0x427E044CUL)) +#define bFM3_EXBUS_TIM0_WADC0 *((volatile unsigned int*)(0x427E0450UL)) +#define bFM3_EXBUS_TIM0_WADC1 *((volatile unsigned int*)(0x427E0454UL)) +#define bFM3_EXBUS_TIM0_WADC2 *((volatile unsigned int*)(0x427E0458UL)) +#define bFM3_EXBUS_TIM0_WADC3 *((volatile unsigned int*)(0x427E045CUL)) +#define bFM3_EXBUS_TIM0_WWEC0 *((volatile unsigned int*)(0x427E0460UL)) +#define bFM3_EXBUS_TIM0_WWEC1 *((volatile unsigned int*)(0x427E0464UL)) +#define bFM3_EXBUS_TIM0_WWEC2 *((volatile unsigned int*)(0x427E0468UL)) +#define bFM3_EXBUS_TIM0_WWEC3 *((volatile unsigned int*)(0x427E046CUL)) +#define bFM3_EXBUS_TIM0_WIDLC0 *((volatile unsigned int*)(0x427E0470UL)) +#define bFM3_EXBUS_TIM0_WIDLC1 *((volatile unsigned int*)(0x427E0474UL)) +#define bFM3_EXBUS_TIM0_WIDLC2 *((volatile unsigned int*)(0x427E0478UL)) +#define bFM3_EXBUS_TIM0_WIDLC3 *((volatile unsigned int*)(0x427E047CUL)) +#define bFM3_EXBUS_TIM1_RACC0 *((volatile unsigned int*)(0x427E0480UL)) +#define bFM3_EXBUS_TIM1_RACC1 *((volatile unsigned int*)(0x427E0484UL)) +#define bFM3_EXBUS_TIM1_RACC2 *((volatile unsigned int*)(0x427E0488UL)) +#define bFM3_EXBUS_TIM1_RACC3 *((volatile unsigned int*)(0x427E048CUL)) +#define bFM3_EXBUS_TIM1_RADC0 *((volatile unsigned int*)(0x427E0490UL)) +#define bFM3_EXBUS_TIM1_RADC1 *((volatile unsigned int*)(0x427E0494UL)) +#define bFM3_EXBUS_TIM1_RADC2 *((volatile unsigned int*)(0x427E0498UL)) +#define bFM3_EXBUS_TIM1_RADC3 *((volatile unsigned int*)(0x427E049CUL)) +#define bFM3_EXBUS_TIM1_FRADC0 *((volatile unsigned int*)(0x427E04A0UL)) +#define bFM3_EXBUS_TIM1_FRADC1 *((volatile unsigned int*)(0x427E04A4UL)) +#define bFM3_EXBUS_TIM1_FRADC2 *((volatile unsigned int*)(0x427E04A8UL)) +#define bFM3_EXBUS_TIM1_FRADC3 *((volatile unsigned int*)(0x427E04ACUL)) +#define bFM3_EXBUS_TIM1_RIDLC0 *((volatile unsigned int*)(0x427E04B0UL)) +#define bFM3_EXBUS_TIM1_RIDLC1 *((volatile unsigned int*)(0x427E04B4UL)) +#define bFM3_EXBUS_TIM1_RIDLC2 *((volatile unsigned int*)(0x427E04B8UL)) +#define bFM3_EXBUS_TIM1_RIDLC3 *((volatile unsigned int*)(0x427E04BCUL)) +#define bFM3_EXBUS_TIM1_WACC0 *((volatile unsigned int*)(0x427E04C0UL)) +#define bFM3_EXBUS_TIM1_WACC1 *((volatile unsigned int*)(0x427E04C4UL)) +#define bFM3_EXBUS_TIM1_WACC2 *((volatile unsigned int*)(0x427E04C8UL)) +#define bFM3_EXBUS_TIM1_WACC3 *((volatile unsigned int*)(0x427E04CCUL)) +#define bFM3_EXBUS_TIM1_WADC0 *((volatile unsigned int*)(0x427E04D0UL)) +#define bFM3_EXBUS_TIM1_WADC1 *((volatile unsigned int*)(0x427E04D4UL)) +#define bFM3_EXBUS_TIM1_WADC2 *((volatile unsigned int*)(0x427E04D8UL)) +#define bFM3_EXBUS_TIM1_WADC3 *((volatile unsigned int*)(0x427E04DCUL)) +#define bFM3_EXBUS_TIM1_WWEC0 *((volatile unsigned int*)(0x427E04E0UL)) +#define bFM3_EXBUS_TIM1_WWEC1 *((volatile unsigned int*)(0x427E04E4UL)) +#define bFM3_EXBUS_TIM1_WWEC2 *((volatile unsigned int*)(0x427E04E8UL)) +#define bFM3_EXBUS_TIM1_WWEC3 *((volatile unsigned int*)(0x427E04ECUL)) +#define bFM3_EXBUS_TIM1_WIDLC0 *((volatile unsigned int*)(0x427E04F0UL)) +#define bFM3_EXBUS_TIM1_WIDLC1 *((volatile unsigned int*)(0x427E04F4UL)) +#define bFM3_EXBUS_TIM1_WIDLC2 *((volatile unsigned int*)(0x427E04F8UL)) +#define bFM3_EXBUS_TIM1_WIDLC3 *((volatile unsigned int*)(0x427E04FCUL)) +#define bFM3_EXBUS_TIM2_RACC0 *((volatile unsigned int*)(0x427E0500UL)) +#define bFM3_EXBUS_TIM2_RACC1 *((volatile unsigned int*)(0x427E0504UL)) +#define bFM3_EXBUS_TIM2_RACC2 *((volatile unsigned int*)(0x427E0508UL)) +#define bFM3_EXBUS_TIM2_RACC3 *((volatile unsigned int*)(0x427E050CUL)) +#define bFM3_EXBUS_TIM2_RADC0 *((volatile unsigned int*)(0x427E0510UL)) +#define bFM3_EXBUS_TIM2_RADC1 *((volatile unsigned int*)(0x427E0514UL)) +#define bFM3_EXBUS_TIM2_RADC2 *((volatile unsigned int*)(0x427E0518UL)) +#define bFM3_EXBUS_TIM2_RADC3 *((volatile unsigned int*)(0x427E051CUL)) +#define bFM3_EXBUS_TIM2_FRADC0 *((volatile unsigned int*)(0x427E0520UL)) +#define bFM3_EXBUS_TIM2_FRADC1 *((volatile unsigned int*)(0x427E0524UL)) +#define bFM3_EXBUS_TIM2_FRADC2 *((volatile unsigned int*)(0x427E0528UL)) +#define bFM3_EXBUS_TIM2_FRADC3 *((volatile unsigned int*)(0x427E052CUL)) +#define bFM3_EXBUS_TIM2_RIDLC0 *((volatile unsigned int*)(0x427E0530UL)) +#define bFM3_EXBUS_TIM2_RIDLC1 *((volatile unsigned int*)(0x427E0534UL)) +#define bFM3_EXBUS_TIM2_RIDLC2 *((volatile unsigned int*)(0x427E0538UL)) +#define bFM3_EXBUS_TIM2_RIDLC3 *((volatile unsigned int*)(0x427E053CUL)) +#define bFM3_EXBUS_TIM2_WACC0 *((volatile unsigned int*)(0x427E0540UL)) +#define bFM3_EXBUS_TIM2_WACC1 *((volatile unsigned int*)(0x427E0544UL)) +#define bFM3_EXBUS_TIM2_WACC2 *((volatile unsigned int*)(0x427E0548UL)) +#define bFM3_EXBUS_TIM2_WACC3 *((volatile unsigned int*)(0x427E054CUL)) +#define bFM3_EXBUS_TIM2_WADC0 *((volatile unsigned int*)(0x427E0550UL)) +#define bFM3_EXBUS_TIM2_WADC1 *((volatile unsigned int*)(0x427E0554UL)) +#define bFM3_EXBUS_TIM2_WADC2 *((volatile unsigned int*)(0x427E0558UL)) +#define bFM3_EXBUS_TIM2_WADC3 *((volatile unsigned int*)(0x427E055CUL)) +#define bFM3_EXBUS_TIM2_WWEC0 *((volatile unsigned int*)(0x427E0560UL)) +#define bFM3_EXBUS_TIM2_WWEC1 *((volatile unsigned int*)(0x427E0564UL)) +#define bFM3_EXBUS_TIM2_WWEC2 *((volatile unsigned int*)(0x427E0568UL)) +#define bFM3_EXBUS_TIM2_WWEC3 *((volatile unsigned int*)(0x427E056CUL)) +#define bFM3_EXBUS_TIM2_WIDLC0 *((volatile unsigned int*)(0x427E0570UL)) +#define bFM3_EXBUS_TIM2_WIDLC1 *((volatile unsigned int*)(0x427E0574UL)) +#define bFM3_EXBUS_TIM2_WIDLC2 *((volatile unsigned int*)(0x427E0578UL)) +#define bFM3_EXBUS_TIM2_WIDLC3 *((volatile unsigned int*)(0x427E057CUL)) +#define bFM3_EXBUS_TIM3_RACC0 *((volatile unsigned int*)(0x427E0580UL)) +#define bFM3_EXBUS_TIM3_RACC1 *((volatile unsigned int*)(0x427E0584UL)) +#define bFM3_EXBUS_TIM3_RACC2 *((volatile unsigned int*)(0x427E0588UL)) +#define bFM3_EXBUS_TIM3_RACC3 *((volatile unsigned int*)(0x427E058CUL)) +#define bFM3_EXBUS_TIM3_RADC0 *((volatile unsigned int*)(0x427E0590UL)) +#define bFM3_EXBUS_TIM3_RADC1 *((volatile unsigned int*)(0x427E0594UL)) +#define bFM3_EXBUS_TIM3_RADC2 *((volatile unsigned int*)(0x427E0598UL)) +#define bFM3_EXBUS_TIM3_RADC3 *((volatile unsigned int*)(0x427E059CUL)) +#define bFM3_EXBUS_TIM3_FRADC0 *((volatile unsigned int*)(0x427E05A0UL)) +#define bFM3_EXBUS_TIM3_FRADC1 *((volatile unsigned int*)(0x427E05A4UL)) +#define bFM3_EXBUS_TIM3_FRADC2 *((volatile unsigned int*)(0x427E05A8UL)) +#define bFM3_EXBUS_TIM3_FRADC3 *((volatile unsigned int*)(0x427E05ACUL)) +#define bFM3_EXBUS_TIM3_RIDLC0 *((volatile unsigned int*)(0x427E05B0UL)) +#define bFM3_EXBUS_TIM3_RIDLC1 *((volatile unsigned int*)(0x427E05B4UL)) +#define bFM3_EXBUS_TIM3_RIDLC2 *((volatile unsigned int*)(0x427E05B8UL)) +#define bFM3_EXBUS_TIM3_RIDLC3 *((volatile unsigned int*)(0x427E05BCUL)) +#define bFM3_EXBUS_TIM3_WACC0 *((volatile unsigned int*)(0x427E05C0UL)) +#define bFM3_EXBUS_TIM3_WACC1 *((volatile unsigned int*)(0x427E05C4UL)) +#define bFM3_EXBUS_TIM3_WACC2 *((volatile unsigned int*)(0x427E05C8UL)) +#define bFM3_EXBUS_TIM3_WACC3 *((volatile unsigned int*)(0x427E05CCUL)) +#define bFM3_EXBUS_TIM3_WADC0 *((volatile unsigned int*)(0x427E05D0UL)) +#define bFM3_EXBUS_TIM3_WADC1 *((volatile unsigned int*)(0x427E05D4UL)) +#define bFM3_EXBUS_TIM3_WADC2 *((volatile unsigned int*)(0x427E05D8UL)) +#define bFM3_EXBUS_TIM3_WADC3 *((volatile unsigned int*)(0x427E05DCUL)) +#define bFM3_EXBUS_TIM3_WWEC0 *((volatile unsigned int*)(0x427E05E0UL)) +#define bFM3_EXBUS_TIM3_WWEC1 *((volatile unsigned int*)(0x427E05E4UL)) +#define bFM3_EXBUS_TIM3_WWEC2 *((volatile unsigned int*)(0x427E05E8UL)) +#define bFM3_EXBUS_TIM3_WWEC3 *((volatile unsigned int*)(0x427E05ECUL)) +#define bFM3_EXBUS_TIM3_WIDLC0 *((volatile unsigned int*)(0x427E05F0UL)) +#define bFM3_EXBUS_TIM3_WIDLC1 *((volatile unsigned int*)(0x427E05F4UL)) +#define bFM3_EXBUS_TIM3_WIDLC2 *((volatile unsigned int*)(0x427E05F8UL)) +#define bFM3_EXBUS_TIM3_WIDLC3 *((volatile unsigned int*)(0x427E05FCUL)) +#define bFM3_EXBUS_TIM4_RACC0 *((volatile unsigned int*)(0x427E0600UL)) +#define bFM3_EXBUS_TIM4_RACC1 *((volatile unsigned int*)(0x427E0604UL)) +#define bFM3_EXBUS_TIM4_RACC2 *((volatile unsigned int*)(0x427E0608UL)) +#define bFM3_EXBUS_TIM4_RACC3 *((volatile unsigned int*)(0x427E060CUL)) +#define bFM3_EXBUS_TIM4_RADC0 *((volatile unsigned int*)(0x427E0610UL)) +#define bFM3_EXBUS_TIM4_RADC1 *((volatile unsigned int*)(0x427E0614UL)) +#define bFM3_EXBUS_TIM4_RADC2 *((volatile unsigned int*)(0x427E0618UL)) +#define bFM3_EXBUS_TIM4_RADC3 *((volatile unsigned int*)(0x427E061CUL)) +#define bFM3_EXBUS_TIM4_FRADC0 *((volatile unsigned int*)(0x427E0620UL)) +#define bFM3_EXBUS_TIM4_FRADC1 *((volatile unsigned int*)(0x427E0624UL)) +#define bFM3_EXBUS_TIM4_FRADC2 *((volatile unsigned int*)(0x427E0628UL)) +#define bFM3_EXBUS_TIM4_FRADC3 *((volatile unsigned int*)(0x427E062CUL)) +#define bFM3_EXBUS_TIM4_RIDLC0 *((volatile unsigned int*)(0x427E0630UL)) +#define bFM3_EXBUS_TIM4_RIDLC1 *((volatile unsigned int*)(0x427E0634UL)) +#define bFM3_EXBUS_TIM4_RIDLC2 *((volatile unsigned int*)(0x427E0638UL)) +#define bFM3_EXBUS_TIM4_RIDLC3 *((volatile unsigned int*)(0x427E063CUL)) +#define bFM3_EXBUS_TIM4_WACC0 *((volatile unsigned int*)(0x427E0640UL)) +#define bFM3_EXBUS_TIM4_WACC1 *((volatile unsigned int*)(0x427E0644UL)) +#define bFM3_EXBUS_TIM4_WACC2 *((volatile unsigned int*)(0x427E0648UL)) +#define bFM3_EXBUS_TIM4_WACC3 *((volatile unsigned int*)(0x427E064CUL)) +#define bFM3_EXBUS_TIM4_WADC0 *((volatile unsigned int*)(0x427E0650UL)) +#define bFM3_EXBUS_TIM4_WADC1 *((volatile unsigned int*)(0x427E0654UL)) +#define bFM3_EXBUS_TIM4_WADC2 *((volatile unsigned int*)(0x427E0658UL)) +#define bFM3_EXBUS_TIM4_WADC3 *((volatile unsigned int*)(0x427E065CUL)) +#define bFM3_EXBUS_TIM4_WWEC0 *((volatile unsigned int*)(0x427E0660UL)) +#define bFM3_EXBUS_TIM4_WWEC1 *((volatile unsigned int*)(0x427E0664UL)) +#define bFM3_EXBUS_TIM4_WWEC2 *((volatile unsigned int*)(0x427E0668UL)) +#define bFM3_EXBUS_TIM4_WWEC3 *((volatile unsigned int*)(0x427E066CUL)) +#define bFM3_EXBUS_TIM4_WIDLC0 *((volatile unsigned int*)(0x427E0670UL)) +#define bFM3_EXBUS_TIM4_WIDLC1 *((volatile unsigned int*)(0x427E0674UL)) +#define bFM3_EXBUS_TIM4_WIDLC2 *((volatile unsigned int*)(0x427E0678UL)) +#define bFM3_EXBUS_TIM4_WIDLC3 *((volatile unsigned int*)(0x427E067CUL)) +#define bFM3_EXBUS_TIM5_RACC0 *((volatile unsigned int*)(0x427E0680UL)) +#define bFM3_EXBUS_TIM5_RACC1 *((volatile unsigned int*)(0x427E0684UL)) +#define bFM3_EXBUS_TIM5_RACC2 *((volatile unsigned int*)(0x427E0688UL)) +#define bFM3_EXBUS_TIM5_RACC3 *((volatile unsigned int*)(0x427E068CUL)) +#define bFM3_EXBUS_TIM5_RADC0 *((volatile unsigned int*)(0x427E0690UL)) +#define bFM3_EXBUS_TIM5_RADC1 *((volatile unsigned int*)(0x427E0694UL)) +#define bFM3_EXBUS_TIM5_RADC2 *((volatile unsigned int*)(0x427E0698UL)) +#define bFM3_EXBUS_TIM5_RADC3 *((volatile unsigned int*)(0x427E069CUL)) +#define bFM3_EXBUS_TIM5_FRADC0 *((volatile unsigned int*)(0x427E06A0UL)) +#define bFM3_EXBUS_TIM5_FRADC1 *((volatile unsigned int*)(0x427E06A4UL)) +#define bFM3_EXBUS_TIM5_FRADC2 *((volatile unsigned int*)(0x427E06A8UL)) +#define bFM3_EXBUS_TIM5_FRADC3 *((volatile unsigned int*)(0x427E06ACUL)) +#define bFM3_EXBUS_TIM5_RIDLC0 *((volatile unsigned int*)(0x427E06B0UL)) +#define bFM3_EXBUS_TIM5_RIDLC1 *((volatile unsigned int*)(0x427E06B4UL)) +#define bFM3_EXBUS_TIM5_RIDLC2 *((volatile unsigned int*)(0x427E06B8UL)) +#define bFM3_EXBUS_TIM5_RIDLC3 *((volatile unsigned int*)(0x427E06BCUL)) +#define bFM3_EXBUS_TIM5_WACC0 *((volatile unsigned int*)(0x427E06C0UL)) +#define bFM3_EXBUS_TIM5_WACC1 *((volatile unsigned int*)(0x427E06C4UL)) +#define bFM3_EXBUS_TIM5_WACC2 *((volatile unsigned int*)(0x427E06C8UL)) +#define bFM3_EXBUS_TIM5_WACC3 *((volatile unsigned int*)(0x427E06CCUL)) +#define bFM3_EXBUS_TIM5_WADC0 *((volatile unsigned int*)(0x427E06D0UL)) +#define bFM3_EXBUS_TIM5_WADC1 *((volatile unsigned int*)(0x427E06D4UL)) +#define bFM3_EXBUS_TIM5_WADC2 *((volatile unsigned int*)(0x427E06D8UL)) +#define bFM3_EXBUS_TIM5_WADC3 *((volatile unsigned int*)(0x427E06DCUL)) +#define bFM3_EXBUS_TIM5_WWEC0 *((volatile unsigned int*)(0x427E06E0UL)) +#define bFM3_EXBUS_TIM5_WWEC1 *((volatile unsigned int*)(0x427E06E4UL)) +#define bFM3_EXBUS_TIM5_WWEC2 *((volatile unsigned int*)(0x427E06E8UL)) +#define bFM3_EXBUS_TIM5_WWEC3 *((volatile unsigned int*)(0x427E06ECUL)) +#define bFM3_EXBUS_TIM5_WIDLC0 *((volatile unsigned int*)(0x427E06F0UL)) +#define bFM3_EXBUS_TIM5_WIDLC1 *((volatile unsigned int*)(0x427E06F4UL)) +#define bFM3_EXBUS_TIM5_WIDLC2 *((volatile unsigned int*)(0x427E06F8UL)) +#define bFM3_EXBUS_TIM5_WIDLC3 *((volatile unsigned int*)(0x427E06FCUL)) +#define bFM3_EXBUS_TIM6_RACC0 *((volatile unsigned int*)(0x427E0700UL)) +#define bFM3_EXBUS_TIM6_RACC1 *((volatile unsigned int*)(0x427E0704UL)) +#define bFM3_EXBUS_TIM6_RACC2 *((volatile unsigned int*)(0x427E0708UL)) +#define bFM3_EXBUS_TIM6_RACC3 *((volatile unsigned int*)(0x427E070CUL)) +#define bFM3_EXBUS_TIM6_RADC0 *((volatile unsigned int*)(0x427E0710UL)) +#define bFM3_EXBUS_TIM6_RADC1 *((volatile unsigned int*)(0x427E0714UL)) +#define bFM3_EXBUS_TIM6_RADC2 *((volatile unsigned int*)(0x427E0718UL)) +#define bFM3_EXBUS_TIM6_RADC3 *((volatile unsigned int*)(0x427E071CUL)) +#define bFM3_EXBUS_TIM6_FRADC0 *((volatile unsigned int*)(0x427E0720UL)) +#define bFM3_EXBUS_TIM6_FRADC1 *((volatile unsigned int*)(0x427E0724UL)) +#define bFM3_EXBUS_TIM6_FRADC2 *((volatile unsigned int*)(0x427E0728UL)) +#define bFM3_EXBUS_TIM6_FRADC3 *((volatile unsigned int*)(0x427E072CUL)) +#define bFM3_EXBUS_TIM6_RIDLC0 *((volatile unsigned int*)(0x427E0730UL)) +#define bFM3_EXBUS_TIM6_RIDLC1 *((volatile unsigned int*)(0x427E0734UL)) +#define bFM3_EXBUS_TIM6_RIDLC2 *((volatile unsigned int*)(0x427E0738UL)) +#define bFM3_EXBUS_TIM6_RIDLC3 *((volatile unsigned int*)(0x427E073CUL)) +#define bFM3_EXBUS_TIM6_WACC0 *((volatile unsigned int*)(0x427E0740UL)) +#define bFM3_EXBUS_TIM6_WACC1 *((volatile unsigned int*)(0x427E0744UL)) +#define bFM3_EXBUS_TIM6_WACC2 *((volatile unsigned int*)(0x427E0748UL)) +#define bFM3_EXBUS_TIM6_WACC3 *((volatile unsigned int*)(0x427E074CUL)) +#define bFM3_EXBUS_TIM6_WADC0 *((volatile unsigned int*)(0x427E0750UL)) +#define bFM3_EXBUS_TIM6_WADC1 *((volatile unsigned int*)(0x427E0754UL)) +#define bFM3_EXBUS_TIM6_WADC2 *((volatile unsigned int*)(0x427E0758UL)) +#define bFM3_EXBUS_TIM6_WADC3 *((volatile unsigned int*)(0x427E075CUL)) +#define bFM3_EXBUS_TIM6_WWEC0 *((volatile unsigned int*)(0x427E0760UL)) +#define bFM3_EXBUS_TIM6_WWEC1 *((volatile unsigned int*)(0x427E0764UL)) +#define bFM3_EXBUS_TIM6_WWEC2 *((volatile unsigned int*)(0x427E0768UL)) +#define bFM3_EXBUS_TIM6_WWEC3 *((volatile unsigned int*)(0x427E076CUL)) +#define bFM3_EXBUS_TIM6_WIDLC0 *((volatile unsigned int*)(0x427E0770UL)) +#define bFM3_EXBUS_TIM6_WIDLC1 *((volatile unsigned int*)(0x427E0774UL)) +#define bFM3_EXBUS_TIM6_WIDLC2 *((volatile unsigned int*)(0x427E0778UL)) +#define bFM3_EXBUS_TIM6_WIDLC3 *((volatile unsigned int*)(0x427E077CUL)) +#define bFM3_EXBUS_TIM7_RACC0 *((volatile unsigned int*)(0x427E0780UL)) +#define bFM3_EXBUS_TIM7_RACC1 *((volatile unsigned int*)(0x427E0784UL)) +#define bFM3_EXBUS_TIM7_RACC2 *((volatile unsigned int*)(0x427E0788UL)) +#define bFM3_EXBUS_TIM7_RACC3 *((volatile unsigned int*)(0x427E078CUL)) +#define bFM3_EXBUS_TIM7_RADC0 *((volatile unsigned int*)(0x427E0790UL)) +#define bFM3_EXBUS_TIM7_RADC1 *((volatile unsigned int*)(0x427E0794UL)) +#define bFM3_EXBUS_TIM7_RADC2 *((volatile unsigned int*)(0x427E0798UL)) +#define bFM3_EXBUS_TIM7_RADC3 *((volatile unsigned int*)(0x427E079CUL)) +#define bFM3_EXBUS_TIM7_FRADC0 *((volatile unsigned int*)(0x427E07A0UL)) +#define bFM3_EXBUS_TIM7_FRADC1 *((volatile unsigned int*)(0x427E07A4UL)) +#define bFM3_EXBUS_TIM7_FRADC2 *((volatile unsigned int*)(0x427E07A8UL)) +#define bFM3_EXBUS_TIM7_FRADC3 *((volatile unsigned int*)(0x427E07ACUL)) +#define bFM3_EXBUS_TIM7_RIDLC0 *((volatile unsigned int*)(0x427E07B0UL)) +#define bFM3_EXBUS_TIM7_RIDLC1 *((volatile unsigned int*)(0x427E07B4UL)) +#define bFM3_EXBUS_TIM7_RIDLC2 *((volatile unsigned int*)(0x427E07B8UL)) +#define bFM3_EXBUS_TIM7_RIDLC3 *((volatile unsigned int*)(0x427E07BCUL)) +#define bFM3_EXBUS_TIM7_WACC0 *((volatile unsigned int*)(0x427E07C0UL)) +#define bFM3_EXBUS_TIM7_WACC1 *((volatile unsigned int*)(0x427E07C4UL)) +#define bFM3_EXBUS_TIM7_WACC2 *((volatile unsigned int*)(0x427E07C8UL)) +#define bFM3_EXBUS_TIM7_WACC3 *((volatile unsigned int*)(0x427E07CCUL)) +#define bFM3_EXBUS_TIM7_WADC0 *((volatile unsigned int*)(0x427E07D0UL)) +#define bFM3_EXBUS_TIM7_WADC1 *((volatile unsigned int*)(0x427E07D4UL)) +#define bFM3_EXBUS_TIM7_WADC2 *((volatile unsigned int*)(0x427E07D8UL)) +#define bFM3_EXBUS_TIM7_WADC3 *((volatile unsigned int*)(0x427E07DCUL)) +#define bFM3_EXBUS_TIM7_WWEC0 *((volatile unsigned int*)(0x427E07E0UL)) +#define bFM3_EXBUS_TIM7_WWEC1 *((volatile unsigned int*)(0x427E07E4UL)) +#define bFM3_EXBUS_TIM7_WWEC2 *((volatile unsigned int*)(0x427E07E8UL)) +#define bFM3_EXBUS_TIM7_WWEC3 *((volatile unsigned int*)(0x427E07ECUL)) +#define bFM3_EXBUS_TIM7_WIDLC0 *((volatile unsigned int*)(0x427E07F0UL)) +#define bFM3_EXBUS_TIM7_WIDLC1 *((volatile unsigned int*)(0x427E07F4UL)) +#define bFM3_EXBUS_TIM7_WIDLC2 *((volatile unsigned int*)(0x427E07F8UL)) +#define bFM3_EXBUS_TIM7_WIDLC3 *((volatile unsigned int*)(0x427E07FCUL)) +#define bFM3_EXBUS_AREA0_ADDR0 *((volatile unsigned int*)(0x427E0800UL)) +#define bFM3_EXBUS_AREA0_ADDR1 *((volatile unsigned int*)(0x427E0804UL)) +#define bFM3_EXBUS_AREA0_ADDR2 *((volatile unsigned int*)(0x427E0808UL)) +#define bFM3_EXBUS_AREA0_ADDR3 *((volatile unsigned int*)(0x427E080CUL)) +#define bFM3_EXBUS_AREA0_ADDR4 *((volatile unsigned int*)(0x427E0810UL)) +#define bFM3_EXBUS_AREA0_ADDR5 *((volatile unsigned int*)(0x427E0814UL)) +#define bFM3_EXBUS_AREA0_ADDR6 *((volatile unsigned int*)(0x427E0818UL)) +#define bFM3_EXBUS_AREA0_ADDR7 *((volatile unsigned int*)(0x427E081CUL)) +#define bFM3_EXBUS_AREA0_MASK0 *((volatile unsigned int*)(0x427E0840UL)) +#define bFM3_EXBUS_AREA0_MASK1 *((volatile unsigned int*)(0x427E0844UL)) +#define bFM3_EXBUS_AREA0_MASK2 *((volatile unsigned int*)(0x427E0848UL)) +#define bFM3_EXBUS_AREA0_MASK3 *((volatile unsigned int*)(0x427E084CUL)) +#define bFM3_EXBUS_AREA0_MASK4 *((volatile unsigned int*)(0x427E0850UL)) +#define bFM3_EXBUS_AREA0_MASK5 *((volatile unsigned int*)(0x427E0854UL)) +#define bFM3_EXBUS_AREA0_MASK6 *((volatile unsigned int*)(0x427E0858UL)) +#define bFM3_EXBUS_AREA1_ADDR0 *((volatile unsigned int*)(0x427E0880UL)) +#define bFM3_EXBUS_AREA1_ADDR1 *((volatile unsigned int*)(0x427E0884UL)) +#define bFM3_EXBUS_AREA1_ADDR2 *((volatile unsigned int*)(0x427E0888UL)) +#define bFM3_EXBUS_AREA1_ADDR3 *((volatile unsigned int*)(0x427E088CUL)) +#define bFM3_EXBUS_AREA1_ADDR4 *((volatile unsigned int*)(0x427E0890UL)) +#define bFM3_EXBUS_AREA1_ADDR5 *((volatile unsigned int*)(0x427E0894UL)) +#define bFM3_EXBUS_AREA1_ADDR6 *((volatile unsigned int*)(0x427E0898UL)) +#define bFM3_EXBUS_AREA1_ADDR7 *((volatile unsigned int*)(0x427E089CUL)) +#define bFM3_EXBUS_AREA1_MASK0 *((volatile unsigned int*)(0x427E08C0UL)) +#define bFM3_EXBUS_AREA1_MASK1 *((volatile unsigned int*)(0x427E08C4UL)) +#define bFM3_EXBUS_AREA1_MASK2 *((volatile unsigned int*)(0x427E08C8UL)) +#define bFM3_EXBUS_AREA1_MASK3 *((volatile unsigned int*)(0x427E08CCUL)) +#define bFM3_EXBUS_AREA1_MASK4 *((volatile unsigned int*)(0x427E08D0UL)) +#define bFM3_EXBUS_AREA1_MASK5 *((volatile unsigned int*)(0x427E08D4UL)) +#define bFM3_EXBUS_AREA1_MASK6 *((volatile unsigned int*)(0x427E08D8UL)) +#define bFM3_EXBUS_AREA2_ADDR0 *((volatile unsigned int*)(0x427E0900UL)) +#define bFM3_EXBUS_AREA2_ADDR1 *((volatile unsigned int*)(0x427E0904UL)) +#define bFM3_EXBUS_AREA2_ADDR2 *((volatile unsigned int*)(0x427E0908UL)) +#define bFM3_EXBUS_AREA2_ADDR3 *((volatile unsigned int*)(0x427E090CUL)) +#define bFM3_EXBUS_AREA2_ADDR4 *((volatile unsigned int*)(0x427E0910UL)) +#define bFM3_EXBUS_AREA2_ADDR5 *((volatile unsigned int*)(0x427E0914UL)) +#define bFM3_EXBUS_AREA2_ADDR6 *((volatile unsigned int*)(0x427E0918UL)) +#define bFM3_EXBUS_AREA2_ADDR7 *((volatile unsigned int*)(0x427E091CUL)) +#define bFM3_EXBUS_AREA2_MASK0 *((volatile unsigned int*)(0x427E0940UL)) +#define bFM3_EXBUS_AREA2_MASK1 *((volatile unsigned int*)(0x427E0944UL)) +#define bFM3_EXBUS_AREA2_MASK2 *((volatile unsigned int*)(0x427E0948UL)) +#define bFM3_EXBUS_AREA2_MASK3 *((volatile unsigned int*)(0x427E094CUL)) +#define bFM3_EXBUS_AREA2_MASK4 *((volatile unsigned int*)(0x427E0950UL)) +#define bFM3_EXBUS_AREA2_MASK5 *((volatile unsigned int*)(0x427E0954UL)) +#define bFM3_EXBUS_AREA2_MASK6 *((volatile unsigned int*)(0x427E0958UL)) +#define bFM3_EXBUS_AREA3_ADDR0 *((volatile unsigned int*)(0x427E0980UL)) +#define bFM3_EXBUS_AREA3_ADDR1 *((volatile unsigned int*)(0x427E0984UL)) +#define bFM3_EXBUS_AREA3_ADDR2 *((volatile unsigned int*)(0x427E0988UL)) +#define bFM3_EXBUS_AREA3_ADDR3 *((volatile unsigned int*)(0x427E098CUL)) +#define bFM3_EXBUS_AREA3_ADDR4 *((volatile unsigned int*)(0x427E0990UL)) +#define bFM3_EXBUS_AREA3_ADDR5 *((volatile unsigned int*)(0x427E0994UL)) +#define bFM3_EXBUS_AREA3_ADDR6 *((volatile unsigned int*)(0x427E0998UL)) +#define bFM3_EXBUS_AREA3_ADDR7 *((volatile unsigned int*)(0x427E099CUL)) +#define bFM3_EXBUS_AREA3_MASK0 *((volatile unsigned int*)(0x427E09C0UL)) +#define bFM3_EXBUS_AREA3_MASK1 *((volatile unsigned int*)(0x427E09C4UL)) +#define bFM3_EXBUS_AREA3_MASK2 *((volatile unsigned int*)(0x427E09C8UL)) +#define bFM3_EXBUS_AREA3_MASK3 *((volatile unsigned int*)(0x427E09CCUL)) +#define bFM3_EXBUS_AREA3_MASK4 *((volatile unsigned int*)(0x427E09D0UL)) +#define bFM3_EXBUS_AREA3_MASK5 *((volatile unsigned int*)(0x427E09D4UL)) +#define bFM3_EXBUS_AREA3_MASK6 *((volatile unsigned int*)(0x427E09D8UL)) +#define bFM3_EXBUS_AREA4_ADDR0 *((volatile unsigned int*)(0x427E0A00UL)) +#define bFM3_EXBUS_AREA4_ADDR1 *((volatile unsigned int*)(0x427E0A04UL)) +#define bFM3_EXBUS_AREA4_ADDR2 *((volatile unsigned int*)(0x427E0A08UL)) +#define bFM3_EXBUS_AREA4_ADDR3 *((volatile unsigned int*)(0x427E0A0CUL)) +#define bFM3_EXBUS_AREA4_ADDR4 *((volatile unsigned int*)(0x427E0A10UL)) +#define bFM3_EXBUS_AREA4_ADDR5 *((volatile unsigned int*)(0x427E0A14UL)) +#define bFM3_EXBUS_AREA4_ADDR6 *((volatile unsigned int*)(0x427E0A18UL)) +#define bFM3_EXBUS_AREA4_ADDR7 *((volatile unsigned int*)(0x427E0A1CUL)) +#define bFM3_EXBUS_AREA4_MASK0 *((volatile unsigned int*)(0x427E0A40UL)) +#define bFM3_EXBUS_AREA4_MASK1 *((volatile unsigned int*)(0x427E0A44UL)) +#define bFM3_EXBUS_AREA4_MASK2 *((volatile unsigned int*)(0x427E0A48UL)) +#define bFM3_EXBUS_AREA4_MASK3 *((volatile unsigned int*)(0x427E0A4CUL)) +#define bFM3_EXBUS_AREA4_MASK4 *((volatile unsigned int*)(0x427E0A50UL)) +#define bFM3_EXBUS_AREA4_MASK5 *((volatile unsigned int*)(0x427E0A54UL)) +#define bFM3_EXBUS_AREA4_MASK6 *((volatile unsigned int*)(0x427E0A58UL)) +#define bFM3_EXBUS_AREA5_ADDR0 *((volatile unsigned int*)(0x427E0A80UL)) +#define bFM3_EXBUS_AREA5_ADDR1 *((volatile unsigned int*)(0x427E0A84UL)) +#define bFM3_EXBUS_AREA5_ADDR2 *((volatile unsigned int*)(0x427E0A88UL)) +#define bFM3_EXBUS_AREA5_ADDR3 *((volatile unsigned int*)(0x427E0A8CUL)) +#define bFM3_EXBUS_AREA5_ADDR4 *((volatile unsigned int*)(0x427E0A90UL)) +#define bFM3_EXBUS_AREA5_ADDR5 *((volatile unsigned int*)(0x427E0A94UL)) +#define bFM3_EXBUS_AREA5_ADDR6 *((volatile unsigned int*)(0x427E0A98UL)) +#define bFM3_EXBUS_AREA5_ADDR7 *((volatile unsigned int*)(0x427E0A9CUL)) +#define bFM3_EXBUS_AREA5_MASK0 *((volatile unsigned int*)(0x427E0AC0UL)) +#define bFM3_EXBUS_AREA5_MASK1 *((volatile unsigned int*)(0x427E0AC4UL)) +#define bFM3_EXBUS_AREA5_MASK2 *((volatile unsigned int*)(0x427E0AC8UL)) +#define bFM3_EXBUS_AREA5_MASK3 *((volatile unsigned int*)(0x427E0ACCUL)) +#define bFM3_EXBUS_AREA5_MASK4 *((volatile unsigned int*)(0x427E0AD0UL)) +#define bFM3_EXBUS_AREA5_MASK5 *((volatile unsigned int*)(0x427E0AD4UL)) +#define bFM3_EXBUS_AREA5_MASK6 *((volatile unsigned int*)(0x427E0AD8UL)) +#define bFM3_EXBUS_AREA6_ADDR0 *((volatile unsigned int*)(0x427E0B00UL)) +#define bFM3_EXBUS_AREA6_ADDR1 *((volatile unsigned int*)(0x427E0B04UL)) +#define bFM3_EXBUS_AREA6_ADDR2 *((volatile unsigned int*)(0x427E0B08UL)) +#define bFM3_EXBUS_AREA6_ADDR3 *((volatile unsigned int*)(0x427E0B0CUL)) +#define bFM3_EXBUS_AREA6_ADDR4 *((volatile unsigned int*)(0x427E0B10UL)) +#define bFM3_EXBUS_AREA6_ADDR5 *((volatile unsigned int*)(0x427E0B14UL)) +#define bFM3_EXBUS_AREA6_ADDR6 *((volatile unsigned int*)(0x427E0B18UL)) +#define bFM3_EXBUS_AREA6_ADDR7 *((volatile unsigned int*)(0x427E0B1CUL)) +#define bFM3_EXBUS_AREA6_MASK0 *((volatile unsigned int*)(0x427E0B40UL)) +#define bFM3_EXBUS_AREA6_MASK1 *((volatile unsigned int*)(0x427E0B44UL)) +#define bFM3_EXBUS_AREA6_MASK2 *((volatile unsigned int*)(0x427E0B48UL)) +#define bFM3_EXBUS_AREA6_MASK3 *((volatile unsigned int*)(0x427E0B4CUL)) +#define bFM3_EXBUS_AREA6_MASK4 *((volatile unsigned int*)(0x427E0B50UL)) +#define bFM3_EXBUS_AREA6_MASK5 *((volatile unsigned int*)(0x427E0B54UL)) +#define bFM3_EXBUS_AREA6_MASK6 *((volatile unsigned int*)(0x427E0B58UL)) +#define bFM3_EXBUS_AREA7_ADDR0 *((volatile unsigned int*)(0x427E0B80UL)) +#define bFM3_EXBUS_AREA7_ADDR1 *((volatile unsigned int*)(0x427E0B84UL)) +#define bFM3_EXBUS_AREA7_ADDR2 *((volatile unsigned int*)(0x427E0B88UL)) +#define bFM3_EXBUS_AREA7_ADDR3 *((volatile unsigned int*)(0x427E0B8CUL)) +#define bFM3_EXBUS_AREA7_ADDR4 *((volatile unsigned int*)(0x427E0B90UL)) +#define bFM3_EXBUS_AREA7_ADDR5 *((volatile unsigned int*)(0x427E0B94UL)) +#define bFM3_EXBUS_AREA7_ADDR6 *((volatile unsigned int*)(0x427E0B98UL)) +#define bFM3_EXBUS_AREA7_ADDR7 *((volatile unsigned int*)(0x427E0B9CUL)) +#define bFM3_EXBUS_AREA7_MASK0 *((volatile unsigned int*)(0x427E0BC0UL)) +#define bFM3_EXBUS_AREA7_MASK1 *((volatile unsigned int*)(0x427E0BC4UL)) +#define bFM3_EXBUS_AREA7_MASK2 *((volatile unsigned int*)(0x427E0BC8UL)) +#define bFM3_EXBUS_AREA7_MASK3 *((volatile unsigned int*)(0x427E0BCCUL)) +#define bFM3_EXBUS_AREA7_MASK4 *((volatile unsigned int*)(0x427E0BD0UL)) +#define bFM3_EXBUS_AREA7_MASK5 *((volatile unsigned int*)(0x427E0BD4UL)) +#define bFM3_EXBUS_AREA7_MASK6 *((volatile unsigned int*)(0x427E0BD8UL)) + +/* USB channel 0 registers */ +#define bFM3_USB0_HCNT_HOST *((volatile unsigned int*)(0x42842000UL)) +#define bFM3_USB0_HCNT_URST *((volatile unsigned int*)(0x42842004UL)) +#define bFM3_USB0_HCNT_SOFIRE *((volatile unsigned int*)(0x42842008UL)) +#define bFM3_USB0_HCNT_DIRE *((volatile unsigned int*)(0x4284200CUL)) +#define bFM3_USB0_HCNT_CNNIRE *((volatile unsigned int*)(0x42842010UL)) +#define bFM3_USB0_HCNT_CMPIRE *((volatile unsigned int*)(0x42842014UL)) +#define bFM3_USB0_HCNT_URIRE *((volatile unsigned int*)(0x42842018UL)) +#define bFM3_USB0_HCNT_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) +#define bFM3_USB0_HCNT_RETRY *((volatile unsigned int*)(0x42842020UL)) +#define bFM3_USB0_HCNT_CANCEL *((volatile unsigned int*)(0x42842024UL)) +#define bFM3_USB0_HCNT_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) +#define bFM3_USB0_HCNT0_HOST *((volatile unsigned int*)(0x42842000UL)) +#define bFM3_USB0_HCNT0_URST *((volatile unsigned int*)(0x42842004UL)) +#define bFM3_USB0_HCNT0_SOFIRE *((volatile unsigned int*)(0x42842008UL)) +#define bFM3_USB0_HCNT0_DIRE *((volatile unsigned int*)(0x4284200CUL)) +#define bFM3_USB0_HCNT0_CNNIRE *((volatile unsigned int*)(0x42842010UL)) +#define bFM3_USB0_HCNT0_CMPIRE *((volatile unsigned int*)(0x42842014UL)) +#define bFM3_USB0_HCNT0_URIRE *((volatile unsigned int*)(0x42842018UL)) +#define bFM3_USB0_HCNT0_RWKIRE *((volatile unsigned int*)(0x4284201CUL)) +#define bFM3_USB0_HCNT1_RETRY *((volatile unsigned int*)(0x42842020UL)) +#define bFM3_USB0_HCNT1_CANCEL *((volatile unsigned int*)(0x42842024UL)) +#define bFM3_USB0_HCNT1_SOFSTEP *((volatile unsigned int*)(0x42842028UL)) +#define bFM3_USB0_HIRQ_SOFIRQ *((volatile unsigned int*)(0x42842080UL)) +#define bFM3_USB0_HIRQ_DIRQ *((volatile unsigned int*)(0x42842084UL)) +#define bFM3_USB0_HIRQ_CNNIRQ *((volatile unsigned int*)(0x42842088UL)) +#define bFM3_USB0_HIRQ_CMPIRQ *((volatile unsigned int*)(0x4284208CUL)) +#define bFM3_USB0_HIRQ_URIRQ *((volatile unsigned int*)(0x42842090UL)) +#define bFM3_USB0_HIRQ_RWKIRQ *((volatile unsigned int*)(0x42842094UL)) +#define bFM3_USB0_HIRQ_TCAN *((volatile unsigned int*)(0x4284209CUL)) +#define bFM3_USB0_HERR_HS0 *((volatile unsigned int*)(0x428420A0UL)) +#define bFM3_USB0_HERR_HS1 *((volatile unsigned int*)(0x428420A4UL)) +#define bFM3_USB0_HERR_STUFF *((volatile unsigned int*)(0x428420A8UL)) +#define bFM3_USB0_HERR_TGERR *((volatile unsigned int*)(0x428420ACUL)) +#define bFM3_USB0_HERR_CRC *((volatile unsigned int*)(0x428420B0UL)) +#define bFM3_USB0_HERR_TOUT *((volatile unsigned int*)(0x428420B4UL)) +#define bFM3_USB0_HERR_RERR *((volatile unsigned int*)(0x428420B8UL)) +#define bFM3_USB0_HERR_LSTOF *((volatile unsigned int*)(0x428420BCUL)) +#define bFM3_USB0_HSTATE_CSTAT *((volatile unsigned int*)(0x42842100UL)) +#define bFM3_USB0_HSTATE_TMODE *((volatile unsigned int*)(0x42842104UL)) +#define bFM3_USB0_HSTATE_SUSP *((volatile unsigned int*)(0x42842108UL)) +#define bFM3_USB0_HSTATE_SOFBUSY *((volatile unsigned int*)(0x4284210CUL)) +#define bFM3_USB0_HSTATE_CLKSEL *((volatile unsigned int*)(0x42842110UL)) +#define bFM3_USB0_HSTATE_ALIVE *((volatile unsigned int*)(0x42842114UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP0 *((volatile unsigned int*)(0x42842120UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP1 *((volatile unsigned int*)(0x42842124UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP2 *((volatile unsigned int*)(0x42842128UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP3 *((volatile unsigned int*)(0x4284212CUL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP4 *((volatile unsigned int*)(0x42842130UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP5 *((volatile unsigned int*)(0x42842134UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP6 *((volatile unsigned int*)(0x42842138UL)) +#define bFM3_USB0_HFCOMP_FRAMECOMP7 *((volatile unsigned int*)(0x4284213CUL)) +#define bFM3_USB0_HRTIMER_RTIMER0 *((volatile unsigned int*)(0x42842180UL)) +#define bFM3_USB0_HRTIMER_RTIMER1 *((volatile unsigned int*)(0x42842184UL)) +#define bFM3_USB0_HRTIMER_RTIMER2 *((volatile unsigned int*)(0x42842188UL)) +#define bFM3_USB0_HRTIMER_RTIMER3 *((volatile unsigned int*)(0x4284218CUL)) +#define bFM3_USB0_HRTIMER_RTIMER4 *((volatile unsigned int*)(0x42842190UL)) +#define bFM3_USB0_HRTIMER_RTIMER5 *((volatile unsigned int*)(0x42842194UL)) +#define bFM3_USB0_HRTIMER_RTIMER6 *((volatile unsigned int*)(0x42842198UL)) +#define bFM3_USB0_HRTIMER_RTIMER7 *((volatile unsigned int*)(0x4284219CUL)) +#define bFM3_USB0_HRTIMER_RTIMER8 *((volatile unsigned int*)(0x428421A0UL)) +#define bFM3_USB0_HRTIMER_RTIMER9 *((volatile unsigned int*)(0x428421A4UL)) +#define bFM3_USB0_HRTIMER_RTIMER10 *((volatile unsigned int*)(0x428421A8UL)) +#define bFM3_USB0_HRTIMER_RTIMER11 *((volatile unsigned int*)(0x428421ACUL)) +#define bFM3_USB0_HRTIMER_RTIMER12 *((volatile unsigned int*)(0x428421B0UL)) +#define bFM3_USB0_HRTIMER_RTIMER13 *((volatile unsigned int*)(0x428421B4UL)) +#define bFM3_USB0_HRTIMER_RTIMER14 *((volatile unsigned int*)(0x428421B8UL)) +#define bFM3_USB0_HRTIMER_RTIMER15 *((volatile unsigned int*)(0x428421BCUL)) +#define bFM3_USB0_HRTIMER0_RTIMER00 *((volatile unsigned int*)(0x42842180UL)) +#define bFM3_USB0_HRTIMER0_RTIMER01 *((volatile unsigned int*)(0x42842184UL)) +#define bFM3_USB0_HRTIMER0_RTIMER02 *((volatile unsigned int*)(0x42842188UL)) +#define bFM3_USB0_HRTIMER0_RTIMER03 *((volatile unsigned int*)(0x4284218CUL)) +#define bFM3_USB0_HRTIMER0_RTIMER04 *((volatile unsigned int*)(0x42842190UL)) +#define bFM3_USB0_HRTIMER0_RTIMER05 *((volatile unsigned int*)(0x42842194UL)) +#define bFM3_USB0_HRTIMER0_RTIMER06 *((volatile unsigned int*)(0x42842198UL)) +#define bFM3_USB0_HRTIMER0_RTIMER07 *((volatile unsigned int*)(0x4284219CUL)) +#define bFM3_USB0_HRTIMER1_RTIMER10 *((volatile unsigned int*)(0x428421A0UL)) +#define bFM3_USB0_HRTIMER1_RTIMER11 *((volatile unsigned int*)(0x428421A4UL)) +#define bFM3_USB0_HRTIMER1_RTIMER12 *((volatile unsigned int*)(0x428421A8UL)) +#define bFM3_USB0_HRTIMER1_RTIMER13 *((volatile unsigned int*)(0x428421ACUL)) +#define bFM3_USB0_HRTIMER1_RTIMER14 *((volatile unsigned int*)(0x428421B0UL)) +#define bFM3_USB0_HRTIMER1_RTIMER15 *((volatile unsigned int*)(0x428421B4UL)) +#define bFM3_USB0_HRTIMER1_RTIMER16 *((volatile unsigned int*)(0x428421B8UL)) +#define bFM3_USB0_HRTIMER1_RTIMER17 *((volatile unsigned int*)(0x428421BCUL)) +#define bFM3_USB0_HRTIMER2_RTIMER20 *((volatile unsigned int*)(0x42842200UL)) +#define bFM3_USB0_HRTIMER2_RTIMER21 *((volatile unsigned int*)(0x42842204UL)) +#define bFM3_USB0_HRTIMER2_RTIMER22 *((volatile unsigned int*)(0x42842208UL)) +#define bFM3_USB0_HADR_ADDRESS0 *((volatile unsigned int*)(0x42842220UL)) +#define bFM3_USB0_HADR_ADDRESS1 *((volatile unsigned int*)(0x42842224UL)) +#define bFM3_USB0_HADR_ADDRESS2 *((volatile unsigned int*)(0x42842228UL)) +#define bFM3_USB0_HADR_ADDRESS3 *((volatile unsigned int*)(0x4284222CUL)) +#define bFM3_USB0_HADR_ADDRESS4 *((volatile unsigned int*)(0x42842230UL)) +#define bFM3_USB0_HADR_ADDRESS5 *((volatile unsigned int*)(0x42842234UL)) +#define bFM3_USB0_HADR_ADDRESS6 *((volatile unsigned int*)(0x42842238UL)) +#define bFM3_USB0_HEOF_EOF0 *((volatile unsigned int*)(0x42842280UL)) +#define bFM3_USB0_HEOF_EOF1 *((volatile unsigned int*)(0x42842284UL)) +#define bFM3_USB0_HEOF_EOF2 *((volatile unsigned int*)(0x42842288UL)) +#define bFM3_USB0_HEOF_EOF3 *((volatile unsigned int*)(0x4284228CUL)) +#define bFM3_USB0_HEOF_EOF4 *((volatile unsigned int*)(0x42842290UL)) +#define bFM3_USB0_HEOF_EOF5 *((volatile unsigned int*)(0x42842294UL)) +#define bFM3_USB0_HEOF_EOF6 *((volatile unsigned int*)(0x42842298UL)) +#define bFM3_USB0_HEOF_EOF7 *((volatile unsigned int*)(0x4284229CUL)) +#define bFM3_USB0_HEOF_EOF8 *((volatile unsigned int*)(0x428422A0UL)) +#define bFM3_USB0_HEOF_EOF9 *((volatile unsigned int*)(0x428422A4UL)) +#define bFM3_USB0_HEOF_EOF10 *((volatile unsigned int*)(0x428422A8UL)) +#define bFM3_USB0_HEOF_EOF11 *((volatile unsigned int*)(0x428422ACUL)) +#define bFM3_USB0_HEOF_EOF12 *((volatile unsigned int*)(0x428422B0UL)) +#define bFM3_USB0_HEOF_EOF13 *((volatile unsigned int*)(0x428422B4UL)) +#define bFM3_USB0_HEOF_EOF14 *((volatile unsigned int*)(0x428422B8UL)) +#define bFM3_USB0_HEOF_EOF15 *((volatile unsigned int*)(0x428422BCUL)) +#define bFM3_USB0_HEOF0_EOF00 *((volatile unsigned int*)(0x42842280UL)) +#define bFM3_USB0_HEOF0_EOF01 *((volatile unsigned int*)(0x42842284UL)) +#define bFM3_USB0_HEOF0_EOF02 *((volatile unsigned int*)(0x42842288UL)) +#define bFM3_USB0_HEOF0_EOF03 *((volatile unsigned int*)(0x4284228CUL)) +#define bFM3_USB0_HEOF0_EOF04 *((volatile unsigned int*)(0x42842290UL)) +#define bFM3_USB0_HEOF0_EOF05 *((volatile unsigned int*)(0x42842294UL)) +#define bFM3_USB0_HEOF0_EOF06 *((volatile unsigned int*)(0x42842298UL)) +#define bFM3_USB0_HEOF0_EOF07 *((volatile unsigned int*)(0x4284229CUL)) +#define bFM3_USB0_HEOF1_EOF10 *((volatile unsigned int*)(0x428422A0UL)) +#define bFM3_USB0_HEOF1_EOF11 *((volatile unsigned int*)(0x428422A4UL)) +#define bFM3_USB0_HEOF1_EOF12 *((volatile unsigned int*)(0x428422A8UL)) +#define bFM3_USB0_HEOF1_EOF13 *((volatile unsigned int*)(0x428422ACUL)) +#define bFM3_USB0_HEOF1_EOF14 *((volatile unsigned int*)(0x428422B0UL)) +#define bFM3_USB0_HEOF1_EOF15 *((volatile unsigned int*)(0x428422B4UL)) +#define bFM3_USB0_HFRAME_FRAME0 *((volatile unsigned int*)(0x42842300UL)) +#define bFM3_USB0_HFRAME_FRAME1 *((volatile unsigned int*)(0x42842304UL)) +#define bFM3_USB0_HFRAME_FRAME2 *((volatile unsigned int*)(0x42842308UL)) +#define bFM3_USB0_HFRAME_FRAME3 *((volatile unsigned int*)(0x4284230CUL)) +#define bFM3_USB0_HFRAME_FRAME4 *((volatile unsigned int*)(0x42842310UL)) +#define bFM3_USB0_HFRAME_FRAME5 *((volatile unsigned int*)(0x42842314UL)) +#define bFM3_USB0_HFRAME_FRAME6 *((volatile unsigned int*)(0x42842318UL)) +#define bFM3_USB0_HFRAME_FRAME7 *((volatile unsigned int*)(0x4284231CUL)) +#define bFM3_USB0_HFRAME_FRAME8 *((volatile unsigned int*)(0x42842320UL)) +#define bFM3_USB0_HFRAME_FRAME9 *((volatile unsigned int*)(0x42842324UL)) +#define bFM3_USB0_HFRAME_FRAME10 *((volatile unsigned int*)(0x42842328UL)) +#define bFM3_USB0_HFRAME0_FRAME00 *((volatile unsigned int*)(0x42842300UL)) +#define bFM3_USB0_HFRAME0_FRAME01 *((volatile unsigned int*)(0x42842304UL)) +#define bFM3_USB0_HFRAME0_FRAME02 *((volatile unsigned int*)(0x42842308UL)) +#define bFM3_USB0_HFRAME0_FRAME03 *((volatile unsigned int*)(0x4284230CUL)) +#define bFM3_USB0_HFRAME0_FRAME04 *((volatile unsigned int*)(0x42842310UL)) +#define bFM3_USB0_HFRAME0_FRAME05 *((volatile unsigned int*)(0x42842314UL)) +#define bFM3_USB0_HFRAME0_FRAME06 *((volatile unsigned int*)(0x42842318UL)) +#define bFM3_USB0_HFRAME0_FRAME07 *((volatile unsigned int*)(0x4284231CUL)) +#define bFM3_USB0_HFRAME1_FRAME10 *((volatile unsigned int*)(0x42842320UL)) +#define bFM3_USB0_HFRAME1_FRAME11 *((volatile unsigned int*)(0x42842324UL)) +#define bFM3_USB0_HFRAME1_FRAME12 *((volatile unsigned int*)(0x42842328UL)) +#define bFM3_USB0_HFRAME1_FRAME13 *((volatile unsigned int*)(0x4284232CUL)) +#define bFM3_USB0_HTOKEN_ENDPT0 *((volatile unsigned int*)(0x42842380UL)) +#define bFM3_USB0_HTOKEN_ENDPT1 *((volatile unsigned int*)(0x42842384UL)) +#define bFM3_USB0_HTOKEN_ENDPT2 *((volatile unsigned int*)(0x42842388UL)) +#define bFM3_USB0_HTOKEN_ENDPT3 *((volatile unsigned int*)(0x4284238CUL)) +#define bFM3_USB0_HTOKEN_TKNEN0 *((volatile unsigned int*)(0x42842390UL)) +#define bFM3_USB0_HTOKEN_TKNEN1 *((volatile unsigned int*)(0x42842394UL)) +#define bFM3_USB0_HTOKEN_TKNEN2 *((volatile unsigned int*)(0x42842398UL)) +#define bFM3_USB0_HTOKEN_TGGL *((volatile unsigned int*)(0x4284239CUL)) +#define bFM3_USB0_UDCC_PWC *((volatile unsigned int*)(0x42842400UL)) +#define bFM3_USB0_UDCC_RFBK *((volatile unsigned int*)(0x42842404UL)) +#define bFM3_USB0_UDCC_STALCLREN *((volatile unsigned int*)(0x4284240CUL)) +#define bFM3_USB0_UDCC_USTP *((volatile unsigned int*)(0x42842410UL)) +#define bFM3_USB0_UDCC_HCONX *((volatile unsigned int*)(0x42842414UL)) +#define bFM3_USB0_UDCC_RESUM *((volatile unsigned int*)(0x42842418UL)) +#define bFM3_USB0_UDCC_RST *((volatile unsigned int*)(0x4284241CUL)) +#define bFM3_USB0_EP0C_PKS00 *((volatile unsigned int*)(0x42842480UL)) +#define bFM3_USB0_EP0C_PKS01 *((volatile unsigned int*)(0x42842484UL)) +#define bFM3_USB0_EP0C_PKS02 *((volatile unsigned int*)(0x42842488UL)) +#define bFM3_USB0_EP0C_PKS03 *((volatile unsigned int*)(0x4284248CUL)) +#define bFM3_USB0_EP0C_PKS04 *((volatile unsigned int*)(0x42842490UL)) +#define bFM3_USB0_EP0C_PKS05 *((volatile unsigned int*)(0x42842494UL)) +#define bFM3_USB0_EP0C_PKS06 *((volatile unsigned int*)(0x42842498UL)) +#define bFM3_USB0_EP0C_STAL *((volatile unsigned int*)(0x428424A4UL)) +#define bFM3_USB0_EP1C_PKS10 *((volatile unsigned int*)(0x42842500UL)) +#define bFM3_USB0_EP1C_PKS11 *((volatile unsigned int*)(0x42842504UL)) +#define bFM3_USB0_EP1C_PKS12 *((volatile unsigned int*)(0x42842508UL)) +#define bFM3_USB0_EP1C_PKS13 *((volatile unsigned int*)(0x4284250CUL)) +#define bFM3_USB0_EP1C_PKS14 *((volatile unsigned int*)(0x42842510UL)) +#define bFM3_USB0_EP1C_PKS15 *((volatile unsigned int*)(0x42842514UL)) +#define bFM3_USB0_EP1C_PKS16 *((volatile unsigned int*)(0x42842518UL)) +#define bFM3_USB0_EP1C_PKS17 *((volatile unsigned int*)(0x4284251CUL)) +#define bFM3_USB0_EP1C_PSK18 *((volatile unsigned int*)(0x42842520UL)) +#define bFM3_USB0_EP1C_STAL *((volatile unsigned int*)(0x42842524UL)) +#define bFM3_USB0_EP1C_NULE *((volatile unsigned int*)(0x42842528UL)) +#define bFM3_USB0_EP1C_DMAE *((volatile unsigned int*)(0x4284252CUL)) +#define bFM3_USB0_EP1C_DIR *((volatile unsigned int*)(0x42842530UL)) +#define bFM3_USB0_EP1C_TYPE0 *((volatile unsigned int*)(0x42842534UL)) +#define bFM3_USB0_EP1C_TYPE1 *((volatile unsigned int*)(0x42842538UL)) +#define bFM3_USB0_EP1C_EPEN *((volatile unsigned int*)(0x4284253CUL)) +#define bFM3_USB0_EP2C_PKS20 *((volatile unsigned int*)(0x42842580UL)) +#define bFM3_USB0_EP2C_PKS21 *((volatile unsigned int*)(0x42842584UL)) +#define bFM3_USB0_EP2C_PKS22 *((volatile unsigned int*)(0x42842588UL)) +#define bFM3_USB0_EP2C_PKS23 *((volatile unsigned int*)(0x4284258CUL)) +#define bFM3_USB0_EP2C_PKS24 *((volatile unsigned int*)(0x42842590UL)) +#define bFM3_USB0_EP2C_PKS25 *((volatile unsigned int*)(0x42842594UL)) +#define bFM3_USB0_EP2C_PKS26 *((volatile unsigned int*)(0x42842598UL)) +#define bFM3_USB0_EP2C_STAL *((volatile unsigned int*)(0x428425A4UL)) +#define bFM3_USB0_EP2C_NULE *((volatile unsigned int*)(0x428425A8UL)) +#define bFM3_USB0_EP2C_DMAE *((volatile unsigned int*)(0x428425ACUL)) +#define bFM3_USB0_EP2C_DIR *((volatile unsigned int*)(0x428425B0UL)) +#define bFM3_USB0_EP2C_TYPE0 *((volatile unsigned int*)(0x428425B4UL)) +#define bFM3_USB0_EP2C_TYPE1 *((volatile unsigned int*)(0x428425B8UL)) +#define bFM3_USB0_EP2C_EPEN *((volatile unsigned int*)(0x428425BCUL)) +#define bFM3_USB0_EP3C_PKS30 *((volatile unsigned int*)(0x42842600UL)) +#define bFM3_USB0_EP3C_PKS31 *((volatile unsigned int*)(0x42842604UL)) +#define bFM3_USB0_EP3C_PKS32 *((volatile unsigned int*)(0x42842608UL)) +#define bFM3_USB0_EP3C_PKS33 *((volatile unsigned int*)(0x4284260CUL)) +#define bFM3_USB0_EP3C_PKS34 *((volatile unsigned int*)(0x42842610UL)) +#define bFM3_USB0_EP3C_PKS35 *((volatile unsigned int*)(0x42842614UL)) +#define bFM3_USB0_EP3C_PKS36 *((volatile unsigned int*)(0x42842618UL)) +#define bFM3_USB0_EP3C_STAL *((volatile unsigned int*)(0x42842624UL)) +#define bFM3_USB0_EP3C_NULE *((volatile unsigned int*)(0x42842628UL)) +#define bFM3_USB0_EP3C_DMAE *((volatile unsigned int*)(0x4284262CUL)) +#define bFM3_USB0_EP3C_DIR *((volatile unsigned int*)(0x42842630UL)) +#define bFM3_USB0_EP3C_TYPE0 *((volatile unsigned int*)(0x42842634UL)) +#define bFM3_USB0_EP3C_TYPE1 *((volatile unsigned int*)(0x42842638UL)) +#define bFM3_USB0_EP3C_EPEN *((volatile unsigned int*)(0x4284263CUL)) +#define bFM3_USB0_EP4C_PKS40 *((volatile unsigned int*)(0x42842680UL)) +#define bFM3_USB0_EP4C_PKS41 *((volatile unsigned int*)(0x42842684UL)) +#define bFM3_USB0_EP4C_PKS42 *((volatile unsigned int*)(0x42842688UL)) +#define bFM3_USB0_EP4C_PKS43 *((volatile unsigned int*)(0x4284268CUL)) +#define bFM3_USB0_EP4C_PKS44 *((volatile unsigned int*)(0x42842690UL)) +#define bFM3_USB0_EP4C_PKS45 *((volatile unsigned int*)(0x42842694UL)) +#define bFM3_USB0_EP4C_PKS46 *((volatile unsigned int*)(0x42842698UL)) +#define bFM3_USB0_EP4C_STAL *((volatile unsigned int*)(0x428426A4UL)) +#define bFM3_USB0_EP4C_NULE *((volatile unsigned int*)(0x428426A8UL)) +#define bFM3_USB0_EP4C_DMAE *((volatile unsigned int*)(0x428426ACUL)) +#define bFM3_USB0_EP4C_DIR *((volatile unsigned int*)(0x428426B0UL)) +#define bFM3_USB0_EP4C_TYPE0 *((volatile unsigned int*)(0x428426B4UL)) +#define bFM3_USB0_EP4C_TYPE1 *((volatile unsigned int*)(0x428426B8UL)) +#define bFM3_USB0_EP4C_EPEN *((volatile unsigned int*)(0x428426BCUL)) +#define bFM3_USB0_EP5C_PKS50 *((volatile unsigned int*)(0x42842700UL)) +#define bFM3_USB0_EP5C_PKS51 *((volatile unsigned int*)(0x42842704UL)) +#define bFM3_USB0_EP5C_PKS52 *((volatile unsigned int*)(0x42842708UL)) +#define bFM3_USB0_EP5C_PKS53 *((volatile unsigned int*)(0x4284270CUL)) +#define bFM3_USB0_EP5C_PKS54 *((volatile unsigned int*)(0x42842710UL)) +#define bFM3_USB0_EP5C_PKS55 *((volatile unsigned int*)(0x42842714UL)) +#define bFM3_USB0_EP5C_PKS56 *((volatile unsigned int*)(0x42842718UL)) +#define bFM3_USB0_EP5C_STAL *((volatile unsigned int*)(0x42842724UL)) +#define bFM3_USB0_EP5C_NULE *((volatile unsigned int*)(0x42842728UL)) +#define bFM3_USB0_EP5C_DMAE *((volatile unsigned int*)(0x4284272CUL)) +#define bFM3_USB0_EP5C_DIR *((volatile unsigned int*)(0x42842730UL)) +#define bFM3_USB0_EP5C_TYPE0 *((volatile unsigned int*)(0x42842734UL)) +#define bFM3_USB0_EP5C_TYPE1 *((volatile unsigned int*)(0x42842738UL)) +#define bFM3_USB0_EP5C_EPEN *((volatile unsigned int*)(0x4284273CUL)) +#define bFM3_USB0_TMSP_TMSP0 *((volatile unsigned int*)(0x42842780UL)) +#define bFM3_USB0_TMSP_TMSP1 *((volatile unsigned int*)(0x42842784UL)) +#define bFM3_USB0_TMSP_TMSP2 *((volatile unsigned int*)(0x42842788UL)) +#define bFM3_USB0_TMSP_TMSP3 *((volatile unsigned int*)(0x4284278CUL)) +#define bFM3_USB0_TMSP_TMSP4 *((volatile unsigned int*)(0x42842790UL)) +#define bFM3_USB0_TMSP_TMSP5 *((volatile unsigned int*)(0x42842794UL)) +#define bFM3_USB0_TMSP_TMSP6 *((volatile unsigned int*)(0x42842798UL)) +#define bFM3_USB0_TMSP_TMSP7 *((volatile unsigned int*)(0x4284279CUL)) +#define bFM3_USB0_TMSP_TMSP8 *((volatile unsigned int*)(0x428427A0UL)) +#define bFM3_USB0_TMSP_TMSP9 *((volatile unsigned int*)(0x428427A4UL)) +#define bFM3_USB0_TMSP_TMSP10 *((volatile unsigned int*)(0x428427A8UL)) +#define bFM3_USB0_UDCS_CONF *((volatile unsigned int*)(0x42842800UL)) +#define bFM3_USB0_UDCS_SETP *((volatile unsigned int*)(0x42842804UL)) +#define bFM3_USB0_UDCS_WKUP *((volatile unsigned int*)(0x42842808UL)) +#define bFM3_USB0_UDCS_BRST *((volatile unsigned int*)(0x4284280CUL)) +#define bFM3_USB0_UDCS_SOF *((volatile unsigned int*)(0x42842810UL)) +#define bFM3_USB0_UDCS_SUSP *((volatile unsigned int*)(0x42842814UL)) +#define bFM3_USB0_UDCIE_CONFIE *((volatile unsigned int*)(0x42842820UL)) +#define bFM3_USB0_UDCIE_CONFN *((volatile unsigned int*)(0x42842824UL)) +#define bFM3_USB0_UDCIE_WKUPIE *((volatile unsigned int*)(0x42842828UL)) +#define bFM3_USB0_UDCIE_BRSTIE *((volatile unsigned int*)(0x4284282CUL)) +#define bFM3_USB0_UDCIE_SOFIE *((volatile unsigned int*)(0x42842830UL)) +#define bFM3_USB0_UDCIE_SUSPIE *((volatile unsigned int*)(0x42842834UL)) +#define bFM3_USB0_EP0IS_DRQI *((volatile unsigned int*)(0x428428A8UL)) +#define bFM3_USB0_EP0IS_DRQIIE *((volatile unsigned int*)(0x428428B8UL)) +#define bFM3_USB0_EP0IS_BFINI *((volatile unsigned int*)(0x428428BCUL)) +#define bFM3_USB0_EP0OS_SIZE0 *((volatile unsigned int*)(0x42842900UL)) +#define bFM3_USB0_EP0OS_SIZE1 *((volatile unsigned int*)(0x42842904UL)) +#define bFM3_USB0_EP0OS_SIZE2 *((volatile unsigned int*)(0x42842908UL)) +#define bFM3_USB0_EP0OS_SIZE3 *((volatile unsigned int*)(0x4284290CUL)) +#define bFM3_USB0_EP0OS_SIZE4 *((volatile unsigned int*)(0x42842910UL)) +#define bFM3_USB0_EP0OS_SIZE5 *((volatile unsigned int*)(0x42842914UL)) +#define bFM3_USB0_EP0OS_SIZE6 *((volatile unsigned int*)(0x42842918UL)) +#define bFM3_USB0_EP0OS_SPK *((volatile unsigned int*)(0x42842924UL)) +#define bFM3_USB0_EP0OS_DRQO *((volatile unsigned int*)(0x42842928UL)) +#define bFM3_USB0_EP0OS_SPKIE *((volatile unsigned int*)(0x42842934UL)) +#define bFM3_USB0_EP0OS_DRQOIE *((volatile unsigned int*)(0x42842938UL)) +#define bFM3_USB0_EP0OS_BFINI *((volatile unsigned int*)(0x4284293CUL)) +#define bFM3_USB0_EP1S_SIZE10 *((volatile unsigned int*)(0x42842980UL)) +#define bFM3_USB0_EP1S_SIZE11 *((volatile unsigned int*)(0x42842984UL)) +#define bFM3_USB0_EP1S_SIZE12 *((volatile unsigned int*)(0x42842988UL)) +#define bFM3_USB0_EP1S_SIZE13 *((volatile unsigned int*)(0x4284298CUL)) +#define bFM3_USB0_EP1S_SIZE14 *((volatile unsigned int*)(0x42842990UL)) +#define bFM3_USB0_EP1S_SIZE15 *((volatile unsigned int*)(0x42842994UL)) +#define bFM3_USB0_EP1S_SIZE16 *((volatile unsigned int*)(0x42842998UL)) +#define bFM3_USB0_EP1S_SIZE17 *((volatile unsigned int*)(0x4284299CUL)) +#define bFM3_USB0_EP1S_SPK *((volatile unsigned int*)(0x428429A4UL)) +#define bFM3_USB0_EP1S_DRQ *((volatile unsigned int*)(0x428429A8UL)) +#define bFM3_USB0_EP1S_BUSY *((volatile unsigned int*)(0x428429ACUL)) +#define bFM3_USB0_EP1S_SPKIE *((volatile unsigned int*)(0x428429B4UL)) +#define bFM3_USB0_EP1S_DRQIE *((volatile unsigned int*)(0x428429B8UL)) +#define bFM3_USB0_EP1S_BFINI *((volatile unsigned int*)(0x428429BCUL)) +#define bFM3_USB0_EP2S_SIZE20 *((volatile unsigned int*)(0x42842A00UL)) +#define bFM3_USB0_EP2S_SIZE21 *((volatile unsigned int*)(0x42842A04UL)) +#define bFM3_USB0_EP2S_SIZE22 *((volatile unsigned int*)(0x42842A08UL)) +#define bFM3_USB0_EP2S_SIZE23 *((volatile unsigned int*)(0x42842A0CUL)) +#define bFM3_USB0_EP2S_SIZE24 *((volatile unsigned int*)(0x42842A10UL)) +#define bFM3_USB0_EP2S_SIZE25 *((volatile unsigned int*)(0x42842A14UL)) +#define bFM3_USB0_EP2S_SIZE26 *((volatile unsigned int*)(0x42842A18UL)) +#define bFM3_USB0_EP2S_SPK *((volatile unsigned int*)(0x42842A24UL)) +#define bFM3_USB0_EP2S_DRQ *((volatile unsigned int*)(0x42842A28UL)) +#define bFM3_USB0_EP2S_BUSY *((volatile unsigned int*)(0x42842A2CUL)) +#define bFM3_USB0_EP2S_SPKIE *((volatile unsigned int*)(0x42842A34UL)) +#define bFM3_USB0_EP2S_DRQIE *((volatile unsigned int*)(0x42842A38UL)) +#define bFM3_USB0_EP2S_BFINI *((volatile unsigned int*)(0x42842A3CUL)) +#define bFM3_USB0_EP3S_SIZE30 *((volatile unsigned int*)(0x42842A80UL)) +#define bFM3_USB0_EP3S_SIZE31 *((volatile unsigned int*)(0x42842A84UL)) +#define bFM3_USB0_EP3S_SIZE32 *((volatile unsigned int*)(0x42842A88UL)) +#define bFM3_USB0_EP3S_SIZE33 *((volatile unsigned int*)(0x42842A8CUL)) +#define bFM3_USB0_EP3S_SIZE34 *((volatile unsigned int*)(0x42842A90UL)) +#define bFM3_USB0_EP3S_SIZE35 *((volatile unsigned int*)(0x42842A94UL)) +#define bFM3_USB0_EP3S_SIZE36 *((volatile unsigned int*)(0x42842A98UL)) +#define bFM3_USB0_EP3S_SPK *((volatile unsigned int*)(0x42842AA4UL)) +#define bFM3_USB0_EP3S_DRQ *((volatile unsigned int*)(0x42842AA8UL)) +#define bFM3_USB0_EP3S_BUSY *((volatile unsigned int*)(0x42842AACUL)) +#define bFM3_USB0_EP3S_SPKIE *((volatile unsigned int*)(0x42842AB4UL)) +#define bFM3_USB0_EP3S_DRQIE *((volatile unsigned int*)(0x42842AB8UL)) +#define bFM3_USB0_EP3S_BFINI *((volatile unsigned int*)(0x42842ABCUL)) +#define bFM3_USB0_EP4S_SIZE40 *((volatile unsigned int*)(0x42842B00UL)) +#define bFM3_USB0_EP4S_SIZE41 *((volatile unsigned int*)(0x42842B04UL)) +#define bFM3_USB0_EP4S_SIZE42 *((volatile unsigned int*)(0x42842B08UL)) +#define bFM3_USB0_EP4S_SIZE43 *((volatile unsigned int*)(0x42842B0CUL)) +#define bFM3_USB0_EP4S_SIZE44 *((volatile unsigned int*)(0x42842B10UL)) +#define bFM3_USB0_EP4S_SIZE45 *((volatile unsigned int*)(0x42842B14UL)) +#define bFM3_USB0_EP4S_SIZE46 *((volatile unsigned int*)(0x42842B18UL)) +#define bFM3_USB0_EP4S_SPK *((volatile unsigned int*)(0x42842B24UL)) +#define bFM3_USB0_EP4S_DRQ *((volatile unsigned int*)(0x42842B28UL)) +#define bFM3_USB0_EP4S_BUSY *((volatile unsigned int*)(0x42842B2CUL)) +#define bFM3_USB0_EP4S_SPKIE *((volatile unsigned int*)(0x42842B34UL)) +#define bFM3_USB0_EP4S_DRQIE *((volatile unsigned int*)(0x42842B38UL)) +#define bFM3_USB0_EP4S_BFINI *((volatile unsigned int*)(0x42842B3CUL)) +#define bFM3_USB0_EP5S_SIZE50 *((volatile unsigned int*)(0x42842B80UL)) +#define bFM3_USB0_EP5S_SIZE51 *((volatile unsigned int*)(0x42842B84UL)) +#define bFM3_USB0_EP5S_SIZE52 *((volatile unsigned int*)(0x42842B88UL)) +#define bFM3_USB0_EP5S_SIZE53 *((volatile unsigned int*)(0x42842B8CUL)) +#define bFM3_USB0_EP5S_SIZE54 *((volatile unsigned int*)(0x42842B90UL)) +#define bFM3_USB0_EP5S_SIZE55 *((volatile unsigned int*)(0x42842B94UL)) +#define bFM3_USB0_EP5S_SIZE56 *((volatile unsigned int*)(0x42842B98UL)) +#define bFM3_USB0_EP5S_SPK *((volatile unsigned int*)(0x42842BA4UL)) +#define bFM3_USB0_EP5S_DRQ *((volatile unsigned int*)(0x42842BA8UL)) +#define bFM3_USB0_EP5S_BUSY *((volatile unsigned int*)(0x42842BACUL)) +#define bFM3_USB0_EP5S_SPKIE *((volatile unsigned int*)(0x42842BB4UL)) +#define bFM3_USB0_EP5S_DRQIE *((volatile unsigned int*)(0x42842BB8UL)) +#define bFM3_USB0_EP5S_BFINI *((volatile unsigned int*)(0x42842BBCUL)) + +/* DMA controller */ +#define bFM3_DMAC_DMACR_DH0 *((volatile unsigned int*)(0x42C00060UL)) +#define bFM3_DMAC_DMACR_DH1 *((volatile unsigned int*)(0x42C00064UL)) +#define bFM3_DMAC_DMACR_DH2 *((volatile unsigned int*)(0x42C00068UL)) +#define bFM3_DMAC_DMACR_DH3 *((volatile unsigned int*)(0x42C0006CUL)) +#define bFM3_DMAC_DMACR_PR *((volatile unsigned int*)(0x42C00070UL)) +#define bFM3_DMAC_DMACR_DS *((volatile unsigned int*)(0x42C00078UL)) +#define bFM3_DMAC_DMACR_DE *((volatile unsigned int*)(0x42C0007CUL)) +#define bFM3_DMAC_DMACA0_TC0 *((volatile unsigned int*)(0x42C00200UL)) +#define bFM3_DMAC_DMACA0_TC1 *((volatile unsigned int*)(0x42C00204UL)) +#define bFM3_DMAC_DMACA0_TC2 *((volatile unsigned int*)(0x42C00208UL)) +#define bFM3_DMAC_DMACA0_TC3 *((volatile unsigned int*)(0x42C0020CUL)) +#define bFM3_DMAC_DMACA0_TC4 *((volatile unsigned int*)(0x42C00210UL)) +#define bFM3_DMAC_DMACA0_TC5 *((volatile unsigned int*)(0x42C00214UL)) +#define bFM3_DMAC_DMACA0_TC6 *((volatile unsigned int*)(0x42C00218UL)) +#define bFM3_DMAC_DMACA0_TC7 *((volatile unsigned int*)(0x42C0021CUL)) +#define bFM3_DMAC_DMACA0_TC8 *((volatile unsigned int*)(0x42C00220UL)) +#define bFM3_DMAC_DMACA0_TC9 *((volatile unsigned int*)(0x42C00224UL)) +#define bFM3_DMAC_DMACA0_TC10 *((volatile unsigned int*)(0x42C00228UL)) +#define bFM3_DMAC_DMACA0_TC11 *((volatile unsigned int*)(0x42C0022CUL)) +#define bFM3_DMAC_DMACA0_TC12 *((volatile unsigned int*)(0x42C00230UL)) +#define bFM3_DMAC_DMACA0_TC13 *((volatile unsigned int*)(0x42C00234UL)) +#define bFM3_DMAC_DMACA0_TC14 *((volatile unsigned int*)(0x42C00238UL)) +#define bFM3_DMAC_DMACA0_TC15 *((volatile unsigned int*)(0x42C0023CUL)) +#define bFM3_DMAC_DMACA0_BC0 *((volatile unsigned int*)(0x42C00240UL)) +#define bFM3_DMAC_DMACA0_BC1 *((volatile unsigned int*)(0x42C00244UL)) +#define bFM3_DMAC_DMACA0_BC2 *((volatile unsigned int*)(0x42C00248UL)) +#define bFM3_DMAC_DMACA0_BC3 *((volatile unsigned int*)(0x42C0024CUL)) +#define bFM3_DMAC_DMACA0_IS0 *((volatile unsigned int*)(0x42C0025CUL)) +#define bFM3_DMAC_DMACA0_IS1 *((volatile unsigned int*)(0x42C00260UL)) +#define bFM3_DMAC_DMACA0_IS2 *((volatile unsigned int*)(0x42C00264UL)) +#define bFM3_DMAC_DMACA0_IS3 *((volatile unsigned int*)(0x42C00268UL)) +#define bFM3_DMAC_DMACA0_IS4 *((volatile unsigned int*)(0x42C0026CUL)) +#define bFM3_DMAC_DMACA0_IS5 *((volatile unsigned int*)(0x42C00270UL)) +#define bFM3_DMAC_DMACA0_ST *((volatile unsigned int*)(0x42C00274UL)) +#define bFM3_DMAC_DMACA0_PB *((volatile unsigned int*)(0x42C00278UL)) +#define bFM3_DMAC_DMACA0_EB *((volatile unsigned int*)(0x42C0027CUL)) +#define bFM3_DMAC_DMACB0_EM *((volatile unsigned int*)(0x42C00280UL)) +#define bFM3_DMAC_DMACB0_SS0 *((volatile unsigned int*)(0x42C002C0UL)) +#define bFM3_DMAC_DMACB0_SS1 *((volatile unsigned int*)(0x42C002C4UL)) +#define bFM3_DMAC_DMACB0_SS2 *((volatile unsigned int*)(0x42C002C8UL)) +#define bFM3_DMAC_DMACB0_CI *((volatile unsigned int*)(0x42C002CCUL)) +#define bFM3_DMAC_DMACB0_EI *((volatile unsigned int*)(0x42C002D0UL)) +#define bFM3_DMAC_DMACB0_RD *((volatile unsigned int*)(0x42C002D4UL)) +#define bFM3_DMAC_DMACB0_RS *((volatile unsigned int*)(0x42C002D8UL)) +#define bFM3_DMAC_DMACB0_RC *((volatile unsigned int*)(0x42C002DCUL)) +#define bFM3_DMAC_DMACB0_FD *((volatile unsigned int*)(0x42C002E0UL)) +#define bFM3_DMAC_DMACB0_FS *((volatile unsigned int*)(0x42C002E4UL)) +#define bFM3_DMAC_DMACB0_TW0 *((volatile unsigned int*)(0x42C002E8UL)) +#define bFM3_DMAC_DMACB0_TW1 *((volatile unsigned int*)(0x42C002ECUL)) +#define bFM3_DMAC_DMACB0_MS0 *((volatile unsigned int*)(0x42C002F0UL)) +#define bFM3_DMAC_DMACB0_MS1 *((volatile unsigned int*)(0x42C002F4UL)) +#define bFM3_DMAC_DMACA1_TC0 *((volatile unsigned int*)(0x42C00400UL)) +#define bFM3_DMAC_DMACA1_TC1 *((volatile unsigned int*)(0x42C00404UL)) +#define bFM3_DMAC_DMACA1_TC2 *((volatile unsigned int*)(0x42C00408UL)) +#define bFM3_DMAC_DMACA1_TC3 *((volatile unsigned int*)(0x42C0040CUL)) +#define bFM3_DMAC_DMACA1_TC4 *((volatile unsigned int*)(0x42C00410UL)) +#define bFM3_DMAC_DMACA1_TC5 *((volatile unsigned int*)(0x42C00414UL)) +#define bFM3_DMAC_DMACA1_TC6 *((volatile unsigned int*)(0x42C00418UL)) +#define bFM3_DMAC_DMACA1_TC7 *((volatile unsigned int*)(0x42C0041CUL)) +#define bFM3_DMAC_DMACA1_TC8 *((volatile unsigned int*)(0x42C00420UL)) +#define bFM3_DMAC_DMACA1_TC9 *((volatile unsigned int*)(0x42C00424UL)) +#define bFM3_DMAC_DMACA1_TC10 *((volatile unsigned int*)(0x42C00428UL)) +#define bFM3_DMAC_DMACA1_TC11 *((volatile unsigned int*)(0x42C0042CUL)) +#define bFM3_DMAC_DMACA1_TC12 *((volatile unsigned int*)(0x42C00430UL)) +#define bFM3_DMAC_DMACA1_TC13 *((volatile unsigned int*)(0x42C00434UL)) +#define bFM3_DMAC_DMACA1_TC14 *((volatile unsigned int*)(0x42C00438UL)) +#define bFM3_DMAC_DMACA1_TC15 *((volatile unsigned int*)(0x42C0043CUL)) +#define bFM3_DMAC_DMACA1_BC0 *((volatile unsigned int*)(0x42C00440UL)) +#define bFM3_DMAC_DMACA1_BC1 *((volatile unsigned int*)(0x42C00444UL)) +#define bFM3_DMAC_DMACA1_BC2 *((volatile unsigned int*)(0x42C00448UL)) +#define bFM3_DMAC_DMACA1_BC3 *((volatile unsigned int*)(0x42C0044CUL)) +#define bFM3_DMAC_DMACA1_IS0 *((volatile unsigned int*)(0x42C0045CUL)) +#define bFM3_DMAC_DMACA1_IS1 *((volatile unsigned int*)(0x42C00460UL)) +#define bFM3_DMAC_DMACA1_IS2 *((volatile unsigned int*)(0x42C00464UL)) +#define bFM3_DMAC_DMACA1_IS3 *((volatile unsigned int*)(0x42C00468UL)) +#define bFM3_DMAC_DMACA1_IS4 *((volatile unsigned int*)(0x42C0046CUL)) +#define bFM3_DMAC_DMACA1_IS5 *((volatile unsigned int*)(0x42C00470UL)) +#define bFM3_DMAC_DMACA1_ST *((volatile unsigned int*)(0x42C00474UL)) +#define bFM3_DMAC_DMACA1_PB *((volatile unsigned int*)(0x42C00478UL)) +#define bFM3_DMAC_DMACA1_EB *((volatile unsigned int*)(0x42C0047CUL)) +#define bFM3_DMAC_DMACB1_EM *((volatile unsigned int*)(0x42C00480UL)) +#define bFM3_DMAC_DMACB1_SS0 *((volatile unsigned int*)(0x42C004C0UL)) +#define bFM3_DMAC_DMACB1_SS1 *((volatile unsigned int*)(0x42C004C4UL)) +#define bFM3_DMAC_DMACB1_SS2 *((volatile unsigned int*)(0x42C004C8UL)) +#define bFM3_DMAC_DMACB1_CI *((volatile unsigned int*)(0x42C004CCUL)) +#define bFM3_DMAC_DMACB1_EI *((volatile unsigned int*)(0x42C004D0UL)) +#define bFM3_DMAC_DMACB1_RD *((volatile unsigned int*)(0x42C004D4UL)) +#define bFM3_DMAC_DMACB1_RS *((volatile unsigned int*)(0x42C004D8UL)) +#define bFM3_DMAC_DMACB1_RC *((volatile unsigned int*)(0x42C004DCUL)) +#define bFM3_DMAC_DMACB1_FD *((volatile unsigned int*)(0x42C004E0UL)) +#define bFM3_DMAC_DMACB1_FS *((volatile unsigned int*)(0x42C004E4UL)) +#define bFM3_DMAC_DMACB1_TW0 *((volatile unsigned int*)(0x42C004E8UL)) +#define bFM3_DMAC_DMACB1_TW1 *((volatile unsigned int*)(0x42C004ECUL)) +#define bFM3_DMAC_DMACB1_MS0 *((volatile unsigned int*)(0x42C004F0UL)) +#define bFM3_DMAC_DMACB1_MS1 *((volatile unsigned int*)(0x42C004F4UL)) +#define bFM3_DMAC_DMACA2_TC0 *((volatile unsigned int*)(0x42C00600UL)) +#define bFM3_DMAC_DMACA2_TC1 *((volatile unsigned int*)(0x42C00604UL)) +#define bFM3_DMAC_DMACA2_TC2 *((volatile unsigned int*)(0x42C00608UL)) +#define bFM3_DMAC_DMACA2_TC3 *((volatile unsigned int*)(0x42C0060CUL)) +#define bFM3_DMAC_DMACA2_TC4 *((volatile unsigned int*)(0x42C00610UL)) +#define bFM3_DMAC_DMACA2_TC5 *((volatile unsigned int*)(0x42C00614UL)) +#define bFM3_DMAC_DMACA2_TC6 *((volatile unsigned int*)(0x42C00618UL)) +#define bFM3_DMAC_DMACA2_TC7 *((volatile unsigned int*)(0x42C0061CUL)) +#define bFM3_DMAC_DMACA2_TC8 *((volatile unsigned int*)(0x42C00620UL)) +#define bFM3_DMAC_DMACA2_TC9 *((volatile unsigned int*)(0x42C00624UL)) +#define bFM3_DMAC_DMACA2_TC10 *((volatile unsigned int*)(0x42C00628UL)) +#define bFM3_DMAC_DMACA2_TC11 *((volatile unsigned int*)(0x42C0062CUL)) +#define bFM3_DMAC_DMACA2_TC12 *((volatile unsigned int*)(0x42C00630UL)) +#define bFM3_DMAC_DMACA2_TC13 *((volatile unsigned int*)(0x42C00634UL)) +#define bFM3_DMAC_DMACA2_TC14 *((volatile unsigned int*)(0x42C00638UL)) +#define bFM3_DMAC_DMACA2_TC15 *((volatile unsigned int*)(0x42C0063CUL)) +#define bFM3_DMAC_DMACA2_BC0 *((volatile unsigned int*)(0x42C00640UL)) +#define bFM3_DMAC_DMACA2_BC1 *((volatile unsigned int*)(0x42C00644UL)) +#define bFM3_DMAC_DMACA2_BC2 *((volatile unsigned int*)(0x42C00648UL)) +#define bFM3_DMAC_DMACA2_BC3 *((volatile unsigned int*)(0x42C0064CUL)) +#define bFM3_DMAC_DMACA2_IS0 *((volatile unsigned int*)(0x42C0065CUL)) +#define bFM3_DMAC_DMACA2_IS1 *((volatile unsigned int*)(0x42C00660UL)) +#define bFM3_DMAC_DMACA2_IS2 *((volatile unsigned int*)(0x42C00664UL)) +#define bFM3_DMAC_DMACA2_IS3 *((volatile unsigned int*)(0x42C00668UL)) +#define bFM3_DMAC_DMACA2_IS4 *((volatile unsigned int*)(0x42C0066CUL)) +#define bFM3_DMAC_DMACA2_IS5 *((volatile unsigned int*)(0x42C00670UL)) +#define bFM3_DMAC_DMACA2_ST *((volatile unsigned int*)(0x42C00674UL)) +#define bFM3_DMAC_DMACA2_PB *((volatile unsigned int*)(0x42C00678UL)) +#define bFM3_DMAC_DMACA2_EB *((volatile unsigned int*)(0x42C0067CUL)) +#define bFM3_DMAC_DMACB2_EM *((volatile unsigned int*)(0x42C00680UL)) +#define bFM3_DMAC_DMACB2_SS0 *((volatile unsigned int*)(0x42C006C0UL)) +#define bFM3_DMAC_DMACB2_SS1 *((volatile unsigned int*)(0x42C006C4UL)) +#define bFM3_DMAC_DMACB2_SS2 *((volatile unsigned int*)(0x42C006C8UL)) +#define bFM3_DMAC_DMACB2_CI *((volatile unsigned int*)(0x42C006CCUL)) +#define bFM3_DMAC_DMACB2_EI *((volatile unsigned int*)(0x42C006D0UL)) +#define bFM3_DMAC_DMACB2_RD *((volatile unsigned int*)(0x42C006D4UL)) +#define bFM3_DMAC_DMACB2_RS *((volatile unsigned int*)(0x42C006D8UL)) +#define bFM3_DMAC_DMACB2_RC *((volatile unsigned int*)(0x42C006DCUL)) +#define bFM3_DMAC_DMACB2_FD *((volatile unsigned int*)(0x42C006E0UL)) +#define bFM3_DMAC_DMACB2_FS *((volatile unsigned int*)(0x42C006E4UL)) +#define bFM3_DMAC_DMACB2_TW0 *((volatile unsigned int*)(0x42C006E8UL)) +#define bFM3_DMAC_DMACB2_TW1 *((volatile unsigned int*)(0x42C006ECUL)) +#define bFM3_DMAC_DMACB2_MS0 *((volatile unsigned int*)(0x42C006F0UL)) +#define bFM3_DMAC_DMACB2_MS1 *((volatile unsigned int*)(0x42C006F4UL)) +#define bFM3_DMAC_DMACA3_TC0 *((volatile unsigned int*)(0x42C00800UL)) +#define bFM3_DMAC_DMACA3_TC1 *((volatile unsigned int*)(0x42C00804UL)) +#define bFM3_DMAC_DMACA3_TC2 *((volatile unsigned int*)(0x42C00808UL)) +#define bFM3_DMAC_DMACA3_TC3 *((volatile unsigned int*)(0x42C0080CUL)) +#define bFM3_DMAC_DMACA3_TC4 *((volatile unsigned int*)(0x42C00810UL)) +#define bFM3_DMAC_DMACA3_TC5 *((volatile unsigned int*)(0x42C00814UL)) +#define bFM3_DMAC_DMACA3_TC6 *((volatile unsigned int*)(0x42C00818UL)) +#define bFM3_DMAC_DMACA3_TC7 *((volatile unsigned int*)(0x42C0081CUL)) +#define bFM3_DMAC_DMACA3_TC8 *((volatile unsigned int*)(0x42C00820UL)) +#define bFM3_DMAC_DMACA3_TC9 *((volatile unsigned int*)(0x42C00824UL)) +#define bFM3_DMAC_DMACA3_TC10 *((volatile unsigned int*)(0x42C00828UL)) +#define bFM3_DMAC_DMACA3_TC11 *((volatile unsigned int*)(0x42C0082CUL)) +#define bFM3_DMAC_DMACA3_TC12 *((volatile unsigned int*)(0x42C00830UL)) +#define bFM3_DMAC_DMACA3_TC13 *((volatile unsigned int*)(0x42C00834UL)) +#define bFM3_DMAC_DMACA3_TC14 *((volatile unsigned int*)(0x42C00838UL)) +#define bFM3_DMAC_DMACA3_TC15 *((volatile unsigned int*)(0x42C0083CUL)) +#define bFM3_DMAC_DMACA3_BC0 *((volatile unsigned int*)(0x42C00840UL)) +#define bFM3_DMAC_DMACA3_BC1 *((volatile unsigned int*)(0x42C00844UL)) +#define bFM3_DMAC_DMACA3_BC2 *((volatile unsigned int*)(0x42C00848UL)) +#define bFM3_DMAC_DMACA3_BC3 *((volatile unsigned int*)(0x42C0084CUL)) +#define bFM3_DMAC_DMACA3_IS0 *((volatile unsigned int*)(0x42C0085CUL)) +#define bFM3_DMAC_DMACA3_IS1 *((volatile unsigned int*)(0x42C00860UL)) +#define bFM3_DMAC_DMACA3_IS2 *((volatile unsigned int*)(0x42C00864UL)) +#define bFM3_DMAC_DMACA3_IS3 *((volatile unsigned int*)(0x42C00868UL)) +#define bFM3_DMAC_DMACA3_IS4 *((volatile unsigned int*)(0x42C0086CUL)) +#define bFM3_DMAC_DMACA3_IS5 *((volatile unsigned int*)(0x42C00870UL)) +#define bFM3_DMAC_DMACA3_ST *((volatile unsigned int*)(0x42C00874UL)) +#define bFM3_DMAC_DMACA3_PB *((volatile unsigned int*)(0x42C00878UL)) +#define bFM3_DMAC_DMACA3_EB *((volatile unsigned int*)(0x42C0087CUL)) +#define bFM3_DMAC_DMACB3_EM *((volatile unsigned int*)(0x42C00880UL)) +#define bFM3_DMAC_DMACB3_SS0 *((volatile unsigned int*)(0x42C008C0UL)) +#define bFM3_DMAC_DMACB3_SS1 *((volatile unsigned int*)(0x42C008C4UL)) +#define bFM3_DMAC_DMACB3_SS2 *((volatile unsigned int*)(0x42C008C8UL)) +#define bFM3_DMAC_DMACB3_CI *((volatile unsigned int*)(0x42C008CCUL)) +#define bFM3_DMAC_DMACB3_EI *((volatile unsigned int*)(0x42C008D0UL)) +#define bFM3_DMAC_DMACB3_RD *((volatile unsigned int*)(0x42C008D4UL)) +#define bFM3_DMAC_DMACB3_RS *((volatile unsigned int*)(0x42C008D8UL)) +#define bFM3_DMAC_DMACB3_RC *((volatile unsigned int*)(0x42C008DCUL)) +#define bFM3_DMAC_DMACB3_FD *((volatile unsigned int*)(0x42C008E0UL)) +#define bFM3_DMAC_DMACB3_FS *((volatile unsigned int*)(0x42C008E4UL)) +#define bFM3_DMAC_DMACB3_TW0 *((volatile unsigned int*)(0x42C008E8UL)) +#define bFM3_DMAC_DMACB3_TW1 *((volatile unsigned int*)(0x42C008ECUL)) +#define bFM3_DMAC_DMACB3_MS0 *((volatile unsigned int*)(0x42C008F0UL)) +#define bFM3_DMAC_DMACB3_MS1 *((volatile unsigned int*)(0x42C008F4UL)) +#define bFM3_DMAC_DMACA4_TC0 *((volatile unsigned int*)(0x42C00A00UL)) +#define bFM3_DMAC_DMACA4_TC1 *((volatile unsigned int*)(0x42C00A04UL)) +#define bFM3_DMAC_DMACA4_TC2 *((volatile unsigned int*)(0x42C00A08UL)) +#define bFM3_DMAC_DMACA4_TC3 *((volatile unsigned int*)(0x42C00A0CUL)) +#define bFM3_DMAC_DMACA4_TC4 *((volatile unsigned int*)(0x42C00A10UL)) +#define bFM3_DMAC_DMACA4_TC5 *((volatile unsigned int*)(0x42C00A14UL)) +#define bFM3_DMAC_DMACA4_TC6 *((volatile unsigned int*)(0x42C00A18UL)) +#define bFM3_DMAC_DMACA4_TC7 *((volatile unsigned int*)(0x42C00A1CUL)) +#define bFM3_DMAC_DMACA4_TC8 *((volatile unsigned int*)(0x42C00A20UL)) +#define bFM3_DMAC_DMACA4_TC9 *((volatile unsigned int*)(0x42C00A24UL)) +#define bFM3_DMAC_DMACA4_TC10 *((volatile unsigned int*)(0x42C00A28UL)) +#define bFM3_DMAC_DMACA4_TC11 *((volatile unsigned int*)(0x42C00A2CUL)) +#define bFM3_DMAC_DMACA4_TC12 *((volatile unsigned int*)(0x42C00A30UL)) +#define bFM3_DMAC_DMACA4_TC13 *((volatile unsigned int*)(0x42C00A34UL)) +#define bFM3_DMAC_DMACA4_TC14 *((volatile unsigned int*)(0x42C00A38UL)) +#define bFM3_DMAC_DMACA4_TC15 *((volatile unsigned int*)(0x42C00A3CUL)) +#define bFM3_DMAC_DMACA4_BC0 *((volatile unsigned int*)(0x42C00A40UL)) +#define bFM3_DMAC_DMACA4_BC1 *((volatile unsigned int*)(0x42C00A44UL)) +#define bFM3_DMAC_DMACA4_BC2 *((volatile unsigned int*)(0x42C00A48UL)) +#define bFM3_DMAC_DMACA4_BC3 *((volatile unsigned int*)(0x42C00A4CUL)) +#define bFM3_DMAC_DMACA4_IS0 *((volatile unsigned int*)(0x42C00A5CUL)) +#define bFM3_DMAC_DMACA4_IS1 *((volatile unsigned int*)(0x42C00A60UL)) +#define bFM3_DMAC_DMACA4_IS2 *((volatile unsigned int*)(0x42C00A64UL)) +#define bFM3_DMAC_DMACA4_IS3 *((volatile unsigned int*)(0x42C00A68UL)) +#define bFM3_DMAC_DMACA4_IS4 *((volatile unsigned int*)(0x42C00A6CUL)) +#define bFM3_DMAC_DMACA4_IS5 *((volatile unsigned int*)(0x42C00A70UL)) +#define bFM3_DMAC_DMACA4_ST *((volatile unsigned int*)(0x42C00A74UL)) +#define bFM3_DMAC_DMACA4_PB *((volatile unsigned int*)(0x42C00A78UL)) +#define bFM3_DMAC_DMACA4_EB *((volatile unsigned int*)(0x42C00A7CUL)) +#define bFM3_DMAC_DMACB4_EM *((volatile unsigned int*)(0x42C00A80UL)) +#define bFM3_DMAC_DMACB4_SS0 *((volatile unsigned int*)(0x42C00AC0UL)) +#define bFM3_DMAC_DMACB4_SS1 *((volatile unsigned int*)(0x42C00AC4UL)) +#define bFM3_DMAC_DMACB4_SS2 *((volatile unsigned int*)(0x42C00AC8UL)) +#define bFM3_DMAC_DMACB4_CI *((volatile unsigned int*)(0x42C00ACCUL)) +#define bFM3_DMAC_DMACB4_EI *((volatile unsigned int*)(0x42C00AD0UL)) +#define bFM3_DMAC_DMACB4_RD *((volatile unsigned int*)(0x42C00AD4UL)) +#define bFM3_DMAC_DMACB4_RS *((volatile unsigned int*)(0x42C00AD8UL)) +#define bFM3_DMAC_DMACB4_RC *((volatile unsigned int*)(0x42C00ADCUL)) +#define bFM3_DMAC_DMACB4_FD *((volatile unsigned int*)(0x42C00AE0UL)) +#define bFM3_DMAC_DMACB4_FS *((volatile unsigned int*)(0x42C00AE4UL)) +#define bFM3_DMAC_DMACB4_TW0 *((volatile unsigned int*)(0x42C00AE8UL)) +#define bFM3_DMAC_DMACB4_TW1 *((volatile unsigned int*)(0x42C00AECUL)) +#define bFM3_DMAC_DMACB4_MS0 *((volatile unsigned int*)(0x42C00AF0UL)) +#define bFM3_DMAC_DMACB4_MS1 *((volatile unsigned int*)(0x42C00AF4UL)) +#define bFM3_DMAC_DMACA5_TC0 *((volatile unsigned int*)(0x42C00C00UL)) +#define bFM3_DMAC_DMACA5_TC1 *((volatile unsigned int*)(0x42C00C04UL)) +#define bFM3_DMAC_DMACA5_TC2 *((volatile unsigned int*)(0x42C00C08UL)) +#define bFM3_DMAC_DMACA5_TC3 *((volatile unsigned int*)(0x42C00C0CUL)) +#define bFM3_DMAC_DMACA5_TC4 *((volatile unsigned int*)(0x42C00C10UL)) +#define bFM3_DMAC_DMACA5_TC5 *((volatile unsigned int*)(0x42C00C14UL)) +#define bFM3_DMAC_DMACA5_TC6 *((volatile unsigned int*)(0x42C00C18UL)) +#define bFM3_DMAC_DMACA5_TC7 *((volatile unsigned int*)(0x42C00C1CUL)) +#define bFM3_DMAC_DMACA5_TC8 *((volatile unsigned int*)(0x42C00C20UL)) +#define bFM3_DMAC_DMACA5_TC9 *((volatile unsigned int*)(0x42C00C24UL)) +#define bFM3_DMAC_DMACA5_TC10 *((volatile unsigned int*)(0x42C00C28UL)) +#define bFM3_DMAC_DMACA5_TC11 *((volatile unsigned int*)(0x42C00C2CUL)) +#define bFM3_DMAC_DMACA5_TC12 *((volatile unsigned int*)(0x42C00C30UL)) +#define bFM3_DMAC_DMACA5_TC13 *((volatile unsigned int*)(0x42C00C34UL)) +#define bFM3_DMAC_DMACA5_TC14 *((volatile unsigned int*)(0x42C00C38UL)) +#define bFM3_DMAC_DMACA5_TC15 *((volatile unsigned int*)(0x42C00C3CUL)) +#define bFM3_DMAC_DMACA5_BC0 *((volatile unsigned int*)(0x42C00C40UL)) +#define bFM3_DMAC_DMACA5_BC1 *((volatile unsigned int*)(0x42C00C44UL)) +#define bFM3_DMAC_DMACA5_BC2 *((volatile unsigned int*)(0x42C00C48UL)) +#define bFM3_DMAC_DMACA5_BC3 *((volatile unsigned int*)(0x42C00C4CUL)) +#define bFM3_DMAC_DMACA5_IS0 *((volatile unsigned int*)(0x42C00C5CUL)) +#define bFM3_DMAC_DMACA5_IS1 *((volatile unsigned int*)(0x42C00C60UL)) +#define bFM3_DMAC_DMACA5_IS2 *((volatile unsigned int*)(0x42C00C64UL)) +#define bFM3_DMAC_DMACA5_IS3 *((volatile unsigned int*)(0x42C00C68UL)) +#define bFM3_DMAC_DMACA5_IS4 *((volatile unsigned int*)(0x42C00C6CUL)) +#define bFM3_DMAC_DMACA5_IS5 *((volatile unsigned int*)(0x42C00C70UL)) +#define bFM3_DMAC_DMACA5_ST *((volatile unsigned int*)(0x42C00C74UL)) +#define bFM3_DMAC_DMACA5_PB *((volatile unsigned int*)(0x42C00C78UL)) +#define bFM3_DMAC_DMACA5_EB *((volatile unsigned int*)(0x42C00C7CUL)) +#define bFM3_DMAC_DMACB5_EM *((volatile unsigned int*)(0x42C00C80UL)) +#define bFM3_DMAC_DMACB5_SS0 *((volatile unsigned int*)(0x42C00CC0UL)) +#define bFM3_DMAC_DMACB5_SS1 *((volatile unsigned int*)(0x42C00CC4UL)) +#define bFM3_DMAC_DMACB5_SS2 *((volatile unsigned int*)(0x42C00CC8UL)) +#define bFM3_DMAC_DMACB5_CI *((volatile unsigned int*)(0x42C00CCCUL)) +#define bFM3_DMAC_DMACB5_EI *((volatile unsigned int*)(0x42C00CD0UL)) +#define bFM3_DMAC_DMACB5_RD *((volatile unsigned int*)(0x42C00CD4UL)) +#define bFM3_DMAC_DMACB5_RS *((volatile unsigned int*)(0x42C00CD8UL)) +#define bFM3_DMAC_DMACB5_RC *((volatile unsigned int*)(0x42C00CDCUL)) +#define bFM3_DMAC_DMACB5_FD *((volatile unsigned int*)(0x42C00CE0UL)) +#define bFM3_DMAC_DMACB5_FS *((volatile unsigned int*)(0x42C00CE4UL)) +#define bFM3_DMAC_DMACB5_TW0 *((volatile unsigned int*)(0x42C00CE8UL)) +#define bFM3_DMAC_DMACB5_TW1 *((volatile unsigned int*)(0x42C00CECUL)) +#define bFM3_DMAC_DMACB5_MS0 *((volatile unsigned int*)(0x42C00CF0UL)) +#define bFM3_DMAC_DMACB5_MS1 *((volatile unsigned int*)(0x42C00CF4UL)) +#define bFM3_DMAC_DMACA6_TC0 *((volatile unsigned int*)(0x42C00E00UL)) +#define bFM3_DMAC_DMACA6_TC1 *((volatile unsigned int*)(0x42C00E04UL)) +#define bFM3_DMAC_DMACA6_TC2 *((volatile unsigned int*)(0x42C00E08UL)) +#define bFM3_DMAC_DMACA6_TC3 *((volatile unsigned int*)(0x42C00E0CUL)) +#define bFM3_DMAC_DMACA6_TC4 *((volatile unsigned int*)(0x42C00E10UL)) +#define bFM3_DMAC_DMACA6_TC5 *((volatile unsigned int*)(0x42C00E14UL)) +#define bFM3_DMAC_DMACA6_TC6 *((volatile unsigned int*)(0x42C00E18UL)) +#define bFM3_DMAC_DMACA6_TC7 *((volatile unsigned int*)(0x42C00E1CUL)) +#define bFM3_DMAC_DMACA6_TC8 *((volatile unsigned int*)(0x42C00E20UL)) +#define bFM3_DMAC_DMACA6_TC9 *((volatile unsigned int*)(0x42C00E24UL)) +#define bFM3_DMAC_DMACA6_TC10 *((volatile unsigned int*)(0x42C00E28UL)) +#define bFM3_DMAC_DMACA6_TC11 *((volatile unsigned int*)(0x42C00E2CUL)) +#define bFM3_DMAC_DMACA6_TC12 *((volatile unsigned int*)(0x42C00E30UL)) +#define bFM3_DMAC_DMACA6_TC13 *((volatile unsigned int*)(0x42C00E34UL)) +#define bFM3_DMAC_DMACA6_TC14 *((volatile unsigned int*)(0x42C00E38UL)) +#define bFM3_DMAC_DMACA6_TC15 *((volatile unsigned int*)(0x42C00E3CUL)) +#define bFM3_DMAC_DMACA6_BC0 *((volatile unsigned int*)(0x42C00E40UL)) +#define bFM3_DMAC_DMACA6_BC1 *((volatile unsigned int*)(0x42C00E44UL)) +#define bFM3_DMAC_DMACA6_BC2 *((volatile unsigned int*)(0x42C00E48UL)) +#define bFM3_DMAC_DMACA6_BC3 *((volatile unsigned int*)(0x42C00E4CUL)) +#define bFM3_DMAC_DMACA6_IS0 *((volatile unsigned int*)(0x42C00E5CUL)) +#define bFM3_DMAC_DMACA6_IS1 *((volatile unsigned int*)(0x42C00E60UL)) +#define bFM3_DMAC_DMACA6_IS2 *((volatile unsigned int*)(0x42C00E64UL)) +#define bFM3_DMAC_DMACA6_IS3 *((volatile unsigned int*)(0x42C00E68UL)) +#define bFM3_DMAC_DMACA6_IS4 *((volatile unsigned int*)(0x42C00E6CUL)) +#define bFM3_DMAC_DMACA6_IS5 *((volatile unsigned int*)(0x42C00E70UL)) +#define bFM3_DMAC_DMACA6_ST *((volatile unsigned int*)(0x42C00E74UL)) +#define bFM3_DMAC_DMACA6_PB *((volatile unsigned int*)(0x42C00E78UL)) +#define bFM3_DMAC_DMACA6_EB *((volatile unsigned int*)(0x42C00E7CUL)) +#define bFM3_DMAC_DMACB6_EM *((volatile unsigned int*)(0x42C00E80UL)) +#define bFM3_DMAC_DMACB6_SS0 *((volatile unsigned int*)(0x42C00EC0UL)) +#define bFM3_DMAC_DMACB6_SS1 *((volatile unsigned int*)(0x42C00EC4UL)) +#define bFM3_DMAC_DMACB6_SS2 *((volatile unsigned int*)(0x42C00EC8UL)) +#define bFM3_DMAC_DMACB6_CI *((volatile unsigned int*)(0x42C00ECCUL)) +#define bFM3_DMAC_DMACB6_EI *((volatile unsigned int*)(0x42C00ED0UL)) +#define bFM3_DMAC_DMACB6_RD *((volatile unsigned int*)(0x42C00ED4UL)) +#define bFM3_DMAC_DMACB6_RS *((volatile unsigned int*)(0x42C00ED8UL)) +#define bFM3_DMAC_DMACB6_RC *((volatile unsigned int*)(0x42C00EDCUL)) +#define bFM3_DMAC_DMACB6_FD *((volatile unsigned int*)(0x42C00EE0UL)) +#define bFM3_DMAC_DMACB6_FS *((volatile unsigned int*)(0x42C00EE4UL)) +#define bFM3_DMAC_DMACB6_TW0 *((volatile unsigned int*)(0x42C00EE8UL)) +#define bFM3_DMAC_DMACB6_TW1 *((volatile unsigned int*)(0x42C00EECUL)) +#define bFM3_DMAC_DMACB6_MS0 *((volatile unsigned int*)(0x42C00EF0UL)) +#define bFM3_DMAC_DMACB6_MS1 *((volatile unsigned int*)(0x42C00EF4UL)) +#define bFM3_DMAC_DMACA7_TC0 *((volatile unsigned int*)(0x42C01000UL)) +#define bFM3_DMAC_DMACA7_TC1 *((volatile unsigned int*)(0x42C01004UL)) +#define bFM3_DMAC_DMACA7_TC2 *((volatile unsigned int*)(0x42C01008UL)) +#define bFM3_DMAC_DMACA7_TC3 *((volatile unsigned int*)(0x42C0100CUL)) +#define bFM3_DMAC_DMACA7_TC4 *((volatile unsigned int*)(0x42C01010UL)) +#define bFM3_DMAC_DMACA7_TC5 *((volatile unsigned int*)(0x42C01014UL)) +#define bFM3_DMAC_DMACA7_TC6 *((volatile unsigned int*)(0x42C01018UL)) +#define bFM3_DMAC_DMACA7_TC7 *((volatile unsigned int*)(0x42C0101CUL)) +#define bFM3_DMAC_DMACA7_TC8 *((volatile unsigned int*)(0x42C01020UL)) +#define bFM3_DMAC_DMACA7_TC9 *((volatile unsigned int*)(0x42C01024UL)) +#define bFM3_DMAC_DMACA7_TC10 *((volatile unsigned int*)(0x42C01028UL)) +#define bFM3_DMAC_DMACA7_TC11 *((volatile unsigned int*)(0x42C0102CUL)) +#define bFM3_DMAC_DMACA7_TC12 *((volatile unsigned int*)(0x42C01030UL)) +#define bFM3_DMAC_DMACA7_TC13 *((volatile unsigned int*)(0x42C01034UL)) +#define bFM3_DMAC_DMACA7_TC14 *((volatile unsigned int*)(0x42C01038UL)) +#define bFM3_DMAC_DMACA7_TC15 *((volatile unsigned int*)(0x42C0103CUL)) +#define bFM3_DMAC_DMACA7_BC0 *((volatile unsigned int*)(0x42C01040UL)) +#define bFM3_DMAC_DMACA7_BC1 *((volatile unsigned int*)(0x42C01044UL)) +#define bFM3_DMAC_DMACA7_BC2 *((volatile unsigned int*)(0x42C01048UL)) +#define bFM3_DMAC_DMACA7_BC3 *((volatile unsigned int*)(0x42C0104CUL)) +#define bFM3_DMAC_DMACA7_IS0 *((volatile unsigned int*)(0x42C0105CUL)) +#define bFM3_DMAC_DMACA7_IS1 *((volatile unsigned int*)(0x42C01060UL)) +#define bFM3_DMAC_DMACA7_IS2 *((volatile unsigned int*)(0x42C01064UL)) +#define bFM3_DMAC_DMACA7_IS3 *((volatile unsigned int*)(0x42C01068UL)) +#define bFM3_DMAC_DMACA7_IS4 *((volatile unsigned int*)(0x42C0106CUL)) +#define bFM3_DMAC_DMACA7_IS5 *((volatile unsigned int*)(0x42C01070UL)) +#define bFM3_DMAC_DMACA7_ST *((volatile unsigned int*)(0x42C01074UL)) +#define bFM3_DMAC_DMACA7_PB *((volatile unsigned int*)(0x42C01078UL)) +#define bFM3_DMAC_DMACA7_EB *((volatile unsigned int*)(0x42C0107CUL)) +#define bFM3_DMAC_DMACB7_EM *((volatile unsigned int*)(0x42C01080UL)) +#define bFM3_DMAC_DMACB7_SS0 *((volatile unsigned int*)(0x42C010C0UL)) +#define bFM3_DMAC_DMACB7_SS1 *((volatile unsigned int*)(0x42C010C4UL)) +#define bFM3_DMAC_DMACB7_SS2 *((volatile unsigned int*)(0x42C010C8UL)) +#define bFM3_DMAC_DMACB7_CI *((volatile unsigned int*)(0x42C010CCUL)) +#define bFM3_DMAC_DMACB7_EI *((volatile unsigned int*)(0x42C010D0UL)) +#define bFM3_DMAC_DMACB7_RD *((volatile unsigned int*)(0x42C010D4UL)) +#define bFM3_DMAC_DMACB7_RS *((volatile unsigned int*)(0x42C010D8UL)) +#define bFM3_DMAC_DMACB7_RC *((volatile unsigned int*)(0x42C010DCUL)) +#define bFM3_DMAC_DMACB7_FD *((volatile unsigned int*)(0x42C010E0UL)) +#define bFM3_DMAC_DMACB7_FS *((volatile unsigned int*)(0x42C010E4UL)) +#define bFM3_DMAC_DMACB7_TW0 *((volatile unsigned int*)(0x42C010E8UL)) +#define bFM3_DMAC_DMACB7_TW1 *((volatile unsigned int*)(0x42C010ECUL)) +#define bFM3_DMAC_DMACB7_MS0 *((volatile unsigned int*)(0x42C010F0UL)) +#define bFM3_DMAC_DMACB7_MS1 *((volatile unsigned int*)(0x42C010F4UL)) + +/* CAN channel 0 registers */ +#define bFM3_CAN0_CTRLR_INIT *((volatile unsigned int*)(0x42C40000UL)) +#define bFM3_CAN0_CTRLR_IE *((volatile unsigned int*)(0x42C40004UL)) +#define bFM3_CAN0_CTRLR_SIE *((volatile unsigned int*)(0x42C40008UL)) +#define bFM3_CAN0_CTRLR_EIE *((volatile unsigned int*)(0x42C4000CUL)) +#define bFM3_CAN0_CTRLR_DAR *((volatile unsigned int*)(0x42C40014UL)) +#define bFM3_CAN0_CTRLR_CCE *((volatile unsigned int*)(0x42C40018UL)) +#define bFM3_CAN0_CTRLR_TEST *((volatile unsigned int*)(0x42C4001CUL)) +#define bFM3_CAN0_STATR_LEC0 *((volatile unsigned int*)(0x42C40040UL)) +#define bFM3_CAN0_STATR_LEC1 *((volatile unsigned int*)(0x42C40044UL)) +#define bFM3_CAN0_STATR_LEC2 *((volatile unsigned int*)(0x42C40048UL)) +#define bFM3_CAN0_STATR_TXOK *((volatile unsigned int*)(0x42C4004CUL)) +#define bFM3_CAN0_STATR_RXOK *((volatile unsigned int*)(0x42C40050UL)) +#define bFM3_CAN0_STATR_EPASS *((volatile unsigned int*)(0x42C40054UL)) +#define bFM3_CAN0_STATR_EWARM *((volatile unsigned int*)(0x42C40058UL)) +#define bFM3_CAN0_STATR_BOFF *((volatile unsigned int*)(0x42C4005CUL)) +#define bFM3_CAN0_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C40080UL)) +#define bFM3_CAN0_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C40084UL)) +#define bFM3_CAN0_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C40088UL)) +#define bFM3_CAN0_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C4008CUL)) +#define bFM3_CAN0_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C40090UL)) +#define bFM3_CAN0_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C40094UL)) +#define bFM3_CAN0_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C40098UL)) +#define bFM3_CAN0_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C4009CUL)) +#define bFM3_CAN0_ERRCNT_REC0 *((volatile unsigned int*)(0x42C400A0UL)) +#define bFM3_CAN0_ERRCNT_REC1 *((volatile unsigned int*)(0x42C400A4UL)) +#define bFM3_CAN0_ERRCNT_REC2 *((volatile unsigned int*)(0x42C400A8UL)) +#define bFM3_CAN0_ERRCNT_REC3 *((volatile unsigned int*)(0x42C400ACUL)) +#define bFM3_CAN0_ERRCNT_REC4 *((volatile unsigned int*)(0x42C400B0UL)) +#define bFM3_CAN0_ERRCNT_REC5 *((volatile unsigned int*)(0x42C400B4UL)) +#define bFM3_CAN0_ERRCNT_REC6 *((volatile unsigned int*)(0x42C400B8UL)) +#define bFM3_CAN0_ERRCNT_RP *((volatile unsigned int*)(0x42C400BCUL)) +#define bFM3_CAN0_BTR_BRP0 *((volatile unsigned int*)(0x42C400C0UL)) +#define bFM3_CAN0_BTR_BRP1 *((volatile unsigned int*)(0x42C400C4UL)) +#define bFM3_CAN0_BTR_BRP2 *((volatile unsigned int*)(0x42C400C8UL)) +#define bFM3_CAN0_BTR_BRP3 *((volatile unsigned int*)(0x42C400CCUL)) +#define bFM3_CAN0_BTR_BRP4 *((volatile unsigned int*)(0x42C400D0UL)) +#define bFM3_CAN0_BTR_BRP5 *((volatile unsigned int*)(0x42C400D4UL)) +#define bFM3_CAN0_BTR_SJW0 *((volatile unsigned int*)(0x42C400D8UL)) +#define bFM3_CAN0_BTR_SJW1 *((volatile unsigned int*)(0x42C400DCUL)) +#define bFM3_CAN0_BTR_TSEG10 *((volatile unsigned int*)(0x42C400E0UL)) +#define bFM3_CAN0_BTR_TSEG11 *((volatile unsigned int*)(0x42C400E4UL)) +#define bFM3_CAN0_BTR_TSEG12 *((volatile unsigned int*)(0x42C400E8UL)) +#define bFM3_CAN0_BTR_TSEG13 *((volatile unsigned int*)(0x42C400ECUL)) +#define bFM3_CAN0_BTR_TSEG20 *((volatile unsigned int*)(0x42C400F0UL)) +#define bFM3_CAN0_BTR_TSEG21 *((volatile unsigned int*)(0x42C400F4UL)) +#define bFM3_CAN0_BTR_TSEG22 *((volatile unsigned int*)(0x42C400F8UL)) +#define bFM3_CAN0_INTR_INTID0 *((volatile unsigned int*)(0x42C40100UL)) +#define bFM3_CAN0_INTR_INTID1 *((volatile unsigned int*)(0x42C40104UL)) +#define bFM3_CAN0_INTR_INTID2 *((volatile unsigned int*)(0x42C40108UL)) +#define bFM3_CAN0_INTR_INTID3 *((volatile unsigned int*)(0x42C4010CUL)) +#define bFM3_CAN0_INTR_INTID4 *((volatile unsigned int*)(0x42C40110UL)) +#define bFM3_CAN0_INTR_INTID5 *((volatile unsigned int*)(0x42C40114UL)) +#define bFM3_CAN0_INTR_INTID6 *((volatile unsigned int*)(0x42C40118UL)) +#define bFM3_CAN0_INTR_INTID7 *((volatile unsigned int*)(0x42C4011CUL)) +#define bFM3_CAN0_INTR_INTID8 *((volatile unsigned int*)(0x42C40120UL)) +#define bFM3_CAN0_INTR_INTID9 *((volatile unsigned int*)(0x42C40124UL)) +#define bFM3_CAN0_INTR_INTID10 *((volatile unsigned int*)(0x42C40128UL)) +#define bFM3_CAN0_INTR_INTID11 *((volatile unsigned int*)(0x42C4012CUL)) +#define bFM3_CAN0_INTR_INTID12 *((volatile unsigned int*)(0x42C40130UL)) +#define bFM3_CAN0_INTR_INTID13 *((volatile unsigned int*)(0x42C40134UL)) +#define bFM3_CAN0_INTR_INTID14 *((volatile unsigned int*)(0x42C40138UL)) +#define bFM3_CAN0_INTR_INTID15 *((volatile unsigned int*)(0x42C4013CUL)) +#define bFM3_CAN0_TESTR_BASIC *((volatile unsigned int*)(0x42C40148UL)) +#define bFM3_CAN0_TESTR_SILENT *((volatile unsigned int*)(0x42C4014CUL)) +#define bFM3_CAN0_TESTR_LBACK *((volatile unsigned int*)(0x42C40150UL)) +#define bFM3_CAN0_TESTR_TX0 *((volatile unsigned int*)(0x42C40154UL)) +#define bFM3_CAN0_TESTR_TX1 *((volatile unsigned int*)(0x42C40158UL)) +#define bFM3_CAN0_TESTR_RX *((volatile unsigned int*)(0x42C4015CUL)) +#define bFM3_CAN0_BRPER_BRPE0 *((volatile unsigned int*)(0x42C40180UL)) +#define bFM3_CAN0_BRPER_BRPE1 *((volatile unsigned int*)(0x42C40184UL)) +#define bFM3_CAN0_BRPER_BRPE2 *((volatile unsigned int*)(0x42C40188UL)) +#define bFM3_CAN0_BRPER_BRPE3 *((volatile unsigned int*)(0x42C4018CUL)) +#define bFM3_CAN0_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C4023CUL)) +#define bFM3_CAN0_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C40240UL)) +#define bFM3_CAN0_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C40244UL)) +#define bFM3_CAN0_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C40248UL)) +#define bFM3_CAN0_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C40248UL)) +#define bFM3_CAN0_IF1CMSK_CIP *((volatile unsigned int*)(0x42C4024CUL)) +#define bFM3_CAN0_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C40250UL)) +#define bFM3_CAN0_IF1CMSK_ARB *((volatile unsigned int*)(0x42C40254UL)) +#define bFM3_CAN0_IF1CMSK_MASK *((volatile unsigned int*)(0x42C40258UL)) +#define bFM3_CAN0_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C4025CUL)) +#define bFM3_CAN0_IF1MSK_MDIR *((volatile unsigned int*)(0x42C402F8UL)) +#define bFM3_CAN0_IF1MSK_MXTD *((volatile unsigned int*)(0x42C402FCUL)) +#define bFM3_CAN0_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C402F8UL)) +#define bFM3_CAN0_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C402FCUL)) +#define bFM3_CAN0_IF1ARB_DIR *((volatile unsigned int*)(0x42C40374UL)) +#define bFM3_CAN0_IF1ARB_XTD *((volatile unsigned int*)(0x42C40378UL)) +#define bFM3_CAN0_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) +#define bFM3_CAN0_IF1ARB2_DIR *((volatile unsigned int*)(0x42C40374UL)) +#define bFM3_CAN0_IF1ARB2_XTD *((volatile unsigned int*)(0x42C40378UL)) +#define bFM3_CAN0_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C4037CUL)) +#define bFM3_CAN0_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C40380UL)) +#define bFM3_CAN0_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C40384UL)) +#define bFM3_CAN0_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C40388UL)) +#define bFM3_CAN0_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C4038CUL)) +#define bFM3_CAN0_IF1MCTR_EOB *((volatile unsigned int*)(0x42C4039CUL)) +#define bFM3_CAN0_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C403A0UL)) +#define bFM3_CAN0_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C403A4UL)) +#define bFM3_CAN0_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C403A8UL)) +#define bFM3_CAN0_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C403ACUL)) +#define bFM3_CAN0_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C403B0UL)) +#define bFM3_CAN0_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C403B4UL)) +#define bFM3_CAN0_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C403B8UL)) +#define bFM3_CAN0_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C403BCUL)) +#define bFM3_CAN0_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C4083CUL)) +#define bFM3_CAN0_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C40840UL)) +#define bFM3_CAN0_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C40844UL)) +#define bFM3_CAN0_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C40848UL)) +#define bFM3_CAN0_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C40848UL)) +#define bFM3_CAN0_IF2CMSK_CIP *((volatile unsigned int*)(0x42C4084CUL)) +#define bFM3_CAN0_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C40850UL)) +#define bFM3_CAN0_IF2CMSK_ARB *((volatile unsigned int*)(0x42C40854UL)) +#define bFM3_CAN0_IF2CMSK_MASK *((volatile unsigned int*)(0x42C40858UL)) +#define bFM3_CAN0_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C4085CUL)) +#define bFM3_CAN0_IF2MSK_MDIR *((volatile unsigned int*)(0x42C408F8UL)) +#define bFM3_CAN0_IF2MSK_MXTD *((volatile unsigned int*)(0x42C408FCUL)) +#define bFM3_CAN0_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C408F8UL)) +#define bFM3_CAN0_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C408FCUL)) +#define bFM3_CAN0_IF2ARB_DIR *((volatile unsigned int*)(0x42C40974UL)) +#define bFM3_CAN0_IF2ARB_XTD *((volatile unsigned int*)(0x42C40978UL)) +#define bFM3_CAN0_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) +#define bFM3_CAN0_IF2ARB2_DIR *((volatile unsigned int*)(0x42C40974UL)) +#define bFM3_CAN0_IF2ARB2_XTD *((volatile unsigned int*)(0x42C40978UL)) +#define bFM3_CAN0_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C4097CUL)) +#define bFM3_CAN0_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C40980UL)) +#define bFM3_CAN0_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C40984UL)) +#define bFM3_CAN0_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C40988UL)) +#define bFM3_CAN0_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C4098CUL)) +#define bFM3_CAN0_IF2MCTR_EOB *((volatile unsigned int*)(0x42C4099CUL)) +#define bFM3_CAN0_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C409A0UL)) +#define bFM3_CAN0_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C409A4UL)) +#define bFM3_CAN0_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C409A8UL)) +#define bFM3_CAN0_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C409ACUL)) +#define bFM3_CAN0_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C409B0UL)) +#define bFM3_CAN0_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C409B4UL)) +#define bFM3_CAN0_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C409B8UL)) +#define bFM3_CAN0_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C409BCUL)) +#define bFM3_CAN0_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) +#define bFM3_CAN0_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) +#define bFM3_CAN0_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) +#define bFM3_CAN0_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) +#define bFM3_CAN0_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) +#define bFM3_CAN0_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) +#define bFM3_CAN0_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) +#define bFM3_CAN0_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) +#define bFM3_CAN0_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) +#define bFM3_CAN0_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) +#define bFM3_CAN0_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) +#define bFM3_CAN0_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) +#define bFM3_CAN0_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) +#define bFM3_CAN0_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) +#define bFM3_CAN0_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) +#define bFM3_CAN0_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) +#define bFM3_CAN0_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) +#define bFM3_CAN0_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) +#define bFM3_CAN0_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) +#define bFM3_CAN0_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) +#define bFM3_CAN0_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) +#define bFM3_CAN0_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) +#define bFM3_CAN0_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) +#define bFM3_CAN0_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) +#define bFM3_CAN0_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) +#define bFM3_CAN0_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) +#define bFM3_CAN0_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) +#define bFM3_CAN0_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) +#define bFM3_CAN0_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) +#define bFM3_CAN0_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) +#define bFM3_CAN0_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) +#define bFM3_CAN0_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) +#define bFM3_CAN0_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C41000UL)) +#define bFM3_CAN0_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C41004UL)) +#define bFM3_CAN0_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C41008UL)) +#define bFM3_CAN0_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C4100CUL)) +#define bFM3_CAN0_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C41010UL)) +#define bFM3_CAN0_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C41014UL)) +#define bFM3_CAN0_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C41018UL)) +#define bFM3_CAN0_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C4101CUL)) +#define bFM3_CAN0_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C41020UL)) +#define bFM3_CAN0_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C41024UL)) +#define bFM3_CAN0_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C41028UL)) +#define bFM3_CAN0_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C4102CUL)) +#define bFM3_CAN0_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C41030UL)) +#define bFM3_CAN0_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C41034UL)) +#define bFM3_CAN0_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C41038UL)) +#define bFM3_CAN0_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C4103CUL)) +#define bFM3_CAN0_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C41040UL)) +#define bFM3_CAN0_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C41044UL)) +#define bFM3_CAN0_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C41048UL)) +#define bFM3_CAN0_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C4104CUL)) +#define bFM3_CAN0_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C41050UL)) +#define bFM3_CAN0_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C41054UL)) +#define bFM3_CAN0_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C41058UL)) +#define bFM3_CAN0_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C4105CUL)) +#define bFM3_CAN0_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C41060UL)) +#define bFM3_CAN0_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C41064UL)) +#define bFM3_CAN0_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C41068UL)) +#define bFM3_CAN0_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C4106CUL)) +#define bFM3_CAN0_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C41070UL)) +#define bFM3_CAN0_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C41074UL)) +#define bFM3_CAN0_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C41078UL)) +#define bFM3_CAN0_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C4107CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) +#define bFM3_CAN0_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) +#define bFM3_CAN0_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) +#define bFM3_CAN0_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) +#define bFM3_CAN0_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) +#define bFM3_CAN0_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) +#define bFM3_CAN0_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) +#define bFM3_CAN0_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) +#define bFM3_CAN0_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) +#define bFM3_CAN0_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) +#define bFM3_CAN0_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) +#define bFM3_CAN0_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) +#define bFM3_CAN0_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) +#define bFM3_CAN0_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) +#define bFM3_CAN0_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) +#define bFM3_CAN0_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) +#define bFM3_CAN0_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) +#define bFM3_CAN0_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) +#define bFM3_CAN0_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) +#define bFM3_CAN0_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) +#define bFM3_CAN0_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) +#define bFM3_CAN0_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) +#define bFM3_CAN0_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) +#define bFM3_CAN0_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) +#define bFM3_CAN0_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) +#define bFM3_CAN0_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) +#define bFM3_CAN0_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C41200UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C41204UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C41208UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C4120CUL)) +#define bFM3_CAN0_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C41210UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C41214UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C41218UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C4121CUL)) +#define bFM3_CAN0_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C41220UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C41224UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C41228UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C4122CUL)) +#define bFM3_CAN0_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C41230UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C41234UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C41238UL)) +#define bFM3_CAN0_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C4123CUL)) +#define bFM3_CAN0_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C41240UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C41244UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C41248UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C4124CUL)) +#define bFM3_CAN0_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C41250UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C41254UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C41258UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C4125CUL)) +#define bFM3_CAN0_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C41260UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C41264UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C41268UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C4126CUL)) +#define bFM3_CAN0_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C41270UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C41274UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C41278UL)) +#define bFM3_CAN0_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C4127CUL)) +#define bFM3_CAN0_INTPND_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) +#define bFM3_CAN0_INTPND_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) +#define bFM3_CAN0_INTPND_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) +#define bFM3_CAN0_INTPND_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) +#define bFM3_CAN0_INTPND_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) +#define bFM3_CAN0_INTPND_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) +#define bFM3_CAN0_INTPND_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) +#define bFM3_CAN0_INTPND_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) +#define bFM3_CAN0_INTPND_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) +#define bFM3_CAN0_INTPND_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) +#define bFM3_CAN0_INTPND_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) +#define bFM3_CAN0_INTPND_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) +#define bFM3_CAN0_INTPND_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) +#define bFM3_CAN0_INTPND_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) +#define bFM3_CAN0_INTPND_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) +#define bFM3_CAN0_INTPND_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) +#define bFM3_CAN0_INTPND_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) +#define bFM3_CAN0_INTPND_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) +#define bFM3_CAN0_INTPND_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) +#define bFM3_CAN0_INTPND_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) +#define bFM3_CAN0_INTPND_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) +#define bFM3_CAN0_INTPND_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) +#define bFM3_CAN0_INTPND_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) +#define bFM3_CAN0_INTPND_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) +#define bFM3_CAN0_INTPND_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) +#define bFM3_CAN0_INTPND_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) +#define bFM3_CAN0_INTPND_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) +#define bFM3_CAN0_INTPND_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) +#define bFM3_CAN0_INTPND_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) +#define bFM3_CAN0_INTPND_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) +#define bFM3_CAN0_INTPND_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) +#define bFM3_CAN0_INTPND_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) +#define bFM3_CAN0_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C41400UL)) +#define bFM3_CAN0_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C41404UL)) +#define bFM3_CAN0_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C41408UL)) +#define bFM3_CAN0_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C4140CUL)) +#define bFM3_CAN0_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C41410UL)) +#define bFM3_CAN0_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C41414UL)) +#define bFM3_CAN0_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C41418UL)) +#define bFM3_CAN0_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C4141CUL)) +#define bFM3_CAN0_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C41420UL)) +#define bFM3_CAN0_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C41424UL)) +#define bFM3_CAN0_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C41428UL)) +#define bFM3_CAN0_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C4142CUL)) +#define bFM3_CAN0_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C41430UL)) +#define bFM3_CAN0_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C41434UL)) +#define bFM3_CAN0_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C41438UL)) +#define bFM3_CAN0_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C4143CUL)) +#define bFM3_CAN0_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C41440UL)) +#define bFM3_CAN0_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C41444UL)) +#define bFM3_CAN0_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C41448UL)) +#define bFM3_CAN0_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C4144CUL)) +#define bFM3_CAN0_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C41450UL)) +#define bFM3_CAN0_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C41454UL)) +#define bFM3_CAN0_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C41458UL)) +#define bFM3_CAN0_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C4145CUL)) +#define bFM3_CAN0_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C41460UL)) +#define bFM3_CAN0_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C41464UL)) +#define bFM3_CAN0_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C41468UL)) +#define bFM3_CAN0_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C4146CUL)) +#define bFM3_CAN0_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C41470UL)) +#define bFM3_CAN0_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C41474UL)) +#define bFM3_CAN0_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C41478UL)) +#define bFM3_CAN0_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C4147CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) +#define bFM3_CAN0_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) +#define bFM3_CAN0_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C41600UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C41604UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C41608UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C4160CUL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C41610UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C41614UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C41618UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C4161CUL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C41620UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C41624UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C41628UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C4162CUL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C41630UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C41634UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C41638UL)) +#define bFM3_CAN0_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C4163CUL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C41640UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C41644UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C41648UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C4164CUL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C41650UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C41654UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C41658UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C4165CUL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C41660UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C41664UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C41668UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C4166CUL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C41670UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C41674UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C41678UL)) +#define bFM3_CAN0_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C4167CUL)) + +/* CAN channel 1 registers */ +#define bFM3_CAN1_CTRLR_INIT *((volatile unsigned int*)(0x42C60000UL)) +#define bFM3_CAN1_CTRLR_IE *((volatile unsigned int*)(0x42C60004UL)) +#define bFM3_CAN1_CTRLR_SIE *((volatile unsigned int*)(0x42C60008UL)) +#define bFM3_CAN1_CTRLR_EIE *((volatile unsigned int*)(0x42C6000CUL)) +#define bFM3_CAN1_CTRLR_DAR *((volatile unsigned int*)(0x42C60014UL)) +#define bFM3_CAN1_CTRLR_CCE *((volatile unsigned int*)(0x42C60018UL)) +#define bFM3_CAN1_CTRLR_TEST *((volatile unsigned int*)(0x42C6001CUL)) +#define bFM3_CAN1_STATR_LEC0 *((volatile unsigned int*)(0x42C60040UL)) +#define bFM3_CAN1_STATR_LEC1 *((volatile unsigned int*)(0x42C60044UL)) +#define bFM3_CAN1_STATR_LEC2 *((volatile unsigned int*)(0x42C60048UL)) +#define bFM3_CAN1_STATR_TXOK *((volatile unsigned int*)(0x42C6004CUL)) +#define bFM3_CAN1_STATR_RXOK *((volatile unsigned int*)(0x42C60050UL)) +#define bFM3_CAN1_STATR_EPASS *((volatile unsigned int*)(0x42C60054UL)) +#define bFM3_CAN1_STATR_EWARM *((volatile unsigned int*)(0x42C60058UL)) +#define bFM3_CAN1_STATR_BOFF *((volatile unsigned int*)(0x42C6005CUL)) +#define bFM3_CAN1_ERRCNT_TEC0 *((volatile unsigned int*)(0x42C60080UL)) +#define bFM3_CAN1_ERRCNT_TEC1 *((volatile unsigned int*)(0x42C60084UL)) +#define bFM3_CAN1_ERRCNT_TEC2 *((volatile unsigned int*)(0x42C60088UL)) +#define bFM3_CAN1_ERRCNT_TEC3 *((volatile unsigned int*)(0x42C6008CUL)) +#define bFM3_CAN1_ERRCNT_TEC4 *((volatile unsigned int*)(0x42C60090UL)) +#define bFM3_CAN1_ERRCNT_TEC5 *((volatile unsigned int*)(0x42C60094UL)) +#define bFM3_CAN1_ERRCNT_TEC6 *((volatile unsigned int*)(0x42C60098UL)) +#define bFM3_CAN1_ERRCNT_TEC7 *((volatile unsigned int*)(0x42C6009CUL)) +#define bFM3_CAN1_ERRCNT_REC0 *((volatile unsigned int*)(0x42C600A0UL)) +#define bFM3_CAN1_ERRCNT_REC1 *((volatile unsigned int*)(0x42C600A4UL)) +#define bFM3_CAN1_ERRCNT_REC2 *((volatile unsigned int*)(0x42C600A8UL)) +#define bFM3_CAN1_ERRCNT_REC3 *((volatile unsigned int*)(0x42C600ACUL)) +#define bFM3_CAN1_ERRCNT_REC4 *((volatile unsigned int*)(0x42C600B0UL)) +#define bFM3_CAN1_ERRCNT_REC5 *((volatile unsigned int*)(0x42C600B4UL)) +#define bFM3_CAN1_ERRCNT_REC6 *((volatile unsigned int*)(0x42C600B8UL)) +#define bFM3_CAN1_ERRCNT_RP *((volatile unsigned int*)(0x42C600BCUL)) +#define bFM3_CAN1_BTR_BRP0 *((volatile unsigned int*)(0x42C600C0UL)) +#define bFM3_CAN1_BTR_BRP1 *((volatile unsigned int*)(0x42C600C4UL)) +#define bFM3_CAN1_BTR_BRP2 *((volatile unsigned int*)(0x42C600C8UL)) +#define bFM3_CAN1_BTR_BRP3 *((volatile unsigned int*)(0x42C600CCUL)) +#define bFM3_CAN1_BTR_BRP4 *((volatile unsigned int*)(0x42C600D0UL)) +#define bFM3_CAN1_BTR_BRP5 *((volatile unsigned int*)(0x42C600D4UL)) +#define bFM3_CAN1_BTR_SJW0 *((volatile unsigned int*)(0x42C600D8UL)) +#define bFM3_CAN1_BTR_SJW1 *((volatile unsigned int*)(0x42C600DCUL)) +#define bFM3_CAN1_BTR_TSEG10 *((volatile unsigned int*)(0x42C600E0UL)) +#define bFM3_CAN1_BTR_TSEG11 *((volatile unsigned int*)(0x42C600E4UL)) +#define bFM3_CAN1_BTR_TSEG12 *((volatile unsigned int*)(0x42C600E8UL)) +#define bFM3_CAN1_BTR_TSEG13 *((volatile unsigned int*)(0x42C600ECUL)) +#define bFM3_CAN1_BTR_TSEG20 *((volatile unsigned int*)(0x42C600F0UL)) +#define bFM3_CAN1_BTR_TSEG21 *((volatile unsigned int*)(0x42C600F4UL)) +#define bFM3_CAN1_BTR_TSEG22 *((volatile unsigned int*)(0x42C600F8UL)) +#define bFM3_CAN1_INTR_INTID0 *((volatile unsigned int*)(0x42C60100UL)) +#define bFM3_CAN1_INTR_INTID1 *((volatile unsigned int*)(0x42C60104UL)) +#define bFM3_CAN1_INTR_INTID2 *((volatile unsigned int*)(0x42C60108UL)) +#define bFM3_CAN1_INTR_INTID3 *((volatile unsigned int*)(0x42C6010CUL)) +#define bFM3_CAN1_INTR_INTID4 *((volatile unsigned int*)(0x42C60110UL)) +#define bFM3_CAN1_INTR_INTID5 *((volatile unsigned int*)(0x42C60114UL)) +#define bFM3_CAN1_INTR_INTID6 *((volatile unsigned int*)(0x42C60118UL)) +#define bFM3_CAN1_INTR_INTID7 *((volatile unsigned int*)(0x42C6011CUL)) +#define bFM3_CAN1_INTR_INTID8 *((volatile unsigned int*)(0x42C60120UL)) +#define bFM3_CAN1_INTR_INTID9 *((volatile unsigned int*)(0x42C60124UL)) +#define bFM3_CAN1_INTR_INTID10 *((volatile unsigned int*)(0x42C60128UL)) +#define bFM3_CAN1_INTR_INTID11 *((volatile unsigned int*)(0x42C6012CUL)) +#define bFM3_CAN1_INTR_INTID12 *((volatile unsigned int*)(0x42C60130UL)) +#define bFM3_CAN1_INTR_INTID13 *((volatile unsigned int*)(0x42C60134UL)) +#define bFM3_CAN1_INTR_INTID14 *((volatile unsigned int*)(0x42C60138UL)) +#define bFM3_CAN1_INTR_INTID15 *((volatile unsigned int*)(0x42C6013CUL)) +#define bFM3_CAN1_TESTR_BASIC *((volatile unsigned int*)(0x42C60148UL)) +#define bFM3_CAN1_TESTR_SILENT *((volatile unsigned int*)(0x42C6014CUL)) +#define bFM3_CAN1_TESTR_LBACK *((volatile unsigned int*)(0x42C60150UL)) +#define bFM3_CAN1_TESTR_TX0 *((volatile unsigned int*)(0x42C60154UL)) +#define bFM3_CAN1_TESTR_TX1 *((volatile unsigned int*)(0x42C60158UL)) +#define bFM3_CAN1_TESTR_RX *((volatile unsigned int*)(0x42C6015CUL)) +#define bFM3_CAN1_BRPER_BRPE0 *((volatile unsigned int*)(0x42C60180UL)) +#define bFM3_CAN1_BRPER_BRPE1 *((volatile unsigned int*)(0x42C60184UL)) +#define bFM3_CAN1_BRPER_BRPE2 *((volatile unsigned int*)(0x42C60188UL)) +#define bFM3_CAN1_BRPER_BRPE3 *((volatile unsigned int*)(0x42C6018CUL)) +#define bFM3_CAN1_IF1CREQ_BUSY *((volatile unsigned int*)(0x42C6023CUL)) +#define bFM3_CAN1_IF1CMSK_DATAB *((volatile unsigned int*)(0x42C60240UL)) +#define bFM3_CAN1_IF1CMSK_DATAA *((volatile unsigned int*)(0x42C60244UL)) +#define bFM3_CAN1_IF1CMSK_TXREST *((volatile unsigned int*)(0x42C60248UL)) +#define bFM3_CAN1_IF1CMSK_NEWDAT *((volatile unsigned int*)(0x42C60248UL)) +#define bFM3_CAN1_IF1CMSK_CIP *((volatile unsigned int*)(0x42C6024CUL)) +#define bFM3_CAN1_IF1CMSK_CONTROL *((volatile unsigned int*)(0x42C60250UL)) +#define bFM3_CAN1_IF1CMSK_ARB *((volatile unsigned int*)(0x42C60254UL)) +#define bFM3_CAN1_IF1CMSK_MASK *((volatile unsigned int*)(0x42C60258UL)) +#define bFM3_CAN1_IF1CMSK_WRRD *((volatile unsigned int*)(0x42C6025CUL)) +#define bFM3_CAN1_IF1MSK_MDIR *((volatile unsigned int*)(0x42C602F8UL)) +#define bFM3_CAN1_IF1MSK_MXTD *((volatile unsigned int*)(0x42C602FCUL)) +#define bFM3_CAN1_IF1MSK2_MDIR *((volatile unsigned int*)(0x42C602F8UL)) +#define bFM3_CAN1_IF1MSK2_MXTD *((volatile unsigned int*)(0x42C602FCUL)) +#define bFM3_CAN1_IF1ARB_DIR *((volatile unsigned int*)(0x42C60374UL)) +#define bFM3_CAN1_IF1ARB_XTD *((volatile unsigned int*)(0x42C60378UL)) +#define bFM3_CAN1_IF1ARB_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) +#define bFM3_CAN1_IF1ARB2_DIR *((volatile unsigned int*)(0x42C60374UL)) +#define bFM3_CAN1_IF1ARB2_XTD *((volatile unsigned int*)(0x42C60378UL)) +#define bFM3_CAN1_IF1ARB2_MSGVAL *((volatile unsigned int*)(0x42C6037CUL)) +#define bFM3_CAN1_IF1MCTR_DLC0 *((volatile unsigned int*)(0x42C60380UL)) +#define bFM3_CAN1_IF1MCTR_DLC1 *((volatile unsigned int*)(0x42C60384UL)) +#define bFM3_CAN1_IF1MCTR_DLC2 *((volatile unsigned int*)(0x42C60388UL)) +#define bFM3_CAN1_IF1MCTR_DLC3 *((volatile unsigned int*)(0x42C6038CUL)) +#define bFM3_CAN1_IF1MCTR_EOB *((volatile unsigned int*)(0x42C6039CUL)) +#define bFM3_CAN1_IF1MCTR_TXRQST *((volatile unsigned int*)(0x42C603A0UL)) +#define bFM3_CAN1_IF1MCTR_RMTEN *((volatile unsigned int*)(0x42C603A4UL)) +#define bFM3_CAN1_IF1MCTR_RXIE *((volatile unsigned int*)(0x42C603A8UL)) +#define bFM3_CAN1_IF1MCTR_TXIE *((volatile unsigned int*)(0x42C603ACUL)) +#define bFM3_CAN1_IF1MCTR_UMASK *((volatile unsigned int*)(0x42C603B0UL)) +#define bFM3_CAN1_IF1MCTR_INTPND *((volatile unsigned int*)(0x42C603B4UL)) +#define bFM3_CAN1_IF1MCTR_MSGLST *((volatile unsigned int*)(0x42C603B8UL)) +#define bFM3_CAN1_IF1MCTR_NEWDAT *((volatile unsigned int*)(0x42C603BCUL)) +#define bFM3_CAN1_IF2CREQ_BUSY *((volatile unsigned int*)(0x42C6083CUL)) +#define bFM3_CAN1_IF2CMSK_DATAB *((volatile unsigned int*)(0x42C60840UL)) +#define bFM3_CAN1_IF2CMSK_DATAA *((volatile unsigned int*)(0x42C60844UL)) +#define bFM3_CAN1_IF2CMSK_TXREST *((volatile unsigned int*)(0x42C60848UL)) +#define bFM3_CAN1_IF2CMSK_NEWDAT *((volatile unsigned int*)(0x42C60848UL)) +#define bFM3_CAN1_IF2CMSK_CIP *((volatile unsigned int*)(0x42C6084CUL)) +#define bFM3_CAN1_IF2CMSK_CONTROL *((volatile unsigned int*)(0x42C60850UL)) +#define bFM3_CAN1_IF2CMSK_ARB *((volatile unsigned int*)(0x42C60854UL)) +#define bFM3_CAN1_IF2CMSK_MASK *((volatile unsigned int*)(0x42C60858UL)) +#define bFM3_CAN1_IF2CMSK_WRRD *((volatile unsigned int*)(0x42C6085CUL)) +#define bFM3_CAN1_IF2MSK_MDIR *((volatile unsigned int*)(0x42C608F8UL)) +#define bFM3_CAN1_IF2MSK_MXTD *((volatile unsigned int*)(0x42C608FCUL)) +#define bFM3_CAN1_IF2MSK2_MDIR *((volatile unsigned int*)(0x42C608F8UL)) +#define bFM3_CAN1_IF2MSK2_MXTD *((volatile unsigned int*)(0x42C608FCUL)) +#define bFM3_CAN1_IF2ARB_DIR *((volatile unsigned int*)(0x42C60974UL)) +#define bFM3_CAN1_IF2ARB_XTD *((volatile unsigned int*)(0x42C60978UL)) +#define bFM3_CAN1_IF2ARB_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) +#define bFM3_CAN1_IF2ARB2_DIR *((volatile unsigned int*)(0x42C60974UL)) +#define bFM3_CAN1_IF2ARB2_XTD *((volatile unsigned int*)(0x42C60978UL)) +#define bFM3_CAN1_IF2ARB2_MSGVAL *((volatile unsigned int*)(0x42C6097CUL)) +#define bFM3_CAN1_IF2MCTR_DLC0 *((volatile unsigned int*)(0x42C60980UL)) +#define bFM3_CAN1_IF2MCTR_DLC1 *((volatile unsigned int*)(0x42C60984UL)) +#define bFM3_CAN1_IF2MCTR_DLC2 *((volatile unsigned int*)(0x42C60988UL)) +#define bFM3_CAN1_IF2MCTR_DLC3 *((volatile unsigned int*)(0x42C6098CUL)) +#define bFM3_CAN1_IF2MCTR_EOB *((volatile unsigned int*)(0x42C6099CUL)) +#define bFM3_CAN1_IF2MCTR_TXRQST *((volatile unsigned int*)(0x42C609A0UL)) +#define bFM3_CAN1_IF2MCTR_RMTEN *((volatile unsigned int*)(0x42C609A4UL)) +#define bFM3_CAN1_IF2MCTR_RXIE *((volatile unsigned int*)(0x42C609A8UL)) +#define bFM3_CAN1_IF2MCTR_TXIE *((volatile unsigned int*)(0x42C609ACUL)) +#define bFM3_CAN1_IF2MCTR_UMASK *((volatile unsigned int*)(0x42C609B0UL)) +#define bFM3_CAN1_IF2MCTR_INTPND *((volatile unsigned int*)(0x42C609B4UL)) +#define bFM3_CAN1_IF2MCTR_MSGLST *((volatile unsigned int*)(0x42C609B8UL)) +#define bFM3_CAN1_IF2MCTR_NEWDAT *((volatile unsigned int*)(0x42C609BCUL)) +#define bFM3_CAN1_TREQR_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) +#define bFM3_CAN1_TREQR_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) +#define bFM3_CAN1_TREQR_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) +#define bFM3_CAN1_TREQR_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) +#define bFM3_CAN1_TREQR_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) +#define bFM3_CAN1_TREQR_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) +#define bFM3_CAN1_TREQR_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) +#define bFM3_CAN1_TREQR_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) +#define bFM3_CAN1_TREQR_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) +#define bFM3_CAN1_TREQR_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) +#define bFM3_CAN1_TREQR_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) +#define bFM3_CAN1_TREQR_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) +#define bFM3_CAN1_TREQR_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) +#define bFM3_CAN1_TREQR_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) +#define bFM3_CAN1_TREQR_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) +#define bFM3_CAN1_TREQR_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) +#define bFM3_CAN1_TREQR_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) +#define bFM3_CAN1_TREQR_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) +#define bFM3_CAN1_TREQR_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) +#define bFM3_CAN1_TREQR_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) +#define bFM3_CAN1_TREQR_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) +#define bFM3_CAN1_TREQR_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) +#define bFM3_CAN1_TREQR_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) +#define bFM3_CAN1_TREQR_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) +#define bFM3_CAN1_TREQR_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) +#define bFM3_CAN1_TREQR_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) +#define bFM3_CAN1_TREQR_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) +#define bFM3_CAN1_TREQR_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) +#define bFM3_CAN1_TREQR_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) +#define bFM3_CAN1_TREQR_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) +#define bFM3_CAN1_TREQR_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) +#define bFM3_CAN1_TREQR_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) +#define bFM3_CAN1_TREQR1_TXRQST1 *((volatile unsigned int*)(0x42C61000UL)) +#define bFM3_CAN1_TREQR1_TXRQST2 *((volatile unsigned int*)(0x42C61004UL)) +#define bFM3_CAN1_TREQR1_TXRQST3 *((volatile unsigned int*)(0x42C61008UL)) +#define bFM3_CAN1_TREQR1_TXRQST4 *((volatile unsigned int*)(0x42C6100CUL)) +#define bFM3_CAN1_TREQR1_TXRQST5 *((volatile unsigned int*)(0x42C61010UL)) +#define bFM3_CAN1_TREQR1_TXRQST6 *((volatile unsigned int*)(0x42C61014UL)) +#define bFM3_CAN1_TREQR1_TXRQST7 *((volatile unsigned int*)(0x42C61018UL)) +#define bFM3_CAN1_TREQR1_TXRQST8 *((volatile unsigned int*)(0x42C6101CUL)) +#define bFM3_CAN1_TREQR1_TXRQST9 *((volatile unsigned int*)(0x42C61020UL)) +#define bFM3_CAN1_TREQR1_TXRQST10 *((volatile unsigned int*)(0x42C61024UL)) +#define bFM3_CAN1_TREQR1_TXRQST11 *((volatile unsigned int*)(0x42C61028UL)) +#define bFM3_CAN1_TREQR1_TXRQST12 *((volatile unsigned int*)(0x42C6102CUL)) +#define bFM3_CAN1_TREQR1_TXRQST13 *((volatile unsigned int*)(0x42C61030UL)) +#define bFM3_CAN1_TREQR1_TXRQST14 *((volatile unsigned int*)(0x42C61034UL)) +#define bFM3_CAN1_TREQR1_TXRQST15 *((volatile unsigned int*)(0x42C61038UL)) +#define bFM3_CAN1_TREQR1_TXRQST16 *((volatile unsigned int*)(0x42C6103CUL)) +#define bFM3_CAN1_TREQR2_TXRQST17 *((volatile unsigned int*)(0x42C61040UL)) +#define bFM3_CAN1_TREQR2_TXRQST18 *((volatile unsigned int*)(0x42C61044UL)) +#define bFM3_CAN1_TREQR2_TXRQST19 *((volatile unsigned int*)(0x42C61048UL)) +#define bFM3_CAN1_TREQR2_TXRQST20 *((volatile unsigned int*)(0x42C6104CUL)) +#define bFM3_CAN1_TREQR2_TXRQST21 *((volatile unsigned int*)(0x42C61050UL)) +#define bFM3_CAN1_TREQR2_TXRQST22 *((volatile unsigned int*)(0x42C61054UL)) +#define bFM3_CAN1_TREQR2_TXRQST23 *((volatile unsigned int*)(0x42C61058UL)) +#define bFM3_CAN1_TREQR2_TXRQST24 *((volatile unsigned int*)(0x42C6105CUL)) +#define bFM3_CAN1_TREQR2_TXRQST25 *((volatile unsigned int*)(0x42C61060UL)) +#define bFM3_CAN1_TREQR2_TXRQST26 *((volatile unsigned int*)(0x42C61064UL)) +#define bFM3_CAN1_TREQR2_TXRQST27 *((volatile unsigned int*)(0x42C61068UL)) +#define bFM3_CAN1_TREQR2_TXRQST28 *((volatile unsigned int*)(0x42C6106CUL)) +#define bFM3_CAN1_TREQR2_TXRQST29 *((volatile unsigned int*)(0x42C61070UL)) +#define bFM3_CAN1_TREQR2_TXRQST30 *((volatile unsigned int*)(0x42C61074UL)) +#define bFM3_CAN1_TREQR2_TXRQST31 *((volatile unsigned int*)(0x42C61078UL)) +#define bFM3_CAN1_TREQR2_TXRQST32 *((volatile unsigned int*)(0x42C6107CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) +#define bFM3_CAN1_NEWDT_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) +#define bFM3_CAN1_NEWDT_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) +#define bFM3_CAN1_NEWDT_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) +#define bFM3_CAN1_NEWDT_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) +#define bFM3_CAN1_NEWDT_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) +#define bFM3_CAN1_NEWDT_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) +#define bFM3_CAN1_NEWDT_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) +#define bFM3_CAN1_NEWDT_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) +#define bFM3_CAN1_NEWDT_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) +#define bFM3_CAN1_NEWDT_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) +#define bFM3_CAN1_NEWDT_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) +#define bFM3_CAN1_NEWDT_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) +#define bFM3_CAN1_NEWDT_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) +#define bFM3_CAN1_NEWDT_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) +#define bFM3_CAN1_NEWDT_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) +#define bFM3_CAN1_NEWDT_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) +#define bFM3_CAN1_NEWDT_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) +#define bFM3_CAN1_NEWDT_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) +#define bFM3_CAN1_NEWDT_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) +#define bFM3_CAN1_NEWDT_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) +#define bFM3_CAN1_NEWDT_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) +#define bFM3_CAN1_NEWDT_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) +#define bFM3_CAN1_NEWDT_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) +#define bFM3_CAN1_NEWDT_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) +#define bFM3_CAN1_NEWDT_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) +#define bFM3_CAN1_NEWDT1_NEWDAT1 *((volatile unsigned int*)(0x42C61200UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT2 *((volatile unsigned int*)(0x42C61204UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT3 *((volatile unsigned int*)(0x42C61208UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT4 *((volatile unsigned int*)(0x42C6120CUL)) +#define bFM3_CAN1_NEWDT1_NEWDAT5 *((volatile unsigned int*)(0x42C61210UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT6 *((volatile unsigned int*)(0x42C61214UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT7 *((volatile unsigned int*)(0x42C61218UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT8 *((volatile unsigned int*)(0x42C6121CUL)) +#define bFM3_CAN1_NEWDT1_NEWDAT9 *((volatile unsigned int*)(0x42C61220UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT10 *((volatile unsigned int*)(0x42C61224UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT11 *((volatile unsigned int*)(0x42C61228UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT12 *((volatile unsigned int*)(0x42C6122CUL)) +#define bFM3_CAN1_NEWDT1_NEWDAT13 *((volatile unsigned int*)(0x42C61230UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT14 *((volatile unsigned int*)(0x42C61234UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT15 *((volatile unsigned int*)(0x42C61238UL)) +#define bFM3_CAN1_NEWDT1_NEWDAT16 *((volatile unsigned int*)(0x42C6123CUL)) +#define bFM3_CAN1_NEWDT2_NEWDAT17 *((volatile unsigned int*)(0x42C61240UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT18 *((volatile unsigned int*)(0x42C61244UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT19 *((volatile unsigned int*)(0x42C61248UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT20 *((volatile unsigned int*)(0x42C6124CUL)) +#define bFM3_CAN1_NEWDT2_NEWDAT21 *((volatile unsigned int*)(0x42C61250UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT22 *((volatile unsigned int*)(0x42C61254UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT23 *((volatile unsigned int*)(0x42C61258UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT24 *((volatile unsigned int*)(0x42C6125CUL)) +#define bFM3_CAN1_NEWDT2_NEWDAT25 *((volatile unsigned int*)(0x42C61260UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT26 *((volatile unsigned int*)(0x42C61264UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT27 *((volatile unsigned int*)(0x42C61268UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT28 *((volatile unsigned int*)(0x42C6126CUL)) +#define bFM3_CAN1_NEWDT2_NEWDAT29 *((volatile unsigned int*)(0x42C61270UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT30 *((volatile unsigned int*)(0x42C61274UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT31 *((volatile unsigned int*)(0x42C61278UL)) +#define bFM3_CAN1_NEWDT2_NEWDAT32 *((volatile unsigned int*)(0x42C6127CUL)) +#define bFM3_CAN1_INTPND_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) +#define bFM3_CAN1_INTPND_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) +#define bFM3_CAN1_INTPND_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) +#define bFM3_CAN1_INTPND_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) +#define bFM3_CAN1_INTPND_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) +#define bFM3_CAN1_INTPND_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) +#define bFM3_CAN1_INTPND_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) +#define bFM3_CAN1_INTPND_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) +#define bFM3_CAN1_INTPND_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) +#define bFM3_CAN1_INTPND_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) +#define bFM3_CAN1_INTPND_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) +#define bFM3_CAN1_INTPND_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) +#define bFM3_CAN1_INTPND_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) +#define bFM3_CAN1_INTPND_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) +#define bFM3_CAN1_INTPND_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) +#define bFM3_CAN1_INTPND_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) +#define bFM3_CAN1_INTPND_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) +#define bFM3_CAN1_INTPND_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) +#define bFM3_CAN1_INTPND_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) +#define bFM3_CAN1_INTPND_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) +#define bFM3_CAN1_INTPND_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) +#define bFM3_CAN1_INTPND_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) +#define bFM3_CAN1_INTPND_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) +#define bFM3_CAN1_INTPND_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) +#define bFM3_CAN1_INTPND_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) +#define bFM3_CAN1_INTPND_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) +#define bFM3_CAN1_INTPND_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) +#define bFM3_CAN1_INTPND_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) +#define bFM3_CAN1_INTPND_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) +#define bFM3_CAN1_INTPND_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) +#define bFM3_CAN1_INTPND_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) +#define bFM3_CAN1_INTPND_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) +#define bFM3_CAN1_INTPND1_INTPND1 *((volatile unsigned int*)(0x42C61400UL)) +#define bFM3_CAN1_INTPND1_INTPND2 *((volatile unsigned int*)(0x42C61404UL)) +#define bFM3_CAN1_INTPND1_INTPND3 *((volatile unsigned int*)(0x42C61408UL)) +#define bFM3_CAN1_INTPND1_INTPND4 *((volatile unsigned int*)(0x42C6140CUL)) +#define bFM3_CAN1_INTPND1_INTPND5 *((volatile unsigned int*)(0x42C61410UL)) +#define bFM3_CAN1_INTPND1_INTPND6 *((volatile unsigned int*)(0x42C61414UL)) +#define bFM3_CAN1_INTPND1_INTPND7 *((volatile unsigned int*)(0x42C61418UL)) +#define bFM3_CAN1_INTPND1_INTPND8 *((volatile unsigned int*)(0x42C6141CUL)) +#define bFM3_CAN1_INTPND1_INTPND9 *((volatile unsigned int*)(0x42C61420UL)) +#define bFM3_CAN1_INTPND1_INTPND10 *((volatile unsigned int*)(0x42C61424UL)) +#define bFM3_CAN1_INTPND1_INTPND11 *((volatile unsigned int*)(0x42C61428UL)) +#define bFM3_CAN1_INTPND1_INTPND12 *((volatile unsigned int*)(0x42C6142CUL)) +#define bFM3_CAN1_INTPND1_INTPND13 *((volatile unsigned int*)(0x42C61430UL)) +#define bFM3_CAN1_INTPND1_INTPND14 *((volatile unsigned int*)(0x42C61434UL)) +#define bFM3_CAN1_INTPND1_INTPND15 *((volatile unsigned int*)(0x42C61438UL)) +#define bFM3_CAN1_INTPND1_INTPND16 *((volatile unsigned int*)(0x42C6143CUL)) +#define bFM3_CAN1_INTPND2_INTPND17 *((volatile unsigned int*)(0x42C61440UL)) +#define bFM3_CAN1_INTPND2_INTPND18 *((volatile unsigned int*)(0x42C61444UL)) +#define bFM3_CAN1_INTPND2_INTPND19 *((volatile unsigned int*)(0x42C61448UL)) +#define bFM3_CAN1_INTPND2_INTPND20 *((volatile unsigned int*)(0x42C6144CUL)) +#define bFM3_CAN1_INTPND2_INTPND21 *((volatile unsigned int*)(0x42C61450UL)) +#define bFM3_CAN1_INTPND2_INTPND22 *((volatile unsigned int*)(0x42C61454UL)) +#define bFM3_CAN1_INTPND2_INTPND23 *((volatile unsigned int*)(0x42C61458UL)) +#define bFM3_CAN1_INTPND2_INTPND24 *((volatile unsigned int*)(0x42C6145CUL)) +#define bFM3_CAN1_INTPND2_INTPND25 *((volatile unsigned int*)(0x42C61460UL)) +#define bFM3_CAN1_INTPND2_INTPND26 *((volatile unsigned int*)(0x42C61464UL)) +#define bFM3_CAN1_INTPND2_INTPND27 *((volatile unsigned int*)(0x42C61468UL)) +#define bFM3_CAN1_INTPND2_INTPND28 *((volatile unsigned int*)(0x42C6146CUL)) +#define bFM3_CAN1_INTPND2_INTPND29 *((volatile unsigned int*)(0x42C61470UL)) +#define bFM3_CAN1_INTPND2_INTPND30 *((volatile unsigned int*)(0x42C61474UL)) +#define bFM3_CAN1_INTPND2_INTPND31 *((volatile unsigned int*)(0x42C61478UL)) +#define bFM3_CAN1_INTPND2_INTPND32 *((volatile unsigned int*)(0x42C6147CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) +#define bFM3_CAN1_MSGVAL_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) +#define bFM3_CAN1_MSGVAL_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL1 *((volatile unsigned int*)(0x42C61600UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL2 *((volatile unsigned int*)(0x42C61604UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL3 *((volatile unsigned int*)(0x42C61608UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL4 *((volatile unsigned int*)(0x42C6160CUL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL5 *((volatile unsigned int*)(0x42C61610UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL6 *((volatile unsigned int*)(0x42C61614UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL7 *((volatile unsigned int*)(0x42C61618UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL8 *((volatile unsigned int*)(0x42C6161CUL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL9 *((volatile unsigned int*)(0x42C61620UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL10 *((volatile unsigned int*)(0x42C61624UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL11 *((volatile unsigned int*)(0x42C61628UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL12 *((volatile unsigned int*)(0x42C6162CUL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL13 *((volatile unsigned int*)(0x42C61630UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL14 *((volatile unsigned int*)(0x42C61634UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL15 *((volatile unsigned int*)(0x42C61638UL)) +#define bFM3_CAN1_MSGVAL1_MSGVAL16 *((volatile unsigned int*)(0x42C6163CUL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL17 *((volatile unsigned int*)(0x42C61640UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL18 *((volatile unsigned int*)(0x42C61644UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL19 *((volatile unsigned int*)(0x42C61648UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL20 *((volatile unsigned int*)(0x42C6164CUL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL21 *((volatile unsigned int*)(0x42C61650UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL22 *((volatile unsigned int*)(0x42C61654UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL23 *((volatile unsigned int*)(0x42C61658UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL24 *((volatile unsigned int*)(0x42C6165CUL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL25 *((volatile unsigned int*)(0x42C61660UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL26 *((volatile unsigned int*)(0x42C61664UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL27 *((volatile unsigned int*)(0x42C61668UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL28 *((volatile unsigned int*)(0x42C6166CUL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL29 *((volatile unsigned int*)(0x42C61670UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL30 *((volatile unsigned int*)(0x42C61674UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL31 *((volatile unsigned int*)(0x42C61678UL)) +#define bFM3_CAN1_MSGVAL2_MSGVAL32 *((volatile unsigned int*)(0x42C6167CUL)) + +#ifdef __cplusplus +} +#endif + +#endif /* _MB9BF506R_H_ */ + diff --git a/bsp/mb9bf506r/CMSIS/start_gcc.S b/bsp/mb9bf506r/CMSIS/start_gcc.S new file mode 100644 index 0000000000..ad0f8af0c3 --- /dev/null +++ b/bsp/mb9bf506r/CMSIS/start_gcc.S @@ -0,0 +1,360 @@ +/* + * File : start_gcc.S + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-07-01 lgnq first version + */ + +.section .bss.init +.equ Stack_Size, 0x00000200 +.space Stack_Size +Initial_spTop: + + .syntax unified + .cpu cortex-m3 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +// .equ Initial_spTop, 0x20000200 +.equ BootRAM, 0xF1E0F85F +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: +/* restore original stack pointer */ + LDR r0, =Initial_spTop + MSR msp, r0 +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss +/* Call the application's entry point.*/ + bl main + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word Initial_spTop + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + .word CSV_IRQHandler + .word SWDT_IRQHandler + .word LVD_IRQHandler + .word WFG_IRQHandler + .word EXINT0_7_IRQHandler + .word EXINT8_15_IRQHandler + .word DTIM_QDU_IRQHandler + .word MFS0RX_IRQHandler + .word MFS0TX_IRQHandler + .word MFS1RX_IRQHandler + .word MFS1TX_IRQHandler + .word MFS2RX_IRQHandler + .word MFS2TX_IRQHandler + .word MFS3RX_IRQHandler + .word MFS3TX_IRQHandler + .word MFS4RX_IRQHandler + .word MFS4TX_IRQHandler + .word MFS5RX_IRQHandler + .word MFS5TX_IRQHandler + .word MFS6RX_IRQHandler + .word MFS6TX_IRQHandler + .word MFS7RX_IRQHandler + .word MFS7TX_IRQHandler + .word PPG_IRQHandler + .word OSC_PLL_WC_IRQHandler + .word ADC0_IRQHandler + .word ADC1_IRQHandler + .word ADC2_IRQHandler + .word FRTIM_IRQHandler + .word INCAP_IRQHandler + .word OUTCOMP_IRQHandler + .word BTIM_IRQHandler + .word CAN0_IRQHandler + .word CAN1_IRQHandler + .word USBF_IRQHandler + .word USBF_USBH_IRQHandler + .word RESERVED_1_IRQHandler + .word RESERVED_2_IRQHandler + .word DMAC0_IRQHandler + .word DMAC1_IRQHandler + .word DMAC2_IRQHandler + .word DMAC3_IRQHandler + .word DMAC4_IRQHandler + .word DMAC5_IRQHandler + .word DMAC6_IRQHandler + .word DMAC7_IRQHandler + .word RESERVED_3_IRQHandler + .word RESERVED_4_IRQHandler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak CSV_IRQHandler + .thumb_set CSV_IRQHandler,Default_Handler + + .weak SWDT_IRQHandler + .thumb_set SWDT_IRQHandler,Default_Handler + + .weak LVD_IRQHandler + .thumb_set LVD_IRQHandler,Default_Handler + + .weak WFG_IRQHandler + .thumb_set WFG_IRQHandler,Default_Handler + + .weak EXINT0_7_IRQHandler + .thumb_set EXINT0_7_IRQHandler,Default_Handler + + .weak EXINT8_15_IRQHandler + .thumb_set EXINT8_15_IRQHandler,Default_Handler + + .weak DTIM_QDU_IRQHandler + .thumb_set DTIM_QDU_IRQHandler,Default_Handler + + .weak MFS0RX_IRQHandler + .thumb_set MFS0RX_IRQHandler,Default_Handler + + .weak MFS0TX_IRQHandler + .thumb_set MFS0TX_IRQHandler,Default_Handler + + .weak MFS1RX_IRQHandler + .thumb_set MFS1RX_IRQHandler,Default_Handler + + .weak MFS1TX_IRQHandler + .thumb_set MFS1TX_IRQHandler,Default_Handler + + .weak MFS2RX_IRQHandler + .thumb_set MFS2RX_IRQHandler,Default_Handler + + .weak MFS2TX_IRQHandler + .thumb_set MFS2TX_IRQHandler,Default_Handler + + .weak MFS3RX_IRQHandler + .thumb_set MFS3RX_IRQHandler,Default_Handler + + .weak MFS3TX_IRQHandler + .thumb_set MFS3TX_IRQHandler,Default_Handler + + .weak MFS4RX_IRQHandler + .thumb_set MFS4RX_IRQHandler,Default_Handler + + .weak MFS4TX_IRQHandler + .thumb_set MFS4TX_IRQHandler,Default_Handler + + .weak MFS5RX_IRQHandler + .thumb_set MFS5RX_IRQHandler,Default_Handler + + .weak MFS5TX_IRQHandler + .thumb_set MFS5TX_IRQHandler,Default_Handler + + .weak MFS6RX_IRQHandler + .thumb_set MFS6RX_IRQHandler,Default_Handler + + .weak MFS6TX_IRQHandler + .thumb_set MFS6TX_IRQHandler,Default_Handler + + .weak MFS7RX_IRQHandler + .thumb_set MFS7RX_IRQHandler,Default_Handler + + .weak MFS7TX_IRQHandler + .thumb_set MFS7TX_IRQHandler,Default_Handler + + .weak PPG_IRQHandler + .thumb_set PPG_IRQHandler,Default_Handler + + .weak OSC_PLL_WC_IRQHandler + .thumb_set OSC_PLL_WC_IRQHandler,Default_Handler + + .weak ADC0_IRQHandler + .thumb_set ADC0_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak ADC2_IRQHandler + .thumb_set ADC2_IRQHandler,Default_Handler + + .weak FRTIM_IRQHandler + .thumb_set FRTIM_IRQHandler,Default_Handler + + .weak INCAP_IRQHandler + .thumb_set INCAP_IRQHandler,Default_Handler + + .weak OUTCOMP_IRQHandler + .thumb_set OUTCOMP_IRQHandler,Default_Handler + + .weak BTIM_IRQHandler + .thumb_set BTIM_IRQHandler,Default_Handler + + .weak CAN0_IRQHandler + .thumb_set CAN0_IRQHandler,Default_Handler + + .weak CAN1_IRQHandler + .thumb_set CAN1_IRQHandler,Default_Handler + + .weak USBF_IRQHandler + .thumb_set USBF_IRQHandler,Default_Handler + + .weak USBF_USBH_IRQHandler + .thumb_set USBF_USBH_IRQHandler,Default_Handler + + .weak RESERVED_1_IRQHandler + .thumb_set RESERVED_1_IRQHandler,Default_Handler + + .weak RESERVED_2_IRQHandler + .thumb_set RESERVED_2_IRQHandler,Default_Handler + + .weak DMAC0_IRQHandler + .thumb_set DMAC0_IRQHandler,Default_Handler + + .weak DMAC1_IRQHandler + .thumb_set DMAC1_IRQHandler,Default_Handler + + .weak DMAC2_IRQHandler + .thumb_set DMAC2_IRQHandler,Default_Handler + + .weak DMAC3_IRQHandler + .thumb_set DMAC3_IRQHandler,Default_Handler + + .weak DMAC4_IRQHandler + .thumb_set DMAC4_IRQHandler,Default_Handler + + .weak DMAC5_IRQHandler + .thumb_set DMAC5_IRQHandler,Default_Handler + + .weak DMAC6_IRQHandler + .thumb_set DMAC6_IRQHandler,Default_Handler + + .weak DMAC7_IRQHandler + .thumb_set DMAC7_IRQHandler,Default_Handler + + .weak RESERVED_3_IRQHandler + .thumb_set RESERVED_3_IRQHandler,Default_Handler + + .weak RESERVED_4_IRQHandler + .thumb_set RESERVED_4_IRQHandler,Default_Handler + diff --git a/bsp/mb9bf506r/CMSIS/start_iar.S b/bsp/mb9bf506r/CMSIS/start_iar.S new file mode 100644 index 0000000000..b111ce9b43 --- /dev/null +++ b/bsp/mb9bf506r/CMSIS/start_iar.S @@ -0,0 +1,363 @@ +;/* +; * File : context_iar.S +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2009-01-17 Bernard first version +; * 2009-09-27 Bernard add protect when contex switch occurs +; */ + +#include "rtconfig.h" + + MODULE ?cstartup + +;; ICODE is the same segment as cstartup. By placing __low_level_init +;; in the same segment, we make sure it can be reached with BL. */ + + SECTION CSTACK:DATA:NOROOT(3) + SECTION .icode:CODE:NOROOT(2) + +#ifdef RT_USING_UART2 + IMPORT MFS2RX_IRQHandler +#endif + PUBLIC __low_level_init + + PUBWEAK SystemInit_ExtMemCtl + SECTION .text:CODE:REORDER(2) + THUMB +SystemInit_ExtMemCtl + BX LR + +__low_level_init: + ;; Initialize hardware. + LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller + MOV R11, LR + BLX R0 + LDR R1, =sfe(CSTACK) ; restore original stack pointer + MSR MSP, R1 + MOV R0,#1 + ;; Return with BX to be independent of mode of caller + BX R11 + + ;; Forward declaration of sections. + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD __iar_program_start + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD CSV_IRQHandler ; Clock Super Visor + DCD SWDT_IRQHandler ; Software Watchdog Timer + DCD LVD_IRQHandler ; Low Voltage Detector + DCD WFG_IRQHandler ; Wave Form Generator + DCD EXINT0_7_IRQHandler ; External Interrupt Request ch.0 to ch.7 + DCD EXINT8_15_IRQHandler ; External Interrupt Request ch.8 to ch.15 + DCD DTIM_QDU_IRQHandler ; Dual Timer / Quad Decoder + DCD MFS0RX_IRQHandler ; MultiFunction Serial ch.0 + DCD MFS0TX_IRQHandler ; MultiFunction Serial ch.0 + DCD MFS1RX_IRQHandler ; MultiFunction Serial ch.1 + DCD MFS1TX_IRQHandler ; MultiFunction Serial ch.1 +#ifdef RT_USING_UART2 + DCD MFS2RX_IRQHandler ; MultiFunction Serial ch.2 +#else + DCD NULL_IRQHandler ; MultiFunction Serial ch.2 +#endif + DCD MFS2TX_IRQHandler ; MultiFunction Serial ch.2 + DCD MFS3RX_IRQHandler ; MultiFunction Serial ch.3 + DCD MFS3TX_IRQHandler ; MultiFunction Serial ch.3 + DCD MFS4RX_IRQHandler ; MultiFunction Serial ch.4 + DCD MFS4TX_IRQHandler ; MultiFunction Serial ch.4 + DCD MFS5RX_IRQHandler ; MultiFunction Serial ch.5 + DCD MFS5TX_IRQHandler ; MultiFunction Serial ch.5 + DCD MFS6RX_IRQHandler ; MultiFunction Serial ch.6 + DCD MFS6TX_IRQHandler ; MultiFunction Serial ch.6 + DCD MFS7RX_IRQHandler ; MultiFunction Serial ch.7 + DCD MFS7TX_IRQHandler ; MultiFunction Serial ch.7 + DCD PPG_IRQHandler ; PPG + DCD OSC_PLL_WC_IRQHandler ; OSC / PLL / Watch Counter + DCD ADC0_IRQHandler ; ADC0 + DCD ADC1_IRQHandler ; ADC1 + DCD ADC2_IRQHandler ; ADC2 + DCD FRTIM_IRQHandler ; Free-run Timer + DCD INCAP_IRQHandler ; Input Capture + DCD OUTCOMP_IRQHandler ; Output Compare + DCD BTIM_IRQHandler ; Base Timer ch.0 to ch.7 + DCD CAN0_IRQHandler ; CAN ch.0 + DCD CAN1_IRQHandler ; CAN ch.1 + DCD USBF_IRQHandler ; USB Function + DCD USBF_USBH_IRQHandler ; USB Function / USB HOST + DCD RESERVED_1_IRQHandler ; Reserved_1 + DCD RESERVED_2_IRQHandler ; Reserved_2 + DCD DMAC0_IRQHandler ; DMAC ch.0 + DCD DMAC1_IRQHandler ; DMAC ch.1 + DCD DMAC2_IRQHandler ; DMAC ch.2 + DCD DMAC3_IRQHandler ; DMAC ch.3 + DCD DMAC4_IRQHandler ; DMAC ch.4 + DCD DMAC5_IRQHandler ; DMAC ch.5 + DCD DMAC6_IRQHandler ; DMAC ch.6 + DCD DMAC7_IRQHandler ; DMAC ch.7 + DCD RESERVED_3_IRQHandler ; Reserved_3 + DCD RESERVED_4_IRQHandler ; Reserved_4 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER(1) +NMI_Handler + B NMI_Handler + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER(1) +HardFault_Handler + B HardFault_Handler + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER(1) +MemManage_Handler + B MemManage_Handler + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER(1) +BusFault_Handler + B BusFault_Handler + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER(1) +SVC_Handler + B SVC_Handler + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER(1) +PendSV_Handler + B PendSV_Handler + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER(1) +SysTick_Handler + B SysTick_Handler + PUBWEAK CSV_IRQHandler + SECTION .text:CODE:REORDER(1) +CSV_IRQHandler + B CSV_IRQHandler + PUBWEAK SWDT_IRQHandler + SECTION .text:CODE:REORDER(1) +SWDT_IRQHandler + B SWDT_IRQHandler + PUBWEAK LVD_IRQHandler + SECTION .text:CODE:REORDER(1) +LVD_IRQHandler + B LVD_IRQHandler + PUBWEAK WFG_IRQHandler + SECTION .text:CODE:REORDER(1) +WFG_IRQHandler + B WFG_IRQHandler + PUBWEAK EXINT0_7_IRQHandler + SECTION .text:CODE:REORDER(1) +EXINT0_7_IRQHandler + B EXINT0_7_IRQHandler + PUBWEAK EXINT8_15_IRQHandler + SECTION .text:CODE:REORDER(1) +EXINT8_15_IRQHandler + B EXINT8_15_IRQHandler + PUBWEAK DTIM_QDU_IRQHandler + SECTION .text:CODE:REORDER(1) +DTIM_QDU_IRQHandler + B DTIM_QDU_IRQHandler + PUBWEAK MFS0RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS0RX_IRQHandler + B MFS0RX_IRQHandler + PUBWEAK MFS0TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS0TX_IRQHandler + B MFS0TX_IRQHandler + PUBWEAK MFS1RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS1RX_IRQHandler + B MFS1RX_IRQHandler + PUBWEAK MFS1TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS1TX_IRQHandler + B MFS1TX_IRQHandler + PUBWEAK NULL_IRQHandler + SECTION .text:CODE:REORDER(1) +NULL_IRQHandler + B NULL_IRQHandler + PUBWEAK MFS2TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS2TX_IRQHandler + B MFS2TX_IRQHandler + PUBWEAK MFS3RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS3RX_IRQHandler + B MFS3RX_IRQHandler + PUBWEAK MFS3TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS3TX_IRQHandler + B MFS3TX_IRQHandler + PUBWEAK MFS4RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS4RX_IRQHandler + B MFS4RX_IRQHandler + PUBWEAK MFS4TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS4TX_IRQHandler + B MFS4TX_IRQHandler + PUBWEAK MFS5RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS5RX_IRQHandler + B MFS5RX_IRQHandler + PUBWEAK MFS5TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS5TX_IRQHandler + B MFS5TX_IRQHandler + PUBWEAK MFS6RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS6RX_IRQHandler + B MFS6RX_IRQHandler + PUBWEAK MFS6TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS6TX_IRQHandler + B MFS6TX_IRQHandler + PUBWEAK MFS7RX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS7RX_IRQHandler + B MFS7RX_IRQHandler + PUBWEAK MFS7TX_IRQHandler + SECTION .text:CODE:REORDER(1) +MFS7TX_IRQHandler + B MFS7TX_IRQHandler + PUBWEAK PPG_IRQHandler + SECTION .text:CODE:REORDER(1) +PPG_IRQHandler + B PPG_IRQHandler + PUBWEAK OSC_PLL_WC_IRQHandler + SECTION .text:CODE:REORDER(1) +OSC_PLL_WC_IRQHandler + B OSC_PLL_WC_IRQHandler + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC0_IRQHandler + B ADC0_IRQHandler + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + PUBWEAK ADC2_IRQHandler + SECTION .text:CODE:REORDER(1) +ADC2_IRQHandler + B ADC2_IRQHandler + PUBWEAK FRTIM_IRQHandler + SECTION .text:CODE:REORDER(1) +FRTIM_IRQHandler + B FRTIM_IRQHandler + PUBWEAK INCAP_IRQHandler + SECTION .text:CODE:REORDER(1) +INCAP_IRQHandler + B INCAP_IRQHandler + PUBWEAK OUTCOMP_IRQHandler + SECTION .text:CODE:REORDER(1) +OUTCOMP_IRQHandler + B OUTCOMP_IRQHandler + PUBWEAK BTIM_IRQHandler + SECTION .text:CODE:REORDER(1) +BTIM_IRQHandler + B BTIM_IRQHandler + PUBWEAK CAN0_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN0_IRQHandler + B CAN0_IRQHandler + PUBWEAK CAN1_IRQHandler + SECTION .text:CODE:REORDER(1) +CAN1_IRQHandler + B CAN1_IRQHandler + PUBWEAK USBF_IRQHandler + SECTION .text:CODE:REORDER(1) +USBF_IRQHandler + B USBF_IRQHandler + PUBWEAK USBF_USBH_IRQHandler + SECTION .text:CODE:REORDER(1) +USBF_USBH_IRQHandler + B USBF_USBH_IRQHandler + PUBWEAK RESERVED_1_IRQHandler + SECTION .text:CODE:REORDER(1) +RESERVED_1_IRQHandler + B RESERVED_1_IRQHandler + PUBWEAK RESERVED_2_IRQHandler + SECTION .text:CODE:REORDER(1) +RESERVED_2_IRQHandler + B RESERVED_2_IRQHandler + PUBWEAK DMAC0_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC0_IRQHandler + B DMAC0_IRQHandler + PUBWEAK DMAC1_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC1_IRQHandler + B DMAC1_IRQHandler + PUBWEAK DMAC2_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC2_IRQHandler + B DMAC2_IRQHandler + PUBWEAK DMAC3_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC3_IRQHandler + B DMAC3_IRQHandler + PUBWEAK DMAC4_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC4_IRQHandler + B DMAC4_IRQHandler + PUBWEAK DMAC5_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC5_IRQHandler + B DMAC5_IRQHandler + PUBWEAK DMAC6_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC6_IRQHandler + B DMAC6_IRQHandler + PUBWEAK DMAC7_IRQHandler + SECTION .text:CODE:REORDER(1) +DMAC7_IRQHandler + B DMAC7_IRQHandler + PUBWEAK RESERVED_3_IRQHandler + SECTION .text:CODE:REORDER(1) +RESERVED_3_IRQHandler + B RESERVED_3_IRQHandler + PUBWEAK RESERVED_4_IRQHandler + SECTION .text:CODE:REORDER(1) +RESERVED_4_IRQHandler + B RESERVED_4_IRQHandler + + END diff --git a/bsp/mb9bf506r/CMSIS/start_rvds.S b/bsp/mb9bf506r/CMSIS/start_rvds.S new file mode 100644 index 0000000000..fc755132c1 --- /dev/null +++ b/bsp/mb9bf506r/CMSIS/start_rvds.S @@ -0,0 +1,291 @@ +; /* +; * File : start_rvds.s +; * This file is part of RT-Thread RTOS +; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team +; * +; * The license and distribution terms for this file may be +; * found in the file LICENSE in this distribution or at +; * http://www.rt-thread.org/license/LICENSE +; * +; * Change Logs: +; * Date Author Notes +; * 2011-02-23 Bernard first implementation +; */ + +;* <<< Use Configuration Wizard in Context Menu >>> + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Note: RT-Thread not use malloc/free in Keil MDK, therefore the heap size is 0. +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + DCD CSV_Handler ; 0: Clock Super Visor + DCD SWDT_Handler ; 1: Software Watchdog Timer + DCD LVD_Handler ; 2: Low Voltage Detector + DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF + DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7 + DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15 + DCD DT_Handler ; 6: Dual Timer / Quad Decoder + DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0 + DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0 + DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1 + DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1 + DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2 + DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2 + DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3 + DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3 + DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4 + DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4 + DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5 + DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5 + DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6 + DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6 + DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7 + DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7 + DCD PPG_Handler ; 23: PPG + DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter + DCD ADC0_IRQHandler ; 25: ADC0 + DCD ADC1_IRQHandler ; 26: ADC1 + DCD ADC2_IRQHandler ; 27: ADC2 + DCD MFT_FRT_IRQHandler ; 28: Free-run Timer + DCD MFT_IPC_IRQHandler ; 29: Input Capture + DCD MFT_OPC_IRQHandler ; 30: Output Compare + DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7 + DCD CAN0_IRQHandler ; 32: CAN ch.0 + DCD CAN1_IRQHandler ; 33: CAN ch.1 + DCD USBF_Handler ; 34: USB Function + DCD USB_Handler ; 35: USB Function / USB HOST + DCD DummyHandler ; 36: Reserved + DCD DummyHandler ; 37: Reserved + DCD DMAC0_Handler ; 38: DMAC ch.0 + DCD DMAC1_Handler ; 39: DMAC ch.1 + DCD DMAC2_Handler ; 40: DMAC ch.2 + DCD DMAC3_Handler ; 41: DMAC ch.3 + DCD DMAC4_Handler ; 42: DMAC ch.4 + DCD DMAC5_Handler ; 43: DMAC ch.5 + DCD DMAC6_Handler ; 44: DMAC ch.6 + DCD DMAC7_Handler ; 45: DMAC ch.7 + DCD DummyHandler ; 46: Reserved + DCD DummyHandler ; 47: Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R1, = __initial_sp ; restore original stack pointer + MSR MSP, R1 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT CSV_Handler [WEAK] + EXPORT SWDT_Handler [WEAK] + EXPORT LVD_Handler [WEAK] + EXPORT MFT_WG_IRQHandler [WEAK] + EXPORT INT0_7_Handler [WEAK] + EXPORT INT8_15_Handler [WEAK] + EXPORT DT_Handler [WEAK] + EXPORT MFS0RX_IRQHandler [WEAK] + EXPORT MFS0TX_IRQHandler [WEAK] + EXPORT MFS1RX_IRQHandler [WEAK] + EXPORT MFS1TX_IRQHandler [WEAK] + EXPORT MFS2RX_IRQHandler [WEAK] + EXPORT MFS2TX_IRQHandler [WEAK] + EXPORT MFS3RX_IRQHandler [WEAK] + EXPORT MFS3TX_IRQHandler [WEAK] + EXPORT MFS4RX_IRQHandler [WEAK] + EXPORT MFS4TX_IRQHandler [WEAK] + EXPORT MFS5RX_IRQHandler [WEAK] + EXPORT MFS5TX_IRQHandler [WEAK] + EXPORT MFS6RX_IRQHandler [WEAK] + EXPORT MFS6TX_IRQHandler [WEAK] + EXPORT MFS7RX_IRQHandler [WEAK] + EXPORT MFS7TX_IRQHandler [WEAK] + EXPORT PPG_Handler [WEAK] + EXPORT TIM_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT ADC2_IRQHandler [WEAK] + EXPORT MFT_FRT_IRQHandler [WEAK] + EXPORT MFT_IPC_IRQHandler [WEAK] + EXPORT MFT_OPC_IRQHandler [WEAK] + EXPORT BT_IRQHandler [WEAK] + EXPORT CAN0_IRQHandler [WEAK] + EXPORT CAN1_IRQHandler [WEAK] + EXPORT USBF_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT DMAC0_Handler [WEAK] + EXPORT DMAC1_Handler [WEAK] + EXPORT DMAC2_Handler [WEAK] + EXPORT DMAC3_Handler [WEAK] + EXPORT DMAC4_Handler [WEAK] + EXPORT DMAC5_Handler [WEAK] + EXPORT DMAC6_Handler [WEAK] + EXPORT DMAC7_Handler [WEAK] + EXPORT DummyHandler [WEAK] + +CSV_Handler +SWDT_Handler +LVD_Handler +MFT_WG_IRQHandler +INT0_7_Handler +INT8_15_Handler +DT_Handler +MFS0RX_IRQHandler +MFS0TX_IRQHandler +MFS1RX_IRQHandler +MFS1TX_IRQHandler +MFS2RX_IRQHandler +MFS2TX_IRQHandler +MFS3RX_IRQHandler +MFS3TX_IRQHandler +MFS4RX_IRQHandler +MFS4TX_IRQHandler +MFS5RX_IRQHandler +MFS5TX_IRQHandler +MFS6RX_IRQHandler +MFS6TX_IRQHandler +MFS7RX_IRQHandler +MFS7TX_IRQHandler +PPG_Handler +TIM_IRQHandler +ADC0_IRQHandler +ADC1_IRQHandler +ADC2_IRQHandler +MFT_FRT_IRQHandler +MFT_IPC_IRQHandler +MFT_OPC_IRQHandler +BT_IRQHandler +CAN0_IRQHandler +CAN1_IRQHandler +USBF_Handler +USB_Handler +DMAC0_Handler +DMAC1_Handler +DMAC2_Handler +DMAC3_Handler +DMAC4_Handler +DMAC5_Handler +DMAC6_Handler +DMAC7_Handler +DummyHandler + B . + ENDP + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + ELSE + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + ENDIF + + END diff --git a/bsp/mb9bf506r/CMSIS/system_mb9bf50x.c b/bsp/mb9bf506r/CMSIS/system_mb9bf50x.c new file mode 100644 index 0000000000..21cd7a3f26 --- /dev/null +++ b/bsp/mb9bf506r/CMSIS/system_mb9bf50x.c @@ -0,0 +1,111 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user’s obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intention and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.4) */ +/************************************************************************/ + +#include "mb9bf506r.h" + +/* + * 80MHz : Master Clock + */ +const uint32_t SystemFrequency = 80000000UL; + +uint32_t SysFreHCLK = 80000000UL; /* HCLK = MasterClock / 1 */ +uint32_t SysFrePCLK0 = 40000000UL; /* PCLK0 = HCLK / 2 */ +uint32_t SysFrePCLK1 = 40000000UL; /* PCLK1 = HCLK / 2 */ +uint32_t SysFrePCLK2 = 40000000UL; /* PCLK2 = HCLK / 2 */ +uint32_t SysFreTPIU = 0UL; /* TPIUCLK : Disable */ + +/* + * Prototype of internal function + */ +static void ClockInit(void); +static void HwwdtDisable(void); + + +/* + * Setup the microcontroller system + */ +void SystemInit (void) +{ + HwwdtDisable(); /* Disable Hardware Watchdog */ + ClockInit(); /* Initialize Clock */ +} +/* + * Initialize Clock + */ +static void ClockInit(void) +{ + /*set Main clock stabilization + wait time to 2ms*/ + FM3_CRG->CSW_TMR = 0x79; + /*Enable Main Oscilator*/ + FM3_CRG->SCM_CTL |= 1<<1; + /*Wait stabilization end*/ + while(!(FM3_CRG->SCM_STR & 0x02)); + + /* sub CLK enable */ + //FM3_CRG->SCM_CTL |= 0x08; + //while(!(FM3_CRG->SCM_STR & 0x08)); + + /*Set PLL stabilization + wait time to 512uS*/ + FM3_CRG->PSW_TMR |= 2; + /*Set PLL to 80MHz*/ + FM3_CRG->PLL_CTL1 = 0; /*K = 1, M=1*/ + FM3_CRG->PLL_CTL2 = 19; /*N = 20*/ + /*Enable PLL*/ + FM3_CRG->SCM_CTL |= 0x10; + /*Set bus prescalers*/ + FM3_CRG->BSC_PSR = 0; /*Base clock Prescaler 1:1*/ + FM3_CRG->APBC0_PSR |= 1; /*APB0 clock Prescaler 1:2*/ + FM3_CRG->APBC1_PSR |= 1; /*APB1 clock Prescaler 1:2*/ + FM3_CRG->APBC2_PSR |= 1; /*APB2 clock Prescaler 1:2*/ + /*Wait PLL stabilizatoin end*/ + while(!(FM3_CRG->SCM_STR & 0x10)); + /*Select PLL for main clock*/ + FM3_CRG->SCM_CTL |= 2<<5; + /*Wait PLL to be connected*/ + while((FM3_CRG->SCM_STR & 0xe0) != 0x40); + +} +/* + * Stop HW Watchdog Timer + */ +static void HwwdtDisable(void) +{ + /* UnLock (except WDG_CTL) */ + FM3_HWWDT->WDG_LCK = 0x1ACCE551; + /* UnLock (WDG_CTL) */ + FM3_HWWDT->WDG_LCK = 0xE5331AAE; + /* Disable WDG */ + FM3_HWWDT->WDG_CTL = 0x00; +} diff --git a/bsp/mb9bf506r/CMSIS/system_mb9bf50x.h b/bsp/mb9bf506r/CMSIS/system_mb9bf50x.h new file mode 100644 index 0000000000..4b4789d5df --- /dev/null +++ b/bsp/mb9bf506r/CMSIS/system_mb9bf50x.h @@ -0,0 +1,71 @@ +/************************************************************************/ +/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */ +/* */ +/* The following software deliverable is intended for and must only be */ +/* used for reference and in an evaluation laboratory environment. */ +/* It is provided on an as-is basis without charge and is subject to */ +/* alterations. */ +/* It is the user's obligation to fully test the software in its */ +/* environment and to ensure proper functionality, qualification and */ +/* compliance with component specifications. */ +/* */ +/* In the event the software deliverable includes the use of open */ +/* source components, the provisions of the governing open source */ +/* license agreement shall apply with respect to such software */ +/* deliverable. */ +/* FSEU does not warrant that the deliverables do not infringe any */ +/* third party intellectual property right (IPR). In the event that */ +/* the deliverables infringe a third party IPR it is the sole */ +/* responsibility of the customer to obtain necessary licenses to */ +/* continue the usage of the deliverable. */ +/* */ +/* To the maximum extent permitted by applicable law FSEU disclaims all */ +/* warranties, whether express or implied, in particular, but not */ +/* limited to, warranties of merchantability and fitness for a */ +/* particular purpose for which the deliverable is not designated. */ +/* */ +/* To the maximum extent permitted by applicable law, FSEU's liability */ +/* is restricted to intentional misconduct and gross negligence. */ +/* FSEU is not liable for consequential damages. */ +/* */ +/* (V1.5) */ +/************************************************************************/ + +#ifndef _SYSTEM_MB9BF50X_H_ +#define _SYSTEM_MB9BF50X_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_MB9BF50X_H */ diff --git a/bsp/mb9bf506r/SConscript b/bsp/mb9bf506r/SConscript new file mode 100644 index 0000000000..d09b858deb --- /dev/null +++ b/bsp/mb9bf506r/SConscript @@ -0,0 +1,16 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +src_bsp = ['application.c', 'startup.c', 'board.c', 'led.c', 'console.c'] +src_drv = ['serial.c', 'nand.c'] + +if GetDepend('RT_USING_RTGUI'): + src_drv += ['info.c'] + +src = src_bsp + src_drv +CPPPATH = [GetCurrentDir()] +CPPDEFINES = [] +group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/mb9bf506r/SConstruct b/bsp/mb9bf506r/SConstruct new file mode 100644 index 0000000000..ad6f3dcd6f --- /dev/null +++ b/bsp/mb9bf506r/SConstruct @@ -0,0 +1,39 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +from building import * + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map']) + env.Replace(ARFLAGS = '') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT) + +objs = objs + SConscript('CMSIS/SConscript', variant_dir='build/bsp/Libraries', duplicate=0) + +# build program +env.Program(TARGET, objs) + +# end building +EndBuilding(TARGET) diff --git a/bsp/mb9bf506r/application.c b/bsp/mb9bf506r/application.c new file mode 100644 index 0000000000..94ffe4819d --- /dev/null +++ b/bsp/mb9bf506r/application.c @@ -0,0 +1,71 @@ +/* + * File : application.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-05-24 Bernard the first version + */ + +/** + * @addtogroup FM3 + */ +/*@{*/ + +#include +#include "board.h" +#include "led.h" + +#ifdef RT_USING_DFS +/* dfs init */ +#include +/* dfs filesystem:ELM filesystem init */ +#include +/* dfs Filesystem APIs */ +#include +#endif + +void rt_init_thread_entry(void *parameter) +{ + /* Filesystem Initialization */ +#ifdef RT_USING_DFS + { + /* init the device filesystem */ + dfs_init(); + +#ifdef RT_USING_DFS_ELMFAT + /* init the elm chan FatFs filesystam*/ + elm_init(); + + /* mount ELM FatFs on NAND flash as root directory */ + if (dfs_mount("nand", "/", "elm", 0, 0) == 0) + { + rt_kprintf("File System initialized!\n"); + } + else + rt_kprintf("File System initialzation failed!\n"); +#endif + } +#endif + /* LED Initialization */ + rt_hw_led_init(); +} + +int rt_application_init() +{ + rt_thread_t tid; + + tid = rt_thread_create("init", + rt_init_thread_entry, RT_NULL, + 2048, 8, 20); + if (tid != RT_NULL) rt_thread_startup(tid); + + return 0; +} + +/*@}*/ diff --git a/bsp/mb9bf506r/board.c b/bsp/mb9bf506r/board.c new file mode 100644 index 0000000000..43daf80d79 --- /dev/null +++ b/bsp/mb9bf506r/board.c @@ -0,0 +1,64 @@ +/* + * File : board.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2011 RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-24 Bernard first implementation + */ + +#include +#include + +#include "board.h" +#include "mb9bf506r.h" + +#include "serial.h" +#include "nand.h" + +extern const uint32_t SystemFrequency; + +/** + * @addtogroup FM3 + */ + +/*@{*/ + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** +* This function will initial FM3 Easy Kit board. + */ +void rt_hw_board_init(void) +{ + /* init systick */ + SysTick_Config(SystemFrequency/RT_TICK_PER_SECOND); + + /* initialize UART device */ + rt_hw_serial_init(); + /* set console as UART device */ + rt_console_set_device("uart2"); + + /* initialize nand flash device */ + rt_hw_nand_init(); +} + +/*@}*/ diff --git a/bsp/mb9bf506r/board.h b/bsp/mb9bf506r/board.h new file mode 100644 index 0000000000..b96f8a167a --- /dev/null +++ b/bsp/mb9bf506r/board.h @@ -0,0 +1,31 @@ +/* + * File : board.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2011-03-04 lgnq add board.h to FM3 bsp + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include "serial.h" + +//Internal SRAM memory size[Kbytes] <8-64> +//MB9BF500 : 32 +//MB9BF504 : 32 +//MB9BF505 : 48 +//MB9BF506 : 64 +#define FM3_SRAM_SIZE 64 +#define FM3_SRAM_END (0x1FFF8000 + FM3_SRAM_SIZE * 1024) + +void rt_hw_board_init(void); + +#endif diff --git a/bsp/mb9bf506r/console.c b/bsp/mb9bf506r/console.c new file mode 100644 index 0000000000..084a7d6a08 --- /dev/null +++ b/bsp/mb9bf506r/console.c @@ -0,0 +1,180 @@ +#include + +#include + +#define RT_CONSOLE_WIDTH 240 +#define RT_CONSOLE_HEIGHT 320 + +#define RT_CONSOLE_FONT_WIDTH 8 +#define RT_CONSOLE_FONT_HEIGHT 16 + +#define RT_CONSOLE_COL (RT_CONSOLE_WIDTH/RT_CONSOLE_FONT_WIDTH) +#define RT_CONSOLE_ROW (RT_CONSOLE_HEIGHT/RT_CONSOLE_FONT_HEIGHT) + +#define RT_CONSOLE_TAB 4 + +#define RT_CONSOLE_FOREPIXEL (0x001f) + +extern struct serial_device uart2; + +struct rt_console +{ + rt_uint8_t* video_ptr; + rt_uint8_t* font_ptr; + + /* bpp and pixel of width */ + rt_uint8_t bpp; + rt_uint32_t pitch; + + /* current cursor */ + rt_uint8_t current_col; + rt_uint8_t current_row; +}; +struct rt_console console; + +void rt_hw_console_init(rt_uint8_t* video_ptr, rt_uint8_t* font_ptr, rt_uint8_t bpp); +void rt_hw_console_newline(void); +void rt_hw_console_putc(char c); +void rt_hw_console_clear(void); + +void rt_hw_console_init(rt_uint8_t* video_ptr, rt_uint8_t* font_ptr, rt_uint8_t bpp) +{ + rt_memset(&console, 0, sizeof(struct rt_console)); + + console.video_ptr = video_ptr; + console.font_ptr = font_ptr; + console.bpp = bpp; + console.pitch = console.bpp * RT_CONSOLE_WIDTH; + + rt_hw_console_clear(); +} + +void rt_hw_console_putc(char c) +{ + switch (c) + { + case 10: + case 11: + case 12: + case 13: + /* to next line */ + rt_hw_console_newline(); + console.current_col = 0; + break; + + case 9: + console.current_col += RT_CONSOLE_TAB; + break; + + default: + { + rt_uint8_t* font_ptr; + register rt_uint32_t cursor; + register rt_uint32_t i, j; + + if (console.current_col == RT_CONSOLE_COL) + { + rt_hw_console_newline(); + console.current_col = 0; + + rt_hw_console_putc(c); + return; + } + + font_ptr = console.font_ptr + c * RT_CONSOLE_FONT_HEIGHT; + cursor = (console.current_row * RT_CONSOLE_FONT_HEIGHT) * console.pitch + + console.current_col * RT_CONSOLE_FONT_WIDTH * console.bpp; + + for (i = 0; i < RT_CONSOLE_FONT_HEIGHT; i ++ ) + { + for (j = 0; j < RT_CONSOLE_FONT_WIDTH; j ++) + { + if ( ((font_ptr[i] >> (7-j)) & 0x01) != 0 ) + { + /* draw a pixel */ + rt_uint8_t *ptr = &(console.video_ptr[cursor + i * console.pitch + j * console.bpp]); + switch(console.bpp) + { + case 1: + *ptr = RT_CONSOLE_FOREPIXEL; + break; + case 2: + *(rt_uint16_t*)ptr = RT_CONSOLE_FOREPIXEL; + break; + case 3: + ptr[0] = RT_CONSOLE_FOREPIXEL & 0xff; + ptr[1] = (RT_CONSOLE_FOREPIXEL >> 8) & 0xff; + ptr[2] = (RT_CONSOLE_FOREPIXEL >> 16) & 0xff; + break; + case 4: + *(rt_uint32_t*)ptr = RT_CONSOLE_FOREPIXEL; + break; + } + } + } + } + + console.current_col ++; + } + break; + } +} + +void rt_hw_console_newline() +{ + console.current_row ++; + if (console.current_row >= RT_CONSOLE_ROW) + { + rt_uint32_t i; + + /* scroll to next line */ + for (i = 0; i < RT_CONSOLE_ROW - 1; i ++) + { + rt_memcpy(console.video_ptr + i * RT_CONSOLE_FONT_HEIGHT * console.pitch, + console.video_ptr + (i + 1) * RT_CONSOLE_FONT_HEIGHT * console.pitch, + RT_CONSOLE_FONT_HEIGHT * console.pitch); + } + + /* clear last line */ + rt_memset(console.video_ptr + (RT_CONSOLE_ROW - 1) * RT_CONSOLE_FONT_HEIGHT * console.pitch, + 0, + RT_CONSOLE_FONT_HEIGHT * console.pitch); + + console.current_row = RT_CONSOLE_ROW - 1; + } +} + +void rt_hw_console_clear() +{ + console.current_col = 0; + console.current_row = 0; + + rt_memset(console.video_ptr, 0, RT_CONSOLE_HEIGHT * console.pitch); +} + +/* write one character to serial, must not trigger interrupt */ +void rt_hw_serial_putc(const char c) +{ + /* + to be polite with serial console add a line feed + to the carriage return character + */ + if (c=='\n')rt_hw_serial_putc('\r'); + + while (!(uart2.uart_device->SSR & SSR_TDRE)); + uart2.uart_device->TDR = (c & 0x1FF); +} + +/** + * This function is used by rt_kprintf to display a string on console. + * + * @param str the displayed string + */ +void rt_hw_console_output(const char* str) +{ + while (*str) + { + rt_hw_serial_putc(*str++); + } +} + diff --git a/bsp/mb9bf506r/fm3_easy_kit.ewp b/bsp/mb9bf506r/fm3_easy_kit.ewp new file mode 100644 index 0000000000..6036a59faf --- /dev/null +++ b/bsp/mb9bf506r/fm3_easy_kit.ewp @@ -0,0 +1,1894 @@ + + + + 2 + + Debug + + ARM + + 1 + + General + 3 + + 20 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 26 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 11 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 20 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 26 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 8 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 11 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + CMSIS + + $PROJ_DIR$\CMSIS\start_iar.S + + + $PROJ_DIR$\CMSIS\system_mb9bf50x.c + + + + Filesystem + + $PROJ_DIR$\..\..\components\dfs\src\dfs.c + + + $PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\dfs_elm.c + + + $PROJ_DIR$\..\..\components\dfs\src\dfs_file.c + + + $PROJ_DIR$\..\..\components\dfs\src\dfs_fs.c + + + $PROJ_DIR$\..\..\components\dfs\src\dfs_posix.c + + + $PROJ_DIR$\..\..\components\dfs\filesystems\elmfat\ff.c + + + + Finsh + + $PROJ_DIR$\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_compiler.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_error.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_heap.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_init.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_node.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_ops.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_parser.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_token.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_var.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_vm.c + + + $PROJ_DIR$\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\components\finsh\symbol.c + + + + FM3 + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\context_iar.S + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m3\cpuport.c + + + + Kernel + + $PROJ_DIR$\..\..\src\clock.c + + + $PROJ_DIR$\..\..\src\device.c + + + $PROJ_DIR$\..\..\src\idle.c + + + $PROJ_DIR$\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\src\irq.c + + + $PROJ_DIR$\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\src\mem.c + + + $PROJ_DIR$\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\src\module.c + + + $PROJ_DIR$\..\..\src\object.c + + + $PROJ_DIR$\..\..\src\rtm.c + + + $PROJ_DIR$\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\src\slab.c + + + $PROJ_DIR$\..\..\src\thread.c + + + $PROJ_DIR$\..\..\src\timer.c + + + + Startup + + $PROJ_DIR$\application.c + + + $PROJ_DIR$\board.c + + + $PROJ_DIR$\led.c + + + $PROJ_DIR$\nand.c + + + $PROJ_DIR$\serial.c + + + $PROJ_DIR$\startup.c + + + + + diff --git a/bsp/mb9bf506r/fm3_easy_kit.eww b/bsp/mb9bf506r/fm3_easy_kit.eww new file mode 100644 index 0000000000..bdaf802ebd --- /dev/null +++ b/bsp/mb9bf506r/fm3_easy_kit.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\fm3_easy_kit.ewp + + + + + diff --git a/bsp/mb9bf506r/fm3_rom.ld b/bsp/mb9bf506r/fm3_rom.ld new file mode 100644 index 0000000000..dc9f4c02b6 --- /dev/null +++ b/bsp/mb9bf506r/fm3_rom.ld @@ -0,0 +1,122 @@ +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + DATA (rw) : ORIGIN = 0x1FFFC000, LENGTH = 0x00010000 +} +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + _etext = .; + } > CODE = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > CODE + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >DATA + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + _estack = .; + + *(.bss.init) + } > DATA + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/mb9bf506r/led.c b/bsp/mb9bf506r/led.c new file mode 100644 index 0000000000..a1ab6a0592 --- /dev/null +++ b/bsp/mb9bf506r/led.c @@ -0,0 +1,141 @@ +/* + * File : led.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-03-03 lgnq + */ + +#include +#include + +#include "mb9bf506r.h" +#include "led.h" + +void rt_hw_led_on(rt_uint8_t num) +{ + RT_ASSERT(num < LEDS_MAX_NUMBER); + + switch (num) + { + case 1: + USER_LED_PDOR &= ~USER_LED1; + break; + case 2: + USER_LED_PDOR &= ~USER_LED2; + break; + case 3: + USER_LED_PDOR &= ~USER_LED3; + break; + default: + break; + } +} + +void rt_hw_led_off(rt_uint8_t num) +{ + RT_ASSERT(num < LEDS_MAX_NUMBER); + + switch (num) + { + case 1: + USER_LED_PDOR |= USER_LED1; + break; + case 2: + USER_LED_PDOR |= USER_LED2; + break; + case 3: + USER_LED_PDOR |= USER_LED3; + break; + default: + break; + } +} + +void rt_hw_led_toggle(rt_uint8_t num) +{ + RT_ASSERT(num < LEDS_MAX_NUMBER); + + switch (num) + { + case 1: + if (USER_LED_PDOR&USER_LED1) + USER_LED_PDOR &= ~USER_LED1; + else + USER_LED_PDOR |= USER_LED1; + break; + case 2: + if (USER_LED_PDOR&USER_LED2) + USER_LED_PDOR &= ~USER_LED2; + else + USER_LED_PDOR |= USER_LED2; + break; + case 3: + if (USER_LED_PDOR&USER_LED3) + USER_LED_PDOR &= ~USER_LED3; + else + USER_LED_PDOR |= USER_LED3; + break; + default: + break; + } +} + +void led_init(void) +{ + /*Select CPIO function*/ + USER_LED_PFR &= ~USER_LED_MASK; + /* disable analog input */ + FM3_GPIO->ADE &= ~USER_LED_MASK; + /*Set CPIO Pull-Up function*/ + USER_LED_PCR |= USER_LED_MASK; + /*Make led pins outputs*/ + USER_LED_DDR |= USER_LED_MASK; + USER_LED_PDOR |= USER_LED_MASK; +} + +void pwm_update(rt_uint16_t value) +{ + FM3_BT2_PWM->PDUT = value; +} + +static void led1_thread_entry(void *parameter) +{ + while (1) + { + rt_hw_led_toggle(1); + rt_thread_delay(RT_TICK_PER_SECOND); + } +} + +static void led2_thread_entry(void *parameter) +{ + while (1) + { + rt_hw_led_toggle(2); + rt_thread_delay(RT_TICK_PER_SECOND/2); + } +} + +static rt_thread_t led1_thread; +static rt_thread_t led2_thread; +void rt_hw_led_init(void) +{ + led_init(); + + led1_thread = rt_thread_create("led1", led1_thread_entry, RT_NULL, 384, 29, 5); + if (led1_thread != RT_NULL) + rt_thread_startup(led1_thread); + + led2_thread = rt_thread_create("led2", led2_thread_entry, RT_NULL, 384, 30, 5); + if (led2_thread != RT_NULL) + rt_thread_startup(led2_thread); +} + + diff --git a/bsp/mb9bf506r/led.h b/bsp/mb9bf506r/led.h new file mode 100644 index 0000000000..5db0980520 --- /dev/null +++ b/bsp/mb9bf506r/led.h @@ -0,0 +1,43 @@ +/* + * File : led.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2011, RT-Thread Develop Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-03-03 lgnq + */ + +#ifndef __LED_H__ +#define __LED_H__ + +#include "mb9bf506r.h" + +#define LEDS_MAX_NUMBER 4 + +/* LED */ +#define USER_LED1 (1UL<<0x9) +#define USER_LED2 (1UL<<0xa) +#define USER_LED3 (1UL<<0xb) + +#define USER_LED_MASK (USER_LED1 | USER_LED2 | USER_LED3) +#define USER_LED_PFR FM3_GPIO->PFR1 +#define USER_LED_PCR FM3_GPIO->PCR1 +#define USER_LED_PDOR FM3_GPIO->PDOR1 +#define USER_LED_DDR FM3_GPIO->DDR1 + +#define RT_DEVICE_CTRL_LED_ON 0 +#define RT_DEVICE_CTRL_LED_OFF 1 +#define RT_DEVICE_CTRL_LED_TOGGLE 2 + +void rt_hw_led_init(void); +void rt_hw_led_on(rt_uint8_t num); +void rt_hw_led_off(rt_uint8_t num); +void rt_hw_led_toggle(rt_uint8_t num); +void pwm_update(rt_uint16_t value); + +#endif diff --git a/bsp/mb9bf506r/mb9bf506.icf b/bsp/mb9bf506r/mb9bf506.icf new file mode 100644 index 0000000000..63518e1ee9 --- /dev/null +++ b/bsp/mb9bf506r/mb9bf506.icf @@ -0,0 +1,33 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x1FFF8000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +keep { section FSymTab }; +keep { section VSymTab }; +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/mb9bf506r/nand.c b/bsp/mb9bf506r/nand.c new file mode 100644 index 0000000000..ada61e3f92 --- /dev/null +++ b/bsp/mb9bf506r/nand.c @@ -0,0 +1,667 @@ +/* + * File : nand.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-05-25 Bernard first version + */ + +#include "nand.h" +#include "mb9bf506r.h" + +/* + * NandFlash driver for SamSung K9F5608 + * 32M x 8bit + */ +#define PAGE_SIZE 512 +#define PAGE_PER_BLOCK 32 +#define BLOCK_NUM 2048 + +/* device driver debug trace */ +/* #define NAND_DEBUG */ +#ifdef NAND_DEBUG +#define trace_log rt_kprintf +#else +#define trace_log(...) +#endif + +/* + * OOB, + * when block has been erased, OOB is 0xff. + * when block has been written, OOB is 0x00. + */ +struct rt_device_nand +{ + struct rt_device parent; /* which is inherited from rt_device */ + + rt_uint16_t block_num; /* total block number in device */ + rt_uint16_t page_per_block; /* pages in one block */ + rt_uint16_t page_size; /* page size */ + + /* this buffer which used as to save data before erase block */ + rt_uint8_t block_buffer[PAGE_SIZE * PAGE_PER_BLOCK]; +}; +static struct rt_device_nand _nand; + +/* Flash operation definition */ +#define NF_CMD(cmd) {*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_CMD_OFFSET) = (unsigned char)(cmd);} +#define NF_ADDR(addr) {*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_ADDR_OFFSET)= (unsigned char)(addr);} +#define NF_RDDATA() (*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_DATA_OFFSET)) +#define NF_WRDATA(data) {*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_DATA_OFFSET)= (unsigned char)(data);} +#define NF_CLR_ALE() {*(volatile unsigned char*)(NF_FLASH_BASE_ADDR+NF_ALE_OFFSET) = (unsigned char)0;} + +/* Flash Control IO definition */ +#define NF_OE_H() {IO_NF_PDOR |= NF_EN;} +#define NF_OE_L() {IO_NF_PDOR &= ~NF_EN;} + +#define NF_DATA_OUT() {IO_NF_PDOR &= ~NF_DATA_DIR;} +#define NF_DATA_IN() {IO_NF_PDOR |= NF_DATA_DIR;} + +static unsigned char NF_ReadStatus(void); +static void Wait(unsigned int cnt); +static void NF_Reset(void); + +static void Wait(unsigned int cnt) +{ + while(cnt--); +} + +static void NF_Reset(void) +{ + NF_OE_L(); + NF_DATA_OUT(); + NF_CMD(NAND_CMD_RESET); + NF_OE_H(); + + Wait(10000); /* wait for Trst */ +} + +static unsigned char NF_ReadStatus(void) +{ + unsigned int timeout=0; + NF_DATA_OUT(); + NF_CMD(NAND_CMD_STATUS); + NF_DATA_IN(); + + while(!(NF_RDDATA() & 0x40)) + { + timeout++; + if(timeout == 0x00080000) + return FLASH_NG; + } + if(NF_RDDATA() & 0x01)return FLASH_NG; + + return FLASH_OK; +} + +/* + * @ Funciton: NF_Init + * Parameter: None + * Return: None + */ +static void NF_Init(void) +{ + FM3_GPIO->PFR5 |= (0x7ff); /* D0-D5, CS7, ALE, CLE, WEX, REX */ + FM3_GPIO->PFR3 |= (0x3); /* D6-D7 */ + FM3_GPIO->EPFR10 |= (1<<13 /* CS enable */ + |1<<6 /* ALE, CLE, WEX, REX enable */ + |1<<0); /* D0-D7 enable */ + FM3_EXBUS->AREA7 = 0x001f00e0; /* Select CS7 area, 32Mbyte size */ + FM3_EXBUS->MODE7 |= (1<<4); /* Nand Flash mode turn on, set 8 bit width */ + + IO_NF_PFR = IO_NF_PFR & ~(NF_EN|NF_DATA_DIR); + IO_NF_DDR = IO_NF_DDR | (NF_EN|NF_DATA_DIR); + IO_NF_PDOR = IO_NF_PDOR | (NF_EN | NF_DATA_DIR); /* disable Flash operation */ + + /*Reset NAND*/ + NF_Reset(); +} + +static void NF_UnInit(void) +{ + FM3_GPIO->PFR5 &= ~(0x7ff); /* disable D0-D5, CS7, ALE, CLE, WEX, REX */ + FM3_GPIO->PFR3 &= ~(0x3); /* disable D6-D7 */ + FM3_GPIO->EPFR10 &= ~(1<<13 /* disable CS enable */ + |1<<6 /* disable ALE, CLE, WEX, REX enable */ + |1<<0); /* disable D0-D7 enable */ + FM3_EXBUS->MODE7 &= ~(1<<4); + IO_NF_PFR = IO_NF_PFR & ~(NF_EN|NF_DATA_DIR); + IO_NF_DDR = IO_NF_DDR | (NF_EN|NF_DATA_DIR); + IO_NF_PDOR = IO_NF_PDOR | (NF_EN | NF_DATA_DIR); /* disable Flash operation */ +} + +/* + * @ Funciton: NF_ReadPage + * Parameter: block (max: 2048) + * page (max:32) + * buffer: pointer to data buffer + * Return: 0: Flash Operation OK + * 1: Flash Operation NG + */ +int NF_ReadPage(unsigned int block, unsigned int page, unsigned char *buffer, + unsigned char *oob) +{ + unsigned int blockPage,i; + + NF_Init(); + blockPage=(block<<5)+page; /* 1 block=32 page */ + NF_OE_L(); + NF_DATA_OUT(); + if (buffer != RT_NULL) + { + volatile unsigned char ch; + + NF_CMD(NAND_CMD_READ0); /* send read data */ + + NF_ADDR(0); + NF_ADDR(blockPage & 0xff); + NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ + NF_CLR_ALE(); + NF_DATA_IN(); + + Wait(500); + + for(i=0;i<512;i++) /* read 512 bytes data */ + buffer[i] = NF_RDDATA(); + for(i=0;i<16;i++) /* read 16 bytes oob */ + if (oob != RT_NULL) + oob[i] = NF_RDDATA(); + else + ch = NF_RDDATA(); + } + else + { + NF_CMD(NAND_CMD_READOOB); /* send read data */ + + NF_ADDR(0); + NF_ADDR(blockPage & 0xff); + NF_ADDR((blockPage>>8) & 0xff); /* send 3 byte address */ + NF_CLR_ALE(); + NF_DATA_IN(); + + Wait(500); + + for (i=0; i<16; i++) /* read 16 bytes oob */ + oob[i] = NF_RDDATA(); + } + + NF_OE_H(); + NF_UnInit(); + return 0; +} + +/* + * @ Funciton: NF_EraseBlock + * Parameter: block (max: 2048) + * Return: 0: Flash Operation OK + * 1: Flash Operation NG + */ +int NF_EraseBlock(unsigned int block) +{ + rt_uint32_t blockPage; + + trace_log("Erase block %d: ", block); + + NF_Init(); + blockPage = (block << 5); + NF_OE_L(); + NF_DATA_OUT(); + NF_CMD(NAND_CMD_ERASE1); /* send erase command */ + NF_ADDR(blockPage & 0xff); + NF_ADDR((blockPage >> 8) & 0xff); + NF_CMD(NAND_CMD_ERASE2); /* start erase */ + + if(NF_ReadStatus()) + { + NF_Reset(); + NF_OE_H(); + NF_UnInit(); + trace_log("Failed\n"); + rt_kprintf("erase block failed\n"); + + return FLASH_NG; + } + + NF_OE_H(); + NF_UnInit(); + + trace_log("OK\n"); + + return FLASH_OK; +} + +/* + * @ Funciton: NF_WritePage + * Parameter: block (max: 2048) + * page (max:32) + * buffer: pointer to data buffer + * Return: 0: Flash Operation OK + * 1: Flash Operation NG + */ +int NF_WritePage(unsigned block, unsigned page, const rt_uint8_t *buffer) +{ + unsigned int blockPage,i; + unsigned char se[16] = {0}; + unsigned char data; + + blockPage = (block<<5)+page; + NF_Init(); + NF_OE_L(); + NF_DATA_OUT(); + NF_CMD(0x00); /* set programming area */ + NF_CMD(NAND_CMD_SEQIN); /* send write command */ + NF_ADDR(0); + NF_ADDR(blockPage & 0xff); + NF_ADDR((blockPage>>8) & 0xff); + NF_CLR_ALE(); + + for(i=0;i<512;i++) NF_WRDATA(buffer[i]); /* write data */ + for(i=0;i<16;i++) NF_WRDATA(se[i]); /* dummy write */ + + NF_CMD(NAND_CMD_PAGEPROG); /* start programming */ + + if(NF_ReadStatus()) + { + NF_Reset(); + NF_OE_H(); + NF_UnInit(); + + trace_log("write failed\n"); + return FLASH_NG; + } + + /* verify the write data */ + NF_DATA_OUT(); + NF_CMD(NAND_CMD_READ0); /* send read command */ + NF_ADDR(0); + NF_ADDR(blockPage & 0xff); + NF_ADDR((blockPage>>8) & 0xff); + NF_CLR_ALE(); + NF_DATA_IN(); + + Wait(500); + for(i=0; i<512; i++) + { + data=NF_RDDATA(); /* verify 1-512 byte */ + if(data != buffer[i]) + { + trace_log("block %d, page %d\n", block , page); + trace_log("write data failed[%d]: %02x %02x\n", i, data, buffer[i]); + + NF_Reset(); + NF_OE_H(); + NF_UnInit(); + return FLASH_NG; + } + } + + for(i=0; i<16; i++) + { + data=NF_RDDATA(); /* verify 16 byte dummy data */ + if(data != se[i]) + { + trace_log("block %d, page %d\n", block , page); + trace_log("write oob failed[%d]: %02x %02x\n", i, data, se[i]); + NF_Reset(); + NF_OE_H(); + NF_UnInit(); + return FLASH_NG; + } + } + + NF_OE_H(); + NF_UnInit(); + return FLASH_OK; +} + +/* + * @ Funciton: NF_ReadID + * Parameter: id: pointer to device ID + * Return: None + */ +void NF_ReadID(unsigned char *id) +{ + unsigned char maker_code; + NF_Init(); + NF_OE_L(); + NF_DATA_OUT(); + NF_CMD(NAND_CMD_READID); + NF_ADDR(0x00); + NF_CLR_ALE(); + Wait(10); + NF_DATA_IN(); + maker_code = NF_RDDATA(); + maker_code = maker_code; + *id = NF_RDDATA(); + NF_OE_H(); + NF_UnInit(); +} + +static rt_err_t rt_nand_init (rt_device_t dev) +{ + /* empty implementation */ + return RT_EOK; +} + +static rt_err_t rt_nand_open(rt_device_t dev, rt_uint16_t oflag) +{ + /* empty implementation */ + return RT_EOK; +} + +static rt_err_t rt_nand_close(rt_device_t dev) +{ + /* empty implementation */ + return RT_EOK; +} + +/* nand device read */ +static rt_size_t rt_nand_read (rt_device_t dev, rt_off_t pos, void* buffer, + rt_size_t size) +{ + rt_ubase_t block; /* block of position */ + rt_ubase_t page, index; /* page in block of position */ + rt_uint8_t *page_ptr, oob[16]; + struct rt_device_nand *nand; + + /* get nand device */ + nand = (struct rt_device_nand*) dev; + RT_ASSERT(nand != RT_NULL); + + /* get block and page */ + block = pos / nand->page_per_block; + page = pos % nand->page_per_block; + + trace_log("nand read: position %d, block %d, page %d, size %d\n", + pos, block, page, size); + + /* set page buffer pointer */ + page_ptr = (rt_uint8_t*) buffer; + for (index = 0; index < size; index ++) + { + NF_ReadPage(block, page + index, page_ptr, oob); + page_ptr += nand->page_size; + + if (page + index > nand->page_per_block) + { + block += 1; + page = 0; + } + } + + /* return read size (count of block) */ + return size; +} + +/* + * write pages by erase block first + * @param nand the nand device driver + * @param block the block of page + * @param page the page + * @param buffer the data buffer to be written + * @param pages the number of pages to be written + */ +static int rt_nand_eraseblock_writepage(struct rt_device_nand* nand, + rt_ubase_t block, rt_ubase_t page, + const rt_uint8_t *buffer, rt_ubase_t pages) +{ + rt_ubase_t index; + rt_uint32_t page_status; + rt_uint8_t *page_ptr, oob[16]; + + /* set page status */ + page_status = 0; + + /* read each page in block */ + page_ptr = nand->block_buffer; + for (index = 0; index < nand->page_per_block; index ++) + { + NF_ReadPage(block, index, page_ptr, oob); + if (!oob[0]) + page_status |= (1 << index); + page_ptr += nand->page_size; + } + + /* erase block */ + NF_EraseBlock(block); + + page_ptr = &(nand->block_buffer[page * nand->page_size]); + /* merge buffer to page buffer */ + for (index = 0; index < pages; index ++) + { + rt_memcpy(page_ptr, buffer, nand->page_size); + + /* set page status */ + page_status |= (1 << (page + index)); + + /* move to next page */ + page_ptr += nand->page_size; + buffer += nand->page_size; + } + + /* write to flash */ + page_ptr = nand->block_buffer; + for (index = 0; index < nand->page_per_block; index ++) + { + if (page_status & (1 << index)) + NF_WritePage(block, index, page_ptr); + + /* move to next page */ + page_ptr += nand->page_size; + } + + return 0; +} + +/* nand device write */ +static rt_size_t rt_nand_write (rt_device_t dev, rt_off_t pos, + const void* buffer, rt_size_t size) +{ + rt_ubase_t block, page; + rt_uint8_t oob[16]; + struct rt_device_nand *nand; + + nand = (struct rt_device_nand*) dev; + RT_ASSERT(nand != RT_NULL); + + /* get block and page */ + block = pos / nand->page_per_block; + page = pos % nand->page_per_block; + + trace_log("nand write: position %d, block %d, page %d, size %d\n", + pos, block, page, size); + + if (size == 1) + { + /* write one page */ + + /* read oob to get page status */ + NF_ReadPage(block, page, RT_NULL, oob); + if (oob[0]) + NF_WritePage(block, page, buffer); + else + /* erase block and then write page */ + rt_nand_eraseblock_writepage(nand, block, page, buffer, 1); + } + else if (size > 1) + { + rt_ubase_t index; + rt_ubase_t need_erase_block; + const rt_uint8_t *page_ptr; + rt_ubase_t chunk_pages, pages; + + pages = size; + page_ptr = (const rt_uint8_t*) buffer; + do + { + need_erase_block = 0; + /* calculate pages in current chunk */ + if (pages > nand->page_per_block - page) + chunk_pages = nand->page_per_block - page; + else + chunk_pages = pages; + + /* get page status in current block */ + for (index = page; index < page + chunk_pages; index ++) + { + NF_ReadPage(block, index, RT_NULL, oob); + if (!oob[0]) + { + /* this page has data, need erase this block firstly */ + need_erase_block = 1; + break; + } + } + + if (need_erase_block) + { + /* erase block and then write it */ + rt_nand_eraseblock_writepage(nand, block, page, page_ptr, chunk_pages); + page_ptr += chunk_pages * nand->page_size; + } + else + { + /* write pages directly */ + for (index = page; index < page + chunk_pages; index ++) + { + NF_WritePage(block, index, page_ptr); + page_ptr += nand->page_size; + } + } + + pages -= chunk_pages; + page = 0; block ++; /* move to next block */ + } + while (pages); + } + + return size; +} + +static rt_err_t rt_nand_control (rt_device_t dev, rt_uint8_t cmd, void *args) +{ + struct rt_device_nand *nand; + + nand = (struct rt_device_nand*) dev; + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_BLK_GETGEOME: + { + struct rt_device_blk_geometry *geometry; + + geometry = (struct rt_device_blk_geometry *)args; + if (geometry == RT_NULL) return -RT_ERROR; + + geometry->bytes_per_sector = nand->page_size; + geometry->block_size = nand->page_size * nand->page_per_block; + geometry->sector_count = nand->block_num * nand->page_per_block; + } + break; + } + + return RT_EOK; +} + +void rt_hw_nand_init(void) +{ + /* initialize nand flash structure */ + _nand.block_num = BLOCK_NUM; + _nand.page_per_block = PAGE_PER_BLOCK; + _nand.page_size = PAGE_SIZE; + + rt_memset(_nand.block_buffer, 0, sizeof(_nand.block_buffer)); + + _nand.parent.type = RT_Device_Class_MTD; + _nand.parent.rx_indicate = RT_NULL; + _nand.parent.tx_complete = RT_NULL; + _nand.parent.init = rt_nand_init; + _nand.parent.open = rt_nand_open; + _nand.parent.close = rt_nand_close; + _nand.parent.read = rt_nand_read; + _nand.parent.write = rt_nand_write; + _nand.parent.control = rt_nand_control; + + /* register a MTD device */ + rt_device_register(&(_nand.parent), "nand", RT_DEVICE_FLAG_RDWR); +} + +#ifdef NAND_DEBUG +#include +unsigned char nand_buffer[512]; +unsigned char nand_oob[16]; + +void dump_mem(unsigned char* buffer, int length) +{ + int i; + + if (length > 64) length = 64; + for (i = 0; i < length; i ++) + { + rt_kprintf("%02x ", *buffer++); + if (((i+1) % 16) == 0) + rt_kprintf("\n"); + } + rt_kprintf("\n"); +} + +void nand_read(int block, int page) +{ + rt_kprintf("read block %d, page %d\n", block, page); + + NF_ReadPage(block, page, nand_buffer, nand_oob); + rt_kprintf("page data:\n"); + dump_mem(nand_buffer, 512); + rt_kprintf("oob data:\n"); + dump_mem(nand_oob, 16); +} +FINSH_FUNCTION_EXPORT_ALIAS(nand_read, read_page, read page[block/page]); + +void nand_write(int block, int page) +{ + int i; + for (i = 0; i < 512; i ++) + nand_buffer[i] = i; + + NF_WritePage(block, page, nand_buffer); +} +FINSH_FUNCTION_EXPORT_ALIAS(nand_write, write_page, write page[block/page]); + +void nand_erase(int block) +{ + NF_EraseBlock(block); +} +FINSH_FUNCTION_EXPORT_ALIAS(nand_erase, erase_block, erase block[block]); + +void nand_readoob(int block, int page) +{ + rt_kprintf("read oob on block %d, page %d\n", block, page); + + NF_ReadPage(block, page, RT_NULL, (unsigned char*)nand_oob); + rt_kprintf("oob data:\n"); + dump_mem(nand_oob, 16); +} +FINSH_FUNCTION_EXPORT_ALIAS(nand_readoob, readoob, read oob[block/page]); + +void nand_erase_chip() +{ + int i; + unsigned char id; + + NF_ReadID(&id); + rt_kprintf("id: %02x\n", id); + + for (i = 0; i < 2048; i ++) + { + NF_EraseBlock(i); + } +} +FINSH_FUNCTION_EXPORT_ALIAS(nand_erase_chip, erase_chip, erase whole chip); +#endif diff --git a/bsp/mb9bf506r/nand.h b/bsp/mb9bf506r/nand.h new file mode 100644 index 0000000000..ffb4bae2c3 --- /dev/null +++ b/bsp/mb9bf506r/nand.h @@ -0,0 +1,57 @@ +/* + * File : nand.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-05-25 Bernard first version + */ + +#ifndef __NAND_H__ +#define __NAND_H__ + +#include + +#define IO_NF_PFR FM3_GPIO->PFR3 +#define IO_NF_DDR FM3_GPIO->DDR3 +#define IO_NF_PDOR FM3_GPIO->PDOR3 + +#define NF_EN 0x0008 +#define NF_DATA_DIR 0x0004 + +#define EXT_BUS_BASE_ADDR 0x60000000 +#define EXT_CS7_OFFSET 0x0E000000 +#define EXT_CS7_SIZE 0x02000000 + +#define NF_FLASH_BASE_ADDR (EXT_BUS_BASE_ADDR+EXT_CS7_OFFSET) + +#define NF_ALE_OFFSET 0x00003000 +#define NF_ADDR_OFFSET 0x00002000 +#define NF_CMD_OFFSET 0x00001000 +#define NF_DATA_OFFSET 0x00000000 + +/* NAND command */ +#define NAND_CMD_READ0 0x00 +#define NAND_CMD_READ1 0x01 +#define NAND_CMD_PAGEPROG 0x10 +#define NAND_CMD_READOOB 0x50 +#define NAND_CMD_ERASE1 0x60 +#define NAND_CMD_STATUS 0x70 +#define NAND_CMD_SEQIN 0x80 +#define NAND_CMD_READID 0x90 +#define NAND_CMD_READID1 0x91 +#define NAND_CMD_ERASE2 0xd0 +#define NAND_CMD_RESET 0xff + +#define FLASH_OK 0 +#define FLASH_NG 1 + +/* nand flash device initialization */ +void rt_hw_nand_init(void); + +#endif diff --git a/bsp/mb9bf506r/rtconfig.h b/bsp/mb9bf506r/rtconfig.h new file mode 100644 index 0000000000..a0c04cbe9a --- /dev/null +++ b/bsp/mb9bf506r/rtconfig.h @@ -0,0 +1,90 @@ +/* RT-Thread config file */ +#ifndef __RTTHREAD_CFG_H__ +#define __RTTHREAD_CFG_H__ + +/* RT_NAME_MAX*/ +#define RT_NAME_MAX 8 + +/* RT_ALIGN_SIZE*/ +#define RT_ALIGN_SIZE 4 + +/* PRIORITY_MAX */ +#define RT_THREAD_PRIORITY_MAX 32 + +/* Tick per Second */ +#define RT_TICK_PER_SECOND 100 + +/* SECTION: RT_DEBUG */ +/* Thread Debug */ +#define RT_DEBUG +#define RT_USING_OVERFLOW_CHECK + +/* Using Hook */ +#define RT_USING_HOOK + +/* SECTION: IPC */ +/* Using Semaphore */ +#define RT_USING_SEMAPHORE + +/* Using Mutex */ +#define RT_USING_MUTEX + +/* Using Event */ +#define RT_USING_EVENT + +/* Using MailBox */ +#define RT_USING_MAILBOX + +/* Using Message Queue */ +#define RT_USING_MESSAGEQUEUE + +/* SECTION: Memory Management */ +/* Using Memory Pool Management*/ +#define RT_USING_MEMPOOL + +/* Using Dynamic Heap Management */ +#define RT_USING_HEAP + +/* Using Small MM */ +#define RT_USING_SMALL_MEM + +/* SECTION: Device System */ +/* Using Device System */ +#define RT_USING_DEVICE +/* RT_USING_UART */ +#define RT_USING_UART2 +#define RT_UART_RX_BUFFER_SIZE 64 + +/* SECTION: Console options */ +/* #define RT_TINY_SIZE */ +#define RT_USING_CONSOLE +/* the buffer size of console */ +#define RT_CONSOLEBUF_SIZE 128 + +/* SECTION: finsh, a C-Express shell */ +/* Using FinSH as Shell*/ +#define RT_USING_FINSH +/* Using symbol table */ +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_STACK_SIZE 1024 + +/* SECTION: Device filesystem support */ +/* using DFS support */ +#define RT_USING_DFS +#define RT_USING_DFS_ELMFAT +/* use long file name feature */ +/* #define RT_DFS_ELM_USE_LFN */ +/* the max number of file length */ +#define RT_DFS_ELM_MAX_LFN 32 +/* #define RT_USING_DFS_UFFS */ +/* #define RT_USING_DFS_DEVFS */ + +/* the max number of mounted filesystem */ +#define DFS_FILESYSTEMS_MAX 2 +/* the max number of opened files */ +#define DFS_FD_MAX 8 +/* using working directory */ +#define DFS_USING_WORKDIR + +#endif diff --git a/bsp/mb9bf506r/rtconfig.py b/bsp/mb9bf506r/rtconfig.py new file mode 100644 index 0000000000..5d6ae38317 --- /dev/null +++ b/bsp/mb9bf506r/rtconfig.py @@ -0,0 +1,113 @@ +# toolchains options +ARCH='arm' +CPU='cortex-m3' +CROSS_TOOL='gcc' + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR + +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = 'C:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = 'C:/Keil' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + IAR_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation' + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'axf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-fm3.map,-cref,-u,Reset_Handler -T fm3_rom.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --device DARMSTM' + CFLAGS = DEVICE + ' --apcs=interwork' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-stm32.map --scatter stm32_rom.sct' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + CFLAGS = '' + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --debug' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M3' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M3' + AFLAGS += ' --fpu None' + AFLAGS += ' -I"' + IAR_PATH + '/arm/INC"' + + LFLAGS = ' --config mb9bf506.icf' + LFLAGS += ' --semihosting' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = IAR_PATH + '/arm/bin/' + POST_ACTION = 'ielftool.exe --srec --verbose $TARGET rtthread.srec' diff --git a/bsp/mb9bf506r/serial.c b/bsp/mb9bf506r/serial.c new file mode 100644 index 0000000000..a5116fc7e3 --- /dev/null +++ b/bsp/mb9bf506r/serial.c @@ -0,0 +1,348 @@ +/* + * File : serial.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-03-13 Bernard first version + * 2011-05-15 lgnq modified according bernard's implementaion. + */ + +#include + +#include "serial.h" + +/** + * @addtogroup FM3 MB9B500 + */ +/*@{*/ + +/* RT-Thread Device Interface */ +/** + * This function initializes serial + */ +static rt_err_t rt_serial_init (rt_device_t dev) +{ + struct serial_device* uart = (struct serial_device*) dev->user_data; + + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } + + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + + return RT_EOK; +} + +/* save a char to serial buffer */ +static void rt_serial_savechar(struct serial_device* uart, char ch) +{ + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; + + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); +} + +static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) +{ + struct serial_device* uart; + + RT_ASSERT(dev != RT_NULL); + uart = (struct serial_device*) dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable interrupt */ + UART_ENABLE_IRQ(uart->rx_irq); + } + + return RT_EOK; +} + +static rt_err_t rt_serial_close(rt_device_t dev) +{ + struct serial_device* uart; + + RT_ASSERT(dev != RT_NULL); + uart = (struct serial_device*) dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable interrupt */ + UART_DISABLE_IRQ(uart->rx_irq); + } + + return RT_EOK; +} + +static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, + rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; + + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (uart->uart_device->SSR & SSR_RDRF) + { + *ptr = uart->uart_device->RDR & 0xff; + ptr ++; + } + } + } + + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, + const void* buffer, rt_size_t size) +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; + + -- size; + + /* move to next position */ + uart->int_tx->save_index ++; + + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } + + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while (!(uart->uart_device->SSR & SSR_TDRE)); + uart->uart_device->TDR = '\r'; + } + + while (!(uart->uart_device->SSR & SSR_TDRE)); + uart->uart_device->TDR = (*ptr & 0x1FF); + + ++ptr; --size; + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; +} + +static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args) +{ + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } + + return RT_EOK; +} + +/* + * serial register + */ +rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, + rt_uint32_t flag, struct serial_device *serial) +{ + RT_ASSERT(device != RT_NULL); + + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; + + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); +} + +/* ISR for serial interrupt */ +void rt_hw_serial_isr(rt_device_t device) +{ + struct serial_device* uart = (struct serial_device*) device->user_data; + + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* save on rx buffer */ + while (uart->uart_device->SSR & SSR_RDRF) + { + rt_serial_savechar(uart, uart->uart_device->RDR & 0xff); + } + + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; + + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; + + device->rx_indicate(device, rx_length); + } +} + +#ifdef RT_USING_UART2 +/* UART2 device driver structure */ +#define UART2 FM3_MFS2_UART +struct serial_int_rx uart2_int_rx; +struct serial_device uart2 = +{ + UART2, + MFS2RX_IRQn, + MFS2TX_IRQn, + &uart2_int_rx, + RT_NULL +}; +struct rt_device uart2_device; + +void MFS2RX_IRQHandler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + rt_hw_serial_isr(&uart2_device); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +void rt_hw_serial_init(void) +{ +#ifdef RT_USING_UART2 + /* initialize UART2 */ + /* Set Uart Ch2 Port, SIN2_1, SOT2_1 */ + FM3_GPIO->PFR2 = FM3_GPIO->PFR2 | 0x0030; + FM3_GPIO->EPFR07 = FM3_GPIO->EPFR07 | 0x000a0000; + + uart2.uart_device->SMR = SMR_MD_UART | SMR_SOE;; + uart2.uart_device->BGR = (40000000UL + (BPS/2))/BPS - 1; + uart2.uart_device->ESCR = ESCR_DATABITS_8; + uart2.uart_device->SCR = SCR_RXE | SCR_TXE | SCR_RIE; + + /* register UART2 device */ + rt_hw_serial_register(&uart2_device, + "uart2", + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, + &uart2); +#endif +} + +/*@}*/ diff --git a/bsp/mb9bf506r/serial.h b/bsp/mb9bf506r/serial.h new file mode 100644 index 0000000000..1fd05d429d --- /dev/null +++ b/bsp/mb9bf506r/serial.h @@ -0,0 +1,99 @@ +/* + * File : serial.h + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2006, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2006-03-13 Bernard first version + * 2011-05-15 lgnq modified according bernard's implementaion. + */ + +#ifndef __RT_HW_SERIAL_H__ +#define __RT_HW_SERIAL_H__ + +#include +#include + +#include "mb9bf506r.h" + +#define SMR_SOE 0x01U +#define SMR_BDS 0x04U +#define SMR_SBL 0x08U +#define SMR_WUCR 0x10U +#define SMR_MD_UART 0x00U +#define SMR_MD_UART_MP 0x20U +#define SMR_MD_SIO 0x40U +#define SMR_MD_LIN 0x60U +#define SMR_MD_I2C 0x80U + +#define SCR_TXE 0x01U +#define SCR_RXE 0x02U +#define SCR_TBIE 0x04U +#define SCR_TIE 0x08U +#define SCR_RIE 0x10U +#define SCR_UPGL 0x80U + +#define SSR_TBI 0x01U +#define SSR_TDRE 0x02U +#define SSR_RDRF 0x04U +#define SSR_ORE 0x08U +#define SSR_FRE 0x10U +#define SSR_PE 0x20U +#define SSR_REC 0x80U + +#define ESCR_P 0x08U +#define ESCR_PEN 0x10U +#define ESCR_INV 0x20U +#define ESCR_ESBL 0x40U +#define ESCR_FLWEN 0x80U +#define ESCR_DATABITS_8 0x00U +#define ESCR_DATABITS_5 0x01U +#define ESCR_DATABITS_6 0x02U +#define ESCR_DATABITS_7 0x03U +#define ESCR_DATABITS_9 0x04U + +#define BPS 115200 /* serial baudrate */ + +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 + +struct serial_int_rx +{ + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; +}; + +struct serial_int_tx +{ + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; +}; + +/* + * Enable/DISABLE Interrupt Controller + */ +/* deviation from MISRA-C:2004 Rule 19.7 */ +#define UART_ENABLE_IRQ(n) NVIC_EnableIRQ((n)) +#define UART_DISABLE_IRQ(n) NVIC_DisableIRQ((n)) + +struct serial_device +{ + FM3_MFS03_UART_TypeDef* uart_device; + /* irq number */ + IRQn_Type rx_irq, tx_irq; + + /* rx structure */ + struct serial_int_rx* int_rx; + /* tx structure */ + struct serial_int_tx* int_tx; +}; + +void rt_hw_serial_isr(rt_device_t device); +void rt_hw_serial_init(void); + +#endif diff --git a/bsp/mb9bf506r/startup.c b/bsp/mb9bf506r/startup.c new file mode 100644 index 0000000000..073318abeb --- /dev/null +++ b/bsp/mb9bf506r/startup.c @@ -0,0 +1,122 @@ +/* + * File : startup.c + * This file is part of RT-Thread RTOS + * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rt-thread.org/license/LICENSE + * + * Change Logs: + * Date Author Notes + * 2011-02-24 Bernard first implementation + */ + +#include +#include + +#include "board.h" +#include "mb9bf506r.h" +#ifdef RT_USING_FINSH +#include +#endif + +/** + * @addtogroup FM3 + */ + +extern struct serial_device uart0; +extern struct rt_device uart0_device; +extern struct serial_device uart2; +extern struct rt_device uart2_device; + +/*@{*/ + +extern int rt_application_init(void); +#ifdef RT_USING_FINSH +extern void finsh_system_init(void); +#endif + +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#elif __ICCARM__ +#pragma section="HEAP" +#else +extern int __bss_end; +#endif + +/** + * This function will startup RT-Thread RTOS. + */ +void rtthread_startup(void) +{ + /* init board */ + rt_hw_board_init(); + + /* show version */ + rt_show_version(); + + /* init tick */ + rt_system_tick_init(); + /* init timer system */ + rt_system_timer_init(); + +#ifdef RT_USING_HEAP + #ifdef __CC_ARM + rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)FM3_SRAM_END); + #elif __ICCARM__ + rt_system_heap_init(__segment_end("HEAP"), (void*)FM3_SRAM_END); + #else + /* init memory system */ + rt_system_heap_init((void*)&__bss_end, (void*)FM3_SRAM_END); + #endif +#endif + + /* init scheduler system */ + rt_system_scheduler_init(); + +#ifdef RT_USING_DFS +#ifdef RT_USING_DFS_UFFS + rt_hw_nand_init(); +#endif +#endif + + /* init application */ + rt_application_init(); + +#ifdef RT_USING_FINSH + /* init finsh */ + finsh_system_init(); +#ifdef RT_USING_DEVICE + finsh_set_device("uart2"); +#endif +#endif + + /* init timer thread */ + rt_system_timer_thread_init(); + + /* init idle thread */ + rt_thread_idle_init(); + + /* start scheduler */ + rt_system_scheduler_start(); + + /* never reach here */ + return ; +} + +int main(void) +{ + /* disable interrupt first */ + rt_hw_interrupt_disable(); + + /* init system setting */ + SystemInit(); + + /* startup RT-Thread RTOS */ + rtthread_startup(); + + return 0; +} + +/*@}*/ -- cgit v1.3.1