From 94221bbdd88cbd6edd208b67d7c246b7f934a17e Mon Sep 17 00:00:00 2001 From: YuQi Date: Sat, 15 Oct 2022 12:56:00 +0800 Subject: [bsp][c28x] 新增adc驱动 (#6520) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1. 在c28x文件目录上一层再套一层文件夹ti，目前28379的项目路径为rt-thread\bsp\ti\c28x\tms320f28379d 2. 新增adc驱动与kconfig配置 --- bsp/c28x/libraries/HAL_Drivers/config/pwm_config.h | 69 - bsp/c28x/libraries/HAL_Drivers/drv_config.h | 16 - bsp/c28x/libraries/HAL_Drivers/drv_gpio.c | 439 - bsp/c28x/libraries/HAL_Drivers/drv_gpio.h | 44 - bsp/c28x/libraries/HAL_Drivers/drv_pwm.c | 587 - bsp/c28x/libraries/HAL_Drivers/drv_pwm.h | 26 - bsp/c28x/libraries/HAL_Drivers/drv_sci.c | 265 - bsp/c28x/libraries/HAL_Drivers/drv_sci.h | 16 - .../common/include/F2837xD_Adc_defines.h | 87 - .../common/include/F2837xD_Can_defines.h | 129 - .../common/include/F2837xD_Cla_defines.h | 201 - .../common/include/F2837xD_Cla_typedefs.h | 128 - .../common/include/F2837xD_Dma_defines.h | 212 - .../common/include/F2837xD_EPwm_defines.h | 342 - .../common/include/F2837xD_Emif_defines.h | 319 - .../common/include/F2837xD_Examples.h | 448 - .../common/include/F2837xD_GlobalPrototypes.h | 363 - .../common/include/F2837xD_Gpio_defines.h | 116 - .../common/include/F2837xD_I2c_defines.h | 184 - .../common/include/F2837xD_Ipc_defines.h | 70 - .../common/include/F2837xD_Ipc_drivers.h | 511 - .../common/include/F2837xD_Pie_defines.h | 74 - .../include/F2837xD_SWPrioritizedIsrLevels.h | 20681 ------------------- .../common/include/F2837xD_SysCtrl_defines.h | 63 - .../common/include/F2837xD_Systick_defines.h | 80 - .../common/include/F2837xD_Upp_defines.h | 86 - .../common/include/F2837xD_cputimervars.h | 138 - .../common/include/F2837xD_defaultisr.h | 216 - .../tms320f28379d/common/include/F2837xD_sci_io.h | 70 - .../common/include/F2837xD_sdfm_drivers.h | 530 - .../tms320f28379d/common/include/F2837xD_struct.h | 82 - .../tms320f28379d/common/include/F28x_Project.h | 58 - .../tms320f28379d/common/include/device.h | 199 - .../tms320f28379d/common/include/driverlib.h | 82 - .../tms320f28379d/common/include/stdint.h | 522 - .../libraries/tms320f28379d/common/include/usb.h | 561 - .../tms320f28379d/common/include/usb_hal.h | 82 - .../tms320f28379d/common/source/F2837xD_Adc.c | 286 - .../common/source/F2837xD_CodeStartBranch.asm | 111 - .../common/source/F2837xD_CpuTimers.c | 181 - .../tms320f28379d/common/source/F2837xD_DBGIER.asm | 60 - .../common/source/F2837xD_DefaultISR.c | 3138 --- .../tms320f28379d/common/source/F2837xD_Dma.c | 1100 - .../tms320f28379d/common/source/F2837xD_ECap.c | 147 - .../tms320f28379d/common/source/F2837xD_EPwm.c | 436 - .../tms320f28379d/common/source/F2837xD_EQep.c | 389 - .../tms320f28379d/common/source/F2837xD_Emif.c | 458 - .../tms320f28379d/common/source/F2837xD_Gpio.c | 506 - .../tms320f28379d/common/source/F2837xD_I2C.c | 301 - .../tms320f28379d/common/source/F2837xD_Ipc.c | 216 - .../common/source/F2837xD_Ipc_Driver.c | 1702 -- .../common/source/F2837xD_Ipc_Driver_Lite.c | 1302 -- .../common/source/F2837xD_Ipc_Driver_Util.c | 469 - .../tms320f28379d/common/source/F2837xD_Mcbsp.c | 584 - .../tms320f28379d/common/source/F2837xD_PieCtrl.c | 121 - .../tms320f28379d/common/source/F2837xD_PieVect.c | 320 - .../common/source/F2837xD_SWPrioritizedPieVect.c | 967 - .../tms320f28379d/common/source/F2837xD_Sci.c | 48 - .../tms320f28379d/common/source/F2837xD_Spi.c | 175 - .../tms320f28379d/common/source/F2837xD_SysCtrl.c | 1276 -- .../common/source/F2837xD_TempSensorConv.c | 153 - .../tms320f28379d/common/source/F2837xD_Upp.c | 153 - .../tms320f28379d/common/source/F2837xD_can.c | 131 - .../tms320f28379d/common/source/F2837xD_sci_io.c | 185 - .../common/source/F2837xD_sdfm_drivers.c | 554 - .../tms320f28379d/common/source/F2837xD_struct.c | 100 - .../common/source/F2837xD_usDelay.asm | 105 - .../libraries/tms320f28379d/common/source/device.c | 328 - .../libraries/tms320f28379d/common/source/usb.c | 3972 ---- .../tms320f28379d/common/source/usb_hal.c | 163 - .../headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd | 287 - .../headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd | 255 - .../headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd | 287 - .../headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd | 251 - .../tms320f28379d/headers/include/F2837xD_adc.h | 1067 - .../headers/include/F2837xD_analogsubsys.h | 199 - .../tms320f28379d/headers/include/F2837xD_can.h | 612 - .../tms320f28379d/headers/include/F2837xD_cla.h | 305 - .../tms320f28379d/headers/include/F2837xD_cmpss.h | 310 - .../headers/include/F2837xD_cputimer.h | 141 - .../tms320f28379d/headers/include/F2837xD_dac.h | 163 - .../tms320f28379d/headers/include/F2837xD_dcsm.h | 449 - .../tms320f28379d/headers/include/F2837xD_device.h | 345 - .../tms320f28379d/headers/include/F2837xD_dma.h | 214 - .../tms320f28379d/headers/include/F2837xD_ecap.h | 203 - .../tms320f28379d/headers/include/F2837xD_emif.h | 302 - .../tms320f28379d/headers/include/F2837xD_epwm.h | 1240 -- .../headers/include/F2837xD_epwm_xbar.h | 832 - .../tms320f28379d/headers/include/F2837xD_eqep.h | 267 - .../tms320f28379d/headers/include/F2837xD_flash.h | 376 - .../tms320f28379d/headers/include/F2837xD_gpio.h | 3882 ---- .../tms320f28379d/headers/include/F2837xD_i2c.h | 256 - .../headers/include/F2837xD_input_xbar.h | 112 - .../tms320f28379d/headers/include/F2837xD_ipc.h | 313 - .../tms320f28379d/headers/include/F2837xD_mcbsp.h | 323 - .../headers/include/F2837xD_memconfig.h | 1071 - .../headers/include/F2837xD_nmiintrupt.h | 175 - .../headers/include/F2837xD_output_xbar.h | 907 - .../headers/include/F2837xD_piectrl.h | 707 - .../headers/include/F2837xD_pievect.h | 306 - .../tms320f28379d/headers/include/F2837xD_sci.h | 266 - .../tms320f28379d/headers/include/F2837xD_sdfm.h | 534 - .../tms320f28379d/headers/include/F2837xD_spi.h | 201 - .../headers/include/F2837xD_sysctrl.h | 1964 -- .../tms320f28379d/headers/include/F2837xD_upp.h | 403 - .../tms320f28379d/headers/include/F2837xD_xbar.h | 303 - .../tms320f28379d/headers/include/F2837xD_xint.h | 143 - .../headers/source/F2837xD_GlobalVariableDefs.c | 876 - bsp/c28x/tms320f28379d/.ccsproject | 17 - bsp/c28x/tms320f28379d/.config | 684 - bsp/c28x/tms320f28379d/.cproject | 224 - bsp/c28x/tms320f28379d/.gitignore | 3 - bsp/c28x/tms320f28379d/.project | 869 - .../.settings/org.eclipse.cdt.codan.core.prefs | 3 - .../.settings/org.eclipse.cdt.debug.core.prefs | 2 - .../.settings/org.eclipse.core.resources.prefs | 91 - bsp/c28x/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd | 119 - bsp/c28x/tms320f28379d/2837x_RAM_lnk_cpu1.cmd | 83 - bsp/c28x/tms320f28379d/Kconfig | 30 - bsp/c28x/tms320f28379d/README.md | 107 - bsp/c28x/tms320f28379d/applications/startup.c | 28 - bsp/c28x/tms320f28379d/board/Kconfig | 1045 - bsp/c28x/tms320f28379d/board/board.c | 145 - bsp/c28x/tms320f28379d/board/board.h | 24 - bsp/c28x/tms320f28379d/figures/build.png | Bin 20564 -> 0 bytes bsp/c28x/tms320f28379d/figures/debug_as.png | Bin 146679 -> 0 bytes bsp/c28x/tms320f28379d/figures/import.png | Bin 88643 -> 0 bytes bsp/c28x/tms320f28379d/figures/import_dia.png | Bin 36380 -> 0 bytes bsp/c28x/tms320f28379d/figures/launch-28379d.png | Bin 477468 -> 0 bytes bsp/c28x/tms320f28379d/figures/launching.png | Bin 24009 -> 0 bytes bsp/c28x/tms320f28379d/rtconfig.h | 195 - bsp/c28x/tms320f28379d/rtconfig_project.h | 27 - .../targetConfigs/TMS320F28379D.ccxml | 22 - bsp/c28x/tms320f28379d/targetConfigs/readme.txt | 9 - .../c28x/libraries/HAL_Drivers/config/adc_config.h | 54 + .../c28x/libraries/HAL_Drivers/config/pwm_config.h | 69 + bsp/ti/c28x/libraries/HAL_Drivers/drv_adc.c | 229 + bsp/ti/c28x/libraries/HAL_Drivers/drv_adc.h | 30 + bsp/ti/c28x/libraries/HAL_Drivers/drv_config.h | 17 + bsp/ti/c28x/libraries/HAL_Drivers/drv_gpio.c | 439 + bsp/ti/c28x/libraries/HAL_Drivers/drv_gpio.h | 44 + bsp/ti/c28x/libraries/HAL_Drivers/drv_pwm.c | 587 + bsp/ti/c28x/libraries/HAL_Drivers/drv_pwm.h | 26 + bsp/ti/c28x/libraries/HAL_Drivers/drv_sci.c | 265 + bsp/ti/c28x/libraries/HAL_Drivers/drv_sci.h | 16 + .../common/include/F2837xD_Adc_defines.h | 87 + .../common/include/F2837xD_Can_defines.h | 129 + .../common/include/F2837xD_Cla_defines.h | 201 + .../common/include/F2837xD_Cla_typedefs.h | 128 + .../common/include/F2837xD_Dma_defines.h | 212 + .../common/include/F2837xD_EPwm_defines.h | 342 + .../common/include/F2837xD_Emif_defines.h | 319 + .../common/include/F2837xD_Examples.h | 448 + .../common/include/F2837xD_GlobalPrototypes.h | 363 + .../common/include/F2837xD_Gpio_defines.h | 116 + .../common/include/F2837xD_I2c_defines.h | 184 + .../common/include/F2837xD_Ipc_defines.h | 70 + .../common/include/F2837xD_Ipc_drivers.h | 511 + .../common/include/F2837xD_Pie_defines.h | 74 + .../include/F2837xD_SWPrioritizedIsrLevels.h | 20681 +++++++++++++++++++ .../common/include/F2837xD_SysCtrl_defines.h | 63 + .../common/include/F2837xD_Systick_defines.h | 80 + .../common/include/F2837xD_Upp_defines.h | 86 + .../common/include/F2837xD_cputimervars.h | 138 + .../common/include/F2837xD_defaultisr.h | 216 + .../tms320f28379d/common/include/F2837xD_sci_io.h | 70 + .../common/include/F2837xD_sdfm_drivers.h | 530 + .../tms320f28379d/common/include/F2837xD_struct.h | 82 + .../tms320f28379d/common/include/F28x_Project.h | 58 + .../tms320f28379d/common/include/device.h | 199 + .../tms320f28379d/common/include/driverlib.h | 82 + .../tms320f28379d/common/include/stdint.h | 522 + .../libraries/tms320f28379d/common/include/usb.h | 561 + .../tms320f28379d/common/include/usb_hal.h | 82 + .../tms320f28379d/common/source/F2837xD_Adc.c | 286 + .../common/source/F2837xD_CodeStartBranch.asm | 111 + .../common/source/F2837xD_CpuTimers.c | 181 + .../tms320f28379d/common/source/F2837xD_DBGIER.asm | 60 + .../common/source/F2837xD_DefaultISR.c | 3138 +++ .../tms320f28379d/common/source/F2837xD_Dma.c | 1100 + .../tms320f28379d/common/source/F2837xD_ECap.c | 147 + .../tms320f28379d/common/source/F2837xD_EPwm.c | 436 + .../tms320f28379d/common/source/F2837xD_EQep.c | 389 + .../tms320f28379d/common/source/F2837xD_Emif.c | 458 + .../tms320f28379d/common/source/F2837xD_Gpio.c | 506 + .../tms320f28379d/common/source/F2837xD_I2C.c | 301 + .../tms320f28379d/common/source/F2837xD_Ipc.c | 216 + .../common/source/F2837xD_Ipc_Driver.c | 1702 ++ .../common/source/F2837xD_Ipc_Driver_Lite.c | 1302 ++ .../common/source/F2837xD_Ipc_Driver_Util.c | 469 + .../tms320f28379d/common/source/F2837xD_Mcbsp.c | 584 + .../tms320f28379d/common/source/F2837xD_PieCtrl.c | 121 + .../tms320f28379d/common/source/F2837xD_PieVect.c | 320 + .../common/source/F2837xD_SWPrioritizedPieVect.c | 967 + .../tms320f28379d/common/source/F2837xD_Sci.c | 48 + .../tms320f28379d/common/source/F2837xD_Spi.c | 175 + .../tms320f28379d/common/source/F2837xD_SysCtrl.c | 1276 ++ .../common/source/F2837xD_TempSensorConv.c | 153 + .../tms320f28379d/common/source/F2837xD_Upp.c | 153 + .../tms320f28379d/common/source/F2837xD_can.c | 131 + .../tms320f28379d/common/source/F2837xD_sci_io.c | 185 + .../common/source/F2837xD_sdfm_drivers.c | 554 + .../tms320f28379d/common/source/F2837xD_struct.c | 100 + .../common/source/F2837xD_usDelay.asm | 105 + .../libraries/tms320f28379d/common/source/device.c | 328 + .../libraries/tms320f28379d/common/source/usb.c | 3972 ++++ .../tms320f28379d/common/source/usb_hal.c | 163 + .../headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd | 287 + .../headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd | 255 + .../headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd | 287 + .../headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd | 251 + .../tms320f28379d/headers/include/F2837xD_adc.h | 1067 + .../headers/include/F2837xD_analogsubsys.h | 199 + .../tms320f28379d/headers/include/F2837xD_can.h | 612 + .../tms320f28379d/headers/include/F2837xD_cla.h | 305 + .../tms320f28379d/headers/include/F2837xD_cmpss.h | 310 + .../headers/include/F2837xD_cputimer.h | 141 + .../tms320f28379d/headers/include/F2837xD_dac.h | 163 + .../tms320f28379d/headers/include/F2837xD_dcsm.h | 449 + .../tms320f28379d/headers/include/F2837xD_device.h | 345 + .../tms320f28379d/headers/include/F2837xD_dma.h | 214 + .../tms320f28379d/headers/include/F2837xD_ecap.h | 203 + .../tms320f28379d/headers/include/F2837xD_emif.h | 302 + .../tms320f28379d/headers/include/F2837xD_epwm.h | 1240 ++ .../headers/include/F2837xD_epwm_xbar.h | 832 + .../tms320f28379d/headers/include/F2837xD_eqep.h | 267 + .../tms320f28379d/headers/include/F2837xD_flash.h | 376 + .../tms320f28379d/headers/include/F2837xD_gpio.h | 3882 ++++ .../tms320f28379d/headers/include/F2837xD_i2c.h | 256 + .../headers/include/F2837xD_input_xbar.h | 112 + .../tms320f28379d/headers/include/F2837xD_ipc.h | 313 + .../tms320f28379d/headers/include/F2837xD_mcbsp.h | 323 + .../headers/include/F2837xD_memconfig.h | 1071 + .../headers/include/F2837xD_nmiintrupt.h | 175 + .../headers/include/F2837xD_output_xbar.h | 907 + .../headers/include/F2837xD_piectrl.h | 707 + .../headers/include/F2837xD_pievect.h | 306 + .../tms320f28379d/headers/include/F2837xD_sci.h | 266 + .../tms320f28379d/headers/include/F2837xD_sdfm.h | 534 + .../tms320f28379d/headers/include/F2837xD_spi.h | 201 + .../headers/include/F2837xD_sysctrl.h | 1964 ++ .../tms320f28379d/headers/include/F2837xD_upp.h | 403 + .../tms320f28379d/headers/include/F2837xD_xbar.h | 303 + .../tms320f28379d/headers/include/F2837xD_xint.h | 143 + .../headers/source/F2837xD_GlobalVariableDefs.c | 876 + bsp/ti/c28x/tms320f28379d/.ccsproject | 17 + bsp/ti/c28x/tms320f28379d/.config | 689 + bsp/ti/c28x/tms320f28379d/.cproject | 225 + bsp/ti/c28x/tms320f28379d/.gitignore | 3 + bsp/ti/c28x/tms320f28379d/.project | 849 + .../.settings/org.eclipse.cdt.codan.core.prefs | 3 + .../.settings/org.eclipse.cdt.debug.core.prefs | 2 + .../.settings/org.eclipse.core.resources.prefs | 91 + bsp/ti/c28x/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd | 119 + bsp/ti/c28x/tms320f28379d/2837x_RAM_lnk_cpu1.cmd | 83 + bsp/ti/c28x/tms320f28379d/Kconfig | 30 + bsp/ti/c28x/tms320f28379d/README.md | 107 + bsp/ti/c28x/tms320f28379d/applications/startup.c | 28 + bsp/ti/c28x/tms320f28379d/board/Kconfig | 1087 + bsp/ti/c28x/tms320f28379d/board/board.c | 145 + bsp/ti/c28x/tms320f28379d/board/board.h | 24 + bsp/ti/c28x/tms320f28379d/figures/build.png | Bin 0 -> 20564 bytes bsp/ti/c28x/tms320f28379d/figures/debug_as.png | Bin 0 -> 146679 bytes bsp/ti/c28x/tms320f28379d/figures/import.png | Bin 0 -> 88643 bytes bsp/ti/c28x/tms320f28379d/figures/import_dia.png | Bin 0 -> 36380 bytes .../c28x/tms320f28379d/figures/launch-28379d.png | Bin 0 -> 477468 bytes bsp/ti/c28x/tms320f28379d/figures/launching.png | Bin 0 -> 24009 bytes bsp/ti/c28x/tms320f28379d/rtconfig.h | 201 + bsp/ti/c28x/tms320f28379d/rtconfig_project.h | 27 + .../targetConfigs/TMS320F28379D.ccxml | 22 + bsp/ti/c28x/tms320f28379d/targetConfigs/readme.txt | 9 + 271 files changed, 73155 insertions(+), 72807 deletions(-) delete mode 100644 bsp/c28x/libraries/HAL_Drivers/config/pwm_config.h delete mode 100644 bsp/c28x/libraries/HAL_Drivers/drv_config.h delete mode 100644 bsp/c28x/libraries/HAL_Drivers/drv_gpio.c delete mode 100644 bsp/c28x/libraries/HAL_Drivers/drv_gpio.h delete mode 100644 bsp/c28x/libraries/HAL_Drivers/drv_pwm.c delete mode 100644 bsp/c28x/libraries/HAL_Drivers/drv_pwm.h delete mode 100644 bsp/c28x/libraries/HAL_Drivers/drv_sci.c delete mode 100644 bsp/c28x/libraries/HAL_Drivers/drv_sci.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Adc_defines.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Can_defines.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_defines.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_typedefs.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Dma_defines.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_EPwm_defines.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Emif_defines.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Examples.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_GlobalPrototypes.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Gpio_defines.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_I2c_defines.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_defines.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_drivers.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Pie_defines.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_SWPrioritizedIsrLevels.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_SysCtrl_defines.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Systick_defines.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Upp_defines.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_cputimervars.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_defaultisr.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_sci_io.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_sdfm_drivers.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_struct.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/F28x_Project.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/device.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/driverlib.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/stdint.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/usb.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/include/usb_hal.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Adc.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_CodeStartBranch.asm delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_CpuTimers.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_DBGIER.asm delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_DefaultISR.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Dma.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_ECap.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_EPwm.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_EQep.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Emif.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Gpio.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_I2C.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Lite.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Util.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Mcbsp.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_PieCtrl.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_PieVect.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_SWPrioritizedPieVect.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Sci.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Spi.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_SysCtrl.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_TempSensorConv.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Upp.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_can.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_sci_io.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_sdfm_drivers.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_struct.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_usDelay.asm delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/device.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/usb.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/common/source/usb_hal.c delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_adc.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_analogsubsys.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_can.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cla.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cmpss.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cputimer.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dac.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dcsm.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_device.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dma.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_ecap.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_emif.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm_xbar.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_eqep.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_flash.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_gpio.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_i2c.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_input_xbar.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_ipc.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_mcbsp.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_memconfig.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_nmiintrupt.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_output_xbar.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_piectrl.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_pievect.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sci.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sdfm.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_spi.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sysctrl.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_upp.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_xbar.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_xint.h delete mode 100644 bsp/c28x/libraries/tms320f28379d/headers/source/F2837xD_GlobalVariableDefs.c delete mode 100644 bsp/c28x/tms320f28379d/.ccsproject delete mode 100644 bsp/c28x/tms320f28379d/.config delete mode 100644 bsp/c28x/tms320f28379d/.cproject delete mode 100644 bsp/c28x/tms320f28379d/.gitignore delete mode 100644 bsp/c28x/tms320f28379d/.project delete mode 100644 bsp/c28x/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs delete mode 100644 bsp/c28x/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs delete mode 100644 bsp/c28x/tms320f28379d/.settings/org.eclipse.core.resources.prefs delete mode 100644 bsp/c28x/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd delete mode 100644 bsp/c28x/tms320f28379d/2837x_RAM_lnk_cpu1.cmd delete mode 100644 bsp/c28x/tms320f28379d/Kconfig delete mode 100644 bsp/c28x/tms320f28379d/README.md delete mode 100644 bsp/c28x/tms320f28379d/applications/startup.c delete mode 100644 bsp/c28x/tms320f28379d/board/Kconfig delete mode 100644 bsp/c28x/tms320f28379d/board/board.c delete mode 100644 bsp/c28x/tms320f28379d/board/board.h delete mode 100644 bsp/c28x/tms320f28379d/figures/build.png delete mode 100644 bsp/c28x/tms320f28379d/figures/debug_as.png delete mode 100644 bsp/c28x/tms320f28379d/figures/import.png delete mode 100644 bsp/c28x/tms320f28379d/figures/import_dia.png delete mode 100644 bsp/c28x/tms320f28379d/figures/launch-28379d.png delete mode 100644 bsp/c28x/tms320f28379d/figures/launching.png delete mode 100644 bsp/c28x/tms320f28379d/rtconfig.h delete mode 100644 bsp/c28x/tms320f28379d/rtconfig_project.h delete mode 100644 bsp/c28x/tms320f28379d/targetConfigs/TMS320F28379D.ccxml delete mode 100644 bsp/c28x/tms320f28379d/targetConfigs/readme.txt create mode 100644 bsp/ti/c28x/libraries/HAL_Drivers/config/adc_config.h create mode 100644 bsp/ti/c28x/libraries/HAL_Drivers/config/pwm_config.h create mode 100644 bsp/ti/c28x/libraries/HAL_Drivers/drv_adc.c create mode 100644 bsp/ti/c28x/libraries/HAL_Drivers/drv_adc.h create mode 100644 bsp/ti/c28x/libraries/HAL_Drivers/drv_config.h create mode 100644 bsp/ti/c28x/libraries/HAL_Drivers/drv_gpio.c create mode 100644 bsp/ti/c28x/libraries/HAL_Drivers/drv_gpio.h create mode 100644 bsp/ti/c28x/libraries/HAL_Drivers/drv_pwm.c create mode 100644 bsp/ti/c28x/libraries/HAL_Drivers/drv_pwm.h create mode 100644 bsp/ti/c28x/libraries/HAL_Drivers/drv_sci.c create mode 100644 bsp/ti/c28x/libraries/HAL_Drivers/drv_sci.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Adc_defines.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Can_defines.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_defines.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_typedefs.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Dma_defines.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_EPwm_defines.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Emif_defines.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Examples.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_GlobalPrototypes.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Gpio_defines.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_I2c_defines.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_defines.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_drivers.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Pie_defines.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_SWPrioritizedIsrLevels.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_SysCtrl_defines.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Systick_defines.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Upp_defines.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_cputimervars.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_defaultisr.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_sci_io.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_sdfm_drivers.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_struct.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/F28x_Project.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/device.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/driverlib.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/stdint.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/usb.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/include/usb_hal.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Adc.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_CodeStartBranch.asm create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_CpuTimers.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_DBGIER.asm create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_DefaultISR.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Dma.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_ECap.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_EPwm.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_EQep.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Emif.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Gpio.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_I2C.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Lite.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Util.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Mcbsp.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_PieCtrl.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_PieVect.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_SWPrioritizedPieVect.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Sci.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Spi.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_SysCtrl.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_TempSensorConv.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Upp.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_can.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_sci_io.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_sdfm_drivers.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_struct.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_usDelay.asm create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/device.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/usb.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/common/source/usb_hal.c create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_adc.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_analogsubsys.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_can.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_cla.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_cmpss.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_cputimer.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_dac.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_dcsm.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_device.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_dma.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_ecap.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_emif.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm_xbar.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_eqep.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_flash.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_gpio.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_i2c.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_input_xbar.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_ipc.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_mcbsp.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_memconfig.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_nmiintrupt.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_output_xbar.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_piectrl.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_pievect.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_sci.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_sdfm.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_spi.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_sysctrl.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_upp.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_xbar.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_xint.h create mode 100644 bsp/ti/c28x/libraries/tms320f28379d/headers/source/F2837xD_GlobalVariableDefs.c create mode 100644 bsp/ti/c28x/tms320f28379d/.ccsproject create mode 100644 bsp/ti/c28x/tms320f28379d/.config create mode 100644 bsp/ti/c28x/tms320f28379d/.cproject create mode 100644 bsp/ti/c28x/tms320f28379d/.gitignore create mode 100644 bsp/ti/c28x/tms320f28379d/.project create mode 100644 bsp/ti/c28x/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 bsp/ti/c28x/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs create mode 100644 bsp/ti/c28x/tms320f28379d/.settings/org.eclipse.core.resources.prefs create mode 100644 bsp/ti/c28x/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd create mode 100644 bsp/ti/c28x/tms320f28379d/2837x_RAM_lnk_cpu1.cmd create mode 100644 bsp/ti/c28x/tms320f28379d/Kconfig create mode 100644 bsp/ti/c28x/tms320f28379d/README.md create mode 100644 bsp/ti/c28x/tms320f28379d/applications/startup.c create mode 100644 bsp/ti/c28x/tms320f28379d/board/Kconfig create mode 100644 bsp/ti/c28x/tms320f28379d/board/board.c create mode 100644 bsp/ti/c28x/tms320f28379d/board/board.h create mode 100644 bsp/ti/c28x/tms320f28379d/figures/build.png create mode 100644 bsp/ti/c28x/tms320f28379d/figures/debug_as.png create mode 100644 bsp/ti/c28x/tms320f28379d/figures/import.png create mode 100644 bsp/ti/c28x/tms320f28379d/figures/import_dia.png create mode 100644 bsp/ti/c28x/tms320f28379d/figures/launch-28379d.png create mode 100644 bsp/ti/c28x/tms320f28379d/figures/launching.png create mode 100644 bsp/ti/c28x/tms320f28379d/rtconfig.h create mode 100644 bsp/ti/c28x/tms320f28379d/rtconfig_project.h create mode 100644 bsp/ti/c28x/tms320f28379d/targetConfigs/TMS320F28379D.ccxml create mode 100644 bsp/ti/c28x/tms320f28379d/targetConfigs/readme.txt (limited to 'bsp') diff --git a/bsp/c28x/libraries/HAL_Drivers/config/pwm_config.h b/bsp/c28x/libraries/HAL_Drivers/config/pwm_config.h deleted file mode 100644 index d490cb4d71..0000000000 --- a/bsp/c28x/libraries/HAL_Drivers/config/pwm_config.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022-09-21 yuqi created - */ - -#ifndef DRIVERS_CONFIG_PWM_CONFIG_H_ -#define DRIVERS_CONFIG_PWM_CONFIG_H_ -#include "F28x_Project.h" // Device Headerfile and Examples Include File -#include "F2837xD_epwm.h" -#include "rtthread.h" -#include "drv_config.h" - -#ifdef __cplusplus -extern "C" { -#endif -#ifdef BSP_USING_PWM1 - #ifndef PWM1_CONFIG - #define PWM1_CONFIG \ - { \ - .name = "pwm1", \ - .pwm_regs = &EPwm1Regs, \ - } - #endif -#endif -#ifdef BSP_USING_PWM2 - #ifndef PWM2_CONFIG - #define PWM2_CONFIG \ - { \ - .name = "pwm2", \ - .pwm_regs = &EPwm2Regs, \ - } - #endif -#endif -#ifdef BSP_USING_PWM3 - #ifndef PWM3_CONFIG - #define PWM3_CONFIG \ - { \ - .name = "pwm3", \ - .pwm_regs = &EPwm3Regs, \ - } - #endif -#endif -#ifdef BSP_USING_PWM4 - #ifndef PWM4_CONFIG - #define PWM4_CONFIG \ - { \ - .name = "pwm4", \ - .pwm_regs = &EPwm4Regs, \ - } - #endif -#endif - -#define TZ_OFF 2 -#define TZ_ON 1 -#ifdef __cplusplus -} -#endif - - -#define RT_SHADOW_MODE CC_SHADOW -#define RT_LOAD_TIME CC_CTR_ZERO -#define RT_CTRMODE TB_COUNT_UPDOWN -#endif /* DRIVERS_CONFIG_PWM_CONFIG_H_ */ - diff --git a/bsp/c28x/libraries/HAL_Drivers/drv_config.h b/bsp/c28x/libraries/HAL_Drivers/drv_config.h deleted file mode 100644 index 926bfc9ad9..0000000000 --- a/bsp/c28x/libraries/HAL_Drivers/drv_config.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022-09-24 qiyu first version - */ - -#ifndef DRIVERS_DRV_CONFIG_H_ -#define DRIVERS_DRV_CONFIG_H_ - -#include "config/pwm_config.h" - -#endif /* DRIVERS_DRV_CONFIG_H_ */ diff --git a/bsp/c28x/libraries/HAL_Drivers/drv_gpio.c b/bsp/c28x/libraries/HAL_Drivers/drv_gpio.c deleted file mode 100644 index 89d5931799..0000000000 --- a/bsp/c28x/libraries/HAL_Drivers/drv_gpio.c +++ /dev/null @@ -1,439 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022-08-28 qiyu first version - */ -#include -#include "drv_gpio.h" -#include "F2837xD_device.h" -#include "F28x_Project.h" // Device Headerfile and Examples Include File -#ifdef RT_USING_PIN - -// the gpio pin number for each port is 32, while it is 16 for ARM -#define PIN_NUM(port, no) (((((port) & 0xFu) << 5) | ((no) & 0x1F))) -#define PIN_PORT(pin) ((rt_uint16_t)(((pin) >> 5) & 0xFu)) -#define PIN_NO(pin) ((rt_uint16_t)((pin) & 0x1Fu)) - -#define PIN_c28x_PORT(pin) (volatile Uint32 *)&GpioDataRegs + (PIN_PORT(pin))*GPY_DATA_OFFSET -#define PIN_c28x_PIN(pin) ((rt_uint32_t)(1u << PIN_NO(pin))) - -#define PIN_c28x_PORT_MAX 6 /* gpioA to GPIOF in total*/ -#define PIN_IRQ_MAX 5 /* XINT1 to XINT5 in total */ - -static rt_err_t c28x_pin_attach_irq(struct rt_device *device, rt_int32_t pin, - rt_uint32_t mode, void (*hdr)(void *args), void *args); -static rt_err_t c28x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin); -static rt_err_t c28x_pin_irq_enable(struct rt_device *device, rt_base_t pin, - rt_uint32_t enabled); - -static rt_base_t c28x_pin_get(const char *name) -{ - int hw_pin_num = 0; - int i, name_len; - - name_len = rt_strlen(name); - - if ((name_len < 3) || (name_len >= 7)) - { - return -RT_EINVAL; - } - /* - * PX.y - */ - if ((name[0] != 'P') || (name[2] != '.')) - { - return -RT_EINVAL; - } - - for (i = 3; i < name_len; i++) - { - hw_pin_num *= 10; - hw_pin_num += name[i] - '0'; - } - return hw_pin_num; -} - -static void c28x_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) -{ - volatile Uint32 *gpioDataReg; - Uint32 pinMask; - if (PIN_PORT(pin) < PIN_c28x_PORT_MAX) - { - gpioDataReg = PIN_c28x_PORT(pin); - pinMask = 1UL << (PIN_NO(pin)); - if (value == 0) - { - gpioDataReg[GPYCLEAR] = pinMask; - } - else - { - gpioDataReg[GPYSET] = pinMask; - } - } -} - -static int c28x_pin_read(rt_device_t dev, rt_base_t pin) -{ - volatile Uint32 *gpioDataReg; - int value = PIN_LOW; - - if (PIN_PORT(pin) < PIN_c28x_PORT_MAX) - { - gpioDataReg = PIN_c28x_PORT(pin); - value = (gpioDataReg[GPYDAT] >> PIN_NO(pin)) & 0x1; - } - - return value; -} - -static void c28x_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) -{ - volatile Uint32 *gpioBaseAddr; - volatile Uint32 *dir, *pud, *odr; - if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX) - { - return; - } - rt_uint32_t pinMask; - pinMask = 1UL << PIN_NO(pin); - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (PIN_PORT(pin))*GPY_CTRL_OFFSET; - - dir = gpioBaseAddr + GPYDIR; - pud = gpioBaseAddr + GPYPUD; - odr = gpioBaseAddr + GPYODR; - - EALLOW; - if (mode == PIN_MODE_OUTPUT) - { - *dir |= pinMask; - } - else if (mode == PIN_MODE_INPUT) - { - *dir &= ~pinMask; - } - else if (mode == PIN_MODE_INPUT_PULLUP) - { - *dir &= ~pinMask; - *pud &= ~pinMask; - } - else if (mode == PIN_MODE_INPUT_PULLDOWN) - { - /* input setting: pull down. */ - *dir &= ~pinMask; - *pud |= pinMask; - } - else if (mode == PIN_MODE_OUTPUT_OD) - { - /* output setting: od. */ - *dir |= pinMask; - *odr |= pinMask; - } - EDIS; -} - -const static struct rt_pin_ops _c28x_pin_ops = -{ - c28x_pin_mode, - c28x_pin_write, - c28x_pin_read, - c28x_pin_attach_irq, - c28x_pin_dettach_irq, - c28x_pin_irq_enable, - c28x_pin_get, -}; - -int rt_hw_pin_init(void) -{ - return rt_device_pin_register("pin", &_c28x_pin_ops, RT_NULL); -} - -static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = -{ - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, -}; - -static rt_int16_t pin_irq_xint_tab[] = -{ - BSP_XINT1_PIN, - BSP_XINT2_PIN, - BSP_XINT3_PIN, - BSP_XINT4_PIN, - BSP_XINT5_PIN -}; -rt_inline rt_int32_t get_irq_index(rt_uint32_t pin) -{ - int i; - for(i = 0 ; i < PIN_IRQ_MAX ; i++) - { - if(pin_irq_xint_tab[i] == pin) - { - return i; - } - } - return -1; -} - -#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) - -static rt_err_t c28x_pin_attach_irq(struct rt_device *device, rt_int32_t pin, - rt_uint32_t mode, void (*hdr)(void *args), void *args) -{ - rt_base_t level; - rt_int32_t irqindex = -1; - - if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX) - { - return -RT_ENOSYS; - } - irqindex = get_irq_index(pin); - level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[irqindex].pin == pin && - pin_irq_hdr_tab[irqindex].hdr == hdr && - pin_irq_hdr_tab[irqindex].mode == mode && - pin_irq_hdr_tab[irqindex].args == args) - { - rt_hw_interrupt_enable(level); - return RT_EOK; - } - if (pin_irq_hdr_tab[irqindex].pin != -1) - { - rt_hw_interrupt_enable(level); - return -RT_EBUSY; - } - pin_irq_hdr_tab[irqindex].pin = pin; - pin_irq_hdr_tab[irqindex].hdr = hdr; - pin_irq_hdr_tab[irqindex].mode = mode; - pin_irq_hdr_tab[irqindex].args = args; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} - -static rt_err_t c28x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) -{ - rt_base_t level; - rt_int32_t irqindex = -1; - rt_uint16_t i; - if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX) - { - return -RT_ENOSYS; - } - - for(i = 0 ; i < PIN_IRQ_MAX ; i++) - { - if(pin_irq_hdr_tab[i].pin == pin) - { - irqindex = i; - break; - } - } - if (irqindex == -1) - { - return -RT_ENOSYS; - } - level = rt_hw_interrupt_disable(); - pin_irq_hdr_tab[irqindex].pin = -1; - pin_irq_hdr_tab[irqindex].hdr = RT_NULL; - pin_irq_hdr_tab[irqindex].mode = 0; - pin_irq_hdr_tab[irqindex].args = RT_NULL; - rt_hw_interrupt_enable(level); - - return RT_EOK; -} - -static rt_err_t c28x_pin_irq_enable(struct rt_device *device, rt_base_t pin, - rt_uint32_t enabled) -{ - rt_base_t level; - rt_int32_t irqindex = -1; - rt_uint16_t channel; - rt_uint16_t edge_mode,pin_mode; - - if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX) - { - return -RT_ENOSYS; - } - - irqindex = get_irq_index(pin); - - /* irqindex+1 = channel*/ - if (irqindex < 0 || irqindex >= PIN_IRQ_MAX) - { - return -RT_ENOSYS; - } - - if (enabled == PIN_IRQ_ENABLE) - { - level = rt_hw_interrupt_disable(); - - if (pin_irq_hdr_tab[irqindex].pin == -1) - { - rt_hw_interrupt_enable(level); - return -RT_ENOSYS; - } - - /* - * 1. set the edge mode of interrupt triggering - * 2. set the GPIO mode - * 3. enable XINT channel and set the input source - */ - channel = irqindex+1; - switch (pin_irq_hdr_tab[irqindex].mode) - { - case PIN_IRQ_MODE_RISING: - edge_mode = 1; - pin_mode = PIN_MODE_INPUT_PULLDOWN; - break; - case PIN_IRQ_MODE_FALLING: - edge_mode = 0; - pin_mode = PIN_MODE_INPUT_PULLUP; - break; - case PIN_IRQ_MODE_RISING_FALLING: - edge_mode = 3; - pin_mode = PIN_MODE_INPUT; - break; - } - if(channel == 1) - { - XintRegs.XINT1CR.bit.ENABLE = 1; // Enable XINT1 - EALLOW; - InputXbarRegs.INPUT4SELECT = pin; //Set XINT1 source to GPIO-pin - EDIS; - XintRegs.XINT1CR.bit.POLARITY = edge_mode; // Falling edge interrupt - } - else if(channel == 2) - { - XintRegs.XINT2CR.bit.ENABLE = 1; // Enable XINT2 - EALLOW; - InputXbarRegs.INPUT5SELECT = pin; //Set XINT1 source to GPIO-pin - EDIS; - XintRegs.XINT2CR.bit.POLARITY = edge_mode; // Falling edge interrupt - } - else if(channel == 3) - { - XintRegs.XINT3CR.bit.ENABLE = 1; // Enable XINT2 - EALLOW; - InputXbarRegs.INPUT6SELECT = pin; //Set XINT1 source to GPIO-pin - EDIS; - XintRegs.XINT3CR.bit.POLARITY = edge_mode; // Falling edge interrupt - } - else if(channel == 4) - { - XintRegs.XINT4CR.bit.ENABLE = 1; // Enable XINT2 - EALLOW; - InputXbarRegs.INPUT13SELECT = pin; //Set XINT1 source to GPIO-pin - EDIS; - XintRegs.XINT4CR.bit.POLARITY = edge_mode; // Falling edge interrupt - } - else if(channel == 5) - { - XintRegs.XINT5CR.bit.ENABLE = 1; // Enable XINT2 - EALLOW; - InputXbarRegs.INPUT14SELECT = pin; //Set XINT1 source to GPIO-pin - EDIS; - XintRegs.XINT5CR.bit.POLARITY = edge_mode; // Falling edge interrupt - } - - c28x_pin_mode(device, pin, pin_mode); - rt_hw_interrupt_enable(level); - } - else if (enabled == PIN_IRQ_DISABLE) - { - level = rt_hw_interrupt_disable(); - channel = irqindex+1; - /* - * TODO modify this simpler - */ - if(channel == 1) - { - XintRegs.XINT1CR.bit.ENABLE = 0; // Disable XINT1 - } - else if(channel == 2) - { - XintRegs.XINT2CR.bit.ENABLE = 0; // Disable XINT2 - } - else if(channel == 3) - { - XintRegs.XINT3CR.bit.ENABLE = 0; // Disable XINT2 - } - else if(channel == 4) - { - XintRegs.XINT4CR.bit.ENABLE = 0; // Disable XINT2 - } - else if(channel == 5) - { - XintRegs.XINT5CR.bit.ENABLE = 0; // Disable XINT2 - } - rt_hw_interrupt_enable(level); - } - else - { - return -RT_ENOSYS; - } - - return RT_EOK; -} - -void GPIO_XINT_Callback(rt_int16_t XINT_number); - -interrupt void XINT1_Handler(void) -{ - rt_interrupt_enter(); - PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - GPIO_XINT_Callback(1); - rt_interrupt_leave(); -} - -interrupt void XINT2_Handler(void) -{ - rt_interrupt_enter(); - GPIO_XINT_Callback(2); - PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - rt_interrupt_leave(); -} - -interrupt void XINT3_Handler(void) -{ - rt_interrupt_enter(); - GPIO_XINT_Callback(3); - PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - rt_interrupt_leave(); -} - -interrupt void XINT4_Handler(void) -{ - rt_interrupt_enter(); - GPIO_XINT_Callback(4); - PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - rt_interrupt_leave(); -} - -interrupt void XINT5_Handler(void) -{ - rt_interrupt_enter(); - GPIO_XINT_Callback(5); - PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - rt_interrupt_leave(); -} - -void GPIO_XINT_Callback(rt_int16_t XINT_number) -{ - rt_int32_t irqindex = XINT_number - 1; - if(pin_irq_hdr_tab[irqindex].hdr) - { - pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args); - } -} - -#endif /* RT_USING_PIN */ - - - diff --git a/bsp/c28x/libraries/HAL_Drivers/drv_gpio.h b/bsp/c28x/libraries/HAL_Drivers/drv_gpio.h deleted file mode 100644 index ceb1cc1cfa..0000000000 --- a/bsp/c28x/libraries/HAL_Drivers/drv_gpio.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022-08-28 qiyu first version - */ - -#ifndef DRIVERS_DRV_GPIO_H_ -#define DRIVERS_DRV_GPIO_H_ - -#include -#include "rtdevice.h" - -#ifdef __cplusplus -extern "C" { -#endif - -int rt_hw_pin_init(void); - -#ifndef BSP_XINT1_PIN -#define BSP_XINT1_PIN -1 -#endif -#ifndef BSP_XINT2_PIN -#define BSP_XINT2_PIN -1 -#endif -#ifndef BSP_XINT3_PIN -#define BSP_XINT3_PIN -1 -#endif -#ifndef BSP_XINT4_PIN -#define BSP_XINT4_PIN -1 -#endif -#ifndef BSP_XINT5_PIN -#define BSP_XINT5_PIN -1 -#endif - -#ifdef __cplusplus -} -#endif - - -#endif /* DRIVERS_DRV_GPIO_H_ */ diff --git a/bsp/c28x/libraries/HAL_Drivers/drv_pwm.c b/bsp/c28x/libraries/HAL_Drivers/drv_pwm.c deleted file mode 100644 index 336e7f6e57..0000000000 --- a/bsp/c28x/libraries/HAL_Drivers/drv_pwm.c +++ /dev/null @@ -1,587 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022-09-24 qiyu first version - */ - -#include "rtdbg.h" -#include "drv_pwm.h" -#include "F2837xD_device.h" -#include "F28x_Project.h" /* Device Headerfile and Examples Include File */ -#include "drv_config.h" -#include "F2837xD_epwm.h" -/* - * for now, cpu rate is a fixed value, waiting to be modified to an auto-ajustable variable. -*/ -#ifdef BSP_USING_PWM -rt_err_t rt_device_pwm_register(struct rt_device_pwm *device, const char *name, const struct rt_pwm_ops *ops, const void *user_data); - -#define CPU_FREQUENCY 200e6 -/* - * TODO unknown issue, according to the configuration, - * this division should be 2, - * while 2 is inconsistent with the measured result - */ -#define PWM_DIVISION 2 -#define CHANNEL_A 1 -#define CHANNEL_B 2 -#define UPDOWN 1 - -enum -{ -#ifdef BSP_USING_PWM1 - PWM1_INDEX, -#endif -#ifdef BSP_USING_PWM2 - PWM2_INDEX, -#endif -#ifdef BSP_USING_PWM3 - PWM3_INDEX, -#endif -#ifdef BSP_USING_PWM4 - PWM4_INDEX, -#endif -#ifdef BSP_USING_PWM5 - PWM5_INDEX, -#endif -#ifdef BSP_USING_PWM6 - PWM6_INDEX, -#endif -#ifdef BSP_USING_PWM7 - PWM7_INDEX, -#endif -#ifdef BSP_USING_PWM8 - PWM8_INDEX, -#endif -#ifdef BSP_USING_PWM9 - PWM9_INDEX, -#endif -#ifdef BSP_USING_PWM10 - PWM10_INDEX, -#endif -#ifdef BSP_USING_PWM11 - PWM11_INDEX, -#endif -#ifdef BSP_USING_PWM12 - PWM12_INDEX, -#endif -}; - -static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg); - -static struct rt_pwm_ops rt_pwm_ops = -{ - drv_pwm_control -}; - -static struct c28x_pwm c28x_pwm_obj[] = -{ -#ifdef BSP_USING_PWM1 - PWM1_CONFIG, -#endif - -#ifdef BSP_USING_PWM2 - PWM2_CONFIG, -#endif - -#ifdef BSP_USING_PWM3 - PWM3_CONFIG, -#endif - -#ifdef BSP_USING_PWM4 - PWM4_CONFIG, -#endif - -#ifdef BSP_USING_PWM5 - PWM5_CONFIG, -#endif - -#ifdef BSP_USING_PWM6 - PWM6_CONFIG, -#endif - -#ifdef BSP_USING_PWM7 - PWM7_CONFIG, -#endif - -#ifdef BSP_USING_PWM8 - PWM8_CONFIG, -#endif - -}; - -static rt_err_t drv_pwm_set(volatile struct EPWM_REGS *epwm,struct rt_pwm_configuration *configuration) -{ - if(epwm == RT_NULL) - { - return -RT_ERROR; - } - /* - * TODO Unknown problem - * the clock division configuration of PWM module is 1 - * however, the experiment result shows the division is 2 - */ - - /* Set the configuration of PWM according to the parameter*/ - rt_uint32_t prd = configuration->period/(1e9/(CPU_FREQUENCY/PWM_DIVISION))/2; - rt_uint32_t comp = prd*configuration->pulse/configuration->period; - rt_uint32_t dead_time = configuration->dead_time/(1e9/(CPU_FREQUENCY/PWM_DIVISION)); - rt_uint32_t phase = configuration->phase; - - epwm->TBPRD = prd; /* Set timer period*/ - epwm->TBCTR = 0x0000; /* Clear counter*/ - epwm->CMPCTL.bit.SHDWAMODE = RT_SHADOW_MODE; /* Load registers every ZERO*/ - epwm->CMPCTL.bit.SHDWBMODE = RT_SHADOW_MODE; - /* Setup compare */ - if(configuration->channel == CHANNEL_A) - { - epwm->CMPA.bit.CMPA = comp; - }else - { - epwm->CMPB.bit.CMPB = comp; - } - - /* Set actions */ - epwm->AQCTLA.bit.CAU = AQ_CLEAR; /* Set PWMA on Zero*/ - epwm->AQCTLA.bit.CAD = AQ_SET; - epwm->AQCTLB.bit.CBU = AQ_CLEAR; /* Set PWMB on Zero*/ - epwm->AQCTLB.bit.CBD = AQ_SET; - - /* Active Low PWMs - Setup Deadband */ - /* TODO finish complementary setting */ - epwm->DBCTL.bit.POLSEL = DB_ACTV_HIC; - epwm->DBRED.bit.DBRED = dead_time; - epwm->DBFED.bit.DBFED = dead_time; - epwm->DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; - /* - if(configuration->complementary) - { - } - else - { - epwm->DBRED.bit.DBRED = 0; - epwm->DBFED.bit.DBFED = 0; - epwm->DBCTL.bit.POLSEL = DB_ACTV_HI; - epwm->DBCTL.bit.OUT_MODE = DB_DISABLE; - } - */ - - epwm->DBCTL.bit.IN_MODE = DBA_ALL; - /* if disable dead time, set dead_time to 0 */ - -#ifdef BSP_PWM1_CTR_MODE_UPDOWN - if(phase<180) - { - epwm->TBPHS.bit.TBPHS = prd * phase/180; - epwm->TBCTL.bit.PHSDIR = 0; /* count up */ - }else - { - epwm->TBPHS.bit.TBPHS = prd-prd * (phase-180)/180; - epwm->TBCTL.bit.PHSDIR = 1; /* count up*/ - } -#endif - if(epwm == &EPwm1Regs) - { - epwm->TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */ - epwm->TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; - }else - { - epwm->TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */ - epwm->TBCTL.bit.SYNCOSEL = TB_SYNC_IN; - } - return RT_EOK; -} - -static rt_err_t drv_pwm_get(struct EPWM_REGS *epwm,struct rt_pwm_configuration *configuration) -{ - /* Retrieve the pwm configuration */ - if(epwm == RT_NULL) - { - return -RT_ERROR; - } - rt_uint32_t prd = epwm->TBPRD; - rt_uint32_t comp = epwm->CMPA.bit.CMPA; - if(UPDOWN) - { - /* if in updown mode, period in configuration has to be doubled */ - configuration->period = prd*(1e9/(CPU_FREQUENCY/PWM_DIVISION))*2; - } - else - { - configuration->period = prd*(1e9/(CPU_FREQUENCY/PWM_DIVISION)); - } - configuration->pulse = comp*configuration->period/prd; - return RT_EOK; -} - -static rt_err_t drv_pwm_set_period(struct EPWM_REGS *epwm, rt_uint32_t period) -{ - if(epwm == RT_NULL) - { - return -RT_ERROR; - } - rt_uint32_t prd = period/(1e9/(CPU_FREQUENCY/PWM_DIVISION))/2; - epwm->TBPRD = prd; /* Set timer period */ - return RT_EOK; -} - -static rt_err_t drv_pwm_set_pulse(struct EPWM_REGS *epwm, int channel, rt_uint32_t pulse) -{ - if(epwm == RT_NULL) - { - return -RT_ERROR; - } - rt_uint32_t comp = pulse/(1e9/(CPU_FREQUENCY/PWM_DIVISION)); - if(channel == CHANNEL_A) - { - epwm->CMPA.bit.CMPA = comp; /* set comparator value */ - }else - { - epwm->CMPB.bit.CMPB = comp; /* set comparator value */ - } - return RT_EOK; -} - -static rt_err_t drv_pwm_set_dead_time(struct EPWM_REGS *epwm, rt_uint32_t dead_time) -{ - if(epwm == RT_NULL) - { - return -RT_ERROR; - } - rt_uint32_t _dead_time = dead_time/(1e9/(CPU_FREQUENCY/PWM_DIVISION)); - epwm->DBRED.bit.DBRED = _dead_time; /* rising dead time */ - epwm->DBFED.bit.DBFED = _dead_time; /* falling dead time */ - return RT_EOK; -} - -static rt_err_t drv_pwm_set_phase(struct EPWM_REGS *epwm, rt_uint32_t phase) -{ - if(epwm == RT_NULL) - { - return -RT_ERROR; - } - if(phase<180) - { - epwm->TBPHS.bit.TBPHS = epwm->TBPRD * phase/180; - epwm->TBCTL.bit.PHSDIR = 0;/* count up */ - }else - { - epwm->TBPHS.bit.TBPHS = epwm->TBPRD-epwm->TBPRD * (phase-180)/180; - epwm->TBCTL.bit.PHSDIR = 1;/* count up */ - } - - return RT_EOK; -} - -static rt_err_t drv_pwm_enable_irq(volatile struct EPWM_REGS *epwm,rt_bool_t enable) -{ - if(epwm == RT_NULL) - { - return -RT_ERROR; - } - if(enable == RT_TRUE) - { - /* Interrupt setting */ - epwm->ETSEL.bit.INTEN = 1; /* Enable INT */ - }else{ - epwm->ETSEL.bit.INTEN = 0; /* Enable INT */ - } - return RT_EOK; -} - -static rt_err_t drv_pwm_enable(volatile struct EPWM_REGS *epwm,rt_bool_t enable) -{ - /* - * TODO - * Still not sure about how to stop PWM in C2000 - */ - if(epwm == RT_NULL) - { - return -RT_ERROR; - } - if(enable == RT_TRUE) - { - /* clear trip zone flag */ - EALLOW; - epwm->TZCLR.bit.OST = 1; - EDIS; - } - else - { - /* set trip zone flag */ - EALLOW; - epwm->TZFRC.bit.OST = 1; - EDIS; - } - return RT_EOK; -} - -static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) -{ - struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; - struct c28x_pwm *pwm = (struct c28x_pwm *)device->parent.user_data; - - switch (cmd) - { - case PWM_CMD_ENABLE: - return drv_pwm_enable((struct EPWM_REGS *)(pwm->pwm_regs), RT_TRUE); - case PWM_CMD_DISABLE: - return drv_pwm_enable((struct EPWM_REGS *)(pwm->pwm_regs), RT_FALSE); - case PWM_CMD_SET: - return drv_pwm_set((struct EPWM_REGS *)(pwm->pwm_regs), configuration); - case PWM_CMD_GET: - return drv_pwm_get((struct EPWM_REGS *)(pwm->pwm_regs), configuration); - case PWM_CMD_SET_PERIOD: - return drv_pwm_set_period((struct EPWM_REGS *)(pwm->pwm_regs), configuration->period); - case PWM_CMD_SET_PULSE: - return drv_pwm_set_pulse((struct EPWM_REGS *)(pwm->pwm_regs), configuration->channel,configuration->pulse); - case PWM_CMD_SET_DEAD_TIME: - return drv_pwm_set_dead_time((struct EPWM_REGS *)(pwm->pwm_regs), configuration->dead_time); - case PWM_CMD_SET_PHASE: - return drv_pwm_set_phase((struct EPWM_REGS *)(pwm->pwm_regs), configuration->phase); - case PWM_CMD_ENABLE_IRQ: - return drv_pwm_enable_irq((struct EPWM_REGS *)(pwm->pwm_regs), RT_TRUE); - case PWM_CMD_DISABLE_IRQ: - return drv_pwm_enable_irq((struct EPWM_REGS *)(pwm->pwm_regs), RT_FALSE); - default: - return RT_EINVAL; - } -} - -static void pwm_isr(struct rt_device_pwm *rt_pwm) -{ - struct c28x_pwm *pwm; - pwm = (struct c28x_pwm *)rt_pwm->parent.user_data; - PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - pwm->pwm_regs->ETCLR.bit.INT = 1; -} - -#define EPWM_ISR_DEFINE(i) void EPWM##i##_Isr(){\ - rt_interrupt_enter(); \ - pwm_isr(&(c28x_pwm_obj[PWM##i##_INDEX].pwm_device)); \ - rt_interrupt_leave(); \ -} - -#ifdef BSP_PWM1_IT_ENABLE -EPWM_ISR_DEFINE(1) -void EPWM1_Isr(); -#endif -#ifdef BSP_PWM2_IT_ENABLE -EPWM_ISR_DEFINE(2) -void EPWM2_Isr(); -#endif -#ifdef BSP_PWM3_IT_ENABLE -EPWM_ISR_DEFINE(3) -void EPWM3_Isr(); -#endif -#ifdef BSP_PWM4_IT_ENABLE -EPWM_ISR_DEFINE(4) -void EPWM4_Isr(); -#endif - - -static int c28x_hw_pwm_init(struct c28x_pwm *device) -{ - IER |= M_INT3; - rt_err_t result = 0; - EALLOW; -#ifdef BSP_USING_PWM1 - GpioCtrlRegs.GPAPUD.all |= 5<<(1-1)*4; /* Disable pull-up(EPWM1A) */ - GpioCtrlRegs.GPAMUX1.all|= 5<<(1-1)*4; /* Configure as EPWM1A */ - EPwm1Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */ - EPwm1Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */ - EPwm1Regs.TBCTL.bit.CTRMODE = BSP_PWM1_CTRMODE; - EPwm1Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM1_HSPCLKDIV; /* Clock ratio to SYSCLKOUT*/ - EPwm1Regs.TBCTL.bit.CLKDIV = BSP_PWM1_CLKDIV; - EPwm1Regs.CMPCTL.bit.LOADAMODE = BSP_PWM1_LOADAMODE; - EPwm1Regs.CMPCTL.bit.LOADBMODE = BSP_PWM1_LOADAMODE; - #ifdef BSP_PWM1_IT_ENABLE - EPwm1Regs.ETSEL.bit.INTEN = 1; /* Enable INT */ - EPwm1Regs.ETSEL.bit.INTSEL = BSP_PWM1_INTSEL; - EPwm1Regs.ETPS.bit.INTPRD = BSP_PWM1_INTPRD; - /* Assigning ISR to PIE */ - PieVectTable.EPWM1_INT = &EPWM1_Isr; - /* ENABLE Interrupt */ - #else - EPwm1Regs.ETSEL.bit.INTEN = 0; /* Disable INT */ - #endif - #ifdef BSP_PWM1_ADC_TRIGGER - EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group - EPwm1Regs.ETSEL.bit.SOCASEL = BSP_PWM1_SOCASEL; // Select SOC from zero - EPwm1Regs.ETPS.bit.SOCAPRD = BSP_PWM1_SOCAPRD; // Generate pulse on 1st event - #else - EPwm1Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group - #endif - #ifdef BSP_PWM1_MASTER - EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */ - EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; - #else - EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */ - EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; - #endif -#endif -#ifdef BSP_USING_PWM2 - GpioCtrlRegs.GPAPUD.all |= 5<<(2-1)*4; /* Disable pull-up on (EPWM2A) */ - GpioCtrlRegs.GPAMUX1.all|= 5<<(2-1)*4; /* Configure as EPWM2A */ - EPwm2Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */ - EPwm2Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */ - EPwm2Regs.TBCTL.bit.CTRMODE = BSP_PWM2_CTRMODE; - EPwm2Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM2_HSPCLKDIV; /* Clock ratio to SYSCLKOUT*/ - EPwm2Regs.TBCTL.bit.CLKDIV = BSP_PWM2_CLKDIV; - EPwm2Regs.CMPCTL.bit.LOADAMODE = BSP_PWM2_LOADAMODE; - EPwm2Regs.CMPCTL.bit.LOADBMODE = BSP_PWM2_LOADAMODE; - #ifdef BSP_PWM2_IT_ENABLE - EPwm2Regs.ETSEL.bit.INTEN = 1; /* Enable INT */ - EPwm2Regs.ETSEL.bit.INTSEL = BSP_PWM2_INTSEL; - EPwm2Regs.ETPS.bit.INTPRD = BSP_PWM2_INTPRD; - /* Assigning ISR to PIE */ - PieVectTable.EPWM2_INT = &EPWM2_Isr; - /* ENABLE Interrupt */ - #else - EPwm2Regs.ETSEL.bit.INTEN = 0; /* Disable INT */ - #endif - #ifdef BSP_PWM2_ADC_TRIGGER - EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group - EPwm2Regs.ETSEL.bit.SOCASEL = BSP_PWM2_SOCASEL; // Select SOC from zero - EPwm2Regs.ETPS.bit.SOCAPRD = BSP_PWM2_SOCAPRD; // Generate pulse on 1st event - #else - EPwm2Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group - #endif - #ifdef BSP_PWM2_MASTER - EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */ - EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; - #else - EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */ - EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; - #endif -#endif -#ifdef BSP_USING_PWM3 - GpioCtrlRegs.GPAPUD.all |= 5<<(3-1)*4; /* Disable pull-up on (EPWM3A) */ - GpioCtrlRegs.GPAMUX1.all|= 5<<(3-1)*4; /* Configure as EPWM3A */ - EPwm3Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */ - EPwm3Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */ - EPwm3Regs.TBCTL.bit.CTRMODE = BSP_PWM3_CTRMODE; - EPwm3Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM3_HSPCLKDIV; /* Clock ratio to SYSCLKOUT*/ - EPwm3Regs.TBCTL.bit.CLKDIV = BSP_PWM3_CLKDIV; - EPwm3Regs.CMPCTL.bit.LOADAMODE = BSP_PWM3_LOADAMODE; - EPwm3Regs.CMPCTL.bit.LOADBMODE = BSP_PWM3_LOADAMODE; - #ifdef BSP_PWM3_IT_ENABLE - EPwm3Regs.ETSEL.bit.INTEN = 1; /* Enable INT */ - EPwm3Regs.ETSEL.bit.INTSEL = BSP_PWM3_INTSEL; - EPwm3Regs.ETPS.bit.INTPRD = BSP_PWM3_INTPRD; - /* Assigning ISR to PIE */ - PieVectTable.EPWM3_INT = &EPWM3_Isr; - /* ENABLE Interrupt */ - #else - EPwm3Regs.ETSEL.bit.INTEN = 0; /* Disable INT */ - #endif - #ifdef BSP_PWM3_ADC_TRIGGER - EPwm3Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group - EPwm3Regs.ETSEL.bit.SOCASEL = BSP_PWM3_SOCASEL; // Select SOC from zero - EPwm3Regs.ETPS.bit.SOCAPRD = BSP_PWM3_SOCAPRD; // Generate pulse on 1st event - #else - EPwm3Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group - #endif - #ifdef BSP_PWM3_MASTER - EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */ - EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; - #else - EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */ - EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; - #endif -#endif -#ifdef BSP_USING_PWM4 - GpioCtrlRegs.GPAPUD.all |= 5<<(4-1)*4; /* Disable pull-up on (EPWM4A) */ - GpioCtrlRegs.GPAMUX1.all|= 5<<(4-1)*4; /* Configure as EPWM4A */ - EPwm4Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */ - EPwm4Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */ - EPwm4Regs.TBCTL.bit.CTRMODE = BSP_PWM4_CTRMODE; - EPwm4Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM4_HSPCLKDIV; /* Clock ratio to SYSCLKOUT*/ - EPwm4Regs.TBCTL.bit.CLKDIV = BSP_PWM4_CLKDIV; - EPwm4Regs.CMPCTL.bit.LOADAMODE = BSP_PWM4_LOADAMODE; - EPwm4Regs.CMPCTL.bit.LOADBMODE = BSP_PWM4_LOADAMODE; - #ifdef BSP_PWM4_IT_ENABLE - EPwm4Regs.ETSEL.bit.INTEN = 1; /* Enable INT */ - EPwm4Regs.ETSEL.bit.INTSEL = BSP_PWM4_INTSEL; - EPwm4Regs.ETPS.bit.INTPRD = BSP_PWM4_INTPRD; - /* Assigning ISR to PIE */ - PieVectTable.EPWM4_INT = &EPWM4_Isr; - /* ENABLE Interrupt */ - #else - EPwm4Regs.ETSEL.bit.INTEN = 0; /* Disable INT */ - #endif - #ifdef BSP_PWM4_ADC_TRIGGER - EPwm4Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group - EPwm4Regs.ETSEL.bit.SOCASEL = BSP_PWM4_SOCASEL; // Select SOC from zero - EPwm4Regs.ETPS.bit.SOCAPRD = BSP_PWM4_SOCAPRD; // Generate pulse on 1st event - #else - EPwm4Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group - #endif - #ifdef BSP_PWM4_MASTER - EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */ - EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; - #else - EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */ - EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; - #endif -#endif - EDIS; - - return result; -} - -int c28x_pwm_init(void) -{ - int i = 0; - int result = RT_EOK; - - for (i = 0; i < sizeof(c28x_pwm_obj) / sizeof(c28x_pwm_obj[0]); i++) - { - /* pwm init */ - if (c28x_hw_pwm_init(&c28x_pwm_obj[i]) != RT_EOK) - { - LOG_E("%s init failed", c28x_pwm_obj[i].name); - result = -RT_ERROR; - return result; - } - else - { - LOG_D("%s init success", c28x_pwm_obj[i].name); - - /* register pwm device */ - if (rt_device_pwm_register(&c28x_pwm_obj[i].pwm_device, c28x_pwm_obj[i].name, &rt_pwm_ops, &c28x_pwm_obj[i]) == RT_EOK) - { - LOG_D("%s register success", c28x_pwm_obj[i].name); - } - else - { - LOG_E("%s register failed", c28x_pwm_obj[i].name); - result = -RT_ERROR; - } - } - } - struct rt_pwm_configuration config_tmp1 = - { - .channel = CHANNEL_A, - .period = BSP_PWM1_INIT_PERIOD, - .pulse = BSP_PWM1_INIT_PULSE, - .dead_time = BSP_PWM1_DB, - .phase = 0, - .complementary = RT_TRUE - }; - drv_pwm_set(c28x_pwm_obj[0].pwm_regs,&config_tmp1); -// config_tmp1.phase = BSP_PWM2_PHASE; -// drv_pwm_set(c28x_pwm_obj[1].pwm_regs,&config_tmp1); -// config_tmp1.phase = BSP_PWM3_PHASE; -// drv_pwm_set(c28x_pwm_obj[2].pwm_regs,&config_tmp1); -// config_tmp1.phase = BSP_PWM4_PHASE; -// drv_pwm_set(c28x_pwm_obj[3].pwm_regs,&config_tmp1); - return result; - -} -INIT_DEVICE_EXPORT(c28x_pwm_init); -#endif /* BSP_USING_PWM */ diff --git a/bsp/c28x/libraries/HAL_Drivers/drv_pwm.h b/bsp/c28x/libraries/HAL_Drivers/drv_pwm.h deleted file mode 100644 index d3ef2ccddd..0000000000 --- a/bsp/c28x/libraries/HAL_Drivers/drv_pwm.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022-09-24 qiyu first version - */ - -#ifndef DRIVERS_DRV_PWM_H_ -#define DRIVERS_DRV_PWM_H_ -#include -#include "rtdevice.h" - -#ifdef BSP_USING_PWM -struct c28x_pwm -{ - struct rt_device_pwm pwm_device; - volatile struct EPWM_REGS *pwm_regs; - const char *name; -}; - -int c28x_pwm_init(void); -#endif /* BSP_USING_PWM */ -#endif /* DRIVERS_DRV_PWM_H_ */ diff --git a/bsp/c28x/libraries/HAL_Drivers/drv_sci.c b/bsp/c28x/libraries/HAL_Drivers/drv_sci.c deleted file mode 100644 index f1ba3f26d3..0000000000 --- a/bsp/c28x/libraries/HAL_Drivers/drv_sci.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-02-02 xuzhuoyi first version - */ - -#include "rtdevice.h" -#include "board.h" -#include "drv_sci.h" -#include "F2837xD_device.h" -#include "F2837xD_sci.h" - -//typedef long off_t; -#include "F2837xD_sci_io.h" - -#ifdef RT_USING_SERIAL - -#define LOG_TAG "drv.sci" - -/* c28x uart driver class */ -struct c28x_uart -{ - const char *name; - volatile struct SCI_REGS *sci_regs; - struct rt_serial_device serial; -}; - -static struct c28x_uart uart_obj[3] = {0}; - -static rt_err_t c28x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - struct c28x_uart *uart; - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - uart = (struct c28x_uart *)serial->parent.user_data; - RT_ASSERT(uart != RT_NULL); - - EALLOW; - - // default config - - // 1 stop bit, No loopback - // No parity,8 char bits, - // async mode, idle-line protocol - uart->sci_regs->SCICCR.all = 0x0007; - - // enable TX, RX, internal SCICLK, - // Disable RX ERR, SLEEP, TXWAKE - uart->sci_regs->SCICTL1.all = 0x0003; - - uart->sci_regs->SCICTL2.bit.TXINTENA = 1; - uart->sci_regs->SCICTL2.bit.RXBKINTENA = 1; - - uart->sci_regs->SCIHBAUD.all = 0x0000; // 115200 baud @LSPCLK = 22.5MHz (90 MHz SYSCLK). - uart->sci_regs->SCILBAUD.all = 53; - - uart->sci_regs->SCICTL1.all = 0x0023; // Relinquish SCI from Reset - - switch (cfg->data_bits) - { - case DATA_BITS_5: - uart->sci_regs->SCICCR.bit.SCICHAR = 4; - break; - case DATA_BITS_6: - uart->sci_regs->SCICCR.bit.SCICHAR = 5; - break; - case DATA_BITS_7: - uart->sci_regs->SCICCR.bit.SCICHAR = 6; - break; - case DATA_BITS_8: - uart->sci_regs->SCICCR.bit.SCICHAR = 7; - break; - default: - uart->sci_regs->SCICCR.bit.SCICHAR = 7; - break; - } - switch (cfg->stop_bits) - { - case STOP_BITS_1: - uart->sci_regs->SCICCR.bit.STOPBITS = 0; - break; - case STOP_BITS_2: - uart->sci_regs->SCICCR.bit.STOPBITS = 1; - break; - default: - uart->sci_regs->SCICCR.bit.STOPBITS = 0; - break; - } - switch (cfg->parity) - { - case PARITY_NONE: - uart->sci_regs->SCICCR.bit.PARITYENA = 0; - break; - case PARITY_ODD: - uart->sci_regs->SCICCR.bit.PARITYENA = 1; - uart->sci_regs->SCICCR.bit.PARITY = 0; - break; - case PARITY_EVEN: - uart->sci_regs->SCICCR.bit.PARITYENA = 1; - uart->sci_regs->SCICCR.bit.PARITY = 1; - break; - default: - uart->sci_regs->SCICCR.bit.PARITYENA = 0; - break; - } - - EDIS; - - return RT_EOK; -} - -static rt_err_t c28x_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct c28x_uart *uart; - uart = (struct c28x_uart *)serial->parent.user_data; - - EALLOW; - - switch (cmd) - { - /* disable interrupt */ - case RT_DEVICE_CTRL_CLR_INT: - /* disable interrupt */ - uart->sci_regs->SCICTL2.bit.TXINTENA = 0; - uart->sci_regs->SCICTL2.bit.RXBKINTENA = 0; - break; - /* enable interrupt */ - case RT_DEVICE_CTRL_SET_INT: - /* enable interrupt */ - uart->sci_regs->SCICTL2.bit.TXINTENA = 1; - uart->sci_regs->SCICTL2.bit.RXBKINTENA = 1; - break; - } - return RT_EOK; -} - -static int c28x_putc(struct rt_serial_device *serial, char c) -{ - SCI_write(0, &c, 1); - return 1; -} - -static int c28x_getc(struct rt_serial_device *serial) -{ - char ch; - if(SCI_read(0, &ch, 1)) - return ch; - else - return -1; -} - -/** - * Uart common interrupt process. This need add to uart ISR. - * - * @param serial serial device - */ -static void uart_isr(struct rt_serial_device *serial) { - struct c28x_uart *uart = (struct c28x_uart *) serial->parent.user_data; - - RT_ASSERT(uart != RT_NULL); - - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); - SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; // Clear Interrupt flag - PieCtrlRegs.PIEACK.all |= 0x100; // Issue PIE ack -} - -static const struct rt_uart_ops c28x_uart_ops = -{ - .configure = c28x_configure, - .control = c28x_control, - .putc = c28x_putc, - .getc = c28x_getc, -}; - -// -// sciaRxFifoIsr - SCIA Receive FIFO ISR -// -interrupt void sciaRxFifoIsr(void) -{ - ALLOW_ISR_PREEMPT(); - - /* enter interrupt */ - rt_interrupt_enter(); - - uart_isr(&uart_obj[0].serial); - - /* leave interrupt */ - rt_interrupt_leave(); -} - -int rt_hw_sci_init(void) -{ - EALLOW; - - GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; - GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; - GpioCtrlRegs.GPBGMUX1.bit.GPIO42 = 3; - GpioCtrlRegs.GPBGMUX1.bit.GPIO43 = 3; - - GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; - GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; - GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 0; - GpioCtrlRegs.GPAGMUX2.bit.GPIO19 = 0; - - GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 2; - GpioCtrlRegs.GPEMUX1.bit.GPIO139 = 2; - GpioCtrlRegs.GPBGMUX2.bit.GPIO56 = 1; - GpioCtrlRegs.GPEGMUX1.bit.GPIO139 = 1; - - CpuSysRegs.PCLKCR7.bit.SCI_A = 1; - CpuSysRegs.PCLKCR7.bit.SCI_B = 1; - CpuSysRegs.PCLKCR7.bit.SCI_C = 1; - - PieVectTable.SCIA_RX_INT = &sciaRxFifoIsr; - - EDIS; - - // - // Enable interrupts required for this example - // - PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block - PieCtrlRegs.PIEIER9.bit.INTx1 = 1; // PIE Group 9, INT1 - IER |= 0x100; // Enable CPU INT - - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - rt_err_t result = 0; - - uart_obj[0].serial.ops = &c28x_uart_ops; - uart_obj[0].serial.config = config; - uart_obj[0].name = "scia"; - uart_obj[0].sci_regs = &SciaRegs; - - uart_obj[1].serial.ops = &c28x_uart_ops; - uart_obj[1].serial.config = config; - uart_obj[1].name = "scib"; - uart_obj[1].sci_regs = &ScibRegs; - - uart_obj[2].serial.ops = &c28x_uart_ops; - uart_obj[2].serial.config = config; - uart_obj[2].name = "scic"; - uart_obj[2].sci_regs = &ScicRegs; - - /* register UART device */ - result = rt_hw_serial_register(&uart_obj[0].serial, uart_obj[0].name, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - &uart_obj[0]); - - /* register UART device */ - result = rt_hw_serial_register(&uart_obj[1].serial, uart_obj[1].name, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - &uart_obj[1]); - - /* register UART device */ - result = rt_hw_serial_register(&uart_obj[2].serial, uart_obj[2].name, - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - &uart_obj[2]); - - return result; -} - -#endif /* RT_USING_SERIAL */ diff --git a/bsp/c28x/libraries/HAL_Drivers/drv_sci.h b/bsp/c28x/libraries/HAL_Drivers/drv_sci.h deleted file mode 100644 index 60fb12bd9b..0000000000 --- a/bsp/c28x/libraries/HAL_Drivers/drv_sci.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-02-02 xuzhuoyi first version - */ - -#ifndef __DRV_SCI_H__ -#define __DRV_SCI_H__ - -int rt_hw_sci_init(void); - -#endif /* __DRV_SCI_H__ */ diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Adc_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Adc_defines.h deleted file mode 100644 index 78ff34a237..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Adc_defines.h +++ /dev/null @@ -1,87 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Adc_defines.h -// -// TITLE: #defines used in ADC examples -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_ADC_DEFINES_H -#define F2837xD_ADC_DEFINES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -//definitions for specifying an ADC -// -#define ADC_ADCA 0 -#define ADC_ADCB 1 -#define ADC_ADCC 2 -#define ADC_ADCD 3 - -// -//definitions for selecting ADC resolution -// -#ifndef _DUAL_HEADERS -#define ADC_RESOLUTION_12BIT 0 -#define ADC_RESOLUTION_16BIT 1 -#else -#define ADC_BITRESOLUTION_12BIT 0 -#define ADC_BITRESOLUTION_16BIT 1 -#endif -// -//definitions for selecting ADC signal mode -//(single-ended mode is only a valid mode for 12-bit resolution) -// -#define ADC_SIGNALMODE_SINGLE 0 -#define ADC_SIGNALMODE_DIFFERENTIAL 1 - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F2837xD_ADC_DEFINES_H - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Can_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Can_defines.h deleted file mode 100644 index a784ef475d..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Can_defines.h +++ /dev/null @@ -1,129 +0,0 @@ -//############################################################################# -// -// FILE: F2837xD_Can_defines.h -// -// TITLE: Common defines used in CAN Test Cases -// -//############################################################################# -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -#ifndef F2837xD_CAN_DEFINES_H -#define F2837xD_CAN_DEFINES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -// Reset Values -// -#define CAN_RESET_VALUE_ZERO 0x00000000 -#define CAN_CTL_RESET_VALUE 0x00001401 -#define CAN_ES_RESET_VALUE 0x00000007 -#define CAN_BTR_RESET_VALUE 0x00002301 -#define CAN_REL_RESET_VALUE 0xA3170504 -#define CAN_RAM_INIT_RESET_VALUE 0x00000005 -#define CAN_IF_CMD_RESET_VALUE 0x00000001 -#define CAN_IF_MASK_RESET_VALUE 0xFFFFFFFF - -// -// Register value when Peripheral Clock is Disabled -// -#define CAN_MODULE_CLK_DISABLE_VALUE 0x00000000 - -// -// Bit field definition of CAN_CTL register. -// -#define CAN_CTL_INIT 0x00000001 // Initialization -#define CAN_CTL_IE0 0x00000002 // Interrupt Enable 0 -#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable -#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable -#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission -#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable -#define CAN_CTL_TEST 0x00000080 // Test Mode Enable -#define CAN_CTL_IDS 0x00000100 // Interruption Debug Support Enable -#define CAN_CTL_ABO 0x00000200 // Auto-Bus On Enable -#define CAN_CTL_PMD_S 10 -#define CAN_CTL_PMD_M 0x00003C00 // Parity/SECDED Enable -#define CAN_CTL_SWR 0x00008000 // Software Reset Enable -#define CAN_CTL_INITDBG 0x00010000 // Debug Mode Status -#define CAN_CTL_IE1 0x00020000 // Interrupt Enable 1 -#define CAN_CTL_PDR 0x01000000 // Power Down Mode Request -#define CAN_CTL_WUBA 0x02000000 // Wake Up on Bus Activity - -// -// Bit field definition of CAN_IF1_CMD register. -// -#define CAN_IF1_CMD_MESSNUM_S 0 -#define CAN_IF1_CMD_MESSNUM_M 0x000000FF // Message Number -#define CAN_IF1_CMD_BUSY 0x00008000 // Busy Flag -#define CAN_IF1_CMD_DATAB 0x00010000 // Access Data B -#define CAN_IF1_CMD_DATAA 0x00020000 // Access Data A -#define CAN_IF1_CMD_TXRQSTNDAT 0x00040000 // Transmission Request Bit -#define CAN_IF1_CMD_CLRINTPND 0x00080000 // Clear Interrupt Pending Bit -#define CAN_IF1_CMD_CONTROL 0x00100000 // Access Control Bits -#define CAN_IF1_CMD_ARB 0x00200000 // Access Arbitration Bits -#define CAN_IF1_CMD_MASK 0x00400000 // Access Mask Bits -#define CAN_IF1_CMD_WR_RD 0x00800000 // Write and Read - -// -// Bit field definition of CAN_IF2_CMD register. -// -#define CAN_IF2_CMD_MESSNUM_S 0 -#define CAN_IF2_CMD_MESSNUM_M 0x000000FF // Message Number -#define CAN_IF2_CMD_BUSY 0x00008000 // Busy Flag -#define CAN_IF2_CMD_DATAB 0x00010000 // Access Data B -#define CAN_IF2_CMD_DATAA 0x00020000 // Access Data A -#define CAN_IF2_CMD_TXRQSTNDAT 0x00040000 // Transmission Request Bit -#define CAN_IF2_CMD_CLRINTPND 0x00080000 // Clear Interrupt Pending Bit -#define CAN_IF2_CMD_CONTROL 0x00100000 // Access Control Bits -#define CAN_IF2_CMD_ARB 0x00200000 // Access Arbitration Bits -#define CAN_IF2_CMD_MASK 0x00400000 // Access Mask Bits -#define CAN_IF2_CMD_WR_RD 0x00800000 // Write and Read - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F2837xD_CAN_DEFINES_H - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_defines.h deleted file mode 100644 index 2df82d7929..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_defines.h +++ /dev/null @@ -1,201 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Cla_defines.h -// -// TITLE: #defines used in CLA examples -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_CLA_DEFINES_H -#define F2837xD_CLA_DEFINES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -// MCTL Register -// -#define CLA_FORCE_RESET 0x1 -#define CLA_IACK_ENABLE 0x1 -#define CLA_IACK_DISABLE 0x0 - -// -// MMEMCFG Register -// -#define CLA_CLA_SPACE 0x1 -#define CLA_CPU_SPACE 0x0 - -// -// MIER Interrupt Enable Register -// -#define CLA_INT_ENABLE 0x1 -#define CLA_INT_DISABLE 0x0 - -// -// Peripheral Interrupt Source Select define for DMAnCLASourceSelect Register -// -#define CLA_TRIG_NOPERPH 0 -#define CLA_TRIG_ADCAINT1 1 -#define CLA_TRIG_ADCAINT2 2 -#define CLA_TRIG_ADCAINT3 3 -#define CLA_TRIG_ADCAINT4 4 -#define CLA_TRIG_ADCAEVT 5 -#define CLA_TRIG_ADCBINT1 6 -#define CLA_TRIG_ADCBINT2 7 -#define CLA_TRIG_ADCBINT3 8 -#define CLA_TRIG_ADCBINT4 9 -#define CLA_TRIG_ADCBEVT 10 -#define CLA_TRIG_ADCCINT1 11 -#define CLA_TRIG_ADCCINT2 12 -#define CLA_TRIG_ADCCINT3 13 -#define CLA_TRIG_ADCCINT4 14 -#define CLA_TRIG_ADCCEVT 15 -#define CLA_TRIG_ADCDINT1 16 -#define CLA_TRIG_ADCDINT2 17 -#define CLA_TRIG_ADCDINT3 18 -#define CLA_TRIG_ADCDINT4 19 -#define CLA_TRIG_ADCDEVT 20 - -#define CLA_TRIG_XINT1 29 -#define CLA_TRIG_XINT2 30 -#define CLA_TRIG_XINT3 31 -#define CLA_TRIG_XINT4 32 -#define CLA_TRIG_XINT5 33 - -#define CLA_TRIG_EPWM1INT 36 -#define CLA_TRIG_EPWM2INT 37 -#define CLA_TRIG_EPWM3INT 38 -#define CLA_TRIG_EPWM4INT 39 -#define CLA_TRIG_EPWM5INT 40 -#define CLA_TRIG_EPWM6INT 41 -#define CLA_TRIG_EPWM7INT 42 -#define CLA_TRIG_EPWM8INT 43 -#define CLA_TRIG_EPWM9INT 44 -#define CLA_TRIG_EPWM10INT 45 -#define CLA_TRIG_EPWM11INT 46 -#define CLA_TRIG_EPWM12INT 47 - -#define CLA_TRIG_TINT0 68 -#define CLA_TRIG_TINT1 69 -#define CLA_TRIG_TINT2 70 - -#define CLA_TRIG_MXEVTA 71 -#define CLA_TRIG_MREVTA 72 -#define CLA_TRIG_MXEVTB 73 -#define CLA_TRIG_MREVTB 74 - -#define CLA_TRIG_ECAP1INT 75 -#define CLA_TRIG_ECAP2INT 76 -#define CLA_TRIG_ECAP3INT 77 -#define CLA_TRIG_ECAP4INT 78 -#define CLA_TRIG_ECAP5INT 79 -#define CLA_TRIG_ECAP6INT 80 - -#define CLA_TRIG_EQEP1INT 83 -#define CLA_TRIG_EQEP2INT 84 -#define CLA_TRIG_EQEP3INT 85 - -#define CLA_TRIG_HRCAP1INT 87 -#define CLA_TRIG_HRCAP2INT 88 - -#define CLA_TRIG_SD1INT 95 -#define CLA_TRIG_SD2INT 96 - -#define CLA_TRIG_UPP1_INT 107 - -#define CLA_TRIG_SPITXINTA 109 -#define CLA_TRIG_SPIRXINTA 110 -#define CLA_TRIG_SPITXINTB 111 -#define CLA_TRIG_SPIRXINTB 112 -#define CLA_TRIG_SPITXINTC 113 -#define CLA_TRIG_SPIRXINTC 114 - -#define Cla1ForceTask1andWait()asm(" IACK #0x0001"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT1 == 1); - -#define Cla1ForceTask2andWait()asm(" IACK #0x0002"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT2 == 1); - -#define Cla1ForceTask3andWait()asm(" IACK #0x0004"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT3 == 1); - -#define Cla1ForceTask4andWait()asm(" IACK #0x0008"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT4 == 1); - -#define Cla1ForceTask5andWait()asm(" IACK #0x0010"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT5 == 1); - -#define Cla1ForceTask6andWait()asm(" IACK #0x0020"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT6 == 1); - -#define Cla1ForceTask7andWait()asm(" IACK #0x0040"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT7 == 1); - -#define Cla1ForceTask8andWait()asm(" IACK #0x0080"); \ - asm(" RPT #3 || NOP"); \ - while(Cla1Regs.MIRUN.bit.INT8 == 1); - -#define Cla1ForceTask1() asm(" IACK #0x0001") -#define Cla1ForceTask2() asm(" IACK #0x0002") -#define Cla1ForceTask3() asm(" IACK #0x0004") -#define Cla1ForceTask4() asm(" IACK #0x0008") -#define Cla1ForceTask5() asm(" IACK #0x0010") -#define Cla1ForceTask6() asm(" IACK #0x0020") -#define Cla1ForceTask7() asm(" IACK #0x0040") -#define Cla1ForceTask8() asm(" IACK #0x0080") - -#ifdef __cplusplus -} -#endif - -#endif // - end of F2837xD_CLA_DEFINES_H - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_typedefs.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_typedefs.h deleted file mode 100644 index 5a4650cbaa..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_typedefs.h +++ /dev/null @@ -1,128 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Cla_typedefs.h -// -// TITLE: Variable type definitions -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_CLA_TYPEDEFS_H_ -#define F2837xD_CLA_TYPEDEFS_H_ - -// -// Macros to manipulate pre-processor to generate a header file name -// at compile time that is based on the test name and can be used as -// an argument to #include -// -#define XSTRINGIZE(s) STRINGIZE(s) -#define STRINGIZE(s) #s -#define XCONCAT(x,y) CONCAT(x,y) -#define CONCAT(x,y) x##y - -// -// Suppress warnings casting CLA pointers -// -#pragma diag_suppress 70,770,232 - -#ifdef __TMS320C28XX_CLA__ -// -// For Portability, User Is Recommended To Use Following Data Type Size -// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: -// -// CLA does not support 64-bit types -// This definition is only to allow inclusion of the standard header files -// which do use 64-bit types -// - -#if (!defined(F28_DATA_TYPES) && !defined(DSP28_DATA_TYPES)) -#define F28_DATA_TYPES -#define DSP28_DATA_TYPES -typedef short int16; -typedef long int32; -typedef unsigned char Uint8; -typedef unsigned short Uint16; -typedef unsigned long Uint32; -typedef float float32; -typedef long double float64; -typedef struct { Uint32 low32; Uint32 high32; } Uint64; -typedef struct { int32 low32; int32 high32; } int64; -#else -#error F2837xD_Cla_Typedefs.h must be included before F2837xD_Device.h or any other header \ -file that redefines data types using the guard macros F28_DATA_TYPES or DSP28_DATA_TYPES -#endif //(!defined(F28_DATA_TYPES) && !defined(DSP28_DATA_TYPES)) - -#ifndef _TI_STD_TYPES -#define _TI_STD_TYPES -// -//These types are also defined in DSP/BIOS 5.x's and the -//SYS/BIOS 6.x's files. We need to protect their -//definition with the #ifndef/#define guard to avoid the duplicate -//definition warning. -// -//SYS/BIOS requires that the file be included before -//any other .h files. -// -#endif - -struct MSTF_SHADOW_BITS { // bits description - Uint16 LVF:1; // 0 Latched Overflow Flag - Uint16 LUF:1; // 1 Latched Underflow Flag - Uint16 NF:1; // 2 Negative Float Flag - Uint16 ZF:1; // 3 Zero Float Flag - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 TF:1; // 6 Test Flag - Uint16 rsvd2:2; // 8:7 Reserved - Uint16 RNDF32:1; // 9 Rounding Mode - Uint16 rsvd3:1; // 10 Reserved - Uint16 MEALLOW:1; // 11 MEALLOW Status - Uint16 RPCL:4; // 15:12 Return PC: Low Portion - Uint16 RPCH:8; // 23:16 Return PC: High Portion - Uint16 rsvd4:8; // 31:24 Reserved -}; -extern __cregister volatile unsigned int MSTF; - -#endif //__TMS320C28XX_CLA__ - -#ifndef __TMS320C28XX__ -#define __cregister -#endif //__TMS320C28xx__ - -#endif //F2837xD_CLA_TYPEDEFS_H_ - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Dma_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Dma_defines.h deleted file mode 100644 index ef6a245b93..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Dma_defines.h +++ /dev/null @@ -1,212 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Dma_defines.h -// -// TITLE: #defines used in DMA examples -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_DMA_DEFINES_H -#define F2837xD_DMA_DEFINES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -// PERINTSEL bits -// -#define DMA_ADCAINT1 1 -#define DMA_ADCAINT2 2 -#define DMA_ADCAINT3 3 -#define DMA_ADCAINT4 4 -#define DMA_ADCAEVT 5 -#define DMA_ADCBINT1 6 -#define DMA_ADCBINT2 7 -#define DMA_ADCBINT3 8 -#define DMA_ADCBINT4 9 -#define DMA_ADCBEVT 10 -#define DMA_ADCCINT1 11 -#define DMA_ADCCINT2 12 -#define DMA_ADCCINT3 13 -#define DMA_ADCCINT4 14 -#define DMA_ADCCEVT 15 -#define DMA_ADCDINT1 16 -#define DMA_ADCDINT2 17 -#define DMA_ADCDINT3 18 -#define DMA_ADCDINT4 19 -#define DMA_ADCDEVT 20 - -#define DMA_XINT1 29 -#define DMA_XINT2 30 -#define DMA_XINT3 31 -#define DMA_XINT4 32 -#define DMA_XINT5 33 - -#define DMA_EPWM1A 36 -#define DMA_EPWM1B 37 -#define DMA_EPWM2A 38 -#define DMA_EPWM2B 39 -#define DMA_EPWM3A 40 -#define DMA_EPWM3B 41 -#define DMA_EPWM4A 42 -#define DMA_EPWM4B 43 -#define DMA_EPWM5A 44 -#define DMA_EPWM5B 45 -#define DMA_EPWM6A 46 -#define DMA_EPWM6B 47 -#define DMA_EPWM7A 48 -#define DMA_EPWM7B 49 -#define DMA_EPWM8A 50 -#define DMA_EPWM8B 51 -#define DMA_EPWM9A 52 -#define DMA_EPWM9B 53 -#define DMA_EPWM10A 54 -#define DMA_EPWM10B 55 -#define DMA_EPWM11A 56 -#define DMA_EPWM11B 57 -#define DMA_EPWM12A 58 -#define DMA_EPWM12B 59 -#define DMA_EPWM13A 60 -#define DMA_EPWM13B 61 -#define DMA_EPWM14A 62 -#define DMA_EPWM14B 63 -#define DMA_EPWM15A 64 -#define DMA_EPWM15B 65 -#define DMA_EPWM16A 66 -#define DMA_EPWM16B 67 - -#define DMA_TINT0 68 -#define DMA_TINT1 69 -#define DMA_TINT2 70 - -#define DMA_MXEVTA 71 -#define DMA_MREVTA 72 -#define DMA_MXEVTB 73 -#define DMA_MREVTB 74 - -#define DMA_SD1FLT1 95 -#define DMA_SD1FLT2 96 -#define DMA_SD1FLT3 97 -#define DMA_SD1FLT4 98 - -#define DMA_SD2FLT1 99 -#define DMA_SD2FLT2 100 -#define DMA_SD2FLT3 101 -#define DMA_SD2FLT4 102 - -#define DMA_SPIATX 109 -#define DMA_SPIARX 110 -#define DMA_SPIBTX 111 -#define DMA_SPIBRX 112 -#define DMA_SPICTX 113 -#define DMA_SPICRX 114 - -#define DMA_USBRX1 131 -#define DMA_USBTX1 132 -#define DMA_USBRX2 133 -#define DMA_USBTX2 134 -#define DMA_USBRX3 135 -#define DMA_USBTX3 136 - -// -// OVERINTE bit -// -#define OVRFLOW_DISABLE 0x0 -#define OVEFLOW_ENABLE 0x1 - -// -// PERINTE bit -// -#define PERINT_DISABLE 0x0 -#define PERINT_ENABLE 0x1 - -// -// CHINTMODE bits -// -#define CHINT_BEGIN 0x0 -#define CHINT_END 0x1 - -// -// ONESHOT bits -// -#define ONESHOT_DISABLE 0x0 -#define ONESHOT_ENABLE 0x1 - -// -// CONTINOUS bit -// -#define CONT_DISABLE 0x0 -#define CONT_ENABLE 0x1 - -// -// SYNCE bit -// -#define SYNC_DISABLE 0x0 -#define SYNC_ENABLE 0x1 - -// -// SYNCSEL bit -// -#define SYNC_SRC 0x0 -#define SYNC_DST 0x1 - -// -// DATASIZE bit -// -#define SIXTEEN_BIT 0x0 -#define THIRTYTWO_BIT 0x1 - -// -// CHINTE bit -// -#define CHINT_DISABLE 0x0 -#define CHINT_ENABLE 0x1 - -#ifdef __cplusplus -} -#endif - -#endif // - end of F2837xD_DMA_DEFINES_H - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_EPwm_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_EPwm_defines.h deleted file mode 100644 index a45ae46f62..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_EPwm_defines.h +++ /dev/null @@ -1,342 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_EPwm_defines.h -// -// TITLE: #defines used in EPwm examples -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_EPWM_DEFINES_H -#define F2837xD_EPWM_DEFINES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -// TBCTL (Time-Base Control) -// - -// -// CTRMODE bits -// -#define TB_COUNT_UP 0x0 -#define TB_COUNT_DOWN 0x1 -#define TB_COUNT_UPDOWN 0x2 -#define TB_FREEZE 0x3 - -// -// PHSEN bit -// -#define TB_DISABLE 0x0 -#define TB_ENABLE 0x1 - -// -// PRDLD bit -// -#define TB_SHADOW 0x0 -#define TB_IMMEDIATE 0x1 - -// -// SYNCOSEL bits -// -#define TB_SYNC_IN 0x0 -#define TB_CTR_ZERO 0x1 -#define TB_CTR_CMPB 0x2 -#define TB_SYNC_DISABLE 0x3 - -// -// HSPCLKDIV and CLKDIV bits -// -#define TB_DIV1 0x0 -#define TB_DIV2 0x1 -#define TB_DIV4 0x2 - -// -// PHSDIR bit -// -#define TB_DOWN 0x0 -#define TB_UP 0x1 - -// -// CMPCTL (Compare Control) -// - -// -// LOADAMODE and LOADBMODE bits -// -#define CC_CTR_ZERO 0x0 -#define CC_CTR_PRD 0x1 -#define CC_CTR_ZERO_PRD 0x2 -#define CC_LD_DISABLE 0x3 - -// -// SHDWAMODE and SHDWBMODE bits -// -#define CC_SHADOW 0x0 -#define CC_IMMEDIATE 0x1 - -// -// AQCTLA and AQCTLB (Action Qualifier Control) -// - -// -// ZRO, PRD, CAU, CAD, CBU, CBD bits -// -#define AQ_NO_ACTION 0x0 -#define AQ_CLEAR 0x1 -#define AQ_SET 0x2 -#define AQ_TOGGLE 0x3 - -// -// DBCTL (Dead-Band Control) -// - -// -// OUT MODE bits -// -#define DB_DISABLE 0x0 -#define DBB_ENABLE 0x1 -#define DBA_ENABLE 0x2 -#define DB_FULL_ENABLE 0x3 - -// -// POLSEL bits -// -#define DB_ACTV_HI 0x0 -#define DB_ACTV_LOC 0x1 -#define DB_ACTV_HIC 0x2 -#define DB_ACTV_LO 0x3 - -// -// IN MODE -// -#define DBA_ALL 0x0 -#define DBB_RED_DBA_FED 0x1 -#define DBA_RED_DBB_FED 0x2 -#define DBB_ALL 0x3 - -// -// CHPCTL (chopper control) -// - -// -// CHPEN bit -// -#define CHP_DISABLE 0x0 -#define CHP_ENABLE 0x1 - -// -// CHPFREQ bits -// -#define CHP_DIV1 0x0 -#define CHP_DIV2 0x1 -#define CHP_DIV3 0x2 -#define CHP_DIV4 0x3 -#define CHP_DIV5 0x4 -#define CHP_DIV6 0x5 -#define CHP_DIV7 0x6 -#define CHP_DIV8 0x7 - -// -// CHPDUTY bits -// -#define CHP1_8TH 0x0 -#define CHP2_8TH 0x1 -#define CHP3_8TH 0x2 -#define CHP4_8TH 0x3 -#define CHP5_8TH 0x4 -#define CHP6_8TH 0x5 -#define CHP7_8TH 0x6 - -// -// TZSEL (Trip Zone Select) -// - -// -// CBCn and OSHTn bits -// -#define TZ_DISABLE 0x0 -#define TZ_ENABLE 0x1 - -// -// TZCTL (Trip Zone Control) -// - -// -// TZA and TZB bits -// -#define TZ_HIZ 0x0 -#define TZ_FORCE_HI 0x1 -#define TZ_FORCE_LO 0x2 -#define TZ_NO_CHANGE 0x3 - -// -// TZDCSEL (Trip Zone Digital Compare) -// - -// -// DCAEVT1, DCAEVT2, DCBEVT1, DCBEVT2 bits -// -#define TZ_EVT_DISABLE 0x0 -#define TZ_DCAH_LOW 0x1 -#define TZ_DCAH_HI 0x2 -#define TZ_DCAL_LOW 0x3 -#define TZ_DCAL_HI 0x4 -#define TZ_DCAL_HI_DCAH_LOW 0x5 - -#define TZ_DCBH_LOW 0x1 -#define TZ_DCBH_HI 0x2 -#define TZ_DCBL_LOW 0x3 -#define TZ_DCBL_HI 0x4 -#define TZ_DCBL_HI_DCBH_LOW 0x5 - -// -// ETSEL (Event Trigger Select) -// -#define ET_DCAEVT1SOC 0x0 -#define ET_CTR_ZERO 0x1 -#define ET_CTR_PRD 0x2 -#define ET_CTR_PRDZERO 0x3 -#define ET_CTRU_CMPA 0x4 -#define ET_CTRD_CMPA 0x5 -#define ET_CTRU_CMPB 0x6 -#define ET_CTRD_CMPB 0x7 - -// -// ETPS (Event Trigger Pre-scale) -// - -// -// INTPRD, SOCAPRD, SOCBPRD bits -// -#define ET_DISABLE 0x0 -#define ET_1ST 0x1 -#define ET_2ND 0x2 -#define ET_3RD 0x3 - -// -// HRPWM (High Resolution PWM) -// - -// -// HRCNFG -// -#define HR_DISABLE 0x0 -#define HR_REP 0x1 -#define HR_FEP 0x2 -#define HR_BEP 0x3 - -#define HR_CMP 0x0 -#define HR_PHS 0x1 - -#define HR_CTR_ZERO 0x0 -#define HR_CTR_PRD 0x1 -#define HR_CTR_ZERO_PRD 0x2 - -#define HR_NORM_B 0x0 -#define HR_INVERT_B 0x1 - -// -// DC (Digital Compare) -// - -// -// DCTRIPSEL -// -#define DC_TZ1 0x0 -#define DC_TZ2 0x1 -#define DC_TZ3 0x2 -#define DC_TRIPIN1 0x0 -#define DC_TRIPIN2 0x1 -#define DC_TRIPIN3 0x2 -#define DC_TRIPIN4 0x3 -#define DC_TRIPIN5 0x4 -#define DC_TRIPIN6 0x5 -#define DC_TRIPIN7 0x6 -#define DC_TRIPIN8 0x7 -#define DC_TRIPIN9 0x8 -#define DC_TRIPIN10 0x9 -#define DC_TRIPIN11 0xA -#define DC_TRIPIN12 0xB -// Reserved 0xC -#define DC_TRIPIN14 0xD -#define DC_TRIPIN15 0xE -#define DC_COMBINATION 0xF - -// -// DCFCTL -// -#define DC_SRC_DCAEVT1 0x0 -#define DC_SRC_DCAEVT2 0x1 -#define DC_SRC_DCBEVT1 0x2 -#define DC_SRC_DCBEVT2 0x3 - -#define DC_PULSESEL_PRD 0x0 -#define DC_PULSESEL_ZERO 0x1 -#define DC_PULSESEL_ZERO_PRD 0x2 - -#define DC_BLANK_DISABLE 0x0 -#define DC_BLANK_ENABLE 0x1 - -#define DC_BLANK_NOTINV 0x0 -#define DC_BLANK_INV 0x1 - -// -//DCACTL/DCBCTL -// -#define DC_EVT1 0x0 -#define DC_EVT2 0x0 -#define DC_EVT_FLT 0x1 -#define DC_EVT_SYNC 0x0 -#define DC_EVT_ASYNC 0x1 -#define DC_SOC_DISABLE 0x0 -#define DC_SOC_ENABLE 0x1 - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F2837xD_EPWM_DEFINES_H - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Emif_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Emif_defines.h deleted file mode 100644 index cb11472b04..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Emif_defines.h +++ /dev/null @@ -1,319 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Emif_defines.h -// -// TITLE: #defines used in EMIF examples -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_EMIF_DEFINES_H -#define F2837xD_EMIF_DEFINES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -//cpu1 to cpu2 message for handshaking -// -#define CPU1_CPU2_MSG 0x3fd00 - -// -//cpu2_to_cpu1 message ram for handshaking -// -#define CPU2_CPU1_MSG 0x3fb00 - -#define MSEL_EMIF1_CPU1 0x93A5CE71 -#define MSEL_EMIF1_CPU2 0x93A5CE72 -#define MSEL_DEF_3 0x93A5CE73 -#define MSEL_DEF_0 0x93A5CE70 -#define MSEL_DEF_1 0x93A5CE71 -#define MSEL_DEF_2 0x93A5CE72 - -// -//soft reset bit register -// -#define EMIF_SOFT_PRES_REG 0x5D084 - -// -//Device capability/EMIF customization register -// -#define EMIF_DEV_DC_REG 0x5D014 - -// -// Values for ASYNC_CSx_CR Registers -// -#define EMIF_ASYNC_ASIZE_8 0x0 -#define EMIF_ASYNC_ASIZE_16 0x1 -#define EMIF_ASYNC_ASIZE_32 0x2 - -#define EMIF_ASYNC_TA_1 0x0 -#define EMIF_ASYNC_TA_2 0x4 -#define EMIF_ASYNC_TA_3 0x8 -#define EMIF_ASYNC_TA_4 0xC - -#define EMIF_ASYNC_RHOLD_1 0x00 -#define EMIF_ASYNC_RHOLD_2 0x10 -#define EMIF_ASYNC_RHOLD_3 0x20 -#define EMIF_ASYNC_RHOLD_4 0x30 -#define EMIF_ASYNC_RHOLD_5 0x40 -#define EMIF_ASYNC_RHOLD_6 0x50 -#define EMIF_ASYNC_RHOLD_7 0x60 -#define EMIF_ASYNC_RHOLD_8 0x70 - -#define EMIF_ASYNC_RSTROBE_1 0x0000 -#define EMIF_ASYNC_RSTROBE_2 0x0080 -#define EMIF_ASYNC_RSTROBE_3 0x0100 -#define EMIF_ASYNC_RSTROBE_4 0x0180 -#define EMIF_ASYNC_RSTROBE_5 0x0200 -#define EMIF_ASYNC_RSTROBE_6 0x0280 -#define EMIF_ASYNC_RSTROBE_7 0x0300 -#define EMIF_ASYNC_RSTROBE_8 0x0380 -#define EMIF_ASYNC_RSTROBE_9 0x0400 -#define EMIF_ASYNC_RSTROBE_10 0x0480 -#define EMIF_ASYNC_RSTROBE_11 0x0500 -#define EMIF_ASYNC_RSTROBE_12 0x0580 -#define EMIF_ASYNC_RSTROBE_13 0x0600 -#define EMIF_ASYNC_RSTROBE_14 0x0680 -#define EMIF_ASYNC_RSTROBE_15 0x0700 -#define EMIF_ASYNC_RSTROBE_16 0x0780 -#define EMIF_ASYNC_RSTROBE_17 0x0800 -#define EMIF_ASYNC_RSTROBE_18 0x0880 -#define EMIF_ASYNC_RSTROBE_19 0x0900 -#define EMIF_ASYNC_RSTROBE_20 0x0980 -#define EMIF_ASYNC_RSTROBE_21 0x0A00 -#define EMIF_ASYNC_RSTROBE_22 0x0A80 -#define EMIF_ASYNC_RSTROBE_23 0x0B00 -#define EMIF_ASYNC_RSTROBE_24 0x0B80 -#define EMIF_ASYNC_RSTROBE_25 0x0C00 -#define EMIF_ASYNC_RSTROBE_26 0x0C80 -#define EMIF_ASYNC_RSTROBE_27 0x0D00 -#define EMIF_ASYNC_RSTROBE_28 0x0D80 -#define EMIF_ASYNC_RSTROBE_29 0x0E00 -#define EMIF_ASYNC_RSTROBE_30 0x0E80 -#define EMIF_ASYNC_RSTROBE_31 0x0F00 -#define EMIF_ASYNC_RSTROBE_32 0x0F80 -#define EMIF_ASYNC_RSTROBE_33 0x1000 -#define EMIF_ASYNC_RSTROBE_34 0x1080 -#define EMIF_ASYNC_RSTROBE_35 0x1100 -#define EMIF_ASYNC_RSTROBE_36 0x1180 -#define EMIF_ASYNC_RSTROBE_37 0x1200 -#define EMIF_ASYNC_RSTROBE_38 0x1280 -#define EMIF_ASYNC_RSTROBE_39 0x1300 -#define EMIF_ASYNC_RSTROBE_40 0x1380 -#define EMIF_ASYNC_RSTROBE_41 0x1400 -#define EMIF_ASYNC_RSTROBE_42 0x1480 -#define EMIF_ASYNC_RSTROBE_43 0x1500 -#define EMIF_ASYNC_RSTROBE_44 0x1580 -#define EMIF_ASYNC_RSTROBE_45 0x1600 -#define EMIF_ASYNC_RSTROBE_46 0x1680 -#define EMIF_ASYNC_RSTROBE_47 0x1700 -#define EMIF_ASYNC_RSTROBE_48 0x1780 -#define EMIF_ASYNC_RSTROBE_49 0x1800 -#define EMIF_ASYNC_RSTROBE_50 0x1880 -#define EMIF_ASYNC_RSTROBE_51 0x1900 -#define EMIF_ASYNC_RSTROBE_52 0x1980 -#define EMIF_ASYNC_RSTROBE_53 0x1A00 -#define EMIF_ASYNC_RSTROBE_54 0x1A80 -#define EMIF_ASYNC_RSTROBE_55 0x1B00 -#define EMIF_ASYNC_RSTROBE_56 0x1B80 -#define EMIF_ASYNC_RSTROBE_57 0x1C00 -#define EMIF_ASYNC_RSTROBE_58 0x1C80 -#define EMIF_ASYNC_RSTROBE_59 0x1D00 -#define EMIF_ASYNC_RSTROBE_60 0x1D80 -#define EMIF_ASYNC_RSTROBE_61 0x1E00 -#define EMIF_ASYNC_RSTROBE_62 0x1E80 -#define EMIF_ASYNC_RSTROBE_63 0x1F00 -#define EMIF_ASYNC_RSTROBE_64 0x1F80 - -#define EMIF_ASYNC_RSETUP_1 0x0000 -#define EMIF_ASYNC_RSETUP_2 0x2000 -#define EMIF_ASYNC_RSETUP_3 0x4000 -#define EMIF_ASYNC_RSETUP_4 0x6000 -#define EMIF_ASYNC_RSETUP_5 0x8000 -#define EMIF_ASYNC_RSETUP_6 0xA000 -#define EMIF_ASYNC_RSETUP_7 0xC000 -#define EMIF_ASYNC_RSETUP_8 0xE000 -#define EMIF_ASYNC_RSETUP_9 0x10000 -#define EMIF_ASYNC_RSETUP_10 0x12000 -#define EMIF_ASYNC_RSETUP_11 0x14000 -#define EMIF_ASYNC_RSETUP_12 0x16000 -#define EMIF_ASYNC_RSETUP_13 0x18000 -#define EMIF_ASYNC_RSETUP_14 0x1A000 -#define EMIF_ASYNC_RSETUP_15 0x1C000 -#define EMIF_ASYNC_RSETUP_16 0x1E000 - -#define EMIF_ASYNC_WHOLD_1 0x00000 -#define EMIF_ASYNC_WHOLD_2 0x20000 -#define EMIF_ASYNC_WHOLD_3 0x40000 -#define EMIF_ASYNC_WHOLD_4 0x60000 -#define EMIF_ASYNC_WHOLD_5 0x80000 -#define EMIF_ASYNC_WHOLD_6 0xA0000 -#define EMIF_ASYNC_WHOLD_7 0xC0000 -#define EMIF_ASYNC_WHOLD_8 0xE0000 - -#define EMIF_ASYNC_WSTROBE_1 0x0000000 -#define EMIF_ASYNC_WSTROBE_2 0x0100000 -#define EMIF_ASYNC_WSTROBE_3 0x0200000 -#define EMIF_ASYNC_WSTROBE_4 0x0300000 -#define EMIF_ASYNC_WSTROBE_5 0x0400000 -#define EMIF_ASYNC_WSTROBE_6 0x0500000 -#define EMIF_ASYNC_WSTROBE_7 0x0600000 -#define EMIF_ASYNC_WSTROBE_8 0x0700000 -#define EMIF_ASYNC_WSTROBE_9 0x0800000 -#define EMIF_ASYNC_WSTROBE_10 0x0900000 -#define EMIF_ASYNC_WSTROBE_11 0x0A00000 -#define EMIF_ASYNC_WSTROBE_12 0x0B00000 -#define EMIF_ASYNC_WSTROBE_13 0x0C00000 -#define EMIF_ASYNC_WSTROBE_14 0x0D00000 -#define EMIF_ASYNC_WSTROBE_15 0x0E00000 -#define EMIF_ASYNC_WSTROBE_16 0x0F00000 -#define EMIF_ASYNC_WSTROBE_17 0x1000000 -#define EMIF_ASYNC_WSTROBE_18 0x1100000 -#define EMIF_ASYNC_WSTROBE_19 0x1200000 -#define EMIF_ASYNC_WSTROBE_20 0x1300000 -#define EMIF_ASYNC_WSTROBE_21 0x1400000 -#define EMIF_ASYNC_WSTROBE_22 0x1500000 -#define EMIF_ASYNC_WSTROBE_23 0x1600000 -#define EMIF_ASYNC_WSTROBE_24 0x1700000 -#define EMIF_ASYNC_WSTROBE_25 0x1800000 -#define EMIF_ASYNC_WSTROBE_26 0x1900000 -#define EMIF_ASYNC_WSTROBE_27 0x1A00000 -#define EMIF_ASYNC_WSTROBE_28 0x1B00000 -#define EMIF_ASYNC_WSTROBE_29 0x1C00000 -#define EMIF_ASYNC_WSTROBE_30 0x1D00000 -#define EMIF_ASYNC_WSTROBE_31 0x1E00000 -#define EMIF_ASYNC_WSTROBE_32 0x1F00000 -#define EMIF_ASYNC_WSTROBE_33 0x2000000 -#define EMIF_ASYNC_WSTROBE_34 0x2100000 -#define EMIF_ASYNC_WSTROBE_35 0x2200000 -#define EMIF_ASYNC_WSTROBE_36 0x2300000 -#define EMIF_ASYNC_WSTROBE_37 0x2400000 -#define EMIF_ASYNC_WSTROBE_38 0x2500000 -#define EMIF_ASYNC_WSTROBE_39 0x2600000 -#define EMIF_ASYNC_WSTROBE_40 0x2700000 -#define EMIF_ASYNC_WSTROBE_41 0x2800000 -#define EMIF_ASYNC_WSTROBE_42 0x2900000 -#define EMIF_ASYNC_WSTROBE_43 0x2A00000 -#define EMIF_ASYNC_WSTROBE_44 0x2B00000 -#define EMIF_ASYNC_WSTROBE_45 0x2C00000 -#define EMIF_ASYNC_WSTROBE_46 0x2D00000 -#define EMIF_ASYNC_WSTROBE_47 0x2E00000 -#define EMIF_ASYNC_WSTROBE_48 0x2F00000 -#define EMIF_ASYNC_WSTROBE_49 0x3000000 -#define EMIF_ASYNC_WSTROBE_50 0x3100000 -#define EMIF_ASYNC_WSTROBE_51 0x3200000 -#define EMIF_ASYNC_WSTROBE_52 0x3300000 -#define EMIF_ASYNC_WSTROBE_53 0x3400000 -#define EMIF_ASYNC_WSTROBE_54 0x3500000 -#define EMIF_ASYNC_WSTROBE_55 0x3600000 -#define EMIF_ASYNC_WSTROBE_56 0x3700000 -#define EMIF_ASYNC_WSTROBE_57 0x3800000 -#define EMIF_ASYNC_WSTROBE_58 0x3900000 -#define EMIF_ASYNC_WSTROBE_59 0x3A00000 -#define EMIF_ASYNC_WSTROBE_60 0x3B00000 -#define EMIF_ASYNC_WSTROBE_61 0x3C00000 -#define EMIF_ASYNC_WSTROBE_62 0x3D00000 -#define EMIF_ASYNC_WSTROBE_63 0x3E00000 -#define EMIF_ASYNC_WSTROBE_64 0x3F00000 - -#define EMIF_ASYNC_WSETUP_1 0x00000000 -#define EMIF_ASYNC_WSETUP_2 0x04000000 -#define EMIF_ASYNC_WSETUP_3 0x08000000 -#define EMIF_ASYNC_WSETUP_4 0x0C000000 -#define EMIF_ASYNC_WSETUP_5 0x10000000 -#define EMIF_ASYNC_WSETUP_6 0x14000000 -#define EMIF_ASYNC_WSETUP_7 0x18000000 -#define EMIF_ASYNC_WSETUP_8 0x1C000000 -#define EMIF_ASYNC_WSETUP_9 0x20000000 -#define EMIF_ASYNC_WSETUP_10 0x24000000 -#define EMIF_ASYNC_WSETUP_11 0x28000000 -#define EMIF_ASYNC_WSETUP_12 0x2C000000 -#define EMIF_ASYNC_WSETUP_13 0x30000000 -#define EMIF_ASYNC_WSETUP_14 0x34000000 -#define EMIF_ASYNC_WSETUP_15 0x38000000 -#define EMIF_ASYNC_WSETUP_16 0x3C000000 - -#define EMIF_ASYNC_EW_DISABLE 0x00000000 -#define EMIF_ASYNC_EW_ENABLE 0x40000000 - -#define EMIF_ASYNC_SS_DISABLE 0x00000000 -#define EMIF_ASYNC_SS_ENABLE 0x80000000 - -// -// Values for ASYNC_WCCR Register -// -#define EMIF_ASYNC_WCCR_WP_LOW 0x00000000 -#define EMIF_ASYNC_WCCR_WP_HIGH 0x01000000 - -// -// Read mask for the registers which has reserved bits. -// -#define ASYNC_WCCR_RDMASK 0xF0FF00FF -#define SDRAM_CR_RDMASK 0xE3FF7F7F -#define SDRAM_RCR_RDMASK 0x00071FFF -#define SDRAM_TR_RDMASK 0xFF77FF70 -#define SDR_EXT_TMNG_RDMASK 0x1F -#define INT_RAW_RDMASK 0x3F -#define INT_MASK_RDMASK 0x3F -#define IO_CTRL_RDMASK_RDMASK 0xFFFF -#define IO_STAT_RDMASK_RDMASK 0xF -#define NAND_FLASH_CTRL_RDMASK 0x3F3F -#define NAND_FLASH_STAT_RDMASK 0x30F0F -#define IODFT_TLECR_REG_RDMASK 0xFFFF -#define IODFT_TLGCR_REG_RDMASK 0x71FF -#define IODFT_TLAMR_REG_RDMASK 0x0FFFFFFF -#define IODFT_TLDCMR_REG_RDMASK 0x3fff3f07 -#define MODEL_REL_NUM_REG_RDMASK 0xFF -#define NAND_FLASH_4BIT_ECCLR_RDMASK 0x3F -#define NAND_FLASH_4BIT_ECCx_RDMASK 0x03ff03ff -#define NAND_FLASH_ERR_ADDRx_RDMASK 0x03ff03ff -#define NAND_FLASH_ERR_VALx_RDMASK 0x03ff03ff - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F2837xD_EMIF_DEFINES_H - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Examples.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Examples.h deleted file mode 100644 index bd3a3994b0..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Examples.h +++ /dev/null @@ -1,448 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Examples.h -// -// TITLE: F2837xD Device Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_EXAMPLES_H -#define F2837xD_EXAMPLES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -// The following are values that can be passed to the -// InitSysPll() & InitAuxPll() to select SYSPLL/AUXPLL integer multiplier -// -#define IMULT_0 0 -#define IMULT_1 1 -#define IMULT_2 2 -#define IMULT_3 3 -#define IMULT_4 4 -#define IMULT_5 5 -#define IMULT_6 6 -#define IMULT_7 7 -#define IMULT_8 8 -#define IMULT_9 9 -#define IMULT_10 10 -#define IMULT_11 11 -#define IMULT_12 12 -#define IMULT_13 13 -#define IMULT_14 14 -#define IMULT_15 15 -#define IMULT_16 16 -#define IMULT_17 17 -#define IMULT_18 18 -#define IMULT_19 19 -#define IMULT_20 20 -#define IMULT_21 21 -#define IMULT_22 22 -#define IMULT_23 23 -#define IMULT_24 24 -#define IMULT_25 25 -#define IMULT_26 26 -#define IMULT_27 27 -#define IMULT_28 28 -#define IMULT_29 29 -#define IMULT_30 30 -#define IMULT_31 31 -#define IMULT_32 32 -#define IMULT_33 33 -#define IMULT_34 34 -#define IMULT_35 35 -#define IMULT_36 36 -#define IMULT_37 37 -#define IMULT_38 38 -#define IMULT_39 39 -#define IMULT_40 40 -#define IMULT_41 41 -#define IMULT_42 42 -#define IMULT_43 43 -#define IMULT_44 44 -#define IMULT_45 45 -#define IMULT_46 46 -#define IMULT_47 47 -#define IMULT_48 48 -#define IMULT_49 49 -#define IMULT_50 50 -#define IMULT_51 51 -#define IMULT_52 52 -#define IMULT_53 53 -#define IMULT_54 54 -#define IMULT_55 55 -#define IMULT_56 56 -#define IMULT_57 57 -#define IMULT_58 58 -#define IMULT_59 59 -#define IMULT_60 60 -#define IMULT_61 61 -#define IMULT_62 62 -#define IMULT_63 63 -#define IMULT_64 64 -#define IMULT_65 65 -#define IMULT_66 66 -#define IMULT_67 67 -#define IMULT_68 68 -#define IMULT_69 69 -#define IMULT_70 70 -#define IMULT_71 71 -#define IMULT_72 72 -#define IMULT_73 73 -#define IMULT_74 74 -#define IMULT_75 75 -#define IMULT_76 76 -#define IMULT_77 77 -#define IMULT_78 78 -#define IMULT_79 79 -#define IMULT_80 80 -#define IMULT_81 81 -#define IMULT_82 82 -#define IMULT_83 83 -#define IMULT_84 84 -#define IMULT_85 85 -#define IMULT_86 86 -#define IMULT_87 87 -#define IMULT_88 88 -#define IMULT_89 89 -#define IMULT_90 90 -#define IMULT_91 91 -#define IMULT_92 92 -#define IMULT_93 93 -#define IMULT_94 94 -#define IMULT_95 95 -#define IMULT_96 96 -#define IMULT_97 97 -#define IMULT_98 98 -#define IMULT_99 99 -#define IMULT_100 100 -#define IMULT_101 101 -#define IMULT_102 102 -#define IMULT_103 103 -#define IMULT_104 104 -#define IMULT_105 105 -#define IMULT_106 106 -#define IMULT_107 107 -#define IMULT_108 108 -#define IMULT_109 109 -#define IMULT_110 110 -#define IMULT_111 111 -#define IMULT_112 112 -#define IMULT_113 113 -#define IMULT_114 114 -#define IMULT_115 115 -#define IMULT_116 116 -#define IMULT_117 117 -#define IMULT_118 118 -#define IMULT_119 119 -#define IMULT_120 120 -#define IMULT_121 121 -#define IMULT_122 122 -#define IMULT_123 123 -#define IMULT_124 124 -#define IMULT_125 125 -#define IMULT_126 126 -#define IMULT_127 127 - -// -// The following are values that can be passed to the -// InitSysPll() & InitAuxPll() to select SYSPLL/AUXPLL fractional multiplier -// -#define FMULT_0 0 -#define FMULT_0pt25 1 -#define FMULT_0pt5 2 -#define FMULT_0pt75 3 - -// -// The following are values that can be passed to the -// InitSysPll() to select divsel for SYSPLL -// -#define PLLCLK_BY_1 0 -#define PLLCLK_BY_2 1 -#define PLLCLK_BY_4 2 -#define PLLCLK_BY_6 3 -#define PLLCLK_BY_8 4 -#define PLLCLK_BY_10 5 -#define PLLCLK_BY_12 6 -#define PLLCLK_BY_14 7 -#define PLLCLK_BY_16 8 -#define PLLCLK_BY_18 9 -#define PLLCLK_BY_20 10 -#define PLLCLK_BY_22 11 -#define PLLCLK_BY_24 12 -#define PLLCLK_BY_26 13 -#define PLLCLK_BY_28 14 -#define PLLCLK_BY_30 15 -#define PLLCLK_BY_32 16 -#define PLLCLK_BY_34 17 -#define PLLCLK_BY_36 18 -#define PLLCLK_BY_38 19 -#define PLLCLK_BY_40 20 -#define PLLCLK_BY_42 21 -#define PLLCLK_BY_44 22 -#define PLLCLK_BY_46 23 -#define PLLCLK_BY_48 24 -#define PLLCLK_BY_50 25 -#define PLLCLK_BY_52 26 -#define PLLCLK_BY_54 27 -#define PLLCLK_BY_56 28 -#define PLLCLK_BY_58 29 -#define PLLCLK_BY_60 30 -#define PLLCLK_BY_62 31 -#define PLLCLK_BY_64 32 -#define PLLCLK_BY_66 33 -#define PLLCLK_BY_68 34 -#define PLLCLK_BY_70 35 -#define PLLCLK_BY_72 36 -#define PLLCLK_BY_74 37 -#define PLLCLK_BY_76 38 -#define PLLCLK_BY_78 39 -#define PLLCLK_BY_80 40 -#define PLLCLK_BY_82 41 -#define PLLCLK_BY_84 42 -#define PLLCLK_BY_86 43 -#define PLLCLK_BY_88 44 -#define PLLCLK_BY_90 45 -#define PLLCLK_BY_92 46 -#define PLLCLK_BY_94 47 -#define PLLCLK_BY_96 48 -#define PLLCLK_BY_98 49 -#define PLLCLK_BY_100 50 -#define PLLCLK_BY_102 51 -#define PLLCLK_BY_104 52 -#define PLLCLK_BY_106 53 -#define PLLCLK_BY_108 54 -#define PLLCLK_BY_110 55 -#define PLLCLK_BY_112 56 -#define PLLCLK_BY_114 57 -#define PLLCLK_BY_116 58 -#define PLLCLK_BY_118 59 -#define PLLCLK_BY_120 60 -#define PLLCLK_BY_122 61 -#define PLLCLK_BY_124 62 -#define PLLCLK_BY_126 63 - -// -// The following are values that can be passed to the -// InitAuxPll() to select divsel for AUXPLL -// -#define AUXPLLRAWCLK_BY_1 0 -#define AUXPLLRAWCLK_BY_2 1 -#define AUXPLLRAWCLK_BY_4 2 -#define AUXPLLRAWCLK_BY_8 3 - -// -// The following are values that can be passed to the -// IntOsc2Sel() & XtalOscSel() to select system PLL (or) AUX PLL -// -#define SYSTEM_PLL (Uint16) 0 -#define AUX_PLL (Uint16) 1 - -// -// The following are values that can be passed to the -// InitSysPll() & InitAuxPll() to select clock source -// -#define INT_OSC2 0 -#define XTAL_OSC 1 -#define INT_OSC1 2 -#define AUXCLKIN 4 - -// -// Specify the clock rate of the CPU (SYSCLKOUT) in nS. -// -// Take into account the input clock frequency and the PLL multiplier -// selected in step 1. -// -// Use one of the values provided, or define your own. -// The trailing L is required tells the compiler to treat -// the number as a 64-bit value. -// -// Only one statement should be uncommented. -// -// Example: 200 MHz devices: -// CLKIN is a 10 MHz crystal or internal 10 MHz oscillator -// -// In step 1 the user specified the PLL multiplier = 40 for a -// 200 MHz CPU clock (SYSCLKOUT = 200 MHz). -// -// In this case, the CPU_RATE will be 5.000L -// Uncomment the line: #define CPU_RATE 5.000L -// - -#define CPU_RATE 5.00L // for a 200MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 5.263L // for a 190MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 5.556L // for a 180MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 5.882L // for a 170MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 6.250L // for a 160MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 7.692L // for a 130MHz CPU clock speed (SYSCLKOUT) -//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) - -// -// The following pointer to a function call calibrates the ADC reference, -// DAC offset, and internal oscillators -// -#define Device_cal (void (*)(void))0x070282 - -// -// The following pointers to functions calibrate the ADC linearity. Use this -// in the AdcSetMode(...) function only -// -#define CalAdcaINL (void (*)(void))0x0703B4 -#define CalAdcbINL (void (*)(void))0x0703B2 -#define CalAdccINL (void (*)(void))0x0703B0 -#define CalAdcdINL (void (*)(void))0x0703AE - -// -// The following pointer to a function call looks up the ADC offset trim for a -// given condition. Use this in the AdcSetMode(...) function only. -// -#define GetAdcOffsetTrimOTP (Uint16 (*)(Uint16 OTPoffset))0x0703AC - -// -// Includes -// -#include "F2837xD_GlobalPrototypes.h" // Prototypes for global functions - // within the .c files. -#include "F2837xD_cputimervars.h" -#include "F2837xD_Cla_defines.h" // Macros used for CLA examples. -#include "F2837xD_EPwm_defines.h" // Macros used for PWM examples. -#include "F2837xD_Adc_defines.h" // Macros used for ADC examples. -#include "F2837xD_Emif_defines.h" // Macros used for EMIF examples. -#include "F2837xD_Gpio_defines.h" // Macros used for GPIO support code -#include "F2837xD_I2c_defines.h" // Macros used for I2C examples. -#include "F2837xD_Ipc_defines.h" // Macros used for IPC support code. -#include "F2837xD_Pie_defines.h" // Macros used for PIE examples. -#include "F2837xD_Dma_defines.h" // Macros used for DMA examples. -#include "F2837xD_SysCtrl_defines.h" // Macros used for LPM support code -#include "F2837xD_Upp_defines.h" // Macros used for UPP examples. - -#define PARTNO_2837xPACKAGEHERE 0x00 - -#define CPU_FRQ_200MHZ 1 -#define CPU_FRQ_150MHZ 0 -#define CPU_FRQ_120MHZ 0 - -// -// Include files not used with F/BIOS -// -#ifndef F28_BIOS -#include "F2837xD_defaultisr.h" -#endif - -extern void F28x_usDelay(long LoopCount); - -// -// DO NOT MODIFY THIS LINE. -// -#define DELAY_US(A) F28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L) - -// -// Timer Operations: -// - -// -// Start Timer: -// -#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 - -// -// Stop Timer: -// -#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 - -// -// Reload Timer With period Value: -// -#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 - -// -// Read 32-Bit Timer Value: -// -#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all - -// -// Read 32-Bit Period Value: -// -#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all - -// -// Start Timer: -// -#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 -#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 - -// -// Stop Timer: -// -#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 -#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 - -// -// Reload Timer With period Value: -// -#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 -#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 - -// -// Read 32-Bit Timer Value: -// -#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all -#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all - -// -// Read 32-Bit Period Value: -// -#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all -#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // end of F2837xD_EXAMPLES_H definition - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_GlobalPrototypes.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_GlobalPrototypes.h deleted file mode 100644 index 1b63dc48ee..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_GlobalPrototypes.h +++ /dev/null @@ -1,363 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_GlobalPrototypes.h -// -// TITLE: Global prototypes for F2837xD Examples -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_GLOBALPROTOTYPES_H -#define F2837xD_GLOBALPROTOTYPES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Function Prototypes (Shared) -// -extern void EnableInterrupts(void); -extern void InitAPwm1Gpio(void); -extern void InitCAN(void); -extern void InitECap(void); -extern void InitECapGpio(void); -extern void InitECap1Gpio(Uint16 pin); -extern void InitECap2Gpio(Uint16 pin); -extern void InitECap3Gpio(Uint16 pin); -extern void InitECap4Gpio(Uint16 pin); -extern void InitECap5Gpio(Uint16 pin); -extern void InitECap6Gpio(Uint16 pin); -extern void InitEQep1Gpio(void); -extern void InitEQep2Gpio(void); -extern void InitEQep3Gpio(void); -extern void InitEPwmGpio(void); -extern void InitEPwm1Gpio(void); -extern void InitEPwm2Gpio(void); -extern void InitEPwm3Gpio(void); -extern void InitEPwm4Gpio(void); -extern void InitEPwm5Gpio(void); -extern void InitEPwm6Gpio(void); -extern void InitEPwm7Gpio(void); -extern void InitEPwm8Gpio(void); -extern void InitEPwm9Gpio(void); -extern void InitEPwm10Gpio(void); -extern void InitEPwm11Gpio(void); -extern void InitEPwm12Gpio(void); -extern void InitPeripheralClocks(void); -extern void DisablePeripheralClocks(void); -extern void InitPieCtrl(void); -extern void InitPieVectTable(void); -extern void InitSpi(void); -extern void InitSpiGpio(void); -extern void InitSpiaGpio(void); -extern void InitSysCtrl(void); -extern void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, - Uint16 divsel); -extern void InitAuxPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, - Uint16 divsel); - -#define KickDog ServiceDog // For compatibility with previous versions -extern void ServiceDog(void); -extern void DisableDog(void); - -extern Uint16 CsmUnlock(void); -extern void SysIntOsc1Sel (void); -extern void SysIntOsc2Sel (void); -extern void SysXtalOscSel (void); - -extern void AuxIntOsc2Sel (void); -extern void AuxXtalOscSel (void); -extern void AuxAuxClkSel (void); - -extern void SetDBGIER(Uint16 dbgier); - -// -// CAUTION -// This function MUST be executed out of RAM. Executing it -// out of OTP/Flash will yield unpredictable results -// -extern void InitFlash(void); -extern void InitFlash_Bank0(void); -extern void InitFlash_Bank1(void); -extern void FlashOff(void); -extern void FlashOff_Bank0(void); -extern void FlashOff_Bank1(void); -extern void SeizeFlashPump(void); -extern void SeizeFlashPump_Bank0(void); -extern void SeizeFlashPump_Bank1(void); -extern void ReleaseFlashPump(void); - -// -//LPM functions in F2837xD_SysCtrl.c -// -void IDLE(); -void STANDBY(); -void HALT(); -void HIB(); - -// -//ADC functions -// -extern void AdcSetMode(Uint16 adc, Uint16 resolution, Uint16 signalmode); -extern void CalAdcINL(Uint16 adc); - -// -// DMA Functions -// -extern void DMAInitialize(void); - -// -// DMA Channel 1 -// -extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); -extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep); -extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, - Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH1(void); - -// -// DMA Channel 2 -// -extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); -extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep); -extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, - Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH2(void); - -// -// DMA Channel 3 -// -extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); -extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep); -extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, - Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH3(void); - -// -// DMA Channel 4 -// -extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); -extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep); -extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, - Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH4(void); - -// -// DMA Channel 5 -// -extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); -extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); -extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep); -extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, - Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH5(void); - -// -// DMA Channel 6 -// -extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, - volatile Uint16 *DMA_Source); -extern void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source); -extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep); -extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); -extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep); -extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, - Uint16 chintmode, - Uint16 chinte); -extern void StartDMACH6(void); - -// -//GPIO Functions -// -extern void InitGpio(); -extern void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition); -extern void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags); -extern void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags); -extern void GPIO_SetupXINT1Gpio(Uint16 gpioNumber); -extern void GPIO_SetupXINT2Gpio(Uint16 gpioNumber); -extern void GPIO_SetupXINT3Gpio(Uint16 gpioNumber); -extern void GPIO_SetupXINT4Gpio(Uint16 gpioNumber); -extern void GPIO_SetupXINT5Gpio(Uint16 gpioNumber); -extern void GPIO_SelectIpcInt(Uint16 newFlag); -extern void GPIO_EnableUnbondedIOPullupsFor100Pin(void); -extern void GPIO_EnableUnbondedIOPullupsFor100Pin(void); -extern void GPIO_EnableUnbondedIOPullups(void); -Uint16 GPIO_ReadPin(Uint16 gpioNumber); -void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal); - -// -//IPC Functions -// -extern void InitIpc(); -extern Uint64 ReadIpcTimer(); -extern void SendIpcData(void *data, Uint16 word_length, Uint16 flag); -extern void RecvIpcData(void *recv_buf, Uint16 word_length); -extern void FillIpcSendData(Uint16 fill_data); -extern void SendIpcCommand(Uint32 command, Uint32 address, Uint32 data, - Uint16 flag); -extern void SendIpcFlag(Uint16 flag); -extern void AckIpcFlag(Uint16 flag); -extern void CancelIpcFlag(Uint16 flag); -extern void WaitForIpcFlag(Uint16 flag); -extern void WaitForIpcAck(Uint16 flag); -extern void IpcSync(Uint16 flag); - -// -// CAN Functions -// -extern void CanGpioPinMuxing(Uint32 ulBase, Uint16 canTxRxPin); -extern void CanAGpioConfig(Uint16 canaTxRxPin); -extern void CanBGpioConfig(Uint16 canbTxRxPin); -extern void CanModuleClkSelect(Uint32 ulBase, Uint16 ucSource); - -// -// I2C Functions -// -extern void I2cAGpioConfig(Uint16 I2caDataClkPin); -extern void I2cBGpioConfig(Uint16 I2cbDataClkPin); - -// -// McBSP functions -// McBSPA -// -extern void InitMcbspa(void); -extern void InitMcbspaInt(void); -extern void InitMcbspa8bit(void); -extern void InitMcbspa12bit(void); -extern void InitMcbspa16bit(void); -extern void InitMcbspa20bit(void); -extern void InitMcbspa24bit(void); -extern void InitMcbspa32bit(void); -extern void InitMcbspaGpio(void); -extern void delay_loop(void); - -// -// McBSPB -// -extern void InitMcbspb(void); -extern void InitMcbspbInt(void); -extern void InitMcbspb8bit(void); -extern void InitMcbspb12bit(void); -extern void InitMcbspb16bit(void); -extern void InitMcbspb20bit(void); -extern void InitMcbspb24bit(void); -extern void InitMcbspb32bit(void); -extern void InitMcbspbGpio(void); - -// -//Temp Sensor Functions -// -extern void InitTempSensor(float32 vrefhi_voltage); -extern int16 GetTemperatureC(int16 sensorSample); -extern int16 GetTemperatureK(int16 sensorSample); - -// -// External symbols created by the linker cmd file -// DSP28 examples will use these to relocate code from one LOAD location -// in Flash to a different RUN location in internal -// RAM -// -extern Uint16 RamfuncsLoadStart; -extern Uint16 RamfuncsLoadEnd; -extern Uint16 RamfuncsLoadSize; -extern Uint16 RamfuncsRunStart; -extern Uint16 RamfuncsRunEnd; -extern Uint16 RamfuncsRunSize; - -// -// External Boot ROM variable definitions -// -extern Uint16 EmuBMode; -extern Uint16 EmuBootPins; - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F2837xD_GLOBALPROTOTYPES_H - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Gpio_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Gpio_defines.h deleted file mode 100644 index ecbff65618..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Gpio_defines.h +++ /dev/null @@ -1,116 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Gpio_defines.h -// -// TITLE: F2837xD GPIO support definitions -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_GPIO_DEFINES_H -#define F2837xD_GPIO_DEFINES_H - -// -// Defines -// - -// -//CPU pin masters for GPIO_SelectPinMux() -// -#define GPIO_MUX_CPU1 0x0 -#define GPIO_MUX_CPU1CLA 0x1 -#define GPIO_MUX_CPU2 0x2 -#define GPIO_MUX_CPU2CLA 0x3 - -// -//Flags for GPIO_SetupPinOptions(). The qualification flags (SYNC, QUAL3, -//QUAL6, and ASYNC) take up two bits and must be in the order specified. -// -#define GPIO_INPUT 0 -#define GPIO_OUTPUT 1 -#define GPIO_PUSHPULL 0 -#define GPIO_PULLUP (1 << 0) -#define GPIO_INVERT (1 << 1) -#define GPIO_OPENDRAIN (1 << 2) -#define GPIO_SYNC (0x0 << 4) -#define GPIO_QUAL3 (0x1 << 4) -#define GPIO_QUAL6 (0x2 << 4) -#define GPIO_ASYNC (0x3 << 4) - -// -//Flags for GPIO_SetupLock(). -// -#define GPIO_UNLOCK 0 -#define GPIO_LOCK 1 - -// -//Commands for the CPU2->CPU1 GPIO configuration interrupt handler -// -#define GPIO_CMD_INIT 1L -#define GPIO_CMD_PINMUX 2L -#define GPIO_CMD_PINOPTS 3L -#define GPIO_CMD_WRITE32 4L -#define GPIO_CMD_WRITE16 5L -#define GPIO_CMD_READ32 6L -#define GPIO_CMD_READ16 7L - -// -//Helpful constants for array-based access to GPIO registers -// -#define GPY_CTRL_OFFSET (0x40/2) -#define GPY_DATA_OFFSET (0x8/2) - -#define GPYQSEL (0x2/2) -#define GPYMUX (0x6/2) -#define GPYDIR (0xA/2) -#define GPYPUD (0xC/2) -#define GPYINV (0x10/2) -#define GPYODR (0x12/2) -#define GPYGMUX (0x20/2) -#define GPYCSEL (0x28/2) -#define GPYLOCK (0x3C/2) -#define GPYCR (0x3E/2) - -#define GPYDAT (0x0/2) -#define GPYSET (0x2/2) -#define GPYCLEAR (0x4/2) -#define GPYTOGGLE (0x6/2) - -#endif // end of F2837xD_GPIO_DEFINES_H definition - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_I2c_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_I2c_defines.h deleted file mode 100644 index 95ed970e7f..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_I2c_defines.h +++ /dev/null @@ -1,184 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_I2c_defines.h -// -// TITLE: F2837xD I2C Common Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_I2C_DEFINES_H -#define F2837xD_I2C_DEFINES_H - -// -// Defines -// - -// -// Error Messages -// -#define I2C_ERROR 0xFFFF -#define I2C_ARB_LOST_ERROR 0x0001 -#define I2C_NACK_ERROR 0x0002 -#define I2C_BUS_BUSY_ERROR 0x1000 -#define I2C_STP_NOT_READY_ERROR 0x5555 -#define I2C_NO_FLAGS 0xAAAA -#define I2C_SUCCESS 0x0000 - -// -// Clear Status Flags -// -#define I2C_CLR_AL_BIT 0x0001 -#define I2C_CLR_NACK_BIT 0x0002 -#define I2C_CLR_ARDY_BIT 0x0004 -#define I2C_CLR_RRDY_BIT 0x0008 -#define I2C_CLR_SCD_BIT 0x0020 - -// -// Interrupt Source Messages -// -#define I2C_NO_ISRC 0x0000 -#define I2C_ARB_ISRC 0x0001 -#define I2C_NACK_ISRC 0x0002 -#define I2C_ARDY_ISRC 0x0003 -#define I2C_RX_ISRC 0x0004 -#define I2C_TX_ISRC 0x0005 -#define I2C_SCD_ISRC 0x0006 -#define I2C_AAS_ISRC 0x0007 - -// -// I2CMSG structure defines -// -#define I2C_NO_STOP 0 -#define I2C_YES_STOP 1 -#define I2C_RECEIVE 0 -#define I2C_TRANSMIT 1 -#define I2C_MAX_BUFFER_SIZE 16 - -// -// I2C Slave State defines -// -#define I2C_NOTSLAVE 0 -#define I2C_ADDR_AS_SLAVE 1 -#define I2C_ST_MSG_READY 2 - -// -// I2C Slave Receiver messages defines -// -#define I2C_SND_MSG1 1 -#define I2C_SND_MSG2 2 - -// -// I2C State defines -// -#define I2C_IDLE 0 -#define I2C_SLAVE_RECEIVER 1 -#define I2C_SLAVE_TRANSMITTER 2 -#define I2C_MASTER_RECEIVER 3 -#define I2C_MASTER_TRANSMITTER 4 - -// -// I2C Message Commands for I2CMSG struct -// -#define I2C_MSGSTAT_INACTIVE 0x0000 -#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 -#define I2C_MSGSTAT_WRITE_BUSY 0x0011 -#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 -#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 -#define I2C_MSGSTAT_RESTART 0x0022 -#define I2C_MSGSTAT_READ_BUSY 0x0023 - -// -// Generic defines -// -#define I2C_TRUE 1 -#define I2C_FALSE 0 -#define I2C_YES 1 -#define I2C_NO 0 -#define I2C_DUMMY_BYTE 0 - - -// -// These are the Defines to select I2C pin muxing when calling the functions -// I2cAGpioConfig() & I2cBGpioConfig() in F2837xD_I2C.c -// -#define I2C_A_GPIO0_GPIO1 1 //switch case 1 -#define I2C_A_GPIO32_GPIO33 2 //switch case 2 -#define I2C_A_GPIO42_GPIO43 3 //switch case 3 -#define I2C_A_GPIO91_GPIO92 4 //switch case 4 -#define I2C_A_GPIO63104_GPIO105 5 //switch case 5 - -#define I2C_B_GPIO2_GPIO3 1 //switch case 1 -#define I2C_B_GPIO134_GPIO35 2 //switch case 2 -#define I2C_B_GPIO40_GPIO41 3 //switch case 3 -#define I2C_B_GPIO66_GPIO69 4 //switch case 4 - -// -// Globals -// - -// -// I2C Message Structure -// -struct I2CMSG { - Uint16 MsgStatus; // Word stating what state msg is in: - // I2C_MSGCMD_INACTIVE = do not send msg - // I2C_MSGCMD_BUSY = msg start has been sent, - // awaiting stop - // I2C_MSGCMD_SEND_WITHSTOP = command to send - // master trans msg complete with a stop bit - // I2C_MSGCMD_SEND_NOSTOP = command to send - // master trans msg without the stop bit - // I2C_MSGCMD_RESTART = command to send a - // restart as a master receiver with a - // stop bit - Uint16 SlaveAddress; // I2C address of slave msg is intended for - Uint16 NumOfBytes; // Num of valid bytes in (or to be put - // in MsgBuffer) - Uint16 MemoryHighAddr; // EEPROM address of data associated with - // msg (high byte) - Uint16 MemoryLowAddr; // EEPROM address of data associated with - // msg (low byte) - Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that - // MAX_BUFFER_SIZE can be is 16 due - // to the FIFO's -}; - -#endif // end of F2837xD_I2C_DEFINES_H definition - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_defines.h deleted file mode 100644 index 404caee0b1..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_defines.h +++ /dev/null @@ -1,70 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Ipc_defines.h -// -// TITLE: F2837xD IPC support definitions -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_IPC_DEFINES_H -#define F2837xD_IPC_DEFINES_H - -// -// Defines -// -#define C1TOC2_MSG_RAM ((void *)0x3FC00) -#define C2TOC1_MSG_RAM ((void *)0x3F800) - -#if defined(CPU1) - #define SEND_MSG_RAM C1TOC2_MSG_RAM - #define RECV_MSG_RAM C2TOC1_MSG_RAM -#elif defined(CPU2) - #define SEND_MSG_RAM C2TOC1_MSG_RAM - #define RECV_MSG_RAM C1TOC2_MSG_RAM -#endif -#define MSG_RAM_SIZE 0x400 - -// -//Used with SendIpcData() and SendIpcCommand() to avoid setting a flag -// -#define NO_IPC_FLAG 32 - -#endif // end of F2837xD_IPC_DEFINES_H definition - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_drivers.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_drivers.h deleted file mode 100644 index 648ad6a83a..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_drivers.h +++ /dev/null @@ -1,511 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Ipc_drivers.h -// -// TITLE: Defines and Macros for the IPC Controller -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -//! \addtogroup ipc_driver_api -//! @{ -// - -#ifndef F2837xD_IPC_DRIVERS_H -#define F2837xD_IPC_DRIVERS_H - -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -#ifdef __cplusplus -extern "C" { -#endif - -// -// Included Files -// -#include "F2837xD_device.h" - -// -// Defines -// - -// -// The following are values that are used to define the maximum size of the -// global circular buffer variables g_asIPCCPU1toCPU2Buffers and -// g_asIPCCPU2toCPU1Buffers. They are also used in the IpcPut() and IpcGet() -// functions. IPC_BUFFER_SIZE and NUM_IPC_INTERRUPTS are user-configurable. -// -#define IPC_BUFFER_SIZE 4 // # of tIpcMessage messages in - // circular buffer - // (must be interval of 2) -#define NUM_IPC_INTERRUPTS 4 // # of IPC interrupts using circular - // buffer - // (must be same number on both CPUs -#define MAX_BUFFER_INDEX IPC_BUFFER_SIZE - 1 - -// -// The following are values that can be passed to IPCInitialize() -// as the usCPU1IpcInterrupt and usCPU2IpcInterrupt parameters -// -#define IPC_INT0 0x0001 -#define IPC_INT1 0x0002 -#define IPC_INT2 0x0003 -#define IPC_INT3 0x0004 - -// -// The following are values that are returned from all of the IPCCtoM command -// functions to determine whether the command was successfully sent or not. -// -#define STATUS_FAIL 0x0001 -#define STATUS_PASS 0x0000 - -// -// The following are values that can be passed to IPCReqMemAccess() as -// usMaster parameter to determine which processor to give master access to -// GSx blocks. -// -#define IPC_GSX_CPU1_MASTER 0x0001 -#define IPC_GSX_CPU2_MASTER 0x0000 - -// -// The following are values that can be passed to all IPC CPU1 to CPU2 or -// CPU2 to CPU1 command functions as bBlock parameter to determine whether to -// wait/block until a slot in PutBuffer is available if it is full, or to exit -// with a failure status. -// -#define ENABLE_BLOCKING 0x0001 -#define DISABLE_BLOCKING 0x0000 - -// -// The following are values that can be passed to IPCCtoMDataRead(), -// IPCCCtoMSetBits(),IPCCCtoMSetBits_Protected(), IPCCCtoMClearBits(), -// IPCCCtoMClearBits_Protected(), IPCCCtoMDataWrite(), -// IPCCtoMDataWrite_Protected() -// as usLength parameter to determine whether command applies to 16- or 32-bit -// data word. -// -#define IPC_LENGTH_16_BITS 0x00000001 -#define IPC_LENGTH_32_BITS 0x00000002 - -// -// The following are values that can be passed to IPCReqMemAccess() as -// ulMask parameter to configure GSxMSEL_REG register for master access to Sx -// RAM block. -// -#define GS0_ACCESS 0x00000001 // Master Access to GS0 -#define GS1_ACCESS 0x00000002 // Master Access to GS1 -#define GS2_ACCESS 0x00000004 // Master Access to GS2 -#define GS3_ACCESS 0x00000008 // Master Access to GS3 -#define GS4_ACCESS 0x00000010 // Master Access to GS4 -#define GS5_ACCESS 0x00000020 // Master Access to GS5 -#define GS6_ACCESS 0x00000040 // Master Access to GS6 -#define GS7_ACCESS 0x00000080 // Master Access to GS7 -#define GS8_ACCESS 0x00000100 // Master Access to GS8 -#define GS9_ACCESS 0x00000200 // Master Access to GS9 -#define GS10_ACCESS 0x00000400 // Master Access to GS10 -#define GS11_ACCESS 0x00000800 // Master Access to GS11 -#define GS12_ACCESS 0x00001000 // Master Access to GS12 -#define GS13_ACCESS 0x00002000 // Master Access to GS13 -#define GS14_ACCESS 0x00004000 // Master Access to GS14 -#define GS15_ACCESS 0x00008000 // Master Access to GS15 - -// -// The following are values that can be passed to IPCCtoMTaskBusy() as the -// ulFlags parameter. -// IPC_FLAG17 - IPC_FLAG32 can also be passed to IPCtoMDataRead() and -// IPCCtoMReadBlock() as the ulResponseFlag parameter. -// -#define NO_FLAG 0x00000000 // NO FLAG -#define IPC_FLAG0 0x00000001 // IPC FLAG 0 -#define IPC_FLAG1 0x00000002 // IPC FLAG 1 -#define IPC_FLAG2 0x00000004 // IPC FLAG 2 -#define IPC_FLAG3 0x00000008 // IPC FLAG 3 -#define IPC_FLAG4 0x00000010 // IPC FLAG 4 -#define IPC_FLAG5 0x00000020 // IPC FLAG 5 -#define IPC_FLAG6 0x00000040 // IPC FLAG 6 -#define IPC_FLAG7 0x00000080 // IPC FLAG 7 -#define IPC_FLAG8 0x00000100 // IPC FLAG 8 -#define IPC_FLAG9 0x00000200 // IPC FLAG 9 -#define IPC_FLAG10 0x00000400 // IPC FLAG 10 -#define IPC_FLAG11 0x00000800 // IPC FLAG 11 -#define IPC_FLAG12 0x00001000 // IPC FLAG 12 -#define IPC_FLAG13 0x00002000 // IPC FLAG 13 -#define IPC_FLAG14 0x00004000 // IPC FLAG 14 -#define IPC_FLAG15 0x00008000 // IPC FLAG 15 -#define IPC_FLAG16 0x00010000 // IPC FLAG 16 -#define IPC_FLAG17 0x00020000 // IPC FLAG 17 -#define IPC_FLAG18 0x00040000 // IPC FLAG 18 -#define IPC_FLAG19 0x00080000 // IPC FLAG 19 -#define IPC_FLAG20 0x00100000 // IPC FLAG 20 -#define IPC_FLAG21 0x00200000 // IPC FLAG 21 -#define IPC_FLAG22 0x00400000 // IPC FLAG 22 -#define IPC_FLAG23 0x00800000 // IPC FLAG 23 -#define IPC_FLAG24 0x01000000 // IPC FLAG 24 -#define IPC_FLAG25 0x02000000 // IPC FLAG 25 -#define IPC_FLAG26 0x04000000 // IPC FLAG 26 -#define IPC_FLAG27 0x08000000 // IPC FLAG 27 -#define IPC_FLAG28 0x10000000 // IPC FLAG 28 -#define IPC_FLAG29 0x20000000 // IPC FLAG 29 -#define IPC_FLAG30 0x40000000 // IPC FLAG 30 -#define IPC_FLAG31 0x80000000 // IPC FLAG 31 - -// -// The following are values that are used by all command functions and passed -// between processors in tIpcMessage.ulmessage or in the xTOyIPCCOM register -// to determine what command is requested by the sending processor. -// -#define IPC_SET_BITS_16 0x00000001 // Used for IPC-Lite -#define IPC_SET_BITS_32 0x00000002 // Used for IPC-Lite -#define IPC_CLEAR_BITS_16 0x00000003 // Used for IPC-Lite -#define IPC_CLEAR_BITS_32 0x00000004 // Used for IPC-Lite -#define IPC_DATA_WRITE_16 0x00000005 // Used for IPC-Lite -#define IPC_DATA_WRITE_32 0x00000006 // Used for IPC-Lite -#define IPC_DATA_READ_16 0x00000007 // Used for Boot ROM -#define IPC_DATA_READ_32 0x00000008 // Used for Boot ROM -#define IPC_DATA_READ 0x00000008 -#define IPC_SET_BITS_16_PROTECTED 0x00000009 // Used for IPC-Lite -#define IPC_SET_BITS_32_PROTECTED 0x0000000A // Used for IPC-Lite -#define IPC_CLEAR_BITS_16_PROTECTED 0x0000000B // Used for IPC-Lite -#define IPC_CLEAR_BITS_32_PROTECTED 0x0000000C // Used for IPC-Lite -#define IPC_DATA_WRITE_16_PROTECTED 0x0000000D // Used for IPC-Lite -#define IPC_DATA_WRITE_32_PROTECTED 0x0000000E // Used for IPC-Lite - -// -// 0x0000000F and 0x0000010 are reserved by boot ROM -// - -#define IPC_BRANCH 0x00000011 -#define IPC_FUNC_CALL 0x00000012 -#define IPC_MTOC_EXECUTE_BOOTMODE_CMD 0x00000013 - -#define IPC_SET_BITS 0x00010001 -#define IPC_CLEAR_BITS 0x00010002 -#define IPC_DATA_WRITE 0x00010003 -#define IPC_BLOCK_READ 0x00010004 -#define IPC_BLOCK_WRITE 0x00010005 -#define IPC_DATA_READ_PROTECTED 0x00010007 -#define IPC_SET_BITS_PROTECTED 0x00010008 -#define IPC_CLEAR_BITS_PROTECTED 0x00010009 -#define IPC_DATA_WRITE_PROTECTED 0x0001000A -#define IPC_BLOCK_WRITE_PROTECTED 0x0001000B - -// -// The following are values that can be passed into the -// IPCBootControlSystem() function in the ulBootMode parameter. -// -#define BROM_IPC_EXECUTE_BOOTMODE_CMD 0x00000013 - -// -// Below are the values programmed into IPCBOOTMODE register -// -#define C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL 0x00000000 -#define C1C2_BROM_BOOTMODE_BOOT_FROM_SCI 0x00000001 -#define C1C2_BROM_BOOTMODE_BOOT_FROM_SPI 0x00000004 -#define C1C2_BROM_BOOTMODE_BOOT_FROM_I2C 0x00000005 -#define C1C2_BROM_BOOTMODE_BOOT_FROM_CAN 0x00000007 -#define C1C2_BROM_BOOTMODE_BOOT_FROM_RAM 0x0000000A -#define C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH 0x0000000B - -// -// The following value is used by the -// IPCBootControlSystem() function to limit the allowed boot mode values. -// -#define C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE 0x0000000C - -// -// The following values report on the CPU02 boot ROM status at all times while -// the CPU02 is booting, and will reside in IPCBOOTSTS[11:0]. -// - -// -// CPU02 has not filled in a valid value yet -// -#define C2_BOOTROM_BOOTSTS_C2TOC1_IGNORE 0x00000000 - -// -// CPU02 has started to boot, but not completed -// the boot process yet -// -#define C2_BOOTROM_BOOTSTS_SYSTEM_START_BOOT 0x00000001 - -// -// CPU02 has completed the boot and is ready for -// CPU01 TO CPU02 IPC commands -// -#define C2_BOOTROM_BOOTSTS_SYSTEM_READY 0x00000002 - -// -// CPU02 ACKs the command in CPU01 TO CPU01 -// BOOTMODE register -// -#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK 0x00000003 - -// -// CPU02 un-supported command in CPU01 TO CPU01 -// BOOTMODE register -// -#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_NOT_SUPPORTED 0x00000004 - -// -// CPU2 NAKs the current boot command in -// CPU01 TO CPU01 BOOTMODE register -// -#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_BUSY_WITH_BOOT 0x00000005 - -// -//! A structure that defines an IPC message. These fields are used by the -//! IPC drivers to determine handling of data passed between processors. -//! Although they have a defined naming scheme, they can also be used -//! generically -//! to pass 32-bit data words between processors. -// -typedef struct -{ - //! The command passed between processor systems. - uint32_t ulcommand; - - //! The receiving processor address the command is requesting action on. - uint32_t uladdress; - - //! A 32-bit variable, the usage of which is determined by ulcommand. - //! The most common usage is to pass length requirements - //! with the upper 16-bits storing a Response Flag for read commands. - uint32_t uldataw1; - - //! A 32-bit variable, the usage of which is determined by ulcommand. - //! For block transfers, this variable is generally the address in - //! shared memory used to pass data between processors. - uint32_t uldataw2; - -} tIpcMessage; - -// -//! A structure that defines an IPC control instance. These -//! fields are used by the IPC drivers, and normally it is not necessary for -//! user software to directly read or write fields in the table. -// -typedef struct -{ - //! The address of the PutBuffer IPC message (in MSGRAM) - tIpcMessage *psPutBuffer; - - //! The IPC INT flag to set when sending messages - //! for this IPC controller instance. - uint32_t ulPutFlag; - - //! The address of the PutBuffer Write index (in MSGRAM) - uint16_t *pusPutWriteIndex; - - //! The address of the PutBuffer Read index (in MSGRAM) - uint16_t *pusPutReadIndex; - - //! The address of the GetBuffer IPC message(in MSGRAM) - tIpcMessage *psGetBuffer; - - //! The address of the GetBuffer Write Index (in MSGRAM) - uint16_t *pusGetWriteIndex; - - //! The address of the GetBuffer Read Index (in MSGRAM) - uint16_t *pusGetReadIndex; - -} tIpcController; - -// -// A type definition for the IPC function call command. -// -typedef uint32_t (*tfIpcFuncCall)(uint32_t ulParam); - -// -// Prototypes for Circular Buffers -// -extern tIpcMessage g_asIPCCPU1toCPU2Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE]; -extern tIpcMessage g_asIPCCPU2toCPU1Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE]; - -// -// Function Prototypes -// -extern void IPCInitialize (volatile tIpcController *psController, - uint16_t usCPU2IpcInterrupt, - uint16_t usCPU1IpcInterrupt); -extern uint16_t IpcPut (volatile tIpcController *psController, - tIpcMessage *psMessage, - uint16_t bBlock); -extern uint16_t IpcGet (volatile tIpcController *psController, - tIpcMessage *psMessage, - uint16_t bBlock); -extern uint16_t IPCLtoRDataRead (volatile tIpcController *psController, - uint32_t ulAddress, void *pvData, - uint16_t usLength, uint16_t bBlock, - uint32_t ulResponseFlag); -extern uint16_t IPCLtoRDataRead_Protected (volatile tIpcController *psController, - uint32_t ulAddress, void *pvData, - uint16_t usLength, uint16_t bBlock, - uint32_t ulResponseFlag); -extern uint16_t IPCLtoRSetBits(volatile tIpcController *psController, - uint32_t ulAddress, uint32_t ulMask, - uint16_t usLength,uint16_t bBlock); -extern uint16_t IPCLtoRSetBits_Protected(volatile tIpcController *psController, - uint32_t ulAddress, uint32_t ulMask, - uint16_t usLength, uint16_t bBlock); -extern uint16_t IPCLtoRClearBits(volatile tIpcController *psController, - uint32_t ulAddress, uint32_t ulMask, - uint16_t usLength,uint16_t bBlock); -extern uint16_t IPCLtoRClearBits_Protected(volatile tIpcController *psController, - uint32_t ulAddress, uint32_t ulMask, - uint16_t usLength, uint16_t bBlock); -extern uint16_t IPCLtoRDataWrite(volatile tIpcController *psController, - uint32_t ulAddress, uint32_t ulData, - uint16_t usLength, uint16_t bBlock, - uint32_t ulResponseFlag); -extern uint16_t IPCLtoRDataWrite_Protected(volatile tIpcController *psController, - uint32_t ulAddress, uint32_t ulData, - uint16_t usLength, uint16_t bBlock, - uint32_t ulResponseFlag); -extern uint16_t IPCLtoRBlockRead(volatile tIpcController *psController, - uint32_t ulAddress, uint32_t ulShareAddress, - uint16_t usLength, uint16_t bBlock, - uint32_t ulResponseFlag); -extern uint16_t IPCLtoRBlockWrite(volatile tIpcController *psController, - uint32_t ulAddress, uint32_t ulShareAddress, - uint16_t usLength, uint16_t usWordLength, - uint16_t bBlock); -extern uint16_t IPCLtoRBlockWrite_Protected(volatile tIpcController *psController, - uint32_t ulAddress, - uint32_t ulShareAddress, - uint16_t usLength, - uint16_t usWordLength, - uint16_t bBlock); -extern uint16_t IPCLtoRFunctionCall(volatile tIpcController *psController, - uint32_t ulAddress, uint32_t ulParam, - uint16_t bBlock); -extern uint16_t IPCLtoRSendMessage(volatile tIpcController *psController, - uint32_t ulCommand, uint32_t ulAddress, - uint32_t ulDataW1, uint32_t ulDataW2, - uint16_t bBlock); -#if defined (CPU2) -uint16_t -IPCReqMemAccess (volatile tIpcController *psController, uint32_t ulMask, - uint16_t usMaster, uint16_t bBlock); -#endif - -extern void IPCRtoLDataWrite(tIpcMessage *psMessage); -extern void IPCRtoLDataWrite_Protected(tIpcMessage *psMessage); -extern void IPCRtoLDataRead(volatile tIpcController *psController, - tIpcMessage *psMessage, uint16_t bBlock); -extern void IPCRtoLDataRead_Protected(volatile tIpcController *psController, - tIpcMessage *psMessage,uint16_t bBlock); -extern void IPCRtoLSetBits(tIpcMessage *psMessage); -extern void IPCRtoLSetBits_Protected(tIpcMessage *psMessage); -extern void IPCRtoLClearBits(tIpcMessage *psMessage); -extern void IPCRtoLClearBits_Protected(tIpcMessage *psMessage); -extern void IPCRtoLBlockRead(tIpcMessage *psMessage); -extern void IPCRtoLBlockWrite(tIpcMessage *psMessage); -extern void IPCRtoLBlockWrite_Protected(tIpcMessage *psMessage); -extern void IPCRtoLFunctionCall(tIpcMessage *psMessage); - -// -// IPC Lite Driver Prototype Definitions -// -extern uint16_t IPCLiteLtoRGetResult (void *pvData, uint16_t usLength, - uint32_t ulStatusFlag); -extern uint16_t IPCLiteLtoRDataRead(uint32_t ulFlag, uint32_t ulAddress, - uint16_t usLength, uint32_t ulStatusFlag); -extern uint16_t IPCLiteLtoRSetBits(uint32_t ulFlag, uint32_t ulAddress, - uint32_t ulMask, uint16_t usLength, - uint32_t ulStatusFlag); -extern uint16_t IPCLiteLtoRSetBits_Protected (uint32_t ulFlag, - uint32_t ulAddress, - uint32_t ulMask, - uint16_t usLength, - uint32_t ulStatusFlag); -extern uint16_t IPCLiteLtoRClearBits(uint32_t ulFlag, uint32_t ulAddress, - uint32_t ulMask, uint16_t usLength, - uint32_t ulStatusFlag); -extern uint16_t IPCLiteLtoRClearBits_Protected (uint32_t ulFlag, - uint32_t ulAddress, - uint32_t ulMask, - uint16_t usLength, - uint32_t ulStatusFlag); -extern uint16_t IPCLiteLtoRDataWrite(uint32_t ulFlag, uint32_t ulAddress, - uint32_t ulData, uint16_t usLength, - uint32_t ulStatusFlag); -extern uint16_t IPCLiteLtoRDataWrite_Protected(uint32_t ulFlag, - uint32_t ulAddress, - uint32_t ulData, - uint16_t usLength, - uint32_t ulStatusFlag); -extern uint16_t IPCLiteLtoRFunctionCall(uint32_t ulFlag, uint32_t ulAddress, - uint32_t ulParam, uint32_t ulStatusFlag); -extern uint16_t IPCLiteReqMemAccess (uint32_t ulFlag, uint32_t ulMask, - uint16_t ulMaster, uint32_t ulStatusFlag); -extern void IPCLiteRtoLDataRead(uint32_t ulFlag, uint32_t ulStatusFlag); -extern void IPCLiteRtoLSetBits(uint32_t ulFlag, uint32_t ulStatusFlag); -extern void IPCLiteRtoLSetBits_Protected (uint32_t ulFlag, uint32_t ulStatusFlag); -extern void IPCLiteRtoLClearBits(uint32_t ulFlag, uint32_t ulStatusFlag); -extern void IPCLiteRtoLClearBits_Protected (uint32_t ulFlag, - uint32_t ulStatusFlag); -extern void IPCLiteRtoLDataWrite(uint32_t ulFlag, uint32_t ulStatusFlag); -extern void IPCLiteRtoLDataWrite_Protected(uint32_t ulFlag, - uint32_t ulStatusFlag); -extern void IPCLiteRtoLFunctionCall(uint32_t ulFlag, uint32_t ulStatusFlag); - -// -// IPC Utility Driver Prototype Definitions -// -extern void IPCRtoLFlagAcknowledge (uint32_t ulFlags); -extern Uint16 IPCRtoLFlagBusy (uint32_t ulFlags); -extern Uint16 IPCLtoRFlagBusy (uint32_t ulFlags); -extern void IPCLtoRFlagSet (uint32_t ulFlags); -extern void IPCLtoRFlagClear (uint32_t ulFlags); -extern uint32_t IPCGetBootStatus (void); -extern uint16_t IPCBootCPU2(uint32_t ulBootMode); -#ifdef __cplusplus -} -#endif /* extern "C" */ - -// -// Close the Doxygen group. -//! @} -// - -#endif // end of F2837xD_IPC_DRIVERS_H definition - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Pie_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Pie_defines.h deleted file mode 100644 index 1905d88ca8..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Pie_defines.h +++ /dev/null @@ -1,74 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Pie_defines.h -// -// TITLE: #defines used in PIE examples -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_PIE_DEFINES_H -#define F2837xD_PIE_DEFINES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// -#define PIEACK_GROUP1 0x0001 -#define PIEACK_GROUP2 0x0002 -#define PIEACK_GROUP3 0x0004 -#define PIEACK_GROUP4 0x0008 -#define PIEACK_GROUP5 0x0010 -#define PIEACK_GROUP6 0x0020 -#define PIEACK_GROUP7 0x0040 -#define PIEACK_GROUP8 0x0080 -#define PIEACK_GROUP9 0x0100 -#define PIEACK_GROUP10 0x0200 -#define PIEACK_GROUP11 0x0400 -#define PIEACK_GROUP12 0x0800 - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F2837xD_PIE_DEFINES_H - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_SWPrioritizedIsrLevels.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_SWPrioritizedIsrLevels.h deleted file mode 100644 index 6fd2700965..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_SWPrioritizedIsrLevels.h +++ /dev/null @@ -1,20681 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_SWPrioritizedIsrLevels.h -// -// TITLE: F28 Devices Software Prioritized Interrupt Service Routine -// Level definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_SW_PRIORITZIED_ISR_H -#define F2837xD_SW_PRIORITZIED_ISR_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Interrupt Enable Register Allocation For F2837xD Devices: -// -// Interrupts can be enabled/disabled using the CPU interrupt enable register -// (IER) and the PIE interrupt enable registers (PIEIER1 to PIEIER12). -// -// -// Set "Global" Interrupt Priority Level (IER register): -// -// The user must set the appropriate priority level for each of the CPU -// interrupts. This is termed as the "global" priority. The priority level -// must be a number between 1 (highest) to 16 (lowest). A value of 0 must -// be entered for reserved interrupts or interrupts that are not used. This -// will also reduce code size by not including ISR's that are not used. -// -// Note: The priority levels below are used to calculate the IER register -// interrupt masks MINT1 to MINT16. -// -// -// Note: The priority levels shown here may not make sense in a -// real application. This is for demonstration purposes only!!! -// -// The user should change these to values that make sense for -// their application. -// -// 0 = not used -// 1 = highest priority -// ... -// 16 = lowest priority -// -#define INT1PL 2 // Group1 Interrupts (PIEIER1) -#define INT2PL 1 // Group2 Interrupts (PIEIER2) -#define INT3PL 4 // Group3 Interrupts (PIEIER3) -#define INT4PL 2 // Group4 Interrupts (PIEIER4) -#define INT5PL 2 // Group5 Interrupts (PIEIER5) -#define INT6PL 3 // Group6 Interrupts (PIEIER6) -#define INT7PL 5 // Group7 Interrupts (PIEIER6) -#define INT8PL 5 // Group8 Interrupts (PIEIER6) -#define INT9PL 3 // Group9 Interrupts (PIEIER9) -#define INT10PL 6 // Group10 Interrupts (PIEIER6) -#define INT11PL 6 // Group11 Interrupts (PIEIER6) -#define INT12PL 8 // Group12 Interrupts (PIEIER6) -#define INT13PL 4 // XINT13 -#define INT14PL 4 // INT14 (TINT2) -#define INT15PL 4 // DATALOG -#define INT16PL 4 // RTOSINT - -// -// Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers): -// -// The user must set the appropriate priority level for each of the PIE -// interrupts. This is termed as the "group" priority. The priority level -// must be a number between 1 (highest) to 16 (lowest). A value of 0 must -// be entered for reserved interrupts or interrupts that are not used. This -// will also reduce code size by not including ISR's that are not used: -// -// Note: The priority levels below are used to calculate the following -// PIEIER register interrupt masks: -// MG1_1 to MG1_16 -// MG2_1 to MG2_16 -// MG3_1 to MG3_16 -// MG4_1 to MG4_16 -// MG5_1 to MG5_16 -// MG6_1 to MG6_16 -// MG7_1 to MG7_16 -// MG8_1 to MG8_16 -// MG9_1 to MG9_16 -// MG10_1 to MG10_16 -// MG11_1 to MG11_16 -// MG12_1 to MG12_16 -// -// Note: The priority levels shown here may not make sense in a -// real application. This is for demonstration purposes only!!! -// -// The user should change these to values that make sense for -// their application. -// -// 0 = not used -// 1 = highest priority -// ... -// 16 = lowest priority -// -#define G1_1PL 5 // ADCA1_INT -#define G1_2PL 3 // ADCB1_INT -#define G1_3PL 1 // ADCC1_INT -#define G1_4PL 4 // XINT1_INT -#define G1_5PL 4 // XINT2_INT -#define G1_6PL 1 // ADCD1_INT -#define G1_7PL 12 // TIMER0_INT -#define G1_8PL 5 // WAKE_INT -#define G1_9PL 0 // Reserved -#define G1_10PL 0 // Reserved -#define G1_11PL 0 // Reserved -#define G1_12PL 0 // Reserved -#define G1_13PL 8 // IPC1_INT -#define G1_14PL 13 // IPC2_INT -#define G1_15PL 15 // IPC3_INT -#define G1_16PL 9 // IPC4_INT - -#define G2_1PL 13 // EPWM1_TZ_INT -#define G2_2PL 1 // EPWM2_TZ_INT -#define G2_3PL 1 // EPWM3_TZ_INT -#define G2_4PL 9 // EPWM4_TZ_INT -#define G2_5PL 3 // EPWM5_TZ_INT -#define G2_6PL 13 // EPWM6_TZ_INT -#define G2_7PL 9 // EPWM7_TZ_INT -#define G2_8PL 13 // EPWM8_TZ_INT -#define G2_9PL 15 // EPWM9_TZ_INT -#define G2_10PL 11 // EPWM10_TZ_INT -#define G2_11PL 7 // EPWM11_TZ_INT -#define G2_12PL 10 // EPWM12_TZ_INT -#define G2_13PL 0 // Reserved -#define G2_14PL 0 // Reserved -#define G2_15PL 0 // Reserved -#define G2_16PL 0 // Reserved - -#define G3_1PL 5 // EPWM1_INT -#define G3_2PL 9 // EPWM2_INT -#define G3_3PL 5 // EPWM3_INT -#define G3_4PL 2 // EPWM4_INT -#define G3_5PL 12 // EPWM5_INT -#define G3_6PL 4 // EPWM6_INT -#define G3_7PL 2 // EPWM7_INT -#define G3_8PL 13 // EPWM8_INT -#define G3_9PL 4 // EPWM9_INT -#define G3_10PL 12 // EPWM10_INT -#define G3_11PL 4 // EPWM11_INT -#define G3_12PL 14 // EPWM12_INT -#define G3_13PL 0 // Reserved -#define G3_14PL 0 // Reserved -#define G3_15PL 0 // Reserved -#define G3_16PL 0 // Reserved - -#define G4_1PL 3 // ECAP1_INT -#define G4_2PL 3 // ECAP2_INT -#define G4_3PL 3 // ECAP3_INT -#define G4_4PL 6 // ECAP4_INT -#define G4_5PL 7 // ECAP5_INT -#define G4_6PL 7 // ECAP6_INT -#define G4_7PL 0 // Reserved -#define G4_8PL 0 // Reserved -#define G4_9PL 0 // Reserved -#define G4_10PL 0 // Reserved -#define G4_11PL 0 // Reserved -#define G4_12PL 0 // Reserved -#define G4_13PL 0 // Reserved -#define G4_14PL 0 // Reserved -#define G4_15PL 0 // Reserved -#define G4_16PL 0 // Reserved - -#define G5_1PL 6 // EQEP1_INT -#define G5_2PL 5 // EQEP2_INT -#define G5_3PL 5 // EQEP3_INT -#define G5_4PL 1 // Reserved -#define G5_5PL 9 // CLB1_INT -#define G5_6PL 10 // CLB2_INT -#define G5_7PL 15 // CLB3_INT -#define G5_8PL 13 // CLB4_INT -#define G5_9PL 12 // SD1_INT -#define G5_10PL 9 // SD2_INT -#define G5_11PL 0 // Reserved -#define G5_12PL 0 // Reserved -#define G5_13PL 0 // Reserved -#define G5_14PL 0 // Reserved -#define G5_15PL 0 // Reserved -#define G5_16PL 0 // Reserved - -#define G6_1PL 1 // SPIA_RX_INT -#define G6_2PL 7 // SPIA_TX_INT -#define G6_3PL 3 // SPIB_RX_INT -#define G6_4PL 3 // SPIB_TX_INT -#define G6_5PL 10 // MCBSPA_RX_INT -#define G6_6PL 7 // MCBSPA_TX_INT -#define G6_7PL 6 // MCBSPB_RX_INT -#define G6_8PL 13 // MCBSPB_TX_INT -#define G6_9PL 14 // SPIC_RX_INT -#define G6_10PL 3 // SPIC_TX_INT -#define G6_11PL 0 // Reserved -#define G6_12PL 0 // Reserved -#define G6_13PL 0 // Reserved -#define G6_14PL 0 // Reserved -#define G6_15PL 0 // Reserved -#define G6_16PL 0 // Reserved - -#define G7_1PL 1 // DMA_CH1_INT -#define G7_2PL 11 // DMA_CH2_INT -#define G7_3PL 14 // DMA_CH3_INT -#define G7_4PL 3 // DMA_CH4_INT -#define G7_5PL 13 // DMA_CH5_INT -#define G7_6PL 14 // DMA_CH6_INT -#define G7_7PL 0 // Reserved -#define G7_8PL 0 // Reserved -#define G7_9PL 0 // Reserved -#define G7_10PL 0 // Reserved -#define G7_11PL 0 // Reserved -#define G7_12PL 0 // Reserved -#define G7_13PL 0 // Reserved -#define G7_14PL 0 // Reserved -#define G7_15PL 0 // Reserved -#define G7_16PL 0 // Reserved - -#define G8_1PL 14 // I2CA_INT -#define G8_2PL 10 // I2CA_FIFO_INT -#define G8_3PL 11 // I2CB_INT -#define G8_4PL 9 // I2CB_FIFO_INT -#define G8_5PL 12 // SCIC_RX_INT -#define G8_6PL 2 // SCIC_TX_INT -#define G8_7PL 8 // SCID_RX_INT -#define G8_8PL 7 // SCID_TX_INT -#define G8_9PL 0 // Reserved -#define G8_10PL 0 // Reserved -#define G8_11PL 0 // Reserved -#define G8_12PL 0 // Reserved -#define G8_13PL 0 // Reserved -#define G8_14PL 0 // Reserved -#define G8_15PL 1 // UPPA_INT -#define G8_16PL 0 // Reserved - -#define G9_1PL 12 // SCIA_RX_INT -#define G9_2PL 14 // SCIA_TX_INT -#define G9_3PL 11 // SCIB_RX_INT -#define G9_4PL 6 // SCIB_TX_INT -#define G9_5PL 14 // CANA0_INT -#define G9_6PL 10 // CANA1_INT -#define G9_7PL 10 // CANB0_INT -#define G9_8PL 5 // CANB1_INT -#define G9_9PL 0 // Reserved -#define G9_10PL 0 // Reserved -#define G9_11PL 0 // Reserved -#define G9_12PL 0 // Reserved -#define G9_13PL 0 // Reserved -#define G9_14PL 0 // Reserved -#define G9_15PL 12 // USBA_INT -#define G9_16PL 0 // Reserved - -#define G10_1PL 14 // ADCA_EVT_INT -#define G10_2PL 3 // ADCA2_INT -#define G10_3PL 1 // ADCA3_INT -#define G10_4PL 12 // ADCA4_INT -#define G10_5PL 5 // ADCB_EVT_INT -#define G10_6PL 11 // ADCB2_INT -#define G10_7PL 12 // ADCB3_INT -#define G10_8PL 13 // ADCB4_INT -#define G10_9PL 7 // ADCC_EVT_INT -#define G10_10PL 8 // ADCC2_INT -#define G10_11PL 4 // ADCC3_INT -#define G10_12PL 9 // ADCC4_INT -#define G10_13PL 2 // ADCD_EVT_INT -#define G10_14PL 10 // ADCD2_INT -#define G10_15PL 11 // ADCD3_INT -#define G10_16PL 5 // ADCD4_INT - -#define G11_1PL 9 // CLA1_1_INT -#define G11_2PL 6 // CLA1_2_INT -#define G11_3PL 9 // CLA1_3_INT -#define G11_4PL 9 // CLA1_4_INT -#define G11_5PL 6 // CLA1_5_INT -#define G11_6PL 13 // CLA1_6_INT -#define G11_7PL 10 // CLA1_7_INT -#define G11_8PL 15 // CLA1_8_INT -#define G11_9PL 0 // Reserved -#define G11_10PL 0 // Reserved -#define G11_11PL 0 // Reserved -#define G11_12PL 0 // Reserved -#define G11_13PL 0 // Reserved -#define G11_14PL 0 // Reserved -#define G11_15PL 0 // Reserved -#define G11_16PL 0 // Reserved - -#define G12_1PL 3 // XINT3_INT -#define G12_2PL 6 // XINT4_INT -#define G12_3PL 10 // XINT5_INT -#define G12_4PL 5 // Reserved -#define G12_5PL 2 // FMC_INT -#define G12_6PL 11 // VCU_INT -#define G12_7PL 14 // FPU_OVERFLOW_ISR -#define G12_8PL 14 // FPU_UNDERFLOW_ISR -#define G12_9PL 6 // EMIF_ERROR_ISR -#define G12_10PL 5 // RAM_CORRECTABLE_ERROR_ISR -#define G12_11PL 4 // FLASH_CORRECTABLE_ERROR_ISR -#define G12_12PL 12 // RAM_ACCESS_VIOLATION_INT -#define G12_13PL 8 // SYS_PLL_SLIP_INT -#define G12_14PL 2 // AUX_PLL_SLIP_INT -#define G12_15PL 12 // CLA_UNDERFLOW_INT -#define G12_16PL 2 // CLA_OVERFLOW_INT - -// -// There should be no need to modify code below this line -// -// Automatically generate IER interrupt masks MINT1 to MINT16: -// -// Beginning of MINT1: -#if (INT1PL == 0) -#define MINT1_1PL ~(1 << 0) -#else -#define MINT1_1PL 0xFFFF -#endif - -#if (INT2PL >= INT1PL) || (INT2PL == 0) -#define MINT1_2PL ~(1 << 1) -#else -#define MINT1_2PL 0xFFFF -#endif - -#if (INT3PL >= INT1PL) || (INT3PL == 0) -#define MINT1_3PL ~(1 << 2) -#else -#define MINT1_3PL 0xFFFF -#endif - -#if (INT4PL >= INT1PL) || (INT4PL == 0) -#define MINT1_4PL ~(1 << 3) -#else -#define MINT1_4PL 0xFFFF -#endif - -#if (INT5PL >= INT1PL) || (INT5PL == 0) -#define MINT1_5PL ~(1 << 4) -#else -#define MINT1_5PL 0xFFFF -#endif - -#if (INT6PL >= INT1PL) || (INT6PL == 0) -#define MINT1_6PL ~(1 << 5) -#else -#define MINT1_6PL 0xFFFF -#endif - -#if (INT7PL >= INT1PL) || (INT7PL == 0) -#define MINT1_7PL ~(1 << 6) -#else -#define MINT1_7PL 0xFFFF -#endif - -#if (INT8PL >= INT1PL) || (INT8PL == 0) -#define MINT1_8PL ~(1 << 7) -#else -#define MINT1_8PL 0xFFFF -#endif - -#if (INT9PL >= INT1PL) || (INT9PL == 0) -#define MINT1_9PL ~(1 << 8) -#else -#define MINT1_9PL 0xFFFF -#endif - -#if (INT10PL >= INT1PL) || (INT10PL == 0) -#define MINT1_10PL ~(1 << 9) -#else -#define MINT1_10PL 0xFFFF -#endif - -#if (INT11PL >= INT1PL) || (INT11PL == 0) -#define MINT1_11PL ~(1 << 10) -#else -#define MINT1_11PL 0xFFFF -#endif - -#if (INT12PL >= INT1PL) || (INT12PL == 0) -#define MINT1_12PL ~(1 << 11) -#else -#define MINT1_12PL 0xFFFF -#endif - -#if (INT13PL >= INT1PL) || (INT13PL == 0) -#define MINT1_13PL ~(1 << 12) -#else -#define MINT1_13PL 0xFFFF -#endif - -#if (INT14PL >= INT1PL) || (INT14PL == 0) -#define MINT1_14PL ~(1 << 13) -#else -#define MINT1_14PL 0xFFFF -#endif - -#if (INT15PL >= INT1PL) || (INT15PL == 0) -#define MINT1_15PL ~(1 << 14) -#else -#define MINT1_15PL 0xFFFF -#endif - -#if (INT16PL >= INT1PL) || (INT16PL == 0) -#define MINT1_16PL ~(1 << 15) -#else -#define MINT1_16PL 0xFFFF -#endif - -#define MINT1 (MINT1_1PL & MINT1_2PL & MINT1_3PL & MINT1_4PL & \ - MINT1_5PL & MINT1_6PL & MINT1_7PL & MINT1_8PL & \ - MINT1_9PL & MINT1_10PL & MINT1_11PL & MINT1_12PL & \ - MINT1_13PL & MINT1_14PL & MINT1_15PL & MINT1_16PL) -// End Of MINT1. - -// Beginning of MINT2: -#if (INT1PL >= INT2PL) || (INT1PL == 0) -#define MINT2_1PL ~(1 << 0) -#else -#define MINT2_1PL 0xFFFF -#endif - -#if (INT2PL == 0) -#define MINT2_2PL ~(1 << 1) -#else -#define MINT2_2PL 0xFFFF -#endif - -#if (INT3PL >= INT2PL) || (INT3PL == 0) -#define MINT2_3PL ~(1 << 2) -#else -#define MINT2_3PL 0xFFFF -#endif - -#if (INT4PL >= INT2PL) || (INT4PL == 0) -#define MINT2_4PL ~(1 << 3) -#else -#define MINT2_4PL 0xFFFF -#endif - -#if (INT5PL >= INT2PL) || (INT5PL == 0) -#define MINT2_5PL ~(1 << 4) -#else -#define MINT2_5PL 0xFFFF -#endif - -#if (INT6PL >= INT2PL) || (INT6PL == 0) -#define MINT2_6PL ~(1 << 5) -#else -#define MINT2_6PL 0xFFFF -#endif - -#if (INT7PL >= INT2PL) || (INT7PL == 0) -#define MINT2_7PL ~(1 << 6) -#else -#define MINT2_7PL 0xFFFF -#endif - -#if (INT8PL >= INT2PL) || (INT8PL == 0) -#define MINT2_8PL ~(1 << 7) -#else -#define MINT2_8PL 0xFFFF -#endif - -#if (INT9PL >= INT2PL) || (INT9PL == 0) -#define MINT2_9PL ~(1 << 8) -#else -#define MINT2_9PL 0xFFFF -#endif - -#if (INT10PL >= INT2PL) || (INT10PL == 0) -#define MINT2_10PL ~(1 << 9) -#else -#define MINT2_10PL 0xFFFF -#endif - -#if (INT11PL >= INT2PL) || (INT11PL == 0) -#define MINT2_11PL ~(1 << 10) -#else -#define MINT2_11PL 0xFFFF -#endif - -#if (INT12PL >= INT2PL) || (INT12PL == 0) -#define MINT2_12PL ~(1 << 11) -#else -#define MINT2_12PL 0xFFFF -#endif - -#if (INT13PL >= INT2PL) || (INT13PL == 0) -#define MINT2_13PL ~(1 << 12) -#else -#define MINT2_13PL 0xFFFF -#endif - -#if (INT14PL >= INT2PL) || (INT14PL == 0) -#define MINT2_14PL ~(1 << 13) -#else -#define MINT2_14PL 0xFFFF -#endif - -#if (INT15PL >= INT2PL) || (INT15PL == 0) -#define MINT2_15PL ~(1 << 14) -#else -#define MINT2_15PL 0xFFFF -#endif - -#if (INT16PL >= INT2PL) || (INT16PL == 0) -#define MINT2_16PL ~(1 << 15) -#else -#define MINT2_16PL 0xFFFF -#endif - -#define MINT2 (MINT2_1PL & MINT2_2PL & MINT2_3PL & MINT2_4PL & \ - MINT2_5PL & MINT2_6PL & MINT2_7PL & MINT2_8PL & \ - MINT2_9PL & MINT2_10PL & MINT2_11PL & MINT2_12PL & \ - MINT2_13PL & MINT2_14PL & MINT2_15PL & MINT2_16PL) -// End Of MINT2. - -// Beginning of MINT3: -#if (INT1PL >= INT3PL) || (INT1PL == 0) -#define MINT3_1PL ~(1 << 0) -#else -#define MINT3_1PL 0xFFFF -#endif - -#if (INT2PL >= INT3PL) || (INT2PL == 0) -#define MINT3_2PL ~(1 << 1) -#else -#define MINT3_2PL 0xFFFF -#endif - -#if (INT3PL == 0) -#define MINT3_3PL ~(1 << 2) -#else -#define MINT3_3PL 0xFFFF -#endif - -#if (INT4PL >= INT3PL) || (INT4PL == 0) -#define MINT3_4PL ~(1 << 3) -#else -#define MINT3_4PL 0xFFFF -#endif - -#if (INT5PL >= INT3PL) || (INT5PL == 0) -#define MINT3_5PL ~(1 << 4) -#else -#define MINT3_5PL 0xFFFF -#endif - -#if (INT6PL >= INT3PL) || (INT6PL == 0) -#define MINT3_6PL ~(1 << 5) -#else -#define MINT3_6PL 0xFFFF -#endif - -#if (INT7PL >= INT3PL) || (INT7PL == 0) -#define MINT3_7PL ~(1 << 6) -#else -#define MINT3_7PL 0xFFFF -#endif - -#if (INT8PL >= INT3PL) || (INT8PL == 0) -#define MINT3_8PL ~(1 << 7) -#else -#define MINT3_8PL 0xFFFF -#endif - -#if (INT9PL >= INT3PL) || (INT9PL == 0) -#define MINT3_9PL ~(1 << 8) -#else -#define MINT3_9PL 0xFFFF -#endif - -#if (INT10PL >= INT3PL) || (INT10PL == 0) -#define MINT3_10PL ~(1 << 9) -#else -#define MINT3_10PL 0xFFFF -#endif - -#if (INT11PL >= INT3PL) || (INT11PL == 0) -#define MINT3_11PL ~(1 << 10) -#else -#define MINT3_11PL 0xFFFF -#endif - -#if (INT12PL >= INT3PL) || (INT12PL == 0) -#define MINT3_12PL ~(1 << 11) -#else -#define MINT3_12PL 0xFFFF -#endif - -#if (INT13PL >= INT3PL) || (INT13PL == 0) -#define MINT3_13PL ~(1 << 12) -#else -#define MINT3_13PL 0xFFFF -#endif - -#if (INT14PL >= INT3PL) || (INT14PL == 0) -#define MINT3_14PL ~(1 << 13) -#else -#define MINT3_14PL 0xFFFF -#endif - -#if (INT15PL >= INT3PL) || (INT15PL == 0) -#define MINT3_15PL ~(1 << 14) -#else -#define MINT3_15PL 0xFFFF -#endif - -#if (INT16PL >= INT3PL) || (INT16PL == 0) -#define MINT3_16PL ~(1 << 15) -#else -#define MINT3_16PL 0xFFFF -#endif - -#define MINT3 (MINT3_1PL & MINT3_2PL & MINT3_3PL & MINT3_4PL & \ - MINT3_5PL & MINT3_6PL & MINT3_7PL & MINT3_8PL & \ - MINT3_9PL & MINT3_10PL & MINT3_11PL & MINT3_12PL & \ - MINT3_13PL & MINT3_14PL & MINT3_15PL & MINT3_16PL) -// End Of MINT3. - -// Beginning of MINT4: -#if (INT1PL >= INT4PL) || (INT1PL == 0) -#define MINT4_1PL ~(1 << 0) -#else -#define MINT4_1PL 0xFFFF -#endif - -#if (INT2PL >= INT4PL) || (INT2PL == 0) -#define MINT4_2PL ~(1 << 1) -#else -#define MINT4_2PL 0xFFFF -#endif - -#if (INT3PL >= INT4PL) || (INT3PL == 0) -#define MINT4_3PL ~(1 << 2) -#else -#define MINT4_3PL 0xFFFF -#endif - -#if (INT4PL == 0) -#define MINT4_4PL ~(1 << 3) -#else -#define MINT4_4PL 0xFFFF -#endif - -#if (INT5PL >= INT4PL) || (INT5PL == 0) -#define MINT4_5PL ~(1 << 4) -#else -#define MINT4_5PL 0xFFFF -#endif - -#if (INT6PL >= INT4PL) || (INT6PL == 0) -#define MINT4_6PL ~(1 << 5) -#else -#define MINT4_6PL 0xFFFF -#endif - -#if (INT7PL >= INT4PL) || (INT7PL == 0) -#define MINT4_7PL ~(1 << 6) -#else -#define MINT4_7PL 0xFFFF -#endif - -#if (INT8PL >= INT4PL) || (INT8PL == 0) -#define MINT4_8PL ~(1 << 7) -#else -#define MINT4_8PL 0xFFFF -#endif - -#if (INT9PL >= INT4PL) || (INT9PL == 0) -#define MINT4_9PL ~(1 << 8) -#else -#define MINT4_9PL 0xFFFF -#endif - -#if (INT10PL >= INT4PL) || (INT10PL == 0) -#define MINT4_10PL ~(1 << 9) -#else -#define MINT4_10PL 0xFFFF -#endif - -#if (INT11PL >= INT4PL) || (INT11PL == 0) -#define MINT4_11PL ~(1 << 10) -#else -#define MINT4_11PL 0xFFFF -#endif - -#if (INT12PL >= INT4PL) || (INT12PL == 0) -#define MINT4_12PL ~(1 << 11) -#else -#define MINT4_12PL 0xFFFF -#endif - -#if (INT13PL >= INT4PL) || (INT13PL == 0) -#define MINT4_13PL ~(1 << 12) -#else -#define MINT4_13PL 0xFFFF -#endif - -#if (INT14PL >= INT4PL) || (INT14PL == 0) -#define MINT4_14PL ~(1 << 13) -#else -#define MINT4_14PL 0xFFFF -#endif - -#if (INT15PL >= INT4PL) || (INT15PL == 0) -#define MINT4_15PL ~(1 << 14) -#else -#define MINT4_15PL 0xFFFF -#endif - -#if (INT16PL >= INT4PL) || (INT16PL == 0) -#define MINT4_16PL ~(1 << 15) -#else -#define MINT4_16PL 0xFFFF -#endif - -#define MINT4 (MINT4_1PL & MINT4_2PL & MINT4_3PL & MINT4_4PL & \ - MINT4_5PL & MINT4_6PL & MINT4_7PL & MINT4_8PL & \ - MINT4_9PL & MINT4_10PL & MINT4_11PL & MINT4_12PL & \ - MINT4_13PL & MINT4_14PL & MINT4_15PL & MINT4_16PL) -// End Of MINT4. - -// Beginning of MINT5: -#if (INT1PL >= INT5PL) || (INT1PL == 0) -#define MINT5_1PL ~(1 << 0) -#else -#define MINT5_1PL 0xFFFF -#endif - -#if (INT2PL >= INT5PL) || (INT2PL == 0) -#define MINT5_2PL ~(1 << 1) -#else -#define MINT5_2PL 0xFFFF -#endif - -#if (INT3PL >= INT5PL) || (INT3PL == 0) -#define MINT5_3PL ~(1 << 2) -#else -#define MINT5_3PL 0xFFFF -#endif - -#if (INT4PL >= INT5PL) || (INT4PL == 0) -#define MINT5_4PL ~(1 << 3) -#else -#define MINT5_4PL 0xFFFF -#endif - -#if (INT5PL == 0) -#define MINT5_5PL ~(1 << 4) -#else -#define MINT5_5PL 0xFFFF -#endif - -#if (INT6PL >= INT5PL) || (INT6PL == 0) -#define MINT5_6PL ~(1 << 5) -#else -#define MINT5_6PL 0xFFFF -#endif - -#if (INT7PL >= INT5PL) || (INT7PL == 0) -#define MINT5_7PL ~(1 << 6) -#else -#define MINT5_7PL 0xFFFF -#endif - -#if (INT8PL >= INT5PL) || (INT8PL == 0) -#define MINT5_8PL ~(1 << 7) -#else -#define MINT5_8PL 0xFFFF -#endif - -#if (INT9PL >= INT5PL) || (INT9PL == 0) -#define MINT5_9PL ~(1 << 8) -#else -#define MINT5_9PL 0xFFFF -#endif - -#if (INT10PL >= INT5PL) || (INT10PL == 0) -#define MINT5_10PL ~(1 << 9) -#else -#define MINT5_10PL 0xFFFF -#endif - -#if (INT11PL >= INT5PL) || (INT11PL == 0) -#define MINT5_11PL ~(1 << 10) -#else -#define MINT5_11PL 0xFFFF -#endif - -#if (INT12PL >= INT5PL) || (INT12PL == 0) -#define MINT5_12PL ~(1 << 11) -#else -#define MINT5_12PL 0xFFFF -#endif - -#if (INT13PL >= INT5PL) || (INT13PL == 0) -#define MINT5_13PL ~(1 << 12) -#else -#define MINT5_13PL 0xFFFF -#endif - -#if (INT14PL >= INT5PL) || (INT14PL == 0) -#define MINT5_14PL ~(1 << 13) -#else -#define MINT5_14PL 0xFFFF -#endif - -#if (INT15PL >= INT5PL) || (INT15PL == 0) -#define MINT5_15PL ~(1 << 14) -#else -#define MINT5_15PL 0xFFFF -#endif - -#if (INT16PL >= INT5PL) || (INT16PL == 0) -#define MINT5_16PL ~(1 << 15) -#else -#define MINT5_16PL 0xFFFF -#endif - -#define MINT5 (MINT5_1PL & MINT5_2PL & MINT5_3PL & MINT5_4PL & \ - MINT5_5PL & MINT5_6PL & MINT5_7PL & MINT5_8PL & \ - MINT5_9PL & MINT5_10PL & MINT5_11PL & MINT5_12PL & \ - MINT5_13PL & MINT5_14PL & MINT5_15PL & MINT5_16PL) -// End Of MINT5. - -// Beginning of MINT6: -#if (INT1PL >= INT6PL) || (INT1PL == 0) -#define MINT6_1PL ~(1 << 0) -#else -#define MINT6_1PL 0xFFFF -#endif - -#if (INT2PL >= INT6PL) || (INT2PL == 0) -#define MINT6_2PL ~(1 << 1) -#else -#define MINT6_2PL 0xFFFF -#endif - -#if (INT3PL >= INT6PL) || (INT3PL == 0) -#define MINT6_3PL ~(1 << 2) -#else -#define MINT6_3PL 0xFFFF -#endif - -#if (INT4PL >= INT6PL) || (INT4PL == 0) -#define MINT6_4PL ~(1 << 3) -#else -#define MINT6_4PL 0xFFFF -#endif - -#if (INT5PL >= INT6PL) || (INT5PL == 0) -#define MINT6_5PL ~(1 << 4) -#else -#define MINT6_5PL 0xFFFF -#endif - -#if (INT6PL == 0) -#define MINT6_6PL ~(1 << 5) -#else -#define MINT6_6PL 0xFFFF -#endif - -#if (INT7PL >= INT6PL) || (INT7PL == 0) -#define MINT6_7PL ~(1 << 6) -#else -#define MINT6_7PL 0xFFFF -#endif - -#if (INT8PL >= INT6PL) || (INT8PL == 0) -#define MINT6_8PL ~(1 << 7) -#else -#define MINT6_8PL 0xFFFF -#endif - -#if (INT9PL >= INT6PL) || (INT9PL == 0) -#define MINT6_9PL ~(1 << 8) -#else -#define MINT6_9PL 0xFFFF -#endif - -#if (INT10PL >= INT6PL) || (INT10PL == 0) -#define MINT6_10PL ~(1 << 9) -#else -#define MINT6_10PL 0xFFFF -#endif - -#if (INT11PL >= INT6PL) || (INT11PL == 0) -#define MINT6_11PL ~(1 << 10) -#else -#define MINT6_11PL 0xFFFF -#endif - -#if (INT12PL >= INT6PL) || (INT12PL == 0) -#define MINT6_12PL ~(1 << 11) -#else -#define MINT6_12PL 0xFFFF -#endif - -#if (INT13PL >= INT6PL) || (INT13PL == 0) -#define MINT6_13PL ~(1 << 12) -#else -#define MINT6_13PL 0xFFFF -#endif - -#if (INT14PL >= INT6PL) || (INT14PL == 0) -#define MINT6_14PL ~(1 << 13) -#else -#define MINT6_14PL 0xFFFF -#endif - -#if (INT15PL >= INT6PL) || (INT15PL == 0) -#define MINT6_15PL ~(1 << 14) -#else -#define MINT6_15PL 0xFFFF -#endif - -#if (INT16PL >= INT6PL) || (INT16PL == 0) -#define MINT6_16PL ~(1 << 15) -#else -#define MINT6_16PL 0xFFFF -#endif - -#define MINT6 (MINT6_1PL & MINT6_2PL & MINT6_3PL & MINT6_4PL & \ - MINT6_5PL & MINT6_6PL & MINT6_7PL & MINT6_8PL & \ - MINT6_9PL & MINT6_10PL & MINT6_11PL & MINT6_12PL & \ - MINT6_13PL & MINT6_14PL & MINT6_15PL & MINT6_16PL) -// End Of MINT6. - -// Beginning of MINT7: -#if (INT1PL >= INT7PL) || (INT1PL == 0) -#define MINT7_1PL ~(1 << 0) -#else -#define MINT7_1PL 0xFFFF -#endif - -#if (INT2PL >= INT7PL) || (INT2PL == 0) -#define MINT7_2PL ~(1 << 1) -#else -#define MINT7_2PL 0xFFFF -#endif - -#if (INT3PL >= INT7PL) || (INT3PL == 0) -#define MINT7_3PL ~(1 << 2) -#else -#define MINT7_3PL 0xFFFF -#endif - -#if (INT4PL >= INT7PL) || (INT4PL == 0) -#define MINT7_4PL ~(1 << 3) -#else -#define MINT7_4PL 0xFFFF -#endif - -#if (INT5PL >= INT7PL) || (INT5PL == 0) -#define MINT7_5PL ~(1 << 4) -#else -#define MINT7_5PL 0xFFFF -#endif - -#if (INT6PL >= INT7PL) || (INT6PL == 0) -#define MINT7_6PL ~(1 << 5) -#else -#define MINT7_6PL 0xFFFF -#endif - -#if (INT7PL == 0) -#define MINT7_7PL ~(1 << 6) -#else -#define MINT7_7PL 0xFFFF -#endif - -#if (INT8PL >= INT7PL) || (INT8PL == 0) -#define MINT7_8PL ~(1 << 7) -#else -#define MINT7_8PL 0xFFFF -#endif - -#if (INT9PL >= INT7PL) || (INT9PL == 0) -#define MINT7_9PL ~(1 << 8) -#else -#define MINT7_9PL 0xFFFF -#endif - -#if (INT10PL >= INT7PL) || (INT10PL == 0) -#define MINT7_10PL ~(1 << 9) -#else -#define MINT7_10PL 0xFFFF -#endif - -#if (INT11PL >= INT7PL) || (INT11PL == 0) -#define MINT7_11PL ~(1 << 10) -#else -#define MINT7_11PL 0xFFFF -#endif - -#if (INT12PL >= INT7PL) || (INT12PL == 0) -#define MINT7_12PL ~(1 << 11) -#else -#define MINT7_12PL 0xFFFF -#endif - -#if (INT13PL >= INT7PL) || (INT13PL == 0) -#define MINT7_13PL ~(1 << 12) -#else -#define MINT7_13PL 0xFFFF -#endif - -#if (INT14PL >= INT7PL) || (INT14PL == 0) -#define MINT7_14PL ~(1 << 13) -#else -#define MINT7_14PL 0xFFFF -#endif - -#if (INT15PL >= INT7PL) || (INT15PL == 0) -#define MINT7_15PL ~(1 << 14) -#else -#define MINT7_15PL 0xFFFF -#endif - -#if (INT16PL >= INT7PL) || (INT16PL == 0) -#define MINT7_16PL ~(1 << 15) -#else -#define MINT7_16PL 0xFFFF -#endif - -#define MINT7 (MINT7_1PL & MINT7_2PL & MINT7_3PL & MINT7_4PL & \ - MINT7_5PL & MINT7_6PL & MINT7_7PL & MINT7_8PL & \ - MINT7_9PL & MINT7_10PL & MINT7_11PL & MINT7_12PL & \ - MINT7_13PL & MINT7_14PL & MINT7_15PL & MINT7_16PL) -// End Of MINT7. - -// Beginning of MINT8: -#if (INT1PL >= INT8PL) || (INT1PL == 0) -#define MINT8_1PL ~(1 << 0) -#else -#define MINT8_1PL 0xFFFF -#endif - -#if (INT2PL >= INT8PL) || (INT2PL == 0) -#define MINT8_2PL ~(1 << 1) -#else -#define MINT8_2PL 0xFFFF -#endif - -#if (INT3PL >= INT8PL) || (INT3PL == 0) -#define MINT8_3PL ~(1 << 2) -#else -#define MINT8_3PL 0xFFFF -#endif - -#if (INT4PL >= INT8PL) || (INT4PL == 0) -#define MINT8_4PL ~(1 << 3) -#else -#define MINT8_4PL 0xFFFF -#endif - -#if (INT5PL >= INT8PL) || (INT5PL == 0) -#define MINT8_5PL ~(1 << 4) -#else -#define MINT8_5PL 0xFFFF -#endif - -#if (INT6PL >= INT8PL) || (INT6PL == 0) -#define MINT8_6PL ~(1 << 5) -#else -#define MINT8_6PL 0xFFFF -#endif - -#if (INT7PL >= INT8PL) || (INT7PL == 0) -#define MINT8_7PL ~(1 << 6) -#else -#define MINT8_7PL 0xFFFF -#endif - -#if (INT8PL == 0) -#define MINT8_8PL ~(1 << 7) -#else -#define MINT8_8PL 0xFFFF -#endif - -#if (INT9PL >= INT8PL) || (INT9PL == 0) -#define MINT8_9PL ~(1 << 8) -#else -#define MINT8_9PL 0xFFFF -#endif - -#if (INT10PL >= INT8PL) || (INT10PL == 0) -#define MINT8_10PL ~(1 << 9) -#else -#define MINT8_10PL 0xFFFF -#endif - -#if (INT11PL >= INT8PL) || (INT11PL == 0) -#define MINT8_11PL ~(1 << 10) -#else -#define MINT8_11PL 0xFFFF -#endif - -#if (INT12PL >= INT8PL) || (INT12PL == 0) -#define MINT8_12PL ~(1 << 11) -#else -#define MINT8_12PL 0xFFFF -#endif - -#if (INT13PL >= INT8PL) || (INT13PL == 0) -#define MINT8_13PL ~(1 << 12) -#else -#define MINT8_13PL 0xFFFF -#endif - -#if (INT14PL >= INT8PL) || (INT14PL == 0) -#define MINT8_14PL ~(1 << 13) -#else -#define MINT8_14PL 0xFFFF -#endif - -#if (INT15PL >= INT8PL) || (INT15PL == 0) -#define MINT8_15PL ~(1 << 14) -#else -#define MINT8_15PL 0xFFFF -#endif - -#if (INT16PL >= INT8PL) || (INT16PL == 0) -#define MINT8_16PL ~(1 << 15) -#else -#define MINT8_16PL 0xFFFF -#endif - -#define MINT8 (MINT8_1PL & MINT8_2PL & MINT8_3PL & MINT8_4PL & \ - MINT8_5PL & MINT8_6PL & MINT8_7PL & MINT8_8PL & \ - MINT8_9PL & MINT8_10PL & MINT8_11PL & MINT8_12PL & \ - MINT8_13PL & MINT8_14PL & MINT8_15PL & MINT8_16PL) -// End Of MINT8. - -// Beginning of MINT9: -#if (INT1PL >= INT9PL) || (INT1PL == 0) -#define MINT9_1PL ~(1 << 0) -#else -#define MINT9_1PL 0xFFFF -#endif - -#if (INT2PL >= INT9PL) || (INT2PL == 0) -#define MINT9_2PL ~(1 << 1) -#else -#define MINT9_2PL 0xFFFF -#endif - -#if (INT3PL >= INT9PL) || (INT3PL == 0) -#define MINT9_3PL ~(1 << 2) -#else -#define MINT9_3PL 0xFFFF -#endif - -#if (INT4PL >= INT9PL) || (INT4PL == 0) -#define MINT9_4PL ~(1 << 3) -#else -#define MINT9_4PL 0xFFFF -#endif - -#if (INT5PL >= INT9PL) || (INT5PL == 0) -#define MINT9_5PL ~(1 << 4) -#else -#define MINT9_5PL 0xFFFF -#endif - -#if (INT6PL >= INT9PL) || (INT6PL == 0) -#define MINT9_6PL ~(1 << 5) -#else -#define MINT9_6PL 0xFFFF -#endif - -#if (INT7PL >= INT9PL) || (INT7PL == 0) -#define MINT9_7PL ~(1 << 6) -#else -#define MINT9_7PL 0xFFFF -#endif - -#if (INT8PL >= INT9PL) || (INT8PL == 0) -#define MINT9_8PL ~(1 << 7) -#else -#define MINT9_8PL 0xFFFF -#endif - -#if (INT9PL == 0) -#define MINT9_9PL ~(1 << 8) -#else -#define MINT9_9PL 0xFFFF -#endif - -#if (INT10PL >= INT9PL) || (INT10PL == 0) -#define MINT9_10PL ~(1 << 9) -#else -#define MINT9_10PL 0xFFFF -#endif - -#if (INT11PL >= INT9PL) || (INT11PL == 0) -#define MINT9_11PL ~(1 << 10) -#else -#define MINT9_11PL 0xFFFF -#endif - -#if (INT12PL >= INT9PL) || (INT12PL == 0) -#define MINT9_12PL ~(1 << 11) -#else -#define MINT9_12PL 0xFFFF -#endif - -#if (INT13PL >= INT9PL) || (INT13PL == 0) -#define MINT9_13PL ~(1 << 12) -#else -#define MINT9_13PL 0xFFFF -#endif - -#if (INT14PL >= INT9PL) || (INT14PL == 0) -#define MINT9_14PL ~(1 << 13) -#else -#define MINT9_14PL 0xFFFF -#endif - -#if (INT15PL >= INT9PL) || (INT15PL == 0) -#define MINT9_15PL ~(1 << 14) -#else -#define MINT9_15PL 0xFFFF -#endif - -#if (INT16PL >= INT9PL) || (INT16PL == 0) -#define MINT9_16PL ~(1 << 15) -#else -#define MINT9_16PL 0xFFFF -#endif - -#define MINT9 (MINT9_1PL & MINT9_2PL & MINT9_3PL & MINT9_4PL & \ - MINT9_5PL & MINT9_6PL & MINT9_7PL & MINT9_8PL & \ - MINT9_9PL & MINT9_10PL & MINT9_11PL & MINT9_12PL & \ - MINT9_13PL & MINT9_14PL & MINT9_15PL & MINT9_16PL) -// End Of MINT9. - -// Beginning of MINT10: -#if (INT1PL >= INT10PL) || (INT1PL == 0) -#define MINT10_1PL ~(1 << 0) -#else -#define MINT10_1PL 0xFFFF -#endif - -#if (INT2PL >= INT10PL) || (INT2PL == 0) -#define MINT10_2PL ~(1 << 1) -#else -#define MINT10_2PL 0xFFFF -#endif - -#if (INT3PL >= INT10PL) || (INT3PL == 0) -#define MINT10_3PL ~(1 << 2) -#else -#define MINT10_3PL 0xFFFF -#endif - -#if (INT4PL >= INT10PL) || (INT4PL == 0) -#define MINT10_4PL ~(1 << 3) -#else -#define MINT10_4PL 0xFFFF -#endif - -#if (INT5PL >= INT10PL) || (INT5PL == 0) -#define MINT10_5PL ~(1 << 4) -#else -#define MINT10_5PL 0xFFFF -#endif - -#if (INT6PL >= INT10PL) || (INT6PL == 0) -#define MINT10_6PL ~(1 << 5) -#else -#define MINT10_6PL 0xFFFF -#endif - -#if (INT7PL >= INT10PL) || (INT7PL == 0) -#define MINT10_7PL ~(1 << 6) -#else -#define MINT10_7PL 0xFFFF -#endif - -#if (INT8PL >= INT10PL) || (INT8PL == 0) -#define MINT10_8PL ~(1 << 7) -#else -#define MINT10_8PL 0xFFFF -#endif - -#if (INT9PL >= INT10PL) || (INT9PL == 0) -#define MINT10_9PL ~(1 << 8) -#else -#define MINT10_9PL 0xFFFF -#endif - -#if (INT10PL == 0) -#define MINT10_10PL ~(1 << 9) -#else -#define MINT10_10PL 0xFFFF -#endif - -#if (INT11PL >= INT10PL) || (INT11PL == 0) -#define MINT10_11PL ~(1 << 10) -#else -#define MINT10_11PL 0xFFFF -#endif - -#if (INT12PL >= INT10PL) || (INT12PL == 0) -#define MINT10_12PL ~(1 << 11) -#else -#define MINT10_12PL 0xFFFF -#endif - -#if (INT13PL >= INT10PL) || (INT13PL == 0) -#define MINT10_13PL ~(1 << 12) -#else -#define MINT10_13PL 0xFFFF -#endif - -#if (INT14PL >= INT10PL) || (INT14PL == 0) -#define MINT10_14PL ~(1 << 13) -#else -#define MINT10_14PL 0xFFFF -#endif - -#if (INT15PL >= INT10PL) || (INT15PL == 0) -#define MINT10_15PL ~(1 << 14) -#else -#define MINT10_15PL 0xFFFF -#endif - -#if (INT16PL >= INT10PL) || (INT16PL == 0) -#define MINT10_16PL ~(1 << 15) -#else -#define MINT10_16PL 0xFFFF -#endif - -#define MINT10 (MINT10_1PL & MINT10_2PL & MINT10_3PL & MINT10_4PL & \ - MINT10_5PL & MINT10_6PL & MINT10_7PL & MINT10_8PL & \ - MINT10_9PL & MINT10_10PL & MINT10_11PL & MINT10_12PL & \ - MINT10_13PL & MINT10_14PL & MINT10_15PL & MINT10_16PL) -// End Of MINT10. - -// Beginning of MINT11: -#if (INT1PL >= INT11PL) || (INT1PL == 0) -#define MINT11_1PL ~(1 << 0) -#else -#define MINT11_1PL 0xFFFF -#endif - -#if (INT2PL >= INT11PL) || (INT2PL == 0) -#define MINT11_2PL ~(1 << 1) -#else -#define MINT11_2PL 0xFFFF -#endif - -#if (INT3PL >= INT11PL) || (INT3PL == 0) -#define MINT11_3PL ~(1 << 2) -#else -#define MINT11_3PL 0xFFFF -#endif - -#if (INT4PL >= INT11PL) || (INT4PL == 0) -#define MINT11_4PL ~(1 << 3) -#else -#define MINT11_4PL 0xFFFF -#endif - -#if (INT5PL >= INT11PL) || (INT5PL == 0) -#define MINT11_5PL ~(1 << 4) -#else -#define MINT11_5PL 0xFFFF -#endif - -#if (INT6PL >= INT11PL) || (INT6PL == 0) -#define MINT11_6PL ~(1 << 5) -#else -#define MINT11_6PL 0xFFFF -#endif - -#if (INT7PL >= INT11PL) || (INT7PL == 0) -#define MINT11_7PL ~(1 << 6) -#else -#define MINT11_7PL 0xFFFF -#endif - -#if (INT8PL >= INT11PL) || (INT8PL == 0) -#define MINT11_8PL ~(1 << 7) -#else -#define MINT11_8PL 0xFFFF -#endif - -#if (INT9PL >= INT11PL) || (INT9PL == 0) -#define MINT11_9PL ~(1 << 8) -#else -#define MINT11_9PL 0xFFFF -#endif - -#if (INT10PL >= INT11PL) || (INT10PL == 0) -#define MINT11_10PL ~(1 << 9) -#else -#define MINT11_10PL 0xFFFF -#endif - -#if (INT11PL == 0) -#define MINT11_11PL ~(1 << 10) -#else -#define MINT11_11PL 0xFFFF -#endif - -#if (INT12PL >= INT11PL) || (INT12PL == 0) -#define MINT11_12PL ~(1 << 11) -#else -#define MINT11_12PL 0xFFFF -#endif - -#if (INT13PL >= INT11PL) || (INT13PL == 0) -#define MINT11_13PL ~(1 << 12) -#else -#define MINT11_13PL 0xFFFF -#endif - -#if (INT14PL >= INT11PL) || (INT14PL == 0) -#define MINT11_14PL ~(1 << 13) -#else -#define MINT11_14PL 0xFFFF -#endif - -#if (INT15PL >= INT11PL) || (INT15PL == 0) -#define MINT11_15PL ~(1 << 14) -#else -#define MINT11_15PL 0xFFFF -#endif - -#if (INT16PL >= INT11PL) || (INT16PL == 0) -#define MINT11_16PL ~(1 << 15) -#else -#define MINT11_16PL 0xFFFF -#endif - -#define MINT11 (MINT11_1PL & MINT11_2PL & MINT11_3PL & MINT11_4PL & \ - MINT11_5PL & MINT11_6PL & MINT11_7PL & MINT11_8PL & \ - MINT11_9PL & MINT11_10PL & MINT11_11PL & MINT11_12PL & \ - MINT11_13PL & MINT11_14PL & MINT11_15PL & MINT11_16PL) -// End Of MINT11. - -// Beginning of MINT12: -#if (INT1PL >= INT12PL) || (INT1PL == 0) -#define MINT12_1PL ~(1 << 0) -#else -#define MINT12_1PL 0xFFFF -#endif - -#if (INT2PL >= INT12PL) || (INT2PL == 0) -#define MINT12_2PL ~(1 << 1) -#else -#define MINT12_2PL 0xFFFF -#endif - -#if (INT3PL >= INT12PL) || (INT3PL == 0) -#define MINT12_3PL ~(1 << 2) -#else -#define MINT12_3PL 0xFFFF -#endif - -#if (INT4PL >= INT12PL) || (INT4PL == 0) -#define MINT12_4PL ~(1 << 3) -#else -#define MINT12_4PL 0xFFFF -#endif - -#if (INT5PL >= INT12PL) || (INT5PL == 0) -#define MINT12_5PL ~(1 << 4) -#else -#define MINT12_5PL 0xFFFF -#endif - -#if (INT6PL >= INT12PL) || (INT6PL == 0) -#define MINT12_6PL ~(1 << 5) -#else -#define MINT12_6PL 0xFFFF -#endif - -#if (INT7PL >= INT12PL) || (INT7PL == 0) -#define MINT12_7PL ~(1 << 6) -#else -#define MINT12_7PL 0xFFFF -#endif - -#if (INT8PL >= INT12PL) || (INT8PL == 0) -#define MINT12_8PL ~(1 << 7) -#else -#define MINT12_8PL 0xFFFF -#endif - -#if (INT9PL >= INT12PL) || (INT9PL == 0) -#define MINT12_9PL ~(1 << 8) -#else -#define MINT12_9PL 0xFFFF -#endif - -#if (INT10PL >= INT12PL) || (INT10PL == 0) -#define MINT12_10PL ~(1 << 9) -#else -#define MINT12_10PL 0xFFFF -#endif - -#if (INT11PL >= INT12PL) || (INT11PL == 0) -#define MINT12_11PL ~(1 << 10) -#else -#define MINT12_11PL 0xFFFF -#endif - -#if (INT12PL == 0) -#define MINT12_12PL ~(1 << 11) -#else -#define MINT12_12PL 0xFFFF -#endif - -#if (INT13PL >= INT12PL) || (INT13PL == 0) -#define MINT12_13PL ~(1 << 12) -#else -#define MINT12_13PL 0xFFFF -#endif - -#if (INT14PL >= INT12PL) || (INT14PL == 0) -#define MINT12_14PL ~(1 << 13) -#else -#define MINT12_14PL 0xFFFF -#endif - -#if (INT15PL >= INT12PL) || (INT15PL == 0) -#define MINT12_15PL ~(1 << 14) -#else -#define MINT12_15PL 0xFFFF -#endif - -#if (INT16PL >= INT12PL) || (INT16PL == 0) -#define MINT12_16PL ~(1 << 15) -#else -#define MINT12_16PL 0xFFFF -#endif - -#define MINT12 (MINT12_1PL & MINT12_2PL & MINT12_3PL & MINT12_4PL & \ - MINT12_5PL & MINT12_6PL & MINT12_7PL & MINT12_8PL & \ - MINT12_9PL & MINT12_10PL & MINT12_11PL & MINT12_12PL & \ - MINT12_13PL & MINT12_14PL & MINT12_15PL & MINT12_16PL) -// End Of MINT12. - -// Beginning of MINT13: -#if (INT1PL >= INT13PL) || (INT1PL == 0) -#define MINT13_1PL ~(1 << 0) -#else -#define MINT13_1PL 0xFFFF -#endif - -#if (INT2PL >= INT13PL) || (INT2PL == 0) -#define MINT13_2PL ~(1 << 1) -#else -#define MINT13_2PL 0xFFFF -#endif - -#if (INT3PL >= INT13PL) || (INT3PL == 0) -#define MINT13_3PL ~(1 << 2) -#else -#define MINT13_3PL 0xFFFF -#endif - -#if (INT4PL >= INT13PL) || (INT4PL == 0) -#define MINT13_4PL ~(1 << 3) -#else -#define MINT13_4PL 0xFFFF -#endif - -#if (INT5PL >= INT13PL) || (INT5PL == 0) -#define MINT13_5PL ~(1 << 4) -#else -#define MINT13_5PL 0xFFFF -#endif - -#if (INT6PL >= INT13PL) || (INT6PL == 0) -#define MINT13_6PL ~(1 << 5) -#else -#define MINT13_6PL 0xFFFF -#endif - -#if (INT7PL >= INT13PL) || (INT7PL == 0) -#define MINT13_7PL ~(1 << 6) -#else -#define MINT13_7PL 0xFFFF -#endif - -#if (INT8PL >= INT13PL) || (INT8PL == 0) -#define MINT13_8PL ~(1 << 7) -#else -#define MINT13_8PL 0xFFFF -#endif - -#if (INT9PL >= INT13PL) || (INT9PL == 0) -#define MINT13_9PL ~(1 << 8) -#else -#define MINT13_9PL 0xFFFF -#endif - -#if (INT10PL >= INT13PL) || (INT10PL == 0) -#define MINT13_10PL ~(1 << 9) -#else -#define MINT13_10PL 0xFFFF -#endif - -#if (INT11PL >= INT13PL) || (INT11PL == 0) -#define MINT13_11PL ~(1 << 10) -#else -#define MINT13_11PL 0xFFFF -#endif - -#if (INT12PL >= INT13PL) || (INT12PL == 0) -#define MINT13_12PL ~(1 << 11) -#else -#define MINT13_12PL 0xFFFF -#endif - -#if (INT13PL == 0) -#define MINT13_13PL ~(1 << 12) -#else -#define MINT13_13PL 0xFFFF -#endif - -#if (INT14PL >= INT13PL) || (INT14PL == 0) -#define MINT13_14PL ~(1 << 13) -#else -#define MINT13_14PL 0xFFFF -#endif - -#if (INT15PL >= INT13PL) || (INT15PL == 0) -#define MINT13_15PL ~(1 << 14) -#else -#define MINT13_15PL 0xFFFF -#endif - -#if (INT16PL >= INT13PL) || (INT16PL == 0) -#define MINT13_16PL ~(1 << 15) -#else -#define MINT13_16PL 0xFFFF -#endif - -#define MINT13 (MINT13_1PL & MINT13_2PL & MINT13_3PL & MINT13_4PL & \ - MINT13_5PL & MINT13_6PL & MINT13_7PL & MINT13_8PL & \ - MINT13_9PL & MINT13_10PL & MINT13_11PL & MINT13_12PL & \ - MINT13_13PL & MINT13_14PL & MINT13_15PL & MINT13_16PL) -// End Of MINT13. - -// Beginning of MINT14: -#if (INT1PL >= INT14PL) || (INT1PL == 0) -#define MINT14_1PL ~(1 << 0) -#else -#define MINT14_1PL 0xFFFF -#endif - -#if (INT2PL >= INT14PL) || (INT2PL == 0) -#define MINT14_2PL ~(1 << 1) -#else -#define MINT14_2PL 0xFFFF -#endif - -#if (INT3PL >= INT14PL) || (INT3PL == 0) -#define MINT14_3PL ~(1 << 2) -#else -#define MINT14_3PL 0xFFFF -#endif - -#if (INT4PL >= INT14PL) || (INT4PL == 0) -#define MINT14_4PL ~(1 << 3) -#else -#define MINT14_4PL 0xFFFF -#endif - -#if (INT5PL >= INT14PL) || (INT5PL == 0) -#define MINT14_5PL ~(1 << 4) -#else -#define MINT14_5PL 0xFFFF -#endif - -#if (INT6PL >= INT14PL) || (INT6PL == 0) -#define MINT14_6PL ~(1 << 5) -#else -#define MINT14_6PL 0xFFFF -#endif - -#if (INT7PL >= INT14PL) || (INT7PL == 0) -#define MINT14_7PL ~(1 << 6) -#else -#define MINT14_7PL 0xFFFF -#endif - -#if (INT8PL >= INT14PL) || (INT8PL == 0) -#define MINT14_8PL ~(1 << 7) -#else -#define MINT14_8PL 0xFFFF -#endif - -#if (INT9PL >= INT14PL) || (INT9PL == 0) -#define MINT14_9PL ~(1 << 8) -#else -#define MINT14_9PL 0xFFFF -#endif - -#if (INT10PL >= INT14PL) || (INT10PL == 0) -#define MINT14_10PL ~(1 << 9) -#else -#define MINT14_10PL 0xFFFF -#endif - -#if (INT11PL >= INT14PL) || (INT11PL == 0) -#define MINT14_11PL ~(1 << 10) -#else -#define MINT14_11PL 0xFFFF -#endif - -#if (INT12PL >= INT14PL) || (INT12PL == 0) -#define MINT14_12PL ~(1 << 11) -#else -#define MINT14_12PL 0xFFFF -#endif - -#if (INT13PL >= INT14PL) || (INT13PL == 0) -#define MINT14_13PL ~(1 << 12) -#else -#define MINT14_13PL 0xFFFF -#endif - -#define MINT14_14PL ~(1 << 13) - -#if (INT15PL >= INT14PL) || (INT15PL == 0) -#define MINT14_15PL ~(1 << 14) -#else -#define MINT14_15PL 0xFFFF -#endif - -#if (INT16PL >= INT14PL) || (INT16PL == 0) -#define MINT14_16PL ~(1 << 15) -#else -#define MINT14_16PL 0xFFFF -#endif - -#define MINT14 (MINT14_1PL & MINT14_2PL & MINT14_3PL & MINT14_4PL & \ - MINT14_5PL & MINT14_6PL & MINT14_7PL & MINT14_8PL & \ - MINT14_9PL & MINT14_10PL & MINT14_11PL & MINT14_12PL & \ - MINT14_13PL & MINT14_14PL & MINT14_15PL & MINT14_16PL) -// End Of MINT14. - -// Beginning of MINT15: -#if (INT1PL >= INT15PL) || (INT1PL == 0) -#define MINT15_1PL ~(1 << 0) -#else -#define MINT15_1PL 0xFFFF -#endif - -#if (INT2PL >= INT15PL) || (INT2PL == 0) -#define MINT15_2PL ~(1 << 1) -#else -#define MINT15_2PL 0xFFFF -#endif - -#if (INT3PL >= INT15PL) || (INT3PL == 0) -#define MINT15_3PL ~(1 << 2) -#else -#define MINT15_3PL 0xFFFF -#endif - -#if (INT4PL >= INT15PL) || (INT4PL == 0) -#define MINT15_4PL ~(1 << 3) -#else -#define MINT15_4PL 0xFFFF -#endif - -#if (INT5PL >= INT15PL) || (INT5PL == 0) -#define MINT15_5PL ~(1 << 4) -#else -#define MINT15_5PL 0xFFFF -#endif - -#if (INT6PL >= INT15PL) || (INT6PL == 0) -#define MINT15_6PL ~(1 << 5) -#else -#define MINT15_6PL 0xFFFF -#endif - -#if (INT7PL >= INT15PL) || (INT7PL == 0) -#define MINT15_7PL ~(1 << 6) -#else -#define MINT15_7PL 0xFFFF -#endif - -#if (INT8PL >= INT15PL) || (INT8PL == 0) -#define MINT15_8PL ~(1 << 7) -#else -#define MINT15_8PL 0xFFFF -#endif - -#if (INT9PL >= INT15PL) || (INT9PL == 0) -#define MINT15_9PL ~(1 << 8) -#else -#define MINT15_9PL 0xFFFF -#endif - -#if (INT10PL >= INT15PL) || (INT10PL == 0) -#define MINT15_10PL ~(1 << 9) -#else -#define MINT15_10PL 0xFFFF -#endif - -#if (INT11PL >= INT15PL) || (INT11PL == 0) -#define MINT15_11PL ~(1 << 10) -#else -#define MINT15_11PL 0xFFFF -#endif - -#if (INT12PL >= INT15PL) || (INT12PL == 0) -#define MINT15_12PL ~(1 << 11) -#else -#define MINT15_12PL 0xFFFF -#endif - -#if (INT13PL >= INT15PL) || (INT13PL == 0) -#define MINT15_13PL ~(1 << 12) -#else -#define MINT15_13PL 0xFFFF -#endif - -#if (INT14PL >= INT15PL) || (INT14PL == 0) -#define MINT15_14PL ~(1 << 13) -#else -#define MINT15_14PL 0xFFFF -#endif - -#define MINT15_15PL ~(1 << 14) - -#if (INT16PL >= INT15PL) || (INT16PL == 0) -#define MINT15_16PL ~(1 << 15) -#else -#define MINT15_16PL 0xFFFF -#endif - -#define MINT15 (MINT15_1PL & MINT15_2PL & MINT15_3PL & MINT15_4PL & \ - MINT15_5PL & MINT15_6PL & MINT15_7PL & MINT15_8PL & \ - MINT15_9PL & MINT15_10PL & MINT15_11PL & MINT15_12PL & \ - MINT15_13PL & MINT15_14PL & MINT15_15PL & MINT15_16PL) -// End Of MINT15. - -// Beginning of MINT16: -#if (INT1PL >= INT16PL) || (INT1PL == 0) -#define MINT16_1PL ~(1 << 0) -#else -#define MINT16_1PL 0xFFFF -#endif - -#if (INT2PL >= INT16PL) || (INT2PL == 0) -#define MINT16_2PL ~(1 << 1) -#else -#define MINT16_2PL 0xFFFF -#endif - -#if (INT3PL >= INT16PL) || (INT3PL == 0) -#define MINT16_3PL ~(1 << 2) -#else -#define MINT16_3PL 0xFFFF -#endif - -#if (INT4PL >= INT16PL) || (INT4PL == 0) -#define MINT16_4PL ~(1 << 3) -#else -#define MINT16_4PL 0xFFFF -#endif - -#if (INT5PL >= INT16PL) || (INT5PL == 0) -#define MINT16_5PL ~(1 << 4) -#else -#define MINT16_5PL 0xFFFF -#endif - -#if (INT6PL >= INT16PL) || (INT6PL == 0) -#define MINT16_6PL ~(1 << 5) -#else -#define MINT16_6PL 0xFFFF -#endif - -#if (INT7PL >= INT16PL) || (INT7PL == 0) -#define MINT16_7PL ~(1 << 6) -#else -#define MINT16_7PL 0xFFFF -#endif - -#if (INT8PL >= INT16PL) || (INT8PL == 0) -#define MINT16_8PL ~(1 << 7) -#else -#define MINT16_8PL 0xFFFF -#endif - -#if (INT9PL >= INT16PL) || (INT9PL == 0) -#define MINT16_9PL ~(1 << 8) -#else -#define MINT16_9PL 0xFFFF -#endif - -#if (INT10PL >= INT16PL) || (INT10PL == 0) -#define MINT16_10PL ~(1 << 9) -#else -#define MINT16_10PL 0xFFFF -#endif - -#if (INT11PL >= INT16PL) || (INT11PL == 0) -#define MINT16_11PL ~(1 << 10) -#else -#define MINT16_11PL 0xFFFF -#endif - -#if (INT12PL >= INT16PL) || (INT12PL == 0) -#define MINT16_12PL ~(1 << 11) -#else -#define MINT16_12PL 0xFFFF -#endif - -#if (INT13PL >= INT16PL) || (INT13PL == 0) -#define MINT16_13PL ~(1 << 12) -#else -#define MINT16_13PL 0xFFFF -#endif - -#if (INT14PL >= INT16PL) || (INT14PL == 0) -#define MINT16_14PL ~(1 << 13) -#else -#define MINT16_14PL 0xFFFF -#endif - -#if (INT15PL >= INT16PL) || (INT15PL == 0) -#define MINT16_15PL ~(1 << 14) -#else -#define MINT16_15PL 0xFFFF -#endif - -#define MINT16_16PL ~(1 << 15) - -#define MINT16 (MINT16_1PL & MINT16_2PL & MINT16_3PL & MINT16_4PL & \ - MINT16_5PL & MINT16_6PL & MINT16_7PL & MINT16_8PL & \ - MINT16_9PL & MINT16_10PL & MINT16_11PL & MINT16_12PL & \ - MINT16_13PL & MINT16_14PL & MINT16_15PL & MINT16_16PL) -// End Of MINT16. - -// -// Automatically generate PIEIER1 interrupt masks MG11 to MG116: -// - -// Beginning of MG11: -#if (G1_2PL >= G1_1PL) || (G1_2PL == 0) -#define MG1_1_12PL ~(1 << 1) -#else -#define MG1_1_12PL 0xFFFF -#endif - -#if (G1_3PL >= G1_1PL) || (G1_3PL == 0) -#define MG1_1_13PL ~(1 << 2) -#else -#define MG1_1_13PL 0xFFFF -#endif - -#if (G1_4PL >= G1_1PL) || (G1_4PL == 0) -#define MG1_1_14PL ~(1 << 3) -#else -#define MG1_1_14PL 0xFFFF -#endif - -#if (G1_5PL >= G1_1PL) || (G1_5PL == 0) -#define MG1_1_15PL ~(1 << 4) -#else -#define MG1_1_15PL 0xFFFF -#endif - -#if (G1_6PL >= G1_1PL) || (G1_6PL == 0) -#define MG1_1_16PL ~(1 << 5) -#else -#define MG1_1_16PL 0xFFFF -#endif - -#if (G1_7PL >= G1_1PL) || (G1_7PL == 0) -#define MG1_1_17PL ~(1 << 6) -#else -#define MG1_1_17PL 0xFFFF -#endif - -#if (G1_8PL >= G1_1PL) || (G1_8PL == 0) -#define MG1_1_18PL ~(1 << 7) -#else -#define MG1_1_18PL 0xFFFF -#endif - -#if (G1_9PL >= G1_1PL) || (G1_9PL == 0) -#define MG1_1_19PL ~(1 << 8) -#else -#define MG1_1_19PL 0xFFFF -#endif - -#if (G1_10PL >= G1_1PL) || (G1_10PL == 0) -#define MG1_1_110PL ~(1 << 9) -#else -#define MG1_1_110PL 0xFFFF -#endif - -#if (G1_11PL >= G1_1PL) || (G1_11PL == 0) -#define MG1_1_111PL ~(1 << 10) -#else -#define MG1_1_111PL 0xFFFF -#endif - -#if (G1_12PL >= G1_1PL) || (G1_12PL == 0) -#define MG1_1_112PL ~(1 << 11) -#else -#define MG1_1_112PL 0xFFFF -#endif - -#if (G1_13PL >= G1_1PL) || (G1_13PL == 0) -#define MG1_1_113PL ~(1 << 12) -#else -#define MG1_1_113PL 0xFFFF -#endif - -#if (G1_14PL >= G1_1PL) || (G1_14PL == 0) -#define MG1_1_114PL ~(1 << 13) -#else -#define MG1_1_114PL 0xFFFF -#endif - -#if (G1_15PL >= G1_1PL) || (G1_15PL == 0) -#define MG1_1_115PL ~(1 << 14) -#else -#define MG1_1_115PL 0xFFFF -#endif - -#if (G1_16PL >= G1_1PL) || (G1_16PL == 0) -#define MG1_1_116PL ~(1 << 15) -#else -#define MG1_1_116PL 0xFFFF -#endif - -#define MG1_1_11PL 0xFFFE -#define MG1_1 (MG1_1_11PL & MG1_1_12PL & MG1_1_13PL & MG1_1_14PL & \ - MG1_1_15PL & MG1_1_16PL & MG1_1_17PL & MG1_1_18PL & \ - MG1_1_19PL & MG1_1_110PL & MG1_1_111PL & MG1_1_112PL & \ - MG1_1_113PL & MG1_1_114PL & MG1_1_115PL & MG1_1_116PL) -// End of MG1_1: -// Beginning of MG12: -#if (G1_1PL >= G1_2PL) || (G1_1PL == 0) -#define MG1_2_11PL ~(1 << 0) -#else -#define MG1_2_11PL 0xFFFF -#endif - -#if (G1_3PL >= G1_2PL) || (G1_3PL == 0) -#define MG1_2_13PL ~(1 << 2) -#else -#define MG1_2_13PL 0xFFFF -#endif - -#if (G1_4PL >= G1_2PL) || (G1_4PL == 0) -#define MG1_2_14PL ~(1 << 3) -#else -#define MG1_2_14PL 0xFFFF -#endif - -#if (G1_5PL >= G1_2PL) || (G1_5PL == 0) -#define MG1_2_15PL ~(1 << 4) -#else -#define MG1_2_15PL 0xFFFF -#endif - -#if (G1_6PL >= G1_2PL) || (G1_6PL == 0) -#define MG1_2_16PL ~(1 << 5) -#else -#define MG1_2_16PL 0xFFFF -#endif - -#if (G1_7PL >= G1_2PL) || (G1_7PL == 0) -#define MG1_2_17PL ~(1 << 6) -#else -#define MG1_2_17PL 0xFFFF -#endif - -#if (G1_8PL >= G1_2PL) || (G1_8PL == 0) -#define MG1_2_18PL ~(1 << 7) -#else -#define MG1_2_18PL 0xFFFF -#endif - -#if (G1_9PL >= G1_2PL) || (G1_9PL == 0) -#define MG1_2_19PL ~(1 << 8) -#else -#define MG1_2_19PL 0xFFFF -#endif - -#if (G1_10PL >= G1_2PL) || (G1_10PL == 0) -#define MG1_2_110PL ~(1 << 9) -#else -#define MG1_2_110PL 0xFFFF -#endif - -#if (G1_11PL >= G1_2PL) || (G1_11PL == 0) -#define MG1_2_111PL ~(1 << 10) -#else -#define MG1_2_111PL 0xFFFF -#endif - -#if (G1_12PL >= G1_2PL) || (G1_12PL == 0) -#define MG1_2_112PL ~(1 << 11) -#else -#define MG1_2_112PL 0xFFFF -#endif - -#if (G1_13PL >= G1_2PL) || (G1_13PL == 0) -#define MG1_2_113PL ~(1 << 12) -#else -#define MG1_2_113PL 0xFFFF -#endif - -#if (G1_14PL >= G1_2PL) || (G1_14PL == 0) -#define MG1_2_114PL ~(1 << 13) -#else -#define MG1_2_114PL 0xFFFF -#endif - -#if (G1_15PL >= G1_2PL) || (G1_15PL == 0) -#define MG1_2_115PL ~(1 << 14) -#else -#define MG1_2_115PL 0xFFFF -#endif - -#if (G1_16PL >= G1_2PL) || (G1_16PL == 0) -#define MG1_2_116PL ~(1 << 15) -#else -#define MG1_2_116PL 0xFFFF -#endif - -#define MG1_2_12PL 0xFFFD -#define MG1_2 (MG1_2_11PL & MG1_2_12PL & MG1_2_13PL & MG1_2_14PL & \ - MG1_2_15PL & MG1_2_16PL & MG1_2_17PL & MG1_2_18PL & \ - MG1_2_19PL & MG1_2_110PL & MG1_2_111PL & MG1_2_112PL & \ - MG1_2_113PL & MG1_2_114PL & MG1_2_115PL & MG1_2_116PL) -// End of MG1_2: -// Beginning of MG13: -#if (G1_1PL >= G1_3PL) || (G1_1PL == 0) -#define MG1_3_11PL ~(1 << 0) -#else -#define MG1_3_11PL 0xFFFF -#endif - -#if (G1_2PL >= G1_3PL) || (G1_2PL == 0) -#define MG1_3_12PL ~(1 << 1) -#else -#define MG1_3_12PL 0xFFFF -#endif - -#if (G1_4PL >= G1_3PL) || (G1_4PL == 0) -#define MG1_3_14PL ~(1 << 3) -#else -#define MG1_3_14PL 0xFFFF -#endif - -#if (G1_5PL >= G1_3PL) || (G1_5PL == 0) -#define MG1_3_15PL ~(1 << 4) -#else -#define MG1_3_15PL 0xFFFF -#endif - -#if (G1_6PL >= G1_3PL) || (G1_6PL == 0) -#define MG1_3_16PL ~(1 << 5) -#else -#define MG1_3_16PL 0xFFFF -#endif - -#if (G1_7PL >= G1_3PL) || (G1_7PL == 0) -#define MG1_3_17PL ~(1 << 6) -#else -#define MG1_3_17PL 0xFFFF -#endif - -#if (G1_8PL >= G1_3PL) || (G1_8PL == 0) -#define MG1_3_18PL ~(1 << 7) -#else -#define MG1_3_18PL 0xFFFF -#endif - -#if (G1_9PL >= G1_3PL) || (G1_9PL == 0) -#define MG1_3_19PL ~(1 << 8) -#else -#define MG1_3_19PL 0xFFFF -#endif - -#if (G1_10PL >= G1_3PL) || (G1_10PL == 0) -#define MG1_3_110PL ~(1 << 9) -#else -#define MG1_3_110PL 0xFFFF -#endif - -#if (G1_11PL >= G1_3PL) || (G1_11PL == 0) -#define MG1_3_111PL ~(1 << 10) -#else -#define MG1_3_111PL 0xFFFF -#endif - -#if (G1_12PL >= G1_3PL) || (G1_12PL == 0) -#define MG1_3_112PL ~(1 << 11) -#else -#define MG1_3_112PL 0xFFFF -#endif - -#if (G1_13PL >= G1_3PL) || (G1_13PL == 0) -#define MG1_3_113PL ~(1 << 12) -#else -#define MG1_3_113PL 0xFFFF -#endif - -#if (G1_14PL >= G1_3PL) || (G1_14PL == 0) -#define MG1_3_114PL ~(1 << 13) -#else -#define MG1_3_114PL 0xFFFF -#endif - -#if (G1_15PL >= G1_3PL) || (G1_15PL == 0) -#define MG1_3_115PL ~(1 << 14) -#else -#define MG1_3_115PL 0xFFFF -#endif - -#if (G1_16PL >= G1_3PL) || (G1_16PL == 0) -#define MG1_3_116PL ~(1 << 15) -#else -#define MG1_3_116PL 0xFFFF -#endif - -#define MG1_3_13PL 0xFFFB -#define MG1_3 (MG1_3_11PL & MG1_3_12PL & MG1_3_13PL & MG1_3_14PL & \ - MG1_3_15PL & MG1_3_16PL & MG1_3_17PL & MG1_3_18PL & \ - MG1_3_19PL & MG1_3_110PL & MG1_3_111PL & MG1_3_112PL & \ - MG1_3_113PL & MG1_3_114PL & MG1_3_115PL & MG1_3_116PL) -// End of MG1_3: -// Beginning of MG14: -#if (G1_1PL >= G1_4PL) || (G1_1PL == 0) -#define MG1_4_11PL ~(1 << 0) -#else -#define MG1_4_11PL 0xFFFF -#endif - -#if (G1_2PL >= G1_4PL) || (G1_2PL == 0) -#define MG1_4_12PL ~(1 << 1) -#else -#define MG1_4_12PL 0xFFFF -#endif - -#if (G1_3PL >= G1_4PL) || (G1_3PL == 0) -#define MG1_4_13PL ~(1 << 2) -#else -#define MG1_4_13PL 0xFFFF -#endif - -#if (G1_5PL >= G1_4PL) || (G1_5PL == 0) -#define MG1_4_15PL ~(1 << 4) -#else -#define MG1_4_15PL 0xFFFF -#endif - -#if (G1_6PL >= G1_4PL) || (G1_6PL == 0) -#define MG1_4_16PL ~(1 << 5) -#else -#define MG1_4_16PL 0xFFFF -#endif - -#if (G1_7PL >= G1_4PL) || (G1_7PL == 0) -#define MG1_4_17PL ~(1 << 6) -#else -#define MG1_4_17PL 0xFFFF -#endif - -#if (G1_8PL >= G1_4PL) || (G1_8PL == 0) -#define MG1_4_18PL ~(1 << 7) -#else -#define MG1_4_18PL 0xFFFF -#endif - -#if (G1_9PL >= G1_4PL) || (G1_9PL == 0) -#define MG1_4_19PL ~(1 << 8) -#else -#define MG1_4_19PL 0xFFFF -#endif - -#if (G1_10PL >= G1_4PL) || (G1_10PL == 0) -#define MG1_4_110PL ~(1 << 9) -#else -#define MG1_4_110PL 0xFFFF -#endif - -#if (G1_11PL >= G1_4PL) || (G1_11PL == 0) -#define MG1_4_111PL ~(1 << 10) -#else -#define MG1_4_111PL 0xFFFF -#endif - -#if (G1_12PL >= G1_4PL) || (G1_12PL == 0) -#define MG1_4_112PL ~(1 << 11) -#else -#define MG1_4_112PL 0xFFFF -#endif - -#if (G1_13PL >= G1_4PL) || (G1_13PL == 0) -#define MG1_4_113PL ~(1 << 12) -#else -#define MG1_4_113PL 0xFFFF -#endif - -#if (G1_14PL >= G1_4PL) || (G1_14PL == 0) -#define MG1_4_114PL ~(1 << 13) -#else -#define MG1_4_114PL 0xFFFF -#endif - -#if (G1_15PL >= G1_4PL) || (G1_15PL == 0) -#define MG1_4_115PL ~(1 << 14) -#else -#define MG1_4_115PL 0xFFFF -#endif - -#if (G1_16PL >= G1_4PL) || (G1_16PL == 0) -#define MG1_4_116PL ~(1 << 15) -#else -#define MG1_4_116PL 0xFFFF -#endif - -#define MG1_4_14PL 0xFFF7 -#define MG1_4 (MG1_4_11PL & MG1_4_12PL & MG1_4_13PL & MG1_4_14PL & \ - MG1_4_15PL & MG1_4_16PL & MG1_4_17PL & MG1_4_18PL & \ - MG1_4_19PL & MG1_4_110PL & MG1_4_111PL & MG1_4_112PL & \ - MG1_4_113PL & MG1_4_114PL & MG1_4_115PL & MG1_4_116PL) -// End of MG1_4: -// Beginning of MG15: -#if (G1_1PL >= G1_5PL) || (G1_1PL == 0) -#define MG1_5_11PL ~(1 << 0) -#else -#define MG1_5_11PL 0xFFFF -#endif - -#if (G1_2PL >= G1_5PL) || (G1_2PL == 0) -#define MG1_5_12PL ~(1 << 1) -#else -#define MG1_5_12PL 0xFFFF -#endif - -#if (G1_3PL >= G1_5PL) || (G1_3PL == 0) -#define MG1_5_13PL ~(1 << 2) -#else -#define MG1_5_13PL 0xFFFF -#endif - -#if (G1_4PL >= G1_5PL) || (G1_4PL == 0) -#define MG1_5_14PL ~(1 << 3) -#else -#define MG1_5_14PL 0xFFFF -#endif - -#if (G1_6PL >= G1_5PL) || (G1_6PL == 0) -#define MG1_5_16PL ~(1 << 5) -#else -#define MG1_5_16PL 0xFFFF -#endif - -#if (G1_7PL >= G1_5PL) || (G1_7PL == 0) -#define MG1_5_17PL ~(1 << 6) -#else -#define MG1_5_17PL 0xFFFF -#endif - -#if (G1_8PL >= G1_5PL) || (G1_8PL == 0) -#define MG1_5_18PL ~(1 << 7) -#else -#define MG1_5_18PL 0xFFFF -#endif - -#if (G1_9PL >= G1_5PL) || (G1_9PL == 0) -#define MG1_5_19PL ~(1 << 8) -#else -#define MG1_5_19PL 0xFFFF -#endif - -#if (G1_10PL >= G1_5PL) || (G1_10PL == 0) -#define MG1_5_110PL ~(1 << 9) -#else -#define MG1_5_110PL 0xFFFF -#endif - -#if (G1_11PL >= G1_5PL) || (G1_11PL == 0) -#define MG1_5_111PL ~(1 << 10) -#else -#define MG1_5_111PL 0xFFFF -#endif - -#if (G1_12PL >= G1_5PL) || (G1_12PL == 0) -#define MG1_5_112PL ~(1 << 11) -#else -#define MG1_5_112PL 0xFFFF -#endif - -#if (G1_13PL >= G1_5PL) || (G1_13PL == 0) -#define MG1_5_113PL ~(1 << 12) -#else -#define MG1_5_113PL 0xFFFF -#endif - -#if (G1_14PL >= G1_5PL) || (G1_14PL == 0) -#define MG1_5_114PL ~(1 << 13) -#else -#define MG1_5_114PL 0xFFFF -#endif - -#if (G1_15PL >= G1_5PL) || (G1_15PL == 0) -#define MG1_5_115PL ~(1 << 14) -#else -#define MG1_5_115PL 0xFFFF -#endif - -#if (G1_16PL >= G1_5PL) || (G1_16PL == 0) -#define MG1_5_116PL ~(1 << 15) -#else -#define MG1_5_116PL 0xFFFF -#endif - -#define MG1_5_15PL 0xFFEF -#define MG1_5 (MG1_5_11PL & MG1_5_12PL & MG1_5_13PL & MG1_5_14PL & \ - MG1_5_15PL & MG1_5_16PL & MG1_5_17PL & MG1_5_18PL & \ - MG1_5_19PL & MG1_5_110PL & MG1_5_111PL & MG1_5_112PL & \ - MG1_5_113PL & MG1_5_114PL & MG1_5_115PL & MG1_5_116PL) -// End of MG1_5: -// Beginning of MG16: -#if (G1_1PL >= G1_6PL) || (G1_1PL == 0) -#define MG1_6_11PL ~(1 << 0) -#else -#define MG1_6_11PL 0xFFFF -#endif - -#if (G1_2PL >= G1_6PL) || (G1_2PL == 0) -#define MG1_6_12PL ~(1 << 1) -#else -#define MG1_6_12PL 0xFFFF -#endif - -#if (G1_3PL >= G1_6PL) || (G1_3PL == 0) -#define MG1_6_13PL ~(1 << 2) -#else -#define MG1_6_13PL 0xFFFF -#endif - -#if (G1_4PL >= G1_6PL) || (G1_4PL == 0) -#define MG1_6_14PL ~(1 << 3) -#else -#define MG1_6_14PL 0xFFFF -#endif - -#if (G1_5PL >= G1_6PL) || (G1_5PL == 0) -#define MG1_6_15PL ~(1 << 4) -#else -#define MG1_6_15PL 0xFFFF -#endif - -#if (G1_7PL >= G1_6PL) || (G1_7PL == 0) -#define MG1_6_17PL ~(1 << 6) -#else -#define MG1_6_17PL 0xFFFF -#endif - -#if (G1_8PL >= G1_6PL) || (G1_8PL == 0) -#define MG1_6_18PL ~(1 << 7) -#else -#define MG1_6_18PL 0xFFFF -#endif - -#if (G1_9PL >= G1_6PL) || (G1_9PL == 0) -#define MG1_6_19PL ~(1 << 8) -#else -#define MG1_6_19PL 0xFFFF -#endif - -#if (G1_10PL >= G1_6PL) || (G1_10PL == 0) -#define MG1_6_110PL ~(1 << 9) -#else -#define MG1_6_110PL 0xFFFF -#endif - -#if (G1_11PL >= G1_6PL) || (G1_11PL == 0) -#define MG1_6_111PL ~(1 << 10) -#else -#define MG1_6_111PL 0xFFFF -#endif - -#if (G1_12PL >= G1_6PL) || (G1_12PL == 0) -#define MG1_6_112PL ~(1 << 11) -#else -#define MG1_6_112PL 0xFFFF -#endif - -#if (G1_13PL >= G1_6PL) || (G1_13PL == 0) -#define MG1_6_113PL ~(1 << 12) -#else -#define MG1_6_113PL 0xFFFF -#endif - -#if (G1_14PL >= G1_6PL) || (G1_14PL == 0) -#define MG1_6_114PL ~(1 << 13) -#else -#define MG1_6_114PL 0xFFFF -#endif - -#if (G1_15PL >= G1_6PL) || (G1_15PL == 0) -#define MG1_6_115PL ~(1 << 14) -#else -#define MG1_6_115PL 0xFFFF -#endif - -#if (G1_16PL >= G1_6PL) || (G1_16PL == 0) -#define MG1_6_116PL ~(1 << 15) -#else -#define MG1_6_116PL 0xFFFF -#endif - -#define MG1_6_16PL 0xFFDF -#define MG1_6 (MG1_6_11PL & MG1_6_12PL & MG1_6_13PL & MG1_6_14PL & \ - MG1_6_15PL & MG1_6_16PL & MG1_6_17PL & MG1_6_18PL & \ - MG1_6_19PL & MG1_6_110PL & MG1_6_111PL & MG1_6_112PL & \ - MG1_6_113PL & MG1_6_114PL & MG1_6_115PL & MG1_6_116PL) -// End of MG1_6: -// Beginning of MG17: -#if (G1_1PL >= G1_7PL) || (G1_1PL == 0) -#define MG1_7_11PL ~(1 << 0) -#else -#define MG1_7_11PL 0xFFFF -#endif - -#if (G1_2PL >= G1_7PL) || (G1_2PL == 0) -#define MG1_7_12PL ~(1 << 1) -#else -#define MG1_7_12PL 0xFFFF -#endif - -#if (G1_3PL >= G1_7PL) || (G1_3PL == 0) -#define MG1_7_13PL ~(1 << 2) -#else -#define MG1_7_13PL 0xFFFF -#endif - -#if (G1_4PL >= G1_7PL) || (G1_4PL == 0) -#define MG1_7_14PL ~(1 << 3) -#else -#define MG1_7_14PL 0xFFFF -#endif - -#if (G1_5PL >= G1_7PL) || (G1_5PL == 0) -#define MG1_7_15PL ~(1 << 4) -#else -#define MG1_7_15PL 0xFFFF -#endif - -#if (G1_6PL >= G1_7PL) || (G1_6PL == 0) -#define MG1_7_16PL ~(1 << 5) -#else -#define MG1_7_16PL 0xFFFF -#endif - -#if (G1_8PL >= G1_7PL) || (G1_8PL == 0) -#define MG1_7_18PL ~(1 << 7) -#else -#define MG1_7_18PL 0xFFFF -#endif - -#if (G1_9PL >= G1_7PL) || (G1_9PL == 0) -#define MG1_7_19PL ~(1 << 8) -#else -#define MG1_7_19PL 0xFFFF -#endif - -#if (G1_10PL >= G1_7PL) || (G1_10PL == 0) -#define MG1_7_110PL ~(1 << 9) -#else -#define MG1_7_110PL 0xFFFF -#endif - -#if (G1_11PL >= G1_7PL) || (G1_11PL == 0) -#define MG1_7_111PL ~(1 << 10) -#else -#define MG1_7_111PL 0xFFFF -#endif - -#if (G1_12PL >= G1_7PL) || (G1_12PL == 0) -#define MG1_7_112PL ~(1 << 11) -#else -#define MG1_7_112PL 0xFFFF -#endif - -#if (G1_13PL >= G1_7PL) || (G1_13PL == 0) -#define MG1_7_113PL ~(1 << 12) -#else -#define MG1_7_113PL 0xFFFF -#endif - -#if (G1_14PL >= G1_7PL) || (G1_14PL == 0) -#define MG1_7_114PL ~(1 << 13) -#else -#define MG1_7_114PL 0xFFFF -#endif - -#if (G1_15PL >= G1_7PL) || (G1_15PL == 0) -#define MG1_7_115PL ~(1 << 14) -#else -#define MG1_7_115PL 0xFFFF -#endif - -#if (G1_16PL >= G1_7PL) || (G1_16PL == 0) -#define MG1_7_116PL ~(1 << 15) -#else -#define MG1_7_116PL 0xFFFF -#endif - -#define MG1_7_17PL 0xFFBF -#define MG1_7 (MG1_7_11PL & MG1_7_12PL & MG1_7_13PL & MG1_7_14PL & \ - MG1_7_15PL & MG1_7_16PL & MG1_7_17PL & MG1_7_18PL & \ - MG1_7_19PL & MG1_7_110PL & MG1_7_111PL & MG1_7_112PL & \ - MG1_7_113PL & MG1_7_114PL & MG1_7_115PL & MG1_7_116PL) -// End of MG1_7: -// Beginning of MG18: -#if (G1_1PL >= G1_8PL) || (G1_1PL == 0) -#define MG1_8_11PL ~(1 << 0) -#else -#define MG1_8_11PL 0xFFFF -#endif - -#if (G1_2PL >= G1_8PL) || (G1_2PL == 0) -#define MG1_8_12PL ~(1 << 1) -#else -#define MG1_8_12PL 0xFFFF -#endif - -#if (G1_3PL >= G1_8PL) || (G1_3PL == 0) -#define MG1_8_13PL ~(1 << 2) -#else -#define MG1_8_13PL 0xFFFF -#endif - -#if (G1_4PL >= G1_8PL) || (G1_4PL == 0) -#define MG1_8_14PL ~(1 << 3) -#else -#define MG1_8_14PL 0xFFFF -#endif - -#if (G1_5PL >= G1_8PL) || (G1_5PL == 0) -#define MG1_8_15PL ~(1 << 4) -#else -#define MG1_8_15PL 0xFFFF -#endif - -#if (G1_6PL >= G1_8PL) || (G1_6PL == 0) -#define MG1_8_16PL ~(1 << 5) -#else -#define MG1_8_16PL 0xFFFF -#endif - -#if (G1_7PL >= G1_8PL) || (G1_7PL == 0) -#define MG1_8_17PL ~(1 << 6) -#else -#define MG1_8_17PL 0xFFFF -#endif - -#if (G1_9PL >= G1_8PL) || (G1_9PL == 0) -#define MG1_8_19PL ~(1 << 8) -#else -#define MG1_8_19PL 0xFFFF -#endif - -#if (G1_10PL >= G1_8PL) || (G1_10PL == 0) -#define MG1_8_110PL ~(1 << 9) -#else -#define MG1_8_110PL 0xFFFF -#endif - -#if (G1_11PL >= G1_8PL) || (G1_11PL == 0) -#define MG1_8_111PL ~(1 << 10) -#else -#define MG1_8_111PL 0xFFFF -#endif - -#if (G1_12PL >= G1_8PL) || (G1_12PL == 0) -#define MG1_8_112PL ~(1 << 11) -#else -#define MG1_8_112PL 0xFFFF -#endif - -#if (G1_13PL >= G1_8PL) || (G1_13PL == 0) -#define MG1_8_113PL ~(1 << 12) -#else -#define MG1_8_113PL 0xFFFF -#endif - -#if (G1_14PL >= G1_8PL) || (G1_14PL == 0) -#define MG1_8_114PL ~(1 << 13) -#else -#define MG1_8_114PL 0xFFFF -#endif - -#if (G1_15PL >= G1_8PL) || (G1_15PL == 0) -#define MG1_8_115PL ~(1 << 14) -#else -#define MG1_8_115PL 0xFFFF -#endif - -#if (G1_16PL >= G1_8PL) || (G1_16PL == 0) -#define MG1_8_116PL ~(1 << 15) -#else -#define MG1_8_116PL 0xFFFF -#endif - -#define MG1_8_18PL 0xFF7F -#define MG1_8 (MG1_8_11PL & MG1_8_12PL & MG1_8_13PL & MG1_8_14PL & \ - MG1_8_15PL & MG1_8_16PL & MG1_8_17PL & MG1_8_18PL & \ - MG1_8_19PL & MG1_8_110PL & MG1_8_111PL & MG1_8_112PL & \ - MG1_8_113PL & MG1_8_114PL & MG1_8_115PL & MG1_8_116PL) -// End of MG1_8: -// Beginning of MG19: -#if (G1_1PL >= G1_9PL) || (G1_1PL == 0) -#define MG1_9_11PL ~(1 << 0) -#else -#define MG1_9_11PL 0xFFFF -#endif - -#if (G1_2PL >= G1_9PL) || (G1_2PL == 0) -#define MG1_9_12PL ~(1 << 1) -#else -#define MG1_9_12PL 0xFFFF -#endif - -#if (G1_3PL >= G1_9PL) || (G1_3PL == 0) -#define MG1_9_13PL ~(1 << 2) -#else -#define MG1_9_13PL 0xFFFF -#endif - -#if (G1_4PL >= G1_9PL) || (G1_4PL == 0) -#define MG1_9_14PL ~(1 << 3) -#else -#define MG1_9_14PL 0xFFFF -#endif - -#if (G1_5PL >= G1_9PL) || (G1_5PL == 0) -#define MG1_9_15PL ~(1 << 4) -#else -#define MG1_9_15PL 0xFFFF -#endif - -#if (G1_6PL >= G1_9PL) || (G1_6PL == 0) -#define MG1_9_16PL ~(1 << 5) -#else -#define MG1_9_16PL 0xFFFF -#endif - -#if (G1_7PL >= G1_9PL) || (G1_7PL == 0) -#define MG1_9_17PL ~(1 << 6) -#else -#define MG1_9_17PL 0xFFFF -#endif - -#if (G1_8PL >= G1_9PL) || (G1_8PL == 0) -#define MG1_9_18PL ~(1 << 7) -#else -#define MG1_9_18PL 0xFFFF -#endif - -#if (G1_10PL >= G1_9PL) || (G1_10PL == 0) -#define MG1_9_110PL ~(1 << 9) -#else -#define MG1_9_110PL 0xFFFF -#endif - -#if (G1_11PL >= G1_9PL) || (G1_11PL == 0) -#define MG1_9_111PL ~(1 << 10) -#else -#define MG1_9_111PL 0xFFFF -#endif - -#if (G1_12PL >= G1_9PL) || (G1_12PL == 0) -#define MG1_9_112PL ~(1 << 11) -#else -#define MG1_9_112PL 0xFFFF -#endif - -#if (G1_13PL >= G1_9PL) || (G1_13PL == 0) -#define MG1_9_113PL ~(1 << 12) -#else -#define MG1_9_113PL 0xFFFF -#endif - -#if (G1_14PL >= G1_9PL) || (G1_14PL == 0) -#define MG1_9_114PL ~(1 << 13) -#else -#define MG1_9_114PL 0xFFFF -#endif - -#if (G1_15PL >= G1_9PL) || (G1_15PL == 0) -#define MG1_9_115PL ~(1 << 14) -#else -#define MG1_9_115PL 0xFFFF -#endif - -#if (G1_16PL >= G1_9PL) || (G1_16PL == 0) -#define MG1_9_116PL ~(1 << 15) -#else -#define MG1_9_116PL 0xFFFF -#endif - -#define MG1_9_19PL 0xFEFF -#define MG1_9 (MG1_9_11PL & MG1_9_12PL & MG1_9_13PL & MG1_9_14PL & \ - MG1_9_15PL & MG1_9_16PL & MG1_9_17PL & MG1_9_18PL & \ - MG1_9_19PL & MG1_9_110PL & MG1_9_111PL & MG1_9_112PL & \ - MG1_9_113PL & MG1_9_114PL & MG1_9_115PL & MG1_9_116PL) -// End of MG1_9: -// Beginning of MG110: -#if (G1_1PL >= G1_10PL) || (G1_1PL == 0) -#define MG1_10_11PL ~(1 << 0) -#else -#define MG1_10_11PL 0xFFFF -#endif - -#if (G1_2PL >= G1_10PL) || (G1_2PL == 0) -#define MG1_10_12PL ~(1 << 1) -#else -#define MG1_10_12PL 0xFFFF -#endif - -#if (G1_3PL >= G1_10PL) || (G1_3PL == 0) -#define MG1_10_13PL ~(1 << 2) -#else -#define MG1_10_13PL 0xFFFF -#endif - -#if (G1_4PL >= G1_10PL) || (G1_4PL == 0) -#define MG1_10_14PL ~(1 << 3) -#else -#define MG1_10_14PL 0xFFFF -#endif - -#if (G1_5PL >= G1_10PL) || (G1_5PL == 0) -#define MG1_10_15PL ~(1 << 4) -#else -#define MG1_10_15PL 0xFFFF -#endif - -#if (G1_6PL >= G1_10PL) || (G1_6PL == 0) -#define MG1_10_16PL ~(1 << 5) -#else -#define MG1_10_16PL 0xFFFF -#endif - -#if (G1_7PL >= G1_10PL) || (G1_7PL == 0) -#define MG1_10_17PL ~(1 << 6) -#else -#define MG1_10_17PL 0xFFFF -#endif - -#if (G1_8PL >= G1_10PL) || (G1_8PL == 0) -#define MG1_10_18PL ~(1 << 7) -#else -#define MG1_10_18PL 0xFFFF -#endif - -#if (G1_9PL >= G1_10PL) || (G1_9PL == 0) -#define MG1_10_19PL ~(1 << 8) -#else -#define MG1_10_19PL 0xFFFF -#endif - -#if (G1_11PL >= G1_10PL) || (G1_11PL == 0) -#define MG1_10_111PL ~(1 << 10) -#else -#define MG1_10_111PL 0xFFFF -#endif - -#if (G1_12PL >= G1_10PL) || (G1_12PL == 0) -#define MG1_10_112PL ~(1 << 11) -#else -#define MG1_10_112PL 0xFFFF -#endif - -#if (G1_13PL >= G1_10PL) || (G1_13PL == 0) -#define MG1_10_113PL ~(1 << 12) -#else -#define MG1_10_113PL 0xFFFF -#endif - -#if (G1_14PL >= G1_10PL) || (G1_14PL == 0) -#define MG1_10_114PL ~(1 << 13) -#else -#define MG1_10_114PL 0xFFFF -#endif - -#if (G1_15PL >= G1_10PL) || (G1_15PL == 0) -#define MG1_10_115PL ~(1 << 14) -#else -#define MG1_10_115PL 0xFFFF -#endif - -#if (G1_16PL >= G1_10PL) || (G1_16PL == 0) -#define MG1_10_116PL ~(1 << 15) -#else -#define MG1_10_116PL 0xFFFF -#endif - -#define MG1_10_110PL 0xFDFF -#define MG1_10 (MG1_10_11PL & MG1_10_12PL & MG1_10_13PL & MG1_10_14PL & \ - MG1_10_15PL & MG1_10_16PL & MG1_10_17PL & MG1_10_18PL & \ - MG1_10_19PL & MG1_10_110PL & MG1_10_111PL & MG1_10_112PL & \ - MG1_10_113PL & MG1_10_114PL & MG1_10_115PL & MG1_10_116PL) -// End of MG1_10: -// Beginning of MG111: -#if (G1_1PL >= G1_11PL) || (G1_1PL == 0) -#define MG1_11_11PL ~(1 << 0) -#else -#define MG1_11_11PL 0xFFFF -#endif - -#if (G1_2PL >= G1_11PL) || (G1_2PL == 0) -#define MG1_11_12PL ~(1 << 1) -#else -#define MG1_11_12PL 0xFFFF -#endif - -#if (G1_3PL >= G1_11PL) || (G1_3PL == 0) -#define MG1_11_13PL ~(1 << 2) -#else -#define MG1_11_13PL 0xFFFF -#endif - -#if (G1_4PL >= G1_11PL) || (G1_4PL == 0) -#define MG1_11_14PL ~(1 << 3) -#else -#define MG1_11_14PL 0xFFFF -#endif - -#if (G1_5PL >= G1_11PL) || (G1_5PL == 0) -#define MG1_11_15PL ~(1 << 4) -#else -#define MG1_11_15PL 0xFFFF -#endif - -#if (G1_6PL >= G1_11PL) || (G1_6PL == 0) -#define MG1_11_16PL ~(1 << 5) -#else -#define MG1_11_16PL 0xFFFF -#endif - -#if (G1_7PL >= G1_11PL) || (G1_7PL == 0) -#define MG1_11_17PL ~(1 << 6) -#else -#define MG1_11_17PL 0xFFFF -#endif - -#if (G1_8PL >= G1_11PL) || (G1_8PL == 0) -#define MG1_11_18PL ~(1 << 7) -#else -#define MG1_11_18PL 0xFFFF -#endif - -#if (G1_9PL >= G1_11PL) || (G1_9PL == 0) -#define MG1_11_19PL ~(1 << 8) -#else -#define MG1_11_19PL 0xFFFF -#endif - -#if (G1_10PL >= G1_11PL) || (G1_10PL == 0) -#define MG1_11_110PL ~(1 << 9) -#else -#define MG1_11_110PL 0xFFFF -#endif - -#if (G1_12PL >= G1_11PL) || (G1_12PL == 0) -#define MG1_11_112PL ~(1 << 11) -#else -#define MG1_11_112PL 0xFFFF -#endif - -#if (G1_13PL >= G1_11PL) || (G1_13PL == 0) -#define MG1_11_113PL ~(1 << 12) -#else -#define MG1_11_113PL 0xFFFF -#endif - -#if (G1_14PL >= G1_11PL) || (G1_14PL == 0) -#define MG1_11_114PL ~(1 << 13) -#else -#define MG1_11_114PL 0xFFFF -#endif - -#if (G1_15PL >= G1_11PL) || (G1_15PL == 0) -#define MG1_11_115PL ~(1 << 14) -#else -#define MG1_11_115PL 0xFFFF -#endif - -#if (G1_16PL >= G1_11PL) || (G1_16PL == 0) -#define MG1_11_116PL ~(1 << 15) -#else -#define MG1_11_116PL 0xFFFF -#endif - -#define MG1_11_111PL 0xFBFF -#define MG1_11 (MG1_11_11PL & MG1_11_12PL & MG1_11_13PL & MG1_11_14PL & \ - MG1_11_15PL & MG1_11_16PL & MG1_11_17PL & MG1_11_18PL & \ - MG1_11_19PL & MG1_11_110PL & MG1_11_111PL & MG1_11_112PL & \ - MG1_11_113PL & MG1_11_114PL & MG1_11_115PL & MG1_11_116PL) -// End of MG1_11: -// Beginning of MG112: -#if (G1_1PL >= G1_12PL) || (G1_1PL == 0) -#define MG1_12_11PL ~(1 << 0) -#else -#define MG1_12_11PL 0xFFFF -#endif - -#if (G1_2PL >= G1_12PL) || (G1_2PL == 0) -#define MG1_12_12PL ~(1 << 1) -#else -#define MG1_12_12PL 0xFFFF -#endif - -#if (G1_3PL >= G1_12PL) || (G1_3PL == 0) -#define MG1_12_13PL ~(1 << 2) -#else -#define MG1_12_13PL 0xFFFF -#endif - -#if (G1_4PL >= G1_12PL) || (G1_4PL == 0) -#define MG1_12_14PL ~(1 << 3) -#else -#define MG1_12_14PL 0xFFFF -#endif - -#if (G1_5PL >= G1_12PL) || (G1_5PL == 0) -#define MG1_12_15PL ~(1 << 4) -#else -#define MG1_12_15PL 0xFFFF -#endif - -#if (G1_6PL >= G1_12PL) || (G1_6PL == 0) -#define MG1_12_16PL ~(1 << 5) -#else -#define MG1_12_16PL 0xFFFF -#endif - -#if (G1_7PL >= G1_12PL) || (G1_7PL == 0) -#define MG1_12_17PL ~(1 << 6) -#else -#define MG1_12_17PL 0xFFFF -#endif - -#if (G1_8PL >= G1_12PL) || (G1_8PL == 0) -#define MG1_12_18PL ~(1 << 7) -#else -#define MG1_12_18PL 0xFFFF -#endif - -#if (G1_9PL >= G1_12PL) || (G1_9PL == 0) -#define MG1_12_19PL ~(1 << 8) -#else -#define MG1_12_19PL 0xFFFF -#endif - -#if (G1_10PL >= G1_12PL) || (G1_10PL == 0) -#define MG1_12_110PL ~(1 << 9) -#else -#define MG1_12_110PL 0xFFFF -#endif - -#if (G1_11PL >= G1_12PL) || (G1_11PL == 0) -#define MG1_12_111PL ~(1 << 10) -#else -#define MG1_12_111PL 0xFFFF -#endif - -#if (G1_13PL >= G1_12PL) || (G1_13PL == 0) -#define MG1_12_113PL ~(1 << 12) -#else -#define MG1_12_113PL 0xFFFF -#endif - -#if (G1_14PL >= G1_12PL) || (G1_14PL == 0) -#define MG1_12_114PL ~(1 << 13) -#else -#define MG1_12_114PL 0xFFFF -#endif - -#if (G1_15PL >= G1_12PL) || (G1_15PL == 0) -#define MG1_12_115PL ~(1 << 14) -#else -#define MG1_12_115PL 0xFFFF -#endif - -#if (G1_16PL >= G1_12PL) || (G1_16PL == 0) -#define MG1_12_116PL ~(1 << 15) -#else -#define MG1_12_116PL 0xFFFF -#endif - -#define MG1_12_112PL 0xF7FF -#define MG1_12 (MG1_12_11PL & MG1_12_12PL & MG1_12_13PL & MG1_12_14PL & \ - MG1_12_15PL & MG1_12_16PL & MG1_12_17PL & MG1_12_18PL & \ - MG1_12_19PL & MG1_12_110PL & MG1_12_111PL & MG1_12_112PL & \ - MG1_12_113PL & MG1_12_114PL & MG1_12_115PL & MG1_12_116PL) -// End of MG1_12: -// Beginning of MG113: -#if (G1_1PL >= G1_13PL) || (G1_1PL == 0) -#define MG1_13_11PL ~(1 << 0) -#else -#define MG1_13_11PL 0xFFFF -#endif - -#if (G1_2PL >= G1_13PL) || (G1_2PL == 0) -#define MG1_13_12PL ~(1 << 1) -#else -#define MG1_13_12PL 0xFFFF -#endif - -#if (G1_3PL >= G1_13PL) || (G1_3PL == 0) -#define MG1_13_13PL ~(1 << 2) -#else -#define MG1_13_13PL 0xFFFF -#endif - -#if (G1_4PL >= G1_13PL) || (G1_4PL == 0) -#define MG1_13_14PL ~(1 << 3) -#else -#define MG1_13_14PL 0xFFFF -#endif - -#if (G1_5PL >= G1_13PL) || (G1_5PL == 0) -#define MG1_13_15PL ~(1 << 4) -#else -#define MG1_13_15PL 0xFFFF -#endif - -#if (G1_6PL >= G1_13PL) || (G1_6PL == 0) -#define MG1_13_16PL ~(1 << 5) -#else -#define MG1_13_16PL 0xFFFF -#endif - -#if (G1_7PL >= G1_13PL) || (G1_7PL == 0) -#define MG1_13_17PL ~(1 << 6) -#else -#define MG1_13_17PL 0xFFFF -#endif - -#if (G1_8PL >= G1_13PL) || (G1_8PL == 0) -#define MG1_13_18PL ~(1 << 7) -#else -#define MG1_13_18PL 0xFFFF -#endif - -#if (G1_9PL >= G1_13PL) || (G1_9PL == 0) -#define MG1_13_19PL ~(1 << 8) -#else -#define MG1_13_19PL 0xFFFF -#endif - -#if (G1_10PL >= G1_13PL) || (G1_10PL == 0) -#define MG1_13_110PL ~(1 << 9) -#else -#define MG1_13_110PL 0xFFFF -#endif - -#if (G1_11PL >= G1_13PL) || (G1_11PL == 0) -#define MG1_13_111PL ~(1 << 10) -#else -#define MG1_13_111PL 0xFFFF -#endif - -#if (G1_12PL >= G1_13PL) || (G1_12PL == 0) -#define MG1_13_112PL ~(1 << 11) -#else -#define MG1_13_112PL 0xFFFF -#endif - -#if (G1_14PL >= G1_13PL) || (G1_14PL == 0) -#define MG1_13_114PL ~(1 << 13) -#else -#define MG1_13_114PL 0xFFFF -#endif - -#if (G1_15PL >= G1_13PL) || (G1_15PL == 0) -#define MG1_13_115PL ~(1 << 14) -#else -#define MG1_13_115PL 0xFFFF -#endif - -#if (G1_16PL >= G1_13PL) || (G1_16PL == 0) -#define MG1_13_116PL ~(1 << 15) -#else -#define MG1_13_116PL 0xFFFF -#endif - -#define MG1_13_113PL 0xEFFF -#define MG1_13 (MG1_13_11PL & MG1_13_12PL & MG1_13_13PL & MG1_13_14PL & \ - MG1_13_15PL & MG1_13_16PL & MG1_13_17PL & MG1_13_18PL & \ - MG1_13_19PL & MG1_13_110PL & MG1_13_111PL & MG1_13_112PL & \ - MG1_13_113PL & MG1_13_114PL & MG1_13_115PL & MG1_13_116PL) -// End of MG1_13: -// Beginning of MG114: -#if (G1_1PL >= G1_14PL) || (G1_1PL == 0) -#define MG1_14_11PL ~(1 << 0) -#else -#define MG1_14_11PL 0xFFFF -#endif - -#if (G1_2PL >= G1_14PL) || (G1_2PL == 0) -#define MG1_14_12PL ~(1 << 1) -#else -#define MG1_14_12PL 0xFFFF -#endif - -#if (G1_3PL >= G1_14PL) || (G1_3PL == 0) -#define MG1_14_13PL ~(1 << 2) -#else -#define MG1_14_13PL 0xFFFF -#endif - -#if (G1_4PL >= G1_14PL) || (G1_4PL == 0) -#define MG1_14_14PL ~(1 << 3) -#else -#define MG1_14_14PL 0xFFFF -#endif - -#if (G1_5PL >= G1_14PL) || (G1_5PL == 0) -#define MG1_14_15PL ~(1 << 4) -#else -#define MG1_14_15PL 0xFFFF -#endif - -#if (G1_6PL >= G1_14PL) || (G1_6PL == 0) -#define MG1_14_16PL ~(1 << 5) -#else -#define MG1_14_16PL 0xFFFF -#endif - -#if (G1_7PL >= G1_14PL) || (G1_7PL == 0) -#define MG1_14_17PL ~(1 << 6) -#else -#define MG1_14_17PL 0xFFFF -#endif - -#if (G1_8PL >= G1_14PL) || (G1_8PL == 0) -#define MG1_14_18PL ~(1 << 7) -#else -#define MG1_14_18PL 0xFFFF -#endif - -#if (G1_9PL >= G1_14PL) || (G1_9PL == 0) -#define MG1_14_19PL ~(1 << 8) -#else -#define MG1_14_19PL 0xFFFF -#endif - -#if (G1_10PL >= G1_14PL) || (G1_10PL == 0) -#define MG1_14_110PL ~(1 << 9) -#else -#define MG1_14_110PL 0xFFFF -#endif - -#if (G1_11PL >= G1_14PL) || (G1_11PL == 0) -#define MG1_14_111PL ~(1 << 10) -#else -#define MG1_14_111PL 0xFFFF -#endif - -#if (G1_12PL >= G1_14PL) || (G1_12PL == 0) -#define MG1_14_112PL ~(1 << 11) -#else -#define MG1_14_112PL 0xFFFF -#endif - -#if (G1_13PL >= G1_14PL) || (G1_13PL == 0) -#define MG1_14_113PL ~(1 << 12) -#else -#define MG1_14_113PL 0xFFFF -#endif - -#if (G1_15PL >= G1_14PL) || (G1_15PL == 0) -#define MG1_14_115PL ~(1 << 14) -#else -#define MG1_14_115PL 0xFFFF -#endif - -#if (G1_16PL >= G1_14PL) || (G1_16PL == 0) -#define MG1_14_116PL ~(1 << 15) -#else -#define MG1_14_116PL 0xFFFF -#endif - -#define MG1_14_114PL 0xDFFF -#define MG1_14 (MG1_14_11PL & MG1_14_12PL & MG1_14_13PL & MG1_14_14PL & \ - MG1_14_15PL & MG1_14_16PL & MG1_14_17PL & MG1_14_18PL & \ - MG1_14_19PL & MG1_14_110PL & MG1_14_111PL & MG1_14_112PL & \ - MG1_14_113PL & MG1_14_114PL & MG1_14_115PL & MG1_14_116PL) -// End of MG1_14: -// Beginning of MG115: -#if (G1_1PL >= G1_15PL) || (G1_1PL == 0) -#define MG1_15_11PL ~(1 << 0) -#else -#define MG1_15_11PL 0xFFFF -#endif - -#if (G1_2PL >= G1_15PL) || (G1_2PL == 0) -#define MG1_15_12PL ~(1 << 1) -#else -#define MG1_15_12PL 0xFFFF -#endif - -#if (G1_3PL >= G1_15PL) || (G1_3PL == 0) -#define MG1_15_13PL ~(1 << 2) -#else -#define MG1_15_13PL 0xFFFF -#endif - -#if (G1_4PL >= G1_15PL) || (G1_4PL == 0) -#define MG1_15_14PL ~(1 << 3) -#else -#define MG1_15_14PL 0xFFFF -#endif - -#if (G1_5PL >= G1_15PL) || (G1_5PL == 0) -#define MG1_15_15PL ~(1 << 4) -#else -#define MG1_15_15PL 0xFFFF -#endif - -#if (G1_6PL >= G1_15PL) || (G1_6PL == 0) -#define MG1_15_16PL ~(1 << 5) -#else -#define MG1_15_16PL 0xFFFF -#endif - -#if (G1_7PL >= G1_15PL) || (G1_7PL == 0) -#define MG1_15_17PL ~(1 << 6) -#else -#define MG1_15_17PL 0xFFFF -#endif - -#if (G1_8PL >= G1_15PL) || (G1_8PL == 0) -#define MG1_15_18PL ~(1 << 7) -#else -#define MG1_15_18PL 0xFFFF -#endif - -#if (G1_9PL >= G1_15PL) || (G1_9PL == 0) -#define MG1_15_19PL ~(1 << 8) -#else -#define MG1_15_19PL 0xFFFF -#endif - -#if (G1_10PL >= G1_15PL) || (G1_10PL == 0) -#define MG1_15_110PL ~(1 << 9) -#else -#define MG1_15_110PL 0xFFFF -#endif - -#if (G1_11PL >= G1_15PL) || (G1_11PL == 0) -#define MG1_15_111PL ~(1 << 10) -#else -#define MG1_15_111PL 0xFFFF -#endif - -#if (G1_12PL >= G1_15PL) || (G1_12PL == 0) -#define MG1_15_112PL ~(1 << 11) -#else -#define MG1_15_112PL 0xFFFF -#endif - -#if (G1_13PL >= G1_15PL) || (G1_13PL == 0) -#define MG1_15_113PL ~(1 << 12) -#else -#define MG1_15_113PL 0xFFFF -#endif - -#if (G1_14PL >= G1_15PL) || (G1_14PL == 0) -#define MG1_15_114PL ~(1 << 13) -#else -#define MG1_15_114PL 0xFFFF -#endif - -#if (G1_16PL >= G1_15PL) || (G1_16PL == 0) -#define MG1_15_116PL ~(1 << 15) -#else -#define MG1_15_116PL 0xFFFF -#endif - -#define MG1_15_115PL 0xBFFF -#define MG1_15 (MG1_15_11PL & MG1_15_12PL & MG1_15_13PL & MG1_15_14PL & \ - MG1_15_15PL & MG1_15_16PL & MG1_15_17PL & MG1_15_18PL & \ - MG1_15_19PL & MG1_15_110PL & MG1_15_111PL & MG1_15_112PL & \ - MG1_15_113PL & MG1_15_114PL & MG1_15_115PL & MG1_15_116PL) -// End of MG1_15: -// Beginning of MG116: -#if (G1_1PL >= G1_16PL) || (G1_1PL == 0) -#define MG1_16_11PL ~(1 << 0) -#else -#define MG1_16_11PL 0xFFFF -#endif - -#if (G1_2PL >= G1_16PL) || (G1_2PL == 0) -#define MG1_16_12PL ~(1 << 1) -#else -#define MG1_16_12PL 0xFFFF -#endif - -#if (G1_3PL >= G1_16PL) || (G1_3PL == 0) -#define MG1_16_13PL ~(1 << 2) -#else -#define MG1_16_13PL 0xFFFF -#endif - -#if (G1_4PL >= G1_16PL) || (G1_4PL == 0) -#define MG1_16_14PL ~(1 << 3) -#else -#define MG1_16_14PL 0xFFFF -#endif - -#if (G1_5PL >= G1_16PL) || (G1_5PL == 0) -#define MG1_16_15PL ~(1 << 4) -#else -#define MG1_16_15PL 0xFFFF -#endif - -#if (G1_6PL >= G1_16PL) || (G1_6PL == 0) -#define MG1_16_16PL ~(1 << 5) -#else -#define MG1_16_16PL 0xFFFF -#endif - -#if (G1_7PL >= G1_16PL) || (G1_7PL == 0) -#define MG1_16_17PL ~(1 << 6) -#else -#define MG1_16_17PL 0xFFFF -#endif - -#if (G1_8PL >= G1_16PL) || (G1_8PL == 0) -#define MG1_16_18PL ~(1 << 7) -#else -#define MG1_16_18PL 0xFFFF -#endif - -#if (G1_9PL >= G1_16PL) || (G1_9PL == 0) -#define MG1_16_19PL ~(1 << 8) -#else -#define MG1_16_19PL 0xFFFF -#endif - -#if (G1_10PL >= G1_16PL) || (G1_10PL == 0) -#define MG1_16_110PL ~(1 << 9) -#else -#define MG1_16_110PL 0xFFFF -#endif - -#if (G1_11PL >= G1_16PL) || (G1_11PL == 0) -#define MG1_16_111PL ~(1 << 10) -#else -#define MG1_16_111PL 0xFFFF -#endif - -#if (G1_12PL >= G1_16PL) || (G1_12PL == 0) -#define MG1_16_112PL ~(1 << 11) -#else -#define MG1_16_112PL 0xFFFF -#endif - -#if (G1_13PL >= G1_16PL) || (G1_13PL == 0) -#define MG1_16_113PL ~(1 << 12) -#else -#define MG1_16_113PL 0xFFFF -#endif - -#if (G1_14PL >= G1_16PL) || (G1_14PL == 0) -#define MG1_16_114PL ~(1 << 13) -#else -#define MG1_16_114PL 0xFFFF -#endif - -#if (G1_15PL >= G1_16PL) || (G1_15PL == 0) -#define MG1_16_115PL ~(1 << 14) -#else -#define MG1_16_115PL 0xFFFF -#endif - -#define MG1_16_116PL 0x7FFF -#define MG1_16 (MG1_16_11PL & MG1_16_12PL & MG1_16_13PL & MG1_16_14PL & \ - MG1_16_15PL & MG1_16_16PL & MG1_16_17PL & MG1_16_18PL & \ - MG1_16_19PL & MG1_16_110PL & MG1_16_111PL & MG1_16_112PL & \ - MG1_16_113PL & MG1_16_114PL & MG1_16_115PL & MG1_16_116PL) -// End of MG1_16: - - -// -// Automatically generate PIEIER2 interrupt masks MG21 to MG216: -// - -// Beginning of MG21: -#if (G2_2PL >= G2_1PL) || (G2_2PL == 0) -#define MG2_1_12PL ~(1 << 1) -#else -#define MG2_1_12PL 0xFFFF -#endif - -#if (G2_3PL >= G2_1PL) || (G2_3PL == 0) -#define MG2_1_13PL ~(1 << 2) -#else -#define MG2_1_13PL 0xFFFF -#endif - -#if (G2_4PL >= G2_1PL) || (G2_4PL == 0) -#define MG2_1_14PL ~(1 << 3) -#else -#define MG2_1_14PL 0xFFFF -#endif - -#if (G2_5PL >= G2_1PL) || (G2_5PL == 0) -#define MG2_1_15PL ~(1 << 4) -#else -#define MG2_1_15PL 0xFFFF -#endif - -#if (G2_6PL >= G2_1PL) || (G2_6PL == 0) -#define MG2_1_16PL ~(1 << 5) -#else -#define MG2_1_16PL 0xFFFF -#endif - -#if (G2_7PL >= G2_1PL) || (G2_7PL == 0) -#define MG2_1_17PL ~(1 << 6) -#else -#define MG2_1_17PL 0xFFFF -#endif - -#if (G2_8PL >= G2_1PL) || (G2_8PL == 0) -#define MG2_1_18PL ~(1 << 7) -#else -#define MG2_1_18PL 0xFFFF -#endif - -#if (G2_9PL >= G2_1PL) || (G2_9PL == 0) -#define MG2_1_19PL ~(1 << 8) -#else -#define MG2_1_19PL 0xFFFF -#endif - -#if (G2_10PL >= G2_1PL) || (G2_10PL == 0) -#define MG2_1_110PL ~(1 << 9) -#else -#define MG2_1_110PL 0xFFFF -#endif - -#if (G2_11PL >= G2_1PL) || (G2_11PL == 0) -#define MG2_1_111PL ~(1 << 10) -#else -#define MG2_1_111PL 0xFFFF -#endif - -#if (G2_12PL >= G2_1PL) || (G2_12PL == 0) -#define MG2_1_112PL ~(1 << 11) -#else -#define MG2_1_112PL 0xFFFF -#endif - -#if (G2_13PL >= G2_1PL) || (G2_13PL == 0) -#define MG2_1_113PL ~(1 << 12) -#else -#define MG2_1_113PL 0xFFFF -#endif - -#if (G2_14PL >= G2_1PL) || (G2_14PL == 0) -#define MG2_1_114PL ~(1 << 13) -#else -#define MG2_1_114PL 0xFFFF -#endif - -#if (G2_15PL >= G2_1PL) || (G2_15PL == 0) -#define MG2_1_115PL ~(1 << 14) -#else -#define MG2_1_115PL 0xFFFF -#endif - -#if (G2_16PL >= G2_1PL) || (G2_16PL == 0) -#define MG2_1_116PL ~(1 << 15) -#else -#define MG2_1_116PL 0xFFFF -#endif - -#define MG2_1_11PL 0xFFFE -#define MG2_1 (MG2_1_11PL & MG2_1_12PL & MG2_1_13PL & MG2_1_14PL & \ - MG2_1_15PL & MG2_1_16PL & MG2_1_17PL & MG2_1_18PL & \ - MG2_1_19PL & MG2_1_110PL & MG2_1_111PL & MG2_1_112PL & \ - MG2_1_113PL & MG2_1_114PL & MG2_1_115PL & MG2_1_116PL) -// End of MG2_1: -// Beginning of MG22: -#if (G2_1PL >= G2_2PL) || (G2_1PL == 0) -#define MG2_2_11PL ~(1 << 0) -#else -#define MG2_2_11PL 0xFFFF -#endif - -#if (G2_3PL >= G2_2PL) || (G2_3PL == 0) -#define MG2_2_13PL ~(1 << 2) -#else -#define MG2_2_13PL 0xFFFF -#endif - -#if (G2_4PL >= G2_2PL) || (G2_4PL == 0) -#define MG2_2_14PL ~(1 << 3) -#else -#define MG2_2_14PL 0xFFFF -#endif - -#if (G2_5PL >= G2_2PL) || (G2_5PL == 0) -#define MG2_2_15PL ~(1 << 4) -#else -#define MG2_2_15PL 0xFFFF -#endif - -#if (G2_6PL >= G2_2PL) || (G2_6PL == 0) -#define MG2_2_16PL ~(1 << 5) -#else -#define MG2_2_16PL 0xFFFF -#endif - -#if (G2_7PL >= G2_2PL) || (G2_7PL == 0) -#define MG2_2_17PL ~(1 << 6) -#else -#define MG2_2_17PL 0xFFFF -#endif - -#if (G2_8PL >= G2_2PL) || (G2_8PL == 0) -#define MG2_2_18PL ~(1 << 7) -#else -#define MG2_2_18PL 0xFFFF -#endif - -#if (G2_9PL >= G2_2PL) || (G2_9PL == 0) -#define MG2_2_19PL ~(1 << 8) -#else -#define MG2_2_19PL 0xFFFF -#endif - -#if (G2_10PL >= G2_2PL) || (G2_10PL == 0) -#define MG2_2_110PL ~(1 << 9) -#else -#define MG2_2_110PL 0xFFFF -#endif - -#if (G2_11PL >= G2_2PL) || (G2_11PL == 0) -#define MG2_2_111PL ~(1 << 10) -#else -#define MG2_2_111PL 0xFFFF -#endif - -#if (G2_12PL >= G2_2PL) || (G2_12PL == 0) -#define MG2_2_112PL ~(1 << 11) -#else -#define MG2_2_112PL 0xFFFF -#endif - -#if (G2_13PL >= G2_2PL) || (G2_13PL == 0) -#define MG2_2_113PL ~(1 << 12) -#else -#define MG2_2_113PL 0xFFFF -#endif - -#if (G2_14PL >= G2_2PL) || (G2_14PL == 0) -#define MG2_2_114PL ~(1 << 13) -#else -#define MG2_2_114PL 0xFFFF -#endif - -#if (G2_15PL >= G2_2PL) || (G2_15PL == 0) -#define MG2_2_115PL ~(1 << 14) -#else -#define MG2_2_115PL 0xFFFF -#endif - -#if (G2_16PL >= G2_2PL) || (G2_16PL == 0) -#define MG2_2_116PL ~(1 << 15) -#else -#define MG2_2_116PL 0xFFFF -#endif - -#define MG2_2_12PL 0xFFFD -#define MG2_2 (MG2_2_11PL & MG2_2_12PL & MG2_2_13PL & MG2_2_14PL & \ - MG2_2_15PL & MG2_2_16PL & MG2_2_17PL & MG2_2_18PL & \ - MG2_2_19PL & MG2_2_110PL & MG2_2_111PL & MG2_2_112PL & \ - MG2_2_113PL & MG2_2_114PL & MG2_2_115PL & MG2_2_116PL) -// End of MG2_2: -// Beginning of MG23: -#if (G2_1PL >= G2_3PL) || (G2_1PL == 0) -#define MG2_3_11PL ~(1 << 0) -#else -#define MG2_3_11PL 0xFFFF -#endif - -#if (G2_2PL >= G2_3PL) || (G2_2PL == 0) -#define MG2_3_12PL ~(1 << 1) -#else -#define MG2_3_12PL 0xFFFF -#endif - -#if (G2_4PL >= G2_3PL) || (G2_4PL == 0) -#define MG2_3_14PL ~(1 << 3) -#else -#define MG2_3_14PL 0xFFFF -#endif - -#if (G2_5PL >= G2_3PL) || (G2_5PL == 0) -#define MG2_3_15PL ~(1 << 4) -#else -#define MG2_3_15PL 0xFFFF -#endif - -#if (G2_6PL >= G2_3PL) || (G2_6PL == 0) -#define MG2_3_16PL ~(1 << 5) -#else -#define MG2_3_16PL 0xFFFF -#endif - -#if (G2_7PL >= G2_3PL) || (G2_7PL == 0) -#define MG2_3_17PL ~(1 << 6) -#else -#define MG2_3_17PL 0xFFFF -#endif - -#if (G2_8PL >= G2_3PL) || (G2_8PL == 0) -#define MG2_3_18PL ~(1 << 7) -#else -#define MG2_3_18PL 0xFFFF -#endif - -#if (G2_9PL >= G2_3PL) || (G2_9PL == 0) -#define MG2_3_19PL ~(1 << 8) -#else -#define MG2_3_19PL 0xFFFF -#endif - -#if (G2_10PL >= G2_3PL) || (G2_10PL == 0) -#define MG2_3_110PL ~(1 << 9) -#else -#define MG2_3_110PL 0xFFFF -#endif - -#if (G2_11PL >= G2_3PL) || (G2_11PL == 0) -#define MG2_3_111PL ~(1 << 10) -#else -#define MG2_3_111PL 0xFFFF -#endif - -#if (G2_12PL >= G2_3PL) || (G2_12PL == 0) -#define MG2_3_112PL ~(1 << 11) -#else -#define MG2_3_112PL 0xFFFF -#endif - -#if (G2_13PL >= G2_3PL) || (G2_13PL == 0) -#define MG2_3_113PL ~(1 << 12) -#else -#define MG2_3_113PL 0xFFFF -#endif - -#if (G2_14PL >= G2_3PL) || (G2_14PL == 0) -#define MG2_3_114PL ~(1 << 13) -#else -#define MG2_3_114PL 0xFFFF -#endif - -#if (G2_15PL >= G2_3PL) || (G2_15PL == 0) -#define MG2_3_115PL ~(1 << 14) -#else -#define MG2_3_115PL 0xFFFF -#endif - -#if (G2_16PL >= G2_3PL) || (G2_16PL == 0) -#define MG2_3_116PL ~(1 << 15) -#else -#define MG2_3_116PL 0xFFFF -#endif - -#define MG2_3_13PL 0xFFFB -#define MG2_3 (MG2_3_11PL & MG2_3_12PL & MG2_3_13PL & MG2_3_14PL & \ - MG2_3_15PL & MG2_3_16PL & MG2_3_17PL & MG2_3_18PL & \ - MG2_3_19PL & MG2_3_110PL & MG2_3_111PL & MG2_3_112PL & \ - MG2_3_113PL & MG2_3_114PL & MG2_3_115PL & MG2_3_116PL) -// End of MG2_3: -// Beginning of MG24: -#if (G2_1PL >= G2_4PL) || (G2_1PL == 0) -#define MG2_4_11PL ~(1 << 0) -#else -#define MG2_4_11PL 0xFFFF -#endif - -#if (G2_2PL >= G2_4PL) || (G2_2PL == 0) -#define MG2_4_12PL ~(1 << 1) -#else -#define MG2_4_12PL 0xFFFF -#endif - -#if (G2_3PL >= G2_4PL) || (G2_3PL == 0) -#define MG2_4_13PL ~(1 << 2) -#else -#define MG2_4_13PL 0xFFFF -#endif - -#if (G2_5PL >= G2_4PL) || (G2_5PL == 0) -#define MG2_4_15PL ~(1 << 4) -#else -#define MG2_4_15PL 0xFFFF -#endif - -#if (G2_6PL >= G2_4PL) || (G2_6PL == 0) -#define MG2_4_16PL ~(1 << 5) -#else -#define MG2_4_16PL 0xFFFF -#endif - -#if (G2_7PL >= G2_4PL) || (G2_7PL == 0) -#define MG2_4_17PL ~(1 << 6) -#else -#define MG2_4_17PL 0xFFFF -#endif - -#if (G2_8PL >= G2_4PL) || (G2_8PL == 0) -#define MG2_4_18PL ~(1 << 7) -#else -#define MG2_4_18PL 0xFFFF -#endif - -#if (G2_9PL >= G2_4PL) || (G2_9PL == 0) -#define MG2_4_19PL ~(1 << 8) -#else -#define MG2_4_19PL 0xFFFF -#endif - -#if (G2_10PL >= G2_4PL) || (G2_10PL == 0) -#define MG2_4_110PL ~(1 << 9) -#else -#define MG2_4_110PL 0xFFFF -#endif - -#if (G2_11PL >= G2_4PL) || (G2_11PL == 0) -#define MG2_4_111PL ~(1 << 10) -#else -#define MG2_4_111PL 0xFFFF -#endif - -#if (G2_12PL >= G2_4PL) || (G2_12PL == 0) -#define MG2_4_112PL ~(1 << 11) -#else -#define MG2_4_112PL 0xFFFF -#endif - -#if (G2_13PL >= G2_4PL) || (G2_13PL == 0) -#define MG2_4_113PL ~(1 << 12) -#else -#define MG2_4_113PL 0xFFFF -#endif - -#if (G2_14PL >= G2_4PL) || (G2_14PL == 0) -#define MG2_4_114PL ~(1 << 13) -#else -#define MG2_4_114PL 0xFFFF -#endif - -#if (G2_15PL >= G2_4PL) || (G2_15PL == 0) -#define MG2_4_115PL ~(1 << 14) -#else -#define MG2_4_115PL 0xFFFF -#endif - -#if (G2_16PL >= G2_4PL) || (G2_16PL == 0) -#define MG2_4_116PL ~(1 << 15) -#else -#define MG2_4_116PL 0xFFFF -#endif - -#define MG2_4_14PL 0xFFF7 -#define MG2_4 (MG2_4_11PL & MG2_4_12PL & MG2_4_13PL & MG2_4_14PL & \ - MG2_4_15PL & MG2_4_16PL & MG2_4_17PL & MG2_4_18PL & \ - MG2_4_19PL & MG2_4_110PL & MG2_4_111PL & MG2_4_112PL & \ - MG2_4_113PL & MG2_4_114PL & MG2_4_115PL & MG2_4_116PL) -// End of MG2_4: -// Beginning of MG25: -#if (G2_1PL >= G2_5PL) || (G2_1PL == 0) -#define MG2_5_11PL ~(1 << 0) -#else -#define MG2_5_11PL 0xFFFF -#endif - -#if (G2_2PL >= G2_5PL) || (G2_2PL == 0) -#define MG2_5_12PL ~(1 << 1) -#else -#define MG2_5_12PL 0xFFFF -#endif - -#if (G2_3PL >= G2_5PL) || (G2_3PL == 0) -#define MG2_5_13PL ~(1 << 2) -#else -#define MG2_5_13PL 0xFFFF -#endif - -#if (G2_4PL >= G2_5PL) || (G2_4PL == 0) -#define MG2_5_14PL ~(1 << 3) -#else -#define MG2_5_14PL 0xFFFF -#endif - -#if (G2_6PL >= G2_5PL) || (G2_6PL == 0) -#define MG2_5_16PL ~(1 << 5) -#else -#define MG2_5_16PL 0xFFFF -#endif - -#if (G2_7PL >= G2_5PL) || (G2_7PL == 0) -#define MG2_5_17PL ~(1 << 6) -#else -#define MG2_5_17PL 0xFFFF -#endif - -#if (G2_8PL >= G2_5PL) || (G2_8PL == 0) -#define MG2_5_18PL ~(1 << 7) -#else -#define MG2_5_18PL 0xFFFF -#endif - -#if (G2_9PL >= G2_5PL) || (G2_9PL == 0) -#define MG2_5_19PL ~(1 << 8) -#else -#define MG2_5_19PL 0xFFFF -#endif - -#if (G2_10PL >= G2_5PL) || (G2_10PL == 0) -#define MG2_5_110PL ~(1 << 9) -#else -#define MG2_5_110PL 0xFFFF -#endif - -#if (G2_11PL >= G2_5PL) || (G2_11PL == 0) -#define MG2_5_111PL ~(1 << 10) -#else -#define MG2_5_111PL 0xFFFF -#endif - -#if (G2_12PL >= G2_5PL) || (G2_12PL == 0) -#define MG2_5_112PL ~(1 << 11) -#else -#define MG2_5_112PL 0xFFFF -#endif - -#if (G2_13PL >= G2_5PL) || (G2_13PL == 0) -#define MG2_5_113PL ~(1 << 12) -#else -#define MG2_5_113PL 0xFFFF -#endif - -#if (G2_14PL >= G2_5PL) || (G2_14PL == 0) -#define MG2_5_114PL ~(1 << 13) -#else -#define MG2_5_114PL 0xFFFF -#endif - -#if (G2_15PL >= G2_5PL) || (G2_15PL == 0) -#define MG2_5_115PL ~(1 << 14) -#else -#define MG2_5_115PL 0xFFFF -#endif - -#if (G2_16PL >= G2_5PL) || (G2_16PL == 0) -#define MG2_5_116PL ~(1 << 15) -#else -#define MG2_5_116PL 0xFFFF -#endif - -#define MG2_5_15PL 0xFFEF -#define MG2_5 (MG2_5_11PL & MG2_5_12PL & MG2_5_13PL & MG2_5_14PL & \ - MG2_5_15PL & MG2_5_16PL & MG2_5_17PL & MG2_5_18PL & \ - MG2_5_19PL & MG2_5_110PL & MG2_5_111PL & MG2_5_112PL & \ - MG2_5_113PL & MG2_5_114PL & MG2_5_115PL & MG2_5_116PL) -// End of MG2_5: -// Beginning of MG26: -#if (G2_1PL >= G2_6PL) || (G2_1PL == 0) -#define MG2_6_11PL ~(1 << 0) -#else -#define MG2_6_11PL 0xFFFF -#endif - -#if (G2_2PL >= G2_6PL) || (G2_2PL == 0) -#define MG2_6_12PL ~(1 << 1) -#else -#define MG2_6_12PL 0xFFFF -#endif - -#if (G2_3PL >= G2_6PL) || (G2_3PL == 0) -#define MG2_6_13PL ~(1 << 2) -#else -#define MG2_6_13PL 0xFFFF -#endif - -#if (G2_4PL >= G2_6PL) || (G2_4PL == 0) -#define MG2_6_14PL ~(1 << 3) -#else -#define MG2_6_14PL 0xFFFF -#endif - -#if (G2_5PL >= G2_6PL) || (G2_5PL == 0) -#define MG2_6_15PL ~(1 << 4) -#else -#define MG2_6_15PL 0xFFFF -#endif - -#if (G2_7PL >= G2_6PL) || (G2_7PL == 0) -#define MG2_6_17PL ~(1 << 6) -#else -#define MG2_6_17PL 0xFFFF -#endif - -#if (G2_8PL >= G2_6PL) || (G2_8PL == 0) -#define MG2_6_18PL ~(1 << 7) -#else -#define MG2_6_18PL 0xFFFF -#endif - -#if (G2_9PL >= G2_6PL) || (G2_9PL == 0) -#define MG2_6_19PL ~(1 << 8) -#else -#define MG2_6_19PL 0xFFFF -#endif - -#if (G2_10PL >= G2_6PL) || (G2_10PL == 0) -#define MG2_6_110PL ~(1 << 9) -#else -#define MG2_6_110PL 0xFFFF -#endif - -#if (G2_11PL >= G2_6PL) || (G2_11PL == 0) -#define MG2_6_111PL ~(1 << 10) -#else -#define MG2_6_111PL 0xFFFF -#endif - -#if (G2_12PL >= G2_6PL) || (G2_12PL == 0) -#define MG2_6_112PL ~(1 << 11) -#else -#define MG2_6_112PL 0xFFFF -#endif - -#if (G2_13PL >= G2_6PL) || (G2_13PL == 0) -#define MG2_6_113PL ~(1 << 12) -#else -#define MG2_6_113PL 0xFFFF -#endif - -#if (G2_14PL >= G2_6PL) || (G2_14PL == 0) -#define MG2_6_114PL ~(1 << 13) -#else -#define MG2_6_114PL 0xFFFF -#endif - -#if (G2_15PL >= G2_6PL) || (G2_15PL == 0) -#define MG2_6_115PL ~(1 << 14) -#else -#define MG2_6_115PL 0xFFFF -#endif - -#if (G2_16PL >= G2_6PL) || (G2_16PL == 0) -#define MG2_6_116PL ~(1 << 15) -#else -#define MG2_6_116PL 0xFFFF -#endif - -#define MG2_6_16PL 0xFFDF -#define MG2_6 (MG2_6_11PL & MG2_6_12PL & MG2_6_13PL & MG2_6_14PL & \ - MG2_6_15PL & MG2_6_16PL & MG2_6_17PL & MG2_6_18PL & \ - MG2_6_19PL & MG2_6_110PL & MG2_6_111PL & MG2_6_112PL & \ - MG2_6_113PL & MG2_6_114PL & MG2_6_115PL & MG2_6_116PL) -// End of MG2_6: -// Beginning of MG27: -#if (G2_1PL >= G2_7PL) || (G2_1PL == 0) -#define MG2_7_11PL ~(1 << 0) -#else -#define MG2_7_11PL 0xFFFF -#endif - -#if (G2_2PL >= G2_7PL) || (G2_2PL == 0) -#define MG2_7_12PL ~(1 << 1) -#else -#define MG2_7_12PL 0xFFFF -#endif - -#if (G2_3PL >= G2_7PL) || (G2_3PL == 0) -#define MG2_7_13PL ~(1 << 2) -#else -#define MG2_7_13PL 0xFFFF -#endif - -#if (G2_4PL >= G2_7PL) || (G2_4PL == 0) -#define MG2_7_14PL ~(1 << 3) -#else -#define MG2_7_14PL 0xFFFF -#endif - -#if (G2_5PL >= G2_7PL) || (G2_5PL == 0) -#define MG2_7_15PL ~(1 << 4) -#else -#define MG2_7_15PL 0xFFFF -#endif - -#if (G2_6PL >= G2_7PL) || (G2_6PL == 0) -#define MG2_7_16PL ~(1 << 5) -#else -#define MG2_7_16PL 0xFFFF -#endif - -#if (G2_8PL >= G2_7PL) || (G2_8PL == 0) -#define MG2_7_18PL ~(1 << 7) -#else -#define MG2_7_18PL 0xFFFF -#endif - -#if (G2_9PL >= G2_7PL) || (G2_9PL == 0) -#define MG2_7_19PL ~(1 << 8) -#else -#define MG2_7_19PL 0xFFFF -#endif - -#if (G2_10PL >= G2_7PL) || (G2_10PL == 0) -#define MG2_7_110PL ~(1 << 9) -#else -#define MG2_7_110PL 0xFFFF -#endif - -#if (G2_11PL >= G2_7PL) || (G2_11PL == 0) -#define MG2_7_111PL ~(1 << 10) -#else -#define MG2_7_111PL 0xFFFF -#endif - -#if (G2_12PL >= G2_7PL) || (G2_12PL == 0) -#define MG2_7_112PL ~(1 << 11) -#else -#define MG2_7_112PL 0xFFFF -#endif - -#if (G2_13PL >= G2_7PL) || (G2_13PL == 0) -#define MG2_7_113PL ~(1 << 12) -#else -#define MG2_7_113PL 0xFFFF -#endif - -#if (G2_14PL >= G2_7PL) || (G2_14PL == 0) -#define MG2_7_114PL ~(1 << 13) -#else -#define MG2_7_114PL 0xFFFF -#endif - -#if (G2_15PL >= G2_7PL) || (G2_15PL == 0) -#define MG2_7_115PL ~(1 << 14) -#else -#define MG2_7_115PL 0xFFFF -#endif - -#if (G2_16PL >= G2_7PL) || (G2_16PL == 0) -#define MG2_7_116PL ~(1 << 15) -#else -#define MG2_7_116PL 0xFFFF -#endif - -#define MG2_7_17PL 0xFFBF -#define MG2_7 (MG2_7_11PL & MG2_7_12PL & MG2_7_13PL & MG2_7_14PL & \ - MG2_7_15PL & MG2_7_16PL & MG2_7_17PL & MG2_7_18PL & \ - MG2_7_19PL & MG2_7_110PL & MG2_7_111PL & MG2_7_112PL & \ - MG2_7_113PL & MG2_7_114PL & MG2_7_115PL & MG2_7_116PL) -// End of MG2_7: -// Beginning of MG28: -#if (G2_1PL >= G2_8PL) || (G2_1PL == 0) -#define MG2_8_11PL ~(1 << 0) -#else -#define MG2_8_11PL 0xFFFF -#endif - -#if (G2_2PL >= G2_8PL) || (G2_2PL == 0) -#define MG2_8_12PL ~(1 << 1) -#else -#define MG2_8_12PL 0xFFFF -#endif - -#if (G2_3PL >= G2_8PL) || (G2_3PL == 0) -#define MG2_8_13PL ~(1 << 2) -#else -#define MG2_8_13PL 0xFFFF -#endif - -#if (G2_4PL >= G2_8PL) || (G2_4PL == 0) -#define MG2_8_14PL ~(1 << 3) -#else -#define MG2_8_14PL 0xFFFF -#endif - -#if (G2_5PL >= G2_8PL) || (G2_5PL == 0) -#define MG2_8_15PL ~(1 << 4) -#else -#define MG2_8_15PL 0xFFFF -#endif - -#if (G2_6PL >= G2_8PL) || (G2_6PL == 0) -#define MG2_8_16PL ~(1 << 5) -#else -#define MG2_8_16PL 0xFFFF -#endif - -#if (G2_7PL >= G2_8PL) || (G2_7PL == 0) -#define MG2_8_17PL ~(1 << 6) -#else -#define MG2_8_17PL 0xFFFF -#endif - -#if (G2_9PL >= G2_8PL) || (G2_9PL == 0) -#define MG2_8_19PL ~(1 << 8) -#else -#define MG2_8_19PL 0xFFFF -#endif - -#if (G2_10PL >= G2_8PL) || (G2_10PL == 0) -#define MG2_8_110PL ~(1 << 9) -#else -#define MG2_8_110PL 0xFFFF -#endif - -#if (G2_11PL >= G2_8PL) || (G2_11PL == 0) -#define MG2_8_111PL ~(1 << 10) -#else -#define MG2_8_111PL 0xFFFF -#endif - -#if (G2_12PL >= G2_8PL) || (G2_12PL == 0) -#define MG2_8_112PL ~(1 << 11) -#else -#define MG2_8_112PL 0xFFFF -#endif - -#if (G2_13PL >= G2_8PL) || (G2_13PL == 0) -#define MG2_8_113PL ~(1 << 12) -#else -#define MG2_8_113PL 0xFFFF -#endif - -#if (G2_14PL >= G2_8PL) || (G2_14PL == 0) -#define MG2_8_114PL ~(1 << 13) -#else -#define MG2_8_114PL 0xFFFF -#endif - -#if (G2_15PL >= G2_8PL) || (G2_15PL == 0) -#define MG2_8_115PL ~(1 << 14) -#else -#define MG2_8_115PL 0xFFFF -#endif - -#if (G2_16PL >= G2_8PL) || (G2_16PL == 0) -#define MG2_8_116PL ~(1 << 15) -#else -#define MG2_8_116PL 0xFFFF -#endif - -#define MG2_8_18PL 0xFF7F -#define MG2_8 (MG2_8_11PL & MG2_8_12PL & MG2_8_13PL & MG2_8_14PL & \ - MG2_8_15PL & MG2_8_16PL & MG2_8_17PL & MG2_8_18PL & \ - MG2_8_19PL & MG2_8_110PL & MG2_8_111PL & MG2_8_112PL & \ - MG2_8_113PL & MG2_8_114PL & MG2_8_115PL & MG2_8_116PL) -// End of MG2_8: -// Beginning of MG29: -#if (G2_1PL >= G2_9PL) || (G2_1PL == 0) -#define MG2_9_11PL ~(1 << 0) -#else -#define MG2_9_11PL 0xFFFF -#endif - -#if (G2_2PL >= G2_9PL) || (G2_2PL == 0) -#define MG2_9_12PL ~(1 << 1) -#else -#define MG2_9_12PL 0xFFFF -#endif - -#if (G2_3PL >= G2_9PL) || (G2_3PL == 0) -#define MG2_9_13PL ~(1 << 2) -#else -#define MG2_9_13PL 0xFFFF -#endif - -#if (G2_4PL >= G2_9PL) || (G2_4PL == 0) -#define MG2_9_14PL ~(1 << 3) -#else -#define MG2_9_14PL 0xFFFF -#endif - -#if (G2_5PL >= G2_9PL) || (G2_5PL == 0) -#define MG2_9_15PL ~(1 << 4) -#else -#define MG2_9_15PL 0xFFFF -#endif - -#if (G2_6PL >= G2_9PL) || (G2_6PL == 0) -#define MG2_9_16PL ~(1 << 5) -#else -#define MG2_9_16PL 0xFFFF -#endif - -#if (G2_7PL >= G2_9PL) || (G2_7PL == 0) -#define MG2_9_17PL ~(1 << 6) -#else -#define MG2_9_17PL 0xFFFF -#endif - -#if (G2_8PL >= G2_9PL) || (G2_8PL == 0) -#define MG2_9_18PL ~(1 << 7) -#else -#define MG2_9_18PL 0xFFFF -#endif - -#if (G2_10PL >= G2_9PL) || (G2_10PL == 0) -#define MG2_9_110PL ~(1 << 9) -#else -#define MG2_9_110PL 0xFFFF -#endif - -#if (G2_11PL >= G2_9PL) || (G2_11PL == 0) -#define MG2_9_111PL ~(1 << 10) -#else -#define MG2_9_111PL 0xFFFF -#endif - -#if (G2_12PL >= G2_9PL) || (G2_12PL == 0) -#define MG2_9_112PL ~(1 << 11) -#else -#define MG2_9_112PL 0xFFFF -#endif - -#if (G2_13PL >= G2_9PL) || (G2_13PL == 0) -#define MG2_9_113PL ~(1 << 12) -#else -#define MG2_9_113PL 0xFFFF -#endif - -#if (G2_14PL >= G2_9PL) || (G2_14PL == 0) -#define MG2_9_114PL ~(1 << 13) -#else -#define MG2_9_114PL 0xFFFF -#endif - -#if (G2_15PL >= G2_9PL) || (G2_15PL == 0) -#define MG2_9_115PL ~(1 << 14) -#else -#define MG2_9_115PL 0xFFFF -#endif - -#if (G2_16PL >= G2_9PL) || (G2_16PL == 0) -#define MG2_9_116PL ~(1 << 15) -#else -#define MG2_9_116PL 0xFFFF -#endif - -#define MG2_9_19PL 0xFEFF -#define MG2_9 (MG2_9_11PL & MG2_9_12PL & MG2_9_13PL & MG2_9_14PL & \ - MG2_9_15PL & MG2_9_16PL & MG2_9_17PL & MG2_9_18PL & \ - MG2_9_19PL & MG2_9_110PL & MG2_9_111PL & MG2_9_112PL & \ - MG2_9_113PL & MG2_9_114PL & MG2_9_115PL & MG2_9_116PL) -// End of MG2_9: -// Beginning of MG210: -#if (G2_1PL >= G2_10PL) || (G2_1PL == 0) -#define MG2_10_11PL ~(1 << 0) -#else -#define MG2_10_11PL 0xFFFF -#endif - -#if (G2_2PL >= G2_10PL) || (G2_2PL == 0) -#define MG2_10_12PL ~(1 << 1) -#else -#define MG2_10_12PL 0xFFFF -#endif - -#if (G2_3PL >= G2_10PL) || (G2_3PL == 0) -#define MG2_10_13PL ~(1 << 2) -#else -#define MG2_10_13PL 0xFFFF -#endif - -#if (G2_4PL >= G2_10PL) || (G2_4PL == 0) -#define MG2_10_14PL ~(1 << 3) -#else -#define MG2_10_14PL 0xFFFF -#endif - -#if (G2_5PL >= G2_10PL) || (G2_5PL == 0) -#define MG2_10_15PL ~(1 << 4) -#else -#define MG2_10_15PL 0xFFFF -#endif - -#if (G2_6PL >= G2_10PL) || (G2_6PL == 0) -#define MG2_10_16PL ~(1 << 5) -#else -#define MG2_10_16PL 0xFFFF -#endif - -#if (G2_7PL >= G2_10PL) || (G2_7PL == 0) -#define MG2_10_17PL ~(1 << 6) -#else -#define MG2_10_17PL 0xFFFF -#endif - -#if (G2_8PL >= G2_10PL) || (G2_8PL == 0) -#define MG2_10_18PL ~(1 << 7) -#else -#define MG2_10_18PL 0xFFFF -#endif - -#if (G2_9PL >= G2_10PL) || (G2_9PL == 0) -#define MG2_10_19PL ~(1 << 8) -#else -#define MG2_10_19PL 0xFFFF -#endif - -#if (G2_11PL >= G2_10PL) || (G2_11PL == 0) -#define MG2_10_111PL ~(1 << 10) -#else -#define MG2_10_111PL 0xFFFF -#endif - -#if (G2_12PL >= G2_10PL) || (G2_12PL == 0) -#define MG2_10_112PL ~(1 << 11) -#else -#define MG2_10_112PL 0xFFFF -#endif - -#if (G2_13PL >= G2_10PL) || (G2_13PL == 0) -#define MG2_10_113PL ~(1 << 12) -#else -#define MG2_10_113PL 0xFFFF -#endif - -#if (G2_14PL >= G2_10PL) || (G2_14PL == 0) -#define MG2_10_114PL ~(1 << 13) -#else -#define MG2_10_114PL 0xFFFF -#endif - -#if (G2_15PL >= G2_10PL) || (G2_15PL == 0) -#define MG2_10_115PL ~(1 << 14) -#else -#define MG2_10_115PL 0xFFFF -#endif - -#if (G2_16PL >= G2_10PL) || (G2_16PL == 0) -#define MG2_10_116PL ~(1 << 15) -#else -#define MG2_10_116PL 0xFFFF -#endif - -#define MG2_10_110PL 0xFDFF -#define MG2_10 (MG2_10_11PL & MG2_10_12PL & MG2_10_13PL & MG2_10_14PL & \ - MG2_10_15PL & MG2_10_16PL & MG2_10_17PL & MG2_10_18PL & \ - MG2_10_19PL & MG2_10_110PL & MG2_10_111PL & MG2_10_112PL & \ - MG2_10_113PL & MG2_10_114PL & MG2_10_115PL & MG2_10_116PL) -// End of MG2_10: -// Beginning of MG211: -#if (G2_1PL >= G2_11PL) || (G2_1PL == 0) -#define MG2_11_11PL ~(1 << 0) -#else -#define MG2_11_11PL 0xFFFF -#endif - -#if (G2_2PL >= G2_11PL) || (G2_2PL == 0) -#define MG2_11_12PL ~(1 << 1) -#else -#define MG2_11_12PL 0xFFFF -#endif - -#if (G2_3PL >= G2_11PL) || (G2_3PL == 0) -#define MG2_11_13PL ~(1 << 2) -#else -#define MG2_11_13PL 0xFFFF -#endif - -#if (G2_4PL >= G2_11PL) || (G2_4PL == 0) -#define MG2_11_14PL ~(1 << 3) -#else -#define MG2_11_14PL 0xFFFF -#endif - -#if (G2_5PL >= G2_11PL) || (G2_5PL == 0) -#define MG2_11_15PL ~(1 << 4) -#else -#define MG2_11_15PL 0xFFFF -#endif - -#if (G2_6PL >= G2_11PL) || (G2_6PL == 0) -#define MG2_11_16PL ~(1 << 5) -#else -#define MG2_11_16PL 0xFFFF -#endif - -#if (G2_7PL >= G2_11PL) || (G2_7PL == 0) -#define MG2_11_17PL ~(1 << 6) -#else -#define MG2_11_17PL 0xFFFF -#endif - -#if (G2_8PL >= G2_11PL) || (G2_8PL == 0) -#define MG2_11_18PL ~(1 << 7) -#else -#define MG2_11_18PL 0xFFFF -#endif - -#if (G2_9PL >= G2_11PL) || (G2_9PL == 0) -#define MG2_11_19PL ~(1 << 8) -#else -#define MG2_11_19PL 0xFFFF -#endif - -#if (G2_10PL >= G2_11PL) || (G2_10PL == 0) -#define MG2_11_110PL ~(1 << 9) -#else -#define MG2_11_110PL 0xFFFF -#endif - -#if (G2_12PL >= G2_11PL) || (G2_12PL == 0) -#define MG2_11_112PL ~(1 << 11) -#else -#define MG2_11_112PL 0xFFFF -#endif - -#if (G2_13PL >= G2_11PL) || (G2_13PL == 0) -#define MG2_11_113PL ~(1 << 12) -#else -#define MG2_11_113PL 0xFFFF -#endif - -#if (G2_14PL >= G2_11PL) || (G2_14PL == 0) -#define MG2_11_114PL ~(1 << 13) -#else -#define MG2_11_114PL 0xFFFF -#endif - -#if (G2_15PL >= G2_11PL) || (G2_15PL == 0) -#define MG2_11_115PL ~(1 << 14) -#else -#define MG2_11_115PL 0xFFFF -#endif - -#if (G2_16PL >= G2_11PL) || (G2_16PL == 0) -#define MG2_11_116PL ~(1 << 15) -#else -#define MG2_11_116PL 0xFFFF -#endif - -#define MG2_11_111PL 0xFBFF -#define MG2_11 (MG2_11_11PL & MG2_11_12PL & MG2_11_13PL & MG2_11_14PL & \ - MG2_11_15PL & MG2_11_16PL & MG2_11_17PL & MG2_11_18PL & \ - MG2_11_19PL & MG2_11_110PL & MG2_11_111PL & MG2_11_112PL & \ - MG2_11_113PL & MG2_11_114PL & MG2_11_115PL & MG2_11_116PL) -// End of MG2_11: -// Beginning of MG212: -#if (G2_1PL >= G2_12PL) || (G2_1PL == 0) -#define MG2_12_11PL ~(1 << 0) -#else -#define MG2_12_11PL 0xFFFF -#endif - -#if (G2_2PL >= G2_12PL) || (G2_2PL == 0) -#define MG2_12_12PL ~(1 << 1) -#else -#define MG2_12_12PL 0xFFFF -#endif - -#if (G2_3PL >= G2_12PL) || (G2_3PL == 0) -#define MG2_12_13PL ~(1 << 2) -#else -#define MG2_12_13PL 0xFFFF -#endif - -#if (G2_4PL >= G2_12PL) || (G2_4PL == 0) -#define MG2_12_14PL ~(1 << 3) -#else -#define MG2_12_14PL 0xFFFF -#endif - -#if (G2_5PL >= G2_12PL) || (G2_5PL == 0) -#define MG2_12_15PL ~(1 << 4) -#else -#define MG2_12_15PL 0xFFFF -#endif - -#if (G2_6PL >= G2_12PL) || (G2_6PL == 0) -#define MG2_12_16PL ~(1 << 5) -#else -#define MG2_12_16PL 0xFFFF -#endif - -#if (G2_7PL >= G2_12PL) || (G2_7PL == 0) -#define MG2_12_17PL ~(1 << 6) -#else -#define MG2_12_17PL 0xFFFF -#endif - -#if (G2_8PL >= G2_12PL) || (G2_8PL == 0) -#define MG2_12_18PL ~(1 << 7) -#else -#define MG2_12_18PL 0xFFFF -#endif - -#if (G2_9PL >= G2_12PL) || (G2_9PL == 0) -#define MG2_12_19PL ~(1 << 8) -#else -#define MG2_12_19PL 0xFFFF -#endif - -#if (G2_10PL >= G2_12PL) || (G2_10PL == 0) -#define MG2_12_110PL ~(1 << 9) -#else -#define MG2_12_110PL 0xFFFF -#endif - -#if (G2_11PL >= G2_12PL) || (G2_11PL == 0) -#define MG2_12_111PL ~(1 << 10) -#else -#define MG2_12_111PL 0xFFFF -#endif - -#if (G2_13PL >= G2_12PL) || (G2_13PL == 0) -#define MG2_12_113PL ~(1 << 12) -#else -#define MG2_12_113PL 0xFFFF -#endif - -#if (G2_14PL >= G2_12PL) || (G2_14PL == 0) -#define MG2_12_114PL ~(1 << 13) -#else -#define MG2_12_114PL 0xFFFF -#endif - -#if (G2_15PL >= G2_12PL) || (G2_15PL == 0) -#define MG2_12_115PL ~(1 << 14) -#else -#define MG2_12_115PL 0xFFFF -#endif - -#if (G2_16PL >= G2_12PL) || (G2_16PL == 0) -#define MG2_12_116PL ~(1 << 15) -#else -#define MG2_12_116PL 0xFFFF -#endif - -#define MG2_12_112PL 0xF7FF -#define MG2_12 (MG2_12_11PL & MG2_12_12PL & MG2_12_13PL & MG2_12_14PL & \ - MG2_12_15PL & MG2_12_16PL & MG2_12_17PL & MG2_12_18PL & \ - MG2_12_19PL & MG2_12_110PL & MG2_12_111PL & MG2_12_112PL & \ - MG2_12_113PL & MG2_12_114PL & MG2_12_115PL & MG2_12_116PL) -// End of MG2_12: -// Beginning of MG213: -#if (G2_1PL >= G2_13PL) || (G2_1PL == 0) -#define MG2_13_11PL ~(1 << 0) -#else -#define MG2_13_11PL 0xFFFF -#endif - -#if (G2_2PL >= G2_13PL) || (G2_2PL == 0) -#define MG2_13_12PL ~(1 << 1) -#else -#define MG2_13_12PL 0xFFFF -#endif - -#if (G2_3PL >= G2_13PL) || (G2_3PL == 0) -#define MG2_13_13PL ~(1 << 2) -#else -#define MG2_13_13PL 0xFFFF -#endif - -#if (G2_4PL >= G2_13PL) || (G2_4PL == 0) -#define MG2_13_14PL ~(1 << 3) -#else -#define MG2_13_14PL 0xFFFF -#endif - -#if (G2_5PL >= G2_13PL) || (G2_5PL == 0) -#define MG2_13_15PL ~(1 << 4) -#else -#define MG2_13_15PL 0xFFFF -#endif - -#if (G2_6PL >= G2_13PL) || (G2_6PL == 0) -#define MG2_13_16PL ~(1 << 5) -#else -#define MG2_13_16PL 0xFFFF -#endif - -#if (G2_7PL >= G2_13PL) || (G2_7PL == 0) -#define MG2_13_17PL ~(1 << 6) -#else -#define MG2_13_17PL 0xFFFF -#endif - -#if (G2_8PL >= G2_13PL) || (G2_8PL == 0) -#define MG2_13_18PL ~(1 << 7) -#else -#define MG2_13_18PL 0xFFFF -#endif - -#if (G2_9PL >= G2_13PL) || (G2_9PL == 0) -#define MG2_13_19PL ~(1 << 8) -#else -#define MG2_13_19PL 0xFFFF -#endif - -#if (G2_10PL >= G2_13PL) || (G2_10PL == 0) -#define MG2_13_110PL ~(1 << 9) -#else -#define MG2_13_110PL 0xFFFF -#endif - -#if (G2_11PL >= G2_13PL) || (G2_11PL == 0) -#define MG2_13_111PL ~(1 << 10) -#else -#define MG2_13_111PL 0xFFFF -#endif - -#if (G2_12PL >= G2_13PL) || (G2_12PL == 0) -#define MG2_13_112PL ~(1 << 11) -#else -#define MG2_13_112PL 0xFFFF -#endif - -#if (G2_14PL >= G2_13PL) || (G2_14PL == 0) -#define MG2_13_114PL ~(1 << 13) -#else -#define MG2_13_114PL 0xFFFF -#endif - -#if (G2_15PL >= G2_13PL) || (G2_15PL == 0) -#define MG2_13_115PL ~(1 << 14) -#else -#define MG2_13_115PL 0xFFFF -#endif - -#if (G2_16PL >= G2_13PL) || (G2_16PL == 0) -#define MG2_13_116PL ~(1 << 15) -#else -#define MG2_13_116PL 0xFFFF -#endif - -#define MG2_13_113PL 0xEFFF -#define MG2_13 (MG2_13_11PL & MG2_13_12PL & MG2_13_13PL & MG2_13_14PL & \ - MG2_13_15PL & MG2_13_16PL & MG2_13_17PL & MG2_13_18PL & \ - MG2_13_19PL & MG2_13_110PL & MG2_13_111PL & MG2_13_112PL & \ - MG2_13_113PL & MG2_13_114PL & MG2_13_115PL & MG2_13_116PL) -// End of MG2_13: -// Beginning of MG214: -#if (G2_1PL >= G2_14PL) || (G2_1PL == 0) -#define MG2_14_11PL ~(1 << 0) -#else -#define MG2_14_11PL 0xFFFF -#endif - -#if (G2_2PL >= G2_14PL) || (G2_2PL == 0) -#define MG2_14_12PL ~(1 << 1) -#else -#define MG2_14_12PL 0xFFFF -#endif - -#if (G2_3PL >= G2_14PL) || (G2_3PL == 0) -#define MG2_14_13PL ~(1 << 2) -#else -#define MG2_14_13PL 0xFFFF -#endif - -#if (G2_4PL >= G2_14PL) || (G2_4PL == 0) -#define MG2_14_14PL ~(1 << 3) -#else -#define MG2_14_14PL 0xFFFF -#endif - -#if (G2_5PL >= G2_14PL) || (G2_5PL == 0) -#define MG2_14_15PL ~(1 << 4) -#else -#define MG2_14_15PL 0xFFFF -#endif - -#if (G2_6PL >= G2_14PL) || (G2_6PL == 0) -#define MG2_14_16PL ~(1 << 5) -#else -#define MG2_14_16PL 0xFFFF -#endif - -#if (G2_7PL >= G2_14PL) || (G2_7PL == 0) -#define MG2_14_17PL ~(1 << 6) -#else -#define MG2_14_17PL 0xFFFF -#endif - -#if (G2_8PL >= G2_14PL) || (G2_8PL == 0) -#define MG2_14_18PL ~(1 << 7) -#else -#define MG2_14_18PL 0xFFFF -#endif - -#if (G2_9PL >= G2_14PL) || (G2_9PL == 0) -#define MG2_14_19PL ~(1 << 8) -#else -#define MG2_14_19PL 0xFFFF -#endif - -#if (G2_10PL >= G2_14PL) || (G2_10PL == 0) -#define MG2_14_110PL ~(1 << 9) -#else -#define MG2_14_110PL 0xFFFF -#endif - -#if (G2_11PL >= G2_14PL) || (G2_11PL == 0) -#define MG2_14_111PL ~(1 << 10) -#else -#define MG2_14_111PL 0xFFFF -#endif - -#if (G2_12PL >= G2_14PL) || (G2_12PL == 0) -#define MG2_14_112PL ~(1 << 11) -#else -#define MG2_14_112PL 0xFFFF -#endif - -#if (G2_13PL >= G2_14PL) || (G2_13PL == 0) -#define MG2_14_113PL ~(1 << 12) -#else -#define MG2_14_113PL 0xFFFF -#endif - -#if (G2_15PL >= G2_14PL) || (G2_15PL == 0) -#define MG2_14_115PL ~(1 << 14) -#else -#define MG2_14_115PL 0xFFFF -#endif - -#if (G2_16PL >= G2_14PL) || (G2_16PL == 0) -#define MG2_14_116PL ~(1 << 15) -#else -#define MG2_14_116PL 0xFFFF -#endif - -#define MG2_14_114PL 0xDFFF -#define MG2_14 (MG2_14_11PL & MG2_14_12PL & MG2_14_13PL & MG2_14_14PL & \ - MG2_14_15PL & MG2_14_16PL & MG2_14_17PL & MG2_14_18PL & \ - MG2_14_19PL & MG2_14_110PL & MG2_14_111PL & MG2_14_112PL & \ - MG2_14_113PL & MG2_14_114PL & MG2_14_115PL & MG2_14_116PL) -// End of MG2_14: -// Beginning of MG215: -#if (G2_1PL >= G2_15PL) || (G2_1PL == 0) -#define MG2_15_11PL ~(1 << 0) -#else -#define MG2_15_11PL 0xFFFF -#endif - -#if (G2_2PL >= G2_15PL) || (G2_2PL == 0) -#define MG2_15_12PL ~(1 << 1) -#else -#define MG2_15_12PL 0xFFFF -#endif - -#if (G2_3PL >= G2_15PL) || (G2_3PL == 0) -#define MG2_15_13PL ~(1 << 2) -#else -#define MG2_15_13PL 0xFFFF -#endif - -#if (G2_4PL >= G2_15PL) || (G2_4PL == 0) -#define MG2_15_14PL ~(1 << 3) -#else -#define MG2_15_14PL 0xFFFF -#endif - -#if (G2_5PL >= G2_15PL) || (G2_5PL == 0) -#define MG2_15_15PL ~(1 << 4) -#else -#define MG2_15_15PL 0xFFFF -#endif - -#if (G2_6PL >= G2_15PL) || (G2_6PL == 0) -#define MG2_15_16PL ~(1 << 5) -#else -#define MG2_15_16PL 0xFFFF -#endif - -#if (G2_7PL >= G2_15PL) || (G2_7PL == 0) -#define MG2_15_17PL ~(1 << 6) -#else -#define MG2_15_17PL 0xFFFF -#endif - -#if (G2_8PL >= G2_15PL) || (G2_8PL == 0) -#define MG2_15_18PL ~(1 << 7) -#else -#define MG2_15_18PL 0xFFFF -#endif - -#if (G2_9PL >= G2_15PL) || (G2_9PL == 0) -#define MG2_15_19PL ~(1 << 8) -#else -#define MG2_15_19PL 0xFFFF -#endif - -#if (G2_10PL >= G2_15PL) || (G2_10PL == 0) -#define MG2_15_110PL ~(1 << 9) -#else -#define MG2_15_110PL 0xFFFF -#endif - -#if (G2_11PL >= G2_15PL) || (G2_11PL == 0) -#define MG2_15_111PL ~(1 << 10) -#else -#define MG2_15_111PL 0xFFFF -#endif - -#if (G2_12PL >= G2_15PL) || (G2_12PL == 0) -#define MG2_15_112PL ~(1 << 11) -#else -#define MG2_15_112PL 0xFFFF -#endif - -#if (G2_13PL >= G2_15PL) || (G2_13PL == 0) -#define MG2_15_113PL ~(1 << 12) -#else -#define MG2_15_113PL 0xFFFF -#endif - -#if (G2_14PL >= G2_15PL) || (G2_14PL == 0) -#define MG2_15_114PL ~(1 << 13) -#else -#define MG2_15_114PL 0xFFFF -#endif - -#if (G2_16PL >= G2_15PL) || (G2_16PL == 0) -#define MG2_15_116PL ~(1 << 15) -#else -#define MG2_15_116PL 0xFFFF -#endif - -#define MG2_15_115PL 0xBFFF -#define MG2_15 (MG2_15_11PL & MG2_15_12PL & MG2_15_13PL & MG2_15_14PL & \ - MG2_15_15PL & MG2_15_16PL & MG2_15_17PL & MG2_15_18PL & \ - MG2_15_19PL & MG2_15_110PL & MG2_15_111PL & MG2_15_112PL & \ - MG2_15_113PL & MG2_15_114PL & MG2_15_115PL & MG2_15_116PL) -// End of MG2_15: -// Beginning of MG216: -#if (G2_1PL >= G2_16PL) || (G2_1PL == 0) -#define MG2_16_11PL ~(1 << 0) -#else -#define MG2_16_11PL 0xFFFF -#endif - -#if (G2_2PL >= G2_16PL) || (G2_2PL == 0) -#define MG2_16_12PL ~(1 << 1) -#else -#define MG2_16_12PL 0xFFFF -#endif - -#if (G2_3PL >= G2_16PL) || (G2_3PL == 0) -#define MG2_16_13PL ~(1 << 2) -#else -#define MG2_16_13PL 0xFFFF -#endif - -#if (G2_4PL >= G2_16PL) || (G2_4PL == 0) -#define MG2_16_14PL ~(1 << 3) -#else -#define MG2_16_14PL 0xFFFF -#endif - -#if (G2_5PL >= G2_16PL) || (G2_5PL == 0) -#define MG2_16_15PL ~(1 << 4) -#else -#define MG2_16_15PL 0xFFFF -#endif - -#if (G2_6PL >= G2_16PL) || (G2_6PL == 0) -#define MG2_16_16PL ~(1 << 5) -#else -#define MG2_16_16PL 0xFFFF -#endif - -#if (G2_7PL >= G2_16PL) || (G2_7PL == 0) -#define MG2_16_17PL ~(1 << 6) -#else -#define MG2_16_17PL 0xFFFF -#endif - -#if (G2_8PL >= G2_16PL) || (G2_8PL == 0) -#define MG2_16_18PL ~(1 << 7) -#else -#define MG2_16_18PL 0xFFFF -#endif - -#if (G2_9PL >= G2_16PL) || (G2_9PL == 0) -#define MG2_16_19PL ~(1 << 8) -#else -#define MG2_16_19PL 0xFFFF -#endif - -#if (G2_10PL >= G2_16PL) || (G2_10PL == 0) -#define MG2_16_110PL ~(1 << 9) -#else -#define MG2_16_110PL 0xFFFF -#endif - -#if (G2_11PL >= G2_16PL) || (G2_11PL == 0) -#define MG2_16_111PL ~(1 << 10) -#else -#define MG2_16_111PL 0xFFFF -#endif - -#if (G2_12PL >= G2_16PL) || (G2_12PL == 0) -#define MG2_16_112PL ~(1 << 11) -#else -#define MG2_16_112PL 0xFFFF -#endif - -#if (G2_13PL >= G2_16PL) || (G2_13PL == 0) -#define MG2_16_113PL ~(1 << 12) -#else -#define MG2_16_113PL 0xFFFF -#endif - -#if (G2_14PL >= G2_16PL) || (G2_14PL == 0) -#define MG2_16_114PL ~(1 << 13) -#else -#define MG2_16_114PL 0xFFFF -#endif - -#if (G2_15PL >= G2_16PL) || (G2_15PL == 0) -#define MG2_16_115PL ~(1 << 14) -#else -#define MG2_16_115PL 0xFFFF -#endif - -#define MG2_16_116PL 0x7FFF -#define MG2_16 (MG2_16_11PL & MG2_16_12PL & MG2_16_13PL & MG2_16_14PL & \ - MG2_16_15PL & MG2_16_16PL & MG2_16_17PL & MG2_16_18PL & \ - MG2_16_19PL & MG2_16_110PL & MG2_16_111PL & MG2_16_112PL & \ - MG2_16_113PL & MG2_16_114PL & MG2_16_115PL & MG2_16_116PL) -// End of MG2_16: - - -// -// Automatically generate PIEIER3 interrupt masks MG31 to MG316: -// - -// Beginning of MG31: -#if (G3_2PL >= G3_1PL) || (G3_2PL == 0) -#define MG3_1_12PL ~(1 << 1) -#else -#define MG3_1_12PL 0xFFFF -#endif - -#if (G3_3PL >= G3_1PL) || (G3_3PL == 0) -#define MG3_1_13PL ~(1 << 2) -#else -#define MG3_1_13PL 0xFFFF -#endif - -#if (G3_4PL >= G3_1PL) || (G3_4PL == 0) -#define MG3_1_14PL ~(1 << 3) -#else -#define MG3_1_14PL 0xFFFF -#endif - -#if (G3_5PL >= G3_1PL) || (G3_5PL == 0) -#define MG3_1_15PL ~(1 << 4) -#else -#define MG3_1_15PL 0xFFFF -#endif - -#if (G3_6PL >= G3_1PL) || (G3_6PL == 0) -#define MG3_1_16PL ~(1 << 5) -#else -#define MG3_1_16PL 0xFFFF -#endif - -#if (G3_7PL >= G3_1PL) || (G3_7PL == 0) -#define MG3_1_17PL ~(1 << 6) -#else -#define MG3_1_17PL 0xFFFF -#endif - -#if (G3_8PL >= G3_1PL) || (G3_8PL == 0) -#define MG3_1_18PL ~(1 << 7) -#else -#define MG3_1_18PL 0xFFFF -#endif - -#if (G3_9PL >= G3_1PL) || (G3_9PL == 0) -#define MG3_1_19PL ~(1 << 8) -#else -#define MG3_1_19PL 0xFFFF -#endif - -#if (G3_10PL >= G3_1PL) || (G3_10PL == 0) -#define MG3_1_110PL ~(1 << 9) -#else -#define MG3_1_110PL 0xFFFF -#endif - -#if (G3_11PL >= G3_1PL) || (G3_11PL == 0) -#define MG3_1_111PL ~(1 << 10) -#else -#define MG3_1_111PL 0xFFFF -#endif - -#if (G3_12PL >= G3_1PL) || (G3_12PL == 0) -#define MG3_1_112PL ~(1 << 11) -#else -#define MG3_1_112PL 0xFFFF -#endif - -#if (G3_13PL >= G3_1PL) || (G3_13PL == 0) -#define MG3_1_113PL ~(1 << 12) -#else -#define MG3_1_113PL 0xFFFF -#endif - -#if (G3_14PL >= G3_1PL) || (G3_14PL == 0) -#define MG3_1_114PL ~(1 << 13) -#else -#define MG3_1_114PL 0xFFFF -#endif - -#if (G3_15PL >= G3_1PL) || (G3_15PL == 0) -#define MG3_1_115PL ~(1 << 14) -#else -#define MG3_1_115PL 0xFFFF -#endif - -#if (G3_16PL >= G3_1PL) || (G3_16PL == 0) -#define MG3_1_116PL ~(1 << 15) -#else -#define MG3_1_116PL 0xFFFF -#endif - -#define MG3_1_11PL 0xFFFE -#define MG3_1 (MG3_1_11PL & MG3_1_12PL & MG3_1_13PL & MG3_1_14PL & \ - MG3_1_15PL & MG3_1_16PL & MG3_1_17PL & MG3_1_18PL & \ - MG3_1_19PL & MG3_1_110PL & MG3_1_111PL & MG3_1_112PL & \ - MG3_1_113PL & MG3_1_114PL & MG3_1_115PL & MG3_1_116PL) -// End of MG3_1: -// Beginning of MG32: -#if (G3_1PL >= G3_2PL) || (G3_1PL == 0) -#define MG3_2_11PL ~(1 << 0) -#else -#define MG3_2_11PL 0xFFFF -#endif - -#if (G3_3PL >= G3_2PL) || (G3_3PL == 0) -#define MG3_2_13PL ~(1 << 2) -#else -#define MG3_2_13PL 0xFFFF -#endif - -#if (G3_4PL >= G3_2PL) || (G3_4PL == 0) -#define MG3_2_14PL ~(1 << 3) -#else -#define MG3_2_14PL 0xFFFF -#endif - -#if (G3_5PL >= G3_2PL) || (G3_5PL == 0) -#define MG3_2_15PL ~(1 << 4) -#else -#define MG3_2_15PL 0xFFFF -#endif - -#if (G3_6PL >= G3_2PL) || (G3_6PL == 0) -#define MG3_2_16PL ~(1 << 5) -#else -#define MG3_2_16PL 0xFFFF -#endif - -#if (G3_7PL >= G3_2PL) || (G3_7PL == 0) -#define MG3_2_17PL ~(1 << 6) -#else -#define MG3_2_17PL 0xFFFF -#endif - -#if (G3_8PL >= G3_2PL) || (G3_8PL == 0) -#define MG3_2_18PL ~(1 << 7) -#else -#define MG3_2_18PL 0xFFFF -#endif - -#if (G3_9PL >= G3_2PL) || (G3_9PL == 0) -#define MG3_2_19PL ~(1 << 8) -#else -#define MG3_2_19PL 0xFFFF -#endif - -#if (G3_10PL >= G3_2PL) || (G3_10PL == 0) -#define MG3_2_110PL ~(1 << 9) -#else -#define MG3_2_110PL 0xFFFF -#endif - -#if (G3_11PL >= G3_2PL) || (G3_11PL == 0) -#define MG3_2_111PL ~(1 << 10) -#else -#define MG3_2_111PL 0xFFFF -#endif - -#if (G3_12PL >= G3_2PL) || (G3_12PL == 0) -#define MG3_2_112PL ~(1 << 11) -#else -#define MG3_2_112PL 0xFFFF -#endif - -#if (G3_13PL >= G3_2PL) || (G3_13PL == 0) -#define MG3_2_113PL ~(1 << 12) -#else -#define MG3_2_113PL 0xFFFF -#endif - -#if (G3_14PL >= G3_2PL) || (G3_14PL == 0) -#define MG3_2_114PL ~(1 << 13) -#else -#define MG3_2_114PL 0xFFFF -#endif - -#if (G3_15PL >= G3_2PL) || (G3_15PL == 0) -#define MG3_2_115PL ~(1 << 14) -#else -#define MG3_2_115PL 0xFFFF -#endif - -#if (G3_16PL >= G3_2PL) || (G3_16PL == 0) -#define MG3_2_116PL ~(1 << 15) -#else -#define MG3_2_116PL 0xFFFF -#endif - -#define MG3_2_12PL 0xFFFD -#define MG3_2 (MG3_2_11PL & MG3_2_12PL & MG3_2_13PL & MG3_2_14PL & \ - MG3_2_15PL & MG3_2_16PL & MG3_2_17PL & MG3_2_18PL & \ - MG3_2_19PL & MG3_2_110PL & MG3_2_111PL & MG3_2_112PL & \ - MG3_2_113PL & MG3_2_114PL & MG3_2_115PL & MG3_2_116PL) -// End of MG3_2: -// Beginning of MG33: -#if (G3_1PL >= G3_3PL) || (G3_1PL == 0) -#define MG3_3_11PL ~(1 << 0) -#else -#define MG3_3_11PL 0xFFFF -#endif - -#if (G3_2PL >= G3_3PL) || (G3_2PL == 0) -#define MG3_3_12PL ~(1 << 1) -#else -#define MG3_3_12PL 0xFFFF -#endif - -#if (G3_4PL >= G3_3PL) || (G3_4PL == 0) -#define MG3_3_14PL ~(1 << 3) -#else -#define MG3_3_14PL 0xFFFF -#endif - -#if (G3_5PL >= G3_3PL) || (G3_5PL == 0) -#define MG3_3_15PL ~(1 << 4) -#else -#define MG3_3_15PL 0xFFFF -#endif - -#if (G3_6PL >= G3_3PL) || (G3_6PL == 0) -#define MG3_3_16PL ~(1 << 5) -#else -#define MG3_3_16PL 0xFFFF -#endif - -#if (G3_7PL >= G3_3PL) || (G3_7PL == 0) -#define MG3_3_17PL ~(1 << 6) -#else -#define MG3_3_17PL 0xFFFF -#endif - -#if (G3_8PL >= G3_3PL) || (G3_8PL == 0) -#define MG3_3_18PL ~(1 << 7) -#else -#define MG3_3_18PL 0xFFFF -#endif - -#if (G3_9PL >= G3_3PL) || (G3_9PL == 0) -#define MG3_3_19PL ~(1 << 8) -#else -#define MG3_3_19PL 0xFFFF -#endif - -#if (G3_10PL >= G3_3PL) || (G3_10PL == 0) -#define MG3_3_110PL ~(1 << 9) -#else -#define MG3_3_110PL 0xFFFF -#endif - -#if (G3_11PL >= G3_3PL) || (G3_11PL == 0) -#define MG3_3_111PL ~(1 << 10) -#else -#define MG3_3_111PL 0xFFFF -#endif - -#if (G3_12PL >= G3_3PL) || (G3_12PL == 0) -#define MG3_3_112PL ~(1 << 11) -#else -#define MG3_3_112PL 0xFFFF -#endif - -#if (G3_13PL >= G3_3PL) || (G3_13PL == 0) -#define MG3_3_113PL ~(1 << 12) -#else -#define MG3_3_113PL 0xFFFF -#endif - -#if (G3_14PL >= G3_3PL) || (G3_14PL == 0) -#define MG3_3_114PL ~(1 << 13) -#else -#define MG3_3_114PL 0xFFFF -#endif - -#if (G3_15PL >= G3_3PL) || (G3_15PL == 0) -#define MG3_3_115PL ~(1 << 14) -#else -#define MG3_3_115PL 0xFFFF -#endif - -#if (G3_16PL >= G3_3PL) || (G3_16PL == 0) -#define MG3_3_116PL ~(1 << 15) -#else -#define MG3_3_116PL 0xFFFF -#endif - -#define MG3_3_13PL 0xFFFB -#define MG3_3 (MG3_3_11PL & MG3_3_12PL & MG3_3_13PL & MG3_3_14PL & \ - MG3_3_15PL & MG3_3_16PL & MG3_3_17PL & MG3_3_18PL & \ - MG3_3_19PL & MG3_3_110PL & MG3_3_111PL & MG3_3_112PL & \ - MG3_3_113PL & MG3_3_114PL & MG3_3_115PL & MG3_3_116PL) -// End of MG3_3: -// Beginning of MG34: -#if (G3_1PL >= G3_4PL) || (G3_1PL == 0) -#define MG3_4_11PL ~(1 << 0) -#else -#define MG3_4_11PL 0xFFFF -#endif - -#if (G3_2PL >= G3_4PL) || (G3_2PL == 0) -#define MG3_4_12PL ~(1 << 1) -#else -#define MG3_4_12PL 0xFFFF -#endif - -#if (G3_3PL >= G3_4PL) || (G3_3PL == 0) -#define MG3_4_13PL ~(1 << 2) -#else -#define MG3_4_13PL 0xFFFF -#endif - -#if (G3_5PL >= G3_4PL) || (G3_5PL == 0) -#define MG3_4_15PL ~(1 << 4) -#else -#define MG3_4_15PL 0xFFFF -#endif - -#if (G3_6PL >= G3_4PL) || (G3_6PL == 0) -#define MG3_4_16PL ~(1 << 5) -#else -#define MG3_4_16PL 0xFFFF -#endif - -#if (G3_7PL >= G3_4PL) || (G3_7PL == 0) -#define MG3_4_17PL ~(1 << 6) -#else -#define MG3_4_17PL 0xFFFF -#endif - -#if (G3_8PL >= G3_4PL) || (G3_8PL == 0) -#define MG3_4_18PL ~(1 << 7) -#else -#define MG3_4_18PL 0xFFFF -#endif - -#if (G3_9PL >= G3_4PL) || (G3_9PL == 0) -#define MG3_4_19PL ~(1 << 8) -#else -#define MG3_4_19PL 0xFFFF -#endif - -#if (G3_10PL >= G3_4PL) || (G3_10PL == 0) -#define MG3_4_110PL ~(1 << 9) -#else -#define MG3_4_110PL 0xFFFF -#endif - -#if (G3_11PL >= G3_4PL) || (G3_11PL == 0) -#define MG3_4_111PL ~(1 << 10) -#else -#define MG3_4_111PL 0xFFFF -#endif - -#if (G3_12PL >= G3_4PL) || (G3_12PL == 0) -#define MG3_4_112PL ~(1 << 11) -#else -#define MG3_4_112PL 0xFFFF -#endif - -#if (G3_13PL >= G3_4PL) || (G3_13PL == 0) -#define MG3_4_113PL ~(1 << 12) -#else -#define MG3_4_113PL 0xFFFF -#endif - -#if (G3_14PL >= G3_4PL) || (G3_14PL == 0) -#define MG3_4_114PL ~(1 << 13) -#else -#define MG3_4_114PL 0xFFFF -#endif - -#if (G3_15PL >= G3_4PL) || (G3_15PL == 0) -#define MG3_4_115PL ~(1 << 14) -#else -#define MG3_4_115PL 0xFFFF -#endif - -#if (G3_16PL >= G3_4PL) || (G3_16PL == 0) -#define MG3_4_116PL ~(1 << 15) -#else -#define MG3_4_116PL 0xFFFF -#endif - -#define MG3_4_14PL 0xFFF7 -#define MG3_4 (MG3_4_11PL & MG3_4_12PL & MG3_4_13PL & MG3_4_14PL & \ - MG3_4_15PL & MG3_4_16PL & MG3_4_17PL & MG3_4_18PL & \ - MG3_4_19PL & MG3_4_110PL & MG3_4_111PL & MG3_4_112PL & \ - MG3_4_113PL & MG3_4_114PL & MG3_4_115PL & MG3_4_116PL) -// End of MG3_4: -// Beginning of MG35: -#if (G3_1PL >= G3_5PL) || (G3_1PL == 0) -#define MG3_5_11PL ~(1 << 0) -#else -#define MG3_5_11PL 0xFFFF -#endif - -#if (G3_2PL >= G3_5PL) || (G3_2PL == 0) -#define MG3_5_12PL ~(1 << 1) -#else -#define MG3_5_12PL 0xFFFF -#endif - -#if (G3_3PL >= G3_5PL) || (G3_3PL == 0) -#define MG3_5_13PL ~(1 << 2) -#else -#define MG3_5_13PL 0xFFFF -#endif - -#if (G3_4PL >= G3_5PL) || (G3_4PL == 0) -#define MG3_5_14PL ~(1 << 3) -#else -#define MG3_5_14PL 0xFFFF -#endif - -#if (G3_6PL >= G3_5PL) || (G3_6PL == 0) -#define MG3_5_16PL ~(1 << 5) -#else -#define MG3_5_16PL 0xFFFF -#endif - -#if (G3_7PL >= G3_5PL) || (G3_7PL == 0) -#define MG3_5_17PL ~(1 << 6) -#else -#define MG3_5_17PL 0xFFFF -#endif - -#if (G3_8PL >= G3_5PL) || (G3_8PL == 0) -#define MG3_5_18PL ~(1 << 7) -#else -#define MG3_5_18PL 0xFFFF -#endif - -#if (G3_9PL >= G3_5PL) || (G3_9PL == 0) -#define MG3_5_19PL ~(1 << 8) -#else -#define MG3_5_19PL 0xFFFF -#endif - -#if (G3_10PL >= G3_5PL) || (G3_10PL == 0) -#define MG3_5_110PL ~(1 << 9) -#else -#define MG3_5_110PL 0xFFFF -#endif - -#if (G3_11PL >= G3_5PL) || (G3_11PL == 0) -#define MG3_5_111PL ~(1 << 10) -#else -#define MG3_5_111PL 0xFFFF -#endif - -#if (G3_12PL >= G3_5PL) || (G3_12PL == 0) -#define MG3_5_112PL ~(1 << 11) -#else -#define MG3_5_112PL 0xFFFF -#endif - -#if (G3_13PL >= G3_5PL) || (G3_13PL == 0) -#define MG3_5_113PL ~(1 << 12) -#else -#define MG3_5_113PL 0xFFFF -#endif - -#if (G3_14PL >= G3_5PL) || (G3_14PL == 0) -#define MG3_5_114PL ~(1 << 13) -#else -#define MG3_5_114PL 0xFFFF -#endif - -#if (G3_15PL >= G3_5PL) || (G3_15PL == 0) -#define MG3_5_115PL ~(1 << 14) -#else -#define MG3_5_115PL 0xFFFF -#endif - -#if (G3_16PL >= G3_5PL) || (G3_16PL == 0) -#define MG3_5_116PL ~(1 << 15) -#else -#define MG3_5_116PL 0xFFFF -#endif - -#define MG3_5_15PL 0xFFEF -#define MG3_5 (MG3_5_11PL & MG3_5_12PL & MG3_5_13PL & MG3_5_14PL & \ - MG3_5_15PL & MG3_5_16PL & MG3_5_17PL & MG3_5_18PL & \ - MG3_5_19PL & MG3_5_110PL & MG3_5_111PL & MG3_5_112PL & \ - MG3_5_113PL & MG3_5_114PL & MG3_5_115PL & MG3_5_116PL) -// End of MG3_5: -// Beginning of MG36: -#if (G3_1PL >= G3_6PL) || (G3_1PL == 0) -#define MG3_6_11PL ~(1 << 0) -#else -#define MG3_6_11PL 0xFFFF -#endif - -#if (G3_2PL >= G3_6PL) || (G3_2PL == 0) -#define MG3_6_12PL ~(1 << 1) -#else -#define MG3_6_12PL 0xFFFF -#endif - -#if (G3_3PL >= G3_6PL) || (G3_3PL == 0) -#define MG3_6_13PL ~(1 << 2) -#else -#define MG3_6_13PL 0xFFFF -#endif - -#if (G3_4PL >= G3_6PL) || (G3_4PL == 0) -#define MG3_6_14PL ~(1 << 3) -#else -#define MG3_6_14PL 0xFFFF -#endif - -#if (G3_5PL >= G3_6PL) || (G3_5PL == 0) -#define MG3_6_15PL ~(1 << 4) -#else -#define MG3_6_15PL 0xFFFF -#endif - -#if (G3_7PL >= G3_6PL) || (G3_7PL == 0) -#define MG3_6_17PL ~(1 << 6) -#else -#define MG3_6_17PL 0xFFFF -#endif - -#if (G3_8PL >= G3_6PL) || (G3_8PL == 0) -#define MG3_6_18PL ~(1 << 7) -#else -#define MG3_6_18PL 0xFFFF -#endif - -#if (G3_9PL >= G3_6PL) || (G3_9PL == 0) -#define MG3_6_19PL ~(1 << 8) -#else -#define MG3_6_19PL 0xFFFF -#endif - -#if (G3_10PL >= G3_6PL) || (G3_10PL == 0) -#define MG3_6_110PL ~(1 << 9) -#else -#define MG3_6_110PL 0xFFFF -#endif - -#if (G3_11PL >= G3_6PL) || (G3_11PL == 0) -#define MG3_6_111PL ~(1 << 10) -#else -#define MG3_6_111PL 0xFFFF -#endif - -#if (G3_12PL >= G3_6PL) || (G3_12PL == 0) -#define MG3_6_112PL ~(1 << 11) -#else -#define MG3_6_112PL 0xFFFF -#endif - -#if (G3_13PL >= G3_6PL) || (G3_13PL == 0) -#define MG3_6_113PL ~(1 << 12) -#else -#define MG3_6_113PL 0xFFFF -#endif - -#if (G3_14PL >= G3_6PL) || (G3_14PL == 0) -#define MG3_6_114PL ~(1 << 13) -#else -#define MG3_6_114PL 0xFFFF -#endif - -#if (G3_15PL >= G3_6PL) || (G3_15PL == 0) -#define MG3_6_115PL ~(1 << 14) -#else -#define MG3_6_115PL 0xFFFF -#endif - -#if (G3_16PL >= G3_6PL) || (G3_16PL == 0) -#define MG3_6_116PL ~(1 << 15) -#else -#define MG3_6_116PL 0xFFFF -#endif - -#define MG3_6_16PL 0xFFDF -#define MG3_6 (MG3_6_11PL & MG3_6_12PL & MG3_6_13PL & MG3_6_14PL & \ - MG3_6_15PL & MG3_6_16PL & MG3_6_17PL & MG3_6_18PL & \ - MG3_6_19PL & MG3_6_110PL & MG3_6_111PL & MG3_6_112PL & \ - MG3_6_113PL & MG3_6_114PL & MG3_6_115PL & MG3_6_116PL) -// End of MG3_6: -// Beginning of MG37: -#if (G3_1PL >= G3_7PL) || (G3_1PL == 0) -#define MG3_7_11PL ~(1 << 0) -#else -#define MG3_7_11PL 0xFFFF -#endif - -#if (G3_2PL >= G3_7PL) || (G3_2PL == 0) -#define MG3_7_12PL ~(1 << 1) -#else -#define MG3_7_12PL 0xFFFF -#endif - -#if (G3_3PL >= G3_7PL) || (G3_3PL == 0) -#define MG3_7_13PL ~(1 << 2) -#else -#define MG3_7_13PL 0xFFFF -#endif - -#if (G3_4PL >= G3_7PL) || (G3_4PL == 0) -#define MG3_7_14PL ~(1 << 3) -#else -#define MG3_7_14PL 0xFFFF -#endif - -#if (G3_5PL >= G3_7PL) || (G3_5PL == 0) -#define MG3_7_15PL ~(1 << 4) -#else -#define MG3_7_15PL 0xFFFF -#endif - -#if (G3_6PL >= G3_7PL) || (G3_6PL == 0) -#define MG3_7_16PL ~(1 << 5) -#else -#define MG3_7_16PL 0xFFFF -#endif - -#if (G3_8PL >= G3_7PL) || (G3_8PL == 0) -#define MG3_7_18PL ~(1 << 7) -#else -#define MG3_7_18PL 0xFFFF -#endif - -#if (G3_9PL >= G3_7PL) || (G3_9PL == 0) -#define MG3_7_19PL ~(1 << 8) -#else -#define MG3_7_19PL 0xFFFF -#endif - -#if (G3_10PL >= G3_7PL) || (G3_10PL == 0) -#define MG3_7_110PL ~(1 << 9) -#else -#define MG3_7_110PL 0xFFFF -#endif - -#if (G3_11PL >= G3_7PL) || (G3_11PL == 0) -#define MG3_7_111PL ~(1 << 10) -#else -#define MG3_7_111PL 0xFFFF -#endif - -#if (G3_12PL >= G3_7PL) || (G3_12PL == 0) -#define MG3_7_112PL ~(1 << 11) -#else -#define MG3_7_112PL 0xFFFF -#endif - -#if (G3_13PL >= G3_7PL) || (G3_13PL == 0) -#define MG3_7_113PL ~(1 << 12) -#else -#define MG3_7_113PL 0xFFFF -#endif - -#if (G3_14PL >= G3_7PL) || (G3_14PL == 0) -#define MG3_7_114PL ~(1 << 13) -#else -#define MG3_7_114PL 0xFFFF -#endif - -#if (G3_15PL >= G3_7PL) || (G3_15PL == 0) -#define MG3_7_115PL ~(1 << 14) -#else -#define MG3_7_115PL 0xFFFF -#endif - -#if (G3_16PL >= G3_7PL) || (G3_16PL == 0) -#define MG3_7_116PL ~(1 << 15) -#else -#define MG3_7_116PL 0xFFFF -#endif - -#define MG3_7_17PL 0xFFBF -#define MG3_7 (MG3_7_11PL & MG3_7_12PL & MG3_7_13PL & MG3_7_14PL & \ - MG3_7_15PL & MG3_7_16PL & MG3_7_17PL & MG3_7_18PL & \ - MG3_7_19PL & MG3_7_110PL & MG3_7_111PL & MG3_7_112PL & \ - MG3_7_113PL & MG3_7_114PL & MG3_7_115PL & MG3_7_116PL) -// End of MG3_7: -// Beginning of MG38: -#if (G3_1PL >= G3_8PL) || (G3_1PL == 0) -#define MG3_8_11PL ~(1 << 0) -#else -#define MG3_8_11PL 0xFFFF -#endif - -#if (G3_2PL >= G3_8PL) || (G3_2PL == 0) -#define MG3_8_12PL ~(1 << 1) -#else -#define MG3_8_12PL 0xFFFF -#endif - -#if (G3_3PL >= G3_8PL) || (G3_3PL == 0) -#define MG3_8_13PL ~(1 << 2) -#else -#define MG3_8_13PL 0xFFFF -#endif - -#if (G3_4PL >= G3_8PL) || (G3_4PL == 0) -#define MG3_8_14PL ~(1 << 3) -#else -#define MG3_8_14PL 0xFFFF -#endif - -#if (G3_5PL >= G3_8PL) || (G3_5PL == 0) -#define MG3_8_15PL ~(1 << 4) -#else -#define MG3_8_15PL 0xFFFF -#endif - -#if (G3_6PL >= G3_8PL) || (G3_6PL == 0) -#define MG3_8_16PL ~(1 << 5) -#else -#define MG3_8_16PL 0xFFFF -#endif - -#if (G3_7PL >= G3_8PL) || (G3_7PL == 0) -#define MG3_8_17PL ~(1 << 6) -#else -#define MG3_8_17PL 0xFFFF -#endif - -#if (G3_9PL >= G3_8PL) || (G3_9PL == 0) -#define MG3_8_19PL ~(1 << 8) -#else -#define MG3_8_19PL 0xFFFF -#endif - -#if (G3_10PL >= G3_8PL) || (G3_10PL == 0) -#define MG3_8_110PL ~(1 << 9) -#else -#define MG3_8_110PL 0xFFFF -#endif - -#if (G3_11PL >= G3_8PL) || (G3_11PL == 0) -#define MG3_8_111PL ~(1 << 10) -#else -#define MG3_8_111PL 0xFFFF -#endif - -#if (G3_12PL >= G3_8PL) || (G3_12PL == 0) -#define MG3_8_112PL ~(1 << 11) -#else -#define MG3_8_112PL 0xFFFF -#endif - -#if (G3_13PL >= G3_8PL) || (G3_13PL == 0) -#define MG3_8_113PL ~(1 << 12) -#else -#define MG3_8_113PL 0xFFFF -#endif - -#if (G3_14PL >= G3_8PL) || (G3_14PL == 0) -#define MG3_8_114PL ~(1 << 13) -#else -#define MG3_8_114PL 0xFFFF -#endif - -#if (G3_15PL >= G3_8PL) || (G3_15PL == 0) -#define MG3_8_115PL ~(1 << 14) -#else -#define MG3_8_115PL 0xFFFF -#endif - -#if (G3_16PL >= G3_8PL) || (G3_16PL == 0) -#define MG3_8_116PL ~(1 << 15) -#else -#define MG3_8_116PL 0xFFFF -#endif - -#define MG3_8_18PL 0xFF7F -#define MG3_8 (MG3_8_11PL & MG3_8_12PL & MG3_8_13PL & MG3_8_14PL & \ - MG3_8_15PL & MG3_8_16PL & MG3_8_17PL & MG3_8_18PL & \ - MG3_8_19PL & MG3_8_110PL & MG3_8_111PL & MG3_8_112PL & \ - MG3_8_113PL & MG3_8_114PL & MG3_8_115PL & MG3_8_116PL) -// End of MG3_8: -// Beginning of MG39: -#if (G3_1PL >= G3_9PL) || (G3_1PL == 0) -#define MG3_9_11PL ~(1 << 0) -#else -#define MG3_9_11PL 0xFFFF -#endif - -#if (G3_2PL >= G3_9PL) || (G3_2PL == 0) -#define MG3_9_12PL ~(1 << 1) -#else -#define MG3_9_12PL 0xFFFF -#endif - -#if (G3_3PL >= G3_9PL) || (G3_3PL == 0) -#define MG3_9_13PL ~(1 << 2) -#else -#define MG3_9_13PL 0xFFFF -#endif - -#if (G3_4PL >= G3_9PL) || (G3_4PL == 0) -#define MG3_9_14PL ~(1 << 3) -#else -#define MG3_9_14PL 0xFFFF -#endif - -#if (G3_5PL >= G3_9PL) || (G3_5PL == 0) -#define MG3_9_15PL ~(1 << 4) -#else -#define MG3_9_15PL 0xFFFF -#endif - -#if (G3_6PL >= G3_9PL) || (G3_6PL == 0) -#define MG3_9_16PL ~(1 << 5) -#else -#define MG3_9_16PL 0xFFFF -#endif - -#if (G3_7PL >= G3_9PL) || (G3_7PL == 0) -#define MG3_9_17PL ~(1 << 6) -#else -#define MG3_9_17PL 0xFFFF -#endif - -#if (G3_8PL >= G3_9PL) || (G3_8PL == 0) -#define MG3_9_18PL ~(1 << 7) -#else -#define MG3_9_18PL 0xFFFF -#endif - -#if (G3_10PL >= G3_9PL) || (G3_10PL == 0) -#define MG3_9_110PL ~(1 << 9) -#else -#define MG3_9_110PL 0xFFFF -#endif - -#if (G3_11PL >= G3_9PL) || (G3_11PL == 0) -#define MG3_9_111PL ~(1 << 10) -#else -#define MG3_9_111PL 0xFFFF -#endif - -#if (G3_12PL >= G3_9PL) || (G3_12PL == 0) -#define MG3_9_112PL ~(1 << 11) -#else -#define MG3_9_112PL 0xFFFF -#endif - -#if (G3_13PL >= G3_9PL) || (G3_13PL == 0) -#define MG3_9_113PL ~(1 << 12) -#else -#define MG3_9_113PL 0xFFFF -#endif - -#if (G3_14PL >= G3_9PL) || (G3_14PL == 0) -#define MG3_9_114PL ~(1 << 13) -#else -#define MG3_9_114PL 0xFFFF -#endif - -#if (G3_15PL >= G3_9PL) || (G3_15PL == 0) -#define MG3_9_115PL ~(1 << 14) -#else -#define MG3_9_115PL 0xFFFF -#endif - -#if (G3_16PL >= G3_9PL) || (G3_16PL == 0) -#define MG3_9_116PL ~(1 << 15) -#else -#define MG3_9_116PL 0xFFFF -#endif - -#define MG3_9_19PL 0xFEFF -#define MG3_9 (MG3_9_11PL & MG3_9_12PL & MG3_9_13PL & MG3_9_14PL & \ - MG3_9_15PL & MG3_9_16PL & MG3_9_17PL & MG3_9_18PL & \ - MG3_9_19PL & MG3_9_110PL & MG3_9_111PL & MG3_9_112PL & \ - MG3_9_113PL & MG3_9_114PL & MG3_9_115PL & MG3_9_116PL) -// End of MG3_9: -// Beginning of MG310: -#if (G3_1PL >= G3_10PL) || (G3_1PL == 0) -#define MG3_10_11PL ~(1 << 0) -#else -#define MG3_10_11PL 0xFFFF -#endif - -#if (G3_2PL >= G3_10PL) || (G3_2PL == 0) -#define MG3_10_12PL ~(1 << 1) -#else -#define MG3_10_12PL 0xFFFF -#endif - -#if (G3_3PL >= G3_10PL) || (G3_3PL == 0) -#define MG3_10_13PL ~(1 << 2) -#else -#define MG3_10_13PL 0xFFFF -#endif - -#if (G3_4PL >= G3_10PL) || (G3_4PL == 0) -#define MG3_10_14PL ~(1 << 3) -#else -#define MG3_10_14PL 0xFFFF -#endif - -#if (G3_5PL >= G3_10PL) || (G3_5PL == 0) -#define MG3_10_15PL ~(1 << 4) -#else -#define MG3_10_15PL 0xFFFF -#endif - -#if (G3_6PL >= G3_10PL) || (G3_6PL == 0) -#define MG3_10_16PL ~(1 << 5) -#else -#define MG3_10_16PL 0xFFFF -#endif - -#if (G3_7PL >= G3_10PL) || (G3_7PL == 0) -#define MG3_10_17PL ~(1 << 6) -#else -#define MG3_10_17PL 0xFFFF -#endif - -#if (G3_8PL >= G3_10PL) || (G3_8PL == 0) -#define MG3_10_18PL ~(1 << 7) -#else -#define MG3_10_18PL 0xFFFF -#endif - -#if (G3_9PL >= G3_10PL) || (G3_9PL == 0) -#define MG3_10_19PL ~(1 << 8) -#else -#define MG3_10_19PL 0xFFFF -#endif - -#if (G3_11PL >= G3_10PL) || (G3_11PL == 0) -#define MG3_10_111PL ~(1 << 10) -#else -#define MG3_10_111PL 0xFFFF -#endif - -#if (G3_12PL >= G3_10PL) || (G3_12PL == 0) -#define MG3_10_112PL ~(1 << 11) -#else -#define MG3_10_112PL 0xFFFF -#endif - -#if (G3_13PL >= G3_10PL) || (G3_13PL == 0) -#define MG3_10_113PL ~(1 << 12) -#else -#define MG3_10_113PL 0xFFFF -#endif - -#if (G3_14PL >= G3_10PL) || (G3_14PL == 0) -#define MG3_10_114PL ~(1 << 13) -#else -#define MG3_10_114PL 0xFFFF -#endif - -#if (G3_15PL >= G3_10PL) || (G3_15PL == 0) -#define MG3_10_115PL ~(1 << 14) -#else -#define MG3_10_115PL 0xFFFF -#endif - -#if (G3_16PL >= G3_10PL) || (G3_16PL == 0) -#define MG3_10_116PL ~(1 << 15) -#else -#define MG3_10_116PL 0xFFFF -#endif - -#define MG3_10_110PL 0xFDFF -#define MG3_10 (MG3_10_11PL & MG3_10_12PL & MG3_10_13PL & MG3_10_14PL & \ - MG3_10_15PL & MG3_10_16PL & MG3_10_17PL & MG3_10_18PL & \ - MG3_10_19PL & MG3_10_110PL & MG3_10_111PL & MG3_10_112PL & \ - MG3_10_113PL & MG3_10_114PL & MG3_10_115PL & MG3_10_116PL) -// End of MG3_10: -// Beginning of MG311: -#if (G3_1PL >= G3_11PL) || (G3_1PL == 0) -#define MG3_11_11PL ~(1 << 0) -#else -#define MG3_11_11PL 0xFFFF -#endif - -#if (G3_2PL >= G3_11PL) || (G3_2PL == 0) -#define MG3_11_12PL ~(1 << 1) -#else -#define MG3_11_12PL 0xFFFF -#endif - -#if (G3_3PL >= G3_11PL) || (G3_3PL == 0) -#define MG3_11_13PL ~(1 << 2) -#else -#define MG3_11_13PL 0xFFFF -#endif - -#if (G3_4PL >= G3_11PL) || (G3_4PL == 0) -#define MG3_11_14PL ~(1 << 3) -#else -#define MG3_11_14PL 0xFFFF -#endif - -#if (G3_5PL >= G3_11PL) || (G3_5PL == 0) -#define MG3_11_15PL ~(1 << 4) -#else -#define MG3_11_15PL 0xFFFF -#endif - -#if (G3_6PL >= G3_11PL) || (G3_6PL == 0) -#define MG3_11_16PL ~(1 << 5) -#else -#define MG3_11_16PL 0xFFFF -#endif - -#if (G3_7PL >= G3_11PL) || (G3_7PL == 0) -#define MG3_11_17PL ~(1 << 6) -#else -#define MG3_11_17PL 0xFFFF -#endif - -#if (G3_8PL >= G3_11PL) || (G3_8PL == 0) -#define MG3_11_18PL ~(1 << 7) -#else -#define MG3_11_18PL 0xFFFF -#endif - -#if (G3_9PL >= G3_11PL) || (G3_9PL == 0) -#define MG3_11_19PL ~(1 << 8) -#else -#define MG3_11_19PL 0xFFFF -#endif - -#if (G3_10PL >= G3_11PL) || (G3_10PL == 0) -#define MG3_11_110PL ~(1 << 9) -#else -#define MG3_11_110PL 0xFFFF -#endif - -#if (G3_12PL >= G3_11PL) || (G3_12PL == 0) -#define MG3_11_112PL ~(1 << 11) -#else -#define MG3_11_112PL 0xFFFF -#endif - -#if (G3_13PL >= G3_11PL) || (G3_13PL == 0) -#define MG3_11_113PL ~(1 << 12) -#else -#define MG3_11_113PL 0xFFFF -#endif - -#if (G3_14PL >= G3_11PL) || (G3_14PL == 0) -#define MG3_11_114PL ~(1 << 13) -#else -#define MG3_11_114PL 0xFFFF -#endif - -#if (G3_15PL >= G3_11PL) || (G3_15PL == 0) -#define MG3_11_115PL ~(1 << 14) -#else -#define MG3_11_115PL 0xFFFF -#endif - -#if (G3_16PL >= G3_11PL) || (G3_16PL == 0) -#define MG3_11_116PL ~(1 << 15) -#else -#define MG3_11_116PL 0xFFFF -#endif - -#define MG3_11_111PL 0xFBFF -#define MG3_11 (MG3_11_11PL & MG3_11_12PL & MG3_11_13PL & MG3_11_14PL & \ - MG3_11_15PL & MG3_11_16PL & MG3_11_17PL & MG3_11_18PL & \ - MG3_11_19PL & MG3_11_110PL & MG3_11_111PL & MG3_11_112PL & \ - MG3_11_113PL & MG3_11_114PL & MG3_11_115PL & MG3_11_116PL) -// End of MG3_11: -// Beginning of MG312: -#if (G3_1PL >= G3_12PL) || (G3_1PL == 0) -#define MG3_12_11PL ~(1 << 0) -#else -#define MG3_12_11PL 0xFFFF -#endif - -#if (G3_2PL >= G3_12PL) || (G3_2PL == 0) -#define MG3_12_12PL ~(1 << 1) -#else -#define MG3_12_12PL 0xFFFF -#endif - -#if (G3_3PL >= G3_12PL) || (G3_3PL == 0) -#define MG3_12_13PL ~(1 << 2) -#else -#define MG3_12_13PL 0xFFFF -#endif - -#if (G3_4PL >= G3_12PL) || (G3_4PL == 0) -#define MG3_12_14PL ~(1 << 3) -#else -#define MG3_12_14PL 0xFFFF -#endif - -#if (G3_5PL >= G3_12PL) || (G3_5PL == 0) -#define MG3_12_15PL ~(1 << 4) -#else -#define MG3_12_15PL 0xFFFF -#endif - -#if (G3_6PL >= G3_12PL) || (G3_6PL == 0) -#define MG3_12_16PL ~(1 << 5) -#else -#define MG3_12_16PL 0xFFFF -#endif - -#if (G3_7PL >= G3_12PL) || (G3_7PL == 0) -#define MG3_12_17PL ~(1 << 6) -#else -#define MG3_12_17PL 0xFFFF -#endif - -#if (G3_8PL >= G3_12PL) || (G3_8PL == 0) -#define MG3_12_18PL ~(1 << 7) -#else -#define MG3_12_18PL 0xFFFF -#endif - -#if (G3_9PL >= G3_12PL) || (G3_9PL == 0) -#define MG3_12_19PL ~(1 << 8) -#else -#define MG3_12_19PL 0xFFFF -#endif - -#if (G3_10PL >= G3_12PL) || (G3_10PL == 0) -#define MG3_12_110PL ~(1 << 9) -#else -#define MG3_12_110PL 0xFFFF -#endif - -#if (G3_11PL >= G3_12PL) || (G3_11PL == 0) -#define MG3_12_111PL ~(1 << 10) -#else -#define MG3_12_111PL 0xFFFF -#endif - -#if (G3_13PL >= G3_12PL) || (G3_13PL == 0) -#define MG3_12_113PL ~(1 << 12) -#else -#define MG3_12_113PL 0xFFFF -#endif - -#if (G3_14PL >= G3_12PL) || (G3_14PL == 0) -#define MG3_12_114PL ~(1 << 13) -#else -#define MG3_12_114PL 0xFFFF -#endif - -#if (G3_15PL >= G3_12PL) || (G3_15PL == 0) -#define MG3_12_115PL ~(1 << 14) -#else -#define MG3_12_115PL 0xFFFF -#endif - -#if (G3_16PL >= G3_12PL) || (G3_16PL == 0) -#define MG3_12_116PL ~(1 << 15) -#else -#define MG3_12_116PL 0xFFFF -#endif - -#define MG3_12_112PL 0xF7FF -#define MG3_12 (MG3_12_11PL & MG3_12_12PL & MG3_12_13PL & MG3_12_14PL & \ - MG3_12_15PL & MG3_12_16PL & MG3_12_17PL & MG3_12_18PL & \ - MG3_12_19PL & MG3_12_110PL & MG3_12_111PL & MG3_12_112PL & \ - MG3_12_113PL & MG3_12_114PL & MG3_12_115PL & MG3_12_116PL) -// End of MG3_12: -// Beginning of MG313: -#if (G3_1PL >= G3_13PL) || (G3_1PL == 0) -#define MG3_13_11PL ~(1 << 0) -#else -#define MG3_13_11PL 0xFFFF -#endif - -#if (G3_2PL >= G3_13PL) || (G3_2PL == 0) -#define MG3_13_12PL ~(1 << 1) -#else -#define MG3_13_12PL 0xFFFF -#endif - -#if (G3_3PL >= G3_13PL) || (G3_3PL == 0) -#define MG3_13_13PL ~(1 << 2) -#else -#define MG3_13_13PL 0xFFFF -#endif - -#if (G3_4PL >= G3_13PL) || (G3_4PL == 0) -#define MG3_13_14PL ~(1 << 3) -#else -#define MG3_13_14PL 0xFFFF -#endif - -#if (G3_5PL >= G3_13PL) || (G3_5PL == 0) -#define MG3_13_15PL ~(1 << 4) -#else -#define MG3_13_15PL 0xFFFF -#endif - -#if (G3_6PL >= G3_13PL) || (G3_6PL == 0) -#define MG3_13_16PL ~(1 << 5) -#else -#define MG3_13_16PL 0xFFFF -#endif - -#if (G3_7PL >= G3_13PL) || (G3_7PL == 0) -#define MG3_13_17PL ~(1 << 6) -#else -#define MG3_13_17PL 0xFFFF -#endif - -#if (G3_8PL >= G3_13PL) || (G3_8PL == 0) -#define MG3_13_18PL ~(1 << 7) -#else -#define MG3_13_18PL 0xFFFF -#endif - -#if (G3_9PL >= G3_13PL) || (G3_9PL == 0) -#define MG3_13_19PL ~(1 << 8) -#else -#define MG3_13_19PL 0xFFFF -#endif - -#if (G3_10PL >= G3_13PL) || (G3_10PL == 0) -#define MG3_13_110PL ~(1 << 9) -#else -#define MG3_13_110PL 0xFFFF -#endif - -#if (G3_11PL >= G3_13PL) || (G3_11PL == 0) -#define MG3_13_111PL ~(1 << 10) -#else -#define MG3_13_111PL 0xFFFF -#endif - -#if (G3_12PL >= G3_13PL) || (G3_12PL == 0) -#define MG3_13_112PL ~(1 << 11) -#else -#define MG3_13_112PL 0xFFFF -#endif - -#if (G3_14PL >= G3_13PL) || (G3_14PL == 0) -#define MG3_13_114PL ~(1 << 13) -#else -#define MG3_13_114PL 0xFFFF -#endif - -#if (G3_15PL >= G3_13PL) || (G3_15PL == 0) -#define MG3_13_115PL ~(1 << 14) -#else -#define MG3_13_115PL 0xFFFF -#endif - -#if (G3_16PL >= G3_13PL) || (G3_16PL == 0) -#define MG3_13_116PL ~(1 << 15) -#else -#define MG3_13_116PL 0xFFFF -#endif - -#define MG3_13_113PL 0xEFFF -#define MG3_13 (MG3_13_11PL & MG3_13_12PL & MG3_13_13PL & MG3_13_14PL & \ - MG3_13_15PL & MG3_13_16PL & MG3_13_17PL & MG3_13_18PL & \ - MG3_13_19PL & MG3_13_110PL & MG3_13_111PL & MG3_13_112PL & \ - MG3_13_113PL & MG3_13_114PL & MG3_13_115PL & MG3_13_116PL) -// End of MG3_13: -// Beginning of MG314: -#if (G3_1PL >= G3_14PL) || (G3_1PL == 0) -#define MG3_14_11PL ~(1 << 0) -#else -#define MG3_14_11PL 0xFFFF -#endif - -#if (G3_2PL >= G3_14PL) || (G3_2PL == 0) -#define MG3_14_12PL ~(1 << 1) -#else -#define MG3_14_12PL 0xFFFF -#endif - -#if (G3_3PL >= G3_14PL) || (G3_3PL == 0) -#define MG3_14_13PL ~(1 << 2) -#else -#define MG3_14_13PL 0xFFFF -#endif - -#if (G3_4PL >= G3_14PL) || (G3_4PL == 0) -#define MG3_14_14PL ~(1 << 3) -#else -#define MG3_14_14PL 0xFFFF -#endif - -#if (G3_5PL >= G3_14PL) || (G3_5PL == 0) -#define MG3_14_15PL ~(1 << 4) -#else -#define MG3_14_15PL 0xFFFF -#endif - -#if (G3_6PL >= G3_14PL) || (G3_6PL == 0) -#define MG3_14_16PL ~(1 << 5) -#else -#define MG3_14_16PL 0xFFFF -#endif - -#if (G3_7PL >= G3_14PL) || (G3_7PL == 0) -#define MG3_14_17PL ~(1 << 6) -#else -#define MG3_14_17PL 0xFFFF -#endif - -#if (G3_8PL >= G3_14PL) || (G3_8PL == 0) -#define MG3_14_18PL ~(1 << 7) -#else -#define MG3_14_18PL 0xFFFF -#endif - -#if (G3_9PL >= G3_14PL) || (G3_9PL == 0) -#define MG3_14_19PL ~(1 << 8) -#else -#define MG3_14_19PL 0xFFFF -#endif - -#if (G3_10PL >= G3_14PL) || (G3_10PL == 0) -#define MG3_14_110PL ~(1 << 9) -#else -#define MG3_14_110PL 0xFFFF -#endif - -#if (G3_11PL >= G3_14PL) || (G3_11PL == 0) -#define MG3_14_111PL ~(1 << 10) -#else -#define MG3_14_111PL 0xFFFF -#endif - -#if (G3_12PL >= G3_14PL) || (G3_12PL == 0) -#define MG3_14_112PL ~(1 << 11) -#else -#define MG3_14_112PL 0xFFFF -#endif - -#if (G3_13PL >= G3_14PL) || (G3_13PL == 0) -#define MG3_14_113PL ~(1 << 12) -#else -#define MG3_14_113PL 0xFFFF -#endif - -#if (G3_15PL >= G3_14PL) || (G3_15PL == 0) -#define MG3_14_115PL ~(1 << 14) -#else -#define MG3_14_115PL 0xFFFF -#endif - -#if (G3_16PL >= G3_14PL) || (G3_16PL == 0) -#define MG3_14_116PL ~(1 << 15) -#else -#define MG3_14_116PL 0xFFFF -#endif - -#define MG3_14_114PL 0xDFFF -#define MG3_14 (MG3_14_11PL & MG3_14_12PL & MG3_14_13PL & MG3_14_14PL & \ - MG3_14_15PL & MG3_14_16PL & MG3_14_17PL & MG3_14_18PL & \ - MG3_14_19PL & MG3_14_110PL & MG3_14_111PL & MG3_14_112PL & \ - MG3_14_113PL & MG3_14_114PL & MG3_14_115PL & MG3_14_116PL) -// End of MG3_14: -// Beginning of MG315: -#if (G3_1PL >= G3_15PL) || (G3_1PL == 0) -#define MG3_15_11PL ~(1 << 0) -#else -#define MG3_15_11PL 0xFFFF -#endif - -#if (G3_2PL >= G3_15PL) || (G3_2PL == 0) -#define MG3_15_12PL ~(1 << 1) -#else -#define MG3_15_12PL 0xFFFF -#endif - -#if (G3_3PL >= G3_15PL) || (G3_3PL == 0) -#define MG3_15_13PL ~(1 << 2) -#else -#define MG3_15_13PL 0xFFFF -#endif - -#if (G3_4PL >= G3_15PL) || (G3_4PL == 0) -#define MG3_15_14PL ~(1 << 3) -#else -#define MG3_15_14PL 0xFFFF -#endif - -#if (G3_5PL >= G3_15PL) || (G3_5PL == 0) -#define MG3_15_15PL ~(1 << 4) -#else -#define MG3_15_15PL 0xFFFF -#endif - -#if (G3_6PL >= G3_15PL) || (G3_6PL == 0) -#define MG3_15_16PL ~(1 << 5) -#else -#define MG3_15_16PL 0xFFFF -#endif - -#if (G3_7PL >= G3_15PL) || (G3_7PL == 0) -#define MG3_15_17PL ~(1 << 6) -#else -#define MG3_15_17PL 0xFFFF -#endif - -#if (G3_8PL >= G3_15PL) || (G3_8PL == 0) -#define MG3_15_18PL ~(1 << 7) -#else -#define MG3_15_18PL 0xFFFF -#endif - -#if (G3_9PL >= G3_15PL) || (G3_9PL == 0) -#define MG3_15_19PL ~(1 << 8) -#else -#define MG3_15_19PL 0xFFFF -#endif - -#if (G3_10PL >= G3_15PL) || (G3_10PL == 0) -#define MG3_15_110PL ~(1 << 9) -#else -#define MG3_15_110PL 0xFFFF -#endif - -#if (G3_11PL >= G3_15PL) || (G3_11PL == 0) -#define MG3_15_111PL ~(1 << 10) -#else -#define MG3_15_111PL 0xFFFF -#endif - -#if (G3_12PL >= G3_15PL) || (G3_12PL == 0) -#define MG3_15_112PL ~(1 << 11) -#else -#define MG3_15_112PL 0xFFFF -#endif - -#if (G3_13PL >= G3_15PL) || (G3_13PL == 0) -#define MG3_15_113PL ~(1 << 12) -#else -#define MG3_15_113PL 0xFFFF -#endif - -#if (G3_14PL >= G3_15PL) || (G3_14PL == 0) -#define MG3_15_114PL ~(1 << 13) -#else -#define MG3_15_114PL 0xFFFF -#endif - -#if (G3_16PL >= G3_15PL) || (G3_16PL == 0) -#define MG3_15_116PL ~(1 << 15) -#else -#define MG3_15_116PL 0xFFFF -#endif - -#define MG3_15_115PL 0xBFFF -#define MG3_15 (MG3_15_11PL & MG3_15_12PL & MG3_15_13PL & MG3_15_14PL & \ - MG3_15_15PL & MG3_15_16PL & MG3_15_17PL & MG3_15_18PL & \ - MG3_15_19PL & MG3_15_110PL & MG3_15_111PL & MG3_15_112PL & \ - MG3_15_113PL & MG3_15_114PL & MG3_15_115PL & MG3_15_116PL) -// End of MG3_15: -// Beginning of MG316: -#if (G3_1PL >= G3_16PL) || (G3_1PL == 0) -#define MG3_16_11PL ~(1 << 0) -#else -#define MG3_16_11PL 0xFFFF -#endif - -#if (G3_2PL >= G3_16PL) || (G3_2PL == 0) -#define MG3_16_12PL ~(1 << 1) -#else -#define MG3_16_12PL 0xFFFF -#endif - -#if (G3_3PL >= G3_16PL) || (G3_3PL == 0) -#define MG3_16_13PL ~(1 << 2) -#else -#define MG3_16_13PL 0xFFFF -#endif - -#if (G3_4PL >= G3_16PL) || (G3_4PL == 0) -#define MG3_16_14PL ~(1 << 3) -#else -#define MG3_16_14PL 0xFFFF -#endif - -#if (G3_5PL >= G3_16PL) || (G3_5PL == 0) -#define MG3_16_15PL ~(1 << 4) -#else -#define MG3_16_15PL 0xFFFF -#endif - -#if (G3_6PL >= G3_16PL) || (G3_6PL == 0) -#define MG3_16_16PL ~(1 << 5) -#else -#define MG3_16_16PL 0xFFFF -#endif - -#if (G3_7PL >= G3_16PL) || (G3_7PL == 0) -#define MG3_16_17PL ~(1 << 6) -#else -#define MG3_16_17PL 0xFFFF -#endif - -#if (G3_8PL >= G3_16PL) || (G3_8PL == 0) -#define MG3_16_18PL ~(1 << 7) -#else -#define MG3_16_18PL 0xFFFF -#endif - -#if (G3_9PL >= G3_16PL) || (G3_9PL == 0) -#define MG3_16_19PL ~(1 << 8) -#else -#define MG3_16_19PL 0xFFFF -#endif - -#if (G3_10PL >= G3_16PL) || (G3_10PL == 0) -#define MG3_16_110PL ~(1 << 9) -#else -#define MG3_16_110PL 0xFFFF -#endif - -#if (G3_11PL >= G3_16PL) || (G3_11PL == 0) -#define MG3_16_111PL ~(1 << 10) -#else -#define MG3_16_111PL 0xFFFF -#endif - -#if (G3_12PL >= G3_16PL) || (G3_12PL == 0) -#define MG3_16_112PL ~(1 << 11) -#else -#define MG3_16_112PL 0xFFFF -#endif - -#if (G3_13PL >= G3_16PL) || (G3_13PL == 0) -#define MG3_16_113PL ~(1 << 12) -#else -#define MG3_16_113PL 0xFFFF -#endif - -#if (G3_14PL >= G3_16PL) || (G3_14PL == 0) -#define MG3_16_114PL ~(1 << 13) -#else -#define MG3_16_114PL 0xFFFF -#endif - -#if (G3_15PL >= G3_16PL) || (G3_15PL == 0) -#define MG3_16_115PL ~(1 << 14) -#else -#define MG3_16_115PL 0xFFFF -#endif - -#define MG3_16_116PL 0x7FFF -#define MG3_16 (MG3_16_11PL & MG3_16_12PL & MG3_16_13PL & MG3_16_14PL & \ - MG3_16_15PL & MG3_16_16PL & MG3_16_17PL & MG3_16_18PL & \ - MG3_16_19PL & MG3_16_110PL & MG3_16_111PL & MG3_16_112PL & \ - MG3_16_113PL & MG3_16_114PL & MG3_16_115PL & MG3_16_116PL) -// End of MG3_16: - - -// -// Automatically generate PIEIER4 interrupt masks MG41 to MG416: -// - -// Beginning of MG41: -#if (G4_2PL >= G4_1PL) || (G4_2PL == 0) -#define MG4_1_12PL ~(1 << 1) -#else -#define MG4_1_12PL 0xFFFF -#endif - -#if (G4_3PL >= G4_1PL) || (G4_3PL == 0) -#define MG4_1_13PL ~(1 << 2) -#else -#define MG4_1_13PL 0xFFFF -#endif - -#if (G4_4PL >= G4_1PL) || (G4_4PL == 0) -#define MG4_1_14PL ~(1 << 3) -#else -#define MG4_1_14PL 0xFFFF -#endif - -#if (G4_5PL >= G4_1PL) || (G4_5PL == 0) -#define MG4_1_15PL ~(1 << 4) -#else -#define MG4_1_15PL 0xFFFF -#endif - -#if (G4_6PL >= G4_1PL) || (G4_6PL == 0) -#define MG4_1_16PL ~(1 << 5) -#else -#define MG4_1_16PL 0xFFFF -#endif - -#if (G4_7PL >= G4_1PL) || (G4_7PL == 0) -#define MG4_1_17PL ~(1 << 6) -#else -#define MG4_1_17PL 0xFFFF -#endif - -#if (G4_8PL >= G4_1PL) || (G4_8PL == 0) -#define MG4_1_18PL ~(1 << 7) -#else -#define MG4_1_18PL 0xFFFF -#endif - -#if (G4_9PL >= G4_1PL) || (G4_9PL == 0) -#define MG4_1_19PL ~(1 << 8) -#else -#define MG4_1_19PL 0xFFFF -#endif - -#if (G4_10PL >= G4_1PL) || (G4_10PL == 0) -#define MG4_1_110PL ~(1 << 9) -#else -#define MG4_1_110PL 0xFFFF -#endif - -#if (G4_11PL >= G4_1PL) || (G4_11PL == 0) -#define MG4_1_111PL ~(1 << 10) -#else -#define MG4_1_111PL 0xFFFF -#endif - -#if (G4_12PL >= G4_1PL) || (G4_12PL == 0) -#define MG4_1_112PL ~(1 << 11) -#else -#define MG4_1_112PL 0xFFFF -#endif - -#if (G4_13PL >= G4_1PL) || (G4_13PL == 0) -#define MG4_1_113PL ~(1 << 12) -#else -#define MG4_1_113PL 0xFFFF -#endif - -#if (G4_14PL >= G4_1PL) || (G4_14PL == 0) -#define MG4_1_114PL ~(1 << 13) -#else -#define MG4_1_114PL 0xFFFF -#endif - -#if (G4_15PL >= G4_1PL) || (G4_15PL == 0) -#define MG4_1_115PL ~(1 << 14) -#else -#define MG4_1_115PL 0xFFFF -#endif - -#if (G4_16PL >= G4_1PL) || (G4_16PL == 0) -#define MG4_1_116PL ~(1 << 15) -#else -#define MG4_1_116PL 0xFFFF -#endif - -#define MG4_1_11PL 0xFFFE -#define MG4_1 (MG4_1_11PL & MG4_1_12PL & MG4_1_13PL & MG4_1_14PL & \ - MG4_1_15PL & MG4_1_16PL & MG4_1_17PL & MG4_1_18PL & \ - MG4_1_19PL & MG4_1_110PL & MG4_1_111PL & MG4_1_112PL & \ - MG4_1_113PL & MG4_1_114PL & MG4_1_115PL & MG4_1_116PL) -// End of MG4_1: -// Beginning of MG42: -#if (G4_1PL >= G4_2PL) || (G4_1PL == 0) -#define MG4_2_11PL ~(1 << 0) -#else -#define MG4_2_11PL 0xFFFF -#endif - -#if (G4_3PL >= G4_2PL) || (G4_3PL == 0) -#define MG4_2_13PL ~(1 << 2) -#else -#define MG4_2_13PL 0xFFFF -#endif - -#if (G4_4PL >= G4_2PL) || (G4_4PL == 0) -#define MG4_2_14PL ~(1 << 3) -#else -#define MG4_2_14PL 0xFFFF -#endif - -#if (G4_5PL >= G4_2PL) || (G4_5PL == 0) -#define MG4_2_15PL ~(1 << 4) -#else -#define MG4_2_15PL 0xFFFF -#endif - -#if (G4_6PL >= G4_2PL) || (G4_6PL == 0) -#define MG4_2_16PL ~(1 << 5) -#else -#define MG4_2_16PL 0xFFFF -#endif - -#if (G4_7PL >= G4_2PL) || (G4_7PL == 0) -#define MG4_2_17PL ~(1 << 6) -#else -#define MG4_2_17PL 0xFFFF -#endif - -#if (G4_8PL >= G4_2PL) || (G4_8PL == 0) -#define MG4_2_18PL ~(1 << 7) -#else -#define MG4_2_18PL 0xFFFF -#endif - -#if (G4_9PL >= G4_2PL) || (G4_9PL == 0) -#define MG4_2_19PL ~(1 << 8) -#else -#define MG4_2_19PL 0xFFFF -#endif - -#if (G4_10PL >= G4_2PL) || (G4_10PL == 0) -#define MG4_2_110PL ~(1 << 9) -#else -#define MG4_2_110PL 0xFFFF -#endif - -#if (G4_11PL >= G4_2PL) || (G4_11PL == 0) -#define MG4_2_111PL ~(1 << 10) -#else -#define MG4_2_111PL 0xFFFF -#endif - -#if (G4_12PL >= G4_2PL) || (G4_12PL == 0) -#define MG4_2_112PL ~(1 << 11) -#else -#define MG4_2_112PL 0xFFFF -#endif - -#if (G4_13PL >= G4_2PL) || (G4_13PL == 0) -#define MG4_2_113PL ~(1 << 12) -#else -#define MG4_2_113PL 0xFFFF -#endif - -#if (G4_14PL >= G4_2PL) || (G4_14PL == 0) -#define MG4_2_114PL ~(1 << 13) -#else -#define MG4_2_114PL 0xFFFF -#endif - -#if (G4_15PL >= G4_2PL) || (G4_15PL == 0) -#define MG4_2_115PL ~(1 << 14) -#else -#define MG4_2_115PL 0xFFFF -#endif - -#if (G4_16PL >= G4_2PL) || (G4_16PL == 0) -#define MG4_2_116PL ~(1 << 15) -#else -#define MG4_2_116PL 0xFFFF -#endif - -#define MG4_2_12PL 0xFFFD -#define MG4_2 (MG4_2_11PL & MG4_2_12PL & MG4_2_13PL & MG4_2_14PL & \ - MG4_2_15PL & MG4_2_16PL & MG4_2_17PL & MG4_2_18PL & \ - MG4_2_19PL & MG4_2_110PL & MG4_2_111PL & MG4_2_112PL & \ - MG4_2_113PL & MG4_2_114PL & MG4_2_115PL & MG4_2_116PL) -// End of MG4_2: -// Beginning of MG43: -#if (G4_1PL >= G4_3PL) || (G4_1PL == 0) -#define MG4_3_11PL ~(1 << 0) -#else -#define MG4_3_11PL 0xFFFF -#endif - -#if (G4_2PL >= G4_3PL) || (G4_2PL == 0) -#define MG4_3_12PL ~(1 << 1) -#else -#define MG4_3_12PL 0xFFFF -#endif - -#if (G4_4PL >= G4_3PL) || (G4_4PL == 0) -#define MG4_3_14PL ~(1 << 3) -#else -#define MG4_3_14PL 0xFFFF -#endif - -#if (G4_5PL >= G4_3PL) || (G4_5PL == 0) -#define MG4_3_15PL ~(1 << 4) -#else -#define MG4_3_15PL 0xFFFF -#endif - -#if (G4_6PL >= G4_3PL) || (G4_6PL == 0) -#define MG4_3_16PL ~(1 << 5) -#else -#define MG4_3_16PL 0xFFFF -#endif - -#if (G4_7PL >= G4_3PL) || (G4_7PL == 0) -#define MG4_3_17PL ~(1 << 6) -#else -#define MG4_3_17PL 0xFFFF -#endif - -#if (G4_8PL >= G4_3PL) || (G4_8PL == 0) -#define MG4_3_18PL ~(1 << 7) -#else -#define MG4_3_18PL 0xFFFF -#endif - -#if (G4_9PL >= G4_3PL) || (G4_9PL == 0) -#define MG4_3_19PL ~(1 << 8) -#else -#define MG4_3_19PL 0xFFFF -#endif - -#if (G4_10PL >= G4_3PL) || (G4_10PL == 0) -#define MG4_3_110PL ~(1 << 9) -#else -#define MG4_3_110PL 0xFFFF -#endif - -#if (G4_11PL >= G4_3PL) || (G4_11PL == 0) -#define MG4_3_111PL ~(1 << 10) -#else -#define MG4_3_111PL 0xFFFF -#endif - -#if (G4_12PL >= G4_3PL) || (G4_12PL == 0) -#define MG4_3_112PL ~(1 << 11) -#else -#define MG4_3_112PL 0xFFFF -#endif - -#if (G4_13PL >= G4_3PL) || (G4_13PL == 0) -#define MG4_3_113PL ~(1 << 12) -#else -#define MG4_3_113PL 0xFFFF -#endif - -#if (G4_14PL >= G4_3PL) || (G4_14PL == 0) -#define MG4_3_114PL ~(1 << 13) -#else -#define MG4_3_114PL 0xFFFF -#endif - -#if (G4_15PL >= G4_3PL) || (G4_15PL == 0) -#define MG4_3_115PL ~(1 << 14) -#else -#define MG4_3_115PL 0xFFFF -#endif - -#if (G4_16PL >= G4_3PL) || (G4_16PL == 0) -#define MG4_3_116PL ~(1 << 15) -#else -#define MG4_3_116PL 0xFFFF -#endif - -#define MG4_3_13PL 0xFFFB -#define MG4_3 (MG4_3_11PL & MG4_3_12PL & MG4_3_13PL & MG4_3_14PL & \ - MG4_3_15PL & MG4_3_16PL & MG4_3_17PL & MG4_3_18PL & \ - MG4_3_19PL & MG4_3_110PL & MG4_3_111PL & MG4_3_112PL & \ - MG4_3_113PL & MG4_3_114PL & MG4_3_115PL & MG4_3_116PL) -// End of MG4_3: -// Beginning of MG44: -#if (G4_1PL >= G4_4PL) || (G4_1PL == 0) -#define MG4_4_11PL ~(1 << 0) -#else -#define MG4_4_11PL 0xFFFF -#endif - -#if (G4_2PL >= G4_4PL) || (G4_2PL == 0) -#define MG4_4_12PL ~(1 << 1) -#else -#define MG4_4_12PL 0xFFFF -#endif - -#if (G4_3PL >= G4_4PL) || (G4_3PL == 0) -#define MG4_4_13PL ~(1 << 2) -#else -#define MG4_4_13PL 0xFFFF -#endif - -#if (G4_5PL >= G4_4PL) || (G4_5PL == 0) -#define MG4_4_15PL ~(1 << 4) -#else -#define MG4_4_15PL 0xFFFF -#endif - -#if (G4_6PL >= G4_4PL) || (G4_6PL == 0) -#define MG4_4_16PL ~(1 << 5) -#else -#define MG4_4_16PL 0xFFFF -#endif - -#if (G4_7PL >= G4_4PL) || (G4_7PL == 0) -#define MG4_4_17PL ~(1 << 6) -#else -#define MG4_4_17PL 0xFFFF -#endif - -#if (G4_8PL >= G4_4PL) || (G4_8PL == 0) -#define MG4_4_18PL ~(1 << 7) -#else -#define MG4_4_18PL 0xFFFF -#endif - -#if (G4_9PL >= G4_4PL) || (G4_9PL == 0) -#define MG4_4_19PL ~(1 << 8) -#else -#define MG4_4_19PL 0xFFFF -#endif - -#if (G4_10PL >= G4_4PL) || (G4_10PL == 0) -#define MG4_4_110PL ~(1 << 9) -#else -#define MG4_4_110PL 0xFFFF -#endif - -#if (G4_11PL >= G4_4PL) || (G4_11PL == 0) -#define MG4_4_111PL ~(1 << 10) -#else -#define MG4_4_111PL 0xFFFF -#endif - -#if (G4_12PL >= G4_4PL) || (G4_12PL == 0) -#define MG4_4_112PL ~(1 << 11) -#else -#define MG4_4_112PL 0xFFFF -#endif - -#if (G4_13PL >= G4_4PL) || (G4_13PL == 0) -#define MG4_4_113PL ~(1 << 12) -#else -#define MG4_4_113PL 0xFFFF -#endif - -#if (G4_14PL >= G4_4PL) || (G4_14PL == 0) -#define MG4_4_114PL ~(1 << 13) -#else -#define MG4_4_114PL 0xFFFF -#endif - -#if (G4_15PL >= G4_4PL) || (G4_15PL == 0) -#define MG4_4_115PL ~(1 << 14) -#else -#define MG4_4_115PL 0xFFFF -#endif - -#if (G4_16PL >= G4_4PL) || (G4_16PL == 0) -#define MG4_4_116PL ~(1 << 15) -#else -#define MG4_4_116PL 0xFFFF -#endif - -#define MG4_4_14PL 0xFFF7 -#define MG4_4 (MG4_4_11PL & MG4_4_12PL & MG4_4_13PL & MG4_4_14PL & \ - MG4_4_15PL & MG4_4_16PL & MG4_4_17PL & MG4_4_18PL & \ - MG4_4_19PL & MG4_4_110PL & MG4_4_111PL & MG4_4_112PL & \ - MG4_4_113PL & MG4_4_114PL & MG4_4_115PL & MG4_4_116PL) -// End of MG4_4: -// Beginning of MG45: -#if (G4_1PL >= G4_5PL) || (G4_1PL == 0) -#define MG4_5_11PL ~(1 << 0) -#else -#define MG4_5_11PL 0xFFFF -#endif - -#if (G4_2PL >= G4_5PL) || (G4_2PL == 0) -#define MG4_5_12PL ~(1 << 1) -#else -#define MG4_5_12PL 0xFFFF -#endif - -#if (G4_3PL >= G4_5PL) || (G4_3PL == 0) -#define MG4_5_13PL ~(1 << 2) -#else -#define MG4_5_13PL 0xFFFF -#endif - -#if (G4_4PL >= G4_5PL) || (G4_4PL == 0) -#define MG4_5_14PL ~(1 << 3) -#else -#define MG4_5_14PL 0xFFFF -#endif - -#if (G4_6PL >= G4_5PL) || (G4_6PL == 0) -#define MG4_5_16PL ~(1 << 5) -#else -#define MG4_5_16PL 0xFFFF -#endif - -#if (G4_7PL >= G4_5PL) || (G4_7PL == 0) -#define MG4_5_17PL ~(1 << 6) -#else -#define MG4_5_17PL 0xFFFF -#endif - -#if (G4_8PL >= G4_5PL) || (G4_8PL == 0) -#define MG4_5_18PL ~(1 << 7) -#else -#define MG4_5_18PL 0xFFFF -#endif - -#if (G4_9PL >= G4_5PL) || (G4_9PL == 0) -#define MG4_5_19PL ~(1 << 8) -#else -#define MG4_5_19PL 0xFFFF -#endif - -#if (G4_10PL >= G4_5PL) || (G4_10PL == 0) -#define MG4_5_110PL ~(1 << 9) -#else -#define MG4_5_110PL 0xFFFF -#endif - -#if (G4_11PL >= G4_5PL) || (G4_11PL == 0) -#define MG4_5_111PL ~(1 << 10) -#else -#define MG4_5_111PL 0xFFFF -#endif - -#if (G4_12PL >= G4_5PL) || (G4_12PL == 0) -#define MG4_5_112PL ~(1 << 11) -#else -#define MG4_5_112PL 0xFFFF -#endif - -#if (G4_13PL >= G4_5PL) || (G4_13PL == 0) -#define MG4_5_113PL ~(1 << 12) -#else -#define MG4_5_113PL 0xFFFF -#endif - -#if (G4_14PL >= G4_5PL) || (G4_14PL == 0) -#define MG4_5_114PL ~(1 << 13) -#else -#define MG4_5_114PL 0xFFFF -#endif - -#if (G4_15PL >= G4_5PL) || (G4_15PL == 0) -#define MG4_5_115PL ~(1 << 14) -#else -#define MG4_5_115PL 0xFFFF -#endif - -#if (G4_16PL >= G4_5PL) || (G4_16PL == 0) -#define MG4_5_116PL ~(1 << 15) -#else -#define MG4_5_116PL 0xFFFF -#endif - -#define MG4_5_15PL 0xFFEF -#define MG4_5 (MG4_5_11PL & MG4_5_12PL & MG4_5_13PL & MG4_5_14PL & \ - MG4_5_15PL & MG4_5_16PL & MG4_5_17PL & MG4_5_18PL & \ - MG4_5_19PL & MG4_5_110PL & MG4_5_111PL & MG4_5_112PL & \ - MG4_5_113PL & MG4_5_114PL & MG4_5_115PL & MG4_5_116PL) -// End of MG4_5: -// Beginning of MG46: -#if (G4_1PL >= G4_6PL) || (G4_1PL == 0) -#define MG4_6_11PL ~(1 << 0) -#else -#define MG4_6_11PL 0xFFFF -#endif - -#if (G4_2PL >= G4_6PL) || (G4_2PL == 0) -#define MG4_6_12PL ~(1 << 1) -#else -#define MG4_6_12PL 0xFFFF -#endif - -#if (G4_3PL >= G4_6PL) || (G4_3PL == 0) -#define MG4_6_13PL ~(1 << 2) -#else -#define MG4_6_13PL 0xFFFF -#endif - -#if (G4_4PL >= G4_6PL) || (G4_4PL == 0) -#define MG4_6_14PL ~(1 << 3) -#else -#define MG4_6_14PL 0xFFFF -#endif - -#if (G4_5PL >= G4_6PL) || (G4_5PL == 0) -#define MG4_6_15PL ~(1 << 4) -#else -#define MG4_6_15PL 0xFFFF -#endif - -#if (G4_7PL >= G4_6PL) || (G4_7PL == 0) -#define MG4_6_17PL ~(1 << 6) -#else -#define MG4_6_17PL 0xFFFF -#endif - -#if (G4_8PL >= G4_6PL) || (G4_8PL == 0) -#define MG4_6_18PL ~(1 << 7) -#else -#define MG4_6_18PL 0xFFFF -#endif - -#if (G4_9PL >= G4_6PL) || (G4_9PL == 0) -#define MG4_6_19PL ~(1 << 8) -#else -#define MG4_6_19PL 0xFFFF -#endif - -#if (G4_10PL >= G4_6PL) || (G4_10PL == 0) -#define MG4_6_110PL ~(1 << 9) -#else -#define MG4_6_110PL 0xFFFF -#endif - -#if (G4_11PL >= G4_6PL) || (G4_11PL == 0) -#define MG4_6_111PL ~(1 << 10) -#else -#define MG4_6_111PL 0xFFFF -#endif - -#if (G4_12PL >= G4_6PL) || (G4_12PL == 0) -#define MG4_6_112PL ~(1 << 11) -#else -#define MG4_6_112PL 0xFFFF -#endif - -#if (G4_13PL >= G4_6PL) || (G4_13PL == 0) -#define MG4_6_113PL ~(1 << 12) -#else -#define MG4_6_113PL 0xFFFF -#endif - -#if (G4_14PL >= G4_6PL) || (G4_14PL == 0) -#define MG4_6_114PL ~(1 << 13) -#else -#define MG4_6_114PL 0xFFFF -#endif - -#if (G4_15PL >= G4_6PL) || (G4_15PL == 0) -#define MG4_6_115PL ~(1 << 14) -#else -#define MG4_6_115PL 0xFFFF -#endif - -#if (G4_16PL >= G4_6PL) || (G4_16PL == 0) -#define MG4_6_116PL ~(1 << 15) -#else -#define MG4_6_116PL 0xFFFF -#endif - -#define MG4_6_16PL 0xFFDF -#define MG4_6 (MG4_6_11PL & MG4_6_12PL & MG4_6_13PL & MG4_6_14PL & \ - MG4_6_15PL & MG4_6_16PL & MG4_6_17PL & MG4_6_18PL & \ - MG4_6_19PL & MG4_6_110PL & MG4_6_111PL & MG4_6_112PL & \ - MG4_6_113PL & MG4_6_114PL & MG4_6_115PL & MG4_6_116PL) -// End of MG4_6: -// Beginning of MG47: -#if (G4_1PL >= G4_7PL) || (G4_1PL == 0) -#define MG4_7_11PL ~(1 << 0) -#else -#define MG4_7_11PL 0xFFFF -#endif - -#if (G4_2PL >= G4_7PL) || (G4_2PL == 0) -#define MG4_7_12PL ~(1 << 1) -#else -#define MG4_7_12PL 0xFFFF -#endif - -#if (G4_3PL >= G4_7PL) || (G4_3PL == 0) -#define MG4_7_13PL ~(1 << 2) -#else -#define MG4_7_13PL 0xFFFF -#endif - -#if (G4_4PL >= G4_7PL) || (G4_4PL == 0) -#define MG4_7_14PL ~(1 << 3) -#else -#define MG4_7_14PL 0xFFFF -#endif - -#if (G4_5PL >= G4_7PL) || (G4_5PL == 0) -#define MG4_7_15PL ~(1 << 4) -#else -#define MG4_7_15PL 0xFFFF -#endif - -#if (G4_6PL >= G4_7PL) || (G4_6PL == 0) -#define MG4_7_16PL ~(1 << 5) -#else -#define MG4_7_16PL 0xFFFF -#endif - -#if (G4_8PL >= G4_7PL) || (G4_8PL == 0) -#define MG4_7_18PL ~(1 << 7) -#else -#define MG4_7_18PL 0xFFFF -#endif - -#if (G4_9PL >= G4_7PL) || (G4_9PL == 0) -#define MG4_7_19PL ~(1 << 8) -#else -#define MG4_7_19PL 0xFFFF -#endif - -#if (G4_10PL >= G4_7PL) || (G4_10PL == 0) -#define MG4_7_110PL ~(1 << 9) -#else -#define MG4_7_110PL 0xFFFF -#endif - -#if (G4_11PL >= G4_7PL) || (G4_11PL == 0) -#define MG4_7_111PL ~(1 << 10) -#else -#define MG4_7_111PL 0xFFFF -#endif - -#if (G4_12PL >= G4_7PL) || (G4_12PL == 0) -#define MG4_7_112PL ~(1 << 11) -#else -#define MG4_7_112PL 0xFFFF -#endif - -#if (G4_13PL >= G4_7PL) || (G4_13PL == 0) -#define MG4_7_113PL ~(1 << 12) -#else -#define MG4_7_113PL 0xFFFF -#endif - -#if (G4_14PL >= G4_7PL) || (G4_14PL == 0) -#define MG4_7_114PL ~(1 << 13) -#else -#define MG4_7_114PL 0xFFFF -#endif - -#if (G4_15PL >= G4_7PL) || (G4_15PL == 0) -#define MG4_7_115PL ~(1 << 14) -#else -#define MG4_7_115PL 0xFFFF -#endif - -#if (G4_16PL >= G4_7PL) || (G4_16PL == 0) -#define MG4_7_116PL ~(1 << 15) -#else -#define MG4_7_116PL 0xFFFF -#endif - -#define MG4_7_17PL 0xFFBF -#define MG4_7 (MG4_7_11PL & MG4_7_12PL & MG4_7_13PL & MG4_7_14PL & \ - MG4_7_15PL & MG4_7_16PL & MG4_7_17PL & MG4_7_18PL & \ - MG4_7_19PL & MG4_7_110PL & MG4_7_111PL & MG4_7_112PL & \ - MG4_7_113PL & MG4_7_114PL & MG4_7_115PL & MG4_7_116PL) -// End of MG4_7: -// Beginning of MG48: -#if (G4_1PL >= G4_8PL) || (G4_1PL == 0) -#define MG4_8_11PL ~(1 << 0) -#else -#define MG4_8_11PL 0xFFFF -#endif - -#if (G4_2PL >= G4_8PL) || (G4_2PL == 0) -#define MG4_8_12PL ~(1 << 1) -#else -#define MG4_8_12PL 0xFFFF -#endif - -#if (G4_3PL >= G4_8PL) || (G4_3PL == 0) -#define MG4_8_13PL ~(1 << 2) -#else -#define MG4_8_13PL 0xFFFF -#endif - -#if (G4_4PL >= G4_8PL) || (G4_4PL == 0) -#define MG4_8_14PL ~(1 << 3) -#else -#define MG4_8_14PL 0xFFFF -#endif - -#if (G4_5PL >= G4_8PL) || (G4_5PL == 0) -#define MG4_8_15PL ~(1 << 4) -#else -#define MG4_8_15PL 0xFFFF -#endif - -#if (G4_6PL >= G4_8PL) || (G4_6PL == 0) -#define MG4_8_16PL ~(1 << 5) -#else -#define MG4_8_16PL 0xFFFF -#endif - -#if (G4_7PL >= G4_8PL) || (G4_7PL == 0) -#define MG4_8_17PL ~(1 << 6) -#else -#define MG4_8_17PL 0xFFFF -#endif - -#if (G4_9PL >= G4_8PL) || (G4_9PL == 0) -#define MG4_8_19PL ~(1 << 8) -#else -#define MG4_8_19PL 0xFFFF -#endif - -#if (G4_10PL >= G4_8PL) || (G4_10PL == 0) -#define MG4_8_110PL ~(1 << 9) -#else -#define MG4_8_110PL 0xFFFF -#endif - -#if (G4_11PL >= G4_8PL) || (G4_11PL == 0) -#define MG4_8_111PL ~(1 << 10) -#else -#define MG4_8_111PL 0xFFFF -#endif - -#if (G4_12PL >= G4_8PL) || (G4_12PL == 0) -#define MG4_8_112PL ~(1 << 11) -#else -#define MG4_8_112PL 0xFFFF -#endif - -#if (G4_13PL >= G4_8PL) || (G4_13PL == 0) -#define MG4_8_113PL ~(1 << 12) -#else -#define MG4_8_113PL 0xFFFF -#endif - -#if (G4_14PL >= G4_8PL) || (G4_14PL == 0) -#define MG4_8_114PL ~(1 << 13) -#else -#define MG4_8_114PL 0xFFFF -#endif - -#if (G4_15PL >= G4_8PL) || (G4_15PL == 0) -#define MG4_8_115PL ~(1 << 14) -#else -#define MG4_8_115PL 0xFFFF -#endif - -#if (G4_16PL >= G4_8PL) || (G4_16PL == 0) -#define MG4_8_116PL ~(1 << 15) -#else -#define MG4_8_116PL 0xFFFF -#endif - -#define MG4_8_18PL 0xFF7F -#define MG4_8 (MG4_8_11PL & MG4_8_12PL & MG4_8_13PL & MG4_8_14PL & \ - MG4_8_15PL & MG4_8_16PL & MG4_8_17PL & MG4_8_18PL & \ - MG4_8_19PL & MG4_8_110PL & MG4_8_111PL & MG4_8_112PL & \ - MG4_8_113PL & MG4_8_114PL & MG4_8_115PL & MG4_8_116PL) -// End of MG4_8: -// Beginning of MG49: -#if (G4_1PL >= G4_9PL) || (G4_1PL == 0) -#define MG4_9_11PL ~(1 << 0) -#else -#define MG4_9_11PL 0xFFFF -#endif - -#if (G4_2PL >= G4_9PL) || (G4_2PL == 0) -#define MG4_9_12PL ~(1 << 1) -#else -#define MG4_9_12PL 0xFFFF -#endif - -#if (G4_3PL >= G4_9PL) || (G4_3PL == 0) -#define MG4_9_13PL ~(1 << 2) -#else -#define MG4_9_13PL 0xFFFF -#endif - -#if (G4_4PL >= G4_9PL) || (G4_4PL == 0) -#define MG4_9_14PL ~(1 << 3) -#else -#define MG4_9_14PL 0xFFFF -#endif - -#if (G4_5PL >= G4_9PL) || (G4_5PL == 0) -#define MG4_9_15PL ~(1 << 4) -#else -#define MG4_9_15PL 0xFFFF -#endif - -#if (G4_6PL >= G4_9PL) || (G4_6PL == 0) -#define MG4_9_16PL ~(1 << 5) -#else -#define MG4_9_16PL 0xFFFF -#endif - -#if (G4_7PL >= G4_9PL) || (G4_7PL == 0) -#define MG4_9_17PL ~(1 << 6) -#else -#define MG4_9_17PL 0xFFFF -#endif - -#if (G4_8PL >= G4_9PL) || (G4_8PL == 0) -#define MG4_9_18PL ~(1 << 7) -#else -#define MG4_9_18PL 0xFFFF -#endif - -#if (G4_10PL >= G4_9PL) || (G4_10PL == 0) -#define MG4_9_110PL ~(1 << 9) -#else -#define MG4_9_110PL 0xFFFF -#endif - -#if (G4_11PL >= G4_9PL) || (G4_11PL == 0) -#define MG4_9_111PL ~(1 << 10) -#else -#define MG4_9_111PL 0xFFFF -#endif - -#if (G4_12PL >= G4_9PL) || (G4_12PL == 0) -#define MG4_9_112PL ~(1 << 11) -#else -#define MG4_9_112PL 0xFFFF -#endif - -#if (G4_13PL >= G4_9PL) || (G4_13PL == 0) -#define MG4_9_113PL ~(1 << 12) -#else -#define MG4_9_113PL 0xFFFF -#endif - -#if (G4_14PL >= G4_9PL) || (G4_14PL == 0) -#define MG4_9_114PL ~(1 << 13) -#else -#define MG4_9_114PL 0xFFFF -#endif - -#if (G4_15PL >= G4_9PL) || (G4_15PL == 0) -#define MG4_9_115PL ~(1 << 14) -#else -#define MG4_9_115PL 0xFFFF -#endif - -#if (G4_16PL >= G4_9PL) || (G4_16PL == 0) -#define MG4_9_116PL ~(1 << 15) -#else -#define MG4_9_116PL 0xFFFF -#endif - -#define MG4_9_19PL 0xFEFF -#define MG4_9 (MG4_9_11PL & MG4_9_12PL & MG4_9_13PL & MG4_9_14PL & \ - MG4_9_15PL & MG4_9_16PL & MG4_9_17PL & MG4_9_18PL & \ - MG4_9_19PL & MG4_9_110PL & MG4_9_111PL & MG4_9_112PL & \ - MG4_9_113PL & MG4_9_114PL & MG4_9_115PL & MG4_9_116PL) -// End of MG4_9: -// Beginning of MG410: -#if (G4_1PL >= G4_10PL) || (G4_1PL == 0) -#define MG4_10_11PL ~(1 << 0) -#else -#define MG4_10_11PL 0xFFFF -#endif - -#if (G4_2PL >= G4_10PL) || (G4_2PL == 0) -#define MG4_10_12PL ~(1 << 1) -#else -#define MG4_10_12PL 0xFFFF -#endif - -#if (G4_3PL >= G4_10PL) || (G4_3PL == 0) -#define MG4_10_13PL ~(1 << 2) -#else -#define MG4_10_13PL 0xFFFF -#endif - -#if (G4_4PL >= G4_10PL) || (G4_4PL == 0) -#define MG4_10_14PL ~(1 << 3) -#else -#define MG4_10_14PL 0xFFFF -#endif - -#if (G4_5PL >= G4_10PL) || (G4_5PL == 0) -#define MG4_10_15PL ~(1 << 4) -#else -#define MG4_10_15PL 0xFFFF -#endif - -#if (G4_6PL >= G4_10PL) || (G4_6PL == 0) -#define MG4_10_16PL ~(1 << 5) -#else -#define MG4_10_16PL 0xFFFF -#endif - -#if (G4_7PL >= G4_10PL) || (G4_7PL == 0) -#define MG4_10_17PL ~(1 << 6) -#else -#define MG4_10_17PL 0xFFFF -#endif - -#if (G4_8PL >= G4_10PL) || (G4_8PL == 0) -#define MG4_10_18PL ~(1 << 7) -#else -#define MG4_10_18PL 0xFFFF -#endif - -#if (G4_9PL >= G4_10PL) || (G4_9PL == 0) -#define MG4_10_19PL ~(1 << 8) -#else -#define MG4_10_19PL 0xFFFF -#endif - -#if (G4_11PL >= G4_10PL) || (G4_11PL == 0) -#define MG4_10_111PL ~(1 << 10) -#else -#define MG4_10_111PL 0xFFFF -#endif - -#if (G4_12PL >= G4_10PL) || (G4_12PL == 0) -#define MG4_10_112PL ~(1 << 11) -#else -#define MG4_10_112PL 0xFFFF -#endif - -#if (G4_13PL >= G4_10PL) || (G4_13PL == 0) -#define MG4_10_113PL ~(1 << 12) -#else -#define MG4_10_113PL 0xFFFF -#endif - -#if (G4_14PL >= G4_10PL) || (G4_14PL == 0) -#define MG4_10_114PL ~(1 << 13) -#else -#define MG4_10_114PL 0xFFFF -#endif - -#if (G4_15PL >= G4_10PL) || (G4_15PL == 0) -#define MG4_10_115PL ~(1 << 14) -#else -#define MG4_10_115PL 0xFFFF -#endif - -#if (G4_16PL >= G4_10PL) || (G4_16PL == 0) -#define MG4_10_116PL ~(1 << 15) -#else -#define MG4_10_116PL 0xFFFF -#endif - -#define MG4_10_110PL 0xFDFF -#define MG4_10 (MG4_10_11PL & MG4_10_12PL & MG4_10_13PL & MG4_10_14PL & \ - MG4_10_15PL & MG4_10_16PL & MG4_10_17PL & MG4_10_18PL & \ - MG4_10_19PL & MG4_10_110PL & MG4_10_111PL & MG4_10_112PL & \ - MG4_10_113PL & MG4_10_114PL & MG4_10_115PL & MG4_10_116PL) -// End of MG4_10: -// Beginning of MG411: -#if (G4_1PL >= G4_11PL) || (G4_1PL == 0) -#define MG4_11_11PL ~(1 << 0) -#else -#define MG4_11_11PL 0xFFFF -#endif - -#if (G4_2PL >= G4_11PL) || (G4_2PL == 0) -#define MG4_11_12PL ~(1 << 1) -#else -#define MG4_11_12PL 0xFFFF -#endif - -#if (G4_3PL >= G4_11PL) || (G4_3PL == 0) -#define MG4_11_13PL ~(1 << 2) -#else -#define MG4_11_13PL 0xFFFF -#endif - -#if (G4_4PL >= G4_11PL) || (G4_4PL == 0) -#define MG4_11_14PL ~(1 << 3) -#else -#define MG4_11_14PL 0xFFFF -#endif - -#if (G4_5PL >= G4_11PL) || (G4_5PL == 0) -#define MG4_11_15PL ~(1 << 4) -#else -#define MG4_11_15PL 0xFFFF -#endif - -#if (G4_6PL >= G4_11PL) || (G4_6PL == 0) -#define MG4_11_16PL ~(1 << 5) -#else -#define MG4_11_16PL 0xFFFF -#endif - -#if (G4_7PL >= G4_11PL) || (G4_7PL == 0) -#define MG4_11_17PL ~(1 << 6) -#else -#define MG4_11_17PL 0xFFFF -#endif - -#if (G4_8PL >= G4_11PL) || (G4_8PL == 0) -#define MG4_11_18PL ~(1 << 7) -#else -#define MG4_11_18PL 0xFFFF -#endif - -#if (G4_9PL >= G4_11PL) || (G4_9PL == 0) -#define MG4_11_19PL ~(1 << 8) -#else -#define MG4_11_19PL 0xFFFF -#endif - -#if (G4_10PL >= G4_11PL) || (G4_10PL == 0) -#define MG4_11_110PL ~(1 << 9) -#else -#define MG4_11_110PL 0xFFFF -#endif - -#if (G4_12PL >= G4_11PL) || (G4_12PL == 0) -#define MG4_11_112PL ~(1 << 11) -#else -#define MG4_11_112PL 0xFFFF -#endif - -#if (G4_13PL >= G4_11PL) || (G4_13PL == 0) -#define MG4_11_113PL ~(1 << 12) -#else -#define MG4_11_113PL 0xFFFF -#endif - -#if (G4_14PL >= G4_11PL) || (G4_14PL == 0) -#define MG4_11_114PL ~(1 << 13) -#else -#define MG4_11_114PL 0xFFFF -#endif - -#if (G4_15PL >= G4_11PL) || (G4_15PL == 0) -#define MG4_11_115PL ~(1 << 14) -#else -#define MG4_11_115PL 0xFFFF -#endif - -#if (G4_16PL >= G4_11PL) || (G4_16PL == 0) -#define MG4_11_116PL ~(1 << 15) -#else -#define MG4_11_116PL 0xFFFF -#endif - -#define MG4_11_111PL 0xFBFF -#define MG4_11 (MG4_11_11PL & MG4_11_12PL & MG4_11_13PL & MG4_11_14PL & \ - MG4_11_15PL & MG4_11_16PL & MG4_11_17PL & MG4_11_18PL & \ - MG4_11_19PL & MG4_11_110PL & MG4_11_111PL & MG4_11_112PL & \ - MG4_11_113PL & MG4_11_114PL & MG4_11_115PL & MG4_11_116PL) -// End of MG4_11: -// Beginning of MG412: -#if (G4_1PL >= G4_12PL) || (G4_1PL == 0) -#define MG4_12_11PL ~(1 << 0) -#else -#define MG4_12_11PL 0xFFFF -#endif - -#if (G4_2PL >= G4_12PL) || (G4_2PL == 0) -#define MG4_12_12PL ~(1 << 1) -#else -#define MG4_12_12PL 0xFFFF -#endif - -#if (G4_3PL >= G4_12PL) || (G4_3PL == 0) -#define MG4_12_13PL ~(1 << 2) -#else -#define MG4_12_13PL 0xFFFF -#endif - -#if (G4_4PL >= G4_12PL) || (G4_4PL == 0) -#define MG4_12_14PL ~(1 << 3) -#else -#define MG4_12_14PL 0xFFFF -#endif - -#if (G4_5PL >= G4_12PL) || (G4_5PL == 0) -#define MG4_12_15PL ~(1 << 4) -#else -#define MG4_12_15PL 0xFFFF -#endif - -#if (G4_6PL >= G4_12PL) || (G4_6PL == 0) -#define MG4_12_16PL ~(1 << 5) -#else -#define MG4_12_16PL 0xFFFF -#endif - -#if (G4_7PL >= G4_12PL) || (G4_7PL == 0) -#define MG4_12_17PL ~(1 << 6) -#else -#define MG4_12_17PL 0xFFFF -#endif - -#if (G4_8PL >= G4_12PL) || (G4_8PL == 0) -#define MG4_12_18PL ~(1 << 7) -#else -#define MG4_12_18PL 0xFFFF -#endif - -#if (G4_9PL >= G4_12PL) || (G4_9PL == 0) -#define MG4_12_19PL ~(1 << 8) -#else -#define MG4_12_19PL 0xFFFF -#endif - -#if (G4_10PL >= G4_12PL) || (G4_10PL == 0) -#define MG4_12_110PL ~(1 << 9) -#else -#define MG4_12_110PL 0xFFFF -#endif - -#if (G4_11PL >= G4_12PL) || (G4_11PL == 0) -#define MG4_12_111PL ~(1 << 10) -#else -#define MG4_12_111PL 0xFFFF -#endif - -#if (G4_13PL >= G4_12PL) || (G4_13PL == 0) -#define MG4_12_113PL ~(1 << 12) -#else -#define MG4_12_113PL 0xFFFF -#endif - -#if (G4_14PL >= G4_12PL) || (G4_14PL == 0) -#define MG4_12_114PL ~(1 << 13) -#else -#define MG4_12_114PL 0xFFFF -#endif - -#if (G4_15PL >= G4_12PL) || (G4_15PL == 0) -#define MG4_12_115PL ~(1 << 14) -#else -#define MG4_12_115PL 0xFFFF -#endif - -#if (G4_16PL >= G4_12PL) || (G4_16PL == 0) -#define MG4_12_116PL ~(1 << 15) -#else -#define MG4_12_116PL 0xFFFF -#endif - -#define MG4_12_112PL 0xF7FF -#define MG4_12 (MG4_12_11PL & MG4_12_12PL & MG4_12_13PL & MG4_12_14PL & \ - MG4_12_15PL & MG4_12_16PL & MG4_12_17PL & MG4_12_18PL & \ - MG4_12_19PL & MG4_12_110PL & MG4_12_111PL & MG4_12_112PL & \ - MG4_12_113PL & MG4_12_114PL & MG4_12_115PL & MG4_12_116PL) -// End of MG4_12: -// Beginning of MG413: -#if (G4_1PL >= G4_13PL) || (G4_1PL == 0) -#define MG4_13_11PL ~(1 << 0) -#else -#define MG4_13_11PL 0xFFFF -#endif - -#if (G4_2PL >= G4_13PL) || (G4_2PL == 0) -#define MG4_13_12PL ~(1 << 1) -#else -#define MG4_13_12PL 0xFFFF -#endif - -#if (G4_3PL >= G4_13PL) || (G4_3PL == 0) -#define MG4_13_13PL ~(1 << 2) -#else -#define MG4_13_13PL 0xFFFF -#endif - -#if (G4_4PL >= G4_13PL) || (G4_4PL == 0) -#define MG4_13_14PL ~(1 << 3) -#else -#define MG4_13_14PL 0xFFFF -#endif - -#if (G4_5PL >= G4_13PL) || (G4_5PL == 0) -#define MG4_13_15PL ~(1 << 4) -#else -#define MG4_13_15PL 0xFFFF -#endif - -#if (G4_6PL >= G4_13PL) || (G4_6PL == 0) -#define MG4_13_16PL ~(1 << 5) -#else -#define MG4_13_16PL 0xFFFF -#endif - -#if (G4_7PL >= G4_13PL) || (G4_7PL == 0) -#define MG4_13_17PL ~(1 << 6) -#else -#define MG4_13_17PL 0xFFFF -#endif - -#if (G4_8PL >= G4_13PL) || (G4_8PL == 0) -#define MG4_13_18PL ~(1 << 7) -#else -#define MG4_13_18PL 0xFFFF -#endif - -#if (G4_9PL >= G4_13PL) || (G4_9PL == 0) -#define MG4_13_19PL ~(1 << 8) -#else -#define MG4_13_19PL 0xFFFF -#endif - -#if (G4_10PL >= G4_13PL) || (G4_10PL == 0) -#define MG4_13_110PL ~(1 << 9) -#else -#define MG4_13_110PL 0xFFFF -#endif - -#if (G4_11PL >= G4_13PL) || (G4_11PL == 0) -#define MG4_13_111PL ~(1 << 10) -#else -#define MG4_13_111PL 0xFFFF -#endif - -#if (G4_12PL >= G4_13PL) || (G4_12PL == 0) -#define MG4_13_112PL ~(1 << 11) -#else -#define MG4_13_112PL 0xFFFF -#endif - -#if (G4_14PL >= G4_13PL) || (G4_14PL == 0) -#define MG4_13_114PL ~(1 << 13) -#else -#define MG4_13_114PL 0xFFFF -#endif - -#if (G4_15PL >= G4_13PL) || (G4_15PL == 0) -#define MG4_13_115PL ~(1 << 14) -#else -#define MG4_13_115PL 0xFFFF -#endif - -#if (G4_16PL >= G4_13PL) || (G4_16PL == 0) -#define MG4_13_116PL ~(1 << 15) -#else -#define MG4_13_116PL 0xFFFF -#endif - -#define MG4_13_113PL 0xEFFF -#define MG4_13 (MG4_13_11PL & MG4_13_12PL & MG4_13_13PL & MG4_13_14PL & \ - MG4_13_15PL & MG4_13_16PL & MG4_13_17PL & MG4_13_18PL & \ - MG4_13_19PL & MG4_13_110PL & MG4_13_111PL & MG4_13_112PL & \ - MG4_13_113PL & MG4_13_114PL & MG4_13_115PL & MG4_13_116PL) -// End of MG4_13: -// Beginning of MG414: -#if (G4_1PL >= G4_14PL) || (G4_1PL == 0) -#define MG4_14_11PL ~(1 << 0) -#else -#define MG4_14_11PL 0xFFFF -#endif - -#if (G4_2PL >= G4_14PL) || (G4_2PL == 0) -#define MG4_14_12PL ~(1 << 1) -#else -#define MG4_14_12PL 0xFFFF -#endif - -#if (G4_3PL >= G4_14PL) || (G4_3PL == 0) -#define MG4_14_13PL ~(1 << 2) -#else -#define MG4_14_13PL 0xFFFF -#endif - -#if (G4_4PL >= G4_14PL) || (G4_4PL == 0) -#define MG4_14_14PL ~(1 << 3) -#else -#define MG4_14_14PL 0xFFFF -#endif - -#if (G4_5PL >= G4_14PL) || (G4_5PL == 0) -#define MG4_14_15PL ~(1 << 4) -#else -#define MG4_14_15PL 0xFFFF -#endif - -#if (G4_6PL >= G4_14PL) || (G4_6PL == 0) -#define MG4_14_16PL ~(1 << 5) -#else -#define MG4_14_16PL 0xFFFF -#endif - -#if (G4_7PL >= G4_14PL) || (G4_7PL == 0) -#define MG4_14_17PL ~(1 << 6) -#else -#define MG4_14_17PL 0xFFFF -#endif - -#if (G4_8PL >= G4_14PL) || (G4_8PL == 0) -#define MG4_14_18PL ~(1 << 7) -#else -#define MG4_14_18PL 0xFFFF -#endif - -#if (G4_9PL >= G4_14PL) || (G4_9PL == 0) -#define MG4_14_19PL ~(1 << 8) -#else -#define MG4_14_19PL 0xFFFF -#endif - -#if (G4_10PL >= G4_14PL) || (G4_10PL == 0) -#define MG4_14_110PL ~(1 << 9) -#else -#define MG4_14_110PL 0xFFFF -#endif - -#if (G4_11PL >= G4_14PL) || (G4_11PL == 0) -#define MG4_14_111PL ~(1 << 10) -#else -#define MG4_14_111PL 0xFFFF -#endif - -#if (G4_12PL >= G4_14PL) || (G4_12PL == 0) -#define MG4_14_112PL ~(1 << 11) -#else -#define MG4_14_112PL 0xFFFF -#endif - -#if (G4_13PL >= G4_14PL) || (G4_13PL == 0) -#define MG4_14_113PL ~(1 << 12) -#else -#define MG4_14_113PL 0xFFFF -#endif - -#if (G4_15PL >= G4_14PL) || (G4_15PL == 0) -#define MG4_14_115PL ~(1 << 14) -#else -#define MG4_14_115PL 0xFFFF -#endif - -#if (G4_16PL >= G4_14PL) || (G4_16PL == 0) -#define MG4_14_116PL ~(1 << 15) -#else -#define MG4_14_116PL 0xFFFF -#endif - -#define MG4_14_114PL 0xDFFF -#define MG4_14 (MG4_14_11PL & MG4_14_12PL & MG4_14_13PL & MG4_14_14PL & \ - MG4_14_15PL & MG4_14_16PL & MG4_14_17PL & MG4_14_18PL & \ - MG4_14_19PL & MG4_14_110PL & MG4_14_111PL & MG4_14_112PL & \ - MG4_14_113PL & MG4_14_114PL & MG4_14_115PL & MG4_14_116PL) -// End of MG4_14: -// Beginning of MG415: -#if (G4_1PL >= G4_15PL) || (G4_1PL == 0) -#define MG4_15_11PL ~(1 << 0) -#else -#define MG4_15_11PL 0xFFFF -#endif - -#if (G4_2PL >= G4_15PL) || (G4_2PL == 0) -#define MG4_15_12PL ~(1 << 1) -#else -#define MG4_15_12PL 0xFFFF -#endif - -#if (G4_3PL >= G4_15PL) || (G4_3PL == 0) -#define MG4_15_13PL ~(1 << 2) -#else -#define MG4_15_13PL 0xFFFF -#endif - -#if (G4_4PL >= G4_15PL) || (G4_4PL == 0) -#define MG4_15_14PL ~(1 << 3) -#else -#define MG4_15_14PL 0xFFFF -#endif - -#if (G4_5PL >= G4_15PL) || (G4_5PL == 0) -#define MG4_15_15PL ~(1 << 4) -#else -#define MG4_15_15PL 0xFFFF -#endif - -#if (G4_6PL >= G4_15PL) || (G4_6PL == 0) -#define MG4_15_16PL ~(1 << 5) -#else -#define MG4_15_16PL 0xFFFF -#endif - -#if (G4_7PL >= G4_15PL) || (G4_7PL == 0) -#define MG4_15_17PL ~(1 << 6) -#else -#define MG4_15_17PL 0xFFFF -#endif - -#if (G4_8PL >= G4_15PL) || (G4_8PL == 0) -#define MG4_15_18PL ~(1 << 7) -#else -#define MG4_15_18PL 0xFFFF -#endif - -#if (G4_9PL >= G4_15PL) || (G4_9PL == 0) -#define MG4_15_19PL ~(1 << 8) -#else -#define MG4_15_19PL 0xFFFF -#endif - -#if (G4_10PL >= G4_15PL) || (G4_10PL == 0) -#define MG4_15_110PL ~(1 << 9) -#else -#define MG4_15_110PL 0xFFFF -#endif - -#if (G4_11PL >= G4_15PL) || (G4_11PL == 0) -#define MG4_15_111PL ~(1 << 10) -#else -#define MG4_15_111PL 0xFFFF -#endif - -#if (G4_12PL >= G4_15PL) || (G4_12PL == 0) -#define MG4_15_112PL ~(1 << 11) -#else -#define MG4_15_112PL 0xFFFF -#endif - -#if (G4_13PL >= G4_15PL) || (G4_13PL == 0) -#define MG4_15_113PL ~(1 << 12) -#else -#define MG4_15_113PL 0xFFFF -#endif - -#if (G4_14PL >= G4_15PL) || (G4_14PL == 0) -#define MG4_15_114PL ~(1 << 13) -#else -#define MG4_15_114PL 0xFFFF -#endif - -#if (G4_16PL >= G4_15PL) || (G4_16PL == 0) -#define MG4_15_116PL ~(1 << 15) -#else -#define MG4_15_116PL 0xFFFF -#endif - -#define MG4_15_115PL 0xBFFF -#define MG4_15 (MG4_15_11PL & MG4_15_12PL & MG4_15_13PL & MG4_15_14PL & \ - MG4_15_15PL & MG4_15_16PL & MG4_15_17PL & MG4_15_18PL & \ - MG4_15_19PL & MG4_15_110PL & MG4_15_111PL & MG4_15_112PL & \ - MG4_15_113PL & MG4_15_114PL & MG4_15_115PL & MG4_15_116PL) -// End of MG4_15: -// Beginning of MG416: -#if (G4_1PL >= G4_16PL) || (G4_1PL == 0) -#define MG4_16_11PL ~(1 << 0) -#else -#define MG4_16_11PL 0xFFFF -#endif - -#if (G4_2PL >= G4_16PL) || (G4_2PL == 0) -#define MG4_16_12PL ~(1 << 1) -#else -#define MG4_16_12PL 0xFFFF -#endif - -#if (G4_3PL >= G4_16PL) || (G4_3PL == 0) -#define MG4_16_13PL ~(1 << 2) -#else -#define MG4_16_13PL 0xFFFF -#endif - -#if (G4_4PL >= G4_16PL) || (G4_4PL == 0) -#define MG4_16_14PL ~(1 << 3) -#else -#define MG4_16_14PL 0xFFFF -#endif - -#if (G4_5PL >= G4_16PL) || (G4_5PL == 0) -#define MG4_16_15PL ~(1 << 4) -#else -#define MG4_16_15PL 0xFFFF -#endif - -#if (G4_6PL >= G4_16PL) || (G4_6PL == 0) -#define MG4_16_16PL ~(1 << 5) -#else -#define MG4_16_16PL 0xFFFF -#endif - -#if (G4_7PL >= G4_16PL) || (G4_7PL == 0) -#define MG4_16_17PL ~(1 << 6) -#else -#define MG4_16_17PL 0xFFFF -#endif - -#if (G4_8PL >= G4_16PL) || (G4_8PL == 0) -#define MG4_16_18PL ~(1 << 7) -#else -#define MG4_16_18PL 0xFFFF -#endif - -#if (G4_9PL >= G4_16PL) || (G4_9PL == 0) -#define MG4_16_19PL ~(1 << 8) -#else -#define MG4_16_19PL 0xFFFF -#endif - -#if (G4_10PL >= G4_16PL) || (G4_10PL == 0) -#define MG4_16_110PL ~(1 << 9) -#else -#define MG4_16_110PL 0xFFFF -#endif - -#if (G4_11PL >= G4_16PL) || (G4_11PL == 0) -#define MG4_16_111PL ~(1 << 10) -#else -#define MG4_16_111PL 0xFFFF -#endif - -#if (G4_12PL >= G4_16PL) || (G4_12PL == 0) -#define MG4_16_112PL ~(1 << 11) -#else -#define MG4_16_112PL 0xFFFF -#endif - -#if (G4_13PL >= G4_16PL) || (G4_13PL == 0) -#define MG4_16_113PL ~(1 << 12) -#else -#define MG4_16_113PL 0xFFFF -#endif - -#if (G4_14PL >= G4_16PL) || (G4_14PL == 0) -#define MG4_16_114PL ~(1 << 13) -#else -#define MG4_16_114PL 0xFFFF -#endif - -#if (G4_15PL >= G4_16PL) || (G4_15PL == 0) -#define MG4_16_115PL ~(1 << 14) -#else -#define MG4_16_115PL 0xFFFF -#endif - -#define MG4_16_116PL 0x7FFF -#define MG4_16 (MG4_16_11PL & MG4_16_12PL & MG4_16_13PL & MG4_16_14PL & \ - MG4_16_15PL & MG4_16_16PL & MG4_16_17PL & MG4_16_18PL & \ - MG4_16_19PL & MG4_16_110PL & MG4_16_111PL & MG4_16_112PL & \ - MG4_16_113PL & MG4_16_114PL & MG4_16_115PL & MG4_16_116PL) -// End of MG4_16: - - -// -// Automatically generate PIEIER5 interrupt masks MG51 to MG516: -// - -// Beginning of MG51: -#if (G5_2PL >= G5_1PL) || (G5_2PL == 0) -#define MG5_1_12PL ~(1 << 1) -#else -#define MG5_1_12PL 0xFFFF -#endif - -#if (G5_3PL >= G5_1PL) || (G5_3PL == 0) -#define MG5_1_13PL ~(1 << 2) -#else -#define MG5_1_13PL 0xFFFF -#endif - -#if (G5_4PL >= G5_1PL) || (G5_4PL == 0) -#define MG5_1_14PL ~(1 << 3) -#else -#define MG5_1_14PL 0xFFFF -#endif - -#if (G5_5PL >= G5_1PL) || (G5_5PL == 0) -#define MG5_1_15PL ~(1 << 4) -#else -#define MG5_1_15PL 0xFFFF -#endif - -#if (G5_6PL >= G5_1PL) || (G5_6PL == 0) -#define MG5_1_16PL ~(1 << 5) -#else -#define MG5_1_16PL 0xFFFF -#endif - -#if (G5_7PL >= G5_1PL) || (G5_7PL == 0) -#define MG5_1_17PL ~(1 << 6) -#else -#define MG5_1_17PL 0xFFFF -#endif - -#if (G5_8PL >= G5_1PL) || (G5_8PL == 0) -#define MG5_1_18PL ~(1 << 7) -#else -#define MG5_1_18PL 0xFFFF -#endif - -#if (G5_9PL >= G5_1PL) || (G5_9PL == 0) -#define MG5_1_19PL ~(1 << 8) -#else -#define MG5_1_19PL 0xFFFF -#endif - -#if (G5_10PL >= G5_1PL) || (G5_10PL == 0) -#define MG5_1_110PL ~(1 << 9) -#else -#define MG5_1_110PL 0xFFFF -#endif - -#if (G5_11PL >= G5_1PL) || (G5_11PL == 0) -#define MG5_1_111PL ~(1 << 10) -#else -#define MG5_1_111PL 0xFFFF -#endif - -#if (G5_12PL >= G5_1PL) || (G5_12PL == 0) -#define MG5_1_112PL ~(1 << 11) -#else -#define MG5_1_112PL 0xFFFF -#endif - -#if (G5_13PL >= G5_1PL) || (G5_13PL == 0) -#define MG5_1_113PL ~(1 << 12) -#else -#define MG5_1_113PL 0xFFFF -#endif - -#if (G5_14PL >= G5_1PL) || (G5_14PL == 0) -#define MG5_1_114PL ~(1 << 13) -#else -#define MG5_1_114PL 0xFFFF -#endif - -#if (G5_15PL >= G5_1PL) || (G5_15PL == 0) -#define MG5_1_115PL ~(1 << 14) -#else -#define MG5_1_115PL 0xFFFF -#endif - -#if (G5_16PL >= G5_1PL) || (G5_16PL == 0) -#define MG5_1_116PL ~(1 << 15) -#else -#define MG5_1_116PL 0xFFFF -#endif - -#define MG5_1_11PL 0xFFFE -#define MG5_1 (MG5_1_11PL & MG5_1_12PL & MG5_1_13PL & MG5_1_14PL & \ - MG5_1_15PL & MG5_1_16PL & MG5_1_17PL & MG5_1_18PL & \ - MG5_1_19PL & MG5_1_110PL & MG5_1_111PL & MG5_1_112PL & \ - MG5_1_113PL & MG5_1_114PL & MG5_1_115PL & MG5_1_116PL) -// End of MG5_1: -// Beginning of MG52: -#if (G5_1PL >= G5_2PL) || (G5_1PL == 0) -#define MG5_2_11PL ~(1 << 0) -#else -#define MG5_2_11PL 0xFFFF -#endif - -#if (G5_3PL >= G5_2PL) || (G5_3PL == 0) -#define MG5_2_13PL ~(1 << 2) -#else -#define MG5_2_13PL 0xFFFF -#endif - -#if (G5_4PL >= G5_2PL) || (G5_4PL == 0) -#define MG5_2_14PL ~(1 << 3) -#else -#define MG5_2_14PL 0xFFFF -#endif - -#if (G5_5PL >= G5_2PL) || (G5_5PL == 0) -#define MG5_2_15PL ~(1 << 4) -#else -#define MG5_2_15PL 0xFFFF -#endif - -#if (G5_6PL >= G5_2PL) || (G5_6PL == 0) -#define MG5_2_16PL ~(1 << 5) -#else -#define MG5_2_16PL 0xFFFF -#endif - -#if (G5_7PL >= G5_2PL) || (G5_7PL == 0) -#define MG5_2_17PL ~(1 << 6) -#else -#define MG5_2_17PL 0xFFFF -#endif - -#if (G5_8PL >= G5_2PL) || (G5_8PL == 0) -#define MG5_2_18PL ~(1 << 7) -#else -#define MG5_2_18PL 0xFFFF -#endif - -#if (G5_9PL >= G5_2PL) || (G5_9PL == 0) -#define MG5_2_19PL ~(1 << 8) -#else -#define MG5_2_19PL 0xFFFF -#endif - -#if (G5_10PL >= G5_2PL) || (G5_10PL == 0) -#define MG5_2_110PL ~(1 << 9) -#else -#define MG5_2_110PL 0xFFFF -#endif - -#if (G5_11PL >= G5_2PL) || (G5_11PL == 0) -#define MG5_2_111PL ~(1 << 10) -#else -#define MG5_2_111PL 0xFFFF -#endif - -#if (G5_12PL >= G5_2PL) || (G5_12PL == 0) -#define MG5_2_112PL ~(1 << 11) -#else -#define MG5_2_112PL 0xFFFF -#endif - -#if (G5_13PL >= G5_2PL) || (G5_13PL == 0) -#define MG5_2_113PL ~(1 << 12) -#else -#define MG5_2_113PL 0xFFFF -#endif - -#if (G5_14PL >= G5_2PL) || (G5_14PL == 0) -#define MG5_2_114PL ~(1 << 13) -#else -#define MG5_2_114PL 0xFFFF -#endif - -#if (G5_15PL >= G5_2PL) || (G5_15PL == 0) -#define MG5_2_115PL ~(1 << 14) -#else -#define MG5_2_115PL 0xFFFF -#endif - -#if (G5_16PL >= G5_2PL) || (G5_16PL == 0) -#define MG5_2_116PL ~(1 << 15) -#else -#define MG5_2_116PL 0xFFFF -#endif - -#define MG5_2_12PL 0xFFFD -#define MG5_2 (MG5_2_11PL & MG5_2_12PL & MG5_2_13PL & MG5_2_14PL & \ - MG5_2_15PL & MG5_2_16PL & MG5_2_17PL & MG5_2_18PL & \ - MG5_2_19PL & MG5_2_110PL & MG5_2_111PL & MG5_2_112PL & \ - MG5_2_113PL & MG5_2_114PL & MG5_2_115PL & MG5_2_116PL) -// End of MG5_2: -// Beginning of MG53: -#if (G5_1PL >= G5_3PL) || (G5_1PL == 0) -#define MG5_3_11PL ~(1 << 0) -#else -#define MG5_3_11PL 0xFFFF -#endif - -#if (G5_2PL >= G5_3PL) || (G5_2PL == 0) -#define MG5_3_12PL ~(1 << 1) -#else -#define MG5_3_12PL 0xFFFF -#endif - -#if (G5_4PL >= G5_3PL) || (G5_4PL == 0) -#define MG5_3_14PL ~(1 << 3) -#else -#define MG5_3_14PL 0xFFFF -#endif - -#if (G5_5PL >= G5_3PL) || (G5_5PL == 0) -#define MG5_3_15PL ~(1 << 4) -#else -#define MG5_3_15PL 0xFFFF -#endif - -#if (G5_6PL >= G5_3PL) || (G5_6PL == 0) -#define MG5_3_16PL ~(1 << 5) -#else -#define MG5_3_16PL 0xFFFF -#endif - -#if (G5_7PL >= G5_3PL) || (G5_7PL == 0) -#define MG5_3_17PL ~(1 << 6) -#else -#define MG5_3_17PL 0xFFFF -#endif - -#if (G5_8PL >= G5_3PL) || (G5_8PL == 0) -#define MG5_3_18PL ~(1 << 7) -#else -#define MG5_3_18PL 0xFFFF -#endif - -#if (G5_9PL >= G5_3PL) || (G5_9PL == 0) -#define MG5_3_19PL ~(1 << 8) -#else -#define MG5_3_19PL 0xFFFF -#endif - -#if (G5_10PL >= G5_3PL) || (G5_10PL == 0) -#define MG5_3_110PL ~(1 << 9) -#else -#define MG5_3_110PL 0xFFFF -#endif - -#if (G5_11PL >= G5_3PL) || (G5_11PL == 0) -#define MG5_3_111PL ~(1 << 10) -#else -#define MG5_3_111PL 0xFFFF -#endif - -#if (G5_12PL >= G5_3PL) || (G5_12PL == 0) -#define MG5_3_112PL ~(1 << 11) -#else -#define MG5_3_112PL 0xFFFF -#endif - -#if (G5_13PL >= G5_3PL) || (G5_13PL == 0) -#define MG5_3_113PL ~(1 << 12) -#else -#define MG5_3_113PL 0xFFFF -#endif - -#if (G5_14PL >= G5_3PL) || (G5_14PL == 0) -#define MG5_3_114PL ~(1 << 13) -#else -#define MG5_3_114PL 0xFFFF -#endif - -#if (G5_15PL >= G5_3PL) || (G5_15PL == 0) -#define MG5_3_115PL ~(1 << 14) -#else -#define MG5_3_115PL 0xFFFF -#endif - -#if (G5_16PL >= G5_3PL) || (G5_16PL == 0) -#define MG5_3_116PL ~(1 << 15) -#else -#define MG5_3_116PL 0xFFFF -#endif - -#define MG5_3_13PL 0xFFFB -#define MG5_3 (MG5_3_11PL & MG5_3_12PL & MG5_3_13PL & MG5_3_14PL & \ - MG5_3_15PL & MG5_3_16PL & MG5_3_17PL & MG5_3_18PL & \ - MG5_3_19PL & MG5_3_110PL & MG5_3_111PL & MG5_3_112PL & \ - MG5_3_113PL & MG5_3_114PL & MG5_3_115PL & MG5_3_116PL) -// End of MG5_3: -// Beginning of MG54: -#if (G5_1PL >= G5_4PL) || (G5_1PL == 0) -#define MG5_4_11PL ~(1 << 0) -#else -#define MG5_4_11PL 0xFFFF -#endif - -#if (G5_2PL >= G5_4PL) || (G5_2PL == 0) -#define MG5_4_12PL ~(1 << 1) -#else -#define MG5_4_12PL 0xFFFF -#endif - -#if (G5_3PL >= G5_4PL) || (G5_3PL == 0) -#define MG5_4_13PL ~(1 << 2) -#else -#define MG5_4_13PL 0xFFFF -#endif - -#if (G5_5PL >= G5_4PL) || (G5_5PL == 0) -#define MG5_4_15PL ~(1 << 4) -#else -#define MG5_4_15PL 0xFFFF -#endif - -#if (G5_6PL >= G5_4PL) || (G5_6PL == 0) -#define MG5_4_16PL ~(1 << 5) -#else -#define MG5_4_16PL 0xFFFF -#endif - -#if (G5_7PL >= G5_4PL) || (G5_7PL == 0) -#define MG5_4_17PL ~(1 << 6) -#else -#define MG5_4_17PL 0xFFFF -#endif - -#if (G5_8PL >= G5_4PL) || (G5_8PL == 0) -#define MG5_4_18PL ~(1 << 7) -#else -#define MG5_4_18PL 0xFFFF -#endif - -#if (G5_9PL >= G5_4PL) || (G5_9PL == 0) -#define MG5_4_19PL ~(1 << 8) -#else -#define MG5_4_19PL 0xFFFF -#endif - -#if (G5_10PL >= G5_4PL) || (G5_10PL == 0) -#define MG5_4_110PL ~(1 << 9) -#else -#define MG5_4_110PL 0xFFFF -#endif - -#if (G5_11PL >= G5_4PL) || (G5_11PL == 0) -#define MG5_4_111PL ~(1 << 10) -#else -#define MG5_4_111PL 0xFFFF -#endif - -#if (G5_12PL >= G5_4PL) || (G5_12PL == 0) -#define MG5_4_112PL ~(1 << 11) -#else -#define MG5_4_112PL 0xFFFF -#endif - -#if (G5_13PL >= G5_4PL) || (G5_13PL == 0) -#define MG5_4_113PL ~(1 << 12) -#else -#define MG5_4_113PL 0xFFFF -#endif - -#if (G5_14PL >= G5_4PL) || (G5_14PL == 0) -#define MG5_4_114PL ~(1 << 13) -#else -#define MG5_4_114PL 0xFFFF -#endif - -#if (G5_15PL >= G5_4PL) || (G5_15PL == 0) -#define MG5_4_115PL ~(1 << 14) -#else -#define MG5_4_115PL 0xFFFF -#endif - -#if (G5_16PL >= G5_4PL) || (G5_16PL == 0) -#define MG5_4_116PL ~(1 << 15) -#else -#define MG5_4_116PL 0xFFFF -#endif - -#define MG5_4_14PL 0xFFF7 -#define MG5_4 (MG5_4_11PL & MG5_4_12PL & MG5_4_13PL & MG5_4_14PL & \ - MG5_4_15PL & MG5_4_16PL & MG5_4_17PL & MG5_4_18PL & \ - MG5_4_19PL & MG5_4_110PL & MG5_4_111PL & MG5_4_112PL & \ - MG5_4_113PL & MG5_4_114PL & MG5_4_115PL & MG5_4_116PL) -// End of MG5_4: -// Beginning of MG55: -#if (G5_1PL >= G5_5PL) || (G5_1PL == 0) -#define MG5_5_11PL ~(1 << 0) -#else -#define MG5_5_11PL 0xFFFF -#endif - -#if (G5_2PL >= G5_5PL) || (G5_2PL == 0) -#define MG5_5_12PL ~(1 << 1) -#else -#define MG5_5_12PL 0xFFFF -#endif - -#if (G5_3PL >= G5_5PL) || (G5_3PL == 0) -#define MG5_5_13PL ~(1 << 2) -#else -#define MG5_5_13PL 0xFFFF -#endif - -#if (G5_4PL >= G5_5PL) || (G5_4PL == 0) -#define MG5_5_14PL ~(1 << 3) -#else -#define MG5_5_14PL 0xFFFF -#endif - -#if (G5_6PL >= G5_5PL) || (G5_6PL == 0) -#define MG5_5_16PL ~(1 << 5) -#else -#define MG5_5_16PL 0xFFFF -#endif - -#if (G5_7PL >= G5_5PL) || (G5_7PL == 0) -#define MG5_5_17PL ~(1 << 6) -#else -#define MG5_5_17PL 0xFFFF -#endif - -#if (G5_8PL >= G5_5PL) || (G5_8PL == 0) -#define MG5_5_18PL ~(1 << 7) -#else -#define MG5_5_18PL 0xFFFF -#endif - -#if (G5_9PL >= G5_5PL) || (G5_9PL == 0) -#define MG5_5_19PL ~(1 << 8) -#else -#define MG5_5_19PL 0xFFFF -#endif - -#if (G5_10PL >= G5_5PL) || (G5_10PL == 0) -#define MG5_5_110PL ~(1 << 9) -#else -#define MG5_5_110PL 0xFFFF -#endif - -#if (G5_11PL >= G5_5PL) || (G5_11PL == 0) -#define MG5_5_111PL ~(1 << 10) -#else -#define MG5_5_111PL 0xFFFF -#endif - -#if (G5_12PL >= G5_5PL) || (G5_12PL == 0) -#define MG5_5_112PL ~(1 << 11) -#else -#define MG5_5_112PL 0xFFFF -#endif - -#if (G5_13PL >= G5_5PL) || (G5_13PL == 0) -#define MG5_5_113PL ~(1 << 12) -#else -#define MG5_5_113PL 0xFFFF -#endif - -#if (G5_14PL >= G5_5PL) || (G5_14PL == 0) -#define MG5_5_114PL ~(1 << 13) -#else -#define MG5_5_114PL 0xFFFF -#endif - -#if (G5_15PL >= G5_5PL) || (G5_15PL == 0) -#define MG5_5_115PL ~(1 << 14) -#else -#define MG5_5_115PL 0xFFFF -#endif - -#if (G5_16PL >= G5_5PL) || (G5_16PL == 0) -#define MG5_5_116PL ~(1 << 15) -#else -#define MG5_5_116PL 0xFFFF -#endif - -#define MG5_5_15PL 0xFFEF -#define MG5_5 (MG5_5_11PL & MG5_5_12PL & MG5_5_13PL & MG5_5_14PL & \ - MG5_5_15PL & MG5_5_16PL & MG5_5_17PL & MG5_5_18PL & \ - MG5_5_19PL & MG5_5_110PL & MG5_5_111PL & MG5_5_112PL & \ - MG5_5_113PL & MG5_5_114PL & MG5_5_115PL & MG5_5_116PL) -// End of MG5_5: -// Beginning of MG56: -#if (G5_1PL >= G5_6PL) || (G5_1PL == 0) -#define MG5_6_11PL ~(1 << 0) -#else -#define MG5_6_11PL 0xFFFF -#endif - -#if (G5_2PL >= G5_6PL) || (G5_2PL == 0) -#define MG5_6_12PL ~(1 << 1) -#else -#define MG5_6_12PL 0xFFFF -#endif - -#if (G5_3PL >= G5_6PL) || (G5_3PL == 0) -#define MG5_6_13PL ~(1 << 2) -#else -#define MG5_6_13PL 0xFFFF -#endif - -#if (G5_4PL >= G5_6PL) || (G5_4PL == 0) -#define MG5_6_14PL ~(1 << 3) -#else -#define MG5_6_14PL 0xFFFF -#endif - -#if (G5_5PL >= G5_6PL) || (G5_5PL == 0) -#define MG5_6_15PL ~(1 << 4) -#else -#define MG5_6_15PL 0xFFFF -#endif - -#if (G5_7PL >= G5_6PL) || (G5_7PL == 0) -#define MG5_6_17PL ~(1 << 6) -#else -#define MG5_6_17PL 0xFFFF -#endif - -#if (G5_8PL >= G5_6PL) || (G5_8PL == 0) -#define MG5_6_18PL ~(1 << 7) -#else -#define MG5_6_18PL 0xFFFF -#endif - -#if (G5_9PL >= G5_6PL) || (G5_9PL == 0) -#define MG5_6_19PL ~(1 << 8) -#else -#define MG5_6_19PL 0xFFFF -#endif - -#if (G5_10PL >= G5_6PL) || (G5_10PL == 0) -#define MG5_6_110PL ~(1 << 9) -#else -#define MG5_6_110PL 0xFFFF -#endif - -#if (G5_11PL >= G5_6PL) || (G5_11PL == 0) -#define MG5_6_111PL ~(1 << 10) -#else -#define MG5_6_111PL 0xFFFF -#endif - -#if (G5_12PL >= G5_6PL) || (G5_12PL == 0) -#define MG5_6_112PL ~(1 << 11) -#else -#define MG5_6_112PL 0xFFFF -#endif - -#if (G5_13PL >= G5_6PL) || (G5_13PL == 0) -#define MG5_6_113PL ~(1 << 12) -#else -#define MG5_6_113PL 0xFFFF -#endif - -#if (G5_14PL >= G5_6PL) || (G5_14PL == 0) -#define MG5_6_114PL ~(1 << 13) -#else -#define MG5_6_114PL 0xFFFF -#endif - -#if (G5_15PL >= G5_6PL) || (G5_15PL == 0) -#define MG5_6_115PL ~(1 << 14) -#else -#define MG5_6_115PL 0xFFFF -#endif - -#if (G5_16PL >= G5_6PL) || (G5_16PL == 0) -#define MG5_6_116PL ~(1 << 15) -#else -#define MG5_6_116PL 0xFFFF -#endif - -#define MG5_6_16PL 0xFFDF -#define MG5_6 (MG5_6_11PL & MG5_6_12PL & MG5_6_13PL & MG5_6_14PL & \ - MG5_6_15PL & MG5_6_16PL & MG5_6_17PL & MG5_6_18PL & \ - MG5_6_19PL & MG5_6_110PL & MG5_6_111PL & MG5_6_112PL & \ - MG5_6_113PL & MG5_6_114PL & MG5_6_115PL & MG5_6_116PL) -// End of MG5_6: -// Beginning of MG57: -#if (G5_1PL >= G5_7PL) || (G5_1PL == 0) -#define MG5_7_11PL ~(1 << 0) -#else -#define MG5_7_11PL 0xFFFF -#endif - -#if (G5_2PL >= G5_7PL) || (G5_2PL == 0) -#define MG5_7_12PL ~(1 << 1) -#else -#define MG5_7_12PL 0xFFFF -#endif - -#if (G5_3PL >= G5_7PL) || (G5_3PL == 0) -#define MG5_7_13PL ~(1 << 2) -#else -#define MG5_7_13PL 0xFFFF -#endif - -#if (G5_4PL >= G5_7PL) || (G5_4PL == 0) -#define MG5_7_14PL ~(1 << 3) -#else -#define MG5_7_14PL 0xFFFF -#endif - -#if (G5_5PL >= G5_7PL) || (G5_5PL == 0) -#define MG5_7_15PL ~(1 << 4) -#else -#define MG5_7_15PL 0xFFFF -#endif - -#if (G5_6PL >= G5_7PL) || (G5_6PL == 0) -#define MG5_7_16PL ~(1 << 5) -#else -#define MG5_7_16PL 0xFFFF -#endif - -#if (G5_8PL >= G5_7PL) || (G5_8PL == 0) -#define MG5_7_18PL ~(1 << 7) -#else -#define MG5_7_18PL 0xFFFF -#endif - -#if (G5_9PL >= G5_7PL) || (G5_9PL == 0) -#define MG5_7_19PL ~(1 << 8) -#else -#define MG5_7_19PL 0xFFFF -#endif - -#if (G5_10PL >= G5_7PL) || (G5_10PL == 0) -#define MG5_7_110PL ~(1 << 9) -#else -#define MG5_7_110PL 0xFFFF -#endif - -#if (G5_11PL >= G5_7PL) || (G5_11PL == 0) -#define MG5_7_111PL ~(1 << 10) -#else -#define MG5_7_111PL 0xFFFF -#endif - -#if (G5_12PL >= G5_7PL) || (G5_12PL == 0) -#define MG5_7_112PL ~(1 << 11) -#else -#define MG5_7_112PL 0xFFFF -#endif - -#if (G5_13PL >= G5_7PL) || (G5_13PL == 0) -#define MG5_7_113PL ~(1 << 12) -#else -#define MG5_7_113PL 0xFFFF -#endif - -#if (G5_14PL >= G5_7PL) || (G5_14PL == 0) -#define MG5_7_114PL ~(1 << 13) -#else -#define MG5_7_114PL 0xFFFF -#endif - -#if (G5_15PL >= G5_7PL) || (G5_15PL == 0) -#define MG5_7_115PL ~(1 << 14) -#else -#define MG5_7_115PL 0xFFFF -#endif - -#if (G5_16PL >= G5_7PL) || (G5_16PL == 0) -#define MG5_7_116PL ~(1 << 15) -#else -#define MG5_7_116PL 0xFFFF -#endif - -#define MG5_7_17PL 0xFFBF -#define MG5_7 (MG5_7_11PL & MG5_7_12PL & MG5_7_13PL & MG5_7_14PL & \ - MG5_7_15PL & MG5_7_16PL & MG5_7_17PL & MG5_7_18PL & \ - MG5_7_19PL & MG5_7_110PL & MG5_7_111PL & MG5_7_112PL & \ - MG5_7_113PL & MG5_7_114PL & MG5_7_115PL & MG5_7_116PL) -// End of MG5_7: -// Beginning of MG58: -#if (G5_1PL >= G5_8PL) || (G5_1PL == 0) -#define MG5_8_11PL ~(1 << 0) -#else -#define MG5_8_11PL 0xFFFF -#endif - -#if (G5_2PL >= G5_8PL) || (G5_2PL == 0) -#define MG5_8_12PL ~(1 << 1) -#else -#define MG5_8_12PL 0xFFFF -#endif - -#if (G5_3PL >= G5_8PL) || (G5_3PL == 0) -#define MG5_8_13PL ~(1 << 2) -#else -#define MG5_8_13PL 0xFFFF -#endif - -#if (G5_4PL >= G5_8PL) || (G5_4PL == 0) -#define MG5_8_14PL ~(1 << 3) -#else -#define MG5_8_14PL 0xFFFF -#endif - -#if (G5_5PL >= G5_8PL) || (G5_5PL == 0) -#define MG5_8_15PL ~(1 << 4) -#else -#define MG5_8_15PL 0xFFFF -#endif - -#if (G5_6PL >= G5_8PL) || (G5_6PL == 0) -#define MG5_8_16PL ~(1 << 5) -#else -#define MG5_8_16PL 0xFFFF -#endif - -#if (G5_7PL >= G5_8PL) || (G5_7PL == 0) -#define MG5_8_17PL ~(1 << 6) -#else -#define MG5_8_17PL 0xFFFF -#endif - -#if (G5_9PL >= G5_8PL) || (G5_9PL == 0) -#define MG5_8_19PL ~(1 << 8) -#else -#define MG5_8_19PL 0xFFFF -#endif - -#if (G5_10PL >= G5_8PL) || (G5_10PL == 0) -#define MG5_8_110PL ~(1 << 9) -#else -#define MG5_8_110PL 0xFFFF -#endif - -#if (G5_11PL >= G5_8PL) || (G5_11PL == 0) -#define MG5_8_111PL ~(1 << 10) -#else -#define MG5_8_111PL 0xFFFF -#endif - -#if (G5_12PL >= G5_8PL) || (G5_12PL == 0) -#define MG5_8_112PL ~(1 << 11) -#else -#define MG5_8_112PL 0xFFFF -#endif - -#if (G5_13PL >= G5_8PL) || (G5_13PL == 0) -#define MG5_8_113PL ~(1 << 12) -#else -#define MG5_8_113PL 0xFFFF -#endif - -#if (G5_14PL >= G5_8PL) || (G5_14PL == 0) -#define MG5_8_114PL ~(1 << 13) -#else -#define MG5_8_114PL 0xFFFF -#endif - -#if (G5_15PL >= G5_8PL) || (G5_15PL == 0) -#define MG5_8_115PL ~(1 << 14) -#else -#define MG5_8_115PL 0xFFFF -#endif - -#if (G5_16PL >= G5_8PL) || (G5_16PL == 0) -#define MG5_8_116PL ~(1 << 15) -#else -#define MG5_8_116PL 0xFFFF -#endif - -#define MG5_8_18PL 0xFF7F -#define MG5_8 (MG5_8_11PL & MG5_8_12PL & MG5_8_13PL & MG5_8_14PL & \ - MG5_8_15PL & MG5_8_16PL & MG5_8_17PL & MG5_8_18PL & \ - MG5_8_19PL & MG5_8_110PL & MG5_8_111PL & MG5_8_112PL & \ - MG5_8_113PL & MG5_8_114PL & MG5_8_115PL & MG5_8_116PL) -// End of MG5_8: -// Beginning of MG59: -#if (G5_1PL >= G5_9PL) || (G5_1PL == 0) -#define MG5_9_11PL ~(1 << 0) -#else -#define MG5_9_11PL 0xFFFF -#endif - -#if (G5_2PL >= G5_9PL) || (G5_2PL == 0) -#define MG5_9_12PL ~(1 << 1) -#else -#define MG5_9_12PL 0xFFFF -#endif - -#if (G5_3PL >= G5_9PL) || (G5_3PL == 0) -#define MG5_9_13PL ~(1 << 2) -#else -#define MG5_9_13PL 0xFFFF -#endif - -#if (G5_4PL >= G5_9PL) || (G5_4PL == 0) -#define MG5_9_14PL ~(1 << 3) -#else -#define MG5_9_14PL 0xFFFF -#endif - -#if (G5_5PL >= G5_9PL) || (G5_5PL == 0) -#define MG5_9_15PL ~(1 << 4) -#else -#define MG5_9_15PL 0xFFFF -#endif - -#if (G5_6PL >= G5_9PL) || (G5_6PL == 0) -#define MG5_9_16PL ~(1 << 5) -#else -#define MG5_9_16PL 0xFFFF -#endif - -#if (G5_7PL >= G5_9PL) || (G5_7PL == 0) -#define MG5_9_17PL ~(1 << 6) -#else -#define MG5_9_17PL 0xFFFF -#endif - -#if (G5_8PL >= G5_9PL) || (G5_8PL == 0) -#define MG5_9_18PL ~(1 << 7) -#else -#define MG5_9_18PL 0xFFFF -#endif - -#if (G5_10PL >= G5_9PL) || (G5_10PL == 0) -#define MG5_9_110PL ~(1 << 9) -#else -#define MG5_9_110PL 0xFFFF -#endif - -#if (G5_11PL >= G5_9PL) || (G5_11PL == 0) -#define MG5_9_111PL ~(1 << 10) -#else -#define MG5_9_111PL 0xFFFF -#endif - -#if (G5_12PL >= G5_9PL) || (G5_12PL == 0) -#define MG5_9_112PL ~(1 << 11) -#else -#define MG5_9_112PL 0xFFFF -#endif - -#if (G5_13PL >= G5_9PL) || (G5_13PL == 0) -#define MG5_9_113PL ~(1 << 12) -#else -#define MG5_9_113PL 0xFFFF -#endif - -#if (G5_14PL >= G5_9PL) || (G5_14PL == 0) -#define MG5_9_114PL ~(1 << 13) -#else -#define MG5_9_114PL 0xFFFF -#endif - -#if (G5_15PL >= G5_9PL) || (G5_15PL == 0) -#define MG5_9_115PL ~(1 << 14) -#else -#define MG5_9_115PL 0xFFFF -#endif - -#if (G5_16PL >= G5_9PL) || (G5_16PL == 0) -#define MG5_9_116PL ~(1 << 15) -#else -#define MG5_9_116PL 0xFFFF -#endif - -#define MG5_9_19PL 0xFEFF -#define MG5_9 (MG5_9_11PL & MG5_9_12PL & MG5_9_13PL & MG5_9_14PL & \ - MG5_9_15PL & MG5_9_16PL & MG5_9_17PL & MG5_9_18PL & \ - MG5_9_19PL & MG5_9_110PL & MG5_9_111PL & MG5_9_112PL & \ - MG5_9_113PL & MG5_9_114PL & MG5_9_115PL & MG5_9_116PL) -// End of MG5_9: -// Beginning of MG510: -#if (G5_1PL >= G5_10PL) || (G5_1PL == 0) -#define MG5_10_11PL ~(1 << 0) -#else -#define MG5_10_11PL 0xFFFF -#endif - -#if (G5_2PL >= G5_10PL) || (G5_2PL == 0) -#define MG5_10_12PL ~(1 << 1) -#else -#define MG5_10_12PL 0xFFFF -#endif - -#if (G5_3PL >= G5_10PL) || (G5_3PL == 0) -#define MG5_10_13PL ~(1 << 2) -#else -#define MG5_10_13PL 0xFFFF -#endif - -#if (G5_4PL >= G5_10PL) || (G5_4PL == 0) -#define MG5_10_14PL ~(1 << 3) -#else -#define MG5_10_14PL 0xFFFF -#endif - -#if (G5_5PL >= G5_10PL) || (G5_5PL == 0) -#define MG5_10_15PL ~(1 << 4) -#else -#define MG5_10_15PL 0xFFFF -#endif - -#if (G5_6PL >= G5_10PL) || (G5_6PL == 0) -#define MG5_10_16PL ~(1 << 5) -#else -#define MG5_10_16PL 0xFFFF -#endif - -#if (G5_7PL >= G5_10PL) || (G5_7PL == 0) -#define MG5_10_17PL ~(1 << 6) -#else -#define MG5_10_17PL 0xFFFF -#endif - -#if (G5_8PL >= G5_10PL) || (G5_8PL == 0) -#define MG5_10_18PL ~(1 << 7) -#else -#define MG5_10_18PL 0xFFFF -#endif - -#if (G5_9PL >= G5_10PL) || (G5_9PL == 0) -#define MG5_10_19PL ~(1 << 8) -#else -#define MG5_10_19PL 0xFFFF -#endif - -#if (G5_11PL >= G5_10PL) || (G5_11PL == 0) -#define MG5_10_111PL ~(1 << 10) -#else -#define MG5_10_111PL 0xFFFF -#endif - -#if (G5_12PL >= G5_10PL) || (G5_12PL == 0) -#define MG5_10_112PL ~(1 << 11) -#else -#define MG5_10_112PL 0xFFFF -#endif - -#if (G5_13PL >= G5_10PL) || (G5_13PL == 0) -#define MG5_10_113PL ~(1 << 12) -#else -#define MG5_10_113PL 0xFFFF -#endif - -#if (G5_14PL >= G5_10PL) || (G5_14PL == 0) -#define MG5_10_114PL ~(1 << 13) -#else -#define MG5_10_114PL 0xFFFF -#endif - -#if (G5_15PL >= G5_10PL) || (G5_15PL == 0) -#define MG5_10_115PL ~(1 << 14) -#else -#define MG5_10_115PL 0xFFFF -#endif - -#if (G5_16PL >= G5_10PL) || (G5_16PL == 0) -#define MG5_10_116PL ~(1 << 15) -#else -#define MG5_10_116PL 0xFFFF -#endif - -#define MG5_10_110PL 0xFDFF -#define MG5_10 (MG5_10_11PL & MG5_10_12PL & MG5_10_13PL & MG5_10_14PL & \ - MG5_10_15PL & MG5_10_16PL & MG5_10_17PL & MG5_10_18PL & \ - MG5_10_19PL & MG5_10_110PL & MG5_10_111PL & MG5_10_112PL & \ - MG5_10_113PL & MG5_10_114PL & MG5_10_115PL & MG5_10_116PL) -// End of MG5_10: -// Beginning of MG511: -#if (G5_1PL >= G5_11PL) || (G5_1PL == 0) -#define MG5_11_11PL ~(1 << 0) -#else -#define MG5_11_11PL 0xFFFF -#endif - -#if (G5_2PL >= G5_11PL) || (G5_2PL == 0) -#define MG5_11_12PL ~(1 << 1) -#else -#define MG5_11_12PL 0xFFFF -#endif - -#if (G5_3PL >= G5_11PL) || (G5_3PL == 0) -#define MG5_11_13PL ~(1 << 2) -#else -#define MG5_11_13PL 0xFFFF -#endif - -#if (G5_4PL >= G5_11PL) || (G5_4PL == 0) -#define MG5_11_14PL ~(1 << 3) -#else -#define MG5_11_14PL 0xFFFF -#endif - -#if (G5_5PL >= G5_11PL) || (G5_5PL == 0) -#define MG5_11_15PL ~(1 << 4) -#else -#define MG5_11_15PL 0xFFFF -#endif - -#if (G5_6PL >= G5_11PL) || (G5_6PL == 0) -#define MG5_11_16PL ~(1 << 5) -#else -#define MG5_11_16PL 0xFFFF -#endif - -#if (G5_7PL >= G5_11PL) || (G5_7PL == 0) -#define MG5_11_17PL ~(1 << 6) -#else -#define MG5_11_17PL 0xFFFF -#endif - -#if (G5_8PL >= G5_11PL) || (G5_8PL == 0) -#define MG5_11_18PL ~(1 << 7) -#else -#define MG5_11_18PL 0xFFFF -#endif - -#if (G5_9PL >= G5_11PL) || (G5_9PL == 0) -#define MG5_11_19PL ~(1 << 8) -#else -#define MG5_11_19PL 0xFFFF -#endif - -#if (G5_10PL >= G5_11PL) || (G5_10PL == 0) -#define MG5_11_110PL ~(1 << 9) -#else -#define MG5_11_110PL 0xFFFF -#endif - -#if (G5_12PL >= G5_11PL) || (G5_12PL == 0) -#define MG5_11_112PL ~(1 << 11) -#else -#define MG5_11_112PL 0xFFFF -#endif - -#if (G5_13PL >= G5_11PL) || (G5_13PL == 0) -#define MG5_11_113PL ~(1 << 12) -#else -#define MG5_11_113PL 0xFFFF -#endif - -#if (G5_14PL >= G5_11PL) || (G5_14PL == 0) -#define MG5_11_114PL ~(1 << 13) -#else -#define MG5_11_114PL 0xFFFF -#endif - -#if (G5_15PL >= G5_11PL) || (G5_15PL == 0) -#define MG5_11_115PL ~(1 << 14) -#else -#define MG5_11_115PL 0xFFFF -#endif - -#if (G5_16PL >= G5_11PL) || (G5_16PL == 0) -#define MG5_11_116PL ~(1 << 15) -#else -#define MG5_11_116PL 0xFFFF -#endif - -#define MG5_11_111PL 0xFBFF -#define MG5_11 (MG5_11_11PL & MG5_11_12PL & MG5_11_13PL & MG5_11_14PL & \ - MG5_11_15PL & MG5_11_16PL & MG5_11_17PL & MG5_11_18PL & \ - MG5_11_19PL & MG5_11_110PL & MG5_11_111PL & MG5_11_112PL & \ - MG5_11_113PL & MG5_11_114PL & MG5_11_115PL & MG5_11_116PL) -// End of MG5_11: -// Beginning of MG512: -#if (G5_1PL >= G5_12PL) || (G5_1PL == 0) -#define MG5_12_11PL ~(1 << 0) -#else -#define MG5_12_11PL 0xFFFF -#endif - -#if (G5_2PL >= G5_12PL) || (G5_2PL == 0) -#define MG5_12_12PL ~(1 << 1) -#else -#define MG5_12_12PL 0xFFFF -#endif - -#if (G5_3PL >= G5_12PL) || (G5_3PL == 0) -#define MG5_12_13PL ~(1 << 2) -#else -#define MG5_12_13PL 0xFFFF -#endif - -#if (G5_4PL >= G5_12PL) || (G5_4PL == 0) -#define MG5_12_14PL ~(1 << 3) -#else -#define MG5_12_14PL 0xFFFF -#endif - -#if (G5_5PL >= G5_12PL) || (G5_5PL == 0) -#define MG5_12_15PL ~(1 << 4) -#else -#define MG5_12_15PL 0xFFFF -#endif - -#if (G5_6PL >= G5_12PL) || (G5_6PL == 0) -#define MG5_12_16PL ~(1 << 5) -#else -#define MG5_12_16PL 0xFFFF -#endif - -#if (G5_7PL >= G5_12PL) || (G5_7PL == 0) -#define MG5_12_17PL ~(1 << 6) -#else -#define MG5_12_17PL 0xFFFF -#endif - -#if (G5_8PL >= G5_12PL) || (G5_8PL == 0) -#define MG5_12_18PL ~(1 << 7) -#else -#define MG5_12_18PL 0xFFFF -#endif - -#if (G5_9PL >= G5_12PL) || (G5_9PL == 0) -#define MG5_12_19PL ~(1 << 8) -#else -#define MG5_12_19PL 0xFFFF -#endif - -#if (G5_10PL >= G5_12PL) || (G5_10PL == 0) -#define MG5_12_110PL ~(1 << 9) -#else -#define MG5_12_110PL 0xFFFF -#endif - -#if (G5_11PL >= G5_12PL) || (G5_11PL == 0) -#define MG5_12_111PL ~(1 << 10) -#else -#define MG5_12_111PL 0xFFFF -#endif - -#if (G5_13PL >= G5_12PL) || (G5_13PL == 0) -#define MG5_12_113PL ~(1 << 12) -#else -#define MG5_12_113PL 0xFFFF -#endif - -#if (G5_14PL >= G5_12PL) || (G5_14PL == 0) -#define MG5_12_114PL ~(1 << 13) -#else -#define MG5_12_114PL 0xFFFF -#endif - -#if (G5_15PL >= G5_12PL) || (G5_15PL == 0) -#define MG5_12_115PL ~(1 << 14) -#else -#define MG5_12_115PL 0xFFFF -#endif - -#if (G5_16PL >= G5_12PL) || (G5_16PL == 0) -#define MG5_12_116PL ~(1 << 15) -#else -#define MG5_12_116PL 0xFFFF -#endif - -#define MG5_12_112PL 0xF7FF -#define MG5_12 (MG5_12_11PL & MG5_12_12PL & MG5_12_13PL & MG5_12_14PL & \ - MG5_12_15PL & MG5_12_16PL & MG5_12_17PL & MG5_12_18PL & \ - MG5_12_19PL & MG5_12_110PL & MG5_12_111PL & MG5_12_112PL & \ - MG5_12_113PL & MG5_12_114PL & MG5_12_115PL & MG5_12_116PL) -// End of MG5_12: -// Beginning of MG513: -#if (G5_1PL >= G5_13PL) || (G5_1PL == 0) -#define MG5_13_11PL ~(1 << 0) -#else -#define MG5_13_11PL 0xFFFF -#endif - -#if (G5_2PL >= G5_13PL) || (G5_2PL == 0) -#define MG5_13_12PL ~(1 << 1) -#else -#define MG5_13_12PL 0xFFFF -#endif - -#if (G5_3PL >= G5_13PL) || (G5_3PL == 0) -#define MG5_13_13PL ~(1 << 2) -#else -#define MG5_13_13PL 0xFFFF -#endif - -#if (G5_4PL >= G5_13PL) || (G5_4PL == 0) -#define MG5_13_14PL ~(1 << 3) -#else -#define MG5_13_14PL 0xFFFF -#endif - -#if (G5_5PL >= G5_13PL) || (G5_5PL == 0) -#define MG5_13_15PL ~(1 << 4) -#else -#define MG5_13_15PL 0xFFFF -#endif - -#if (G5_6PL >= G5_13PL) || (G5_6PL == 0) -#define MG5_13_16PL ~(1 << 5) -#else -#define MG5_13_16PL 0xFFFF -#endif - -#if (G5_7PL >= G5_13PL) || (G5_7PL == 0) -#define MG5_13_17PL ~(1 << 6) -#else -#define MG5_13_17PL 0xFFFF -#endif - -#if (G5_8PL >= G5_13PL) || (G5_8PL == 0) -#define MG5_13_18PL ~(1 << 7) -#else -#define MG5_13_18PL 0xFFFF -#endif - -#if (G5_9PL >= G5_13PL) || (G5_9PL == 0) -#define MG5_13_19PL ~(1 << 8) -#else -#define MG5_13_19PL 0xFFFF -#endif - -#if (G5_10PL >= G5_13PL) || (G5_10PL == 0) -#define MG5_13_110PL ~(1 << 9) -#else -#define MG5_13_110PL 0xFFFF -#endif - -#if (G5_11PL >= G5_13PL) || (G5_11PL == 0) -#define MG5_13_111PL ~(1 << 10) -#else -#define MG5_13_111PL 0xFFFF -#endif - -#if (G5_12PL >= G5_13PL) || (G5_12PL == 0) -#define MG5_13_112PL ~(1 << 11) -#else -#define MG5_13_112PL 0xFFFF -#endif - -#if (G5_14PL >= G5_13PL) || (G5_14PL == 0) -#define MG5_13_114PL ~(1 << 13) -#else -#define MG5_13_114PL 0xFFFF -#endif - -#if (G5_15PL >= G5_13PL) || (G5_15PL == 0) -#define MG5_13_115PL ~(1 << 14) -#else -#define MG5_13_115PL 0xFFFF -#endif - -#if (G5_16PL >= G5_13PL) || (G5_16PL == 0) -#define MG5_13_116PL ~(1 << 15) -#else -#define MG5_13_116PL 0xFFFF -#endif - -#define MG5_13_113PL 0xEFFF -#define MG5_13 (MG5_13_11PL & MG5_13_12PL & MG5_13_13PL & MG5_13_14PL & \ - MG5_13_15PL & MG5_13_16PL & MG5_13_17PL & MG5_13_18PL & \ - MG5_13_19PL & MG5_13_110PL & MG5_13_111PL & MG5_13_112PL & \ - MG5_13_113PL & MG5_13_114PL & MG5_13_115PL & MG5_13_116PL) -// End of MG5_13: -// Beginning of MG514: -#if (G5_1PL >= G5_14PL) || (G5_1PL == 0) -#define MG5_14_11PL ~(1 << 0) -#else -#define MG5_14_11PL 0xFFFF -#endif - -#if (G5_2PL >= G5_14PL) || (G5_2PL == 0) -#define MG5_14_12PL ~(1 << 1) -#else -#define MG5_14_12PL 0xFFFF -#endif - -#if (G5_3PL >= G5_14PL) || (G5_3PL == 0) -#define MG5_14_13PL ~(1 << 2) -#else -#define MG5_14_13PL 0xFFFF -#endif - -#if (G5_4PL >= G5_14PL) || (G5_4PL == 0) -#define MG5_14_14PL ~(1 << 3) -#else -#define MG5_14_14PL 0xFFFF -#endif - -#if (G5_5PL >= G5_14PL) || (G5_5PL == 0) -#define MG5_14_15PL ~(1 << 4) -#else -#define MG5_14_15PL 0xFFFF -#endif - -#if (G5_6PL >= G5_14PL) || (G5_6PL == 0) -#define MG5_14_16PL ~(1 << 5) -#else -#define MG5_14_16PL 0xFFFF -#endif - -#if (G5_7PL >= G5_14PL) || (G5_7PL == 0) -#define MG5_14_17PL ~(1 << 6) -#else -#define MG5_14_17PL 0xFFFF -#endif - -#if (G5_8PL >= G5_14PL) || (G5_8PL == 0) -#define MG5_14_18PL ~(1 << 7) -#else -#define MG5_14_18PL 0xFFFF -#endif - -#if (G5_9PL >= G5_14PL) || (G5_9PL == 0) -#define MG5_14_19PL ~(1 << 8) -#else -#define MG5_14_19PL 0xFFFF -#endif - -#if (G5_10PL >= G5_14PL) || (G5_10PL == 0) -#define MG5_14_110PL ~(1 << 9) -#else -#define MG5_14_110PL 0xFFFF -#endif - -#if (G5_11PL >= G5_14PL) || (G5_11PL == 0) -#define MG5_14_111PL ~(1 << 10) -#else -#define MG5_14_111PL 0xFFFF -#endif - -#if (G5_12PL >= G5_14PL) || (G5_12PL == 0) -#define MG5_14_112PL ~(1 << 11) -#else -#define MG5_14_112PL 0xFFFF -#endif - -#if (G5_13PL >= G5_14PL) || (G5_13PL == 0) -#define MG5_14_113PL ~(1 << 12) -#else -#define MG5_14_113PL 0xFFFF -#endif - -#if (G5_15PL >= G5_14PL) || (G5_15PL == 0) -#define MG5_14_115PL ~(1 << 14) -#else -#define MG5_14_115PL 0xFFFF -#endif - -#if (G5_16PL >= G5_14PL) || (G5_16PL == 0) -#define MG5_14_116PL ~(1 << 15) -#else -#define MG5_14_116PL 0xFFFF -#endif - -#define MG5_14_114PL 0xDFFF -#define MG5_14 (MG5_14_11PL & MG5_14_12PL & MG5_14_13PL & MG5_14_14PL & \ - MG5_14_15PL & MG5_14_16PL & MG5_14_17PL & MG5_14_18PL & \ - MG5_14_19PL & MG5_14_110PL & MG5_14_111PL & MG5_14_112PL & \ - MG5_14_113PL & MG5_14_114PL & MG5_14_115PL & MG5_14_116PL) -// End of MG5_14: -// Beginning of MG515: -#if (G5_1PL >= G5_15PL) || (G5_1PL == 0) -#define MG5_15_11PL ~(1 << 0) -#else -#define MG5_15_11PL 0xFFFF -#endif - -#if (G5_2PL >= G5_15PL) || (G5_2PL == 0) -#define MG5_15_12PL ~(1 << 1) -#else -#define MG5_15_12PL 0xFFFF -#endif - -#if (G5_3PL >= G5_15PL) || (G5_3PL == 0) -#define MG5_15_13PL ~(1 << 2) -#else -#define MG5_15_13PL 0xFFFF -#endif - -#if (G5_4PL >= G5_15PL) || (G5_4PL == 0) -#define MG5_15_14PL ~(1 << 3) -#else -#define MG5_15_14PL 0xFFFF -#endif - -#if (G5_5PL >= G5_15PL) || (G5_5PL == 0) -#define MG5_15_15PL ~(1 << 4) -#else -#define MG5_15_15PL 0xFFFF -#endif - -#if (G5_6PL >= G5_15PL) || (G5_6PL == 0) -#define MG5_15_16PL ~(1 << 5) -#else -#define MG5_15_16PL 0xFFFF -#endif - -#if (G5_7PL >= G5_15PL) || (G5_7PL == 0) -#define MG5_15_17PL ~(1 << 6) -#else -#define MG5_15_17PL 0xFFFF -#endif - -#if (G5_8PL >= G5_15PL) || (G5_8PL == 0) -#define MG5_15_18PL ~(1 << 7) -#else -#define MG5_15_18PL 0xFFFF -#endif - -#if (G5_9PL >= G5_15PL) || (G5_9PL == 0) -#define MG5_15_19PL ~(1 << 8) -#else -#define MG5_15_19PL 0xFFFF -#endif - -#if (G5_10PL >= G5_15PL) || (G5_10PL == 0) -#define MG5_15_110PL ~(1 << 9) -#else -#define MG5_15_110PL 0xFFFF -#endif - -#if (G5_11PL >= G5_15PL) || (G5_11PL == 0) -#define MG5_15_111PL ~(1 << 10) -#else -#define MG5_15_111PL 0xFFFF -#endif - -#if (G5_12PL >= G5_15PL) || (G5_12PL == 0) -#define MG5_15_112PL ~(1 << 11) -#else -#define MG5_15_112PL 0xFFFF -#endif - -#if (G5_13PL >= G5_15PL) || (G5_13PL == 0) -#define MG5_15_113PL ~(1 << 12) -#else -#define MG5_15_113PL 0xFFFF -#endif - -#if (G5_14PL >= G5_15PL) || (G5_14PL == 0) -#define MG5_15_114PL ~(1 << 13) -#else -#define MG5_15_114PL 0xFFFF -#endif - -#if (G5_16PL >= G5_15PL) || (G5_16PL == 0) -#define MG5_15_116PL ~(1 << 15) -#else -#define MG5_15_116PL 0xFFFF -#endif - -#define MG5_15_115PL 0xBFFF -#define MG5_15 (MG5_15_11PL & MG5_15_12PL & MG5_15_13PL & MG5_15_14PL & \ - MG5_15_15PL & MG5_15_16PL & MG5_15_17PL & MG5_15_18PL & \ - MG5_15_19PL & MG5_15_110PL & MG5_15_111PL & MG5_15_112PL & \ - MG5_15_113PL & MG5_15_114PL & MG5_15_115PL & MG5_15_116PL) -// End of MG5_15: -// Beginning of MG516: -#if (G5_1PL >= G5_16PL) || (G5_1PL == 0) -#define MG5_16_11PL ~(1 << 0) -#else -#define MG5_16_11PL 0xFFFF -#endif - -#if (G5_2PL >= G5_16PL) || (G5_2PL == 0) -#define MG5_16_12PL ~(1 << 1) -#else -#define MG5_16_12PL 0xFFFF -#endif - -#if (G5_3PL >= G5_16PL) || (G5_3PL == 0) -#define MG5_16_13PL ~(1 << 2) -#else -#define MG5_16_13PL 0xFFFF -#endif - -#if (G5_4PL >= G5_16PL) || (G5_4PL == 0) -#define MG5_16_14PL ~(1 << 3) -#else -#define MG5_16_14PL 0xFFFF -#endif - -#if (G5_5PL >= G5_16PL) || (G5_5PL == 0) -#define MG5_16_15PL ~(1 << 4) -#else -#define MG5_16_15PL 0xFFFF -#endif - -#if (G5_6PL >= G5_16PL) || (G5_6PL == 0) -#define MG5_16_16PL ~(1 << 5) -#else -#define MG5_16_16PL 0xFFFF -#endif - -#if (G5_7PL >= G5_16PL) || (G5_7PL == 0) -#define MG5_16_17PL ~(1 << 6) -#else -#define MG5_16_17PL 0xFFFF -#endif - -#if (G5_8PL >= G5_16PL) || (G5_8PL == 0) -#define MG5_16_18PL ~(1 << 7) -#else -#define MG5_16_18PL 0xFFFF -#endif - -#if (G5_9PL >= G5_16PL) || (G5_9PL == 0) -#define MG5_16_19PL ~(1 << 8) -#else -#define MG5_16_19PL 0xFFFF -#endif - -#if (G5_10PL >= G5_16PL) || (G5_10PL == 0) -#define MG5_16_110PL ~(1 << 9) -#else -#define MG5_16_110PL 0xFFFF -#endif - -#if (G5_11PL >= G5_16PL) || (G5_11PL == 0) -#define MG5_16_111PL ~(1 << 10) -#else -#define MG5_16_111PL 0xFFFF -#endif - -#if (G5_12PL >= G5_16PL) || (G5_12PL == 0) -#define MG5_16_112PL ~(1 << 11) -#else -#define MG5_16_112PL 0xFFFF -#endif - -#if (G5_13PL >= G5_16PL) || (G5_13PL == 0) -#define MG5_16_113PL ~(1 << 12) -#else -#define MG5_16_113PL 0xFFFF -#endif - -#if (G5_14PL >= G5_16PL) || (G5_14PL == 0) -#define MG5_16_114PL ~(1 << 13) -#else -#define MG5_16_114PL 0xFFFF -#endif - -#if (G5_15PL >= G5_16PL) || (G5_15PL == 0) -#define MG5_16_115PL ~(1 << 14) -#else -#define MG5_16_115PL 0xFFFF -#endif - -#define MG5_16_116PL 0x7FFF -#define MG5_16 (MG5_16_11PL & MG5_16_12PL & MG5_16_13PL & MG5_16_14PL & \ - MG5_16_15PL & MG5_16_16PL & MG5_16_17PL & MG5_16_18PL & \ - MG5_16_19PL & MG5_16_110PL & MG5_16_111PL & MG5_16_112PL & \ - MG5_16_113PL & MG5_16_114PL & MG5_16_115PL & MG5_16_116PL) -// End of MG5_16: - - -// -// Automatically generate PIEIER6 interrupt masks MG61 to MG616: -// - -// Beginning of MG61: -#if (G6_2PL >= G6_1PL) || (G6_2PL == 0) -#define MG6_1_12PL ~(1 << 1) -#else -#define MG6_1_12PL 0xFFFF -#endif - -#if (G6_3PL >= G6_1PL) || (G6_3PL == 0) -#define MG6_1_13PL ~(1 << 2) -#else -#define MG6_1_13PL 0xFFFF -#endif - -#if (G6_4PL >= G6_1PL) || (G6_4PL == 0) -#define MG6_1_14PL ~(1 << 3) -#else -#define MG6_1_14PL 0xFFFF -#endif - -#if (G6_5PL >= G6_1PL) || (G6_5PL == 0) -#define MG6_1_15PL ~(1 << 4) -#else -#define MG6_1_15PL 0xFFFF -#endif - -#if (G6_6PL >= G6_1PL) || (G6_6PL == 0) -#define MG6_1_16PL ~(1 << 5) -#else -#define MG6_1_16PL 0xFFFF -#endif - -#if (G6_7PL >= G6_1PL) || (G6_7PL == 0) -#define MG6_1_17PL ~(1 << 6) -#else -#define MG6_1_17PL 0xFFFF -#endif - -#if (G6_8PL >= G6_1PL) || (G6_8PL == 0) -#define MG6_1_18PL ~(1 << 7) -#else -#define MG6_1_18PL 0xFFFF -#endif - -#if (G6_9PL >= G6_1PL) || (G6_9PL == 0) -#define MG6_1_19PL ~(1 << 8) -#else -#define MG6_1_19PL 0xFFFF -#endif - -#if (G6_10PL >= G6_1PL) || (G6_10PL == 0) -#define MG6_1_110PL ~(1 << 9) -#else -#define MG6_1_110PL 0xFFFF -#endif - -#if (G6_11PL >= G6_1PL) || (G6_11PL == 0) -#define MG6_1_111PL ~(1 << 10) -#else -#define MG6_1_111PL 0xFFFF -#endif - -#if (G6_12PL >= G6_1PL) || (G6_12PL == 0) -#define MG6_1_112PL ~(1 << 11) -#else -#define MG6_1_112PL 0xFFFF -#endif - -#if (G6_13PL >= G6_1PL) || (G6_13PL == 0) -#define MG6_1_113PL ~(1 << 12) -#else -#define MG6_1_113PL 0xFFFF -#endif - -#if (G6_14PL >= G6_1PL) || (G6_14PL == 0) -#define MG6_1_114PL ~(1 << 13) -#else -#define MG6_1_114PL 0xFFFF -#endif - -#if (G6_15PL >= G6_1PL) || (G6_15PL == 0) -#define MG6_1_115PL ~(1 << 14) -#else -#define MG6_1_115PL 0xFFFF -#endif - -#if (G6_16PL >= G6_1PL) || (G6_16PL == 0) -#define MG6_1_116PL ~(1 << 15) -#else -#define MG6_1_116PL 0xFFFF -#endif - -#define MG6_1_11PL 0xFFFE -#define MG6_1 (MG6_1_11PL & MG6_1_12PL & MG6_1_13PL & MG6_1_14PL & \ - MG6_1_15PL & MG6_1_16PL & MG6_1_17PL & MG6_1_18PL & \ - MG6_1_19PL & MG6_1_110PL & MG6_1_111PL & MG6_1_112PL & \ - MG6_1_113PL & MG6_1_114PL & MG6_1_115PL & MG6_1_116PL) -// End of MG6_1: -// Beginning of MG62: -#if (G6_1PL >= G6_2PL) || (G6_1PL == 0) -#define MG6_2_11PL ~(1 << 0) -#else -#define MG6_2_11PL 0xFFFF -#endif - -#if (G6_3PL >= G6_2PL) || (G6_3PL == 0) -#define MG6_2_13PL ~(1 << 2) -#else -#define MG6_2_13PL 0xFFFF -#endif - -#if (G6_4PL >= G6_2PL) || (G6_4PL == 0) -#define MG6_2_14PL ~(1 << 3) -#else -#define MG6_2_14PL 0xFFFF -#endif - -#if (G6_5PL >= G6_2PL) || (G6_5PL == 0) -#define MG6_2_15PL ~(1 << 4) -#else -#define MG6_2_15PL 0xFFFF -#endif - -#if (G6_6PL >= G6_2PL) || (G6_6PL == 0) -#define MG6_2_16PL ~(1 << 5) -#else -#define MG6_2_16PL 0xFFFF -#endif - -#if (G6_7PL >= G6_2PL) || (G6_7PL == 0) -#define MG6_2_17PL ~(1 << 6) -#else -#define MG6_2_17PL 0xFFFF -#endif - -#if (G6_8PL >= G6_2PL) || (G6_8PL == 0) -#define MG6_2_18PL ~(1 << 7) -#else -#define MG6_2_18PL 0xFFFF -#endif - -#if (G6_9PL >= G6_2PL) || (G6_9PL == 0) -#define MG6_2_19PL ~(1 << 8) -#else -#define MG6_2_19PL 0xFFFF -#endif - -#if (G6_10PL >= G6_2PL) || (G6_10PL == 0) -#define MG6_2_110PL ~(1 << 9) -#else -#define MG6_2_110PL 0xFFFF -#endif - -#if (G6_11PL >= G6_2PL) || (G6_11PL == 0) -#define MG6_2_111PL ~(1 << 10) -#else -#define MG6_2_111PL 0xFFFF -#endif - -#if (G6_12PL >= G6_2PL) || (G6_12PL == 0) -#define MG6_2_112PL ~(1 << 11) -#else -#define MG6_2_112PL 0xFFFF -#endif - -#if (G6_13PL >= G6_2PL) || (G6_13PL == 0) -#define MG6_2_113PL ~(1 << 12) -#else -#define MG6_2_113PL 0xFFFF -#endif - -#if (G6_14PL >= G6_2PL) || (G6_14PL == 0) -#define MG6_2_114PL ~(1 << 13) -#else -#define MG6_2_114PL 0xFFFF -#endif - -#if (G6_15PL >= G6_2PL) || (G6_15PL == 0) -#define MG6_2_115PL ~(1 << 14) -#else -#define MG6_2_115PL 0xFFFF -#endif - -#if (G6_16PL >= G6_2PL) || (G6_16PL == 0) -#define MG6_2_116PL ~(1 << 15) -#else -#define MG6_2_116PL 0xFFFF -#endif - -#define MG6_2_12PL 0xFFFD -#define MG6_2 (MG6_2_11PL & MG6_2_12PL & MG6_2_13PL & MG6_2_14PL & \ - MG6_2_15PL & MG6_2_16PL & MG6_2_17PL & MG6_2_18PL & \ - MG6_2_19PL & MG6_2_110PL & MG6_2_111PL & MG6_2_112PL & \ - MG6_2_113PL & MG6_2_114PL & MG6_2_115PL & MG6_2_116PL) -// End of MG6_2: -// Beginning of MG63: -#if (G6_1PL >= G6_3PL) || (G6_1PL == 0) -#define MG6_3_11PL ~(1 << 0) -#else -#define MG6_3_11PL 0xFFFF -#endif - -#if (G6_2PL >= G6_3PL) || (G6_2PL == 0) -#define MG6_3_12PL ~(1 << 1) -#else -#define MG6_3_12PL 0xFFFF -#endif - -#if (G6_4PL >= G6_3PL) || (G6_4PL == 0) -#define MG6_3_14PL ~(1 << 3) -#else -#define MG6_3_14PL 0xFFFF -#endif - -#if (G6_5PL >= G6_3PL) || (G6_5PL == 0) -#define MG6_3_15PL ~(1 << 4) -#else -#define MG6_3_15PL 0xFFFF -#endif - -#if (G6_6PL >= G6_3PL) || (G6_6PL == 0) -#define MG6_3_16PL ~(1 << 5) -#else -#define MG6_3_16PL 0xFFFF -#endif - -#if (G6_7PL >= G6_3PL) || (G6_7PL == 0) -#define MG6_3_17PL ~(1 << 6) -#else -#define MG6_3_17PL 0xFFFF -#endif - -#if (G6_8PL >= G6_3PL) || (G6_8PL == 0) -#define MG6_3_18PL ~(1 << 7) -#else -#define MG6_3_18PL 0xFFFF -#endif - -#if (G6_9PL >= G6_3PL) || (G6_9PL == 0) -#define MG6_3_19PL ~(1 << 8) -#else -#define MG6_3_19PL 0xFFFF -#endif - -#if (G6_10PL >= G6_3PL) || (G6_10PL == 0) -#define MG6_3_110PL ~(1 << 9) -#else -#define MG6_3_110PL 0xFFFF -#endif - -#if (G6_11PL >= G6_3PL) || (G6_11PL == 0) -#define MG6_3_111PL ~(1 << 10) -#else -#define MG6_3_111PL 0xFFFF -#endif - -#if (G6_12PL >= G6_3PL) || (G6_12PL == 0) -#define MG6_3_112PL ~(1 << 11) -#else -#define MG6_3_112PL 0xFFFF -#endif - -#if (G6_13PL >= G6_3PL) || (G6_13PL == 0) -#define MG6_3_113PL ~(1 << 12) -#else -#define MG6_3_113PL 0xFFFF -#endif - -#if (G6_14PL >= G6_3PL) || (G6_14PL == 0) -#define MG6_3_114PL ~(1 << 13) -#else -#define MG6_3_114PL 0xFFFF -#endif - -#if (G6_15PL >= G6_3PL) || (G6_15PL == 0) -#define MG6_3_115PL ~(1 << 14) -#else -#define MG6_3_115PL 0xFFFF -#endif - -#if (G6_16PL >= G6_3PL) || (G6_16PL == 0) -#define MG6_3_116PL ~(1 << 15) -#else -#define MG6_3_116PL 0xFFFF -#endif - -#define MG6_3_13PL 0xFFFB -#define MG6_3 (MG6_3_11PL & MG6_3_12PL & MG6_3_13PL & MG6_3_14PL & \ - MG6_3_15PL & MG6_3_16PL & MG6_3_17PL & MG6_3_18PL & \ - MG6_3_19PL & MG6_3_110PL & MG6_3_111PL & MG6_3_112PL & \ - MG6_3_113PL & MG6_3_114PL & MG6_3_115PL & MG6_3_116PL) -// End of MG6_3: -// Beginning of MG64: -#if (G6_1PL >= G6_4PL) || (G6_1PL == 0) -#define MG6_4_11PL ~(1 << 0) -#else -#define MG6_4_11PL 0xFFFF -#endif - -#if (G6_2PL >= G6_4PL) || (G6_2PL == 0) -#define MG6_4_12PL ~(1 << 1) -#else -#define MG6_4_12PL 0xFFFF -#endif - -#if (G6_3PL >= G6_4PL) || (G6_3PL == 0) -#define MG6_4_13PL ~(1 << 2) -#else -#define MG6_4_13PL 0xFFFF -#endif - -#if (G6_5PL >= G6_4PL) || (G6_5PL == 0) -#define MG6_4_15PL ~(1 << 4) -#else -#define MG6_4_15PL 0xFFFF -#endif - -#if (G6_6PL >= G6_4PL) || (G6_6PL == 0) -#define MG6_4_16PL ~(1 << 5) -#else -#define MG6_4_16PL 0xFFFF -#endif - -#if (G6_7PL >= G6_4PL) || (G6_7PL == 0) -#define MG6_4_17PL ~(1 << 6) -#else -#define MG6_4_17PL 0xFFFF -#endif - -#if (G6_8PL >= G6_4PL) || (G6_8PL == 0) -#define MG6_4_18PL ~(1 << 7) -#else -#define MG6_4_18PL 0xFFFF -#endif - -#if (G6_9PL >= G6_4PL) || (G6_9PL == 0) -#define MG6_4_19PL ~(1 << 8) -#else -#define MG6_4_19PL 0xFFFF -#endif - -#if (G6_10PL >= G6_4PL) || (G6_10PL == 0) -#define MG6_4_110PL ~(1 << 9) -#else -#define MG6_4_110PL 0xFFFF -#endif - -#if (G6_11PL >= G6_4PL) || (G6_11PL == 0) -#define MG6_4_111PL ~(1 << 10) -#else -#define MG6_4_111PL 0xFFFF -#endif - -#if (G6_12PL >= G6_4PL) || (G6_12PL == 0) -#define MG6_4_112PL ~(1 << 11) -#else -#define MG6_4_112PL 0xFFFF -#endif - -#if (G6_13PL >= G6_4PL) || (G6_13PL == 0) -#define MG6_4_113PL ~(1 << 12) -#else -#define MG6_4_113PL 0xFFFF -#endif - -#if (G6_14PL >= G6_4PL) || (G6_14PL == 0) -#define MG6_4_114PL ~(1 << 13) -#else -#define MG6_4_114PL 0xFFFF -#endif - -#if (G6_15PL >= G6_4PL) || (G6_15PL == 0) -#define MG6_4_115PL ~(1 << 14) -#else -#define MG6_4_115PL 0xFFFF -#endif - -#if (G6_16PL >= G6_4PL) || (G6_16PL == 0) -#define MG6_4_116PL ~(1 << 15) -#else -#define MG6_4_116PL 0xFFFF -#endif - -#define MG6_4_14PL 0xFFF7 -#define MG6_4 (MG6_4_11PL & MG6_4_12PL & MG6_4_13PL & MG6_4_14PL & \ - MG6_4_15PL & MG6_4_16PL & MG6_4_17PL & MG6_4_18PL & \ - MG6_4_19PL & MG6_4_110PL & MG6_4_111PL & MG6_4_112PL & \ - MG6_4_113PL & MG6_4_114PL & MG6_4_115PL & MG6_4_116PL) -// End of MG6_4: -// Beginning of MG65: -#if (G6_1PL >= G6_5PL) || (G6_1PL == 0) -#define MG6_5_11PL ~(1 << 0) -#else -#define MG6_5_11PL 0xFFFF -#endif - -#if (G6_2PL >= G6_5PL) || (G6_2PL == 0) -#define MG6_5_12PL ~(1 << 1) -#else -#define MG6_5_12PL 0xFFFF -#endif - -#if (G6_3PL >= G6_5PL) || (G6_3PL == 0) -#define MG6_5_13PL ~(1 << 2) -#else -#define MG6_5_13PL 0xFFFF -#endif - -#if (G6_4PL >= G6_5PL) || (G6_4PL == 0) -#define MG6_5_14PL ~(1 << 3) -#else -#define MG6_5_14PL 0xFFFF -#endif - -#if (G6_6PL >= G6_5PL) || (G6_6PL == 0) -#define MG6_5_16PL ~(1 << 5) -#else -#define MG6_5_16PL 0xFFFF -#endif - -#if (G6_7PL >= G6_5PL) || (G6_7PL == 0) -#define MG6_5_17PL ~(1 << 6) -#else -#define MG6_5_17PL 0xFFFF -#endif - -#if (G6_8PL >= G6_5PL) || (G6_8PL == 0) -#define MG6_5_18PL ~(1 << 7) -#else -#define MG6_5_18PL 0xFFFF -#endif - -#if (G6_9PL >= G6_5PL) || (G6_9PL == 0) -#define MG6_5_19PL ~(1 << 8) -#else -#define MG6_5_19PL 0xFFFF -#endif - -#if (G6_10PL >= G6_5PL) || (G6_10PL == 0) -#define MG6_5_110PL ~(1 << 9) -#else -#define MG6_5_110PL 0xFFFF -#endif - -#if (G6_11PL >= G6_5PL) || (G6_11PL == 0) -#define MG6_5_111PL ~(1 << 10) -#else -#define MG6_5_111PL 0xFFFF -#endif - -#if (G6_12PL >= G6_5PL) || (G6_12PL == 0) -#define MG6_5_112PL ~(1 << 11) -#else -#define MG6_5_112PL 0xFFFF -#endif - -#if (G6_13PL >= G6_5PL) || (G6_13PL == 0) -#define MG6_5_113PL ~(1 << 12) -#else -#define MG6_5_113PL 0xFFFF -#endif - -#if (G6_14PL >= G6_5PL) || (G6_14PL == 0) -#define MG6_5_114PL ~(1 << 13) -#else -#define MG6_5_114PL 0xFFFF -#endif - -#if (G6_15PL >= G6_5PL) || (G6_15PL == 0) -#define MG6_5_115PL ~(1 << 14) -#else -#define MG6_5_115PL 0xFFFF -#endif - -#if (G6_16PL >= G6_5PL) || (G6_16PL == 0) -#define MG6_5_116PL ~(1 << 15) -#else -#define MG6_5_116PL 0xFFFF -#endif - -#define MG6_5_15PL 0xFFEF -#define MG6_5 (MG6_5_11PL & MG6_5_12PL & MG6_5_13PL & MG6_5_14PL & \ - MG6_5_15PL & MG6_5_16PL & MG6_5_17PL & MG6_5_18PL & \ - MG6_5_19PL & MG6_5_110PL & MG6_5_111PL & MG6_5_112PL & \ - MG6_5_113PL & MG6_5_114PL & MG6_5_115PL & MG6_5_116PL) -// End of MG6_5: -// Beginning of MG66: -#if (G6_1PL >= G6_6PL) || (G6_1PL == 0) -#define MG6_6_11PL ~(1 << 0) -#else -#define MG6_6_11PL 0xFFFF -#endif - -#if (G6_2PL >= G6_6PL) || (G6_2PL == 0) -#define MG6_6_12PL ~(1 << 1) -#else -#define MG6_6_12PL 0xFFFF -#endif - -#if (G6_3PL >= G6_6PL) || (G6_3PL == 0) -#define MG6_6_13PL ~(1 << 2) -#else -#define MG6_6_13PL 0xFFFF -#endif - -#if (G6_4PL >= G6_6PL) || (G6_4PL == 0) -#define MG6_6_14PL ~(1 << 3) -#else -#define MG6_6_14PL 0xFFFF -#endif - -#if (G6_5PL >= G6_6PL) || (G6_5PL == 0) -#define MG6_6_15PL ~(1 << 4) -#else -#define MG6_6_15PL 0xFFFF -#endif - -#if (G6_7PL >= G6_6PL) || (G6_7PL == 0) -#define MG6_6_17PL ~(1 << 6) -#else -#define MG6_6_17PL 0xFFFF -#endif - -#if (G6_8PL >= G6_6PL) || (G6_8PL == 0) -#define MG6_6_18PL ~(1 << 7) -#else -#define MG6_6_18PL 0xFFFF -#endif - -#if (G6_9PL >= G6_6PL) || (G6_9PL == 0) -#define MG6_6_19PL ~(1 << 8) -#else -#define MG6_6_19PL 0xFFFF -#endif - -#if (G6_10PL >= G6_6PL) || (G6_10PL == 0) -#define MG6_6_110PL ~(1 << 9) -#else -#define MG6_6_110PL 0xFFFF -#endif - -#if (G6_11PL >= G6_6PL) || (G6_11PL == 0) -#define MG6_6_111PL ~(1 << 10) -#else -#define MG6_6_111PL 0xFFFF -#endif - -#if (G6_12PL >= G6_6PL) || (G6_12PL == 0) -#define MG6_6_112PL ~(1 << 11) -#else -#define MG6_6_112PL 0xFFFF -#endif - -#if (G6_13PL >= G6_6PL) || (G6_13PL == 0) -#define MG6_6_113PL ~(1 << 12) -#else -#define MG6_6_113PL 0xFFFF -#endif - -#if (G6_14PL >= G6_6PL) || (G6_14PL == 0) -#define MG6_6_114PL ~(1 << 13) -#else -#define MG6_6_114PL 0xFFFF -#endif - -#if (G6_15PL >= G6_6PL) || (G6_15PL == 0) -#define MG6_6_115PL ~(1 << 14) -#else -#define MG6_6_115PL 0xFFFF -#endif - -#if (G6_16PL >= G6_6PL) || (G6_16PL == 0) -#define MG6_6_116PL ~(1 << 15) -#else -#define MG6_6_116PL 0xFFFF -#endif - -#define MG6_6_16PL 0xFFDF -#define MG6_6 (MG6_6_11PL & MG6_6_12PL & MG6_6_13PL & MG6_6_14PL & \ - MG6_6_15PL & MG6_6_16PL & MG6_6_17PL & MG6_6_18PL & \ - MG6_6_19PL & MG6_6_110PL & MG6_6_111PL & MG6_6_112PL & \ - MG6_6_113PL & MG6_6_114PL & MG6_6_115PL & MG6_6_116PL) -// End of MG6_6: -// Beginning of MG67: -#if (G6_1PL >= G6_7PL) || (G6_1PL == 0) -#define MG6_7_11PL ~(1 << 0) -#else -#define MG6_7_11PL 0xFFFF -#endif - -#if (G6_2PL >= G6_7PL) || (G6_2PL == 0) -#define MG6_7_12PL ~(1 << 1) -#else -#define MG6_7_12PL 0xFFFF -#endif - -#if (G6_3PL >= G6_7PL) || (G6_3PL == 0) -#define MG6_7_13PL ~(1 << 2) -#else -#define MG6_7_13PL 0xFFFF -#endif - -#if (G6_4PL >= G6_7PL) || (G6_4PL == 0) -#define MG6_7_14PL ~(1 << 3) -#else -#define MG6_7_14PL 0xFFFF -#endif - -#if (G6_5PL >= G6_7PL) || (G6_5PL == 0) -#define MG6_7_15PL ~(1 << 4) -#else -#define MG6_7_15PL 0xFFFF -#endif - -#if (G6_6PL >= G6_7PL) || (G6_6PL == 0) -#define MG6_7_16PL ~(1 << 5) -#else -#define MG6_7_16PL 0xFFFF -#endif - -#if (G6_8PL >= G6_7PL) || (G6_8PL == 0) -#define MG6_7_18PL ~(1 << 7) -#else -#define MG6_7_18PL 0xFFFF -#endif - -#if (G6_9PL >= G6_7PL) || (G6_9PL == 0) -#define MG6_7_19PL ~(1 << 8) -#else -#define MG6_7_19PL 0xFFFF -#endif - -#if (G6_10PL >= G6_7PL) || (G6_10PL == 0) -#define MG6_7_110PL ~(1 << 9) -#else -#define MG6_7_110PL 0xFFFF -#endif - -#if (G6_11PL >= G6_7PL) || (G6_11PL == 0) -#define MG6_7_111PL ~(1 << 10) -#else -#define MG6_7_111PL 0xFFFF -#endif - -#if (G6_12PL >= G6_7PL) || (G6_12PL == 0) -#define MG6_7_112PL ~(1 << 11) -#else -#define MG6_7_112PL 0xFFFF -#endif - -#if (G6_13PL >= G6_7PL) || (G6_13PL == 0) -#define MG6_7_113PL ~(1 << 12) -#else -#define MG6_7_113PL 0xFFFF -#endif - -#if (G6_14PL >= G6_7PL) || (G6_14PL == 0) -#define MG6_7_114PL ~(1 << 13) -#else -#define MG6_7_114PL 0xFFFF -#endif - -#if (G6_15PL >= G6_7PL) || (G6_15PL == 0) -#define MG6_7_115PL ~(1 << 14) -#else -#define MG6_7_115PL 0xFFFF -#endif - -#if (G6_16PL >= G6_7PL) || (G6_16PL == 0) -#define MG6_7_116PL ~(1 << 15) -#else -#define MG6_7_116PL 0xFFFF -#endif - -#define MG6_7_17PL 0xFFBF -#define MG6_7 (MG6_7_11PL & MG6_7_12PL & MG6_7_13PL & MG6_7_14PL & \ - MG6_7_15PL & MG6_7_16PL & MG6_7_17PL & MG6_7_18PL & \ - MG6_7_19PL & MG6_7_110PL & MG6_7_111PL & MG6_7_112PL & \ - MG6_7_113PL & MG6_7_114PL & MG6_7_115PL & MG6_7_116PL) -// End of MG6_7: -// Beginning of MG68: -#if (G6_1PL >= G6_8PL) || (G6_1PL == 0) -#define MG6_8_11PL ~(1 << 0) -#else -#define MG6_8_11PL 0xFFFF -#endif - -#if (G6_2PL >= G6_8PL) || (G6_2PL == 0) -#define MG6_8_12PL ~(1 << 1) -#else -#define MG6_8_12PL 0xFFFF -#endif - -#if (G6_3PL >= G6_8PL) || (G6_3PL == 0) -#define MG6_8_13PL ~(1 << 2) -#else -#define MG6_8_13PL 0xFFFF -#endif - -#if (G6_4PL >= G6_8PL) || (G6_4PL == 0) -#define MG6_8_14PL ~(1 << 3) -#else -#define MG6_8_14PL 0xFFFF -#endif - -#if (G6_5PL >= G6_8PL) || (G6_5PL == 0) -#define MG6_8_15PL ~(1 << 4) -#else -#define MG6_8_15PL 0xFFFF -#endif - -#if (G6_6PL >= G6_8PL) || (G6_6PL == 0) -#define MG6_8_16PL ~(1 << 5) -#else -#define MG6_8_16PL 0xFFFF -#endif - -#if (G6_7PL >= G6_8PL) || (G6_7PL == 0) -#define MG6_8_17PL ~(1 << 6) -#else -#define MG6_8_17PL 0xFFFF -#endif - -#if (G6_9PL >= G6_8PL) || (G6_9PL == 0) -#define MG6_8_19PL ~(1 << 8) -#else -#define MG6_8_19PL 0xFFFF -#endif - -#if (G6_10PL >= G6_8PL) || (G6_10PL == 0) -#define MG6_8_110PL ~(1 << 9) -#else -#define MG6_8_110PL 0xFFFF -#endif - -#if (G6_11PL >= G6_8PL) || (G6_11PL == 0) -#define MG6_8_111PL ~(1 << 10) -#else -#define MG6_8_111PL 0xFFFF -#endif - -#if (G6_12PL >= G6_8PL) || (G6_12PL == 0) -#define MG6_8_112PL ~(1 << 11) -#else -#define MG6_8_112PL 0xFFFF -#endif - -#if (G6_13PL >= G6_8PL) || (G6_13PL == 0) -#define MG6_8_113PL ~(1 << 12) -#else -#define MG6_8_113PL 0xFFFF -#endif - -#if (G6_14PL >= G6_8PL) || (G6_14PL == 0) -#define MG6_8_114PL ~(1 << 13) -#else -#define MG6_8_114PL 0xFFFF -#endif - -#if (G6_15PL >= G6_8PL) || (G6_15PL == 0) -#define MG6_8_115PL ~(1 << 14) -#else -#define MG6_8_115PL 0xFFFF -#endif - -#if (G6_16PL >= G6_8PL) || (G6_16PL == 0) -#define MG6_8_116PL ~(1 << 15) -#else -#define MG6_8_116PL 0xFFFF -#endif - -#define MG6_8_18PL 0xFF7F -#define MG6_8 (MG6_8_11PL & MG6_8_12PL & MG6_8_13PL & MG6_8_14PL & \ - MG6_8_15PL & MG6_8_16PL & MG6_8_17PL & MG6_8_18PL & \ - MG6_8_19PL & MG6_8_110PL & MG6_8_111PL & MG6_8_112PL & \ - MG6_8_113PL & MG6_8_114PL & MG6_8_115PL & MG6_8_116PL) -// End of MG6_8: -// Beginning of MG69: -#if (G6_1PL >= G6_9PL) || (G6_1PL == 0) -#define MG6_9_11PL ~(1 << 0) -#else -#define MG6_9_11PL 0xFFFF -#endif - -#if (G6_2PL >= G6_9PL) || (G6_2PL == 0) -#define MG6_9_12PL ~(1 << 1) -#else -#define MG6_9_12PL 0xFFFF -#endif - -#if (G6_3PL >= G6_9PL) || (G6_3PL == 0) -#define MG6_9_13PL ~(1 << 2) -#else -#define MG6_9_13PL 0xFFFF -#endif - -#if (G6_4PL >= G6_9PL) || (G6_4PL == 0) -#define MG6_9_14PL ~(1 << 3) -#else -#define MG6_9_14PL 0xFFFF -#endif - -#if (G6_5PL >= G6_9PL) || (G6_5PL == 0) -#define MG6_9_15PL ~(1 << 4) -#else -#define MG6_9_15PL 0xFFFF -#endif - -#if (G6_6PL >= G6_9PL) || (G6_6PL == 0) -#define MG6_9_16PL ~(1 << 5) -#else -#define MG6_9_16PL 0xFFFF -#endif - -#if (G6_7PL >= G6_9PL) || (G6_7PL == 0) -#define MG6_9_17PL ~(1 << 6) -#else -#define MG6_9_17PL 0xFFFF -#endif - -#if (G6_8PL >= G6_9PL) || (G6_8PL == 0) -#define MG6_9_18PL ~(1 << 7) -#else -#define MG6_9_18PL 0xFFFF -#endif - -#if (G6_10PL >= G6_9PL) || (G6_10PL == 0) -#define MG6_9_110PL ~(1 << 9) -#else -#define MG6_9_110PL 0xFFFF -#endif - -#if (G6_11PL >= G6_9PL) || (G6_11PL == 0) -#define MG6_9_111PL ~(1 << 10) -#else -#define MG6_9_111PL 0xFFFF -#endif - -#if (G6_12PL >= G6_9PL) || (G6_12PL == 0) -#define MG6_9_112PL ~(1 << 11) -#else -#define MG6_9_112PL 0xFFFF -#endif - -#if (G6_13PL >= G6_9PL) || (G6_13PL == 0) -#define MG6_9_113PL ~(1 << 12) -#else -#define MG6_9_113PL 0xFFFF -#endif - -#if (G6_14PL >= G6_9PL) || (G6_14PL == 0) -#define MG6_9_114PL ~(1 << 13) -#else -#define MG6_9_114PL 0xFFFF -#endif - -#if (G6_15PL >= G6_9PL) || (G6_15PL == 0) -#define MG6_9_115PL ~(1 << 14) -#else -#define MG6_9_115PL 0xFFFF -#endif - -#if (G6_16PL >= G6_9PL) || (G6_16PL == 0) -#define MG6_9_116PL ~(1 << 15) -#else -#define MG6_9_116PL 0xFFFF -#endif - -#define MG6_9_19PL 0xFEFF -#define MG6_9 (MG6_9_11PL & MG6_9_12PL & MG6_9_13PL & MG6_9_14PL & \ - MG6_9_15PL & MG6_9_16PL & MG6_9_17PL & MG6_9_18PL & \ - MG6_9_19PL & MG6_9_110PL & MG6_9_111PL & MG6_9_112PL & \ - MG6_9_113PL & MG6_9_114PL & MG6_9_115PL & MG6_9_116PL) -// End of MG6_9: -// Beginning of MG610: -#if (G6_1PL >= G6_10PL) || (G6_1PL == 0) -#define MG6_10_11PL ~(1 << 0) -#else -#define MG6_10_11PL 0xFFFF -#endif - -#if (G6_2PL >= G6_10PL) || (G6_2PL == 0) -#define MG6_10_12PL ~(1 << 1) -#else -#define MG6_10_12PL 0xFFFF -#endif - -#if (G6_3PL >= G6_10PL) || (G6_3PL == 0) -#define MG6_10_13PL ~(1 << 2) -#else -#define MG6_10_13PL 0xFFFF -#endif - -#if (G6_4PL >= G6_10PL) || (G6_4PL == 0) -#define MG6_10_14PL ~(1 << 3) -#else -#define MG6_10_14PL 0xFFFF -#endif - -#if (G6_5PL >= G6_10PL) || (G6_5PL == 0) -#define MG6_10_15PL ~(1 << 4) -#else -#define MG6_10_15PL 0xFFFF -#endif - -#if (G6_6PL >= G6_10PL) || (G6_6PL == 0) -#define MG6_10_16PL ~(1 << 5) -#else -#define MG6_10_16PL 0xFFFF -#endif - -#if (G6_7PL >= G6_10PL) || (G6_7PL == 0) -#define MG6_10_17PL ~(1 << 6) -#else -#define MG6_10_17PL 0xFFFF -#endif - -#if (G6_8PL >= G6_10PL) || (G6_8PL == 0) -#define MG6_10_18PL ~(1 << 7) -#else -#define MG6_10_18PL 0xFFFF -#endif - -#if (G6_9PL >= G6_10PL) || (G6_9PL == 0) -#define MG6_10_19PL ~(1 << 8) -#else -#define MG6_10_19PL 0xFFFF -#endif - -#if (G6_11PL >= G6_10PL) || (G6_11PL == 0) -#define MG6_10_111PL ~(1 << 10) -#else -#define MG6_10_111PL 0xFFFF -#endif - -#if (G6_12PL >= G6_10PL) || (G6_12PL == 0) -#define MG6_10_112PL ~(1 << 11) -#else -#define MG6_10_112PL 0xFFFF -#endif - -#if (G6_13PL >= G6_10PL) || (G6_13PL == 0) -#define MG6_10_113PL ~(1 << 12) -#else -#define MG6_10_113PL 0xFFFF -#endif - -#if (G6_14PL >= G6_10PL) || (G6_14PL == 0) -#define MG6_10_114PL ~(1 << 13) -#else -#define MG6_10_114PL 0xFFFF -#endif - -#if (G6_15PL >= G6_10PL) || (G6_15PL == 0) -#define MG6_10_115PL ~(1 << 14) -#else -#define MG6_10_115PL 0xFFFF -#endif - -#if (G6_16PL >= G6_10PL) || (G6_16PL == 0) -#define MG6_10_116PL ~(1 << 15) -#else -#define MG6_10_116PL 0xFFFF -#endif - -#define MG6_10_110PL 0xFDFF -#define MG6_10 (MG6_10_11PL & MG6_10_12PL & MG6_10_13PL & MG6_10_14PL & \ - MG6_10_15PL & MG6_10_16PL & MG6_10_17PL & MG6_10_18PL & \ - MG6_10_19PL & MG6_10_110PL & MG6_10_111PL & MG6_10_112PL & \ - MG6_10_113PL & MG6_10_114PL & MG6_10_115PL & MG6_10_116PL) -// End of MG6_10: -// Beginning of MG611: -#if (G6_1PL >= G6_11PL) || (G6_1PL == 0) -#define MG6_11_11PL ~(1 << 0) -#else -#define MG6_11_11PL 0xFFFF -#endif - -#if (G6_2PL >= G6_11PL) || (G6_2PL == 0) -#define MG6_11_12PL ~(1 << 1) -#else -#define MG6_11_12PL 0xFFFF -#endif - -#if (G6_3PL >= G6_11PL) || (G6_3PL == 0) -#define MG6_11_13PL ~(1 << 2) -#else -#define MG6_11_13PL 0xFFFF -#endif - -#if (G6_4PL >= G6_11PL) || (G6_4PL == 0) -#define MG6_11_14PL ~(1 << 3) -#else -#define MG6_11_14PL 0xFFFF -#endif - -#if (G6_5PL >= G6_11PL) || (G6_5PL == 0) -#define MG6_11_15PL ~(1 << 4) -#else -#define MG6_11_15PL 0xFFFF -#endif - -#if (G6_6PL >= G6_11PL) || (G6_6PL == 0) -#define MG6_11_16PL ~(1 << 5) -#else -#define MG6_11_16PL 0xFFFF -#endif - -#if (G6_7PL >= G6_11PL) || (G6_7PL == 0) -#define MG6_11_17PL ~(1 << 6) -#else -#define MG6_11_17PL 0xFFFF -#endif - -#if (G6_8PL >= G6_11PL) || (G6_8PL == 0) -#define MG6_11_18PL ~(1 << 7) -#else -#define MG6_11_18PL 0xFFFF -#endif - -#if (G6_9PL >= G6_11PL) || (G6_9PL == 0) -#define MG6_11_19PL ~(1 << 8) -#else -#define MG6_11_19PL 0xFFFF -#endif - -#if (G6_10PL >= G6_11PL) || (G6_10PL == 0) -#define MG6_11_110PL ~(1 << 9) -#else -#define MG6_11_110PL 0xFFFF -#endif - -#if (G6_12PL >= G6_11PL) || (G6_12PL == 0) -#define MG6_11_112PL ~(1 << 11) -#else -#define MG6_11_112PL 0xFFFF -#endif - -#if (G6_13PL >= G6_11PL) || (G6_13PL == 0) -#define MG6_11_113PL ~(1 << 12) -#else -#define MG6_11_113PL 0xFFFF -#endif - -#if (G6_14PL >= G6_11PL) || (G6_14PL == 0) -#define MG6_11_114PL ~(1 << 13) -#else -#define MG6_11_114PL 0xFFFF -#endif - -#if (G6_15PL >= G6_11PL) || (G6_15PL == 0) -#define MG6_11_115PL ~(1 << 14) -#else -#define MG6_11_115PL 0xFFFF -#endif - -#if (G6_16PL >= G6_11PL) || (G6_16PL == 0) -#define MG6_11_116PL ~(1 << 15) -#else -#define MG6_11_116PL 0xFFFF -#endif - -#define MG6_11_111PL 0xFBFF -#define MG6_11 (MG6_11_11PL & MG6_11_12PL & MG6_11_13PL & MG6_11_14PL & \ - MG6_11_15PL & MG6_11_16PL & MG6_11_17PL & MG6_11_18PL & \ - MG6_11_19PL & MG6_11_110PL & MG6_11_111PL & MG6_11_112PL & \ - MG6_11_113PL & MG6_11_114PL & MG6_11_115PL & MG6_11_116PL) -// End of MG6_11: -// Beginning of MG612: -#if (G6_1PL >= G6_12PL) || (G6_1PL == 0) -#define MG6_12_11PL ~(1 << 0) -#else -#define MG6_12_11PL 0xFFFF -#endif - -#if (G6_2PL >= G6_12PL) || (G6_2PL == 0) -#define MG6_12_12PL ~(1 << 1) -#else -#define MG6_12_12PL 0xFFFF -#endif - -#if (G6_3PL >= G6_12PL) || (G6_3PL == 0) -#define MG6_12_13PL ~(1 << 2) -#else -#define MG6_12_13PL 0xFFFF -#endif - -#if (G6_4PL >= G6_12PL) || (G6_4PL == 0) -#define MG6_12_14PL ~(1 << 3) -#else -#define MG6_12_14PL 0xFFFF -#endif - -#if (G6_5PL >= G6_12PL) || (G6_5PL == 0) -#define MG6_12_15PL ~(1 << 4) -#else -#define MG6_12_15PL 0xFFFF -#endif - -#if (G6_6PL >= G6_12PL) || (G6_6PL == 0) -#define MG6_12_16PL ~(1 << 5) -#else -#define MG6_12_16PL 0xFFFF -#endif - -#if (G6_7PL >= G6_12PL) || (G6_7PL == 0) -#define MG6_12_17PL ~(1 << 6) -#else -#define MG6_12_17PL 0xFFFF -#endif - -#if (G6_8PL >= G6_12PL) || (G6_8PL == 0) -#define MG6_12_18PL ~(1 << 7) -#else -#define MG6_12_18PL 0xFFFF -#endif - -#if (G6_9PL >= G6_12PL) || (G6_9PL == 0) -#define MG6_12_19PL ~(1 << 8) -#else -#define MG6_12_19PL 0xFFFF -#endif - -#if (G6_10PL >= G6_12PL) || (G6_10PL == 0) -#define MG6_12_110PL ~(1 << 9) -#else -#define MG6_12_110PL 0xFFFF -#endif - -#if (G6_11PL >= G6_12PL) || (G6_11PL == 0) -#define MG6_12_111PL ~(1 << 10) -#else -#define MG6_12_111PL 0xFFFF -#endif - -#if (G6_13PL >= G6_12PL) || (G6_13PL == 0) -#define MG6_12_113PL ~(1 << 12) -#else -#define MG6_12_113PL 0xFFFF -#endif - -#if (G6_14PL >= G6_12PL) || (G6_14PL == 0) -#define MG6_12_114PL ~(1 << 13) -#else -#define MG6_12_114PL 0xFFFF -#endif - -#if (G6_15PL >= G6_12PL) || (G6_15PL == 0) -#define MG6_12_115PL ~(1 << 14) -#else -#define MG6_12_115PL 0xFFFF -#endif - -#if (G6_16PL >= G6_12PL) || (G6_16PL == 0) -#define MG6_12_116PL ~(1 << 15) -#else -#define MG6_12_116PL 0xFFFF -#endif - -#define MG6_12_112PL 0xF7FF -#define MG6_12 (MG6_12_11PL & MG6_12_12PL & MG6_12_13PL & MG6_12_14PL & \ - MG6_12_15PL & MG6_12_16PL & MG6_12_17PL & MG6_12_18PL & \ - MG6_12_19PL & MG6_12_110PL & MG6_12_111PL & MG6_12_112PL & \ - MG6_12_113PL & MG6_12_114PL & MG6_12_115PL & MG6_12_116PL) -// End of MG6_12: -// Beginning of MG613: -#if (G6_1PL >= G6_13PL) || (G6_1PL == 0) -#define MG6_13_11PL ~(1 << 0) -#else -#define MG6_13_11PL 0xFFFF -#endif - -#if (G6_2PL >= G6_13PL) || (G6_2PL == 0) -#define MG6_13_12PL ~(1 << 1) -#else -#define MG6_13_12PL 0xFFFF -#endif - -#if (G6_3PL >= G6_13PL) || (G6_3PL == 0) -#define MG6_13_13PL ~(1 << 2) -#else -#define MG6_13_13PL 0xFFFF -#endif - -#if (G6_4PL >= G6_13PL) || (G6_4PL == 0) -#define MG6_13_14PL ~(1 << 3) -#else -#define MG6_13_14PL 0xFFFF -#endif - -#if (G6_5PL >= G6_13PL) || (G6_5PL == 0) -#define MG6_13_15PL ~(1 << 4) -#else -#define MG6_13_15PL 0xFFFF -#endif - -#if (G6_6PL >= G6_13PL) || (G6_6PL == 0) -#define MG6_13_16PL ~(1 << 5) -#else -#define MG6_13_16PL 0xFFFF -#endif - -#if (G6_7PL >= G6_13PL) || (G6_7PL == 0) -#define MG6_13_17PL ~(1 << 6) -#else -#define MG6_13_17PL 0xFFFF -#endif - -#if (G6_8PL >= G6_13PL) || (G6_8PL == 0) -#define MG6_13_18PL ~(1 << 7) -#else -#define MG6_13_18PL 0xFFFF -#endif - -#if (G6_9PL >= G6_13PL) || (G6_9PL == 0) -#define MG6_13_19PL ~(1 << 8) -#else -#define MG6_13_19PL 0xFFFF -#endif - -#if (G6_10PL >= G6_13PL) || (G6_10PL == 0) -#define MG6_13_110PL ~(1 << 9) -#else -#define MG6_13_110PL 0xFFFF -#endif - -#if (G6_11PL >= G6_13PL) || (G6_11PL == 0) -#define MG6_13_111PL ~(1 << 10) -#else -#define MG6_13_111PL 0xFFFF -#endif - -#if (G6_12PL >= G6_13PL) || (G6_12PL == 0) -#define MG6_13_112PL ~(1 << 11) -#else -#define MG6_13_112PL 0xFFFF -#endif - -#if (G6_14PL >= G6_13PL) || (G6_14PL == 0) -#define MG6_13_114PL ~(1 << 13) -#else -#define MG6_13_114PL 0xFFFF -#endif - -#if (G6_15PL >= G6_13PL) || (G6_15PL == 0) -#define MG6_13_115PL ~(1 << 14) -#else -#define MG6_13_115PL 0xFFFF -#endif - -#if (G6_16PL >= G6_13PL) || (G6_16PL == 0) -#define MG6_13_116PL ~(1 << 15) -#else -#define MG6_13_116PL 0xFFFF -#endif - -#define MG6_13_113PL 0xEFFF -#define MG6_13 (MG6_13_11PL & MG6_13_12PL & MG6_13_13PL & MG6_13_14PL & \ - MG6_13_15PL & MG6_13_16PL & MG6_13_17PL & MG6_13_18PL & \ - MG6_13_19PL & MG6_13_110PL & MG6_13_111PL & MG6_13_112PL & \ - MG6_13_113PL & MG6_13_114PL & MG6_13_115PL & MG6_13_116PL) -// End of MG6_13: -// Beginning of MG614: -#if (G6_1PL >= G6_14PL) || (G6_1PL == 0) -#define MG6_14_11PL ~(1 << 0) -#else -#define MG6_14_11PL 0xFFFF -#endif - -#if (G6_2PL >= G6_14PL) || (G6_2PL == 0) -#define MG6_14_12PL ~(1 << 1) -#else -#define MG6_14_12PL 0xFFFF -#endif - -#if (G6_3PL >= G6_14PL) || (G6_3PL == 0) -#define MG6_14_13PL ~(1 << 2) -#else -#define MG6_14_13PL 0xFFFF -#endif - -#if (G6_4PL >= G6_14PL) || (G6_4PL == 0) -#define MG6_14_14PL ~(1 << 3) -#else -#define MG6_14_14PL 0xFFFF -#endif - -#if (G6_5PL >= G6_14PL) || (G6_5PL == 0) -#define MG6_14_15PL ~(1 << 4) -#else -#define MG6_14_15PL 0xFFFF -#endif - -#if (G6_6PL >= G6_14PL) || (G6_6PL == 0) -#define MG6_14_16PL ~(1 << 5) -#else -#define MG6_14_16PL 0xFFFF -#endif - -#if (G6_7PL >= G6_14PL) || (G6_7PL == 0) -#define MG6_14_17PL ~(1 << 6) -#else -#define MG6_14_17PL 0xFFFF -#endif - -#if (G6_8PL >= G6_14PL) || (G6_8PL == 0) -#define MG6_14_18PL ~(1 << 7) -#else -#define MG6_14_18PL 0xFFFF -#endif - -#if (G6_9PL >= G6_14PL) || (G6_9PL == 0) -#define MG6_14_19PL ~(1 << 8) -#else -#define MG6_14_19PL 0xFFFF -#endif - -#if (G6_10PL >= G6_14PL) || (G6_10PL == 0) -#define MG6_14_110PL ~(1 << 9) -#else -#define MG6_14_110PL 0xFFFF -#endif - -#if (G6_11PL >= G6_14PL) || (G6_11PL == 0) -#define MG6_14_111PL ~(1 << 10) -#else -#define MG6_14_111PL 0xFFFF -#endif - -#if (G6_12PL >= G6_14PL) || (G6_12PL == 0) -#define MG6_14_112PL ~(1 << 11) -#else -#define MG6_14_112PL 0xFFFF -#endif - -#if (G6_13PL >= G6_14PL) || (G6_13PL == 0) -#define MG6_14_113PL ~(1 << 12) -#else -#define MG6_14_113PL 0xFFFF -#endif - -#if (G6_15PL >= G6_14PL) || (G6_15PL == 0) -#define MG6_14_115PL ~(1 << 14) -#else -#define MG6_14_115PL 0xFFFF -#endif - -#if (G6_16PL >= G6_14PL) || (G6_16PL == 0) -#define MG6_14_116PL ~(1 << 15) -#else -#define MG6_14_116PL 0xFFFF -#endif - -#define MG6_14_114PL 0xDFFF -#define MG6_14 (MG6_14_11PL & MG6_14_12PL & MG6_14_13PL & MG6_14_14PL & \ - MG6_14_15PL & MG6_14_16PL & MG6_14_17PL & MG6_14_18PL & \ - MG6_14_19PL & MG6_14_110PL & MG6_14_111PL & MG6_14_112PL & \ - MG6_14_113PL & MG6_14_114PL & MG6_14_115PL & MG6_14_116PL) -// End of MG6_14: -// Beginning of MG615: -#if (G6_1PL >= G6_15PL) || (G6_1PL == 0) -#define MG6_15_11PL ~(1 << 0) -#else -#define MG6_15_11PL 0xFFFF -#endif - -#if (G6_2PL >= G6_15PL) || (G6_2PL == 0) -#define MG6_15_12PL ~(1 << 1) -#else -#define MG6_15_12PL 0xFFFF -#endif - -#if (G6_3PL >= G6_15PL) || (G6_3PL == 0) -#define MG6_15_13PL ~(1 << 2) -#else -#define MG6_15_13PL 0xFFFF -#endif - -#if (G6_4PL >= G6_15PL) || (G6_4PL == 0) -#define MG6_15_14PL ~(1 << 3) -#else -#define MG6_15_14PL 0xFFFF -#endif - -#if (G6_5PL >= G6_15PL) || (G6_5PL == 0) -#define MG6_15_15PL ~(1 << 4) -#else -#define MG6_15_15PL 0xFFFF -#endif - -#if (G6_6PL >= G6_15PL) || (G6_6PL == 0) -#define MG6_15_16PL ~(1 << 5) -#else -#define MG6_15_16PL 0xFFFF -#endif - -#if (G6_7PL >= G6_15PL) || (G6_7PL == 0) -#define MG6_15_17PL ~(1 << 6) -#else -#define MG6_15_17PL 0xFFFF -#endif - -#if (G6_8PL >= G6_15PL) || (G6_8PL == 0) -#define MG6_15_18PL ~(1 << 7) -#else -#define MG6_15_18PL 0xFFFF -#endif - -#if (G6_9PL >= G6_15PL) || (G6_9PL == 0) -#define MG6_15_19PL ~(1 << 8) -#else -#define MG6_15_19PL 0xFFFF -#endif - -#if (G6_10PL >= G6_15PL) || (G6_10PL == 0) -#define MG6_15_110PL ~(1 << 9) -#else -#define MG6_15_110PL 0xFFFF -#endif - -#if (G6_11PL >= G6_15PL) || (G6_11PL == 0) -#define MG6_15_111PL ~(1 << 10) -#else -#define MG6_15_111PL 0xFFFF -#endif - -#if (G6_12PL >= G6_15PL) || (G6_12PL == 0) -#define MG6_15_112PL ~(1 << 11) -#else -#define MG6_15_112PL 0xFFFF -#endif - -#if (G6_13PL >= G6_15PL) || (G6_13PL == 0) -#define MG6_15_113PL ~(1 << 12) -#else -#define MG6_15_113PL 0xFFFF -#endif - -#if (G6_14PL >= G6_15PL) || (G6_14PL == 0) -#define MG6_15_114PL ~(1 << 13) -#else -#define MG6_15_114PL 0xFFFF -#endif - -#if (G6_16PL >= G6_15PL) || (G6_16PL == 0) -#define MG6_15_116PL ~(1 << 15) -#else -#define MG6_15_116PL 0xFFFF -#endif - -#define MG6_15_115PL 0xBFFF -#define MG6_15 (MG6_15_11PL & MG6_15_12PL & MG6_15_13PL & MG6_15_14PL & \ - MG6_15_15PL & MG6_15_16PL & MG6_15_17PL & MG6_15_18PL & \ - MG6_15_19PL & MG6_15_110PL & MG6_15_111PL & MG6_15_112PL & \ - MG6_15_113PL & MG6_15_114PL & MG6_15_115PL & MG6_15_116PL) -// End of MG6_15: -// Beginning of MG616: -#if (G6_1PL >= G6_16PL) || (G6_1PL == 0) -#define MG6_16_11PL ~(1 << 0) -#else -#define MG6_16_11PL 0xFFFF -#endif - -#if (G6_2PL >= G6_16PL) || (G6_2PL == 0) -#define MG6_16_12PL ~(1 << 1) -#else -#define MG6_16_12PL 0xFFFF -#endif - -#if (G6_3PL >= G6_16PL) || (G6_3PL == 0) -#define MG6_16_13PL ~(1 << 2) -#else -#define MG6_16_13PL 0xFFFF -#endif - -#if (G6_4PL >= G6_16PL) || (G6_4PL == 0) -#define MG6_16_14PL ~(1 << 3) -#else -#define MG6_16_14PL 0xFFFF -#endif - -#if (G6_5PL >= G6_16PL) || (G6_5PL == 0) -#define MG6_16_15PL ~(1 << 4) -#else -#define MG6_16_15PL 0xFFFF -#endif - -#if (G6_6PL >= G6_16PL) || (G6_6PL == 0) -#define MG6_16_16PL ~(1 << 5) -#else -#define MG6_16_16PL 0xFFFF -#endif - -#if (G6_7PL >= G6_16PL) || (G6_7PL == 0) -#define MG6_16_17PL ~(1 << 6) -#else -#define MG6_16_17PL 0xFFFF -#endif - -#if (G6_8PL >= G6_16PL) || (G6_8PL == 0) -#define MG6_16_18PL ~(1 << 7) -#else -#define MG6_16_18PL 0xFFFF -#endif - -#if (G6_9PL >= G6_16PL) || (G6_9PL == 0) -#define MG6_16_19PL ~(1 << 8) -#else -#define MG6_16_19PL 0xFFFF -#endif - -#if (G6_10PL >= G6_16PL) || (G6_10PL == 0) -#define MG6_16_110PL ~(1 << 9) -#else -#define MG6_16_110PL 0xFFFF -#endif - -#if (G6_11PL >= G6_16PL) || (G6_11PL == 0) -#define MG6_16_111PL ~(1 << 10) -#else -#define MG6_16_111PL 0xFFFF -#endif - -#if (G6_12PL >= G6_16PL) || (G6_12PL == 0) -#define MG6_16_112PL ~(1 << 11) -#else -#define MG6_16_112PL 0xFFFF -#endif - -#if (G6_13PL >= G6_16PL) || (G6_13PL == 0) -#define MG6_16_113PL ~(1 << 12) -#else -#define MG6_16_113PL 0xFFFF -#endif - -#if (G6_14PL >= G6_16PL) || (G6_14PL == 0) -#define MG6_16_114PL ~(1 << 13) -#else -#define MG6_16_114PL 0xFFFF -#endif - -#if (G6_15PL >= G6_16PL) || (G6_15PL == 0) -#define MG6_16_115PL ~(1 << 14) -#else -#define MG6_16_115PL 0xFFFF -#endif - -#define MG6_16_116PL 0x7FFF -#define MG6_16 (MG6_16_11PL & MG6_16_12PL & MG6_16_13PL & MG6_16_14PL & \ - MG6_16_15PL & MG6_16_16PL & MG6_16_17PL & MG6_16_18PL & \ - MG6_16_19PL & MG6_16_110PL & MG6_16_111PL & MG6_16_112PL & \ - MG6_16_113PL & MG6_16_114PL & MG6_16_115PL & MG6_16_116PL) -// End of MG6_16: - - -// -// Automatically generate PIEIER7 interrupt masks MG71 to MG716: -// - -// Beginning of MG71: -#if (G7_2PL >= G7_1PL) || (G7_2PL == 0) -#define MG7_1_12PL ~(1 << 1) -#else -#define MG7_1_12PL 0xFFFF -#endif - -#if (G7_3PL >= G7_1PL) || (G7_3PL == 0) -#define MG7_1_13PL ~(1 << 2) -#else -#define MG7_1_13PL 0xFFFF -#endif - -#if (G7_4PL >= G7_1PL) || (G7_4PL == 0) -#define MG7_1_14PL ~(1 << 3) -#else -#define MG7_1_14PL 0xFFFF -#endif - -#if (G7_5PL >= G7_1PL) || (G7_5PL == 0) -#define MG7_1_15PL ~(1 << 4) -#else -#define MG7_1_15PL 0xFFFF -#endif - -#if (G7_6PL >= G7_1PL) || (G7_6PL == 0) -#define MG7_1_16PL ~(1 << 5) -#else -#define MG7_1_16PL 0xFFFF -#endif - -#if (G7_7PL >= G7_1PL) || (G7_7PL == 0) -#define MG7_1_17PL ~(1 << 6) -#else -#define MG7_1_17PL 0xFFFF -#endif - -#if (G7_8PL >= G7_1PL) || (G7_8PL == 0) -#define MG7_1_18PL ~(1 << 7) -#else -#define MG7_1_18PL 0xFFFF -#endif - -#if (G7_9PL >= G7_1PL) || (G7_9PL == 0) -#define MG7_1_19PL ~(1 << 8) -#else -#define MG7_1_19PL 0xFFFF -#endif - -#if (G7_10PL >= G7_1PL) || (G7_10PL == 0) -#define MG7_1_110PL ~(1 << 9) -#else -#define MG7_1_110PL 0xFFFF -#endif - -#if (G7_11PL >= G7_1PL) || (G7_11PL == 0) -#define MG7_1_111PL ~(1 << 10) -#else -#define MG7_1_111PL 0xFFFF -#endif - -#if (G7_12PL >= G7_1PL) || (G7_12PL == 0) -#define MG7_1_112PL ~(1 << 11) -#else -#define MG7_1_112PL 0xFFFF -#endif - -#if (G7_13PL >= G7_1PL) || (G7_13PL == 0) -#define MG7_1_113PL ~(1 << 12) -#else -#define MG7_1_113PL 0xFFFF -#endif - -#if (G7_14PL >= G7_1PL) || (G7_14PL == 0) -#define MG7_1_114PL ~(1 << 13) -#else -#define MG7_1_114PL 0xFFFF -#endif - -#if (G7_15PL >= G7_1PL) || (G7_15PL == 0) -#define MG7_1_115PL ~(1 << 14) -#else -#define MG7_1_115PL 0xFFFF -#endif - -#if (G7_16PL >= G7_1PL) || (G7_16PL == 0) -#define MG7_1_116PL ~(1 << 15) -#else -#define MG7_1_116PL 0xFFFF -#endif - -#define MG7_1_11PL 0xFFFE -#define MG7_1 (MG7_1_11PL & MG7_1_12PL & MG7_1_13PL & MG7_1_14PL & \ - MG7_1_15PL & MG7_1_16PL & MG7_1_17PL & MG7_1_18PL & \ - MG7_1_19PL & MG7_1_110PL & MG7_1_111PL & MG7_1_112PL & \ - MG7_1_113PL & MG7_1_114PL & MG7_1_115PL & MG7_1_116PL) -// End of MG7_1: -// Beginning of MG72: -#if (G7_1PL >= G7_2PL) || (G7_1PL == 0) -#define MG7_2_11PL ~(1 << 0) -#else -#define MG7_2_11PL 0xFFFF -#endif - -#if (G7_3PL >= G7_2PL) || (G7_3PL == 0) -#define MG7_2_13PL ~(1 << 2) -#else -#define MG7_2_13PL 0xFFFF -#endif - -#if (G7_4PL >= G7_2PL) || (G7_4PL == 0) -#define MG7_2_14PL ~(1 << 3) -#else -#define MG7_2_14PL 0xFFFF -#endif - -#if (G7_5PL >= G7_2PL) || (G7_5PL == 0) -#define MG7_2_15PL ~(1 << 4) -#else -#define MG7_2_15PL 0xFFFF -#endif - -#if (G7_6PL >= G7_2PL) || (G7_6PL == 0) -#define MG7_2_16PL ~(1 << 5) -#else -#define MG7_2_16PL 0xFFFF -#endif - -#if (G7_7PL >= G7_2PL) || (G7_7PL == 0) -#define MG7_2_17PL ~(1 << 6) -#else -#define MG7_2_17PL 0xFFFF -#endif - -#if (G7_8PL >= G7_2PL) || (G7_8PL == 0) -#define MG7_2_18PL ~(1 << 7) -#else -#define MG7_2_18PL 0xFFFF -#endif - -#if (G7_9PL >= G7_2PL) || (G7_9PL == 0) -#define MG7_2_19PL ~(1 << 8) -#else -#define MG7_2_19PL 0xFFFF -#endif - -#if (G7_10PL >= G7_2PL) || (G7_10PL == 0) -#define MG7_2_110PL ~(1 << 9) -#else -#define MG7_2_110PL 0xFFFF -#endif - -#if (G7_11PL >= G7_2PL) || (G7_11PL == 0) -#define MG7_2_111PL ~(1 << 10) -#else -#define MG7_2_111PL 0xFFFF -#endif - -#if (G7_12PL >= G7_2PL) || (G7_12PL == 0) -#define MG7_2_112PL ~(1 << 11) -#else -#define MG7_2_112PL 0xFFFF -#endif - -#if (G7_13PL >= G7_2PL) || (G7_13PL == 0) -#define MG7_2_113PL ~(1 << 12) -#else -#define MG7_2_113PL 0xFFFF -#endif - -#if (G7_14PL >= G7_2PL) || (G7_14PL == 0) -#define MG7_2_114PL ~(1 << 13) -#else -#define MG7_2_114PL 0xFFFF -#endif - -#if (G7_15PL >= G7_2PL) || (G7_15PL == 0) -#define MG7_2_115PL ~(1 << 14) -#else -#define MG7_2_115PL 0xFFFF -#endif - -#if (G7_16PL >= G7_2PL) || (G7_16PL == 0) -#define MG7_2_116PL ~(1 << 15) -#else -#define MG7_2_116PL 0xFFFF -#endif - -#define MG7_2_12PL 0xFFFD -#define MG7_2 (MG7_2_11PL & MG7_2_12PL & MG7_2_13PL & MG7_2_14PL & \ - MG7_2_15PL & MG7_2_16PL & MG7_2_17PL & MG7_2_18PL & \ - MG7_2_19PL & MG7_2_110PL & MG7_2_111PL & MG7_2_112PL & \ - MG7_2_113PL & MG7_2_114PL & MG7_2_115PL & MG7_2_116PL) -// End of MG7_2: -// Beginning of MG73: -#if (G7_1PL >= G7_3PL) || (G7_1PL == 0) -#define MG7_3_11PL ~(1 << 0) -#else -#define MG7_3_11PL 0xFFFF -#endif - -#if (G7_2PL >= G7_3PL) || (G7_2PL == 0) -#define MG7_3_12PL ~(1 << 1) -#else -#define MG7_3_12PL 0xFFFF -#endif - -#if (G7_4PL >= G7_3PL) || (G7_4PL == 0) -#define MG7_3_14PL ~(1 << 3) -#else -#define MG7_3_14PL 0xFFFF -#endif - -#if (G7_5PL >= G7_3PL) || (G7_5PL == 0) -#define MG7_3_15PL ~(1 << 4) -#else -#define MG7_3_15PL 0xFFFF -#endif - -#if (G7_6PL >= G7_3PL) || (G7_6PL == 0) -#define MG7_3_16PL ~(1 << 5) -#else -#define MG7_3_16PL 0xFFFF -#endif - -#if (G7_7PL >= G7_3PL) || (G7_7PL == 0) -#define MG7_3_17PL ~(1 << 6) -#else -#define MG7_3_17PL 0xFFFF -#endif - -#if (G7_8PL >= G7_3PL) || (G7_8PL == 0) -#define MG7_3_18PL ~(1 << 7) -#else -#define MG7_3_18PL 0xFFFF -#endif - -#if (G7_9PL >= G7_3PL) || (G7_9PL == 0) -#define MG7_3_19PL ~(1 << 8) -#else -#define MG7_3_19PL 0xFFFF -#endif - -#if (G7_10PL >= G7_3PL) || (G7_10PL == 0) -#define MG7_3_110PL ~(1 << 9) -#else -#define MG7_3_110PL 0xFFFF -#endif - -#if (G7_11PL >= G7_3PL) || (G7_11PL == 0) -#define MG7_3_111PL ~(1 << 10) -#else -#define MG7_3_111PL 0xFFFF -#endif - -#if (G7_12PL >= G7_3PL) || (G7_12PL == 0) -#define MG7_3_112PL ~(1 << 11) -#else -#define MG7_3_112PL 0xFFFF -#endif - -#if (G7_13PL >= G7_3PL) || (G7_13PL == 0) -#define MG7_3_113PL ~(1 << 12) -#else -#define MG7_3_113PL 0xFFFF -#endif - -#if (G7_14PL >= G7_3PL) || (G7_14PL == 0) -#define MG7_3_114PL ~(1 << 13) -#else -#define MG7_3_114PL 0xFFFF -#endif - -#if (G7_15PL >= G7_3PL) || (G7_15PL == 0) -#define MG7_3_115PL ~(1 << 14) -#else -#define MG7_3_115PL 0xFFFF -#endif - -#if (G7_16PL >= G7_3PL) || (G7_16PL == 0) -#define MG7_3_116PL ~(1 << 15) -#else -#define MG7_3_116PL 0xFFFF -#endif - -#define MG7_3_13PL 0xFFFB -#define MG7_3 (MG7_3_11PL & MG7_3_12PL & MG7_3_13PL & MG7_3_14PL & \ - MG7_3_15PL & MG7_3_16PL & MG7_3_17PL & MG7_3_18PL & \ - MG7_3_19PL & MG7_3_110PL & MG7_3_111PL & MG7_3_112PL & \ - MG7_3_113PL & MG7_3_114PL & MG7_3_115PL & MG7_3_116PL) -// End of MG7_3: -// Beginning of MG74: -#if (G7_1PL >= G7_4PL) || (G7_1PL == 0) -#define MG7_4_11PL ~(1 << 0) -#else -#define MG7_4_11PL 0xFFFF -#endif - -#if (G7_2PL >= G7_4PL) || (G7_2PL == 0) -#define MG7_4_12PL ~(1 << 1) -#else -#define MG7_4_12PL 0xFFFF -#endif - -#if (G7_3PL >= G7_4PL) || (G7_3PL == 0) -#define MG7_4_13PL ~(1 << 2) -#else -#define MG7_4_13PL 0xFFFF -#endif - -#if (G7_5PL >= G7_4PL) || (G7_5PL == 0) -#define MG7_4_15PL ~(1 << 4) -#else -#define MG7_4_15PL 0xFFFF -#endif - -#if (G7_6PL >= G7_4PL) || (G7_6PL == 0) -#define MG7_4_16PL ~(1 << 5) -#else -#define MG7_4_16PL 0xFFFF -#endif - -#if (G7_7PL >= G7_4PL) || (G7_7PL == 0) -#define MG7_4_17PL ~(1 << 6) -#else -#define MG7_4_17PL 0xFFFF -#endif - -#if (G7_8PL >= G7_4PL) || (G7_8PL == 0) -#define MG7_4_18PL ~(1 << 7) -#else -#define MG7_4_18PL 0xFFFF -#endif - -#if (G7_9PL >= G7_4PL) || (G7_9PL == 0) -#define MG7_4_19PL ~(1 << 8) -#else -#define MG7_4_19PL 0xFFFF -#endif - -#if (G7_10PL >= G7_4PL) || (G7_10PL == 0) -#define MG7_4_110PL ~(1 << 9) -#else -#define MG7_4_110PL 0xFFFF -#endif - -#if (G7_11PL >= G7_4PL) || (G7_11PL == 0) -#define MG7_4_111PL ~(1 << 10) -#else -#define MG7_4_111PL 0xFFFF -#endif - -#if (G7_12PL >= G7_4PL) || (G7_12PL == 0) -#define MG7_4_112PL ~(1 << 11) -#else -#define MG7_4_112PL 0xFFFF -#endif - -#if (G7_13PL >= G7_4PL) || (G7_13PL == 0) -#define MG7_4_113PL ~(1 << 12) -#else -#define MG7_4_113PL 0xFFFF -#endif - -#if (G7_14PL >= G7_4PL) || (G7_14PL == 0) -#define MG7_4_114PL ~(1 << 13) -#else -#define MG7_4_114PL 0xFFFF -#endif - -#if (G7_15PL >= G7_4PL) || (G7_15PL == 0) -#define MG7_4_115PL ~(1 << 14) -#else -#define MG7_4_115PL 0xFFFF -#endif - -#if (G7_16PL >= G7_4PL) || (G7_16PL == 0) -#define MG7_4_116PL ~(1 << 15) -#else -#define MG7_4_116PL 0xFFFF -#endif - -#define MG7_4_14PL 0xFFF7 -#define MG7_4 (MG7_4_11PL & MG7_4_12PL & MG7_4_13PL & MG7_4_14PL & \ - MG7_4_15PL & MG7_4_16PL & MG7_4_17PL & MG7_4_18PL & \ - MG7_4_19PL & MG7_4_110PL & MG7_4_111PL & MG7_4_112PL & \ - MG7_4_113PL & MG7_4_114PL & MG7_4_115PL & MG7_4_116PL) -// End of MG7_4: -// Beginning of MG75: -#if (G7_1PL >= G7_5PL) || (G7_1PL == 0) -#define MG7_5_11PL ~(1 << 0) -#else -#define MG7_5_11PL 0xFFFF -#endif - -#if (G7_2PL >= G7_5PL) || (G7_2PL == 0) -#define MG7_5_12PL ~(1 << 1) -#else -#define MG7_5_12PL 0xFFFF -#endif - -#if (G7_3PL >= G7_5PL) || (G7_3PL == 0) -#define MG7_5_13PL ~(1 << 2) -#else -#define MG7_5_13PL 0xFFFF -#endif - -#if (G7_4PL >= G7_5PL) || (G7_4PL == 0) -#define MG7_5_14PL ~(1 << 3) -#else -#define MG7_5_14PL 0xFFFF -#endif - -#if (G7_6PL >= G7_5PL) || (G7_6PL == 0) -#define MG7_5_16PL ~(1 << 5) -#else -#define MG7_5_16PL 0xFFFF -#endif - -#if (G7_7PL >= G7_5PL) || (G7_7PL == 0) -#define MG7_5_17PL ~(1 << 6) -#else -#define MG7_5_17PL 0xFFFF -#endif - -#if (G7_8PL >= G7_5PL) || (G7_8PL == 0) -#define MG7_5_18PL ~(1 << 7) -#else -#define MG7_5_18PL 0xFFFF -#endif - -#if (G7_9PL >= G7_5PL) || (G7_9PL == 0) -#define MG7_5_19PL ~(1 << 8) -#else -#define MG7_5_19PL 0xFFFF -#endif - -#if (G7_10PL >= G7_5PL) || (G7_10PL == 0) -#define MG7_5_110PL ~(1 << 9) -#else -#define MG7_5_110PL 0xFFFF -#endif - -#if (G7_11PL >= G7_5PL) || (G7_11PL == 0) -#define MG7_5_111PL ~(1 << 10) -#else -#define MG7_5_111PL 0xFFFF -#endif - -#if (G7_12PL >= G7_5PL) || (G7_12PL == 0) -#define MG7_5_112PL ~(1 << 11) -#else -#define MG7_5_112PL 0xFFFF -#endif - -#if (G7_13PL >= G7_5PL) || (G7_13PL == 0) -#define MG7_5_113PL ~(1 << 12) -#else -#define MG7_5_113PL 0xFFFF -#endif - -#if (G7_14PL >= G7_5PL) || (G7_14PL == 0) -#define MG7_5_114PL ~(1 << 13) -#else -#define MG7_5_114PL 0xFFFF -#endif - -#if (G7_15PL >= G7_5PL) || (G7_15PL == 0) -#define MG7_5_115PL ~(1 << 14) -#else -#define MG7_5_115PL 0xFFFF -#endif - -#if (G7_16PL >= G7_5PL) || (G7_16PL == 0) -#define MG7_5_116PL ~(1 << 15) -#else -#define MG7_5_116PL 0xFFFF -#endif - -#define MG7_5_15PL 0xFFEF -#define MG7_5 (MG7_5_11PL & MG7_5_12PL & MG7_5_13PL & MG7_5_14PL & \ - MG7_5_15PL & MG7_5_16PL & MG7_5_17PL & MG7_5_18PL & \ - MG7_5_19PL & MG7_5_110PL & MG7_5_111PL & MG7_5_112PL & \ - MG7_5_113PL & MG7_5_114PL & MG7_5_115PL & MG7_5_116PL) -// End of MG7_5: -// Beginning of MG76: -#if (G7_1PL >= G7_6PL) || (G7_1PL == 0) -#define MG7_6_11PL ~(1 << 0) -#else -#define MG7_6_11PL 0xFFFF -#endif - -#if (G7_2PL >= G7_6PL) || (G7_2PL == 0) -#define MG7_6_12PL ~(1 << 1) -#else -#define MG7_6_12PL 0xFFFF -#endif - -#if (G7_3PL >= G7_6PL) || (G7_3PL == 0) -#define MG7_6_13PL ~(1 << 2) -#else -#define MG7_6_13PL 0xFFFF -#endif - -#if (G7_4PL >= G7_6PL) || (G7_4PL == 0) -#define MG7_6_14PL ~(1 << 3) -#else -#define MG7_6_14PL 0xFFFF -#endif - -#if (G7_5PL >= G7_6PL) || (G7_5PL == 0) -#define MG7_6_15PL ~(1 << 4) -#else -#define MG7_6_15PL 0xFFFF -#endif - -#if (G7_7PL >= G7_6PL) || (G7_7PL == 0) -#define MG7_6_17PL ~(1 << 6) -#else -#define MG7_6_17PL 0xFFFF -#endif - -#if (G7_8PL >= G7_6PL) || (G7_8PL == 0) -#define MG7_6_18PL ~(1 << 7) -#else -#define MG7_6_18PL 0xFFFF -#endif - -#if (G7_9PL >= G7_6PL) || (G7_9PL == 0) -#define MG7_6_19PL ~(1 << 8) -#else -#define MG7_6_19PL 0xFFFF -#endif - -#if (G7_10PL >= G7_6PL) || (G7_10PL == 0) -#define MG7_6_110PL ~(1 << 9) -#else -#define MG7_6_110PL 0xFFFF -#endif - -#if (G7_11PL >= G7_6PL) || (G7_11PL == 0) -#define MG7_6_111PL ~(1 << 10) -#else -#define MG7_6_111PL 0xFFFF -#endif - -#if (G7_12PL >= G7_6PL) || (G7_12PL == 0) -#define MG7_6_112PL ~(1 << 11) -#else -#define MG7_6_112PL 0xFFFF -#endif - -#if (G7_13PL >= G7_6PL) || (G7_13PL == 0) -#define MG7_6_113PL ~(1 << 12) -#else -#define MG7_6_113PL 0xFFFF -#endif - -#if (G7_14PL >= G7_6PL) || (G7_14PL == 0) -#define MG7_6_114PL ~(1 << 13) -#else -#define MG7_6_114PL 0xFFFF -#endif - -#if (G7_15PL >= G7_6PL) || (G7_15PL == 0) -#define MG7_6_115PL ~(1 << 14) -#else -#define MG7_6_115PL 0xFFFF -#endif - -#if (G7_16PL >= G7_6PL) || (G7_16PL == 0) -#define MG7_6_116PL ~(1 << 15) -#else -#define MG7_6_116PL 0xFFFF -#endif - -#define MG7_6_16PL 0xFFDF -#define MG7_6 (MG7_6_11PL & MG7_6_12PL & MG7_6_13PL & MG7_6_14PL & \ - MG7_6_15PL & MG7_6_16PL & MG7_6_17PL & MG7_6_18PL & \ - MG7_6_19PL & MG7_6_110PL & MG7_6_111PL & MG7_6_112PL & \ - MG7_6_113PL & MG7_6_114PL & MG7_6_115PL & MG7_6_116PL) -// End of MG7_6: -// Beginning of MG77: -#if (G7_1PL >= G7_7PL) || (G7_1PL == 0) -#define MG7_7_11PL ~(1 << 0) -#else -#define MG7_7_11PL 0xFFFF -#endif - -#if (G7_2PL >= G7_7PL) || (G7_2PL == 0) -#define MG7_7_12PL ~(1 << 1) -#else -#define MG7_7_12PL 0xFFFF -#endif - -#if (G7_3PL >= G7_7PL) || (G7_3PL == 0) -#define MG7_7_13PL ~(1 << 2) -#else -#define MG7_7_13PL 0xFFFF -#endif - -#if (G7_4PL >= G7_7PL) || (G7_4PL == 0) -#define MG7_7_14PL ~(1 << 3) -#else -#define MG7_7_14PL 0xFFFF -#endif - -#if (G7_5PL >= G7_7PL) || (G7_5PL == 0) -#define MG7_7_15PL ~(1 << 4) -#else -#define MG7_7_15PL 0xFFFF -#endif - -#if (G7_6PL >= G7_7PL) || (G7_6PL == 0) -#define MG7_7_16PL ~(1 << 5) -#else -#define MG7_7_16PL 0xFFFF -#endif - -#if (G7_8PL >= G7_7PL) || (G7_8PL == 0) -#define MG7_7_18PL ~(1 << 7) -#else -#define MG7_7_18PL 0xFFFF -#endif - -#if (G7_9PL >= G7_7PL) || (G7_9PL == 0) -#define MG7_7_19PL ~(1 << 8) -#else -#define MG7_7_19PL 0xFFFF -#endif - -#if (G7_10PL >= G7_7PL) || (G7_10PL == 0) -#define MG7_7_110PL ~(1 << 9) -#else -#define MG7_7_110PL 0xFFFF -#endif - -#if (G7_11PL >= G7_7PL) || (G7_11PL == 0) -#define MG7_7_111PL ~(1 << 10) -#else -#define MG7_7_111PL 0xFFFF -#endif - -#if (G7_12PL >= G7_7PL) || (G7_12PL == 0) -#define MG7_7_112PL ~(1 << 11) -#else -#define MG7_7_112PL 0xFFFF -#endif - -#if (G7_13PL >= G7_7PL) || (G7_13PL == 0) -#define MG7_7_113PL ~(1 << 12) -#else -#define MG7_7_113PL 0xFFFF -#endif - -#if (G7_14PL >= G7_7PL) || (G7_14PL == 0) -#define MG7_7_114PL ~(1 << 13) -#else -#define MG7_7_114PL 0xFFFF -#endif - -#if (G7_15PL >= G7_7PL) || (G7_15PL == 0) -#define MG7_7_115PL ~(1 << 14) -#else -#define MG7_7_115PL 0xFFFF -#endif - -#if (G7_16PL >= G7_7PL) || (G7_16PL == 0) -#define MG7_7_116PL ~(1 << 15) -#else -#define MG7_7_116PL 0xFFFF -#endif - -#define MG7_7_17PL 0xFFBF -#define MG7_7 (MG7_7_11PL & MG7_7_12PL & MG7_7_13PL & MG7_7_14PL & \ - MG7_7_15PL & MG7_7_16PL & MG7_7_17PL & MG7_7_18PL & \ - MG7_7_19PL & MG7_7_110PL & MG7_7_111PL & MG7_7_112PL & \ - MG7_7_113PL & MG7_7_114PL & MG7_7_115PL & MG7_7_116PL) -// End of MG7_7: -// Beginning of MG78: -#if (G7_1PL >= G7_8PL) || (G7_1PL == 0) -#define MG7_8_11PL ~(1 << 0) -#else -#define MG7_8_11PL 0xFFFF -#endif - -#if (G7_2PL >= G7_8PL) || (G7_2PL == 0) -#define MG7_8_12PL ~(1 << 1) -#else -#define MG7_8_12PL 0xFFFF -#endif - -#if (G7_3PL >= G7_8PL) || (G7_3PL == 0) -#define MG7_8_13PL ~(1 << 2) -#else -#define MG7_8_13PL 0xFFFF -#endif - -#if (G7_4PL >= G7_8PL) || (G7_4PL == 0) -#define MG7_8_14PL ~(1 << 3) -#else -#define MG7_8_14PL 0xFFFF -#endif - -#if (G7_5PL >= G7_8PL) || (G7_5PL == 0) -#define MG7_8_15PL ~(1 << 4) -#else -#define MG7_8_15PL 0xFFFF -#endif - -#if (G7_6PL >= G7_8PL) || (G7_6PL == 0) -#define MG7_8_16PL ~(1 << 5) -#else -#define MG7_8_16PL 0xFFFF -#endif - -#if (G7_7PL >= G7_8PL) || (G7_7PL == 0) -#define MG7_8_17PL ~(1 << 6) -#else -#define MG7_8_17PL 0xFFFF -#endif - -#if (G7_9PL >= G7_8PL) || (G7_9PL == 0) -#define MG7_8_19PL ~(1 << 8) -#else -#define MG7_8_19PL 0xFFFF -#endif - -#if (G7_10PL >= G7_8PL) || (G7_10PL == 0) -#define MG7_8_110PL ~(1 << 9) -#else -#define MG7_8_110PL 0xFFFF -#endif - -#if (G7_11PL >= G7_8PL) || (G7_11PL == 0) -#define MG7_8_111PL ~(1 << 10) -#else -#define MG7_8_111PL 0xFFFF -#endif - -#if (G7_12PL >= G7_8PL) || (G7_12PL == 0) -#define MG7_8_112PL ~(1 << 11) -#else -#define MG7_8_112PL 0xFFFF -#endif - -#if (G7_13PL >= G7_8PL) || (G7_13PL == 0) -#define MG7_8_113PL ~(1 << 12) -#else -#define MG7_8_113PL 0xFFFF -#endif - -#if (G7_14PL >= G7_8PL) || (G7_14PL == 0) -#define MG7_8_114PL ~(1 << 13) -#else -#define MG7_8_114PL 0xFFFF -#endif - -#if (G7_15PL >= G7_8PL) || (G7_15PL == 0) -#define MG7_8_115PL ~(1 << 14) -#else -#define MG7_8_115PL 0xFFFF -#endif - -#if (G7_16PL >= G7_8PL) || (G7_16PL == 0) -#define MG7_8_116PL ~(1 << 15) -#else -#define MG7_8_116PL 0xFFFF -#endif - -#define MG7_8_18PL 0xFF7F -#define MG7_8 (MG7_8_11PL & MG7_8_12PL & MG7_8_13PL & MG7_8_14PL & \ - MG7_8_15PL & MG7_8_16PL & MG7_8_17PL & MG7_8_18PL & \ - MG7_8_19PL & MG7_8_110PL & MG7_8_111PL & MG7_8_112PL & \ - MG7_8_113PL & MG7_8_114PL & MG7_8_115PL & MG7_8_116PL) -// End of MG7_8: -// Beginning of MG79: -#if (G7_1PL >= G7_9PL) || (G7_1PL == 0) -#define MG7_9_11PL ~(1 << 0) -#else -#define MG7_9_11PL 0xFFFF -#endif - -#if (G7_2PL >= G7_9PL) || (G7_2PL == 0) -#define MG7_9_12PL ~(1 << 1) -#else -#define MG7_9_12PL 0xFFFF -#endif - -#if (G7_3PL >= G7_9PL) || (G7_3PL == 0) -#define MG7_9_13PL ~(1 << 2) -#else -#define MG7_9_13PL 0xFFFF -#endif - -#if (G7_4PL >= G7_9PL) || (G7_4PL == 0) -#define MG7_9_14PL ~(1 << 3) -#else -#define MG7_9_14PL 0xFFFF -#endif - -#if (G7_5PL >= G7_9PL) || (G7_5PL == 0) -#define MG7_9_15PL ~(1 << 4) -#else -#define MG7_9_15PL 0xFFFF -#endif - -#if (G7_6PL >= G7_9PL) || (G7_6PL == 0) -#define MG7_9_16PL ~(1 << 5) -#else -#define MG7_9_16PL 0xFFFF -#endif - -#if (G7_7PL >= G7_9PL) || (G7_7PL == 0) -#define MG7_9_17PL ~(1 << 6) -#else -#define MG7_9_17PL 0xFFFF -#endif - -#if (G7_8PL >= G7_9PL) || (G7_8PL == 0) -#define MG7_9_18PL ~(1 << 7) -#else -#define MG7_9_18PL 0xFFFF -#endif - -#if (G7_10PL >= G7_9PL) || (G7_10PL == 0) -#define MG7_9_110PL ~(1 << 9) -#else -#define MG7_9_110PL 0xFFFF -#endif - -#if (G7_11PL >= G7_9PL) || (G7_11PL == 0) -#define MG7_9_111PL ~(1 << 10) -#else -#define MG7_9_111PL 0xFFFF -#endif - -#if (G7_12PL >= G7_9PL) || (G7_12PL == 0) -#define MG7_9_112PL ~(1 << 11) -#else -#define MG7_9_112PL 0xFFFF -#endif - -#if (G7_13PL >= G7_9PL) || (G7_13PL == 0) -#define MG7_9_113PL ~(1 << 12) -#else -#define MG7_9_113PL 0xFFFF -#endif - -#if (G7_14PL >= G7_9PL) || (G7_14PL == 0) -#define MG7_9_114PL ~(1 << 13) -#else -#define MG7_9_114PL 0xFFFF -#endif - -#if (G7_15PL >= G7_9PL) || (G7_15PL == 0) -#define MG7_9_115PL ~(1 << 14) -#else -#define MG7_9_115PL 0xFFFF -#endif - -#if (G7_16PL >= G7_9PL) || (G7_16PL == 0) -#define MG7_9_116PL ~(1 << 15) -#else -#define MG7_9_116PL 0xFFFF -#endif - -#define MG7_9_19PL 0xFEFF -#define MG7_9 (MG7_9_11PL & MG7_9_12PL & MG7_9_13PL & MG7_9_14PL & \ - MG7_9_15PL & MG7_9_16PL & MG7_9_17PL & MG7_9_18PL & \ - MG7_9_19PL & MG7_9_110PL & MG7_9_111PL & MG7_9_112PL & \ - MG7_9_113PL & MG7_9_114PL & MG7_9_115PL & MG7_9_116PL) -// End of MG7_9: -// Beginning of MG710: -#if (G7_1PL >= G7_10PL) || (G7_1PL == 0) -#define MG7_10_11PL ~(1 << 0) -#else -#define MG7_10_11PL 0xFFFF -#endif - -#if (G7_2PL >= G7_10PL) || (G7_2PL == 0) -#define MG7_10_12PL ~(1 << 1) -#else -#define MG7_10_12PL 0xFFFF -#endif - -#if (G7_3PL >= G7_10PL) || (G7_3PL == 0) -#define MG7_10_13PL ~(1 << 2) -#else -#define MG7_10_13PL 0xFFFF -#endif - -#if (G7_4PL >= G7_10PL) || (G7_4PL == 0) -#define MG7_10_14PL ~(1 << 3) -#else -#define MG7_10_14PL 0xFFFF -#endif - -#if (G7_5PL >= G7_10PL) || (G7_5PL == 0) -#define MG7_10_15PL ~(1 << 4) -#else -#define MG7_10_15PL 0xFFFF -#endif - -#if (G7_6PL >= G7_10PL) || (G7_6PL == 0) -#define MG7_10_16PL ~(1 << 5) -#else -#define MG7_10_16PL 0xFFFF -#endif - -#if (G7_7PL >= G7_10PL) || (G7_7PL == 0) -#define MG7_10_17PL ~(1 << 6) -#else -#define MG7_10_17PL 0xFFFF -#endif - -#if (G7_8PL >= G7_10PL) || (G7_8PL == 0) -#define MG7_10_18PL ~(1 << 7) -#else -#define MG7_10_18PL 0xFFFF -#endif - -#if (G7_9PL >= G7_10PL) || (G7_9PL == 0) -#define MG7_10_19PL ~(1 << 8) -#else -#define MG7_10_19PL 0xFFFF -#endif - -#if (G7_11PL >= G7_10PL) || (G7_11PL == 0) -#define MG7_10_111PL ~(1 << 10) -#else -#define MG7_10_111PL 0xFFFF -#endif - -#if (G7_12PL >= G7_10PL) || (G7_12PL == 0) -#define MG7_10_112PL ~(1 << 11) -#else -#define MG7_10_112PL 0xFFFF -#endif - -#if (G7_13PL >= G7_10PL) || (G7_13PL == 0) -#define MG7_10_113PL ~(1 << 12) -#else -#define MG7_10_113PL 0xFFFF -#endif - -#if (G7_14PL >= G7_10PL) || (G7_14PL == 0) -#define MG7_10_114PL ~(1 << 13) -#else -#define MG7_10_114PL 0xFFFF -#endif - -#if (G7_15PL >= G7_10PL) || (G7_15PL == 0) -#define MG7_10_115PL ~(1 << 14) -#else -#define MG7_10_115PL 0xFFFF -#endif - -#if (G7_16PL >= G7_10PL) || (G7_16PL == 0) -#define MG7_10_116PL ~(1 << 15) -#else -#define MG7_10_116PL 0xFFFF -#endif - -#define MG7_10_110PL 0xFDFF -#define MG7_10 (MG7_10_11PL & MG7_10_12PL & MG7_10_13PL & MG7_10_14PL & \ - MG7_10_15PL & MG7_10_16PL & MG7_10_17PL & MG7_10_18PL & \ - MG7_10_19PL & MG7_10_110PL & MG7_10_111PL & MG7_10_112PL & \ - MG7_10_113PL & MG7_10_114PL & MG7_10_115PL & MG7_10_116PL) -// End of MG7_10: -// Beginning of MG711: -#if (G7_1PL >= G7_11PL) || (G7_1PL == 0) -#define MG7_11_11PL ~(1 << 0) -#else -#define MG7_11_11PL 0xFFFF -#endif - -#if (G7_2PL >= G7_11PL) || (G7_2PL == 0) -#define MG7_11_12PL ~(1 << 1) -#else -#define MG7_11_12PL 0xFFFF -#endif - -#if (G7_3PL >= G7_11PL) || (G7_3PL == 0) -#define MG7_11_13PL ~(1 << 2) -#else -#define MG7_11_13PL 0xFFFF -#endif - -#if (G7_4PL >= G7_11PL) || (G7_4PL == 0) -#define MG7_11_14PL ~(1 << 3) -#else -#define MG7_11_14PL 0xFFFF -#endif - -#if (G7_5PL >= G7_11PL) || (G7_5PL == 0) -#define MG7_11_15PL ~(1 << 4) -#else -#define MG7_11_15PL 0xFFFF -#endif - -#if (G7_6PL >= G7_11PL) || (G7_6PL == 0) -#define MG7_11_16PL ~(1 << 5) -#else -#define MG7_11_16PL 0xFFFF -#endif - -#if (G7_7PL >= G7_11PL) || (G7_7PL == 0) -#define MG7_11_17PL ~(1 << 6) -#else -#define MG7_11_17PL 0xFFFF -#endif - -#if (G7_8PL >= G7_11PL) || (G7_8PL == 0) -#define MG7_11_18PL ~(1 << 7) -#else -#define MG7_11_18PL 0xFFFF -#endif - -#if (G7_9PL >= G7_11PL) || (G7_9PL == 0) -#define MG7_11_19PL ~(1 << 8) -#else -#define MG7_11_19PL 0xFFFF -#endif - -#if (G7_10PL >= G7_11PL) || (G7_10PL == 0) -#define MG7_11_110PL ~(1 << 9) -#else -#define MG7_11_110PL 0xFFFF -#endif - -#if (G7_12PL >= G7_11PL) || (G7_12PL == 0) -#define MG7_11_112PL ~(1 << 11) -#else -#define MG7_11_112PL 0xFFFF -#endif - -#if (G7_13PL >= G7_11PL) || (G7_13PL == 0) -#define MG7_11_113PL ~(1 << 12) -#else -#define MG7_11_113PL 0xFFFF -#endif - -#if (G7_14PL >= G7_11PL) || (G7_14PL == 0) -#define MG7_11_114PL ~(1 << 13) -#else -#define MG7_11_114PL 0xFFFF -#endif - -#if (G7_15PL >= G7_11PL) || (G7_15PL == 0) -#define MG7_11_115PL ~(1 << 14) -#else -#define MG7_11_115PL 0xFFFF -#endif - -#if (G7_16PL >= G7_11PL) || (G7_16PL == 0) -#define MG7_11_116PL ~(1 << 15) -#else -#define MG7_11_116PL 0xFFFF -#endif - -#define MG7_11_111PL 0xFBFF -#define MG7_11 (MG7_11_11PL & MG7_11_12PL & MG7_11_13PL & MG7_11_14PL & \ - MG7_11_15PL & MG7_11_16PL & MG7_11_17PL & MG7_11_18PL & \ - MG7_11_19PL & MG7_11_110PL & MG7_11_111PL & MG7_11_112PL & \ - MG7_11_113PL & MG7_11_114PL & MG7_11_115PL & MG7_11_116PL) -// End of MG7_11: -// Beginning of MG712: -#if (G7_1PL >= G7_12PL) || (G7_1PL == 0) -#define MG7_12_11PL ~(1 << 0) -#else -#define MG7_12_11PL 0xFFFF -#endif - -#if (G7_2PL >= G7_12PL) || (G7_2PL == 0) -#define MG7_12_12PL ~(1 << 1) -#else -#define MG7_12_12PL 0xFFFF -#endif - -#if (G7_3PL >= G7_12PL) || (G7_3PL == 0) -#define MG7_12_13PL ~(1 << 2) -#else -#define MG7_12_13PL 0xFFFF -#endif - -#if (G7_4PL >= G7_12PL) || (G7_4PL == 0) -#define MG7_12_14PL ~(1 << 3) -#else -#define MG7_12_14PL 0xFFFF -#endif - -#if (G7_5PL >= G7_12PL) || (G7_5PL == 0) -#define MG7_12_15PL ~(1 << 4) -#else -#define MG7_12_15PL 0xFFFF -#endif - -#if (G7_6PL >= G7_12PL) || (G7_6PL == 0) -#define MG7_12_16PL ~(1 << 5) -#else -#define MG7_12_16PL 0xFFFF -#endif - -#if (G7_7PL >= G7_12PL) || (G7_7PL == 0) -#define MG7_12_17PL ~(1 << 6) -#else -#define MG7_12_17PL 0xFFFF -#endif - -#if (G7_8PL >= G7_12PL) || (G7_8PL == 0) -#define MG7_12_18PL ~(1 << 7) -#else -#define MG7_12_18PL 0xFFFF -#endif - -#if (G7_9PL >= G7_12PL) || (G7_9PL == 0) -#define MG7_12_19PL ~(1 << 8) -#else -#define MG7_12_19PL 0xFFFF -#endif - -#if (G7_10PL >= G7_12PL) || (G7_10PL == 0) -#define MG7_12_110PL ~(1 << 9) -#else -#define MG7_12_110PL 0xFFFF -#endif - -#if (G7_11PL >= G7_12PL) || (G7_11PL == 0) -#define MG7_12_111PL ~(1 << 10) -#else -#define MG7_12_111PL 0xFFFF -#endif - -#if (G7_13PL >= G7_12PL) || (G7_13PL == 0) -#define MG7_12_113PL ~(1 << 12) -#else -#define MG7_12_113PL 0xFFFF -#endif - -#if (G7_14PL >= G7_12PL) || (G7_14PL == 0) -#define MG7_12_114PL ~(1 << 13) -#else -#define MG7_12_114PL 0xFFFF -#endif - -#if (G7_15PL >= G7_12PL) || (G7_15PL == 0) -#define MG7_12_115PL ~(1 << 14) -#else -#define MG7_12_115PL 0xFFFF -#endif - -#if (G7_16PL >= G7_12PL) || (G7_16PL == 0) -#define MG7_12_116PL ~(1 << 15) -#else -#define MG7_12_116PL 0xFFFF -#endif - -#define MG7_12_112PL 0xF7FF -#define MG7_12 (MG7_12_11PL & MG7_12_12PL & MG7_12_13PL & MG7_12_14PL & \ - MG7_12_15PL & MG7_12_16PL & MG7_12_17PL & MG7_12_18PL & \ - MG7_12_19PL & MG7_12_110PL & MG7_12_111PL & MG7_12_112PL & \ - MG7_12_113PL & MG7_12_114PL & MG7_12_115PL & MG7_12_116PL) -// End of MG7_12: -// Beginning of MG713: -#if (G7_1PL >= G7_13PL) || (G7_1PL == 0) -#define MG7_13_11PL ~(1 << 0) -#else -#define MG7_13_11PL 0xFFFF -#endif - -#if (G7_2PL >= G7_13PL) || (G7_2PL == 0) -#define MG7_13_12PL ~(1 << 1) -#else -#define MG7_13_12PL 0xFFFF -#endif - -#if (G7_3PL >= G7_13PL) || (G7_3PL == 0) -#define MG7_13_13PL ~(1 << 2) -#else -#define MG7_13_13PL 0xFFFF -#endif - -#if (G7_4PL >= G7_13PL) || (G7_4PL == 0) -#define MG7_13_14PL ~(1 << 3) -#else -#define MG7_13_14PL 0xFFFF -#endif - -#if (G7_5PL >= G7_13PL) || (G7_5PL == 0) -#define MG7_13_15PL ~(1 << 4) -#else -#define MG7_13_15PL 0xFFFF -#endif - -#if (G7_6PL >= G7_13PL) || (G7_6PL == 0) -#define MG7_13_16PL ~(1 << 5) -#else -#define MG7_13_16PL 0xFFFF -#endif - -#if (G7_7PL >= G7_13PL) || (G7_7PL == 0) -#define MG7_13_17PL ~(1 << 6) -#else -#define MG7_13_17PL 0xFFFF -#endif - -#if (G7_8PL >= G7_13PL) || (G7_8PL == 0) -#define MG7_13_18PL ~(1 << 7) -#else -#define MG7_13_18PL 0xFFFF -#endif - -#if (G7_9PL >= G7_13PL) || (G7_9PL == 0) -#define MG7_13_19PL ~(1 << 8) -#else -#define MG7_13_19PL 0xFFFF -#endif - -#if (G7_10PL >= G7_13PL) || (G7_10PL == 0) -#define MG7_13_110PL ~(1 << 9) -#else -#define MG7_13_110PL 0xFFFF -#endif - -#if (G7_11PL >= G7_13PL) || (G7_11PL == 0) -#define MG7_13_111PL ~(1 << 10) -#else -#define MG7_13_111PL 0xFFFF -#endif - -#if (G7_12PL >= G7_13PL) || (G7_12PL == 0) -#define MG7_13_112PL ~(1 << 11) -#else -#define MG7_13_112PL 0xFFFF -#endif - -#if (G7_14PL >= G7_13PL) || (G7_14PL == 0) -#define MG7_13_114PL ~(1 << 13) -#else -#define MG7_13_114PL 0xFFFF -#endif - -#if (G7_15PL >= G7_13PL) || (G7_15PL == 0) -#define MG7_13_115PL ~(1 << 14) -#else -#define MG7_13_115PL 0xFFFF -#endif - -#if (G7_16PL >= G7_13PL) || (G7_16PL == 0) -#define MG7_13_116PL ~(1 << 15) -#else -#define MG7_13_116PL 0xFFFF -#endif - -#define MG7_13_113PL 0xEFFF -#define MG7_13 (MG7_13_11PL & MG7_13_12PL & MG7_13_13PL & MG7_13_14PL & \ - MG7_13_15PL & MG7_13_16PL & MG7_13_17PL & MG7_13_18PL & \ - MG7_13_19PL & MG7_13_110PL & MG7_13_111PL & MG7_13_112PL & \ - MG7_13_113PL & MG7_13_114PL & MG7_13_115PL & MG7_13_116PL) -// End of MG7_13: -// Beginning of MG714: -#if (G7_1PL >= G7_14PL) || (G7_1PL == 0) -#define MG7_14_11PL ~(1 << 0) -#else -#define MG7_14_11PL 0xFFFF -#endif - -#if (G7_2PL >= G7_14PL) || (G7_2PL == 0) -#define MG7_14_12PL ~(1 << 1) -#else -#define MG7_14_12PL 0xFFFF -#endif - -#if (G7_3PL >= G7_14PL) || (G7_3PL == 0) -#define MG7_14_13PL ~(1 << 2) -#else -#define MG7_14_13PL 0xFFFF -#endif - -#if (G7_4PL >= G7_14PL) || (G7_4PL == 0) -#define MG7_14_14PL ~(1 << 3) -#else -#define MG7_14_14PL 0xFFFF -#endif - -#if (G7_5PL >= G7_14PL) || (G7_5PL == 0) -#define MG7_14_15PL ~(1 << 4) -#else -#define MG7_14_15PL 0xFFFF -#endif - -#if (G7_6PL >= G7_14PL) || (G7_6PL == 0) -#define MG7_14_16PL ~(1 << 5) -#else -#define MG7_14_16PL 0xFFFF -#endif - -#if (G7_7PL >= G7_14PL) || (G7_7PL == 0) -#define MG7_14_17PL ~(1 << 6) -#else -#define MG7_14_17PL 0xFFFF -#endif - -#if (G7_8PL >= G7_14PL) || (G7_8PL == 0) -#define MG7_14_18PL ~(1 << 7) -#else -#define MG7_14_18PL 0xFFFF -#endif - -#if (G7_9PL >= G7_14PL) || (G7_9PL == 0) -#define MG7_14_19PL ~(1 << 8) -#else -#define MG7_14_19PL 0xFFFF -#endif - -#if (G7_10PL >= G7_14PL) || (G7_10PL == 0) -#define MG7_14_110PL ~(1 << 9) -#else -#define MG7_14_110PL 0xFFFF -#endif - -#if (G7_11PL >= G7_14PL) || (G7_11PL == 0) -#define MG7_14_111PL ~(1 << 10) -#else -#define MG7_14_111PL 0xFFFF -#endif - -#if (G7_12PL >= G7_14PL) || (G7_12PL == 0) -#define MG7_14_112PL ~(1 << 11) -#else -#define MG7_14_112PL 0xFFFF -#endif - -#if (G7_13PL >= G7_14PL) || (G7_13PL == 0) -#define MG7_14_113PL ~(1 << 12) -#else -#define MG7_14_113PL 0xFFFF -#endif - -#if (G7_15PL >= G7_14PL) || (G7_15PL == 0) -#define MG7_14_115PL ~(1 << 14) -#else -#define MG7_14_115PL 0xFFFF -#endif - -#if (G7_16PL >= G7_14PL) || (G7_16PL == 0) -#define MG7_14_116PL ~(1 << 15) -#else -#define MG7_14_116PL 0xFFFF -#endif - -#define MG7_14_114PL 0xDFFF -#define MG7_14 (MG7_14_11PL & MG7_14_12PL & MG7_14_13PL & MG7_14_14PL & \ - MG7_14_15PL & MG7_14_16PL & MG7_14_17PL & MG7_14_18PL & \ - MG7_14_19PL & MG7_14_110PL & MG7_14_111PL & MG7_14_112PL & \ - MG7_14_113PL & MG7_14_114PL & MG7_14_115PL & MG7_14_116PL) -// End of MG7_14: -// Beginning of MG715: -#if (G7_1PL >= G7_15PL) || (G7_1PL == 0) -#define MG7_15_11PL ~(1 << 0) -#else -#define MG7_15_11PL 0xFFFF -#endif - -#if (G7_2PL >= G7_15PL) || (G7_2PL == 0) -#define MG7_15_12PL ~(1 << 1) -#else -#define MG7_15_12PL 0xFFFF -#endif - -#if (G7_3PL >= G7_15PL) || (G7_3PL == 0) -#define MG7_15_13PL ~(1 << 2) -#else -#define MG7_15_13PL 0xFFFF -#endif - -#if (G7_4PL >= G7_15PL) || (G7_4PL == 0) -#define MG7_15_14PL ~(1 << 3) -#else -#define MG7_15_14PL 0xFFFF -#endif - -#if (G7_5PL >= G7_15PL) || (G7_5PL == 0) -#define MG7_15_15PL ~(1 << 4) -#else -#define MG7_15_15PL 0xFFFF -#endif - -#if (G7_6PL >= G7_15PL) || (G7_6PL == 0) -#define MG7_15_16PL ~(1 << 5) -#else -#define MG7_15_16PL 0xFFFF -#endif - -#if (G7_7PL >= G7_15PL) || (G7_7PL == 0) -#define MG7_15_17PL ~(1 << 6) -#else -#define MG7_15_17PL 0xFFFF -#endif - -#if (G7_8PL >= G7_15PL) || (G7_8PL == 0) -#define MG7_15_18PL ~(1 << 7) -#else -#define MG7_15_18PL 0xFFFF -#endif - -#if (G7_9PL >= G7_15PL) || (G7_9PL == 0) -#define MG7_15_19PL ~(1 << 8) -#else -#define MG7_15_19PL 0xFFFF -#endif - -#if (G7_10PL >= G7_15PL) || (G7_10PL == 0) -#define MG7_15_110PL ~(1 << 9) -#else -#define MG7_15_110PL 0xFFFF -#endif - -#if (G7_11PL >= G7_15PL) || (G7_11PL == 0) -#define MG7_15_111PL ~(1 << 10) -#else -#define MG7_15_111PL 0xFFFF -#endif - -#if (G7_12PL >= G7_15PL) || (G7_12PL == 0) -#define MG7_15_112PL ~(1 << 11) -#else -#define MG7_15_112PL 0xFFFF -#endif - -#if (G7_13PL >= G7_15PL) || (G7_13PL == 0) -#define MG7_15_113PL ~(1 << 12) -#else -#define MG7_15_113PL 0xFFFF -#endif - -#if (G7_14PL >= G7_15PL) || (G7_14PL == 0) -#define MG7_15_114PL ~(1 << 13) -#else -#define MG7_15_114PL 0xFFFF -#endif - -#if (G7_16PL >= G7_15PL) || (G7_16PL == 0) -#define MG7_15_116PL ~(1 << 15) -#else -#define MG7_15_116PL 0xFFFF -#endif - -#define MG7_15_115PL 0xBFFF -#define MG7_15 (MG7_15_11PL & MG7_15_12PL & MG7_15_13PL & MG7_15_14PL & \ - MG7_15_15PL & MG7_15_16PL & MG7_15_17PL & MG7_15_18PL & \ - MG7_15_19PL & MG7_15_110PL & MG7_15_111PL & MG7_15_112PL & \ - MG7_15_113PL & MG7_15_114PL & MG7_15_115PL & MG7_15_116PL) -// End of MG7_15: -// Beginning of MG716: -#if (G7_1PL >= G7_16PL) || (G7_1PL == 0) -#define MG7_16_11PL ~(1 << 0) -#else -#define MG7_16_11PL 0xFFFF -#endif - -#if (G7_2PL >= G7_16PL) || (G7_2PL == 0) -#define MG7_16_12PL ~(1 << 1) -#else -#define MG7_16_12PL 0xFFFF -#endif - -#if (G7_3PL >= G7_16PL) || (G7_3PL == 0) -#define MG7_16_13PL ~(1 << 2) -#else -#define MG7_16_13PL 0xFFFF -#endif - -#if (G7_4PL >= G7_16PL) || (G7_4PL == 0) -#define MG7_16_14PL ~(1 << 3) -#else -#define MG7_16_14PL 0xFFFF -#endif - -#if (G7_5PL >= G7_16PL) || (G7_5PL == 0) -#define MG7_16_15PL ~(1 << 4) -#else -#define MG7_16_15PL 0xFFFF -#endif - -#if (G7_6PL >= G7_16PL) || (G7_6PL == 0) -#define MG7_16_16PL ~(1 << 5) -#else -#define MG7_16_16PL 0xFFFF -#endif - -#if (G7_7PL >= G7_16PL) || (G7_7PL == 0) -#define MG7_16_17PL ~(1 << 6) -#else -#define MG7_16_17PL 0xFFFF -#endif - -#if (G7_8PL >= G7_16PL) || (G7_8PL == 0) -#define MG7_16_18PL ~(1 << 7) -#else -#define MG7_16_18PL 0xFFFF -#endif - -#if (G7_9PL >= G7_16PL) || (G7_9PL == 0) -#define MG7_16_19PL ~(1 << 8) -#else -#define MG7_16_19PL 0xFFFF -#endif - -#if (G7_10PL >= G7_16PL) || (G7_10PL == 0) -#define MG7_16_110PL ~(1 << 9) -#else -#define MG7_16_110PL 0xFFFF -#endif - -#if (G7_11PL >= G7_16PL) || (G7_11PL == 0) -#define MG7_16_111PL ~(1 << 10) -#else -#define MG7_16_111PL 0xFFFF -#endif - -#if (G7_12PL >= G7_16PL) || (G7_12PL == 0) -#define MG7_16_112PL ~(1 << 11) -#else -#define MG7_16_112PL 0xFFFF -#endif - -#if (G7_13PL >= G7_16PL) || (G7_13PL == 0) -#define MG7_16_113PL ~(1 << 12) -#else -#define MG7_16_113PL 0xFFFF -#endif - -#if (G7_14PL >= G7_16PL) || (G7_14PL == 0) -#define MG7_16_114PL ~(1 << 13) -#else -#define MG7_16_114PL 0xFFFF -#endif - -#if (G7_15PL >= G7_16PL) || (G7_15PL == 0) -#define MG7_16_115PL ~(1 << 14) -#else -#define MG7_16_115PL 0xFFFF -#endif - -#define MG7_16_116PL 0x7FFF -#define MG7_16 (MG7_16_11PL & MG7_16_12PL & MG7_16_13PL & MG7_16_14PL & \ - MG7_16_15PL & MG7_16_16PL & MG7_16_17PL & MG7_16_18PL & \ - MG7_16_19PL & MG7_16_110PL & MG7_16_111PL & MG7_16_112PL & \ - MG7_16_113PL & MG7_16_114PL & MG7_16_115PL & MG7_16_116PL) -// End of MG7_16: - - -// -// Automatically generate PIEIER8 interrupt masks MG81 to MG816: -// - -// Beginning of MG81: -#if (G8_2PL >= G8_1PL) || (G8_2PL == 0) -#define MG8_1_12PL ~(1 << 1) -#else -#define MG8_1_12PL 0xFFFF -#endif - -#if (G8_3PL >= G8_1PL) || (G8_3PL == 0) -#define MG8_1_13PL ~(1 << 2) -#else -#define MG8_1_13PL 0xFFFF -#endif - -#if (G8_4PL >= G8_1PL) || (G8_4PL == 0) -#define MG8_1_14PL ~(1 << 3) -#else -#define MG8_1_14PL 0xFFFF -#endif - -#if (G8_5PL >= G8_1PL) || (G8_5PL == 0) -#define MG8_1_15PL ~(1 << 4) -#else -#define MG8_1_15PL 0xFFFF -#endif - -#if (G8_6PL >= G8_1PL) || (G8_6PL == 0) -#define MG8_1_16PL ~(1 << 5) -#else -#define MG8_1_16PL 0xFFFF -#endif - -#if (G8_7PL >= G8_1PL) || (G8_7PL == 0) -#define MG8_1_17PL ~(1 << 6) -#else -#define MG8_1_17PL 0xFFFF -#endif - -#if (G8_8PL >= G8_1PL) || (G8_8PL == 0) -#define MG8_1_18PL ~(1 << 7) -#else -#define MG8_1_18PL 0xFFFF -#endif - -#if (G8_9PL >= G8_1PL) || (G8_9PL == 0) -#define MG8_1_19PL ~(1 << 8) -#else -#define MG8_1_19PL 0xFFFF -#endif - -#if (G8_10PL >= G8_1PL) || (G8_10PL == 0) -#define MG8_1_110PL ~(1 << 9) -#else -#define MG8_1_110PL 0xFFFF -#endif - -#if (G8_11PL >= G8_1PL) || (G8_11PL == 0) -#define MG8_1_111PL ~(1 << 10) -#else -#define MG8_1_111PL 0xFFFF -#endif - -#if (G8_12PL >= G8_1PL) || (G8_12PL == 0) -#define MG8_1_112PL ~(1 << 11) -#else -#define MG8_1_112PL 0xFFFF -#endif - -#if (G8_13PL >= G8_1PL) || (G8_13PL == 0) -#define MG8_1_113PL ~(1 << 12) -#else -#define MG8_1_113PL 0xFFFF -#endif - -#if (G8_14PL >= G8_1PL) || (G8_14PL == 0) -#define MG8_1_114PL ~(1 << 13) -#else -#define MG8_1_114PL 0xFFFF -#endif - -#if (G8_15PL >= G8_1PL) || (G8_15PL == 0) -#define MG8_1_115PL ~(1 << 14) -#else -#define MG8_1_115PL 0xFFFF -#endif - -#if (G8_16PL >= G8_1PL) || (G8_16PL == 0) -#define MG8_1_116PL ~(1 << 15) -#else -#define MG8_1_116PL 0xFFFF -#endif - -#define MG8_1_11PL 0xFFFE -#define MG8_1 (MG8_1_11PL & MG8_1_12PL & MG8_1_13PL & MG8_1_14PL & \ - MG8_1_15PL & MG8_1_16PL & MG8_1_17PL & MG8_1_18PL & \ - MG8_1_19PL & MG8_1_110PL & MG8_1_111PL & MG8_1_112PL & \ - MG8_1_113PL & MG8_1_114PL & MG8_1_115PL & MG8_1_116PL) -// End of MG8_1: -// Beginning of MG82: -#if (G8_1PL >= G8_2PL) || (G8_1PL == 0) -#define MG8_2_11PL ~(1 << 0) -#else -#define MG8_2_11PL 0xFFFF -#endif - -#if (G8_3PL >= G8_2PL) || (G8_3PL == 0) -#define MG8_2_13PL ~(1 << 2) -#else -#define MG8_2_13PL 0xFFFF -#endif - -#if (G8_4PL >= G8_2PL) || (G8_4PL == 0) -#define MG8_2_14PL ~(1 << 3) -#else -#define MG8_2_14PL 0xFFFF -#endif - -#if (G8_5PL >= G8_2PL) || (G8_5PL == 0) -#define MG8_2_15PL ~(1 << 4) -#else -#define MG8_2_15PL 0xFFFF -#endif - -#if (G8_6PL >= G8_2PL) || (G8_6PL == 0) -#define MG8_2_16PL ~(1 << 5) -#else -#define MG8_2_16PL 0xFFFF -#endif - -#if (G8_7PL >= G8_2PL) || (G8_7PL == 0) -#define MG8_2_17PL ~(1 << 6) -#else -#define MG8_2_17PL 0xFFFF -#endif - -#if (G8_8PL >= G8_2PL) || (G8_8PL == 0) -#define MG8_2_18PL ~(1 << 7) -#else -#define MG8_2_18PL 0xFFFF -#endif - -#if (G8_9PL >= G8_2PL) || (G8_9PL == 0) -#define MG8_2_19PL ~(1 << 8) -#else -#define MG8_2_19PL 0xFFFF -#endif - -#if (G8_10PL >= G8_2PL) || (G8_10PL == 0) -#define MG8_2_110PL ~(1 << 9) -#else -#define MG8_2_110PL 0xFFFF -#endif - -#if (G8_11PL >= G8_2PL) || (G8_11PL == 0) -#define MG8_2_111PL ~(1 << 10) -#else -#define MG8_2_111PL 0xFFFF -#endif - -#if (G8_12PL >= G8_2PL) || (G8_12PL == 0) -#define MG8_2_112PL ~(1 << 11) -#else -#define MG8_2_112PL 0xFFFF -#endif - -#if (G8_13PL >= G8_2PL) || (G8_13PL == 0) -#define MG8_2_113PL ~(1 << 12) -#else -#define MG8_2_113PL 0xFFFF -#endif - -#if (G8_14PL >= G8_2PL) || (G8_14PL == 0) -#define MG8_2_114PL ~(1 << 13) -#else -#define MG8_2_114PL 0xFFFF -#endif - -#if (G8_15PL >= G8_2PL) || (G8_15PL == 0) -#define MG8_2_115PL ~(1 << 14) -#else -#define MG8_2_115PL 0xFFFF -#endif - -#if (G8_16PL >= G8_2PL) || (G8_16PL == 0) -#define MG8_2_116PL ~(1 << 15) -#else -#define MG8_2_116PL 0xFFFF -#endif - -#define MG8_2_12PL 0xFFFD -#define MG8_2 (MG8_2_11PL & MG8_2_12PL & MG8_2_13PL & MG8_2_14PL & \ - MG8_2_15PL & MG8_2_16PL & MG8_2_17PL & MG8_2_18PL & \ - MG8_2_19PL & MG8_2_110PL & MG8_2_111PL & MG8_2_112PL & \ - MG8_2_113PL & MG8_2_114PL & MG8_2_115PL & MG8_2_116PL) -// End of MG8_2: -// Beginning of MG83: -#if (G8_1PL >= G8_3PL) || (G8_1PL == 0) -#define MG8_3_11PL ~(1 << 0) -#else -#define MG8_3_11PL 0xFFFF -#endif - -#if (G8_2PL >= G8_3PL) || (G8_2PL == 0) -#define MG8_3_12PL ~(1 << 1) -#else -#define MG8_3_12PL 0xFFFF -#endif - -#if (G8_4PL >= G8_3PL) || (G8_4PL == 0) -#define MG8_3_14PL ~(1 << 3) -#else -#define MG8_3_14PL 0xFFFF -#endif - -#if (G8_5PL >= G8_3PL) || (G8_5PL == 0) -#define MG8_3_15PL ~(1 << 4) -#else -#define MG8_3_15PL 0xFFFF -#endif - -#if (G8_6PL >= G8_3PL) || (G8_6PL == 0) -#define MG8_3_16PL ~(1 << 5) -#else -#define MG8_3_16PL 0xFFFF -#endif - -#if (G8_7PL >= G8_3PL) || (G8_7PL == 0) -#define MG8_3_17PL ~(1 << 6) -#else -#define MG8_3_17PL 0xFFFF -#endif - -#if (G8_8PL >= G8_3PL) || (G8_8PL == 0) -#define MG8_3_18PL ~(1 << 7) -#else -#define MG8_3_18PL 0xFFFF -#endif - -#if (G8_9PL >= G8_3PL) || (G8_9PL == 0) -#define MG8_3_19PL ~(1 << 8) -#else -#define MG8_3_19PL 0xFFFF -#endif - -#if (G8_10PL >= G8_3PL) || (G8_10PL == 0) -#define MG8_3_110PL ~(1 << 9) -#else -#define MG8_3_110PL 0xFFFF -#endif - -#if (G8_11PL >= G8_3PL) || (G8_11PL == 0) -#define MG8_3_111PL ~(1 << 10) -#else -#define MG8_3_111PL 0xFFFF -#endif - -#if (G8_12PL >= G8_3PL) || (G8_12PL == 0) -#define MG8_3_112PL ~(1 << 11) -#else -#define MG8_3_112PL 0xFFFF -#endif - -#if (G8_13PL >= G8_3PL) || (G8_13PL == 0) -#define MG8_3_113PL ~(1 << 12) -#else -#define MG8_3_113PL 0xFFFF -#endif - -#if (G8_14PL >= G8_3PL) || (G8_14PL == 0) -#define MG8_3_114PL ~(1 << 13) -#else -#define MG8_3_114PL 0xFFFF -#endif - -#if (G8_15PL >= G8_3PL) || (G8_15PL == 0) -#define MG8_3_115PL ~(1 << 14) -#else -#define MG8_3_115PL 0xFFFF -#endif - -#if (G8_16PL >= G8_3PL) || (G8_16PL == 0) -#define MG8_3_116PL ~(1 << 15) -#else -#define MG8_3_116PL 0xFFFF -#endif - -#define MG8_3_13PL 0xFFFB -#define MG8_3 (MG8_3_11PL & MG8_3_12PL & MG8_3_13PL & MG8_3_14PL & \ - MG8_3_15PL & MG8_3_16PL & MG8_3_17PL & MG8_3_18PL & \ - MG8_3_19PL & MG8_3_110PL & MG8_3_111PL & MG8_3_112PL & \ - MG8_3_113PL & MG8_3_114PL & MG8_3_115PL & MG8_3_116PL) -// End of MG8_3: -// Beginning of MG84: -#if (G8_1PL >= G8_4PL) || (G8_1PL == 0) -#define MG8_4_11PL ~(1 << 0) -#else -#define MG8_4_11PL 0xFFFF -#endif - -#if (G8_2PL >= G8_4PL) || (G8_2PL == 0) -#define MG8_4_12PL ~(1 << 1) -#else -#define MG8_4_12PL 0xFFFF -#endif - -#if (G8_3PL >= G8_4PL) || (G8_3PL == 0) -#define MG8_4_13PL ~(1 << 2) -#else -#define MG8_4_13PL 0xFFFF -#endif - -#if (G8_5PL >= G8_4PL) || (G8_5PL == 0) -#define MG8_4_15PL ~(1 << 4) -#else -#define MG8_4_15PL 0xFFFF -#endif - -#if (G8_6PL >= G8_4PL) || (G8_6PL == 0) -#define MG8_4_16PL ~(1 << 5) -#else -#define MG8_4_16PL 0xFFFF -#endif - -#if (G8_7PL >= G8_4PL) || (G8_7PL == 0) -#define MG8_4_17PL ~(1 << 6) -#else -#define MG8_4_17PL 0xFFFF -#endif - -#if (G8_8PL >= G8_4PL) || (G8_8PL == 0) -#define MG8_4_18PL ~(1 << 7) -#else -#define MG8_4_18PL 0xFFFF -#endif - -#if (G8_9PL >= G8_4PL) || (G8_9PL == 0) -#define MG8_4_19PL ~(1 << 8) -#else -#define MG8_4_19PL 0xFFFF -#endif - -#if (G8_10PL >= G8_4PL) || (G8_10PL == 0) -#define MG8_4_110PL ~(1 << 9) -#else -#define MG8_4_110PL 0xFFFF -#endif - -#if (G8_11PL >= G8_4PL) || (G8_11PL == 0) -#define MG8_4_111PL ~(1 << 10) -#else -#define MG8_4_111PL 0xFFFF -#endif - -#if (G8_12PL >= G8_4PL) || (G8_12PL == 0) -#define MG8_4_112PL ~(1 << 11) -#else -#define MG8_4_112PL 0xFFFF -#endif - -#if (G8_13PL >= G8_4PL) || (G8_13PL == 0) -#define MG8_4_113PL ~(1 << 12) -#else -#define MG8_4_113PL 0xFFFF -#endif - -#if (G8_14PL >= G8_4PL) || (G8_14PL == 0) -#define MG8_4_114PL ~(1 << 13) -#else -#define MG8_4_114PL 0xFFFF -#endif - -#if (G8_15PL >= G8_4PL) || (G8_15PL == 0) -#define MG8_4_115PL ~(1 << 14) -#else -#define MG8_4_115PL 0xFFFF -#endif - -#if (G8_16PL >= G8_4PL) || (G8_16PL == 0) -#define MG8_4_116PL ~(1 << 15) -#else -#define MG8_4_116PL 0xFFFF -#endif - -#define MG8_4_14PL 0xFFF7 -#define MG8_4 (MG8_4_11PL & MG8_4_12PL & MG8_4_13PL & MG8_4_14PL & \ - MG8_4_15PL & MG8_4_16PL & MG8_4_17PL & MG8_4_18PL & \ - MG8_4_19PL & MG8_4_110PL & MG8_4_111PL & MG8_4_112PL & \ - MG8_4_113PL & MG8_4_114PL & MG8_4_115PL & MG8_4_116PL) -// End of MG8_4: -// Beginning of MG85: -#if (G8_1PL >= G8_5PL) || (G8_1PL == 0) -#define MG8_5_11PL ~(1 << 0) -#else -#define MG8_5_11PL 0xFFFF -#endif - -#if (G8_2PL >= G8_5PL) || (G8_2PL == 0) -#define MG8_5_12PL ~(1 << 1) -#else -#define MG8_5_12PL 0xFFFF -#endif - -#if (G8_3PL >= G8_5PL) || (G8_3PL == 0) -#define MG8_5_13PL ~(1 << 2) -#else -#define MG8_5_13PL 0xFFFF -#endif - -#if (G8_4PL >= G8_5PL) || (G8_4PL == 0) -#define MG8_5_14PL ~(1 << 3) -#else -#define MG8_5_14PL 0xFFFF -#endif - -#if (G8_6PL >= G8_5PL) || (G8_6PL == 0) -#define MG8_5_16PL ~(1 << 5) -#else -#define MG8_5_16PL 0xFFFF -#endif - -#if (G8_7PL >= G8_5PL) || (G8_7PL == 0) -#define MG8_5_17PL ~(1 << 6) -#else -#define MG8_5_17PL 0xFFFF -#endif - -#if (G8_8PL >= G8_5PL) || (G8_8PL == 0) -#define MG8_5_18PL ~(1 << 7) -#else -#define MG8_5_18PL 0xFFFF -#endif - -#if (G8_9PL >= G8_5PL) || (G8_9PL == 0) -#define MG8_5_19PL ~(1 << 8) -#else -#define MG8_5_19PL 0xFFFF -#endif - -#if (G8_10PL >= G8_5PL) || (G8_10PL == 0) -#define MG8_5_110PL ~(1 << 9) -#else -#define MG8_5_110PL 0xFFFF -#endif - -#if (G8_11PL >= G8_5PL) || (G8_11PL == 0) -#define MG8_5_111PL ~(1 << 10) -#else -#define MG8_5_111PL 0xFFFF -#endif - -#if (G8_12PL >= G8_5PL) || (G8_12PL == 0) -#define MG8_5_112PL ~(1 << 11) -#else -#define MG8_5_112PL 0xFFFF -#endif - -#if (G8_13PL >= G8_5PL) || (G8_13PL == 0) -#define MG8_5_113PL ~(1 << 12) -#else -#define MG8_5_113PL 0xFFFF -#endif - -#if (G8_14PL >= G8_5PL) || (G8_14PL == 0) -#define MG8_5_114PL ~(1 << 13) -#else -#define MG8_5_114PL 0xFFFF -#endif - -#if (G8_15PL >= G8_5PL) || (G8_15PL == 0) -#define MG8_5_115PL ~(1 << 14) -#else -#define MG8_5_115PL 0xFFFF -#endif - -#if (G8_16PL >= G8_5PL) || (G8_16PL == 0) -#define MG8_5_116PL ~(1 << 15) -#else -#define MG8_5_116PL 0xFFFF -#endif - -#define MG8_5_15PL 0xFFEF -#define MG8_5 (MG8_5_11PL & MG8_5_12PL & MG8_5_13PL & MG8_5_14PL & \ - MG8_5_15PL & MG8_5_16PL & MG8_5_17PL & MG8_5_18PL & \ - MG8_5_19PL & MG8_5_110PL & MG8_5_111PL & MG8_5_112PL & \ - MG8_5_113PL & MG8_5_114PL & MG8_5_115PL & MG8_5_116PL) -// End of MG8_5: -// Beginning of MG86: -#if (G8_1PL >= G8_6PL) || (G8_1PL == 0) -#define MG8_6_11PL ~(1 << 0) -#else -#define MG8_6_11PL 0xFFFF -#endif - -#if (G8_2PL >= G8_6PL) || (G8_2PL == 0) -#define MG8_6_12PL ~(1 << 1) -#else -#define MG8_6_12PL 0xFFFF -#endif - -#if (G8_3PL >= G8_6PL) || (G8_3PL == 0) -#define MG8_6_13PL ~(1 << 2) -#else -#define MG8_6_13PL 0xFFFF -#endif - -#if (G8_4PL >= G8_6PL) || (G8_4PL == 0) -#define MG8_6_14PL ~(1 << 3) -#else -#define MG8_6_14PL 0xFFFF -#endif - -#if (G8_5PL >= G8_6PL) || (G8_5PL == 0) -#define MG8_6_15PL ~(1 << 4) -#else -#define MG8_6_15PL 0xFFFF -#endif - -#if (G8_7PL >= G8_6PL) || (G8_7PL == 0) -#define MG8_6_17PL ~(1 << 6) -#else -#define MG8_6_17PL 0xFFFF -#endif - -#if (G8_8PL >= G8_6PL) || (G8_8PL == 0) -#define MG8_6_18PL ~(1 << 7) -#else -#define MG8_6_18PL 0xFFFF -#endif - -#if (G8_9PL >= G8_6PL) || (G8_9PL == 0) -#define MG8_6_19PL ~(1 << 8) -#else -#define MG8_6_19PL 0xFFFF -#endif - -#if (G8_10PL >= G8_6PL) || (G8_10PL == 0) -#define MG8_6_110PL ~(1 << 9) -#else -#define MG8_6_110PL 0xFFFF -#endif - -#if (G8_11PL >= G8_6PL) || (G8_11PL == 0) -#define MG8_6_111PL ~(1 << 10) -#else -#define MG8_6_111PL 0xFFFF -#endif - -#if (G8_12PL >= G8_6PL) || (G8_12PL == 0) -#define MG8_6_112PL ~(1 << 11) -#else -#define MG8_6_112PL 0xFFFF -#endif - -#if (G8_13PL >= G8_6PL) || (G8_13PL == 0) -#define MG8_6_113PL ~(1 << 12) -#else -#define MG8_6_113PL 0xFFFF -#endif - -#if (G8_14PL >= G8_6PL) || (G8_14PL == 0) -#define MG8_6_114PL ~(1 << 13) -#else -#define MG8_6_114PL 0xFFFF -#endif - -#if (G8_15PL >= G8_6PL) || (G8_15PL == 0) -#define MG8_6_115PL ~(1 << 14) -#else -#define MG8_6_115PL 0xFFFF -#endif - -#if (G8_16PL >= G8_6PL) || (G8_16PL == 0) -#define MG8_6_116PL ~(1 << 15) -#else -#define MG8_6_116PL 0xFFFF -#endif - -#define MG8_6_16PL 0xFFDF -#define MG8_6 (MG8_6_11PL & MG8_6_12PL & MG8_6_13PL & MG8_6_14PL & \ - MG8_6_15PL & MG8_6_16PL & MG8_6_17PL & MG8_6_18PL & \ - MG8_6_19PL & MG8_6_110PL & MG8_6_111PL & MG8_6_112PL & \ - MG8_6_113PL & MG8_6_114PL & MG8_6_115PL & MG8_6_116PL) -// End of MG8_6: -// Beginning of MG87: -#if (G8_1PL >= G8_7PL) || (G8_1PL == 0) -#define MG8_7_11PL ~(1 << 0) -#else -#define MG8_7_11PL 0xFFFF -#endif - -#if (G8_2PL >= G8_7PL) || (G8_2PL == 0) -#define MG8_7_12PL ~(1 << 1) -#else -#define MG8_7_12PL 0xFFFF -#endif - -#if (G8_3PL >= G8_7PL) || (G8_3PL == 0) -#define MG8_7_13PL ~(1 << 2) -#else -#define MG8_7_13PL 0xFFFF -#endif - -#if (G8_4PL >= G8_7PL) || (G8_4PL == 0) -#define MG8_7_14PL ~(1 << 3) -#else -#define MG8_7_14PL 0xFFFF -#endif - -#if (G8_5PL >= G8_7PL) || (G8_5PL == 0) -#define MG8_7_15PL ~(1 << 4) -#else -#define MG8_7_15PL 0xFFFF -#endif - -#if (G8_6PL >= G8_7PL) || (G8_6PL == 0) -#define MG8_7_16PL ~(1 << 5) -#else -#define MG8_7_16PL 0xFFFF -#endif - -#if (G8_8PL >= G8_7PL) || (G8_8PL == 0) -#define MG8_7_18PL ~(1 << 7) -#else -#define MG8_7_18PL 0xFFFF -#endif - -#if (G8_9PL >= G8_7PL) || (G8_9PL == 0) -#define MG8_7_19PL ~(1 << 8) -#else -#define MG8_7_19PL 0xFFFF -#endif - -#if (G8_10PL >= G8_7PL) || (G8_10PL == 0) -#define MG8_7_110PL ~(1 << 9) -#else -#define MG8_7_110PL 0xFFFF -#endif - -#if (G8_11PL >= G8_7PL) || (G8_11PL == 0) -#define MG8_7_111PL ~(1 << 10) -#else -#define MG8_7_111PL 0xFFFF -#endif - -#if (G8_12PL >= G8_7PL) || (G8_12PL == 0) -#define MG8_7_112PL ~(1 << 11) -#else -#define MG8_7_112PL 0xFFFF -#endif - -#if (G8_13PL >= G8_7PL) || (G8_13PL == 0) -#define MG8_7_113PL ~(1 << 12) -#else -#define MG8_7_113PL 0xFFFF -#endif - -#if (G8_14PL >= G8_7PL) || (G8_14PL == 0) -#define MG8_7_114PL ~(1 << 13) -#else -#define MG8_7_114PL 0xFFFF -#endif - -#if (G8_15PL >= G8_7PL) || (G8_15PL == 0) -#define MG8_7_115PL ~(1 << 14) -#else -#define MG8_7_115PL 0xFFFF -#endif - -#if (G8_16PL >= G8_7PL) || (G8_16PL == 0) -#define MG8_7_116PL ~(1 << 15) -#else -#define MG8_7_116PL 0xFFFF -#endif - -#define MG8_7_17PL 0xFFBF -#define MG8_7 (MG8_7_11PL & MG8_7_12PL & MG8_7_13PL & MG8_7_14PL & \ - MG8_7_15PL & MG8_7_16PL & MG8_7_17PL & MG8_7_18PL & \ - MG8_7_19PL & MG8_7_110PL & MG8_7_111PL & MG8_7_112PL & \ - MG8_7_113PL & MG8_7_114PL & MG8_7_115PL & MG8_7_116PL) -// End of MG8_7: -// Beginning of MG88: -#if (G8_1PL >= G8_8PL) || (G8_1PL == 0) -#define MG8_8_11PL ~(1 << 0) -#else -#define MG8_8_11PL 0xFFFF -#endif - -#if (G8_2PL >= G8_8PL) || (G8_2PL == 0) -#define MG8_8_12PL ~(1 << 1) -#else -#define MG8_8_12PL 0xFFFF -#endif - -#if (G8_3PL >= G8_8PL) || (G8_3PL == 0) -#define MG8_8_13PL ~(1 << 2) -#else -#define MG8_8_13PL 0xFFFF -#endif - -#if (G8_4PL >= G8_8PL) || (G8_4PL == 0) -#define MG8_8_14PL ~(1 << 3) -#else -#define MG8_8_14PL 0xFFFF -#endif - -#if (G8_5PL >= G8_8PL) || (G8_5PL == 0) -#define MG8_8_15PL ~(1 << 4) -#else -#define MG8_8_15PL 0xFFFF -#endif - -#if (G8_6PL >= G8_8PL) || (G8_6PL == 0) -#define MG8_8_16PL ~(1 << 5) -#else -#define MG8_8_16PL 0xFFFF -#endif - -#if (G8_7PL >= G8_8PL) || (G8_7PL == 0) -#define MG8_8_17PL ~(1 << 6) -#else -#define MG8_8_17PL 0xFFFF -#endif - -#if (G8_9PL >= G8_8PL) || (G8_9PL == 0) -#define MG8_8_19PL ~(1 << 8) -#else -#define MG8_8_19PL 0xFFFF -#endif - -#if (G8_10PL >= G8_8PL) || (G8_10PL == 0) -#define MG8_8_110PL ~(1 << 9) -#else -#define MG8_8_110PL 0xFFFF -#endif - -#if (G8_11PL >= G8_8PL) || (G8_11PL == 0) -#define MG8_8_111PL ~(1 << 10) -#else -#define MG8_8_111PL 0xFFFF -#endif - -#if (G8_12PL >= G8_8PL) || (G8_12PL == 0) -#define MG8_8_112PL ~(1 << 11) -#else -#define MG8_8_112PL 0xFFFF -#endif - -#if (G8_13PL >= G8_8PL) || (G8_13PL == 0) -#define MG8_8_113PL ~(1 << 12) -#else -#define MG8_8_113PL 0xFFFF -#endif - -#if (G8_14PL >= G8_8PL) || (G8_14PL == 0) -#define MG8_8_114PL ~(1 << 13) -#else -#define MG8_8_114PL 0xFFFF -#endif - -#if (G8_15PL >= G8_8PL) || (G8_15PL == 0) -#define MG8_8_115PL ~(1 << 14) -#else -#define MG8_8_115PL 0xFFFF -#endif - -#if (G8_16PL >= G8_8PL) || (G8_16PL == 0) -#define MG8_8_116PL ~(1 << 15) -#else -#define MG8_8_116PL 0xFFFF -#endif - -#define MG8_8_18PL 0xFF7F -#define MG8_8 (MG8_8_11PL & MG8_8_12PL & MG8_8_13PL & MG8_8_14PL & \ - MG8_8_15PL & MG8_8_16PL & MG8_8_17PL & MG8_8_18PL & \ - MG8_8_19PL & MG8_8_110PL & MG8_8_111PL & MG8_8_112PL & \ - MG8_8_113PL & MG8_8_114PL & MG8_8_115PL & MG8_8_116PL) -// End of MG8_8: -// Beginning of MG89: -#if (G8_1PL >= G8_9PL) || (G8_1PL == 0) -#define MG8_9_11PL ~(1 << 0) -#else -#define MG8_9_11PL 0xFFFF -#endif - -#if (G8_2PL >= G8_9PL) || (G8_2PL == 0) -#define MG8_9_12PL ~(1 << 1) -#else -#define MG8_9_12PL 0xFFFF -#endif - -#if (G8_3PL >= G8_9PL) || (G8_3PL == 0) -#define MG8_9_13PL ~(1 << 2) -#else -#define MG8_9_13PL 0xFFFF -#endif - -#if (G8_4PL >= G8_9PL) || (G8_4PL == 0) -#define MG8_9_14PL ~(1 << 3) -#else -#define MG8_9_14PL 0xFFFF -#endif - -#if (G8_5PL >= G8_9PL) || (G8_5PL == 0) -#define MG8_9_15PL ~(1 << 4) -#else -#define MG8_9_15PL 0xFFFF -#endif - -#if (G8_6PL >= G8_9PL) || (G8_6PL == 0) -#define MG8_9_16PL ~(1 << 5) -#else -#define MG8_9_16PL 0xFFFF -#endif - -#if (G8_7PL >= G8_9PL) || (G8_7PL == 0) -#define MG8_9_17PL ~(1 << 6) -#else -#define MG8_9_17PL 0xFFFF -#endif - -#if (G8_8PL >= G8_9PL) || (G8_8PL == 0) -#define MG8_9_18PL ~(1 << 7) -#else -#define MG8_9_18PL 0xFFFF -#endif - -#if (G8_10PL >= G8_9PL) || (G8_10PL == 0) -#define MG8_9_110PL ~(1 << 9) -#else -#define MG8_9_110PL 0xFFFF -#endif - -#if (G8_11PL >= G8_9PL) || (G8_11PL == 0) -#define MG8_9_111PL ~(1 << 10) -#else -#define MG8_9_111PL 0xFFFF -#endif - -#if (G8_12PL >= G8_9PL) || (G8_12PL == 0) -#define MG8_9_112PL ~(1 << 11) -#else -#define MG8_9_112PL 0xFFFF -#endif - -#if (G8_13PL >= G8_9PL) || (G8_13PL == 0) -#define MG8_9_113PL ~(1 << 12) -#else -#define MG8_9_113PL 0xFFFF -#endif - -#if (G8_14PL >= G8_9PL) || (G8_14PL == 0) -#define MG8_9_114PL ~(1 << 13) -#else -#define MG8_9_114PL 0xFFFF -#endif - -#if (G8_15PL >= G8_9PL) || (G8_15PL == 0) -#define MG8_9_115PL ~(1 << 14) -#else -#define MG8_9_115PL 0xFFFF -#endif - -#if (G8_16PL >= G8_9PL) || (G8_16PL == 0) -#define MG8_9_116PL ~(1 << 15) -#else -#define MG8_9_116PL 0xFFFF -#endif - -#define MG8_9_19PL 0xFEFF -#define MG8_9 (MG8_9_11PL & MG8_9_12PL & MG8_9_13PL & MG8_9_14PL & \ - MG8_9_15PL & MG8_9_16PL & MG8_9_17PL & MG8_9_18PL & \ - MG8_9_19PL & MG8_9_110PL & MG8_9_111PL & MG8_9_112PL & \ - MG8_9_113PL & MG8_9_114PL & MG8_9_115PL & MG8_9_116PL) -// End of MG8_9: -// Beginning of MG810: -#if (G8_1PL >= G8_10PL) || (G8_1PL == 0) -#define MG8_10_11PL ~(1 << 0) -#else -#define MG8_10_11PL 0xFFFF -#endif - -#if (G8_2PL >= G8_10PL) || (G8_2PL == 0) -#define MG8_10_12PL ~(1 << 1) -#else -#define MG8_10_12PL 0xFFFF -#endif - -#if (G8_3PL >= G8_10PL) || (G8_3PL == 0) -#define MG8_10_13PL ~(1 << 2) -#else -#define MG8_10_13PL 0xFFFF -#endif - -#if (G8_4PL >= G8_10PL) || (G8_4PL == 0) -#define MG8_10_14PL ~(1 << 3) -#else -#define MG8_10_14PL 0xFFFF -#endif - -#if (G8_5PL >= G8_10PL) || (G8_5PL == 0) -#define MG8_10_15PL ~(1 << 4) -#else -#define MG8_10_15PL 0xFFFF -#endif - -#if (G8_6PL >= G8_10PL) || (G8_6PL == 0) -#define MG8_10_16PL ~(1 << 5) -#else -#define MG8_10_16PL 0xFFFF -#endif - -#if (G8_7PL >= G8_10PL) || (G8_7PL == 0) -#define MG8_10_17PL ~(1 << 6) -#else -#define MG8_10_17PL 0xFFFF -#endif - -#if (G8_8PL >= G8_10PL) || (G8_8PL == 0) -#define MG8_10_18PL ~(1 << 7) -#else -#define MG8_10_18PL 0xFFFF -#endif - -#if (G8_9PL >= G8_10PL) || (G8_9PL == 0) -#define MG8_10_19PL ~(1 << 8) -#else -#define MG8_10_19PL 0xFFFF -#endif - -#if (G8_11PL >= G8_10PL) || (G8_11PL == 0) -#define MG8_10_111PL ~(1 << 10) -#else -#define MG8_10_111PL 0xFFFF -#endif - -#if (G8_12PL >= G8_10PL) || (G8_12PL == 0) -#define MG8_10_112PL ~(1 << 11) -#else -#define MG8_10_112PL 0xFFFF -#endif - -#if (G8_13PL >= G8_10PL) || (G8_13PL == 0) -#define MG8_10_113PL ~(1 << 12) -#else -#define MG8_10_113PL 0xFFFF -#endif - -#if (G8_14PL >= G8_10PL) || (G8_14PL == 0) -#define MG8_10_114PL ~(1 << 13) -#else -#define MG8_10_114PL 0xFFFF -#endif - -#if (G8_15PL >= G8_10PL) || (G8_15PL == 0) -#define MG8_10_115PL ~(1 << 14) -#else -#define MG8_10_115PL 0xFFFF -#endif - -#if (G8_16PL >= G8_10PL) || (G8_16PL == 0) -#define MG8_10_116PL ~(1 << 15) -#else -#define MG8_10_116PL 0xFFFF -#endif - -#define MG8_10_110PL 0xFDFF -#define MG8_10 (MG8_10_11PL & MG8_10_12PL & MG8_10_13PL & MG8_10_14PL & \ - MG8_10_15PL & MG8_10_16PL & MG8_10_17PL & MG8_10_18PL & \ - MG8_10_19PL & MG8_10_110PL & MG8_10_111PL & MG8_10_112PL & \ - MG8_10_113PL & MG8_10_114PL & MG8_10_115PL & MG8_10_116PL) -// End of MG8_10: -// Beginning of MG811: -#if (G8_1PL >= G8_11PL) || (G8_1PL == 0) -#define MG8_11_11PL ~(1 << 0) -#else -#define MG8_11_11PL 0xFFFF -#endif - -#if (G8_2PL >= G8_11PL) || (G8_2PL == 0) -#define MG8_11_12PL ~(1 << 1) -#else -#define MG8_11_12PL 0xFFFF -#endif - -#if (G8_3PL >= G8_11PL) || (G8_3PL == 0) -#define MG8_11_13PL ~(1 << 2) -#else -#define MG8_11_13PL 0xFFFF -#endif - -#if (G8_4PL >= G8_11PL) || (G8_4PL == 0) -#define MG8_11_14PL ~(1 << 3) -#else -#define MG8_11_14PL 0xFFFF -#endif - -#if (G8_5PL >= G8_11PL) || (G8_5PL == 0) -#define MG8_11_15PL ~(1 << 4) -#else -#define MG8_11_15PL 0xFFFF -#endif - -#if (G8_6PL >= G8_11PL) || (G8_6PL == 0) -#define MG8_11_16PL ~(1 << 5) -#else -#define MG8_11_16PL 0xFFFF -#endif - -#if (G8_7PL >= G8_11PL) || (G8_7PL == 0) -#define MG8_11_17PL ~(1 << 6) -#else -#define MG8_11_17PL 0xFFFF -#endif - -#if (G8_8PL >= G8_11PL) || (G8_8PL == 0) -#define MG8_11_18PL ~(1 << 7) -#else -#define MG8_11_18PL 0xFFFF -#endif - -#if (G8_9PL >= G8_11PL) || (G8_9PL == 0) -#define MG8_11_19PL ~(1 << 8) -#else -#define MG8_11_19PL 0xFFFF -#endif - -#if (G8_10PL >= G8_11PL) || (G8_10PL == 0) -#define MG8_11_110PL ~(1 << 9) -#else -#define MG8_11_110PL 0xFFFF -#endif - -#if (G8_12PL >= G8_11PL) || (G8_12PL == 0) -#define MG8_11_112PL ~(1 << 11) -#else -#define MG8_11_112PL 0xFFFF -#endif - -#if (G8_13PL >= G8_11PL) || (G8_13PL == 0) -#define MG8_11_113PL ~(1 << 12) -#else -#define MG8_11_113PL 0xFFFF -#endif - -#if (G8_14PL >= G8_11PL) || (G8_14PL == 0) -#define MG8_11_114PL ~(1 << 13) -#else -#define MG8_11_114PL 0xFFFF -#endif - -#if (G8_15PL >= G8_11PL) || (G8_15PL == 0) -#define MG8_11_115PL ~(1 << 14) -#else -#define MG8_11_115PL 0xFFFF -#endif - -#if (G8_16PL >= G8_11PL) || (G8_16PL == 0) -#define MG8_11_116PL ~(1 << 15) -#else -#define MG8_11_116PL 0xFFFF -#endif - -#define MG8_11_111PL 0xFBFF -#define MG8_11 (MG8_11_11PL & MG8_11_12PL & MG8_11_13PL & MG8_11_14PL & \ - MG8_11_15PL & MG8_11_16PL & MG8_11_17PL & MG8_11_18PL & \ - MG8_11_19PL & MG8_11_110PL & MG8_11_111PL & MG8_11_112PL & \ - MG8_11_113PL & MG8_11_114PL & MG8_11_115PL & MG8_11_116PL) -// End of MG8_11: -// Beginning of MG812: -#if (G8_1PL >= G8_12PL) || (G8_1PL == 0) -#define MG8_12_11PL ~(1 << 0) -#else -#define MG8_12_11PL 0xFFFF -#endif - -#if (G8_2PL >= G8_12PL) || (G8_2PL == 0) -#define MG8_12_12PL ~(1 << 1) -#else -#define MG8_12_12PL 0xFFFF -#endif - -#if (G8_3PL >= G8_12PL) || (G8_3PL == 0) -#define MG8_12_13PL ~(1 << 2) -#else -#define MG8_12_13PL 0xFFFF -#endif - -#if (G8_4PL >= G8_12PL) || (G8_4PL == 0) -#define MG8_12_14PL ~(1 << 3) -#else -#define MG8_12_14PL 0xFFFF -#endif - -#if (G8_5PL >= G8_12PL) || (G8_5PL == 0) -#define MG8_12_15PL ~(1 << 4) -#else -#define MG8_12_15PL 0xFFFF -#endif - -#if (G8_6PL >= G8_12PL) || (G8_6PL == 0) -#define MG8_12_16PL ~(1 << 5) -#else -#define MG8_12_16PL 0xFFFF -#endif - -#if (G8_7PL >= G8_12PL) || (G8_7PL == 0) -#define MG8_12_17PL ~(1 << 6) -#else -#define MG8_12_17PL 0xFFFF -#endif - -#if (G8_8PL >= G8_12PL) || (G8_8PL == 0) -#define MG8_12_18PL ~(1 << 7) -#else -#define MG8_12_18PL 0xFFFF -#endif - -#if (G8_9PL >= G8_12PL) || (G8_9PL == 0) -#define MG8_12_19PL ~(1 << 8) -#else -#define MG8_12_19PL 0xFFFF -#endif - -#if (G8_10PL >= G8_12PL) || (G8_10PL == 0) -#define MG8_12_110PL ~(1 << 9) -#else -#define MG8_12_110PL 0xFFFF -#endif - -#if (G8_11PL >= G8_12PL) || (G8_11PL == 0) -#define MG8_12_111PL ~(1 << 10) -#else -#define MG8_12_111PL 0xFFFF -#endif - -#if (G8_13PL >= G8_12PL) || (G8_13PL == 0) -#define MG8_12_113PL ~(1 << 12) -#else -#define MG8_12_113PL 0xFFFF -#endif - -#if (G8_14PL >= G8_12PL) || (G8_14PL == 0) -#define MG8_12_114PL ~(1 << 13) -#else -#define MG8_12_114PL 0xFFFF -#endif - -#if (G8_15PL >= G8_12PL) || (G8_15PL == 0) -#define MG8_12_115PL ~(1 << 14) -#else -#define MG8_12_115PL 0xFFFF -#endif - -#if (G8_16PL >= G8_12PL) || (G8_16PL == 0) -#define MG8_12_116PL ~(1 << 15) -#else -#define MG8_12_116PL 0xFFFF -#endif - -#define MG8_12_112PL 0xF7FF -#define MG8_12 (MG8_12_11PL & MG8_12_12PL & MG8_12_13PL & MG8_12_14PL & \ - MG8_12_15PL & MG8_12_16PL & MG8_12_17PL & MG8_12_18PL & \ - MG8_12_19PL & MG8_12_110PL & MG8_12_111PL & MG8_12_112PL & \ - MG8_12_113PL & MG8_12_114PL & MG8_12_115PL & MG8_12_116PL) -// End of MG8_12: -// Beginning of MG813: -#if (G8_1PL >= G8_13PL) || (G8_1PL == 0) -#define MG8_13_11PL ~(1 << 0) -#else -#define MG8_13_11PL 0xFFFF -#endif - -#if (G8_2PL >= G8_13PL) || (G8_2PL == 0) -#define MG8_13_12PL ~(1 << 1) -#else -#define MG8_13_12PL 0xFFFF -#endif - -#if (G8_3PL >= G8_13PL) || (G8_3PL == 0) -#define MG8_13_13PL ~(1 << 2) -#else -#define MG8_13_13PL 0xFFFF -#endif - -#if (G8_4PL >= G8_13PL) || (G8_4PL == 0) -#define MG8_13_14PL ~(1 << 3) -#else -#define MG8_13_14PL 0xFFFF -#endif - -#if (G8_5PL >= G8_13PL) || (G8_5PL == 0) -#define MG8_13_15PL ~(1 << 4) -#else -#define MG8_13_15PL 0xFFFF -#endif - -#if (G8_6PL >= G8_13PL) || (G8_6PL == 0) -#define MG8_13_16PL ~(1 << 5) -#else -#define MG8_13_16PL 0xFFFF -#endif - -#if (G8_7PL >= G8_13PL) || (G8_7PL == 0) -#define MG8_13_17PL ~(1 << 6) -#else -#define MG8_13_17PL 0xFFFF -#endif - -#if (G8_8PL >= G8_13PL) || (G8_8PL == 0) -#define MG8_13_18PL ~(1 << 7) -#else -#define MG8_13_18PL 0xFFFF -#endif - -#if (G8_9PL >= G8_13PL) || (G8_9PL == 0) -#define MG8_13_19PL ~(1 << 8) -#else -#define MG8_13_19PL 0xFFFF -#endif - -#if (G8_10PL >= G8_13PL) || (G8_10PL == 0) -#define MG8_13_110PL ~(1 << 9) -#else -#define MG8_13_110PL 0xFFFF -#endif - -#if (G8_11PL >= G8_13PL) || (G8_11PL == 0) -#define MG8_13_111PL ~(1 << 10) -#else -#define MG8_13_111PL 0xFFFF -#endif - -#if (G8_12PL >= G8_13PL) || (G8_12PL == 0) -#define MG8_13_112PL ~(1 << 11) -#else -#define MG8_13_112PL 0xFFFF -#endif - -#if (G8_14PL >= G8_13PL) || (G8_14PL == 0) -#define MG8_13_114PL ~(1 << 13) -#else -#define MG8_13_114PL 0xFFFF -#endif - -#if (G8_15PL >= G8_13PL) || (G8_15PL == 0) -#define MG8_13_115PL ~(1 << 14) -#else -#define MG8_13_115PL 0xFFFF -#endif - -#if (G8_16PL >= G8_13PL) || (G8_16PL == 0) -#define MG8_13_116PL ~(1 << 15) -#else -#define MG8_13_116PL 0xFFFF -#endif - -#define MG8_13_113PL 0xEFFF -#define MG8_13 (MG8_13_11PL & MG8_13_12PL & MG8_13_13PL & MG8_13_14PL & \ - MG8_13_15PL & MG8_13_16PL & MG8_13_17PL & MG8_13_18PL & \ - MG8_13_19PL & MG8_13_110PL & MG8_13_111PL & MG8_13_112PL & \ - MG8_13_113PL & MG8_13_114PL & MG8_13_115PL & MG8_13_116PL) -// End of MG8_13: -// Beginning of MG814: -#if (G8_1PL >= G8_14PL) || (G8_1PL == 0) -#define MG8_14_11PL ~(1 << 0) -#else -#define MG8_14_11PL 0xFFFF -#endif - -#if (G8_2PL >= G8_14PL) || (G8_2PL == 0) -#define MG8_14_12PL ~(1 << 1) -#else -#define MG8_14_12PL 0xFFFF -#endif - -#if (G8_3PL >= G8_14PL) || (G8_3PL == 0) -#define MG8_14_13PL ~(1 << 2) -#else -#define MG8_14_13PL 0xFFFF -#endif - -#if (G8_4PL >= G8_14PL) || (G8_4PL == 0) -#define MG8_14_14PL ~(1 << 3) -#else -#define MG8_14_14PL 0xFFFF -#endif - -#if (G8_5PL >= G8_14PL) || (G8_5PL == 0) -#define MG8_14_15PL ~(1 << 4) -#else -#define MG8_14_15PL 0xFFFF -#endif - -#if (G8_6PL >= G8_14PL) || (G8_6PL == 0) -#define MG8_14_16PL ~(1 << 5) -#else -#define MG8_14_16PL 0xFFFF -#endif - -#if (G8_7PL >= G8_14PL) || (G8_7PL == 0) -#define MG8_14_17PL ~(1 << 6) -#else -#define MG8_14_17PL 0xFFFF -#endif - -#if (G8_8PL >= G8_14PL) || (G8_8PL == 0) -#define MG8_14_18PL ~(1 << 7) -#else -#define MG8_14_18PL 0xFFFF -#endif - -#if (G8_9PL >= G8_14PL) || (G8_9PL == 0) -#define MG8_14_19PL ~(1 << 8) -#else -#define MG8_14_19PL 0xFFFF -#endif - -#if (G8_10PL >= G8_14PL) || (G8_10PL == 0) -#define MG8_14_110PL ~(1 << 9) -#else -#define MG8_14_110PL 0xFFFF -#endif - -#if (G8_11PL >= G8_14PL) || (G8_11PL == 0) -#define MG8_14_111PL ~(1 << 10) -#else -#define MG8_14_111PL 0xFFFF -#endif - -#if (G8_12PL >= G8_14PL) || (G8_12PL == 0) -#define MG8_14_112PL ~(1 << 11) -#else -#define MG8_14_112PL 0xFFFF -#endif - -#if (G8_13PL >= G8_14PL) || (G8_13PL == 0) -#define MG8_14_113PL ~(1 << 12) -#else -#define MG8_14_113PL 0xFFFF -#endif - -#if (G8_15PL >= G8_14PL) || (G8_15PL == 0) -#define MG8_14_115PL ~(1 << 14) -#else -#define MG8_14_115PL 0xFFFF -#endif - -#if (G8_16PL >= G8_14PL) || (G8_16PL == 0) -#define MG8_14_116PL ~(1 << 15) -#else -#define MG8_14_116PL 0xFFFF -#endif - -#define MG8_14_114PL 0xDFFF -#define MG8_14 (MG8_14_11PL & MG8_14_12PL & MG8_14_13PL & MG8_14_14PL & \ - MG8_14_15PL & MG8_14_16PL & MG8_14_17PL & MG8_14_18PL & \ - MG8_14_19PL & MG8_14_110PL & MG8_14_111PL & MG8_14_112PL & \ - MG8_14_113PL & MG8_14_114PL & MG8_14_115PL & MG8_14_116PL) -// End of MG8_14: -// Beginning of MG815: -#if (G8_1PL >= G8_15PL) || (G8_1PL == 0) -#define MG8_15_11PL ~(1 << 0) -#else -#define MG8_15_11PL 0xFFFF -#endif - -#if (G8_2PL >= G8_15PL) || (G8_2PL == 0) -#define MG8_15_12PL ~(1 << 1) -#else -#define MG8_15_12PL 0xFFFF -#endif - -#if (G8_3PL >= G8_15PL) || (G8_3PL == 0) -#define MG8_15_13PL ~(1 << 2) -#else -#define MG8_15_13PL 0xFFFF -#endif - -#if (G8_4PL >= G8_15PL) || (G8_4PL == 0) -#define MG8_15_14PL ~(1 << 3) -#else -#define MG8_15_14PL 0xFFFF -#endif - -#if (G8_5PL >= G8_15PL) || (G8_5PL == 0) -#define MG8_15_15PL ~(1 << 4) -#else -#define MG8_15_15PL 0xFFFF -#endif - -#if (G8_6PL >= G8_15PL) || (G8_6PL == 0) -#define MG8_15_16PL ~(1 << 5) -#else -#define MG8_15_16PL 0xFFFF -#endif - -#if (G8_7PL >= G8_15PL) || (G8_7PL == 0) -#define MG8_15_17PL ~(1 << 6) -#else -#define MG8_15_17PL 0xFFFF -#endif - -#if (G8_8PL >= G8_15PL) || (G8_8PL == 0) -#define MG8_15_18PL ~(1 << 7) -#else -#define MG8_15_18PL 0xFFFF -#endif - -#if (G8_9PL >= G8_15PL) || (G8_9PL == 0) -#define MG8_15_19PL ~(1 << 8) -#else -#define MG8_15_19PL 0xFFFF -#endif - -#if (G8_10PL >= G8_15PL) || (G8_10PL == 0) -#define MG8_15_110PL ~(1 << 9) -#else -#define MG8_15_110PL 0xFFFF -#endif - -#if (G8_11PL >= G8_15PL) || (G8_11PL == 0) -#define MG8_15_111PL ~(1 << 10) -#else -#define MG8_15_111PL 0xFFFF -#endif - -#if (G8_12PL >= G8_15PL) || (G8_12PL == 0) -#define MG8_15_112PL ~(1 << 11) -#else -#define MG8_15_112PL 0xFFFF -#endif - -#if (G8_13PL >= G8_15PL) || (G8_13PL == 0) -#define MG8_15_113PL ~(1 << 12) -#else -#define MG8_15_113PL 0xFFFF -#endif - -#if (G8_14PL >= G8_15PL) || (G8_14PL == 0) -#define MG8_15_114PL ~(1 << 13) -#else -#define MG8_15_114PL 0xFFFF -#endif - -#if (G8_16PL >= G8_15PL) || (G8_16PL == 0) -#define MG8_15_116PL ~(1 << 15) -#else -#define MG8_15_116PL 0xFFFF -#endif - -#define MG8_15_115PL 0xBFFF -#define MG8_15 (MG8_15_11PL & MG8_15_12PL & MG8_15_13PL & MG8_15_14PL & \ - MG8_15_15PL & MG8_15_16PL & MG8_15_17PL & MG8_15_18PL & \ - MG8_15_19PL & MG8_15_110PL & MG8_15_111PL & MG8_15_112PL & \ - MG8_15_113PL & MG8_15_114PL & MG8_15_115PL & MG8_15_116PL) -// End of MG8_15: -// Beginning of MG816: -#if (G8_1PL >= G8_16PL) || (G8_1PL == 0) -#define MG8_16_11PL ~(1 << 0) -#else -#define MG8_16_11PL 0xFFFF -#endif - -#if (G8_2PL >= G8_16PL) || (G8_2PL == 0) -#define MG8_16_12PL ~(1 << 1) -#else -#define MG8_16_12PL 0xFFFF -#endif - -#if (G8_3PL >= G8_16PL) || (G8_3PL == 0) -#define MG8_16_13PL ~(1 << 2) -#else -#define MG8_16_13PL 0xFFFF -#endif - -#if (G8_4PL >= G8_16PL) || (G8_4PL == 0) -#define MG8_16_14PL ~(1 << 3) -#else -#define MG8_16_14PL 0xFFFF -#endif - -#if (G8_5PL >= G8_16PL) || (G8_5PL == 0) -#define MG8_16_15PL ~(1 << 4) -#else -#define MG8_16_15PL 0xFFFF -#endif - -#if (G8_6PL >= G8_16PL) || (G8_6PL == 0) -#define MG8_16_16PL ~(1 << 5) -#else -#define MG8_16_16PL 0xFFFF -#endif - -#if (G8_7PL >= G8_16PL) || (G8_7PL == 0) -#define MG8_16_17PL ~(1 << 6) -#else -#define MG8_16_17PL 0xFFFF -#endif - -#if (G8_8PL >= G8_16PL) || (G8_8PL == 0) -#define MG8_16_18PL ~(1 << 7) -#else -#define MG8_16_18PL 0xFFFF -#endif - -#if (G8_9PL >= G8_16PL) || (G8_9PL == 0) -#define MG8_16_19PL ~(1 << 8) -#else -#define MG8_16_19PL 0xFFFF -#endif - -#if (G8_10PL >= G8_16PL) || (G8_10PL == 0) -#define MG8_16_110PL ~(1 << 9) -#else -#define MG8_16_110PL 0xFFFF -#endif - -#if (G8_11PL >= G8_16PL) || (G8_11PL == 0) -#define MG8_16_111PL ~(1 << 10) -#else -#define MG8_16_111PL 0xFFFF -#endif - -#if (G8_12PL >= G8_16PL) || (G8_12PL == 0) -#define MG8_16_112PL ~(1 << 11) -#else -#define MG8_16_112PL 0xFFFF -#endif - -#if (G8_13PL >= G8_16PL) || (G8_13PL == 0) -#define MG8_16_113PL ~(1 << 12) -#else -#define MG8_16_113PL 0xFFFF -#endif - -#if (G8_14PL >= G8_16PL) || (G8_14PL == 0) -#define MG8_16_114PL ~(1 << 13) -#else -#define MG8_16_114PL 0xFFFF -#endif - -#if (G8_15PL >= G8_16PL) || (G8_15PL == 0) -#define MG8_16_115PL ~(1 << 14) -#else -#define MG8_16_115PL 0xFFFF -#endif - -#define MG8_16_116PL 0x7FFF -#define MG8_16 (MG8_16_11PL & MG8_16_12PL & MG8_16_13PL & MG8_16_14PL & \ - MG8_16_15PL & MG8_16_16PL & MG8_16_17PL & MG8_16_18PL & \ - MG8_16_19PL & MG8_16_110PL & MG8_16_111PL & MG8_16_112PL & \ - MG8_16_113PL & MG8_16_114PL & MG8_16_115PL & MG8_16_116PL) -// End of MG8_16: - - -// -// Automatically generate PIEIER9 interrupt masks MG91 to MG916: -// - -// Beginning of MG91: -#if (G9_2PL >= G9_1PL) || (G9_2PL == 0) -#define MG9_1_12PL ~(1 << 1) -#else -#define MG9_1_12PL 0xFFFF -#endif - -#if (G9_3PL >= G9_1PL) || (G9_3PL == 0) -#define MG9_1_13PL ~(1 << 2) -#else -#define MG9_1_13PL 0xFFFF -#endif - -#if (G9_4PL >= G9_1PL) || (G9_4PL == 0) -#define MG9_1_14PL ~(1 << 3) -#else -#define MG9_1_14PL 0xFFFF -#endif - -#if (G9_5PL >= G9_1PL) || (G9_5PL == 0) -#define MG9_1_15PL ~(1 << 4) -#else -#define MG9_1_15PL 0xFFFF -#endif - -#if (G9_6PL >= G9_1PL) || (G9_6PL == 0) -#define MG9_1_16PL ~(1 << 5) -#else -#define MG9_1_16PL 0xFFFF -#endif - -#if (G9_7PL >= G9_1PL) || (G9_7PL == 0) -#define MG9_1_17PL ~(1 << 6) -#else -#define MG9_1_17PL 0xFFFF -#endif - -#if (G9_8PL >= G9_1PL) || (G9_8PL == 0) -#define MG9_1_18PL ~(1 << 7) -#else -#define MG9_1_18PL 0xFFFF -#endif - -#if (G9_9PL >= G9_1PL) || (G9_9PL == 0) -#define MG9_1_19PL ~(1 << 8) -#else -#define MG9_1_19PL 0xFFFF -#endif - -#if (G9_10PL >= G9_1PL) || (G9_10PL == 0) -#define MG9_1_110PL ~(1 << 9) -#else -#define MG9_1_110PL 0xFFFF -#endif - -#if (G9_11PL >= G9_1PL) || (G9_11PL == 0) -#define MG9_1_111PL ~(1 << 10) -#else -#define MG9_1_111PL 0xFFFF -#endif - -#if (G9_12PL >= G9_1PL) || (G9_12PL == 0) -#define MG9_1_112PL ~(1 << 11) -#else -#define MG9_1_112PL 0xFFFF -#endif - -#if (G9_13PL >= G9_1PL) || (G9_13PL == 0) -#define MG9_1_113PL ~(1 << 12) -#else -#define MG9_1_113PL 0xFFFF -#endif - -#if (G9_14PL >= G9_1PL) || (G9_14PL == 0) -#define MG9_1_114PL ~(1 << 13) -#else -#define MG9_1_114PL 0xFFFF -#endif - -#if (G9_15PL >= G9_1PL) || (G9_15PL == 0) -#define MG9_1_115PL ~(1 << 14) -#else -#define MG9_1_115PL 0xFFFF -#endif - -#if (G9_16PL >= G9_1PL) || (G9_16PL == 0) -#define MG9_1_116PL ~(1 << 15) -#else -#define MG9_1_116PL 0xFFFF -#endif - -#define MG9_1_11PL 0xFFFE -#define MG9_1 (MG9_1_11PL & MG9_1_12PL & MG9_1_13PL & MG9_1_14PL & \ - MG9_1_15PL & MG9_1_16PL & MG9_1_17PL & MG9_1_18PL & \ - MG9_1_19PL & MG9_1_110PL & MG9_1_111PL & MG9_1_112PL & \ - MG9_1_113PL & MG9_1_114PL & MG9_1_115PL & MG9_1_116PL) -// End of MG9_1: -// Beginning of MG92: -#if (G9_1PL >= G9_2PL) || (G9_1PL == 0) -#define MG9_2_11PL ~(1 << 0) -#else -#define MG9_2_11PL 0xFFFF -#endif - -#if (G9_3PL >= G9_2PL) || (G9_3PL == 0) -#define MG9_2_13PL ~(1 << 2) -#else -#define MG9_2_13PL 0xFFFF -#endif - -#if (G9_4PL >= G9_2PL) || (G9_4PL == 0) -#define MG9_2_14PL ~(1 << 3) -#else -#define MG9_2_14PL 0xFFFF -#endif - -#if (G9_5PL >= G9_2PL) || (G9_5PL == 0) -#define MG9_2_15PL ~(1 << 4) -#else -#define MG9_2_15PL 0xFFFF -#endif - -#if (G9_6PL >= G9_2PL) || (G9_6PL == 0) -#define MG9_2_16PL ~(1 << 5) -#else -#define MG9_2_16PL 0xFFFF -#endif - -#if (G9_7PL >= G9_2PL) || (G9_7PL == 0) -#define MG9_2_17PL ~(1 << 6) -#else -#define MG9_2_17PL 0xFFFF -#endif - -#if (G9_8PL >= G9_2PL) || (G9_8PL == 0) -#define MG9_2_18PL ~(1 << 7) -#else -#define MG9_2_18PL 0xFFFF -#endif - -#if (G9_9PL >= G9_2PL) || (G9_9PL == 0) -#define MG9_2_19PL ~(1 << 8) -#else -#define MG9_2_19PL 0xFFFF -#endif - -#if (G9_10PL >= G9_2PL) || (G9_10PL == 0) -#define MG9_2_110PL ~(1 << 9) -#else -#define MG9_2_110PL 0xFFFF -#endif - -#if (G9_11PL >= G9_2PL) || (G9_11PL == 0) -#define MG9_2_111PL ~(1 << 10) -#else -#define MG9_2_111PL 0xFFFF -#endif - -#if (G9_12PL >= G9_2PL) || (G9_12PL == 0) -#define MG9_2_112PL ~(1 << 11) -#else -#define MG9_2_112PL 0xFFFF -#endif - -#if (G9_13PL >= G9_2PL) || (G9_13PL == 0) -#define MG9_2_113PL ~(1 << 12) -#else -#define MG9_2_113PL 0xFFFF -#endif - -#if (G9_14PL >= G9_2PL) || (G9_14PL == 0) -#define MG9_2_114PL ~(1 << 13) -#else -#define MG9_2_114PL 0xFFFF -#endif - -#if (G9_15PL >= G9_2PL) || (G9_15PL == 0) -#define MG9_2_115PL ~(1 << 14) -#else -#define MG9_2_115PL 0xFFFF -#endif - -#if (G9_16PL >= G9_2PL) || (G9_16PL == 0) -#define MG9_2_116PL ~(1 << 15) -#else -#define MG9_2_116PL 0xFFFF -#endif - -#define MG9_2_12PL 0xFFFD -#define MG9_2 (MG9_2_11PL & MG9_2_12PL & MG9_2_13PL & MG9_2_14PL & \ - MG9_2_15PL & MG9_2_16PL & MG9_2_17PL & MG9_2_18PL & \ - MG9_2_19PL & MG9_2_110PL & MG9_2_111PL & MG9_2_112PL & \ - MG9_2_113PL & MG9_2_114PL & MG9_2_115PL & MG9_2_116PL) -// End of MG9_2: -// Beginning of MG93: -#if (G9_1PL >= G9_3PL) || (G9_1PL == 0) -#define MG9_3_11PL ~(1 << 0) -#else -#define MG9_3_11PL 0xFFFF -#endif - -#if (G9_2PL >= G9_3PL) || (G9_2PL == 0) -#define MG9_3_12PL ~(1 << 1) -#else -#define MG9_3_12PL 0xFFFF -#endif - -#if (G9_4PL >= G9_3PL) || (G9_4PL == 0) -#define MG9_3_14PL ~(1 << 3) -#else -#define MG9_3_14PL 0xFFFF -#endif - -#if (G9_5PL >= G9_3PL) || (G9_5PL == 0) -#define MG9_3_15PL ~(1 << 4) -#else -#define MG9_3_15PL 0xFFFF -#endif - -#if (G9_6PL >= G9_3PL) || (G9_6PL == 0) -#define MG9_3_16PL ~(1 << 5) -#else -#define MG9_3_16PL 0xFFFF -#endif - -#if (G9_7PL >= G9_3PL) || (G9_7PL == 0) -#define MG9_3_17PL ~(1 << 6) -#else -#define MG9_3_17PL 0xFFFF -#endif - -#if (G9_8PL >= G9_3PL) || (G9_8PL == 0) -#define MG9_3_18PL ~(1 << 7) -#else -#define MG9_3_18PL 0xFFFF -#endif - -#if (G9_9PL >= G9_3PL) || (G9_9PL == 0) -#define MG9_3_19PL ~(1 << 8) -#else -#define MG9_3_19PL 0xFFFF -#endif - -#if (G9_10PL >= G9_3PL) || (G9_10PL == 0) -#define MG9_3_110PL ~(1 << 9) -#else -#define MG9_3_110PL 0xFFFF -#endif - -#if (G9_11PL >= G9_3PL) || (G9_11PL == 0) -#define MG9_3_111PL ~(1 << 10) -#else -#define MG9_3_111PL 0xFFFF -#endif - -#if (G9_12PL >= G9_3PL) || (G9_12PL == 0) -#define MG9_3_112PL ~(1 << 11) -#else -#define MG9_3_112PL 0xFFFF -#endif - -#if (G9_13PL >= G9_3PL) || (G9_13PL == 0) -#define MG9_3_113PL ~(1 << 12) -#else -#define MG9_3_113PL 0xFFFF -#endif - -#if (G9_14PL >= G9_3PL) || (G9_14PL == 0) -#define MG9_3_114PL ~(1 << 13) -#else -#define MG9_3_114PL 0xFFFF -#endif - -#if (G9_15PL >= G9_3PL) || (G9_15PL == 0) -#define MG9_3_115PL ~(1 << 14) -#else -#define MG9_3_115PL 0xFFFF -#endif - -#if (G9_16PL >= G9_3PL) || (G9_16PL == 0) -#define MG9_3_116PL ~(1 << 15) -#else -#define MG9_3_116PL 0xFFFF -#endif - -#define MG9_3_13PL 0xFFFB -#define MG9_3 (MG9_3_11PL & MG9_3_12PL & MG9_3_13PL & MG9_3_14PL & \ - MG9_3_15PL & MG9_3_16PL & MG9_3_17PL & MG9_3_18PL & \ - MG9_3_19PL & MG9_3_110PL & MG9_3_111PL & MG9_3_112PL & \ - MG9_3_113PL & MG9_3_114PL & MG9_3_115PL & MG9_3_116PL) -// End of MG9_3: -// Beginning of MG94: -#if (G9_1PL >= G9_4PL) || (G9_1PL == 0) -#define MG9_4_11PL ~(1 << 0) -#else -#define MG9_4_11PL 0xFFFF -#endif - -#if (G9_2PL >= G9_4PL) || (G9_2PL == 0) -#define MG9_4_12PL ~(1 << 1) -#else -#define MG9_4_12PL 0xFFFF -#endif - -#if (G9_3PL >= G9_4PL) || (G9_3PL == 0) -#define MG9_4_13PL ~(1 << 2) -#else -#define MG9_4_13PL 0xFFFF -#endif - -#if (G9_5PL >= G9_4PL) || (G9_5PL == 0) -#define MG9_4_15PL ~(1 << 4) -#else -#define MG9_4_15PL 0xFFFF -#endif - -#if (G9_6PL >= G9_4PL) || (G9_6PL == 0) -#define MG9_4_16PL ~(1 << 5) -#else -#define MG9_4_16PL 0xFFFF -#endif - -#if (G9_7PL >= G9_4PL) || (G9_7PL == 0) -#define MG9_4_17PL ~(1 << 6) -#else -#define MG9_4_17PL 0xFFFF -#endif - -#if (G9_8PL >= G9_4PL) || (G9_8PL == 0) -#define MG9_4_18PL ~(1 << 7) -#else -#define MG9_4_18PL 0xFFFF -#endif - -#if (G9_9PL >= G9_4PL) || (G9_9PL == 0) -#define MG9_4_19PL ~(1 << 8) -#else -#define MG9_4_19PL 0xFFFF -#endif - -#if (G9_10PL >= G9_4PL) || (G9_10PL == 0) -#define MG9_4_110PL ~(1 << 9) -#else -#define MG9_4_110PL 0xFFFF -#endif - -#if (G9_11PL >= G9_4PL) || (G9_11PL == 0) -#define MG9_4_111PL ~(1 << 10) -#else -#define MG9_4_111PL 0xFFFF -#endif - -#if (G9_12PL >= G9_4PL) || (G9_12PL == 0) -#define MG9_4_112PL ~(1 << 11) -#else -#define MG9_4_112PL 0xFFFF -#endif - -#if (G9_13PL >= G9_4PL) || (G9_13PL == 0) -#define MG9_4_113PL ~(1 << 12) -#else -#define MG9_4_113PL 0xFFFF -#endif - -#if (G9_14PL >= G9_4PL) || (G9_14PL == 0) -#define MG9_4_114PL ~(1 << 13) -#else -#define MG9_4_114PL 0xFFFF -#endif - -#if (G9_15PL >= G9_4PL) || (G9_15PL == 0) -#define MG9_4_115PL ~(1 << 14) -#else -#define MG9_4_115PL 0xFFFF -#endif - -#if (G9_16PL >= G9_4PL) || (G9_16PL == 0) -#define MG9_4_116PL ~(1 << 15) -#else -#define MG9_4_116PL 0xFFFF -#endif - -#define MG9_4_14PL 0xFFF7 -#define MG9_4 (MG9_4_11PL & MG9_4_12PL & MG9_4_13PL & MG9_4_14PL & \ - MG9_4_15PL & MG9_4_16PL & MG9_4_17PL & MG9_4_18PL & \ - MG9_4_19PL & MG9_4_110PL & MG9_4_111PL & MG9_4_112PL & \ - MG9_4_113PL & MG9_4_114PL & MG9_4_115PL & MG9_4_116PL) -// End of MG9_4: -// Beginning of MG95: -#if (G9_1PL >= G9_5PL) || (G9_1PL == 0) -#define MG9_5_11PL ~(1 << 0) -#else -#define MG9_5_11PL 0xFFFF -#endif - -#if (G9_2PL >= G9_5PL) || (G9_2PL == 0) -#define MG9_5_12PL ~(1 << 1) -#else -#define MG9_5_12PL 0xFFFF -#endif - -#if (G9_3PL >= G9_5PL) || (G9_3PL == 0) -#define MG9_5_13PL ~(1 << 2) -#else -#define MG9_5_13PL 0xFFFF -#endif - -#if (G9_4PL >= G9_5PL) || (G9_4PL == 0) -#define MG9_5_14PL ~(1 << 3) -#else -#define MG9_5_14PL 0xFFFF -#endif - -#if (G9_6PL >= G9_5PL) || (G9_6PL == 0) -#define MG9_5_16PL ~(1 << 5) -#else -#define MG9_5_16PL 0xFFFF -#endif - -#if (G9_7PL >= G9_5PL) || (G9_7PL == 0) -#define MG9_5_17PL ~(1 << 6) -#else -#define MG9_5_17PL 0xFFFF -#endif - -#if (G9_8PL >= G9_5PL) || (G9_8PL == 0) -#define MG9_5_18PL ~(1 << 7) -#else -#define MG9_5_18PL 0xFFFF -#endif - -#if (G9_9PL >= G9_5PL) || (G9_9PL == 0) -#define MG9_5_19PL ~(1 << 8) -#else -#define MG9_5_19PL 0xFFFF -#endif - -#if (G9_10PL >= G9_5PL) || (G9_10PL == 0) -#define MG9_5_110PL ~(1 << 9) -#else -#define MG9_5_110PL 0xFFFF -#endif - -#if (G9_11PL >= G9_5PL) || (G9_11PL == 0) -#define MG9_5_111PL ~(1 << 10) -#else -#define MG9_5_111PL 0xFFFF -#endif - -#if (G9_12PL >= G9_5PL) || (G9_12PL == 0) -#define MG9_5_112PL ~(1 << 11) -#else -#define MG9_5_112PL 0xFFFF -#endif - -#if (G9_13PL >= G9_5PL) || (G9_13PL == 0) -#define MG9_5_113PL ~(1 << 12) -#else -#define MG9_5_113PL 0xFFFF -#endif - -#if (G9_14PL >= G9_5PL) || (G9_14PL == 0) -#define MG9_5_114PL ~(1 << 13) -#else -#define MG9_5_114PL 0xFFFF -#endif - -#if (G9_15PL >= G9_5PL) || (G9_15PL == 0) -#define MG9_5_115PL ~(1 << 14) -#else -#define MG9_5_115PL 0xFFFF -#endif - -#if (G9_16PL >= G9_5PL) || (G9_16PL == 0) -#define MG9_5_116PL ~(1 << 15) -#else -#define MG9_5_116PL 0xFFFF -#endif - -#define MG9_5_15PL 0xFFEF -#define MG9_5 (MG9_5_11PL & MG9_5_12PL & MG9_5_13PL & MG9_5_14PL & \ - MG9_5_15PL & MG9_5_16PL & MG9_5_17PL & MG9_5_18PL & \ - MG9_5_19PL & MG9_5_110PL & MG9_5_111PL & MG9_5_112PL & \ - MG9_5_113PL & MG9_5_114PL & MG9_5_115PL & MG9_5_116PL) -// End of MG9_5: -// Beginning of MG96: -#if (G9_1PL >= G9_6PL) || (G9_1PL == 0) -#define MG9_6_11PL ~(1 << 0) -#else -#define MG9_6_11PL 0xFFFF -#endif - -#if (G9_2PL >= G9_6PL) || (G9_2PL == 0) -#define MG9_6_12PL ~(1 << 1) -#else -#define MG9_6_12PL 0xFFFF -#endif - -#if (G9_3PL >= G9_6PL) || (G9_3PL == 0) -#define MG9_6_13PL ~(1 << 2) -#else -#define MG9_6_13PL 0xFFFF -#endif - -#if (G9_4PL >= G9_6PL) || (G9_4PL == 0) -#define MG9_6_14PL ~(1 << 3) -#else -#define MG9_6_14PL 0xFFFF -#endif - -#if (G9_5PL >= G9_6PL) || (G9_5PL == 0) -#define MG9_6_15PL ~(1 << 4) -#else -#define MG9_6_15PL 0xFFFF -#endif - -#if (G9_7PL >= G9_6PL) || (G9_7PL == 0) -#define MG9_6_17PL ~(1 << 6) -#else -#define MG9_6_17PL 0xFFFF -#endif - -#if (G9_8PL >= G9_6PL) || (G9_8PL == 0) -#define MG9_6_18PL ~(1 << 7) -#else -#define MG9_6_18PL 0xFFFF -#endif - -#if (G9_9PL >= G9_6PL) || (G9_9PL == 0) -#define MG9_6_19PL ~(1 << 8) -#else -#define MG9_6_19PL 0xFFFF -#endif - -#if (G9_10PL >= G9_6PL) || (G9_10PL == 0) -#define MG9_6_110PL ~(1 << 9) -#else -#define MG9_6_110PL 0xFFFF -#endif - -#if (G9_11PL >= G9_6PL) || (G9_11PL == 0) -#define MG9_6_111PL ~(1 << 10) -#else -#define MG9_6_111PL 0xFFFF -#endif - -#if (G9_12PL >= G9_6PL) || (G9_12PL == 0) -#define MG9_6_112PL ~(1 << 11) -#else -#define MG9_6_112PL 0xFFFF -#endif - -#if (G9_13PL >= G9_6PL) || (G9_13PL == 0) -#define MG9_6_113PL ~(1 << 12) -#else -#define MG9_6_113PL 0xFFFF -#endif - -#if (G9_14PL >= G9_6PL) || (G9_14PL == 0) -#define MG9_6_114PL ~(1 << 13) -#else -#define MG9_6_114PL 0xFFFF -#endif - -#if (G9_15PL >= G9_6PL) || (G9_15PL == 0) -#define MG9_6_115PL ~(1 << 14) -#else -#define MG9_6_115PL 0xFFFF -#endif - -#if (G9_16PL >= G9_6PL) || (G9_16PL == 0) -#define MG9_6_116PL ~(1 << 15) -#else -#define MG9_6_116PL 0xFFFF -#endif - -#define MG9_6_16PL 0xFFDF -#define MG9_6 (MG9_6_11PL & MG9_6_12PL & MG9_6_13PL & MG9_6_14PL & \ - MG9_6_15PL & MG9_6_16PL & MG9_6_17PL & MG9_6_18PL & \ - MG9_6_19PL & MG9_6_110PL & MG9_6_111PL & MG9_6_112PL & \ - MG9_6_113PL & MG9_6_114PL & MG9_6_115PL & MG9_6_116PL) -// End of MG9_6: -// Beginning of MG97: -#if (G9_1PL >= G9_7PL) || (G9_1PL == 0) -#define MG9_7_11PL ~(1 << 0) -#else -#define MG9_7_11PL 0xFFFF -#endif - -#if (G9_2PL >= G9_7PL) || (G9_2PL == 0) -#define MG9_7_12PL ~(1 << 1) -#else -#define MG9_7_12PL 0xFFFF -#endif - -#if (G9_3PL >= G9_7PL) || (G9_3PL == 0) -#define MG9_7_13PL ~(1 << 2) -#else -#define MG9_7_13PL 0xFFFF -#endif - -#if (G9_4PL >= G9_7PL) || (G9_4PL == 0) -#define MG9_7_14PL ~(1 << 3) -#else -#define MG9_7_14PL 0xFFFF -#endif - -#if (G9_5PL >= G9_7PL) || (G9_5PL == 0) -#define MG9_7_15PL ~(1 << 4) -#else -#define MG9_7_15PL 0xFFFF -#endif - -#if (G9_6PL >= G9_7PL) || (G9_6PL == 0) -#define MG9_7_16PL ~(1 << 5) -#else -#define MG9_7_16PL 0xFFFF -#endif - -#if (G9_8PL >= G9_7PL) || (G9_8PL == 0) -#define MG9_7_18PL ~(1 << 7) -#else -#define MG9_7_18PL 0xFFFF -#endif - -#if (G9_9PL >= G9_7PL) || (G9_9PL == 0) -#define MG9_7_19PL ~(1 << 8) -#else -#define MG9_7_19PL 0xFFFF -#endif - -#if (G9_10PL >= G9_7PL) || (G9_10PL == 0) -#define MG9_7_110PL ~(1 << 9) -#else -#define MG9_7_110PL 0xFFFF -#endif - -#if (G9_11PL >= G9_7PL) || (G9_11PL == 0) -#define MG9_7_111PL ~(1 << 10) -#else -#define MG9_7_111PL 0xFFFF -#endif - -#if (G9_12PL >= G9_7PL) || (G9_12PL == 0) -#define MG9_7_112PL ~(1 << 11) -#else -#define MG9_7_112PL 0xFFFF -#endif - -#if (G9_13PL >= G9_7PL) || (G9_13PL == 0) -#define MG9_7_113PL ~(1 << 12) -#else -#define MG9_7_113PL 0xFFFF -#endif - -#if (G9_14PL >= G9_7PL) || (G9_14PL == 0) -#define MG9_7_114PL ~(1 << 13) -#else -#define MG9_7_114PL 0xFFFF -#endif - -#if (G9_15PL >= G9_7PL) || (G9_15PL == 0) -#define MG9_7_115PL ~(1 << 14) -#else -#define MG9_7_115PL 0xFFFF -#endif - -#if (G9_16PL >= G9_7PL) || (G9_16PL == 0) -#define MG9_7_116PL ~(1 << 15) -#else -#define MG9_7_116PL 0xFFFF -#endif - -#define MG9_7_17PL 0xFFBF -#define MG9_7 (MG9_7_11PL & MG9_7_12PL & MG9_7_13PL & MG9_7_14PL & \ - MG9_7_15PL & MG9_7_16PL & MG9_7_17PL & MG9_7_18PL & \ - MG9_7_19PL & MG9_7_110PL & MG9_7_111PL & MG9_7_112PL & \ - MG9_7_113PL & MG9_7_114PL & MG9_7_115PL & MG9_7_116PL) -// End of MG9_7: -// Beginning of MG98: -#if (G9_1PL >= G9_8PL) || (G9_1PL == 0) -#define MG9_8_11PL ~(1 << 0) -#else -#define MG9_8_11PL 0xFFFF -#endif - -#if (G9_2PL >= G9_8PL) || (G9_2PL == 0) -#define MG9_8_12PL ~(1 << 1) -#else -#define MG9_8_12PL 0xFFFF -#endif - -#if (G9_3PL >= G9_8PL) || (G9_3PL == 0) -#define MG9_8_13PL ~(1 << 2) -#else -#define MG9_8_13PL 0xFFFF -#endif - -#if (G9_4PL >= G9_8PL) || (G9_4PL == 0) -#define MG9_8_14PL ~(1 << 3) -#else -#define MG9_8_14PL 0xFFFF -#endif - -#if (G9_5PL >= G9_8PL) || (G9_5PL == 0) -#define MG9_8_15PL ~(1 << 4) -#else -#define MG9_8_15PL 0xFFFF -#endif - -#if (G9_6PL >= G9_8PL) || (G9_6PL == 0) -#define MG9_8_16PL ~(1 << 5) -#else -#define MG9_8_16PL 0xFFFF -#endif - -#if (G9_7PL >= G9_8PL) || (G9_7PL == 0) -#define MG9_8_17PL ~(1 << 6) -#else -#define MG9_8_17PL 0xFFFF -#endif - -#if (G9_9PL >= G9_8PL) || (G9_9PL == 0) -#define MG9_8_19PL ~(1 << 8) -#else -#define MG9_8_19PL 0xFFFF -#endif - -#if (G9_10PL >= G9_8PL) || (G9_10PL == 0) -#define MG9_8_110PL ~(1 << 9) -#else -#define MG9_8_110PL 0xFFFF -#endif - -#if (G9_11PL >= G9_8PL) || (G9_11PL == 0) -#define MG9_8_111PL ~(1 << 10) -#else -#define MG9_8_111PL 0xFFFF -#endif - -#if (G9_12PL >= G9_8PL) || (G9_12PL == 0) -#define MG9_8_112PL ~(1 << 11) -#else -#define MG9_8_112PL 0xFFFF -#endif - -#if (G9_13PL >= G9_8PL) || (G9_13PL == 0) -#define MG9_8_113PL ~(1 << 12) -#else -#define MG9_8_113PL 0xFFFF -#endif - -#if (G9_14PL >= G9_8PL) || (G9_14PL == 0) -#define MG9_8_114PL ~(1 << 13) -#else -#define MG9_8_114PL 0xFFFF -#endif - -#if (G9_15PL >= G9_8PL) || (G9_15PL == 0) -#define MG9_8_115PL ~(1 << 14) -#else -#define MG9_8_115PL 0xFFFF -#endif - -#if (G9_16PL >= G9_8PL) || (G9_16PL == 0) -#define MG9_8_116PL ~(1 << 15) -#else -#define MG9_8_116PL 0xFFFF -#endif - -#define MG9_8_18PL 0xFF7F -#define MG9_8 (MG9_8_11PL & MG9_8_12PL & MG9_8_13PL & MG9_8_14PL & \ - MG9_8_15PL & MG9_8_16PL & MG9_8_17PL & MG9_8_18PL & \ - MG9_8_19PL & MG9_8_110PL & MG9_8_111PL & MG9_8_112PL & \ - MG9_8_113PL & MG9_8_114PL & MG9_8_115PL & MG9_8_116PL) -// End of MG9_8: -// Beginning of MG99: -#if (G9_1PL >= G9_9PL) || (G9_1PL == 0) -#define MG9_9_11PL ~(1 << 0) -#else -#define MG9_9_11PL 0xFFFF -#endif - -#if (G9_2PL >= G9_9PL) || (G9_2PL == 0) -#define MG9_9_12PL ~(1 << 1) -#else -#define MG9_9_12PL 0xFFFF -#endif - -#if (G9_3PL >= G9_9PL) || (G9_3PL == 0) -#define MG9_9_13PL ~(1 << 2) -#else -#define MG9_9_13PL 0xFFFF -#endif - -#if (G9_4PL >= G9_9PL) || (G9_4PL == 0) -#define MG9_9_14PL ~(1 << 3) -#else -#define MG9_9_14PL 0xFFFF -#endif - -#if (G9_5PL >= G9_9PL) || (G9_5PL == 0) -#define MG9_9_15PL ~(1 << 4) -#else -#define MG9_9_15PL 0xFFFF -#endif - -#if (G9_6PL >= G9_9PL) || (G9_6PL == 0) -#define MG9_9_16PL ~(1 << 5) -#else -#define MG9_9_16PL 0xFFFF -#endif - -#if (G9_7PL >= G9_9PL) || (G9_7PL == 0) -#define MG9_9_17PL ~(1 << 6) -#else -#define MG9_9_17PL 0xFFFF -#endif - -#if (G9_8PL >= G9_9PL) || (G9_8PL == 0) -#define MG9_9_18PL ~(1 << 7) -#else -#define MG9_9_18PL 0xFFFF -#endif - -#if (G9_10PL >= G9_9PL) || (G9_10PL == 0) -#define MG9_9_110PL ~(1 << 9) -#else -#define MG9_9_110PL 0xFFFF -#endif - -#if (G9_11PL >= G9_9PL) || (G9_11PL == 0) -#define MG9_9_111PL ~(1 << 10) -#else -#define MG9_9_111PL 0xFFFF -#endif - -#if (G9_12PL >= G9_9PL) || (G9_12PL == 0) -#define MG9_9_112PL ~(1 << 11) -#else -#define MG9_9_112PL 0xFFFF -#endif - -#if (G9_13PL >= G9_9PL) || (G9_13PL == 0) -#define MG9_9_113PL ~(1 << 12) -#else -#define MG9_9_113PL 0xFFFF -#endif - -#if (G9_14PL >= G9_9PL) || (G9_14PL == 0) -#define MG9_9_114PL ~(1 << 13) -#else -#define MG9_9_114PL 0xFFFF -#endif - -#if (G9_15PL >= G9_9PL) || (G9_15PL == 0) -#define MG9_9_115PL ~(1 << 14) -#else -#define MG9_9_115PL 0xFFFF -#endif - -#if (G9_16PL >= G9_9PL) || (G9_16PL == 0) -#define MG9_9_116PL ~(1 << 15) -#else -#define MG9_9_116PL 0xFFFF -#endif - -#define MG9_9_19PL 0xFEFF -#define MG9_9 (MG9_9_11PL & MG9_9_12PL & MG9_9_13PL & MG9_9_14PL & \ - MG9_9_15PL & MG9_9_16PL & MG9_9_17PL & MG9_9_18PL & \ - MG9_9_19PL & MG9_9_110PL & MG9_9_111PL & MG9_9_112PL & \ - MG9_9_113PL & MG9_9_114PL & MG9_9_115PL & MG9_9_116PL) -// End of MG9_9: -// Beginning of MG910: -#if (G9_1PL >= G9_10PL) || (G9_1PL == 0) -#define MG9_10_11PL ~(1 << 0) -#else -#define MG9_10_11PL 0xFFFF -#endif - -#if (G9_2PL >= G9_10PL) || (G9_2PL == 0) -#define MG9_10_12PL ~(1 << 1) -#else -#define MG9_10_12PL 0xFFFF -#endif - -#if (G9_3PL >= G9_10PL) || (G9_3PL == 0) -#define MG9_10_13PL ~(1 << 2) -#else -#define MG9_10_13PL 0xFFFF -#endif - -#if (G9_4PL >= G9_10PL) || (G9_4PL == 0) -#define MG9_10_14PL ~(1 << 3) -#else -#define MG9_10_14PL 0xFFFF -#endif - -#if (G9_5PL >= G9_10PL) || (G9_5PL == 0) -#define MG9_10_15PL ~(1 << 4) -#else -#define MG9_10_15PL 0xFFFF -#endif - -#if (G9_6PL >= G9_10PL) || (G9_6PL == 0) -#define MG9_10_16PL ~(1 << 5) -#else -#define MG9_10_16PL 0xFFFF -#endif - -#if (G9_7PL >= G9_10PL) || (G9_7PL == 0) -#define MG9_10_17PL ~(1 << 6) -#else -#define MG9_10_17PL 0xFFFF -#endif - -#if (G9_8PL >= G9_10PL) || (G9_8PL == 0) -#define MG9_10_18PL ~(1 << 7) -#else -#define MG9_10_18PL 0xFFFF -#endif - -#if (G9_9PL >= G9_10PL) || (G9_9PL == 0) -#define MG9_10_19PL ~(1 << 8) -#else -#define MG9_10_19PL 0xFFFF -#endif - -#if (G9_11PL >= G9_10PL) || (G9_11PL == 0) -#define MG9_10_111PL ~(1 << 10) -#else -#define MG9_10_111PL 0xFFFF -#endif - -#if (G9_12PL >= G9_10PL) || (G9_12PL == 0) -#define MG9_10_112PL ~(1 << 11) -#else -#define MG9_10_112PL 0xFFFF -#endif - -#if (G9_13PL >= G9_10PL) || (G9_13PL == 0) -#define MG9_10_113PL ~(1 << 12) -#else -#define MG9_10_113PL 0xFFFF -#endif - -#if (G9_14PL >= G9_10PL) || (G9_14PL == 0) -#define MG9_10_114PL ~(1 << 13) -#else -#define MG9_10_114PL 0xFFFF -#endif - -#if (G9_15PL >= G9_10PL) || (G9_15PL == 0) -#define MG9_10_115PL ~(1 << 14) -#else -#define MG9_10_115PL 0xFFFF -#endif - -#if (G9_16PL >= G9_10PL) || (G9_16PL == 0) -#define MG9_10_116PL ~(1 << 15) -#else -#define MG9_10_116PL 0xFFFF -#endif - -#define MG9_10_110PL 0xFDFF -#define MG9_10 (MG9_10_11PL & MG9_10_12PL & MG9_10_13PL & MG9_10_14PL & \ - MG9_10_15PL & MG9_10_16PL & MG9_10_17PL & MG9_10_18PL & \ - MG9_10_19PL & MG9_10_110PL & MG9_10_111PL & MG9_10_112PL & \ - MG9_10_113PL & MG9_10_114PL & MG9_10_115PL & MG9_10_116PL) -// End of MG9_10: -// Beginning of MG911: -#if (G9_1PL >= G9_11PL) || (G9_1PL == 0) -#define MG9_11_11PL ~(1 << 0) -#else -#define MG9_11_11PL 0xFFFF -#endif - -#if (G9_2PL >= G9_11PL) || (G9_2PL == 0) -#define MG9_11_12PL ~(1 << 1) -#else -#define MG9_11_12PL 0xFFFF -#endif - -#if (G9_3PL >= G9_11PL) || (G9_3PL == 0) -#define MG9_11_13PL ~(1 << 2) -#else -#define MG9_11_13PL 0xFFFF -#endif - -#if (G9_4PL >= G9_11PL) || (G9_4PL == 0) -#define MG9_11_14PL ~(1 << 3) -#else -#define MG9_11_14PL 0xFFFF -#endif - -#if (G9_5PL >= G9_11PL) || (G9_5PL == 0) -#define MG9_11_15PL ~(1 << 4) -#else -#define MG9_11_15PL 0xFFFF -#endif - -#if (G9_6PL >= G9_11PL) || (G9_6PL == 0) -#define MG9_11_16PL ~(1 << 5) -#else -#define MG9_11_16PL 0xFFFF -#endif - -#if (G9_7PL >= G9_11PL) || (G9_7PL == 0) -#define MG9_11_17PL ~(1 << 6) -#else -#define MG9_11_17PL 0xFFFF -#endif - -#if (G9_8PL >= G9_11PL) || (G9_8PL == 0) -#define MG9_11_18PL ~(1 << 7) -#else -#define MG9_11_18PL 0xFFFF -#endif - -#if (G9_9PL >= G9_11PL) || (G9_9PL == 0) -#define MG9_11_19PL ~(1 << 8) -#else -#define MG9_11_19PL 0xFFFF -#endif - -#if (G9_10PL >= G9_11PL) || (G9_10PL == 0) -#define MG9_11_110PL ~(1 << 9) -#else -#define MG9_11_110PL 0xFFFF -#endif - -#if (G9_12PL >= G9_11PL) || (G9_12PL == 0) -#define MG9_11_112PL ~(1 << 11) -#else -#define MG9_11_112PL 0xFFFF -#endif - -#if (G9_13PL >= G9_11PL) || (G9_13PL == 0) -#define MG9_11_113PL ~(1 << 12) -#else -#define MG9_11_113PL 0xFFFF -#endif - -#if (G9_14PL >= G9_11PL) || (G9_14PL == 0) -#define MG9_11_114PL ~(1 << 13) -#else -#define MG9_11_114PL 0xFFFF -#endif - -#if (G9_15PL >= G9_11PL) || (G9_15PL == 0) -#define MG9_11_115PL ~(1 << 14) -#else -#define MG9_11_115PL 0xFFFF -#endif - -#if (G9_16PL >= G9_11PL) || (G9_16PL == 0) -#define MG9_11_116PL ~(1 << 15) -#else -#define MG9_11_116PL 0xFFFF -#endif - -#define MG9_11_111PL 0xFBFF -#define MG9_11 (MG9_11_11PL & MG9_11_12PL & MG9_11_13PL & MG9_11_14PL & \ - MG9_11_15PL & MG9_11_16PL & MG9_11_17PL & MG9_11_18PL & \ - MG9_11_19PL & MG9_11_110PL & MG9_11_111PL & MG9_11_112PL & \ - MG9_11_113PL & MG9_11_114PL & MG9_11_115PL & MG9_11_116PL) -// End of MG9_11: -// Beginning of MG912: -#if (G9_1PL >= G9_12PL) || (G9_1PL == 0) -#define MG9_12_11PL ~(1 << 0) -#else -#define MG9_12_11PL 0xFFFF -#endif - -#if (G9_2PL >= G9_12PL) || (G9_2PL == 0) -#define MG9_12_12PL ~(1 << 1) -#else -#define MG9_12_12PL 0xFFFF -#endif - -#if (G9_3PL >= G9_12PL) || (G9_3PL == 0) -#define MG9_12_13PL ~(1 << 2) -#else -#define MG9_12_13PL 0xFFFF -#endif - -#if (G9_4PL >= G9_12PL) || (G9_4PL == 0) -#define MG9_12_14PL ~(1 << 3) -#else -#define MG9_12_14PL 0xFFFF -#endif - -#if (G9_5PL >= G9_12PL) || (G9_5PL == 0) -#define MG9_12_15PL ~(1 << 4) -#else -#define MG9_12_15PL 0xFFFF -#endif - -#if (G9_6PL >= G9_12PL) || (G9_6PL == 0) -#define MG9_12_16PL ~(1 << 5) -#else -#define MG9_12_16PL 0xFFFF -#endif - -#if (G9_7PL >= G9_12PL) || (G9_7PL == 0) -#define MG9_12_17PL ~(1 << 6) -#else -#define MG9_12_17PL 0xFFFF -#endif - -#if (G9_8PL >= G9_12PL) || (G9_8PL == 0) -#define MG9_12_18PL ~(1 << 7) -#else -#define MG9_12_18PL 0xFFFF -#endif - -#if (G9_9PL >= G9_12PL) || (G9_9PL == 0) -#define MG9_12_19PL ~(1 << 8) -#else -#define MG9_12_19PL 0xFFFF -#endif - -#if (G9_10PL >= G9_12PL) || (G9_10PL == 0) -#define MG9_12_110PL ~(1 << 9) -#else -#define MG9_12_110PL 0xFFFF -#endif - -#if (G9_11PL >= G9_12PL) || (G9_11PL == 0) -#define MG9_12_111PL ~(1 << 10) -#else -#define MG9_12_111PL 0xFFFF -#endif - -#if (G9_13PL >= G9_12PL) || (G9_13PL == 0) -#define MG9_12_113PL ~(1 << 12) -#else -#define MG9_12_113PL 0xFFFF -#endif - -#if (G9_14PL >= G9_12PL) || (G9_14PL == 0) -#define MG9_12_114PL ~(1 << 13) -#else -#define MG9_12_114PL 0xFFFF -#endif - -#if (G9_15PL >= G9_12PL) || (G9_15PL == 0) -#define MG9_12_115PL ~(1 << 14) -#else -#define MG9_12_115PL 0xFFFF -#endif - -#if (G9_16PL >= G9_12PL) || (G9_16PL == 0) -#define MG9_12_116PL ~(1 << 15) -#else -#define MG9_12_116PL 0xFFFF -#endif - -#define MG9_12_112PL 0xF7FF -#define MG9_12 (MG9_12_11PL & MG9_12_12PL & MG9_12_13PL & MG9_12_14PL & \ - MG9_12_15PL & MG9_12_16PL & MG9_12_17PL & MG9_12_18PL & \ - MG9_12_19PL & MG9_12_110PL & MG9_12_111PL & MG9_12_112PL & \ - MG9_12_113PL & MG9_12_114PL & MG9_12_115PL & MG9_12_116PL) -// End of MG9_12: -// Beginning of MG913: -#if (G9_1PL >= G9_13PL) || (G9_1PL == 0) -#define MG9_13_11PL ~(1 << 0) -#else -#define MG9_13_11PL 0xFFFF -#endif - -#if (G9_2PL >= G9_13PL) || (G9_2PL == 0) -#define MG9_13_12PL ~(1 << 1) -#else -#define MG9_13_12PL 0xFFFF -#endif - -#if (G9_3PL >= G9_13PL) || (G9_3PL == 0) -#define MG9_13_13PL ~(1 << 2) -#else -#define MG9_13_13PL 0xFFFF -#endif - -#if (G9_4PL >= G9_13PL) || (G9_4PL == 0) -#define MG9_13_14PL ~(1 << 3) -#else -#define MG9_13_14PL 0xFFFF -#endif - -#if (G9_5PL >= G9_13PL) || (G9_5PL == 0) -#define MG9_13_15PL ~(1 << 4) -#else -#define MG9_13_15PL 0xFFFF -#endif - -#if (G9_6PL >= G9_13PL) || (G9_6PL == 0) -#define MG9_13_16PL ~(1 << 5) -#else -#define MG9_13_16PL 0xFFFF -#endif - -#if (G9_7PL >= G9_13PL) || (G9_7PL == 0) -#define MG9_13_17PL ~(1 << 6) -#else -#define MG9_13_17PL 0xFFFF -#endif - -#if (G9_8PL >= G9_13PL) || (G9_8PL == 0) -#define MG9_13_18PL ~(1 << 7) -#else -#define MG9_13_18PL 0xFFFF -#endif - -#if (G9_9PL >= G9_13PL) || (G9_9PL == 0) -#define MG9_13_19PL ~(1 << 8) -#else -#define MG9_13_19PL 0xFFFF -#endif - -#if (G9_10PL >= G9_13PL) || (G9_10PL == 0) -#define MG9_13_110PL ~(1 << 9) -#else -#define MG9_13_110PL 0xFFFF -#endif - -#if (G9_11PL >= G9_13PL) || (G9_11PL == 0) -#define MG9_13_111PL ~(1 << 10) -#else -#define MG9_13_111PL 0xFFFF -#endif - -#if (G9_12PL >= G9_13PL) || (G9_12PL == 0) -#define MG9_13_112PL ~(1 << 11) -#else -#define MG9_13_112PL 0xFFFF -#endif - -#if (G9_14PL >= G9_13PL) || (G9_14PL == 0) -#define MG9_13_114PL ~(1 << 13) -#else -#define MG9_13_114PL 0xFFFF -#endif - -#if (G9_15PL >= G9_13PL) || (G9_15PL == 0) -#define MG9_13_115PL ~(1 << 14) -#else -#define MG9_13_115PL 0xFFFF -#endif - -#if (G9_16PL >= G9_13PL) || (G9_16PL == 0) -#define MG9_13_116PL ~(1 << 15) -#else -#define MG9_13_116PL 0xFFFF -#endif - -#define MG9_13_113PL 0xEFFF -#define MG9_13 (MG9_13_11PL & MG9_13_12PL & MG9_13_13PL & MG9_13_14PL & \ - MG9_13_15PL & MG9_13_16PL & MG9_13_17PL & MG9_13_18PL & \ - MG9_13_19PL & MG9_13_110PL & MG9_13_111PL & MG9_13_112PL & \ - MG9_13_113PL & MG9_13_114PL & MG9_13_115PL & MG9_13_116PL) -// End of MG9_13: -// Beginning of MG914: -#if (G9_1PL >= G9_14PL) || (G9_1PL == 0) -#define MG9_14_11PL ~(1 << 0) -#else -#define MG9_14_11PL 0xFFFF -#endif - -#if (G9_2PL >= G9_14PL) || (G9_2PL == 0) -#define MG9_14_12PL ~(1 << 1) -#else -#define MG9_14_12PL 0xFFFF -#endif - -#if (G9_3PL >= G9_14PL) || (G9_3PL == 0) -#define MG9_14_13PL ~(1 << 2) -#else -#define MG9_14_13PL 0xFFFF -#endif - -#if (G9_4PL >= G9_14PL) || (G9_4PL == 0) -#define MG9_14_14PL ~(1 << 3) -#else -#define MG9_14_14PL 0xFFFF -#endif - -#if (G9_5PL >= G9_14PL) || (G9_5PL == 0) -#define MG9_14_15PL ~(1 << 4) -#else -#define MG9_14_15PL 0xFFFF -#endif - -#if (G9_6PL >= G9_14PL) || (G9_6PL == 0) -#define MG9_14_16PL ~(1 << 5) -#else -#define MG9_14_16PL 0xFFFF -#endif - -#if (G9_7PL >= G9_14PL) || (G9_7PL == 0) -#define MG9_14_17PL ~(1 << 6) -#else -#define MG9_14_17PL 0xFFFF -#endif - -#if (G9_8PL >= G9_14PL) || (G9_8PL == 0) -#define MG9_14_18PL ~(1 << 7) -#else -#define MG9_14_18PL 0xFFFF -#endif - -#if (G9_9PL >= G9_14PL) || (G9_9PL == 0) -#define MG9_14_19PL ~(1 << 8) -#else -#define MG9_14_19PL 0xFFFF -#endif - -#if (G9_10PL >= G9_14PL) || (G9_10PL == 0) -#define MG9_14_110PL ~(1 << 9) -#else -#define MG9_14_110PL 0xFFFF -#endif - -#if (G9_11PL >= G9_14PL) || (G9_11PL == 0) -#define MG9_14_111PL ~(1 << 10) -#else -#define MG9_14_111PL 0xFFFF -#endif - -#if (G9_12PL >= G9_14PL) || (G9_12PL == 0) -#define MG9_14_112PL ~(1 << 11) -#else -#define MG9_14_112PL 0xFFFF -#endif - -#if (G9_13PL >= G9_14PL) || (G9_13PL == 0) -#define MG9_14_113PL ~(1 << 12) -#else -#define MG9_14_113PL 0xFFFF -#endif - -#if (G9_15PL >= G9_14PL) || (G9_15PL == 0) -#define MG9_14_115PL ~(1 << 14) -#else -#define MG9_14_115PL 0xFFFF -#endif - -#if (G9_16PL >= G9_14PL) || (G9_16PL == 0) -#define MG9_14_116PL ~(1 << 15) -#else -#define MG9_14_116PL 0xFFFF -#endif - -#define MG9_14_114PL 0xDFFF -#define MG9_14 (MG9_14_11PL & MG9_14_12PL & MG9_14_13PL & MG9_14_14PL & \ - MG9_14_15PL & MG9_14_16PL & MG9_14_17PL & MG9_14_18PL & \ - MG9_14_19PL & MG9_14_110PL & MG9_14_111PL & MG9_14_112PL & \ - MG9_14_113PL & MG9_14_114PL & MG9_14_115PL & MG9_14_116PL) -// End of MG9_14: -// Beginning of MG915: -#if (G9_1PL >= G9_15PL) || (G9_1PL == 0) -#define MG9_15_11PL ~(1 << 0) -#else -#define MG9_15_11PL 0xFFFF -#endif - -#if (G9_2PL >= G9_15PL) || (G9_2PL == 0) -#define MG9_15_12PL ~(1 << 1) -#else -#define MG9_15_12PL 0xFFFF -#endif - -#if (G9_3PL >= G9_15PL) || (G9_3PL == 0) -#define MG9_15_13PL ~(1 << 2) -#else -#define MG9_15_13PL 0xFFFF -#endif - -#if (G9_4PL >= G9_15PL) || (G9_4PL == 0) -#define MG9_15_14PL ~(1 << 3) -#else -#define MG9_15_14PL 0xFFFF -#endif - -#if (G9_5PL >= G9_15PL) || (G9_5PL == 0) -#define MG9_15_15PL ~(1 << 4) -#else -#define MG9_15_15PL 0xFFFF -#endif - -#if (G9_6PL >= G9_15PL) || (G9_6PL == 0) -#define MG9_15_16PL ~(1 << 5) -#else -#define MG9_15_16PL 0xFFFF -#endif - -#if (G9_7PL >= G9_15PL) || (G9_7PL == 0) -#define MG9_15_17PL ~(1 << 6) -#else -#define MG9_15_17PL 0xFFFF -#endif - -#if (G9_8PL >= G9_15PL) || (G9_8PL == 0) -#define MG9_15_18PL ~(1 << 7) -#else -#define MG9_15_18PL 0xFFFF -#endif - -#if (G9_9PL >= G9_15PL) || (G9_9PL == 0) -#define MG9_15_19PL ~(1 << 8) -#else -#define MG9_15_19PL 0xFFFF -#endif - -#if (G9_10PL >= G9_15PL) || (G9_10PL == 0) -#define MG9_15_110PL ~(1 << 9) -#else -#define MG9_15_110PL 0xFFFF -#endif - -#if (G9_11PL >= G9_15PL) || (G9_11PL == 0) -#define MG9_15_111PL ~(1 << 10) -#else -#define MG9_15_111PL 0xFFFF -#endif - -#if (G9_12PL >= G9_15PL) || (G9_12PL == 0) -#define MG9_15_112PL ~(1 << 11) -#else -#define MG9_15_112PL 0xFFFF -#endif - -#if (G9_13PL >= G9_15PL) || (G9_13PL == 0) -#define MG9_15_113PL ~(1 << 12) -#else -#define MG9_15_113PL 0xFFFF -#endif - -#if (G9_14PL >= G9_15PL) || (G9_14PL == 0) -#define MG9_15_114PL ~(1 << 13) -#else -#define MG9_15_114PL 0xFFFF -#endif - -#if (G9_16PL >= G9_15PL) || (G9_16PL == 0) -#define MG9_15_116PL ~(1 << 15) -#else -#define MG9_15_116PL 0xFFFF -#endif - -#define MG9_15_115PL 0xBFFF -#define MG9_15 (MG9_15_11PL & MG9_15_12PL & MG9_15_13PL & MG9_15_14PL & \ - MG9_15_15PL & MG9_15_16PL & MG9_15_17PL & MG9_15_18PL & \ - MG9_15_19PL & MG9_15_110PL & MG9_15_111PL & MG9_15_112PL & \ - MG9_15_113PL & MG9_15_114PL & MG9_15_115PL & MG9_15_116PL) -// End of MG9_15: -// Beginning of MG916: -#if (G9_1PL >= G9_16PL) || (G9_1PL == 0) -#define MG9_16_11PL ~(1 << 0) -#else -#define MG9_16_11PL 0xFFFF -#endif - -#if (G9_2PL >= G9_16PL) || (G9_2PL == 0) -#define MG9_16_12PL ~(1 << 1) -#else -#define MG9_16_12PL 0xFFFF -#endif - -#if (G9_3PL >= G9_16PL) || (G9_3PL == 0) -#define MG9_16_13PL ~(1 << 2) -#else -#define MG9_16_13PL 0xFFFF -#endif - -#if (G9_4PL >= G9_16PL) || (G9_4PL == 0) -#define MG9_16_14PL ~(1 << 3) -#else -#define MG9_16_14PL 0xFFFF -#endif - -#if (G9_5PL >= G9_16PL) || (G9_5PL == 0) -#define MG9_16_15PL ~(1 << 4) -#else -#define MG9_16_15PL 0xFFFF -#endif - -#if (G9_6PL >= G9_16PL) || (G9_6PL == 0) -#define MG9_16_16PL ~(1 << 5) -#else -#define MG9_16_16PL 0xFFFF -#endif - -#if (G9_7PL >= G9_16PL) || (G9_7PL == 0) -#define MG9_16_17PL ~(1 << 6) -#else -#define MG9_16_17PL 0xFFFF -#endif - -#if (G9_8PL >= G9_16PL) || (G9_8PL == 0) -#define MG9_16_18PL ~(1 << 7) -#else -#define MG9_16_18PL 0xFFFF -#endif - -#if (G9_9PL >= G9_16PL) || (G9_9PL == 0) -#define MG9_16_19PL ~(1 << 8) -#else -#define MG9_16_19PL 0xFFFF -#endif - -#if (G9_10PL >= G9_16PL) || (G9_10PL == 0) -#define MG9_16_110PL ~(1 << 9) -#else -#define MG9_16_110PL 0xFFFF -#endif - -#if (G9_11PL >= G9_16PL) || (G9_11PL == 0) -#define MG9_16_111PL ~(1 << 10) -#else -#define MG9_16_111PL 0xFFFF -#endif - -#if (G9_12PL >= G9_16PL) || (G9_12PL == 0) -#define MG9_16_112PL ~(1 << 11) -#else -#define MG9_16_112PL 0xFFFF -#endif - -#if (G9_13PL >= G9_16PL) || (G9_13PL == 0) -#define MG9_16_113PL ~(1 << 12) -#else -#define MG9_16_113PL 0xFFFF -#endif - -#if (G9_14PL >= G9_16PL) || (G9_14PL == 0) -#define MG9_16_114PL ~(1 << 13) -#else -#define MG9_16_114PL 0xFFFF -#endif - -#if (G9_15PL >= G9_16PL) || (G9_15PL == 0) -#define MG9_16_115PL ~(1 << 14) -#else -#define MG9_16_115PL 0xFFFF -#endif - -#define MG9_16_116PL 0x7FFF -#define MG9_16 (MG9_16_11PL & MG9_16_12PL & MG9_16_13PL & MG9_16_14PL & \ - MG9_16_15PL & MG9_16_16PL & MG9_16_17PL & MG9_16_18PL & \ - MG9_16_19PL & MG9_16_110PL & MG9_16_111PL & MG9_16_112PL & \ - MG9_16_113PL & MG9_16_114PL & MG9_16_115PL & MG9_16_116PL) -// End of MG9_16: - - -// -// Automatically generate PIEIER10 interrupt masks MG101 to MG1016: -// - -// Beginning of MG101: -#if (G10_2PL >= G10_1PL) || (G10_2PL == 0) -#define MG10_1_12PL ~(1 << 1) -#else -#define MG10_1_12PL 0xFFFF -#endif - -#if (G10_3PL >= G10_1PL) || (G10_3PL == 0) -#define MG10_1_13PL ~(1 << 2) -#else -#define MG10_1_13PL 0xFFFF -#endif - -#if (G10_4PL >= G10_1PL) || (G10_4PL == 0) -#define MG10_1_14PL ~(1 << 3) -#else -#define MG10_1_14PL 0xFFFF -#endif - -#if (G10_5PL >= G10_1PL) || (G10_5PL == 0) -#define MG10_1_15PL ~(1 << 4) -#else -#define MG10_1_15PL 0xFFFF -#endif - -#if (G10_6PL >= G10_1PL) || (G10_6PL == 0) -#define MG10_1_16PL ~(1 << 5) -#else -#define MG10_1_16PL 0xFFFF -#endif - -#if (G10_7PL >= G10_1PL) || (G10_7PL == 0) -#define MG10_1_17PL ~(1 << 6) -#else -#define MG10_1_17PL 0xFFFF -#endif - -#if (G10_8PL >= G10_1PL) || (G10_8PL == 0) -#define MG10_1_18PL ~(1 << 7) -#else -#define MG10_1_18PL 0xFFFF -#endif - -#if (G10_9PL >= G10_1PL) || (G10_9PL == 0) -#define MG10_1_19PL ~(1 << 8) -#else -#define MG10_1_19PL 0xFFFF -#endif - -#if (G10_10PL >= G10_1PL) || (G10_10PL == 0) -#define MG10_1_110PL ~(1 << 9) -#else -#define MG10_1_110PL 0xFFFF -#endif - -#if (G10_11PL >= G10_1PL) || (G10_11PL == 0) -#define MG10_1_111PL ~(1 << 10) -#else -#define MG10_1_111PL 0xFFFF -#endif - -#if (G10_12PL >= G10_1PL) || (G10_12PL == 0) -#define MG10_1_112PL ~(1 << 11) -#else -#define MG10_1_112PL 0xFFFF -#endif - -#if (G10_13PL >= G10_1PL) || (G10_13PL == 0) -#define MG10_1_113PL ~(1 << 12) -#else -#define MG10_1_113PL 0xFFFF -#endif - -#if (G10_14PL >= G10_1PL) || (G10_14PL == 0) -#define MG10_1_114PL ~(1 << 13) -#else -#define MG10_1_114PL 0xFFFF -#endif - -#if (G10_15PL >= G10_1PL) || (G10_15PL == 0) -#define MG10_1_115PL ~(1 << 14) -#else -#define MG10_1_115PL 0xFFFF -#endif - -#if (G10_16PL >= G10_1PL) || (G10_16PL == 0) -#define MG10_1_116PL ~(1 << 15) -#else -#define MG10_1_116PL 0xFFFF -#endif - -#define MG10_1_11PL 0xFFFE -#define MG10_1 (MG10_1_11PL & MG10_1_12PL & MG10_1_13PL & MG10_1_14PL & \ - MG10_1_15PL & MG10_1_16PL & MG10_1_17PL & MG10_1_18PL & \ - MG10_1_19PL & MG10_1_110PL & MG10_1_111PL & MG10_1_112PL & \ - MG10_1_113PL & MG10_1_114PL & MG10_1_115PL & MG10_1_116PL) -// End of MG10_1: -// Beginning of MG102: -#if (G10_1PL >= G10_2PL) || (G10_1PL == 0) -#define MG10_2_11PL ~(1 << 0) -#else -#define MG10_2_11PL 0xFFFF -#endif - -#if (G10_3PL >= G10_2PL) || (G10_3PL == 0) -#define MG10_2_13PL ~(1 << 2) -#else -#define MG10_2_13PL 0xFFFF -#endif - -#if (G10_4PL >= G10_2PL) || (G10_4PL == 0) -#define MG10_2_14PL ~(1 << 3) -#else -#define MG10_2_14PL 0xFFFF -#endif - -#if (G10_5PL >= G10_2PL) || (G10_5PL == 0) -#define MG10_2_15PL ~(1 << 4) -#else -#define MG10_2_15PL 0xFFFF -#endif - -#if (G10_6PL >= G10_2PL) || (G10_6PL == 0) -#define MG10_2_16PL ~(1 << 5) -#else -#define MG10_2_16PL 0xFFFF -#endif - -#if (G10_7PL >= G10_2PL) || (G10_7PL == 0) -#define MG10_2_17PL ~(1 << 6) -#else -#define MG10_2_17PL 0xFFFF -#endif - -#if (G10_8PL >= G10_2PL) || (G10_8PL == 0) -#define MG10_2_18PL ~(1 << 7) -#else -#define MG10_2_18PL 0xFFFF -#endif - -#if (G10_9PL >= G10_2PL) || (G10_9PL == 0) -#define MG10_2_19PL ~(1 << 8) -#else -#define MG10_2_19PL 0xFFFF -#endif - -#if (G10_10PL >= G10_2PL) || (G10_10PL == 0) -#define MG10_2_110PL ~(1 << 9) -#else -#define MG10_2_110PL 0xFFFF -#endif - -#if (G10_11PL >= G10_2PL) || (G10_11PL == 0) -#define MG10_2_111PL ~(1 << 10) -#else -#define MG10_2_111PL 0xFFFF -#endif - -#if (G10_12PL >= G10_2PL) || (G10_12PL == 0) -#define MG10_2_112PL ~(1 << 11) -#else -#define MG10_2_112PL 0xFFFF -#endif - -#if (G10_13PL >= G10_2PL) || (G10_13PL == 0) -#define MG10_2_113PL ~(1 << 12) -#else -#define MG10_2_113PL 0xFFFF -#endif - -#if (G10_14PL >= G10_2PL) || (G10_14PL == 0) -#define MG10_2_114PL ~(1 << 13) -#else -#define MG10_2_114PL 0xFFFF -#endif - -#if (G10_15PL >= G10_2PL) || (G10_15PL == 0) -#define MG10_2_115PL ~(1 << 14) -#else -#define MG10_2_115PL 0xFFFF -#endif - -#if (G10_16PL >= G10_2PL) || (G10_16PL == 0) -#define MG10_2_116PL ~(1 << 15) -#else -#define MG10_2_116PL 0xFFFF -#endif - -#define MG10_2_12PL 0xFFFD -#define MG10_2 (MG10_2_11PL & MG10_2_12PL & MG10_2_13PL & MG10_2_14PL & \ - MG10_2_15PL & MG10_2_16PL & MG10_2_17PL & MG10_2_18PL & \ - MG10_2_19PL & MG10_2_110PL & MG10_2_111PL & MG10_2_112PL & \ - MG10_2_113PL & MG10_2_114PL & MG10_2_115PL & MG10_2_116PL) -// End of MG10_2: -// Beginning of MG103: -#if (G10_1PL >= G10_3PL) || (G10_1PL == 0) -#define MG10_3_11PL ~(1 << 0) -#else -#define MG10_3_11PL 0xFFFF -#endif - -#if (G10_2PL >= G10_3PL) || (G10_2PL == 0) -#define MG10_3_12PL ~(1 << 1) -#else -#define MG10_3_12PL 0xFFFF -#endif - -#if (G10_4PL >= G10_3PL) || (G10_4PL == 0) -#define MG10_3_14PL ~(1 << 3) -#else -#define MG10_3_14PL 0xFFFF -#endif - -#if (G10_5PL >= G10_3PL) || (G10_5PL == 0) -#define MG10_3_15PL ~(1 << 4) -#else -#define MG10_3_15PL 0xFFFF -#endif - -#if (G10_6PL >= G10_3PL) || (G10_6PL == 0) -#define MG10_3_16PL ~(1 << 5) -#else -#define MG10_3_16PL 0xFFFF -#endif - -#if (G10_7PL >= G10_3PL) || (G10_7PL == 0) -#define MG10_3_17PL ~(1 << 6) -#else -#define MG10_3_17PL 0xFFFF -#endif - -#if (G10_8PL >= G10_3PL) || (G10_8PL == 0) -#define MG10_3_18PL ~(1 << 7) -#else -#define MG10_3_18PL 0xFFFF -#endif - -#if (G10_9PL >= G10_3PL) || (G10_9PL == 0) -#define MG10_3_19PL ~(1 << 8) -#else -#define MG10_3_19PL 0xFFFF -#endif - -#if (G10_10PL >= G10_3PL) || (G10_10PL == 0) -#define MG10_3_110PL ~(1 << 9) -#else -#define MG10_3_110PL 0xFFFF -#endif - -#if (G10_11PL >= G10_3PL) || (G10_11PL == 0) -#define MG10_3_111PL ~(1 << 10) -#else -#define MG10_3_111PL 0xFFFF -#endif - -#if (G10_12PL >= G10_3PL) || (G10_12PL == 0) -#define MG10_3_112PL ~(1 << 11) -#else -#define MG10_3_112PL 0xFFFF -#endif - -#if (G10_13PL >= G10_3PL) || (G10_13PL == 0) -#define MG10_3_113PL ~(1 << 12) -#else -#define MG10_3_113PL 0xFFFF -#endif - -#if (G10_14PL >= G10_3PL) || (G10_14PL == 0) -#define MG10_3_114PL ~(1 << 13) -#else -#define MG10_3_114PL 0xFFFF -#endif - -#if (G10_15PL >= G10_3PL) || (G10_15PL == 0) -#define MG10_3_115PL ~(1 << 14) -#else -#define MG10_3_115PL 0xFFFF -#endif - -#if (G10_16PL >= G10_3PL) || (G10_16PL == 0) -#define MG10_3_116PL ~(1 << 15) -#else -#define MG10_3_116PL 0xFFFF -#endif - -#define MG10_3_13PL 0xFFFB -#define MG10_3 (MG10_3_11PL & MG10_3_12PL & MG10_3_13PL & MG10_3_14PL & \ - MG10_3_15PL & MG10_3_16PL & MG10_3_17PL & MG10_3_18PL & \ - MG10_3_19PL & MG10_3_110PL & MG10_3_111PL & MG10_3_112PL & \ - MG10_3_113PL & MG10_3_114PL & MG10_3_115PL & MG10_3_116PL) -// End of MG10_3: -// Beginning of MG104: -#if (G10_1PL >= G10_4PL) || (G10_1PL == 0) -#define MG10_4_11PL ~(1 << 0) -#else -#define MG10_4_11PL 0xFFFF -#endif - -#if (G10_2PL >= G10_4PL) || (G10_2PL == 0) -#define MG10_4_12PL ~(1 << 1) -#else -#define MG10_4_12PL 0xFFFF -#endif - -#if (G10_3PL >= G10_4PL) || (G10_3PL == 0) -#define MG10_4_13PL ~(1 << 2) -#else -#define MG10_4_13PL 0xFFFF -#endif - -#if (G10_5PL >= G10_4PL) || (G10_5PL == 0) -#define MG10_4_15PL ~(1 << 4) -#else -#define MG10_4_15PL 0xFFFF -#endif - -#if (G10_6PL >= G10_4PL) || (G10_6PL == 0) -#define MG10_4_16PL ~(1 << 5) -#else -#define MG10_4_16PL 0xFFFF -#endif - -#if (G10_7PL >= G10_4PL) || (G10_7PL == 0) -#define MG10_4_17PL ~(1 << 6) -#else -#define MG10_4_17PL 0xFFFF -#endif - -#if (G10_8PL >= G10_4PL) || (G10_8PL == 0) -#define MG10_4_18PL ~(1 << 7) -#else -#define MG10_4_18PL 0xFFFF -#endif - -#if (G10_9PL >= G10_4PL) || (G10_9PL == 0) -#define MG10_4_19PL ~(1 << 8) -#else -#define MG10_4_19PL 0xFFFF -#endif - -#if (G10_10PL >= G10_4PL) || (G10_10PL == 0) -#define MG10_4_110PL ~(1 << 9) -#else -#define MG10_4_110PL 0xFFFF -#endif - -#if (G10_11PL >= G10_4PL) || (G10_11PL == 0) -#define MG10_4_111PL ~(1 << 10) -#else -#define MG10_4_111PL 0xFFFF -#endif - -#if (G10_12PL >= G10_4PL) || (G10_12PL == 0) -#define MG10_4_112PL ~(1 << 11) -#else -#define MG10_4_112PL 0xFFFF -#endif - -#if (G10_13PL >= G10_4PL) || (G10_13PL == 0) -#define MG10_4_113PL ~(1 << 12) -#else -#define MG10_4_113PL 0xFFFF -#endif - -#if (G10_14PL >= G10_4PL) || (G10_14PL == 0) -#define MG10_4_114PL ~(1 << 13) -#else -#define MG10_4_114PL 0xFFFF -#endif - -#if (G10_15PL >= G10_4PL) || (G10_15PL == 0) -#define MG10_4_115PL ~(1 << 14) -#else -#define MG10_4_115PL 0xFFFF -#endif - -#if (G10_16PL >= G10_4PL) || (G10_16PL == 0) -#define MG10_4_116PL ~(1 << 15) -#else -#define MG10_4_116PL 0xFFFF -#endif - -#define MG10_4_14PL 0xFFF7 -#define MG10_4 (MG10_4_11PL & MG10_4_12PL & MG10_4_13PL & MG10_4_14PL & \ - MG10_4_15PL & MG10_4_16PL & MG10_4_17PL & MG10_4_18PL & \ - MG10_4_19PL & MG10_4_110PL & MG10_4_111PL & MG10_4_112PL & \ - MG10_4_113PL & MG10_4_114PL & MG10_4_115PL & MG10_4_116PL) -// End of MG10_4: -// Beginning of MG105: -#if (G10_1PL >= G10_5PL) || (G10_1PL == 0) -#define MG10_5_11PL ~(1 << 0) -#else -#define MG10_5_11PL 0xFFFF -#endif - -#if (G10_2PL >= G10_5PL) || (G10_2PL == 0) -#define MG10_5_12PL ~(1 << 1) -#else -#define MG10_5_12PL 0xFFFF -#endif - -#if (G10_3PL >= G10_5PL) || (G10_3PL == 0) -#define MG10_5_13PL ~(1 << 2) -#else -#define MG10_5_13PL 0xFFFF -#endif - -#if (G10_4PL >= G10_5PL) || (G10_4PL == 0) -#define MG10_5_14PL ~(1 << 3) -#else -#define MG10_5_14PL 0xFFFF -#endif - -#if (G10_6PL >= G10_5PL) || (G10_6PL == 0) -#define MG10_5_16PL ~(1 << 5) -#else -#define MG10_5_16PL 0xFFFF -#endif - -#if (G10_7PL >= G10_5PL) || (G10_7PL == 0) -#define MG10_5_17PL ~(1 << 6) -#else -#define MG10_5_17PL 0xFFFF -#endif - -#if (G10_8PL >= G10_5PL) || (G10_8PL == 0) -#define MG10_5_18PL ~(1 << 7) -#else -#define MG10_5_18PL 0xFFFF -#endif - -#if (G10_9PL >= G10_5PL) || (G10_9PL == 0) -#define MG10_5_19PL ~(1 << 8) -#else -#define MG10_5_19PL 0xFFFF -#endif - -#if (G10_10PL >= G10_5PL) || (G10_10PL == 0) -#define MG10_5_110PL ~(1 << 9) -#else -#define MG10_5_110PL 0xFFFF -#endif - -#if (G10_11PL >= G10_5PL) || (G10_11PL == 0) -#define MG10_5_111PL ~(1 << 10) -#else -#define MG10_5_111PL 0xFFFF -#endif - -#if (G10_12PL >= G10_5PL) || (G10_12PL == 0) -#define MG10_5_112PL ~(1 << 11) -#else -#define MG10_5_112PL 0xFFFF -#endif - -#if (G10_13PL >= G10_5PL) || (G10_13PL == 0) -#define MG10_5_113PL ~(1 << 12) -#else -#define MG10_5_113PL 0xFFFF -#endif - -#if (G10_14PL >= G10_5PL) || (G10_14PL == 0) -#define MG10_5_114PL ~(1 << 13) -#else -#define MG10_5_114PL 0xFFFF -#endif - -#if (G10_15PL >= G10_5PL) || (G10_15PL == 0) -#define MG10_5_115PL ~(1 << 14) -#else -#define MG10_5_115PL 0xFFFF -#endif - -#if (G10_16PL >= G10_5PL) || (G10_16PL == 0) -#define MG10_5_116PL ~(1 << 15) -#else -#define MG10_5_116PL 0xFFFF -#endif - -#define MG10_5_15PL 0xFFEF -#define MG10_5 (MG10_5_11PL & MG10_5_12PL & MG10_5_13PL & MG10_5_14PL & \ - MG10_5_15PL & MG10_5_16PL & MG10_5_17PL & MG10_5_18PL & \ - MG10_5_19PL & MG10_5_110PL & MG10_5_111PL & MG10_5_112PL & \ - MG10_5_113PL & MG10_5_114PL & MG10_5_115PL & MG10_5_116PL) -// End of MG10_5: -// Beginning of MG106: -#if (G10_1PL >= G10_6PL) || (G10_1PL == 0) -#define MG10_6_11PL ~(1 << 0) -#else -#define MG10_6_11PL 0xFFFF -#endif - -#if (G10_2PL >= G10_6PL) || (G10_2PL == 0) -#define MG10_6_12PL ~(1 << 1) -#else -#define MG10_6_12PL 0xFFFF -#endif - -#if (G10_3PL >= G10_6PL) || (G10_3PL == 0) -#define MG10_6_13PL ~(1 << 2) -#else -#define MG10_6_13PL 0xFFFF -#endif - -#if (G10_4PL >= G10_6PL) || (G10_4PL == 0) -#define MG10_6_14PL ~(1 << 3) -#else -#define MG10_6_14PL 0xFFFF -#endif - -#if (G10_5PL >= G10_6PL) || (G10_5PL == 0) -#define MG10_6_15PL ~(1 << 4) -#else -#define MG10_6_15PL 0xFFFF -#endif - -#if (G10_7PL >= G10_6PL) || (G10_7PL == 0) -#define MG10_6_17PL ~(1 << 6) -#else -#define MG10_6_17PL 0xFFFF -#endif - -#if (G10_8PL >= G10_6PL) || (G10_8PL == 0) -#define MG10_6_18PL ~(1 << 7) -#else -#define MG10_6_18PL 0xFFFF -#endif - -#if (G10_9PL >= G10_6PL) || (G10_9PL == 0) -#define MG10_6_19PL ~(1 << 8) -#else -#define MG10_6_19PL 0xFFFF -#endif - -#if (G10_10PL >= G10_6PL) || (G10_10PL == 0) -#define MG10_6_110PL ~(1 << 9) -#else -#define MG10_6_110PL 0xFFFF -#endif - -#if (G10_11PL >= G10_6PL) || (G10_11PL == 0) -#define MG10_6_111PL ~(1 << 10) -#else -#define MG10_6_111PL 0xFFFF -#endif - -#if (G10_12PL >= G10_6PL) || (G10_12PL == 0) -#define MG10_6_112PL ~(1 << 11) -#else -#define MG10_6_112PL 0xFFFF -#endif - -#if (G10_13PL >= G10_6PL) || (G10_13PL == 0) -#define MG10_6_113PL ~(1 << 12) -#else -#define MG10_6_113PL 0xFFFF -#endif - -#if (G10_14PL >= G10_6PL) || (G10_14PL == 0) -#define MG10_6_114PL ~(1 << 13) -#else -#define MG10_6_114PL 0xFFFF -#endif - -#if (G10_15PL >= G10_6PL) || (G10_15PL == 0) -#define MG10_6_115PL ~(1 << 14) -#else -#define MG10_6_115PL 0xFFFF -#endif - -#if (G10_16PL >= G10_6PL) || (G10_16PL == 0) -#define MG10_6_116PL ~(1 << 15) -#else -#define MG10_6_116PL 0xFFFF -#endif - -#define MG10_6_16PL 0xFFDF -#define MG10_6 (MG10_6_11PL & MG10_6_12PL & MG10_6_13PL & MG10_6_14PL & \ - MG10_6_15PL & MG10_6_16PL & MG10_6_17PL & MG10_6_18PL & \ - MG10_6_19PL & MG10_6_110PL & MG10_6_111PL & MG10_6_112PL & \ - MG10_6_113PL & MG10_6_114PL & MG10_6_115PL & MG10_6_116PL) -// End of MG10_6: -// Beginning of MG107: -#if (G10_1PL >= G10_7PL) || (G10_1PL == 0) -#define MG10_7_11PL ~(1 << 0) -#else -#define MG10_7_11PL 0xFFFF -#endif - -#if (G10_2PL >= G10_7PL) || (G10_2PL == 0) -#define MG10_7_12PL ~(1 << 1) -#else -#define MG10_7_12PL 0xFFFF -#endif - -#if (G10_3PL >= G10_7PL) || (G10_3PL == 0) -#define MG10_7_13PL ~(1 << 2) -#else -#define MG10_7_13PL 0xFFFF -#endif - -#if (G10_4PL >= G10_7PL) || (G10_4PL == 0) -#define MG10_7_14PL ~(1 << 3) -#else -#define MG10_7_14PL 0xFFFF -#endif - -#if (G10_5PL >= G10_7PL) || (G10_5PL == 0) -#define MG10_7_15PL ~(1 << 4) -#else -#define MG10_7_15PL 0xFFFF -#endif - -#if (G10_6PL >= G10_7PL) || (G10_6PL == 0) -#define MG10_7_16PL ~(1 << 5) -#else -#define MG10_7_16PL 0xFFFF -#endif - -#if (G10_8PL >= G10_7PL) || (G10_8PL == 0) -#define MG10_7_18PL ~(1 << 7) -#else -#define MG10_7_18PL 0xFFFF -#endif - -#if (G10_9PL >= G10_7PL) || (G10_9PL == 0) -#define MG10_7_19PL ~(1 << 8) -#else -#define MG10_7_19PL 0xFFFF -#endif - -#if (G10_10PL >= G10_7PL) || (G10_10PL == 0) -#define MG10_7_110PL ~(1 << 9) -#else -#define MG10_7_110PL 0xFFFF -#endif - -#if (G10_11PL >= G10_7PL) || (G10_11PL == 0) -#define MG10_7_111PL ~(1 << 10) -#else -#define MG10_7_111PL 0xFFFF -#endif - -#if (G10_12PL >= G10_7PL) || (G10_12PL == 0) -#define MG10_7_112PL ~(1 << 11) -#else -#define MG10_7_112PL 0xFFFF -#endif - -#if (G10_13PL >= G10_7PL) || (G10_13PL == 0) -#define MG10_7_113PL ~(1 << 12) -#else -#define MG10_7_113PL 0xFFFF -#endif - -#if (G10_14PL >= G10_7PL) || (G10_14PL == 0) -#define MG10_7_114PL ~(1 << 13) -#else -#define MG10_7_114PL 0xFFFF -#endif - -#if (G10_15PL >= G10_7PL) || (G10_15PL == 0) -#define MG10_7_115PL ~(1 << 14) -#else -#define MG10_7_115PL 0xFFFF -#endif - -#if (G10_16PL >= G10_7PL) || (G10_16PL == 0) -#define MG10_7_116PL ~(1 << 15) -#else -#define MG10_7_116PL 0xFFFF -#endif - -#define MG10_7_17PL 0xFFBF -#define MG10_7 (MG10_7_11PL & MG10_7_12PL & MG10_7_13PL & MG10_7_14PL & \ - MG10_7_15PL & MG10_7_16PL & MG10_7_17PL & MG10_7_18PL & \ - MG10_7_19PL & MG10_7_110PL & MG10_7_111PL & MG10_7_112PL & \ - MG10_7_113PL & MG10_7_114PL & MG10_7_115PL & MG10_7_116PL) -// End of MG10_7: -// Beginning of MG108: -#if (G10_1PL >= G10_8PL) || (G10_1PL == 0) -#define MG10_8_11PL ~(1 << 0) -#else -#define MG10_8_11PL 0xFFFF -#endif - -#if (G10_2PL >= G10_8PL) || (G10_2PL == 0) -#define MG10_8_12PL ~(1 << 1) -#else -#define MG10_8_12PL 0xFFFF -#endif - -#if (G10_3PL >= G10_8PL) || (G10_3PL == 0) -#define MG10_8_13PL ~(1 << 2) -#else -#define MG10_8_13PL 0xFFFF -#endif - -#if (G10_4PL >= G10_8PL) || (G10_4PL == 0) -#define MG10_8_14PL ~(1 << 3) -#else -#define MG10_8_14PL 0xFFFF -#endif - -#if (G10_5PL >= G10_8PL) || (G10_5PL == 0) -#define MG10_8_15PL ~(1 << 4) -#else -#define MG10_8_15PL 0xFFFF -#endif - -#if (G10_6PL >= G10_8PL) || (G10_6PL == 0) -#define MG10_8_16PL ~(1 << 5) -#else -#define MG10_8_16PL 0xFFFF -#endif - -#if (G10_7PL >= G10_8PL) || (G10_7PL == 0) -#define MG10_8_17PL ~(1 << 6) -#else -#define MG10_8_17PL 0xFFFF -#endif - -#if (G10_9PL >= G10_8PL) || (G10_9PL == 0) -#define MG10_8_19PL ~(1 << 8) -#else -#define MG10_8_19PL 0xFFFF -#endif - -#if (G10_10PL >= G10_8PL) || (G10_10PL == 0) -#define MG10_8_110PL ~(1 << 9) -#else -#define MG10_8_110PL 0xFFFF -#endif - -#if (G10_11PL >= G10_8PL) || (G10_11PL == 0) -#define MG10_8_111PL ~(1 << 10) -#else -#define MG10_8_111PL 0xFFFF -#endif - -#if (G10_12PL >= G10_8PL) || (G10_12PL == 0) -#define MG10_8_112PL ~(1 << 11) -#else -#define MG10_8_112PL 0xFFFF -#endif - -#if (G10_13PL >= G10_8PL) || (G10_13PL == 0) -#define MG10_8_113PL ~(1 << 12) -#else -#define MG10_8_113PL 0xFFFF -#endif - -#if (G10_14PL >= G10_8PL) || (G10_14PL == 0) -#define MG10_8_114PL ~(1 << 13) -#else -#define MG10_8_114PL 0xFFFF -#endif - -#if (G10_15PL >= G10_8PL) || (G10_15PL == 0) -#define MG10_8_115PL ~(1 << 14) -#else -#define MG10_8_115PL 0xFFFF -#endif - -#if (G10_16PL >= G10_8PL) || (G10_16PL == 0) -#define MG10_8_116PL ~(1 << 15) -#else -#define MG10_8_116PL 0xFFFF -#endif - -#define MG10_8_18PL 0xFF7F -#define MG10_8 (MG10_8_11PL & MG10_8_12PL & MG10_8_13PL & MG10_8_14PL & \ - MG10_8_15PL & MG10_8_16PL & MG10_8_17PL & MG10_8_18PL & \ - MG10_8_19PL & MG10_8_110PL & MG10_8_111PL & MG10_8_112PL & \ - MG10_8_113PL & MG10_8_114PL & MG10_8_115PL & MG10_8_116PL) -// End of MG10_8: -// Beginning of MG109: -#if (G10_1PL >= G10_9PL) || (G10_1PL == 0) -#define MG10_9_11PL ~(1 << 0) -#else -#define MG10_9_11PL 0xFFFF -#endif - -#if (G10_2PL >= G10_9PL) || (G10_2PL == 0) -#define MG10_9_12PL ~(1 << 1) -#else -#define MG10_9_12PL 0xFFFF -#endif - -#if (G10_3PL >= G10_9PL) || (G10_3PL == 0) -#define MG10_9_13PL ~(1 << 2) -#else -#define MG10_9_13PL 0xFFFF -#endif - -#if (G10_4PL >= G10_9PL) || (G10_4PL == 0) -#define MG10_9_14PL ~(1 << 3) -#else -#define MG10_9_14PL 0xFFFF -#endif - -#if (G10_5PL >= G10_9PL) || (G10_5PL == 0) -#define MG10_9_15PL ~(1 << 4) -#else -#define MG10_9_15PL 0xFFFF -#endif - -#if (G10_6PL >= G10_9PL) || (G10_6PL == 0) -#define MG10_9_16PL ~(1 << 5) -#else -#define MG10_9_16PL 0xFFFF -#endif - -#if (G10_7PL >= G10_9PL) || (G10_7PL == 0) -#define MG10_9_17PL ~(1 << 6) -#else -#define MG10_9_17PL 0xFFFF -#endif - -#if (G10_8PL >= G10_9PL) || (G10_8PL == 0) -#define MG10_9_18PL ~(1 << 7) -#else -#define MG10_9_18PL 0xFFFF -#endif - -#if (G10_10PL >= G10_9PL) || (G10_10PL == 0) -#define MG10_9_110PL ~(1 << 9) -#else -#define MG10_9_110PL 0xFFFF -#endif - -#if (G10_11PL >= G10_9PL) || (G10_11PL == 0) -#define MG10_9_111PL ~(1 << 10) -#else -#define MG10_9_111PL 0xFFFF -#endif - -#if (G10_12PL >= G10_9PL) || (G10_12PL == 0) -#define MG10_9_112PL ~(1 << 11) -#else -#define MG10_9_112PL 0xFFFF -#endif - -#if (G10_13PL >= G10_9PL) || (G10_13PL == 0) -#define MG10_9_113PL ~(1 << 12) -#else -#define MG10_9_113PL 0xFFFF -#endif - -#if (G10_14PL >= G10_9PL) || (G10_14PL == 0) -#define MG10_9_114PL ~(1 << 13) -#else -#define MG10_9_114PL 0xFFFF -#endif - -#if (G10_15PL >= G10_9PL) || (G10_15PL == 0) -#define MG10_9_115PL ~(1 << 14) -#else -#define MG10_9_115PL 0xFFFF -#endif - -#if (G10_16PL >= G10_9PL) || (G10_16PL == 0) -#define MG10_9_116PL ~(1 << 15) -#else -#define MG10_9_116PL 0xFFFF -#endif - -#define MG10_9_19PL 0xFEFF -#define MG10_9 (MG10_9_11PL & MG10_9_12PL & MG10_9_13PL & MG10_9_14PL & \ - MG10_9_15PL & MG10_9_16PL & MG10_9_17PL & MG10_9_18PL & \ - MG10_9_19PL & MG10_9_110PL & MG10_9_111PL & MG10_9_112PL & \ - MG10_9_113PL & MG10_9_114PL & MG10_9_115PL & MG10_9_116PL) -// End of MG10_9: -// Beginning of MG1010: -#if (G10_1PL >= G10_10PL) || (G10_1PL == 0) -#define MG10_10_11PL ~(1 << 0) -#else -#define MG10_10_11PL 0xFFFF -#endif - -#if (G10_2PL >= G10_10PL) || (G10_2PL == 0) -#define MG10_10_12PL ~(1 << 1) -#else -#define MG10_10_12PL 0xFFFF -#endif - -#if (G10_3PL >= G10_10PL) || (G10_3PL == 0) -#define MG10_10_13PL ~(1 << 2) -#else -#define MG10_10_13PL 0xFFFF -#endif - -#if (G10_4PL >= G10_10PL) || (G10_4PL == 0) -#define MG10_10_14PL ~(1 << 3) -#else -#define MG10_10_14PL 0xFFFF -#endif - -#if (G10_5PL >= G10_10PL) || (G10_5PL == 0) -#define MG10_10_15PL ~(1 << 4) -#else -#define MG10_10_15PL 0xFFFF -#endif - -#if (G10_6PL >= G10_10PL) || (G10_6PL == 0) -#define MG10_10_16PL ~(1 << 5) -#else -#define MG10_10_16PL 0xFFFF -#endif - -#if (G10_7PL >= G10_10PL) || (G10_7PL == 0) -#define MG10_10_17PL ~(1 << 6) -#else -#define MG10_10_17PL 0xFFFF -#endif - -#if (G10_8PL >= G10_10PL) || (G10_8PL == 0) -#define MG10_10_18PL ~(1 << 7) -#else -#define MG10_10_18PL 0xFFFF -#endif - -#if (G10_9PL >= G10_10PL) || (G10_9PL == 0) -#define MG10_10_19PL ~(1 << 8) -#else -#define MG10_10_19PL 0xFFFF -#endif - -#if (G10_11PL >= G10_10PL) || (G10_11PL == 0) -#define MG10_10_111PL ~(1 << 10) -#else -#define MG10_10_111PL 0xFFFF -#endif - -#if (G10_12PL >= G10_10PL) || (G10_12PL == 0) -#define MG10_10_112PL ~(1 << 11) -#else -#define MG10_10_112PL 0xFFFF -#endif - -#if (G10_13PL >= G10_10PL) || (G10_13PL == 0) -#define MG10_10_113PL ~(1 << 12) -#else -#define MG10_10_113PL 0xFFFF -#endif - -#if (G10_14PL >= G10_10PL) || (G10_14PL == 0) -#define MG10_10_114PL ~(1 << 13) -#else -#define MG10_10_114PL 0xFFFF -#endif - -#if (G10_15PL >= G10_10PL) || (G10_15PL == 0) -#define MG10_10_115PL ~(1 << 14) -#else -#define MG10_10_115PL 0xFFFF -#endif - -#if (G10_16PL >= G10_10PL) || (G10_16PL == 0) -#define MG10_10_116PL ~(1 << 15) -#else -#define MG10_10_116PL 0xFFFF -#endif - -#define MG10_10_110PL 0xFDFF -#define MG10_10 (MG10_10_11PL & MG10_10_12PL & MG10_10_13PL & MG10_10_14PL & \ - MG10_10_15PL & MG10_10_16PL & MG10_10_17PL & MG10_10_18PL & \ - MG10_10_19PL & MG10_10_110PL & MG10_10_111PL & MG10_10_112PL & \ - MG10_10_113PL & MG10_10_114PL & MG10_10_115PL & MG10_10_116PL) -// End of MG10_10: -// Beginning of MG1011: -#if (G10_1PL >= G10_11PL) || (G10_1PL == 0) -#define MG10_11_11PL ~(1 << 0) -#else -#define MG10_11_11PL 0xFFFF -#endif - -#if (G10_2PL >= G10_11PL) || (G10_2PL == 0) -#define MG10_11_12PL ~(1 << 1) -#else -#define MG10_11_12PL 0xFFFF -#endif - -#if (G10_3PL >= G10_11PL) || (G10_3PL == 0) -#define MG10_11_13PL ~(1 << 2) -#else -#define MG10_11_13PL 0xFFFF -#endif - -#if (G10_4PL >= G10_11PL) || (G10_4PL == 0) -#define MG10_11_14PL ~(1 << 3) -#else -#define MG10_11_14PL 0xFFFF -#endif - -#if (G10_5PL >= G10_11PL) || (G10_5PL == 0) -#define MG10_11_15PL ~(1 << 4) -#else -#define MG10_11_15PL 0xFFFF -#endif - -#if (G10_6PL >= G10_11PL) || (G10_6PL == 0) -#define MG10_11_16PL ~(1 << 5) -#else -#define MG10_11_16PL 0xFFFF -#endif - -#if (G10_7PL >= G10_11PL) || (G10_7PL == 0) -#define MG10_11_17PL ~(1 << 6) -#else -#define MG10_11_17PL 0xFFFF -#endif - -#if (G10_8PL >= G10_11PL) || (G10_8PL == 0) -#define MG10_11_18PL ~(1 << 7) -#else -#define MG10_11_18PL 0xFFFF -#endif - -#if (G10_9PL >= G10_11PL) || (G10_9PL == 0) -#define MG10_11_19PL ~(1 << 8) -#else -#define MG10_11_19PL 0xFFFF -#endif - -#if (G10_10PL >= G10_11PL) || (G10_10PL == 0) -#define MG10_11_110PL ~(1 << 9) -#else -#define MG10_11_110PL 0xFFFF -#endif - -#if (G10_12PL >= G10_11PL) || (G10_12PL == 0) -#define MG10_11_112PL ~(1 << 11) -#else -#define MG10_11_112PL 0xFFFF -#endif - -#if (G10_13PL >= G10_11PL) || (G10_13PL == 0) -#define MG10_11_113PL ~(1 << 12) -#else -#define MG10_11_113PL 0xFFFF -#endif - -#if (G10_14PL >= G10_11PL) || (G10_14PL == 0) -#define MG10_11_114PL ~(1 << 13) -#else -#define MG10_11_114PL 0xFFFF -#endif - -#if (G10_15PL >= G10_11PL) || (G10_15PL == 0) -#define MG10_11_115PL ~(1 << 14) -#else -#define MG10_11_115PL 0xFFFF -#endif - -#if (G10_16PL >= G10_11PL) || (G10_16PL == 0) -#define MG10_11_116PL ~(1 << 15) -#else -#define MG10_11_116PL 0xFFFF -#endif - -#define MG10_11_111PL 0xFBFF -#define MG10_11 (MG10_11_11PL & MG10_11_12PL & MG10_11_13PL & MG10_11_14PL & \ - MG10_11_15PL & MG10_11_16PL & MG10_11_17PL & MG10_11_18PL & \ - MG10_11_19PL & MG10_11_110PL & MG10_11_111PL & MG10_11_112PL & \ - MG10_11_113PL & MG10_11_114PL & MG10_11_115PL & MG10_11_116PL) -// End of MG10_11: -// Beginning of MG1012: -#if (G10_1PL >= G10_12PL) || (G10_1PL == 0) -#define MG10_12_11PL ~(1 << 0) -#else -#define MG10_12_11PL 0xFFFF -#endif - -#if (G10_2PL >= G10_12PL) || (G10_2PL == 0) -#define MG10_12_12PL ~(1 << 1) -#else -#define MG10_12_12PL 0xFFFF -#endif - -#if (G10_3PL >= G10_12PL) || (G10_3PL == 0) -#define MG10_12_13PL ~(1 << 2) -#else -#define MG10_12_13PL 0xFFFF -#endif - -#if (G10_4PL >= G10_12PL) || (G10_4PL == 0) -#define MG10_12_14PL ~(1 << 3) -#else -#define MG10_12_14PL 0xFFFF -#endif - -#if (G10_5PL >= G10_12PL) || (G10_5PL == 0) -#define MG10_12_15PL ~(1 << 4) -#else -#define MG10_12_15PL 0xFFFF -#endif - -#if (G10_6PL >= G10_12PL) || (G10_6PL == 0) -#define MG10_12_16PL ~(1 << 5) -#else -#define MG10_12_16PL 0xFFFF -#endif - -#if (G10_7PL >= G10_12PL) || (G10_7PL == 0) -#define MG10_12_17PL ~(1 << 6) -#else -#define MG10_12_17PL 0xFFFF -#endif - -#if (G10_8PL >= G10_12PL) || (G10_8PL == 0) -#define MG10_12_18PL ~(1 << 7) -#else -#define MG10_12_18PL 0xFFFF -#endif - -#if (G10_9PL >= G10_12PL) || (G10_9PL == 0) -#define MG10_12_19PL ~(1 << 8) -#else -#define MG10_12_19PL 0xFFFF -#endif - -#if (G10_10PL >= G10_12PL) || (G10_10PL == 0) -#define MG10_12_110PL ~(1 << 9) -#else -#define MG10_12_110PL 0xFFFF -#endif - -#if (G10_11PL >= G10_12PL) || (G10_11PL == 0) -#define MG10_12_111PL ~(1 << 10) -#else -#define MG10_12_111PL 0xFFFF -#endif - -#if (G10_13PL >= G10_12PL) || (G10_13PL == 0) -#define MG10_12_113PL ~(1 << 12) -#else -#define MG10_12_113PL 0xFFFF -#endif - -#if (G10_14PL >= G10_12PL) || (G10_14PL == 0) -#define MG10_12_114PL ~(1 << 13) -#else -#define MG10_12_114PL 0xFFFF -#endif - -#if (G10_15PL >= G10_12PL) || (G10_15PL == 0) -#define MG10_12_115PL ~(1 << 14) -#else -#define MG10_12_115PL 0xFFFF -#endif - -#if (G10_16PL >= G10_12PL) || (G10_16PL == 0) -#define MG10_12_116PL ~(1 << 15) -#else -#define MG10_12_116PL 0xFFFF -#endif - -#define MG10_12_112PL 0xF7FF -#define MG10_12 (MG10_12_11PL & MG10_12_12PL & MG10_12_13PL & MG10_12_14PL & \ - MG10_12_15PL & MG10_12_16PL & MG10_12_17PL & MG10_12_18PL & \ - MG10_12_19PL & MG10_12_110PL & MG10_12_111PL & MG10_12_112PL & \ - MG10_12_113PL & MG10_12_114PL & MG10_12_115PL & MG10_12_116PL) -// End of MG10_12: -// Beginning of MG1013: -#if (G10_1PL >= G10_13PL) || (G10_1PL == 0) -#define MG10_13_11PL ~(1 << 0) -#else -#define MG10_13_11PL 0xFFFF -#endif - -#if (G10_2PL >= G10_13PL) || (G10_2PL == 0) -#define MG10_13_12PL ~(1 << 1) -#else -#define MG10_13_12PL 0xFFFF -#endif - -#if (G10_3PL >= G10_13PL) || (G10_3PL == 0) -#define MG10_13_13PL ~(1 << 2) -#else -#define MG10_13_13PL 0xFFFF -#endif - -#if (G10_4PL >= G10_13PL) || (G10_4PL == 0) -#define MG10_13_14PL ~(1 << 3) -#else -#define MG10_13_14PL 0xFFFF -#endif - -#if (G10_5PL >= G10_13PL) || (G10_5PL == 0) -#define MG10_13_15PL ~(1 << 4) -#else -#define MG10_13_15PL 0xFFFF -#endif - -#if (G10_6PL >= G10_13PL) || (G10_6PL == 0) -#define MG10_13_16PL ~(1 << 5) -#else -#define MG10_13_16PL 0xFFFF -#endif - -#if (G10_7PL >= G10_13PL) || (G10_7PL == 0) -#define MG10_13_17PL ~(1 << 6) -#else -#define MG10_13_17PL 0xFFFF -#endif - -#if (G10_8PL >= G10_13PL) || (G10_8PL == 0) -#define MG10_13_18PL ~(1 << 7) -#else -#define MG10_13_18PL 0xFFFF -#endif - -#if (G10_9PL >= G10_13PL) || (G10_9PL == 0) -#define MG10_13_19PL ~(1 << 8) -#else -#define MG10_13_19PL 0xFFFF -#endif - -#if (G10_10PL >= G10_13PL) || (G10_10PL == 0) -#define MG10_13_110PL ~(1 << 9) -#else -#define MG10_13_110PL 0xFFFF -#endif - -#if (G10_11PL >= G10_13PL) || (G10_11PL == 0) -#define MG10_13_111PL ~(1 << 10) -#else -#define MG10_13_111PL 0xFFFF -#endif - -#if (G10_12PL >= G10_13PL) || (G10_12PL == 0) -#define MG10_13_112PL ~(1 << 11) -#else -#define MG10_13_112PL 0xFFFF -#endif - -#if (G10_14PL >= G10_13PL) || (G10_14PL == 0) -#define MG10_13_114PL ~(1 << 13) -#else -#define MG10_13_114PL 0xFFFF -#endif - -#if (G10_15PL >= G10_13PL) || (G10_15PL == 0) -#define MG10_13_115PL ~(1 << 14) -#else -#define MG10_13_115PL 0xFFFF -#endif - -#if (G10_16PL >= G10_13PL) || (G10_16PL == 0) -#define MG10_13_116PL ~(1 << 15) -#else -#define MG10_13_116PL 0xFFFF -#endif - -#define MG10_13_113PL 0xEFFF -#define MG10_13 (MG10_13_11PL & MG10_13_12PL & MG10_13_13PL & MG10_13_14PL & \ - MG10_13_15PL & MG10_13_16PL & MG10_13_17PL & MG10_13_18PL & \ - MG10_13_19PL & MG10_13_110PL & MG10_13_111PL & MG10_13_112PL & \ - MG10_13_113PL & MG10_13_114PL & MG10_13_115PL & MG10_13_116PL) -// End of MG10_13: -// Beginning of MG1014: -#if (G10_1PL >= G10_14PL) || (G10_1PL == 0) -#define MG10_14_11PL ~(1 << 0) -#else -#define MG10_14_11PL 0xFFFF -#endif - -#if (G10_2PL >= G10_14PL) || (G10_2PL == 0) -#define MG10_14_12PL ~(1 << 1) -#else -#define MG10_14_12PL 0xFFFF -#endif - -#if (G10_3PL >= G10_14PL) || (G10_3PL == 0) -#define MG10_14_13PL ~(1 << 2) -#else -#define MG10_14_13PL 0xFFFF -#endif - -#if (G10_4PL >= G10_14PL) || (G10_4PL == 0) -#define MG10_14_14PL ~(1 << 3) -#else -#define MG10_14_14PL 0xFFFF -#endif - -#if (G10_5PL >= G10_14PL) || (G10_5PL == 0) -#define MG10_14_15PL ~(1 << 4) -#else -#define MG10_14_15PL 0xFFFF -#endif - -#if (G10_6PL >= G10_14PL) || (G10_6PL == 0) -#define MG10_14_16PL ~(1 << 5) -#else -#define MG10_14_16PL 0xFFFF -#endif - -#if (G10_7PL >= G10_14PL) || (G10_7PL == 0) -#define MG10_14_17PL ~(1 << 6) -#else -#define MG10_14_17PL 0xFFFF -#endif - -#if (G10_8PL >= G10_14PL) || (G10_8PL == 0) -#define MG10_14_18PL ~(1 << 7) -#else -#define MG10_14_18PL 0xFFFF -#endif - -#if (G10_9PL >= G10_14PL) || (G10_9PL == 0) -#define MG10_14_19PL ~(1 << 8) -#else -#define MG10_14_19PL 0xFFFF -#endif - -#if (G10_10PL >= G10_14PL) || (G10_10PL == 0) -#define MG10_14_110PL ~(1 << 9) -#else -#define MG10_14_110PL 0xFFFF -#endif - -#if (G10_11PL >= G10_14PL) || (G10_11PL == 0) -#define MG10_14_111PL ~(1 << 10) -#else -#define MG10_14_111PL 0xFFFF -#endif - -#if (G10_12PL >= G10_14PL) || (G10_12PL == 0) -#define MG10_14_112PL ~(1 << 11) -#else -#define MG10_14_112PL 0xFFFF -#endif - -#if (G10_13PL >= G10_14PL) || (G10_13PL == 0) -#define MG10_14_113PL ~(1 << 12) -#else -#define MG10_14_113PL 0xFFFF -#endif - -#if (G10_15PL >= G10_14PL) || (G10_15PL == 0) -#define MG10_14_115PL ~(1 << 14) -#else -#define MG10_14_115PL 0xFFFF -#endif - -#if (G10_16PL >= G10_14PL) || (G10_16PL == 0) -#define MG10_14_116PL ~(1 << 15) -#else -#define MG10_14_116PL 0xFFFF -#endif - -#define MG10_14_114PL 0xDFFF -#define MG10_14 (MG10_14_11PL & MG10_14_12PL & MG10_14_13PL & MG10_14_14PL & \ - MG10_14_15PL & MG10_14_16PL & MG10_14_17PL & MG10_14_18PL & \ - MG10_14_19PL & MG10_14_110PL & MG10_14_111PL & MG10_14_112PL & \ - MG10_14_113PL & MG10_14_114PL & MG10_14_115PL & MG10_14_116PL) -// End of MG10_14: -// Beginning of MG1015: -#if (G10_1PL >= G10_15PL) || (G10_1PL == 0) -#define MG10_15_11PL ~(1 << 0) -#else -#define MG10_15_11PL 0xFFFF -#endif - -#if (G10_2PL >= G10_15PL) || (G10_2PL == 0) -#define MG10_15_12PL ~(1 << 1) -#else -#define MG10_15_12PL 0xFFFF -#endif - -#if (G10_3PL >= G10_15PL) || (G10_3PL == 0) -#define MG10_15_13PL ~(1 << 2) -#else -#define MG10_15_13PL 0xFFFF -#endif - -#if (G10_4PL >= G10_15PL) || (G10_4PL == 0) -#define MG10_15_14PL ~(1 << 3) -#else -#define MG10_15_14PL 0xFFFF -#endif - -#if (G10_5PL >= G10_15PL) || (G10_5PL == 0) -#define MG10_15_15PL ~(1 << 4) -#else -#define MG10_15_15PL 0xFFFF -#endif - -#if (G10_6PL >= G10_15PL) || (G10_6PL == 0) -#define MG10_15_16PL ~(1 << 5) -#else -#define MG10_15_16PL 0xFFFF -#endif - -#if (G10_7PL >= G10_15PL) || (G10_7PL == 0) -#define MG10_15_17PL ~(1 << 6) -#else -#define MG10_15_17PL 0xFFFF -#endif - -#if (G10_8PL >= G10_15PL) || (G10_8PL == 0) -#define MG10_15_18PL ~(1 << 7) -#else -#define MG10_15_18PL 0xFFFF -#endif - -#if (G10_9PL >= G10_15PL) || (G10_9PL == 0) -#define MG10_15_19PL ~(1 << 8) -#else -#define MG10_15_19PL 0xFFFF -#endif - -#if (G10_10PL >= G10_15PL) || (G10_10PL == 0) -#define MG10_15_110PL ~(1 << 9) -#else -#define MG10_15_110PL 0xFFFF -#endif - -#if (G10_11PL >= G10_15PL) || (G10_11PL == 0) -#define MG10_15_111PL ~(1 << 10) -#else -#define MG10_15_111PL 0xFFFF -#endif - -#if (G10_12PL >= G10_15PL) || (G10_12PL == 0) -#define MG10_15_112PL ~(1 << 11) -#else -#define MG10_15_112PL 0xFFFF -#endif - -#if (G10_13PL >= G10_15PL) || (G10_13PL == 0) -#define MG10_15_113PL ~(1 << 12) -#else -#define MG10_15_113PL 0xFFFF -#endif - -#if (G10_14PL >= G10_15PL) || (G10_14PL == 0) -#define MG10_15_114PL ~(1 << 13) -#else -#define MG10_15_114PL 0xFFFF -#endif - -#if (G10_16PL >= G10_15PL) || (G10_16PL == 0) -#define MG10_15_116PL ~(1 << 15) -#else -#define MG10_15_116PL 0xFFFF -#endif - -#define MG10_15_115PL 0xBFFF -#define MG10_15 (MG10_15_11PL & MG10_15_12PL & MG10_15_13PL & MG10_15_14PL & \ - MG10_15_15PL & MG10_15_16PL & MG10_15_17PL & MG10_15_18PL & \ - MG10_15_19PL & MG10_15_110PL & MG10_15_111PL & MG10_15_112PL & \ - MG10_15_113PL & MG10_15_114PL & MG10_15_115PL & MG10_15_116PL) -// End of MG10_15: -// Beginning of MG1016: -#if (G10_1PL >= G10_16PL) || (G10_1PL == 0) -#define MG10_16_11PL ~(1 << 0) -#else -#define MG10_16_11PL 0xFFFF -#endif - -#if (G10_2PL >= G10_16PL) || (G10_2PL == 0) -#define MG10_16_12PL ~(1 << 1) -#else -#define MG10_16_12PL 0xFFFF -#endif - -#if (G10_3PL >= G10_16PL) || (G10_3PL == 0) -#define MG10_16_13PL ~(1 << 2) -#else -#define MG10_16_13PL 0xFFFF -#endif - -#if (G10_4PL >= G10_16PL) || (G10_4PL == 0) -#define MG10_16_14PL ~(1 << 3) -#else -#define MG10_16_14PL 0xFFFF -#endif - -#if (G10_5PL >= G10_16PL) || (G10_5PL == 0) -#define MG10_16_15PL ~(1 << 4) -#else -#define MG10_16_15PL 0xFFFF -#endif - -#if (G10_6PL >= G10_16PL) || (G10_6PL == 0) -#define MG10_16_16PL ~(1 << 5) -#else -#define MG10_16_16PL 0xFFFF -#endif - -#if (G10_7PL >= G10_16PL) || (G10_7PL == 0) -#define MG10_16_17PL ~(1 << 6) -#else -#define MG10_16_17PL 0xFFFF -#endif - -#if (G10_8PL >= G10_16PL) || (G10_8PL == 0) -#define MG10_16_18PL ~(1 << 7) -#else -#define MG10_16_18PL 0xFFFF -#endif - -#if (G10_9PL >= G10_16PL) || (G10_9PL == 0) -#define MG10_16_19PL ~(1 << 8) -#else -#define MG10_16_19PL 0xFFFF -#endif - -#if (G10_10PL >= G10_16PL) || (G10_10PL == 0) -#define MG10_16_110PL ~(1 << 9) -#else -#define MG10_16_110PL 0xFFFF -#endif - -#if (G10_11PL >= G10_16PL) || (G10_11PL == 0) -#define MG10_16_111PL ~(1 << 10) -#else -#define MG10_16_111PL 0xFFFF -#endif - -#if (G10_12PL >= G10_16PL) || (G10_12PL == 0) -#define MG10_16_112PL ~(1 << 11) -#else -#define MG10_16_112PL 0xFFFF -#endif - -#if (G10_13PL >= G10_16PL) || (G10_13PL == 0) -#define MG10_16_113PL ~(1 << 12) -#else -#define MG10_16_113PL 0xFFFF -#endif - -#if (G10_14PL >= G10_16PL) || (G10_14PL == 0) -#define MG10_16_114PL ~(1 << 13) -#else -#define MG10_16_114PL 0xFFFF -#endif - -#if (G10_15PL >= G10_16PL) || (G10_15PL == 0) -#define MG10_16_115PL ~(1 << 14) -#else -#define MG10_16_115PL 0xFFFF -#endif - -#define MG10_16_116PL 0x7FFF -#define MG10_16 (MG10_16_11PL & MG10_16_12PL & MG10_16_13PL & MG10_16_14PL & \ - MG10_16_15PL & MG10_16_16PL & MG10_16_17PL & MG10_16_18PL & \ - MG10_16_19PL & MG10_16_110PL & MG10_16_111PL & MG10_16_112PL & \ - MG10_16_113PL & MG10_16_114PL & MG10_16_115PL & MG10_16_116PL) -// End of MG10_16: - - -// -// Automatically generate PIEIER11 interrupt masks MG111 to MG1116: -// - -// Beginning of MG111: -#if (G11_2PL >= G11_1PL) || (G11_2PL == 0) -#define MG11_1_12PL ~(1 << 1) -#else -#define MG11_1_12PL 0xFFFF -#endif - -#if (G11_3PL >= G11_1PL) || (G11_3PL == 0) -#define MG11_1_13PL ~(1 << 2) -#else -#define MG11_1_13PL 0xFFFF -#endif - -#if (G11_4PL >= G11_1PL) || (G11_4PL == 0) -#define MG11_1_14PL ~(1 << 3) -#else -#define MG11_1_14PL 0xFFFF -#endif - -#if (G11_5PL >= G11_1PL) || (G11_5PL == 0) -#define MG11_1_15PL ~(1 << 4) -#else -#define MG11_1_15PL 0xFFFF -#endif - -#if (G11_6PL >= G11_1PL) || (G11_6PL == 0) -#define MG11_1_16PL ~(1 << 5) -#else -#define MG11_1_16PL 0xFFFF -#endif - -#if (G11_7PL >= G11_1PL) || (G11_7PL == 0) -#define MG11_1_17PL ~(1 << 6) -#else -#define MG11_1_17PL 0xFFFF -#endif - -#if (G11_8PL >= G11_1PL) || (G11_8PL == 0) -#define MG11_1_18PL ~(1 << 7) -#else -#define MG11_1_18PL 0xFFFF -#endif - -#if (G11_9PL >= G11_1PL) || (G11_9PL == 0) -#define MG11_1_19PL ~(1 << 8) -#else -#define MG11_1_19PL 0xFFFF -#endif - -#if (G11_10PL >= G11_1PL) || (G11_10PL == 0) -#define MG11_1_110PL ~(1 << 9) -#else -#define MG11_1_110PL 0xFFFF -#endif - -#if (G11_11PL >= G11_1PL) || (G11_11PL == 0) -#define MG11_1_111PL ~(1 << 10) -#else -#define MG11_1_111PL 0xFFFF -#endif - -#if (G11_12PL >= G11_1PL) || (G11_12PL == 0) -#define MG11_1_112PL ~(1 << 11) -#else -#define MG11_1_112PL 0xFFFF -#endif - -#if (G11_13PL >= G11_1PL) || (G11_13PL == 0) -#define MG11_1_113PL ~(1 << 12) -#else -#define MG11_1_113PL 0xFFFF -#endif - -#if (G11_14PL >= G11_1PL) || (G11_14PL == 0) -#define MG11_1_114PL ~(1 << 13) -#else -#define MG11_1_114PL 0xFFFF -#endif - -#if (G11_15PL >= G11_1PL) || (G11_15PL == 0) -#define MG11_1_115PL ~(1 << 14) -#else -#define MG11_1_115PL 0xFFFF -#endif - -#if (G11_16PL >= G11_1PL) || (G11_16PL == 0) -#define MG11_1_116PL ~(1 << 15) -#else -#define MG11_1_116PL 0xFFFF -#endif - -#define MG11_1_11PL 0xFFFE -#define MG11_1 (MG11_1_11PL & MG11_1_12PL & MG11_1_13PL & MG11_1_14PL & \ - MG11_1_15PL & MG11_1_16PL & MG11_1_17PL & MG11_1_18PL & \ - MG11_1_19PL & MG11_1_110PL & MG11_1_111PL & MG11_1_112PL & \ - MG11_1_113PL & MG11_1_114PL & MG11_1_115PL & MG11_1_116PL) -// End of MG11_1: -// Beginning of MG112: -#if (G11_1PL >= G11_2PL) || (G11_1PL == 0) -#define MG11_2_11PL ~(1 << 0) -#else -#define MG11_2_11PL 0xFFFF -#endif - -#if (G11_3PL >= G11_2PL) || (G11_3PL == 0) -#define MG11_2_13PL ~(1 << 2) -#else -#define MG11_2_13PL 0xFFFF -#endif - -#if (G11_4PL >= G11_2PL) || (G11_4PL == 0) -#define MG11_2_14PL ~(1 << 3) -#else -#define MG11_2_14PL 0xFFFF -#endif - -#if (G11_5PL >= G11_2PL) || (G11_5PL == 0) -#define MG11_2_15PL ~(1 << 4) -#else -#define MG11_2_15PL 0xFFFF -#endif - -#if (G11_6PL >= G11_2PL) || (G11_6PL == 0) -#define MG11_2_16PL ~(1 << 5) -#else -#define MG11_2_16PL 0xFFFF -#endif - -#if (G11_7PL >= G11_2PL) || (G11_7PL == 0) -#define MG11_2_17PL ~(1 << 6) -#else -#define MG11_2_17PL 0xFFFF -#endif - -#if (G11_8PL >= G11_2PL) || (G11_8PL == 0) -#define MG11_2_18PL ~(1 << 7) -#else -#define MG11_2_18PL 0xFFFF -#endif - -#if (G11_9PL >= G11_2PL) || (G11_9PL == 0) -#define MG11_2_19PL ~(1 << 8) -#else -#define MG11_2_19PL 0xFFFF -#endif - -#if (G11_10PL >= G11_2PL) || (G11_10PL == 0) -#define MG11_2_110PL ~(1 << 9) -#else -#define MG11_2_110PL 0xFFFF -#endif - -#if (G11_11PL >= G11_2PL) || (G11_11PL == 0) -#define MG11_2_111PL ~(1 << 10) -#else -#define MG11_2_111PL 0xFFFF -#endif - -#if (G11_12PL >= G11_2PL) || (G11_12PL == 0) -#define MG11_2_112PL ~(1 << 11) -#else -#define MG11_2_112PL 0xFFFF -#endif - -#if (G11_13PL >= G11_2PL) || (G11_13PL == 0) -#define MG11_2_113PL ~(1 << 12) -#else -#define MG11_2_113PL 0xFFFF -#endif - -#if (G11_14PL >= G11_2PL) || (G11_14PL == 0) -#define MG11_2_114PL ~(1 << 13) -#else -#define MG11_2_114PL 0xFFFF -#endif - -#if (G11_15PL >= G11_2PL) || (G11_15PL == 0) -#define MG11_2_115PL ~(1 << 14) -#else -#define MG11_2_115PL 0xFFFF -#endif - -#if (G11_16PL >= G11_2PL) || (G11_16PL == 0) -#define MG11_2_116PL ~(1 << 15) -#else -#define MG11_2_116PL 0xFFFF -#endif - -#define MG11_2_12PL 0xFFFD -#define MG11_2 (MG11_2_11PL & MG11_2_12PL & MG11_2_13PL & MG11_2_14PL & \ - MG11_2_15PL & MG11_2_16PL & MG11_2_17PL & MG11_2_18PL & \ - MG11_2_19PL & MG11_2_110PL & MG11_2_111PL & MG11_2_112PL & \ - MG11_2_113PL & MG11_2_114PL & MG11_2_115PL & MG11_2_116PL) -// End of MG11_2: -// Beginning of MG113: -#if (G11_1PL >= G11_3PL) || (G11_1PL == 0) -#define MG11_3_11PL ~(1 << 0) -#else -#define MG11_3_11PL 0xFFFF -#endif - -#if (G11_2PL >= G11_3PL) || (G11_2PL == 0) -#define MG11_3_12PL ~(1 << 1) -#else -#define MG11_3_12PL 0xFFFF -#endif - -#if (G11_4PL >= G11_3PL) || (G11_4PL == 0) -#define MG11_3_14PL ~(1 << 3) -#else -#define MG11_3_14PL 0xFFFF -#endif - -#if (G11_5PL >= G11_3PL) || (G11_5PL == 0) -#define MG11_3_15PL ~(1 << 4) -#else -#define MG11_3_15PL 0xFFFF -#endif - -#if (G11_6PL >= G11_3PL) || (G11_6PL == 0) -#define MG11_3_16PL ~(1 << 5) -#else -#define MG11_3_16PL 0xFFFF -#endif - -#if (G11_7PL >= G11_3PL) || (G11_7PL == 0) -#define MG11_3_17PL ~(1 << 6) -#else -#define MG11_3_17PL 0xFFFF -#endif - -#if (G11_8PL >= G11_3PL) || (G11_8PL == 0) -#define MG11_3_18PL ~(1 << 7) -#else -#define MG11_3_18PL 0xFFFF -#endif - -#if (G11_9PL >= G11_3PL) || (G11_9PL == 0) -#define MG11_3_19PL ~(1 << 8) -#else -#define MG11_3_19PL 0xFFFF -#endif - -#if (G11_10PL >= G11_3PL) || (G11_10PL == 0) -#define MG11_3_110PL ~(1 << 9) -#else -#define MG11_3_110PL 0xFFFF -#endif - -#if (G11_11PL >= G11_3PL) || (G11_11PL == 0) -#define MG11_3_111PL ~(1 << 10) -#else -#define MG11_3_111PL 0xFFFF -#endif - -#if (G11_12PL >= G11_3PL) || (G11_12PL == 0) -#define MG11_3_112PL ~(1 << 11) -#else -#define MG11_3_112PL 0xFFFF -#endif - -#if (G11_13PL >= G11_3PL) || (G11_13PL == 0) -#define MG11_3_113PL ~(1 << 12) -#else -#define MG11_3_113PL 0xFFFF -#endif - -#if (G11_14PL >= G11_3PL) || (G11_14PL == 0) -#define MG11_3_114PL ~(1 << 13) -#else -#define MG11_3_114PL 0xFFFF -#endif - -#if (G11_15PL >= G11_3PL) || (G11_15PL == 0) -#define MG11_3_115PL ~(1 << 14) -#else -#define MG11_3_115PL 0xFFFF -#endif - -#if (G11_16PL >= G11_3PL) || (G11_16PL == 0) -#define MG11_3_116PL ~(1 << 15) -#else -#define MG11_3_116PL 0xFFFF -#endif - -#define MG11_3_13PL 0xFFFB -#define MG11_3 (MG11_3_11PL & MG11_3_12PL & MG11_3_13PL & MG11_3_14PL & \ - MG11_3_15PL & MG11_3_16PL & MG11_3_17PL & MG11_3_18PL & \ - MG11_3_19PL & MG11_3_110PL & MG11_3_111PL & MG11_3_112PL & \ - MG11_3_113PL & MG11_3_114PL & MG11_3_115PL & MG11_3_116PL) -// End of MG11_3: -// Beginning of MG114: -#if (G11_1PL >= G11_4PL) || (G11_1PL == 0) -#define MG11_4_11PL ~(1 << 0) -#else -#define MG11_4_11PL 0xFFFF -#endif - -#if (G11_2PL >= G11_4PL) || (G11_2PL == 0) -#define MG11_4_12PL ~(1 << 1) -#else -#define MG11_4_12PL 0xFFFF -#endif - -#if (G11_3PL >= G11_4PL) || (G11_3PL == 0) -#define MG11_4_13PL ~(1 << 2) -#else -#define MG11_4_13PL 0xFFFF -#endif - -#if (G11_5PL >= G11_4PL) || (G11_5PL == 0) -#define MG11_4_15PL ~(1 << 4) -#else -#define MG11_4_15PL 0xFFFF -#endif - -#if (G11_6PL >= G11_4PL) || (G11_6PL == 0) -#define MG11_4_16PL ~(1 << 5) -#else -#define MG11_4_16PL 0xFFFF -#endif - -#if (G11_7PL >= G11_4PL) || (G11_7PL == 0) -#define MG11_4_17PL ~(1 << 6) -#else -#define MG11_4_17PL 0xFFFF -#endif - -#if (G11_8PL >= G11_4PL) || (G11_8PL == 0) -#define MG11_4_18PL ~(1 << 7) -#else -#define MG11_4_18PL 0xFFFF -#endif - -#if (G11_9PL >= G11_4PL) || (G11_9PL == 0) -#define MG11_4_19PL ~(1 << 8) -#else -#define MG11_4_19PL 0xFFFF -#endif - -#if (G11_10PL >= G11_4PL) || (G11_10PL == 0) -#define MG11_4_110PL ~(1 << 9) -#else -#define MG11_4_110PL 0xFFFF -#endif - -#if (G11_11PL >= G11_4PL) || (G11_11PL == 0) -#define MG11_4_111PL ~(1 << 10) -#else -#define MG11_4_111PL 0xFFFF -#endif - -#if (G11_12PL >= G11_4PL) || (G11_12PL == 0) -#define MG11_4_112PL ~(1 << 11) -#else -#define MG11_4_112PL 0xFFFF -#endif - -#if (G11_13PL >= G11_4PL) || (G11_13PL == 0) -#define MG11_4_113PL ~(1 << 12) -#else -#define MG11_4_113PL 0xFFFF -#endif - -#if (G11_14PL >= G11_4PL) || (G11_14PL == 0) -#define MG11_4_114PL ~(1 << 13) -#else -#define MG11_4_114PL 0xFFFF -#endif - -#if (G11_15PL >= G11_4PL) || (G11_15PL == 0) -#define MG11_4_115PL ~(1 << 14) -#else -#define MG11_4_115PL 0xFFFF -#endif - -#if (G11_16PL >= G11_4PL) || (G11_16PL == 0) -#define MG11_4_116PL ~(1 << 15) -#else -#define MG11_4_116PL 0xFFFF -#endif - -#define MG11_4_14PL 0xFFF7 -#define MG11_4 (MG11_4_11PL & MG11_4_12PL & MG11_4_13PL & MG11_4_14PL & \ - MG11_4_15PL & MG11_4_16PL & MG11_4_17PL & MG11_4_18PL & \ - MG11_4_19PL & MG11_4_110PL & MG11_4_111PL & MG11_4_112PL & \ - MG11_4_113PL & MG11_4_114PL & MG11_4_115PL & MG11_4_116PL) -// End of MG11_4: -// Beginning of MG115: -#if (G11_1PL >= G11_5PL) || (G11_1PL == 0) -#define MG11_5_11PL ~(1 << 0) -#else -#define MG11_5_11PL 0xFFFF -#endif - -#if (G11_2PL >= G11_5PL) || (G11_2PL == 0) -#define MG11_5_12PL ~(1 << 1) -#else -#define MG11_5_12PL 0xFFFF -#endif - -#if (G11_3PL >= G11_5PL) || (G11_3PL == 0) -#define MG11_5_13PL ~(1 << 2) -#else -#define MG11_5_13PL 0xFFFF -#endif - -#if (G11_4PL >= G11_5PL) || (G11_4PL == 0) -#define MG11_5_14PL ~(1 << 3) -#else -#define MG11_5_14PL 0xFFFF -#endif - -#if (G11_6PL >= G11_5PL) || (G11_6PL == 0) -#define MG11_5_16PL ~(1 << 5) -#else -#define MG11_5_16PL 0xFFFF -#endif - -#if (G11_7PL >= G11_5PL) || (G11_7PL == 0) -#define MG11_5_17PL ~(1 << 6) -#else -#define MG11_5_17PL 0xFFFF -#endif - -#if (G11_8PL >= G11_5PL) || (G11_8PL == 0) -#define MG11_5_18PL ~(1 << 7) -#else -#define MG11_5_18PL 0xFFFF -#endif - -#if (G11_9PL >= G11_5PL) || (G11_9PL == 0) -#define MG11_5_19PL ~(1 << 8) -#else -#define MG11_5_19PL 0xFFFF -#endif - -#if (G11_10PL >= G11_5PL) || (G11_10PL == 0) -#define MG11_5_110PL ~(1 << 9) -#else -#define MG11_5_110PL 0xFFFF -#endif - -#if (G11_11PL >= G11_5PL) || (G11_11PL == 0) -#define MG11_5_111PL ~(1 << 10) -#else -#define MG11_5_111PL 0xFFFF -#endif - -#if (G11_12PL >= G11_5PL) || (G11_12PL == 0) -#define MG11_5_112PL ~(1 << 11) -#else -#define MG11_5_112PL 0xFFFF -#endif - -#if (G11_13PL >= G11_5PL) || (G11_13PL == 0) -#define MG11_5_113PL ~(1 << 12) -#else -#define MG11_5_113PL 0xFFFF -#endif - -#if (G11_14PL >= G11_5PL) || (G11_14PL == 0) -#define MG11_5_114PL ~(1 << 13) -#else -#define MG11_5_114PL 0xFFFF -#endif - -#if (G11_15PL >= G11_5PL) || (G11_15PL == 0) -#define MG11_5_115PL ~(1 << 14) -#else -#define MG11_5_115PL 0xFFFF -#endif - -#if (G11_16PL >= G11_5PL) || (G11_16PL == 0) -#define MG11_5_116PL ~(1 << 15) -#else -#define MG11_5_116PL 0xFFFF -#endif - -#define MG11_5_15PL 0xFFEF -#define MG11_5 (MG11_5_11PL & MG11_5_12PL & MG11_5_13PL & MG11_5_14PL & \ - MG11_5_15PL & MG11_5_16PL & MG11_5_17PL & MG11_5_18PL & \ - MG11_5_19PL & MG11_5_110PL & MG11_5_111PL & MG11_5_112PL & \ - MG11_5_113PL & MG11_5_114PL & MG11_5_115PL & MG11_5_116PL) -// End of MG11_5: -// Beginning of MG116: -#if (G11_1PL >= G11_6PL) || (G11_1PL == 0) -#define MG11_6_11PL ~(1 << 0) -#else -#define MG11_6_11PL 0xFFFF -#endif - -#if (G11_2PL >= G11_6PL) || (G11_2PL == 0) -#define MG11_6_12PL ~(1 << 1) -#else -#define MG11_6_12PL 0xFFFF -#endif - -#if (G11_3PL >= G11_6PL) || (G11_3PL == 0) -#define MG11_6_13PL ~(1 << 2) -#else -#define MG11_6_13PL 0xFFFF -#endif - -#if (G11_4PL >= G11_6PL) || (G11_4PL == 0) -#define MG11_6_14PL ~(1 << 3) -#else -#define MG11_6_14PL 0xFFFF -#endif - -#if (G11_5PL >= G11_6PL) || (G11_5PL == 0) -#define MG11_6_15PL ~(1 << 4) -#else -#define MG11_6_15PL 0xFFFF -#endif - -#if (G11_7PL >= G11_6PL) || (G11_7PL == 0) -#define MG11_6_17PL ~(1 << 6) -#else -#define MG11_6_17PL 0xFFFF -#endif - -#if (G11_8PL >= G11_6PL) || (G11_8PL == 0) -#define MG11_6_18PL ~(1 << 7) -#else -#define MG11_6_18PL 0xFFFF -#endif - -#if (G11_9PL >= G11_6PL) || (G11_9PL == 0) -#define MG11_6_19PL ~(1 << 8) -#else -#define MG11_6_19PL 0xFFFF -#endif - -#if (G11_10PL >= G11_6PL) || (G11_10PL == 0) -#define MG11_6_110PL ~(1 << 9) -#else -#define MG11_6_110PL 0xFFFF -#endif - -#if (G11_11PL >= G11_6PL) || (G11_11PL == 0) -#define MG11_6_111PL ~(1 << 10) -#else -#define MG11_6_111PL 0xFFFF -#endif - -#if (G11_12PL >= G11_6PL) || (G11_12PL == 0) -#define MG11_6_112PL ~(1 << 11) -#else -#define MG11_6_112PL 0xFFFF -#endif - -#if (G11_13PL >= G11_6PL) || (G11_13PL == 0) -#define MG11_6_113PL ~(1 << 12) -#else -#define MG11_6_113PL 0xFFFF -#endif - -#if (G11_14PL >= G11_6PL) || (G11_14PL == 0) -#define MG11_6_114PL ~(1 << 13) -#else -#define MG11_6_114PL 0xFFFF -#endif - -#if (G11_15PL >= G11_6PL) || (G11_15PL == 0) -#define MG11_6_115PL ~(1 << 14) -#else -#define MG11_6_115PL 0xFFFF -#endif - -#if (G11_16PL >= G11_6PL) || (G11_16PL == 0) -#define MG11_6_116PL ~(1 << 15) -#else -#define MG11_6_116PL 0xFFFF -#endif - -#define MG11_6_16PL 0xFFDF -#define MG11_6 (MG11_6_11PL & MG11_6_12PL & MG11_6_13PL & MG11_6_14PL & \ - MG11_6_15PL & MG11_6_16PL & MG11_6_17PL & MG11_6_18PL & \ - MG11_6_19PL & MG11_6_110PL & MG11_6_111PL & MG11_6_112PL & \ - MG11_6_113PL & MG11_6_114PL & MG11_6_115PL & MG11_6_116PL) -// End of MG11_6: -// Beginning of MG117: -#if (G11_1PL >= G11_7PL) || (G11_1PL == 0) -#define MG11_7_11PL ~(1 << 0) -#else -#define MG11_7_11PL 0xFFFF -#endif - -#if (G11_2PL >= G11_7PL) || (G11_2PL == 0) -#define MG11_7_12PL ~(1 << 1) -#else -#define MG11_7_12PL 0xFFFF -#endif - -#if (G11_3PL >= G11_7PL) || (G11_3PL == 0) -#define MG11_7_13PL ~(1 << 2) -#else -#define MG11_7_13PL 0xFFFF -#endif - -#if (G11_4PL >= G11_7PL) || (G11_4PL == 0) -#define MG11_7_14PL ~(1 << 3) -#else -#define MG11_7_14PL 0xFFFF -#endif - -#if (G11_5PL >= G11_7PL) || (G11_5PL == 0) -#define MG11_7_15PL ~(1 << 4) -#else -#define MG11_7_15PL 0xFFFF -#endif - -#if (G11_6PL >= G11_7PL) || (G11_6PL == 0) -#define MG11_7_16PL ~(1 << 5) -#else -#define MG11_7_16PL 0xFFFF -#endif - -#if (G11_8PL >= G11_7PL) || (G11_8PL == 0) -#define MG11_7_18PL ~(1 << 7) -#else -#define MG11_7_18PL 0xFFFF -#endif - -#if (G11_9PL >= G11_7PL) || (G11_9PL == 0) -#define MG11_7_19PL ~(1 << 8) -#else -#define MG11_7_19PL 0xFFFF -#endif - -#if (G11_10PL >= G11_7PL) || (G11_10PL == 0) -#define MG11_7_110PL ~(1 << 9) -#else -#define MG11_7_110PL 0xFFFF -#endif - -#if (G11_11PL >= G11_7PL) || (G11_11PL == 0) -#define MG11_7_111PL ~(1 << 10) -#else -#define MG11_7_111PL 0xFFFF -#endif - -#if (G11_12PL >= G11_7PL) || (G11_12PL == 0) -#define MG11_7_112PL ~(1 << 11) -#else -#define MG11_7_112PL 0xFFFF -#endif - -#if (G11_13PL >= G11_7PL) || (G11_13PL == 0) -#define MG11_7_113PL ~(1 << 12) -#else -#define MG11_7_113PL 0xFFFF -#endif - -#if (G11_14PL >= G11_7PL) || (G11_14PL == 0) -#define MG11_7_114PL ~(1 << 13) -#else -#define MG11_7_114PL 0xFFFF -#endif - -#if (G11_15PL >= G11_7PL) || (G11_15PL == 0) -#define MG11_7_115PL ~(1 << 14) -#else -#define MG11_7_115PL 0xFFFF -#endif - -#if (G11_16PL >= G11_7PL) || (G11_16PL == 0) -#define MG11_7_116PL ~(1 << 15) -#else -#define MG11_7_116PL 0xFFFF -#endif - -#define MG11_7_17PL 0xFFBF -#define MG11_7 (MG11_7_11PL & MG11_7_12PL & MG11_7_13PL & MG11_7_14PL & \ - MG11_7_15PL & MG11_7_16PL & MG11_7_17PL & MG11_7_18PL & \ - MG11_7_19PL & MG11_7_110PL & MG11_7_111PL & MG11_7_112PL & \ - MG11_7_113PL & MG11_7_114PL & MG11_7_115PL & MG11_7_116PL) -// End of MG11_7: -// Beginning of MG118: -#if (G11_1PL >= G11_8PL) || (G11_1PL == 0) -#define MG11_8_11PL ~(1 << 0) -#else -#define MG11_8_11PL 0xFFFF -#endif - -#if (G11_2PL >= G11_8PL) || (G11_2PL == 0) -#define MG11_8_12PL ~(1 << 1) -#else -#define MG11_8_12PL 0xFFFF -#endif - -#if (G11_3PL >= G11_8PL) || (G11_3PL == 0) -#define MG11_8_13PL ~(1 << 2) -#else -#define MG11_8_13PL 0xFFFF -#endif - -#if (G11_4PL >= G11_8PL) || (G11_4PL == 0) -#define MG11_8_14PL ~(1 << 3) -#else -#define MG11_8_14PL 0xFFFF -#endif - -#if (G11_5PL >= G11_8PL) || (G11_5PL == 0) -#define MG11_8_15PL ~(1 << 4) -#else -#define MG11_8_15PL 0xFFFF -#endif - -#if (G11_6PL >= G11_8PL) || (G11_6PL == 0) -#define MG11_8_16PL ~(1 << 5) -#else -#define MG11_8_16PL 0xFFFF -#endif - -#if (G11_7PL >= G11_8PL) || (G11_7PL == 0) -#define MG11_8_17PL ~(1 << 6) -#else -#define MG11_8_17PL 0xFFFF -#endif - -#if (G11_9PL >= G11_8PL) || (G11_9PL == 0) -#define MG11_8_19PL ~(1 << 8) -#else -#define MG11_8_19PL 0xFFFF -#endif - -#if (G11_10PL >= G11_8PL) || (G11_10PL == 0) -#define MG11_8_110PL ~(1 << 9) -#else -#define MG11_8_110PL 0xFFFF -#endif - -#if (G11_11PL >= G11_8PL) || (G11_11PL == 0) -#define MG11_8_111PL ~(1 << 10) -#else -#define MG11_8_111PL 0xFFFF -#endif - -#if (G11_12PL >= G11_8PL) || (G11_12PL == 0) -#define MG11_8_112PL ~(1 << 11) -#else -#define MG11_8_112PL 0xFFFF -#endif - -#if (G11_13PL >= G11_8PL) || (G11_13PL == 0) -#define MG11_8_113PL ~(1 << 12) -#else -#define MG11_8_113PL 0xFFFF -#endif - -#if (G11_14PL >= G11_8PL) || (G11_14PL == 0) -#define MG11_8_114PL ~(1 << 13) -#else -#define MG11_8_114PL 0xFFFF -#endif - -#if (G11_15PL >= G11_8PL) || (G11_15PL == 0) -#define MG11_8_115PL ~(1 << 14) -#else -#define MG11_8_115PL 0xFFFF -#endif - -#if (G11_16PL >= G11_8PL) || (G11_16PL == 0) -#define MG11_8_116PL ~(1 << 15) -#else -#define MG11_8_116PL 0xFFFF -#endif - -#define MG11_8_18PL 0xFF7F -#define MG11_8 (MG11_8_11PL & MG11_8_12PL & MG11_8_13PL & MG11_8_14PL & \ - MG11_8_15PL & MG11_8_16PL & MG11_8_17PL & MG11_8_18PL & \ - MG11_8_19PL & MG11_8_110PL & MG11_8_111PL & MG11_8_112PL & \ - MG11_8_113PL & MG11_8_114PL & MG11_8_115PL & MG11_8_116PL) -// End of MG11_8: -// Beginning of MG119: -#if (G11_1PL >= G11_9PL) || (G11_1PL == 0) -#define MG11_9_11PL ~(1 << 0) -#else -#define MG11_9_11PL 0xFFFF -#endif - -#if (G11_2PL >= G11_9PL) || (G11_2PL == 0) -#define MG11_9_12PL ~(1 << 1) -#else -#define MG11_9_12PL 0xFFFF -#endif - -#if (G11_3PL >= G11_9PL) || (G11_3PL == 0) -#define MG11_9_13PL ~(1 << 2) -#else -#define MG11_9_13PL 0xFFFF -#endif - -#if (G11_4PL >= G11_9PL) || (G11_4PL == 0) -#define MG11_9_14PL ~(1 << 3) -#else -#define MG11_9_14PL 0xFFFF -#endif - -#if (G11_5PL >= G11_9PL) || (G11_5PL == 0) -#define MG11_9_15PL ~(1 << 4) -#else -#define MG11_9_15PL 0xFFFF -#endif - -#if (G11_6PL >= G11_9PL) || (G11_6PL == 0) -#define MG11_9_16PL ~(1 << 5) -#else -#define MG11_9_16PL 0xFFFF -#endif - -#if (G11_7PL >= G11_9PL) || (G11_7PL == 0) -#define MG11_9_17PL ~(1 << 6) -#else -#define MG11_9_17PL 0xFFFF -#endif - -#if (G11_8PL >= G11_9PL) || (G11_8PL == 0) -#define MG11_9_18PL ~(1 << 7) -#else -#define MG11_9_18PL 0xFFFF -#endif - -#if (G11_10PL >= G11_9PL) || (G11_10PL == 0) -#define MG11_9_110PL ~(1 << 9) -#else -#define MG11_9_110PL 0xFFFF -#endif - -#if (G11_11PL >= G11_9PL) || (G11_11PL == 0) -#define MG11_9_111PL ~(1 << 10) -#else -#define MG11_9_111PL 0xFFFF -#endif - -#if (G11_12PL >= G11_9PL) || (G11_12PL == 0) -#define MG11_9_112PL ~(1 << 11) -#else -#define MG11_9_112PL 0xFFFF -#endif - -#if (G11_13PL >= G11_9PL) || (G11_13PL == 0) -#define MG11_9_113PL ~(1 << 12) -#else -#define MG11_9_113PL 0xFFFF -#endif - -#if (G11_14PL >= G11_9PL) || (G11_14PL == 0) -#define MG11_9_114PL ~(1 << 13) -#else -#define MG11_9_114PL 0xFFFF -#endif - -#if (G11_15PL >= G11_9PL) || (G11_15PL == 0) -#define MG11_9_115PL ~(1 << 14) -#else -#define MG11_9_115PL 0xFFFF -#endif - -#if (G11_16PL >= G11_9PL) || (G11_16PL == 0) -#define MG11_9_116PL ~(1 << 15) -#else -#define MG11_9_116PL 0xFFFF -#endif - -#define MG11_9_19PL 0xFEFF -#define MG11_9 (MG11_9_11PL & MG11_9_12PL & MG11_9_13PL & MG11_9_14PL & \ - MG11_9_15PL & MG11_9_16PL & MG11_9_17PL & MG11_9_18PL & \ - MG11_9_19PL & MG11_9_110PL & MG11_9_111PL & MG11_9_112PL & \ - MG11_9_113PL & MG11_9_114PL & MG11_9_115PL & MG11_9_116PL) -// End of MG11_9: -// Beginning of MG1110: -#if (G11_1PL >= G11_10PL) || (G11_1PL == 0) -#define MG11_10_11PL ~(1 << 0) -#else -#define MG11_10_11PL 0xFFFF -#endif - -#if (G11_2PL >= G11_10PL) || (G11_2PL == 0) -#define MG11_10_12PL ~(1 << 1) -#else -#define MG11_10_12PL 0xFFFF -#endif - -#if (G11_3PL >= G11_10PL) || (G11_3PL == 0) -#define MG11_10_13PL ~(1 << 2) -#else -#define MG11_10_13PL 0xFFFF -#endif - -#if (G11_4PL >= G11_10PL) || (G11_4PL == 0) -#define MG11_10_14PL ~(1 << 3) -#else -#define MG11_10_14PL 0xFFFF -#endif - -#if (G11_5PL >= G11_10PL) || (G11_5PL == 0) -#define MG11_10_15PL ~(1 << 4) -#else -#define MG11_10_15PL 0xFFFF -#endif - -#if (G11_6PL >= G11_10PL) || (G11_6PL == 0) -#define MG11_10_16PL ~(1 << 5) -#else -#define MG11_10_16PL 0xFFFF -#endif - -#if (G11_7PL >= G11_10PL) || (G11_7PL == 0) -#define MG11_10_17PL ~(1 << 6) -#else -#define MG11_10_17PL 0xFFFF -#endif - -#if (G11_8PL >= G11_10PL) || (G11_8PL == 0) -#define MG11_10_18PL ~(1 << 7) -#else -#define MG11_10_18PL 0xFFFF -#endif - -#if (G11_9PL >= G11_10PL) || (G11_9PL == 0) -#define MG11_10_19PL ~(1 << 8) -#else -#define MG11_10_19PL 0xFFFF -#endif - -#if (G11_11PL >= G11_10PL) || (G11_11PL == 0) -#define MG11_10_111PL ~(1 << 10) -#else -#define MG11_10_111PL 0xFFFF -#endif - -#if (G11_12PL >= G11_10PL) || (G11_12PL == 0) -#define MG11_10_112PL ~(1 << 11) -#else -#define MG11_10_112PL 0xFFFF -#endif - -#if (G11_13PL >= G11_10PL) || (G11_13PL == 0) -#define MG11_10_113PL ~(1 << 12) -#else -#define MG11_10_113PL 0xFFFF -#endif - -#if (G11_14PL >= G11_10PL) || (G11_14PL == 0) -#define MG11_10_114PL ~(1 << 13) -#else -#define MG11_10_114PL 0xFFFF -#endif - -#if (G11_15PL >= G11_10PL) || (G11_15PL == 0) -#define MG11_10_115PL ~(1 << 14) -#else -#define MG11_10_115PL 0xFFFF -#endif - -#if (G11_16PL >= G11_10PL) || (G11_16PL == 0) -#define MG11_10_116PL ~(1 << 15) -#else -#define MG11_10_116PL 0xFFFF -#endif - -#define MG11_10_110PL 0xFDFF -#define MG11_10 (MG11_10_11PL & MG11_10_12PL & MG11_10_13PL & MG11_10_14PL & \ - MG11_10_15PL & MG11_10_16PL & MG11_10_17PL & MG11_10_18PL & \ - MG11_10_19PL & MG11_10_110PL & MG11_10_111PL & MG11_10_112PL & \ - MG11_10_113PL & MG11_10_114PL & MG11_10_115PL & MG11_10_116PL) -// End of MG11_10: -// Beginning of MG1111: -#if (G11_1PL >= G11_11PL) || (G11_1PL == 0) -#define MG11_11_11PL ~(1 << 0) -#else -#define MG11_11_11PL 0xFFFF -#endif - -#if (G11_2PL >= G11_11PL) || (G11_2PL == 0) -#define MG11_11_12PL ~(1 << 1) -#else -#define MG11_11_12PL 0xFFFF -#endif - -#if (G11_3PL >= G11_11PL) || (G11_3PL == 0) -#define MG11_11_13PL ~(1 << 2) -#else -#define MG11_11_13PL 0xFFFF -#endif - -#if (G11_4PL >= G11_11PL) || (G11_4PL == 0) -#define MG11_11_14PL ~(1 << 3) -#else -#define MG11_11_14PL 0xFFFF -#endif - -#if (G11_5PL >= G11_11PL) || (G11_5PL == 0) -#define MG11_11_15PL ~(1 << 4) -#else -#define MG11_11_15PL 0xFFFF -#endif - -#if (G11_6PL >= G11_11PL) || (G11_6PL == 0) -#define MG11_11_16PL ~(1 << 5) -#else -#define MG11_11_16PL 0xFFFF -#endif - -#if (G11_7PL >= G11_11PL) || (G11_7PL == 0) -#define MG11_11_17PL ~(1 << 6) -#else -#define MG11_11_17PL 0xFFFF -#endif - -#if (G11_8PL >= G11_11PL) || (G11_8PL == 0) -#define MG11_11_18PL ~(1 << 7) -#else -#define MG11_11_18PL 0xFFFF -#endif - -#if (G11_9PL >= G11_11PL) || (G11_9PL == 0) -#define MG11_11_19PL ~(1 << 8) -#else -#define MG11_11_19PL 0xFFFF -#endif - -#if (G11_10PL >= G11_11PL) || (G11_10PL == 0) -#define MG11_11_110PL ~(1 << 9) -#else -#define MG11_11_110PL 0xFFFF -#endif - -#if (G11_12PL >= G11_11PL) || (G11_12PL == 0) -#define MG11_11_112PL ~(1 << 11) -#else -#define MG11_11_112PL 0xFFFF -#endif - -#if (G11_13PL >= G11_11PL) || (G11_13PL == 0) -#define MG11_11_113PL ~(1 << 12) -#else -#define MG11_11_113PL 0xFFFF -#endif - -#if (G11_14PL >= G11_11PL) || (G11_14PL == 0) -#define MG11_11_114PL ~(1 << 13) -#else -#define MG11_11_114PL 0xFFFF -#endif - -#if (G11_15PL >= G11_11PL) || (G11_15PL == 0) -#define MG11_11_115PL ~(1 << 14) -#else -#define MG11_11_115PL 0xFFFF -#endif - -#if (G11_16PL >= G11_11PL) || (G11_16PL == 0) -#define MG11_11_116PL ~(1 << 15) -#else -#define MG11_11_116PL 0xFFFF -#endif - -#define MG11_11_111PL 0xFBFF -#define MG11_11 (MG11_11_11PL & MG11_11_12PL & MG11_11_13PL & MG11_11_14PL & \ - MG11_11_15PL & MG11_11_16PL & MG11_11_17PL & MG11_11_18PL & \ - MG11_11_19PL & MG11_11_110PL & MG11_11_111PL & MG11_11_112PL & \ - MG11_11_113PL & MG11_11_114PL & MG11_11_115PL & MG11_11_116PL) -// End of MG11_11: -// Beginning of MG1112: -#if (G11_1PL >= G11_12PL) || (G11_1PL == 0) -#define MG11_12_11PL ~(1 << 0) -#else -#define MG11_12_11PL 0xFFFF -#endif - -#if (G11_2PL >= G11_12PL) || (G11_2PL == 0) -#define MG11_12_12PL ~(1 << 1) -#else -#define MG11_12_12PL 0xFFFF -#endif - -#if (G11_3PL >= G11_12PL) || (G11_3PL == 0) -#define MG11_12_13PL ~(1 << 2) -#else -#define MG11_12_13PL 0xFFFF -#endif - -#if (G11_4PL >= G11_12PL) || (G11_4PL == 0) -#define MG11_12_14PL ~(1 << 3) -#else -#define MG11_12_14PL 0xFFFF -#endif - -#if (G11_5PL >= G11_12PL) || (G11_5PL == 0) -#define MG11_12_15PL ~(1 << 4) -#else -#define MG11_12_15PL 0xFFFF -#endif - -#if (G11_6PL >= G11_12PL) || (G11_6PL == 0) -#define MG11_12_16PL ~(1 << 5) -#else -#define MG11_12_16PL 0xFFFF -#endif - -#if (G11_7PL >= G11_12PL) || (G11_7PL == 0) -#define MG11_12_17PL ~(1 << 6) -#else -#define MG11_12_17PL 0xFFFF -#endif - -#if (G11_8PL >= G11_12PL) || (G11_8PL == 0) -#define MG11_12_18PL ~(1 << 7) -#else -#define MG11_12_18PL 0xFFFF -#endif - -#if (G11_9PL >= G11_12PL) || (G11_9PL == 0) -#define MG11_12_19PL ~(1 << 8) -#else -#define MG11_12_19PL 0xFFFF -#endif - -#if (G11_10PL >= G11_12PL) || (G11_10PL == 0) -#define MG11_12_110PL ~(1 << 9) -#else -#define MG11_12_110PL 0xFFFF -#endif - -#if (G11_11PL >= G11_12PL) || (G11_11PL == 0) -#define MG11_12_111PL ~(1 << 10) -#else -#define MG11_12_111PL 0xFFFF -#endif - -#if (G11_13PL >= G11_12PL) || (G11_13PL == 0) -#define MG11_12_113PL ~(1 << 12) -#else -#define MG11_12_113PL 0xFFFF -#endif - -#if (G11_14PL >= G11_12PL) || (G11_14PL == 0) -#define MG11_12_114PL ~(1 << 13) -#else -#define MG11_12_114PL 0xFFFF -#endif - -#if (G11_15PL >= G11_12PL) || (G11_15PL == 0) -#define MG11_12_115PL ~(1 << 14) -#else -#define MG11_12_115PL 0xFFFF -#endif - -#if (G11_16PL >= G11_12PL) || (G11_16PL == 0) -#define MG11_12_116PL ~(1 << 15) -#else -#define MG11_12_116PL 0xFFFF -#endif - -#define MG11_12_112PL 0xF7FF -#define MG11_12 (MG11_12_11PL & MG11_12_12PL & MG11_12_13PL & MG11_12_14PL & \ - MG11_12_15PL & MG11_12_16PL & MG11_12_17PL & MG11_12_18PL & \ - MG11_12_19PL & MG11_12_110PL & MG11_12_111PL & MG11_12_112PL & \ - MG11_12_113PL & MG11_12_114PL & MG11_12_115PL & MG11_12_116PL) -// End of MG11_12: -// Beginning of MG1113: -#if (G11_1PL >= G11_13PL) || (G11_1PL == 0) -#define MG11_13_11PL ~(1 << 0) -#else -#define MG11_13_11PL 0xFFFF -#endif - -#if (G11_2PL >= G11_13PL) || (G11_2PL == 0) -#define MG11_13_12PL ~(1 << 1) -#else -#define MG11_13_12PL 0xFFFF -#endif - -#if (G11_3PL >= G11_13PL) || (G11_3PL == 0) -#define MG11_13_13PL ~(1 << 2) -#else -#define MG11_13_13PL 0xFFFF -#endif - -#if (G11_4PL >= G11_13PL) || (G11_4PL == 0) -#define MG11_13_14PL ~(1 << 3) -#else -#define MG11_13_14PL 0xFFFF -#endif - -#if (G11_5PL >= G11_13PL) || (G11_5PL == 0) -#define MG11_13_15PL ~(1 << 4) -#else -#define MG11_13_15PL 0xFFFF -#endif - -#if (G11_6PL >= G11_13PL) || (G11_6PL == 0) -#define MG11_13_16PL ~(1 << 5) -#else -#define MG11_13_16PL 0xFFFF -#endif - -#if (G11_7PL >= G11_13PL) || (G11_7PL == 0) -#define MG11_13_17PL ~(1 << 6) -#else -#define MG11_13_17PL 0xFFFF -#endif - -#if (G11_8PL >= G11_13PL) || (G11_8PL == 0) -#define MG11_13_18PL ~(1 << 7) -#else -#define MG11_13_18PL 0xFFFF -#endif - -#if (G11_9PL >= G11_13PL) || (G11_9PL == 0) -#define MG11_13_19PL ~(1 << 8) -#else -#define MG11_13_19PL 0xFFFF -#endif - -#if (G11_10PL >= G11_13PL) || (G11_10PL == 0) -#define MG11_13_110PL ~(1 << 9) -#else -#define MG11_13_110PL 0xFFFF -#endif - -#if (G11_11PL >= G11_13PL) || (G11_11PL == 0) -#define MG11_13_111PL ~(1 << 10) -#else -#define MG11_13_111PL 0xFFFF -#endif - -#if (G11_12PL >= G11_13PL) || (G11_12PL == 0) -#define MG11_13_112PL ~(1 << 11) -#else -#define MG11_13_112PL 0xFFFF -#endif - -#if (G11_14PL >= G11_13PL) || (G11_14PL == 0) -#define MG11_13_114PL ~(1 << 13) -#else -#define MG11_13_114PL 0xFFFF -#endif - -#if (G11_15PL >= G11_13PL) || (G11_15PL == 0) -#define MG11_13_115PL ~(1 << 14) -#else -#define MG11_13_115PL 0xFFFF -#endif - -#if (G11_16PL >= G11_13PL) || (G11_16PL == 0) -#define MG11_13_116PL ~(1 << 15) -#else -#define MG11_13_116PL 0xFFFF -#endif - -#define MG11_13_113PL 0xEFFF -#define MG11_13 (MG11_13_11PL & MG11_13_12PL & MG11_13_13PL & MG11_13_14PL & \ - MG11_13_15PL & MG11_13_16PL & MG11_13_17PL & MG11_13_18PL & \ - MG11_13_19PL & MG11_13_110PL & MG11_13_111PL & MG11_13_112PL & \ - MG11_13_113PL & MG11_13_114PL & MG11_13_115PL & MG11_13_116PL) -// End of MG11_13: -// Beginning of MG1114: -#if (G11_1PL >= G11_14PL) || (G11_1PL == 0) -#define MG11_14_11PL ~(1 << 0) -#else -#define MG11_14_11PL 0xFFFF -#endif - -#if (G11_2PL >= G11_14PL) || (G11_2PL == 0) -#define MG11_14_12PL ~(1 << 1) -#else -#define MG11_14_12PL 0xFFFF -#endif - -#if (G11_3PL >= G11_14PL) || (G11_3PL == 0) -#define MG11_14_13PL ~(1 << 2) -#else -#define MG11_14_13PL 0xFFFF -#endif - -#if (G11_4PL >= G11_14PL) || (G11_4PL == 0) -#define MG11_14_14PL ~(1 << 3) -#else -#define MG11_14_14PL 0xFFFF -#endif - -#if (G11_5PL >= G11_14PL) || (G11_5PL == 0) -#define MG11_14_15PL ~(1 << 4) -#else -#define MG11_14_15PL 0xFFFF -#endif - -#if (G11_6PL >= G11_14PL) || (G11_6PL == 0) -#define MG11_14_16PL ~(1 << 5) -#else -#define MG11_14_16PL 0xFFFF -#endif - -#if (G11_7PL >= G11_14PL) || (G11_7PL == 0) -#define MG11_14_17PL ~(1 << 6) -#else -#define MG11_14_17PL 0xFFFF -#endif - -#if (G11_8PL >= G11_14PL) || (G11_8PL == 0) -#define MG11_14_18PL ~(1 << 7) -#else -#define MG11_14_18PL 0xFFFF -#endif - -#if (G11_9PL >= G11_14PL) || (G11_9PL == 0) -#define MG11_14_19PL ~(1 << 8) -#else -#define MG11_14_19PL 0xFFFF -#endif - -#if (G11_10PL >= G11_14PL) || (G11_10PL == 0) -#define MG11_14_110PL ~(1 << 9) -#else -#define MG11_14_110PL 0xFFFF -#endif - -#if (G11_11PL >= G11_14PL) || (G11_11PL == 0) -#define MG11_14_111PL ~(1 << 10) -#else -#define MG11_14_111PL 0xFFFF -#endif - -#if (G11_12PL >= G11_14PL) || (G11_12PL == 0) -#define MG11_14_112PL ~(1 << 11) -#else -#define MG11_14_112PL 0xFFFF -#endif - -#if (G11_13PL >= G11_14PL) || (G11_13PL == 0) -#define MG11_14_113PL ~(1 << 12) -#else -#define MG11_14_113PL 0xFFFF -#endif - -#if (G11_15PL >= G11_14PL) || (G11_15PL == 0) -#define MG11_14_115PL ~(1 << 14) -#else -#define MG11_14_115PL 0xFFFF -#endif - -#if (G11_16PL >= G11_14PL) || (G11_16PL == 0) -#define MG11_14_116PL ~(1 << 15) -#else -#define MG11_14_116PL 0xFFFF -#endif - -#define MG11_14_114PL 0xDFFF -#define MG11_14 (MG11_14_11PL & MG11_14_12PL & MG11_14_13PL & MG11_14_14PL & \ - MG11_14_15PL & MG11_14_16PL & MG11_14_17PL & MG11_14_18PL & \ - MG11_14_19PL & MG11_14_110PL & MG11_14_111PL & MG11_14_112PL & \ - MG11_14_113PL & MG11_14_114PL & MG11_14_115PL & MG11_14_116PL) -// End of MG11_14: -// Beginning of MG1115: -#if (G11_1PL >= G11_15PL) || (G11_1PL == 0) -#define MG11_15_11PL ~(1 << 0) -#else -#define MG11_15_11PL 0xFFFF -#endif - -#if (G11_2PL >= G11_15PL) || (G11_2PL == 0) -#define MG11_15_12PL ~(1 << 1) -#else -#define MG11_15_12PL 0xFFFF -#endif - -#if (G11_3PL >= G11_15PL) || (G11_3PL == 0) -#define MG11_15_13PL ~(1 << 2) -#else -#define MG11_15_13PL 0xFFFF -#endif - -#if (G11_4PL >= G11_15PL) || (G11_4PL == 0) -#define MG11_15_14PL ~(1 << 3) -#else -#define MG11_15_14PL 0xFFFF -#endif - -#if (G11_5PL >= G11_15PL) || (G11_5PL == 0) -#define MG11_15_15PL ~(1 << 4) -#else -#define MG11_15_15PL 0xFFFF -#endif - -#if (G11_6PL >= G11_15PL) || (G11_6PL == 0) -#define MG11_15_16PL ~(1 << 5) -#else -#define MG11_15_16PL 0xFFFF -#endif - -#if (G11_7PL >= G11_15PL) || (G11_7PL == 0) -#define MG11_15_17PL ~(1 << 6) -#else -#define MG11_15_17PL 0xFFFF -#endif - -#if (G11_8PL >= G11_15PL) || (G11_8PL == 0) -#define MG11_15_18PL ~(1 << 7) -#else -#define MG11_15_18PL 0xFFFF -#endif - -#if (G11_9PL >= G11_15PL) || (G11_9PL == 0) -#define MG11_15_19PL ~(1 << 8) -#else -#define MG11_15_19PL 0xFFFF -#endif - -#if (G11_10PL >= G11_15PL) || (G11_10PL == 0) -#define MG11_15_110PL ~(1 << 9) -#else -#define MG11_15_110PL 0xFFFF -#endif - -#if (G11_11PL >= G11_15PL) || (G11_11PL == 0) -#define MG11_15_111PL ~(1 << 10) -#else -#define MG11_15_111PL 0xFFFF -#endif - -#if (G11_12PL >= G11_15PL) || (G11_12PL == 0) -#define MG11_15_112PL ~(1 << 11) -#else -#define MG11_15_112PL 0xFFFF -#endif - -#if (G11_13PL >= G11_15PL) || (G11_13PL == 0) -#define MG11_15_113PL ~(1 << 12) -#else -#define MG11_15_113PL 0xFFFF -#endif - -#if (G11_14PL >= G11_15PL) || (G11_14PL == 0) -#define MG11_15_114PL ~(1 << 13) -#else -#define MG11_15_114PL 0xFFFF -#endif - -#if (G11_16PL >= G11_15PL) || (G11_16PL == 0) -#define MG11_15_116PL ~(1 << 15) -#else -#define MG11_15_116PL 0xFFFF -#endif - -#define MG11_15_115PL 0xBFFF -#define MG11_15 (MG11_15_11PL & MG11_15_12PL & MG11_15_13PL & MG11_15_14PL & \ - MG11_15_15PL & MG11_15_16PL & MG11_15_17PL & MG11_15_18PL & \ - MG11_15_19PL & MG11_15_110PL & MG11_15_111PL & MG11_15_112PL & \ - MG11_15_113PL & MG11_15_114PL & MG11_15_115PL & MG11_15_116PL) -// End of MG11_15: -// Beginning of MG1116: -#if (G11_1PL >= G11_16PL) || (G11_1PL == 0) -#define MG11_16_11PL ~(1 << 0) -#else -#define MG11_16_11PL 0xFFFF -#endif - -#if (G11_2PL >= G11_16PL) || (G11_2PL == 0) -#define MG11_16_12PL ~(1 << 1) -#else -#define MG11_16_12PL 0xFFFF -#endif - -#if (G11_3PL >= G11_16PL) || (G11_3PL == 0) -#define MG11_16_13PL ~(1 << 2) -#else -#define MG11_16_13PL 0xFFFF -#endif - -#if (G11_4PL >= G11_16PL) || (G11_4PL == 0) -#define MG11_16_14PL ~(1 << 3) -#else -#define MG11_16_14PL 0xFFFF -#endif - -#if (G11_5PL >= G11_16PL) || (G11_5PL == 0) -#define MG11_16_15PL ~(1 << 4) -#else -#define MG11_16_15PL 0xFFFF -#endif - -#if (G11_6PL >= G11_16PL) || (G11_6PL == 0) -#define MG11_16_16PL ~(1 << 5) -#else -#define MG11_16_16PL 0xFFFF -#endif - -#if (G11_7PL >= G11_16PL) || (G11_7PL == 0) -#define MG11_16_17PL ~(1 << 6) -#else -#define MG11_16_17PL 0xFFFF -#endif - -#if (G11_8PL >= G11_16PL) || (G11_8PL == 0) -#define MG11_16_18PL ~(1 << 7) -#else -#define MG11_16_18PL 0xFFFF -#endif - -#if (G11_9PL >= G11_16PL) || (G11_9PL == 0) -#define MG11_16_19PL ~(1 << 8) -#else -#define MG11_16_19PL 0xFFFF -#endif - -#if (G11_10PL >= G11_16PL) || (G11_10PL == 0) -#define MG11_16_110PL ~(1 << 9) -#else -#define MG11_16_110PL 0xFFFF -#endif - -#if (G11_11PL >= G11_16PL) || (G11_11PL == 0) -#define MG11_16_111PL ~(1 << 10) -#else -#define MG11_16_111PL 0xFFFF -#endif - -#if (G11_12PL >= G11_16PL) || (G11_12PL == 0) -#define MG11_16_112PL ~(1 << 11) -#else -#define MG11_16_112PL 0xFFFF -#endif - -#if (G11_13PL >= G11_16PL) || (G11_13PL == 0) -#define MG11_16_113PL ~(1 << 12) -#else -#define MG11_16_113PL 0xFFFF -#endif - -#if (G11_14PL >= G11_16PL) || (G11_14PL == 0) -#define MG11_16_114PL ~(1 << 13) -#else -#define MG11_16_114PL 0xFFFF -#endif - -#if (G11_15PL >= G11_16PL) || (G11_15PL == 0) -#define MG11_16_115PL ~(1 << 14) -#else -#define MG11_16_115PL 0xFFFF -#endif - -#define MG11_16_116PL 0x7FFF -#define MG11_16 (MG11_16_11PL & MG11_16_12PL & MG11_16_13PL & MG11_16_14PL & \ - MG11_16_15PL & MG11_16_16PL & MG11_16_17PL & MG11_16_18PL & \ - MG11_16_19PL & MG11_16_110PL & MG11_16_111PL & MG11_16_112PL & \ - MG11_16_113PL & MG11_16_114PL & MG11_16_115PL & MG11_16_116PL) -// End of MG11_16: - - -// -// Automatically generate PIEIER12 interrupt masks MG121 to MG1216: -// - -// Beginning of MG121: -#if (G12_2PL >= G12_1PL) || (G12_2PL == 0) -#define MG12_1_12PL ~(1 << 1) -#else -#define MG12_1_12PL 0xFFFF -#endif - -#if (G12_3PL >= G12_1PL) || (G12_3PL == 0) -#define MG12_1_13PL ~(1 << 2) -#else -#define MG12_1_13PL 0xFFFF -#endif - -#if (G12_4PL >= G12_1PL) || (G12_4PL == 0) -#define MG12_1_14PL ~(1 << 3) -#else -#define MG12_1_14PL 0xFFFF -#endif - -#if (G12_5PL >= G12_1PL) || (G12_5PL == 0) -#define MG12_1_15PL ~(1 << 4) -#else -#define MG12_1_15PL 0xFFFF -#endif - -#if (G12_6PL >= G12_1PL) || (G12_6PL == 0) -#define MG12_1_16PL ~(1 << 5) -#else -#define MG12_1_16PL 0xFFFF -#endif - -#if (G12_7PL >= G12_1PL) || (G12_7PL == 0) -#define MG12_1_17PL ~(1 << 6) -#else -#define MG12_1_17PL 0xFFFF -#endif - -#if (G12_8PL >= G12_1PL) || (G12_8PL == 0) -#define MG12_1_18PL ~(1 << 7) -#else -#define MG12_1_18PL 0xFFFF -#endif - -#if (G12_9PL >= G12_1PL) || (G12_9PL == 0) -#define MG12_1_19PL ~(1 << 8) -#else -#define MG12_1_19PL 0xFFFF -#endif - -#if (G12_10PL >= G12_1PL) || (G12_10PL == 0) -#define MG12_1_110PL ~(1 << 9) -#else -#define MG12_1_110PL 0xFFFF -#endif - -#if (G12_11PL >= G12_1PL) || (G12_11PL == 0) -#define MG12_1_111PL ~(1 << 10) -#else -#define MG12_1_111PL 0xFFFF -#endif - -#if (G12_12PL >= G12_1PL) || (G12_12PL == 0) -#define MG12_1_112PL ~(1 << 11) -#else -#define MG12_1_112PL 0xFFFF -#endif - -#if (G12_13PL >= G12_1PL) || (G12_13PL == 0) -#define MG12_1_113PL ~(1 << 12) -#else -#define MG12_1_113PL 0xFFFF -#endif - -#if (G12_14PL >= G12_1PL) || (G12_14PL == 0) -#define MG12_1_114PL ~(1 << 13) -#else -#define MG12_1_114PL 0xFFFF -#endif - -#if (G12_15PL >= G12_1PL) || (G12_15PL == 0) -#define MG12_1_115PL ~(1 << 14) -#else -#define MG12_1_115PL 0xFFFF -#endif - -#if (G12_16PL >= G12_1PL) || (G12_16PL == 0) -#define MG12_1_116PL ~(1 << 15) -#else -#define MG12_1_116PL 0xFFFF -#endif - -#define MG12_1_11PL 0xFFFE -#define MG12_1 (MG12_1_11PL & MG12_1_12PL & MG12_1_13PL & MG12_1_14PL & \ - MG12_1_15PL & MG12_1_16PL & MG12_1_17PL & MG12_1_18PL & \ - MG12_1_19PL & MG12_1_110PL & MG12_1_111PL & MG12_1_112PL & \ - MG12_1_113PL & MG12_1_114PL & MG12_1_115PL & MG12_1_116PL) -// End of MG12_1: -// Beginning of MG122: -#if (G12_1PL >= G12_2PL) || (G12_1PL == 0) -#define MG12_2_11PL ~(1 << 0) -#else -#define MG12_2_11PL 0xFFFF -#endif - -#if (G12_3PL >= G12_2PL) || (G12_3PL == 0) -#define MG12_2_13PL ~(1 << 2) -#else -#define MG12_2_13PL 0xFFFF -#endif - -#if (G12_4PL >= G12_2PL) || (G12_4PL == 0) -#define MG12_2_14PL ~(1 << 3) -#else -#define MG12_2_14PL 0xFFFF -#endif - -#if (G12_5PL >= G12_2PL) || (G12_5PL == 0) -#define MG12_2_15PL ~(1 << 4) -#else -#define MG12_2_15PL 0xFFFF -#endif - -#if (G12_6PL >= G12_2PL) || (G12_6PL == 0) -#define MG12_2_16PL ~(1 << 5) -#else -#define MG12_2_16PL 0xFFFF -#endif - -#if (G12_7PL >= G12_2PL) || (G12_7PL == 0) -#define MG12_2_17PL ~(1 << 6) -#else -#define MG12_2_17PL 0xFFFF -#endif - -#if (G12_8PL >= G12_2PL) || (G12_8PL == 0) -#define MG12_2_18PL ~(1 << 7) -#else -#define MG12_2_18PL 0xFFFF -#endif - -#if (G12_9PL >= G12_2PL) || (G12_9PL == 0) -#define MG12_2_19PL ~(1 << 8) -#else -#define MG12_2_19PL 0xFFFF -#endif - -#if (G12_10PL >= G12_2PL) || (G12_10PL == 0) -#define MG12_2_110PL ~(1 << 9) -#else -#define MG12_2_110PL 0xFFFF -#endif - -#if (G12_11PL >= G12_2PL) || (G12_11PL == 0) -#define MG12_2_111PL ~(1 << 10) -#else -#define MG12_2_111PL 0xFFFF -#endif - -#if (G12_12PL >= G12_2PL) || (G12_12PL == 0) -#define MG12_2_112PL ~(1 << 11) -#else -#define MG12_2_112PL 0xFFFF -#endif - -#if (G12_13PL >= G12_2PL) || (G12_13PL == 0) -#define MG12_2_113PL ~(1 << 12) -#else -#define MG12_2_113PL 0xFFFF -#endif - -#if (G12_14PL >= G12_2PL) || (G12_14PL == 0) -#define MG12_2_114PL ~(1 << 13) -#else -#define MG12_2_114PL 0xFFFF -#endif - -#if (G12_15PL >= G12_2PL) || (G12_15PL == 0) -#define MG12_2_115PL ~(1 << 14) -#else -#define MG12_2_115PL 0xFFFF -#endif - -#if (G12_16PL >= G12_2PL) || (G12_16PL == 0) -#define MG12_2_116PL ~(1 << 15) -#else -#define MG12_2_116PL 0xFFFF -#endif - -#define MG12_2_12PL 0xFFFD -#define MG12_2 (MG12_2_11PL & MG12_2_12PL & MG12_2_13PL & MG12_2_14PL & \ - MG12_2_15PL & MG12_2_16PL & MG12_2_17PL & MG12_2_18PL & \ - MG12_2_19PL & MG12_2_110PL & MG12_2_111PL & MG12_2_112PL & \ - MG12_2_113PL & MG12_2_114PL & MG12_2_115PL & MG12_2_116PL) -// End of MG12_2: -// Beginning of MG123: -#if (G12_1PL >= G12_3PL) || (G12_1PL == 0) -#define MG12_3_11PL ~(1 << 0) -#else -#define MG12_3_11PL 0xFFFF -#endif - -#if (G12_2PL >= G12_3PL) || (G12_2PL == 0) -#define MG12_3_12PL ~(1 << 1) -#else -#define MG12_3_12PL 0xFFFF -#endif - -#if (G12_4PL >= G12_3PL) || (G12_4PL == 0) -#define MG12_3_14PL ~(1 << 3) -#else -#define MG12_3_14PL 0xFFFF -#endif - -#if (G12_5PL >= G12_3PL) || (G12_5PL == 0) -#define MG12_3_15PL ~(1 << 4) -#else -#define MG12_3_15PL 0xFFFF -#endif - -#if (G12_6PL >= G12_3PL) || (G12_6PL == 0) -#define MG12_3_16PL ~(1 << 5) -#else -#define MG12_3_16PL 0xFFFF -#endif - -#if (G12_7PL >= G12_3PL) || (G12_7PL == 0) -#define MG12_3_17PL ~(1 << 6) -#else -#define MG12_3_17PL 0xFFFF -#endif - -#if (G12_8PL >= G12_3PL) || (G12_8PL == 0) -#define MG12_3_18PL ~(1 << 7) -#else -#define MG12_3_18PL 0xFFFF -#endif - -#if (G12_9PL >= G12_3PL) || (G12_9PL == 0) -#define MG12_3_19PL ~(1 << 8) -#else -#define MG12_3_19PL 0xFFFF -#endif - -#if (G12_10PL >= G12_3PL) || (G12_10PL == 0) -#define MG12_3_110PL ~(1 << 9) -#else -#define MG12_3_110PL 0xFFFF -#endif - -#if (G12_11PL >= G12_3PL) || (G12_11PL == 0) -#define MG12_3_111PL ~(1 << 10) -#else -#define MG12_3_111PL 0xFFFF -#endif - -#if (G12_12PL >= G12_3PL) || (G12_12PL == 0) -#define MG12_3_112PL ~(1 << 11) -#else -#define MG12_3_112PL 0xFFFF -#endif - -#if (G12_13PL >= G12_3PL) || (G12_13PL == 0) -#define MG12_3_113PL ~(1 << 12) -#else -#define MG12_3_113PL 0xFFFF -#endif - -#if (G12_14PL >= G12_3PL) || (G12_14PL == 0) -#define MG12_3_114PL ~(1 << 13) -#else -#define MG12_3_114PL 0xFFFF -#endif - -#if (G12_15PL >= G12_3PL) || (G12_15PL == 0) -#define MG12_3_115PL ~(1 << 14) -#else -#define MG12_3_115PL 0xFFFF -#endif - -#if (G12_16PL >= G12_3PL) || (G12_16PL == 0) -#define MG12_3_116PL ~(1 << 15) -#else -#define MG12_3_116PL 0xFFFF -#endif - -#define MG12_3_13PL 0xFFFB -#define MG12_3 (MG12_3_11PL & MG12_3_12PL & MG12_3_13PL & MG12_3_14PL & \ - MG12_3_15PL & MG12_3_16PL & MG12_3_17PL & MG12_3_18PL & \ - MG12_3_19PL & MG12_3_110PL & MG12_3_111PL & MG12_3_112PL & \ - MG12_3_113PL & MG12_3_114PL & MG12_3_115PL & MG12_3_116PL) -// End of MG12_3: -// Beginning of MG124: -#if (G12_1PL >= G12_4PL) || (G12_1PL == 0) -#define MG12_4_11PL ~(1 << 0) -#else -#define MG12_4_11PL 0xFFFF -#endif - -#if (G12_2PL >= G12_4PL) || (G12_2PL == 0) -#define MG12_4_12PL ~(1 << 1) -#else -#define MG12_4_12PL 0xFFFF -#endif - -#if (G12_3PL >= G12_4PL) || (G12_3PL == 0) -#define MG12_4_13PL ~(1 << 2) -#else -#define MG12_4_13PL 0xFFFF -#endif - -#if (G12_5PL >= G12_4PL) || (G12_5PL == 0) -#define MG12_4_15PL ~(1 << 4) -#else -#define MG12_4_15PL 0xFFFF -#endif - -#if (G12_6PL >= G12_4PL) || (G12_6PL == 0) -#define MG12_4_16PL ~(1 << 5) -#else -#define MG12_4_16PL 0xFFFF -#endif - -#if (G12_7PL >= G12_4PL) || (G12_7PL == 0) -#define MG12_4_17PL ~(1 << 6) -#else -#define MG12_4_17PL 0xFFFF -#endif - -#if (G12_8PL >= G12_4PL) || (G12_8PL == 0) -#define MG12_4_18PL ~(1 << 7) -#else -#define MG12_4_18PL 0xFFFF -#endif - -#if (G12_9PL >= G12_4PL) || (G12_9PL == 0) -#define MG12_4_19PL ~(1 << 8) -#else -#define MG12_4_19PL 0xFFFF -#endif - -#if (G12_10PL >= G12_4PL) || (G12_10PL == 0) -#define MG12_4_110PL ~(1 << 9) -#else -#define MG12_4_110PL 0xFFFF -#endif - -#if (G12_11PL >= G12_4PL) || (G12_11PL == 0) -#define MG12_4_111PL ~(1 << 10) -#else -#define MG12_4_111PL 0xFFFF -#endif - -#if (G12_12PL >= G12_4PL) || (G12_12PL == 0) -#define MG12_4_112PL ~(1 << 11) -#else -#define MG12_4_112PL 0xFFFF -#endif - -#if (G12_13PL >= G12_4PL) || (G12_13PL == 0) -#define MG12_4_113PL ~(1 << 12) -#else -#define MG12_4_113PL 0xFFFF -#endif - -#if (G12_14PL >= G12_4PL) || (G12_14PL == 0) -#define MG12_4_114PL ~(1 << 13) -#else -#define MG12_4_114PL 0xFFFF -#endif - -#if (G12_15PL >= G12_4PL) || (G12_15PL == 0) -#define MG12_4_115PL ~(1 << 14) -#else -#define MG12_4_115PL 0xFFFF -#endif - -#if (G12_16PL >= G12_4PL) || (G12_16PL == 0) -#define MG12_4_116PL ~(1 << 15) -#else -#define MG12_4_116PL 0xFFFF -#endif - -#define MG12_4_14PL 0xFFF7 -#define MG12_4 (MG12_4_11PL & MG12_4_12PL & MG12_4_13PL & MG12_4_14PL & \ - MG12_4_15PL & MG12_4_16PL & MG12_4_17PL & MG12_4_18PL & \ - MG12_4_19PL & MG12_4_110PL & MG12_4_111PL & MG12_4_112PL & \ - MG12_4_113PL & MG12_4_114PL & MG12_4_115PL & MG12_4_116PL) -// End of MG12_4: -// Beginning of MG125: -#if (G12_1PL >= G12_5PL) || (G12_1PL == 0) -#define MG12_5_11PL ~(1 << 0) -#else -#define MG12_5_11PL 0xFFFF -#endif - -#if (G12_2PL >= G12_5PL) || (G12_2PL == 0) -#define MG12_5_12PL ~(1 << 1) -#else -#define MG12_5_12PL 0xFFFF -#endif - -#if (G12_3PL >= G12_5PL) || (G12_3PL == 0) -#define MG12_5_13PL ~(1 << 2) -#else -#define MG12_5_13PL 0xFFFF -#endif - -#if (G12_4PL >= G12_5PL) || (G12_4PL == 0) -#define MG12_5_14PL ~(1 << 3) -#else -#define MG12_5_14PL 0xFFFF -#endif - -#if (G12_6PL >= G12_5PL) || (G12_6PL == 0) -#define MG12_5_16PL ~(1 << 5) -#else -#define MG12_5_16PL 0xFFFF -#endif - -#if (G12_7PL >= G12_5PL) || (G12_7PL == 0) -#define MG12_5_17PL ~(1 << 6) -#else -#define MG12_5_17PL 0xFFFF -#endif - -#if (G12_8PL >= G12_5PL) || (G12_8PL == 0) -#define MG12_5_18PL ~(1 << 7) -#else -#define MG12_5_18PL 0xFFFF -#endif - -#if (G12_9PL >= G12_5PL) || (G12_9PL == 0) -#define MG12_5_19PL ~(1 << 8) -#else -#define MG12_5_19PL 0xFFFF -#endif - -#if (G12_10PL >= G12_5PL) || (G12_10PL == 0) -#define MG12_5_110PL ~(1 << 9) -#else -#define MG12_5_110PL 0xFFFF -#endif - -#if (G12_11PL >= G12_5PL) || (G12_11PL == 0) -#define MG12_5_111PL ~(1 << 10) -#else -#define MG12_5_111PL 0xFFFF -#endif - -#if (G12_12PL >= G12_5PL) || (G12_12PL == 0) -#define MG12_5_112PL ~(1 << 11) -#else -#define MG12_5_112PL 0xFFFF -#endif - -#if (G12_13PL >= G12_5PL) || (G12_13PL == 0) -#define MG12_5_113PL ~(1 << 12) -#else -#define MG12_5_113PL 0xFFFF -#endif - -#if (G12_14PL >= G12_5PL) || (G12_14PL == 0) -#define MG12_5_114PL ~(1 << 13) -#else -#define MG12_5_114PL 0xFFFF -#endif - -#if (G12_15PL >= G12_5PL) || (G12_15PL == 0) -#define MG12_5_115PL ~(1 << 14) -#else -#define MG12_5_115PL 0xFFFF -#endif - -#if (G12_16PL >= G12_5PL) || (G12_16PL == 0) -#define MG12_5_116PL ~(1 << 15) -#else -#define MG12_5_116PL 0xFFFF -#endif - -#define MG12_5_15PL 0xFFEF -#define MG12_5 (MG12_5_11PL & MG12_5_12PL & MG12_5_13PL & MG12_5_14PL & \ - MG12_5_15PL & MG12_5_16PL & MG12_5_17PL & MG12_5_18PL & \ - MG12_5_19PL & MG12_5_110PL & MG12_5_111PL & MG12_5_112PL & \ - MG12_5_113PL & MG12_5_114PL & MG12_5_115PL & MG12_5_116PL) -// End of MG12_5: -// Beginning of MG126: -#if (G12_1PL >= G12_6PL) || (G12_1PL == 0) -#define MG12_6_11PL ~(1 << 0) -#else -#define MG12_6_11PL 0xFFFF -#endif - -#if (G12_2PL >= G12_6PL) || (G12_2PL == 0) -#define MG12_6_12PL ~(1 << 1) -#else -#define MG12_6_12PL 0xFFFF -#endif - -#if (G12_3PL >= G12_6PL) || (G12_3PL == 0) -#define MG12_6_13PL ~(1 << 2) -#else -#define MG12_6_13PL 0xFFFF -#endif - -#if (G12_4PL >= G12_6PL) || (G12_4PL == 0) -#define MG12_6_14PL ~(1 << 3) -#else -#define MG12_6_14PL 0xFFFF -#endif - -#if (G12_5PL >= G12_6PL) || (G12_5PL == 0) -#define MG12_6_15PL ~(1 << 4) -#else -#define MG12_6_15PL 0xFFFF -#endif - -#if (G12_7PL >= G12_6PL) || (G12_7PL == 0) -#define MG12_6_17PL ~(1 << 6) -#else -#define MG12_6_17PL 0xFFFF -#endif - -#if (G12_8PL >= G12_6PL) || (G12_8PL == 0) -#define MG12_6_18PL ~(1 << 7) -#else -#define MG12_6_18PL 0xFFFF -#endif - -#if (G12_9PL >= G12_6PL) || (G12_9PL == 0) -#define MG12_6_19PL ~(1 << 8) -#else -#define MG12_6_19PL 0xFFFF -#endif - -#if (G12_10PL >= G12_6PL) || (G12_10PL == 0) -#define MG12_6_110PL ~(1 << 9) -#else -#define MG12_6_110PL 0xFFFF -#endif - -#if (G12_11PL >= G12_6PL) || (G12_11PL == 0) -#define MG12_6_111PL ~(1 << 10) -#else -#define MG12_6_111PL 0xFFFF -#endif - -#if (G12_12PL >= G12_6PL) || (G12_12PL == 0) -#define MG12_6_112PL ~(1 << 11) -#else -#define MG12_6_112PL 0xFFFF -#endif - -#if (G12_13PL >= G12_6PL) || (G12_13PL == 0) -#define MG12_6_113PL ~(1 << 12) -#else -#define MG12_6_113PL 0xFFFF -#endif - -#if (G12_14PL >= G12_6PL) || (G12_14PL == 0) -#define MG12_6_114PL ~(1 << 13) -#else -#define MG12_6_114PL 0xFFFF -#endif - -#if (G12_15PL >= G12_6PL) || (G12_15PL == 0) -#define MG12_6_115PL ~(1 << 14) -#else -#define MG12_6_115PL 0xFFFF -#endif - -#if (G12_16PL >= G12_6PL) || (G12_16PL == 0) -#define MG12_6_116PL ~(1 << 15) -#else -#define MG12_6_116PL 0xFFFF -#endif - -#define MG12_6_16PL 0xFFDF -#define MG12_6 (MG12_6_11PL & MG12_6_12PL & MG12_6_13PL & MG12_6_14PL & \ - MG12_6_15PL & MG12_6_16PL & MG12_6_17PL & MG12_6_18PL & \ - MG12_6_19PL & MG12_6_110PL & MG12_6_111PL & MG12_6_112PL & \ - MG12_6_113PL & MG12_6_114PL & MG12_6_115PL & MG12_6_116PL) -// End of MG12_6: -// Beginning of MG127: -#if (G12_1PL >= G12_7PL) || (G12_1PL == 0) -#define MG12_7_11PL ~(1 << 0) -#else -#define MG12_7_11PL 0xFFFF -#endif - -#if (G12_2PL >= G12_7PL) || (G12_2PL == 0) -#define MG12_7_12PL ~(1 << 1) -#else -#define MG12_7_12PL 0xFFFF -#endif - -#if (G12_3PL >= G12_7PL) || (G12_3PL == 0) -#define MG12_7_13PL ~(1 << 2) -#else -#define MG12_7_13PL 0xFFFF -#endif - -#if (G12_4PL >= G12_7PL) || (G12_4PL == 0) -#define MG12_7_14PL ~(1 << 3) -#else -#define MG12_7_14PL 0xFFFF -#endif - -#if (G12_5PL >= G12_7PL) || (G12_5PL == 0) -#define MG12_7_15PL ~(1 << 4) -#else -#define MG12_7_15PL 0xFFFF -#endif - -#if (G12_6PL >= G12_7PL) || (G12_6PL == 0) -#define MG12_7_16PL ~(1 << 5) -#else -#define MG12_7_16PL 0xFFFF -#endif - -#if (G12_8PL >= G12_7PL) || (G12_8PL == 0) -#define MG12_7_18PL ~(1 << 7) -#else -#define MG12_7_18PL 0xFFFF -#endif - -#if (G12_9PL >= G12_7PL) || (G12_9PL == 0) -#define MG12_7_19PL ~(1 << 8) -#else -#define MG12_7_19PL 0xFFFF -#endif - -#if (G12_10PL >= G12_7PL) || (G12_10PL == 0) -#define MG12_7_110PL ~(1 << 9) -#else -#define MG12_7_110PL 0xFFFF -#endif - -#if (G12_11PL >= G12_7PL) || (G12_11PL == 0) -#define MG12_7_111PL ~(1 << 10) -#else -#define MG12_7_111PL 0xFFFF -#endif - -#if (G12_12PL >= G12_7PL) || (G12_12PL == 0) -#define MG12_7_112PL ~(1 << 11) -#else -#define MG12_7_112PL 0xFFFF -#endif - -#if (G12_13PL >= G12_7PL) || (G12_13PL == 0) -#define MG12_7_113PL ~(1 << 12) -#else -#define MG12_7_113PL 0xFFFF -#endif - -#if (G12_14PL >= G12_7PL) || (G12_14PL == 0) -#define MG12_7_114PL ~(1 << 13) -#else -#define MG12_7_114PL 0xFFFF -#endif - -#if (G12_15PL >= G12_7PL) || (G12_15PL == 0) -#define MG12_7_115PL ~(1 << 14) -#else -#define MG12_7_115PL 0xFFFF -#endif - -#if (G12_16PL >= G12_7PL) || (G12_16PL == 0) -#define MG12_7_116PL ~(1 << 15) -#else -#define MG12_7_116PL 0xFFFF -#endif - -#define MG12_7_17PL 0xFFBF -#define MG12_7 (MG12_7_11PL & MG12_7_12PL & MG12_7_13PL & MG12_7_14PL & \ - MG12_7_15PL & MG12_7_16PL & MG12_7_17PL & MG12_7_18PL & \ - MG12_7_19PL & MG12_7_110PL & MG12_7_111PL & MG12_7_112PL & \ - MG12_7_113PL & MG12_7_114PL & MG12_7_115PL & MG12_7_116PL) -// End of MG12_7: -// Beginning of MG128: -#if (G12_1PL >= G12_8PL) || (G12_1PL == 0) -#define MG12_8_11PL ~(1 << 0) -#else -#define MG12_8_11PL 0xFFFF -#endif - -#if (G12_2PL >= G12_8PL) || (G12_2PL == 0) -#define MG12_8_12PL ~(1 << 1) -#else -#define MG12_8_12PL 0xFFFF -#endif - -#if (G12_3PL >= G12_8PL) || (G12_3PL == 0) -#define MG12_8_13PL ~(1 << 2) -#else -#define MG12_8_13PL 0xFFFF -#endif - -#if (G12_4PL >= G12_8PL) || (G12_4PL == 0) -#define MG12_8_14PL ~(1 << 3) -#else -#define MG12_8_14PL 0xFFFF -#endif - -#if (G12_5PL >= G12_8PL) || (G12_5PL == 0) -#define MG12_8_15PL ~(1 << 4) -#else -#define MG12_8_15PL 0xFFFF -#endif - -#if (G12_6PL >= G12_8PL) || (G12_6PL == 0) -#define MG12_8_16PL ~(1 << 5) -#else -#define MG12_8_16PL 0xFFFF -#endif - -#if (G12_7PL >= G12_8PL) || (G12_7PL == 0) -#define MG12_8_17PL ~(1 << 6) -#else -#define MG12_8_17PL 0xFFFF -#endif - -#if (G12_9PL >= G12_8PL) || (G12_9PL == 0) -#define MG12_8_19PL ~(1 << 8) -#else -#define MG12_8_19PL 0xFFFF -#endif - -#if (G12_10PL >= G12_8PL) || (G12_10PL == 0) -#define MG12_8_110PL ~(1 << 9) -#else -#define MG12_8_110PL 0xFFFF -#endif - -#if (G12_11PL >= G12_8PL) || (G12_11PL == 0) -#define MG12_8_111PL ~(1 << 10) -#else -#define MG12_8_111PL 0xFFFF -#endif - -#if (G12_12PL >= G12_8PL) || (G12_12PL == 0) -#define MG12_8_112PL ~(1 << 11) -#else -#define MG12_8_112PL 0xFFFF -#endif - -#if (G12_13PL >= G12_8PL) || (G12_13PL == 0) -#define MG12_8_113PL ~(1 << 12) -#else -#define MG12_8_113PL 0xFFFF -#endif - -#if (G12_14PL >= G12_8PL) || (G12_14PL == 0) -#define MG12_8_114PL ~(1 << 13) -#else -#define MG12_8_114PL 0xFFFF -#endif - -#if (G12_15PL >= G12_8PL) || (G12_15PL == 0) -#define MG12_8_115PL ~(1 << 14) -#else -#define MG12_8_115PL 0xFFFF -#endif - -#if (G12_16PL >= G12_8PL) || (G12_16PL == 0) -#define MG12_8_116PL ~(1 << 15) -#else -#define MG12_8_116PL 0xFFFF -#endif - -#define MG12_8_18PL 0xFF7F -#define MG12_8 (MG12_8_11PL & MG12_8_12PL & MG12_8_13PL & MG12_8_14PL & \ - MG12_8_15PL & MG12_8_16PL & MG12_8_17PL & MG12_8_18PL & \ - MG12_8_19PL & MG12_8_110PL & MG12_8_111PL & MG12_8_112PL & \ - MG12_8_113PL & MG12_8_114PL & MG12_8_115PL & MG12_8_116PL) -// End of MG12_8: -// Beginning of MG129: -#if (G12_1PL >= G12_9PL) || (G12_1PL == 0) -#define MG12_9_11PL ~(1 << 0) -#else -#define MG12_9_11PL 0xFFFF -#endif - -#if (G12_2PL >= G12_9PL) || (G12_2PL == 0) -#define MG12_9_12PL ~(1 << 1) -#else -#define MG12_9_12PL 0xFFFF -#endif - -#if (G12_3PL >= G12_9PL) || (G12_3PL == 0) -#define MG12_9_13PL ~(1 << 2) -#else -#define MG12_9_13PL 0xFFFF -#endif - -#if (G12_4PL >= G12_9PL) || (G12_4PL == 0) -#define MG12_9_14PL ~(1 << 3) -#else -#define MG12_9_14PL 0xFFFF -#endif - -#if (G12_5PL >= G12_9PL) || (G12_5PL == 0) -#define MG12_9_15PL ~(1 << 4) -#else -#define MG12_9_15PL 0xFFFF -#endif - -#if (G12_6PL >= G12_9PL) || (G12_6PL == 0) -#define MG12_9_16PL ~(1 << 5) -#else -#define MG12_9_16PL 0xFFFF -#endif - -#if (G12_7PL >= G12_9PL) || (G12_7PL == 0) -#define MG12_9_17PL ~(1 << 6) -#else -#define MG12_9_17PL 0xFFFF -#endif - -#if (G12_8PL >= G12_9PL) || (G12_8PL == 0) -#define MG12_9_18PL ~(1 << 7) -#else -#define MG12_9_18PL 0xFFFF -#endif - -#if (G12_10PL >= G12_9PL) || (G12_10PL == 0) -#define MG12_9_110PL ~(1 << 9) -#else -#define MG12_9_110PL 0xFFFF -#endif - -#if (G12_11PL >= G12_9PL) || (G12_11PL == 0) -#define MG12_9_111PL ~(1 << 10) -#else -#define MG12_9_111PL 0xFFFF -#endif - -#if (G12_12PL >= G12_9PL) || (G12_12PL == 0) -#define MG12_9_112PL ~(1 << 11) -#else -#define MG12_9_112PL 0xFFFF -#endif - -#if (G12_13PL >= G12_9PL) || (G12_13PL == 0) -#define MG12_9_113PL ~(1 << 12) -#else -#define MG12_9_113PL 0xFFFF -#endif - -#if (G12_14PL >= G12_9PL) || (G12_14PL == 0) -#define MG12_9_114PL ~(1 << 13) -#else -#define MG12_9_114PL 0xFFFF -#endif - -#if (G12_15PL >= G12_9PL) || (G12_15PL == 0) -#define MG12_9_115PL ~(1 << 14) -#else -#define MG12_9_115PL 0xFFFF -#endif - -#if (G12_16PL >= G12_9PL) || (G12_16PL == 0) -#define MG12_9_116PL ~(1 << 15) -#else -#define MG12_9_116PL 0xFFFF -#endif - -#define MG12_9_19PL 0xFEFF -#define MG12_9 (MG12_9_11PL & MG12_9_12PL & MG12_9_13PL & MG12_9_14PL & \ - MG12_9_15PL & MG12_9_16PL & MG12_9_17PL & MG12_9_18PL & \ - MG12_9_19PL & MG12_9_110PL & MG12_9_111PL & MG12_9_112PL & \ - MG12_9_113PL & MG12_9_114PL & MG12_9_115PL & MG12_9_116PL) -// End of MG12_9: -// Beginning of MG1210: -#if (G12_1PL >= G12_10PL) || (G12_1PL == 0) -#define MG12_10_11PL ~(1 << 0) -#else -#define MG12_10_11PL 0xFFFF -#endif - -#if (G12_2PL >= G12_10PL) || (G12_2PL == 0) -#define MG12_10_12PL ~(1 << 1) -#else -#define MG12_10_12PL 0xFFFF -#endif - -#if (G12_3PL >= G12_10PL) || (G12_3PL == 0) -#define MG12_10_13PL ~(1 << 2) -#else -#define MG12_10_13PL 0xFFFF -#endif - -#if (G12_4PL >= G12_10PL) || (G12_4PL == 0) -#define MG12_10_14PL ~(1 << 3) -#else -#define MG12_10_14PL 0xFFFF -#endif - -#if (G12_5PL >= G12_10PL) || (G12_5PL == 0) -#define MG12_10_15PL ~(1 << 4) -#else -#define MG12_10_15PL 0xFFFF -#endif - -#if (G12_6PL >= G12_10PL) || (G12_6PL == 0) -#define MG12_10_16PL ~(1 << 5) -#else -#define MG12_10_16PL 0xFFFF -#endif - -#if (G12_7PL >= G12_10PL) || (G12_7PL == 0) -#define MG12_10_17PL ~(1 << 6) -#else -#define MG12_10_17PL 0xFFFF -#endif - -#if (G12_8PL >= G12_10PL) || (G12_8PL == 0) -#define MG12_10_18PL ~(1 << 7) -#else -#define MG12_10_18PL 0xFFFF -#endif - -#if (G12_9PL >= G12_10PL) || (G12_9PL == 0) -#define MG12_10_19PL ~(1 << 8) -#else -#define MG12_10_19PL 0xFFFF -#endif - -#if (G12_11PL >= G12_10PL) || (G12_11PL == 0) -#define MG12_10_111PL ~(1 << 10) -#else -#define MG12_10_111PL 0xFFFF -#endif - -#if (G12_12PL >= G12_10PL) || (G12_12PL == 0) -#define MG12_10_112PL ~(1 << 11) -#else -#define MG12_10_112PL 0xFFFF -#endif - -#if (G12_13PL >= G12_10PL) || (G12_13PL == 0) -#define MG12_10_113PL ~(1 << 12) -#else -#define MG12_10_113PL 0xFFFF -#endif - -#if (G12_14PL >= G12_10PL) || (G12_14PL == 0) -#define MG12_10_114PL ~(1 << 13) -#else -#define MG12_10_114PL 0xFFFF -#endif - -#if (G12_15PL >= G12_10PL) || (G12_15PL == 0) -#define MG12_10_115PL ~(1 << 14) -#else -#define MG12_10_115PL 0xFFFF -#endif - -#if (G12_16PL >= G12_10PL) || (G12_16PL == 0) -#define MG12_10_116PL ~(1 << 15) -#else -#define MG12_10_116PL 0xFFFF -#endif - -#define MG12_10_110PL 0xFDFF -#define MG12_10 (MG12_10_11PL & MG12_10_12PL & MG12_10_13PL & MG12_10_14PL & \ - MG12_10_15PL & MG12_10_16PL & MG12_10_17PL & MG12_10_18PL & \ - MG12_10_19PL & MG12_10_110PL & MG12_10_111PL & MG12_10_112PL & \ - MG12_10_113PL & MG12_10_114PL & MG12_10_115PL & MG12_10_116PL) -// End of MG12_10: -// Beginning of MG1211: -#if (G12_1PL >= G12_11PL) || (G12_1PL == 0) -#define MG12_11_11PL ~(1 << 0) -#else -#define MG12_11_11PL 0xFFFF -#endif - -#if (G12_2PL >= G12_11PL) || (G12_2PL == 0) -#define MG12_11_12PL ~(1 << 1) -#else -#define MG12_11_12PL 0xFFFF -#endif - -#if (G12_3PL >= G12_11PL) || (G12_3PL == 0) -#define MG12_11_13PL ~(1 << 2) -#else -#define MG12_11_13PL 0xFFFF -#endif - -#if (G12_4PL >= G12_11PL) || (G12_4PL == 0) -#define MG12_11_14PL ~(1 << 3) -#else -#define MG12_11_14PL 0xFFFF -#endif - -#if (G12_5PL >= G12_11PL) || (G12_5PL == 0) -#define MG12_11_15PL ~(1 << 4) -#else -#define MG12_11_15PL 0xFFFF -#endif - -#if (G12_6PL >= G12_11PL) || (G12_6PL == 0) -#define MG12_11_16PL ~(1 << 5) -#else -#define MG12_11_16PL 0xFFFF -#endif - -#if (G12_7PL >= G12_11PL) || (G12_7PL == 0) -#define MG12_11_17PL ~(1 << 6) -#else -#define MG12_11_17PL 0xFFFF -#endif - -#if (G12_8PL >= G12_11PL) || (G12_8PL == 0) -#define MG12_11_18PL ~(1 << 7) -#else -#define MG12_11_18PL 0xFFFF -#endif - -#if (G12_9PL >= G12_11PL) || (G12_9PL == 0) -#define MG12_11_19PL ~(1 << 8) -#else -#define MG12_11_19PL 0xFFFF -#endif - -#if (G12_10PL >= G12_11PL) || (G12_10PL == 0) -#define MG12_11_110PL ~(1 << 9) -#else -#define MG12_11_110PL 0xFFFF -#endif - -#if (G12_12PL >= G12_11PL) || (G12_12PL == 0) -#define MG12_11_112PL ~(1 << 11) -#else -#define MG12_11_112PL 0xFFFF -#endif - -#if (G12_13PL >= G12_11PL) || (G12_13PL == 0) -#define MG12_11_113PL ~(1 << 12) -#else -#define MG12_11_113PL 0xFFFF -#endif - -#if (G12_14PL >= G12_11PL) || (G12_14PL == 0) -#define MG12_11_114PL ~(1 << 13) -#else -#define MG12_11_114PL 0xFFFF -#endif - -#if (G12_15PL >= G12_11PL) || (G12_15PL == 0) -#define MG12_11_115PL ~(1 << 14) -#else -#define MG12_11_115PL 0xFFFF -#endif - -#if (G12_16PL >= G12_11PL) || (G12_16PL == 0) -#define MG12_11_116PL ~(1 << 15) -#else -#define MG12_11_116PL 0xFFFF -#endif - -#define MG12_11_111PL 0xFBFF -#define MG12_11 (MG12_11_11PL & MG12_11_12PL & MG12_11_13PL & MG12_11_14PL & \ - MG12_11_15PL & MG12_11_16PL & MG12_11_17PL & MG12_11_18PL & \ - MG12_11_19PL & MG12_11_110PL & MG12_11_111PL & MG12_11_112PL & \ - MG12_11_113PL & MG12_11_114PL & MG12_11_115PL & MG12_11_116PL) -// End of MG12_11: -// Beginning of MG1212: -#if (G12_1PL >= G12_12PL) || (G12_1PL == 0) -#define MG12_12_11PL ~(1 << 0) -#else -#define MG12_12_11PL 0xFFFF -#endif - -#if (G12_2PL >= G12_12PL) || (G12_2PL == 0) -#define MG12_12_12PL ~(1 << 1) -#else -#define MG12_12_12PL 0xFFFF -#endif - -#if (G12_3PL >= G12_12PL) || (G12_3PL == 0) -#define MG12_12_13PL ~(1 << 2) -#else -#define MG12_12_13PL 0xFFFF -#endif - -#if (G12_4PL >= G12_12PL) || (G12_4PL == 0) -#define MG12_12_14PL ~(1 << 3) -#else -#define MG12_12_14PL 0xFFFF -#endif - -#if (G12_5PL >= G12_12PL) || (G12_5PL == 0) -#define MG12_12_15PL ~(1 << 4) -#else -#define MG12_12_15PL 0xFFFF -#endif - -#if (G12_6PL >= G12_12PL) || (G12_6PL == 0) -#define MG12_12_16PL ~(1 << 5) -#else -#define MG12_12_16PL 0xFFFF -#endif - -#if (G12_7PL >= G12_12PL) || (G12_7PL == 0) -#define MG12_12_17PL ~(1 << 6) -#else -#define MG12_12_17PL 0xFFFF -#endif - -#if (G12_8PL >= G12_12PL) || (G12_8PL == 0) -#define MG12_12_18PL ~(1 << 7) -#else -#define MG12_12_18PL 0xFFFF -#endif - -#if (G12_9PL >= G12_12PL) || (G12_9PL == 0) -#define MG12_12_19PL ~(1 << 8) -#else -#define MG12_12_19PL 0xFFFF -#endif - -#if (G12_10PL >= G12_12PL) || (G12_10PL == 0) -#define MG12_12_110PL ~(1 << 9) -#else -#define MG12_12_110PL 0xFFFF -#endif - -#if (G12_11PL >= G12_12PL) || (G12_11PL == 0) -#define MG12_12_111PL ~(1 << 10) -#else -#define MG12_12_111PL 0xFFFF -#endif - -#if (G12_13PL >= G12_12PL) || (G12_13PL == 0) -#define MG12_12_113PL ~(1 << 12) -#else -#define MG12_12_113PL 0xFFFF -#endif - -#if (G12_14PL >= G12_12PL) || (G12_14PL == 0) -#define MG12_12_114PL ~(1 << 13) -#else -#define MG12_12_114PL 0xFFFF -#endif - -#if (G12_15PL >= G12_12PL) || (G12_15PL == 0) -#define MG12_12_115PL ~(1 << 14) -#else -#define MG12_12_115PL 0xFFFF -#endif - -#if (G12_16PL >= G12_12PL) || (G12_16PL == 0) -#define MG12_12_116PL ~(1 << 15) -#else -#define MG12_12_116PL 0xFFFF -#endif - -#define MG12_12_112PL 0xF7FF -#define MG12_12 (MG12_12_11PL & MG12_12_12PL & MG12_12_13PL & MG12_12_14PL & \ - MG12_12_15PL & MG12_12_16PL & MG12_12_17PL & MG12_12_18PL & \ - MG12_12_19PL & MG12_12_110PL & MG12_12_111PL & MG12_12_112PL & \ - MG12_12_113PL & MG12_12_114PL & MG12_12_115PL & MG12_12_116PL) -// End of MG12_12: -// Beginning of MG1213: -#if (G12_1PL >= G12_13PL) || (G12_1PL == 0) -#define MG12_13_11PL ~(1 << 0) -#else -#define MG12_13_11PL 0xFFFF -#endif - -#if (G12_2PL >= G12_13PL) || (G12_2PL == 0) -#define MG12_13_12PL ~(1 << 1) -#else -#define MG12_13_12PL 0xFFFF -#endif - -#if (G12_3PL >= G12_13PL) || (G12_3PL == 0) -#define MG12_13_13PL ~(1 << 2) -#else -#define MG12_13_13PL 0xFFFF -#endif - -#if (G12_4PL >= G12_13PL) || (G12_4PL == 0) -#define MG12_13_14PL ~(1 << 3) -#else -#define MG12_13_14PL 0xFFFF -#endif - -#if (G12_5PL >= G12_13PL) || (G12_5PL == 0) -#define MG12_13_15PL ~(1 << 4) -#else -#define MG12_13_15PL 0xFFFF -#endif - -#if (G12_6PL >= G12_13PL) || (G12_6PL == 0) -#define MG12_13_16PL ~(1 << 5) -#else -#define MG12_13_16PL 0xFFFF -#endif - -#if (G12_7PL >= G12_13PL) || (G12_7PL == 0) -#define MG12_13_17PL ~(1 << 6) -#else -#define MG12_13_17PL 0xFFFF -#endif - -#if (G12_8PL >= G12_13PL) || (G12_8PL == 0) -#define MG12_13_18PL ~(1 << 7) -#else -#define MG12_13_18PL 0xFFFF -#endif - -#if (G12_9PL >= G12_13PL) || (G12_9PL == 0) -#define MG12_13_19PL ~(1 << 8) -#else -#define MG12_13_19PL 0xFFFF -#endif - -#if (G12_10PL >= G12_13PL) || (G12_10PL == 0) -#define MG12_13_110PL ~(1 << 9) -#else -#define MG12_13_110PL 0xFFFF -#endif - -#if (G12_11PL >= G12_13PL) || (G12_11PL == 0) -#define MG12_13_111PL ~(1 << 10) -#else -#define MG12_13_111PL 0xFFFF -#endif - -#if (G12_12PL >= G12_13PL) || (G12_12PL == 0) -#define MG12_13_112PL ~(1 << 11) -#else -#define MG12_13_112PL 0xFFFF -#endif - -#if (G12_14PL >= G12_13PL) || (G12_14PL == 0) -#define MG12_13_114PL ~(1 << 13) -#else -#define MG12_13_114PL 0xFFFF -#endif - -#if (G12_15PL >= G12_13PL) || (G12_15PL == 0) -#define MG12_13_115PL ~(1 << 14) -#else -#define MG12_13_115PL 0xFFFF -#endif - -#if (G12_16PL >= G12_13PL) || (G12_16PL == 0) -#define MG12_13_116PL ~(1 << 15) -#else -#define MG12_13_116PL 0xFFFF -#endif - -#define MG12_13_113PL 0xEFFF -#define MG12_13 (MG12_13_11PL & MG12_13_12PL & MG12_13_13PL & MG12_13_14PL & \ - MG12_13_15PL & MG12_13_16PL & MG12_13_17PL & MG12_13_18PL & \ - MG12_13_19PL & MG12_13_110PL & MG12_13_111PL & MG12_13_112PL & \ - MG12_13_113PL & MG12_13_114PL & MG12_13_115PL & MG12_13_116PL) -// End of MG12_13: -// Beginning of MG1214: -#if (G12_1PL >= G12_14PL) || (G12_1PL == 0) -#define MG12_14_11PL ~(1 << 0) -#else -#define MG12_14_11PL 0xFFFF -#endif - -#if (G12_2PL >= G12_14PL) || (G12_2PL == 0) -#define MG12_14_12PL ~(1 << 1) -#else -#define MG12_14_12PL 0xFFFF -#endif - -#if (G12_3PL >= G12_14PL) || (G12_3PL == 0) -#define MG12_14_13PL ~(1 << 2) -#else -#define MG12_14_13PL 0xFFFF -#endif - -#if (G12_4PL >= G12_14PL) || (G12_4PL == 0) -#define MG12_14_14PL ~(1 << 3) -#else -#define MG12_14_14PL 0xFFFF -#endif - -#if (G12_5PL >= G12_14PL) || (G12_5PL == 0) -#define MG12_14_15PL ~(1 << 4) -#else -#define MG12_14_15PL 0xFFFF -#endif - -#if (G12_6PL >= G12_14PL) || (G12_6PL == 0) -#define MG12_14_16PL ~(1 << 5) -#else -#define MG12_14_16PL 0xFFFF -#endif - -#if (G12_7PL >= G12_14PL) || (G12_7PL == 0) -#define MG12_14_17PL ~(1 << 6) -#else -#define MG12_14_17PL 0xFFFF -#endif - -#if (G12_8PL >= G12_14PL) || (G12_8PL == 0) -#define MG12_14_18PL ~(1 << 7) -#else -#define MG12_14_18PL 0xFFFF -#endif - -#if (G12_9PL >= G12_14PL) || (G12_9PL == 0) -#define MG12_14_19PL ~(1 << 8) -#else -#define MG12_14_19PL 0xFFFF -#endif - -#if (G12_10PL >= G12_14PL) || (G12_10PL == 0) -#define MG12_14_110PL ~(1 << 9) -#else -#define MG12_14_110PL 0xFFFF -#endif - -#if (G12_11PL >= G12_14PL) || (G12_11PL == 0) -#define MG12_14_111PL ~(1 << 10) -#else -#define MG12_14_111PL 0xFFFF -#endif - -#if (G12_12PL >= G12_14PL) || (G12_12PL == 0) -#define MG12_14_112PL ~(1 << 11) -#else -#define MG12_14_112PL 0xFFFF -#endif - -#if (G12_13PL >= G12_14PL) || (G12_13PL == 0) -#define MG12_14_113PL ~(1 << 12) -#else -#define MG12_14_113PL 0xFFFF -#endif - -#if (G12_15PL >= G12_14PL) || (G12_15PL == 0) -#define MG12_14_115PL ~(1 << 14) -#else -#define MG12_14_115PL 0xFFFF -#endif - -#if (G12_16PL >= G12_14PL) || (G12_16PL == 0) -#define MG12_14_116PL ~(1 << 15) -#else -#define MG12_14_116PL 0xFFFF -#endif - -#define MG12_14_114PL 0xDFFF -#define MG12_14 (MG12_14_11PL & MG12_14_12PL & MG12_14_13PL & MG12_14_14PL & \ - MG12_14_15PL & MG12_14_16PL & MG12_14_17PL & MG12_14_18PL & \ - MG12_14_19PL & MG12_14_110PL & MG12_14_111PL & MG12_14_112PL & \ - MG12_14_113PL & MG12_14_114PL & MG12_14_115PL & MG12_14_116PL) -// End of MG12_14: -// Beginning of MG1215: -#if (G12_1PL >= G12_15PL) || (G12_1PL == 0) -#define MG12_15_11PL ~(1 << 0) -#else -#define MG12_15_11PL 0xFFFF -#endif - -#if (G12_2PL >= G12_15PL) || (G12_2PL == 0) -#define MG12_15_12PL ~(1 << 1) -#else -#define MG12_15_12PL 0xFFFF -#endif - -#if (G12_3PL >= G12_15PL) || (G12_3PL == 0) -#define MG12_15_13PL ~(1 << 2) -#else -#define MG12_15_13PL 0xFFFF -#endif - -#if (G12_4PL >= G12_15PL) || (G12_4PL == 0) -#define MG12_15_14PL ~(1 << 3) -#else -#define MG12_15_14PL 0xFFFF -#endif - -#if (G12_5PL >= G12_15PL) || (G12_5PL == 0) -#define MG12_15_15PL ~(1 << 4) -#else -#define MG12_15_15PL 0xFFFF -#endif - -#if (G12_6PL >= G12_15PL) || (G12_6PL == 0) -#define MG12_15_16PL ~(1 << 5) -#else -#define MG12_15_16PL 0xFFFF -#endif - -#if (G12_7PL >= G12_15PL) || (G12_7PL == 0) -#define MG12_15_17PL ~(1 << 6) -#else -#define MG12_15_17PL 0xFFFF -#endif - -#if (G12_8PL >= G12_15PL) || (G12_8PL == 0) -#define MG12_15_18PL ~(1 << 7) -#else -#define MG12_15_18PL 0xFFFF -#endif - -#if (G12_9PL >= G12_15PL) || (G12_9PL == 0) -#define MG12_15_19PL ~(1 << 8) -#else -#define MG12_15_19PL 0xFFFF -#endif - -#if (G12_10PL >= G12_15PL) || (G12_10PL == 0) -#define MG12_15_110PL ~(1 << 9) -#else -#define MG12_15_110PL 0xFFFF -#endif - -#if (G12_11PL >= G12_15PL) || (G12_11PL == 0) -#define MG12_15_111PL ~(1 << 10) -#else -#define MG12_15_111PL 0xFFFF -#endif - -#if (G12_12PL >= G12_15PL) || (G12_12PL == 0) -#define MG12_15_112PL ~(1 << 11) -#else -#define MG12_15_112PL 0xFFFF -#endif - -#if (G12_13PL >= G12_15PL) || (G12_13PL == 0) -#define MG12_15_113PL ~(1 << 12) -#else -#define MG12_15_113PL 0xFFFF -#endif - -#if (G12_14PL >= G12_15PL) || (G12_14PL == 0) -#define MG12_15_114PL ~(1 << 13) -#else -#define MG12_15_114PL 0xFFFF -#endif - -#if (G12_16PL >= G12_15PL) || (G12_16PL == 0) -#define MG12_15_116PL ~(1 << 15) -#else -#define MG12_15_116PL 0xFFFF -#endif - -#define MG12_15_115PL 0xBFFF -#define MG12_15 (MG12_15_11PL & MG12_15_12PL & MG12_15_13PL & MG12_15_14PL & \ - MG12_15_15PL & MG12_15_16PL & MG12_15_17PL & MG12_15_18PL & \ - MG12_15_19PL & MG12_15_110PL & MG12_15_111PL & MG12_15_112PL & \ - MG12_15_113PL & MG12_15_114PL & MG12_15_115PL & MG12_15_116PL) -// End of MG12_15: -// Beginning of MG1216: -#if (G12_1PL >= G12_16PL) || (G12_1PL == 0) -#define MG12_16_11PL ~(1 << 0) -#else -#define MG12_16_11PL 0xFFFF -#endif - -#if (G12_2PL >= G12_16PL) || (G12_2PL == 0) -#define MG12_16_12PL ~(1 << 1) -#else -#define MG12_16_12PL 0xFFFF -#endif - -#if (G12_3PL >= G12_16PL) || (G12_3PL == 0) -#define MG12_16_13PL ~(1 << 2) -#else -#define MG12_16_13PL 0xFFFF -#endif - -#if (G12_4PL >= G12_16PL) || (G12_4PL == 0) -#define MG12_16_14PL ~(1 << 3) -#else -#define MG12_16_14PL 0xFFFF -#endif - -#if (G12_5PL >= G12_16PL) || (G12_5PL == 0) -#define MG12_16_15PL ~(1 << 4) -#else -#define MG12_16_15PL 0xFFFF -#endif - -#if (G12_6PL >= G12_16PL) || (G12_6PL == 0) -#define MG12_16_16PL ~(1 << 5) -#else -#define MG12_16_16PL 0xFFFF -#endif - -#if (G12_7PL >= G12_16PL) || (G12_7PL == 0) -#define MG12_16_17PL ~(1 << 6) -#else -#define MG12_16_17PL 0xFFFF -#endif - -#if (G12_8PL >= G12_16PL) || (G12_8PL == 0) -#define MG12_16_18PL ~(1 << 7) -#else -#define MG12_16_18PL 0xFFFF -#endif - -#if (G12_9PL >= G12_16PL) || (G12_9PL == 0) -#define MG12_16_19PL ~(1 << 8) -#else -#define MG12_16_19PL 0xFFFF -#endif - -#if (G12_10PL >= G12_16PL) || (G12_10PL == 0) -#define MG12_16_110PL ~(1 << 9) -#else -#define MG12_16_110PL 0xFFFF -#endif - -#if (G12_11PL >= G12_16PL) || (G12_11PL == 0) -#define MG12_16_111PL ~(1 << 10) -#else -#define MG12_16_111PL 0xFFFF -#endif - -#if (G12_12PL >= G12_16PL) || (G12_12PL == 0) -#define MG12_16_112PL ~(1 << 11) -#else -#define MG12_16_112PL 0xFFFF -#endif - -#if (G12_13PL >= G12_16PL) || (G12_13PL == 0) -#define MG12_16_113PL ~(1 << 12) -#else -#define MG12_16_113PL 0xFFFF -#endif - -#if (G12_14PL >= G12_16PL) || (G12_14PL == 0) -#define MG12_16_114PL ~(1 << 13) -#else -#define MG12_16_114PL 0xFFFF -#endif - -#if (G12_15PL >= G12_16PL) || (G12_15PL == 0) -#define MG12_16_115PL ~(1 << 14) -#else -#define MG12_16_115PL 0xFFFF -#endif - -#define MG12_16_116PL 0x7FFF -#define MG12_16 (MG12_16_11PL & MG12_16_12PL & MG12_16_13PL & MG12_16_14PL & \ - MG12_16_15PL & MG12_16_16PL & MG12_16_17PL & MG12_16_18PL & \ - MG12_16_19PL & MG12_16_110PL & MG12_16_111PL & MG12_16_112PL & \ - MG12_16_113PL & MG12_16_114PL & MG12_16_115PL & MG12_16_116PL) -// End of MG12_16: - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // eof - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_SysCtrl_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_SysCtrl_defines.h deleted file mode 100644 index a0f342d14c..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_SysCtrl_defines.h +++ /dev/null @@ -1,63 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_SysCtrl_defines.h -// -// TITLE: F2837xD LPM support definitions -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_SYSCTRL_DEFINES_H -#define F2837xD_SYSCTRL_DEFINES_H - -// -// Defines -// -#define LPM_IDLE 0x0 -#define LPM_STANDBY 0x1 -#define LPM_HALT 0x2 -#define LPM_HIB 0x3 - -// -//Key value used for write access to the flash pump semaphore register -// -#define IPC_PUMP_KEY 0x5a5a0000 - -#endif // end of F2837xD_SYSCTRL_DEFINES_H definition - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Systick_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Systick_defines.h deleted file mode 100644 index dbf45cb249..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Systick_defines.h +++ /dev/null @@ -1,80 +0,0 @@ -//########################################################################### -// -// FILE: systick.h -// -// TITLE: Stellaris style wrapper driver for C28x CPU Timer 0. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __SYSTICK_H__ -#define __SYSTICK_H__ - -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -#ifdef __cplusplus -extern "C" -{ -#endif - -// -// Function Prototypes -// -extern void SysTickInit(void); -extern void SysTickEnable(void); -extern void SysTickDisable(void); -extern void SysTickIntRegister(void (*pfnHandler)(void)); -extern void SysTickIntUnregister(void); -extern void SysTickIntEnable(void); -extern void SysTickIntDisable(void); -extern void SysTickPeriodSet(unsigned long ulPeriod); -extern unsigned long SysTickPeriodGet(void); -extern unsigned long SysTickValueGet(void); - -// -// Mark the end of the C bindings section for C++ compilers. -// -#ifdef __cplusplus -} -#endif - -#endif // __SYSTICK_H__ - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Upp_defines.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Upp_defines.h deleted file mode 100644 index 43d602bfb0..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_Upp_defines.h +++ /dev/null @@ -1,86 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Upp_defines.h -// -// TITLE: #defines used in Upp examples -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_UPP_DEFINES_H -#define F2837xD_UPP_DEFINES_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// -#define uPP_TX_MSGRAM_ADDR 0x6C00 -#define uPP_TX_MSGRAM_SIZE 512 - -#define uPP_RX_MSGRAM_ADDR 0x6E00 -#define uPP_RX_MSGRAM_SIZE 512 - -#define uPP_RX_MODE 0 -#define uPP_TX_MODE 1 - -#define uPP_SDR 0 -#define uPP_DDR 1 - -#define uPP_TX_SIZE_64B 0 -#define uPP_TX_SIZE_128B 1 -#define uPP_TX_SIZE_256B 3 - -#define uPP_RX_SIZE_64B 0 -#define uPP_RX_SIZE_128B 1 -#define uPP_RX_SIZE_256B 3 - -#define uPP_INT_EOWI 0x8 -#define uPP_INT_EOLI 0x10 -#define uPP_INT_EOWQ 0x800 -#define uPP_INT_EOLQ 0x1000 - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F2837xD_UPP_DEFINES_H - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_cputimervars.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_cputimervars.h deleted file mode 100644 index 0f32f58aea..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_cputimervars.h +++ /dev/null @@ -1,138 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Cputimers.h -// -// TITLE: F2837xD Device CPUTIMERS Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_CPUTIMERVARS_H -#define F2837xD_CPUTIMERVARS_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Globals -// -struct CPUTIMER_VARS { - volatile struct CPUTIMER_REGS *RegsAddr; - Uint32 InterruptCount; - float CPUFreqInMHz; - float PeriodInUSec; -}; - -extern struct CPUTIMER_VARS CpuTimer0; -extern struct CPUTIMER_VARS CpuTimer1; -extern struct CPUTIMER_VARS CpuTimer2; - -// -// Defines -// - -// -// Start Timer: -// -#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 - -// -// Stop Timer: -// -#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 - -// -// Reload Timer With period Value: -// -#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 - -// -// Read 32-Bit Timer Value: -// -#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all - -// -// Read 32-Bit Period Value: -// -#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all - -// -// Start Timer: -// -#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 -#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 - -// -// Stop Timer: -// -#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 -#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 - -// -// Reload Timer With period Value: -// -#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 -#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 - -// -// Read 32-Bit Timer Value: -// -#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all -#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all - -// -// Read 32-Bit Period Value: -// -#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all -#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all - -// -// Function Prototypes -// -void InitCpuTimers(void); -void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); - -#ifdef __cplusplus -} -#endif /* extern "C" */ - - -#endif // end of F2837xD_CPUTIMERVARS_H definition - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_defaultisr.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_defaultisr.h deleted file mode 100644 index 3f351d85b7..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_defaultisr.h +++ /dev/null @@ -1,216 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_defaultisr.h -// -// TITLE: F2837xD Device Default Interrupt Service Routines Definitions -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_DEFAULT_ISR_H -#define F2837xD_DEFAULT_ISR_H -#ifdef __cplusplus -extern "C" { -#endif - -// -// Default Interrupt Service Routine Declarations: -// The following function prototypes are for the -// default ISR routines used with the default PIE vector table. -// This default vector table is found in the F2837xD_pievect.h -// file. -// -interrupt void TIMER1_ISR(void); // CPU Timer 1 Interrupt -interrupt void TIMER2_ISR(void); // CPU Timer 2 Interrupt -interrupt void DATALOG_ISR(void); // Datalogging Interrupt -interrupt void RTOS_ISR(void); // RTOS Interrupt -interrupt void EMU_ISR(void); // Emulation Interrupt -interrupt void NMI_ISR(void); // Non-Maskable Interrupt -interrupt void ILLEGAL_ISR(void); // Illegal Operation Trap -interrupt void USER1_ISR(void); // User Defined Trap 1 -interrupt void USER2_ISR(void); // User Defined Trap 2 -interrupt void USER3_ISR(void); // User Defined Trap 3 -interrupt void USER4_ISR(void); // User Defined Trap 4 -interrupt void USER5_ISR(void); // User Defined Trap 5 -interrupt void USER6_ISR(void); // User Defined Trap 6 -interrupt void USER7_ISR(void); // User Defined Trap 7 -interrupt void USER8_ISR(void); // User Defined Trap 8 -interrupt void USER9_ISR(void); // User Defined Trap 9 -interrupt void USER10_ISR(void); // User Defined Trap 10 -interrupt void USER11_ISR(void); // User Defined Trap 11 -interrupt void USER12_ISR(void); // User Defined Trap 12 -interrupt void ADCA1_ISR(void); // 1.1 - ADCA Interrupt 1 -interrupt void ADCB1_ISR(void); // 1.2 - ADCB Interrupt 1 -interrupt void ADCC1_ISR(void); // 1.3 - ADCC Interrupt 1 -interrupt void XINT1_ISR(void); // 1.4 - XINT1 Interrupt -interrupt void XINT2_ISR(void); // 1.5 - XINT2 Interrupt -interrupt void ADCD1_ISR(void); // 1.6 - ADCD Interrupt 1 -interrupt void TIMER0_ISR(void); // 1.7 - Timer 0 Interrupt -interrupt void WAKE_ISR(void); // 1.8 - Standby and Halt Wakeup Interrupt -interrupt void EPWM1_TZ_ISR(void); // 2.1 - ePWM1 Trip Zone Interrupt -interrupt void EPWM2_TZ_ISR(void); // 2.2 - ePWM2 Trip Zone Interrupt -interrupt void EPWM3_TZ_ISR(void); // 2.3 - ePWM3 Trip Zone Interrupt -interrupt void EPWM4_TZ_ISR(void); // 2.4 - ePWM4 Trip Zone Interrupt -interrupt void EPWM5_TZ_ISR(void); // 2.5 - ePWM5 Trip Zone Interrupt -interrupt void EPWM6_TZ_ISR(void); // 2.6 - ePWM6 Trip Zone Interrupt -interrupt void EPWM7_TZ_ISR(void); // 2.7 - ePWM7 Trip Zone Interrupt -interrupt void EPWM8_TZ_ISR(void); // 2.8 - ePWM8 Trip Zone Interrupt -interrupt void EPWM1_ISR(void); // 3.1 - ePWM1 Interrupt -interrupt void EPWM2_ISR(void); // 3.2 - ePWM2 Interrupt -interrupt void EPWM3_ISR(void); // 3.3 - ePWM3 Interrupt -interrupt void EPWM4_ISR(void); // 3.4 - ePWM4 Interrupt -interrupt void EPWM5_ISR(void); // 3.5 - ePWM5 Interrupt -interrupt void EPWM6_ISR(void); // 3.6 - ePWM6 Interrupt -interrupt void EPWM7_ISR(void); // 3.7 - ePWM7 Interrupt -interrupt void EPWM8_ISR(void); // 3.8 - ePWM8 Interrupt -interrupt void ECAP1_ISR(void); // 4.1 - eCAP1 Interrupt -interrupt void ECAP2_ISR(void); // 4.2 - eCAP2 Interrupt -interrupt void ECAP3_ISR(void); // 4.3 - eCAP3 Interrupt -interrupt void ECAP4_ISR(void); // 4.4 - eCAP4 Interrupt -interrupt void ECAP5_ISR(void); // 4.5 - eCAP5 Interrupt -interrupt void ECAP6_ISR(void); // 4.6 - eCAP6 Interrupt -interrupt void EQEP1_ISR(void); // 5.1 - eQEP1 Interrupt -interrupt void EQEP2_ISR(void); // 5.2 - eQEP2 Interrupt -interrupt void EQEP3_ISR(void); // 5.3 - eQEP3 Interrupt -interrupt void SPIA_RX_ISR(void); // 6.1 - SPIA Receive Interrupt -interrupt void SPIA_TX_ISR(void); // 6.2 - SPIA Transmit Interrupt -interrupt void SPIB_RX_ISR(void); // 6.3 - SPIB Receive Interrupt -interrupt void SPIB_TX_ISR(void); // 6.4 - SPIB Transmit Interrupt -interrupt void MCBSPA_RX_ISR(void); // 6.5 - McBSPA Receive Interrupt -interrupt void MCBSPA_TX_ISR(void); // 6.6 - McBSPA Transmit Interrupt -interrupt void MCBSPB_RX_ISR(void); // 6.7 - McBSPB Receive Interrupt -interrupt void MCBSPB_TX_ISR(void); // 6.8 - McBSPB Transmit Interrupt -interrupt void DMA_CH1_ISR(void); // 7.1 - DMA Channel 1 Interrupt -interrupt void DMA_CH2_ISR(void); // 7.2 - DMA Channel 2 Interrupt -interrupt void DMA_CH3_ISR(void); // 7.3 - DMA Channel 3 Interrupt -interrupt void DMA_CH4_ISR(void); // 7.4 - DMA Channel 4 Interrupt -interrupt void DMA_CH5_ISR(void); // 7.5 - DMA Channel 5 Interrupt -interrupt void DMA_CH6_ISR(void); // 7.6 - DMA Channel 6 Interrupt -interrupt void I2CA_ISR(void); // 8.1 - I2CA Interrupt 1 -interrupt void I2CA_FIFO_ISR(void); // 8.2 - I2CA Interrupt 2 -interrupt void I2CB_ISR(void); // 8.3 - I2CB Interrupt 1 -interrupt void I2CB_FIFO_ISR(void); // 8.4 - I2CB Interrupt 2 -interrupt void SCIC_RX_ISR(void); // 8.5 - SCIC Receive Interrupt -interrupt void SCIC_TX_ISR(void); // 8.6 - SCIC Transmit Interrupt -interrupt void SCID_RX_ISR(void); // 8.7 - SCID Receive Interrupt -interrupt void SCID_TX_ISR(void); // 8.8 - SCID Transmit Interrupt -interrupt void SCIA_RX_ISR(void); // 9.1 - SCIA Receive Interrupt -interrupt void SCIA_TX_ISR(void); // 9.2 - SCIA Transmit Interrupt -interrupt void SCIB_RX_ISR(void); // 9.3 - SCIB Receive Interrupt -interrupt void SCIB_TX_ISR(void); // 9.4 - SCIB Transmit Interrupt -interrupt void CANA0_ISR(void); // 9.5 - CANA Interrupt 0 -interrupt void CANA1_ISR(void); // 9.6 - CANA Interrupt 1 -interrupt void CANB0_ISR(void); // 9.7 - CANB Interrupt 0 -interrupt void CANB1_ISR(void); // 9.8 - CANB Interrupt 1 -interrupt void ADCA_EVT_ISR(void); // 10.1 - ADCA Event Interrupt -interrupt void ADCA2_ISR(void); // 10.2 - ADCA Interrupt 2 -interrupt void ADCA3_ISR(void); // 10.3 - ADCA Interrupt 3 -interrupt void ADCA4_ISR(void); // 10.4 - ADCA Interrupt 4 -interrupt void ADCB_EVT_ISR(void); // 10.5 - ADCB Event Interrupt -interrupt void ADCB2_ISR(void); // 10.6 - ADCB Interrupt 2 -interrupt void ADCB3_ISR(void); // 10.7 - ADCB Interrupt 3 -interrupt void ADCB4_ISR(void); // 10.8 - ADCB Interrupt 4 -interrupt void CLA1_1_ISR(void); // 11.1 - CLA1 Interrupt 1 -interrupt void CLA1_2_ISR(void); // 11.2 - CLA1 Interrupt 2 -interrupt void CLA1_3_ISR(void); // 11.3 - CLA1 Interrupt 3 -interrupt void CLA1_4_ISR(void); // 11.4 - CLA1 Interrupt 4 -interrupt void CLA1_5_ISR(void); // 11.5 - CLA1 Interrupt 5 -interrupt void CLA1_6_ISR(void); // 11.6 - CLA1 Interrupt 6 -interrupt void CLA1_7_ISR(void); // 11.7 - CLA1 Interrupt 7 -interrupt void CLA1_8_ISR(void); // 11.8 - CLA1 Interrupt 8 -interrupt void XINT3_ISR(void); // 12.1 - XINT3 Interrupt -interrupt void XINT4_ISR(void); // 12.2 - XINT4 Interrupt -interrupt void XINT5_ISR(void); // 12.3 - XINT5 Interrupt -interrupt void VCU_ISR(void); // 12.6 - VCU Interrupt -interrupt void FPU_OVERFLOW_ISR(void); // 12.7 - FPU Overflow Interrupt -interrupt void FPU_UNDERFLOW_ISR(void); // 12.8 - FPU Underflow Interrupt -interrupt void IPC0_ISR(void); // 1.13 - IPC Interrupt 0 -interrupt void IPC1_ISR(void); // 1.14 - IPC Interrupt 1 -interrupt void IPC2_ISR(void); // 1.15 - IPC Interrupt 2 -interrupt void IPC3_ISR(void); // 1.16 - IPC Interrupt 3 -interrupt void EPWM9_TZ_ISR(void); // 2.9 - ePWM9 Trip Zone Interrupt -interrupt void EPWM10_TZ_ISR(void); // 2.10 - ePWM10 Trip Zone Interrupt -interrupt void EPWM11_TZ_ISR(void); // 2.11 - ePWM11 Trip Zone Interrupt -interrupt void EPWM12_TZ_ISR(void); // 2.12 - ePWM12 Trip Zone Interrupt -interrupt void EPWM9_ISR(void); // 3.9 - ePWM9 Interrupt -interrupt void EPWM10_ISR(void); // 3.10 - ePWM10 Interrupt -interrupt void EPWM11_ISR(void); // 3.11 - ePWM11 Interrupt -interrupt void EPWM12_ISR(void); // 3.12 - ePWM12 Interrupt -interrupt void SD1_ISR(void); // 5.9 - SD1 Interrupt -interrupt void SD2_ISR(void); // 5.10 - SD2 Interrupt -interrupt void SPIC_RX_ISR(void); // 6.9 - SPIC Receive Interrupt -interrupt void SPIC_TX_ISR(void); // 6.10 - SPIC Transmit Interrupt -interrupt void UPPA_ISR(void); // 8.15 - uPPA Interrupt -interrupt void USBA_ISR(void); // 9.15 - USBA Interrupt -interrupt void ADCC_EVT_ISR(void); // 10.9 - ADCC Event Interrupt -interrupt void ADCC2_ISR(void); // 10.10 - ADCC Interrupt 2 -interrupt void ADCC3_ISR(void); // 10.11 - ADCC Interrupt 3 -interrupt void ADCC4_ISR(void); // 10.12 - ADCC Interrupt 4 -interrupt void ADCD_EVT_ISR(void); // 10.13 - ADCD Event Interrupt -interrupt void ADCD2_ISR(void); // 10.14 - ADCD Interrupt 2 -interrupt void ADCD3_ISR(void); // 10.15 - ADCD Interrupt 3 -interrupt void ADCD4_ISR(void); // 10.16 - ADCD Interrupt 4 -interrupt void EMIF_ERROR_ISR(void); // 12.9 - EMIF Error Interrupt -interrupt void RAM_CORRECTABLE_ERROR_ISR(void); // 12.10 - RAM Correctable - // Error Interrupt -interrupt void FLASH_CORRECTABLE_ERROR_ISR(void); // 12.11 - Flash Correctable - // Error Interrupt -interrupt void RAM_ACCESS_VIOLATION_ISR(void); // 12.12 - RAM Access - // Violation Interrupt -interrupt void SYS_PLL_SLIP_ISR(void); // 12.13 - System PLL Slip - // Interrupt -interrupt void AUX_PLL_SLIP_ISR(void); // 12.14 - Auxiliary PLL - // Slip Interrupt -interrupt void CLA_OVERFLOW_ISR(void); // 12.15 - CLA Overflow - // Interrupt -interrupt void CLA_UNDERFLOW_ISR(void); // 12.16 - CLA Underflow - // Interrupt - -// -// Catch-all for PIE Reserved Locations for testing purposes: -// -interrupt void PIE_RESERVED_ISR(void); // Reserved ISR -interrupt void EMPTY_ISR(void); // Only does a return -interrupt void NOTUSED_ISR(void); // Unused ISR -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // end of F2837xD_PIEVECT_H definition - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_sci_io.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_sci_io.h deleted file mode 100644 index 41ecacb9be..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_sci_io.h +++ /dev/null @@ -1,70 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_sci_io.h -// -// TITLE: Prototypes for SCI redirection to STDIO -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_SCI_IO_H -#define F2837xD_SCI_IO_H - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Function Prototypes -// -extern int SCI_open(const char * path, unsigned flags, int llv_fd); -extern int SCI_close(int dev_fd); -extern int SCI_read(int dev_fd, char * buf, unsigned count); -extern int SCI_write(int dev_fd, char * buf, unsigned count); -extern off_t SCI_lseek(int dev_fd, off_t offset, int origin); -extern int SCI_unlink(const char * path); -extern int SCI_rename(const char * old_name, const char * new_name); - -#ifdef __cplusplus -} -#endif /* extern "C" */ - - -#endif - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_sdfm_drivers.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_sdfm_drivers.h deleted file mode 100644 index 0cde1ad5ae..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_sdfm_drivers.h +++ /dev/null @@ -1,530 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_sdfm_drivers.h -// -// TITLE: Defines and Macros for the SDFM driver Controller -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_SDFM_DRIVERS_H -#define F2837xD_SDFM_DRIVERS_H - - -#ifdef __cplusplus -extern "C" { -#endif - -// -// Defines -// - -// -// This is used to select either SDFM module 1 & SDFM module 2 -// -#define SDFM1 1 //Can be used to select SDFM module 1 -#define SDFM2 2 //Can be used to select SDFM module 2 - -// -// Max OSR values of different modules -// -#define COMPARATOR_MAX_OSR 32 //Max OSR for comparator -#define DATA_FILTER_MAX_OSR 256 //Max OSR for Data filter - -// -// Different Input Control modes -// These values can be passed as argument to Sdfm_configureInputCtrl() -// -#define MODE_0 0 //Used to select Mode0 : - //Modulator clock rate = Modulator data rate -#define MODE_1 1 //Used to select MODE1 : - //Modulator clock rate = (Modulator data rate / 2) -#define MODE_2 2 //Used to select MODE2 : - //Manchester encoded data - //(Modulator clock is encoded into data) -#define MODE_3 3 //Used to select MODE3 : - //Modulator clock rate = (2 x Modulator data rate) - -// -// The following are values that can be passed to following functions -// -// (1) Sdfm_configureInputCtrl() -// (2) Sdfm_configureComparator() -// (3) Sdfm_configureData_filter() -// (4) Sdfm_configureInterrupt() -// -#define FILTER1 0x01 //Used to select filter1 for comparator or Data filter -#define FILTER2 0x02 //Used to select filter2 for comparator or Data filter -#define FILTER3 0x04 //Used to select filter3 for comparator or Data filter -#define FILTER4 0x08 //Used to select filter4 for comparator or Data filter - -// -// The following are values that can be passed to Sdfm_configureData_filter() -// -#define FILTER_DISABLE 0 //Used to disable filter -#define FILTER_ENABLE 1 //Used to enable filter - -// -// The following are values that can be passed to following functions -// -// (1) Sdfm_configureComparator() -// (2) Sdfm_configureData_filter() -// -#define SINCFAST 0x00 //Used to select Sincfast filter type for comparator - //or Data filter -#define SINC1 0x01 //Used to select Sinc1 filter type for comparator - //or Data filter -#define SINC2 0x02 //Used to select Sinc2 filter type for comparator - //or Data filter -#define SINC3 0x03 //Used to select Sinc3 filter type for comparator - //or Data filter - -// -// Enable / Disable High-level threshold interrupt for Comparator filter output -// These values can be passed as argument to Sdfm_configureInterrupt() -// -#define IEH_DISABLE 0 //Used to disable over value interrupt to CPU -#define IEH_ENABLE 1 //Used to enable over value interrupt to CPU - -// -// Enable / Disable Low-level threshold interrupt for Comparator filter output -// These values can be passed as argument to Sdfm_configureInterrupt() -// -#define IEL_DISABLE 0 //Used to disable under value interrupt to CPU -#define IEL_ENABLE 1 //Used to enable under value interrupt to CPU - -// -//Enable / Disable modulator failure interrupt -// These values can be passed as argument to Sdfm_configureInterrupt() -// -#define MFIE_DISABLE 0 //Used to disable modulator failure interrupt to CPU -#define MFIE_ENABLE 1 //Used to enable modulator failure interrupt to CPU - -// -// Enable / Disable Acknowledge flag -// These values can be passed as argument to Sdfm_configureInterrupt() -// -#define AE_DISABLE 0 //Used to disable new filter data acknowledge - //interrupt to CPU -#define AE_ENABLE 1 //Used to enable new filter data acknowledge - //interrupt to CPU - -// -// Sinc Filter Reset enable / disable for External Reset from PWM Compare -// output -// This following value can be passed to Sdfm_configureExternalreset() -// -#define FILTER_1_EXT_RESET_DISABLE 0 -#define FILTER_1_EXT_RESET_ENABLE 1 -#define FILTER_2_EXT_RESET_DISABLE 0 -#define FILTER_2_EXT_RESET_ENABLE 1 -#define FILTER_3_EXT_RESET_DISABLE 0 -#define FILTER_3_EXT_RESET_ENABLE 1 -#define FILTER_4_EXT_RESET_DISABLE 0 -#define FILTER_4_EXT_RESET_ENABLE 1 - -// -// Filter output data can be represented in 16 bit (or) 32 bit format -// This value can be passed to Sdfm_configureData_filter() -// -#define DATA_16_BIT 0 //Data stored in 16b 2's complement -#define DATA_32_BIT 1 //Data stored in 32b 2's complement - -// -// Macro to read the SDFM1 filter data in 16 bit format -// -#define SDFM1_READ_FILTER1_DATA_16BIT *(volatile Uint16 *)0x5E17 -#define SDFM1_READ_FILTER2_DATA_16BIT *(volatile Uint16 *)0x5E27 -#define SDFM1_READ_FILTER3_DATA_16BIT *(volatile Uint16 *)0x5E37 -#define SDFM1_READ_FILTER4_DATA_16BIT *(volatile Uint16 *)0x5E47 - -// -// Macro to read the SDFM1 filter data in 32 bit format -// -#define SDFM1_READ_FILTER1_DATA_32BIT *(volatile Uint32 *)0x5E16 -#define SDFM1_READ_FILTER2_DATA_32BIT *(volatile Uint32 *)0x5E26 -#define SDFM1_READ_FILTER3_DATA_32BIT *(volatile Uint32 *)0x5E36 -#define SDFM1_READ_FILTER4_DATA_32BIT *(volatile Uint32 *)0x5E46 - -// -// Macro to read the SDFM2 filter data in 16 bit format -// -#define SDFM2_READ_FILTER1_DATA_16BIT *(volatile Uint16 *)0x5E97 -#define SDFM2_READ_FILTER2_DATA_16BIT *(volatile Uint16 *)0x5EA7 -#define SDFM2_READ_FILTER3_DATA_16BIT *(volatile Uint16 *)0x5EB7 -#define SDFM2_READ_FILTER4_DATA_16BIT *(volatile Uint16 *)0x5EC7 - -// -// Macro to read the SDFM2 filter data in 32 bit format -// -#define SDFM2_READ_FILTER1_DATA_32BIT *(volatile Uint16 *)0x5E96 -#define SDFM2_READ_FILTER2_DATA_32BIT *(volatile Uint16 *)0x5EA6 -#define SDFM2_READ_FILTER3_DATA_32BIT *(volatile Uint16 *)0x5EB6 -#define SDFM2_READ_FILTER4_DATA_32BIT *(volatile Uint16 *)0x5EC6 - -// -// The following are defines for different OSR values -// -#define OSR_1 0 -#define OSR_2 1 -#define OSR_3 2 -#define OSR_4 3 -#define OSR_5 4 -#define OSR_6 5 -#define OSR_7 6 -#define OSR_8 7 -#define OSR_9 8 -#define OSR_10 9 -#define OSR_11 10 -#define OSR_12 11 -#define OSR_13 12 -#define OSR_14 13 -#define OSR_15 14 -#define OSR_16 15 -#define OSR_17 16 -#define OSR_18 17 -#define OSR_19 18 -#define OSR_20 19 -#define OSR_21 20 -#define OSR_22 21 -#define OSR_23 22 -#define OSR_24 23 -#define OSR_25 24 -#define OSR_26 25 -#define OSR_27 26 -#define OSR_28 27 -#define OSR_29 28 -#define OSR_30 29 -#define OSR_31 30 -#define OSR_32 31 -#define OSR_33 32 -#define OSR_34 33 -#define OSR_35 34 -#define OSR_36 35 -#define OSR_37 36 -#define OSR_38 37 -#define OSR_39 38 -#define OSR_40 39 -#define OSR_41 40 -#define OSR_42 41 -#define OSR_43 42 -#define OSR_44 43 -#define OSR_45 44 -#define OSR_46 45 -#define OSR_47 46 -#define OSR_48 47 -#define OSR_49 48 -#define OSR_50 49 -#define OSR_51 50 -#define OSR_52 51 -#define OSR_53 52 -#define OSR_54 53 -#define OSR_55 54 -#define OSR_56 55 -#define OSR_57 56 -#define OSR_58 57 -#define OSR_59 58 -#define OSR_60 59 -#define OSR_61 60 -#define OSR_62 61 -#define OSR_63 62 -#define OSR_64 63 -#define OSR_65 64 -#define OSR_66 65 -#define OSR_67 66 -#define OSR_68 67 -#define OSR_69 68 -#define OSR_70 69 -#define OSR_71 70 -#define OSR_72 71 -#define OSR_73 72 -#define OSR_74 73 -#define OSR_75 74 -#define OSR_76 75 -#define OSR_77 76 -#define OSR_78 77 -#define OSR_79 78 -#define OSR_80 79 -#define OSR_81 80 -#define OSR_82 81 -#define OSR_83 82 -#define OSR_84 83 -#define OSR_85 84 -#define OSR_86 85 -#define OSR_87 86 -#define OSR_88 87 -#define OSR_89 88 -#define OSR_90 89 -#define OSR_91 90 -#define OSR_92 91 -#define OSR_93 92 -#define OSR_94 93 -#define OSR_95 94 -#define OSR_96 95 -#define OSR_97 96 -#define OSR_98 97 -#define OSR_99 98 -#define OSR_100 99 -#define OSR_101 100 -#define OSR_102 101 -#define OSR_103 102 -#define OSR_104 103 -#define OSR_105 104 -#define OSR_106 105 -#define OSR_107 106 -#define OSR_108 107 -#define OSR_109 108 -#define OSR_110 109 -#define OSR_111 110 -#define OSR_112 111 -#define OSR_113 112 -#define OSR_114 113 -#define OSR_115 114 -#define OSR_116 115 -#define OSR_117 116 -#define OSR_118 117 -#define OSR_119 118 -#define OSR_120 119 -#define OSR_121 120 -#define OSR_122 121 -#define OSR_123 122 -#define OSR_124 123 -#define OSR_125 124 -#define OSR_126 125 -#define OSR_127 126 -#define OSR_128 127 -#define OSR_129 128 -#define OSR_130 129 -#define OSR_131 130 -#define OSR_132 131 -#define OSR_133 132 -#define OSR_134 133 -#define OSR_135 134 -#define OSR_136 135 -#define OSR_137 136 -#define OSR_138 137 -#define OSR_139 138 -#define OSR_140 139 -#define OSR_141 140 -#define OSR_142 141 -#define OSR_143 142 -#define OSR_144 143 -#define OSR_145 144 -#define OSR_146 145 -#define OSR_147 146 -#define OSR_148 147 -#define OSR_149 148 -#define OSR_150 149 -#define OSR_151 150 -#define OSR_152 151 -#define OSR_153 152 -#define OSR_154 153 -#define OSR_155 154 -#define OSR_156 155 -#define OSR_157 156 -#define OSR_158 157 -#define OSR_159 158 -#define OSR_160 159 -#define OSR_161 160 -#define OSR_162 161 -#define OSR_163 162 -#define OSR_164 163 -#define OSR_165 164 -#define OSR_166 165 -#define OSR_167 166 -#define OSR_168 167 -#define OSR_169 168 -#define OSR_170 169 -#define OSR_171 170 -#define OSR_172 171 -#define OSR_173 172 -#define OSR_174 173 -#define OSR_175 174 -#define OSR_176 175 -#define OSR_177 176 -#define OSR_178 177 -#define OSR_179 178 -#define OSR_180 179 -#define OSR_181 180 -#define OSR_182 181 -#define OSR_183 182 -#define OSR_184 183 -#define OSR_185 184 -#define OSR_186 185 -#define OSR_187 186 -#define OSR_188 187 -#define OSR_189 188 -#define OSR_190 189 -#define OSR_191 190 -#define OSR_192 191 -#define OSR_193 192 -#define OSR_194 193 -#define OSR_195 194 -#define OSR_196 195 -#define OSR_197 196 -#define OSR_198 197 -#define OSR_199 198 -#define OSR_200 199 -#define OSR_201 200 -#define OSR_202 201 -#define OSR_203 202 -#define OSR_204 203 -#define OSR_205 204 -#define OSR_206 205 -#define OSR_207 206 -#define OSR_208 207 -#define OSR_209 208 -#define OSR_210 209 -#define OSR_211 210 -#define OSR_212 211 -#define OSR_213 212 -#define OSR_214 213 -#define OSR_215 214 -#define OSR_216 215 -#define OSR_217 216 -#define OSR_218 217 -#define OSR_219 218 -#define OSR_220 219 -#define OSR_221 220 -#define OSR_222 221 -#define OSR_223 222 -#define OSR_224 223 -#define OSR_225 224 -#define OSR_226 225 -#define OSR_227 226 -#define OSR_228 227 -#define OSR_229 228 -#define OSR_230 229 -#define OSR_231 230 -#define OSR_232 231 -#define OSR_233 232 -#define OSR_234 233 -#define OSR_235 234 -#define OSR_236 235 -#define OSR_237 236 -#define OSR_238 237 -#define OSR_239 238 -#define OSR_240 239 -#define OSR_241 240 -#define OSR_242 241 -#define OSR_243 242 -#define OSR_244 243 -#define OSR_245 244 -#define OSR_246 245 -#define OSR_247 246 -#define OSR_248 247 -#define OSR_249 248 -#define OSR_250 249 -#define OSR_251 250 -#define OSR_252 251 -#define OSR_253 252 -#define OSR_254 253 -#define OSR_255 254 -#define OSR_256 255 - -// -// The following are defines for different OSR values -// -#define SHIFT_0_BITS 0 -#define SHIFT_1_BITS 1 -#define SHIFT_2_BITS 2 -#define SHIFT_3_BITS 3 -#define SHIFT_4_BITS 4 -#define SHIFT_5_BITS 5 -#define SHIFT_6_BITS 6 -#define SHIFT_7_BITS 7 -#define SHIFT_8_BITS 8 -#define SHIFT_9_BITS 9 -#define SHIFT_10_BITS 10 -#define SHIFT_11_BITS 11 -#define SHIFT_12_BITS 12 -#define SHIFT_13_BITS 13 -#define SHIFT_14_BITS 14 -#define SHIFT_15_BITS 15 -#define SHIFT_16_BITS 16 -#define SHIFT_17_BITS 17 -#define SHIFT_18_BITS 18 -#define SHIFT_19_BITS 19 -#define SHIFT_20_BITS 20 -#define SHIFT_21_BITS 21 -#define SHIFT_22_BITS 22 -#define SHIFT_23_BITS 23 -#define SHIFT_24_BITS 24 -#define SHIFT_25_BITS 25 -#define SHIFT_26_BITS 26 -#define SHIFT_27_BITS 27 -#define SHIFT_28_BITS 28 -#define SHIFT_29_BITS 29 -#define SHIFT_30_BITS 30 -#define SHIFT_31_BITS 31 - -// -// Function prototypes -// -extern void Sdfm_configureInputCtrl(Uint16 SDFM_number, - Uint16 Filter_number, Uint16 mode); -extern void Sdfm_configureComparator(Uint16 SDFM_number, - Uint16 Filter_number, Uint16 Filter_type, - Uint16 OSR, Uint16 HLT, Uint16 LLT); -extern void Sdfm_configureData_filter(Uint16 sdfmNumber, Uint16 filterNumber, - Uint16 Filter_switch, Uint16 filterType, - Uint16 OSR, Uint16 DR_switch, - Uint16 shift_bits); -extern void Sdfm_enableMFE(Uint16 SDFM_number); -extern void Sdfm_disableMFE(Uint16 SDFM_number); -extern void Sdfm_configureInterrupt(Uint16 SDFM_number, Uint16 Filter_number, - Uint16 IEH_Switch, Uint16 IEL_Switch, - Uint16 MFIE_Switch, Uint16 AE_Switch); -extern void Sdfm_enableMIE(Uint16 SDFM_number); -extern void Sdfm_disableMIE(Uint16 SDFM_number); -extern void Sdfm_configureExternalreset(Uint16 SDFM_number, - Uint16 filter1_Config_ext_reset, - Uint16 filter2_Config_ext_reset, - Uint16 filter3_Config_ext_reset, - Uint16 filter4_Config_ext_reset); -extern Uint32 Sdfm_readFlagRegister(Uint16 SDFM_number); -extern void Sdfm_clearFlagRegister(Uint16 sdfmNumber, - Uint32 sdfmReadFlagRegister); - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F2837xD_SDFM_DRIVERS_H - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_struct.h b/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_struct.h deleted file mode 100644 index bd307dd782..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F2837xD_struct.h +++ /dev/null @@ -1,82 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_sdfm_strut.h -// -// TITLE: contains structures used for the SDFM driver. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_SDFM_STRUCT_H -#define F2837xD_SDFM_STRUCT_H - -#ifdef __cplusplus -extern "C" { -#endif - -#define MAX_CPUTIMER 4 -#define MAX_ECAP 7 -#define MAX_EPWM 13 -#define MAX_EQEP 4 -#define MAX_I2C 2 -#define MAX_MCBSP 2 -#define MAX_SCI 2 -#define MAX_SPI 4 -#define MAX_ADC 5 -#define MAX_SDFM 3 -#define MAX_TRIPSEL 15 - -extern volatile Uint16 *TRIP_SEL[MAX_TRIPSEL]; -extern volatile struct ADC_REGS *ADC[MAX_ADC]; -extern volatile struct CPUTIMER_REGS *CPUTIMER[MAX_CPUTIMER]; -extern volatile struct ECAP_REGS *ECAP[MAX_ECAP]; -extern volatile struct EPWM_REGS *EPWM[MAX_EPWM]; -extern volatile struct EQEP_REGS *EQEP[MAX_EQEP]; -extern volatile struct I2C_REGS *I2C[MAX_I2C]; -extern volatile struct McBSP_REGS *MCBSP[MAX_MCBSP]; -extern volatile struct SCI_REGS *SCI[MAX_SCI]; -extern volatile struct SPI_REGS *SPI[MAX_SPI]; -extern volatile struct SDFM_REGS *SDFM[MAX_SDFM]; - -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif // - end of F2837xD_SDFM_STRUCT_H - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/F28x_Project.h b/bsp/c28x/libraries/tms320f28379d/common/include/F28x_Project.h deleted file mode 100644 index ffdaa6e98c..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/F28x_Project.h +++ /dev/null @@ -1,58 +0,0 @@ -//########################################################################### -// -// FILE: F28x_Project.h -// -// TITLE: F28x Project Headerfile and Examples Include File -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F28X_PROJECT_H -#define F28X_PROJECT_H - -// -// Included Files -// -#include "F2837xD_Cla_typedefs.h" // F2837xD CLA Type definitions -#include "F2837xD_device.h" // F2837xD Headerfile Include File -#include "F2837xD_Examples.h" // F2837xD Examples Include File - - -#endif // end of F28X_PROJECT_H definition - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/device.h b/bsp/c28x/libraries/tms320f28379d/common/include/device.h deleted file mode 100644 index 9a8e0ad33e..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/device.h +++ /dev/null @@ -1,199 +0,0 @@ -//############################################################################# -// -// FILE: device.h -// -// TITLE: Device setup for examples. -// -//############################################################################# -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -// -// Included Files -// -#include "driverlib.h" - -#if (!defined(CPU1) && !defined(CPU2)) -#error "You must define CPU1 or CPU2 in your project properties. Otherwise, \ -the offsets in your header files will be inaccurate." -#endif - -#if (defined(CPU1) && defined(CPU2)) -#error "You have defined both CPU1 and CPU2 in your project properties. Only \ -a single CPU should be defined." -#endif - -//***************************************************************************** -// -// Defines for pin numbers and other GPIO configuration -// -//***************************************************************************** -// -// LEDs -// -#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD2 -#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD3 -#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD2 -#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD3 - -// -// SCI for USB-to-UART adapter on FTDI chip -// -#define DEVICE_GPIO_PIN_SCIRXDA 28U // GPIO number for SCI RX -#define DEVICE_GPIO_PIN_SCITXDA 29U // GPIO number for SCI TX -#define DEVICE_GPIO_CFG_SCIRXDA GPIO_28_SCIRXDA // "pinConfig" for SCI RX -#define DEVICE_GPIO_CFG_SCITXDA GPIO_29_SCITXDA // "pinConfig" for SCI TX - -// -// CANA -// -#define DEVICE_GPIO_PIN_CANTXA 31U // GPIO number for CANTXA -#define DEVICE_GPIO_PIN_CANRXA 30U // GPIO number for CANRXA - -// -// CAN External Loopback -// -#define DEVICE_GPIO_CFG_CANRXA GPIO_30_CANRXA // "pinConfig" for CANA RX -#define DEVICE_GPIO_CFG_CANTXA GPIO_31_CANTXA // "pinConfig" for CANA TX -#define DEVICE_GPIO_CFG_CANRXB GPIO_10_CANRXB // "pinConfig" for CANB RX -#define DEVICE_GPIO_CFG_CANTXB GPIO_8_CANTXB // "pinConfig" for CANB TX - -//***************************************************************************** -// -// Defines related to clock configuration -// -//***************************************************************************** -// -// Launchpad Configuration -// -#ifdef _LAUNCHXL_F28379D - -// -// 10MHz XTAL on LaunchPad. For use with SysCtl_getClock(). -// -#define DEVICE_OSCSRC_FREQ 10000000U - -// -// Define to pass to SysCtl_setClock(). Will configure the clock as follows: -// PLLSYSCLK = 10MHz (XTAL_OSC) * 40 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) -// -#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(40) | \ - SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ - SYSCTL_PLL_ENABLE) - -// -// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the -// code below if a different clock configuration is used! -// -#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 40 * 1) / 2) - -// -// ControlCARD Configuration -// -#else - -// -// 20MHz XTAL on controlCARD. For use with SysCtl_getClock(). -// -#define DEVICE_OSCSRC_FREQ 20000000U - -// -// Define to pass to SysCtl_setClock(). Will configure the clock as follows: -// PLLSYSCLK = 20MHz (XTAL_OSC) * 20 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) -// -#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(20) | \ - SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ - SYSCTL_PLL_ENABLE) - -// -// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the -// code below if a different clock configuration is used! -// -#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 20 * 1) / 2) - -#endif - -// -// 50MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default -// low speed peripheral clock divider of 4. Update the code below if a -// different LSPCLK divider is used! -// -#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4) - -//***************************************************************************** -// -// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro -// will convert the desired delay in microseconds to the count value expected -// by the function. \b x is the number of microseconds to delay. -// -//***************************************************************************** -#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \ - (long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L) - -//***************************************************************************** -// -// Defines, Globals, and Header Includes related to Flash Support -// -//***************************************************************************** -#ifdef _FLASH -#include - -extern uint16_t RamfuncsLoadStart; -extern uint16_t RamfuncsLoadEnd; -extern uint16_t RamfuncsLoadSize; -extern uint16_t RamfuncsRunStart; -extern uint16_t RamfuncsRunEnd; -extern uint16_t RamfuncsRunSize; - -#define DEVICE_FLASH_WAITSTATES 3 - -#endif - -//***************************************************************************** -// -// Function Prototypes -// -//***************************************************************************** -extern void Device_init(void); -extern void Device_enableAllPeripherals(void); -extern void Device_initGPIO(void); -extern void Device_enableUnbondedGPIOPullupsFor176Pin(void); -extern void Device_enableUnbondedGPIOPullupsFor100Pin(void); -extern void Device_enableUnbondedGPIOPullups(void); -extern void __error__(char *filename, uint32_t line); - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/driverlib.h b/bsp/c28x/libraries/tms320f28379d/common/include/driverlib.h deleted file mode 100644 index 0dd941033f..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/driverlib.h +++ /dev/null @@ -1,82 +0,0 @@ -//############################################################################# -// -// FILE: driverlib.h -// -// TITLE: C28x Driverlib Header File -// -//############################################################################# -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# -#ifndef DRIVERLIB_H -#define DRIVERLIB_H - -#include "inc/hw_memmap.h" - -#include "adc.h" -#include "asysctl.h" -#include "can.h" -#include "cla.h" -#include "cmpss.h" -#include "cpu.h" -#include "cputimer.h" -#include "dac.h" -#include "dcsm.h" -#include "debug.h" -#include "dma.h" -#include "ecap.h" -#include "emif.h" -#include "epwm.h" -#include "eqep.h" -#include "flash.h" -#include "gpio.h" -#include "hrpwm.h" -#include "i2c.h" -#include "interrupt.h" -#include "mcbsp.h" -#include "memcfg.h" -#include "pin_map.h" -#include "sci.h" -#include "sdfm.h" -#include "spi.h" -#include "sysctl.h" -#include "upp.h" -#include "version.h" -#include "xbar.h" - -#endif // end of DRIVERLIB_H definition - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/stdint.h b/bsp/c28x/libraries/tms320f28379d/common/include/stdint.h deleted file mode 100644 index 479234292a..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/stdint.h +++ /dev/null @@ -1,522 +0,0 @@ -/*****************************************************************************/ -/* STDINT.H */ -/* */ -/* Copyright (c) 2002 Texas Instruments Incorporated */ -/* http://www.ti.com/ */ -/* */ -/* Redistribution and use in source and binary forms, with or without */ -/* modification, are permitted provided that the following conditions */ -/* are met: */ -/* */ -/* Redistributions of source code must retain the above copyright */ -/* notice, this list of conditions and the following disclaimer. */ -/* */ -/* Redistributions in binary form must reproduce the above copyright */ -/* notice, this list of conditions and the following disclaimer in */ -/* the documentation and/or other materials provided with the */ -/* distribution. */ -/* */ -/* Neither the name of Texas Instruments Incorporated nor the names */ -/* of its contributors may be used to endorse or promote products */ -/* derived from this software without specific prior written */ -/* permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ -/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ -/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ -/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ -/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ -/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ -/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ -/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ -/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ -/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ -/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* */ -/*****************************************************************************/ -#ifndef _STDINT_H_ -#define _STDINT_H_ - -#if __has_include() -#include -#else -/* 7.18.1.1 Exact-width integer types */ - -#if defined(__MSP430__) || defined(__TMS320C55X_PLUS_BYTE__) - typedef signed char int8_t; - typedef unsigned char uint8_t; - typedef int int16_t; - typedef unsigned int uint16_t; - typedef long int32_t; - typedef unsigned long uint32_t; -#elif defined(_TMS320C5XX) || defined(__TMS320C55X__) - typedef int int16_t; - typedef unsigned int uint16_t; - typedef long int32_t; - typedef unsigned long uint32_t; -#elif defined(_TMS320C6X) || defined(__ARM_ARCH) || defined(__ARP32__) || \ - defined(__PRU__) || defined(__FROZEN__) - typedef signed char int8_t; - typedef unsigned char uint8_t; - typedef short int16_t; - typedef unsigned short uint16_t; - typedef int int32_t; - typedef unsigned int uint32_t; -#elif defined (__TMS320C2000__) -#if defined(__TMS320C28XX_CLA__) - typedef short int16_t; - typedef unsigned short uint16_t; - typedef int int32_t; - typedef unsigned int uint32_t; -#else - typedef char int8_t; - typedef unsigned char uint8_t; - typedef int int16_t; - typedef unsigned int uint16_t; - typedef long int32_t; - typedef unsigned long uint32_t; -#endif -#endif - -#if defined(__TMS320C55X__) - typedef long long int40_t; - typedef unsigned long long uint40_t; -#elif defined(_TMS320C6X) && !defined(__C6X_MIGRATION__) - typedef __int40_t int40_t; - typedef unsigned __int40_t uint40_t; -#endif - -#if defined(__ARM_ARCH) || defined(_TMS320C6X) || defined(__ARP32__) || \ - defined(__MSP430__) || defined(__PRU__) || defined(__FROZEN__) - typedef long long int64_t; - typedef unsigned long long uint64_t; -#elif defined(__TMS320C2000__) -#if defined(__TMS320C28X__) || \ - (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) - typedef long long int64_t; - typedef unsigned long long uint64_t; -#endif -#endif - -/* 7.18.1.2 Minimum-width integer types */ - -#if defined(_TMS320C6X) || defined(__ARM_ARCH) || defined(__MSP430__) || \ - defined(__TMS320C55X_PLUS_BYTE__) || defined(__ARP32__) || \ - defined(__PRU__) || defined(__FROZEN__) - typedef int8_t int_least8_t; - typedef uint8_t uint_least8_t; -#elif defined(__TMS320C2000__) || defined(_TMS320C5XX) || defined(__TMS320C55X__) - typedef int16_t int_least8_t; - typedef uint16_t uint_least8_t; -#endif - - typedef int16_t int_least16_t; - typedef uint16_t uint_least16_t; - typedef int32_t int_least32_t; - typedef uint32_t uint_least32_t; - -#if defined(__TMS320C55X__) || \ - (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) - typedef int40_t int_least40_t; - typedef uint40_t uint_least40_t; -#endif - -#if defined(__ARM_ARCH) || defined(_TMS320C6X) || defined(__FROZEN__) || \ - defined(__ARP32__) || defined(__MSP430__) || defined(__PRU__) - typedef int64_t int_least64_t; - typedef uint64_t uint_least64_t; -#elif defined(__TMS320C2000__) -#if defined(__TMS320C28X__) || \ - (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) - typedef int64_t int_least64_t; - typedef uint64_t uint_least64_t; -#else -/* sorry, [u]int_least64_t not implemented for C27X, CLA */ -#endif -#elif defined(_TMS320C5XX) || defined(__TMS320C55X__) -/* sorry, [u]int_least64_t not implemented for C54x, C55x */ -#endif - -/* 7.18.1.3 Fastest minimum-width integer types */ - -#if defined(_TMS320C5XX) || defined(__TMS320C55X__) || defined(__MSP430__) - typedef int16_t int_fast8_t; - typedef uint16_t uint_fast8_t; - typedef int16_t int_fast16_t; - typedef uint16_t uint_fast16_t; -#elif defined(_TMS320C6X) || defined(__ARM_ARCH) || defined(__ARP32__) || \ - defined(__PRU__) || defined(__FROZEN__) - typedef int32_t int_fast8_t; - typedef uint32_t uint_fast8_t; - typedef int32_t int_fast16_t; - typedef uint32_t uint_fast16_t; -#elif defined (__TMS320C2000__) -#if defined(__TMS320C28XX_CLA__) - typedef int32_t int_fast8_t; - typedef uint32_t uint_fast8_t; - typedef int32_t int_fast16_t; - typedef uint32_t uint_fast16_t; -#else - typedef int16_t int_fast8_t; - typedef uint16_t uint_fast8_t; - typedef int16_t int_fast16_t; - typedef uint16_t uint_fast16_t; -#endif -#endif - - typedef int32_t int_fast32_t; - typedef uint32_t uint_fast32_t; - -#if defined(__TMS320C55X__) || \ - (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) - typedef int40_t int_fast40_t; - typedef uint40_t uint_fast40_t; -#endif - -#if defined(__ARM_ARCH) || defined(_TMS320C6X) || defined(__FROZEN__) || \ - defined(__ARP32__) || defined(__MSP430__) || defined(__PRU__) - typedef int64_t int_fast64_t; - typedef uint64_t uint_fast64_t; -#elif defined(__TMS320C2000__) -#if defined(__TMS320C28X__) || \ - (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) - typedef int64_t int_fast64_t; - typedef uint64_t uint_fast64_t; -#else -/* sorry, [u]int_fast64_t not implemented for C27X, CLA */ -#endif -#elif defined(_TMS320C5XX) || defined(__TMS320C55X__) -/* sorry, [u]int_fast64_t not implemented for C54x, C55x */ -#endif - -/* 7.18.1.4 Integer types capable of holding object pointers */ -#if defined(_TMS320C5XX) || defined(__TMS320C55X__) || \ - (defined(__MSP430__) && defined(__LARGE_CODE_MODEL__)) || \ - defined(__FROZEN__) - typedef long intptr_t; - typedef unsigned long uintptr_t; -#elif defined(_TMS320C6X) || defined(__ARM_ARCH) || defined(__MSP430__) || \ - defined(__ARP32__) || defined(__PRU__) - typedef int intptr_t; - typedef unsigned int uintptr_t; -#elif defined(__TMS320C2000__) -#if defined(__TMS320C28XX_CLA__) - typedef short intptr_t; - typedef unsigned short uintptr_t; -#else - typedef long intptr_t; - typedef unsigned long uintptr_t; -#endif -#endif - -/* 7.18.1.5 Greatest-width integer types */ -#if defined(__TMS320C55X__) || defined(__ARM_ARCH) || defined(_TMS320C6X) || \ - defined(__ARP32__) || defined(__MSP430__) || defined(__PRU__) || \ - defined(__FROZEN__) - typedef long long intmax_t; - typedef unsigned long long uintmax_t; -#elif defined(_TMS320C5XX) - typedef long intmax_t; - typedef unsigned long uintmax_t; -#elif defined(__TMS320C2000__) -#if defined(__TMS320C28X__) || \ - (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) - typedef long long intmax_t; - typedef unsigned long long uintmax_t; -#else /* C27X or CLA */ - typedef long intmax_t; - typedef unsigned long uintmax_t; -#endif -#endif - -/* - According to footnotes in the 1999 C standard, "C++ implementations - should define these macros only when __STDC_LIMIT_MACROS is defined - before is included." -*/ -#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) - -/* 7.18.2 Limits of specified width integer types */ - -#if defined(_TMS320C6X) || defined(__ARM_ARCH) || defined(__MSP430__) || \ - defined(__TMS320C55X_PLUS_BYTE__) || defined(__ARP32__) || \ - defined(__PRU__) || defined(__FROZEN__) - #define INT8_MAX 0x7f - #define INT8_MIN (-INT8_MAX-1) - #define UINT8_MAX 0xff -#endif - - #define INT16_MAX 0x7fff - #define INT16_MIN (-INT16_MAX-1) - #define UINT16_MAX 0xffff - - #define INT32_MAX 0x7fffffff - #define INT32_MIN (-INT32_MAX-1) - #define UINT32_MAX 0xffffffff - -#if defined(__TMS320C55X__) || \ - (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) - #define INT40_MAX 0x7fffffffff - #define INT40_MIN (-INT40_MAX-1) - #define UINT40_MAX 0xffffffffff -#endif - -#if defined(__ARM_ARCH) || defined(_TMS320C6X) || defined(__FROZEN__) || \ - defined(__ARP32__) || defined(__MSP430__) || defined(__PRU__) - #define INT64_MAX 0x7fffffffffffffff - #define INT64_MIN (-INT64_MAX-1) - #define UINT64_MAX 0xffffffffffffffff -#elif defined(__TMS320C2000__) -#if defined(__TMS320C28X__) || \ - (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) - #define INT64_MAX 0x7fffffffffffffff - #define INT64_MIN (-INT64_MAX-1) - #define UINT64_MAX 0xffffffffffffffff -#endif -#endif - -#if defined(_TMS320C6X) || defined(__ARM_ARCH) || defined(__MSP430__) || \ - defined(__TMS320C55X_PLUS_BYTE__) || defined(__ARP32__) || \ - defined(__PRU__) || defined(__FROZEN__) - #define INT_LEAST8_MAX (INT8_MAX) - #define INT_LEAST8_MIN (INT8_MIN) - #define UINT_LEAST8_MAX (UINT8_MAX) -#elif defined(__TMS320C2000__) || defined(_TMS320C5XX) || defined(__TMS320C55X__) - #define INT_LEAST8_MAX (INT16_MAX) - #define INT_LEAST8_MIN (INT16_MIN) - #define UINT_LEAST8_MAX (UINT16_MAX) -#endif - - #define INT_LEAST16_MAX (INT16_MAX) - #define INT_LEAST16_MIN (INT16_MIN) - #define UINT_LEAST16_MAX (UINT16_MAX) - #define INT_LEAST32_MAX (INT32_MAX) - #define INT_LEAST32_MIN (INT32_MIN) - #define UINT_LEAST32_MAX (UINT32_MAX) - -#if defined(__TMS320C55X__) || \ - (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) - #define INT_LEAST40_MAX (INT40_MAX) - #define INT_LEAST40_MIN (INT40_MIN) - #define UINT_LEAST40_MAX (UINT40_MAX) -#endif - -#if defined(__ARM_ARCH) || defined(_TMS320C6X) || defined(__FROZEN__) || \ - defined(__ARP32__) || defined(__MSP430__) || defined(__PRU__) - #define INT_LEAST64_MAX (INT64_MAX) - #define INT_LEAST64_MIN (INT64_MIN) - #define UINT_LEAST64_MAX (UINT64_MAX) -#elif defined(__TMS320C2000__) -#if defined(__TMS320C28X__) || \ - (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) - #define INT_LEAST64_MAX (INT64_MAX) - #define INT_LEAST64_MIN (INT64_MIN) - #define UINT_LEAST64_MAX (UINT64_MAX) -#endif -#endif - -#if defined(_TMS320C5XX) || defined(__TMS320C55X__) - #define INT_FAST8_MAX (INT16_MAX) - #define INT_FAST8_MIN (INT16_MIN) - #define UINT_FAST8_MAX (UINT16_MAX) - #define INT_FAST16_MAX (INT16_MAX) - #define INT_FAST16_MIN (INT16_MIN) - #define UINT_FAST16_MAX (UINT16_MAX) -#elif defined(_TMS320C6X) || defined(__ARM_ARCH) || defined(__ARP32__) || \ - defined(__PRU__) || defined(__FROZEN__) - #define INT_FAST8_MAX (INT32_MAX) - #define INT_FAST8_MIN (INT32_MIN) - #define UINT_FAST8_MAX (UINT32_MAX) - #define INT_FAST16_MAX (INT32_MAX) - #define INT_FAST16_MIN (INT32_MIN) - #define UINT_FAST16_MAX (UINT32_MAX) -#elif defined(__MSP430__) - #define INT_FAST8_MAX (INT16_MAX) - #define INT_FAST8_MIN (INT16_MIN) - #define UINT_FAST8_MAX (UINT16_MAX) - #define INT_FAST16_MAX (INT16_MAX) - #define INT_FAST16_MIN (INT16_MIN) - #define UINT_FAST16_MAX (UINT16_MAX) -#elif defined (__TMS320C2000__) -#if defined(__TMS320C28XX_CLA__) - #define INT_FAST8_MAX (INT32_MAX) - #define INT_FAST8_MIN (INT32_MIN) - #define UINT_FAST8_MAX (UINT32_MAX) - #define INT_FAST16_MAX (INT32_MAX) - #define INT_FAST16_MIN (INT32_MIN) - #define UINT_FAST16_MAX (UINT32_MAX) -#else - #define INT_FAST8_MAX (INT16_MAX) - #define INT_FAST8_MIN (INT16_MIN) - #define UINT_FAST8_MAX (UINT16_MAX) - #define INT_FAST16_MAX (INT16_MAX) - #define INT_FAST16_MIN (INT16_MIN) - #define UINT_FAST16_MAX (UINT16_MAX) -#endif -#endif - - #define INT_FAST32_MAX (INT32_MAX) - #define INT_FAST32_MIN (INT32_MIN) - #define UINT_FAST32_MAX (UINT32_MAX) - -#if defined(__TMS320C55X__) || \ - (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) - #define INT_FAST40_MAX (INT40_MAX) - #define INT_FAST40_MIN (INT40_MIN) - #define UINT_FAST40_MAX (UINT40_MAX) -#endif - -#if defined(__ARM_ARCH) || defined(_TMS320C6X) || defined(__FROZEN__) || \ - defined(__ARP32__) || defined(__MSP430__) || defined(__PRU__) - #define INT_FAST64_MAX (INT64_MAX) - #define INT_FAST64_MIN (INT64_MIN) - #define UINT_FAST64_MAX (UINT64_MAX) -#elif defined(__TMS320C2000__) -#if defined(__TMS320C28X__) || \ - (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) - #define INT_FAST64_MAX (INT64_MAX) - #define INT_FAST64_MIN (INT64_MIN) - #define UINT_FAST64_MAX (UINT64_MAX) -#endif -#endif - -#if defined(__MSP430__) && !defined(__LARGE_CODE_MODEL__) - #define INTPTR_MAX (INT16_MAX) - #define INTPTR_MIN (INT16_MIN) - #define UINTPTR_MAX (UINT16_MAX) -#elif defined(__FROZEN__) - #define INTPTR_MAX (INT64_MAX) - #define INTPTR_MIN (INT64_MIN) - #define UINTPTR_MAX (UINT64_MAX) -#else - #define INTPTR_MAX (INT32_MAX) - #define INTPTR_MIN (INT32_MIN) - #define UINTPTR_MAX (UINT32_MAX) -#endif - -#if defined(__ARM_ARCH) || defined(_TMS320C6X) || defined(__FROZEN__) || \ - defined(__ARP32__) || defined(__MSP430__) || defined(__PRU__) - #define INTMAX_MIN (INT64_MIN) - #define INTMAX_MAX (INT64_MAX) - #define UINTMAX_MAX (UINT64_MAX) -#elif defined(__TMS320C55X__) - #define INTMAX_MIN (INT40_MIN) - #define INTMAX_MAX (INT40_MAX) - #define UINTMAX_MAX (UINT40_MAX) -#elif defined(_TMS320C5XX) - #define INTMAX_MIN (INT32_MIN) - #define INTMAX_MAX (INT32_MAX) - #define UINTMAX_MAX (UINT32_MAX) -#elif defined(__TMS320C2000__) -#if defined(__TMS320C28X__) || \ - (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) - #define INTMAX_MIN (INT64_MIN) - #define INTMAX_MAX (INT64_MAX) - #define UINTMAX_MAX (UINT64_MAX) -#else - #define INTMAX_MIN (INT32_MIN) - #define INTMAX_MAX (INT32_MAX) - #define UINTMAX_MAX (UINT32_MAX) -#endif -#endif - -/* 7.18.3 Limits of other integer types */ - -#if defined(_TMS320C5XX) || defined(__TMS320C55X__) || \ - (defined(__MSP430__) && !defined(__LONG_PTRDIFF_T__)) - #define PTRDIFF_MAX (INT16_MAX) - #define PTRDIFF_MIN (INT16_MIN) -#elif defined(__TMS320C2000__) || defined(__MSP430__) || \ - (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \ - defined(__ARM_ARCH) || defined(__ARP32__) || defined(__PRU__) - #define PTRDIFF_MAX (INT32_MAX) - #define PTRDIFF_MIN (INT32_MIN) -#elif defined(__FROZEN__) - #define PTRDIFF_MAX (INT64_MAX) - #define PTRDIFF_MIN (INT64_MIN) -#endif - -#if defined(_TMS320C5XX) || defined(__TMS320C55X__) || defined(__MSP430__) - #define SIG_ATOMIC_MIN (INT16_MIN) - #define SIG_ATOMIC_MAX (INT16_MAX) -#elif defined(__TMS320C2000__) || defined(_TMS320C6X) || defined(__FROZEN__) || \ - defined(__ARM_ARCH) || defined(__ARP32__) || defined(__PRU__) - #define SIG_ATOMIC_MIN (INT32_MIN) - #define SIG_ATOMIC_MAX (INT32_MAX) -#endif - -#if defined(_TMS320C5XX) || defined(__TMS320C55X__) || \ - (defined(__MSP430__) && !defined(__LONG_PTRDIFF_T__)) - #define SIZE_MAX (UINT16_MAX) -#elif defined(__TMS320C2000__) || defined(__MSP430__) || \ - (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \ - defined(__ARM_ARCH) || defined(__ARP32__) || defined(__PRU__) - #define SIZE_MAX (UINT32_MAX) -#elif defined(__FROZEN__) - #define SIZE_MAX (UINT64_MAX) -#endif - -#ifndef WCHAR_MAX -#if !defined(__TI_WCHAR_T_BITS__) || __TI_WCHAR_T_BITS__ == 16 -#define WCHAR_MAX 0xffffu -#else -#define WCHAR_MAX 0xffffffffu -#endif -#endif - -#ifndef WCHAR_MIN -#define WCHAR_MIN 0 -#endif - -#if defined(_TMS320C5XX) || defined(__TMS320C55X__) || defined(__MSP430__) - #define WINT_MIN (INT16_MIN) - #define WINT_MAX (INT16_MAX) -#elif defined(__TMS320C2000__) || defined(_TMS320C6X) || defined(__FROZEN__) || \ - defined(__ARM_ARCH) || defined(__ARP32__) || defined(__PRU__) - #define WINT_MIN (INT32_MIN) - #define WINT_MAX (INT32_MAX) -#endif - -/* 7.18.4.1 Macros for minimum-width integer constants */ - -/* - There is a defect report filed against the C99 standard concerning how - the (U)INTN_C macros should be implemented. Please refer to -- - http://wwwold.dkuug.dk/JTC1/SC22/WG14/www/docs/dr_209.htm - for more information. These macros are implemented according to the - suggestion given at this web site. -*/ - - #define INT8_C(value) ((int_least8_t)(value)) - #define UINT8_C(value) ((uint_least8_t)(value)) - #define INT16_C(value) ((int_least16_t)(value)) - #define UINT16_C(value) ((uint_least16_t)(value)) - #define INT32_C(value) ((int_least32_t)(value)) - #define UINT32_C(value) ((uint_least32_t)(value)) - -#if defined(__TMS320C55X__) || \ - (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) - #define INT40_C(value) ((int_least40_t)(value)) - #define UINT40_C(value) ((uint_least40_t)(value)) -#endif - -#if defined(__ARM_ARCH) || defined(_TMS320C6X) || defined(__FROZEN__) || \ - defined(__ARP32__) || defined(__MSP430__) || defined(__PRU__) - #define INT64_C(value) ((int_least64_t)(value)) - #define UINT64_C(value) ((uint_least64_t)(value)) -#elif defined(__TMS320C2000__) -#if defined(__TMS320C28X__) || \ - (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) - #define INT64_C(value) ((int_least64_t)(value)) - #define UINT64_C(value) ((uint_least64_t)(value)) -#endif -#endif - -/* 7.18.4.2 Macros for greatest-width integer constants */ - - #define INTMAX_C(value) ((intmax_t)(value)) - #define UINTMAX_C(value) ((uintmax_t)(value)) - -#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ -#endif -#endif /* _STDINT_H_ */ diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/usb.h b/bsp/c28x/libraries/tms320f28379d/common/include/usb.h deleted file mode 100644 index 1eb1f8396e..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/usb.h +++ /dev/null @@ -1,561 +0,0 @@ -//########################################################################### -// -// FILE: usb.h -// -// TITLE: Prototypes for the USB Interface Driver. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - - -#ifndef __DRIVERLIB_USB_H__ -#define __DRIVERLIB_USB_H__ - -//***************************************************************************** -// -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -// -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - -//***************************************************************************** -// -// The following are defines for the g_usUSBFlags variable -// -//***************************************************************************** -#define USB_VBUS_VALID 0x0001 -#define USB_ID_HOST 0x0002 -#define USB_ID_DEVICE 0x0000 -#define USB_PFLT_ACTIVE 0x0004 - -//***************************************************************************** -// -// The following are values that can be passed to USBIntEnableControl() and -// USBIntDisableControl() as the ui32Flags parameter, and are returned from -// USBIntStatusControl(). -// -//***************************************************************************** -#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources -#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts -#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error -#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected -#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected -#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected -#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected -#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected -#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled -#define USB_INTCTRL_RESET 0x00000004 // Reset signaled -#define USB_INTCTRL_RESUME 0x00000002 // Resume detected -#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected -#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid -#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected - -//***************************************************************************** -// -// The following are values that can be passed to USBIntEnableEndpoint() and -// USBIntDisableEndpoint() as the ui32Flags parameter, and are returned from -// USBIntStatusEndpoint(). -// -//***************************************************************************** -#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts -#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts -#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt -#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt -#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt -#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt -#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt -#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt -#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt -#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt -#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt -#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt -#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt -#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt -#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt -#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt -#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt - -#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts -#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt -#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt - -#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts -#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt -#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt - -#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts -#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt -#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt -#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt -#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt -#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt -#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt -#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt -#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt -#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt -#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt -#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt -#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt -#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt -#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt -#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt - -#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt - -//***************************************************************************** -// -// The following are values that are returned from USBSpeedGet(). -// -//***************************************************************************** -#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined -#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed -#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed - -//***************************************************************************** -// -// The following are values that are returned from USBEndpointStatus(). The -// USB_HOST_* values are used when the USB controller is in host mode and the -// USB_DEV_* values are used when the USB controller is in device mode. -// -//***************************************************************************** -#define USB_HOST_IN_STATUS 0xFFFF0000 // Mask of all host IN interrupts -#define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received -#define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond -#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received -#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error - // (ISOC Mode) -#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the - // specified timeout period -#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a - // device -#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full -#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready -#define USB_HOST_OUT_STATUS 0x0000FFFF // Mask of all host OUT interrupts -#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the - // specified timeout period -#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device - // (ISOC mode) -#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received -#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a - // device -#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty -#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted -#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the - // specified timeout period -#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet -#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a - // device -#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received -#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready -#define USB_DEV_RX_PID_ERROR 0x01000000 // PID error in isochronous - // transfer -#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint -#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data -#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to - // a full FIFO -#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full -#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready -#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data - // to come -#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint -#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready -#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty -#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted -#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before - // Data End seen -#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint -#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending -#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready - -//***************************************************************************** -// -// The following are values that can be passed to USBHostEndpointConfig() and -// USBDevEndpointConfigSet() as the ui32Flags parameter. -// -//***************************************************************************** -#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled -#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled -#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled -#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0 -#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1 -#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint -#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint -#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint -#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint -#define USB_EP_MODE_MASK 0x00000300 // Mode Mask -#define USB_EP_SPEED_LOW 0x00000000 // Low Speed -#define USB_EP_SPEED_FULL 0x00001000 // Full Speed -#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint -#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint -#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint -#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint - -//***************************************************************************** -// -// The following are values that can be passed to USBHostPwrConfig() as the -// ui32Flags parameter. -// -//***************************************************************************** -#define USB_HOST_PWRFLT_LOW 0x00000010 -#define USB_HOST_PWRFLT_HIGH 0x00000030 -#define USB_HOST_PWRFLT_EP_NONE 0x00000000 -#define USB_HOST_PWRFLT_EP_TRI 0x00000140 -#define USB_HOST_PWRFLT_EP_LOW 0x00000240 -#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 -#define USB_HOST_PWREN_MAN_LOW 0x00000000 -#define USB_HOST_PWREN_MAN_HIGH 0x00000001 -#define USB_HOST_PWREN_AUTOLOW 0x00000002 -#define USB_HOST_PWREN_AUTOHIGH 0x00000003 -#define USB_HOST_PWREN_FILTER 0x00010000 - -//***************************************************************************** -// -// The following are special values that can be passed to -// USBHostEndpointConfig() as the ui32NAKPollInterval parameter. -// -//***************************************************************************** -#define MAX_NAK_LIMIT 31 // Maximum NAK interval -#define DISABLE_NAK_LIMIT 0 // No NAK timeouts - -//***************************************************************************** -// -// This value specifies the maximum size of transfers on endpoint 0 as 64 -// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. -// -//***************************************************************************** -#define MAX_PACKET_SIZE_EP0 64 - -//***************************************************************************** -// -// These values are used to indicate which endpoint to access. -// -//***************************************************************************** -#define USB_EP_0 0x00000000 // Endpoint 0 -#define USB_EP_1 0x00000010 // Endpoint 1 -#define USB_EP_2 0x00000020 // Endpoint 2 -#define USB_EP_3 0x00000030 // Endpoint 3 -#define USB_EP_4 0x00000040 // Endpoint 4 -#define USB_EP_5 0x00000050 // Endpoint 5 -#define USB_EP_6 0x00000060 // Endpoint 6 -#define USB_EP_7 0x00000070 // Endpoint 7 -#define USB_EP_8 0x00000080 // Endpoint 8 -#define USB_EP_9 0x00000090 // Endpoint 9 -#define USB_EP_10 0x000000A0 // Endpoint 10 -#define USB_EP_11 0x000000B0 // Endpoint 11 -#define USB_EP_12 0x000000C0 // Endpoint 12 -#define USB_EP_13 0x000000D0 // Endpoint 13 -#define USB_EP_14 0x000000E0 // Endpoint 14 -#define USB_EP_15 0x000000F0 // Endpoint 15 -#define NUM_USB_EP 16 // Number of supported endpoints - -//***************************************************************************** -// -// These macros allow conversion between 0-based endpoint indices and the -// USB_EP_x values required when calling various USB APIs. -// -//***************************************************************************** -#define IndexToUSBEP(x) (((uint32_t)(x) << 4) & 0xFF) -#define USBEPToIndex(x) ((x) >> 4) - -//***************************************************************************** -// -// The following are values that can be passed to USBFIFOConfigSet() as the -// ui32FIFOSize parameter. -// -//***************************************************************************** -#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO -#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO -#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO -#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO -#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO -#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO -#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO -#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO -#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO -#define USB_FIFO_SZ_4096 0x00000009 // 4096 byte FIFO -#define USB_FIFO_SZ_8_DB 0x00000010 // 8 byte double buffered FIFO - // (occupying 16 bytes) -#define USB_FIFO_SZ_16_DB 0x00000011 // 16 byte double buffered FIFO - // (occupying 32 bytes) -#define USB_FIFO_SZ_32_DB 0x00000012 // 32 byte double buffered FIFO - // (occupying 64 bytes) -#define USB_FIFO_SZ_64_DB 0x00000013 // 64 byte double buffered FIFO - // (occupying 128 bytes) -#define USB_FIFO_SZ_128_DB 0x00000014 // 128 byte double buffered FIFO - // (occupying 256 bytes) -#define USB_FIFO_SZ_256_DB 0x00000015 // 256 byte double buffered FIFO - // (occupying 512 bytes) -#define USB_FIFO_SZ_512_DB 0x00000016 // 512 byte double buffered FIFO - // (occupying 1024 bytes) -#define USB_FIFO_SZ_1024_DB 0x00000017 // 1024 byte double buffered FIFO - // (occupying 2048 bytes) -#define USB_FIFO_SZ_2048_DB 0x00000018 // 2048 byte double buffered FIFO - // (occupying 4096 bytes) - -//***************************************************************************** -// -// This macro allow conversion from a FIFO size label as defined above to -// a number of bytes -// -//***************************************************************************** -#define USB_FIFO_SIZE_DB_FLAG 0x00000010 -#define USBFIFOSizeToBytes(x) ((uint32_t)8 << (x)) - -//***************************************************************************** -// -// The following are values that can be passed to USBEndpointDataSend() as the -// ui32TransType parameter. -// -//***************************************************************************** -#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction -#define USB_TRANS_IN 0x00000102 // Normal IN transaction -#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for - // endpoint 0 in device mode) -#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint - // 0) -#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint - // 0) - -//***************************************************************************** -// -// The following are values are returned by the USBModeGet function. -// -//***************************************************************************** -#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host - // mode. -#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in - // Device mode. -#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not - // set. -#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of - // the cable. -#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of - // the cable. -#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of - // the cable Session Valid. -#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of - // the cable A valid. -#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of - // the cable. -#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of - // the cable. -#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of - // the cable. -#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of - // the cable. -#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set. - -//***************************************************************************** -// -// Prototypes for the APIs. -// -//***************************************************************************** -extern uint32_t USBDevAddrGet(uint32_t ui32Base); -extern void USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address); -extern void USBDevConnect(uint32_t ui32Base); -extern void USBDevDisconnect(uint32_t ui32Base); -extern void USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32MaxPacketSize, - uint32_t ui32Flags); -extern void USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t *pui32MaxPacketSize, - uint32_t *pui32Flags); -extern void USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, - bool bIsLastPacket); -extern void USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern uint32_t USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint); -extern void USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Config); -extern int32_t USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint8_t *pui8Data, uint32_t *pui32Size); -extern int32_t USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, - uint8_t *pui8Data, uint32_t ui32Size); -extern int32_t USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32TransType); -extern void USBEndpointDataToggleClear(uint32_t ui32Base, - uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Count); -extern uint32_t USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint); -extern uint32_t USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint); -extern void USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t *pui32FIFOAddress, - uint32_t *pui32FIFOSize, uint32_t ui32Flags); -extern void USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, - uint32_t ui32Flags); -extern void USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern uint32_t USBFrameNumberGet(uint32_t ui32Base); -extern uint32_t USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Addr, uint32_t ui32Flags); -extern void USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32MaxPacketSize, - uint32_t ui32NAKPollInterval, - uint32_t ui32TargetEndpoint, - uint32_t ui32Flags); -extern void USBHostEndpointDataAck(uint32_t ui32Base, - uint32_t ui32Endpoint); -extern void USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, - bool bDataToggle, uint32_t ui32Flags); -extern void USBHostEndpointStatusClear(uint32_t ui32Base, - uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern uint32_t USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags); -extern void USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Addr, uint32_t ui32Flags); -extern void USBHostPwrDisable(uint32_t ui32Base); -extern void USBHostPwrEnable(uint32_t ui32Base); -extern void USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags); -extern void USBHostPwrFaultDisable(uint32_t ui32Base); -extern void USBHostPwrFaultEnable(uint32_t ui32Base); -extern void USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint); -extern void USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint); -extern void USBHostRequestStatus(uint32_t ui32Base); -extern void USBHostReset(uint32_t ui32Base, bool bStart); -extern void USBHostResume(uint32_t ui32Base, bool bStart); -extern uint32_t USBHostSpeedGet(uint32_t ui32Base); -extern void USBHostSuspend(uint32_t ui32Base); -extern void USBIntDisableControl(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void USBIntEnableControl(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t USBIntStatus(uint32_t ui32Base, uint32_t *ui32IntStatusEP); -extern uint32_t USBIntStatusControl(uint32_t ui32Base); -extern void USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); -extern void USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); -extern uint32_t USBIntStatusEndpoint(uint32_t ui32Base); -extern void USBIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); -extern void USBIntUnregister(uint32_t ui32Base); -extern void USBOTGSessionRequest(uint32_t ui32Base, bool bStart); -extern uint32_t USBModeGet(uint32_t ui32Base); -extern void USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Channel); -extern void USBHostMode(uint32_t ui32Base); -extern void USBDevMode(uint32_t ui32Base); -extern void USBOTGMode(uint32_t ui32Base); -extern void USBPHYPowerOff(uint32_t ui32Base); -extern void USBPHYPowerOn(uint32_t ui32Base); -extern uint32_t USBNumEndpointsGet(uint32_t ui32Base); - -//***************************************************************************** -// The following are values that can be passed to USBIntEnable() and -// USBIntDisable() as the ulIntFlags parameter, and are returned from -// USBIntStatus(). -//***************************************************************************** -#define USB_INT_ALL 0xFF030E0F // All Interrupt sources -#define USB_INT_STATUS 0xFF000000 // Status Interrupts -#define USB_INT_VBUS_ERR 0x80000000 // VBUS Error -#define USB_INT_SESSION_START 0x40000000 // Session Start Detected -#define USB_INT_SESSION_END 0x20000000 // Session End Detected -#define USB_INT_DISCONNECT 0x20000000 // Disconnect Detected -#define USB_INT_CONNECT 0x10000000 // Device Connect Detected -#define USB_INT_SOF 0x08000000 // Start of Frame Detected -#define USB_INT_BABBLE 0x04000000 // Babble signaled -#define USB_INT_RESET 0x04000000 // Reset signaled -#define USB_INT_RESUME 0x02000000 // Resume detected -#define USB_INT_SUSPEND 0x01000000 // Suspend detected -#define USB_INT_MODE_DETECT 0x00020000 // Mode value valid -#define USB_INT_POWER_FAULT 0x00010000 // Power Fault detected -#define USB_INT_HOST_IN 0x00000E00 // Host IN Interrupts -#define USB_INT_DEV_OUT 0x00000E00 // Device OUT Interrupts -#define USB_INT_HOST_IN_EP3 0x00000800 // Endpoint 3 Host IN Interrupt -#define USB_INT_HOST_IN_EP2 0x00000400 // Endpoint 2 Host IN Interrupt -#define USB_INT_HOST_IN_EP1 0x00000200 // Endpoint 1 Host IN Interrupt -#define USB_INT_DEV_OUT_EP3 0x00000800 // Endpoint 3 Device OUT Interrupt -#define USB_INT_DEV_OUT_EP2 0x00000400 // Endpoint 2 Device OUT Interrupt -#define USB_INT_DEV_OUT_EP1 0x00000200 // Endpoint 1 Device OUT Interrupt -#define USB_INT_HOST_OUT 0x0000000E // Host OUT Interrupts -#define USB_INT_DEV_IN 0x0000000E // Device IN Interrupts -#define USB_INT_HOST_OUT_EP3 0x00000008 // Endpoint 3 HOST_OUT Interrupt -#define USB_INT_HOST_OUT_EP2 0x00000004 // Endpoint 2 HOST_OUT Interrupt -#define USB_INT_HOST_OUT_EP1 0x00000002 // Endpoint 1 HOST_OUT Interrupt -#define USB_INT_DEV_IN_EP3 0x00000008 // Endpoint 3 DEV_IN Interrupt -#define USB_INT_DEV_IN_EP2 0x00000004 // Endpoint 2 DEV_IN Interrupt -#define USB_INT_DEV_IN_EP1 0x00000002 // Endpoint 1 DEV_IN Interrupt -#define USB_INT_EP0 0x00000001 // Endpoint 0 Interrupt - -//***************************************************************************** -// -// Mark the end of the C bindings section for C++ compilers. -// -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -#endif // __DRIVERLIB_USB_H__ diff --git a/bsp/c28x/libraries/tms320f28379d/common/include/usb_hal.h b/bsp/c28x/libraries/tms320f28379d/common/include/usb_hal.h deleted file mode 100644 index d89577ebc3..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/include/usb_hal.h +++ /dev/null @@ -1,82 +0,0 @@ -//########################################################################### -// FILE: usb_hal.h -// TITLE: Compatability layer for ported software. -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __USB_HAL_H__ -#define __USB_HAL_H__ - -//***************************************************************************** -// If building with a C++ compiler, make all of the definitions in this header -// have a C binding. -//***************************************************************************** -#ifdef __cplusplus -extern "C" -{ -#endif - - - -//***************************************************************************** -//! \addtogroup c2000_specific -//! @{ -//***************************************************************************** - -extern void USBGPIOEnable(void); -extern void USBGPIODisable(void); -extern void USBDelay(uint32_t ui32Delay); - -extern void f28x_USB0DeviceIntHandler(void); -extern void f28x_USB0HostIntHandler(void); -extern void f28x_USB0DualModeIntHandler(void); -extern void f28x_USB0OTGModeIntHandler(void); - - -//***************************************************************************** -// Mark the end of the C bindings section for C++ compilers. -//***************************************************************************** -#ifdef __cplusplus -} -#endif - -//***************************************************************************** -// Close the Doxygen group. -//! @} -//***************************************************************************** - -#endif // __F28X_USB_HAL_H__ - diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Adc.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Adc.c deleted file mode 100644 index 3959c44698..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Adc.c +++ /dev/null @@ -1,286 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Adc.c -// -// TITLE: F2837xD Adc Support Functions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" - -// -// AdcSetMode - Set the resolution and signalmode for a given ADC. This will -// ensure that the correct trim is loaded. -// -// NOTE!!! There is no EALLOW/EDIS in this function! You need to make sure you -// perform the EALLOW before calling this function or else the ADC registers -// will not be configured. -// -void AdcSetMode(Uint16 adc, Uint16 resolution, Uint16 signalmode) -{ - Uint16 adcOffsetTrimOTPIndex; //index into OTP table of ADC offset trims - Uint16 adcOffsetTrim; //temporary ADC offset trim - - // - //re-populate INL trim - // - CalAdcINL(adc); - - if(0xFFFF != *((Uint16*)GetAdcOffsetTrimOTP)) - { - // - //offset trim function is programmed into OTP, so call it - // - - // - //calculate the index into OTP table of offset trims and call - //function to return the correct offset trim - // -#ifndef _DUAL_HEADERS - if(ADC_RESOLUTION_12BIT == resolution) -#else - if(ADC_BITRESOLUTION_12BIT == resolution) -#endif - { - adcOffsetTrimOTPIndex = 4*adc + 1*signalmode; - } - else - { - adcOffsetTrimOTPIndex = 4*adc + 1*signalmode + 2; - } - - adcOffsetTrim = (*GetAdcOffsetTrimOTP)(adcOffsetTrimOTPIndex); - } - else - { - // - //offset trim function is not populated, so set offset trim to 0 - // - adcOffsetTrim = 0; - } - - // - // Apply the resolution and signalmode to the specified ADC. - // Also apply the offset trim and, if needed, linearity trim correction. - // - switch(adc) - { - case ADC_ADCA: - { - AdcaRegs.ADCCTL2.bit.SIGNALMODE = signalmode; - AdcaRegs.ADCOFFTRIM.all = adcOffsetTrim; -#ifndef _DUAL_HEADERS - if(ADC_RESOLUTION_12BIT == resolution) -#else - if(ADC_BITRESOLUTION_12BIT == resolution) -#endif - { - AdcaRegs.ADCCTL2.bit.RESOLUTION = 0; - - // - //12-bit linearity trim workaround - // - AdcaRegs.ADCINLTRIM1 &= 0xFFFF0000; - AdcaRegs.ADCINLTRIM2 &= 0xFFFF0000; - AdcaRegs.ADCINLTRIM4 &= 0xFFFF0000; - AdcaRegs.ADCINLTRIM5 &= 0xFFFF0000; - } - else - { - AdcaRegs.ADCCTL2.bit.RESOLUTION = 1; - } - break; - } - case ADC_ADCB: - { - AdcbRegs.ADCCTL2.bit.SIGNALMODE = signalmode; - AdcbRegs.ADCOFFTRIM.all = adcOffsetTrim; -#ifndef _DUAL_HEADERS - if(ADC_RESOLUTION_12BIT == resolution) -#else - if(ADC_BITRESOLUTION_12BIT == resolution) -#endif - { - AdcbRegs.ADCCTL2.bit.RESOLUTION = 0; - - // - //12-bit linearity trim workaround - // - AdcbRegs.ADCINLTRIM1 &= 0xFFFF0000; - AdcbRegs.ADCINLTRIM2 &= 0xFFFF0000; - AdcbRegs.ADCINLTRIM4 &= 0xFFFF0000; - AdcbRegs.ADCINLTRIM5 &= 0xFFFF0000; - } - else - { - AdcbRegs.ADCCTL2.bit.RESOLUTION = 1; - } - break; - } - case ADC_ADCC: - { - AdccRegs.ADCCTL2.bit.SIGNALMODE = signalmode; - AdccRegs.ADCOFFTRIM.all = adcOffsetTrim; -#ifndef _DUAL_HEADERS - if(ADC_RESOLUTION_12BIT == resolution) -#else - if(ADC_BITRESOLUTION_12BIT == resolution) -#endif - { - AdccRegs.ADCCTL2.bit.RESOLUTION = 0; - // - //12-bit linearity trim workaround - // - AdccRegs.ADCINLTRIM1 &= 0xFFFF0000; - AdccRegs.ADCINLTRIM2 &= 0xFFFF0000; - AdccRegs.ADCINLTRIM4 &= 0xFFFF0000; - AdccRegs.ADCINLTRIM5 &= 0xFFFF0000; - } - else - { - AdccRegs.ADCCTL2.bit.RESOLUTION = 1; - } - break; - } - case ADC_ADCD: - { - AdcdRegs.ADCCTL2.bit.SIGNALMODE = signalmode; - AdcdRegs.ADCOFFTRIM.all = adcOffsetTrim; -#ifndef _DUAL_HEADERS - if(ADC_RESOLUTION_12BIT == resolution) -#else - if(ADC_BITRESOLUTION_12BIT == resolution) -#endif - { - AdcdRegs.ADCCTL2.bit.RESOLUTION = 0; - - // - //12-bit linearity trim workaround - // - AdcdRegs.ADCINLTRIM1 &= 0xFFFF0000; - AdcdRegs.ADCINLTRIM2 &= 0xFFFF0000; - AdcdRegs.ADCINLTRIM4 &= 0xFFFF0000; - AdcdRegs.ADCINLTRIM5 &= 0xFFFF0000; - } - else - { - AdcdRegs.ADCCTL2.bit.RESOLUTION = 1; - } - break; - } - } -} - -// -// CalAdcINL - Loads INL trim values from OTP into the trim registers of the -// specified ADC. Use only as part of AdcSetMode function, since -// linearity trim correction is needed for some modes. -// -void CalAdcINL(Uint16 adc) -{ - switch(adc) - { - case ADC_ADCA: - if(0xFFFF != *((Uint16*)CalAdcaINL)) - { - // - //trim function is programmed into OTP, so call it - // - (*CalAdcaINL)(); - } - else - { - // - //do nothing, no INL trim function populated - // - } - break; - case ADC_ADCB: - if(0xFFFF != *((Uint16*)CalAdcbINL)) - { - // - //trim function is programmed into OTP, so call it - // - (*CalAdcbINL)(); - } - else - { - // - //do nothing, no INL trim function populated - // - } - break; - case ADC_ADCC: - if(0xFFFF != *((Uint16*)CalAdccINL)) - { - // - //trim function is programmed into OTP, so call it - // - (*CalAdccINL)(); - } - else - { - // - //do nothing, no INL trim function populated - // - } - break; - case ADC_ADCD: - if(0xFFFF != *((Uint16*)CalAdcdINL)) - { - // - //trim function is programmed into OTP, so call it - // - (*CalAdcdINL)(); - } - else - { - // - //do nothing, no INL trim function populated - // - } - break; - } -} - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_CodeStartBranch.asm b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_CodeStartBranch.asm deleted file mode 100644 index cd08bf30c0..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_CodeStartBranch.asm +++ /dev/null @@ -1,111 +0,0 @@ -;//########################################################################### -;// -;// FILE: F2837xD_CodeStartBranch.asm -;// -;// TITLE: Branch for redirecting code execution after boot. -;// -;// For these examples, code_start is the first code that is executed after -;// exiting the boot ROM code. -;// -;// The codestart section in the linker cmd file is used to physically place -;// this code at the correct memory location. This section should be placed -;// at the location the BOOT ROM will re-direct the code to. For example, -;// for boot to FLASH this code will be located at 0x3f7ff6. -;// -;// In addition, the example F2837xD projects are setup such that the codegen -;// entry point is also set to the code_start label. This is done by linker -;// option -e in the project build options. When the debugger loads the code, -;// it will automatically set the PC to the "entry point" address indicated by -;// the -e linker option. In this case the debugger is simply assigning the PC, -;// it is not the same as a full reset of the device. -;// -;// The compiler may warn that the entry point for the project is other then -;// _c_init00. _c_init00 is the C environment setup and is run before -;// main() is entered. The code_start code will re-direct the execution -;// to _c_init00 and thus there is no worry and this warning can be ignored. -;// -;//########################################################################### -;// $TI Release: F2837xD Support Library v3.05.00.00 $ -;// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -;// $Copyright: -;// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -;// -;// Redistribution and use in source and binary forms, with or without -;// modification, are permitted provided that the following conditions -;// are met: -;// -;// Redistributions of source code must retain the above copyright -;// notice, this list of conditions and the following disclaimer. -;// -;// Redistributions in binary form must reproduce the above copyright -;// notice, this list of conditions and the following disclaimer in the -;// documentation and/or other materials provided with the -;// distribution. -;// -;// Neither the name of Texas Instruments Incorporated nor the names of -;// its contributors may be used to endorse or promote products derived -;// from this software without specific prior written permission. -;// -;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;// $ -;//########################################################################### - -*********************************************************************** - -WD_DISABLE .set 0 ;set to 1 to disable WD, else set to 0 - - .ref _c_int00 - .global code_start - -*********************************************************************** -* Function: codestart section -* -* Description: Branch to code starting point -*********************************************************************** - - .sect "codestart" - -code_start: - .if WD_DISABLE == 1 - LB wd_disable ;Branch to watchdog disable code - .else - LB _c_int00 ;Branch to start of boot._asm in RTS library - .endif - -;end codestart section - -*********************************************************************** -* Function: wd_disable -* -* Description: Disables the watchdog timer -*********************************************************************** - .if WD_DISABLE == 1 - - .text -wd_disable: - SETC OBJMODE ;Set OBJMODE for 28x object code - EALLOW ;Enable EALLOW protected register access - MOVZ DP, #7029h>>6 ;Set data page for WDCR register - MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD - EDIS ;Disable EALLOW protected register access - LB _c_int00 ;Branch to start of boot._asm in RTS library - - .endif - -;end wd_disable - - .end - -;// -;// End of file. -;// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_CpuTimers.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_CpuTimers.c deleted file mode 100644 index 1a0877ea6d..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_CpuTimers.c +++ /dev/null @@ -1,181 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_CpuTimers.c -// -// TITLE: CPU 32-bit Timers Initialization & Support Functions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" - -// -// Globals -// -struct CPUTIMER_VARS CpuTimer0; -struct CPUTIMER_VARS CpuTimer1; -struct CPUTIMER_VARS CpuTimer2; - -// -// InitCpuTimers - This function initializes all three CPU timers to a known -// state. -// -void InitCpuTimers(void) -{ - // - // CPU Timer 0 - // Initialize address pointers to respective timer registers: - // - CpuTimer0.RegsAddr = &CpuTimer0Regs; - - // - // Initialize timer period to maximum: - // - CpuTimer0Regs.PRD.all = 0xFFFFFFFF; - - // - // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): - // - CpuTimer0Regs.TPR.all = 0; - CpuTimer0Regs.TPRH.all = 0; - - // - // Make sure timer is stopped: - // - CpuTimer0Regs.TCR.bit.TSS = 1; - - // - // Reload all counter register with period value: - // - CpuTimer0Regs.TCR.bit.TRB = 1; - - // - // Reset interrupt counters: - // - CpuTimer0.InterruptCount = 0; - - // - // Initialize address pointers to respective timer registers: - // - CpuTimer1.RegsAddr = &CpuTimer1Regs; - CpuTimer2.RegsAddr = &CpuTimer2Regs; - - // - // Initialize timer period to maximum: - // - CpuTimer1Regs.PRD.all = 0xFFFFFFFF; - CpuTimer2Regs.PRD.all = 0xFFFFFFFF; - - // - // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): - // - CpuTimer1Regs.TPR.all = 0; - CpuTimer1Regs.TPRH.all = 0; - CpuTimer2Regs.TPR.all = 0; - CpuTimer2Regs.TPRH.all = 0; - - // - // Make sure timers are stopped: - // - CpuTimer1Regs.TCR.bit.TSS = 1; - CpuTimer2Regs.TCR.bit.TSS = 1; - - // - // Reload all counter register with period value: - // - CpuTimer1Regs.TCR.bit.TRB = 1; - CpuTimer2Regs.TCR.bit.TRB = 1; - - // - // Reset interrupt counters: - // - CpuTimer1.InterruptCount = 0; - CpuTimer2.InterruptCount = 0; -} - -// -// ConfigCpuTimer - This function initializes the selected timer to the period -// specified by the "Freq" and "Period" parameters. The "Freq" -// is entered as "MHz" and the period in "uSeconds". The timer -// is held in the stopped state after configuration. -// -void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) -{ - Uint32 temp; - - // - // Initialize timer period: - // - Timer->CPUFreqInMHz = Freq; - Timer->PeriodInUSec = Period; - temp = (long) (Freq * Period); - - // - // Counter decrements PRD+1 times each period - // - Timer->RegsAddr->PRD.all = temp - 1; - - // - // Set pre-scale counter to divide by 1 (SYSCLKOUT): - // - Timer->RegsAddr->TPR.all = 0; - Timer->RegsAddr->TPRH.all = 0; - - // - // Initialize timer control register: - // - Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart - // Timer - Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer - Timer->RegsAddr->TCR.bit.SOFT = 0; - Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled - Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer - // Interrupt - - // - // Reset interrupt counter: - // - Timer->InterruptCount = 0; -} - - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_DBGIER.asm b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_DBGIER.asm deleted file mode 100644 index 951fe6a28a..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_DBGIER.asm +++ /dev/null @@ -1,60 +0,0 @@ -;//########################################################################### -;// -;// FILE: F2837xD_DBGIER.asm -;// -;// TITLE: Set the DBGIER register -;// -;// DESCRIPTION: -;// -;// Function to set the DBGIER register (for realtime emulation). -;// Function Prototype: void SetDBGIER(Uint16) -;// Usage: SetDBGIER(value); -;// Input Parameters: Uint16 value = value to put in DBGIER register. -;// Return Value: none -;// -;//########################################################################### -;// $TI Release: F2837xD Support Library v3.05.00.00 $ -;// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -;// $Copyright: -;// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -;// -;// Redistribution and use in source and binary forms, with or without -;// modification, are permitted provided that the following conditions -;// are met: -;// -;// Redistributions of source code must retain the above copyright -;// notice, this list of conditions and the following disclaimer. -;// -;// Redistributions in binary form must reproduce the above copyright -;// notice, this list of conditions and the following disclaimer in the -;// documentation and/or other materials provided with the -;// distribution. -;// -;// Neither the name of Texas Instruments Incorporated nor the names of -;// its contributors may be used to endorse or promote products derived -;// from this software without specific prior written permission. -;// -;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;// $ -;//########################################################################### - .global _SetDBGIER - .text - -_SetDBGIER: - MOV *SP++,AL - POP DBGIER - LRETR - -;// -;// End of file -;// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_DefaultISR.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_DefaultISR.c deleted file mode 100644 index bd589343b6..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_DefaultISR.c +++ /dev/null @@ -1,3138 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_DefaultISR.c -// -// TITLE: F2837xD Device Default Interrupt Service Routines -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" - -// -// CPU Timer 1 Interrupt -// -interrupt void TIMER1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// CPU Timer 2 Interrupt -// -interrupt void TIMER2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// Datalogging Interrupt -// -interrupt void DATALOG_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// RTOS Interrupt -// -interrupt void RTOS_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// Emulation Interrupt -// -interrupt void EMU_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// Non-Maskable Interrupt -// -interrupt void NMI_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// Illegal Operation Trap -// -interrupt void ILLEGAL_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// User Defined Trap 1 -// -interrupt void USER1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// User Defined Trap 2 -// -interrupt void USER2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// User Defined Trap 3 -// -interrupt void USER3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// User Defined Trap 4 -// -interrupt void USER4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// User Defined Trap 5 -// -interrupt void USER5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// User Defined Trap 6 -// -interrupt void USER6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// User Defined Trap 7 -// -interrupt void USER7_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// User Defined Trap 8 -// -interrupt void USER8_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// User Defined Trap 9 -// -interrupt void USER9_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// User Defined Trap 10 -// -interrupt void USER10_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// User Defined Trap 11 -// -interrupt void USER11_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// User Defined Trap 12 -// -interrupt void USER12_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 1.1 - ADCA Interrupt 1 -// -interrupt void ADCA1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 1.2 - ADCB Interrupt 1 -// -interrupt void ADCB1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 1.3 - ADCC Interrupt 1 -// -interrupt void ADCC1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 1.4 - XINT1 Interrupt -// -interrupt void XINT1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 1.5 - XINT2 Interrupt -// -interrupt void XINT2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 1.6 - ADCD Interrupt 1 -// -interrupt void ADCD1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 1.7 - Timer 0 Interrupt -// -interrupt void TIMER0_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 1.8 - Standby and Halt Wakeup Interrupt -// -interrupt void WAKE_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 2.1 - ePWM1 Trip Zone Interrupt -// -interrupt void EPWM1_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 2.2 - ePWM2 Trip Zone Interrupt -// -interrupt void EPWM2_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 2.3 - ePWM3 Trip Zone Interrupt -// -interrupt void EPWM3_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 2.4 - ePWM4 Trip Zone Interrupt -// -interrupt void EPWM4_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 2.5 - ePWM5 Trip Zone Interrupt -// -interrupt void EPWM5_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 2.6 - ePWM6 Trip Zone Interrupt -// -interrupt void EPWM6_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 2.7 - ePWM7 Trip Zone Interrupt -// -interrupt void EPWM7_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 2.8 - ePWM8 Trip Zone Interrupt -// -interrupt void EPWM8_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 3.1 - ePWM1 Interrupt -// -interrupt void EPWM1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 3.2 - ePWM2 Interrupt -// -interrupt void EPWM2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 3.3 - ePWM3 Interrupt -// -interrupt void EPWM3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 3.4 - ePWM4 Interrupt -// -interrupt void EPWM4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 3.5 - ePWM5 Interrupt -// -interrupt void EPWM5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 3.6 - ePWM6 Interrupt -// -interrupt void EPWM6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 3.7 - ePWM7 Interrupt -// -interrupt void EPWM7_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 3.8 - ePWM8 Interrupt -// -interrupt void EPWM8_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 4.1 - eCAP1 Interrupt -// -interrupt void ECAP1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 4.2 - eCAP2 Interrupt -// -interrupt void ECAP2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 4.3 - eCAP3 Interrupt -// -interrupt void ECAP3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 4.4 - eCAP4 Interrupt -// -interrupt void ECAP4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 4.5 - eCAP5 Interrupt -// -interrupt void ECAP5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 4.6 - eCAP6 Interrupt -// -interrupt void ECAP6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 5.1 - eQEP1 Interrupt -// -interrupt void EQEP1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 5.2 - eQEP2 Interrupt -// -interrupt void EQEP2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 5.3 - eQEP3 Interrupt -// -interrupt void EQEP3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 6.1 - SPIA Receive Interrupt -// -interrupt void SPIA_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 6.2 - SPIA Transmit Interrupt -// -interrupt void SPIA_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 6.3 - SPIB Receive Interrupt -// -interrupt void SPIB_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 6.4 - SPIB Transmit Interrupt -// -interrupt void SPIB_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 6.5 - McBSPA Receive Interrupt -// -interrupt void MCBSPA_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 6.6 - McBSPA Transmit Interrupt -// -interrupt void MCBSPA_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 6.7 - McBSPB Receive Interrupt -// -interrupt void MCBSPB_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 6.8 - McBSPB Transmit Interrupt -// -interrupt void MCBSPB_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 7.1 - DMA Channel 1 Interrupt -// -interrupt void DMA_CH1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 7.2 - DMA Channel 2 Interrupt -// -interrupt void DMA_CH2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 7.3 - DMA Channel 3 Interrupt -// -interrupt void DMA_CH3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 7.4 - DMA Channel 4 Interrupt -// -interrupt void DMA_CH4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 7.5 - DMA Channel 5 Interrupt -// -interrupt void DMA_CH5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 7.6 - DMA Channel 6 Interrupt -// -interrupt void DMA_CH6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 8.1 - I2CA Interrupt 1 -// -interrupt void I2CA_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 8.2 - I2CA Interrupt 2 -// -interrupt void I2CA_FIFO_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 8.3 - I2CB Interrupt 1 -// -interrupt void I2CB_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 8.4 - I2CB Interrupt 2 -// -interrupt void I2CB_FIFO_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 8.5 - SCIC Receive Interrupt -// -interrupt void SCIC_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 8.6 - SCIC Transmit Interrupt -// -interrupt void SCIC_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 8.7 - SCID Receive Interrupt -// -interrupt void SCID_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 8.8 - SCID Transmit Interrupt -// -interrupt void SCID_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 9.1 - SCIA Receive Interrupt -// -interrupt void SCIA_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 9.2 - SCIA Transmit Interrupt -// -interrupt void SCIA_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 9.3 - SCIB Receive Interrupt -// -interrupt void SCIB_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 9.4 - SCIB Transmit Interrupt -// -interrupt void SCIB_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 9.5 - CANA Interrupt 0 -// -interrupt void CANA0_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 9.6 - CANA Interrupt 1 -// -interrupt void CANA1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 9.7 - CANB Interrupt 0 -// -interrupt void CANB0_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 9.8 - CANB Interrupt 1 -// -interrupt void CANB1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 10.1 - ADCA Event Interrupt -// -interrupt void ADCA_EVT_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 10.2 - ADCA Interrupt 2 -// -interrupt void ADCA2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 10.3 - ADCA Interrupt 3 -// -interrupt void ADCA3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 10.4 - ADCA Interrupt 4 -// -interrupt void ADCA4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 10.5 - ADCB Event Interrupt -// -interrupt void ADCB_EVT_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 10.6 - ADCB Interrupt 2 -// -interrupt void ADCB2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 10.7 - ADCB Interrupt 3 -// -interrupt void ADCB3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 10.8 - ADCB Interrupt 4 -// -interrupt void ADCB4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 11.1 - CLA1 Interrupt 1 -// -interrupt void CLA1_1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 11.2 - CLA1 Interrupt 2 -// -interrupt void CLA1_2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 11.3 - CLA1 Interrupt 3 -// -interrupt void CLA1_3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 11.4 - CLA1 Interrupt 4 -// -interrupt void CLA1_4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 11.5 - CLA1 Interrupt 5 -// -interrupt void CLA1_5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 11.6 - CLA1 Interrupt 6 -// -interrupt void CLA1_6_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 11.7 - CLA1 Interrupt 7 -// -interrupt void CLA1_7_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 11.8 - CLA1 Interrupt 8 -// -interrupt void CLA1_8_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 12.1 - XINT3 Interrupt -// -interrupt void XINT3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 12.2 - XINT4 Interrupt -// -interrupt void XINT4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 12.3 - XINT5 Interrupt -// -interrupt void XINT5_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 12.6 - VCU Interrupt -// -interrupt void VCU_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 12.7 - FPU Overflow Interrupt -// -interrupt void FPU_OVERFLOW_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 12.8 - FPU Underflow Interrupt -// -interrupt void FPU_UNDERFLOW_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 1.13 - IPC Interrupt 0 -// -interrupt void IPC0_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 1.14 - IPC Interrupt 1 -// -interrupt void IPC1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 1.15 - IPC Interrupt 2 -// -interrupt void IPC2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 1.16 - IPC Interrupt 3 -// -interrupt void IPC3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 2.9 - ePWM9 Trip Zone Interrupt -// -interrupt void EPWM9_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 2.10 - ePWM10 Trip Zone Interrupt -// -interrupt void EPWM10_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 2.11 - ePWM11 Trip Zone Interrupt -// -interrupt void EPWM11_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 2.12 - ePWM12 Trip Zone Interrupt -// -interrupt void EPWM12_TZ_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 3.9 - ePWM9 Interrupt -// -interrupt void EPWM9_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 3.10 - ePWM10 Interrupt -// -interrupt void EPWM10_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 3.11 - ePWM11 Interrupt -// -interrupt void EPWM11_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 3.12 - ePWM12 Interrupt -// -interrupt void EPWM12_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 5.9 - SD1 Interrupt -// -interrupt void SD1_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 5.10 - SD2 Interrupt -// -interrupt void SD2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 6.9 - SPIC Receive Interrupt -// -interrupt void SPIC_RX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 6.10 - SPIC Transmit Interrupt -// -interrupt void SPIC_TX_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 8.15 - uPPA Interrupt -// -interrupt void UPPA_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 9.15 - USBA Interrupt -// -interrupt void USBA_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 10.9 - ADCC Event Interrupt -// -interrupt void ADCC_EVT_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 10.10 - ADCC Interrupt 2 -// -interrupt void ADCC2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 10.11 - ADCC Interrupt 3 -// -interrupt void ADCC3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 10.12 - ADCC Interrupt 4 -// -interrupt void ADCC4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 10.13 - ADCD Event Interrupt -// -interrupt void ADCD_EVT_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 10.14 - ADCD Interrupt 2 -// -interrupt void ADCD2_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 10.15 - ADCD Interrupt 3 -// -interrupt void ADCD3_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 10.16 - ADCD Interrupt 4 -// -interrupt void ADCD4_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 12.9 - EMIF Error Interrupt -// -interrupt void EMIF_ERROR_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 12.10 - RAM Correctable Error Interrupt -// -interrupt void RAM_CORRECTABLE_ERROR_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 12.11 - Flash Correctable Error Interrupt -// -interrupt void FLASH_CORRECTABLE_ERROR_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 12.12 - RAM Access Violation Interrupt -// -interrupt void RAM_ACCESS_VIOLATION_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 12.13 - System PLL Slip Interrupt -// -interrupt void SYS_PLL_SLIP_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 12.14 - Auxiliary PLL Slip Interrupt -// -interrupt void AUX_PLL_SLIP_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 12.15 - CLA Overflow Interrupt -// -interrupt void CLA_OVERFLOW_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// 12.16 - CLA Underflow Interrupt -// -interrupt void CLA_UNDERFLOW_ISR(void) -{ - // - // Insert ISR Code here - // - - // - // To receive more interrupts from this PIE group, - // acknowledge this interrupt. - // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; - // - - // - // Next two lines for debug only to halt the processor here - // Remove after inserting ISR Code - // - asm (" ESTOP0"); - for(;;); -} - -// -// Catch-all Default ISRs: -// - -// -// PIE_RESERVED_ISR - Reserved ISR -// -interrupt void PIE_RESERVED_ISR(void) -{ - asm (" ESTOP0"); - for(;;); -} - -// -// EMPTY_ISR - Only does a return -// -interrupt void EMPTY_ISR(void) -{ - -} - -// -// NOTUSED_ISR - Unused ISR -// -interrupt void NOTUSED_ISR(void) -{ - asm (" ESTOP0"); - for(;;); -} - diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Dma.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Dma.c deleted file mode 100644 index ca5593c851..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Dma.c +++ /dev/null @@ -1,1100 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_DMA.c -// -// TITLE: F2837xD Device DMA Initialization & Support Functions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" - -// -// DMAInitialize - This function initializes the DMA to a known state. -// -void DMAInitialize(void) -{ - EALLOW; - - // - // Perform a hard reset on DMA - // - DmaRegs.DMACTRL.bit.HARDRESET = 1; - __asm (" nop"); // one NOP required after HARDRESET - - // - // Allow DMA to run free on emulation suspend - // - DmaRegs.DEBUGCTRL.bit.FREE = 1; - - EDIS; -} - -// -// DMACH1AddrConfig - DMA Channel 1 Address Configuration -// -void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to - // beginning of - // source buffer - DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to - // beginning of - // destination buffer - DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH1BurstConfig - DMA Channel 1 Burst size configuration -// -void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH1.BURST_SIZE.all = bsize; // Number of words(X-1) - // x-ferred in a burst. - DmaRegs.CH1.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH1.DST_BURST_STEP = desbstep; // Increment dest addr between - // each word x-ferred. - - EDIS; -} - -// -// DMACH1TransferConfig - DMA Channel 1 Transfer size configuration -// -void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH1.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored - // when WRAP occurs. - DmaRegs.CH1.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored - // when WRAP occurs. - - EDIS; -} - -// -// DMACH1WrapConfig - DMA Channel 1 Wrap size configuration -// -void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH1.DST_WRAP_SIZE = deswsize; // Wrap destination address after - // N bursts. - DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH1ModeConfig - DMA Channel 1 Mode configuration -// -void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH1 = persel; - DmaRegs.CH1.MODE.bit.PERINTSEL = 1; - DmaRegs.CH1.MODE.bit.PERINTE = perinte; - DmaRegs.CH1.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH1.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH1.MODE.bit.DATASIZE = datasize; - DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH1.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: interrupt and sync error flags - // - DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH1 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx1 = 1; - - EDIS; -} - -// -// StartDMACH1 - This function starts DMA Channel 1. -// -void StartDMACH1(void) -{ - EALLOW; - DmaRegs.CH1.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH2AddrConfig - DMA Channel 2 Address Configuration -// -void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to - // beginning of - // source buffer. - DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH2BurstConfig - DMA Channel 2 Burst size configuration -// -void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH2.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH2.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH2.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH2TransferConfig - DMA Channel 2 Transfer size Configuration -// -void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH2.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH2.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH2WrapConfig - DMA Channel 2 Wrap size configuration -// -void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH2.DST_WRAP_SIZE = deswsize; // Wrap destination address after - // N bursts. - DmaRegs.CH2.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH2ModeConfig - DMA Channel 2 Mode configuration -// -void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH2 = persel; - DmaRegs.CH2.MODE.bit.PERINTSEL = 2; - DmaRegs.CH2.MODE.bit.PERINTE = perinte; - DmaRegs.CH2.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH2.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH2.MODE.bit.DATASIZE = datasize; - DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH2.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: Interrupt flags and sync error flags - // - DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH2 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx2 = 1; - - EDIS; -} - -// -// StartDMACH2 - This function starts DMA Channel 2. -// -void StartDMACH2(void) -{ - EALLOW; - DmaRegs.CH2.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH3AddrConfig - DMA Channel 3 Address configuration -// -void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning - // of source buffer. - DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH3BurstConfig - DMA Channel 3 burst size configuration -// -void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH3.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH3.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH3.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH3TransferConfig - DMA channel 3 transfer size configuration -// -void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH3.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH3.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH3WrapConfig - DMA Channel 3 wrap size configuration -// -void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH3.DST_WRAP_SIZE = deswsize; // Wrap destination address after N - // bursts. - DmaRegs.CH3.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH3ModeConfig - DMA Channel 3 mode configuration -// -void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH3 = persel; - DmaRegs.CH3.MODE.bit.PERINTSEL = 3; - DmaRegs.CH3.MODE.bit.PERINTE = perinte; - DmaRegs.CH3.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH3.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH3.MODE.bit.DATASIZE = datasize; - DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH3.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: interrupt flags and sync error flags - // - DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH3 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx3 = 1; - - EDIS; -} - -// -// StartDMACH3 - This function starts DMA Channel 3. -// -void StartDMACH3(void) -{ - EALLOW; - DmaRegs.CH3.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH4AddrConfig - DMA Channel 4 address configuration -// -void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning - // of source buffer. - DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH4BurstConfig - DMA Channel 4 burst size configuration -// -void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH4.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH4.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH4.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH4TransferConfig - DMA channel 4 transfer size configuration -// -void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH4.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH4.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH4WrapConfig - DMA channel 4 wrap size configuration -// -void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH4.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH4.DST_WRAP_SIZE = deswsize; // Wrap destination address after - // N bursts. - DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH4ModeConfig - DMA Channel 4 mode configuration -// -void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH4 = persel; - DmaRegs.CH4.MODE.bit.PERINTSEL = 4; - DmaRegs.CH4.MODE.bit.PERINTE = perinte; - DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH4.MODE.bit.DATASIZE = datasize; - DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH4.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: Interrupt flags and sync error flags - // - DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH4 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx4 = 1; - - EDIS; -} - -// -// StartDMACH4 - This function starts DMA Channel 4. -// -void StartDMACH4(void) -{ - EALLOW; - DmaRegs.CH4.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH5AddrConfig - DMA channel 5 address configuration -// -void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning - // of source buffer - DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH5BurstConfig - DMA Channel 5 burst size configuration -// -void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH5.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH5.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH5.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH5TransferConfig - DMA channel 5 transfer size configuration -// -void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH5.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH5.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH5WrapConfig - DMA Channel 5 wrap size configuration -// -void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH5.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH5.DST_WRAP_SIZE = deswsize; // Wrap destination address after - // N bursts. - DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH5ModeConfig - DMA Channel 5 mode configuration -// -void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH5 = persel; - DmaRegs.CH5.MODE.bit.PERINTSEL = 5; - DmaRegs.CH5.MODE.bit.PERINTE = perinte; - DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH5.MODE.bit.DATASIZE = datasize; - DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH5.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: Interrupt flags and sync error flags - // - DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH5 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx5 = 1; - - EDIS; -} - -// -// StartDMACH5 - This function starts DMA Channel 5. -// -void StartDMACH5(void) -{ - EALLOW; - DmaRegs.CH5.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// DMACH6AddrConfig - DMA Channel 6 address configuration -// -void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning - // of source buffer. - DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH6BurstConfig - DMA Channel 6 burst size configuration -// -void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep) -{ - EALLOW; - - // - // Set up BURST registers: - // - DmaRegs.CH6.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in - // a burst. - DmaRegs.CH6.SRC_BURST_STEP = srcbstep; // Increment source addr between - // each word x-ferred. - DmaRegs.CH6.DST_BURST_STEP = desbstep; // Increment dest addr between each - // word x-ferred. - - EDIS; -} - -// -// DMACH6TransferConfig - DMA channel 6 transfer size configuration -// -void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) -{ - EALLOW; - - // - // Set up TRANSFER registers: - // - DmaRegs.CH6.TRANSFER_SIZE = tsize; // Number of bursts per transfer, - // DMA interrupt will occur after - // completed transfer. - DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when - // WRAP occurs. - DmaRegs.CH6.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when - // WRAP occurs. - - EDIS; -} - -// -// DMACH6WrapConfig - DMA Channel 6 wrap size configuration -// -void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, - int16 deswstep) -{ - EALLOW; - - // - // Set up WRAP registers: - // - DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts - DmaRegs.CH6.SRC_WRAP_STEP = srcwstep; // Step for source wrap - - DmaRegs.CH6.DST_WRAP_SIZE = deswsize; // Wrap destination address after N - // bursts. - DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap - - EDIS; -} - -// -// DMACH6ModeConfig - DMA Channel 6 mode configuration -// -void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, - Uint16 cont, Uint16 synce, Uint16 syncsel, - Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, - Uint16 chinte) -{ - EALLOW; - - // - // Set up MODE Register: - // persel - Source select - // PERINTSEL - Should be hard coded to channel, above now selects source - // PERINTE - Peripheral interrupt enable - // ONESHOT - Oneshot enable - // CONTINUOUS - Continuous enable - // OVRINTE - Enable/disable the overflow interrupt - // DATASIZE - 16-bit/32-bit data size transfers - // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer - // CHINTE - Channel Interrupt to CPU enable - // - DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH6 = persel; - DmaRegs.CH6.MODE.bit.PERINTSEL = 6; - DmaRegs.CH6.MODE.bit.PERINTE = perinte; - DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; - DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; - DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte; - DmaRegs.CH6.MODE.bit.DATASIZE = datasize; - DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode; - DmaRegs.CH6.MODE.bit.CHINTE = chinte; - - // - // Clear any spurious flags: Interrupt flags and sync error flags - // - DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; - DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; - - // - // Initialize PIE vector for CPU interrupt: - // Enable DMA CH6 interrupt in PIE - // - PieCtrlRegs.PIEIER7.bit.INTx6 = 1; - - EDIS; -} - -// -// StartDMACH6 - This function starts DMA Channel 6. -// -void StartDMACH6(void) -{ - EALLOW; - DmaRegs.CH6.CONTROL.bit.RUN = 1; - EDIS; -} - -// -// NOTE: -// Following functions are required for EMIF as the address is out of -// 22bit range -// - -// -// DMACH1AddrConfig32bit - DMA Channel 1 address configuration for 32bit -// -void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning - // of source buffer - DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer - DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH2AddrConfig32bit - DMA Channel 2 address configuration for 32bit -// -void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning - // of source buffer - DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer - DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH3AddrConfig32bit - DMA Channel 3 address configuration for 32bit -// -void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning - // of source buffer - DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer. - DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH4AddrConfig32bit - DMA Channel 4 address configuration for 32bit -// -void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning - // of source buffer - DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer - DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH5AddrConfig32bit - DMA Channel 5 address configuration for 32bit -// -void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning - // of source buffer - DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer - DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// DMACH6AddrConfig32bit - DMA Channel 6 address configuration for 32bit -// -void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest, - volatile Uint32 *DMA_Source) -{ - EALLOW; - - // - // Set up SOURCE address: - // - DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning - // of source buffer - DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; - - // - // Set up DESTINATION address: - // - DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning - // of destination - // buffer - DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; - - EDIS; -} - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_ECap.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_ECap.c deleted file mode 100644 index d9dcfab62e..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_ECap.c +++ /dev/null @@ -1,147 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_ECap.c -// -// TITLE: F2837xD eCAP Initialization & Support Functions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" - -// -// InitECap - This function initializes the eCAP(s) to a known state. -// -void InitECap(void) -{ - // Initialize eCAP1/2/3/4/5/6 - - //tbd... -} - -// -// InitECapGpio - This function initializes GPIO pins to function as ECAP pins -// Each GPIO pin can be configured as a GPIO pin or up to 3 -// different peripheral functional pins. By default all pins -// come up as GPIO inputs after reset. -// Caution: -// For each eCAP peripheral -// Only one GPIO pin should be enabled for ECAP operation. -// Comment out other unwanted lines. -// -void InitECapGpio() -{ -} - -// -// InitECap1Gpio - Initialize ECAP1 GPIOs -// -void InitECap1Gpio(Uint16 pin) -{ - EALLOW; - InputXbarRegs.INPUT7SELECT = pin; // Set eCAP1 source to GPIO-pin - EDIS; -} - -// -// InitECap2Gpio - Initialize ECAP2 GPIOs -// -void InitECap2Gpio(Uint16 pin) -{ - EALLOW; - InputXbarRegs.INPUT8SELECT = pin; // Set eCAP2 source to GPIO-pin - EDIS; -} - -// -// InitECap3Gpio - Initialize ECAP3 GPIOs -// -void InitECap3Gpio(Uint16 pin) -{ - EALLOW; - InputXbarRegs.INPUT9SELECT = pin; // Set eCAP3 source to GPIO-pin - EDIS; -} - -// -// InitECap4Gpio - Initialize ECAP4 GPIOs -// -void InitECap4Gpio(Uint16 pin) -{ - EALLOW; - InputXbarRegs.INPUT10SELECT = pin; // Set eCAP4 source to GPIO-pin - EDIS; -} - -// -// InitECap5Gpio - Initialize ECAP5 GPIOs -// -void InitECap5Gpio(Uint16 pin) -{ - EALLOW; - InputXbarRegs.INPUT11SELECT = pin; // Set eCAP5 source to GPIO-pin - EDIS; -} - -// -// InitECap6Gpio - Initialize ECAP6 GPIOs -// -void InitECap6Gpio(Uint16 pin) -{ - EALLOW; - InputXbarRegs.INPUT12SELECT = pin; // Set eCAP6 source to GPIO-pin - EDIS; -} - -// -// InitAPwm1Gpio - Initialize EPWM1 GPIOs -// -void InitAPwm1Gpio() -{ - EALLOW; - OutputXbarRegs.OUTPUT3MUX0TO15CFG.bit.MUX0 = 3; // Select ECAP1.OUT on Mux0 - OutputXbarRegs.OUTPUT3MUXENABLE.bit.MUX0 = 1; // Enable MUX0 for ECAP1.OUT - GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 3; // Select OUTPUTXBAR3 on GPIO5 - EDIS; -} - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_EPwm.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_EPwm.c deleted file mode 100644 index 2581fe46c9..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_EPwm.c +++ /dev/null @@ -1,436 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_EPwm.c -// -// TITLE: F2837xD EPwm Initialization & Support Functions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" - -// -// InitEPwmGpio - Initialize all EPWM modules' GPIOs -// -void InitEPwmGpio(void) -{ - InitEPwm1Gpio(); - InitEPwm2Gpio(); - InitEPwm3Gpio(); - InitEPwm4Gpio(); - InitEPwm5Gpio(); - InitEPwm6Gpio(); - InitEPwm7Gpio(); - InitEPwm8Gpio(); - InitEPwm9Gpio(); - InitEPwm10Gpio(); - InitEPwm11Gpio(); - InitEPwm12Gpio(); -} - -// -// InitEPwm1Gpio - Initialize EPWM1 GPIOs -// -void InitEPwm1Gpio(void) -{ - EALLOW; - - // - // Disable internal pull-up for the selected output pins - // for reduced power consumption - // Pull-ups can be enabled or disabled by the user. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1; // Disable pull-up on GPIO0 (EPWM1A) - GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; // Disable pull-up on GPIO1 (EPWM1B) - // GpioCtrlRegs.GPEPUD.bit.GPIO145 = 1; // Disable pull-up on GPIO145 (EPWM1A) - // GpioCtrlRegs.GPEPUD.bit.GPIO146 = 1; // Disable pull-up on GPIO146 (EPWM1B) - - // - // Configure EPWM-1 pins using GPIO regs - // This specifies which of the possible GPIO pins will be EPWM1 functional - // pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A - GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B - // GpioCtrlRegs.GPEMUX2.bit.GPIO145 = 1; // Configure GPIO145 as EPWM1A - // GpioCtrlRegs.GPEMUX2.bit.GPIO146 = 1; // Configure GPIO0146 as EPWM1B - - EDIS; -} - -// -// InitEPwm2Gpio - Initialize EPWM2 GPIOs -// -void InitEPwm2Gpio(void) -{ - EALLOW; - - // - // Disable internal pull-up for the selected output pins - // for reduced power consumption - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Disable pull-up on GPIO2 (EPWM2A) - GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; // Disable pull-up on GPIO3 (EPWM2B) - // GpioCtrlRegs.GPEPUD.bit.GPIO147 = 1; // Disable pull-up on GPIO147 (EPWM2A) - // GpioCtrlRegs.GPEPUD.bit.GPIO148 = 1; // Disable pull-up on GPIO148 (EPWM2B) - - // - // Configure EPwm-2 pins using GPIO regs - // This specifies which of the possible GPIO pins will be EPWM2 functional pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A - GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B - // GpioCtrlRegs.GPEMUX2.bit.GPIO147 = 1; // Configure GPIO147 as EPWM2A - // GpioCtrlRegs.GPEMUX2.bit.GPIO148 = 1; // Configure GPIO148 as EPWM2B - - EDIS; -} - -// -// InitEPwm3Gpio - Initialize EPWM3 GPIOs -// -void InitEPwm3Gpio(void) -{ - EALLOW; - - // - // Disable internal pull-up for the selected output pins - // for reduced power consumption - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAPUD.bit.GPIO4 = 1; // Disable pull-up on GPIO4 (EPWM3A) - GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1; // Disable pull-up on GPIO5 (EPWM3B) - // GpioCtrlRegs.GPEPUD.bit.GPIO149 = 1; // Disable pull-up on GPIO149 (EPWM3A) - // GpioCtrlRegs.GPEPUD.bit.GPIO150 = 1; // Disable pull-up on GPIO150 (EPWM3B) - - // - // Configure EPwm-3 pins using GPIO regs - // This specifies which of the possible GPIO pins will be EPWM3 functional pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A - GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B - // GpioCtrlRegs.GPEMUX2.bit.GPIO149 = 1; // Configure GPIO149 as EPWM3A - // GpioCtrlRegs.GPEMUX2.bit.GPIO150 = 1; // Configure GPIO150 as EPWM3B - - EDIS; -} - -// -// InitEPwm4Gpio - Initialize EPWM4 GPIOs -// -void InitEPwm4Gpio(void) -{ - EALLOW; - - // - // Disable internal pull-up for the selected output pins - // for reduced power consumption - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up on GPIO6 (EPWM4A) - GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; // Disable pull-up on GPIO7 (EPWM4B) - // GpioCtrlRegs.GPEPUD.bit.GPIO151 = 1; // Disable pull-up on GPIO151 (EPWM4A) - // GpioCtrlRegs.GPEPUD.bit.GPIO152 = 1; // Disable pull-up on GPIO152 (EPWM4B) - - // - // Configure EPWM-4 pins using GPIO regs - // This specifies which of the possible GPIO pins will be EPWM4 functional - // pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A - GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B - // GpioCtrlRegs.GPEMUX2.bit.GPIO151 = 1; // Configure GPIO151 as EPWM4A - // GpioCtrlRegs.GPEMUX2.bit.GPIO152 = 1; // Configure GPIO152 as EPWM4B - - EDIS; -} - -// -// InitEPwm5Gpio - Initialize EPWM5 GPIOs -// -void InitEPwm5Gpio(void) -{ - EALLOW; - // - // Disable internal pull-up for the selected output pins - // for reduced power consumption - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; // Disable pull-up on GPIO8 (EPWM5A) - GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; // Disable pull-up on GPIO9 (EPWM5B) - // GpioCtrlRegs.GPEPUD.bit.GPIO153 = 1; // Disable pull-up on GPIO153 (EPWM5A) - // GpioCtrlRegs.GPEPUD.bit.GPIO154 = 1; // Disable pull-up on GPIO154 (EPWM5B) - - // - // Configure EPWM-5 pins using GPIO regs - // This specifies which of the possible GPIO pins will be EPWM5 functional - // pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A - GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B - // GpioCtrlRegs.GPEMUX2.bit.GPIO153 = 1; // Configure GPIO153 as EPWM5A - // GpioCtrlRegs.GPEMUX2.bit.GPIO154 = 1; // Configure GPIO0154 as EPWM5B - - EDIS; -} - -// -// InitEPwm6Gpio - Initialize EPWM6 GPIOs -// -void InitEPwm6Gpio(void) -{ - EALLOW; - // - // Disable internal pull-up for the selected output pins - // for reduced power consumption - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (EPWM6A) - GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (EPWM6B) - // GpioCtrlRegs.GPEPUD.bit.GPIO155 = 1; // Disable pull-up on GPIO155 (EPWM6A) - // GpioCtrlRegs.GPEPUD.bit.GPIO156 = 1; // Disable pull-up on GPIO156 (EPWM6B) - - // - // Configure EPWM-6 pins using GPIO regs - // This specifies which of the possible GPIO pins will be EPWM6 functional - // pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A - GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B - // GpioCtrlRegs.GPEMUX2.bit.GPIO155 = 1; // Configure GPIO155 as EPWM6A - // GpioCtrlRegs.GPEMUX2.bit.GPIO156 = 1; // Configure GPIO156 as EPWM6B - - EDIS; -} - -// -// InitEPwm7Gpio - Initialize EPWM7 GPIOs -// -void InitEPwm7Gpio(void) -{ - EALLOW; - - // - // Disable internal pull-up for the selected output pins - // for reduced power consumption - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (EPWM7A) - GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (EPWM7B) - // GpioCtrlRegs.GPEPUD.bit.GPIO157 = 1; // Disable pull-up on GPIO157 (EPWM7A) - // GpioCtrlRegs.GPEPUD.bit.GPIO158 = 1; // Disable pull-up on GPIO158 (EPWM7B) - - // - // Configure EPWM-6 pins using GPIO regs - // This specifies which of the possible GPIO pins will be EPWM6 functional - // pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EPWM7A - GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EPWM7B - // GpioCtrlRegs.GPEMUX2.bit.GPIO157 = 1; // Configure GPIO157 as EPWM7A - // GpioCtrlRegs.GPEMUX2.bit.GPIO158 = 1; // Configure GPIO158 as EPWM7B - - EDIS; -} - -// -// InitEPwm8Gpio - Initialize EPWM8 GPIOs -// -void InitEPwm8Gpio(void) -{ - EALLOW; - // - // Disable internal pull-up for the selected output pins - // for reduced power consumption - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; // Disable pull-up on GPIO14 (EPWM8A) - GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1; // Disable pull-up on GPIO15 (EPWM8B) -// GpioCtrlRegs.GPEPUD.bit.GPIO159 = 1; // Disable pull-up on GPIO159 (EPWM8A) -// GpioCtrlRegs.GPFPUD.bit.GPIO160 = 1; // Disable pull-up on GPIO160 (EPWM8B) - - // - // Configure EPWM-6 pins using GPIO regs - // This specifies which of the possible GPIO pins will be EPWM6 functional - // pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as EPWM8A - GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as EPWM8B - // GpioCtrlRegs.GPEMUX2.bit.GPIO159 = 1; // Configure GPIO159 as EPWM8A - // GpioCtrlRegs.GPFMUX1.bit.GPIO160 = 1; // Configure GPIO160 as EPWM8B - - EDIS; -} - -// -// InitEPwm9Gpio - Initialize EPWM9 GPIOs -// -void InitEPwm9Gpio(void) -{ - EALLOW; - // - // Disable internal pull-up for the selected output pins - // for reduced power consumption - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPFPUD.bit.GPIO161 = 1; // Disable pull-up on GPIO161 (EPWM9A) - GpioCtrlRegs.GPFPUD.bit.GPIO162 = 1; // Disable pull-up on GPIO162 (EPWM9B) - - // - // Configure EPWM-6 pins using GPIO regs - // This specifies which of the possible GPIO pins will be EPWM6 functional - // pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPFMUX1.bit.GPIO161 = 1; // Configure GPIO161 as EPWM9A - GpioCtrlRegs.GPFMUX1.bit.GPIO162 = 1; // Configure GPIO162 as EPWM9B - - EDIS; -} - -// -// InitEPwm10Gpio - Initialize EPWM10 GPIOs -// -void InitEPwm10Gpio(void) -{ - EALLOW; - // - // Disable internal pull-up for the selected output pins - // for reduced power consumption - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPFPUD.bit.GPIO163 = 1; // Disable pull-up on GPIO163 (EPWM10A) - GpioCtrlRegs.GPFPUD.bit.GPIO164 = 1; // Disable pull-up on GPIO164 (EPWM10B) - - // - // Configure EPWM-6 pins using GPIO regs - // This specifies which of the possible GPIO pins will be EPWM6 functional - // pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPFMUX1.bit.GPIO163 = 1; // Configure GPIO163 as EPWM10A - GpioCtrlRegs.GPFMUX1.bit.GPIO164 = 1; // Configure GPIO164 as EPWM10B - - EDIS; -} - -// -// InitEPwm11Gpio - Initialize EPWM11 GPIOs -// -void InitEPwm11Gpio(void) -{ - EALLOW; - // - // Disable internal pull-up for the selected output pins - // for reduced power consumption - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPFPUD.bit.GPIO165 = 1; // Disable pull-up on GPIO165 (EPWM11A) - GpioCtrlRegs.GPFPUD.bit.GPIO166 = 1; // Disable pull-up on GPIO166 (EPWM11B) - - // - // Configure EPWM-6 pins using GPIO regs - // This specifies which of the possible GPIO pins will be EPWM6 functional - // pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPFMUX1.bit.GPIO165 = 1; // Configure GPIO165 as EPWM11A - GpioCtrlRegs.GPFMUX1.bit.GPIO166 = 1; // Configure GPIO166 as EPWM11B - - EDIS; -} - -// -// InitEPwm12Gpio - Initialize EPWM12 GPIOs -// -void InitEPwm12Gpio(void) -{ - EALLOW; - // - // Disable internal pull-up for the selected output pins - // for reduced power consumption - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPFPUD.bit.GPIO167 = 1; // Disable pull-up on GPIO167 (EPWM12A) - GpioCtrlRegs.GPFPUD.bit.GPIO168 = 1; // Disable pull-up on GPIO168 (EPWM12B) - - // - // Configure EPWM-6 pins using GPIO regs - // This specifies which of the possible GPIO pins will be EPWM6 functional - // pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPFMUX1.bit.GPIO167 = 1; // Configure GPIO167 as EPWM12A - GpioCtrlRegs.GPFMUX1.bit.GPIO168 = 1; // Configure GPIO168 as EPWM12B - - EDIS; -} diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_EQep.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_EQep.c deleted file mode 100644 index 90629e6f40..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_EQep.c +++ /dev/null @@ -1,389 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_EQep.c -// -// TITLE: F2837xD eQEP Initialization & Support Functions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" - -// -// InitEQep - This function initializes the eQEP(s) to a known state. -// -void InitEQep(void) -{ - // Initialize eQEP1 - - //tbd... -} - -// -// InitEQepGpio - This function initializes GPIO pins to function as eQEP pins -// Each GPIO pin can be configured as a GPIO pin or up to 3 -// different peripheral functional pins. By default all pins -// come up as GPIO inputs after reset. -// Caution: -// For each eQEP peripheral -// Only one GPIO pin should be enabled for EQEPxA operation. -// Only one GPIO pin should be enabled for EQEPxB operation. -// Only one GPIO pin should be enabled for EQEPxS operation. -// Only one GPIO pin should be enabled for EQEPxI operation. -// Comment out other unwanted lines. -// -void InitEQepGpio() -{ - InitEQep1Gpio(); - InitEQep2Gpio(); - InitEQep3Gpio(); -} - -// -// InitEQep1Gpio - Initialize EQEP-1 GPIOs -// Caution: -// For each eQEP peripheral -// Only one GPIO pin should be enabled for EQEPxA operation. -// Only one GPIO pin should be enabled for EQEPxB operation. -// Only one GPIO pin should be enabled for EQEPxS operation. -// Only one GPIO pin should be enabled for EQEPxI operation. -// Comment out other unwanted lines. -// -void InitEQep1Gpio(void) -{ - EALLOW; - - // - // Disable internal pull-up for the selected output pins - // for reduced power consumption - // Pull-ups can be enabled or disabled by the user. - // Comment out other unwanted lines. - // - -// GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (EQEP1A) -// GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (EQEP1B) -// GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (EQEP1S) -// GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (EQEP1I) - - GpioCtrlRegs.GPAPUD.bit.GPIO20 = 1; // Disable pull-up on GPIO20 (EQEP1A) - GpioCtrlRegs.GPAPUD.bit.GPIO21 = 1; // Disable pull-up on GPIO21 (EQEP1B) - GpioCtrlRegs.GPAPUD.bit.GPIO22 = 1; // Disable pull-up on GPIO22 (EQEP1S) - GpioCtrlRegs.GPAPUD.bit.GPIO23 = 1; // Disable pull-up on GPIO23 (EQEP1I) - -// GpioCtrlRegs.GPBPUD.bit.GPIO50 = 1; // Disable pull-up on GPIO50 (EQEP1A) -// GpioCtrlRegs.GPBPUD.bit.GPIO51 = 1; // Disable pull-up on GPIO51 (EQEP1B) -// GpioCtrlRegs.GPBPUD.bit.GPIO52 = 1; // Disable pull-up on GPIO52 (EQEP1S) -// GpioCtrlRegs.GPBPUD.bit.GPIO53 = 1; // Disable pull-up on GPIO53 (EQEP1I) - -// GpioCtrlRegs.GPDPUD.bit.GPIO96 = 1; // Disable pull-up on GPIO96 (EQEP1A) -// GpioCtrlRegs.GPDPUD.bit.GPIO97 = 1; // Disable pull-up on GPIO97 (EQEP1B) -// GpioCtrlRegs.GPDPUD.bit.GPIO98 = 1; // Disable pull-up on GPIO98 (EQEP1S) -// GpioCtrlRegs.GPDPUD.bit.GPIO99 = 1; // Disable pull-up on GPIO99 (EQEP1I) - - // - // Synchronize inputs to SYSCLK - // Synchronization can be enabled or disabled by the user. - // Comment out other unwanted lines. - // - -// GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 0; // Sync GPIO10 to SYSCLK (EQEP1A) -// GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0; // Sync GPIO11 to SYSCLK (EQEP1B) -// GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 0; // Sync GPIO12 to SYSCLK (EQEP1S) -// GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 0; // Sync GPIO13 to SYSCLK (EQEP1I) - - GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Sync GPIO20 to SYSCLK (EQEP1A) - GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Sync GPIO21 to SYSCLK (EQEP1B) - GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Sync GPIO22 to SYSCLK (EQEP1S) - GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Sync GPIO23 to SYSCLK (EQEP1I) - -// GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; // Sync GPIO50 to SYSCLK (EQEP1A) -// GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; // Sync GPIO51 to SYSCLK (EQEP1B) -// GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 0; // Sync GPIO52 to SYSCLK (EQEP1S) -// GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 0; // Sync GPIO53 to SYSCLK (EQEP1I) - -// GpioCtrlRegs.GPDQSEL1.bit.GPIO96 = 0; // Sync GPIO96 to SYSCLK (EQEP1A) -// GpioCtrlRegs.GPDQSEL1.bit.GPIO97 = 0; // Sync GPIO97 to SYSCLK (EQEP1B) -// GpioCtrlRegs.GPDQSEL1.bit.GPIO98 = 0; // Sync GPIO98 to SYSCLK (EQEP1S) -// GpioCtrlRegs.GPDQSEL1.bit.GPIO99 = 0; // Sync GPIO99 to SYSCLK (EQEP1I) - - // - // Configure EQEP-1 pins using GPIO regs - // This specifies which of the possible GPIO pins will be EQEP1 functional - // pins. - // Comment out other unwanted lines. - // - -// GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EQEP1A -// GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EQEP1A -// GpioCtrlRegs.GPAGMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EQEP1B -// GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EQEP1B -// GpioCtrlRegs.GPAGMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EQEP1S -// GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EQEP1S -// GpioCtrlRegs.GPAGMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EQEP1I -// GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EQEP1I - - GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A - GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B - GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S - GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I - -// GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // Configure GPIO50 as EQEP1A -// GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // Configure GPIO51 as EQEP1B -// GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 1; // Configure GPIO52 as EQEP1S -// GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1; // Configure GPIO53 as EQEP1I - -// GpioCtrlRegs.GPDGMUX1.bit.GPIO96 = 1; // Configure GPIO96 as EQEP1A -// GpioCtrlRegs.GPDMUX1.bit.GPIO96 = 1; // Configure GPIO96 as EQEP1A -// GpioCtrlRegs.GPDGMUX1.bit.GPIO97 = 1; // Configure GPIO97 as EQEP1B -// GpioCtrlRegs.GPDMUX1.bit.GPIO97 = 1; // Configure GPIO97 as EQEP1B -// GpioCtrlRegs.GPDGMUX1.bit.GPIO98 = 1; // Configure GPIO98 as EQEP1S -// GpioCtrlRegs.GPDMUX1.bit.GPIO98 = 1; // Configure GPIO98 as EQEP1S -// GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 1; // Configure GPIO99 as EQEP1I -// GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 1; // Configure GPIO99 as EQEP1I - - EDIS; -} - -// -// InitEQep2Gpio - Initialize EQEP-2 GPIOs -// -void InitEQep2Gpio(void) -{ - EALLOW; - - // - // Disable internal pull-up for the selected output pins - // for reduced power consumption - // Pull-ups can be enabled or disabled by the user. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAPUD.bit.GPIO24 = 1; // Disable pull-up on GPIO24 (EQEP2A) - GpioCtrlRegs.GPAPUD.bit.GPIO25 = 1; // Disable pull-up on GPIO25 (EQEP2B) - GpioCtrlRegs.GPAPUD.bit.GPIO26 = 1; // Disable pull-up on GPIO26 (EQEP2S) - GpioCtrlRegs.GPAPUD.bit.GPIO27 = 1; // Disable pull-up on GPIO27 (EQEP2I) - -// GpioCtrlRegs.GPBPUD.bit.GPIO54 = 1; // Disable pull-up on GPIO54 (EQEP2A) -// GpioCtrlRegs.GPBPUD.bit.GPIO55 = 1; // Disable pull-up on GPIO55 (EQEP2B) -// GpioCtrlRegs.GPBPUD.bit.GPIO56 = 1; // Disable pull-up on GPIO56 (EQEP2S) -// GpioCtrlRegs.GPBPUD.bit.GPIO57 = 1; // Disable pull-up on GPIO57 (EQEP2I) - -// GpioCtrlRegs.GPCPUD.bit.GPIO78 = 1; // Disable pull-up on GPIO78 (EQEP2A) -// GpioCtrlRegs.GPCPUD.bit.GPIO79 = 1; // Disable pull-up on GPIO79 (EQEP2B) -// GpioCtrlRegs.GPCPUD.bit.GPIO80 = 1; // Disable pull-up on GPIO80 (EQEP2S) -// GpioCtrlRegs.GPCPUD.bit.GPIO81 = 1; // Disable pull-up on GPIO81 (EQEP2I) - -// GpioCtrlRegs.GPDPUD.bit.GPIO100 = 1; // Disable pull-up on GPIO100 (EQEP2A) -// GpioCtrlRegs.GPDPUD.bit.GPIO101 = 1; // Disable pull-up on GPIO101 (EQEP2B) -// GpioCtrlRegs.GPDPUD.bit.GPIO102 = 1; // Disable pull-up on GPIO102 (EQEP2S) -// GpioCtrlRegs.GPDPUD.bit.GPIO103 = 1; // Disable pull-up on GPIO103 (EQEP2I) - - // - // Synchronize inputs to SYSCLK - // Synchronization can be enabled or disabled by the user. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Sync GPIO24 to SYSCLK (EQEP2A) - GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Sync GPIO25 to SYSCLK (EQEP2B) - GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Sync GPIO26 to SYSCLK (EQEP2S) - GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Sync GPIO27 to SYSCLK (EQEP2I) - -// GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 0; // Sync GPIO54 to SYSCLK (EQEP2A) -// GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 0; // Sync GPIO55 to SYSCLK (EQEP2B) -// GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 0; // Sync GPIO56 to SYSCLK (EQEP2S) -// GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 0; // Sync GPIO57 to SYSCLK (EQEP2I) - -// GpioCtrlRegs.GPCQSEL1.bit.GPIO78 = 0; // Sync GPIO78 to SYSCLK (EQEP2A) -// GpioCtrlRegs.GPCQSEL1.bit.GPIO79 = 0; // Sync GPIO79 to SYSCLK (EQEP2B) -// GpioCtrlRegs.GPCQSEL2.bit.GPIO80 = 0; // Sync GPIO80 to SYSCLK (EQEP2S) -// GpioCtrlRegs.GPCQSEL2.bit.GPIO81 = 0; // Sync GPIO81 to SYSCLK (EQEP2I) - -// GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 0; // Sync GPIO100 to SYSCLK (EQEP2A) -// GpioCtrlRegs.GPDQSEL1.bit.GPIO101 = 0; // Sync GPIO101 to SYSCLK (EQEP2B) -// GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 0; // Sync GPIO102 to SYSCLK (EQEP2S) -// GpioCtrlRegs.GPDQSEL1.bit.GPIO103 = 0; // Sync GPIO103 to SYSCLK (EQEP2I) - - // - // Configure EQEP-1 pins using GPIO regs - // This specifies which of the possible GPIO pins will be EQEP2 functional pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A - GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B - GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2S - GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2I - -// GpioCtrlRegs.GPBGMUX2.bit.GPIO54 = 1; // Configure GPIO54 as EQEP2A -// GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as EQEP2A -// GpioCtrlRegs.GPBGMUX2.bit.GPIO55 = 1; // Configure GPIO55 as EQEP2B -// GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as EQEP2B -// GpioCtrlRegs.GPBGMUX2.bit.GPIO56 = 1; // Configure GPIO56 as EQEP2S -// GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as EQEP2S -// GpioCtrlRegs.GPBGMUX2.bit.GPIO57 = 1; // Configure GPIO57 as EQEP2I -// GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as EQEP2I - -// GpioCtrlRegs.GPCGMUX1.bit.GPIO78 = 1; // Configure GPIO78 as EQEP2A -// GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 2; // Configure GPIO78 as EQEP2A -// GpioCtrlRegs.GPCGMUX1.bit.GPIO79 = 1; // Configure GPIO79 as EQEP2B -// GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 2; // Configure GPIO79 as EQEP2B -// GpioCtrlRegs.GPCGMUX2.bit.GPIO80 = 1; // Configure GPIO80 as EQEP2S -// GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 2; // Configure GPIO80 as EQEP2S -// GpioCtrlRegs.GPCGMUX2.bit.GPIO81 = 1; // Configure GPIO81 as EQEP2I -// GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 2; // Configure GPIO81 as EQEP2I - -// GpioCtrlRegs.GPDGMUX1.bit.GPIO100 = 1; // Configure GPIO100 as EQEP2A -// GpioCtrlRegs.GPDMUX1.bit.GPIO100 = 1; // Configure GPIO100 as EQEP2A -// GpioCtrlRegs.GPDGMUX1.bit.GPIO101 = 1; // Configure GPIO101 as EQEP2B -// GpioCtrlRegs.GPDMUX1.bit.GPIO101 = 1; // Configure GPIO101 as EQEP2B -// GpioCtrlRegs.GPDGMUX1.bit.GPIO102 = 1; // Configure GPIO102 as EQEP2S -// GpioCtrlRegs.GPDMUX1.bit.GPIO102 = 1; // Configure GPIO102 as EQEP2S -// GpioCtrlRegs.GPDGMUX1.bit.GPIO103 = 1; // Configure GPIO103 as EQEP2I -// GpioCtrlRegs.GPDMUX1.bit.GPIO103 = 1; // Configure GPIO103 as EQEP2I - - EDIS; -} - -// -// InitEQep3Gpio - Initialize EQEP-3 GPIOs -// -void InitEQep3Gpio(void) -{ - EALLOW; - - // - // Disable internal pull-up for the selected output pins - // for reduced power consumption - // Pull-ups can be enabled or disabled by the user. - // Comment out other unwanted lines. - // - -// GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up on GPIO6 (EQEP3A) -// GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; // Disable pull-up on GPIO7 (EQEP3B) -// GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; // Disable pull-up on GPIO8 (EQEP3S) -// GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; // Disable pull-up on GPIO9 (EQEP3I) - - GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Disable pull-up on GPIO28 (EQEP3A) - GpioCtrlRegs.GPAPUD.bit.GPIO29 = 1; // Disable pull-up on GPIO29 (EQEP3B) - GpioCtrlRegs.GPAPUD.bit.GPIO30 = 1; // Disable pull-up on GPIO30 (EQEP3S) - GpioCtrlRegs.GPAPUD.bit.GPIO31 = 1; // Disable pull-up on GPIO31 (EQEP3I) - -// GpioCtrlRegs.GPBPUD.bit.GPIO62 = 1; // Disable pull-up on GPIO62 (EQEP3A) -// GpioCtrlRegs.GPBPUD.bit.GPIO63 = 1; // Disable pull-up on GPIO63 (EQEP3B) -// GpioCtrlRegs.GPCPUD.bit.GPIO64 = 1; // Disable pull-up on GPIO64 (EQEP3S) -// GpioCtrlRegs.GPCPUD.bit.GPIO65 = 1; // Disable pull-up on GPIO65 (EQEP3I) - -// GpioCtrlRegs.GPDPUD.bit.GPIO104 = 1; // Disable pull-up on GPIO104 (EQEP3A) -// GpioCtrlRegs.GPDPUD.bit.GPIO105 = 1; // Disable pull-up on GPIO105 (EQEP3B) -// GpioCtrlRegs.GPDPUD.bit.GPIO106 = 1; // Disable pull-up on GPIO106 (EQEP3S) -// GpioCtrlRegs.GPDPUD.bit.GPIO107 = 1; // Disable pull-up on GPIO107 (EQEP3I) - - // - // Synchronize inputs to SYSCLK - // Synchronization can be enabled or disabled by the user. - // Comment out other unwanted lines. - // - -// GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0; // Sync GPIO6 to SYSCLK (EQEP3A) -// GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Sync GPIO7 to SYSCLK (EQEP3B) -// GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 0; // Sync GPIO8 to SYSCLK (EQEP3S) -// GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0; // Sync GPIO9 to SYSCLK (EQEP3I) - - GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 0; // Sync GPIO28 to SYSCLK (EQEP3A) - GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 0; // Sync GPIO29 to SYSCLK (EQEP3B) - GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 0; // Sync GPIO30 to SYSCLK (EQEP3S) - GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 0; // Sync GPIO31 to SYSCLK (EQEP3I) - -// GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 0; // Sync GPIO62 to SYSCLK (EQEP3A) -// GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 0; // Sync GPIO63 to SYSCLK (EQEP3B) -// GpioCtrlRegs.GPCQSEL1.bit.GPIO64 = 0; // Sync GPIO64 to SYSCLK (EQEP3S) -// GpioCtrlRegs.GPCQSEL1.bit.GPIO65 = 0; // Sync GPIO65 to SYSCLK (EQEP3I) - -// GpioCtrlRegs.GPDQSEL1.bit.GPIO104 = 0; // Sync GPIO104 to SYSCLK (EQEP3A) -// GpioCtrlRegs.GPDQSEL1.bit.GPIO105 = 0; // Sync GPIO105 to SYSCLK (EQEP3B) -// GpioCtrlRegs.GPDQSEL1.bit.GPIO106 = 0; // Sync GPIO106 to SYSCLK (EQEP3S) -// GpioCtrlRegs.GPDQSEL1.bit.GPIO107 = 0; // Sync GPIO107 to SYSCLK (EQEP3I) - - // - // Configure EQEP-1 pins using GPIO regs - // This specifies which of the possible GPIO pins will be EQEP3 functional pins. - // Comment out other unwanted lines. - // - -// GpioCtrlRegs.GPAGMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EQEP3A -// GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EQEP3A -// GpioCtrlRegs.GPAGMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EQEP3B -// GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EQEP3B -// GpioCtrlRegs.GPAGMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EQEP3S -// GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EQEP3S -// GpioCtrlRegs.GPAGMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EQEP3I -// GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EQEP3I - - GpioCtrlRegs.GPAGMUX2.bit.GPIO28 = 1; // Configure GPIO28 as EQEP3A - GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 2; // Configure GPIO28 as EQEP3A - GpioCtrlRegs.GPAGMUX2.bit.GPIO29 = 1; // Configure GPIO29 as EQEP3B - GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 2; // Configure GPIO29 as EQEP3B - GpioCtrlRegs.GPAGMUX2.bit.GPIO30 = 1; // Configure GPIO30 as EQEP3S - GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 2; // Configure GPIO30 as EQEP3S - GpioCtrlRegs.GPAGMUX2.bit.GPIO31 = 1; // Configure GPIO31 as EQEP3I - GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 2; // Configure GPIO31 as EQEP3I - -// GpioCtrlRegs.GPBGMUX2.bit.GPIO62 = 1; // Configure GPIO62 as EQEP3A -// GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 as EQEP3A -// GpioCtrlRegs.GPBGMUX2.bit.GPIO63 = 1; // Configure GPIO63 as EQEP3B -// GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 as EQEP3B -// GpioCtrlRegs.GPCGMUX1.bit.GPIO64 = 1; // Configure GPIO64 as EQEP3S -// GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 1; // Configure GPIO64 as EQEP3S -// GpioCtrlRegs.GPCGMUX1.bit.GPIO65 = 1; // Configure GPIO65 as EQEP3I -// GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 1; // Configure GPIO65 as EQEP3I - -// GpioCtrlRegs.GPDGMUX1.bit.GPIO104 = 1; // Configure GPIO104 as EQEP3A -// GpioCtrlRegs.GPDMUX1.bit.GPIO104 = 1; // Configure GPIO104 as EQEP3A -// GpioCtrlRegs.GPDGMUX1.bit.GPIO105 = 1; // Configure GPIO105 as EQEP3B -// GpioCtrlRegs.GPDMUX1.bit.GPIO105 = 1; // Configure GPIO105 as EQEP3B -// GpioCtrlRegs.GPDGMUX1.bit.GPIO106 = 1; // Configure GPIO106 as EQEP3S -// GpioCtrlRegs.GPDMUX1.bit.GPIO106 = 1; // Configure GPIO106 as EQEP3S -// GpioCtrlRegs.GPDGMUX1.bit.GPIO107 = 1; // Configure GPIO107 as EQEP3I -// GpioCtrlRegs.GPDMUX1.bit.GPIO107 = 1; // Configure GPIO107 as EQEP3I - - EDIS; -} - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Emif.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Emif.c deleted file mode 100644 index 0f8ff9d52b..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Emif.c +++ /dev/null @@ -1,458 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Emif.c -// -// TITLE: F2837xD EMIF Initialization & Support Functions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" - -// -// Emif1Initialize - This function initializes the EMIF1 to a known state. -// -void Emif1Initialize(void) -{ - EALLOW; - // - // Perform a Module soft reset on EMIF - // -#ifdef CPU1 - DevCfgRegs.SOFTPRES1.all = 0x1; - __asm (" nop"); - DevCfgRegs.SOFTPRES1.all = 0x0; -#endif - EDIS; -} - -// -// Emif2Initialize - This function initializes the EMIF2 to a known state. -// -void Emif2Initialize(void) -{ - EALLOW; - // - // Perform a Module soft reset on EMIF - // -#ifdef CPU1 - DevCfgRegs.SOFTPRES1.all = 0x2; - __asm (" nop"); - DevCfgRegs.SOFTPRES1.all = 0x0; -#endif - EDIS; -} - -// -// ASync_wait_config - Async wait configuration function -// -void ASync_wait_config(Uint16 inst, Uint16 wait_count, Uint16 wait_polarity) -{ - if (inst == 0) - { - // - // 7:0 Maximum Extended Wait cycles. - // - Emif1Regs.ASYNC_WCCR.bit.MAX_EXT_WAIT = wait_count; - - // - // 28 Wait Polarity for pad_wait_i[0]. - // - Emif1Regs.ASYNC_WCCR.bit.WP0 = wait_polarity; - } - else - { - // - // 7:0 Maximum Extended Wait cycles. - // - Emif2Regs.ASYNC_WCCR.bit.MAX_EXT_WAIT = wait_count; - - // - // 28 Wait Polarity for pad_wait_i[0]. - // - Emif2Regs.ASYNC_WCCR.bit.WP0 = wait_polarity; - } -} - -// -// ASync_cs2_config - Async CS2 Configuration -// -void ASync_cs2_config(Uint16 inst, Uint16 async_mem_data_width, - Uint16 turn_around_time, Uint16 r_hold_time, - Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold, - Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait, - Uint16 strobe_sel) -{ - if (inst == 0) - { - // - // 1:0 Asynchronous Memory Size. - // 3:2 Turn Around cycles. - // 6:4 Read Strobe Hold cycles. - // 12:7 Read Strobe Duration cycles. - // 16:13 Read Strobe Setup cycles. - // 19:17 Write Strobe Hold cycles. - // 25:20 Write Strobe Duration cycles. - // 29:26 Write Strobe Setup cycles. - // 30 Extend Wait mode. - // 31 Select Strobe mode. - // - Emif1Regs.ASYNC_CS2_CR.bit.ASIZE = async_mem_data_width; - Emif1Regs.ASYNC_CS2_CR.bit.TA= turn_around_time; - Emif1Regs.ASYNC_CS2_CR.bit.R_HOLD= r_hold_time; - Emif1Regs.ASYNC_CS2_CR.bit.R_STROBE = r_strobe_time; - Emif1Regs.ASYNC_CS2_CR.bit.R_SETUP = r_setup; - Emif1Regs.ASYNC_CS2_CR.bit.W_HOLD = w_hold; - Emif1Regs.ASYNC_CS2_CR.bit.W_STROBE = w_strobe; - Emif1Regs.ASYNC_CS2_CR.bit.W_SETUP = w_setup; - Emif1Regs.ASYNC_CS2_CR.bit.EW = extend_wait; - Emif1Regs.ASYNC_CS2_CR.bit.SS = strobe_sel; - } - else - { - // - // 1:0 Asynchronous Memory Size. - // 3:2 Turn Around cycles. - // 6:4 Read Strobe Hold cycles. - // 12:7 Read Strobe Duration cycles. - // 16:13 Read Strobe Setup cycles. - // 19:17 Write Strobe Hold cycles. - // 25:20 Write Strobe Duration cycles. - // 29:26 Write Strobe Setup cycles. - // 30 Extend Wait mode. - // 31 Select Strobe mode. - // - Emif2Regs.ASYNC_CS2_CR.bit.ASIZE = async_mem_data_width; - Emif2Regs.ASYNC_CS2_CR.bit.TA= turn_around_time; - Emif2Regs.ASYNC_CS2_CR.bit.R_HOLD= r_hold_time; - Emif2Regs.ASYNC_CS2_CR.bit.R_STROBE = r_strobe_time; - Emif2Regs.ASYNC_CS2_CR.bit.R_SETUP = r_setup; - Emif2Regs.ASYNC_CS2_CR.bit.W_HOLD = w_hold; - Emif2Regs.ASYNC_CS2_CR.bit.W_STROBE = w_strobe; - Emif2Regs.ASYNC_CS2_CR.bit.W_SETUP = w_setup; - Emif2Regs.ASYNC_CS2_CR.bit.EW = extend_wait; - Emif2Regs.ASYNC_CS2_CR.bit.SS = strobe_sel; - } -} - -// -// ASync_cs3_config - Async CS3 Configuration -// -void ASync_cs3_config(Uint16 inst, Uint16 async_mem_data_width, - Uint16 turn_around_time, Uint16 r_hold_time, - Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold, - Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait, - Uint16 strobe_sel) -{ - // - // 1:0 Asynchronous Memory Size. - // 3:2 Turn Around cycles. - // 6:4 Read Strobe Hold cycles. - // 12:7 Read Strobe Duration cycles. - // 16:13 Read Strobe Setup cycles. - // 19:17 Write Strobe Hold cycles. - // 25:20 Write Strobe Duration cycles. - // 29:26 Write Strobe Setup cycles. - // 30 Extend Wait mode. - // 31 Select Strobe mode. - // - Emif1Regs.ASYNC_CS3_CR.bit.ASIZE = async_mem_data_width; - Emif1Regs.ASYNC_CS3_CR.bit.TA= turn_around_time; - Emif1Regs.ASYNC_CS3_CR.bit.R_HOLD= r_hold_time; - Emif1Regs.ASYNC_CS3_CR.bit.R_STROBE = r_strobe_time; - Emif1Regs.ASYNC_CS3_CR.bit.R_SETUP = r_setup; - Emif1Regs.ASYNC_CS3_CR.bit.W_HOLD = w_hold; - Emif1Regs.ASYNC_CS3_CR.bit.W_STROBE = w_strobe; - Emif1Regs.ASYNC_CS3_CR.bit.W_SETUP = w_setup; - Emif1Regs.ASYNC_CS3_CR.bit.EW = extend_wait; - Emif1Regs.ASYNC_CS3_CR.bit.SS = strobe_sel; -} - -// -// ASync_cs4_config - Async CS4 Configuration -// -void ASync_cs4_config(Uint16 inst, Uint16 async_mem_data_width, - Uint16 turn_around_time, Uint16 r_hold_time, - Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold, - Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait, - Uint16 strobe_sel) -{ - // - // 1:0 Asynchronous Memory Size. - // 3:2 Turn Around cycles. - // 6:4 Read Strobe Hold cycles. - // 12:7 Read Strobe Duration cycles. - // 16:13 Read Strobe Setup cycles. - // 19:17 Write Strobe Hold cycles. - // 25:20 Write Strobe Duration cycles. - // 29:26 Write Strobe Setup cycles. - // 30 Extend Wait mode. - // 31 Select Strobe mode. - // - Emif1Regs.ASYNC_CS4_CR.bit.ASIZE = async_mem_data_width; - Emif1Regs.ASYNC_CS4_CR.bit.TA= turn_around_time; - Emif1Regs.ASYNC_CS4_CR.bit.R_HOLD= r_hold_time; - Emif1Regs.ASYNC_CS4_CR.bit.R_STROBE = r_strobe_time; - Emif1Regs.ASYNC_CS4_CR.bit.R_SETUP = r_setup; - Emif1Regs.ASYNC_CS4_CR.bit.W_HOLD = w_hold; - Emif1Regs.ASYNC_CS4_CR.bit.W_STROBE = w_strobe; - Emif1Regs.ASYNC_CS4_CR.bit.W_SETUP = w_setup; - Emif1Regs.ASYNC_CS4_CR.bit.EW = extend_wait; - Emif1Regs.ASYNC_CS4_CR.bit.SS = strobe_sel; -} - -#ifdef CPU1 -// -// setup_emif1_pinmux_async_16bit - function for EMIF1 GPIO pin setup -// -void setup_emif1_pinmux_async_16bit(Uint16 cpu_sel) -{ - Uint16 i; - - for (i=28; i<=52; i++) - { - if ((i != 42) && (i != 43)) - { - GPIO_SetupPinMux(i,cpu_sel,2); - } - } - for (i=63; i<=87; i++) - { - if (i != 84) - { - GPIO_SetupPinMux(i,cpu_sel,2); - } - } - - GPIO_SetupPinMux(88,cpu_sel,3); - GPIO_SetupPinMux(89,cpu_sel,3); - GPIO_SetupPinMux(90,cpu_sel,3); - GPIO_SetupPinMux(91,cpu_sel,3); - GPIO_SetupPinMux(92,cpu_sel,3); - GPIO_SetupPinMux(93,cpu_sel,3); - GPIO_SetupPinMux(94,cpu_sel,2); - - // - //setup async mode and enable pull-ups for Data pins - // - for (i=69; i<=85; i++) - { - if (i != 84) - { - GPIO_SetupPinOptions(i,0,0x31); // GPIO_ASYNC||GPIO_PULLUP - } - } -} - -// -// setup_emif1_pinmux_async_32bit - Setup pinmux for 32bit async -// -void setup_emif1_pinmux_async_32bit(Uint16 cpu_sel) -{ - Uint16 i; - - for (i=28; i<=87; i++) - { - if ((i != 42) && (i != 43) && (i != 84)) - { - GPIO_SetupPinMux(i,cpu_sel,2); - } - } - - GPIO_SetupPinMux(88,cpu_sel,3); - GPIO_SetupPinMux(89,cpu_sel,3); - GPIO_SetupPinMux(90,cpu_sel,3); - GPIO_SetupPinMux(91,cpu_sel,3); - GPIO_SetupPinMux(92,cpu_sel,3); - GPIO_SetupPinMux(93,cpu_sel,3); - GPIO_SetupPinMux(94,cpu_sel,2); - - // - //setup async mode for Data pins - // - for (i=53; i<=85; i++) - { - if (i != 84) - { - GPIO_SetupPinOptions(i,0,0x31); - } - } -} - -// -// setup_emif2_pinmux_async_16bit - function for EMIF1 GPIO pin setup -// -void setup_emif2_pinmux_async_16bit(Uint16 cpu_sel) -{ - Uint16 i; - - for (i=96; i<=121; i++) - { - GPIO_SetupPinMux(i,cpu_sel,3); - } - - for (i=53; i<=68; i++) - { - GPIO_SetupPinMux(i,cpu_sel,3); - } - - // - //setup async mode for Data pins - // - for (i=53; i<=68; i++) - { - GPIO_SetupPinOptions(i,0,0x31); - } -} - -// -// setup_emif1_pinmux_sdram_16bit - Setup pinmux for 16bit SDRAM -// -void setup_emif1_pinmux_sdram_16bit(Uint16 cpu_sel) -{ - int i; - - for (i=29; i<=52; i++) - { - if ((i != 42) && (i != 43)) - { - GPIO_SetupPinMux(i,cpu_sel,2); - } - } - - for (i=69; i<=85; i++) - { - if (i != 84) - { - GPIO_SetupPinMux(i,cpu_sel,2); - } - } - - for(i=86; i<=93; i++) - { - GPIO_SetupPinMux(i,cpu_sel,3); - } - - // - //configure Data pins for Async mode - // - for (i = 69; i <= 85; i++) - { - if (i != 84) - { - GPIO_SetupPinOptions(i,0,0x31); - } - } - - GPIO_SetupPinOptions(88,0,0x31); - GPIO_SetupPinOptions(89,0,0x31); - GPIO_SetupPinOptions(90,0,0x31); - GPIO_SetupPinOptions(91,0,0x31); -} - -// -// setup_emif2_pinmux_sdram_16bit - Setup pinmux for 16bit SDRAM -// -void setup_emif2_pinmux_sdram_16bit(Uint16 cpu_sel) -{ - int i; - - for (i=53; i<=68; i++) - { - GPIO_SetupPinMux(i,cpu_sel,3); - } - for (i=96; i<=121; i++) - { - GPIO_SetupPinMux(i,cpu_sel,3); - } - - // - //configure Data pins for Async mode - // - for (i = 53; i <= 68; i++) - { - GPIO_SetupPinOptions(i,0,0x31); - } -} - -// -// setup_emif1_pinmux_sdram_32bit - Setup pinmux for 32bit SDRAM -// -void setup_emif1_pinmux_sdram_32bit(Uint16 cpu_sel) -{ - int i; - - for (i=28; i<=85; i++) - { - if ((i != 42) && (i != 43) && (i != 84)) - { - GPIO_SetupPinMux(i,cpu_sel,2); - } - } - - for(i=86; i<=93; i++) - { - GPIO_SetupPinMux(i,cpu_sel,3); - } - - GPIO_SetupPinMux(94,cpu_sel,2); - - // - //configure Data pins for Async mode - // - for (i = 53; i <= 85; i++) - { - if (i != 84) - { - GPIO_SetupPinOptions(i,0,0x31); - } - } - - GPIO_SetupPinOptions(88,0,0x31); - GPIO_SetupPinOptions(89,0,0x31); - GPIO_SetupPinOptions(90,0,0x31); - GPIO_SetupPinOptions(91,0,0x31); - } - -#endif // CPU1 - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Gpio.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Gpio.c deleted file mode 100644 index 0c5927b5ed..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Gpio.c +++ /dev/null @@ -1,506 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Gpio.c -// -// TITLE: GPIO module support functions -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" - -// -//Low-level functions for GPIO configuration (CPU1 only) -// - -#ifdef CPU1 - // - // InitGpio - Sets all pins to be muxed to GPIO in input mode with pull-ups - // enabled. Also resets CPU control to CPU1 and disables open - // drain and polarity inversion and sets the qualification to - // synchronous. Also unlocks all GPIOs. Only one CPU should call - // this function. - // - void InitGpio() - { - volatile Uint32 *gpioBaseAddr; - Uint16 regOffset; - - // - //Disable pin locks - // - EALLOW; - GpioCtrlRegs.GPALOCK.all = 0x00000000; - GpioCtrlRegs.GPBLOCK.all = 0x00000000; - GpioCtrlRegs.GPCLOCK.all = 0x00000000; - GpioCtrlRegs.GPDLOCK.all = 0x00000000; - GpioCtrlRegs.GPELOCK.all = 0x00000000; - GpioCtrlRegs.GPFLOCK.all = 0x00000000; - - // - // Fill all registers with zeros. Writing to each register separately - // for six GPIO modules would make this function *very* long. - // Fortunately, we'd be writing them all with zeros anyway, so this - // saves a lot of space. - // - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs; - for (regOffset = 0; regOffset < sizeof(GpioCtrlRegs)/2; regOffset++) - { - // - //Hack to avoid enabling pull-ups on all pins. GPyPUD is offset - //0x0C in each register group of 0x40 words. Since this is a - //32-bit pointer, the addresses must be divided by 2. - // - if (regOffset % (0x40/2) != (0x0C/2)) - { - gpioBaseAddr[regOffset] = 0x00000000; - } - } - - gpioBaseAddr = (Uint32 *)&GpioDataRegs; - for (regOffset = 0; regOffset < sizeof(GpioDataRegs)/2; regOffset++) - { - gpioBaseAddr[regOffset] = 0x00000000; - } - - EDIS; - } - - // - // GPIO_SetupPinMux - Set the peripheral muxing for the specified pin. The - // appropriate parameters can be found in the GPIO Muxed - // Pins table(4.4) in the datasheet. Use the GPIO index - // row (0 to 15) to select a muxing option for the GPIO. - // - void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition) - { - volatile Uint32 *gpioBaseAddr; - volatile Uint32 *mux, *gmux, *csel; - Uint16 pin32, pin16, pin8; - - pin32 = gpioNumber % 32; - pin16 = gpioNumber % 16; - pin8 = gpioNumber % 8; - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; - - // - //Sanity check for valid cpu and peripheral values - // - if (cpu > GPIO_MUX_CPU2CLA || muxPosition > 0xF) - return; - - // - //Create pointers to the appropriate registers. This is a workaround - //for the way GPIO registers are defined. The standard definition - //in the header file makes it very easy to do named accesses of one - //register or bit, but hard to do arbitrary numerical accesses. It's - //easier to have an array of GPIO modules with identical registers, - //including arrays for multi-register groups like GPyCSEL1-4. But - //the header file doesn't define anything we can turn into an array, - //so manual pointer arithmetic is used instead. - // - mux = gpioBaseAddr + GPYMUX + pin32/16; - gmux = gpioBaseAddr + GPYGMUX + pin32/16; - csel = gpioBaseAddr + GPYCSEL + pin32/8; - - // - //Now for the actual function - // - EALLOW; - - // - //To change the muxing, set the peripheral mux to 0/GPIO first to avoid - //glitches, then change the group mux, then set the peripheral mux to - //its target value. Finally, set the CPU select. This procedure is - //described in the TRM. Unfortunately, since we don't know the pin in - //advance we can't hardcode a bitfield reference, so there's some - //tricky bit twiddling here. - // - *mux &= ~(0x3UL << (2*pin16)); - *gmux &= ~(0x3UL << (2*pin16)); - *gmux |= (Uint32)((muxPosition >> 2) & 0x3UL) << (2*pin16); - *mux |= (Uint32)(muxPosition & 0x3UL) << (2*pin16); - - *csel &= ~(0x3L << (4*pin8)); - *csel |= (Uint32)(cpu & 0x3L) << (4*pin8); - - // - //WARNING: This code does not touch the analog mode select registers, - //which are needed to give the USB module control of its IOs. - // - EDIS; - } - - // - // GPIO_SetupPinOptions - Setup up the GPIO input/output options for the - // specified pin. - // - //The flags are a 16-bit mask produced by ORing together options. - //For input pins, the valid flags are: - //GPIO_PULLUP Enable pull-up - //GPIO_INVERT Enable input polarity inversion - //GPIO_SYNC Synchronize the input latch to PLLSYSCLK - // (default -- you don't need to specify this) - //GPIO_QUAL3 Use 3-sample qualification - //GPIO_QUAL6 Use 6-sample qualification - //GPIO_ASYNC Do not use synchronization or qualification - //(Note: only one of SYNC, QUAL3, QUAL6, or ASYNC is allowed) - // - //For output pins, the valid flags are: - //GPIO_OPENDRAIN Output in open drain mode - //GPIO_PULLUP If open drain enabled, also enable the pull-up - //and the input qualification flags (SYNC/QUAL3/QUAL6/SYNC) listed above. - // - //With no flags, the default input state is synchronous with no - //pull-up or polarity inversion. The default output state is - //the standard digital output. - // - void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags) - { - volatile Uint32 *gpioBaseAddr; - volatile Uint32 *dir, *pud, *inv, *odr, *qsel; - Uint32 pin32, pin16, pinMask, qual; - - pin32 = gpioNumber % 32; - pin16 = gpioNumber % 16; - pinMask = 1UL << pin32; - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; - - // - //Create pointers to the appropriate registers. This is a workaround - //for the way GPIO registers are defined. The standard definition - //in the header file makes it very easy to do named accesses of one - //register or bit, but hard to do arbitrary numerical accesses. It's - //easier to have an array of GPIO modules with identical registers, - //including arrays for multi-register groups like GPyQSEL1-2. But - //the header file doesn't define anything we can turn into an array, - //so manual pointer arithmetic is used instead. - // - dir = gpioBaseAddr + GPYDIR; - pud = gpioBaseAddr + GPYPUD; - inv = gpioBaseAddr + GPYINV; - odr = gpioBaseAddr + GPYODR; - qsel = gpioBaseAddr + GPYQSEL + pin32/16; - - EALLOW; - - // - //Set the data direction - // - *dir &= ~pinMask; - if (output == 1) - { - // - //Output, with optional open drain mode and pull-up - // - *dir |= pinMask; - - // - //Enable open drain if necessary - // - if (flags & GPIO_OPENDRAIN) - { - *odr |= pinMask; - } - else - { - *odr &= ~pinMask; - } - - // - //Enable pull-up if necessary. Open drain mode must be active. - // - if (flags & (GPIO_OPENDRAIN | GPIO_PULLUP)) - { - *pud &= ~pinMask; - } - else - { - *pud |= pinMask; - } - } - else - { - // - //Input, with optional pull-up, qualification, and polarity - //inversion - // - *dir &= ~pinMask; - - // - //Enable pull-up if necessary - // - if (flags & GPIO_PULLUP) - { - *pud &= ~pinMask; - } - else - { - *pud |= pinMask; - } - - // - //Invert polarity if necessary - // - if (flags & GPIO_INVERT) - { - *inv |= pinMask; - } - else - { - *inv &= ~pinMask; - } - } - - // - //Extract the qualification parameter and load it into the register. - //This is also needed for open drain outputs, so we might as well do it - //all the time. - // - qual = (flags & GPIO_ASYNC) / GPIO_QUAL3; - *qsel &= ~(0x3L << (2 * pin16)); - if (qual != 0x0) - { - *qsel |= qual << (2 * pin16); - } - - EDIS; - } - - // - // GPIO_SetupLock - Enable or disable the GPIO register bit lock for the - // specified pin. - // The valid flags are: - // GPIO_UNLOCK - Unlock the pin setup register bits for - // the specified pin - // GPIO_LOCK - Lock the pin setup register bits for the - // specified pin - // - void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags) - { - volatile Uint32 *gpioBaseAddr; - volatile Uint32 *lock; - Uint32 pin32, pinMask; - - pin32 = gpioNumber % 32; - pinMask = 1UL << pin32; - gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; - - // - //Create pointers to the appropriate registers. This is a workaround - //for the way GPIO registers are defined. The standard definition - //in the header file makes it very easy to do named accesses of one - //register or bit, but hard to do arbitrary numerical accesses. It's - //easier to have an array of GPIO modules with identical registers, - //including arrays for multi-register groups like GPyQSEL1-2. But - //the header file doesn't define anything we can turn into an array, - //so manual pointer arithmetic is used instead. - // - lock = gpioBaseAddr + GPYLOCK; - - EALLOW; - if(flags) - { - //Lock the pin - *lock |= pinMask; - } - else - { - //Unlock the pin - *lock &= ~pinMask; - } - EDIS; - } - - // - //External interrupt setup - // - void GPIO_SetupXINT1Gpio(Uint16 gpioNumber) - { - EALLOW; - InputXbarRegs.INPUT4SELECT = gpioNumber; //Set XINT1 source to GPIO-pin - EDIS; - } - void GPIO_SetupXINT2Gpio(Uint16 gpioNumber) - { - EALLOW; - InputXbarRegs.INPUT5SELECT = gpioNumber; //Set XINT2 source to GPIO-pin - EDIS; - } - void GPIO_SetupXINT3Gpio(Uint16 gpioNumber) - { - EALLOW; - InputXbarRegs.INPUT6SELECT = gpioNumber; //Set XINT3 source to GPIO-pin - EDIS; - } - void GPIO_SetupXINT4Gpio(Uint16 gpioNumber) - { - EALLOW; - InputXbarRegs.INPUT13SELECT = gpioNumber; //Set XINT4 source to GPIO-pin - EDIS; - } - void GPIO_SetupXINT5Gpio(Uint16 gpioNumber) - { - EALLOW; - InputXbarRegs.INPUT14SELECT = gpioNumber; //Set XINT5 source to GPIO-pin - EDIS; - } - - // - //GPIO_EnableUnbondedIOPullupsFor176Pin - Enable pullups for the unbonded - // GPIOs on the 176PTP package: - // GPIOs Grp Bits - // 95-132 C 31 - // D 31:0 - // E 4:0 - // 134-168 E 31:6 - // F 8:0 - // - void GPIO_EnableUnbondedIOPullupsFor176Pin() - { - EALLOW; - GpioCtrlRegs.GPCPUD.all = ~0x80000000; //GPIO 95 - GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127 - GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFDF; //GPIOs 128-159 except for 133 - GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168 - EDIS; - } - - // - // GPIO_EnableUnbondedIOPullupsFor100Pin - Enable pullups for the unbonded - // GPIOs on the 100PZ package: - // GPIOs Grp Bits - // 0-1 A 1:0 - // 5-9 A 9:5 - // 22-40 A 31:22 - // B 8:0 - // 44-57 B 25:12 - // 67-68 C 4:3 - // 74-77 C 13:10 - // 79-83 C 19:15 - // 93-168 C 31:29 - // D 31:0 - // E 31:0 - // F 8:0 - // - void GPIO_EnableUnbondedIOPullupsFor100Pin() - { - EALLOW; - GpioCtrlRegs.GPAPUD.all = ~0xFFC003E3; //GPIOs 0-1, 5-9, 22-31 - GpioCtrlRegs.GPBPUD.all = ~0x03FFF1FF; //GPIOs 32-40, 44-57 - GpioCtrlRegs.GPCPUD.all = ~0xE10FBC18; //GPIOs 67-68, 74-77, 79-83, 93-95 - GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127 - GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFFF; //GPIOs 128-159 - GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168 - EDIS; - } - - // - // GPIO_EnableUnbondedIOPullups - InitSysCtrl would call this function - // this takes care of enabling IO pullups. - // - void GPIO_EnableUnbondedIOPullups() - { - // - //bits 8-10 have pin count - // - unsigned char pin_count = ((DevCfgRegs.PARTIDL.all & 0x00000700) >> 8) ; - - // - //5 = 100 pin - //6 = 176 pin - //7 = 337 pin - // - if(pin_count == 5) - { - GPIO_EnableUnbondedIOPullupsFor100Pin(); - } - else if (pin_count == 6) - { - GPIO_EnableUnbondedIOPullupsFor176Pin(); - } - else - { - //do nothing - this is 337 pin package - } - } - -#endif //CPU1 - -// -// GPIO_ReadPin - Read the GPyDAT register bit for the specified pin. Note that -// this returns the actual state of the pin, not the state of -// the output latch. -// -Uint16 GPIO_ReadPin(Uint16 gpioNumber) -{ - volatile Uint32 *gpioDataReg; - Uint16 pinVal; - - gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; - pinVal = (gpioDataReg[GPYDAT] >> (gpioNumber % 32)) & 0x1; - - return pinVal; -} - -// -// GPIO_WritePin - Set the GPyDAT register bit for the specified pin. -// -void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal) -{ - volatile Uint32 *gpioDataReg; - Uint32 pinMask; - - gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; - pinMask = 1UL << (gpioNumber % 32); - - if (outVal == 0) - { - gpioDataReg[GPYCLEAR] = pinMask; - } - else - { - gpioDataReg[GPYSET] = pinMask; - } -} - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_I2C.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_I2C.c deleted file mode 100644 index d17266a9b0..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_I2C.c +++ /dev/null @@ -1,301 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_I2C.c -// -// TITLE: F2837xD I2C Initialization & Support Functions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" - -// -//--------------------------------------------------------------------------- -// Example: I2cAGpioConfig(), I2cBGpioConfig() -//--------------------------------------------------------------------------- -// These functions configures GPIO pins to function as I2C pins -// -// Each GPIO pin can be configured as a GPIO pin or up to 3 different -// peripheral functional pins. By default all pins come up as GPIO -// inputs after reset. -// - -#ifdef CPU1 -// -// I2cAGpioConfig - Configure I2CA GPIOs -// 'I2caDataClkPin' should be assign with one of the -// possible I2C_A SDA - SDL GPIO pin Use defined Macros from -// "F2837xD_I2c_defines.h" for assignment -// -void I2cAGpioConfig(Uint16 I2caDataClkPin) -{ - EALLOW; - - switch(I2caDataClkPin) - { - case I2C_A_GPIO0_GPIO1: - - // - // Enable internal pull-up for the selected I2C pins - // Enable pull-up for GPIO0 (SDAA) - // Enable pull-up for GPIO1 (SDLA) - // - GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; - GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; - - // - // Set qualification for the selected I2C pins - // Async/no qualification (I/ps sync to SYSCLKOUT by default) - // - GpioCtrlRegs.GPAQSEL1.bit.GPIO0 = 3; - GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; - - // - // Configure which of the possible GPIO pins will be I2C_A pins - // using GPIO regs - // Configure GPIO0 for SDAA operation - // Configure GPIO0 for SDAA operation - // - GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 1; - GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 2; - - // - // Configure GPIO1 for SDLA operation - // Configure GPIO1 for SDLA operation - // - GpioCtrlRegs.GPAGMUX1.bit.GPIO1 = 1; - GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 2; - - break; - - case I2C_A_GPIO32_GPIO33: - // - // Enable internal pull-up for the selected I2C pins - // - GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; - GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; - - // - // Set qualification for the selected I2C pins - // - GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; - GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; - - // - // Configure which of the possible GPIO pins will be I2C_A pins - // using GPIO regs - // - GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; - GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; - - break; - - case I2C_A_GPIO42_GPIO43: - // - // Enable internal pull-up for the selected I2C pins - // - - // - // Set qualification for the selected I2C pins - // - - // - // Configure which of the possible GPIO pins will be I2C_A pins - // using GPIO regs - // - break; - - case I2C_A_GPIO91_GPIO92: - // - // Enable internal pull-up for the selected I2C pins - // - GpioCtrlRegs.GPCPUD.bit.GPIO91 = 0; - GpioCtrlRegs.GPCPUD.bit.GPIO92 = 0; - - // - // Set qualification for the selected I2C pins - // - GpioCtrlRegs.GPCQSEL2.bit.GPIO91 = 3; - GpioCtrlRegs.GPCQSEL2.bit.GPIO92 = 3; - - // - // Configure which of the possible GPIO pins will be I2C_A pins - // using GPIO regs - // - GpioCtrlRegs.GPCGMUX2.bit.GPIO91 = 1; - GpioCtrlRegs.GPCMUX2.bit.GPIO91 = 2; - GpioCtrlRegs.GPCGMUX2.bit.GPIO92 = 1; - GpioCtrlRegs.GPCMUX2.bit.GPIO92 = 2; - break; - - case I2C_A_GPIO63104_GPIO105: - // - // Enable internal pull-up for the selected I2C pins - // - - // - // Set qualification for the selected I2C pins - // - - // - // Configure which of the possible GPIO pins will be I2C_A pins - // using GPIO regs - // - break; - - default: - - break; - - } // End of Switch - EDIS; -} - -// -// I2cBGpioConfig - Configure I2CB GPIOs -// 'I2cbDataClkPin' should be assign with one of the possible -// I2C_B SDA - SDL GPIO pin Use defined Macros from -// "F2837xD_I2c_defines.h" for assignment -// -void I2cBGpioConfig(Uint16 I2cbDataClkPin) -{ - EALLOW; - - switch(I2cbDataClkPin) - { - case I2C_B_GPIO2_GPIO3: - // - // Enable internal pull-up for the selected I2C pins - // Enable pull-up for GPIO2 (SDAB) - // Enable pull-up for GPIO3 (SDLB) - // - GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; - GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; - - // - // Set qualification for the selected I2C pins - // Async/no qualification (I/ps sync to SYSCLKOUT by default) - // - GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 3; - GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; - - // - // Configure which of the possible GPIO pins will be I2C_B pins - // using GPIO regs - // Configure GPIO2 for SDAB operation - // Configure GPIO3 for SDAB operation - // Configure GPIO1 for SDLB operation - // Configure GPIO1 for SDLB operation - // - GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 1; - GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 2; - - GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 1; - GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; - - break; - - case I2C_B_GPIO134_GPIO35: - // - // Enable internal pull-up for the selected I2C pins - // - - // - // Set qualification for the selected I2C pins - // - - // - // Configure which of the possible GPIO pins will be I2C_B pins - // using GPIO regs - // - break; - - case I2C_B_GPIO40_GPIO41: - // - // Enable internal pull-up for the selected I2C pins - // - - // - // Set qualification for the selected I2C pins - // - - // - // Configure which of the possible GPIO pins will be I2C_B pins - // using GPIO regs - // - break; - - case I2C_B_GPIO66_GPIO69: - // - // Enable internal pull-up for the selected I2C pins - // - GpioCtrlRegs.GPCPUD.bit.GPIO66 = 0; //SDAB - GpioCtrlRegs.GPCPUD.bit.GPIO69 = 0; //SCLB - - // - // Set qualification for the selected I2C pins - // - GpioCtrlRegs.GPCQSEL1.bit.GPIO66 = 3; - GpioCtrlRegs.GPCQSEL1.bit.GPIO69 = 3; - - // - // Configure which of the possible GPIO pins will be I2C_B pins - // using GPIO regs - // - GpioCtrlRegs.GPCGMUX1.bit.GPIO66 = 1; //0x6 - GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 2; - - GpioCtrlRegs.GPCGMUX1.bit.GPIO69 = 1; //0x6 - GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 2; - break; - - default: - break; - - } - EDIS; -} - -#endif - - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc.c deleted file mode 100644 index a58533c200..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc.c +++ /dev/null @@ -1,216 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Ipc.c -// -// TITLE: Inter-Processor Communication module support functions -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" -#include - -// -// InitIpc - Initialize all IPC registers and clear all flags -// -void InitIpc() -{ - // - //Clear sent flags. Received flags must not be cleared locally - //to handle the case where the remote CPU starts executing first. - //In this case, a remote flag could be sent correctly and be - //incorrectly cleared by this function. Unfortunately, we're - //still left with a startup synchronization problem if the - //remote CPU has flags left over from a previous run. There's - //probably a better way of handling this. - // - IpcRegs.IPCCLR.all = 0xFFFFFFFF; - - // - //Clear commands - // - IpcRegs.IPCSENDCOM = 0; - IpcRegs.IPCSENDADDR = 0; - IpcRegs.IPCSENDDATA = 0; - IpcRegs.IPCLOCALREPLY = 0; - - // - //Clear boot status and pump semaphore - // - #if defined(CPU1) - IpcRegs.IPCBOOTMODE = 0; - #elif defined(CPU2) - IpcRegs.IPCBOOTSTS = 0; - #endif - ReleaseFlashPump(); -} - -// -// ReadIpcTimer - Read the current IPC timer value. The low register must be -// read first to latch a value in the high register. -// -unsigned long long ReadIpcTimer() -{ - Uint32 low, high; - - low = IpcRegs.IPCCOUNTERL; - high = IpcRegs.IPCCOUNTERH; - return ((unsigned long long)high << 32) | (unsigned long long)low; -} - -// -// SendIpcData - Copy data into the IPC send message RAM for this CPU and set -// a flag. If the specified 16-bit word length is greater than -// the size of the message RAM, the data is truncated. -// -void SendIpcData(void *data, Uint16 word_length, Uint16 flag) -{ - word_length = (word_length < MSG_RAM_SIZE) ? word_length : MSG_RAM_SIZE; - - memcpy(SEND_MSG_RAM, data, word_length); - - if (flag != NO_IPC_FLAG) - { - SendIpcFlag(flag); - } -} - -// -// RecvIpcData - Copy data out of the IPC receive message RAM for this CPU. If -// the specified 16-bit word length is greater than the size of -// the message RAM, the data is truncated. -// -void RecvIpcData(void *recv_buf, Uint16 word_length) -{ - word_length = (word_length < MSG_RAM_SIZE) ? word_length : MSG_RAM_SIZE; - memcpy(recv_buf, RECV_MSG_RAM, word_length); -} - -// -// FillIpcSendData - Fill the IPC send message RAM for this CPU with a constant -// value -// -void FillIpcSendData(Uint16 fill_data) -{ - memset(SEND_MSG_RAM, fill_data, MSG_RAM_SIZE); -} - -// -// SendIpcCommand - Write the send command, address, and data registers with -// the specified values, then set an IPC flag. -// -void SendIpcCommand(Uint32 command, Uint32 address, Uint32 data, Uint16 flag) -{ - IpcRegs.IPCSENDCOM = command; - IpcRegs.IPCSENDADDR = address; - IpcRegs.IPCSENDDATA = data; - - if (flag != NO_IPC_FLAG) - { - SendIpcFlag(flag); - } -} - -// -// SendIpcFlag - Set an IPC flag bit for the other CPU. Flags 0-3 will generate -// PIE interrupts. -// -void SendIpcFlag(Uint16 flag) -{ - IpcRegs.IPCSET.all = 1UL << flag; -} - -// -// AckIpcFlag - Acknowledge/clear a received IPC flag -// -void AckIpcFlag(Uint16 flag) -{ - IpcRegs.IPCACK.all = 1UL << flag; -} - -// -// CancelIpcFlag - Clear a sent IPC flag bit before the other CPU acknowledges -// it. You will normally never use this function. To clear a -// received flag, call AckIpcFlag() instead. -// -void CancelIpcFlag(Uint16 flag) -{ - IpcRegs.IPCCLR.all = 1UL << flag; -} - -// -// WaitForIpcFlag - Wait for any IPC flag in the specified mask to be set. -// WARNING: If you use this function to wait for an IPC -// interrupt, you must not clear the IPC flag in the interrupt -// handler. Otherwise, this function will never return. -// -void WaitForIpcFlag(Uint16 flag) -{ - // - //WARNING: Don't use this function to wait for an IPC interrupt! - // - while ((IpcRegs.IPCSTS.all & (1UL << flag)) == 0x00000000) {;} -} - -// -// WaitForIpcAck - Wait for any IPC flag in the specified mask to be -// acknowledged. -// -void WaitForIpcAck(Uint16 flag) -{ - while ((IpcRegs.IPCFLG.all & (1UL << flag)) != 0x00000000) {;} -} - -// -// IpcSync - Synchronize the two CPUs. Neither CPU will return from this -// function call before the other one enters it. Must be called with -// the same flag number on both CPUs. -// -void IpcSync(Uint16 flag) -{ - SendIpcFlag(flag); - WaitForIpcFlag(flag); - AckIpcFlag(flag); - WaitForIpcAck(flag); -} - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver.c deleted file mode 100644 index 9b38efc7b5..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver.c +++ /dev/null @@ -1,1702 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Ipc_Driver.c -// -// TITLE: F2837xD Inter-Processor Communication (IPC) API Driver Functions. -// -// DESCRIPTION: -// 28x API functions for inter-processor communications between the -// two CPUs. The IPC functions require the usage of the CPU1 to CPU2 -// and CPU2 to CPU1 MSG RAM's to store the circular ring -// buffer and indexes. Commands can be queued up in order on a single -// IPC interrupt channel. For those IPC commands which are not -// interdependent, multiple IPC interrupt channels may be used. -// The driver functions in this file are available only as -// sample functions for application development. Due to the generic -// nature of these functions and the cycle overhead inherent to a -// function call, the code is not intended to be used in cases where -// maximum efficiency is required in a system. -// NOTE: This source code is used by both CPUs. That is both CPU1 and CPU2 -// Cores use this code. -// The active debug CPU will be referred to as Local CPU. -// When using this source code in CPU1, the term "local" -// will mean CPU1 and the term "remote" CPU will be mean CPU2. -// When using this source code in CPU2, the term "local" -// will mean CPU2 and the term "remote" CPU will be mean CPU1. -// -// The abbreviations LtoR and RtoL within the function names mean -// Local to Remote and Remote to Local respectively. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -//***************************************************************************** -//! \addtogroup ipc_driver_api -//! @{ -//***************************************************************************** -#include "F2837xD_device.h" -#include "F2837xD_Ipc_drivers.h" - -#if defined(CPU1) -#pragma DATA_SECTION(g_asIPCCPU1toCPU2Buffers, "PUTBUFFER"); -#pragma DATA_SECTION(g_usPutWriteIndexes, "PUTWRITEIDX"); -#pragma DATA_SECTION(g_usGetReadIndexes, "GETREADIDX"); - -#pragma DATA_SECTION(g_asIPCCPU2toCPU1Buffers, "GETBUFFER"); -#pragma DATA_SECTION(g_usGetWriteIndexes, "GETWRITEIDX"); -#pragma DATA_SECTION(g_usPutReadIndexes, "PUTREADIDX"); - -#elif defined(CPU2) - -#pragma DATA_SECTION(g_asIPCCPU2toCPU1Buffers, "PUTBUFFER"); -#pragma DATA_SECTION(g_usPutWriteIndexes, "PUTWRITEIDX"); -#pragma DATA_SECTION(g_usGetReadIndexes, "GETREADIDX"); - -#pragma DATA_SECTION(g_asIPCCPU1toCPU2Buffers, "GETBUFFER"); -#pragma DATA_SECTION(g_usGetWriteIndexes, "GETWRITEIDX"); -#pragma DATA_SECTION(g_usPutReadIndexes, "PUTREADIDX"); - -#endif - -// -// Global Circular Buffer Definitions -// -tIpcMessage g_asIPCCPU1toCPU2Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE]; -tIpcMessage g_asIPCCPU2toCPU1Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE]; - -// -// Global Circular Buffer Index Definitions -// -uint16_t g_usPutWriteIndexes[NUM_IPC_INTERRUPTS]; -uint16_t g_usPutReadIndexes[NUM_IPC_INTERRUPTS]; -uint16_t g_usGetWriteIndexes[NUM_IPC_INTERRUPTS]; -uint16_t g_usGetReadIndexes[NUM_IPC_INTERRUPTS]; - -//***************************************************************************** -// -//! Initializes System IPC driver controller -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param usCPU2IpcInterrupt specifies the CPU2 IPC interrupt number used by -//! psController. -//! \param usCPU1IpcInterrupt specifies the CPU1 IPC interrupt number used by -//! psController. -//! -//! This function initializes the IPC driver controller with circular buffer -//! and index addresses for an IPC interrupt pair. The -//! \e usCPU2IpcInterrupt and \e usCPU1IpcInterrupt parameters can be one of -//! the following values: -//! \b IPC_INT0, \b IPC_INT1, \b IPC_INT2, \b IPC_INT3. -//! -//! \note If an interrupt is currently in use by an \e tIpcController instance, -//! that particular interrupt should not be tied to a second \e tIpcController -//! instance. -//! -//! \note For a particular usCPU2IpcInterrupt - usCPU1IpcInterrupt pair, there -//! must be an instance of tIpcController defined and initialized on both the -//! CPU1 and CPU2 systems. -//! -//! \return None. -// -//***************************************************************************** -void -IPCInitialize (volatile tIpcController *psController, - uint16_t usCPU2IpcInterrupt, uint16_t usCPU1IpcInterrupt) -{ -#if defined(CPU1) - // CPU1toCPU2PutBuffer and Index Initialization - psController->psPutBuffer = &g_asIPCCPU1toCPU2Buffers[usCPU2IpcInterrupt-1][0]; - psController->pusPutWriteIndex = &g_usPutWriteIndexes[usCPU2IpcInterrupt-1]; - psController->pusGetReadIndex = &g_usGetReadIndexes[usCPU1IpcInterrupt-1]; - psController->ulPutFlag = (uint32_t)(1 << (usCPU2IpcInterrupt - 1)); - - // CPU1toCPU2GetBuffer and Index Initialization - psController->psGetBuffer = &g_asIPCCPU2toCPU1Buffers[usCPU1IpcInterrupt-1][0]; - psController->pusGetWriteIndex = &g_usGetWriteIndexes[usCPU1IpcInterrupt-1]; - psController->pusPutReadIndex = &g_usPutReadIndexes[usCPU2IpcInterrupt-1]; -#elif defined(CPU2) - // CPU2toCPU1PutBuffer and Index Initialization - psController->psPutBuffer = &g_asIPCCPU2toCPU1Buffers[usCPU1IpcInterrupt-1][0]; - psController->pusPutWriteIndex = &g_usPutWriteIndexes[usCPU1IpcInterrupt-1]; - psController->pusGetReadIndex = &g_usGetReadIndexes[usCPU2IpcInterrupt-1]; - psController->ulPutFlag = (uint32_t)(1 << (usCPU1IpcInterrupt - 1)); - - // CPU1toCPU2GetBuffer and Index Initialization - psController->psGetBuffer = &g_asIPCCPU1toCPU2Buffers[usCPU2IpcInterrupt-1][0]; - psController->pusGetWriteIndex = &g_usGetWriteIndexes[usCPU2IpcInterrupt-1]; - psController->pusPutReadIndex = &g_usPutReadIndexes[usCPU1IpcInterrupt-1]; -#endif - // Initialize PutBuffer WriteIndex = 0 and GetBuffer ReadIndex = 0 - *(psController->pusPutWriteIndex) = 0; - *(psController->pusGetReadIndex) = 0; -} - -//***************************************************************************** -// -//! Writes a message into the PutBuffer. -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param psMessage specifies the address of the \e tIpcMessage instance to be -//! written to PutBuffer. -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a free slot (1= wait until free spot available, 0 = exit with -//! STATUS_FAIL if no free slot). -//! -//! This function checks if there is a free slot in the PutBuffer. If so, it -//! puts the message pointed to by \e psMessage into the free slot and -//! increments the WriteIndex. Then it sets the appropriate IPC interrupt flag -//! specified by \e psController->usPutFlag. The \e bBlock parameter can be -//! one of the following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. -//! -//! \return \b STATUS_FAIL if PutBuffer is full. \b STATUS_PASS if Put occurs -//! successfully. -// -//***************************************************************************** -uint16_t -IpcPut (volatile tIpcController *psController, tIpcMessage *psMessage, - uint16_t bBlock) -{ - uint16_t writeIndex; - uint16_t readIndex; - uint16_t returnStatus = STATUS_PASS; - - writeIndex = *(psController->pusPutWriteIndex); - readIndex = *(psController->pusPutReadIndex); - - // - // Wait until Put Buffer slot is free - // - while (((writeIndex + 1) & MAX_BUFFER_INDEX) == readIndex) - { - // - // If designated as a "Blocking" function, and Put buffer is full, - // return immediately with fail status. - // - if (!bBlock) - { - returnStatus = STATUS_FAIL; - break; - } - - readIndex = *(psController->pusPutReadIndex); - } - - if (returnStatus != STATUS_FAIL) - { - // - // When slot is free, Write Message to PutBuffer, update PutWriteIndex, - // and set the CPU IPC INT Flag - // - psController->psPutBuffer[writeIndex] = *psMessage; - - writeIndex = (writeIndex + 1) & MAX_BUFFER_INDEX; - *(psController->pusPutWriteIndex) = writeIndex; - - IpcRegs.IPCSET.all |= psController->ulPutFlag; - } - - return returnStatus; -} - -//***************************************************************************** -// -//! Reads a message from the GetBuffer. -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param psMessage specifies the address of the \e tIpcMessage instance where -//! the message from GetBuffer should be written to. -//! \param bBlock specifies whether to allow function to block until GetBuffer -//! has a message (1= wait until message available, 0 = exit with STATUS_FAIL -//! if no message). -//! -//! This function checks if there is a message in the GetBuffer. If so, it gets -//! the message in the GetBuffer pointed to by the ReadIndex and writes it to -//! the address pointed to by \e psMessage. The \e bBlock parameter can be one -//! of the following -//! values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. -//! -//! \return \b STATUS_PASS if GetBuffer is empty. \b STATUS_FAIL if Get occurs -//! successfully. -// -//***************************************************************************** -uint16_t -IpcGet (volatile tIpcController *psController, tIpcMessage *psMessage, - uint16_t bBlock) -{ - uint16_t writeIndex; - uint16_t readIndex; - uint16_t returnStatus = STATUS_PASS; - - writeIndex = *(psController->pusGetWriteIndex); - readIndex = *(psController->pusGetReadIndex); - - // - // Loop while GetBuffer is empty - // - while (writeIndex == readIndex) - { - // - // If designated as a "Blocking" function, and Get buffer is empty, - // return immediately with fail status. - // - if (!bBlock) - { - returnStatus = STATUS_FAIL; - break; - } - - writeIndex = *(psController->pusGetWriteIndex); - } - - if (returnStatus != STATUS_FAIL) - { - // - // If there is a message in GetBuffer, Read Message and update - // the ReadIndex - // - *psMessage = psController->psGetBuffer[readIndex]; - - readIndex = (readIndex + 1) & MAX_BUFFER_INDEX; - *(psController->pusGetReadIndex) = readIndex; - } - - return returnStatus; -} - -//***************************************************************************** -// -//! Sends a command to read either a 16- or 32-bit data word from the remote -//! CPU -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param ulAddress specifies the remote CPU address to read from -//! \param pvData is a pointer to the 16/32-bit variable where read data will -//! be stored. -//! \param usLength designates 16- or 32-bit read (1 = 16-bit, 2 = 32-bit) -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). -//! \param ulResponseFlag indicates the remote CPU to the local CPU Flag -//! number mask used to report when the read data is available at pvData. -//! (\e ulResponseFlag MUST use IPC flags 17-32, and not 1-16) -//! -//! This function will allow the local CPU system to send a 16/32-bit data -//! read command to the remote CPU system and set a ResponseFlag to track the -//! status of the read. -//! The remote CPU will respond with a DataWrite command which will place -//! the data in the local CPU address pointed to by \e pvData. When the local -//! CPU receives the DataWrite command and writes the read data into \e *pvData location, -//! it will clear the ResponseFlag, indicating to the rest of the system that -//! the data is ready. The \e usLength parameter can be one of the -//! following values: \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e -//! bBlock parameter can be one of the following values: \b ENABLE_BLOCKING or -//! \b DISABLE_BLOCKING. -//! The \e ulResponseFlag parameter can be any single one of the flags \b -//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. -//! -//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error -//! because PutBuffer was full, command was not sent) -// -//***************************************************************************** -uint16_t -IPCLtoRDataRead (volatile tIpcController *psController, uint32_t ulAddress, - void *pvData, uint16_t usLength, uint16_t bBlock, - uint32_t ulResponseFlag) -{ - - uint16_t status; - tIpcMessage sMessage; - - // - // Set up read command, address, dataw1 = ResponseFlag | word length, - // dataw2 = address where word - // should be written to when returned. - // - sMessage.ulcommand = IPC_DATA_READ; - sMessage.uladdress = ulAddress; - sMessage.uldataw1 = (ulResponseFlag & 0xFFFF0000)|(uint32_t)usLength; - sMessage.uldataw2 = (uint32_t)pvData; - - // - // Set ResponseFlag (cleared once data is read into address at pvData) - // Put Message into PutBuffer and set IPC INT flag - // - IpcRegs.IPCSET.all |= (ulResponseFlag & 0xFFFF0000); - status = IpcPut (psController, &sMessage, bBlock); - - return status; - - // - //Note: Read Response will have sMessage.ulcommand = IPC_DATA_WRITE - // sMessage.uladdress = (uint32_t) pvData - // sMessage.uldataw1 = ulStatusFlag | - // (uint32_t) usLength; - // sMessage.uldataw2 = word to be read into - // pvData address. - // -} - -//***************************************************************************** -// -//! Sends the command to read either a 16- or 32-bit data word from remote -//! CPU system address to a write-protected local CPU address. -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param ulAddress specifies the remote CPU address to read from -//! \param pvData is a pointer to the 16/32-bit variable where read data will -//! be stored. -//! \param usLength designates 16- or 32-bit read (1 = 16-bit, 2 = 32-bit) -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). -//! \param ulResponseFlag indicates the local CPU to remote CPU Flag number -//! mask used to report when the read data is available at pvData. -//! (\e ulResponseFlag MUST use IPC flags 17-32, and not 1-16) -//! -//! This function will allow the local CPU system to send a 16/32-bit data -//! read command to the remote CPU system and set a ResponseFlag to track the -//! status of the read. -//! The remote CPU system will respond with a DataWrite command which will -//! place the data in the local CPU address pointed to by \e pvData. -//! When the local CPU receives the DataWrite command and writes the read data -//! into \e *pvData location, it will clear the ResponseFlag, indicating to -//! the rest of the system that the data is ready. The \e usLength parameter -//! can be one of the following values: \b IPC_LENGTH_16_BITS or -//! \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be one of the following -//! values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. -//! The \e ulResponseFlag parameter can be any single one of the flags \b -//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. -//! -//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error -//! because PutBuffer was full, command was not sent) -// -//***************************************************************************** -uint16_t -IPCLtoRDataRead_Protected (volatile tIpcController *psController, - uint32_t ulAddress, void *pvData, uint16_t usLength, - uint16_t bBlock, - uint32_t ulResponseFlag) -{ - uint16_t status; - tIpcMessage sMessage; - - // - // Set up read command, address, dataw1 = ResponseFlag | word length, dataw2 - // = address where word should be written to when returned. - // - sMessage.ulcommand = IPC_DATA_READ_PROTECTED; - sMessage.uladdress = ulAddress; - sMessage.uldataw1 = (ulResponseFlag & 0xFFFF0000)|(uint32_t)usLength; - sMessage.uldataw2 = (uint32_t)pvData; - - // - // Set ResponseFlag (cleared once data is read into address at pvData) - // Put Message into PutBuffer and set IPC INT flag - // - IpcRegs.IPCSET.all |= (ulResponseFlag & 0xFFFF0000); - status = IpcPut (psController, &sMessage, bBlock); - - return status; - // - // Note: Read Response will have sMessage.ulcommand = IPC_DATA_WRITE - // sMessage.uladdress = (uint32_t) pvData - // sMessage.uldataw1 = ulStatusFlag | - // (uint32_t) usLength; - // sMessage.uldataw2 = word to be read into - // pvData address. - // -} - -//***************************************************************************** -// -//! Sets the designated bits in a 16-bit data word at the remote CPU system -//! address -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param ulAddress specifies the remote CPU address to write to -//! \param ulMask specifies the 16/32-bit mask for bits which should be set at -//! \e ulAddress. -//! 16-bit masks should fill the lower 16-bits (upper 16-bits will be all -//! 0x0000). -//! \param usLength specifies the length of the bit mask (1=16-bits, 2=32-bits) -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). -//! -//! This function will allow the local CPU system to set bits specified by the -//! \e ulMask variable in a 16/32-bit word on the remote CPU system. The \e -//! usLength parameter can be one of the following values: \b IPC_LENGTH_16_BITS -//! or \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be one of the -//! following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. -//! -//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error -//! because PutBuffer was full, command was not sent) -// -//***************************************************************************** -uint16_t -IPCLtoRSetBits(volatile tIpcController *psController, uint32_t ulAddress, - uint32_t ulMask, uint16_t usLength, - uint16_t bBlock) -{ - uint16_t status; - tIpcMessage sMessage; - - // - // Set up set bits command, address, dataw1 = word length, dataw2 = - // 16/32-bit mask - // - sMessage.ulcommand = IPC_SET_BITS; - sMessage.uladdress = ulAddress; - sMessage.uldataw1 = (uint32_t)usLength; - sMessage.uldataw2 = ulMask; - - // - // Put Message into PutBuffer and set IPC INT flag - // - status = IpcPut (psController, &sMessage, bBlock); - return status; -} -//***************************************************************************** -// -//! Sets the designated bits in a 16-bit write-protected data word at the -//! remote CPU system address -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param ulAddress specifies the remote CPU address to write to -//! \param ulMask specifies the 16/32-bit mask for bits which should be set at -//! \e ulAddress. 16-bit masks should fill the lower 16-bits (upper 16-bits -//! will be all 0x0000). -//! \param usLength specifies the length of the bit mask (1=16-bits, 2=32-bits) -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). -//! -//! This function will allow the local CPU system to set bits specified by the -//! \e ulMask variable in a write-protected 16/32-bit word on the remote CPU -//! system. The \e usLength parameter can be one of the following values: \b -//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be -//! one of the following values: -//! \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. -//! -//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error -//! because PutBuffer was full, command was not sent) -// -//***************************************************************************** -uint16_t -IPCLtoRSetBits_Protected(volatile tIpcController *psController, - uint32_t ulAddress, uint32_t ulMask, uint16_t usLength, - uint16_t bBlock) -{ - uint16_t status; - tIpcMessage sMessage; - - // - // Set up set bits command, address, dataw1 = word length, dataw2 = - // 16/32-bit mask - // - sMessage.ulcommand = IPC_SET_BITS_PROTECTED; - sMessage.uladdress = ulAddress; - sMessage.uldataw1 = (uint32_t)usLength; - sMessage.uldataw2 = ulMask; - - // - // Put Message into PutBuffer and set IPC INT flag - // - status = IpcPut (psController, &sMessage, bBlock); - return status; -} - -//***************************************************************************** -// -//! Clears the designated bits in a 16-bit data word at the remote CPU system -//! address -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param ulAddress specifies the remote CPU address to write to -//! \param ulMask specifies the 16/32-bit mask for bits which should be cleared -//! at \e ulAddress. 16-bit masks should fill the lower 16-bits (upper 16-bits -//! will be all 0x0000). -//! \param usLength specifies the length of the bit mask (1=16-bits, 2=32-bits) -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). -//! -//! This function will allow the local CPU system to clear bits specified by -//! the \e ulMask variable in a 16/32-bit word on the remote CPU system. The \e -//! usLength parameter can be one of the following values: \b -//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be -//! one of the following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. -//! -//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error -//! because PutBuffer was full, command was not sent) -// -//***************************************************************************** -uint16_t -IPCLtoRClearBits(volatile tIpcController *psController, uint32_t ulAddress, - uint32_t ulMask, uint16_t usLength, - uint16_t bBlock) -{ - uint16_t status; - tIpcMessage sMessage; - - // - // Set up clear bits command, address, dataw1 = word length, dataw2 = - // 16/32-bit mask - // - sMessage.ulcommand = IPC_CLEAR_BITS; - sMessage.uladdress = ulAddress; - sMessage.uldataw1 = (uint32_t)usLength; - sMessage.uldataw2 = ulMask; - - // - // Put Message into PutBuffer and set IPC INT flag - // - status = IpcPut (psController, &sMessage, bBlock); - return status; -} - -//***************************************************************************** -// -//! Clears the designated bits in a 16-bit write-protected data word at -//! remote CPU system address -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param ulAddress specifies the secondary CPU address to write to -//! \param ulMask specifies the 16/32-bit mask for bits which should be cleared -//! at \e ulAddress. 16-bit masks should fill the lower 16-bits (upper 16-bits -//! will be all 0x0000). -//! \param usLength specifies the length of the bit mask (1=16-bits, 2=32-bits) -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). -//! -//! This function will allow the local CPU system to set bits specified by the -//! \e ulMask variable in a write-protected 16/32-bit word on the remote CPU -//! system. The \e usLength parameter can be one of the following values: \b -//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be -//! one of the following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. -//! -//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error -//! because PutBuffer was full, command was not sent) -// -//***************************************************************************** -uint16_t -IPCLtoRClearBits_Protected(volatile tIpcController *psController, - uint32_t ulAddress, uint32_t ulMask, - uint16_t usLength, uint16_t bBlock) -{ - uint16_t status; - tIpcMessage sMessage; - - // - // Set up clear bits command, address, dataw1 = word length, dataw2 = - // 16/32-bit mask - // - sMessage.ulcommand = IPC_CLEAR_BITS_PROTECTED; - sMessage.uladdress = ulAddress; - sMessage.uldataw1 = (uint32_t)usLength; - sMessage.uldataw2 = ulMask; - - // - // Put Message into PutBuffer and set IPC INT flag - // - status = IpcPut (psController, &sMessage, bBlock); - return status; -} - -//***************************************************************************** -// -//! Writes a 16/32-bit data word to the remote CPU system address -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param ulAddress specifies the remote cpu address to write to -//! \param ulData specifies the 16/32-bit word which will be written. -//! For 16-bit words, only the lower 16-bits of ulData will be considered by -//! the master system. -//! \param usLength is the length of the word to write (1 = 16-bits, 2 = -//! 32-bits) -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). -//! \param ulResponseFlag is used to pass the \e ulResponseFlag back to the -//! remote cpu only when this function is called in response to \e -//! IPCMtoCDataRead(). Otherwise, set to 0. -//! -//! This function will allow the local CPU system to write a 16/32-bit word -//! via the \e ulData variable to an address on the remote CPU system. -//! The \e usLength parameter can be one of the following values: -//! \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter -//! can be one of the following values: \b ENABLE_BLOCKING or \b -//! DISABLE_BLOCKING. -//! The \e ulResponseFlag parameter can be any single one of the flags \b -//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. -//! -//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error -//! because PutBuffer was full, command was not sent) -// -//***************************************************************************** -uint16_t -IPCLtoRDataWrite(volatile tIpcController *psController, uint32_t ulAddress, - uint32_t ulData, uint16_t usLength, uint16_t bBlock, - uint32_t ulResponseFlag) -{ - uint16_t status; - tIpcMessage sMessage; - - // - // Set up write command, address, dataw1 = ResponseFlag | word length, - // dataw2 = data to write - // - sMessage.ulcommand = IPC_DATA_WRITE; - sMessage.uladdress = ulAddress; - sMessage.uldataw1 = ulResponseFlag |(uint32_t)usLength; - sMessage.uldataw2 = ulData; - - // - // Put Message into PutBuffer and set IPC INT flag - // - status = IpcPut (psController, &sMessage, bBlock); - return status; -} - -//***************************************************************************** -// -//! Writes a 16/32-bit data word to a write-protected remote CPU system address -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param ulAddress specifies the write-protected remote CPU address to -//! write to -//! \param ulData specifies the 16/32-bit word which will be written. For -//! 16-bit words, only the lower 16-bits of ulData will be considered by the -//! master system. -//! \param usLength is the length of the word to write (1 = 16-bits, 2 = -//! 32-bits) -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). -//! \param ulResponseFlag is used to pass the \e ulResponseFlag back to the -//! remote CPU only when this function is called in response to \e -//! IPCMtoCDataRead(). Otherwise, set to 0. -//! -//! This function will allow the local CPU system to write a 16/32-bit word -//! via the \e ulData variable to a write-protected address on the remote CPU -//! system. The \e usLength parameter can be one of the following values: -//! \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter -//! can be one of the following values: \b ENABLE_BLOCKING or \b -//! DISABLE_BLOCKING. -//! The \e ulResponseFlag parameter can be any single one of the flags \b -//! IPC_FLAG16 - -//! \b IPC_FLAG31 or \b NO_FLAG. -//! -//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error -//! because PutBuffer was full, command was not sent) -// -//***************************************************************************** -uint16_t -IPCLtoRDataWrite_Protected(volatile tIpcController *psController, - uint32_t ulAddress, uint32_t ulData, - uint16_t usLength, uint16_t bBlock, - uint32_t ulResponseFlag) -{ - uint16_t status; - tIpcMessage sMessage; - - // - // Set up write command, address, dataw1 = ResponseFlag | word length, - // dataw2 = data to write - // - sMessage.ulcommand = IPC_DATA_WRITE_PROTECTED; - sMessage.uladdress = ulAddress; - sMessage.uldataw1 = ulResponseFlag |(uint32_t)usLength; - sMessage.uldataw2 = ulData; - - // - // Put Message into PutBuffer and set IPC INT flag - // - status = IpcPut (psController, &sMessage, bBlock); - return status; -} - -//***************************************************************************** -// -//! Sends the command to read a block of data from remote CPU system address -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param ulAddress specifies the remote CPU memory block starting address -//! to read from. -//! \param ulShareAddress specifies the local CPU shared memory address the -//! read block will read to. -//! \param usLength designates the block size in 16-bit words. -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). -//! \param ulResponseFlag indicates the local CPU to remote CPU Flag number -//! mask used to report when the read block data is available starting at -//! /e ulShareAddress. (\e ulResponseFlag MUST use IPC flags 17-32, and not -//! 1-16) -//! -//! This function will allow the local CPU system to send a read block -//! command to the remote CPU system and set a ResponseFlag to track the status -//! of the read. The remote CPU system will process the read and place the data -//! in shared memory at the location specified in the \e ulShareAddress -//! parameter and then clear the ResponseFlag, indicating that the block is -//! ready. The \e bBlock parameter can be one of the following values: \b -//! ENABLE_BLOCKING or \b DISABLE_BLOCKING. The \e ulResponseFlag parameter can -//! be any single one of the flags \b IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. -//! -//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error -//! because PutBuffer was full, command was not sent) -// -//***************************************************************************** -uint16_t -IPCLtoRBlockRead(volatile tIpcController *psController, uint32_t ulAddress, - uint32_t ulShareAddress, uint16_t usLength, uint16_t bBlock, - uint32_t ulResponseFlag) -{ - uint16_t status; - tIpcMessage sMessage; - - // - // Set up block read command, address, dataw1 = ResponseFlag | block length, - // dataw2 = remote CPU address in shared memory - // where block data should be read to - // (corresponding to local CPU ulShareAddress). - // - sMessage.ulcommand = IPC_BLOCK_READ; - sMessage.uladdress = ulAddress; - sMessage.uldataw1 = (ulResponseFlag & 0xFFFF0000) |(uint32_t)usLength; - sMessage.uldataw2 = ulShareAddress; - - // - // Set ResponseFlag (cleared once data is read into Share Address location) - // Put Message into PutBuffer and set IPC INT flag - // - IpcRegs.IPCSET.all |= (ulResponseFlag & 0xFFFF0000); - status = IpcPut (psController, &sMessage, bBlock); - - return status; - // - // Note: Read Block Response will occur in processing of ReadBlock (since - // remote CPU has access to shared memory) - // -} - -//***************************************************************************** -// -//! Writes a block of data to remote CPU system address -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param ulAddress specifies the remote CPU memory block starting address -//! to write to. -//! \param ulShareAddress specifies the local CPU shared memory address where -//! data to write from resides. -//! \param usLength designates the block size in 16- or 32-bit words (depends -//! on \e usWordLength). -//! \param usWordLength designates the word size (16-bits = 1 or 32-bits = 2). -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). -//! -//! This function will allow the local CPU system to write a block of data to -//! the remote CPU system starting from the location specified by the -//! \e ulAdress parameter. Prior to calling this function, the local CPU -//! system code should place the data to write in shared memory starting at /e -//! ulShareAddress. -//! The \e usWordLength parameter can be one of the following values: -//! \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter -//! can be one of the following values: \b ENABLE_BLOCKING or \b -//! DISABLE_BLOCKING. -//! The \e ulResponseFlag parameter can be any single one of the flags \b -//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. -//! -//! \note If the shared SARAM blocks are used to pass the RAM block between the -//! processors, the IPCReqMemAccess() function must be called first in order to -//! give the slave CPU write access to the shared memory block(s). -//! -//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error -//! because PutBuffer was full, command was not sent) -// -//***************************************************************************** -uint16_t -IPCLtoRBlockWrite(volatile tIpcController *psController, uint32_t ulAddress, - uint32_t ulShareAddress, uint16_t usLength, - uint16_t usWordLength, uint16_t bBlock) -{ - uint16_t status; - tIpcMessage sMessage; - - // - // Set up block write command, address, dataw1 = block length, - // dataw2 = remote CPU shared mem address - // where write data resides - // - sMessage.ulcommand = IPC_BLOCK_WRITE; - sMessage.uladdress = ulAddress; - sMessage.uldataw1 = ((uint32_t)(usWordLength)<<16) + (uint32_t)usLength; - sMessage.uldataw2 = ulShareAddress; - - // - // Put Message into PutBuffer and set IPC INT flag - // - status = IpcPut (psController, &sMessage, bBlock); - return status; -} - -//***************************************************************************** -// -//! Writes a block of data to a write-protected remote CPU system address -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param ulAddress specifies the write-protected remote CPU block starting -//! address to write to. -//! \param ulShareAddress specifies the local CPU shared memory address where -//! data to write from resides. -//! \param usLength designates the block size in 16- or 32-bit words (depends -//! on \e usWordLength). -//! \param usWordLength designates the word size (16-bits = 1 or 32-bits = 2). -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). -//! -//! This function will allow the local CPU system to write a block of data to -//! a write-protected region on the remote CPU system starting from the -//! location specified by the \e ulAdress parameter. Prior to calling this -//! function, the local CPU system code should place the data to write in -//! shared memory starting at /e ulShareAddress. -//! The \e usWordLength parameter can be one of the following values: -//! \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter -//! can be one of the following values: \b ENABLE_BLOCKING or \b -//! DISABLE_BLOCKING. -//! The \e ulResponseFlag parameter can be any single one of the flags \b -//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. -//! -//! \note If the shared SARAM blocks are used to pass the RAM block between the -//! processors, the IPCReqMemAccess() function must be called first in order to -//! give the the slave CPU write access to the shared memory block(s). -//! -//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error -//! because PutBuffer was full, command was not sent) -// -//***************************************************************************** -uint16_t -IPCLtoRBlockWrite_Protected(volatile tIpcController *psController, - uint32_t ulAddress, uint32_t ulShareAddress, - uint16_t usLength, uint16_t usWordLength, - uint16_t bBlock) -{ - uint16_t status; - tIpcMessage sMessage; - - // - // Set up block write command, address, dataw1 = block length, - // dataw2 = remote CPU shared mem address - // where write data resides - // - sMessage.ulcommand = IPC_BLOCK_WRITE_PROTECTED; - sMessage.uladdress = ulAddress; - sMessage.uldataw1 = ((uint32_t)(usWordLength)<<16) + (uint32_t)usLength; - sMessage.uldataw2 = ulShareAddress; - - // - // Put Message into PutBuffer and set IPC INT flag - // - status = IpcPut (psController, &sMessage, bBlock); - return status; -} - -//***************************************************************************** -// -//! Calls remote CPU function with 1 optional parameter . -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param ulAddress specifies the remote CPU function address -//! \param ulParam specifies the 32-bit optional parameter value. If not used, -//! this can be a dummy value. -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). -//! -//! This function will allow the local CPU system to call a function on the -//! remote CPU. The \e ulParam variable is a single optional 32-bit parameter -//! to pass to the function. The \e bBlock parameter can be one of the -//! following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. -//! -//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error -//! because PutBuffer was full, command was not sent) -// -//***************************************************************************** -uint16_t -IPCLtoRFunctionCall(volatile tIpcController *psController, uint32_t ulAddress, - uint32_t ulParam, - uint16_t bBlock) -{ - uint16_t status; - tIpcMessage sMessage; - - // - // Set up function call command, address, dataw1 = 32-bit parameter - // - sMessage.ulcommand = IPC_FUNC_CALL; - sMessage.uladdress = ulAddress; - sMessage.uldataw1 = ulParam; - - // - // Put Message into PutBuffer and set IPC INT flag - // - status = IpcPut (psController, &sMessage, bBlock); - return status; -} - -//***************************************************************************** -// -//! Sends generic message to remote CPU system -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param ulCommand specifies 32-bit command word to insert into message. -//! \param ulAddress specifies 32-bit address word to insert into message. -//! \param ulDataW1 specifies 1st 32-bit data word to insert into message. -//! \param ulDataW2 specifies 2nd 32-bit data word to insert into message. -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). -//! -//! This function will allow the local CPU system to send a generic message to -//! the remote CPU system. Note that the user should create a corresponding -//! function on the remote CPU side to interpret/use the message or fill -//! parameters in such a way that the existing IPC drivers can recognize the -//! command and properly process the message. -//! The \e bBlock parameter can be one of the following values: \b -//! ENABLE_BLOCKING or \b DISABLE_BLOCKING. -//! -//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error -//! because PutBuffer was full, command was not sent) -// -//***************************************************************************** -uint16_t -IPCLtoRSendMessage(volatile tIpcController *psController, uint32_t ulCommand, - uint32_t ulAddress, uint32_t ulDataW1, uint32_t ulDataW2, - uint16_t bBlock) -{ - uint16_t status; - tIpcMessage sMessage; - - // - // Package message to send - // - sMessage.ulcommand = ulCommand; - sMessage.uladdress = ulAddress; - sMessage.uldataw1 = ulDataW1; - sMessage.uldataw2 = ulDataW2; - - // - // Put Message into PutBuffer and set IPC INT flag - // - status = IpcPut (psController, &sMessage, bBlock); - return status; -} - -#if defined (CPU2) -//***************************************************************************** -// -//! Slave CPU Configures master R/W/Exe Access to Shared SARAM. -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param ulMask specifies the 32-bit mask for the GSxMSEL RAM control -//! register to indicate which GSx SARAM blocks the slave CPU is requesting -//! master access to. -//! \param usMaster specifies whether the CPU1 or CPU2 are given -//! master access to the GSx blocks. -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). -//! -//! This function will allow the slave CPU system to configure master R/W/Exe -//! access to the GSx SARAM blocks specified by the /e ulMask parameter. The -//! function calls the \e IPCSetBits_Protected() or \e -//! IPCClearBits_Protected() functions, and therefore in the master CPU -//! application code, the corresponding functions should be called. -//! The \e bBlock parameter can be one of the following values: \b -//! ENABLE_BLOCKING or \b DISABLE_BLOCKING. The \e usMaster parameter can be -//! either: \b IPC_GSX_CPU2_MASTER or \b IPC_GSX_CPU1_MASTER. The \e ulMask -//! parameter can be any of the options: \b S0_ACCESS - \b S7_ACCESS. -//! -//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error -//! because PutBuffer was full, command was not sent) -// -//***************************************************************************** -uint16_t -IPCReqMemAccess (volatile tIpcController *psController, uint32_t ulMask, - uint16_t usMaster, uint16_t bBlock) -{ - uint16_t status = STATUS_PASS; - uint32_t GSxMSEL_REGaddress = (uint32_t)(&MemCfgRegs.GSxMSEL.all); - - if (usMaster == IPC_GSX_CPU2_MASTER) - { - if ((MemCfgRegs.GSxMSEL.all & ulMask) != ulMask) - { - status = - IPCLtoRSetBits_Protected (psController, GSxMSEL_REGaddress, - ulMask, IPC_LENGTH_32_BITS, - bBlock); - } - } - else if (usMaster == IPC_GSX_CPU1_MASTER) - { - if ((MemCfgRegs.GSxMSEL.all & ulMask) != 0) - { - status = - IPCLtoRClearBits_Protected (psController, GSxMSEL_REGaddress, - ulMask, IPC_LENGTH_32_BITS, - bBlock); - } - } - - return status; -} -#endif - -//***************************************************************************** -// -//! Responds to 16/32-bit data word write command the remote CPU system -//! -//! \param psMessage specifies the pointer to the message received from remote -//! CPU system which includes the 16/32-bit data word to write to the local CPU -//! address. -//! -//! This function will allow the local CPU system to write a 16/32-bit word -//! received from the remote CPU system to the address indicated in \e -//! *psMessage. In the event that the IPC_DATA_WRITE command was received as a -//! result of an IPC_DATA_READ command, this function will also clear the IPC -//! response flag tracking the read so other threads in the local CPU system -//! will be aware that the data is ready. -//! -//! \return None. -// -//***************************************************************************** -void -IPCRtoLDataWrite(tIpcMessage *psMessage) -{ - // - // Data word length = dataw1 (15:0), responseFlag = valid only for IPC - // flags 17-32 - // - uint16_t length = (uint16_t) psMessage->uldataw1; - uint32_t responseFlag = (psMessage->uldataw1) & 0xFFFF0000; - - // - // Write 16/32-bit word to address - // - if (length == IPC_LENGTH_16_BITS) - { - *(uint16_t *)(psMessage->uladdress) = (uint16_t)psMessage->uldataw2; - } - else if (length == IPC_LENGTH_32_BITS) - { - *(uint32_t *)(psMessage->uladdress) = psMessage->uldataw2; - } - - // - // If data write command is in response to a data read command from remote - // CPU to local CPU clear ResponseFlag, indicating read data from remote - // CPU is ready. - // - IpcRegs.IPCCLR.all |= responseFlag; -} - -//***************************************************************************** -// -//! Responds to 16/32-bit write-protected data word write command from -//! secondary CPU system -//! -//! \param psMessage specifies the pointer to the message received from the -//! secondary CPU system which includes the 16/32-bit data word to write to the -//! local CPU address. -//! -//! This function will allow the local CPU system to write a 16/32-bit word -//! received from the secondary CPU system to the write-protected address -//! indicated in \e *psMessage. -//! In the event that the IPC_DATA_WRITE_PROTECTED command was received as a -//! result of an IPC_DATA_READ_PROTECTED command, this function will also clear -//! the IPC response flag tracking the read so other threads in the local CPU -//! will be aware that the data is ready. -//! -//! \return None. -// -//***************************************************************************** -void -IPCRtoLDataWrite_Protected(tIpcMessage *psMessage) -{ - // - // Data word length = dataw1 (15:0), responseFlag = valid only for IPC - // flags 17-32 - // - uint16_t length = (uint16_t) psMessage->uldataw1; - uint32_t responseFlag = (psMessage->uldataw1) & 0xFFFF0000; - - // - // Allow access to EALLOW-protected registers. - // - EALLOW; - - // - // Write 16/32-bit word to EALLOW-protected address - // - if (length == IPC_LENGTH_16_BITS) - { - *(uint16_t *)(psMessage->uladdress) = (uint16_t)psMessage->uldataw2; - } - else if (length == IPC_LENGTH_32_BITS) - { - *(uint32_t *)(psMessage->uladdress) = psMessage->uldataw2; - } - - // - // Disable access to EALLOW-protected registers. - // - EDIS; - - // - // If data write command is in response to a data read command from local - // CPU to remote CPU, clear ResponseFlag, indicating read data from - // secondary CPU is ready - // - IpcRegs.IPCCLR.all |= responseFlag; -} - -//***************************************************************************** -// -//! Responds to 16/32-bit data word read command from remote CPU system. -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param psMessage specifies the pointer to the message received from the -//! remote CPU system. -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). -//! -//! This function will allow the remote CPU system to read a 16/32-bit data -//! word at the local CPU address specified in /e psMessage, and send a Write -//! command with the read data back to the local CPU system. It will also send -//! the Response Flag used to track the read back to the remote CPU. -//! The \e bBlock parameter can be one of the following values: \b -//! ENABLE_BLOCKING or \b DISABLE_BLOCKING. -//! -//! \return None. -// -//***************************************************************************** -void -IPCRtoLDataRead(volatile tIpcController *psController, tIpcMessage *psMessage, - uint16_t bBlock) -{ - unsigned long ulReaddata; - uint16_t usLength; - - // - // If data word length = 16-bits, read the 16-bit value at the given - // address and cast as 32-bit word to send back to remote CPU. - // If data word length = 32-bits, read the 32-bit value at the given - // address. - // - usLength = (uint16_t)psMessage->uldataw1; - - if (usLength == IPC_LENGTH_16_BITS) - { - ulReaddata = (unsigned long)(*(volatile uint16_t *)psMessage->uladdress); - } - else if (usLength == IPC_LENGTH_32_BITS) - { - ulReaddata = *(unsigned long *)psMessage->uladdress; - } - - // - // Send a Write command to write the requested data to the remote CPU read - // into address. - // psMessage->uldataw2 contains remote CPU address where readdata will be - // written. - // psMessage->uldataw1 contains the read response flag in IPC flag 17-32. - // - IPCLtoRDataWrite(psController, psMessage->uldataw2, ulReaddata, usLength, - bBlock,(psMessage->uldataw1 & 0xFFFF0000)); -} - -//***************************************************************************** -// -//! Responds to 16/32-bit data word read command from remote CPU system. -//! to read into a write-protected word on the remote CPU system. -//! -//! \param psController specifies the address of a \e tIpcController instance -//! used to store information about the "Put" and "Get" circular buffers and -//! their respective indexes. -//! \param psMessage specifies the pointer to the message received from the -//! remote CPU system. -//! \param bBlock specifies whether to allow function to block until PutBuffer -//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). -//! -//! This function will allow the remote CPU system to read a 16/32-bit data -//! word at the local CPU address specified in /e psMessage, and send a Write -//! Protected command with the read data back to the remote CPU system at a -//! write protected address. It will also send the Response Flag used to track -//! the read back to the remote CPU. The \e bBlock parameter can be one of the -//! following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. -//! -//! \return None. -// -//***************************************************************************** -void -IPCRtoLDataRead_Protected(volatile tIpcController *psController, - tIpcMessage *psMessage, uint16_t bBlock) -{ - unsigned long ulReaddata; - uint16_t usLength; - - // - // If data word length = 16-bits, read the 16-bit value at the given - // address and cast as 32-bit word to send back to remote CPU. - // If data word length = 32-bits, read the 32-bit value at the given - // address. - // - usLength = (uint16_t)psMessage->uldataw1; - - if (usLength == IPC_LENGTH_16_BITS) - { - ulReaddata = (unsigned long)(*(volatile uint16_t *)psMessage->uladdress); - } - else if (usLength == IPC_LENGTH_32_BITS) - { - ulReaddata = *(unsigned long *)psMessage->uladdress; - } - - // - // Send a Write command to write the requested data to the remote CPU read - // into address. - // psMessage->uldataw2 contains remote CPU address where readdata will be - // written. - // psMessage->uldataw1 contains the read response flag in IPC flag 17-32. - // - IPCLtoRDataWrite_Protected(psController, psMessage->uldataw2, ulReaddata, - usLength, bBlock, - (psMessage->uldataw1 & 0xFFFF0000)); -} - -//***************************************************************************** -// -//! Sets the designated bits in a 16/32-bit data word at a local CPU system -//! address -//! -//! \param psMessage specifies the pointer to the message received from the -//! remote CPU system. -//! -//! This function will allow the remote CPU system to set the bits in a -//! 16/32-bit word on the local CPU system via a local CPU address and mask -//! passed in via the \e psMessage. -//! -//! \return None. -// -//***************************************************************************** -void -IPCRtoLSetBits(tIpcMessage *psMessage) -{ - uint16_t usLength; - - // - // Determine length of word at psMessage->uladdress and then set bits based - // on either the 16-bit or 32-bit bit-mask in psMessage->uldataw2. - // (16-bit length ignores upper 16-bits of psMessage->uldataw2) - // - usLength = (uint16_t)psMessage->uldataw1; - - if (usLength == IPC_LENGTH_16_BITS) - { - *(volatile uint16_t*)psMessage->uladdress |= - (uint16_t) psMessage->uldataw2; - } - else if (usLength == IPC_LENGTH_32_BITS) - { - *(volatile unsigned long *)psMessage->uladdress |= psMessage->uldataw2; - } -} - -//***************************************************************************** -// -//! Sets the designated bits in a 16/32-bit write-protected data word at a -//! local CPU system address -//! -//! \param psMessage specifies the pointer to the message received from the -//! remote CPU system. -//! -//! This function will allow the remote CPU system to set the bits in a write- -//! protected 16/32-bit word on the local CPU system via a local CPU address -//! and mask passed in via the \e psMessage. -//! -//! \return None -// -//***************************************************************************** -void -IPCRtoLSetBits_Protected(tIpcMessage *psMessage) -{ - uint16_t usLength; - - // - // Allow access to EALLOW-protected registers. - // - EALLOW; - - // - // Determine length of word at psMessage->uladdress and then set bits based - // on either the 16-bit or 32-bit bit-mask in psMessage->uldataw2. - // (16-bit length ignores upper 16-bits of psMessage->uldataw2) - // - usLength = (uint16_t)psMessage->uldataw1; - - if (usLength == IPC_LENGTH_16_BITS) - { - *(volatile uint16_t*)psMessage->uladdress |= - (uint16_t) psMessage->uldataw2; - } - else if (usLength == IPC_LENGTH_32_BITS) - { - *(volatile unsigned long *)psMessage->uladdress |= psMessage->uldataw2; - } - - // - // Disable access to EALLOW-protected registers. - // - EDIS; -} - -//***************************************************************************** -// -//! Clears the designated bits in a 32-bit data word at a local CPU system -//! address -//! -//! \param psMessage specifies the pointer to the message received from the -//! remote CPU system. -//! -//! This function will allow the remote CPU system to clear the bits in a -//! 16/32-bit word on the local CPU system via a local CPU address and mask -//! passed in via the \e psMessage. -//! -//! \return None. -// -//***************************************************************************** -void -IPCRtoLClearBits(tIpcMessage *psMessage) -{ - uint16_t usLength; - - // - // Determine length of word at psMessage->uladdress and then clear bits - // based on - // either the 16-bit or 32-bit bit-mask in psMessage->uldataw2. - // (16-bit length ignores upper 16-bits of psMessage->uldataw2) - // - usLength = (uint16_t)psMessage->uldataw1; - - if (usLength == IPC_LENGTH_16_BITS) - { - *(volatile uint16_t*)psMessage->uladdress &= - ~((uint16_t) psMessage->uldataw2); - } - else if (usLength == IPC_LENGTH_32_BITS) - { - *(volatile unsigned long *)psMessage->uladdress &= - ~(psMessage->uldataw2); - } -} - -//***************************************************************************** -// -//! Clears the designated bits in a write-protected 16/32-bit data word at a -//! local CPU system address -//! -//! \param psMessage specifies the pointer to the message received from the -//! remote CPU system. -//! -//! This function will allow the secondary CPU system to clear the bits in a -//! 16/32-bit write-protected word on the local CPU system via a local -//! CPU address and mask passed in via the \e psMessage. -//! -//! \return None. -// -//***************************************************************************** -void -IPCRtoLClearBits_Protected(tIpcMessage *psMessage) -{ - uint16_t usLength; - - // - // Allow access to EALLOW-protected registers. - // - EALLOW; - - // - // Determine length of word at psMessage->uladdress and then clear bits - // based on - // either the 16-bit or 32-bit bit-mask in psMessage->uldataw2. - // (16-bit length ignores upper 16-bits of psMessage->uldataw2) - // - usLength = (uint16_t)psMessage->uldataw1; - - if (usLength == IPC_LENGTH_16_BITS) - { - *(volatile uint16_t*)psMessage->uladdress &= - ~((uint16_t) psMessage->uldataw2); - } - else if (usLength == IPC_LENGTH_32_BITS) - { - *(volatile unsigned long *)psMessage->uladdress &= - ~(psMessage->uldataw2); - } - - // - // Disable access to EALLOW-protected registers. - // - EDIS; -} - -//***************************************************************************** -// -//! Reads a block of data from a remote CPU system address and stores into -//! shared RAM -//! -//! \param psMessage specifies the pointer to the message received from the -//! remote CPU system. -//! -//! This function will respond to the remote CPU system request to read a block -//! of data from the local control system, by reading the data and placing that -//! data into the shared RAM location specified in \e psMessage. -//! -//! \return None. -// -//***************************************************************************** -void -IPCRtoLBlockRead(tIpcMessage *psMessage) -{ - - uint16_t usLength; - volatile uint16_t* pusRAddress; - volatile uint16_t* pusWAddress; - uint16_t usIndex; - - pusRAddress = (volatile uint16_t *)psMessage->uladdress; - pusWAddress = (volatile uint16_t *)psMessage->uldataw2; - usLength = (uint16_t)psMessage->uldataw1; - - for (usIndex=0; usIndexuldataw1 & 0xFFFF0000); -} - -//***************************************************************************** -// -//! Writes a block of data to a local CPU system address from shared RAM -//! -//! \param psMessage specifies the pointer to the message received from the -//! remote CPU system. -//! -//! This function will write a block of data to an address on the local CPU -//! system. -//! The data is first written by the remote CPU to shared RAM. This function -//! reads the shared RAM location, word size (16- or 32-bit), and block size -//! from \e psMessage and writes the block to the local address specified -//! in \e psMessage. -//! -//! \return None. -// -//***************************************************************************** -void -IPCRtoLBlockWrite(tIpcMessage *psMessage) -{ - uint16_t usLength; - uint16_t usWLength; - uint16_t usIndex; - - usLength = (uint16_t)psMessage->uldataw1; - usWLength = (uint16_t)((psMessage->uldataw1)>>16); - - // - // Determine data word access size to write to data block. - // - if (usWLength == IPC_LENGTH_16_BITS) - { - volatile uint16_t *pusWAddress = (volatile uint16_t *)psMessage->uladdress; - volatile uint16_t *pusRAddress = (volatile uint16_t *)psMessage->uldataw2; - for (usIndex=0; usIndexuladdress; - volatile unsigned long *pulRAddress = - (volatile unsigned long *)psMessage->uldataw2; - - for (usIndex=0; usIndexuldataw1; - usWLength = (uint16_t)((psMessage->uldataw1)>>16); - - // - // Determine data word access size to write to data block. - // (Writes registers accessible via APB bus must be 32-bits wide) - // - if (usWLength == IPC_LENGTH_16_BITS) - { - volatile uint16_t *pusWAddress = (volatile uint16_t *)psMessage->uladdress; - volatile uint16_t *pusRAddress = (volatile uint16_t *)psMessage->uldataw2; - for (usIndex=0; usIndexuladdress; - volatile unsigned long *pulRAddress = - (volatile unsigned long *)psMessage->uldataw2; - - for (usIndex=0; usIndexuladdress; - func_call(psMessage->uldataw1); -} - -//***************************************************************************** -// Close the Doxygen group. -//! @} -//***************************************************************************** - - diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Lite.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Lite.c deleted file mode 100644 index 9f8dc61c9c..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Lite.c +++ /dev/null @@ -1,1302 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Ipc_Driver_Lite.c -// -// TITLE: F2837xD Inter-Processor Communication (IPC) Lite API Driver -// Functions. -// -// DESCRIPTION: -// API functions for inter-processor communications between -// CPU1 control system and CPU2 control system (Lite version). The IPC -// Lite functions only allow for basic functions such as data writes, -// reads, bit setting, and bit clearing. The Lite functions do not -// require the usage of the MSG RAM's or shared memories and can only -// be used with a single IPC interrupt channel. Commands can only -// be processed one at a time without queuing. -// The driver functions in this file are available only as -// sample functions for application development. Due to the generic -// nature of these functions and the cycle overhead inherent to a -// function call, the code is not intended to be used in cases where -// maximum efficiency is required in a system. -// -// NOTE: This source code is used by both CPUs. That is both CPU1 and CPU2 -// cores use this code. -// The active debug CPU will be referred to as Local CPU and the other -// CPU will be referred to as Remote CPU. -// When using this source code in CPU1, the term "local" -// will mean CPU1 and the term "remote" CPU will be mean CPU2. -// When using this source code in CPU2, the term "local" -// will mean CPU2 and the term "remote" CPU will be mean CPU1. -// -// The abbreviations LtoR and RtoL within the function names mean -// Local to Remote and Remote to Local respectively. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -//***************************************************************************** -//! \addtogroup ipc_lite_api IPC-Lite API Drivers -//! @{ -//***************************************************************************** -#include "F2837xD_device.h" -#include "F2837xD_Ipc_drivers.h" - -// -// Function Prototypes -// -void DelayLoop (void); - -//***************************************************************************** -// -//! Reads single word data result of Local to Remote IPC command -//! -//! \param pvData is a pointer to the 16/32-bit variable where the result data -//! will be stored. -//! \param usLength designates 16- or 32-bit read. -//! \param ulStatusFlag indicates the Local to Remote CPU Flag number mask used -//! to report the status of the command sent back from the Remote CPU. If -//! a status flag was not used with the command call, set this parameter to 0. -//! -//! Allows the caller to read the 16/32-bit data result of non-blocking IPC -//! functions from the IPCREMOTEREPLY register if the status flag is cleared -//! indicating the IPC command was successfully interpreted. If the status flag -//! is not cleared, the command was not recognized, and the function will -//! return STATUS_FAIL. To determine what data is read from a call to this -//! function, see the descriptions of the non-blocking IPC functions. -//! The \e usLength parameter accepts the following values: \b -//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter -//! accepts any of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. -//! The function returns \b STATUS_PASS or \b STATUS_FAIL. -//! -//! \return status of command (0=success, 1=error) -// -//***************************************************************************** -uint16_t -IPCLiteLtoRGetResult (void *pvData, uint16_t usLength, uint32_t ulStatusFlag) -{ - uint16_t returnStatus; - - // - // If Remote System never acknowledged Status Task, indicates command - // failure. - // - if (IpcRegs.IPCFLG.all & ulStatusFlag) - { - returnStatus = STATUS_FAIL; - } - else - { - // - // Read data. - // - if (usLength == IPC_LENGTH_16_BITS) - { - *(uint16_t *)pvData = IpcRegs.IPCREMOTEREPLY; - } - else if (usLength == IPC_LENGTH_32_BITS) - { - *(uint32_t *)pvData = IpcRegs.IPCREMOTEREPLY; - } - - returnStatus = STATUS_PASS; - } - - return returnStatus; -} - -//***************************************************************************** -// -//! Reads either a 16- or 32-bit data word from the remote CPU System address -//! -//! \param ulFlag specifies Local to Remote IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulAddress specifies the remote address to read from -//! \param usLength designates 16- or 32-bit read (1 = 16-bit, 2 = 32-bit) -//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to -//! report the status of the command sent back from the remote system. -//! -//! This function will allow the Local CPU System to read 16/32-bit data from -//! the Remote CPU System into the IPCREMOTEREPLY register. After calling this -//! function, a call to \e IPCLiteLtoRGetResult() will read the data value in -//! the IPCREMOTEREPLY register into a 16- or 32-bit variable in the local CPU -//! application. -//! The \e usLength parameter accepts the following values: \b -//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter -//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b -//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful -//! or \b STATUS_FAIL if the request or status flags are unavailable. -//! -//! \return status of command (0=success, 1=error) -// -//***************************************************************************** -uint16_t -IPCLiteLtoRDataRead(uint32_t ulFlag, uint32_t ulAddress, uint16_t usLength, - uint32_t ulStatusFlag) -{ - uint16_t returnStatus; - - // - // Return false if IPC Local to Remote request or status flags are not - // available. - // - if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) - { - returnStatus = STATUS_FAIL; - } - else - { - // - // Set up read command, address, and word length. - // - if (usLength == IPC_LENGTH_16_BITS) - { - IpcRegs.IPCSENDCOM = IPC_DATA_READ_16; - } - else if (usLength == IPC_LENGTH_32_BITS) - { - IpcRegs.IPCSENDCOM = IPC_DATA_READ_32; - } - IpcRegs.IPCSENDADDR = ulAddress; - - // - // Force IPC event on selected request task and enable status-checking. - // - IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); - - returnStatus = STATUS_PASS; - } - - return returnStatus; -} - -//***************************************************************************** -// -//! Sets the designated bits in a 16/32-bit data word at the remote CPU system -//! address -//! -//! \param ulFlag specifies Local to Remote IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulAddress specifies the Remote address to write to. -//! \param ulMask specifies the 16/32-bit mask for bits which should be set at -//! remote ulAddress. For 16-bit mask, only the lower 16-bits of ulMask are -//! considered. -//! \param usLength specifies the length of the \e ulMask (1 = 16-bit, 2 = -//! 32-bit). -//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to -//! report the status of the command sent back from the Remote system. -//! -//! This function will allow the Local CPU system to set bits specified by the -//! \e usMask variable in a 16/32-bit word on the Remote CPU system. The data -//! word at /e ulAddress after the set bits command is then read into the -//! IPCREMOTEREPLY register. After calling this function, a call to \e -//! IPCLiteLtoRGetResult() will read the data value in the IPCREMOTEREPLY -//! register into a 16/32-bit variable in the Local CPU application. -//! The \e usLength parameter accepts the following values: \b -//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter -//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b -//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful -//! or \b STATUS_FAIL if the request or status flags are unavailable. -//! -//! \return status of command (0=success, 1=error) -// -//***************************************************************************** -uint16_t -IPCLiteLtoRSetBits(uint32_t ulFlag, uint32_t ulAddress, uint32_t ulMask, - uint16_t usLength, uint32_t ulStatusFlag) -{ - uint16_t returnStatus; - - // - // Return false if IPC Local to Remote request or status flags are not - // available. - // - if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) - { - returnStatus = STATUS_FAIL; - } - else - { - if (usLength == IPC_LENGTH_16_BITS) - { - // - // Set up 16-bit set bits command, address, and mask. - // - IpcRegs.IPCSENDCOM = IPC_SET_BITS_16; - IpcRegs.IPCSENDADDR = ulAddress; - IpcRegs.IPCSENDDATA = ulMask & (0x0000FFFF); - } - else if (usLength == IPC_LENGTH_32_BITS) - { - // - // Set up 32-bit set bits command, address, and mask. - // - IpcRegs.IPCSENDCOM = IPC_SET_BITS_32; - IpcRegs.IPCSENDADDR = ulAddress; - IpcRegs.IPCSENDDATA = ulMask; - } - - // - // Force IPC event on selected request task and enable status-checking. - // - IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); - - returnStatus = STATUS_PASS; - } - - return returnStatus; -} - -//***************************************************************************** -// -//! Sets the designated bits in a 16/32-bit write-protected data word at -//! the Remote CPU system address -//! -//! \param ulFlag specifies Local to Remote IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulAddress specifies the Remote CPU write-protected address to write -//! to. -//! \param ulMask specifies the 16/32-bit mask for bits which should be set at -//! Remote CPU ulAddress.For 16-bit mask, only the lower 16-bits of ulMask are -//! considered. -//! \param usLength specifies the length of the \e ulMask (1 = 16-bit, 2 = -//! 32-bit). -//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to -//! report the status of the command sent back from the Master system. -//! -//! This function will allow the Local CPU system to set bits specified by the -//! \e usMask variable in a write-protected 16/32-bit word on the REmote CPU -//! system. -//! The data word at /e ulAddress after the set bits command is then read into -//! the IPCREMOTEREPLY register. After calling this function, a call to -//! \e IPCLiteLtoRGetResult() will read the data value in the IPCREMOTEREPLY -//! register into a 16/32-bit variable in the Local application. -//! The \e usLength parameter accepts the following values: \b -//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter -//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b -//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful -//! or \b STATUS_FAIL if the request or status flags are unavailable. -//! -//! \return status of command (0=success, 1=error) -// -//***************************************************************************** -uint16_t -IPCLiteLtoRSetBits_Protected (uint32_t ulFlag, uint32_t ulAddress, - uint32_t ulMask, uint16_t usLength, - uint32_t ulStatusFlag) -{ - uint16_t returnStatus; - - // - // Return false if IPC Local to Remote request or status flags are not - // available. - // - if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) - { - returnStatus = STATUS_FAIL; - } - else - { - if (usLength == IPC_LENGTH_16_BITS) - { - // - // Set up 16-bit set bits command, address, and mask. - // - IpcRegs.IPCSENDCOM = IPC_SET_BITS_16_PROTECTED; - IpcRegs.IPCSENDADDR = ulAddress; - IpcRegs.IPCSENDDATA = ulMask & (0x0000FFFF); - } - else if (usLength == IPC_LENGTH_32_BITS) - { - // - // Set up 32-bit set bits command, address, and mask. - // - IpcRegs.IPCSENDCOM = IPC_SET_BITS_32_PROTECTED; - IpcRegs.IPCSENDADDR = ulAddress; - IpcRegs.IPCSENDDATA = ulMask; - } - - // - // Force IPC event on selected request task and enable status-checking. - // - IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); - - returnStatus = STATUS_PASS; - } - - return returnStatus; -} - -//***************************************************************************** -// -//! Sets the designated bits in a 16/32-bit data word at the remote CPU system -//! address -//! -//! \param ulFlag specifies Local to Remote IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulAddress specifies the Remote CPU address to write to. -//! \param ulMask specifies the 16/32-bit mask for bits which should be set at -//! the remote CPU ulAddress. (For 16-bit mask, only the lower 16-bits of -//! ulMask are considered. -//! \param usLength specifies the length of the \e ulMask (1 = 16-bit, 2 = -//! 32-bit). -//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to -//! report the status of the command sent back from the Master system. -//! -//! This function will allow the Local CPU system to set bits specified by the -//! \e usMask variable in a 16/32-bit word on the Remote CPU system. The data -//! word at /e ulAddress after the set bits command is then read into the -//! IPCREMOTEREPLY register. After calling this function, a call to \e -//! IPCLiteLtoRGetResult() will read the data value in the IPCREMOTEREPLY -//! register into a 16/32-bit variable in the Local CPU application. -//! The \e usLength parameter accepts the following values: \b -//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter -//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b -//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful -//! or \b STATUS_FAIL if the request or status flags are unavailable. -//! -//! \return status of command (0=success, 1=error) -// -//***************************************************************************** -uint16_t -IPCLiteLtoRClearBits(uint32_t ulFlag, uint32_t ulAddress, uint32_t ulMask, - uint16_t usLength, uint32_t ulStatusFlag) -{ - uint16_t returnStatus; - - // - // Return false if IPC Local to Remote request or status flags are not - // available. - // - if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) - { - returnStatus = STATUS_FAIL; - } - else - { - if (usLength == IPC_LENGTH_16_BITS) - { - // - // Set up 16-bit set bits command, address, and mask. - // - IpcRegs.IPCSENDCOM = IPC_CLEAR_BITS_16; - IpcRegs.IPCSENDADDR = ulAddress; - IpcRegs.IPCSENDDATA = ulMask & (0x0000FFFF); - } - else if (usLength == IPC_LENGTH_32_BITS) - { - // - // Set up 32-bit set bits command, address, and mask. - // - IpcRegs.IPCSENDCOM = IPC_CLEAR_BITS_32; - IpcRegs.IPCSENDADDR = ulAddress; - IpcRegs.IPCSENDDATA = ulMask; - } - - // - // Force IPC event on selected request task and enable status-checking. - // - IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); - - returnStatus = STATUS_PASS; - } - - return returnStatus; -} - -//***************************************************************************** -// -//! Clears the designated bits in a 16/32-bit write-protected data word at -//! Remote CPU system address -//! -//! \param ulFlag specifies Local to Remote IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulAddress specifies the Remote CPU write-protected address to write -//! to. -//! \param ulMask specifies the 16/32-bit mask for bits which should be cleared -//! at Remote CPU ulAddress.For 16-bit mask, only the lower 16-bits of ulMask -//! are considered. -//! \param usLength specifies the length of the \e ulMask (1 = 16-bit, 2 = -//! 32-bit). -//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to -//! report the status of the command sent back from the Master system. -//! -//! This function will allow the Local CPU system to clear bits specified by -//! the \e usMask variable in a write-protected 16/32-bit word on the Remote -//! CPU system. -//! The data word at /e ulAddress after the clear bits command is then read -//! into the IPCREMOTEREPLY register. After calling this function, a call to -//! \e IPCLiteLtoRGetResult() will read the data value in the IPCREMOTEREPLY -//! register into a 16/32-bit variable in the Local CPU application. -//! The \e usLength parameter accepts the following values: \b -//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter -//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b -//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful -//! or \b STATUS_FAIL if the request or status flags are unavailable. -//! -//! \return status of command (0=success, 1=error) -// -//***************************************************************************** -uint16_t -IPCLiteLtoRClearBits_Protected (uint32_t ulFlag, uint32_t ulAddress, - uint32_t ulMask, uint16_t usLength, - uint32_t ulStatusFlag) -{ - uint16_t returnStatus; - - // - // Return false if IPC Local to Remote request or status flags are not - // available. - // - if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) - { - returnStatus = STATUS_FAIL; - } - else - { - if (usLength == IPC_LENGTH_16_BITS) - { - // - // Set up 16-bit set bits command, address, and mask. - // - IpcRegs.IPCSENDCOM = IPC_CLEAR_BITS_16_PROTECTED; - IpcRegs.IPCSENDADDR = ulAddress; - IpcRegs.IPCSENDDATA = ulMask & (0x0000FFFF); - } - else if (usLength == IPC_LENGTH_32_BITS) - { - // - // Set up 32-bit set bits command, address, and mask. - // - IpcRegs.IPCSENDCOM = IPC_CLEAR_BITS_32_PROTECTED; - IpcRegs.IPCSENDADDR = ulAddress; - IpcRegs.IPCSENDDATA = ulMask; - } - - // - // Force IPC event on selected request task and enable status-checking. - // - IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); - - returnStatus = STATUS_PASS; - } - - return returnStatus; -} - -//***************************************************************************** -// -//! Writes a 16/32-bit data word to Remote CPU System address -//! -//! \param ulFlag specifies Local to Remote IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulAddress specifies the Remote CPU address to write to -//! \param ulData specifies the 16/32-bit word which will be written. -//! For 16-bit words, only the lower 16-bits of ulData will be considered by -//! the master system. -//! \param usLength is the length of the word to write (0 = 16-bits, 1 = -//! 32-bits) -//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to -//! report the status of the command sent back from the Remote CPU system. -//! -//! This function will allow the Local CPU System to write a 16/32-bit word -//! via the \e ulData variable to an address on the Remote CPU System. -//! The \e usLength parameter accepts the following values: \b -//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter -//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b -//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful -//! or \b STATUS_FAIL if the request or status flags are unavailable. -//! -//! \return status of command (0=success, 1=error) -// -//***************************************************************************** -uint16_t -IPCLiteLtoRDataWrite(uint32_t ulFlag, uint32_t ulAddress, uint32_t ulData, - uint16_t usLength, uint32_t ulStatusFlag) -{ - uint16_t returnStatus; - - // - // Return false if IPC Local to Remote request or status flags are not - // available. - // - if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) - { - returnStatus = STATUS_FAIL; - } - else - { - // - // Set up data write command, address, and data. For 16-bit write, - // Master system will look at lower 16-bits only. - // - if (usLength == IPC_LENGTH_16_BITS) - { - IpcRegs.IPCSENDCOM = IPC_DATA_WRITE_16; - } - else if (usLength == IPC_LENGTH_32_BITS) - { - IpcRegs.IPCSENDCOM = IPC_DATA_WRITE_32; - } - IpcRegs.IPCSENDADDR = ulAddress; - IpcRegs.IPCSENDDATA = ulData; - - // - // Force IPC event on selected request task and enable status-checking - // - IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); - - returnStatus = STATUS_PASS; - } - - return returnStatus; -} - -//***************************************************************************** -// -//! Writes a 16/32-bit data word to a protected Remote CPU System address -//! -//! \param ulFlag specifies Local to Remote IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulAddress specifies the Remote CPU address to write to -//! \param ulData specifies the 16/32-bit word which will be written. -//! For 16-bit words, only the lower 16-bits of ulData will be considered by -//! the master system. -//! \param usLength is the length of the word to write (0 = 16-bits, 1 = -//! 32-bits) -//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to -//! report the status of the command sent back from the Master system. -//! -//! This function will allow the Local CPU System to write a 16/32-bit word -//! via the \e ulData variable to a write-protected address on the Remote CPU -//! System. The \e usLength parameter accepts the following values: \b -//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter -//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b -//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful -//! or \b STATUS_FAIL if the request or status flags are unavailable. -//! -//! \return status of command (0=success, 1=error) -// -//***************************************************************************** -uint16_t -IPCLiteLtoRDataWrite_Protected(uint32_t ulFlag, uint32_t ulAddress, - uint32_t ulData, uint16_t usLength, - uint32_t ulStatusFlag) -{ - uint16_t returnStatus; - - // - // Return false if IPC Local to Remote request or status flags are not - // available. - // - if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) - { - returnStatus = STATUS_FAIL; - } - else - { - // - // Set up data write command, address, and data. For 16-bit write, Master - // system will look at lower 16-bits only. - // - if (usLength == IPC_LENGTH_16_BITS) - { - IpcRegs.IPCSENDCOM = IPC_DATA_WRITE_16_PROTECTED; - } - else if (usLength == IPC_LENGTH_32_BITS) - { - IpcRegs.IPCSENDCOM = IPC_DATA_WRITE_32_PROTECTED; - } - IpcRegs.IPCSENDADDR = ulAddress; - IpcRegs.IPCSENDDATA = ulData; - - // - // Force IPC event on selected request task and enable status-checking - // - IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); - - returnStatus = STATUS_PASS; - } - - return returnStatus; -} - -//***************************************************************************** -// -//! Calls a Remote CPU function with 1 optional parameter and an optional -//! return value. -//! -//! \param ulFlag specifies Local to Remote IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulAddress specifies the Remote CPU function address -//! \param ulParam specifies the 32-bit optional parameter value -//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to -//! report the status of the command sent back from the control system. -//! -//! This function will allow the Local CPU system to call a function on the -//! Remote CPU. The \e ulParam variable is a single optional 32-bit parameter -//! to pass to the function. The \e ulFlag parameter accepts any one of the -//! flag values \b IPC_FLAG1 - \b IPC_FLAG32. The \e ulStatusFlag parameter -//! accepts any other one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 -//! and \b NO_FLAG. The function returns \b STATUS_PASS if the command is -//! successful or \b STATUS_FAIL if the request or status flags are unavailable. -//! -//! \return status of command (0=success, 1=error) -// -//***************************************************************************** -uint16_t -IPCLiteLtoRFunctionCall(uint32_t ulFlag, uint32_t ulAddress, uint32_t ulParam, - uint32_t ulStatusFlag) -{ - uint16_t returnStatus; - - // - // Return false if IPC Remote to Local request or status flags are not - // available. - // - if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) - { - returnStatus = STATUS_FAIL; - } - else - { - // - // Set up function call command, address, and parameter. - // - IpcRegs.IPCSENDCOM = IPC_FUNC_CALL; - IpcRegs.IPCSENDADDR = ulAddress; - IpcRegs.IPCSENDDATA = ulParam; - - // - // Force IPC event on selected request task and enable status-checking - // - IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); - - returnStatus = STATUS_PASS; - } - - return returnStatus; -} - -//***************************************************************************** -// -//! Slave Requests Master R/W/Exe Access to Shared SARAM. -//! -//! \param ulFlag specifies Local to Remote IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulMask specifies the 32-bit mask for the GSxMEMSEL RAM control -//! register to indicate which GSx SARAM blocks the Slave is requesting master -//! access to. -//! \param ulMaster specifies whether CPU1 or CPU2 should be the master of the -//! GSx RAM. -//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to -//! report the status of the command sent back from the Master system. -//! -//! This function will allow the slave CPU System to request slave or master -//! mastership of any of the GSx Shared SARAM blocks. -//! The \e ulMaster parameter accepts the following values: -//! \b IPC_GSX_CPU2_MASTER or \b IPC_GSX_CPU1_MASTER. The \e ulStatusFlag -//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 -//! and \b NO_FLAG. The function returns \b STATUS_PASS if the command is -//! successful or \b STATUS_FAIL if the request or status flags are unavailable. -//! \note This function calls the \e IPCLiteLtoRSetBits_Protected() or the -//! \e IPCLiteLtoRClearBits_Protected function, and therefore in order to -//! process this function, the above 2 functions should be ready to be called -//! on the master system to process this command. -//! -//! \return status of command (0=success, 1=error) -// -//***************************************************************************** -uint16_t -IPCLiteReqMemAccess (uint32_t ulFlag, uint32_t ulMask, uint16_t ulMaster, - uint32_t ulStatusFlag) -{ - uint16_t status; - uint32_t GSxMSEL_REGaddress = (uint32_t)(&MemCfgRegs.GSxMSEL.all); - if (ulMaster == IPC_GSX_CPU2_MASTER) - { - status = - IPCLiteLtoRSetBits_Protected (ulFlag, GSxMSEL_REGaddress, ulMask, - IPC_LENGTH_32_BITS, - ulStatusFlag); - } - else if (ulMaster == IPC_GSX_CPU1_MASTER) - { - status = - IPCLiteLtoRClearBits_Protected (ulFlag, GSxMSEL_REGaddress, ulMask, - IPC_LENGTH_32_BITS, - ulStatusFlag); - } - - return status; -} - -//***************************************************************************** -// -//! Reads either a 16- or 32-bit data word from the Local CPU system address -//! -//! \param ulFlag specifies Remote to Local IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to -//! report the status of the command sent back from the control system. -//! -//! This function will allow the Remote CPU system to read 16/32-bit data from -//! the Local CPU system. The \e ulFlag parameter accepts any one of the -//! flag values \b IPC_FLAG1 - \b IPC_FLAG32, and the \e ulStatusFlag parameter -//! accepts any other one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and -//! \b NO_FLAG. -// -//***************************************************************************** -void -IPCLiteRtoLDataRead(uint32_t ulFlag, uint32_t ulStatusFlag) -{ - - uint32_t* pulRAddress; - uint16_t* pusRAddress; - - // - // Wait until IPC Remote to Local request task is flagged - // - while (!(IpcRegs.IPCSTS.all & ulFlag)) - { - } - - // - // If the command and data length are correct for this function: - // Then read from requested address and write 16/32-bit data - // to IPCLOCALREPLY. Acknowledge the status flag - // and the task flag. - // - if (IpcRegs.IPCRECVCOM == IPC_DATA_READ_16) - { - // - // Perform 16-bit read. - // - pusRAddress = (uint16_t *)IpcRegs.IPCRECVADDR; - IpcRegs.IPCLOCALREPLY = (uint32_t)(*pusRAddress); - IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); - } - else if (IpcRegs.IPCRECVCOM == IPC_DATA_READ_32) - { - pulRAddress = (uint32_t *)IpcRegs.IPCRECVADDR; - IpcRegs.IPCLOCALREPLY = *pulRAddress; - IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); - } - - // - // Otherwise, only acknowledge the task flag. - //(Indicates to Remote CPU there was an error) - // - else - { - IpcRegs.IPCACK.all |= (ulFlag); - } -} - -//***************************************************************************** -// -//! Sets the designated bits in a 16/32-bit data word at the Local CPU system -//! address -//! -//! \param ulFlag specifies Remote to Local IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to -//! report the status of the command sent back from the control system. -//! -//! This function will allow the Remote CPU system to set bits specified by a -//! mask variable in a 16/32-bit word on the Local CPU system, and then read -//! back the word into the IPCLOCALREPLY register. The \e ulFlag parameter -//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, and the -//! \e ulStatusFlag parameter accepts any other one of the flag values \b -//! IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. -// -//***************************************************************************** -void -IPCLiteRtoLSetBits(uint32_t ulFlag, uint32_t ulStatusFlag) -{ - - uint16_t* pusAddress; - uint32_t* pulAddress; - - // - // Wait until IPC Remote to Local request task is flagged - // - while (!(IpcRegs.IPCSTS.all & ulFlag)) - { - } - - // - // If the command is correct for this function: - // Then set the mask bits at the requested address - // and write back the 16/32-bit data to IPCLOCALREPLY. - // Acknowledge the status flag and the task flag. - // - if (IpcRegs.IPCRECVCOM == IPC_SET_BITS_16) - { - pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; - *pusAddress |= (uint16_t)IpcRegs.IPCRECVDATA; - IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; - - IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); - } - else if (IpcRegs.IPCRECVCOM == IPC_SET_BITS_32) - { - pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR;; - *pulAddress |= (uint32_t)IpcRegs.IPCRECVDATA; - IpcRegs.IPCLOCALREPLY = *pulAddress; - - IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); - } - - // - // Otherwise, only acknowledge the task flag. - // (Indicates to Remote CPU there was an error) - // - else - { - IpcRegs.IPCACK.all |= (ulFlag); - } -} - -//***************************************************************************** -// -//! Sets the designated bits in a 16-bit data word at the Local CPU system -//! write-protected address -//! -//! \param ulFlag specifies Remote to Local IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to -//! report the status of the command sent back from the control system. -//! -//! This function will allow the Remote CPU system to set bits specified by a -//! mask variable in a write-protected 16/32-bit word on the Local CPU system, -//! and then read back the word into the IPCLOCALREPLY register. The \e ulFlag -//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, -//! and the \e ulStatusFlag parameter accepts any other one of the flag values -//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. -// -//***************************************************************************** -void -IPCLiteRtoLSetBits_Protected (uint32_t ulFlag, uint32_t ulStatusFlag) -{ - - uint16_t* pusAddress; - uint32_t* pulAddress; - - // - // Wait until IPC Remote to Local request task is flagged - // - while (!(IpcRegs.IPCSTS.all & ulFlag)) - { - } - - // - // If the command is correct for this function: - // Then enable write access with EALLOW and - // set the mask bits at the requested address. - // Write back the 16-bit data to IPCLOCALREPLY. - // Restore write-protection with EDIS. - // Acknowledge the status flag and the task flag. - // - - EALLOW; - - if (IpcRegs.IPCRECVCOM == IPC_SET_BITS_16_PROTECTED) - { - pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR; - *pusAddress |= (uint16_t)IpcRegs.IPCRECVDATA; - IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; - - IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); - } - else if (IpcRegs.IPCRECVCOM == IPC_SET_BITS_32_PROTECTED) - { - pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR; - *pulAddress |= (uint32_t)IpcRegs.IPCRECVDATA; - IpcRegs.IPCLOCALREPLY = *pulAddress; - - IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); - } - - // - // Otherwise, only acknowledge the task flag. - //(Indicates to the Remote CPU there was an error) - // - else - { - IpcRegs.IPCACK.all |= (ulFlag); - } - - EDIS; -} - -//***************************************************************************** -// -//! Clears the designated bits in a 16/32-bit data word at Local CPU system -//! address -//! -//! \param ulFlag specifies Remote to Local IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to -//! report the status of the command sent back from the control system. -//! -//! This function will allow the Remote CPU system to clear bits specified by a -//! mask variable in a 16/32-bit word on the Local CPU system, and then read -//! back the word into the IPCLOCALREPLY register. The \e ulFlag -//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, -//! and the \e ulStatusFlag parameter accepts any other one of the flag values -//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. -// -//***************************************************************************** -void -IPCLiteRtoLClearBits(uint32_t ulFlag, uint32_t ulStatusFlag) -{ - uint16_t* pusAddress; - uint32_t* pulAddress; - - // - // Wait until IPC Remote to Local request task is flagged - // - while (!(IpcRegs.IPCSTS.all & ulFlag)) - { - } - - // - // If the command is correct for this function: - // Then clear the mask bits at the requested address - // and write back the 16/32-bit data to IPCLOCALREPLY. - // Acknowledge the status flag and the task flag. - // - if (IpcRegs.IPCRECVCOM == IPC_CLEAR_BITS_16) - { - pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; - *pusAddress &= ~((uint16_t)IpcRegs.IPCRECVDATA); - IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; - - IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); - } - else if (IpcRegs.IPCRECVCOM == IPC_CLEAR_BITS_32) - { - pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR; - *pulAddress &= ~((uint32_t)IpcRegs.IPCRECVDATA); - IpcRegs.IPCLOCALREPLY = *pulAddress; - - IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); - } - - // - // Otherwise, only acknowledge the task flag. - // (Indicates to Remote CPU there was an error) - // - else - { - IpcRegs.IPCACK.all |= (ulFlag); - } -} - -//***************************************************************************** -// -//! Clears the designated bits in a 16/32-bit data word at the Local CPU system -//! write-protected address -//! -//! \param ulFlag specifies Remote to Local IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to -//! report the status of the command sent back from the control system. -//! -//! This function will allow the Remote CPU system to clear bits specified by a -//! mask variable in a 16/32-bit word on the Local CPU system, and then read -//! back the word into the IPCLOCALREPLY register. The \e ulFlag -//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, -//! and the \e ulStatusFlag parameter accepts any other one of the flag values -//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. -// -//***************************************************************************** -void -IPCLiteRtoLClearBits_Protected (uint32_t ulFlag, uint32_t ulStatusFlag) -{ - uint16_t* pusAddress; - uint32_t* pulAddress; - - // - // Wait until IPC Remote to Local request task is flagged - // - while (!(IpcRegs.IPCSTS.all & ulFlag)) - { - } - - // - // If the command is correct for this function: - // Then enable write access with EALLOW and - // clear the mask bits at the requested address. - // Write back the 16/32-bit data to IPCLOCALREPLY. - // Restore the status of the EALLOW register. - // Acknowledge the status flag and the task flag. - // - EALLOW; - - if (IpcRegs.IPCRECVCOM == IPC_CLEAR_BITS_16_PROTECTED) - { - - pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; - *pusAddress &= ~((uint16_t)IpcRegs.IPCRECVDATA); - IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; - - IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); - } - else if (IpcRegs.IPCRECVCOM == IPC_CLEAR_BITS_32_PROTECTED) - { - - pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR;; - *pulAddress &= ~((uint32_t)IpcRegs.IPCRECVDATA); - IpcRegs.IPCLOCALREPLY = (uint32_t)*pulAddress; - - IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); - } - - // - // Otherwise, only acknowledge the task flag. - // (Indicates to Remote CPU there was an error) - // - else - { - IpcRegs.IPCACK.all |= (ulFlag); - } - - EDIS; -} - -//***************************************************************************** -// -//! Writes a 16/32-bit data word to Local CPU system address -//! -//! \param ulFlag specifies Remote to Local IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to -//! report the status of the command sent back from the control system. -//! -//! This function will allow the Remote CPU system to write a 16/32-bit word -//! to an address on the Local CPU system. The \e ulFlag -//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, -//! and the \e ulStatusFlag parameter accepts any other one of the flag values -//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. -// -//***************************************************************************** -void -IPCLiteRtoLDataWrite(uint32_t ulFlag, uint32_t ulStatusFlag) -{ - uint32_t* pulAddress; - uint16_t* pusAddress; - - // - // Wait until IPC Remote to Local request task is flagged - // - while (!(IpcRegs.IPCSTS.all & ulFlag)) - { - } - - // - // If the command is correct for this function: - // Then write the 16/32-bit data to the requested address - // and write back the 16/32-bit data to IPCLOCALREPLY. - // Acknowledge the status flag and the task flag. - // - if (IpcRegs.IPCRECVCOM == IPC_DATA_WRITE_16) - { - pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; - *pusAddress = (uint16_t)IpcRegs.IPCRECVDATA; - IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; - - IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); - } - else if (IpcRegs.IPCRECVCOM == IPC_DATA_WRITE_32) - { - pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR;; - *pulAddress = IpcRegs.IPCRECVDATA; - IpcRegs.IPCLOCALREPLY = *pulAddress; - - IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); - - } - - // - // Otherwise, only acknowledge the task flag. - // (Indicates to Remote CPU there was an error) - // - else - { - IpcRegs.IPCACK.all |= (ulFlag); - } -} - -//***************************************************************************** -// -//! Writes a 16/32-bit data word to a write-protected Local CPU system address -//! -//! \param ulFlag specifies Remote to Local IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to -//! report the status of the command sent back from the control system. -//! -//! This function will allow the Remote CPU system to write a 16/32-bit word -//! to an address on the Local CPU system. The \e ulFlag -//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, -//! and the \e ulStatusFlag parameter accepts any other one of the flag values -//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. -// -//***************************************************************************** -void -IPCLiteRtoLDataWrite_Protected(uint32_t ulFlag, uint32_t ulStatusFlag) -{ - uint32_t* pulAddress; - uint16_t* pusAddress; - - // - // Wait until IPC Remote to Local request task is flagged - // - while (!(IpcRegs.IPCSTS.all & ulFlag)) - { - } - - // - // If the command is correct for this function: - // Then enable write access with EALLOW and - // write the 16/32-bit data to the requested address - // and write back the 16/32-bit data to IPCLOCALREPLY. - // Acknowledge the status flag and the task flag. - // - EALLOW; - - if (IpcRegs.IPCRECVCOM == IPC_DATA_WRITE_16_PROTECTED) - { - pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; - *pusAddress = (uint16_t)IpcRegs.IPCRECVDATA; - IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; - - IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); - } - else if (IpcRegs.IPCRECVCOM == IPC_DATA_WRITE_32_PROTECTED) - { - pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR; - *pulAddress = IpcRegs.IPCRECVDATA; - IpcRegs.IPCLOCALREPLY = *pulAddress; - - IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); - - } - - // - // Otherwise, only acknowledge the task flag. - // (Indicates to Remote CPU there was an error) - // - else - { - IpcRegs.IPCACK.all |= (ulFlag); - } - - // - // Restore write-protection status. - // - EDIS; -} - -//***************************************************************************** -// -//! Calls a Local CPU function with a single optional parameter and return -//! value. -//! -//! \param ulFlag specifies Remote to Local IPC Flag number mask used to -//! indicate a command is being sent. -//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to -//! report the status of the command sent back from the control system. -//! -//! This function will allow the Remote CPU system to call a Local CPU function -//! with a single optional parameter and places an optional return value in the -//! IPCLOCALREPLY register. The \e ulFlag parameter accepts any one of the flag -//! values \b IPC_FLAG1 - \b IPC_FLAG32, and the \e ulStatusFlag parameter -//! accepts any other one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and -//! \b NO_FLAG. -// -//***************************************************************************** -void -IPCLiteRtoLFunctionCall(uint32_t ulFlag, uint32_t ulStatusFlag) -{ - // - // Wait until IPC Remote to Local request task is flagged - // - while (!(IpcRegs.IPCSTS.all & ulFlag)) - { - } - - // - // If the command is correct for this function: - // Then call function at requested address - // and if there is a return value, insert into - // IPCLOCALREPLY register. - // Acknowledge the status flag and the task flag. - // - if (IpcRegs.IPCRECVCOM == IPC_FUNC_CALL) - { - tfIpcFuncCall func_call = (tfIpcFuncCall)IpcRegs.IPCRECVADDR; - IpcRegs.IPCLOCALREPLY = func_call(IpcRegs.IPCRECVDATA); - - IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); - } - - // - // Otherwise, only acknowledge the task flag. - //(Indicates to Remote CPU there was an error) - // - else - { - IpcRegs.IPCACK.all |= (ulFlag); - } -} - -void DelayLoop (void) -{ - __asm(" nop"); - __asm(" nop"); - __asm(" nop"); - __asm(" nop"); - __asm(" nop"); -} - -//***************************************************************************** -// Close the Doxygen group. -//! @} -//***************************************************************************** - - diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Util.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Util.c deleted file mode 100644 index 7f98a29ea1..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Util.c +++ /dev/null @@ -1,469 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Ipc_Driver_Util.c -// -// TITLE: F2837xD Inter-Processor Communication (IPC) API Driver Utility -// Functions -// -// DESCRIPTION: -// API functions for inter-processor communications between the -// Local and Remote CPU system. -// The driver functions in this file are available only as -// sample functions for application development. Due to the generic -// nature of these functions and the cycle overhead inherent to a -// function call, the code is not intended to be used in cases where -// maximum efficiency is required in a system. -// -// NOTE: This source code is used by both CPUs. That is both CPU1 and CPU2 -// cores use this code. -// The active debug CPU will be referred to as Local CPU and the other -// CPU will be referred to as Remote CPU. -// When using this source code in CPU1, the term "local" -// will mean CPU1 and the term "remote" CPU will be mean CPU2. -// When using this source code in CPU2, the term "local" -// will mean CPU2 and the term "remote" CPU will be mean CPU1. -// -// The abbreviations LtoR and RtoL within the function names mean -// Local to Remote and Remote to Local respectively. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -//***************************************************************************** -// -//! \addtogroup ipc_util_api -//! @{ -// -//***************************************************************************** -#include "F2837xD_device.h" -#include "F2837xD_GlobalPrototypes.h" -#include "F2837xD_Gpio_defines.h" -#include "F2837xD_Ipc_drivers.h" - -//***************************************************************************** -// -//! Local CPU Acknowledges Remote to Local IPC Flag. -//! -//! \param ulFlags specifies the IPC flag mask for flags being acknowledged. -//! -//! This function will allow the Local CPU system to acknowledge/clear the IPC -//! flag set by the Remote CPU system. The \e ulFlags parameter can be any of -//! the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. -//! -//! \return None. -// -//***************************************************************************** -void -IPCRtoLFlagAcknowledge (uint32_t ulFlags) -{ - IpcRegs.IPCACK.all |= ulFlags; -} - -//***************************************************************************** -// -//! Determines whether the given Remote to Local IPC flags are busy or not. -//! -//! \param ulFlags specifies Remote to Local IPC Flag number masks to check the -//! status of. -//! -//! Allows the caller to determine whether the designated IPC flags are -//! pending. The \e ulFlags parameter can be any of the IPC flag -//! values: \b IPC_FLAG0 - \b IPC_FLAG31. -//! -//! \return Returns \b 1 if the IPC flags are busy or \b 0 if designated -//! IPC flags are free. -// -//***************************************************************************** -Uint16 -IPCRtoLFlagBusy (uint32_t ulFlags) -{ - Uint16 returnStatus; - - if ((IpcRegs.IPCSTS.all & ulFlags) == 0) - { - returnStatus = 0; - } - else - { - returnStatus = 1; - } - - return returnStatus; -} - -//***************************************************************************** -// -//! Determines whether the given IPC flags are busy or not. -//! -//! \param ulFlags specifies Local to Remote IPC Flag number masks to check the -//! status of. -//! -//! Allows the caller to determine whether the designated IPC flags are -//! available for further control to master system communication. If \b 0 is -//! returned, then all designated tasks have completed and are available. -//! The \e ulFlags parameter can be any of the IPC flag -//! values: \b IPC_FLAG0 - \b IPC_FLAG31. -//! -//! \return Returns \b 1 if the IPC flags are busy or \b 0 if designated -//! IPC flags are free. -// -//***************************************************************************** -Uint16 -IPCLtoRFlagBusy (uint32_t ulFlags) -{ - Uint16 returnStatus; - - if ((IpcRegs.IPCFLG.all & ulFlags) == 0) - { - returnStatus = 0; - } - else - { - returnStatus = 1; - } - - return returnStatus; -} - -//***************************************************************************** -// -//! Local CPU Sets Local to Remote IPC Flag -//! -//! \param ulFlags specifies the IPC flag mask for flags being set. -//! -//! This function will allow the Local CPU system to set the designated IPC -//! flags to send to the Remote CPU system. The \e ulFlags parameter can be any -//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. -//! -//! \return None. -// -//***************************************************************************** -void -IPCLtoRFlagSet (uint32_t ulFlags) -{ - IpcRegs.IPCSET.all |= ulFlags; -} - -//***************************************************************************** -// -//! Local CPU Clears Local to Remote IPC Flag -//! -//! \param ulFlags specifies the IPC flag mask for flags being set. -//! -//! This function will allow the Local CPU system to set the designated IPC -//! flags to send to the Remote CPU system. The \e ulFlags parameter can be any -//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. -//! -//! \return None. -// -//***************************************************************************** -void -IPCLtoRFlagClear (uint32_t ulFlags) -{ - IpcRegs.IPCCLR.all |= ulFlags; -} - -//***************************************************************************** -// -//! Local Return CPU02 BOOT status -//! -//! This function returns the value at IPCBOOTSTS register. -//! -//! \return Boot status. -// -//***************************************************************************** -uint32_t -IPCGetBootStatus (void) -{ - return(IpcRegs.IPCBOOTSTS); -} - -#if defined (CPU1) -//***************************************************************************** -//! Executes a CPU02 control system bootloader. -//! -//! \param ulBootMode specifies which CPU02 control system boot mode to execute. -//! -//! This function will allow the CPU01 master system to boot the CPU02 control -//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI, -//! SCI, I2C, or parallel I/O. Unlike other IPCLite driver functions, this -//! function blocks and waits until the control system boot ROM is configured -//! and ready to receive CPU01 to CPU02 IPC INT0 interrupts. It then blocks and -//! waits until IPC INT0 and IPC FLAG31 are available in the CPU02 boot ROM -//! prior to sending the command to execute the selected bootloader. The \e -//! ulBootMode parameter accepts one of the following values: \b -//! C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL, \b -//! C1C2_BROM_BOOTMODE_BOOT_FROM_SCI, \b -//! C1C2_BROM_BOOTMODE_BOOT_FROM_SPI, \b -//! C1C2_BROM_BOOTMODE_BOOT_FROM_I2C, \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN, -//! \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM, \b -//! C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH. -//! -//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is -//! invalid and command was not sent. -// -//***************************************************************************** -uint16_t -IPCBootCPU2(uint32_t ulBootMode) -{ - uint32_t bootStatus; - uint16_t pin; - uint16_t returnStatus = STATUS_PASS; - - // - // If CPU2 has already booted, return a fail to let the application - // know that something is out of the ordinary. - // - bootStatus = IPCGetBootStatus() & 0x0000000F; - - if(bootStatus == C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK) - { - // - // Check if MSB is set as well - // - bootStatus = ((uint32_t)(IPCGetBootStatus() & 0x80000000)) >> 31U; - - if(bootStatus != 0) - { - returnStatus = STATUS_FAIL; - - return returnStatus; - } - } - - // - // Wait until CPU02 control system boot ROM is ready to receive - // CPU01 to CPU02 INT1 interrupts. - // - do - { - bootStatus = IPCGetBootStatus() & C2_BOOTROM_BOOTSTS_SYSTEM_READY; - } while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY)); - - // - // Loop until CPU02 control system IPC flags 1 and 32 are available - // - while ((IPCLtoRFlagBusy(IPC_FLAG0) == 1) || - (IPCLtoRFlagBusy(IPC_FLAG31) == 1)) - { - - } - - if (ulBootMode >= C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE) - { - returnStatus = STATUS_FAIL; - } - else - { - // - // Based on boot mode, enable pull-ups on peripheral pins and - // give GPIO pin control to CPU02 control system. - // - switch (ulBootMode) - { - case C1C2_BROM_BOOTMODE_BOOT_FROM_SCI: - - EALLOW; - - // - //SCIA connected to CPU02 - // - DevCfgRegs.CPUSEL5.bit.SCI_A = 1; - - // - //Allows CPU02 bootrom to take control of clock - //configuration registers - // - ClkCfgRegs.CLKSEM.all = 0xA5A50000; - - ClkCfgRegs.LOSPCP.all = 0x0002; - EDIS; - - GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC); - GPIO_SetupPinMux(29,GPIO_MUX_CPU2,1); - - GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_ASYNC); - GPIO_SetupPinMux(28,GPIO_MUX_CPU2,1); - - break; - - case C1C2_BROM_BOOTMODE_BOOT_FROM_SPI: - EALLOW; - - // - //SPI-A connected to CPU02 - // - DevCfgRegs.CPUSEL6.bit.SPI_A = 1; - - // - //Allows CPU02 bootrom to take control of clock configuration - // registers - // - ClkCfgRegs.CLKSEM.all = 0xA5A50000; - EDIS; - - GPIO_SetupPinOptions(16, GPIO_INPUT, GPIO_ASYNC); - GPIO_SetupPinMux(16,GPIO_MUX_CPU2,1); - - GPIO_SetupPinOptions(17, GPIO_INPUT, GPIO_ASYNC); - GPIO_SetupPinMux(17,GPIO_MUX_CPU2,1); - - GPIO_SetupPinOptions(18, GPIO_INPUT, GPIO_ASYNC); - GPIO_SetupPinMux(18,GPIO_MUX_CPU2,1); - - GPIO_SetupPinOptions(19, GPIO_OUTPUT, GPIO_ASYNC); - GPIO_SetupPinMux(19,GPIO_MUX_CPU2,0); - - break; - - case C1C2_BROM_BOOTMODE_BOOT_FROM_I2C: - EALLOW; - - // - //I2CA connected to CPU02 - // - DevCfgRegs.CPUSEL7.bit.I2C_A = 1; - - // - //Allows CPU2 bootrom to take control of clock - //configuration registers - // - ClkCfgRegs.CLKSEM.all = 0xA5A50000; - ClkCfgRegs.LOSPCP.all = 0x0002; - EDIS; - GPIO_SetupPinOptions(32, GPIO_INPUT, GPIO_ASYNC); - GPIO_SetupPinMux(32,GPIO_MUX_CPU2,1); - - GPIO_SetupPinOptions(33, GPIO_INPUT, GPIO_ASYNC); - GPIO_SetupPinMux(33,GPIO_MUX_CPU2,1); - - break; - case C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL: - - for(pin=58;pin<=65;pin++) - { - GPIO_SetupPinOptions(pin, GPIO_INPUT, GPIO_ASYNC); - GPIO_SetupPinMux(pin,GPIO_MUX_CPU2,0); - } - - GPIO_SetupPinOptions(69, GPIO_OUTPUT, GPIO_ASYNC); - GPIO_SetupPinMux(69,GPIO_MUX_CPU2,0); - - GPIO_SetupPinOptions(70, GPIO_INPUT, GPIO_ASYNC); - GPIO_SetupPinMux(70,GPIO_MUX_CPU2,0); - break; - - - case C1C2_BROM_BOOTMODE_BOOT_FROM_CAN: - // - //Set up the GPIO mux to bring out CANATX on GPIO71 - //and CANARX on GPIO70 - // - EALLOW; - GpioCtrlRegs.GPCLOCK.all = 0x00000000; //Unlock GPIOs 64-95 - - // - //Give CPU2 control just in case - // - GpioCtrlRegs.GPCCSEL1.bit.GPIO71 = GPIO_MUX_CPU2; - - // - //Set the extended mux to 0x5 - // - GpioCtrlRegs.GPCGMUX1.bit.GPIO71 = 0x1; - GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 0x1; - - // - //Set qualification to async just in case - // - GpioCtrlRegs.GPCQSEL1.bit.GPIO71 = 0x3; - - GpioCtrlRegs.GPCLOCK.all = 0x00000000; //Unlock GPIOs 64-95 - - // - //Give CPU2 control just in case - // - GpioCtrlRegs.GPCCSEL1.bit.GPIO70 = GPIO_MUX_CPU2; - - // - //Set the extended mux to bring out CANATX - // - GpioCtrlRegs.GPCGMUX1.bit.GPIO70 = 0x1; - GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 0x1; - - // - //Set qualification to async just in case - // - GpioCtrlRegs.GPCQSEL1.bit.GPIO70 = 0x3; - GpioCtrlRegs.GPCLOCK.all = 0xFFFFFFFF; //Lock GPIOs 64-95 - ClkCfgRegs.CLKSRCCTL2.bit.CANABCLKSEL = 0x0; - CpuSysRegs.PCLKCR10.bit.CAN_A = 1; - EDIS; - - break; - - } - - // - //CPU01 to CPU02 IPC Boot Mode Register - // - IpcRegs.IPCBOOTMODE = ulBootMode; - - // - // CPU01 To CPU02 IPC Command Register - // - IpcRegs.IPCSENDCOM = BROM_IPC_EXECUTE_BOOTMODE_CMD; - - // - // CPU01 to CPU02 IPC flag register - // - IpcRegs.IPCSET.all = 0x80000001; - - } - - - - return returnStatus; -} - - -#endif -//***************************************************************************** -// Close the Doxygen group. -//! @} -//***************************************************************************** - - diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Mcbsp.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Mcbsp.c deleted file mode 100644 index b93b01a4ff..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Mcbsp.c +++ /dev/null @@ -1,584 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_McBSP.c -// -// TITLE: F2837xD Device McBSP Initialization & Support Functions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" - -// -// MCBSP_INIT_DELAY determines the amount of CPU cycles in the 2 sample rate -// generator (SRG) cycles required for the Mcbsp initialization routine. -// MCBSP_CLKG_DELAY determines the amount of CPU cycles in the 2 clock -// generator (CLKG) cycles required for the Mcbsp initialization routine. -// - -// -// Defines -// -#define CPU_SPD 200E6 -#define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4) - // for examples -#define CLKGDV_VAL 1 - -// # of CPU cycles in 2 SRG cycles-init delay -#define MCBSP_INIT_DELAY 2*(CPU_SPD/MCBSP_SRG_FREQ) - -// # of CPU cycles in 2 CLKG cycles-init delay -#define MCBSP_CLKG_DELAY 2*(CPU_SPD/(MCBSP_SRG_FREQ/(1+CLKGDV_VAL))) - -// -// Function Prototypes -// -void delay_loop(void); // Delay function used for SRG initialization -void clkg_delay_loop(void); // Delay function used for CLKG initialization - -// -// InitMcbsp - This function initializes the McBSP to a known state. -// -void InitMcbspa(void) -{ - // - // Reset the McBSP - // Disable all interrupts - // Frame sync generator reset - // Sample rate generator reset - // Transmitter reset - // Receiver reset - // - McbspaRegs.SPCR2.bit.FRST = 0; - McbspaRegs.SPCR2.bit.GRST = 0; - McbspaRegs.SPCR2.bit.XRST = 0; - McbspaRegs.SPCR1.bit.RRST = 0; - - // - // Enable loop back mode - // This does not require external hardware - // - McbspaRegs.SPCR2.all = 0x0000; - McbspaRegs.SPCR1.all = 0x8000; - - // - // RX data delay is 1 bit - // TX data delay is 1 bit - // - McbspaRegs.RCR2.bit.RDATDLY = 1; - McbspaRegs.XCR2.bit.XDATDLY = 1; - - // - // No clock sync for CLKG - // Frame-synchronization period - // - McbspaRegs.SRGR2.bit.GSYNC = 0; - McbspaRegs.SRGR2.bit.FPER = 320; - - // - // Frame-synchronization pulses from - // the sample rate generator - // - McbspaRegs.SRGR2.bit.FSGM = 1; - - // - // Sample rate generator input clock is LSPCLK - // - McbspaRegs.SRGR2.bit.CLKSM = 1; - McbspaRegs.PCR.bit.SCLKME = 0; - - // - // Divide-down value for CLKG - // Frame-synchronization pulse width - // - McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; - clkg_delay_loop(); - McbspaRegs.SRGR1.bit.FWID = 1; - - // - // CLKX is driven by the sample rate generator - // Transmit frame synchronization generated by internal - // sample rate generator - // - McbspaRegs.PCR.bit.CLKXM = 1; - McbspaRegs.PCR.bit.FSXM = 1; - - // - // Enable Sample rate generator and - // wait at least 2 CLKG clock cycles - // - McbspaRegs.SPCR2.bit.GRST = 1; - clkg_delay_loop(); - - // - // Release from reset - // RX, TX and frame sync generator - // - McbspaRegs.SPCR2.bit.XRST = 1; - McbspaRegs.SPCR1.bit.RRST = 1; - McbspaRegs.SPCR2.bit.FRST = 1; -} - -// -// InitMcbspaInt - Enable TX and RX interrupts -// -void InitMcbspaInt(void) -{ - // Reset TX and RX - // Enable interrupts for TX and RX - // Release TX and RX - McbspaRegs.SPCR2.bit.XRST = 0; - McbspaRegs.SPCR1.bit.RRST = 0; - McbspaRegs.MFFINT.bit.XINT = 1; - McbspaRegs.MFFINT.bit.RINT = 1; - McbspaRegs.SPCR2.bit.XRST = 1; - McbspaRegs.SPCR1.bit.RRST = 1; -} - -// -// InitMcbspa8bit - McBSP uses an 8-bit word for both TX and RX -// -void InitMcbspa8bit(void) -{ - McbspaRegs.RCR1.bit.RWDLEN1 = 0; - McbspaRegs.XCR1.bit.XWDLEN1 = 0; -} - -// -// InitMcbspa12bit - McBSP uses an 12-bit word for both TX and RX -// -void InitMcbspa12bit(void) -{ - McbspaRegs.RCR1.bit.RWDLEN1 = 1; - McbspaRegs.XCR1.bit.XWDLEN1 = 1; -} - -// -// InitMcbspa16bit - McBSP uses an 16-bit word for both TX and RX -// -void InitMcbspa16bit(void) -{ - McbspaRegs.RCR1.bit.RWDLEN1 = 2; - McbspaRegs.XCR1.bit.XWDLEN1 = 2; -} - -// -// InitMcbspa20bit - McBSP uses an 20-bit word for both TX and RX -// -void InitMcbspa20bit(void) -{ - McbspaRegs.RCR1.bit.RWDLEN1 = 3; - McbspaRegs.XCR1.bit.XWDLEN1 = 3; -} - -// -// InitMcbspa24bit - McBSP uses an 24-bit word for both TX and RX -// -void InitMcbspa24bit(void) -{ - McbspaRegs.RCR1.bit.RWDLEN1 = 4; - McbspaRegs.XCR1.bit.XWDLEN1 = 4; -} - -// -// InitMcbspa32bit - McBSP uses an 32-bit word for both TX and RX -// -void InitMcbspa32bit(void) -{ - McbspaRegs.RCR1.bit.RWDLEN1 = 5; - McbspaRegs.XCR1.bit.XWDLEN1 = 5; -} - -// -// InitMcbspaGpio - Assign GPIO pins to the McBSP peripheral -// (Note: This function must be called from CPU1.) -// -void InitMcbspaGpio(void) -{ -#ifdef CPU1 - EALLOW; - - // - // This specifies which of the possible GPIO pins will be - // McBSPA functional pins. Comment out unwanted connections. - // Set qualification for selected input pins to asynchronous only - // This will select asynchronous (no qualification) for the selected pins. - // - - // - // MDXA - // GPIO20 - // GPIO84 - // - GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2; - //GpioCtrlRegs.GPCGMUX2.bit.GPIO84 = 3; - //GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; - - // - // MDRA - // GPIO21 with asynchronous qualification - // GPIO85 with asynchronous qualification - // - GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2; - GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; - //GpioCtrlRegs.GPCGMUX2.bit.GPIO85 = 3; - //GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; - //GpioCtrlRegs.GPCQSEL2.bit.GPIO85 = 3; - - // - // MCLKXA - // GPIO22 with asynchronous qualification - // GPIO86 with asynchronous qualification - // - GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2; - //GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3; - //GpioCtrlRegs.GPCGMUX2.bit.GPIO86 = 3; - //GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; - //GpioCtrlRegs.GPCQSEL2.bit.GPIO86 = 3; - - // - // MCLKRA - // Select one of the following - // GPIO7 with asynchronous qualification - // GPIO58 with asynchronous qualification - // - GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2; - GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3; - //GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1; - //GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; - - // - // MFSXA - // GPIO23 with asynchronous qualification - // GPIO87 with asynchronous qualification - // - GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2; - //GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; - //GpioCtrlRegs.GPCGMUX2.bit.GPIO87 = 3; - //GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; - //GpioCtrlRegs.GPCQSEL2.bit.GPIO87 = 3; - - // - // MFSRA - // Select one of the following - // GPIO5 with asynchronous qualification - // GPIO59 with asynchronous qualification - // - GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; - GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; - //GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1; - //GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; - - EDIS; -#endif -} - -// -// InitMcbspb - McBSPB initialization routine for examples -// -void InitMcbspb(void) -{ - // - // Reset the McBSP - // Disable all interrupts - // Frame sync generator reset - // Sample rate generator reset - // Transmitter reset - // Receiver reset - // - McbspbRegs.SPCR2.bit.FRST = 0; - McbspbRegs.SPCR2.bit.GRST = 0; - McbspbRegs.SPCR2.bit.XRST = 0; - McbspbRegs.SPCR1.bit.RRST = 0; - - // - // Enable loop back mode - // This does not require external hardware - // - McbspbRegs.SPCR2.all = 0x0000; - McbspbRegs.SPCR1.all = 0x8000; - - // - // RX data delay is 1 bit - // TX data delay is 1 bit - // - McbspbRegs.RCR2.bit.RDATDLY = 1; - McbspbRegs.XCR2.bit.XDATDLY = 1; - - // - // No clock sync for CLKG - // Frame-synchronization period - // - McbspbRegs.SRGR2.bit.GSYNC = 0; - McbspbRegs.SRGR2.bit.FPER = 320; - - // - // Frame-synchronization pulses from - // the sample rate generator - // - McbspbRegs.SRGR2.bit.FSGM = 1; - - // - // Sample rate generator input clock is LSPCLK - // - McbspbRegs.SRGR2.bit.CLKSM = 1; - McbspbRegs.PCR.bit.SCLKME = 0; - - // - // Divide-down value for CLKG - // Frame-synchronization pulse width - // - McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; - clkg_delay_loop(); - McbspbRegs.SRGR1.bit.FWID = 1; - - // - // CLKX is driven by the sample rate generator - // Transmit frame synchronization generated by internal - // sample rate generator - // - McbspbRegs.PCR.bit.CLKXM = 1; - McbspbRegs.PCR.bit.FSXM = 1; - - // - // Enable Sample rate generator and - // wait at least 2 CLKG clock cycles - // - McbspbRegs.SPCR2.bit.GRST = 1; - clkg_delay_loop(); - - // - // Release from reset - // RX, TX and frame sync generator - // - McbspbRegs.SPCR2.bit.XRST = 1; - McbspbRegs.SPCR1.bit.RRST = 1; - McbspbRegs.SPCR2.bit.FRST = 1; -} - -// -// InitMcbspbInt - Enable TX and RX interrupts -// -void InitMcbspbInt(void) -{ - // - // Reset TX and RX - // Enable interrupts for TX and RX - // Release TX and RX - // - McbspbRegs.SPCR2.bit.XRST = 0; - McbspbRegs.SPCR1.bit.RRST = 0; - McbspbRegs.MFFINT.bit.XINT = 1; - McbspbRegs.MFFINT.bit.RINT = 1; - McbspbRegs.SPCR2.bit.XRST = 1; - McbspbRegs.SPCR1.bit.RRST = 1; -} - -// -// InitMcbspb8bit - McBSPB uses an 8-bit word for both TX and RX -// -void InitMcbspb8bit(void) -{ - McbspbRegs.RCR1.bit.RWDLEN1 = 0; - McbspbRegs.XCR1.bit.XWDLEN1 = 0; -} - -// -// IniMcbspb12bit - McBSPB uses an 12-bit word for both TX and RX -// -void IniMcbspb12bit(void) -{ - McbspbRegs.RCR1.bit.RWDLEN1 = 1; - McbspbRegs.XCR1.bit.XWDLEN1 = 1; -} - -// -// InitMcbspb16bit - McBSPB uses an 16-bit word for both TX and RX -// -void InitMcbspb16bit(void) -{ - McbspbRegs.RCR1.bit.RWDLEN1 = 2; - McbspbRegs.XCR1.bit.XWDLEN1 = 2; -} - -// -// InitMcbspb20bit - McBSPB uses an 20-bit word for both TX and RX -// -void InitMcbspb20bit(void) -{ - McbspbRegs.RCR1.bit.RWDLEN1 = 3; - McbspbRegs.XCR1.bit.XWDLEN1 = 3; -} - -// -// InitMcbspb24bit - McBSPB uses an 24-bit word for both TX and RX -// -void InitMcbspb24bit(void) -{ - McbspbRegs.RCR1.bit.RWDLEN1 = 4; - McbspbRegs.XCR1.bit.XWDLEN1 = 4; -} - -// -// InitMcbspb32bit - McBSPB uses an 32-bit word for both TX and RX -// -void InitMcbspb32bit(void) -{ - McbspbRegs.RCR1.bit.RWDLEN1 = 5; - McbspbRegs.XCR1.bit.XWDLEN1 = 5; -} - -// -// InitMcbspbGpio - Assign GPIO pins to the McBSP peripheral -// (Note: This function must be called from CPU1.) -// -void InitMcbspbGpio(void) -{ -#ifdef CPU1 - EALLOW; - - // - // This specifies which of the possible GPIO pins will be - // McBSPB functional pins. Comment out unwanted connections. - // Set qualification for selected input pins to asynchronous only - // This will select asynchronous (no qualification) for the selected pins. - // - - // - // Select one of the following for MDXB - // GPIO24 - // GPIO84 - // - //GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3; - GpioCtrlRegs.GPCGMUX2.bit.GPIO84 = 1; - GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 2; - - // - // MDRB - // GPIO13 with asynchronous qualification - // GPIO25 with asynchronous qualification - // GPIO85 with asynchronous qualification - // - //GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; - //GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; - //GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3; - //GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; - GpioCtrlRegs.GPCGMUX2.bit.GPIO85 = 1; - GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 2; - GpioCtrlRegs.GPCQSEL2.bit.GPIO85 = 3; - - // - // MCLKXB - // GPIO14 with asynchronous qualification - // GPIO26 with asynchronous qualification - // GPIO86 with asynchronous qualification - // - //GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; - //GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; - //GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3; - //GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; - GpioCtrlRegs.GPCGMUX2.bit.GPIO86 = 1; - GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 2; - GpioCtrlRegs.GPCQSEL2.bit.GPIO86= 3; - - // - // MCLKRB - // Select one of the following - // GPIO3 with asynchronous qualification - // GPIO60 with asynchronous qualification - // - //GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 3; - //GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; - GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 1; - GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; - - // - // MFSXB - // GPIO15 with asynchronous qualification - // GPIO27 with asynchronous qualification - // GPIO87 with asynchronous qualification - // - //GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; - //GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; - //GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 3; - //GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; - GpioCtrlRegs.GPCGMUX2.bit.GPIO87 = 1; - GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 2; - GpioCtrlRegs.GPCQSEL2.bit.GPIO87= 3; - - // - // MFSRB - // Select one of the following - // GPIO1 with asynchronous qualification - // GPIO61 with asynchronous qualification - // - //GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 3; - //GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; - GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 1; - GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; - - EDIS; - -#endif -} - -// -// delay_loop - Delay function (at least 2 SRG cycles) -// Required in McBSP initialization -// -void delay_loop(void) -{ - long i; - for (i = 0; i < MCBSP_INIT_DELAY; i++) {} -} - -// -// clkg_delay_loop - Delay function (at least 2 CLKG cycles) -// Required in McBSP init -// -void clkg_delay_loop(void) -{ - long i; - for (i = 0; i < MCBSP_CLKG_DELAY; i++) {} -} - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_PieCtrl.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_PieCtrl.c deleted file mode 100644 index e6be2e920c..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_PieCtrl.c +++ /dev/null @@ -1,121 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_PieCtrl.c -// -// TITLE: F2837xD Device PIE Control Register Initialization Functions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" // F2837xD Headerfile Include File -#include "F2837xD_Examples.h" // F2837xD Examples Include File - -// -// InitPieCtrl - This function initializes the PIE control registers to a -// known state. -// -void InitPieCtrl(void) -{ - // - // Disable Interrupts at the CPU level: - // - DINT; - - // - // Disable the PIE - // - PieCtrlRegs.PIECTRL.bit.ENPIE = 0; - - // - // Clear all PIEIER registers: - // - PieCtrlRegs.PIEIER1.all = 0; - PieCtrlRegs.PIEIER2.all = 0; - PieCtrlRegs.PIEIER3.all = 0; - PieCtrlRegs.PIEIER4.all = 0; - PieCtrlRegs.PIEIER5.all = 0; - PieCtrlRegs.PIEIER6.all = 0; - PieCtrlRegs.PIEIER7.all = 0; - PieCtrlRegs.PIEIER8.all = 0; - PieCtrlRegs.PIEIER9.all = 0; - PieCtrlRegs.PIEIER10.all = 0; - PieCtrlRegs.PIEIER11.all = 0; - PieCtrlRegs.PIEIER12.all = 0; - - // - // Clear all PIEIFR registers: - // - PieCtrlRegs.PIEIFR1.all = 0; - PieCtrlRegs.PIEIFR2.all = 0; - PieCtrlRegs.PIEIFR3.all = 0; - PieCtrlRegs.PIEIFR4.all = 0; - PieCtrlRegs.PIEIFR5.all = 0; - PieCtrlRegs.PIEIFR6.all = 0; - PieCtrlRegs.PIEIFR7.all = 0; - PieCtrlRegs.PIEIFR8.all = 0; - PieCtrlRegs.PIEIFR9.all = 0; - PieCtrlRegs.PIEIFR10.all = 0; - PieCtrlRegs.PIEIFR11.all = 0; - PieCtrlRegs.PIEIFR12.all = 0; -} - -// -// EnableInterrupts - This function enables the PIE module and CPU __interrupts -// -void EnableInterrupts() -{ - // - // Enable the PIE - // - PieCtrlRegs.PIECTRL.bit.ENPIE = 1; - - // - // Enables PIE to drive a pulse into the CPU - // - PieCtrlRegs.PIEACK.all = 0xFFFF; - - // - // Enable Interrupts at the CPU level - // - EINT; -} - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_PieVect.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_PieVect.c deleted file mode 100644 index 20e8fbf74b..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_PieVect.c +++ /dev/null @@ -1,320 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_PieVect.c -// -// TITLE: F2837xD Device PIE Vector Initialization Functions -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" - -// -// Globals -// -const struct PIE_VECT_TABLE PieVectTableInit = { - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - TIMER1_ISR, // CPU Timer 1 Interrupt - TIMER2_ISR, // CPU Timer 2 Interrupt - DATALOG_ISR, // Datalogging Interrupt - RTOS_ISR, // RTOS Interrupt - EMU_ISR, // Emulation Interrupt - NMI_ISR, // Non-Maskable Interrupt - ILLEGAL_ISR, // Illegal Operation Trap - USER1_ISR, // User Defined Trap 1 - USER2_ISR, // User Defined Trap 2 - USER3_ISR, // User Defined Trap 3 - USER4_ISR, // User Defined Trap 4 - USER5_ISR, // User Defined Trap 5 - USER6_ISR, // User Defined Trap 6 - USER7_ISR, // User Defined Trap 7 - USER8_ISR, // User Defined Trap 8 - USER9_ISR, // User Defined Trap 9 - USER10_ISR, // User Defined Trap 10 - USER11_ISR, // User Defined Trap 11 - USER12_ISR, // User Defined Trap 12 - ADCA1_ISR, // 1.1 - ADCA Interrupt 1 - ADCB1_ISR, // 1.2 - ADCB Interrupt 1 - ADCC1_ISR, // 1.3 - ADCC Interrupt 1 - XINT1_ISR, // 1.4 - XINT1 Interrupt - XINT2_ISR, // 1.5 - XINT2 Interrupt - ADCD1_ISR, // 1.6 - ADCD Interrupt 1 - TIMER0_ISR, // 1.7 - Timer 0 Interrupt - WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt - EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt - EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt - EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt - EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt - EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt - EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt - EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt - EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt - EPWM1_ISR, // 3.1 - ePWM1 Interrupt - EPWM2_ISR, // 3.2 - ePWM2 Interrupt - EPWM3_ISR, // 3.3 - ePWM3 Interrupt - EPWM4_ISR, // 3.4 - ePWM4 Interrupt - EPWM5_ISR, // 3.5 - ePWM5 Interrupt - EPWM6_ISR, // 3.6 - ePWM6 Interrupt - EPWM7_ISR, // 3.7 - ePWM7 Interrupt - EPWM8_ISR, // 3.8 - ePWM8 Interrupt - ECAP1_ISR, // 4.1 - eCAP1 Interrupt - ECAP2_ISR, // 4.2 - eCAP2 Interrupt - ECAP3_ISR, // 4.3 - eCAP3 Interrupt - ECAP4_ISR, // 4.4 - eCAP4 Interrupt - ECAP5_ISR, // 4.5 - eCAP5 Interrupt - ECAP6_ISR, // 4.6 - eCAP6 Interrupt - PIE_RESERVED_ISR, // 4.7 - Reserved - PIE_RESERVED_ISR, // 4.8 - Reserved - EQEP1_ISR, // 5.1 - eQEP1 Interrupt - EQEP2_ISR, // 5.2 - eQEP2 Interrupt - EQEP3_ISR, // 5.3 - eQEP3 Interrupt - PIE_RESERVED_ISR, // 5.4 - Reserved - PIE_RESERVED_ISR, // 5.5 - Reserved - PIE_RESERVED_ISR, // 5.6 - Reserved - PIE_RESERVED_ISR, // 5.7 - Reserved - PIE_RESERVED_ISR, // 5.8 - Reserved - SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt - SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt - SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt - SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt - MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt - MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt - MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt - MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt - DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt - DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt - DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt - DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt - DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt - DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt - PIE_RESERVED_ISR, // 7.7 - Reserved - PIE_RESERVED_ISR, // 7.8 - Reserved - I2CA_ISR, // 8.1 - I2CA Interrupt 1 - I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2 - I2CB_ISR, // 8.3 - I2CB Interrupt 1 - I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2 - SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt - SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt - SCID_RX_ISR, // 8.7 - SCID Receive Interrupt - SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt - SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt - SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt - SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt - SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt - CANA0_ISR, // 9.5 - CANA Interrupt 0 - CANA1_ISR, // 9.6 - CANA Interrupt 1 - CANB0_ISR, // 9.7 - CANB Interrupt 0 - CANB1_ISR, // 9.8 - CANB Interrupt 1 - ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt - ADCA2_ISR, // 10.2 - ADCA Interrupt 2 - ADCA3_ISR, // 10.3 - ADCA Interrupt 3 - ADCA4_ISR, // 10.4 - ADCA Interrupt 4 - ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt - ADCB2_ISR, // 10.6 - ADCB Interrupt 2 - ADCB3_ISR, // 10.7 - ADCB Interrupt 3 - ADCB4_ISR, // 10.8 - ADCB Interrupt 4 - CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1 - CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2 - CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3 - CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4 - CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5 - CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6 - CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7 - CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8 - XINT3_ISR, // 12.1 - XINT3 Interrupt - XINT4_ISR, // 12.2 - XINT4 Interrupt - XINT5_ISR, // 12.3 - XINT5 Interrupt - PIE_RESERVED_ISR, // 12.4 - Reserved - PIE_RESERVED_ISR, // 12.5 - Reserved - VCU_ISR, // 12.6 - VCU Interrupt - FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt - FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt - PIE_RESERVED_ISR, // 1.9 - Reserved - PIE_RESERVED_ISR, // 1.10 - Reserved - PIE_RESERVED_ISR, // 1.11 - Reserved - PIE_RESERVED_ISR, // 1.12 - Reserved - IPC0_ISR, // 1.13 - IPC Interrupt 0 - IPC1_ISR, // 1.14 - IPC Interrupt 1 - IPC2_ISR, // 1.15 - IPC Interrupt 2 - IPC3_ISR, // 1.16 - IPC Interrupt 3 - EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt - EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt - EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt - EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt - PIE_RESERVED_ISR, // 2.13 - Reserved - PIE_RESERVED_ISR, // 2.14 - Reserved - PIE_RESERVED_ISR, // 2.15 - Reserved - PIE_RESERVED_ISR, // 2.16 - Reserved - EPWM9_ISR, // 3.9 - ePWM9 Interrupt - EPWM10_ISR, // 3.10 - ePWM10 Interrupt - EPWM11_ISR, // 3.11 - ePWM11 Interrupt - EPWM12_ISR, // 3.12 - ePWM12 Interrupt - PIE_RESERVED_ISR, // 3.13 - Reserved - PIE_RESERVED_ISR, // 3.14 - Reserved - PIE_RESERVED_ISR, // 3.15 - Reserved - PIE_RESERVED_ISR, // 3.16 - Reserved - PIE_RESERVED_ISR, // 4.9 - Reserved - PIE_RESERVED_ISR, // 4.10 - Reserved - PIE_RESERVED_ISR, // 4.11 - Reserved - PIE_RESERVED_ISR, // 4.12 - Reserved - PIE_RESERVED_ISR, // 4.13 - Reserved - PIE_RESERVED_ISR, // 4.14 - Reserved - PIE_RESERVED_ISR, // 4.15 - Reserved - PIE_RESERVED_ISR, // 4.16 - Reserved - SD1_ISR, // 5.9 - SD1 Interrupt - SD2_ISR, // 5.10 - SD2 Interrupt - PIE_RESERVED_ISR, // 5.11 - Reserved - PIE_RESERVED_ISR, // 5.12 - Reserved - PIE_RESERVED_ISR, // 5.13 - Reserved - PIE_RESERVED_ISR, // 5.14 - Reserved - PIE_RESERVED_ISR, // 5.15 - Reserved - PIE_RESERVED_ISR, // 5.16 - Reserved - SPIC_RX_ISR, // 6.9 - SPIC Receive Interrupt - SPIC_TX_ISR, // 6.10 - SPIC Transmit Interrupt - PIE_RESERVED_ISR, // 6.11 - Reserved - PIE_RESERVED_ISR, // 6.12 - Reserved - PIE_RESERVED_ISR, // 6.13 - Reserved - PIE_RESERVED_ISR, // 6.14 - Reserved - PIE_RESERVED_ISR, // 6.15 - Reserved - PIE_RESERVED_ISR, // 6.16 - Reserved - PIE_RESERVED_ISR, // 7.9 - Reserved - PIE_RESERVED_ISR, // 7.10 - Reserved - PIE_RESERVED_ISR, // 7.11 - Reserved - PIE_RESERVED_ISR, // 7.12 - Reserved - PIE_RESERVED_ISR, // 7.13 - Reserved - PIE_RESERVED_ISR, // 7.14 - Reserved - PIE_RESERVED_ISR, // 7.15 - Reserved - PIE_RESERVED_ISR, // 7.16 - Reserved - PIE_RESERVED_ISR, // 8.9 - Reserved - PIE_RESERVED_ISR, // 8.10 - Reserved - PIE_RESERVED_ISR, // 8.11 - Reserved - PIE_RESERVED_ISR, // 8.12 - Reserved - PIE_RESERVED_ISR, // 8.13 - Reserved - PIE_RESERVED_ISR, // 8.14 - Reserved -#ifdef CPU1 - UPPA_ISR, // 8.15 - uPPA Interrupt - PIE_RESERVED_ISR, // 8.16 - Reserved -#elif defined(CPU2) - PIE_RESERVED_ISR, // 8.15 - Reserved - PIE_RESERVED_ISR, // 8.16 - Reserved -#endif - PIE_RESERVED_ISR, // 9.9 - Reserved - PIE_RESERVED_ISR, // 9.10 - Reserved - PIE_RESERVED_ISR, // 9.11 - Reserved - PIE_RESERVED_ISR, // 9.12 - Reserved - PIE_RESERVED_ISR, // 9.13 - Reserved - PIE_RESERVED_ISR, // 9.14 - Reserved -#ifdef CPU1 - USBA_ISR, // 9.15 - USBA Interrupt -#elif defined(CPU2) - PIE_RESERVED_ISR, // 9.15 - Reserved -#endif - PIE_RESERVED_ISR, // 9.16 - Reserved - ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt - ADCC2_ISR, // 10.10 - ADCC Interrupt 2 - ADCC3_ISR, // 10.11 - ADCC Interrupt 3 - ADCC4_ISR, // 10.12 - ADCC Interrupt 4 - ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt - ADCD2_ISR, // 10.14 - ADCD Interrupt 2 - ADCD3_ISR, // 10.15 - ADCD Interrupt 3 - ADCD4_ISR, // 10.16 - ADCD Interrupt 4 - PIE_RESERVED_ISR, // 11.9 - Reserved - PIE_RESERVED_ISR, // 11.10 - Reserved - PIE_RESERVED_ISR, // 11.11 - Reserved - PIE_RESERVED_ISR, // 11.12 - Reserved - PIE_RESERVED_ISR, // 11.13 - Reserved - PIE_RESERVED_ISR, // 11.14 - Reserved - PIE_RESERVED_ISR, // 11.15 - Reserved - PIE_RESERVED_ISR, // 11.16 - Reserved - EMIF_ERROR_ISR, // 12.9 - EMIF Error Interrupt - RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt - FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt - RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt - SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt - AUX_PLL_SLIP_ISR, // 12.14 - Auxiliary PLL Slip Interrupt - CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt - CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt -}; - -// -// InitPieVectTable - This function initializes the PIE vector table to a -// known state and must be executed after boot time. -// -void InitPieVectTable(void) -{ - Uint16 i; - Uint32 *Source = (void *) &PieVectTableInit; - Uint32 *Dest = (void *) &PieVectTable; - - // - // Do not write over first 3 32-bit locations (these locations are - // initialized by Boot ROM with boot variables) - // - Source = Source + 3; - Dest = Dest + 3; - - EALLOW; - for(i = 0; i < 221; i++) - { - *Dest++ = *Source++; - } - EDIS; - - // - // Enable the PIE Vector Table - // - PieCtrlRegs.PIECTRL.bit.ENPIE = 1; -} - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_SWPrioritizedPieVect.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_SWPrioritizedPieVect.c deleted file mode 100644 index 7c2b5d1f56..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_SWPrioritizedPieVect.c +++ /dev/null @@ -1,967 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_SWPrioritizedPieVect.c -// -// TITLE: F2837xD Devices SW Prioritized PIE Vector Table Initialization. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" -#include "F2837xD_SWPrioritizedIsrLevels.h" - -const struct PIE_VECT_TABLE PieVectTableInit = -{ - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - PIE_RESERVED_ISR, // Reserved - - // - // Non-Peripheral Interrupts: - // - #if (INT13PL != 0) - TIMER1_ISR, // CPU Timer 1 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (INT14PL != 0) - TIMER2_ISR, // CPU Timer 2 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (INT15PL != 0) - DATALOG_ISR, // Datalogging interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (INT16PL != 0) - RTOS_ISR, // RTOS Interrupt - #else - INT_NOTUSED_ISR, - #endif - - EMU_ISR, // Emulation Interrupt - NMI_ISR, // Non-Maskable Interrupt - ILLEGAL_ISR, // Illegal Operation Trap - USER1_ISR, // User Defined Trap 1 - USER2_ISR, // User Defined Trap 2 - USER3_ISR, // User Defined Trap 3 - USER4_ISR, // User Defined Trap 4 - USER5_ISR, // User Defined Trap 5 - USER6_ISR, // User Defined Trap 6 - USER7_ISR, // User Defined Trap 7 - USER8_ISR, // User Defined Trap 8 - USER9_ISR, // User Defined Trap 9 - USER10_ISR, // User Defined Trap 10 - USER11_ISR, // User Defined Trap 11 - USER12_ISR, // User Defined Trap 12 - - // - // Group 1 PIE Vectors: - // - #if (G1_1PL != 0) - ADCA1_ISR, // 1.1 - ADCA Interrupt 1 - #else - INT_NOTUSED_ISR, - #endif - - #if (G1_2PL != 0) - ADCB1_ISR, // 1.2 - ADCB Interrupt 1 - #else - INT_NOTUSED_ISR, - #endif - - #if (G1_3PL != 0) - ADCC1_ISR, // 1.3 - ADCC Interrupt 1 - #else - INT_NOTUSED_ISR, - #endif - - #if (G1_4PL != 0) - XINT1_ISR, // 1.4 - XINT1 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G1_5PL != 0) - XINT2_ISR, // 1.5 - XINT2 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G1_6PL != 0) - ADCD1_ISR, // 1.6 - ADCD Interrupt 1 - #else - INT_NOTUSED_ISR, - #endif - - #if (G1_7PL != 0) - TIMER0_ISR, // 1.7 - Timer 0 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G1_8PL != 0) - WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt - #else - INT_NOTUSED_ISR, - #endif - - // - // Group 2 PIE Vectors: - // - #if (G2_1PL != 0) - EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G2_2PL != 0) - EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G2_3PL != 0) - EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G2_4PL != 0) - EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G2_5PL != 0) - EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G2_6PL != 0) - EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G2_7PL != 0) - EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G2_8PL != 0) - EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt - #else - INT_NOTUSED_ISR, - #endif - - // - // Group 3 PIE Vectors: - // - #if (G3_1PL != 0) - EPWM1_ISR, // 3.1 - ePWM1 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G3_2PL != 0) - EPWM2_ISR, // 3.2 - ePWM2 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G3_3PL != 0) - EPWM3_ISR, // 3.3 - ePWM3 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G3_4PL != 0) - EPWM4_ISR, // 3.4 - ePWM4 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G3_5PL != 0) - EPWM5_ISR, // 3.5 - ePWM5 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G3_6PL != 0) - EPWM6_ISR, // 3.6 - ePWM6 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G3_7PL != 0) - EPWM7_ISR, // 3.7 - ePWM7 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G3_8PL != 0) - EPWM8_ISR, // 3.8 - ePWM8 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - // - // Group 4 PIE Vectors: - // - #if (G4_1PL != 0) - ECAP1_ISR, // 4.1 - eCAP1 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G4_2PL != 0) - ECAP2_ISR, // 4.2 - eCAP2 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G4_3PL != 0) - ECAP3_ISR, // 4.3 - eCAP3 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G4_4PL != 0) - ECAP4_ISR, // 4.4 - eCAP4 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G4_5PL != 0) - ECAP5_ISR, // 4.5 - eCAP5 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G4_6PL != 0) - ECAP6_ISR, // 4.6 - eCAP6 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - PIE_RESERVED_ISR, // 4.7 - Reserved - PIE_RESERVED_ISR, // 4.8 - Reserved - - // - // Group 5 PIE Vectors: - // - #if (G5_1PL != 0) - EQEP1_ISR, // 5.1 - eQEP1 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G5_2PL != 0) - EQEP2_ISR, // 5.2 - eQEP2 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G5_3PL != 0) - EQEP3_ISR, // 5.3 - eQEP3 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - PIE_RESERVED_ISR, // 5.4 - Reserved - PIE_RESERVED_ISR, // 5.5 - Reserved - PIE_RESERVED_ISR, // 5.6 - Reserved - PIE_RESERVED_ISR, // 5.7 - Reserved - PIE_RESERVED_ISR, // 5.8 - Reserved - - // - // Group 6 PIE Vectors: - // - #if (G6_1PL != 0) - SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G6_2PL != 0) - SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G6_3PL != 0) - SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G6_4PL != 0) - SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G6_5PL != 0) - MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G6_6PL != 0) - MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G6_7PL != 0) - MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G6_8PL != 0) - MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt - #else - INT_NOTUSED_ISR, - #endif - - // - // Group 7 PIE Vectors: - // - #if (G7_1PL != 0) - DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G7_2PL != 0) - DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G7_3PL != 0) - DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G7_4PL != 0) - DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G7_5PL != 0) - DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G7_6PL != 0) - DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - PIE_RESERVED_ISR, // 7.7 - Reserved - PIE_RESERVED_ISR, // 7.8 - Reserved - - // - // Group 8 PIE Vectors: - // - #if (G8_1PL != 0) - I2CA_ISR, // 8.1 - I2CA Interrupt 1 - #else - INT_NOTUSED_ISR, - #endif - - #if (G8_2PL != 0) - I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2 - #else - INT_NOTUSED_ISR, - #endif - - #if (G8_3PL != 0) - I2CB_ISR, // 8.3 - I2CB Interrupt 1 - #else - INT_NOTUSED_ISR, - #endif - - #if (G8_4PL != 0) - I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2 - #else - INT_NOTUSED_ISR, - #endif - - #if (G8_5PL != 0) - SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G8_6PL != 0) - SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G8_7PL != 0) - SCID_RX_ISR, // 8.7 - SCID Receive Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G8_8PL != 0) - SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt - #else - INT_NOTUSED_ISR, - #endif - - // - // Group 9 PIE Vectors: - // - #if (G9_1PL != 0) - SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G9_2PL != 0) - SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G9_3PL != 0) - SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G9_4PL != 0) - SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G9_5PL != 0) - CANA0_ISR, // 9.5 - CANA Interrupt 0 - #else - INT_NOTUSED_ISR, - #endif - - #if (G9_6PL != 0) - CANA1_ISR, // 9.6 - CANA Interrupt 1 - #else - INT_NOTUSED_ISR, - #endif - - #if (G9_7PL != 0) - CANB0_ISR, // 9.7 - CANB Interrupt 0 - #else - INT_NOTUSED_ISR, - #endif - - #if (G9_8PL != 0) - CANB1_ISR, // 9.8 - CANB Interrupt 1 - #else - INT_NOTUSED_ISR, - #endif - - // - // Group 10 PIE Vectors - // - #if (G10_1PL != 0) - ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G10_2PL != 0) - ADCA2_ISR, // 10.2 - ADCA Interrupt 2 - #else - INT_NOTUSED_ISR, - #endif - - #if (G10_3PL != 0) - ADCA3_ISR, // 10.3 - ADCA Interrupt 3 - #else - INT_NOTUSED_ISR, - #endif - - #if (G10_4PL != 0) - ADCA4_ISR, // 10.4 - ADCA Interrupt 4 - #else - INT_NOTUSED_ISR, - #endif - - #if (G10_5PL != 0) - ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G10_6PL != 0) - ADCB2_ISR, // 10.6 - ADCB Interrupt 2 - #else - INT_NOTUSED_ISR, - #endif - - #if (G10_7PL != 0) - ADCB3_ISR, // 10.7 - ADCB Interrupt 3 - #else - INT_NOTUSED_ISR, - #endif - - #if (G10_8PL != 0) - ADCB4_ISR, // 10.8 - ADCB Interrupt 4 - #else - INT_NOTUSED_ISR, - #endif - - // - // Group 11 PIE Vectors - // - #if (G11_1PL != 0) - CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1 - #else - INT_NOTUSED_ISR, - #endif - - #if (G11_2PL != 0) - CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2 - #else - INT_NOTUSED_ISR, - #endif - - #if (G11_3PL != 0) - CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3 - #else - INT_NOTUSED_ISR, - #endif - - #if (G11_4PL != 0) - CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4 - #else - INT_NOTUSED_ISR, - #endif - - #if (G11_5PL != 0) - CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5 - #else - INT_NOTUSED_ISR, - #endif - - #if (G11_6PL != 0) - CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6 - #else - INT_NOTUSED_ISR, - #endif - - #if (G11_7PL != 0) - CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7 - #else - INT_NOTUSED_ISR, - #endif - - #if (G11_8PL != 0) - CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8 - #else - INT_NOTUSED_ISR, - #endif - - // - // Group 12 PIE Vectors - // - #if (G12_1PL != 0) - XINT3_ISR, // 12.1 - XINT3 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G12_2PL != 0) - XINT4_ISR, // 12.2 - XINT4 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G12_3PL != 0) - XINT5_ISR, // 12.3 - XINT5 Interrupt - #else - INT_NOTUSED_ISR, - #endif - PIE_RESERVED_ISR, // 12.4 - Reserved - PIE_RESERVED_ISR, // 12.5 - Reserved - - #if (G12_6PL != 0) - VCU_ISR, // 12.6 - VCU Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G12_7PL != 0) - FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G12_8PL != 0) - FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt - #else - INT_NOTUSED_ISR, - #endif - PIE_RESERVED_ISR, // 1.9 - Reserved - PIE_RESERVED_ISR, // 1.10 - Reserved - PIE_RESERVED_ISR, // 1.11 - Reserved - PIE_RESERVED_ISR, // 1.12 - Reserved - - #if (G1_13PL != 0) - IPC0_ISR, // 1.13 - IPC Interrupt 0 - #else - INT_NOTUSED_ISR, - #endif - - #if (G1_14PL != 0) - IPC1_ISR, // 1.14 - IPC Interrupt 1 - #else - INT_NOTUSED_ISR, - #endif - - #if (G1_15PL != 0) - IPC2_ISR, // 1.15 - IPC Interrupt 2 - #else - INT_NOTUSED_ISR, - #endif - - #if (G1_16PL != 0) - IPC3_ISR, // 1.16 - IPC Interrupt 3 - #else - INT_NOTUSED_ISR, - #endif - - #if (G2_9PL != 0) - EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G2_10PL != 0) - EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G2_11PL != 0) - EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G2_12PL != 0) - EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt - #else - INT_NOTUSED_ISR, - #endif - PIE_RESERVED_ISR, // 2.13 - Reserved - PIE_RESERVED_ISR, // 2.14 - Reserved - PIE_RESERVED_ISR, // 2.15 - Reserved - PIE_RESERVED_ISR, // 2.16 - Reserved - - #if (G3_9PL != 0) - EPWM9_ISR, // 3.9 - ePWM9 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G3_10PL != 0) - EPWM10_ISR, // 3.10 - ePWM10 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G3_11PL != 0) - EPWM11_ISR, // 3.11 - ePWM11 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G3_12PL != 0) - EPWM12_ISR, // 3.12 - ePWM12 Interrupt - #else - INT_NOTUSED_ISR, - #endif - PIE_RESERVED_ISR, // 3.13 - Reserved - PIE_RESERVED_ISR, // 3.14 - Reserved - PIE_RESERVED_ISR, // 3.15 - Reserved - PIE_RESERVED_ISR, // 3.16 - Reserved - PIE_RESERVED_ISR, // 4.9 - Reserved - PIE_RESERVED_ISR, // 4.10 - Reserved - PIE_RESERVED_ISR, // 4.11 - Reserved - PIE_RESERVED_ISR, // 4.12 - Reserved - PIE_RESERVED_ISR, // 4.13 - Reserved - PIE_RESERVED_ISR, // 4.14 - Reserved - PIE_RESERVED_ISR, // 4.15 - Reserved - PIE_RESERVED_ISR, // 4.16 - Reserved - - #if (G5_9PL != 0) - SD1_ISR, // 5.9 - SD1 Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G5_10PL != 0) - SD2_ISR, // 5.10 - SD2 Interrupt - #else - INT_NOTUSED_ISR, - #endif - PIE_RESERVED_ISR, // 5.11 - Reserved - PIE_RESERVED_ISR, // 5.12 - Reserved - PIE_RESERVED_ISR, // 5.13 - Reserved - PIE_RESERVED_ISR, // 5.14 - Reserved - PIE_RESERVED_ISR, // 5.15 - Reserved - PIE_RESERVED_ISR, // 5.16 - Reserved - - #if (G6_9PL != 0) - SPIC_RX_ISR, // 6.9 - SPIC Receive Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G6_10PL != 0) - SPIC_TX_ISR, // 6.10 - SPIC Transmit Interrupt - #else - INT_NOTUSED_ISR, - #endif - PIE_RESERVED_ISR, // 6.11 - Reserved - PIE_RESERVED_ISR, // 6.12 - Reserved - PIE_RESERVED_ISR, // 6.13 - Reserved - PIE_RESERVED_ISR, // 6.14 - Reserved - PIE_RESERVED_ISR, // 6.15 - Reserved - PIE_RESERVED_ISR, // 6.16 - Reserved - PIE_RESERVED_ISR, // 7.9 - Reserved - PIE_RESERVED_ISR, // 7.10 - Reserved - PIE_RESERVED_ISR, // 7.11 - Reserved - PIE_RESERVED_ISR, // 7.12 - Reserved - PIE_RESERVED_ISR, // 7.13 - Reserved - PIE_RESERVED_ISR, // 7.14 - Reserved - PIE_RESERVED_ISR, // 7.15 - Reserved - PIE_RESERVED_ISR, // 7.16 - Reserved - PIE_RESERVED_ISR, // 8.9 - Reserved - PIE_RESERVED_ISR, // 8.10 - Reserved - PIE_RESERVED_ISR, // 8.11 - Reserved - PIE_RESERVED_ISR, // 8.12 - Reserved - PIE_RESERVED_ISR, // 8.13 - Reserved - PIE_RESERVED_ISR, // 8.14 - Reserved -#ifdef CPU1 - - #if (G8_15PL != 0) - UPPA_ISR, // 8.15 - uPPA Interrupt - #else - INT_NOTUSED_ISR, - #endif - PIE_RESERVED_ISR, // 8.16 - Reserved -#elif defined(CPU2) - PIE_RESERVED_ISR, // 8.15 - Reserved - PIE_RESERVED_ISR, // 8.16 - Reserved -#endif - PIE_RESERVED_ISR, // 9.9 - Reserved - PIE_RESERVED_ISR, // 9.10 - Reserved - PIE_RESERVED_ISR, // 9.11 - Reserved - PIE_RESERVED_ISR, // 9.12 - Reserved - PIE_RESERVED_ISR, // 9.13 - Reserved - PIE_RESERVED_ISR, // 9.14 - Reserved -#ifdef CPU1 - - #if (G9_15PL != 0) - USBA_ISR, // 9.15 - USBA Interrupt - #else - INT_NOTUSED_ISR, - #endif -#elif defined(CPU2) - PIE_RESERVED_ISR, // 9.15 - Reserved -#endif - PIE_RESERVED_ISR, // 9.16 - Reserved - - #if (G10_9PL != 0) - ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G10_10PL != 0) - ADCC2_ISR, // 10.10 - ADCC Interrupt 2 - #else - INT_NOTUSED_ISR, - #endif - - #if (G10_11PL != 0) - ADCC3_ISR, // 10.11 - ADCC Interrupt 3 - #else - INT_NOTUSED_ISR, - #endif - - #if (G10_12PL != 0) - ADCC4_ISR, // 10.12 - ADCC Interrupt 4 - #else - INT_NOTUSED_ISR, - #endif - - #if (G10_13PL != 0) - ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G10_14PL != 0) - ADCD2_ISR, // 10.14 - ADCD Interrupt 2 - #else - INT_NOTUSED_ISR, - #endif - - #if (G10_15PL != 0) - ADCD3_ISR, // 10.15 - ADCD Interrupt 3 - #else - INT_NOTUSED_ISR, - #endif - - #if (G10_16PL != 0) - ADCD4_ISR, // 10.16 - ADCD Interrupt 4 - #else - INT_NOTUSED_ISR, - #endif - PIE_RESERVED_ISR, // 11.9 - Reserved - PIE_RESERVED_ISR, // 11.10 - Reserved - PIE_RESERVED_ISR, // 11.11 - Reserved - PIE_RESERVED_ISR, // 11.12 - Reserved - PIE_RESERVED_ISR, // 11.13 - Reserved - PIE_RESERVED_ISR, // 11.14 - Reserved - PIE_RESERVED_ISR, // 11.15 - Reserved - PIE_RESERVED_ISR, // 11.16 - Reserved - - #if (G12_9PL != 0) - EMIF_ERROR_ISR, // 12.9 - EMIF Error Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G12_10PL != 0) - RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G12_11PL != 0) - FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G12_12PL != 0) - RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G12_13PL != 0) - SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G12_14PL != 0) - AUX_PLL_SLIP_ISR, // 12.14 - Auxiliary PLL Slip Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G12_15PL != 0) - CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt - #else - INT_NOTUSED_ISR, - #endif - - #if (G12_16PL != 0) - CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt - #else - INT_NOTUSED_ISR, - #endif - -}; - -// -// InitPieVectTable - This function initializes the PIE vector table to a known -// state. This function must be executed after boot time. -// -void -InitPieVectTable(void) -{ - int16 i; - Uint32 *Source = (void *) &PieVectTableInit; - Uint32 *Dest = (void *) &PieVectTable; - - EALLOW; - for(i=0; i < 221; i++) - { - *Dest++ = *Source++; - } - EDIS; -} - -// -// End of File -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Sci.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Sci.c deleted file mode 100644 index e21b934a5e..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Sci.c +++ /dev/null @@ -1,48 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Sci.c -// -// TITLE: F2837xD SCI Initialization & Support Functions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#include "F2837xD_device.h" // F2837xD Headerfile Include File -#include "F2837xD_Examples.h" // F2837xD Examples Include File - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Spi.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Spi.c deleted file mode 100644 index 1a82751d7e..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Spi.c +++ /dev/null @@ -1,175 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Spi.c -// -// TITLE: F2837xD SPI Initialization & Support Functions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" - -// -// Calculate BRR: 7-bit baud rate register value -// SPI CLK freq = 500 kHz -// LSPCLK freq = CPU freq / 4 (by default) -// BRR = (LSPCLK freq / SPI CLK freq) - 1 -// -#if CPU_FRQ_200MHZ -#define SPI_BRR ((200E6 / 4) / 500E3) - 1 -#endif - -#if CPU_FRQ_150MHZ -#define SPI_BRR ((150E6 / 4) / 500E3) - 1 -#endif - -#if CPU_FRQ_120MHZ -#define SPI_BRR ((120E6 / 4) / 500E3) - 1 -#endif - -// -// InitSPI - This function initializes the SPI to a known state -// -void InitSpi(void) -{ - // Initialize SPI-A - - // Set reset low before configuration changes - // Clock polarity (0 == rising, 1 == falling) - // 16-bit character - // Enable loop-back - SpiaRegs.SPICCR.bit.SPISWRESET = 0; - SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; - SpiaRegs.SPICCR.bit.SPICHAR = (16-1); - SpiaRegs.SPICCR.bit.SPILBK = 1; - - // Enable master (0 == slave, 1 == master) - // Enable transmission (Talk) - // Clock phase (0 == normal, 1 == delayed) - // SPI interrupts are disabled - SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; - SpiaRegs.SPICTL.bit.TALK = 1; - SpiaRegs.SPICTL.bit.CLK_PHASE = 0; - SpiaRegs.SPICTL.bit.SPIINTENA = 0; - - // Set the baud rate - SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = SPI_BRR; - - // Set FREE bit - // Halting on a breakpoint will not halt the SPI - SpiaRegs.SPIPRI.bit.FREE = 1; - - // Release the SPI from reset - SpiaRegs.SPICCR.bit.SPISWRESET = 1; -} - -// -// InitSpiGpio - This function initializes GPIO pins to function as SPI pins. -// Each GPIO pin can be configured as a GPIO pin or up to 3 -// different peripheral functional pins. By default all pins come -// up as GPIO inputs after reset. -// -// Caution: -// For each SPI peripheral -// Only one GPIO pin should be enabled for SPISOMO operation. -// Only one GPIO pin should be enabled for SPISOMI operation. -// Only one GPIO pin should be enabled for SPICLK operation. -// Only one GPIO pin should be enabled for SPISTE operation. -// Comment out other unwanted lines. -// -void InitSpiGpio() -{ - InitSpiaGpio(); -} - -// -// InitSpiaGpio - Initialize SPIA GPIOs -// -void InitSpiaGpio() -{ - EALLOW; - - // - // Enable internal pull-up for the selected pins - // - // Pull-ups can be enabled or disabled by the user. - // This will enable the pullups for the specified pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA) -// GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (SPISIMOA) - GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA) -// GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (SPISOMIA) - GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA) - GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA) - - // - // Set qualification for selected pins to asynch only - // - // This will select asynch (no qualification) for the selected pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) -// GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; // Asynch input GPIO5 (SPISIMOA) - GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) -// GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; // Asynch input GPIO3 (SPISOMIA) - GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) - GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA) - - // - //Configure SPI-A pins using GPIO regs - // - // This specifies which of the possible GPIO pins will be SPI functional - // pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA -// GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; // Configure GPIO5 as SPISIMOA - GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA -// GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as SPISOMIA - GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA - GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA - - EDIS; -} - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_SysCtrl.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_SysCtrl.c deleted file mode 100644 index 0971cee2d5..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_SysCtrl.c +++ /dev/null @@ -1,1276 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_SysCtrl.c -// -// TITLE: F2837xD Device System Control Initialization & Support Functions. -// -// DESCRIPTION: -// -// Example initialization of system resources. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" -#ifdef __cplusplus -using std::memcpy; -#endif - -#define STATUS_FAIL 0 -#define STATUS_SUCCESS 1 -#define TMR1SYSCLKCTR 0xF0000000 -#define TMR2INPCLKCTR 0x800 - -// -// Functions that will be run from RAM need to be assigned to a different -// section. This section will then be mapped to a load and run address using -// the linker cmd file. -// -// *IMPORTANT* -// -// IF RUNNING FROM FLASH, PLEASE COPY OVER THE SECTION ".TI.ramfunc" FROM -// FLASH TO RAM PRIOR TO CALLING InitSysCtrl(). THIS PREVENTS THE MCU FROM -// THROWING AN EXCEPTION WHEN A CALL TO DELAY_US() IS MADE. -// -#ifndef __cplusplus - #ifdef __TI_COMPILER_VERSION__ - #if __TI_COMPILER_VERSION__ >= 15009000 - #pragma CODE_SECTION(InitFlash, ".TI.ramfunc"); - #pragma CODE_SECTION(FlashOff, ".TI.ramfunc"); - #else - #pragma CODE_SECTION(InitFlash, "ramfuncs"); - #pragma CODE_SECTION(FlashOff, "ramfuncs"); - #endif - #endif -#endif - -// -// InitSysCtrl - Initialization of system resources. -// -void InitSysCtrl(void) -{ - // - // Disable the watchdog - // - DisableDog(); - -#ifdef _FLASH - // - // Copy time critical code and Flash setup code to RAM. This includes the - // following functions: InitFlash() - // - // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart - // symbols are created by the linker. Refer to the device .cmd file. - // - memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); - - // - // Call Flash Initialization to setup flash waitstates. This function must - // reside in RAM. - // - InitFlash(); -#endif - - // - // *IMPORTANT* - // - // The Device_cal function, which copies the ADC & oscillator calibration - // values from TI reserved OTP into the appropriate trim registers, occurs - // automatically in the Boot ROM. If the boot ROM code is bypassed during - // the debug process, the following function MUST be called for the ADC and - // oscillators to function according to specification. The clocks to the - // ADC MUST be enabled before calling this function. - // - // See the device data manual and/or the ADC Reference Manual for more - // information. - // -#ifdef CPU1 - EALLOW; - - // - // Enable pull-ups on unbonded IOs as soon as possible to reduce power - // consumption. - // - GPIO_EnableUnbondedIOPullups(); - - CpuSysRegs.PCLKCR13.bit.ADC_A = 1; - CpuSysRegs.PCLKCR13.bit.ADC_B = 1; - CpuSysRegs.PCLKCR13.bit.ADC_C = 1; - CpuSysRegs.PCLKCR13.bit.ADC_D = 1; - - // - // Check if device is trimmed - // - if(*((Uint16 *)0x5D1B6) == 0x0000){ - // - // Device is not trimmed--apply static calibration values - // - AnalogSubsysRegs.ANAREFTRIMA.all = 31709; - AnalogSubsysRegs.ANAREFTRIMB.all = 31709; - AnalogSubsysRegs.ANAREFTRIMC.all = 31709; - AnalogSubsysRegs.ANAREFTRIMD.all = 31709; - } - - CpuSysRegs.PCLKCR13.bit.ADC_A = 0; - CpuSysRegs.PCLKCR13.bit.ADC_B = 0; - CpuSysRegs.PCLKCR13.bit.ADC_C = 0; - CpuSysRegs.PCLKCR13.bit.ADC_D = 0; - EDIS; - - // - // Initialize the PLL control: SYSPLLMULT and SYSCLKDIVSEL. - // - // Defined options to be passed as arguments to this function are defined - // in F2837xD_Examples.h. - // - // Note: The internal oscillator CANNOT be used as the PLL source if the - // PLLSYSCLK is configured to frequencies above 194 MHz. - // - // PLLSYSCLK = (XTAL_OSC) * (IMULT + FMULT) / (PLLSYSCLKDIV) - // -#ifdef _LAUNCHXL_F28379D - InitSysPll(XTAL_OSC,IMULT_40,FMULT_0,PLLCLK_BY_2); -#else - InitSysPll(XTAL_OSC, IMULT_20, FMULT_0, PLLCLK_BY_2); -#endif // _LAUNCHXL_F28379D - -#endif // CPU1 - - // - // Turn on all peripherals - // - InitPeripheralClocks(); -} - -// -// InitPeripheralClocks - Initializes the clocks for the peripherals. -// -// Note: In order to reduce power consumption, turn off the clocks to any -// peripheral that is not specified for your part-number or is not used in the -// application -// -void InitPeripheralClocks(void) -{ - EALLOW; - - CpuSysRegs.PCLKCR0.bit.CLA1 = 1; - CpuSysRegs.PCLKCR0.bit.DMA = 1; - CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1; - CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 1; - CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 1; - -#ifdef CPU1 - CpuSysRegs.PCLKCR0.bit.HRPWM = 1; -#endif - - CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; - -#ifdef CPU1 - CpuSysRegs.PCLKCR1.bit.EMIF1 = 1; - CpuSysRegs.PCLKCR1.bit.EMIF2 = 1; -#endif - - CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM2 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM3 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM4 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM5 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM6 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM7 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM8 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM9 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM10 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM11 = 1; - CpuSysRegs.PCLKCR2.bit.EPWM12 = 1; - - CpuSysRegs.PCLKCR3.bit.ECAP1 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP2 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP3 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP4 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP5 = 1; - CpuSysRegs.PCLKCR3.bit.ECAP6 = 1; - - CpuSysRegs.PCLKCR4.bit.EQEP1 = 1; - CpuSysRegs.PCLKCR4.bit.EQEP2 = 1; - CpuSysRegs.PCLKCR4.bit.EQEP3 = 1; - - CpuSysRegs.PCLKCR6.bit.SD1 = 1; - CpuSysRegs.PCLKCR6.bit.SD2 = 1; - - CpuSysRegs.PCLKCR7.bit.SCI_A = 1; - CpuSysRegs.PCLKCR7.bit.SCI_B = 1; - CpuSysRegs.PCLKCR7.bit.SCI_C = 1; - CpuSysRegs.PCLKCR7.bit.SCI_D = 1; - - CpuSysRegs.PCLKCR8.bit.SPI_A = 1; - CpuSysRegs.PCLKCR8.bit.SPI_B = 1; - CpuSysRegs.PCLKCR8.bit.SPI_C = 1; - - CpuSysRegs.PCLKCR9.bit.I2C_A = 1; - CpuSysRegs.PCLKCR9.bit.I2C_B = 1; - - CpuSysRegs.PCLKCR10.bit.CAN_A = 1; - CpuSysRegs.PCLKCR10.bit.CAN_B = 1; - - CpuSysRegs.PCLKCR11.bit.McBSP_A = 1; - CpuSysRegs.PCLKCR11.bit.McBSP_B = 1; - -#ifdef CPU1 - CpuSysRegs.PCLKCR11.bit.USB_A = 1; - - CpuSysRegs.PCLKCR12.bit.uPP_A = 1; -#endif - - CpuSysRegs.PCLKCR13.bit.ADC_A = 1; - CpuSysRegs.PCLKCR13.bit.ADC_B = 1; - CpuSysRegs.PCLKCR13.bit.ADC_C = 1; - CpuSysRegs.PCLKCR13.bit.ADC_D = 1; - - CpuSysRegs.PCLKCR14.bit.CMPSS1 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS2 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS3 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS4 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS5 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS6 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS7 = 1; - CpuSysRegs.PCLKCR14.bit.CMPSS8 = 1; - - CpuSysRegs.PCLKCR16.bit.DAC_A = 1; - CpuSysRegs.PCLKCR16.bit.DAC_B = 1; - CpuSysRegs.PCLKCR16.bit.DAC_C = 1; - - EDIS; -} - -// -// DisablePeripheralClocks - Gates-off all peripheral clocks. -// -void DisablePeripheralClocks(void) -{ - EALLOW; - - CpuSysRegs.PCLKCR0.all = 0; - CpuSysRegs.PCLKCR1.all = 0; - CpuSysRegs.PCLKCR2.all = 0; - CpuSysRegs.PCLKCR3.all = 0; - CpuSysRegs.PCLKCR4.all = 0; - CpuSysRegs.PCLKCR6.all = 0; - CpuSysRegs.PCLKCR7.all = 0; - CpuSysRegs.PCLKCR8.all = 0; - CpuSysRegs.PCLKCR9.all = 0; - CpuSysRegs.PCLKCR10.all = 0; - CpuSysRegs.PCLKCR11.all = 0; - CpuSysRegs.PCLKCR12.all = 0; - CpuSysRegs.PCLKCR13.all = 0; - CpuSysRegs.PCLKCR14.all = 0; - CpuSysRegs.PCLKCR16.all = 0; - - EDIS; -} - -// -// InitFlash - This function initializes the Flash Control registers. -// -// *CAUTION* -// This function MUST be executed out of RAM. Executing it out of OTP/Flash -// will yield unpredictable results. -// -#ifdef __cplusplus - #ifdef __TI_COMPILER_VERSION__ - #if __TI_COMPILER_VERSION__ >= 15009000 - #pragma CODE_SECTION(".TI.ramfunc"); - #else - #pragma CODE_SECTION("ramfuncs"); - #endif - #endif -#endif -void InitFlash(void) -{ - EALLOW; - - // - // The default value of VREADST is good enough for the flash to power up - // properly at the INTOSC frequency. Below VREADST configuration covers up - // to the max frequency possible for this device. This is required for - // proper flash wake up at the higher frequencies if users put it to sleep - // for power saving reason. - // - Flash0CtrlRegs.FBAC.bit.VREADST = 0x14; - - // - // At reset bank and pump are in sleep. A Flash access will power up the - // bank and pump automatically. - // - // After a Flash access, bank and pump go to low power mode (configurable - // in FBFALLBACK/FPAC1 registers) if there is no further access to flash. - // - // Power up Flash bank and pump. This also sets the fall back mode of - // flash and pump as active. - // - Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1; - Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3; - - // - // Disable Cache and prefetch mechanism before changing wait states - // - Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0; - Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0; - - // - // Set waitstates according to frequency - // - // *CAUTION* - // Minimum waitstates required for the flash operating at a given CPU rate - // must be characterized by TI. Refer to the datasheet for the latest - // information. - // - #if CPU_FRQ_200MHZ - Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x3; - #endif - - #if CPU_FRQ_150MHZ - Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2; - #endif - - #if CPU_FRQ_120MHZ - Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2; - #endif - - // - // Enable Cache and prefetch mechanism to improve performance of code - // executed from Flash. - // - Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1; - Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1; - - // - // At reset, ECC is enabled. If it is disabled by application software and - // if application again wants to enable ECC. - // - Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA; - - EDIS; - - // - // Force a pipeline flush to ensure that the write to the last register - // configured occurs before returning. - // - __asm(" RPT #7 || NOP"); -} - -// -// FlashOff - This function powers down the flash -// -// *CAUTION* -// This function MUST be executed out of RAM. Executing it out of OTP/Flash -// will yield unpredictable results. Also you must seize the flash pump in -// order to power it down. -// -#ifdef __cplusplus - #ifdef __TI_COMPILER_VERSION__ - #if __TI_COMPILER_VERSION__ >= 15009000 - #pragma CODE_SECTION(".TI.ramfunc"); - #else - #pragma CODE_SECTION("ramfuncs"); - #endif - #endif -#endif -void FlashOff(void) -{ - EALLOW; - - // - // Set VREADST to the proper value for the flash banks to power up properly - // - Flash0CtrlRegs.FBAC.bit.VREADST = 0x14; - - // - // Power down bank - // - Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0; - - // - // Power down pump - // - Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0; - - EDIS; -} - -// -// SeizeFlashPump - Wait until the flash pump is available. Then take control -// of it using the flash pump Semaphore. -// -void SeizeFlashPump(void) -{ - EALLOW; - #ifdef CPU1 - while (FlashPumpSemaphoreRegs.PUMPREQUEST.bit.PUMP_OWNERSHIP != 0x2) - { - FlashPumpSemaphoreRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x2; - } - #elif defined(CPU2) - while (FlashPumpSemaphoreRegs.PUMPREQUEST.bit.PUMP_OWNERSHIP != 0x1) - { - FlashPumpSemaphoreRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x1; - } - #endif - EDIS; -} - -// -// ReleaseFlashPump - Release control of the flash pump using the flash pump -// semaphore. -// -void ReleaseFlashPump(void) -{ - EALLOW; - FlashPumpSemaphoreRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x0; - EDIS; -} - -// -// ServiceDog - This function resets the watchdog timer. -// -// Enable this function for using ServiceDog in the application. -// -void ServiceDog(void) -{ - EALLOW; - WdRegs.WDKEY.bit.WDKEY = 0x0055; - WdRegs.WDKEY.bit.WDKEY = 0x00AA; - EDIS; -} - -// -// DisableDog - This function disables the watchdog timer. -// -void DisableDog(void) -{ - volatile Uint16 temp; - - // - // Grab the clock config first so we don't clobber it - // - EALLOW; - temp = WdRegs.WDCR.all & 0x0007; - WdRegs.WDCR.all = 0x0068 | temp; - EDIS; -} - -#ifdef CPU1 -// -// InitSysPll() -// This function initializes the PLL registers. -// Note: -// - The internal oscillator CANNOT be used as the PLL source if the -// PLLSYSCLK is configured to frequencies above 194 MHz. -// -// - This function uses the Watchdog as a monitor for the PLL. The user -// watchdog settings will be modified and restored upon completion. Function -// allows for a minimum re lock attempt for 5 tries. Re lock attempt is carried -// out if either SLIP condition occurs or SYSCLK to Input Clock ratio is off by 10% -// -// - This function uses the following resources to support PLL initialization: -// o Watchdog -// o CPU Timer 1 -// o CPU Timer 2 -// -void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel) -{ - Uint16 SCSR, WDCR, WDWCR, intStatus, t1TCR, t1TPR, t1TPRH; - Uint16 t2TCR, t2TPR, t2TPRH, t2SRC, t2Prescale; - Uint32 t1PRD, t2PRD, ctr1; - float sysclkToInClkError, mult, div; - bool sysclkInvalidFreq=true; - - if((clock_source == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) && - (imult == ClkCfgRegs.SYSPLLMULT.bit.IMULT) && - (fmult == ClkCfgRegs.SYSPLLMULT.bit.FMULT) && - (divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV)) - { - // - // Everything is set as required, so just return - // - return; - } - - if(clock_source != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) - { - switch (clock_source) - { - case INT_OSC1: - SysIntOsc1Sel(); - break; - - case INT_OSC2: - SysIntOsc2Sel(); - break; - - case XTAL_OSC: - SysXtalOscSel(); - break; - } - } - - EALLOW; - if(imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT || - fmult != ClkCfgRegs.SYSPLLMULT.bit.FMULT) - { - Uint16 i; - - // - // This bit is reset only by POR - // - if(DevCfgRegs.SYSDBGCTL.bit.BIT_0 == 1) - { - // - // The user can optionally insert handler code here. This will only - // be executed if a watchdog reset occurred after a failed system - // PLL initialization. See your device user's guide for more - // information. - // - // If the application has a watchdog reset handler, this bit should - // be checked to determine if the watchdog reset occurred because - // of the PLL. - // - // No action here will continue with retrying the PLL as normal. - // - // Failed PLL initialization is due to any of the following: - // - No PLL clock - // - SLIP condition - // - Wrong Frequency - // - } - - // - // Bypass PLL and set dividers to /1 - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; - asm(" RPT #20 || NOP"); - ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0; - - // - // Lock the PLL five times. This helps ensure a successful start. - // Five is the minimum recommended number. The user can increase this - // number according to allotted system initialization time. - // - for(i = 0; i < 5; i++) - { - // - // Turn off PLL - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; - asm(" RPT #20 || NOP"); - - // - // Write multiplier, which automatically turns on the PLL - // - ClkCfgRegs.SYSPLLMULT.all = ((fmult << 8U) | imult); - - // - // Wait for the SYSPLL lock counter - // - while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1) - { - // - // Uncomment to service the watchdog - // - // ServiceDog(); - } - } - } - - // - // Set divider to produce slower output frequency to limit current increase - // - if(divsel != PLLCLK_BY_126) - { - ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1; - } - else - { - ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; - } - - // - // *CAUTION* - // It is recommended to use the following watchdog code to monitor the PLL - // startup sequence. If your application has already cleared the watchdog - // SCRS[WDOVERRIDE] bit this cannot be done. It is recommended not to clear - // this bit until after the PLL has been initiated. - // - - // - // Backup User Watchdog - // - SCSR = WdRegs.SCSR.all; - WDCR = WdRegs.WDCR.all; - WDWCR = WdRegs.WDWCR.all; - - // - // Disable windowed functionality, reset counter - // - EALLOW; - WdRegs.WDWCR.all = 0x0; - WdRegs.WDKEY.bit.WDKEY = 0x55; - WdRegs.WDKEY.bit.WDKEY = 0xAA; - - // - // Disable global interrupts - // - intStatus = __disable_interrupts(); - - // - // Configure for watchdog reset and to run at max frequency - // - WdRegs.SCSR.all = 0x0; - WdRegs.WDCR.all = 0x28; - - // - // This bit is reset only by power-on-reset (POR) and will not be cleared - // by a WD reset - // - DevCfgRegs.SYSDBGCTL.bit.BIT_0 = 1; - - // - // Enable PLLSYSCLK is fed from system PLL clock - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; - - // - // Delay to ensure system is clocking from PLL prior to clearing status bit - // - asm(" RPT #20 || NOP"); - - // - // Service watchdog - // - ServiceDog(); - - // - // Slip Bit Monitor and SYSCLK Frequency Check using timers - // Re-lock routine for SLIP condition or if SYSCLK and CLKSRC timer counts - // are off by +/- 10%. - // At a minimum, SYSCLK check is performed. Re lock attempt is carried out - // if SLIPS bit is set. This while loop is monitored by watchdog. - // In the event that the PLL does not successfully lock, the loop will be - // aborted by watchdog reset. - // - EALLOW; - while(sysclkInvalidFreq == true) - { - if(ClkCfgRegs.SYSPLLSTS.bit.SLIPS == 1) - { - // - // Bypass PLL - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; - asm(" RPT #20 || NOP"); - - // - // Turn off PLL - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; - asm(" RPT #20 || NOP"); - - // - // Write multipliers, which automatically turns on the PLL - // - ClkCfgRegs.SYSPLLMULT.all = ((fmult << 8U) | imult); - - // - // Wait for the SYSPLL lock counter to expire - // - while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1); - - // - // Enable PLLSYSCLK is fed from system PLL clock - // - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; - - // - // Delay to ensure system is clocking from PLL - // - asm(" RPT #20 || NOP"); - } - - // - // Backup timer1 and timer2 settings - // - t1TCR = CpuTimer1Regs.TCR.all; - t1PRD = CpuTimer1Regs.PRD.all; - t1TPR = CpuTimer1Regs.TPR.all; - t1TPRH = CpuTimer1Regs.TPRH.all; - t2SRC = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL; - t2Prescale = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE; - t2TCR = CpuTimer2Regs.TCR.all; - t2PRD = CpuTimer2Regs.PRD.all; - t2TPR = CpuTimer2Regs.TPR.all; - t2TPRH = CpuTimer2Regs.TPRH.all; - - // - // Set up timers 1 and 2 - // Configure timer1 to count SYSCLK cycles - // - CpuTimer1Regs.TCR.bit.TSS = 1; // stop timer1 - CpuTimer1Regs.PRD.all = TMR1SYSCLKCTR; // seed timer1 counter - CpuTimer1Regs.TPR.bit.TDDR = 0x0; // sysclock divider - CpuTimer1Regs.TCR.bit.TRB = 1; // reload timer with value in PRD - CpuTimer1Regs.TCR.bit.TIF = 1; // clear interrupt flag - CpuTimer1Regs.TCR.bit.TIE = 1; // enable interrupt - - // - // Configure timer2 to count Input clock cycles - // - switch(clock_source) - { - case INT_OSC1: - // Clk Src = INT_OSC1 - CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x1; - break; - case INT_OSC2: - // Clk Src = INT_OSC2 - CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x2; - break; - case XTAL_OSC: - // Clk Src = XTAL - CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x3; - break; - - } - CpuTimer2Regs.TCR.bit.TIF = 1; // clear interrupt flag - CpuTimer2Regs.TCR.bit.TIE = 1; // enable interrupt - CpuTimer2Regs.TCR.bit.TSS = 1; // stop timer2 - CpuTimer2Regs.PRD.all = TMR2INPCLKCTR; // seed timer2 counter - CpuTimer2Regs.TPR.bit.TDDR = 0x0; // sysclock divider - CpuTimer2Regs.TCR.bit.TRB = 1; // reload timer with value in PRD - - // - // Stop/Start timer counters - // - CpuTimer1Regs.TCR.bit.TSS = 1; // stop timer1 - CpuTimer2Regs.TCR.bit.TSS = 1; // stop timer2 - CpuTimer1Regs.TCR.bit.TRB = 1; // reload timer1 with value in PRD - CpuTimer2Regs.TCR.bit.TRB = 1; // reload timer2 with value in PRD - CpuTimer2Regs.TCR.bit.TIF = 1; // clear timer2 interrupt flag - CpuTimer2Regs.TCR.bit.TSS = 0; // start timer2 - CpuTimer1Regs.TCR.bit.TSS = 0; // start timer1 - - // - // Stop timers if either timer1 or timer2 counters overflow - // - while((CpuTimer2Regs.TCR.bit.TIF == 0) && (CpuTimer1Regs.TCR.bit.TIF == 0)); - - CpuTimer1Regs.TCR.bit.TSS = 1; // stop timer1 - CpuTimer2Regs.TCR.bit.TSS = 1; // stop timer2 - - // - // Calculate elapsed counts on timer1 - // - ctr1 = TMR1SYSCLKCTR - CpuTimer1Regs.TIM.all; - - // - // Restore timer settings - // - CpuTimer1Regs.TCR.all = t1TCR; - CpuTimer1Regs.PRD.all = t1PRD; - CpuTimer1Regs.TPR.all = t1TPR; - CpuTimer1Regs.TPRH.all = t1TPRH; - CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = t2SRC; - CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE = t2Prescale; - CpuTimer2Regs.TCR.all = t2TCR; - CpuTimer2Regs.PRD.all = t2PRD; - CpuTimer2Regs.TPR.all = t2TPR; - CpuTimer2Regs.TPRH.all = t2TPRH; - - // - // Calculate Clock Error: - // Error = (mult/div) - (timer1 count/timer2 count) - // - mult = (float)(imult) + (float)(fmult)/4; - div = (float)((!ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV) ? 1 : (ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV << 1)); - - sysclkToInClkError = (mult/div) - ((float)ctr1/(float)TMR2INPCLKCTR); - - // - // sysclkInvalidFreq will be set to true if sysclkToInClkError is off by 10% - // - sysclkInvalidFreq = ((sysclkToInClkError > 0.10) || (sysclkToInClkError < -0.10)); - } - - // - // Clear bit - // - DevCfgRegs.SYSDBGCTL.bit.BIT_0 = 0; - - // - // Restore user watchdog, first resetting counter - // - WdRegs.WDKEY.bit.WDKEY = 0x55; - WdRegs.WDKEY.bit.WDKEY = 0xAA; - - WDCR |= 0x28; // Setup WD key--KEY bits always read 0 - WdRegs.WDCR.all = WDCR; - WdRegs.WDWCR.all = WDWCR; - WdRegs.SCSR.all = SCSR & 0xFFFE; // Mask write to bit 0 (W1toClr) - - // - // Restore state of ST1[INTM]. This was set by the __disable_interrupts() - // intrinsic previously. - // - if(!(intStatus & 0x1)) - { - EINT; - } - - // - // Restore state of ST1[DBGM]. This was set by the __disable_interrupts() - // intrinsic previously. - // - if(!(intStatus & 0x2)) - { - asm(" CLRC DBGM"); - } - - // - // 200 PLLSYSCLK delay to allow voltage regulator to stabilize prior - // to increasing entire system clock frequency. - // - asm(" RPT #200 || NOP"); - - // - // Set the divider to user value - // - ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; - - EDIS; -} -#endif // CPU1 - -// -// InitAuxPll - This function initializes the AUXPLL registers. -// -// Note: For this function to properly detect PLL startup, -// SYSCLK >= 2*AUXPLLCLK after the AUXPLL is selected as the clocking source. -// -// This function will use CPU Timer 2 to monitor a successful lock of the -// AUXPLL. -// -void InitAuxPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel) -{ - Uint16 i; - Uint16 counter = 0; - Uint16 started = 0; - Uint16 t2TCR, t2TPR, t2TPRH, t2SRC, t2Prescale, attempts; - Uint32 t2PRD; - - if((clock_source == ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL) && - (imult == ClkCfgRegs.AUXPLLMULT.bit.IMULT) && - (fmult == ClkCfgRegs.AUXPLLMULT.bit.FMULT) && - (divsel == ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV)) - { - // - // Everything is set as required, so just return - // - return; - } - - switch (clock_source) - { - case INT_OSC2: - AuxIntOsc2Sel(); - break; - - case XTAL_OSC: - AuxXtalOscSel(); - break; - - case AUXCLKIN: - AuxAuxClkSel(); - break; - } - - // - // Backup Timer 2 settings - // - t2SRC = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL; - t2Prescale = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE; - t2TCR = CpuTimer2Regs.TCR.all; - t2PRD = CpuTimer2Regs.PRD.all; - t2TPR = CpuTimer2Regs.TPR.all; - t2TPRH = CpuTimer2Regs.TPRH.all; - - // - // Configure Timer 2 for AUXPLL as source in known configuration - // - EALLOW; - CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x6; - CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE = 0x0; // Divide by 1 - - CpuTimer2Regs.TCR.bit.TSS = 1; // Stop timer - CpuTimer2Regs.PRD.all = 10; // Small PRD value to detect overflow - CpuTimer2Regs.TPR.all = 0; - CpuTimer2Regs.TPRH.all = 0; - CpuTimer2Regs.TCR.bit.TIE = 0; // Disable timer interrupts - - // - // Set AUX Divide by 8 to ensure that AUXPLLCLK <= SYSCLK/2 while using - // Timer 2 - // - ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = 0x3; - EDIS; - - while((counter < 5) && (started == 0)) - { - EALLOW; - ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 0; // Turn off AUXPLL - asm(" RPT #20 || NOP"); // Small delay for power down - - // - // Set integer and fractional multiplier, which automatically turns on - // the PLL - // - ClkCfgRegs.AUXPLLMULT.all = ((fmult << 8U) | imult); - - // - // Enable AUXPLL - // - ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 1; - EDIS; - - // - // Wait for the AUXPLL lock counter - // - while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1) - { - // - // Uncomment to service the watchdog - // - // ServiceDog(); - } - - // - // Enable AUXPLLCLK to be fed from AUX PLL - // - EALLOW; - ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1; - asm(" RPT #20 || NOP"); - - // - // CPU Timer 2 will now be setup to be clocked from AUXPLLCLK. This is - // used to test that the PLL has successfully started. - // - CpuTimer2Regs.TCR.bit.TRB = 1; // Reload period value - CpuTimer2Regs.TCR.bit.TSS = 0; // Start Timer - - // - // Check to see timer is counting properly - // - for(i = 0; i < 1000; i++) - { - // - // Check overflow flag - // - if(CpuTimer2Regs.TCR.bit.TIF) - { - // - // Clear overflow flag - // - CpuTimer2Regs.TCR.bit.TIF = 1; - - // - // Set flag to indicate PLL started and break out of for-loop - // - started = 1; - break; - } - } - - // - // Stop timer - // - CpuTimer2Regs.TCR.bit.TSS = 1; - counter++; - EDIS; - } - - if(started == 0) - { - // - // AUX PLL may not have started. Reset multiplier to 0 (bypass PLL). - // - EALLOW; - ClkCfgRegs.AUXPLLMULT.all = 0; - EDIS; - - // - // The user should put some handler code here based on how this - // condition should be handled in their application. - // - asm(" ESTOP0"); - } - - // - // Slip Bit Monitor - // Re-lock routine for SLIP condition - // - attempts = 0; - while(ClkCfgRegs.AUXPLLSTS.bit.SLIPS && (attempts < 10)) - { - EALLOW; - // - // Bypass AUXPLL - // - ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 0; - asm(" RPT #20 || NOP"); - - // - // Turn off AUXPLL - // - ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 0; - asm(" RPT #20 || NOP"); - - // - // Set integer and fractional multiplier, which automatically turns - // on the PLL - // - ClkCfgRegs.AUXPLLMULT.all = ((fmult << 8U) | imult); - - // - // Wait for the AUXPLL lock counter - // - while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1); - - // - // Enable AUXPLLCLK to be fed from AUXPLL - // - ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1; - asm(" RPT #20 || NOP"); - - attempts++; - EDIS; - } - - // - // Set divider to desired value - // - EALLOW; - ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = divsel; - - // - // Restore Timer 2 configuration - // - CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = t2SRC; - CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE = t2Prescale; - CpuTimer2Regs.TCR.all = t2TCR; - CpuTimer2Regs.PRD.all = t2PRD; - CpuTimer2Regs.TPR.all = t2TPR; - CpuTimer2Regs.TPRH.all = t2TPRH; - - // - // Reload period value - // - CpuTimer2Regs.TCR.bit.TRB = 1; - EDIS; -} - -// -// CsmUnlock - This function unlocks the CSM. User must replace 0xFFFF's with -// current password for the DSP. Returns 1 if unlock is successful. -// -Uint16 CsmUnlock(void) -{ - volatile Uint16 temp; - - // - // Load the key registers with the current password. The 0xFFFF's are dummy - // passwords. User should replace them with the correct password for the - // DSP. - // - EALLOW; - DcsmZ1Regs.Z1_CSMKEY0 = 0xFFFFFFFF; - DcsmZ1Regs.Z1_CSMKEY1 = 0xFFFFFFFF; - DcsmZ1Regs.Z1_CSMKEY2 = 0xFFFFFFFF; - DcsmZ1Regs.Z1_CSMKEY3 = 0xFFFFFFFF; - - DcsmZ2Regs.Z2_CSMKEY0 = 0xFFFFFFFF; - DcsmZ2Regs.Z2_CSMKEY1 = 0xFFFFFFFF; - DcsmZ2Regs.Z2_CSMKEY2 = 0xFFFFFFFF; - DcsmZ2Regs.Z2_CSMKEY3 = 0xFFFFFFFF; - EDIS; - - return(0); -} - -// -// SysIntOsc1Sel - This function switches to Internal Oscillator 1. -// -void SysIntOsc1Sel(void) -{ - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2; // Clk Src = INTOSC1 - ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC - EDIS; -} - -// -// SysIntOsc2Sel - This function switches to Internal oscillator 2. -// -void SysIntOsc2Sel(void) -{ - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2 - ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC - EDIS; -} - -// -// SysXtalOscSel - This function switches to External CRYSTAL oscillator. -// -void SysXtalOscSel(void) -{ - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC - ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; // Clk Src = XTAL - EDIS; -} - -// -// AuxIntOsc2Sel - This function switches to Internal oscillator 2. -// -void AuxIntOsc2Sel(void) -{ - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 - ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 0; // Clk Src = INTOSC2 - EDIS; -} - -// -// AuxXtalOscSel - This function switches to External CRYSTAL oscillator. -// -void AuxXtalOscSel(void) -{ - EALLOW; - ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC - ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 1; // Clk Src = XTAL - EDIS; -} - -// -// AuxAUXCLKOscSel - This function switches to AUXCLKIN (from a GPIO). -// -void AuxAuxClkSel(void) -{ - EALLOW; - ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 2; // Clk Src = XTAL - EDIS; -} - -// -// IDLE - Enter IDLE mode (single CPU). -// -void IDLE(void) -{ - EALLOW; - CpuSysRegs.LPMCR.bit.LPM = LPM_IDLE; - EDIS; - asm(" IDLE"); -} - -// -// STANDBY - Enter STANDBY mode (single CPU). -// -void STANDBY(void) -{ - EALLOW; - CpuSysRegs.LPMCR.bit.LPM = LPM_STANDBY; - EDIS; - asm(" IDLE"); -} - -// -// HALT - Enter HALT mode (dual CPU). Puts CPU2 in IDLE mode first. -// -void HALT(void) -{ -#if defined(CPU2) - IDLE(); -#elif defined(CPU1) - EALLOW; - CpuSysRegs.LPMCR.bit.LPM = LPM_HALT; - EDIS; - - while(DevCfgRegs.LPMSTAT.bit.CPU2LPMSTAT != 0x1); - - EALLOW; - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; - ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; - EDIS; - asm(" IDLE"); -#endif -} - -// -// HIB - Enter HIB mode (dual CPU). Puts CPU2 in STANDBY first. Alternately, -// CPU2 may be in reset. -void HIB(void) -{ -#if defined(CPU2) - STANDBY(); -#elif defined(CPU1) - EALLOW; - CpuSysRegs.LPMCR.bit.LPM = LPM_HIB; - EDIS; - - while((DevCfgRegs.LPMSTAT.bit.CPU2LPMSTAT == 0x0) && - (DevCfgRegs.RSTSTAT.bit.CPU2RES == 1)); - - DisablePeripheralClocks(); - EALLOW; - ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; - ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; - EDIS; - asm(" IDLE"); -#endif -} - diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_TempSensorConv.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_TempSensorConv.c deleted file mode 100644 index ffc70fec07..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_TempSensorConv.c +++ /dev/null @@ -1,153 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_TempSensorConv.c -// -// TITLE: F2837xD Temperature Sensor Conversion Functions -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" - -// -// Defines -// -#define FP_SCALE 32768 //Scale factor for Q15 fixed point numbers (2^15) -#define FP_ROUND FP_SCALE/2 //Added to Q15 numbers before converting to - //integer to round the number. -#define KELVIN 273 // Amount to add to Q15 fixed point numbers - // to shift from Celsius to Kelvin - // (Converting guarantees number is - // positive, which makes rounding more - // efficient) -#define KELVIN_OFF FP_SCALE*KELVIN -#define getTempSlope() (*(int (*)(void))0x7036E)() //Slope of temperature sensor - //(deg. C / ADC code). - //Stored in fixed point Q15 - //format. -#define getTempOffset() (*(int (*)(void))0x70372)() //ADC code corresponding to - //temperature sensor output - //at 0 deg. C - -// -// Globals -// -float32 tempSensor_tempSlope; -float32 tempSensor_tempOffset; -float32 tempSensor_scaleFactor; - -// -// InitTempSensor - Initialize the temperature sensor by powering up the -// sensor, loading the calibration values from OTP to RAM, -// and recording the intended VREFHI voltage. -// Note: This function doesn't support VREFLO != 0.0V, -// but this could be implemented if desired. -// -void InitTempSensor(float32 vrefhi_voltage) -{ - EALLOW; - - // - //power up the the temperature sensor - // - AnalogSubsysRegs.TSNSCTL.bit.ENABLE = 1; - - // - //delay to allow the sensor to power up - // - DELAY_US(1000); - - EDIS; - - // - //need to remember VREFHI voltage so that sensor readings can be scaled - //to match 2.5V values used for calibration data. - // - tempSensor_scaleFactor = vrefhi_voltage; - - // - //check the device revision - // - if(DevCfgRegs.REVID >= 3) - { - // - //for production devices (Rev. C), pull the slope and offset from OTP - // - tempSensor_tempSlope = (int32)getTempSlope(); - tempSensor_tempOffset = getTempOffset(); - } - else - { - // - //for pre-production devices, use these static values for slope - //and offset - // - tempSensor_tempSlope = 5196; - tempSensor_tempOffset = 1788; - } -} - -// -// GetTemperatureC - This function uses the reference data stored in OTP to -// convert the raw temperature sensor reading into degrees C -// -int16 GetTemperatureC(int16 sensorSample) -{ - sensorSample = (int16)((tempSensor_scaleFactor/2.5)*(sensorSample)); - - return (((sensorSample - tempSensor_tempOffset)*tempSensor_tempSlope + - FP_ROUND + KELVIN_OFF)/FP_SCALE - KELVIN); -} - -// -// GetTemperatureK - This function uses the reference data stored in OTP to -// convert the raw temperature sensor reading into degrees K -// -int16 GetTemperatureK(int16 sensorSample) -{ - sensorSample = (int16)((2.5/tempSensor_scaleFactor)*(sensorSample)); - - return (((sensorSample - tempSensor_tempOffset)*tempSensor_tempSlope + - FP_ROUND + KELVIN_OFF)/FP_SCALE); -} - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Upp.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Upp.c deleted file mode 100644 index f0432c9c8d..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_Upp.c +++ /dev/null @@ -1,153 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_Upp.c -// -// TITLE: F2837xD Upp Initialization & Support Functions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" - -// -// InitUpp1Gpio - Initialize UPP1 GPIOs -// -void InitUpp1Gpio(void) -{ - EALLOW; - - // - // Disable internal pull-up for the selected output pins - // for reduced power consumption - // Pull-ups can be enabled or disabled by the user. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (uPP_WAIT) - GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (uPP_START) - GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (uPP_ENA) - GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (uPP_D7) - GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; // Disable pull-up on GPIO14 (uPP_D6) - GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1; // Disable pull-up on GPIO15 (uPP_D5) - GpioCtrlRegs.GPAPUD.bit.GPIO16 = 1; // Disable pull-up on GPIO16 (uPP_D4) - GpioCtrlRegs.GPAPUD.bit.GPIO17 = 1; // Disable pull-up on GPIO17 (uPP_D3) - GpioCtrlRegs.GPAPUD.bit.GPIO18 = 1; // Disable pull-up on GPIO18 (uPP_D2) - GpioCtrlRegs.GPAPUD.bit.GPIO19 = 1; // Disable pull-up on GPIO19 (uPP_D1) - GpioCtrlRegs.GPAPUD.bit.GPIO20 = 1; // Disable pull-up on GPIO20 (uPP_D0) - GpioCtrlRegs.GPAPUD.bit.GPIO21 = 1; // Disable pull-up on GPIO21 (uPP_CLK) - - // - // Disable QUAL for selected pins (ASYNC Input) - // - GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Disable pull-up on GPIO10 (uPP_WAIT) - GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Disable pull-up on GPIO11 (uPP_START) - GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // Disable pull-up on GPIO12 (uPP_ENA) - GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Disable pull-up on GPIO13 (uPP_D7) - GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Disable pull-up on GPIO14 (uPP_D6) - GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Disable pull-up on GPIO15 (uPP_D5) - GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Disable pull-up on GPIO16 (uPP_D4) - GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Disable pull-up on GPIO17 (uPP_D3) - GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Disable pull-up on GPIO18 (uPP_D2) - GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Disable pull-up on GPIO19 (uPP_D1) - GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 3; // Disable pull-up on GPIO20 (uPP_D0) - GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Disable pull-up on GPIO21 (uPP_CLK) - - // - // Configure uPP-1 pins using GPIO regs - // This specifies which of the possible GPIO pins will be EPWM1 functional - // pins. - // Comment out other unwanted lines. - // - GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 3; // Configure GPIO10 as uPP_WAIT - GpioCtrlRegs.GPAGMUX1.bit.GPIO11 = 3; // Configure GPIO11 as uPP_START - GpioCtrlRegs.GPAGMUX1.bit.GPIO12 = 3; // Configure GPIO12 as uPP_ENA - GpioCtrlRegs.GPAGMUX1.bit.GPIO13 = 3; // Configure GPIO13 as uPP_D7 - GpioCtrlRegs.GPAGMUX1.bit.GPIO14 = 3; // Configure GPIO14 as uPP_D6 - GpioCtrlRegs.GPAGMUX1.bit.GPIO15 = 3; // Configure GPIO15 as uPP_D5 - GpioCtrlRegs.GPAGMUX2.bit.GPIO16 = 3; // Configure GPIO16 as uPP_D4 - GpioCtrlRegs.GPAGMUX2.bit.GPIO17 = 3; // Configure GPIO17 as uPP_D3 - GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 3; // Configure GPIO18 as uPP_D2 - GpioCtrlRegs.GPAGMUX2.bit.GPIO19 = 3; // Configure GPIO19 as uPP_D1 - GpioCtrlRegs.GPAGMUX2.bit.GPIO20 = 3; // Configure GPIO20 as uPP_D0 - GpioCtrlRegs.GPAGMUX2.bit.GPIO21 = 3; // Configure GPIO21 as uPP_CLK - - GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 3; // Configure GPIO10 as uPP_WAIT - GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 3; // Configure GPIO11 as uPP_START - GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3; // Configure GPIO12 as uPP_ENA - GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // Configure GPIO13 as uPP_D7 - GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // Configure GPIO14 as uPP_D6 - GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // Configure GPIO15 as uPP_D5 - GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as uPP_D4 - GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3; // Configure GPIO17 as uPP_D3 - GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 as uPP_D2 - GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 as uPP_D1 - GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 as uPP_D0 - GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 as uPP_CLK - - EDIS; -} - -// -// SoftResetUpp - Trigger an internal uPP reset -// -void SoftResetUpp(void) -{ - UppRegs.PERCTL.bit.SOFTRST = 1; // Issue uPP Internal Reset. - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - asm(" NOP"); - UppRegs.PERCTL.bit.SOFTRST = 0; // Release uPP Internal Reset. -} - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_can.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_can.c deleted file mode 100644 index 3b3cb24bea..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_can.c +++ /dev/null @@ -1,131 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_can.c -// -// TITLE: F2837xD CAN Support Functions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" - -// -// InitCAN - Initializes the CAN-A controller after reset. -// -void InitCAN(void) -{ - int16_t iMsg; - - // - // Place CAN controller in init state, regardless of previous state. This - // will put controller in idle, and allow the message object RAM to be - // programmed. - // - CanaRegs.CAN_CTL.bit.Init = 1; - CanaRegs.CAN_CTL.bit.SWR = 1; - - // - // Wait for busy bit to clear - // - while(CanaRegs.CAN_IF1CMD.bit.Busy) - { - } - - // - // Clear the message value bit in the arbitration register. This indicates - // the message is not valid and is a "safe" condition to leave the message - // object. The same arb reg is used to program all the message objects. - // - CanaRegs.CAN_IF1CMD.bit.DIR = 1; - CanaRegs.CAN_IF1CMD.bit.Arb = 1; - CanaRegs.CAN_IF1CMD.bit.Control = 1; - - CanaRegs.CAN_IF1ARB.all = 0; - - CanaRegs.CAN_IF1MCTL.all = 0; - - CanaRegs.CAN_IF2CMD.bit.DIR = 1; - CanaRegs.CAN_IF2CMD.bit.Arb = 1; - CanaRegs.CAN_IF2CMD.bit.Control = 1; - - CanaRegs.CAN_IF2ARB.all = 0; - - CanaRegs.CAN_IF2MCTL.all = 0; - - // - // Loop through to program all 32 message objects - // - for(iMsg = 1; iMsg <= 32; iMsg+=2) - { - // - // Wait for busy bit to clear - // - while(CanaRegs.CAN_IF1CMD.bit.Busy) - { - } - - // - // Initiate programming the message object - // - CanaRegs.CAN_IF1CMD.bit.MSG_NUM = iMsg; - - // - // Wait for busy bit to clear - // - while(CanaRegs.CAN_IF2CMD.bit.Busy) - { - } - - // - // Initiate programming the message object - // - CanaRegs.CAN_IF2CMD.bit.MSG_NUM = iMsg + 1; - } - - // - // Acknowledge any pending status interrupts. - // - volatile uint32_t discardRead = CanaRegs.CAN_ES.all; - -} - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_sci_io.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_sci_io.c deleted file mode 100644 index 28c676c18d..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_sci_io.c +++ /dev/null @@ -1,185 +0,0 @@ -//############################################################################# -// -// File: F2837xD_sci_io.c -// -// Description: Contains the various functions related to the serial -// communications interface (SCI) object -// -//############################################################################# -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -// -// Included Files -// -#include -#include -#include "F28x_Project.h" -#include "F2837xD_sci_io.h" - -// -// Globals -// -uint16_t deviceOpen = 0; - -// -// SCI_open - Initialize and setup SCI -// -int SCI_open(const char * path, unsigned flags, int llv_fd) -{ - if(deviceOpen) - { - return (-1); - } - else - { - EALLOW; - CpuSysRegs.PCLKCR7.bit.SCI_A = 1; - SciaRegs.SCIFFTX.all=0xE040; - SciaRegs.SCIFFRX.all=0x2044; - SciaRegs.SCIFFCT.all=0x0; - SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback - // No parity,8 char bits, - // async mode, idle-line protocol - SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK, - // Disable RX ERR, SLEEP, TXWAKE - SciaRegs.SCICTL2.all =0x0003; - SciaRegs.SCICTL2.bit.TXINTENA =1; - SciaRegs.SCICTL2.bit.RXBKINTENA =1; - - SciaRegs.SCIHBAUD.bit.BAUD =0x0000; // 9600 baud @LSPCLK = 10MHz - //(40 MHz SYSCLK). - SciaRegs.SCILBAUD.bit.BAUD =0x0081; - - SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset - EDIS; - - deviceOpen = 1; - return (1); - } -} - -// -// SCI_close - Set SCI to closed -// -int SCI_close(int dev_fd) -{ - if((dev_fd != 1) || (!deviceOpen)) - { - return (-1); - } - else - { - deviceOpen = 0; - return (0); - } -} - -// -// SCI_read - Read from the SCI RX buffer -// -int SCI_read(int dev_fd, char * buf, unsigned count) -{ - uint16_t readCount = 0; - uint16_t * bufPtr = (uint16_t *) buf; - - if(count == 0) - { - return (0); - } - - while((readCount < count) && SciaRegs.SCIRXST.bit.RXRDY) - { - *bufPtr = SciaRegs.SCIRXBUF.bit.SAR; - readCount++; - bufPtr++; - } - - return (readCount); -} - -// -// SCI_write - Write to the SCI TX buffer -// -int SCI_write(int dev_fd, char * buf, unsigned count) -{ - uint16_t writeCount = 0; - uint16_t * bufPtr = (uint16_t *) buf; - - if(count == 0) - { - return (0); - } - - while(writeCount < count) - { - while(SciaRegs.SCICTL2.bit.TXRDY != 1) - { - } - SciaRegs.SCITXBUF.bit.TXDT = *bufPtr; - writeCount++; - bufPtr++; - } - - return (writeCount); -} - -// -// SCI_lseek - Do nothing -// -off_t SCI_lseek(int dev_fd, off_t offset, int origin) -{ - return (0); -} - -// -// SCI_unlink - Do nothing -// -int SCI_unlink(const char * path) -{ - return (0); -} - -// -// SCI_rename - Do nothing -// -int SCI_rename(const char * old_name, const char * new_name) -{ - return (0); -} - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_sdfm_drivers.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_sdfm_drivers.c deleted file mode 100644 index 4bbfdf5890..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_sdfm_drivers.c +++ /dev/null @@ -1,554 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_sdfm_drivers.c -// -// TITLE: SDFM Driver functions -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F28x_Project.h" -#include "F2837xD_struct.h" -#include "F2837xD_sdfm_drivers.h" - -// -// Sdfm_configureInputCtrl - This function configures SDFM Input control unit. -// sdfmNumber - This parameter should be used to -// select SDFM1 (or) SDFM2 -// filterNumber - This parameter is used to select -// which filter (FILTER1,FILTER2, -// FILTER3,FILTER4) needs to be -// configured. -// mode - This parameter is used to select -// one of the modes mentioned above -// -// Input control unit can be configured in four different modes: -// MODE_0 : Modulator clock rate = Modulator data rate -// MODE_1 : Modulator clock rate = (Modulator data rate / 2) -// MODE_2 : Manchester encoded data (Modulator clock is encoded into data) -// MODE_3 : Modulator clock rate = (2 x Modulator data rate) -// -void Sdfm_configureInputCtrl(Uint16 sdfmNumber, Uint16 filterNumber, - Uint16 mode) -{ - EALLOW; - - switch (filterNumber) - { - case FILTER1: - (*SDFM[sdfmNumber]).SDCTLPARM1.bit.MOD = mode; - break; - - case FILTER2: - (*SDFM[sdfmNumber]).SDCTLPARM2.bit.MOD = mode; - break; - - case FILTER3: - (*SDFM[sdfmNumber]).SDCTLPARM3.bit.MOD = mode; - break; - - case FILTER4: - (*SDFM[sdfmNumber]).SDCTLPARM4.bit.MOD = mode; - break; - } - - EDIS; -} - -// -// Sdfm_configureComparator - This function configures SDFM Comparator unit. -// Comparator unit can be configured to monitor -// input conditions with a fast settling time. -// This module can be programmed to detect over and -// under value conditions. -// -// sdfmNumber - This parameter should be used to -// select SDFM1 (or) SDFM2 -// filterNumber - This parameter is used to select -// which filter (FILTER1,FILTER2, -// FILTER3,FILTER3) -// filterType - This parameter is used to select -// one of the filter type mentioned -// above (SINC1,SINC2,SINC3,SINCFAST) -// OSR - This parameter is used to -// configure oversampling ratio for -// comparator -// HLT - This parameter is used to -// configure to detect over value -// condition -// LLT - This parameter is used to -// configure to detect under value -// condition -// -void Sdfm_configureComparator(Uint16 sdfmNumber, Uint16 filterNumber, - Uint16 filterType, Uint16 OSR, Uint16 HLT, - Uint16 LLT) -{ - EALLOW; - - switch (filterNumber) - { - case FILTER1: //Filter 1 - - // - //Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 - // - (*SDFM[sdfmNumber]).SDCPARM1.bit.CS1_CS0 = filterType; - - // - //Configure OSR value - // - if(OSR<=COMPARATOR_MAX_OSR) - { - (*SDFM[sdfmNumber]).SDCPARM1.bit.COSR = OSR; - } - else - { - (*SDFM[sdfmNumber]).SDCPARM1.bit.COSR = COMPARATOR_MAX_OSR; - } - - (*SDFM[sdfmNumber]).SDCMPH1.bit.HLT = HLT; - (*SDFM[sdfmNumber]).SDCMPL1.bit.LLT = LLT; - break; - - case FILTER2: //Filter 2 - // - //Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 - // - (*SDFM[sdfmNumber]).SDCPARM2.bit.CS1_CS0 = filterType; - - // - //Configure OSR value - // - if(OSR<=COMPARATOR_MAX_OSR) - { - (*SDFM[sdfmNumber]).SDCPARM2.bit.COSR = OSR; - } - else - { - (*SDFM[sdfmNumber]).SDCPARM2.bit.COSR = COMPARATOR_MAX_OSR; - } - - (*SDFM[sdfmNumber]).SDCMPH2.bit.HLT = HLT; - (*SDFM[sdfmNumber]).SDCMPL2.bit.LLT = LLT; - break; - - case FILTER3: //Filter 3 - // - //Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 - // - (*SDFM[sdfmNumber]).SDCPARM3.bit.CS1_CS0 = filterType; - - // - //Configure OSR value - // - if(OSR<=COMPARATOR_MAX_OSR) - { - (*SDFM[sdfmNumber]).SDCPARM3.bit.COSR = OSR; - } - else - { - (*SDFM[sdfmNumber]).SDCPARM3.bit.COSR = COMPARATOR_MAX_OSR; - } - - (*SDFM[sdfmNumber]).SDCMPH3.bit.HLT = HLT; - (*SDFM[sdfmNumber]).SDCMPL3.bit.LLT = LLT; - break; - - case FILTER4: //Filter 4 - // - //Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 - // - (*SDFM[sdfmNumber]).SDCPARM4.bit.CS1_CS0 = filterType; - - // - //Configure Comparator OSR value - // - if(OSR<=COMPARATOR_MAX_OSR) - { - (*SDFM[sdfmNumber]).SDCPARM4.bit.COSR = OSR; - } - else - { - (*SDFM[sdfmNumber]).SDCPARM4.bit.COSR = COMPARATOR_MAX_OSR; - } - - (*SDFM[sdfmNumber]).SDCMPH4.bit.HLT = HLT; - (*SDFM[sdfmNumber]).SDCMPL4.bit.LLT = LLT; - break; - } - - EDIS; -} - - -// -// SDFM_configureData_filter - This function configures SDFM Data filter unit -// -// SDFM Data filter unit can be configured in any -// of four different Sinc filter types: -// sdfmNumber - This parameter should be used to -// select SDFM1 (or) SDFM2 -// filterNumber - This parameter is used to select -// which filter(FILTER1,FILTER2, -// FILTER3,FILTER3) needs to be -// configured -// Filter_switch - This parameter is used to -// enable/disable a filter -// filterType - This parameter is used to select -// one of the filter type mentioned -// above (SINC1 / SINC2 / SINC3 / -// SINCFAST) -// OSR - This parameter is used to -// configure oversampling ratio -// for Data filter (Upto OSR_256) -// DR_switch - This parameter selects whether -// data is represented in 16 (or) -// 32 bits -// shift_bits - When user chooses 16 bit -// representation, this variable -// allows to right shift by -// specific number of bits -// -void Sdfm_configureData_filter(Uint16 sdfmNumber, Uint16 filterNumber, - Uint16 Filter_switch, Uint16 filterType, - Uint16 OSR, Uint16 DR_switch, Uint16 shift_bits) -{ - EALLOW; - - switch(filterNumber) - { - - case FILTER1: //Filter 1 - (*SDFM[sdfmNumber]).SDDFPARM1.bit.FEN = Filter_switch; - (*SDFM[sdfmNumber]).SDDFPARM1.bit.SST = filterType; - - // - //Configure Sinc filter OSR value - // - if(OSR<=DATA_FILTER_MAX_OSR) - { - (*SDFM[sdfmNumber]).SDDFPARM1.bit.DOSR = OSR; - } - else - { - (*SDFM[sdfmNumber]).SDDFPARM1.bit.DOSR = DATA_FILTER_MAX_OSR; - } - - // - //Configure Data filter data representation - //DR_switch - Data Representation (0/1 = 16/32b 2's complement) - // - (*SDFM[sdfmNumber]).SDDPARM1.bit.DR = DR_switch; - if(DR_switch == 0) - { - (*SDFM[sdfmNumber]).SDDPARM1.bit.SH = shift_bits; - } - - break; - - case FILTER2: //Filter 2 - (*SDFM[sdfmNumber]).SDDFPARM2.bit.FEN = Filter_switch; - (*SDFM[sdfmNumber]).SDDFPARM2.bit.SST = filterType; - - // - //Configure Sinc filter OSR value - // - if(OSR<=DATA_FILTER_MAX_OSR) - { - (*SDFM[sdfmNumber]).SDDFPARM2.bit.DOSR = OSR; - } - else - { - (*SDFM[sdfmNumber]).SDDFPARM2.bit.DOSR = DATA_FILTER_MAX_OSR; - } - - // - //Configure Data filter data representation - // DR_switch - Data Representation (0/1 = 16/32b 2's complement) - // - (*SDFM[sdfmNumber]).SDDPARM2.bit.DR = DR_switch; - if(DR_switch == 0) - { - (*SDFM[sdfmNumber]).SDDPARM2.bit.SH = shift_bits; - } - - break; - - case FILTER3: //Filter 3 - (*SDFM[sdfmNumber]).SDDFPARM3.bit.FEN = Filter_switch; - (*SDFM[sdfmNumber]).SDDFPARM3.bit.SST = filterType; - - // - //Configure Sinc filter OSR value - // - if(OSR<=DATA_FILTER_MAX_OSR) - { - (*SDFM[sdfmNumber]).SDDFPARM3.bit.DOSR = OSR; - } - else - { - (*SDFM[sdfmNumber]).SDDFPARM3.bit.DOSR = DATA_FILTER_MAX_OSR; - } - - // - //Configure Data filter data representation - // DR_switch - Data Representation (0/1 = 16/32b 2's complement) - // - (*SDFM[sdfmNumber]).SDDPARM3.bit.DR = DR_switch; - if(DR_switch == 0) - { - (*SDFM[sdfmNumber]).SDDPARM3.bit.SH = shift_bits; - } - - break; - - case FILTER4: //Filter 4 - (*SDFM[sdfmNumber]).SDDFPARM4.bit.FEN = Filter_switch; - (*SDFM[sdfmNumber]).SDDFPARM4.bit.SST = filterType; - - // - //Configure Sinc filter OSR value - // - if(OSR<=DATA_FILTER_MAX_OSR) - { - (*SDFM[sdfmNumber]).SDDFPARM4.bit.DOSR = OSR; - } - else - { - (*SDFM[sdfmNumber]).SDDFPARM4.bit.DOSR = DATA_FILTER_MAX_OSR; - } - - // - //Configure Data filter data representation - // DR_switch - Data Representation (0/1 = 16/32b 2's complement) - // - (*SDFM[sdfmNumber]).SDDPARM4.bit.DR = DR_switch; - if(DR_switch == 0) - { - (*SDFM[sdfmNumber]).SDDPARM4.bit.SH = shift_bits; - } - - break; - } - - EDIS; -} - -// -// Sdfm_configureInterrupt - This function configures SDFM Interrupt unit. -// SDFM Interrupt unit can be configured to -// enable/disable different sources of SDFM -// interrupts which should trigger CPU interrupt. -// -// sdfmNumber - This parameter should be used to -// select SDFM1 (or) SDFM2 -// filterNumber - This parameter is used to select -// which filter(FILTER1,FILTER2, -// FILTER3,FILTER3) needs to be -// configured -// IEH_Switch - This parameter allows over value -// condition to trigger CPU interrupt -// IEL_Switch - This parameter allows under value -// condition to trigger CPU interrupt -// MFIE_Switch - This parameter allows modulator -// failure to trigger CPU interrupt -// AE_Switch - This parameter allows new filter -// data acknowledge interrupt signal -// to trigger CPU interrupt -// -void Sdfm_configureInterrupt(Uint16 sdfmNumber, Uint16 filterNumber, - Uint16 IEH_Switch, Uint16 IEL_Switch, - Uint16 MFIE_Switch, Uint16 AE_Switch) -{ - EALLOW; - - switch(filterNumber) - { - case FILTER1: //Filter 1 - (*SDFM[sdfmNumber]).SDCPARM1.bit.IEH = IEH_Switch; - (*SDFM[sdfmNumber]).SDCPARM1.bit.IEL = IEL_Switch; - (*SDFM[sdfmNumber]).SDCPARM1.bit.MFIE = MFIE_Switch; - (*SDFM[sdfmNumber]).SDDFPARM1.bit.AE = AE_Switch; - break; - - case FILTER2: //Filter 2 - (*SDFM[sdfmNumber]).SDCPARM2.bit.IEH = IEH_Switch; - (*SDFM[sdfmNumber]).SDCPARM2.bit.IEL = IEL_Switch; - (*SDFM[sdfmNumber]).SDCPARM2.bit.MFIE = MFIE_Switch; - (*SDFM[sdfmNumber]).SDDFPARM2.bit.AE = AE_Switch; - break; - - case FILTER3: //Filter 3 - (*SDFM[sdfmNumber]).SDCPARM3.bit.IEH = IEH_Switch; - (*SDFM[sdfmNumber]).SDCPARM3.bit.IEL = IEL_Switch; - (*SDFM[sdfmNumber]).SDCPARM3.bit.MFIE = MFIE_Switch; - (*SDFM[sdfmNumber]).SDDFPARM3.bit.AE = AE_Switch; - break; - - case FILTER4: //Filter 4 - (*SDFM[sdfmNumber]).SDCPARM4.bit.IEH = IEH_Switch; - (*SDFM[sdfmNumber]).SDCPARM4.bit.IEL = IEL_Switch; - (*SDFM[sdfmNumber]).SDCPARM4.bit.MFIE = MFIE_Switch; - (*SDFM[sdfmNumber]).SDDFPARM4.bit.AE = AE_Switch; - break; - } - - EDIS; -} - - -// -// SDFM_configExternalreset - This function configures SDFM module to -// enable/disable external filter reset from PWM -// -// sdfmNumber - This parameter should -// be used to select -// SDFM1 (or) SDFM2 -// filter1_Config_ext_reset - This parameter is used -// to enable/disable -// external PWM reset for -// filter1 -// filter2_Config_ext_reset - This parameter is used -// to enable/disable -// external PWM reset for -// filter2 -// filter3_Config_ext_reset - This parameter is used -// to enable / disable -// external PWM reset for -// filter3 -// filter4_Config_ext_reset - This parameter is used -// to enable / disable -// external PWM reset for -// filter4 -// -void Sdfm_configureExternalreset(Uint16 sdfmNumber, - Uint16 filter1_Config_ext_reset, - Uint16 filter2_Config_ext_reset, - Uint16 filter3_Config_ext_reset, - Uint16 filter4_Config_ext_reset) -{ - EALLOW; - (*SDFM[sdfmNumber]).SDDFPARM1.bit.SDSYNCEN = filter1_Config_ext_reset; - (*SDFM[sdfmNumber]).SDDFPARM2.bit.SDSYNCEN = filter2_Config_ext_reset; - (*SDFM[sdfmNumber]).SDDFPARM3.bit.SDSYNCEN = filter3_Config_ext_reset; - (*SDFM[sdfmNumber]).SDDFPARM4.bit.SDSYNCEN = filter4_Config_ext_reset; - EDIS; -} - -// -// SDFM_enableMFE - This function enables Master filter bit of SDFM module -// -// sdfmNumber - This parameter should be used to select -// SDFM1 (or) SDFM2 -// -void Sdfm_enableMFE(Uint16 sdfmNumber) -{ - EALLOW; - (*SDFM[sdfmNumber]).SDMFILEN.bit.MFE = 1; //Master Filter bit is enabled - EDIS; -} - -// -// SDFM_disableMFE - This function disable Master filter bit of SDFM module -// -// sdfmNumber - This parameter should be used to select -// SDFM1 (or) SDFM2 -// -void SDFM_disableMFE(Uint16 sdfmNumber) -{ - EALLOW; - (*SDFM[sdfmNumber]).SDMFILEN.bit.MFE = 0; //Master Filter bit is disabled - EDIS; -} - -// -// SDFM_enableMIE - This function enable Master Interrupt bit of SDFM module -// -// sdfmNumber - This parameter should be used to select -// SDFM1 (or) SDFM2 -// -void Sdfm_enableMIE(Uint16 sdfmNumber) -{ - EALLOW; - // - //Enable MIE (Master Interrupt Enable) bit - // - (*SDFM[sdfmNumber]).SDCTL.bit.MIE = 1; - EDIS; -} - -// -// Sdfm_disableMIE - This function disable Master Interrupt bit of SDFM module -// -// sdfmNumber - This parameter should be used to select -// SDFM1 (or) SDFM2 -// -void Sdfm_disableMIE(Uint16 sdfmNumber) -{ - - EALLOW; - // - //Disable MIE (Master Interrupt Enable) bit - // - (*SDFM[sdfmNumber]).SDCTL.bit.MIE = 0; - EDIS; -} - -// -// Sdfm_readFlagRegister - This function helps user read SDFM flag -// register (SDIFLG) -// -Uint32 Sdfm_readFlagRegister(Uint16 sdfmNumber) -{ - return ((*SDFM[sdfmNumber]).SDIFLG.all); -} - -// -// Sdfm_clearFlagRegister - This function helps is used to clear -// SDIFLG register -// -void Sdfm_clearFlagRegister(Uint16 sdfmNumber,Uint32 sdfmReadFlagRegister) -{ - (*SDFM[sdfmNumber]).SDIFLGCLR.all = sdfmReadFlagRegister; -} - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_struct.c b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_struct.c deleted file mode 100644 index 1a306bd1d4..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_struct.c +++ /dev/null @@ -1,100 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_struct.c -// -// TITLE: F2837xD SDFM structure -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -// -// Included Files -// -#include "F2837xD_device.h" -#include "F2837xD_struct.h" - -// -// Globals -// -#if defined(CPU1) -volatile struct ADC_REGS *ADC[MAX_ADC] = -{ 0, &AdcaRegs, &AdcbRegs, - &AdccRegs, &AdcdRegs }; -#endif - -volatile struct ECAP_REGS *ECAP[MAX_ECAP] = -{ 0, &ECap1Regs, &ECap2Regs, &ECap3Regs, - &ECap4Regs, &ECap5Regs, &ECap6Regs }; - -volatile struct EPWM_REGS *EPWM[MAX_EPWM] = -{ 0, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, - &EPwm4Regs, &EPwm5Regs, &EPwm6Regs, - &EPwm7Regs, &EPwm8Regs, &EPwm9Regs, - &EPwm10Regs, &EPwm11Regs, &EPwm12Regs }; - -volatile struct EQEP_REGS *EQEP[MAX_EQEP] = -{ 0, &EQep1Regs, &EQep2Regs, &EQep3Regs }; - -volatile struct I2C_REGS *I2C[MAX_I2C] = -{ 0, &I2caRegs }; - -volatile struct McBSP_REGS *MCBSP[MAX_MCBSP] = -{ 0, &McbspaRegs }; - -volatile struct SCI_REGS *SCI[MAX_SCI] = -{ 0, &SciaRegs }; - -volatile struct SPI_REGS *SPI[MAX_SPI] = -{ 0, &SpiaRegs, &SpibRegs, &SpicRegs }; - -volatile struct SDFM_REGS *SDFM[MAX_SDFM] = -{ 0, &Sdfm1Regs, &Sdfm2Regs}; - -#if defined(CPU1) -volatile Uint16 *TRIP_SEL[MAX_TRIPSEL] = -{ 0, &InputXbarRegs.INPUT1SELECT, &InputXbarRegs.INPUT2SELECT, - &InputXbarRegs.INPUT3SELECT, &InputXbarRegs.INPUT4SELECT, - &InputXbarRegs.INPUT5SELECT, &InputXbarRegs.INPUT6SELECT, - &InputXbarRegs.INPUT7SELECT, &InputXbarRegs.INPUT8SELECT, - &InputXbarRegs.INPUT9SELECT, &InputXbarRegs.INPUT10SELECT, - &InputXbarRegs.INPUT11SELECT, &InputXbarRegs.INPUT12SELECT, - &InputXbarRegs.INPUT13SELECT, &InputXbarRegs.INPUT14SELECT -}; -#endif - -// -// End of file -// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_usDelay.asm b/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_usDelay.asm deleted file mode 100644 index 71d3606fd0..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/F2837xD_usDelay.asm +++ /dev/null @@ -1,105 +0,0 @@ -;//########################################################################### -;// -;// FILE: F2837xD_usDelay.asm -;// -;// TITLE: Simple delay function -;// -;// DESCRIPTION: -;// This is a simple delay function that can be used to insert a specified -;// delay into code. -;// This function is only accurate if executed from internal zero-waitstate -;// SARAM. If it is executed from waitstate memory then the delay will be -;// longer then specified. -;// To use this function: -;// 1 - update the CPU clock speed in the F2837xD_Examples.h -;// file. For example: -;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed -;// 2 - Call this function by using the DELAY_US(A) macro -;// that is defined in the F2837xD_Device.h file. This macro -;// will convert the number of microseconds specified -;// into a loop count for use with this function. -;// This count will be based on the CPU frequency you specify. -;// 3 - For the most accurate delay -;// - Execute this function in 0 waitstate RAM. -;// - Disable interrupts before calling the function -;// If you do not disable interrupts, then think of -;// this as an "at least" delay function as the actual -;// delay may be longer. -;// The C assembly call from the DELAY_US(time) macro will -;// look as follows: -;// extern void Delay(long LoopCount); -;// MOV AL,#LowLoopCount -;// MOV AH,#HighLoopCount -;// LCR _Delay -;// Or as follows (if count is less then 16-bits): -;// MOV ACC,#LoopCount -;// LCR _Delay -;// -;//########################################################################### -;// $TI Release: F2837xD Support Library v3.05.00.00 $ -;// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -;// $Copyright: -;// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -;// -;// Redistribution and use in source and binary forms, with or without -;// modification, are permitted provided that the following conditions -;// are met: -;// -;// Redistributions of source code must retain the above copyright -;// notice, this list of conditions and the following disclaimer. -;// -;// Redistributions in binary form must reproduce the above copyright -;// notice, this list of conditions and the following disclaimer in the -;// documentation and/or other materials provided with the -;// distribution. -;// -;// Neither the name of Texas Instruments Incorporated nor the names of -;// its contributors may be used to endorse or promote products derived -;// from this software without specific prior written permission. -;// -;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;// $ -;//########################################################################### - - .def _F28x_usDelay - - .cdecls LIST ;;Used to populate __TI_COMPILER_VERSION__ macro - %{ - %} - - .if __TI_COMPILER_VERSION__ - .if __TI_COMPILER_VERSION__ >= 15009000 - .sect ".TI.ramfunc" ;;Used with compiler v15.9.0 and newer - .else - .sect "ramfuncs" ;;Used with compilers older than v15.9.0 - .endif - .endif - - .global __F28x_usDelay -_F28x_usDelay: - SUB ACC,#1 - BF _F28x_usDelay,GEQ ;; Loop if ACC >= 0 - LRETR - -;There is a 9/10 cycle overhead and each loop -;takes five cycles. The LoopCount is given by -;the following formula: -; DELAY_CPU_CYCLES = 9 + 5*LoopCount -; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 -; The macro DELAY_US(A) performs this calculation for you -; -; - -;// -;// End of file -;// diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/device.c b/bsp/c28x/libraries/tms320f28379d/common/source/device.c deleted file mode 100644 index 171d3ac8f1..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/device.c +++ /dev/null @@ -1,328 +0,0 @@ -//############################################################################# -// -// FILE: device.c -// -// TITLE: Device setup for examples. -// -//############################################################################# -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//############################################################################# - -// -// Included Files -// -#include "device.h" -#include "driverlib.h" -#ifdef __cplusplus -using std::memcpy; -#endif - -//***************************************************************************** -// -// Function to initialize the device. Primarily initializes system control to a -// known state by disabling the watchdog, setting up the SYSCLKOUT frequency, -// and enabling the clocks to the peripherals. -// -//***************************************************************************** -void Device_init(void) -{ - // - // Disable the watchdog - // - SysCtl_disableWatchdog(); - -#ifdef _FLASH - // - // Copy time critical code and flash setup code to RAM. This includes the - // following functions: InitFlash(); - // - // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols - // are created by the linker. Refer to the device .cmd file. - // - memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); - - // - // Call Flash Initialization to setup flash waitstates. This function must - // reside in RAM. - // - Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES); -#endif -#ifdef CPU1 - // - // Set up PLL control and clock dividers - // - SysCtl_setClock(DEVICE_SETCLOCK_CFG); - - // - // Make sure the LSPCLK divider is set to the default (divide by 4) - // - SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_4); - - // - // These asserts will check that the #defines for the clock rates in - // device.h match the actual rates that have been configured. If they do - // not match, check that the calculations of DEVICE_SYSCLK_FREQ and - // DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as - // expected if these are not correct. - // - ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ); - ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ); -#endif - // - // Turn on all peripherals - // - Device_enableAllPeripherals(); -} - -//***************************************************************************** -// -// Function to turn on all peripherals, enabling reads and writes to the -// peripherals' registers. -// -// Note that to reduce power, unused peripherals should be disabled. -// -//***************************************************************************** -void Device_enableAllPeripherals(void) -{ - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DMA); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER0); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER1); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER2); -#ifdef CPU1 - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRPWM); -#endif - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_GTBCLKSYNC); - -#ifdef CPU1 - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF1); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF2); -#endif - - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM4); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM5); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM6); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM8); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM9); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM10); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM11); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM12); - - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP1); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP2); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP3); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP4); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP5); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP6); - - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP1); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP2); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP3); - - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD1); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD2); - - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIA); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIB); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIC); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCID); - - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIA); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIB); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIC); - - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CA); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CB); - - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANB); - - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPA); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPB); - -#ifdef CPU1 - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_USBA); - - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_UPPA); -#endif - - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD); - - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS1); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS2); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS3); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS4); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS5); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS6); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS7); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS8); - - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACA); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACB); - SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACC); -} - -//***************************************************************************** -// -// Function to disable pin locks on GPIOs. -// -//***************************************************************************** -void Device_initGPIO(void) -{ - // - // Disable pin locks. - // - GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF); - GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF); - GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF); - GPIO_unlockPortConfig(GPIO_PORT_D, 0xFFFFFFFF); - GPIO_unlockPortConfig(GPIO_PORT_E, 0xFFFFFFFF); - GPIO_unlockPortConfig(GPIO_PORT_F, 0xFFFFFFFF); - - // - // Enable GPIO Pullups - // - Device_enableUnbondedGPIOPullups(); -} - -//***************************************************************************** -// -// Function to enable pullups for the unbonded GPIOs on the 176PTP package: -// GPIOs Grp Bits -// 95-132 C 31 -// D 31:0 -// E 4:0 -// 134-168 E 31:6 -// F 8:0 -// -//***************************************************************************** - -void Device_enableUnbondedGPIOPullupsFor176Pin(void) -{ - EALLOW; - HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0x80000000U; - HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; - HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFDFU; - HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; - EDIS; -} - -//***************************************************************************** -// -// Function to enable pullups for the unbonded GPIOs on the 100PZ package: -// GPIOs Grp Bits -// 0-1 A 1:0 -// 5-9 A 9:5 -// 22-40 A 31:22 -// B 8:0 -// 44-57 B 25:12 -// 67-68 C 4:3 -// 74-77 C 13:10 -// 79-83 C 19:15 -// 93-168 C 31:29 -// D 31:0 -// E 31:0 -// F 8:0 -// -//***************************************************************************** -void Device_enableUnbondedGPIOPullupsFor100Pin(void) -{ - EALLOW; - HWREG(GPIOCTRL_BASE + GPIO_O_GPAPUD) = ~0xFFC003E3U; - HWREG(GPIOCTRL_BASE + GPIO_O_GPBPUD) = ~0x03FFF1FFU; - HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0xE10FBC18U; - HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; - HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFFFU; - HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; - EDIS; -} - -//***************************************************************************** -// -// Function to enable pullups for the unbonded GPIOs on the 100PZ or -// 176PTP package. -// -//***************************************************************************** -void Device_enableUnbondedGPIOPullups(void) -{ - // - // bits 8-10 have pin count - // - uint16_t pinCount = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & - (uint32_t)SYSCTL_PARTIDL_PIN_COUNT_M) >> - SYSCTL_PARTIDL_PIN_COUNT_S); - - /* - * 5 = 100 pin - * 6 = 176 pin - * 7 = 337 pin - */ - if(pinCount == 5) - { - Device_enableUnbondedGPIOPullupsFor100Pin(); - } - else if(pinCount == 6) - { - Device_enableUnbondedGPIOPullupsFor176Pin(); - } - else - { - // - // Do nothing - this is 337 pin package - // - } -} - -//***************************************************************************** -// -// Error handling function to be called when an ASSERT is violated -// -//***************************************************************************** -void __error__(char *filename, uint32_t line) -{ - // - // An ASSERT condition was evaluated as false. You can use the filename and - // line parameters to determine what went wrong. - // - ESTOP0; -} diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/usb.c b/bsp/c28x/libraries/tms320f28379d/common/source/usb.c deleted file mode 100644 index db82fb7a39..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/usb.c +++ /dev/null @@ -1,3972 +0,0 @@ -//########################################################################### -// -// FILE: usb.c -// -// TITLE: Driver for the USB Interface. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - - -//***************************************************************************** -// -//! \addtogroup usb_api -//! @{ -// -//***************************************************************************** - -#include -#include -#include "inc/hw_ints.h" -#include "inc/hw_memmap.h" -#include "inc/hw_types.h" -#include "inc/hw_usb.h" -#include "driverlib/debug.h" -#include "driverlib/interrupt.h" -#include "driverlib/sysctl.h" -#include "usb.h" - -//***************************************************************************** -// -// Amount to shift the RX interrupt sources by in the flags used in the -// interrupt calls. -// -//***************************************************************************** -#define USB_INTEP_RX_SHIFT 16 - -//***************************************************************************** -// -// Amount to shift the RX endpoint status sources by in the flags used in the -// calls. -// -//***************************************************************************** -#define USB_RX_EPSTATUS_SHIFT 16 - -//***************************************************************************** -// -// Converts from an endpoint specifier to the offset of the endpoint's -// control/status registers. -// -//***************************************************************************** -#define EP_OFFSET(Endpoint) (Endpoint - 0x10) - -//***************************************************************************** -// -// Sets one of the indexed registers. -// -// \param ui32Base specifies the USB module base address. -// \param ui32Endpoint is the endpoint index to target for this write. -// \param ui32IndexedReg is the indexed register to write to. -// \param ui8Value is the value to write to the register. -// -// This function is used to access the indexed registers for each endpoint. -// The only registers that are indexed are the FIFO configuration registers, -// which are not used after configuration. -// -// \return None. -// -//***************************************************************************** -static void -_USBIndexWrite(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32IndexedReg, uint32_t ui32Value, uint32_t ui32Size) -{ - uint32_t ui32Index; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) || - (ui32Endpoint == 3)); - ASSERT((ui32Size == 1) || (ui32Size == 2)); - - // - // Save the old index in case it was in use. - // - ui32Index = HWREGB(ui32Base + USB_O_EPIDX); - - // - // Set the index. - // - HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; - - // - // Determine the size of the register value. - // - if(ui32Size == 1) - { - // - // Set the value. - // - HWREGB(ui32Base + ui32IndexedReg) = ui32Value; - } - else - { - // - // Set the value. - // - HWREGH(ui32Base + ui32IndexedReg) = ui32Value; - } - - // - // Restore the old index in case it was in use. - // - HWREGB(ui32Base + USB_O_EPIDX) = ui32Index; -} - -//***************************************************************************** -// -// Reads one of the indexed registers. -// -// \param ui32Base specifies the USB module base address. -// \param ui32Endpoint is the endpoint index to target for this write. -// \param ui32IndexedReg is the indexed register to write to. -// -// This function is used internally to access the indexed registers for each -// endpoint. The only registers that are indexed are the FIFO configuration -// registers, which are not used after configuration. -// -// \return The value in the register requested. -// -//***************************************************************************** -static uint32_t -_USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32IndexedReg, uint32_t ui32Size) -{ - uint8_t ui8Index; - uint8_t ui8Value; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) || - (ui32Endpoint == 3)); - ASSERT((ui32Size == 1) || (ui32Size == 2)); - - // - // Save the old index in case it was in use. - // - ui8Index = HWREGB(ui32Base + USB_O_EPIDX); - - // - // Set the index. - // - HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; - - // - // Determine the size of the register value. - // - if(ui32Size == 1) - { - // - // Get the value. - // - ui8Value = HWREGB(ui32Base + ui32IndexedReg); - } - else - { - // - // Get the value. - // - ui8Value = HWREGH(ui32Base + ui32IndexedReg); - } - - // - // Restore the old index in case it was in use. - // - HWREGB(ui32Base + USB_O_EPIDX) = ui8Index; - - // - // Return the register's value. - // - return(ui8Value); -} - -//***************************************************************************** -// -//! Puts the USB bus in a suspended state. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! When used in host mode, this function puts the USB bus in the suspended -//! state. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostSuspend(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Send the suspend signaling to the USB bus. - // - HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SUSPEND; -} - -//***************************************************************************** -// -//! Handles the USB bus reset condition. -//! -//! \param ui32Base specifies the USB module base address. -//! \param bStart specifies whether to start or stop signaling reset on the USB -//! bus. -//! -//! When this function is called with the \e bStart parameter set to \b true, -//! this function causes the start of a reset condition on the USB bus. -//! The caller must then delay at least 20ms before calling this function -//! again with the \e bStart parameter set to \b false. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostReset(uint32_t ui32Base, bool bStart) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Send a reset signal to the bus. - // - if(bStart) - { - HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESET; - } - else - { - HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESET; - } -} - -//***************************************************************************** -// -//! Handles the USB bus resume condition. -//! -//! \param ui32Base specifies the USB module base address. -//! \param bStart specifies if the USB controller is entering or leaving the -//! resume signaling state. -//! -//! When in device mode, this function brings the USB controller out of the -//! suspend state. This call must first be made with the \e bStart parameter -//! set to \b true to start resume signaling. The device application must -//! then delay at least 10ms but not more than 15ms before calling this -//! function with the \e bStart parameter set to \b false. -//! -//! When in host mode, this function signals devices to leave the suspend -//! state. This call must first be made with the \e bStart parameter set to -//! \b true to start resume signaling. The host application must then delay -//! at least 20ms before calling this function with the \e bStart parameter set -//! to \b false. This action causes the controller to complete the resume -//! signaling on the USB bus. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostResume(uint32_t ui32Base, bool bStart) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Send a resume signal to the bus. - // - if(bStart) - { - HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESUME; - } - else - { - HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESUME; - } -} - -//***************************************************************************** -// -//! Returns the current speed of the USB device connected. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the current speed of the USB bus in host mode. -//! -//! \b Example: Get the USB connection speed. -//! -//! \verbatim -//! // -//! // Get the connection speed of the device connected to the USB controller. -//! // -//! USBHostSpeedGet(USB0_BASE); -//! \endverbatim -//! -//! \note This function must only be called in host mode. -//! -//! \return Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, -//! or \b USB_UNDEF_SPEED. -// -//***************************************************************************** -uint32_t -USBHostSpeedGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // If the Full Speed device bit is set, then this is a full speed device. - // - if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_FSDEV) - { - return(USB_FULL_SPEED); - } - - // - // If the Low Speed device bit is set, then this is a low speed device. - // - if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_LSDEV) - { - return(USB_LOW_SPEED); - } - - // - // The device speed is not known. - // - return(USB_UNDEF_SPEED); -} - -//***************************************************************************** -// -//! Disables control interrupts on a given USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Flags specifies which control interrupts to disable. -//! -//! This function disables the control interrupts for the USB controller -//! specified by the \e ui32Base parameter. The \e ui32Flags parameter -//! specifies which control interrupts to disable. The flags passed in the -//! \e ui32Flags parameters must be the definitions that start with -//! \b USB_INTCTRL_* and not any other \b USB_INT flags. -//! -//! \return None. -// -//***************************************************************************** -void -USBIntDisableControl(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Flags & ~(USB_INTCTRL_ALL)) == 0); - - // - // If any general interrupts were disabled then write the general interrupt - // settings out to the hardware. - // - if(ui32Flags & USB_INTCTRL_STATUS) - { - HWREGB(ui32Base + USB_O_IE) &= ~(ui32Flags & USB_INTCTRL_STATUS); - } - - // - // Disable the power fault interrupt. - // - if(ui32Flags & USB_INTCTRL_POWER_FAULT) - { - HWREG(ui32Base + USB_O_EPCIM) = 0; - } - - // - // Disable the ID pin detect interrupt. - // - if(ui32Flags & USB_INTCTRL_MODE_DETECT) - { - HWREG(USB0_BASE + USB_O_IDVIM) = 0; - } -} - -//***************************************************************************** -// -//! Enables control interrupts on a given USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Flags specifies which control interrupts to enable. -//! -//! This function enables the control interrupts for the USB controller -//! specified by the \e ui32Base parameter. The \e ui32Flags parameter -//! specifies which control interrupts to enable. The flags passed in the -//! \e ui32Flags parameters must be the definitions that start with -//! \b USB_INTCTRL_* and not any other \b USB_INT flags. -//! -//! \return None. -// -//***************************************************************************** -void -USBIntEnableControl(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Flags & (~USB_INTCTRL_ALL)) == 0); - - // - // If any general interrupts were enabled, then write the general - // interrupt settings out to the hardware. - // - if(ui32Flags & USB_INTCTRL_STATUS) - { - HWREGB(ui32Base + USB_O_IE) |= ui32Flags; - } - - // - // Enable the power fault interrupt. - // - if(ui32Flags & USB_INTCTRL_POWER_FAULT) - { - HWREG(ui32Base + USB_O_EPCIM) = USB_EPCIM_PF; - } - - // - // Enable the ID pin detect interrupt. - // - if(ui32Flags & USB_INTCTRL_MODE_DETECT) - { - HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID; - } -} - -//***************************************************************************** -// -//! Returns the control interrupt status on a given USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32IntStatusEP is a pointer to the variable which holds the -//! endpoint interrupt status from RXIS And TXIS. -//! -//! This function reads control interrupt status for a USB controller. This -//! call returns the current status for control interrupts only, the endpoint -//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit -//! values returned are compared against the \b USB_INTCTRL_* values. -//! -//! The following are the meanings of all \b USB_INCTRL_ flags and the modes -//! for which they are valid. These values apply to any calls to -//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). -//! Some of these flags are only valid in the following modes as indicated in -//! the parentheses: Host, Device, and OTG. -//! -//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. -//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). -//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable -//! (OTG Only). -//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) -//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) -//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) -//! - \b USB_INTCTRL_SOF - Start of Frame Detected. -//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past -//! the end of a frame (Host Only) -//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) -//! - \b USB_INTCTRL_RESUME - Resume signaling detected. -//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device -//! Only) -//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed -//! (OTG Only) -//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) -//! -//! \note This call clears the source of all of the control status interrupts. -//! -//! \return Returns the status of the control interrupts for a USB controller. -//! This is the value of USBIS. -// -//***************************************************************************** -uint32_t -USBIntStatus(uint32_t ui32Base, uint32_t *pui32IntStatusEP) -{ - uint32_t ui32Status = 0; - *pui32IntStatusEP = 0; - uint32_t usbis = 0; - uint32_t rxis = 0; - uint32_t txis = 0; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - // - // Do-While to make sure that all status registers are cleared before continuing. - // This eliminates the race condition which can cause the USB interrupt to stay high - // and never get triggered again. - // - do - { - // Get the general interrupt status. - usbis = (uint32_t)HWREGB(ui32Base + USB_O_IS); - // Get the transmit interrupt status. - txis = (uint32_t)HWREGH(ui32Base + USB_O_TXIS); - // Get the receive interrupt status. - rxis = (uint32_t)HWREGH(ui32Base + USB_O_RXIS); - - // Get the general interrupt status, these bits go into the upper 8 bits - // of the returned value. - ui32Status |= usbis; - // Get the transmit interrupt status. - *pui32IntStatusEP |= txis; - // Get the receive interrupt status, these bits go into the second byte of - // the returned value. - *pui32IntStatusEP |= ((uint32_t)rxis << USB_INTEP_RX_SHIFT); - - } while(usbis != 0x0000 || txis != 0x0000 || rxis != 0x0000); - - // - // Add the power fault status. - // - if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) - { - // - // Indicate a power fault was detected. - // - ui32Status |= USB_INTCTRL_POWER_FAULT; - - // - // Clear the power fault interrupt. - // - HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; - } - - if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID) - { - // - // Indicate an id detection. - // - ui32Status |= USB_INTCTRL_MODE_DETECT; - - // - // Clear the id detection interrupt. - // - HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID; - } - - // - // Return the combined interrupt status. - // - return(ui32Status); -} - -//***************************************************************************** -// -//! Returns the control interrupt status on a given USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function reads control interrupt status for a USB controller. This -//! call returns the current status for control interrupts only, the endpoint -//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit -//! values returned are compared against the \b USB_INTCTRL_* values. -//! -//! The following are the meanings of all \b USB_INCTRL_ flags and the modes -//! for which they are valid. These values apply to any calls to -//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). -//! Some of these flags are only valid in the following modes as indicated in -//! the parentheses: Host, Device, and OTG. -//! -//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. -//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). -//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable -//! (OTG Only). -//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) -//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) -//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) -//! - \b USB_INTCTRL_SOF - Start of Frame Detected. -//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past -//! the end of a frame (Host Only) -//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) -//! - \b USB_INTCTRL_RESUME - Resume signaling detected. -//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device -//! Only) -//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed -//! (OTG Only) -//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) -//! -//! \note This call clears the source of all of the control status interrupts. -//! -//! \return Returns the status of the control interrupts for a USB controller. -// -//***************************************************************************** -uint32_t -USBIntStatusControl(uint32_t ui32Base) -{ - uint32_t ui32Status; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Get the general interrupt status, these bits go into the upper 8 bits - // of the returned value. - // - ui32Status = HWREGB(ui32Base + USB_O_IS); - - //*ui32EPStatus = USBIntStatusEndpoint(ui32Base); - - // - // Add the power fault status. - // - if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) - { - // - // Indicate a power fault was detected. - // - ui32Status |= USB_INTCTRL_POWER_FAULT; - - // - // Clear the power fault interrupt. - // - HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; - } - - if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID) - { - // - // Indicate an id detection. - // - ui32Status |= USB_INTCTRL_MODE_DETECT; - - // - // Clear the id detection interrupt. - // - HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID; - } - - // - // Return the combined interrupt status. - // - return(ui32Status); -} - -//***************************************************************************** -// -//! Disables endpoint interrupts on a given USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Flags specifies which endpoint interrupts to disable. -//! -//! This function disables endpoint interrupts for the USB controller specified -//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which -//! endpoint interrupts to disable. The flags passed in the \e ui32Flags -//! parameters must be the definitions that start with \b USB_INTEP_* and not -//! any other \b USB_INT flags. -//! -//! \return None. -// -//***************************************************************************** -void -USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // If any transmit interrupts were disabled, then write the transmit - // interrupt settings out to the hardware. - // - HWREGH(ui32Base + USB_O_TXIE) &= - ~(ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); - - // - // If any receive interrupts were disabled, then write the receive - // interrupt settings out to the hardware. - // - HWREGH(ui32Base + USB_O_RXIE) &= - ~((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> - USB_INTEP_RX_SHIFT); -} - -//***************************************************************************** -// -//! Enables endpoint interrupts on a given USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Flags specifies which endpoint interrupts to enable. -//! -//! This function enables endpoint interrupts for the USB controller specified -//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which -//! endpoint interrupts to enable. The flags passed in the \e ui32Flags -//! parameters must be the definitions that start with \b USB_INTEP_* and not -//! any other \b USB_INT flags. -//! -//! \return None. -// -//***************************************************************************** -void -USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Enable any transmit endpoint interrupts. - // - HWREGH(ui32Base + USB_O_TXIE) |= - ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0); - - // - // Enable any receive endpoint interrupts. - // - HWREGH(ui32Base + USB_O_RXIE) |= - ((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> - USB_INTEP_RX_SHIFT); -} - -//***************************************************************************** -// -//! Returns the endpoint interrupt status on a given USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function reads endpoint interrupt status for a USB controller. This -//! call returns the current status for endpoint interrupts only, the control -//! interrupt status is retrieved by calling USBIntStatusControl(). The bit -//! values returned are compared against the \b USB_INTEP_* values. -//! These values are grouped into classes for \b USB_INTEP_HOST_* and -//! \b USB_INTEP_DEV_* values to handle both host and device modes with all -//! endpoints. -//! -//! \note This call clears the source of all of the endpoint interrupts. -//! -//! \return Returns the status of the endpoint interrupts for a USB controller. -// -//***************************************************************************** -uint32_t -USBIntStatusEndpoint(uint32_t ui32Base) -{ - uint32_t ui32Status; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Get the transmit interrupt status. - // - ui32Status = HWREGH(ui32Base + USB_O_TXIS); - ui32Status |= ((uint32_t)HWREGH(ui32Base + USB_O_RXIS) << USB_INTEP_RX_SHIFT); - - // - // Return the combined interrupt status. - // - return(ui32Status); -} - -//***************************************************************************** -// -//! Returns the interrupt number for a given USB module. -//! -//! \param ui32Base is the base address of the USB module. -//! -//! This function returns the interrupt number for the USB module with the base -//! address passed in the \e ui32Base parameter. -//! -//! \return Returns the USB interrupt number or 0 if the interrupt does not -//! exist. -// -//***************************************************************************** -static uint32_t -_USBIntNumberGet(uint32_t ui32Base) -{ - return(INT_USB0); -} - -//***************************************************************************** -// -//! Registers an interrupt handler for the USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! \param pfnHandler is a pointer to the function to be called when a USB -//! interrupt occurs. -//! -//! This function registers the handler to be called when a USB interrupt -//! occurs and enables the global USB interrupt in the interrupt controller. -//! The specific desired USB interrupts must be enabled via a separate call to -//! USBIntEnable(). It is the interrupt handler's responsibility to clear the -//! interrupt sources via calls to USBIntStatusControl() and -//! USBIntStatusEndpoint(). -//! -//! \sa IntRegister() for important information about registering interrupt -//! handlers. -//! -//! \return None. -// -//***************************************************************************** -void -USBIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - ui32Int = _USBIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Register the interrupt handler. - // - IntRegister(ui32Int, pfnHandler); - - // - // Enable the USB interrupt. - // - IntEnable(ui32Int); -} - -//***************************************************************************** -// -//! Unregisters an interrupt handler for the USB controller. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function unregisters the interrupt handler. This function also -//! disables the USB interrupt in the interrupt controller. -//! -//! \sa IntRegister() for important information about registering or -//! unregistering interrupt handlers. -//! -//! \return None. -// -//***************************************************************************** -void -USBIntUnregister(uint32_t ui32Base) -{ - uint32_t ui32Int; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - ui32Int = _USBIntNumberGet(ui32Base); - - ASSERT(ui32Int != 0); - - // - // Disable the USB interrupt. - // - IntDisable(ui32Int); - - // - // Unregister the interrupt handler. - // - IntUnregister(ui32Int); -} - -//***************************************************************************** -// -//! Returns the current status of an endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! -//! This function returns the status of a given endpoint. If any of these -//! status bits must be cleared, then the USBDevEndpointStatusClear() or the -//! USBHostEndpointStatusClear() functions must be called. -//! -//! The following are the status flags for host mode: -//! -//! - \b USB_HOST_IN_PID_ERROR - PID error on the given endpoint. -//! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request. -//! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint. -//! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN -//! endpoint in Isochronous mode. -//! - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than -//! the specified timeout period. -//! - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN -//! endpoint. -//! - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full. -//! - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint. -//! - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than -//! the specified timeout period. -//! - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT -//! request. -//! - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint. -//! - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this -//! OUT endpoint. -//! - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty. -//! - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not -//! completed. -//! - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the -//! specified timeout period. -//! - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on -//! endpoint zero. -//! - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an -//! IN transaction. -//! - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN -//! transaction. -//! -//! The following are the status flags for device mode: -//! -//! - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint. -//! - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT -//! endpoint. -//! - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO. -//! - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full. -//! - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT -//! endpoint's FIFO. -//! - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come. -//! - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint. -//! - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no -//! data was ready. -//! - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty. -//! - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not -//! completed. -//! - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End -//! condition was sent. -//! - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero. -//! - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not -//! completed. -//! - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint -//! zero's OUT FIFO. -//! -//! \return The current status flags for the endpoint depending on mode. -// -//***************************************************************************** -uint32_t -USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint) -{ - uint32_t ui32Status; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Get the TX portion of the endpoint status. - // - ui32Status = HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1); - - // - // Get the RX portion of the endpoint status. - // - ui32Status |= - (((uint32_t)HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1)) << - USB_RX_EPSTATUS_SHIFT); - - // - // Return the endpoint status. - // - return(ui32Status); -} - -//***************************************************************************** -// -//! Clears the status bits in this endpoint in host mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Flags are the status bits that are cleared. -//! -//! This function clears the status of any bits that are passed in the -//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value -//! returned from the USBEndpointStatus() call. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Clear the specified flags for the endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - HWREGB(ui32Base + USB_O_CSRL0) &= ~ui32Flags; - } - else - { - HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= - ~ui32Flags; - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= - ~(ui32Flags >> USB_RX_EPSTATUS_SHIFT); - } -} - -//***************************************************************************** -// -//! Clears the status bits in this endpoint in device mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Flags are the status bits that are cleared. -//! -//! This function clears the status of any bits that are passed in the -//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value -//! returned from the USBEndpointStatus() call. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // If this is endpoint 0, then the bits have different meaning and map - // into the TX memory location. - // - if(ui32Endpoint == USB_EP_0) - { - // - // Set the Serviced RxPktRdy bit to clear the RxPktRdy. - // - if(ui32Flags & USB_DEV_EP0_OUT_PKTRDY) - { - HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_RXRDYC; - } - - // - // Set the serviced Setup End bit to clear the SetupEnd status. - // - if(ui32Flags & USB_DEV_EP0_SETUP_END) - { - HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_SETENDC; - } - - // - // Clear the Sent Stall status flag. - // - if(ui32Flags & USB_DEV_EP0_SENT_STALL) - { - HWREGB(ui32Base + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL); - } - } - else - { - // - // Clear out any TX flags that were passed in. Only - // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN must be cleared. - // - HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= - ~(ui32Flags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN)); - - // - // Clear out valid RX flags that were passed in. Only - // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN - // must be cleared. - // - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= - ~((ui32Flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR | - USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT); - } -} - -//***************************************************************************** -// -//! Sets the value data toggle on an endpoint in host mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint specifies the endpoint to reset the data toggle. -//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1. -//! \param ui32Flags specifies whether to set the IN or OUT endpoint. -//! -//! This function is used to force the state of the data toggle in host mode. -//! If the value passed in the \e bDataToggle parameter is \b false, then the -//! data toggle is set to the DATA0 state, and if it is \b true it is set to -//! the DATA1 state. The \e ui32Flags parameter can be \b USB_EP_HOST_IN or -//! \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The -//! \e ui32Flags parameter is ignored for endpoint zero. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, - bool bDataToggle, uint32_t ui32Flags) -{ - uint32_t ui32DataToggle; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // The data toggle defaults to DATA0. - // - ui32DataToggle = 0; - - // - // See if the data toggle must be set to DATA1. - // - if(bDataToggle) - { - // - // Select the data toggle bit based on the endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - ui32DataToggle = USB_CSRH0_DT; - } - else if(ui32Flags == USB_EP_HOST_IN) - { - ui32DataToggle = USB_RXCSRH1_DT; - } - else - { - ui32DataToggle = USB_TXCSRH1_DT; - } - } - - // - // Set the data toggle based on the endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - // - // Set the write enable and the bit value for endpoint zero. - // - HWREGB(ui32Base + USB_O_CSRH0) = - ((HWREGB(ui32Base + USB_O_CSRH0) & - ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) | - (ui32DataToggle | USB_CSRH0_DTWE)); - } - else if(ui32Flags == USB_EP_HOST_IN) - { - // - // Set the Write enable and the bit value for an IN endpoint. - // - HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) = - ((HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) & - ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) | - (ui32DataToggle | USB_RXCSRH1_DTWE)); - } - else - { - // - // Set the Write enable and the bit value for an OUT endpoint. - // - HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) = - ((HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) & - ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) | - (ui32DataToggle | USB_TXCSRH1_DTWE)); - } -} - -//***************************************************************************** -// -//! Sets the data toggle on an endpoint to zero. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint specifies the endpoint to reset the data toggle. -//! \param ui32Flags specifies whether to access the IN or OUT endpoint. -//! -//! This function causes the USB controller to clear the data toggle for an -//! endpoint. This call is not valid for endpoint zero and can be made with -//! host or device controllers. -//! -//! The \e ui32Flags parameter must be one of \b USB_EP_HOST_OUT, -//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. -//! -//! \return None. -// -//***************************************************************************** -void -USBEndpointDataToggleClear(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || - (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || - (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || - (ui32Endpoint == USB_EP_7)); - - // - // See if the transmit or receive data toggle must be cleared. - // - if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) - { - HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= - USB_TXCSRL1_CLRDT; - } - else - { - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= - USB_RXCSRL1_CLRDT; - } -} - -//***************************************************************************** -// -//! Stalls the specified endpoint in device mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint specifies the endpoint to stall. -//! \param ui32Flags specifies whether to stall the IN or OUT endpoint. -//! -//! This function causes the endpoint number passed in to go into a stall -//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the -//! stall is issued on the IN portion of this endpoint. If the \e ui32Flags -//! parameter is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion -//! of this endpoint. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Determine how to stall this endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - // - // Perform a stall on endpoint zero. - // - HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_STALL | USB_CSRL0_RXRDYC; - } - else if(ui32Flags == USB_EP_DEV_IN) - { - // - // Perform a stall on an IN endpoint. - // - HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= - USB_TXCSRL1_STALL; - } - else - { - // - // Perform a stall on an OUT endpoint. - // - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= - USB_RXCSRL1_STALL; - } -} - -//***************************************************************************** -// -//! Clears the stall condition on the specified endpoint in device mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint specifies which endpoint to remove the stall condition. -//! \param ui32Flags specifies whether to remove the stall condition from the -//! IN or the OUT portion of this endpoint. -//! -//! This function causes the endpoint number passed in to exit the stall -//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the -//! stall is cleared on the IN portion of this endpoint. If the \e ui32Flags -//! parameter is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT -//! portion of this endpoint. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0); - - // - // Determine how to clear the stall on this endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - // - // Clear the stall on endpoint zero. - // - HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_STALLED; - } - else if(ui32Flags == USB_EP_DEV_IN) - { - // - // Clear the stall on an IN endpoint. - // - HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= - ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); - - // - // Reset the data toggle. - // - HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= - USB_TXCSRL1_CLRDT; - } - else - { - // - // Clear the stall on an OUT endpoint. - // - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= - ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); - - // - // Reset the data toggle. - // - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= - USB_RXCSRL1_CLRDT; - } -} - -//***************************************************************************** -// -//! Connects the USB controller to the bus in device mode. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function causes the soft connect feature of the USB controller to -//! be enabled. Call USBDevDisconnect() to remove the USB device from the bus. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevConnect(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Enable connection to the USB bus. - // - HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SOFTCONN; -} - -//***************************************************************************** -// -//! Removes the USB controller from the bus in device mode. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function causes the soft connect feature of the USB controller to -//! remove the device from the USB bus. A call to USBDevConnect() is needed to -//! reconnect to the bus. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevDisconnect(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Disable connection to the USB bus. - // - HWREGB(ui32Base + USB_O_POWER) &= (~USB_POWER_SOFTCONN); -} - -//***************************************************************************** -// -//! Sets the address in device mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Address is the address to use for a device. -//! -//! This function configures the device address on the USB bus. This address -//! was likely received via a SET ADDRESS command from the host controller. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Set the function address in the correct location. - // - HWREGB(ui32Base + USB_O_FADDR) = (uint8_t)ui32Address; -} - -//***************************************************************************** -// -//! Returns the current device address in device mode. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the current device address. This address was set -//! by a call to USBDevAddrSet(). -//! -//! \note This function must only be called in device mode. -//! -//! \return The current device address. -// -//***************************************************************************** -uint32_t -USBDevAddrGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Return the function address. - // - return(HWREGB(ui32Base + USB_O_FADDR)); -} - -//***************************************************************************** -// -//! Sets the base configuration for a host endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32MaxPayload is the maximum payload for this endpoint. -//! \param ui32NAKPollInterval is the either the NAK timeout limit or the -//! polling interval, depending on the type of endpoint. -//! \param ui32TargetEndpoint is the endpoint that the host endpoint is -//! targeting. -//! \param ui32Flags are used to configure other endpoint settings. -//! -//! This function sets the basic configuration for the transmit or receive -//! portion of an endpoint in host mode. The \e ui32Flags parameter determines -//! some of the configuration while the other parameters provide the rest. The -//! \e ui32Flags parameter determines whether this is an IN endpoint -//! (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint -//! (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed -//! endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint -//! (\b USB_EP_SPEED_LOW). -//! -//! The \b USB_EP_MODE_ flags control the type of the endpoint. -//! - \b USB_EP_MODE_CTRL is a control endpoint. -//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. -//! - \b USB_EP_MODE_BULK is a bulk endpoint. -//! - \b USB_EP_MODE_INT is an interrupt endpoint. -//! -//! The \e ui32NAKPollInterval parameter has different meanings based on the -//! \b USB_EP_MODE value and whether or not this call is being made for -//! endpoint zero or another endpoint. For endpoint zero or any Bulk -//! endpoints, this value always indicates the number of frames to allow a -//! device to NAK before considering it a timeout. If this endpoint is an -//! isochronous or interrupt endpoint, this value is the polling interval for -//! this endpoint. -//! -//! For interrupt endpoints, the polling interval is the number of frames -//! between interrupt IN requests to an endpoint and has a range of 1 to 255. -//! For isochronous endpoints this value represents a polling interval of -//! 2 ^ (\e ui32NAKPollInterval - 1) frames. When used as a NAK timeout, the -//! \e ui32NAKPollInterval value specifies 2 ^ (\e ui32NAKPollInterval - 1) -//! frames before issuing a time out. -//! -//! There are two special time out values that can be specified when setting -//! the \e ui32NAKPollInterval value. The first is \b MAX_NAK_LIMIT, which is -//! the maximum value that can be passed in this variable. The other is -//! \b DISABLE_NAK_LIMIT, which indicates that there is no limit on the -//! number of NAKs. -//! -//! The \b USB_EP_DMA_MODE_ flags enable the type of DMA used to access the -//! endpoint's data FIFOs. The choice of the DMA mode depends on how the DMA -//! controller is configured and how it is being used. See the ``Using USB -//! with the uDMA Controller'' section for more information on DMA -//! configuration. -//! -//! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit -//! is specified to cause the transmission of data on the USB bus to start -//! as soon as the number of bytes specified by \e ui32MaxPayload has been -//! written into the OUT FIFO for this endpoint. -//! -//! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST -//! bit can be specified to trigger the request for more data once the FIFO has -//! been drained enough to fit \e ui32MaxPayload bytes. The -//! \b USB_EP_AUTO_CLEAR bit can be used to clear the data packet ready flag -//! automatically once the data has been read from the FIFO. If this option is -//! not used, this flag must be manually cleared via a call to -//! USBDevEndpointStatusClear() or USBHostEndpointStatusClear(). -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32MaxPayload, uint32_t ui32NAKPollInterval, - uint32_t ui32TargetEndpoint, uint32_t ui32Flags) -{ - uint32_t ui32Register; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - ASSERT(ui32NAKPollInterval <= MAX_NAK_LIMIT); - - // - // Endpoint zero is configured differently than the other endpoints, so see - // if this is endpoint zero. - // - if(ui32Endpoint == USB_EP_0) - { - // - // Set the NAK timeout. - // - HWREGB(ui32Base + USB_O_NAKLMT) = ui32NAKPollInterval; - - // - // Set the transfer type information. - // - HWREGB(ui32Base + USB_O_TYPE0) = - ((ui32Flags & USB_EP_SPEED_FULL) ? USB_TYPE0_SPEED_FULL : - USB_TYPE0_SPEED_LOW); - } - else - { - // - // Start with the target endpoint. - // - ui32Register = ui32TargetEndpoint; - - // - // Set the speed for the device using this endpoint. - // - if(ui32Flags & USB_EP_SPEED_FULL) - { - ui32Register |= USB_TXTYPE1_SPEED_FULL; - } - else - { - ui32Register |= USB_TXTYPE1_SPEED_LOW; - } - - // - // Set the protocol for the device using this endpoint. - // - switch(ui32Flags & USB_EP_MODE_MASK) - { - // - // The bulk protocol is being used. - // - case USB_EP_MODE_BULK: - { - ui32Register |= USB_TXTYPE1_PROTO_BULK; - break; - } - - // - // The isochronous protocol is being used. - // - case USB_EP_MODE_ISOC: - { - ui32Register |= USB_TXTYPE1_PROTO_ISOC; - break; - } - - // - // The interrupt protocol is being used. - // - case USB_EP_MODE_INT: - { - ui32Register |= USB_TXTYPE1_PROTO_INT; - break; - } - - // - // The control protocol is being used. - // - case USB_EP_MODE_CTRL: - { - ui32Register |= USB_TXTYPE1_PROTO_CTRL; - break; - } - } - - // - // See if the transmit or receive endpoint is being configured. - // - if(ui32Flags & USB_EP_HOST_OUT) - { - // - // Set the transfer type information. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) = - ui32Register; - - // - // Set the NAK timeout or polling interval. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXINTERVAL1) = - ui32NAKPollInterval; - - // - // Set the Maximum Payload per transaction. - // - HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = - ui32MaxPayload; - - // - // Set the transmit control value to zero. - // - ui32Register = 0; - - // - // Allow auto setting of TxPktRdy when max packet size has been - // loaded into the FIFO. - // - if(ui32Flags & USB_EP_AUTO_SET) - { - ui32Register |= USB_TXCSRH1_AUTOSET; - } - - // - // Configure the DMA Mode. - // - if(ui32Flags & USB_EP_DMA_MODE_1) - { - ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; - } - else if(ui32Flags & USB_EP_DMA_MODE_0) - { - ui32Register |= USB_TXCSRH1_DMAEN; - } - - // - // Write out the transmit control value. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = - (uint8_t)ui32Register; - } - else - { - // - // Set the transfer type information. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) = - ui32Register; - - // - // Set the NAK timeout or polling interval. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXINTERVAL1) = - ui32NAKPollInterval; - - // - // Set the Maximum Payload per transaction. - // - HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = - ui32MaxPayload; - - // - // Set the receive control value to zero. - // - ui32Register = 0; - - // - // Allow auto clearing of RxPktRdy when packet of size max packet - // has been unloaded from the FIFO. - // - if(ui32Flags & USB_EP_AUTO_CLEAR) - { - ui32Register |= USB_RXCSRH1_AUTOCL; - } - - // - // Allow auto generation of DMA requests. - // - if(ui32Flags & USB_EP_AUTO_REQUEST) - { - ui32Register |= USB_RXCSRH1_AUTORQ; - } - - // - // Configure the DMA Mode. - // - if(ui32Flags & USB_EP_DMA_MODE_1) - { - ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; - } - else if(ui32Flags & USB_EP_DMA_MODE_0) - { - ui32Register |= USB_RXCSRH1_DMAEN; - } - - // - // Write out the receive control value. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = - (uint8_t)ui32Register; - } - } -} - -//***************************************************************************** -// -//! Sets the configuration for an endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32MaxPacketSize is the maximum packet size for this endpoint. -//! \param ui32Flags are used to configure other endpoint settings. -//! -//! This function sets the basic configuration for an endpoint in device mode. -//! Endpoint zero does not have a dynamic configuration, so this function -//! must not be called for endpoint zero. The \e ui32Flags parameter -//! determines some of the configuration while the other parameters provide the -//! rest. -//! -//! The \b USB_EP_MODE_ flags define what the type is for the given endpoint. -//! -//! - \b USB_EP_MODE_CTRL is a control endpoint. -//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. -//! - \b USB_EP_MODE_BULK is a bulk endpoint. -//! - \b USB_EP_MODE_INT is an interrupt endpoint. -//! -//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the -//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA -//! controller is configured and how it is being used. See the ``Using USB -//! with the uDMA Controller'' section for more information on DMA -//! configuration. -//! -//! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be -//! specified to cause the automatic transmission of data on the USB bus as -//! soon as \e ui32MaxPacketSize bytes of data are written into the FIFO for -//! this endpoint. This option is commonly used with DMA as no interaction is -//! required to start the transmission of data. -//! -//! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is -//! specified to trigger the request for more data once the FIFO has been -//! drained enough to receive \e ui32MaxPacketSize more bytes of data. Also -//! for OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the -//! data packet ready flag automatically once the data has been read from the -//! FIFO. If this option is not used, this flag must be manually cleared via a -//! call to USBDevEndpointStatusClear(). Both of these settings can be used to -//! remove the need for extra calls when using the controller in DMA mode. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32MaxPacketSize, uint32_t ui32Flags) -{ - uint32_t ui32Register; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || - (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || - (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || - (ui32Endpoint == USB_EP_7)); - - // - // Determine if a transmit or receive endpoint is being configured. - // - if(ui32Flags & USB_EP_DEV_IN) - { - // - // Set the maximum packet size. - // - HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = - ui32MaxPacketSize; - - // - // The transmit control value is zero unless options are enabled. - // - ui32Register = 0; - - // - // Allow auto setting of TxPktRdy when max packet size has been loaded - // into the FIFO. - // - if(ui32Flags & USB_EP_AUTO_SET) - { - ui32Register |= USB_TXCSRH1_AUTOSET; - } - - // - // Configure the DMA mode. - // - if(ui32Flags & USB_EP_DMA_MODE_1) - { - ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; - } - else if(ui32Flags & USB_EP_DMA_MODE_0) - { - ui32Register |= USB_TXCSRH1_DMAEN; - } - - // - // Enable isochronous mode if requested. - // - if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) - { - ui32Register |= USB_TXCSRH1_ISO; - } - - // - // Write the transmit control value. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = - (uint8_t)ui32Register; - - // - // Reset the Data toggle to zero. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1) = - USB_TXCSRL1_CLRDT; - } - else - { - // - // Set the MaxPacketSize. - // - HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = - ui32MaxPacketSize; - - // - // The receive control value is zero unless options are enabled. - // - ui32Register = 0; - - // - // Allow auto clearing of RxPktRdy when packet of size max packet - // has been unloaded from the FIFO. - // - if(ui32Flags & USB_EP_AUTO_CLEAR) - { - ui32Register = USB_RXCSRH1_AUTOCL; - } - - // - // Configure the DMA mode. - // - if(ui32Flags & USB_EP_DMA_MODE_1) - { - ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; - } - else if(ui32Flags & USB_EP_DMA_MODE_0) - { - ui32Register |= USB_RXCSRH1_DMAEN; - } - - // - // Enable isochronous mode if requested. - // - if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) - { - ui32Register |= USB_RXCSRH1_ISO; - } - - // - // Write the receive control value. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = - (uint8_t)ui32Register; - - // - // Reset the Data toggle to zero. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1) = - USB_RXCSRL1_CLRDT; - } -} - -//***************************************************************************** -// -//! Gets the current configuration for an endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param pui32MaxPacketSize is a pointer which is written with the maximum -//! packet size for this endpoint. -//! \param pui32Flags is a pointer which is written with the current endpoint -//! settings. On entry to the function, this pointer must contain either -//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT -//! endpoint is to be queried. -//! -//! This function returns the basic configuration for an endpoint in device -//! mode. The values returned in \e *pui32MaxPacketSize and \e *pui32Flags are -//! equivalent to the \e ui32MaxPacketSize and \e ui32Flags previously passed -//! to USBDevEndpointConfigSet() for this endpoint. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t *pui32MaxPacketSize, uint32_t *pui32Flags) -{ - uint32_t ui32Register; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT(pui32MaxPacketSize && pui32Flags); - ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || - (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || - (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || - (ui32Endpoint == USB_EP_7)); - - // - // Determine if a transmit or receive endpoint is being queried. - // - if(*pui32Flags & USB_EP_DEV_IN) - { - // - // Clear the flags other than the direction bit. - // - *pui32Flags = USB_EP_DEV_IN; - - // - // Get the maximum packet size. - // - *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + - EP_OFFSET(ui32Endpoint) + - USB_O_TXMAXP1); - - // - // Get the current transmit control register value. - // - ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + - USB_O_TXCSRH1); - - // - // Are we allowing auto setting of TxPktRdy when max packet size has - // been loaded into the FIFO? - // - if(ui32Register & USB_TXCSRH1_AUTOSET) - { - *pui32Flags |= USB_EP_AUTO_SET; - } - - // - // Get the DMA mode. - // - if(ui32Register & USB_TXCSRH1_DMAEN) - { - if(ui32Register & USB_TXCSRH1_DMAMOD) - { - *pui32Flags |= USB_EP_DMA_MODE_1; - } - else - { - *pui32Flags |= USB_EP_DMA_MODE_0; - } - } - - // - // Are we in isochronous mode? - // - if(ui32Register & USB_TXCSRH1_ISO) - { - *pui32Flags |= USB_EP_MODE_ISOC; - } - else - { - // - // The hardware doesn't differentiate between bulk, interrupt - // and control mode for the endpoint so we just set something - // that isn't isochronous. This protocol ensures that anyone - // modifying the returned flags in preparation for a call to - // USBDevEndpointConfigSet do not see an unexpected mode change. - // If they decode the returned mode, however, they may be in for - // a surprise. - // - *pui32Flags |= USB_EP_MODE_BULK; - } - } - else - { - // - // Clear the flags other than the direction bit. - // - *pui32Flags = USB_EP_DEV_OUT; - - // - // Get the MaxPacketSize. - // - *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + - EP_OFFSET(ui32Endpoint) + - USB_O_RXMAXP1); - - // - // Get the current receive control register value. - // - ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + - USB_O_RXCSRH1); - - // - // Are we allowing auto clearing of RxPktRdy when packet of size max - // packet has been unloaded from the FIFO? - // - if(ui32Register & USB_RXCSRH1_AUTOCL) - { - *pui32Flags |= USB_EP_AUTO_CLEAR; - } - - // - // Get the DMA mode. - // - if(ui32Register & USB_RXCSRH1_DMAEN) - { - if(ui32Register & USB_RXCSRH1_DMAMOD) - { - *pui32Flags |= USB_EP_DMA_MODE_1; - } - else - { - *pui32Flags |= USB_EP_DMA_MODE_0; - } - } - - // - // Are we in isochronous mode? - // - if(ui32Register & USB_RXCSRH1_ISO) - { - *pui32Flags |= USB_EP_MODE_ISOC; - } - else - { - // - // The hardware doesn't differentiate between bulk, interrupt - // and control mode for the endpoint so we just set something - // that isn't isochronous. This protocol ensures that anyone - // modifying the returned flags in preparation for a call to - // USBDevEndpointConfigSet do not see an unexpected mode change. - // If they decode the returned mode, however, they may be in for - // a surprise. - // - *pui32Flags |= USB_EP_MODE_BULK; - } - } -} - -//***************************************************************************** -// -//! Sets the FIFO configuration for an endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32FIFOAddress is the starting address for the FIFO. -//! \param ui32FIFOSize is the size of the FIFO specified by one of the -//! USB_FIFO_SZ_ values. -//! \param ui32Flags specifies what information to set in the FIFO -//! configuration. -//! -//! This function configures the starting FIFO RAM address and size of the FIFO -//! for a given endpoint. Endpoint zero does not have a dynamically -//! configurable FIFO, so this function must not be called for endpoint zero. -//! The \e ui32FIFOSize parameter must be one of the values in the -//! \b USB_FIFO_SZ_ values. -//! -//! The \e ui32FIFOAddress value must be a multiple of 8 bytes and directly -//! indicates the starting address in the USB controller's FIFO RAM. For -//! example, a value of 64 indicates that the FIFO starts 64 bytes into -//! the USB controller's FIFO memory. The \e ui32Flags value specifies whether -//! the endpoint's OUT or IN FIFO must be configured. If in host mode, use -//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use -//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. -//! -//! \return None. -// -//***************************************************************************** -void -USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || - (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || - (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || - (ui32Endpoint == USB_EP_7)); - - // - // See if the transmit or receive FIFO is being configured. - // - if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) - { - // - // Set the transmit FIFO location and size for this endpoint. - // - _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_TXFIFOSZ, - ui32FIFOSize, 1); - _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_TXFIFOADD, - ui32FIFOAddress >> 3, 2); - } - else - { - // - // Set the receive FIFO location and size for this endpoint. - // - _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_RXFIFOSZ, - ui32FIFOSize, 1); - _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_RXFIFOADD, - ui32FIFOAddress >> 3, 2); - } -} - -//***************************************************************************** -// -//! Returns the FIFO configuration for an endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param pui32FIFOAddress is the starting address for the FIFO. -//! \param pui32FIFOSize is the size of the FIFO as specified by one of the -//! USB_FIFO_SZ_ values. -//! \param ui32Flags specifies what information to retrieve from the FIFO -//! configuration. -//! -//! This function returns the starting address and size of the FIFO for a -//! given endpoint. Endpoint zero does not have a dynamically configurable -//! FIFO, so this function must not be called for endpoint zero. The -//! \e ui32Flags parameter specifies whether the endpoint's OUT or IN FIFO must -//! be read. If in host mode, the \e ui32Flags parameter must be -//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the -//! \e ui32Flags parameter must be either \b USB_EP_DEV_OUT or -//! \b USB_EP_DEV_IN. -//! -//! \return None. -// -//***************************************************************************** -void -USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t *pui32FIFOAddress, uint32_t *pui32FIFOSize, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || - (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || - (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || - (ui32Endpoint == USB_EP_7)); - - // - // See if the transmit or receive FIFO is being configured. - // - if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) - { - // - // Get the transmit FIFO location and size for this endpoint. - // - *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4, - (uint32_t)USB_O_TXFIFOADD, - 2)) << 3; - *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4, - (uint32_t)USB_O_TXFIFOSZ, 1); - } - else - { - // - // Get the receive FIFO location and size for this endpoint. - // - *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4, - (uint32_t)USB_O_RXFIFOADD, - 2)) << 3; - *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4, - (uint32_t)USB_O_RXFIFOSZ, 1); - } -} - -//***************************************************************************** -// -//! Configure the DMA settings for an endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Config specifies the configuration options for an endpoint. -//! -//! This function configures the DMA settings for a given endpoint without -//! changing other options that may already be configured. In order for the -//! DMA transfer to be enabled, the USBEndpointDMAEnable() function must be -//! called before starting the DMA transfer. The configuration -//! options are passed in the \e ui32Config parameter and can have the values -//! described below. -//! -//! One of the following values to specify direction: -//! - \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN - This setting is used with -//! DMA transfers from memory to the USB controller. -//! - \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT - This setting is used with -//! DMA transfers from the USB controller to memory. -//! -//! One of the following values: -//! - \b USB_EP_DMA_MODE_0(default) - This setting is typically used for -//! transfers that do not span multiple packets or when interrupts are -//! required for each packet. -//! - \b USB_EP_DMA_MODE_1 - This setting is typically used for -//! transfers that span multiple packets and do not require interrupts -//! between packets. -//! -//! Values only used with \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN: -//! - \b USB_EP_AUTO_SET - This setting is used to allow transmit DMA transfers -//! to automatically be sent when a full packet is loaded into a FIFO. -//! This is needed with \b USB_EP_DMA_MODE_1 to ensure that packets go -//! out when the FIFO becomes full and the DMA has more data to send. -//! -//! Values only used with \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT: -//! - \b USB_EP_AUTO_CLEAR - This setting is used to allow receive DMA -//! transfers to automatically be acknowledged as they are received. This is -//! needed with \b USB_EP_DMA_MODE_1 to ensure that packets continue to -//! be received and acknowledged when the FIFO is emptied by the DMA -//! transfer. -//! -//! Values only used with \b USB_EP_HOST_IN: -//! - \b USB_EP_AUTO_REQUEST - This setting is used to allow receive DMA -//! transfers to automatically request a new IN transaction when the -//! previous transfer has emptied the FIFO. This is typically used in -//! conjunction with \b USB_EP_AUTO_CLEAR so that receive DMA transfers -//! can continue without interrupting the main processor. -//! -//! \b Example: Set endpoint 1 receive endpoint to automatically acknowledge -//! request and automatically generate a new IN request in host mode. -//! -//! \verbatim -//! // -//! // Configure endpoint 1 for receiving multiple packets using DMA. -//! // -//! USBEndpointDMAConfigSet(USB0_BASE, USB_EP_1, USB_EP_HOST_IN | -//! USB_EP_DMA_MODE_1 | -//! USB_EP_AUTO_CLEAR | -//! USB_EP_AUTO_REQUEST); -//! \endverbatim -//! -//! \b Example: Set endpoint 2 transmit endpoint to automatically send each -//! packet in host mode when spanning multiple packets. -//! -//! \verbatim -//! // -//! // Configure endpoint 1 for transmitting multiple packets using DMA. -//! // -//! USBEndpointDMAConfigSet(USB0_BASE, USB_EP_2, USB_EP_HOST_OUT | -//! USB_EP_DMA_MODE_1 | -//! USB_EP_AUTO_SET); -//! \endverbatim -//! -//! \return None. -// -//***************************************************************************** -void -USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Config) -{ - uint32_t ui32NewConfig; - - if(ui32Config & USB_EP_HOST_OUT) - { - // - // Clear mode and DMA enable. - // - ui32NewConfig = - (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) & - ~(USB_TXCSRH1_DMAMOD | USB_TXCSRH1_AUTOSET)); - - if(ui32Config & USB_EP_DMA_MODE_1) - { - ui32NewConfig |= USB_TXCSRH1_DMAMOD; - } - - if(ui32Config & USB_EP_AUTO_SET) - { - ui32NewConfig |= USB_TXCSRH1_AUTOSET; - } - - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = - ui32NewConfig; - } - else - { - ui32NewConfig = - (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) & - ~(USB_RXCSRH1_AUTORQ | USB_RXCSRH1_AUTOCL | USB_RXCSRH1_DMAMOD)); - - if(ui32Config & USB_EP_DMA_MODE_1) - { - ui32NewConfig |= USB_RXCSRH1_DMAMOD; - } - - if(ui32Config & USB_EP_AUTO_CLEAR) - { - ui32NewConfig |= USB_RXCSRH1_AUTOCL; - } - if(ui32Config & USB_EP_AUTO_REQUEST) - { - ui32NewConfig |= USB_RXCSRH1_AUTORQ; - } - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = - ui32NewConfig; - } -} - -//***************************************************************************** -// -//! Enable DMA on a given endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Flags specifies which direction and what mode to use when -//! enabling DMA. -//! -//! This function enables DMA on a given endpoint and configures the mode -//! according to the values in the \e ui32Flags parameter. The \e ui32Flags -//! parameter must have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. Once this -//! function is called the only DMA or error interrupts are generated by the -//! USB controller. -//! -//! \note If this function is called when an endpoint is configured in DMA -//! mode 0 the USB controller does not generate an interrupt. -//! -//! \return None. -// -//***************************************************************************** -void -USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // See if the transmit DMA is being enabled. - // - if(ui32Flags & USB_EP_DEV_IN) - { - // - // Enable DMA on the transmit endpoint. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) |= - USB_TXCSRH1_DMAEN; - } - else - { - // - // Enable DMA on the receive endpoint. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) |= - USB_RXCSRH1_DMAEN; - } -} - -//***************************************************************************** -// -//! Disable DMA on a given endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Flags specifies which direction to disable. -//! -//! This function disables DMA on a given endpoint to allow non-DMA USB -//! transactions to generate interrupts normally. The \e ui32Flags parameter -//! must be \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored. -//! -//! \return None. -// -//***************************************************************************** -void -USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Flags) -{ - // - // If this was a request to disable DMA on the IN portion of the endpoint - // then handle it. - // - if(ui32Flags & USB_EP_DEV_IN) - { - // - // Just disable DMA leave the mode setting. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) &= - ~USB_TXCSRH1_DMAEN; - } - else - { - // - // Just disable DMA leave the mode setting. - // - HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) &= - ~USB_RXCSRH1_DMAEN; - } -} - -//***************************************************************************** -// -//! Determine the number of bytes of data available in a given endpoint's FIFO. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! -//! This function returns the number of bytes of data currently available in -//! the FIFO for the given receive (OUT) endpoint. It may be used prior to -//! calling USBEndpointDataGet() to determine the size of buffer required to -//! hold the newly-received packet. -//! -//! \return This call returns the number of bytes available in a given endpoint -//! FIFO. -// -//***************************************************************************** -uint32_t -USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint) -{ - uint32_t ui32Register; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Get the address of the receive status register to use, based on the - // endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - ui32Register = USB_O_CSRL0; - } - else - { - ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); - } - - // - // Is there a packet ready in the FIFO? - // - if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) - { - return(0); - } - - // - // Return the byte count in the FIFO. - // - return(HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint)); -} - -//***************************************************************************** -// -//! Retrieves data from the given endpoint's FIFO. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param pui8Data is a pointer to the data area used to return the data from -//! the FIFO. -//! \param pui32Size is initially the size of the buffer passed into this call -//! via the \e pui8Data parameter. It is set to the amount of data returned in -//! the buffer. -//! -//! This function returns the data from the FIFO for the given endpoint. -//! The \e pui32Size parameter indicates the size of the buffer passed in -//! the \e pui32Data parameter. The data in the \e pui32Size parameter is -//! changed to match the amount of data returned in the \e pui8Data parameter. -//! If a zero-byte packet is received, this call does not return an error but -//! instead just returns a zero in the \e pui32Size parameter. The only error -//! case occurs when there is no data packet available. -//! -//! \return This call returns 0, or -1 if no packet was received. -// -//***************************************************************************** -int32_t -USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint8_t *pui8Data, uint32_t *pui32Size) -{ - uint32_t ui32Register, ui32ByteCount, ui32FIFO; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Get the address of the receive status register to use, based on the - // endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - ui32Register = USB_O_CSRL0; - } - else - { - ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); - } - - // - // Don't allow reading of data if the RxPktRdy bit is not set. - // - if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) - { - // - // Can't read the data because none is available. - // - *pui32Size = 0; - - // - // Return a failure since there is no data to read. - // - return(-1); - } - - // - // Get the byte count in the FIFO. - // - ui32ByteCount = HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint); - - // - // Determine how many bytes are copied. - // - ui32ByteCount = (ui32ByteCount < *pui32Size) ? ui32ByteCount : *pui32Size; - - // - // Return the number of bytes we are going to read. - // - *pui32Size = ui32ByteCount; - - // - // Calculate the FIFO address. - // - ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); - - // - // Read the data out of the FIFO. - // - for(; ui32ByteCount > 0; ui32ByteCount--) - { - // - // Read a byte at a time from the FIFO. - // - *pui8Data++ = HWREGB(ui32FIFO); - } - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Acknowledge that data was read from the given endpoint's FIFO in device -//! mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param bIsLastPacket indicates if this packet is the last one. -//! -//! This function acknowledges that the data was read from the endpoint's FIFO. -//! The \e bIsLastPacket parameter is set to a \b true value if this is the -//! last in a series of data packets on endpoint zero. The \e bIsLastPacket -//! parameter is not used for endpoints other than endpoint zero. This call -//! can be used if processing is required between reading the data and -//! acknowledging that the data has been read. -//! -//! \note This function must only be called in device mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, - bool bIsLastPacket) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Determine which endpoint is being acked. - // - if(ui32Endpoint == USB_EP_0) - { - // - // Clear RxPktRdy, and optionally DataEnd, on endpoint zero. - // - HWREGB(ui32Base + USB_O_CSRL0) = - USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0); - } - else - { - // - // Clear RxPktRdy on all other endpoints. - // - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= - ~(USB_RXCSRL1_RXRDY); - } -} - -//***************************************************************************** -// -//! Acknowledge that data was read from the given endpoint's FIFO in host -//! mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! -//! This function acknowledges that the data was read from the endpoint's FIFO. -//! This call is used if processing is required between reading the data and -//! acknowledging that the data has been read. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Clear RxPktRdy. - // - if(ui32Endpoint == USB_EP_0) - { - HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY; - } - else - { - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= - ~(USB_RXCSRL1_RXRDY); - } -} - -//***************************************************************************** -// -//! Puts data into the given endpoint's FIFO. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param pui8Data is a pointer to the data area used as the source for the -//! data to put into the FIFO. -//! \param ui32Size is the amount of data to put into the FIFO. -//! -//! This function puts the data from the \e pui8Data parameter into the FIFO -//! for this endpoint. If a packet is already pending for transmission, then -//! this call does not put any of the data into the FIFO and returns -1. Care -//! must be taken to not write more data than can fit into the FIFO -//! allocated by the call to USBFIFOConfigSet(). -//! -//! \return This call returns 0 on success, or -1 to indicate that the FIFO -//! is in use and cannot be written. -// -//***************************************************************************** -int32_t -USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, - uint8_t *pui8Data, uint32_t ui32Size) -{ - uint32_t ui32FIFO; - uint8_t ui8TxPktRdy; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Get the bit position of TxPktRdy based on the endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - ui8TxPktRdy = USB_CSRL0_TXRDY; - } - else - { - ui8TxPktRdy = USB_TXCSRL1_TXRDY; - } - - // - // Don't allow transmit of data if the TxPktRdy bit is already set. - // - if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & ui8TxPktRdy) - { - return(-1); - } - - // - // Calculate the FIFO address. - // - ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); - - // - // Write the data to the FIFO. - // - for(; ui32Size > 0; ui32Size--) - { - HWREGB(ui32FIFO) = *pui8Data++; - } - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Starts the transfer of data from an endpoint's FIFO. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32TransType is set to indicate what type of data is being sent. -//! -//! This function starts the transfer of data from the FIFO for a given -//! endpoint. This function is called if the \b USB_EP_AUTO_SET bit was -//! not enabled for the endpoint. Setting the \e ui32TransType parameter -//! allows the appropriate signaling on the USB bus for the type of transaction -//! being requested. The \e ui32TransType parameter must be one of the -//! following: -//! -//! - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode. -//! - \b USB_TRANS_IN for IN transaction on any endpoint in device mode. -//! - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a -//! sequence of IN transactions. -//! - \b USB_TRANS_SETUP for setup transactions on endpoint zero. -//! - \b USB_TRANS_STATUS for status results on endpoint zero. -//! -//! \return This call returns 0 on success, or -1 if a transmission is already -//! in progress. -// -//***************************************************************************** -int32_t -USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32TransType) -{ - uint32_t ui32TxPktRdy; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Get the bit position of TxPktRdy based on the endpoint. - // - if(ui32Endpoint == USB_EP_0) - { - // - // Don't allow transmit of data if the TxPktRdy bit is already set. - // - if(HWREGB(ui32Base + USB_O_CSRL0) & USB_CSRL0_TXRDY) - { - return(-1); - } - - ui32TxPktRdy = ui32TransType & 0xff; - } - else - { - // - // Don't allow transmit of data if the TxPktRdy bit is already set. - // - if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & USB_TXCSRL1_TXRDY) - { - return(-1); - } - - ui32TxPktRdy = (ui32TransType >> 8) & 0xff; - } - - // - // Set TxPktRdy in order to send the data. - // - HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) = ui32TxPktRdy; - - // - // Success. - // - return(0); -} - -//***************************************************************************** -// -//! Forces a flush of an endpoint's FIFO. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Flags specifies if the IN or OUT endpoint is accessed. -//! -//! This function forces the USB controller to flush out the data in the FIFO. -//! The function can be called with either host or device controllers and -//! requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT, -//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. -//! -//! \return None. -// -//***************************************************************************** -void -USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Endpoint zero has a different register set for FIFO flushing. - // - if(ui32Endpoint == USB_EP_0) - { - // - // Nothing in the FIFO if neither of these bits are set. - // - if((HWREGB(ui32Base + USB_O_CSRL0) & - (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0) - { - // - // Hit the Flush FIFO bit. - // - HWREGB(ui32Base + USB_O_CSRH0) = USB_CSRH0_FLUSH; - } - } - else - { - // - // Only reset the IN or OUT FIFO. - // - if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) - { - // - // Make sure the FIFO is not empty. - // - if(HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) & - USB_TXCSRL1_TXRDY) - { - // - // Hit the Flush FIFO bit. - // - HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= - USB_TXCSRL1_FLUSH; - } - } - else - { - // - // Make sure that the FIFO is not empty. - // - if(HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) & - USB_RXCSRL1_RXRDY) - { - // - // Hit the Flush FIFO bit. - // - HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= - USB_RXCSRL1_FLUSH; - } - } - } -} - -//***************************************************************************** -// -//! Schedules a request for an IN transaction on an endpoint in host mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! -//! This function schedules a request for an IN transaction. When the USB -//! device being communicated with responds with the data, the data can be -//! retrieved by calling USBEndpointDataGet() or via a DMA transfer. -//! -//! \note This function must only be called in host mode and only for IN -//! endpoints. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint) -{ - uint32_t ui32Register; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Endpoint zero uses a different offset than the other endpoints. - // - if(ui32Endpoint == USB_EP_0) - { - ui32Register = USB_O_CSRL0; - } - else - { - ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); - } - - // - // Set the request for an IN transaction. - // - HWREGB(ui32Base + ui32Register) = USB_RXCSRL1_REQPKT; -} - -//***************************************************************************** -// -//! Clears a scheduled IN transaction for an endpoint in host mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! -//! This function clears a previously scheduled IN transaction if it is still -//! pending. This function is used to safely disable any scheduled IN -//! transactions if the endpoint specified by \e ui32Endpoint is reconfigured -//! for communications with other devices. -//! -//! \note This function must only be called in host mode and only for IN -//! endpoints. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint) -{ - uint32_t ui32Register; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // Endpoint zero uses a different offset than the other endpoints. - // - if(ui32Endpoint == USB_EP_0) - { - ui32Register = USB_O_CSRL0; - } - else - { - ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); - } - - // - // Clear the request for an IN transaction. - // - HWREGB(ui32Base + ui32Register) &= ~USB_RXCSRL1_REQPKT; -} - -//***************************************************************************** -// -//! Issues a request for a status IN transaction on endpoint zero. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function is used to cause a request for a status IN transaction from -//! a device on endpoint zero. This function can only be used with endpoint -//! zero as that is the only control endpoint that supports this ability. This -//! function is used to complete the last phase of a control transaction to a -//! device and an interrupt is signaled when the status packet has been -//! received. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostRequestStatus(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Set the request for a status IN transaction. - // - HWREGB(ui32Base + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS; -} - -//***************************************************************************** -// -//! Sets the functional address for the device that is connected to an -//! endpoint in host mode. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Addr is the functional address for the controller to use for -//! this endpoint. -//! \param ui32Flags determines if this is an IN or an OUT endpoint. -//! -//! This function configures the functional address for a device that is using -//! this endpoint for communication. This \e ui32Addr parameter is the address -//! of the target device that this endpoint is communicating with. The -//! \e ui32Flags parameter indicates if the IN or OUT endpoint is set. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // See if the transmit or receive address is set. - // - if(ui32Flags & USB_EP_HOST_OUT) - { - // - // Set the transmit address. - // - HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1)) = ui32Addr; - } - else - { - // - // Set the receive address. - // - HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4 + (ui32Endpoint >> 1)) = - ui32Addr; - } -} - -//***************************************************************************** -// -//! Gets the current functional device address for an endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Flags determines if this is an IN or an OUT endpoint. -//! -//! This function returns the current functional address that an endpoint is -//! using to communicate with a device. The \e ui32Flags parameter determines -//! if the IN or OUT endpoint's device address is returned. -//! -//! \note This function must only be called in host mode. -//! -//! \return Returns the current function address being used by an endpoint. -// -//***************************************************************************** -uint32_t -USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // See if the transmit or receive address is returned. - // - if(ui32Flags & USB_EP_HOST_OUT) - { - // - // Return this endpoint's transmit address. - // - return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1))); - } - else - { - // - // Return this endpoint's receive address. - // - return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4 + (ui32Endpoint >> 1))); - } -} - -//***************************************************************************** -// -//! Sets the hub address for the device that is connected to an endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Addr is the hub address and port for the device using this -//! endpoint. The hub address must be defined in bits 0 through 6 with the -//! port number in bits 8 through 14. -//! \param ui32Flags determines if this is an IN or an OUT endpoint. -//! -//! This function configures the hub address for a device that is using this -//! endpoint for communication. The \e ui32Flags parameter determines if the -//! device address for the IN or the OUT endpoint is configured by this call -//! and sets the speed of the downstream device. Valid values are one of -//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with -//! \b USB_EP_SPEED_LOW. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, - uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // See if the hub transmit or receive address is being set. - // - if(ui32Flags & USB_EP_HOST_OUT) - { - // - // Set the hub transmit address and port number for this endpoint. - // - HWREGH(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1)) = ui32Addr; - } - else - { - // - // Set the hub receive address and port number for this endpoint. - // - HWREGH(ui32Base + USB_O_TXHUBADDR0 + 4 + (ui32Endpoint >> 1)) = - ui32Addr; - } - - // - // Set the speed of communication for endpoint 0. This configuration is - // done here because it changes on a transaction-by-transaction basis for - // EP0. For other endpoints, this is set in USBHostEndpointConfig(). - // - if(ui32Endpoint == USB_EP_0) - { - if(ui32Flags & USB_EP_SPEED_FULL) - { - HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL; - } - else - { - HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW; - } - } -} - -//***************************************************************************** -// -//! Gets the current device hub address for this endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint to access. -//! \param ui32Flags determines if this is an IN or an OUT endpoint. -//! -//! This function returns the current hub address that an endpoint is using -//! to communicate with a device. The \e ui32Flags parameter determines if the -//! device address for the IN or OUT endpoint is returned. -//! -//! \note This function must only be called in host mode. -//! -//! \return This function returns the current hub address being used by an -//! endpoint. -// -//***************************************************************************** -uint32_t -USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || - (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || - (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || - (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); - - // - // See if the hub transmit or receive address is returned. - // - if(ui32Flags & USB_EP_HOST_OUT) - { - // - // Return the hub transmit address for this endpoint. - // - return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1))); - } - else - { - // - // Return the hub receive address for this endpoint. - // - return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + 4 + (ui32Endpoint >> 1))); - } -} - -//***************************************************************************** -// -//! Sets the configuration for USB power fault. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Flags specifies the configuration of the power fault. -//! -//! This function controls how the USB controller uses its external power -//! control pins (USBnPFLT and USBnEPEN). The flags specify the power -//! fault level sensitivity, the power fault action, and the power enable level -//! and source. -//! -//! One of the following can be selected as the power fault level sensitivity: -//! -//! - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin -//! being driven low. -//! - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin -//! being driven high. -//! -//! One of the following can be selected as the power fault action: -//! -//! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault -//! detected. -//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a -//! power fault. -//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a -//! power fault. -//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a -//! power fault. -//! -//! One of the following can be selected as the power enable level and source: -//! -//! - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller -//! when USBHostPwrEnable() is called. -//! - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB -//! controller when USBHostPwrEnable() is -//! called. -//! - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller -//! automatically if USBOTGSessionRequest() has -//! enabled a session. -//! - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB -//! controller automatically if -//! USBOTGSessionRequest() has enabled a -//! session. -//! -//! On devices that support the VBUS glitch filter, the -//! \b USB_HOST_PWREN_FILTER can be added to ignore small, short drops in VBUS -//! level caused by high power consumption. This feature is mainly used to -//! avoid causing VBUS errors caused by devices with high in-rush current. -//! -//! \note This function must only be called on microcontrollers that support -//! host mode or OTG operation. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Flags & ~(USB_HOST_PWREN_FILTER | USB_EPC_PFLTACT_M | - USB_EPC_PFLTAEN | USB_EPC_PFLTSEN_HIGH | - USB_EPC_EPEN_M)) == 0); - - // - // If requested, enable VBUS droop detection on parts that support this - // feature. - // - HWREG(ui32Base + USB_O_VDC) = ui32Flags >> 16; - - // - // Set the power fault configuration as specified. This configuration - // does not change whether fault detection is enabled or not. - // - HWREGH(ui32Base + USB_O_EPC) = - (ui32Flags | (HWREGH(ui32Base + USB_O_EPC) & - ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN | - USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M))); -} - -//***************************************************************************** -// -//! Enables power fault detection. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function enables power fault detection in the USB controller. If the -//! USBnPFLT pin is not in use, this function must not be used. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostPwrFaultEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Enable power fault input. - // - HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_PFLTEN; -} - -//***************************************************************************** -// -//! Disables power fault detection. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function disables power fault detection in the USB controller. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostPwrFaultDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Enable power fault input. - // - HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_PFLTEN; -} - -//***************************************************************************** -// -//! Enables the external power pin. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function enables the USBnEPEN signal, which enables an external power -//! supply in host mode operation. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostPwrEnable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Enable the external power supply enable signal. - // - HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_EPENDE; -} - -//***************************************************************************** -// -//! Disables the external power pin. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function disables the USBnEPEN signal, which disables an external -//! power supply in host mode operation. -//! -//! \note This function must only be called in host mode. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostPwrDisable(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Disable the external power supply enable signal. - // - HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_EPENDE; -} - -//***************************************************************************** -// -//! Get the current frame number. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the last frame number received. -//! -//! \return The last frame number received. -// -//***************************************************************************** -uint32_t -USBFrameNumberGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Return the most recent frame number. - // - return(HWREGH(ui32Base + USB_O_FRAME)); -} - -//***************************************************************************** -// -//! Starts or ends a session. -//! -//! \param ui32Base specifies the USB module base address. -//! \param bStart specifies if this call starts or ends a session. -//! -//! This function is used in OTG mode to start a session request or end a -//! session. If the \e bStart parameter is set to \b true, then this function -//! starts a session and if it is \b false it ends a session. -//! -//! \return None. -// -//***************************************************************************** -void -USBOTGSessionRequest(uint32_t ui32Base, bool bStart) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Start or end the session as directed. - // - if(bStart) - { - HWREGB(ui32Base + USB_O_DEVCTL) |= USB_DEVCTL_SESSION; - } - else - { - HWREGB(ui32Base + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION; - } -} - -//***************************************************************************** -// -//! Returns the absolute FIFO address for a given endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint specifies which endpoint's FIFO address to return. -//! -//! This function returns the actual physical address of the FIFO. This -//! address is needed when the USB is going to be used with the uDMA -//! controller and the source or destination address must be set to the -//! physical FIFO address for a given endpoint. -//! -//! \return None. -// -//***************************************************************************** -uint32_t -USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint) -{ - // - // Return the FIFO address for this endpoint. - // - return(ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2)); -} - -//***************************************************************************** -// -//! Returns the current operating mode of the controller. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the current operating mode on USB controllers with -//! OTG or Dual mode functionality. -//! -//! For OTG controllers: -//! -//! The function returns one of the following values on OTG controllers: -//! \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, -//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, -//! \b USB_OTG_MODE_NONE. -//! -//! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode -//! on the A-side of the cable. -//! -//! \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode -//! on the A-side of the cable. -//! -//! \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode -//! on the B-side of the cable. -//! -//! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode -//! on the B-side of the cable. If an OTG session request is started with no -//! cable in place, this mode is the default. -//! -//! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to -//! determine its role in the system. -//! -//! For Dual Mode controllers: -//! -//! The function returns one of the following values: -//! \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or -//! \b USB_DUAL_MODE_NONE. -//! -//! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host. -//! -//! \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device. -//! -//! \b USB_DUAL_MODE_NONE indicates that the controller is not active as -//! either a host or device. -//! -//! \return Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, -//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, -//! \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or -//! \b USB_DUAL_MODE_NONE. -// -//***************************************************************************** -uint32_t -USBModeGet(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Checks the current mode in the USB_O_DEVCTL and returns the current - // mode. - // - // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION - // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION - // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION | - // USB_DEVCTL_HOST - // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION - // USB_OTG_MODE_NONE: USB_DEVCTL_DEV - // - return(HWREGB(ui32Base + USB_O_DEVCTL) & - (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION | - USB_DEVCTL_VBUS_M)); -} - -//***************************************************************************** -// -//! Sets the DMA channel to use for a given endpoint. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint specifies which endpoint's FIFO address to return. -//! \param ui32Channel specifies which DMA channel to use for which endpoint. -//! -//! This function is used to configure which DMA channel to use with a given -//! endpoint. Receive DMA channels can only be used with receive endpoints -//! and transmit DMA channels can only be used with transmit endpoints. As a -//! result, the 3 receive and 3 transmit DMA channels can be mapped to any -//! endpoint other than 0. The values that are passed into the -//! \e ui32Channel value are the UDMA_CHANNEL_USBEP* values defined in udma.h. -//! -//! \note This function only has an effect on microcontrollers that have the -//! ability to change the DMA channel for an endpoint. Calling this function -//! on other devices has no effect. -//! -//! \return None. -//! -//***************************************************************************** -void -USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Channel) -{ - uint32_t ui32Mask; - - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || - (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || - (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || - (ui32Endpoint == USB_EP_7)); -// ASSERT(ui32Channel <= UDMA_CHANNEL_USBEP3TX); - - // - // The input select mask must be shifted into the correct position - // based on the channel. - // - ui32Mask = (uint32_t)0xf << (ui32Channel * 4); - - // - // Clear out the current selection for the channel. - // - ui32Mask = HWREG(ui32Base + USB_O_DMASEL) & (~ui32Mask); - - // - // The input select is now shifted into the correct position based on the - // channel. - // - ui32Mask |= ((uint32_t)USBEPToIndex(ui32Endpoint)) << (ui32Channel * 4); - - // - // Write the value out to the register. - // - HWREG(ui32Base + USB_O_DMASEL) = ui32Mask; -} - -//***************************************************************************** -// -//! Change the mode of the USB controller to host. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function changes the mode of the USB controller to host mode. -//! -//! \note This function must only be called on microcontrollers that support -//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. -//! -//! \return None. -// -//***************************************************************************** -void -USBHostMode(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Force mode in OTG parts that support forcing USB controller mode. - // This bit is not writable in USB controllers that do not support - // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a - // force of host mode. - // - HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG; -} - -//***************************************************************************** -// -//! Change the mode of the USB controller to device. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function changes the mode of the USB controller to device mode. -//! -//! \note This function must only be called on microcontrollers that support -//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. -//! -//! \return None. -// -//***************************************************************************** -void -USBDevMode(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Set the USB controller mode to device. - // - HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD; -} - -//***************************************************************************** -// -//! Change the mode of the USB controller to OTG. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function changes the mode of the USB controller to OTG mode. This -//! function is only valid on microcontrollers that have the OTG capabilities. -//! -//! \return None. -// -//***************************************************************************** -void -USBOTGMode(uint32_t ui32Base) -{ - // - // Check the arguments. - // - ASSERT(ui32Base == USB0_BASE); - - // - // Disable the override of the USB controller mode when running on an OTG - // device. - // - HWREGB(ui32Base + USB_O_GPCS) = 0; -} - -//***************************************************************************** -// -//! Powers off the USB PHY. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function powers off the USB PHY, reducing the current consuption -//! of the device. While in the powered-off state, the USB controller is -//! unable to operate. -//! -//! \return None. -// -//***************************************************************************** -void -USBPHYPowerOff(uint32_t ui32Base) -{ - // - // Set the PWRDNPHY bit in the PHY, putting it into its low power mode. - // - HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_PWRDNPHY; -} - -//***************************************************************************** -// -//! Powers on the USB PHY. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function powers on the USB PHY, enabling it return to normal -//! operation. By default, the PHY is powered on, so this function must -//! only be called if USBPHYPowerOff() has previously been called. -//! -//! \return None. -// -//***************************************************************************** -void -USBPHYPowerOn(uint32_t ui32Base) -{ - // - // Clear the PWRDNPHY bit in the PHY, putting it into normal operating - // mode. - // - HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_PWRDNPHY; -} - -//***************************************************************************** -// -//! Sets the number of packets to request when transferring multiple bulk -//! packets. -//! -//! \param ui32Base specifies the USB module base address. -//! \param ui32Endpoint is the endpoint index to target for this write. -//! \param ui32Count is the number of packets to request. -//! -//! This function sets the number of consecutive bulk packets to request -//! when transferring multiple bulk packets with DMA. -//! -//! \note This feature is not available on all Tiva devices. Please -//! check the data sheet to determine if the USB controller has a DMA -//! controller or if it must use the uDMA controller for DMA transfers. -//! -//! \return None. -// -//***************************************************************************** -void -USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, - uint32_t ui32Count) -{ - HWREG(ui32Base + USB_O_RQPKTCOUNT1 + - (0x4 * (USBEPToIndex(ui32Endpoint) - 1))) = ui32Count; -} - -//***************************************************************************** -// -//! Returns the number of USB endpoint pairs on the device. -//! -//! \param ui32Base specifies the USB module base address. -//! -//! This function returns the number of endpoint pairs supported by the USB -//! controller corresponding to the passed base address. The value returned is -//! the number of IN or OUT endpoints available and does not include endpoint 0 -//! (the control endpoint). For example, if 15 is returned, there are 15 IN -//! and 15 OUT endpoints available in addition to endpoint 0. -//! -//! \return Returns the number of IN or OUT endpoints available. -// -//***************************************************************************** -uint32_t -USBNumEndpointsGet(uint32_t ui32Base) -{ - // - // Read the number of endpoints from the hardware. The number of TX and - // RX endpoints are always the same. - // - return(15); -} - diff --git a/bsp/c28x/libraries/tms320f28379d/common/source/usb_hal.c b/bsp/c28x/libraries/tms320f28379d/common/source/usb_hal.c deleted file mode 100644 index f73ff48a86..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/common/source/usb_hal.c +++ /dev/null @@ -1,163 +0,0 @@ -//########################################################################### -// -// FILE: usb_hal.c -// -// TITLE: Wrapper for interrupt functions and USB support pins. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#include "F2837xD_device.h" -#include "F2837xD_Examples.h" -#include "inc/hw_types.h" -#include "inc/hw_memmap.h" -#include "inc/hw_usb.h" -#include "usb_hal.h" -#include "usb.h" -#include "include/usblib.h" -#include "include/usblibpriv.h" -#include "include/device/usbdevice.h" -#include "include/host/usbhost.h" -#include "include/host/usbhostpriv.h" -#include "include/usblibpriv.h" - -//***************************************************************************** -// -//! \addtogroup c2000_specific -//! @{ -// -//***************************************************************************** - -//***************************************************************************** -// -//! Enables USB related GPIOs to perform their USB function. -// -//***************************************************************************** -void USBGPIOEnable(void) -{ - EALLOW; - GpioCtrlRegs.GPBLOCK.all = 0x00000000; - GpioCtrlRegs.GPBAMSEL.bit.GPIO42 = 1; - GpioCtrlRegs.GPBAMSEL.bit.GPIO43 = 1; - - //VBUS - GpioCtrlRegs.GPBDIR.bit.GPIO46 = 0; - //ID - GpioCtrlRegs.GPBDIR.bit.GPIO47 = 0; - - GpioCtrlRegs.GPDGMUX2.bit.GPIO120 = 3; - GpioCtrlRegs.GPDMUX2.bit.GPIO120 = 3; - GpioCtrlRegs.GPDGMUX2.bit.GPIO121 = 3; - GpioCtrlRegs.GPDMUX2.bit.GPIO121 = 3; - EDIS; -} - -//***************************************************************************** -// -//! Disables USB related GPIOs from performing their USB function. -// -//***************************************************************************** -void USBGPIODisable(void) -{ - EALLOW; - GpioCtrlRegs.GPBLOCK.all = 0x00000000; - GpioCtrlRegs.GPBAMSEL.bit.GPIO42 = 0; - GpioCtrlRegs.GPBAMSEL.bit.GPIO43 = 0; - - GpioCtrlRegs.GPDGMUX2.bit.GPIO120 = 0; - GpioCtrlRegs.GPDMUX2.bit.GPIO120 = 0; - GpioCtrlRegs.GPDGMUX2.bit.GPIO121 = 0; - GpioCtrlRegs.GPDMUX2.bit.GPIO121 = 0; - EDIS; -} - - -//***************************************************************************** -// -//! Wrapper function to implement mS based delay for USB functions -// -//***************************************************************************** -void USBDelay(uint32_t ui32Delay) -{ - DELAY_US(ui32Delay*1000); -} - -//***************************************************************************** -// -//! Device interrupt service routine wrapper to make ISR compatible with -//! C2000 PIE controller. -// -//***************************************************************************** - -__interrupt void -f28x_USB0DeviceIntHandler(void) -{ - USB0DeviceIntHandler(); - PieCtrlRegs.PIEACK.all |= 0x0100; -} -//***************************************************************************** -// -//! Host interrupt service routine wrapper to make ISR compatible with -//! C2000 PIE controller. -// -//***************************************************************************** -__interrupt void -f28x_USB0HostIntHandler(void) -{ - USB0HostIntHandler(); - PieCtrlRegs.PIEACK.all |= 0x0100; -} - -//***************************************************************************** -// -//! Dual mode interrupt service routine wrapper to make ISR compatible with -//! C2000 PIE controller. -// -//***************************************************************************** -__interrupt void -f28x_USB0DualModeIntHandler(void) -{ - USB0DualModeIntHandler(); - PieCtrlRegs.PIEACK.all |= 0x0100; -} - -//***************************************************************************** -// -// Close the c2000_specific Doxygen group. -//! @} -// -//***************************************************************************** - diff --git a/bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd b/bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd deleted file mode 100644 index 2f91325867..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd +++ /dev/null @@ -1,287 +0,0 @@ - -MEMORY -{ - PAGE 0: /* Program Memory */ - - PAGE 1: /* Data Memory */ - - ADCA_RESULT : origin = 0x000B00, length = 0x000020 - ADCB_RESULT : origin = 0x000B20, length = 0x000020 - ADCC_RESULT : origin = 0x000B40, length = 0x000020 - ADCD_RESULT : origin = 0x000B60, length = 0x000020 - - ADCA : origin = 0x007400, length = 0x000080 - ADCB : origin = 0x007480, length = 0x000080 - ADCC : origin = 0x007500, length = 0x000080 - ADCD : origin = 0x007580, length = 0x000080 - - ANALOG_SUBSYS : origin = 0x05D180, length = 0x000080 - - CANA : origin = 0x048000, length = 0x000800 - CANB : origin = 0x04A000, length = 0x000800 - - CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */ - - CLB_XBAR : origin = 0x007A40, length = 0x000040 - - CMPSS1 : origin = 0x005C80, length = 0x000020 - CMPSS2 : origin = 0x005CA0, length = 0x000020 - CMPSS3 : origin = 0x005CC0, length = 0x000020 - CMPSS4 : origin = 0x005CE0, length = 0x000020 - CMPSS5 : origin = 0x005D00, length = 0x000020 - CMPSS6 : origin = 0x005D20, length = 0x000020 - CMPSS7 : origin = 0x005D40, length = 0x000020 - CMPSS8 : origin = 0x005D60, length = 0x000020 - - CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ - CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ - CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ - - DACA : origin = 0x005C00, length = 0x000010 - DACB : origin = 0x005C10, length = 0x000010 - DACC : origin = 0x005C20, length = 0x000010 - - DMA : origin = 0x001000, length = 0x000200 - DMACLASRCSEL : origin = 0x007980, length = 0x000040 - - ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */ - ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */ - ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */ - ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */ - ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */ - ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */ - - EMIF1 : origin = 0x047000, length = 0x000800 - EMIF2 : origin = 0x047800, length = 0x000800 - - EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ - EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ - EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */ - - EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ - EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ - EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ - EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ - EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ - EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ - EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ - EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ - EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */ - EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */ - EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */ - EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */ - - EPWM_XBAR : origin = 0x007A00, length = 0x000040 - - FLASH0_CTRL : origin = 0x05F800, length = 0x000300 - FLASH0_ECC : origin = 0x05FB00, length = 0x000040 - - GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */ - GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */ - - OUTPUT_XBAR : origin = 0x007A80, length = 0x000040 - I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ - I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */ - - IPC : origin = 0x050000, length = 0x000024 - - FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002 - - ROMPREFETCH : origin = 0x05E608, length = 0x000002 - - MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ - EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */ - EMIF2CONFIG : origin = 0x05F4A0, length = 0x000020 /* Emif-2 Config registers */ - ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ - MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ - ROMWAITSTATE : origin = 0x05F540, length = 0x000002 /* ROM Config registers */ - - - MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */ - MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */ - - NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ - - PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ - PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ - SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ - SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ - SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */ - SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */ - - SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ - SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */ - - SPIA : origin = 0x006100, length = 0x000010 - SPIB : origin = 0x006110, length = 0x000010 - SPIC : origin = 0x006120, length = 0x000010 - SPID : origin = 0x006130, length = 0x000010 - - UPP : origin = 0x006200, length = 0x000100 /* uPP registers */ - - DEV_CFG : origin = 0x05D000, length = 0x000180 - CLK_CFG : origin = 0x05D200, length = 0x000100 - CPU_SYS : origin = 0x05D300, length = 0x000100 - - INPUT_XBAR : origin = 0x007900, length = 0x000020 - XBAR : origin = 0x007920, length = 0x000020 - SYNC_SOC : origin = 0x007940, length = 0x000010 - WD : origin = 0x007000, length = 0x000040 - - XINT : origin = 0x007070, length = 0x000010 - - DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */ - DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */ - DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ - -} - - -SECTIONS -{ -/*** PIE Vect Table and Boot ROM Variables Structures ***/ - UNION run = PIE_VECT, PAGE = 1 - { - PieVectTableFile : TYPE=DSECT - GROUP - { - EmuBModeVar : TYPE=DSECT - EmuBootPinsVar : TYPE=DSECT - } - } - - AdcaResultFile : > ADCA_RESULT, PAGE = 1 - AdcbResultFile : > ADCB_RESULT, PAGE = 1 - AdccResultFile : > ADCC_RESULT, PAGE = 1 - AdcdResultFile : > ADCD_RESULT, PAGE = 1 - - AdcaRegsFile : > ADCA, PAGE = 1 - AdcbRegsFile : > ADCB, PAGE = 1 - AdccRegsFile : > ADCC, PAGE = 1 - AdcdRegsFile : > ADCD, PAGE = 1 - - AnalogSubsysRegsFile : > ANALOG_SUBSYS, PAGE = 1 - - CanaRegsFile : > CANA, PAGE = 1 - CanbRegsFile : > CANB, PAGE = 1 - - Cla1RegsFile : > CLA1, PAGE = 1 - Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT - - ClbXbarRegsFile : > CLB_XBAR PAGE = 1 - - Cmpss1RegsFile : > CMPSS1, PAGE = 1 - Cmpss2RegsFile : > CMPSS2, PAGE = 1 - Cmpss3RegsFile : > CMPSS3, PAGE = 1 - Cmpss4RegsFile : > CMPSS4, PAGE = 1 - Cmpss5RegsFile : > CMPSS5, PAGE = 1 - Cmpss6RegsFile : > CMPSS6, PAGE = 1 - Cmpss7RegsFile : > CMPSS7, PAGE = 1 - Cmpss8RegsFile : > CMPSS8, PAGE = 1 - - CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 - CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 - CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 - - DacaRegsFile : > DACA PAGE = 1 - DacbRegsFile : > DACB PAGE = 1 - DaccRegsFile : > DACC PAGE = 1 - - DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1 - DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1 - DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 - - DmaRegsFile : > DMA PAGE = 1 - DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 - - ECap1RegsFile : > ECAP1, PAGE = 1 - ECap2RegsFile : > ECAP2, PAGE = 1 - ECap3RegsFile : > ECAP3, PAGE = 1 - ECap4RegsFile : > ECAP4, PAGE = 1 - ECap5RegsFile : > ECAP5, PAGE = 1 - ECap6RegsFile : > ECAP6, PAGE = 1 - - Emif1RegsFile : > EMIF1 PAGE = 1 - Emif2RegsFile : > EMIF2 PAGE = 1 - - EPwm1RegsFile : > EPWM1, PAGE = 1 - EPwm2RegsFile : > EPWM2, PAGE = 1 - EPwm3RegsFile : > EPWM3, PAGE = 1 - EPwm4RegsFile : > EPWM4, PAGE = 1 - EPwm5RegsFile : > EPWM5, PAGE = 1 - EPwm6RegsFile : > EPWM6, PAGE = 1 - EPwm7RegsFile : > EPWM7, PAGE = 1 - EPwm8RegsFile : > EPWM8, PAGE = 1 - EPwm9RegsFile : > EPWM9, PAGE = 1 - EPwm10RegsFile : > EPWM10, PAGE = 1 - EPwm11RegsFile : > EPWM11, PAGE = 1 - EPwm12RegsFile : > EPWM12, PAGE = 1 - - EPwmXbarRegsFile : > EPWM_XBAR PAGE = 1 - - EQep1RegsFile : > EQEP1, PAGE = 1 - EQep2RegsFile : > EQEP2, PAGE = 1 - EQep3RegsFile : > EQEP3, PAGE = 1 - - Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 - Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 - - GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 - GpioDataRegsFile : > GPIODAT, PAGE = 1 - - OutputXbarRegsFile : > OUTPUT_XBAR PAGE = 1 - I2caRegsFile : > I2CA, PAGE = 1 - I2cbRegsFile : > I2CB, PAGE = 1 - InputXbarRegsFile : > INPUT_XBAR PAGE = 1 - XbarRegsFile : > XBAR PAGE = 1 - IpcRegsFile : > IPC, PAGE = 1 - - FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1 - - RomPrefetchRegsFile : > ROMPREFETCH, PAGE = 1 - MemCfgRegsFile : > MEMCFG, PAGE = 1 - Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1 - Emif2ConfigRegsFile : > EMIF2CONFIG, PAGE = 1 - AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 - MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 - RomWaitStateRegsFile : > ROMWAITSTATE, PAGE = 1 - - McbspaRegsFile : > MCBSPA, PAGE = 1 - McbspbRegsFile : > MCBSPB, PAGE = 1 - - UppRegsFile : > UPP, PAGE = 1 - - NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 - PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 - - SciaRegsFile : > SCIA, PAGE = 1 - ScibRegsFile : > SCIB, PAGE = 1 - ScicRegsFile : > SCIC, PAGE = 1 - ScidRegsFile : > SCID, PAGE = 1 - - Sdfm1RegsFile : > SDFM1, PAGE = 1 - Sdfm2RegsFile : > SDFM2, PAGE = 1 - - SpiaRegsFile : > SPIA, PAGE = 1 - SpibRegsFile : > SPIB, PAGE = 1 - SpicRegsFile : > SPIC, PAGE = 1 - SpidRegsFile : > SPID, PAGE = 1 - - DevCfgRegsFile : > DEV_CFG, PAGE = 1 - ClkCfgRegsFile : > CLK_CFG, PAGE = 1 - CpuSysRegsFile : > CPU_SYS, PAGE = 1 - - SyncSocRegsFile : > SYNC_SOC, PAGE = 1 - - WdRegsFile : > WD, PAGE = 1 - - XintRegsFile : > XINT PAGE = 1 - MemCfgRegs : > MEMCFG PAGE = 1 - -} - -/* -//=========================================================================== -// End of file. -//=========================================================================== -*/ diff --git a/bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd b/bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd deleted file mode 100644 index 189250ad3b..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd +++ /dev/null @@ -1,255 +0,0 @@ - -MEMORY -{ - PAGE 0: /* Program Memory */ - - PAGE 1: /* Data Memory */ - - ADCA_RESULT : origin = 0x000B00, length = 0x000020 - ADCB_RESULT : origin = 0x000B20, length = 0x000020 - ADCC_RESULT : origin = 0x000B40, length = 0x000020 - ADCD_RESULT : origin = 0x000B60, length = 0x000020 - - ADCA : origin = 0x007400, length = 0x000080 - ADCB : origin = 0x007480, length = 0x000080 - ADCC : origin = 0x007500, length = 0x000080 - ADCD : origin = 0x007580, length = 0x000080 - - CANA : origin = 0x048000, length = 0x000800 - CANB : origin = 0x04A000, length = 0x000800 - - CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */ - - CMPSS1 : origin = 0x005C80, length = 0x000020 - CMPSS2 : origin = 0x005CA0, length = 0x000020 - CMPSS3 : origin = 0x005CC0, length = 0x000020 - CMPSS4 : origin = 0x005CE0, length = 0x000020 - CMPSS5 : origin = 0x005D00, length = 0x000020 - CMPSS6 : origin = 0x005D20, length = 0x000020 - CMPSS7 : origin = 0x005D40, length = 0x000020 - CMPSS8 : origin = 0x005D60, length = 0x000020 - - CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ - CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ - CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ - - DACA : origin = 0x005C00, length = 0x000010 - DACB : origin = 0x005C10, length = 0x000010 - DACC : origin = 0x005C20, length = 0x000010 - - DMA : origin = 0x001000, length = 0x000200 - DMACLASRCSEL : origin = 0x007980, length = 0x000040 - - ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */ - ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */ - ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */ - ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */ - ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */ - ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */ - - EMIF1 : origin = 0x047000, length = 0x000800 - EMIF2 : origin = 0x047800, length = 0x000800 - - EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ - EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ - EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */ - - EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ - EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ - EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ - EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ - EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ - EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ - EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ - EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ - EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */ - EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */ - EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */ - EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */ - - FLASH0_CTRL : origin = 0x05F800, length = 0x000300 - FLASH0_ECC : origin = 0x05FB00, length = 0x000040 - - GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */ - GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */ - I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ - I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */ - - IPC : origin = 0x050000, length = 0x000024 - - FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002 - - MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ - EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */ - ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ - MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ - - - MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */ - MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */ - - NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ - - PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ - PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ - - SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ - SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ - SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */ - SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */ - - SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ - SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */ - - SPIA : origin = 0x006100, length = 0x000010 - SPIB : origin = 0x006110, length = 0x000010 - SPIC : origin = 0x006120, length = 0x000010 - SPID : origin = 0x006130, length = 0x000010 - - DEV_CFG : origin = 0x05D000, length = 0x000200 - CLK_CFG : origin = 0x05D200, length = 0x000100 - CPU_SYS : origin = 0x05D300, length = 0x000100 - - WD : origin = 0x007000, length = 0x000040 - - XINT : origin = 0x007070, length = 0x000010 - - DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */ - DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */ - DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ - -} - - -SECTIONS -{ -/*** PIE Vect Table and Boot ROM Variables Structures ***/ - UNION run = PIE_VECT, PAGE = 1 - { - PieVectTableFile : TYPE=DSECT - GROUP - { - EmuBModeVar : TYPE=DSECT - } - } - - AdcaResultFile : > ADCA_RESULT, PAGE = 1 - AdcbResultFile : > ADCB_RESULT, PAGE = 1 - AdccResultFile : > ADCC_RESULT, PAGE = 1 - AdcdResultFile : > ADCD_RESULT, PAGE = 1 - - AdcaRegsFile : > ADCA, PAGE = 1 - AdcbRegsFile : > ADCB, PAGE = 1 - AdccRegsFile : > ADCC, PAGE = 1 - AdcdRegsFile : > ADCD, PAGE = 1 - - CanaRegsFile : > CANA, PAGE = 1 - CanbRegsFile : > CANB, PAGE = 1 - - Cla1RegsFile : > CLA1, PAGE = 1 - Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT - - Cmpss1RegsFile : > CMPSS1, PAGE = 1 - Cmpss2RegsFile : > CMPSS2, PAGE = 1 - Cmpss3RegsFile : > CMPSS3, PAGE = 1 - Cmpss4RegsFile : > CMPSS4, PAGE = 1 - Cmpss5RegsFile : > CMPSS5, PAGE = 1 - Cmpss6RegsFile : > CMPSS6, PAGE = 1 - Cmpss7RegsFile : > CMPSS7, PAGE = 1 - Cmpss8RegsFile : > CMPSS8, PAGE = 1 - - CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 - CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 - CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 - - DacaRegsFile : > DACA PAGE = 1 - DacbRegsFile : > DACB PAGE = 1 - DaccRegsFile : > DACC PAGE = 1 - - DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1 - DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1 - DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 - - DmaRegsFile : > DMA PAGE = 1 - DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 - - ECap1RegsFile : > ECAP1, PAGE = 1 - ECap2RegsFile : > ECAP2, PAGE = 1 - ECap3RegsFile : > ECAP3, PAGE = 1 - ECap4RegsFile : > ECAP4, PAGE = 1 - ECap5RegsFile : > ECAP5, PAGE = 1 - ECap6RegsFile : > ECAP6, PAGE = 1 - - Emif1RegsFile : > EMIF1 PAGE = 1 - Emif2RegsFile : > EMIF2 PAGE = 1 - - EPwm1RegsFile : > EPWM1, PAGE = 1 - EPwm2RegsFile : > EPWM2, PAGE = 1 - EPwm3RegsFile : > EPWM3, PAGE = 1 - EPwm4RegsFile : > EPWM4, PAGE = 1 - EPwm5RegsFile : > EPWM5, PAGE = 1 - EPwm6RegsFile : > EPWM6, PAGE = 1 - EPwm7RegsFile : > EPWM7, PAGE = 1 - EPwm8RegsFile : > EPWM8, PAGE = 1 - EPwm9RegsFile : > EPWM9, PAGE = 1 - EPwm10RegsFile : > EPWM10, PAGE = 1 - EPwm11RegsFile : > EPWM11, PAGE = 1 - EPwm12RegsFile : > EPWM12, PAGE = 1 - - EQep1RegsFile : > EQEP1, PAGE = 1 - EQep2RegsFile : > EQEP2, PAGE = 1 - EQep3RegsFile : > EQEP3, PAGE = 1 - - GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 - GpioDataRegsFile : > GPIODAT, PAGE = 1 - - Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 - Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 - - I2caRegsFile : > I2CA, PAGE = 1 - I2cbRegsFile : > I2CB, PAGE = 1 - IpcRegsFile : > IPC, PAGE = 1 - - FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1 - - MemCfgRegsFile : > MEMCFG, PAGE = 1 - Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1 - AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 - MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 - - McbspaRegsFile : > MCBSPA, PAGE = 1 - McbspbRegsFile : > MCBSPB, PAGE = 1 - - NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 - - PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 - - SciaRegsFile : > SCIA, PAGE = 1 - ScibRegsFile : > SCIB, PAGE = 1 - ScicRegsFile : > SCIC, PAGE = 1 - ScidRegsFile : > SCID, PAGE = 1 - - Sdfm1RegsFile : > SDFM1, PAGE = 1 - Sdfm2RegsFile : > SDFM2, PAGE = 1 - - SpiaRegsFile : > SPIA, PAGE = 1 - SpibRegsFile : > SPIB, PAGE = 1 - SpicRegsFile : > SPIC, PAGE = 1 - SpidRegsFile : > SPID, PAGE = 1 - - DevCfgRegsFile : > DEV_CFG, PAGE = 1 - ClkCfgRegsFile : > CLK_CFG, PAGE = 1 - CpuSysRegsFile : > CPU_SYS, PAGE = 1 - - WdRegsFile : > WD, PAGE = 1 - - XintRegsFile : > XINT PAGE = 1 - MemCfgRegs : > MEMCFG PAGE = 1 - -} - -/* -//=========================================================================== -// End of file. -//=========================================================================== -*/ diff --git a/bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd b/bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd deleted file mode 100644 index c125c94918..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd +++ /dev/null @@ -1,287 +0,0 @@ - -MEMORY -{ - PAGE 0: /* Program Memory */ - - PAGE 1: /* Data Memory */ - - ADCA_RESULT : origin = 0x000B00, length = 0x000020 - ADCB_RESULT : origin = 0x000B20, length = 0x000020 - ADCC_RESULT : origin = 0x000B40, length = 0x000020 - ADCD_RESULT : origin = 0x000B60, length = 0x000020 - - ADCA : origin = 0x007400, length = 0x000080 - ADCB : origin = 0x007480, length = 0x000080 - ADCC : origin = 0x007500, length = 0x000080 - ADCD : origin = 0x007580, length = 0x000080 - - ANALOG_SUBSYS : origin = 0x05D180, length = 0x000080 - - CANA : origin = 0x048000, length = 0x000800 - CANB : origin = 0x04A000, length = 0x000800 - - CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */ - - CLB_XBAR : origin = 0x007A40, length = 0x000040 - - CMPSS1 : origin = 0x005C80, length = 0x000020 - CMPSS2 : origin = 0x005CA0, length = 0x000020 - CMPSS3 : origin = 0x005CC0, length = 0x000020 - CMPSS4 : origin = 0x005CE0, length = 0x000020 - CMPSS5 : origin = 0x005D00, length = 0x000020 - CMPSS6 : origin = 0x005D20, length = 0x000020 - CMPSS7 : origin = 0x005D40, length = 0x000020 - CMPSS8 : origin = 0x005D60, length = 0x000020 - - CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ - CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ - CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ - - DACA : origin = 0x005C00, length = 0x000010 - DACB : origin = 0x005C10, length = 0x000010 - DACC : origin = 0x005C20, length = 0x000010 - - DMA : origin = 0x001000, length = 0x000200 - DMACLASRCSEL : origin = 0x007980, length = 0x000040 - - ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */ - ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */ - ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */ - ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */ - ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */ - ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */ - - EMIF1 : origin = 0x047000, length = 0x000800 - EMIF2 : origin = 0x047800, length = 0x000800 - - EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ - EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ - EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */ - - EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ - EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ - EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ - EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ - EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ - EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ - EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ - EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ - EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */ - EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */ - EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */ - EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */ - - EPWM_XBAR : origin = 0x007A00, length = 0x000040 - - FLASH0_CTRL : origin = 0x05F800, length = 0x000300 - FLASH0_ECC : origin = 0x05FB00, length = 0x000040 - - GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */ - GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */ - - OUTPUT_XBAR : origin = 0x007A80, length = 0x000040 - I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ - I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */ - - IPC : origin = 0x050000, length = 0x000024 - - FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002 - - ROMPREFETCH : origin = 0x05E608, length = 0x000002 - - MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ - EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */ - EMIF2CONFIG : origin = 0x05F4A0, length = 0x000020 /* Emif-2 Config registers */ - ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ - MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ - ROMWAITSTATE : origin = 0x05F540, length = 0x000002 /* ROM Config registers */ - - - MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */ - MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */ - - NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ - - PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ - PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ - SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ - SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ - SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */ - SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */ - - SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ - SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */ - - SPIA : origin = 0x006100, length = 0x000010 - SPIB : origin = 0x006110, length = 0x000010 - SPIC : origin = 0x006120, length = 0x000010 - SPID : origin = 0x006130, length = 0x000010 - - UPP : origin = 0x006200, length = 0x000100 /* uPP registers */ - - DEV_CFG : origin = 0x05D000, length = 0x000180 - CLK_CFG : origin = 0x05D200, length = 0x000100 - CPU_SYS : origin = 0x05D300, length = 0x000100 - - INPUT_XBAR : origin = 0x007900, length = 0x000020 - XBAR : origin = 0x007920, length = 0x000020 - SYNC_SOC : origin = 0x007940, length = 0x000010 - WD : origin = 0x007000, length = 0x000040 - - XINT : origin = 0x007070, length = 0x000010 - - DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */ - DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */ - DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ - -} - - -SECTIONS -{ -/*** PIE Vect Table and Boot ROM Variables Structures ***/ - UNION run = PIE_VECT, PAGE = 1 - { - PieVectTableFile - GROUP - { - EmuBModeVar - EmuBootPinsVar - } - } - - AdcaResultFile : > ADCA_RESULT, PAGE = 1 - AdcbResultFile : > ADCB_RESULT, PAGE = 1 - AdccResultFile : > ADCC_RESULT, PAGE = 1 - AdcdResultFile : > ADCD_RESULT, PAGE = 1 - - AdcaRegsFile : > ADCA, PAGE = 1 - AdcbRegsFile : > ADCB, PAGE = 1 - AdccRegsFile : > ADCC, PAGE = 1 - AdcdRegsFile : > ADCD, PAGE = 1 - - AnalogSubsysRegsFile : > ANALOG_SUBSYS, PAGE = 1 - - CanaRegsFile : > CANA, PAGE = 1 - CanbRegsFile : > CANB, PAGE = 1 - - Cla1RegsFile : > CLA1, PAGE = 1 - Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT - - ClbXbarRegsFile : > CLB_XBAR PAGE = 1 - - Cmpss1RegsFile : > CMPSS1, PAGE = 1 - Cmpss2RegsFile : > CMPSS2, PAGE = 1 - Cmpss3RegsFile : > CMPSS3, PAGE = 1 - Cmpss4RegsFile : > CMPSS4, PAGE = 1 - Cmpss5RegsFile : > CMPSS5, PAGE = 1 - Cmpss6RegsFile : > CMPSS6, PAGE = 1 - Cmpss7RegsFile : > CMPSS7, PAGE = 1 - Cmpss8RegsFile : > CMPSS8, PAGE = 1 - - CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 - CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 - CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 - - DacaRegsFile : > DACA PAGE = 1 - DacbRegsFile : > DACB PAGE = 1 - DaccRegsFile : > DACC PAGE = 1 - - DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1 - DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1 - DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 - - DmaRegsFile : > DMA PAGE = 1 - DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 - - ECap1RegsFile : > ECAP1, PAGE = 1 - ECap2RegsFile : > ECAP2, PAGE = 1 - ECap3RegsFile : > ECAP3, PAGE = 1 - ECap4RegsFile : > ECAP4, PAGE = 1 - ECap5RegsFile : > ECAP5, PAGE = 1 - ECap6RegsFile : > ECAP6, PAGE = 1 - - Emif1RegsFile : > EMIF1 PAGE = 1 - Emif2RegsFile : > EMIF2 PAGE = 1 - - EPwm1RegsFile : > EPWM1, PAGE = 1 - EPwm2RegsFile : > EPWM2, PAGE = 1 - EPwm3RegsFile : > EPWM3, PAGE = 1 - EPwm4RegsFile : > EPWM4, PAGE = 1 - EPwm5RegsFile : > EPWM5, PAGE = 1 - EPwm6RegsFile : > EPWM6, PAGE = 1 - EPwm7RegsFile : > EPWM7, PAGE = 1 - EPwm8RegsFile : > EPWM8, PAGE = 1 - EPwm9RegsFile : > EPWM9, PAGE = 1 - EPwm10RegsFile : > EPWM10, PAGE = 1 - EPwm11RegsFile : > EPWM11, PAGE = 1 - EPwm12RegsFile : > EPWM12, PAGE = 1 - - EPwmXbarRegsFile : > EPWM_XBAR PAGE = 1 - - EQep1RegsFile : > EQEP1, PAGE = 1 - EQep2RegsFile : > EQEP2, PAGE = 1 - EQep3RegsFile : > EQEP3, PAGE = 1 - - Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 - Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 - - GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 - GpioDataRegsFile : > GPIODAT, PAGE = 1 - - OutputXbarRegsFile : > OUTPUT_XBAR PAGE = 1 - I2caRegsFile : > I2CA, PAGE = 1 - I2cbRegsFile : > I2CB, PAGE = 1 - InputXbarRegsFile : > INPUT_XBAR PAGE = 1 - XbarRegsFile : > XBAR PAGE = 1 - IpcRegsFile : > IPC, PAGE = 1 - - FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1 - - RomPrefetchRegsFile : > ROMPREFETCH, PAGE = 1 - MemCfgRegsFile : > MEMCFG, PAGE = 1 - Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1 - Emif2ConfigRegsFile : > EMIF2CONFIG, PAGE = 1 - AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 - MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 - RomWaitStateRegsFile : > ROMWAITSTATE, PAGE = 1 - - McbspaRegsFile : > MCBSPA, PAGE = 1 - McbspbRegsFile : > MCBSPB, PAGE = 1 - - UppRegsFile : > UPP, PAGE = 1 - - NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 - PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 - - SciaRegsFile : > SCIA, PAGE = 1 - ScibRegsFile : > SCIB, PAGE = 1 - ScicRegsFile : > SCIC, PAGE = 1 - ScidRegsFile : > SCID, PAGE = 1 - - Sdfm1RegsFile : > SDFM1, PAGE = 1 - Sdfm2RegsFile : > SDFM2, PAGE = 1 - - SpiaRegsFile : > SPIA, PAGE = 1 - SpibRegsFile : > SPIB, PAGE = 1 - SpicRegsFile : > SPIC, PAGE = 1 - SpidRegsFile : > SPID, PAGE = 1 - - DevCfgRegsFile : > DEV_CFG, PAGE = 1 - ClkCfgRegsFile : > CLK_CFG, PAGE = 1 - CpuSysRegsFile : > CPU_SYS, PAGE = 1 - - SyncSocRegsFile : > SYNC_SOC, PAGE = 1 - - WdRegsFile : > WD, PAGE = 1 - - XintRegsFile : > XINT PAGE = 1 - MemCfgRegs : > MEMCFG PAGE = 1 - -} - -/* -//=========================================================================== -// End of file. -//=========================================================================== -*/ diff --git a/bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd b/bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd deleted file mode 100644 index af9414a90d..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd +++ /dev/null @@ -1,251 +0,0 @@ - -MEMORY -{ - PAGE 0: /* Program Memory */ - - PAGE 1: /* Data Memory */ - - ADCA_RESULT : origin = 0x000B00, length = 0x000020 - ADCB_RESULT : origin = 0x000B20, length = 0x000020 - ADCC_RESULT : origin = 0x000B40, length = 0x000020 - ADCD_RESULT : origin = 0x000B60, length = 0x000020 - - ADCA : origin = 0x007400, length = 0x000080 - ADCB : origin = 0x007480, length = 0x000080 - ADCC : origin = 0x007500, length = 0x000080 - ADCD : origin = 0x007580, length = 0x000080 - - CANA : origin = 0x048000, length = 0x000800 - CANB : origin = 0x04A000, length = 0x000800 - - CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */ - - CMPSS1 : origin = 0x005C80, length = 0x000020 - CMPSS2 : origin = 0x005CA0, length = 0x000020 - CMPSS3 : origin = 0x005CC0, length = 0x000020 - CMPSS4 : origin = 0x005CE0, length = 0x000020 - CMPSS5 : origin = 0x005D00, length = 0x000020 - CMPSS6 : origin = 0x005D20, length = 0x000020 - CMPSS7 : origin = 0x005D40, length = 0x000020 - CMPSS8 : origin = 0x005D60, length = 0x000020 - - CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ - CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ - CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ - - DACA : origin = 0x005C00, length = 0x000010 - DACB : origin = 0x005C10, length = 0x000010 - DACC : origin = 0x005C20, length = 0x000010 - - DMA : origin = 0x001000, length = 0x000200 - DMACLASRCSEL : origin = 0x007980, length = 0x000040 - - ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */ - ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */ - ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */ - ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */ - ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */ - ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */ - - EMIF1 : origin = 0x047000, length = 0x000800 - EMIF2 : origin = 0x047800, length = 0x000800 - - EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ - EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ - EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */ - - EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ - EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ - EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ - EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ - EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ - EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ - EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ - EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ - EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */ - EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */ - EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */ - EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */ - - FLASH0_CTRL : origin = 0x05F800, length = 0x000300 - FLASH0_ECC : origin = 0x05FB00, length = 0x000040 - - GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */ - GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */ - I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ - I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */ - - IPC : origin = 0x050000, length = 0x000024 - - FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002 - - MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ - EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */ - ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ - MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ - - - MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */ - MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */ - - NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ - - PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ - PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ - SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ - SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ - SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */ - SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */ - - SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ - SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */ - - SPIA : origin = 0x006100, length = 0x000010 - SPIB : origin = 0x006110, length = 0x000010 - SPIC : origin = 0x006120, length = 0x000010 - SPID : origin = 0x006130, length = 0x000010 - CLK_CFG : origin = 0x05D200, length = 0x000100 - CPU_SYS : origin = 0x05D300, length = 0x000100 - - WD : origin = 0x007000, length = 0x000040 - - XINT : origin = 0x007070, length = 0x000010 - - DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */ - DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */ - DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ - -} - - -SECTIONS -{ -/*** PIE Vect Table and Boot ROM Variables Structures ***/ - UNION run = PIE_VECT, PAGE = 1 - { - PieVectTableFile - GROUP - { - EmuBModeVar - } - } - - AdcaResultFile : > ADCA_RESULT, PAGE = 1 - AdcbResultFile : > ADCB_RESULT, PAGE = 1 - AdccResultFile : > ADCC_RESULT, PAGE = 1 - AdcdResultFile : > ADCD_RESULT, PAGE = 1 - - AdcaRegsFile : > ADCA, PAGE = 1 - AdcbRegsFile : > ADCB, PAGE = 1 - AdccRegsFile : > ADCC, PAGE = 1 - AdcdRegsFile : > ADCD, PAGE = 1 - - CanaRegsFile : > CANA, PAGE = 1 - CanbRegsFile : > CANB, PAGE = 1 - - Cla1RegsFile : > CLA1, PAGE = 1 - Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT - - Cmpss1RegsFile : > CMPSS1, PAGE = 1 - Cmpss2RegsFile : > CMPSS2, PAGE = 1 - Cmpss3RegsFile : > CMPSS3, PAGE = 1 - Cmpss4RegsFile : > CMPSS4, PAGE = 1 - Cmpss5RegsFile : > CMPSS5, PAGE = 1 - Cmpss6RegsFile : > CMPSS6, PAGE = 1 - Cmpss7RegsFile : > CMPSS7, PAGE = 1 - Cmpss8RegsFile : > CMPSS8, PAGE = 1 - - CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 - CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 - CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 - - DacaRegsFile : > DACA PAGE = 1 - DacbRegsFile : > DACB PAGE = 1 - DaccRegsFile : > DACC PAGE = 1 - - DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1 - DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1 - DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 - - DmaRegsFile : > DMA PAGE = 1 - DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 - - ECap1RegsFile : > ECAP1, PAGE = 1 - ECap2RegsFile : > ECAP2, PAGE = 1 - ECap3RegsFile : > ECAP3, PAGE = 1 - ECap4RegsFile : > ECAP4, PAGE = 1 - ECap5RegsFile : > ECAP5, PAGE = 1 - ECap6RegsFile : > ECAP6, PAGE = 1 - - Emif1RegsFile : > EMIF1 PAGE = 1 - Emif2RegsFile : > EMIF2 PAGE = 1 - - EPwm1RegsFile : > EPWM1, PAGE = 1 - EPwm2RegsFile : > EPWM2, PAGE = 1 - EPwm3RegsFile : > EPWM3, PAGE = 1 - EPwm4RegsFile : > EPWM4, PAGE = 1 - EPwm5RegsFile : > EPWM5, PAGE = 1 - EPwm6RegsFile : > EPWM6, PAGE = 1 - EPwm7RegsFile : > EPWM7, PAGE = 1 - EPwm8RegsFile : > EPWM8, PAGE = 1 - EPwm9RegsFile : > EPWM9, PAGE = 1 - EPwm10RegsFile : > EPWM10, PAGE = 1 - EPwm11RegsFile : > EPWM11, PAGE = 1 - EPwm12RegsFile : > EPWM12, PAGE = 1 - - EQep1RegsFile : > EQEP1, PAGE = 1 - EQep2RegsFile : > EQEP2, PAGE = 1 - EQep3RegsFile : > EQEP3, PAGE = 1 - - Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 - Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 - - GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 - GpioDataRegsFile : > GPIODAT, PAGE = 1 - - I2caRegsFile : > I2CA, PAGE = 1 - I2cbRegsFile : > I2CB, PAGE = 1 - - IpcRegsFile : > IPC, PAGE = 1 - - FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1 - - MemCfgRegsFile : > MEMCFG, PAGE = 1 - Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1 - AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 - MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 - - McbspaRegsFile : > MCBSPA, PAGE = 1 - McbspbRegsFile : > MCBSPB, PAGE = 1 - - NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 - PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 - - SciaRegsFile : > SCIA, PAGE = 1 - ScibRegsFile : > SCIB, PAGE = 1 - ScicRegsFile : > SCIC, PAGE = 1 - ScidRegsFile : > SCID, PAGE = 1 - - Sdfm1RegsFile : > SDFM1, PAGE = 1 - Sdfm2RegsFile : > SDFM2, PAGE = 1 - - SpiaRegsFile : > SPIA, PAGE = 1 - SpibRegsFile : > SPIB, PAGE = 1 - SpicRegsFile : > SPIC, PAGE = 1 - SpidRegsFile : > SPID, PAGE = 1 - - ClkCfgRegsFile : > CLK_CFG, PAGE = 1 - CpuSysRegsFile : > CPU_SYS, PAGE = 1 - - WdRegsFile : > WD, PAGE = 1 - - XintRegsFile : > XINT PAGE = 1 - MemCfgRegs : > MEMCFG PAGE = 1 - -} - -/* -//=========================================================================== -// End of file. -//=========================================================================== -*/ diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_adc.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_adc.h deleted file mode 100644 index cdcee353fb..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_adc.h +++ /dev/null @@ -1,1067 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_adc.h -// -// TITLE: ADC Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_ADC_H__ -#define __F2837xD_ADC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// ADC Individual Register Bit Definitions: - -struct ADCCTL1_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 INTPULSEPOS:1; // 2 ADC Interrupt Pulse Position - Uint16 rsvd2:4; // 6:3 Reserved - Uint16 ADCPWDNZ:1; // 7 ADC Power Down - Uint16 ADCBSYCHN:4; // 11:8 ADC Busy Channel - Uint16 rsvd3:1; // 12 Reserved - Uint16 ADCBSY:1; // 13 ADC Busy - Uint16 rsvd4:2; // 15:14 Reserved -}; - -union ADCCTL1_REG { - Uint16 all; - struct ADCCTL1_BITS bit; -}; - -struct ADCCTL2_BITS { // bits description - Uint16 PRESCALE:4; // 3:0 ADC Clock Prescaler - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 RESOLUTION:1; // 6 SOC Conversion Resolution - Uint16 SIGNALMODE:1; // 7 SOC Signaling Mode - Uint16 rsvd2:5; // 12:8 Reserved - Uint16 rsvd3:3; // 15:13 Reserved -}; - -union ADCCTL2_REG { - Uint16 all; - struct ADCCTL2_BITS bit; -}; - -struct ADCBURSTCTL_BITS { // bits description - Uint16 BURSTTRIGSEL:6; // 5:0 SOC Burst Trigger Source Select - Uint16 rsvd1:2; // 7:6 Reserved - Uint16 BURSTSIZE:4; // 11:8 SOC Burst Size Select - Uint16 rsvd2:3; // 14:12 Reserved - Uint16 BURSTEN:1; // 15 SOC Burst Mode Enable -}; - -union ADCBURSTCTL_REG { - Uint16 all; - struct ADCBURSTCTL_BITS bit; -}; - -struct ADCINTFLG_BITS { // bits description - Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag - Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag - Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag - Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union ADCINTFLG_REG { - Uint16 all; - struct ADCINTFLG_BITS bit; -}; - -struct ADCINTFLGCLR_BITS { // bits description - Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag Clear - Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag Clear - Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag Clear - Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag Clear - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union ADCINTFLGCLR_REG { - Uint16 all; - struct ADCINTFLGCLR_BITS bit; -}; - -struct ADCINTOVF_BITS { // bits description - Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Flags - Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Flags - Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Flags - Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Flags - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union ADCINTOVF_REG { - Uint16 all; - struct ADCINTOVF_BITS bit; -}; - -struct ADCINTOVFCLR_BITS { // bits description - Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Clear Bits - Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Clear Bits - Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Clear Bits - Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Clear Bits - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union ADCINTOVFCLR_REG { - Uint16 all; - struct ADCINTOVFCLR_BITS bit; -}; - -struct ADCINTSEL1N2_BITS { // bits description - Uint16 INT1SEL:4; // 3:0 ADCINT1 EOC Source Select - Uint16 rsvd1:1; // 4 Reserved - Uint16 INT1E:1; // 5 ADCINT1 Interrupt Enable - Uint16 INT1CONT:1; // 6 ADCINT1 Continuous Mode Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 INT2SEL:4; // 11:8 ADCINT2 EOC Source Select - Uint16 rsvd3:1; // 12 Reserved - Uint16 INT2E:1; // 13 ADCINT2 Interrupt Enable - Uint16 INT2CONT:1; // 14 ADCINT2 Continuous Mode Enable - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCINTSEL1N2_REG { - Uint16 all; - struct ADCINTSEL1N2_BITS bit; -}; - -struct ADCINTSEL3N4_BITS { // bits description - Uint16 INT3SEL:4; // 3:0 ADCINT3 EOC Source Select - Uint16 rsvd1:1; // 4 Reserved - Uint16 INT3E:1; // 5 ADCINT3 Interrupt Enable - Uint16 INT3CONT:1; // 6 ADCINT3 Continuous Mode Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 INT4SEL:4; // 11:8 ADCINT4 EOC Source Select - Uint16 rsvd3:1; // 12 Reserved - Uint16 INT4E:1; // 13 ADCINT4 Interrupt Enable - Uint16 INT4CONT:1; // 14 ADCINT4 Continuous Mode Enable - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCINTSEL3N4_REG { - Uint16 all; - struct ADCINTSEL3N4_BITS bit; -}; - -struct ADCSOCPRICTL_BITS { // bits description - Uint16 SOCPRIORITY:5; // 4:0 SOC Priority - Uint16 RRPOINTER:5; // 9:5 Round Robin Pointer - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCSOCPRICTL_REG { - Uint16 all; - struct ADCSOCPRICTL_BITS bit; -}; - -struct ADCINTSOCSEL1_BITS { // bits description - Uint16 SOC0:2; // 1:0 SOC0 ADC Interrupt Trigger Select - Uint16 SOC1:2; // 3:2 SOC1 ADC Interrupt Trigger Select - Uint16 SOC2:2; // 5:4 SOC2 ADC Interrupt Trigger Select - Uint16 SOC3:2; // 7:6 SOC3 ADC Interrupt Trigger Select - Uint16 SOC4:2; // 9:8 SOC4 ADC Interrupt Trigger Select - Uint16 SOC5:2; // 11:10 SOC5 ADC Interrupt Trigger Select - Uint16 SOC6:2; // 13:12 SOC6 ADC Interrupt Trigger Select - Uint16 SOC7:2; // 15:14 SOC7 ADC Interrupt Trigger Select -}; - -union ADCINTSOCSEL1_REG { - Uint16 all; - struct ADCINTSOCSEL1_BITS bit; -}; - -struct ADCINTSOCSEL2_BITS { // bits description - Uint16 SOC8:2; // 1:0 SOC8 ADC Interrupt Trigger Select - Uint16 SOC9:2; // 3:2 SOC9 ADC Interrupt Trigger Select - Uint16 SOC10:2; // 5:4 SOC10 ADC Interrupt Trigger Select - Uint16 SOC11:2; // 7:6 SOC11 ADC Interrupt Trigger Select - Uint16 SOC12:2; // 9:8 SOC12 ADC Interrupt Trigger Select - Uint16 SOC13:2; // 11:10 SOC13 ADC Interrupt Trigger Select - Uint16 SOC14:2; // 13:12 SOC14 ADC Interrupt Trigger Select - Uint16 SOC15:2; // 15:14 SOC15 ADC Interrupt Trigger Select -}; - -union ADCINTSOCSEL2_REG { - Uint16 all; - struct ADCINTSOCSEL2_BITS bit; -}; - -struct ADCSOCFLG1_BITS { // bits description - Uint16 SOC0:1; // 0 SOC0 Start of Conversion Flag - Uint16 SOC1:1; // 1 SOC1 Start of Conversion Flag - Uint16 SOC2:1; // 2 SOC2 Start of Conversion Flag - Uint16 SOC3:1; // 3 SOC3 Start of Conversion Flag - Uint16 SOC4:1; // 4 SOC4 Start of Conversion Flag - Uint16 SOC5:1; // 5 SOC5 Start of Conversion Flag - Uint16 SOC6:1; // 6 SOC6 Start of Conversion Flag - Uint16 SOC7:1; // 7 SOC7 Start of Conversion Flag - Uint16 SOC8:1; // 8 SOC8 Start of Conversion Flag - Uint16 SOC9:1; // 9 SOC9 Start of Conversion Flag - Uint16 SOC10:1; // 10 SOC10 Start of Conversion Flag - Uint16 SOC11:1; // 11 SOC11 Start of Conversion Flag - Uint16 SOC12:1; // 12 SOC12 Start of Conversion Flag - Uint16 SOC13:1; // 13 SOC13 Start of Conversion Flag - Uint16 SOC14:1; // 14 SOC14 Start of Conversion Flag - Uint16 SOC15:1; // 15 SOC15 Start of Conversion Flag -}; - -union ADCSOCFLG1_REG { - Uint16 all; - struct ADCSOCFLG1_BITS bit; -}; - -struct ADCSOCFRC1_BITS { // bits description - Uint16 SOC0:1; // 0 SOC0 Force Start of Conversion Bit - Uint16 SOC1:1; // 1 SOC1 Force Start of Conversion Bit - Uint16 SOC2:1; // 2 SOC2 Force Start of Conversion Bit - Uint16 SOC3:1; // 3 SOC3 Force Start of Conversion Bit - Uint16 SOC4:1; // 4 SOC4 Force Start of Conversion Bit - Uint16 SOC5:1; // 5 SOC5 Force Start of Conversion Bit - Uint16 SOC6:1; // 6 SOC6 Force Start of Conversion Bit - Uint16 SOC7:1; // 7 SOC7 Force Start of Conversion Bit - Uint16 SOC8:1; // 8 SOC8 Force Start of Conversion Bit - Uint16 SOC9:1; // 9 SOC9 Force Start of Conversion Bit - Uint16 SOC10:1; // 10 SOC10 Force Start of Conversion Bit - Uint16 SOC11:1; // 11 SOC11 Force Start of Conversion Bit - Uint16 SOC12:1; // 12 SOC12 Force Start of Conversion Bit - Uint16 SOC13:1; // 13 SOC13 Force Start of Conversion Bit - Uint16 SOC14:1; // 14 SOC14 Force Start of Conversion Bit - Uint16 SOC15:1; // 15 SOC15 Force Start of Conversion Bit -}; - -union ADCSOCFRC1_REG { - Uint16 all; - struct ADCSOCFRC1_BITS bit; -}; - -struct ADCSOCOVF1_BITS { // bits description - Uint16 SOC0:1; // 0 SOC0 Start of Conversion Overflow Flag - Uint16 SOC1:1; // 1 SOC1 Start of Conversion Overflow Flag - Uint16 SOC2:1; // 2 SOC2 Start of Conversion Overflow Flag - Uint16 SOC3:1; // 3 SOC3 Start of Conversion Overflow Flag - Uint16 SOC4:1; // 4 SOC4 Start of Conversion Overflow Flag - Uint16 SOC5:1; // 5 SOC5 Start of Conversion Overflow Flag - Uint16 SOC6:1; // 6 SOC6 Start of Conversion Overflow Flag - Uint16 SOC7:1; // 7 SOC7 Start of Conversion Overflow Flag - Uint16 SOC8:1; // 8 SOC8 Start of Conversion Overflow Flag - Uint16 SOC9:1; // 9 SOC9 Start of Conversion Overflow Flag - Uint16 SOC10:1; // 10 SOC10 Start of Conversion Overflow Flag - Uint16 SOC11:1; // 11 SOC11 Start of Conversion Overflow Flag - Uint16 SOC12:1; // 12 SOC12 Start of Conversion Overflow Flag - Uint16 SOC13:1; // 13 SOC13 Start of Conversion Overflow Flag - Uint16 SOC14:1; // 14 SOC14 Start of Conversion Overflow Flag - Uint16 SOC15:1; // 15 SOC15 Start of Conversion Overflow Flag -}; - -union ADCSOCOVF1_REG { - Uint16 all; - struct ADCSOCOVF1_BITS bit; -}; - -struct ADCSOCOVFCLR1_BITS { // bits description - Uint16 SOC0:1; // 0 SOC0 Clear Start of Conversion Overflow Bit - Uint16 SOC1:1; // 1 SOC1 Clear Start of Conversion Overflow Bit - Uint16 SOC2:1; // 2 SOC2 Clear Start of Conversion Overflow Bit - Uint16 SOC3:1; // 3 SOC3 Clear Start of Conversion Overflow Bit - Uint16 SOC4:1; // 4 SOC4 Clear Start of Conversion Overflow Bit - Uint16 SOC5:1; // 5 SOC5 Clear Start of Conversion Overflow Bit - Uint16 SOC6:1; // 6 SOC6 Clear Start of Conversion Overflow Bit - Uint16 SOC7:1; // 7 SOC7 Clear Start of Conversion Overflow Bit - Uint16 SOC8:1; // 8 SOC8 Clear Start of Conversion Overflow Bit - Uint16 SOC9:1; // 9 SOC9 Clear Start of Conversion Overflow Bit - Uint16 SOC10:1; // 10 SOC10 Clear Start of Conversion Overflow Bit - Uint16 SOC11:1; // 11 SOC11 Clear Start of Conversion Overflow Bit - Uint16 SOC12:1; // 12 SOC12 Clear Start of Conversion Overflow Bit - Uint16 SOC13:1; // 13 SOC13 Clear Start of Conversion Overflow Bit - Uint16 SOC14:1; // 14 SOC14 Clear Start of Conversion Overflow Bit - Uint16 SOC15:1; // 15 SOC15 Clear Start of Conversion Overflow Bit -}; - -union ADCSOCOVFCLR1_REG { - Uint16 all; - struct ADCSOCOVFCLR1_BITS bit; -}; - -struct ADCSOC0CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC0 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC0 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC0 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC0CTL_REG { - Uint32 all; - struct ADCSOC0CTL_BITS bit; -}; - -struct ADCSOC1CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC1 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC1 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC1 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC1CTL_REG { - Uint32 all; - struct ADCSOC1CTL_BITS bit; -}; - -struct ADCSOC2CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC2 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC2 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC2 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC2CTL_REG { - Uint32 all; - struct ADCSOC2CTL_BITS bit; -}; - -struct ADCSOC3CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC3 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC3 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC3 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC3CTL_REG { - Uint32 all; - struct ADCSOC3CTL_BITS bit; -}; - -struct ADCSOC4CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC4 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC4 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC4 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC4CTL_REG { - Uint32 all; - struct ADCSOC4CTL_BITS bit; -}; - -struct ADCSOC5CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC5 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC5 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC5 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC5CTL_REG { - Uint32 all; - struct ADCSOC5CTL_BITS bit; -}; - -struct ADCSOC6CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC6 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC6 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC6 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC6CTL_REG { - Uint32 all; - struct ADCSOC6CTL_BITS bit; -}; - -struct ADCSOC7CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC7 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC7 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC7 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC7CTL_REG { - Uint32 all; - struct ADCSOC7CTL_BITS bit; -}; - -struct ADCSOC8CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC8 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC8 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC8 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC8CTL_REG { - Uint32 all; - struct ADCSOC8CTL_BITS bit; -}; - -struct ADCSOC9CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC9 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC9 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC9 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC9CTL_REG { - Uint32 all; - struct ADCSOC9CTL_BITS bit; -}; - -struct ADCSOC10CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC10 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC10 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC10 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC10CTL_REG { - Uint32 all; - struct ADCSOC10CTL_BITS bit; -}; - -struct ADCSOC11CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC11 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC11 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC11 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC11CTL_REG { - Uint32 all; - struct ADCSOC11CTL_BITS bit; -}; - -struct ADCSOC12CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC12 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC12 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC12 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC12CTL_REG { - Uint32 all; - struct ADCSOC12CTL_BITS bit; -}; - -struct ADCSOC13CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC13 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC13 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC13 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC13CTL_REG { - Uint32 all; - struct ADCSOC13CTL_BITS bit; -}; - -struct ADCSOC14CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC14 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC14 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC14 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC14CTL_REG { - Uint32 all; - struct ADCSOC14CTL_BITS bit; -}; - -struct ADCSOC15CTL_BITS { // bits description - Uint16 ACQPS:9; // 8:0 SOC15 Acquisition Prescale - Uint16 rsvd1:6; // 14:9 Reserved - Uint32 CHSEL:4; // 18:15 SOC15 Channel Select - Uint16 rsvd2:1; // 19 Reserved - Uint16 TRIGSEL:5; // 24:20 SOC15 Trigger Source Select - Uint16 rsvd3:7; // 31:25 Reserved -}; - -union ADCSOC15CTL_REG { - Uint32 all; - struct ADCSOC15CTL_BITS bit; -}; - -struct ADCEVTSTAT_BITS { // bits description - Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Flag - Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Flag - Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Flag - Uint16 rsvd1:1; // 3 Reserved - Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Flag - Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Flag - Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Flag - Uint16 rsvd2:1; // 7 Reserved - Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Flag - Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Flag - Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Flag - Uint16 rsvd3:1; // 11 Reserved - Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Flag - Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Flag - Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Flag - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCEVTSTAT_REG { - Uint16 all; - struct ADCEVTSTAT_BITS bit; -}; - -struct ADCEVTCLR_BITS { // bits description - Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Clear - Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Clear - Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Clear - Uint16 rsvd1:1; // 3 Reserved - Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Clear - Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Clear - Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Clear - Uint16 rsvd2:1; // 7 Reserved - Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Clear - Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Clear - Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Clear - Uint16 rsvd3:1; // 11 Reserved - Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Clear - Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Clear - Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Clear - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCEVTCLR_REG { - Uint16 all; - struct ADCEVTCLR_BITS bit; -}; - -struct ADCEVTSEL_BITS { // bits description - Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Event Enable - Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Event Enable - Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Event Enable - Uint16 rsvd1:1; // 3 Reserved - Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Event Enable - Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Event Enable - Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Event Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Event Enable - Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Event Enable - Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Event Enable - Uint16 rsvd3:1; // 11 Reserved - Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Event Enable - Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Event Enable - Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Event Enable - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCEVTSEL_REG { - Uint16 all; - struct ADCEVTSEL_BITS bit; -}; - -struct ADCEVTINTSEL_BITS { // bits description - Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Interrupt Enable - Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Interrupt Enable - Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Interrupt Enable - Uint16 rsvd1:1; // 3 Reserved - Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Interrupt Enable - Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Interrupt Enable - Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Interrupt Enable - Uint16 rsvd2:1; // 7 Reserved - Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Interrupt Enable - Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Interrupt Enable - Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Interrupt Enable - Uint16 rsvd3:1; // 11 Reserved - Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Interrupt Enable - Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Interrupt Enable - Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Interrupt Enable - Uint16 rsvd4:1; // 15 Reserved -}; - -union ADCEVTINTSEL_REG { - Uint16 all; - struct ADCEVTINTSEL_BITS bit; -}; - -struct ADCCOUNTER_BITS { // bits description - Uint16 FREECOUNT:12; // 11:0 ADC Free Running Counter Value - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCCOUNTER_REG { - Uint16 all; - struct ADCCOUNTER_BITS bit; -}; - -struct ADCREV_BITS { // bits description - Uint16 TYPE:8; // 7:0 ADC Type - Uint16 REV:8; // 15:8 ADC Revision -}; - -union ADCREV_REG { - Uint16 all; - struct ADCREV_BITS bit; -}; - -struct ADCOFFTRIM_BITS { // bits description - Uint16 OFFTRIM:8; // 7:0 ADC Offset Trim - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union ADCOFFTRIM_REG { - Uint16 all; - struct ADCOFFTRIM_BITS bit; -}; - -struct ADCPPB1CONFIG_BITS { // bits description - Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 1 Configuration - Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 1 Two's Complement Enable - Uint16 rsvd1:1; // 5 Reserved - Uint16 rsvd2:10; // 15:6 Reserved -}; - -union ADCPPB1CONFIG_REG { - Uint16 all; - struct ADCPPB1CONFIG_BITS bit; -}; - -struct ADCPPB1STAMP_BITS { // bits description - Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 1 Delay Time Stamp - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCPPB1STAMP_REG { - Uint16 all; - struct ADCPPB1STAMP_BITS bit; -}; - -struct ADCPPB1OFFCAL_BITS { // bits description - Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCPPB1OFFCAL_REG { - Uint16 all; - struct ADCPPB1OFFCAL_BITS bit; -}; - -struct ADCPPB1TRIPHI_BITS { // bits description - Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 1 Trip High Limit - Uint16 HSIGN:1; // 16 High Limit Sign Bit - Uint16 rsvd1:15; // 31:17 Reserved -}; - -union ADCPPB1TRIPHI_REG { - Uint32 all; - struct ADCPPB1TRIPHI_BITS bit; -}; - -struct ADCPPB1TRIPLO_BITS { // bits description - Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 1 Trip Low Limit - Uint16 LSIGN:1; // 16 Low Limit Sign Bit - Uint16 rsvd1:3; // 19:17 Reserved - Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 1 Request Time Stamp -}; - -union ADCPPB1TRIPLO_REG { - Uint32 all; - struct ADCPPB1TRIPLO_BITS bit; -}; - -struct ADCPPB2CONFIG_BITS { // bits description - Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 2 Configuration - Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 2 Two's Complement Enable - Uint16 rsvd1:1; // 5 Reserved - Uint16 rsvd2:10; // 15:6 Reserved -}; - -union ADCPPB2CONFIG_REG { - Uint16 all; - struct ADCPPB2CONFIG_BITS bit; -}; - -struct ADCPPB2STAMP_BITS { // bits description - Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 2 Delay Time Stamp - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCPPB2STAMP_REG { - Uint16 all; - struct ADCPPB2STAMP_BITS bit; -}; - -struct ADCPPB2OFFCAL_BITS { // bits description - Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCPPB2OFFCAL_REG { - Uint16 all; - struct ADCPPB2OFFCAL_BITS bit; -}; - -struct ADCPPB2TRIPHI_BITS { // bits description - Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 2 Trip High Limit - Uint16 HSIGN:1; // 16 High Limit Sign Bit - Uint16 rsvd1:15; // 31:17 Reserved -}; - -union ADCPPB2TRIPHI_REG { - Uint32 all; - struct ADCPPB2TRIPHI_BITS bit; -}; - -struct ADCPPB2TRIPLO_BITS { // bits description - Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 2 Trip Low Limit - Uint16 LSIGN:1; // 16 Low Limit Sign Bit - Uint16 rsvd1:3; // 19:17 Reserved - Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 2 Request Time Stamp -}; - -union ADCPPB2TRIPLO_REG { - Uint32 all; - struct ADCPPB2TRIPLO_BITS bit; -}; - -struct ADCPPB3CONFIG_BITS { // bits description - Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 3 Configuration - Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 3 Two's Complement Enable - Uint16 rsvd1:1; // 5 Reserved - Uint16 rsvd2:10; // 15:6 Reserved -}; - -union ADCPPB3CONFIG_REG { - Uint16 all; - struct ADCPPB3CONFIG_BITS bit; -}; - -struct ADCPPB3STAMP_BITS { // bits description - Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 3 Delay Time Stamp - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCPPB3STAMP_REG { - Uint16 all; - struct ADCPPB3STAMP_BITS bit; -}; - -struct ADCPPB3OFFCAL_BITS { // bits description - Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCPPB3OFFCAL_REG { - Uint16 all; - struct ADCPPB3OFFCAL_BITS bit; -}; - -struct ADCPPB3TRIPHI_BITS { // bits description - Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 3 Trip High Limit - Uint16 HSIGN:1; // 16 High Limit Sign Bit - Uint16 rsvd1:15; // 31:17 Reserved -}; - -union ADCPPB3TRIPHI_REG { - Uint32 all; - struct ADCPPB3TRIPHI_BITS bit; -}; - -struct ADCPPB3TRIPLO_BITS { // bits description - Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 3 Trip Low Limit - Uint16 LSIGN:1; // 16 Low Limit Sign Bit - Uint16 rsvd1:3; // 19:17 Reserved - Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 3 Request Time Stamp -}; - -union ADCPPB3TRIPLO_REG { - Uint32 all; - struct ADCPPB3TRIPLO_BITS bit; -}; - -struct ADCPPB4CONFIG_BITS { // bits description - Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 4 Configuration - Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 4 Two's Complement Enable - Uint16 rsvd1:1; // 5 Reserved - Uint16 rsvd2:10; // 15:6 Reserved -}; - -union ADCPPB4CONFIG_REG { - Uint16 all; - struct ADCPPB4CONFIG_BITS bit; -}; - -struct ADCPPB4STAMP_BITS { // bits description - Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 4 Delay Time Stamp - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ADCPPB4STAMP_REG { - Uint16 all; - struct ADCPPB4STAMP_BITS bit; -}; - -struct ADCPPB4OFFCAL_BITS { // bits description - Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union ADCPPB4OFFCAL_REG { - Uint16 all; - struct ADCPPB4OFFCAL_BITS bit; -}; - -struct ADCPPB4TRIPHI_BITS { // bits description - Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 4 Trip High Limit - Uint16 HSIGN:1; // 16 High Limit Sign Bit - Uint16 rsvd1:15; // 31:17 Reserved -}; - -union ADCPPB4TRIPHI_REG { - Uint32 all; - struct ADCPPB4TRIPHI_BITS bit; -}; - -struct ADCPPB4TRIPLO_BITS { // bits description - Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 4 Trip Low Limit - Uint16 LSIGN:1; // 16 Low Limit Sign Bit - Uint16 rsvd1:3; // 19:17 Reserved - Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 4 Request Time Stamp -}; - -union ADCPPB4TRIPLO_REG { - Uint32 all; - struct ADCPPB4TRIPLO_BITS bit; -}; - -struct ADC_REGS { - union ADCCTL1_REG ADCCTL1; // ADC Control 1 Register - union ADCCTL2_REG ADCCTL2; // ADC Control 2 Register - union ADCBURSTCTL_REG ADCBURSTCTL; // ADC Burst Control Register - union ADCINTFLG_REG ADCINTFLG; // ADC Interrupt Flag Register - union ADCINTFLGCLR_REG ADCINTFLGCLR; // ADC Interrupt Flag Clear Register - union ADCINTOVF_REG ADCINTOVF; // ADC Interrupt Overflow Register - union ADCINTOVFCLR_REG ADCINTOVFCLR; // ADC Interrupt Overflow Clear Register - union ADCINTSEL1N2_REG ADCINTSEL1N2; // ADC Interrupt 1 and 2 Selection Register - union ADCINTSEL3N4_REG ADCINTSEL3N4; // ADC Interrupt 3 and 4 Selection Register - union ADCSOCPRICTL_REG ADCSOCPRICTL; // ADC SOC Priority Control Register - union ADCINTSOCSEL1_REG ADCINTSOCSEL1; // ADC Interrupt SOC Selection 1 Register - union ADCINTSOCSEL2_REG ADCINTSOCSEL2; // ADC Interrupt SOC Selection 2 Register - union ADCSOCFLG1_REG ADCSOCFLG1; // ADC SOC Flag 1 Register - union ADCSOCFRC1_REG ADCSOCFRC1; // ADC SOC Force 1 Register - union ADCSOCOVF1_REG ADCSOCOVF1; // ADC SOC Overflow 1 Register - union ADCSOCOVFCLR1_REG ADCSOCOVFCLR1; // ADC SOC Overflow Clear 1 Register - union ADCSOC0CTL_REG ADCSOC0CTL; // ADC SOC0 Control Register - union ADCSOC1CTL_REG ADCSOC1CTL; // ADC SOC1 Control Register - union ADCSOC2CTL_REG ADCSOC2CTL; // ADC SOC2 Control Register - union ADCSOC3CTL_REG ADCSOC3CTL; // ADC SOC3 Control Register - union ADCSOC4CTL_REG ADCSOC4CTL; // ADC SOC4 Control Register - union ADCSOC5CTL_REG ADCSOC5CTL; // ADC SOC5 Control Register - union ADCSOC6CTL_REG ADCSOC6CTL; // ADC SOC6 Control Register - union ADCSOC7CTL_REG ADCSOC7CTL; // ADC SOC7 Control Register - union ADCSOC8CTL_REG ADCSOC8CTL; // ADC SOC8 Control Register - union ADCSOC9CTL_REG ADCSOC9CTL; // ADC SOC9 Control Register - union ADCSOC10CTL_REG ADCSOC10CTL; // ADC SOC10 Control Register - union ADCSOC11CTL_REG ADCSOC11CTL; // ADC SOC11 Control Register - union ADCSOC12CTL_REG ADCSOC12CTL; // ADC SOC12 Control Register - union ADCSOC13CTL_REG ADCSOC13CTL; // ADC SOC13 Control Register - union ADCSOC14CTL_REG ADCSOC14CTL; // ADC SOC14 Control Register - union ADCSOC15CTL_REG ADCSOC15CTL; // ADC SOC15 Control Register - union ADCEVTSTAT_REG ADCEVTSTAT; // ADC Event Status Register - Uint16 rsvd1; // Reserved - union ADCEVTCLR_REG ADCEVTCLR; // ADC Event Clear Register - Uint16 rsvd2; // Reserved - union ADCEVTSEL_REG ADCEVTSEL; // ADC Event Selection Register - Uint16 rsvd3; // Reserved - union ADCEVTINTSEL_REG ADCEVTINTSEL; // ADC Event Interrupt Selection Register - Uint16 rsvd4[2]; // Reserved - union ADCCOUNTER_REG ADCCOUNTER; // ADC Counter Register - union ADCREV_REG ADCREV; // ADC Revision Register - union ADCOFFTRIM_REG ADCOFFTRIM; // ADC Offset Trim Register - Uint16 rsvd5[4]; // Reserved - union ADCPPB1CONFIG_REG ADCPPB1CONFIG; // ADC PPB1 Config Register - union ADCPPB1STAMP_REG ADCPPB1STAMP; // ADC PPB1 Sample Delay Time Stamp Register - union ADCPPB1OFFCAL_REG ADCPPB1OFFCAL; // ADC PPB1 Offset Calibration Register - Uint16 ADCPPB1OFFREF; // ADC PPB1 Offset Reference Register - union ADCPPB1TRIPHI_REG ADCPPB1TRIPHI; // ADC PPB1 Trip High Register - union ADCPPB1TRIPLO_REG ADCPPB1TRIPLO; // ADC PPB1 Trip Low/Trigger Time Stamp Register - union ADCPPB2CONFIG_REG ADCPPB2CONFIG; // ADC PPB2 Config Register - union ADCPPB2STAMP_REG ADCPPB2STAMP; // ADC PPB2 Sample Delay Time Stamp Register - union ADCPPB2OFFCAL_REG ADCPPB2OFFCAL; // ADC PPB2 Offset Calibration Register - Uint16 ADCPPB2OFFREF; // ADC PPB2 Offset Reference Register - union ADCPPB2TRIPHI_REG ADCPPB2TRIPHI; // ADC PPB2 Trip High Register - union ADCPPB2TRIPLO_REG ADCPPB2TRIPLO; // ADC PPB2 Trip Low/Trigger Time Stamp Register - union ADCPPB3CONFIG_REG ADCPPB3CONFIG; // ADC PPB3 Config Register - union ADCPPB3STAMP_REG ADCPPB3STAMP; // ADC PPB3 Sample Delay Time Stamp Register - union ADCPPB3OFFCAL_REG ADCPPB3OFFCAL; // ADC PPB3 Offset Calibration Register - Uint16 ADCPPB3OFFREF; // ADC PPB3 Offset Reference Register - union ADCPPB3TRIPHI_REG ADCPPB3TRIPHI; // ADC PPB3 Trip High Register - union ADCPPB3TRIPLO_REG ADCPPB3TRIPLO; // ADC PPB3 Trip Low/Trigger Time Stamp Register - union ADCPPB4CONFIG_REG ADCPPB4CONFIG; // ADC PPB4 Config Register - union ADCPPB4STAMP_REG ADCPPB4STAMP; // ADC PPB4 Sample Delay Time Stamp Register - union ADCPPB4OFFCAL_REG ADCPPB4OFFCAL; // ADC PPB4 Offset Calibration Register - Uint16 ADCPPB4OFFREF; // ADC PPB4 Offset Reference Register - union ADCPPB4TRIPHI_REG ADCPPB4TRIPHI; // ADC PPB4 Trip High Register - union ADCPPB4TRIPLO_REG ADCPPB4TRIPLO; // ADC PPB4 Trip Low/Trigger Time Stamp Register - Uint16 rsvd6[16]; // Reserved - Uint32 ADCINLTRIM1; // ADC Linearity Trim 1 Register - Uint32 ADCINLTRIM2; // ADC Linearity Trim 2 Register - Uint32 ADCINLTRIM3; // ADC Linearity Trim 3 Register - Uint32 ADCINLTRIM4; // ADC Linearity Trim 4 Register - Uint32 ADCINLTRIM5; // ADC Linearity Trim 5 Register - Uint32 ADCINLTRIM6; // ADC Linearity Trim 6 Register - Uint16 rsvd7[4]; // Reserved -}; - -struct ADCPPB1RESULT_BITS { // bits description - Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result - Uint16 SIGN:16; // 31:16 Sign Extended Bits -}; - -union ADCPPB1RESULT_REG { - Uint32 all; - struct ADCPPB1RESULT_BITS bit; -}; - -struct ADCPPB2RESULT_BITS { // bits description - Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result - Uint16 SIGN:16; // 31:16 Sign Extended Bits -}; - -union ADCPPB2RESULT_REG { - Uint32 all; - struct ADCPPB2RESULT_BITS bit; -}; - -struct ADCPPB3RESULT_BITS { // bits description - Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result - Uint16 SIGN:16; // 31:16 Sign Extended Bits -}; - -union ADCPPB3RESULT_REG { - Uint32 all; - struct ADCPPB3RESULT_BITS bit; -}; - -struct ADCPPB4RESULT_BITS { // bits description - Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result - Uint16 SIGN:16; // 31:16 Sign Extended Bits -}; - -union ADCPPB4RESULT_REG { - Uint32 all; - struct ADCPPB4RESULT_BITS bit; -}; - -struct ADC_RESULT_REGS { - Uint16 ADCRESULT0; // ADC Result 0 Register - Uint16 ADCRESULT1; // ADC Result 1 Register - Uint16 ADCRESULT2; // ADC Result 2 Register - Uint16 ADCRESULT3; // ADC Result 3 Register - Uint16 ADCRESULT4; // ADC Result 4 Register - Uint16 ADCRESULT5; // ADC Result 5 Register - Uint16 ADCRESULT6; // ADC Result 6 Register - Uint16 ADCRESULT7; // ADC Result 7 Register - Uint16 ADCRESULT8; // ADC Result 8 Register - Uint16 ADCRESULT9; // ADC Result 9 Register - Uint16 ADCRESULT10; // ADC Result 10 Register - Uint16 ADCRESULT11; // ADC Result 11 Register - Uint16 ADCRESULT12; // ADC Result 12 Register - Uint16 ADCRESULT13; // ADC Result 13 Register - Uint16 ADCRESULT14; // ADC Result 14 Register - Uint16 ADCRESULT15; // ADC Result 15 Register - union ADCPPB1RESULT_REG ADCPPB1RESULT; // ADC Post Processing Block 1 Result Register - union ADCPPB2RESULT_REG ADCPPB2RESULT; // ADC Post Processing Block 2 Result Register - union ADCPPB3RESULT_REG ADCPPB3RESULT; // ADC Post Processing Block 3 Result Register - union ADCPPB4RESULT_REG ADCPPB4RESULT; // ADC Post Processing Block 4 Result Register -}; - -//--------------------------------------------------------------------------- -// ADC External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct ADC_RESULT_REGS AdcaResultRegs; -extern volatile struct ADC_RESULT_REGS AdcbResultRegs; -extern volatile struct ADC_RESULT_REGS AdccResultRegs; -extern volatile struct ADC_RESULT_REGS AdcdResultRegs; -extern volatile struct ADC_REGS AdcaRegs; -extern volatile struct ADC_REGS AdcbRegs; -extern volatile struct ADC_REGS AdccRegs; -extern volatile struct ADC_REGS AdcdRegs; -#endif -#ifdef CPU2 -extern volatile struct ADC_RESULT_REGS AdcaResultRegs; -extern volatile struct ADC_RESULT_REGS AdcbResultRegs; -extern volatile struct ADC_RESULT_REGS AdccResultRegs; -extern volatile struct ADC_RESULT_REGS AdcdResultRegs; -extern volatile struct ADC_REGS AdcaRegs; -extern volatile struct ADC_REGS AdcbRegs; -extern volatile struct ADC_REGS AdccRegs; -extern volatile struct ADC_REGS AdcdRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_analogsubsys.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_analogsubsys.h deleted file mode 100644 index b116e47d77..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_analogsubsys.h +++ /dev/null @@ -1,199 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_analogsubsys.h -// -// TITLE: ANALOGSUBSYS Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_ANALOGSUBSYS_H__ -#define __F2837xD_ANALOGSUBSYS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// ANALOGSUBSYS Individual Register Bit Definitions: - -struct INTOSC1TRIM_BITS { // bits description - Uint16 VALFINETRIM:12; // 11:0 Oscillator Value Fine Trim Bits - Uint16 rsvd1:4; // 15:12 Reserved - Uint16 rsvd2:8; // 23:16 Reserved - Uint16 rsvd3:8; // 31:24 Reserved -}; - -union INTOSC1TRIM_REG { - Uint32 all; - struct INTOSC1TRIM_BITS bit; -}; - -struct INTOSC2TRIM_BITS { // bits description - Uint16 VALFINETRIM:12; // 11:0 Oscillator Value Fine Trim Bits - Uint16 rsvd1:4; // 15:12 Reserved - Uint16 rsvd2:8; // 23:16 Reserved - Uint16 rsvd3:8; // 31:24 Reserved -}; - -union INTOSC2TRIM_REG { - Uint32 all; - struct INTOSC2TRIM_BITS bit; -}; - -struct TSNSCTL_BITS { // bits description - Uint16 ENABLE:1; // 0 Temperature Sensor Enable - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union TSNSCTL_REG { - Uint16 all; - struct TSNSCTL_BITS bit; -}; - -struct LOCK_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 TSNSCTL:1; // 3 Temperature Sensor Control Register Lock - Uint16 rsvd4:1; // 4 Reserved - Uint16 rsvd5:1; // 5 Reserved - Uint16 rsvd6:1; // 6 Reserved - Uint32 rsvd7:12; // 18:7 Reserved - Uint16 rsvd8:1; // 19 Reserved - Uint16 rsvd9:1; // 20 Reserved - Uint16 rsvd10:1; // 21 Reserved - Uint16 rsvd11:1; // 22 Reserved - Uint16 rsvd12:1; // 23 Reserved - Uint16 rsvd13:1; // 24 Reserved - Uint16 rsvd14:1; // 25 Reserved - Uint16 rsvd15:1; // 26 Reserved - Uint16 rsvd16:1; // 27 Reserved - Uint16 rsvd17:1; // 28 Reserved - Uint16 rsvd18:1; // 29 Reserved - Uint16 rsvd19:1; // 30 Reserved - Uint16 rsvd20:1; // 31 Reserved -}; - -union LOCK_REG { - Uint32 all; - struct LOCK_BITS bit; -}; - -struct ANAREFTRIMA_BITS { // bits description - Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim - Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim - Uint16 IREFTRIM:5; // 15:11 Reference Current Trim - Uint16 rsvd1:8; // 23:16 Reserved - Uint16 rsvd2:8; // 31:24 Reserved -}; - -union ANAREFTRIMA_REG { - Uint32 all; - struct ANAREFTRIMA_BITS bit; -}; - -struct ANAREFTRIMB_BITS { // bits description - Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim - Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim - Uint16 IREFTRIM:5; // 15:11 Reference Current Trim - Uint16 rsvd1:8; // 23:16 Reserved - Uint16 rsvd2:8; // 31:24 Reserved -}; - -union ANAREFTRIMB_REG { - Uint32 all; - struct ANAREFTRIMB_BITS bit; -}; - -struct ANAREFTRIMC_BITS { // bits description - Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim - Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim - Uint16 IREFTRIM:5; // 15:11 Reference Current Trim - Uint16 rsvd1:8; // 23:16 Reserved - Uint16 rsvd2:8; // 31:24 Reserved -}; - -union ANAREFTRIMC_REG { - Uint32 all; - struct ANAREFTRIMC_BITS bit; -}; - -struct ANAREFTRIMD_BITS { // bits description - Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim - Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim - Uint16 IREFTRIM:5; // 15:11 Reference Current Trim - Uint16 rsvd1:8; // 23:16 Reserved - Uint16 rsvd2:8; // 31:24 Reserved -}; - -union ANAREFTRIMD_REG { - Uint32 all; - struct ANAREFTRIMD_BITS bit; -}; - -struct ANALOG_SUBSYS_REGS { - Uint16 rsvd1[32]; // Reserved - union INTOSC1TRIM_REG INTOSC1TRIM; // Internal Oscillator 1 Trim Register - union INTOSC2TRIM_REG INTOSC2TRIM; // Internal Oscillator 2 Trim Register - Uint16 rsvd2[2]; // Reserved - union TSNSCTL_REG TSNSCTL; // Temperature Sensor Control Register - Uint16 rsvd3[7]; // Reserved - union LOCK_REG LOCK; // Lock Register - Uint16 rsvd4[6]; // Reserved - union ANAREFTRIMA_REG ANAREFTRIMA; // Analog Reference Trim A Register - union ANAREFTRIMB_REG ANAREFTRIMB; // Analog Reference Trim B Register - union ANAREFTRIMC_REG ANAREFTRIMC; // Analog Reference Trim C Register - union ANAREFTRIMD_REG ANAREFTRIMD; // Analog Reference Trim D Register - Uint16 rsvd5[10]; // Reserved -}; - -//--------------------------------------------------------------------------- -// ANALOGSUBSYS External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_can.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_can.h deleted file mode 100644 index ad625e4554..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_can.h +++ /dev/null @@ -1,612 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_can.h -// -// TITLE: CAN Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_CAN_H__ -#define __F2837xD_CAN_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CAN Individual Register Bit Definitions: - -struct CAN_CTL_BITS { // bits description - bp_16 Init:1; // 0 Initialization - bp_16 IE0:1; // 1 Interrupt line 0 Enable - bp_16 SIE:1; // 2 Status Change Interrupt Enable - bp_16 EIE:1; // 3 Error Interrupt Enable - bp_16 rsvd1:1; // 4 Reserved - bp_16 DAR:1; // 5 Disable Automatic Retransmission - bp_16 CCE:1; // 6 Configuration Change Enable - bp_16 Test:1; // 7 Test Mode Enable - bp_16 IDS:1; // 8 Interruption Debug Support Enable - bp_16 ABO:1; // 9 Auto-Bus-On Enable - bp_16 PMD:4; // 13:10 Parity on/off - bp_16 rsvd2:1; // 14 Reserved - bp_16 SWR:1; // 15 SW Reset Enable - bp_32 INITDBG:1; // 16 Debug Mode Status - bp_32 IE1:1; // 17 Interrupt line 1 Enable Disabled - bp_32 rsvd3:1; // 18 Reserved - bp_32 rsvd4:1; // 19 Reserved - bp_32 rsvd5:1; // 20 Reserved - bp_32 rsvd6:3; // 23:21 Reserved - bp_32 rsvd7:1; // 24 Reserved - bp_32 rsvd8:1; // 25 Reserved - bp_32 rsvd9:6; // 31:26 Reserved -}; - -union CAN_CTL_REG { - bp_32 all; - struct CAN_CTL_BITS bit; -}; - -struct CAN_ES_BITS { // bits description - bp_16 LEC:3; // 2:0 Last Error Code - bp_16 TxOk:1; // 3 Transmission status - bp_16 RxOk:1; // 4 Reception status - bp_16 EPass:1; // 5 Error Passive State - bp_16 EWarn:1; // 6 Warning State - bp_16 BOff:1; // 7 Bus-Off State - bp_16 PER:1; // 8 Parity Error Detected - bp_16 rsvd1:1; // 9 Reserved - bp_16 rsvd2:1; // 10 Reserved - bp_16 rsvd3:5; // 15:11 Reserved - bp_32 rsvd4:16; // 31:16 Reserved -}; - -union CAN_ES_REG { - bp_32 all; - struct CAN_ES_BITS bit; -}; - -struct CAN_ERRC_BITS { // bits description - bp_16 TEC:8; // 7:0 Transmit Error Counter - bp_16 REC:7; // 14:8 Receive Error Counter - bp_16 RP:1; // 15 Receive Error Passive - bp_32 rsvd1:16; // 31:16 Reserved -}; - -union CAN_ERRC_REG { - bp_32 all; - struct CAN_ERRC_BITS bit; -}; - -struct CAN_BTR_BITS { // bits description - bp_16 BRP:6; // 5:0 Baud Rate Prescaler - bp_16 SJW:2; // 7:6 Synchronization Jump Width - bp_16 TSEG1:4; // 11:8 Time segment - bp_16 TSEG2:3; // 14:12 Time segment - bp_16 rsvd1:1; // 15 Reserved - bp_32 BRPE:4; // 19:16 Baud Rate Prescaler Extension - bp_32 rsvd2:12; // 31:20 Reserved -}; - -union CAN_BTR_REG { - bp_32 all; - struct CAN_BTR_BITS bit; -}; - -struct CAN_INT_BITS { // bits description - bp_16 INT0ID:16; // 15:0 Interrupt Identifier - bp_32 INT1ID:8; // 23:16 Interrupt 1 Identifier - bp_32 rsvd1:8; // 31:24 Reserved -}; - -union CAN_INT_REG { - bp_32 all; - struct CAN_INT_BITS bit; -}; - -struct CAN_TEST_BITS { // bits description - bp_16 rsvd1:3; // 2:0 Reserved - bp_16 SILENT:1; // 3 Silent Mode - bp_16 LBACK:1; // 4 Loopback Mode - bp_16 TX:2; // 6:5 CANTX Pin Control - bp_16 RX:1; // 7 CANRX Pin Status - bp_16 EXL:1; // 8 External Loopback Mode - bp_16 RDA:1; // 9 RAM Direct Access Enable: - bp_16 rsvd2:6; // 15:10 Reserved - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union CAN_TEST_REG { - bp_32 all; - struct CAN_TEST_BITS bit; -}; - -struct CAN_PERR_BITS { // bits description - bp_16 MSG_NUM:8; // 7:0 Message Number - bp_16 WORD_NUM:3; // 10:8 Word Number - bp_16 rsvd1:5; // 15:11 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_PERR_REG { - bp_32 all; - struct CAN_PERR_BITS bit; -}; - -struct CAN_RAM_INIT_BITS { // bits description - bp_16 KEY0:1; // 0 KEY0 - bp_16 KEY1:1; // 1 KEY1 - bp_16 KEY2:1; // 2 KEY2 - bp_16 KEY3:1; // 3 KEY3 - bp_16 CAN_RAM_INIT:1; // 4 Initialize CAN Mailbox RAM - bp_16 RAM_INIT_DONE:1; // 5 CAN RAM initialization complete - bp_16 rsvd1:10; // 15:6 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_RAM_INIT_REG { - bp_32 all; - struct CAN_RAM_INIT_BITS bit; -}; - -struct CAN_GLB_INT_EN_BITS { // bits description - bp_16 GLBINT0_EN:1; // 0 Global Interrupt Enable for CAN INT0 - bp_16 GLBINT1_EN:1; // 1 Global Interrupt Enable for CAN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_GLB_INT_EN_REG { - bp_32 all; - struct CAN_GLB_INT_EN_BITS bit; -}; - -struct CAN_GLB_INT_FLG_BITS { // bits description - bp_16 INT0_FLG:1; // 0 Global Interrupt Flag for CAN INT0 - bp_16 INT1_FLG:1; // 1 Global Interrupt Flag for CAN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_GLB_INT_FLG_REG { - bp_32 all; - struct CAN_GLB_INT_FLG_BITS bit; -}; - -struct CAN_GLB_INT_CLR_BITS { // bits description - bp_16 INT0_FLG_CLR:1; // 0 Global Interrupt flag clear for CAN INT0 - bp_16 INT1_FLG_CLR:1; // 1 Global Interrupt flag clear for CAN INT1 - bp_16 rsvd1:14; // 15:2 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_GLB_INT_CLR_REG { - bp_32 all; - struct CAN_GLB_INT_CLR_BITS bit; -}; - -struct CAN_TXRQ_X_BITS { // bits description - bp_16 TxRqstReg1:2; // 1:0 Transmit Request Register 1 - bp_16 TxRqstReg2:2; // 3:2 Transmit Request Register 2 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_TXRQ_X_REG { - bp_32 all; - struct CAN_TXRQ_X_BITS bit; -}; - -struct CAN_NDAT_X_BITS { // bits description - bp_16 NewDatReg1:2; // 1:0 New Data Register 1 - bp_16 NewDatReg2:2; // 3:2 New Data Register 2 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_NDAT_X_REG { - bp_32 all; - struct CAN_NDAT_X_BITS bit; -}; - -struct CAN_IPEN_X_BITS { // bits description - bp_16 IntPndReg1:2; // 1:0 Interrupt Pending Register 1 - bp_16 IntPndReg2:2; // 3:2 Interrupt Pending Register 2 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_IPEN_X_REG { - bp_32 all; - struct CAN_IPEN_X_BITS bit; -}; - -struct CAN_MVAL_X_BITS { // bits description - bp_16 MsgValReg1:2; // 1:0 Message Valid Register 1 - bp_16 MsgValReg2:2; // 3:2 Message Valid Register 2 - bp_16 rsvd1:12; // 15:4 Reserved - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_MVAL_X_REG { - bp_32 all; - struct CAN_MVAL_X_BITS bit; -}; - -struct CAN_IF1CMD_BITS { // bits description - bp_16 MSG_NUM:8; // 7:0 Message Number - bp_16 rsvd1:6; // 13:8 Reserved - bp_16 rsvd2:1; // 14 Reserved - bp_16 Busy:1; // 15 Busy Flag - bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 - bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 - bp_32 TXRQST:1; // 18 Access Transmission Request Bit - bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit - bp_32 Control:1; // 20 Access Control Bits - bp_32 Arb:1; // 21 Access Arbitration Bits - bp_32 Mask:1; // 22 Access Mask Bits - bp_32 DIR:1; // 23 Write/Read Direction - bp_32 rsvd3:8; // 31:24 Reserved -}; - -union CAN_IF1CMD_REG { - bp_32 all; - struct CAN_IF1CMD_BITS bit; -}; - -struct CAN_IF1MSK_BITS { // bits description - bp_32 Msk:29; // 28:0 Identifier Mask - bp_32 rsvd1:1; // 29 Reserved - bp_32 MDir:1; // 30 Mask Message Direction - bp_32 MXtd:1; // 31 Mask Extended Identifier -}; - -union CAN_IF1MSK_REG { - bp_32 all; - struct CAN_IF1MSK_BITS bit; -}; - -struct CAN_IF1ARB_BITS { // bits description - bp_32 ID:29; // 28:0 ` - bp_32 Dir:1; // 29 Message Direction - bp_32 Xtd:1; // 30 Extended Identifier - bp_32 MsgVal:1; // 31 Message Valid -}; - -union CAN_IF1ARB_REG { - bp_32 all; - struct CAN_IF1ARB_BITS bit; -}; - -struct CAN_IF1MCTL_BITS { // bits description - bp_16 DLC:4; // 3:0 Data length code - bp_16 rsvd1:3; // 6:4 Reserved - bp_16 EoB:1; // 7 End of Block - bp_16 TxRqst:1; // 8 Transmit Request - bp_16 RmtEn:1; // 9 Remote Enable - bp_16 RxIE:1; // 10 Receive Interrupt Enable - bp_16 TxIE:1; // 11 Transmit Interrupt Enable - bp_16 UMask:1; // 12 Use Acceptance Mask - bp_16 IntPnd:1; // 13 Interrupt Pending - bp_16 MsgLst:1; // 14 Message Lost - bp_16 NewDat:1; // 15 New Data - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_IF1MCTL_REG { - bp_32 all; - struct CAN_IF1MCTL_BITS bit; -}; - -struct CAN_IF1DATA_BITS { // bits description - bp_16 Data_0:8; // 7:0 Data Byte 0 - bp_16 Data_1:8; // 15:8 Data Byte 1 - bp_32 Data_2:8; // 23:16 Data Byte 2 - bp_32 Data_3:8; // 31:24 Data Byte 3 -}; - -union CAN_IF1DATA_REG { - bp_32 all; - struct CAN_IF1DATA_BITS bit; -}; - -struct CAN_IF1DATB_BITS { // bits description - bp_16 Data_4:8; // 7:0 Data Byte 4 - bp_16 Data_5:8; // 15:8 Data Byte 5 - bp_32 Data_6:8; // 23:16 Data Byte 6 - bp_32 Data_7:8; // 31:24 Data Byte 7 -}; - -union CAN_IF1DATB_REG { - bp_32 all; - struct CAN_IF1DATB_BITS bit; -}; - -struct CAN_IF2CMD_BITS { // bits description - bp_16 MSG_NUM:8; // 7:0 Message Number - bp_16 rsvd1:6; // 13:8 Reserved - bp_16 rsvd2:1; // 14 Reserved - bp_16 Busy:1; // 15 Busy Flag - bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 - bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 - bp_32 TxRqst:1; // 18 Access Transmission Request Bit - bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit - bp_32 Control:1; // 20 Access Control Bits - bp_32 Arb:1; // 21 Access Arbitration Bits - bp_32 Mask:1; // 22 Access Mask Bits - bp_32 DIR:1; // 23 Write/Read Direction - bp_32 rsvd3:8; // 31:24 Reserved -}; - -union CAN_IF2CMD_REG { - bp_32 all; - struct CAN_IF2CMD_BITS bit; -}; - -struct CAN_IF2MSK_BITS { // bits description - bp_32 Msk:29; // 28:0 Identifier Mask - bp_32 rsvd1:1; // 29 Reserved - bp_32 MDir:1; // 30 Mask Message Direction - bp_32 MXtd:1; // 31 Mask Extended Identifier -}; - -union CAN_IF2MSK_REG { - bp_32 all; - struct CAN_IF2MSK_BITS bit; -}; - -struct CAN_IF2ARB_BITS { // bits description - bp_32 ID:29; // 28:0 Message Identifier - bp_32 Dir:1; // 29 Message Direction - bp_32 Xtd:1; // 30 Extended Identifier - bp_32 MsgVal:1; // 31 Message Valid -}; - -union CAN_IF2ARB_REG { - bp_32 all; - struct CAN_IF2ARB_BITS bit; -}; - -struct CAN_IF2MCTL_BITS { // bits description - bp_16 DLC:4; // 3:0 Data length code - bp_16 rsvd1:3; // 6:4 Reserved - bp_16 EoB:1; // 7 End of Block - bp_16 TxRqst:1; // 8 Transmit Request - bp_16 RmtEn:1; // 9 Remote Enable - bp_16 RxIE:1; // 10 Receive Interrupt Enable - bp_16 TxIE:1; // 11 Transmit Interrupt Enable - bp_16 UMask:1; // 12 Use Acceptance Mask - bp_16 IntPnd:1; // 13 Interrupt Pending - bp_16 MsgLst:1; // 14 Message Lost - bp_16 NewDat:1; // 15 New Data - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_IF2MCTL_REG { - bp_32 all; - struct CAN_IF2MCTL_BITS bit; -}; - -struct CAN_IF2DATA_BITS { // bits description - bp_16 Data_0:8; // 7:0 Data Byte 0 - bp_16 Data_1:8; // 15:8 Data Byte 1 - bp_32 Data_2:8; // 23:16 Data Byte 2 - bp_32 Data_3:8; // 31:24 Data Byte 3 -}; - -union CAN_IF2DATA_REG { - bp_32 all; - struct CAN_IF2DATA_BITS bit; -}; - -struct CAN_IF2DATB_BITS { // bits description - bp_16 Data_4:8; // 7:0 Data Byte 4 - bp_16 Data_5:8; // 15:8 Data Byte 5 - bp_32 Data_6:8; // 23:16 Data Byte 6 - bp_32 Data_7:8; // 31:24 Data Byte 7 -}; - -union CAN_IF2DATB_REG { - bp_32 all; - struct CAN_IF2DATB_BITS bit; -}; - -struct CAN_IF3OBS_BITS { // bits description - bp_16 Mask:1; // 0 Mask data read observation - bp_16 Arb:1; // 1 Arbitration data read observation - bp_16 Ctrl:1; // 2 Ctrl read observation - bp_16 Data_A:1; // 3 Data A read observation - bp_16 Data_B:1; // 4 Data B read observation - bp_16 rsvd1:3; // 7:5 Reserved - bp_16 IF3SM:1; // 8 IF3 Status of Mask data read access - bp_16 IF3SA:1; // 9 IF3 Status of Arbitration data read access - bp_16 IF3SC:1; // 10 IF3 Status of Control bits read access - bp_16 IF3SDA:1; // 11 IF3 Status of Data A read access - bp_16 IF3SDB:1; // 12 IF3 Status of Data B read access - bp_16 rsvd2:2; // 14:13 Reserved - bp_16 IF3Upd:1; // 15 IF3 Update Data - bp_32 rsvd3:16; // 31:16 Reserved -}; - -union CAN_IF3OBS_REG { - bp_32 all; - struct CAN_IF3OBS_BITS bit; -}; - -struct CAN_IF3MSK_BITS { // bits description - bp_32 Msk:29; // 28:0 Mask - bp_32 rsvd1:1; // 29 Reserved - bp_32 MDir:1; // 30 Mask Message Direction - bp_32 MXtd:1; // 31 Mask Extended Identifier -}; - -union CAN_IF3MSK_REG { - bp_32 all; - struct CAN_IF3MSK_BITS bit; -}; - -struct CAN_IF3ARB_BITS { // bits description - bp_32 ID:29; // 28:0 Message Identifier - bp_32 Dir:1; // 29 Message Direction - bp_32 Xtd:1; // 30 Extended Identifier - bp_32 MsgVal:1; // 31 Message Valid -}; - -union CAN_IF3ARB_REG { - bp_32 all; - struct CAN_IF3ARB_BITS bit; -}; - -struct CAN_IF3MCTL_BITS { // bits description - bp_16 DLC:4; // 3:0 Data length code - bp_16 rsvd1:3; // 6:4 Reserved - bp_16 EoB:1; // 7 End of Block - bp_16 TxRqst:1; // 8 Transmit Request - bp_16 RmtEn:1; // 9 Remote Enable - bp_16 RxIE:1; // 10 Receive Interrupt Enable - bp_16 TxIE:1; // 11 Transmit Interrupt Enable - bp_16 UMask:1; // 12 Use Acceptance Mask - bp_16 IntPnd:1; // 13 Interrupt Pending - bp_16 MsgLst:1; // 14 Message Lost - bp_16 NewDat:1; // 15 New Data - bp_32 rsvd2:16; // 31:16 Reserved -}; - -union CAN_IF3MCTL_REG { - bp_32 all; - struct CAN_IF3MCTL_BITS bit; -}; - -struct CAN_IF3DATA_BITS { // bits description - bp_16 Data_0:8; // 7:0 Data Byte 0 - bp_16 Data_1:8; // 15:8 Data Byte 1 - bp_32 Data_2:8; // 23:16 Data Byte 2 - bp_32 Data_3:8; // 31:24 Data Byte 3 -}; - -union CAN_IF3DATA_REG { - bp_32 all; - struct CAN_IF3DATA_BITS bit; -}; - -struct CAN_IF3DATB_BITS { // bits description - bp_16 Data_4:8; // 7:0 Data Byte 4 - bp_16 Data_5:8; // 15:8 Data Byte 5 - bp_32 Data_6:8; // 23:16 Data Byte 6 - bp_32 Data_7:8; // 31:24 Data Byte 7 -}; - -union CAN_IF3DATB_REG { - bp_32 all; - struct CAN_IF3DATB_BITS bit; -}; - -struct CAN_REGS { - union CAN_CTL_REG CAN_CTL; // CAN Control Register - union CAN_ES_REG CAN_ES; // Error and Status Register - union CAN_ERRC_REG CAN_ERRC; // Error Counter Register - union CAN_BTR_REG CAN_BTR; // Bit Timing Register - union CAN_INT_REG CAN_INT; // Interrupt Register - union CAN_TEST_REG CAN_TEST; // Test Register - uint32_t rsvd1[2]; // Reserved - union CAN_PERR_REG CAN_PERR; // CAN Parity Error Code Register - uint32_t rsvd2[16]; // Reserved - union CAN_RAM_INIT_REG CAN_RAM_INIT; // CAN RAM Initialization Register - uint32_t rsvd3[6]; // Reserved - union CAN_GLB_INT_EN_REG CAN_GLB_INT_EN; // CAN Global Interrupt Enable Register - union CAN_GLB_INT_FLG_REG CAN_GLB_INT_FLG; // CAN Global Interrupt Flag Register - union CAN_GLB_INT_CLR_REG CAN_GLB_INT_CLR; // CAN Global Interrupt Clear Register - uint32_t rsvd4[18]; // Reserved - bp_32 CAN_ABOTR; // Auto-Bus-On Time Register - union CAN_TXRQ_X_REG CAN_TXRQ_X; // CAN Transmission Request Register - bp_32 CAN_TXRQ_21; // CAN Transmission Request 2_1 Register - uint32_t rsvd5[6]; // Reserved - union CAN_NDAT_X_REG CAN_NDAT_X; // CAN New Data Register - bp_32 CAN_NDAT_21; // CAN New Data 2_1 Register - uint32_t rsvd6[6]; // Reserved - union CAN_IPEN_X_REG CAN_IPEN_X; // CAN Interrupt Pending Register - bp_32 CAN_IPEN_21; // CAN Interrupt Pending 2_1 Register - uint32_t rsvd7[6]; // Reserved - union CAN_MVAL_X_REG CAN_MVAL_X; // CAN Message Valid Register - bp_32 CAN_MVAL_21; // CAN Message Valid 2_1 Register - uint32_t rsvd8[8]; // Reserved - bp_32 CAN_IP_MUX21; // CAN Interrupt Multiplexer 2_1 Register - uint32_t rsvd9[18]; // Reserved - union CAN_IF1CMD_REG CAN_IF1CMD; // IF1 Command Register - union CAN_IF1MSK_REG CAN_IF1MSK; // IF1 Mask Register - union CAN_IF1ARB_REG CAN_IF1ARB; // IF1 Arbitration Register - union CAN_IF1MCTL_REG CAN_IF1MCTL; // IF1 Message Control Register - union CAN_IF1DATA_REG CAN_IF1DATA; // IF1 Data A Register - union CAN_IF1DATB_REG CAN_IF1DATB; // IF1 Data B Register - uint32_t rsvd10[4]; // Reserved - union CAN_IF2CMD_REG CAN_IF2CMD; // IF2 Command Register - union CAN_IF2MSK_REG CAN_IF2MSK; // IF2 Mask Register - union CAN_IF2ARB_REG CAN_IF2ARB; // IF2 Arbitration Register - union CAN_IF2MCTL_REG CAN_IF2MCTL; // IF2 Message Control Register - union CAN_IF2DATA_REG CAN_IF2DATA; // IF2 Data A Register - union CAN_IF2DATB_REG CAN_IF2DATB; // IF2 Data B Register - uint32_t rsvd11[4]; // Reserved - union CAN_IF3OBS_REG CAN_IF3OBS; // IF3 Observation Register - union CAN_IF3MSK_REG CAN_IF3MSK; // IF3 Mask Register - union CAN_IF3ARB_REG CAN_IF3ARB; // IF3 Arbitration Register - union CAN_IF3MCTL_REG CAN_IF3MCTL; // IF3 Message Control Register - union CAN_IF3DATA_REG CAN_IF3DATA; // IF3 Data A Register - union CAN_IF3DATB_REG CAN_IF3DATB; // IF3 Data B Register - uint32_t rsvd12[4]; // Reserved - bp_32 CAN_IF3UPD; // IF3 Update Enable Register -}; - -//--------------------------------------------------------------------------- -// CAN External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct CAN_REGS CanaRegs; -extern volatile struct CAN_REGS CanbRegs; -#endif -#ifdef CPU2 -extern volatile struct CAN_REGS CanaRegs; -extern volatile struct CAN_REGS CanbRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cla.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cla.h deleted file mode 100644 index 683333074c..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cla.h +++ /dev/null @@ -1,305 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_cla.h -// -// TITLE: CLA Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_CLA_H__ -#define __F2837xD_CLA_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CLA Individual Register Bit Definitions: - -struct MCTL_BITS { // bits description - Uint16 HARDRESET:1; // 0 Hard Reset - Uint16 SOFTRESET:1; // 1 Soft Reset - Uint16 IACKE:1; // 2 IACK enable - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union MCTL_REG { - Uint16 all; - struct MCTL_BITS bit; -}; - -struct MIFR_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Flag - Uint16 INT2:1; // 1 Task 2 Interrupt Flag - Uint16 INT3:1; // 2 Task 3 Interrupt Flag - Uint16 INT4:1; // 3 Task 4 Interrupt Flag - Uint16 INT5:1; // 4 Task 5 Interrupt Flag - Uint16 INT6:1; // 5 Task 6 Interrupt Flag - Uint16 INT7:1; // 6 Task 7 Interrupt Flag - Uint16 INT8:1; // 7 Task 8 Interrupt Flag - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIFR_REG { - Uint16 all; - struct MIFR_BITS bit; -}; - -struct MIOVF_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag - Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag - Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag - Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag - Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag - Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag - Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag - Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIOVF_REG { - Uint16 all; - struct MIOVF_BITS bit; -}; - -struct MIFRC_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Force - Uint16 INT2:1; // 1 Task 2 Interrupt Force - Uint16 INT3:1; // 2 Task 3 Interrupt Force - Uint16 INT4:1; // 3 Task 4 Interrupt Force - Uint16 INT5:1; // 4 Task 5 Interrupt Force - Uint16 INT6:1; // 5 Task 6 Interrupt Force - Uint16 INT7:1; // 6 Task 7 Interrupt Force - Uint16 INT8:1; // 7 Task 8 Interrupt Force - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIFRC_REG { - Uint16 all; - struct MIFRC_BITS bit; -}; - -struct MICLR_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Flag Clear - Uint16 INT2:1; // 1 Task 2 Interrupt Flag Clear - Uint16 INT3:1; // 2 Task 3 Interrupt Flag Clear - Uint16 INT4:1; // 3 Task 4 Interrupt Flag Clear - Uint16 INT5:1; // 4 Task 5 Interrupt Flag Clear - Uint16 INT6:1; // 5 Task 6 Interrupt Flag Clear - Uint16 INT7:1; // 6 Task 7 Interrupt Flag Clear - Uint16 INT8:1; // 7 Task 8 Interrupt Flag Clear - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MICLR_REG { - Uint16 all; - struct MICLR_BITS bit; -}; - -struct MICLROVF_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag Clear - Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag Clear - Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag Clear - Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag Clear - Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag Clear - Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag Clear - Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag Clear - Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag Clear - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MICLROVF_REG { - Uint16 all; - struct MICLROVF_BITS bit; -}; - -struct MIER_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Interrupt Enable - Uint16 INT2:1; // 1 Task 2 Interrupt Enable - Uint16 INT3:1; // 2 Task 3 Interrupt Enable - Uint16 INT4:1; // 3 Task 4 Interrupt Enable - Uint16 INT5:1; // 4 Task 5 Interrupt Enable - Uint16 INT6:1; // 5 Task 6 Interrupt Enable - Uint16 INT7:1; // 6 Task 7 Interrupt Enable - Uint16 INT8:1; // 7 Task 8 Interrupt Enable - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIER_REG { - Uint16 all; - struct MIER_BITS bit; -}; - -struct MIRUN_BITS { // bits description - Uint16 INT1:1; // 0 Task 1 Run Status - Uint16 INT2:1; // 1 Task 2 Run Status - Uint16 INT3:1; // 2 Task 3 Run Status - Uint16 INT4:1; // 3 Task 4 Run Status - Uint16 INT5:1; // 4 Task 5 Run Status - Uint16 INT6:1; // 5 Task 6 Run Status - Uint16 INT7:1; // 6 Task 7 Run Status - Uint16 INT8:1; // 7 Task 8 Run Status - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union MIRUN_REG { - Uint16 all; - struct MIRUN_BITS bit; -}; - -struct _MSTF_BITS { // bits description - Uint16 LVF:1; // 0 Latched Overflow Flag - Uint16 LUF:1; // 1 Latched Underflow Flag - Uint16 NF:1; // 2 Negative Float Flag - Uint16 ZF:1; // 3 Zero Float Flag - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 TF:1; // 6 Test Flag - Uint16 rsvd2:2; // 8:7 Reserved - Uint16 RNDF32:1; // 9 Round 32-bit Floating-Point Mode - Uint16 rsvd3:1; // 10 Reserved - Uint16 MEALLOW:1; // 11 MEALLOW Status - Uint32 _RPC:16; // 27:12 Return PC - Uint16 rsvd4:4; // 31:28 Reserved -}; - -union _MSTF_REG { - Uint32 all; - struct _MSTF_BITS bit; -}; - -union MR_REG { - Uint32 i32; - float f32; -}; - -struct CLA_REGS { - Uint16 MVECT1; // Task Interrupt Vector - Uint16 MVECT2; // Task Interrupt Vector - Uint16 MVECT3; // Task Interrupt Vector - Uint16 MVECT4; // Task Interrupt Vector - Uint16 MVECT5; // Task Interrupt Vector - Uint16 MVECT6; // Task Interrupt Vector - Uint16 MVECT7; // Task Interrupt Vector - Uint16 MVECT8; // Task Interrupt Vector - Uint16 rsvd1[8]; // Reserved - union MCTL_REG MCTL; // Control Register - Uint16 rsvd2[15]; // Reserved - union MIFR_REG MIFR; // Interrupt Flag Register - union MIOVF_REG MIOVF; // Interrupt Overflow Flag Register - union MIFRC_REG MIFRC; // Interrupt Force Register - union MICLR_REG MICLR; // Interrupt Flag Clear Register - union MICLROVF_REG MICLROVF; // Interrupt Overflow Flag Clear Register - union MIER_REG MIER; // Interrupt Enable Register - union MIRUN_REG MIRUN; // Interrupt Run Status Register - Uint16 rsvd3; // Reserved - Uint16 _MPC; // CLA Program Counter - Uint16 rsvd4; // Reserved - Uint16 _MAR0; // CLA Auxiliary Register 0 - Uint16 _MAR1; // CLA Auxiliary Register 1 - Uint16 rsvd5[2]; // Reserved - union _MSTF_REG _MSTF; // CLA Floating-Point Status Register - union MR_REG _MR0; // CLA Floating-Point Result Register 0 - Uint16 rsvd6[2]; // Reserved - union MR_REG _MR1; // CLA Floating-Point Result Register 1 - Uint16 rsvd7[2]; // Reserved - union MR_REG _MR2; // CLA Floating-Point Result Register 2 - Uint16 rsvd8[2]; // Reserved - union MR_REG _MR3; // CLA Floating-Point Result Register 3 -}; - -struct SOFTINTEN_BITS { // bits description - Uint16 TASK1:1; // 0 Task 1 Software Interrupt Enable - Uint16 TASK2:1; // 1 Task 2 Software Interrupt Enable - Uint16 TASK3:1; // 2 Task 3 Software Interrupt Enable - Uint16 TASK4:1; // 3 Task 4 Software Interrupt Enable - Uint16 TASK5:1; // 4 Task 5 Software Interrupt Enable - Uint16 TASK6:1; // 5 Task 6 Software Interrupt Enable - Uint16 TASK7:1; // 6 Task 7 Software Interrupt Enable - Uint16 TASK8:1; // 7 Task 8 Software Interrupt Enable - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SOFTINTEN_REG { - Uint32 all; - struct SOFTINTEN_BITS bit; -}; - -struct SOFTINTFRC_BITS { // bits description - Uint16 TASK1:1; // 0 Task 1 Software Interrupt Force - Uint16 TASK2:1; // 1 Task 2 Software Interrupt Force - Uint16 TASK3:1; // 2 Task 3 Software Interrupt Force - Uint16 TASK4:1; // 3 Task 4 Software Interrupt Force - Uint16 TASK5:1; // 4 Task 5 Software Interrupt Force - Uint16 TASK6:1; // 5 Task 6 Software Interrupt Force - Uint16 TASK7:1; // 6 Task 7 Software Interrupt Force - Uint16 TASK8:1; // 7 Task 8 Software Interrupt Force - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SOFTINTFRC_REG { - Uint32 all; - struct SOFTINTFRC_BITS bit; -}; - -struct CLA_SOFTINT_REGS { - union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register - union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register -}; - -//--------------------------------------------------------------------------- -// CLA External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; -extern volatile struct CLA_REGS Cla1Regs; -#endif -#ifdef CPU2 -extern volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; -extern volatile struct CLA_REGS Cla1Regs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cmpss.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cmpss.h deleted file mode 100644 index 51b595b01c..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cmpss.h +++ /dev/null @@ -1,310 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_cmpss.h -// -// TITLE: CMPSS Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_CMPSS_H__ -#define __F2837xD_CMPSS_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CMPSS Individual Register Bit Definitions: - -struct COMPCTL_BITS { // bits description - Uint16 COMPHSOURCE:1; // 0 High Comparator Source Select - Uint16 COMPHINV:1; // 1 High Comparator Invert Select - Uint16 CTRIPHSEL:2; // 3:2 High Comparator Trip Select - Uint16 CTRIPOUTHSEL:2; // 5:4 High Comparator Trip Output Select - Uint16 ASYNCHEN:1; // 6 High Comparator Asynchronous Path Enable - Uint16 rsvd1:1; // 7 Reserved - Uint16 COMPLSOURCE:1; // 8 Low Comparator Source Select - Uint16 COMPLINV:1; // 9 Low Comparator Invert Select - Uint16 CTRIPLSEL:2; // 11:10 Low Comparator Trip Select - Uint16 CTRIPOUTLSEL:2; // 13:12 Low Comparator Trip Output Select - Uint16 ASYNCLEN:1; // 14 Low Comparator Asynchronous Path Enable - Uint16 COMPDACE:1; // 15 Comparator/DAC Enable -}; - -union COMPCTL_REG { - Uint16 all; - struct COMPCTL_BITS bit; -}; - -struct COMPHYSCTL_BITS { // bits description - Uint16 COMPHYS:3; // 2:0 Comparator Hysteresis Trim - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union COMPHYSCTL_REG { - Uint16 all; - struct COMPHYSCTL_BITS bit; -}; - -struct COMPSTS_BITS { // bits description - Uint16 COMPHSTS:1; // 0 High Comparator Status - Uint16 COMPHLATCH:1; // 1 High Comparator Latched Status - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 COMPLSTS:1; // 8 Low Comparator Status - Uint16 COMPLLATCH:1; // 9 Low Comparator Latched Status - Uint16 rsvd2:6; // 15:10 Reserved -}; - -union COMPSTS_REG { - Uint16 all; - struct COMPSTS_BITS bit; -}; - -struct COMPSTSCLR_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 HLATCHCLR:1; // 1 High Comparator Latched Status Clear - Uint16 HSYNCCLREN:1; // 2 High Comparator PWMSYNC Clear Enable - Uint16 rsvd2:6; // 8:3 Reserved - Uint16 LLATCHCLR:1; // 9 Low Comparator Latched Status Clear - Uint16 LSYNCCLREN:1; // 10 Low Comparator PWMSYNC Clear Enable - Uint16 rsvd3:5; // 15:11 Reserved -}; - -union COMPSTSCLR_REG { - Uint16 all; - struct COMPSTSCLR_BITS bit; -}; - -struct COMPDACCTL_BITS { // bits description - Uint16 DACSOURCE:1; // 0 DAC Source Control - Uint16 RAMPSOURCE:4; // 4:1 Ramp Generator Source Control - Uint16 SELREF:1; // 5 DAC Reference Select - Uint16 RAMPLOADSEL:1; // 6 Ramp Load Select - Uint16 SWLOADSEL:1; // 7 Software Load Select - Uint16 rsvd1:6; // 13:8 Reserved - Uint16 FREESOFT:2; // 15:14 Free/Soft Emulation Bits -}; - -union COMPDACCTL_REG { - Uint16 all; - struct COMPDACCTL_BITS bit; -}; - -struct DACHVALS_BITS { // bits description - Uint16 DACVAL:12; // 11:0 DAC Value Control - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACHVALS_REG { - Uint16 all; - struct DACHVALS_BITS bit; -}; - -struct DACHVALA_BITS { // bits description - Uint16 DACVAL:12; // 11:0 DAC Value Control - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACHVALA_REG { - Uint16 all; - struct DACHVALA_BITS bit; -}; - -struct DACLVALS_BITS { // bits description - Uint16 DACVAL:12; // 11:0 DAC Value Control - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACLVALS_REG { - Uint16 all; - struct DACLVALS_BITS bit; -}; - -struct DACLVALA_BITS { // bits description - Uint16 DACVAL:12; // 11:0 DAC Value Control - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACLVALA_REG { - Uint16 all; - struct DACLVALA_BITS bit; -}; - -struct RAMPDLYA_BITS { // bits description - Uint16 DELAY:13; // 12:0 Ramp Delay Value - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union RAMPDLYA_REG { - Uint16 all; - struct RAMPDLYA_BITS bit; -}; - -struct RAMPDLYS_BITS { // bits description - Uint16 DELAY:13; // 12:0 Ramp Delay Value - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union RAMPDLYS_REG { - Uint16 all; - struct RAMPDLYS_BITS bit; -}; - -struct CTRIPLFILCTL_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 SAMPWIN:5; // 8:4 Sample Window - Uint16 THRESH:5; // 13:9 Majority Voting Threshold - Uint16 rsvd2:1; // 14 Reserved - Uint16 FILINIT:1; // 15 Filter Initialization Bit -}; - -union CTRIPLFILCTL_REG { - Uint16 all; - struct CTRIPLFILCTL_BITS bit; -}; - -struct CTRIPLFILCLKCTL_BITS { // bits description - Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union CTRIPLFILCLKCTL_REG { - Uint16 all; - struct CTRIPLFILCLKCTL_BITS bit; -}; - -struct CTRIPHFILCTL_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 SAMPWIN:5; // 8:4 Sample Window - Uint16 THRESH:5; // 13:9 Majority Voting Threshold - Uint16 rsvd2:1; // 14 Reserved - Uint16 FILINIT:1; // 15 Filter Initialization Bit -}; - -union CTRIPHFILCTL_REG { - Uint16 all; - struct CTRIPHFILCTL_BITS bit; -}; - -struct CTRIPHFILCLKCTL_BITS { // bits description - Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union CTRIPHFILCLKCTL_REG { - Uint16 all; - struct CTRIPHFILCLKCTL_BITS bit; -}; - -struct COMPLOCK_BITS { // bits description - Uint16 COMPCTL:1; // 0 COMPCTL Lock - Uint16 COMPHYSCTL:1; // 1 COMPHYSCTL Lock - Uint16 DACCTL:1; // 2 DACCTL Lock - Uint16 CTRIP:1; // 3 CTRIP Lock - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:11; // 15:5 Reserved -}; - -union COMPLOCK_REG { - Uint16 all; - struct COMPLOCK_BITS bit; -}; - -struct CMPSS_REGS { - union COMPCTL_REG COMPCTL; // CMPSS Comparator Control Register - union COMPHYSCTL_REG COMPHYSCTL; // CMPSS Comparator Hysteresis Control Register - union COMPSTS_REG COMPSTS; // CMPSS Comparator Status Register - union COMPSTSCLR_REG COMPSTSCLR; // CMPSS Comparator Status Clear Register - union COMPDACCTL_REG COMPDACCTL; // CMPSS DAC Control Register - Uint16 rsvd1; // Reserved - union DACHVALS_REG DACHVALS; // CMPSS High DAC Value Shadow Register - union DACHVALA_REG DACHVALA; // CMPSS High DAC Value Active Register - Uint16 RAMPMAXREFA; // CMPSS Ramp Max Reference Active Register - Uint16 rsvd2; // Reserved - Uint16 RAMPMAXREFS; // CMPSS Ramp Max Reference Shadow Register - Uint16 rsvd3; // Reserved - Uint16 RAMPDECVALA; // CMPSS Ramp Decrement Value Active Register - Uint16 rsvd4; // Reserved - Uint16 RAMPDECVALS; // CMPSS Ramp Decrement Value Shadow Register - Uint16 rsvd5; // Reserved - Uint16 RAMPSTS; // CMPSS Ramp Status Register - Uint16 rsvd6; // Reserved - union DACLVALS_REG DACLVALS; // CMPSS Low DAC Value Shadow Register - union DACLVALA_REG DACLVALA; // CMPSS Low DAC Value Active Register - union RAMPDLYA_REG RAMPDLYA; // CMPSS Ramp Delay Active Register - union RAMPDLYS_REG RAMPDLYS; // CMPSS Ramp Delay Shadow Register - union CTRIPLFILCTL_REG CTRIPLFILCTL; // CTRIPL Filter Control Register - union CTRIPLFILCLKCTL_REG CTRIPLFILCLKCTL; // CTRIPL Filter Clock Control Register - union CTRIPHFILCTL_REG CTRIPHFILCTL; // CTRIPH Filter Control Register - union CTRIPHFILCLKCTL_REG CTRIPHFILCLKCTL; // CTRIPH Filter Clock Control Register - union COMPLOCK_REG COMPLOCK; // CMPSS Lock Register - Uint16 rsvd7[5]; // Reserved -}; - -//--------------------------------------------------------------------------- -// CMPSS External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct CMPSS_REGS Cmpss1Regs; -extern volatile struct CMPSS_REGS Cmpss2Regs; -extern volatile struct CMPSS_REGS Cmpss3Regs; -extern volatile struct CMPSS_REGS Cmpss4Regs; -extern volatile struct CMPSS_REGS Cmpss5Regs; -extern volatile struct CMPSS_REGS Cmpss6Regs; -extern volatile struct CMPSS_REGS Cmpss7Regs; -extern volatile struct CMPSS_REGS Cmpss8Regs; -#endif -#ifdef CPU2 -extern volatile struct CMPSS_REGS Cmpss1Regs; -extern volatile struct CMPSS_REGS Cmpss2Regs; -extern volatile struct CMPSS_REGS Cmpss3Regs; -extern volatile struct CMPSS_REGS Cmpss4Regs; -extern volatile struct CMPSS_REGS Cmpss5Regs; -extern volatile struct CMPSS_REGS Cmpss6Regs; -extern volatile struct CMPSS_REGS Cmpss7Regs; -extern volatile struct CMPSS_REGS Cmpss8Regs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cputimer.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cputimer.h deleted file mode 100644 index f822f516e5..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_cputimer.h +++ /dev/null @@ -1,141 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_cputimer.h -// -// TITLE: CPUTIMER Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_CPUTIMER_H__ -#define __F2837xD_CPUTIMER_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// CPUTIMER Individual Register Bit Definitions: - -struct TIM_BITS { // bits description - Uint16 LSW:16; // 15:0 CPU-Timer Counter Registers - Uint16 MSW:16; // 31:16 CPU-Timer Counter Registers High -}; - -union TIM_REG { - Uint32 all; - struct TIM_BITS bit; -}; - -struct PRD_BITS { // bits description - Uint16 LSW:16; // 15:0 CPU-Timer Period Registers - Uint16 MSW:16; // 31:16 CPU-Timer Period Registers High -}; - -union PRD_REG { - Uint32 all; - struct PRD_BITS bit; -}; - -struct TCR_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 TSS:1; // 4 CPU-Timer stop status bit. - Uint16 TRB:1; // 5 Timer reload - Uint16 rsvd2:4; // 9:6 Reserved - Uint16 SOFT:1; // 10 Emulation modes - Uint16 FREE:1; // 11 Emulation modes - Uint16 rsvd3:2; // 13:12 Reserved - Uint16 TIE:1; // 14 CPU-Timer Interrupt Enable. - Uint16 TIF:1; // 15 CPU-Timer Interrupt Flag. -}; - -union TCR_REG { - Uint16 all; - struct TCR_BITS bit; -}; - -struct TPR_BITS { // bits description - Uint16 TDDR:8; // 7:0 CPU-Timer Divide-Down. - Uint16 PSC:8; // 15:8 CPU-Timer Prescale Counter. -}; - -union TPR_REG { - Uint16 all; - struct TPR_BITS bit; -}; - -struct TPRH_BITS { // bits description - Uint16 TDDRH:8; // 7:0 CPU-Timer Divide-Down. - Uint16 PSCH:8; // 15:8 CPU-Timer Prescale Counter. -}; - -union TPRH_REG { - Uint16 all; - struct TPRH_BITS bit; -}; - -struct CPUTIMER_REGS { - union TIM_REG TIM; // CPU-Timer, Counter Register - union PRD_REG PRD; // CPU-Timer, Period Register - union TCR_REG TCR; // CPU-Timer, Control Register - Uint16 rsvd1; // Reserved - union TPR_REG TPR; // CPU-Timer, Prescale Register - union TPRH_REG TPRH; // CPU-Timer, Prescale Register High -}; - -//--------------------------------------------------------------------------- -// CPUTIMER External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct CPUTIMER_REGS CpuTimer0Regs; -extern volatile struct CPUTIMER_REGS CpuTimer1Regs; -extern volatile struct CPUTIMER_REGS CpuTimer2Regs; -#endif -#ifdef CPU2 -extern volatile struct CPUTIMER_REGS CpuTimer0Regs; -extern volatile struct CPUTIMER_REGS CpuTimer1Regs; -extern volatile struct CPUTIMER_REGS CpuTimer2Regs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dac.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dac.h deleted file mode 100644 index 6594bf2334..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dac.h +++ /dev/null @@ -1,163 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_dac.h -// -// TITLE: DAC Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_DAC_H__ -#define __F2837xD_DAC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// DAC Individual Register Bit Definitions: - -struct DACREV_BITS { // bits description - Uint16 REV:8; // 7:0 DAC Revision Register - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union DACREV_REG { - Uint16 all; - struct DACREV_BITS bit; -}; - -struct DACCTL_BITS { // bits description - Uint16 DACREFSEL:1; // 0 DAC Reference Select - Uint16 rsvd1:1; // 1 Reserved - Uint16 LOADMODE:1; // 2 DACVALA Load Mode - Uint16 rsvd2:1; // 3 Reserved - Uint16 SYNCSEL:4; // 7:4 DAC PWMSYNC Select - Uint16 rsvd3:8; // 15:8 Reserved -}; - -union DACCTL_REG { - Uint16 all; - struct DACCTL_BITS bit; -}; - -struct DACVALA_BITS { // bits description - Uint16 DACVALA:12; // 11:0 DAC Active Output Code - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACVALA_REG { - Uint16 all; - struct DACVALA_BITS bit; -}; - -struct DACVALS_BITS { // bits description - Uint16 DACVALS:12; // 11:0 DAC Shadow Output Code - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union DACVALS_REG { - Uint16 all; - struct DACVALS_BITS bit; -}; - -struct DACOUTEN_BITS { // bits description - Uint16 DACOUTEN:1; // 0 DAC Output Code - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union DACOUTEN_REG { - Uint16 all; - struct DACOUTEN_BITS bit; -}; - -struct DACLOCK_BITS { // bits description - Uint16 DACCTL:1; // 0 DAC Control Register Lock - Uint16 DACVAL:1; // 1 DAC Value Register Lock - Uint16 DACOUTEN:1; // 2 DAC Output Enable Register Lock - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union DACLOCK_REG { - Uint16 all; - struct DACLOCK_BITS bit; -}; - -struct DACTRIM_BITS { // bits description - Uint16 OFFSET_TRIM:8; // 7:0 DAC Offset Trim - Uint16 rsvd1:4; // 11:8 Reserved - Uint16 rsvd2:4; // 15:12 Reserved -}; - -union DACTRIM_REG { - Uint16 all; - struct DACTRIM_BITS bit; -}; - -struct DAC_REGS { - union DACREV_REG DACREV; // DAC Revision Register - union DACCTL_REG DACCTL; // DAC Control Register - union DACVALA_REG DACVALA; // DAC Value Register - Active - union DACVALS_REG DACVALS; // DAC Value Register - Shadow - union DACOUTEN_REG DACOUTEN; // DAC Output Enable Register - union DACLOCK_REG DACLOCK; // DAC Lock Register - union DACTRIM_REG DACTRIM; // DAC Trim Register - Uint16 rsvd1; // Reserved -}; - -//--------------------------------------------------------------------------- -// DAC External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct DAC_REGS DacaRegs; -extern volatile struct DAC_REGS DacbRegs; -extern volatile struct DAC_REGS DaccRegs; -#endif -#ifdef CPU2 -extern volatile struct DAC_REGS DacaRegs; -extern volatile struct DAC_REGS DacbRegs; -extern volatile struct DAC_REGS DaccRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dcsm.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dcsm.h deleted file mode 100644 index 4ea33d6843..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dcsm.h +++ /dev/null @@ -1,449 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_dcsm.h -// -// TITLE: DCSM Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_DCSM_H__ -#define __F2837xD_DCSM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// DCSM Individual Register Bit Definitions: - -struct Z1_LINKPOINTER_BITS { // bits description - Uint32 LINKPOINTER:29; // 28:0 Zone1 LINK Pointer. - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union Z1_LINKPOINTER_REG { - Uint32 all; - struct Z1_LINKPOINTER_BITS bit; -}; - -struct Z1_OTPSECLOCK_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 PSWDLOCK:4; // 7:4 Zone1 Password Lock. - Uint16 CRCLOCK:4; // 11:8 Zone1 CRC Lock. - Uint16 rsvd2:4; // 15:12 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union Z1_OTPSECLOCK_REG { - Uint32 all; - struct Z1_OTPSECLOCK_BITS bit; -}; - -struct Z1_BOOTCTRL_BITS { // bits description - Uint16 KEY:8; // 7:0 OTP Boot Key - Uint16 BMODE:8; // 15:8 OTP Boot Mode - Uint16 BOOTPIN0:8; // 23:16 OTP Boot Pin 0 Mapping - Uint16 BOOTPIN1:8; // 31:24 OTP Boot Pin 1 Mapping -}; - -union Z1_BOOTCTRL_REG { - Uint32 all; - struct Z1_BOOTCTRL_BITS bit; -}; - -struct Z1_CR_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros - Uint16 ALLONE:1; // 4 CSMPSWD All Ones - Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY - Uint16 ARMED:1; // 6 CSM Armed - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:7; // 14:8 Reserved - Uint16 FORCESEC:1; // 15 Force Secure -}; - -union Z1_CR_REG { - Uint16 all; - struct Z1_CR_BITS bit; -}; - -struct Z1_GRABSECTR_BITS { // bits description - Uint16 GRAB_SECTA:2; // 1:0 Grab Flash Sector A - Uint16 GRAB_SECTB:2; // 3:2 Grab Flash Sector B - Uint16 GRAB_SECTC:2; // 5:4 Grab Flash Sector C - Uint16 GRAB_SECTD:2; // 7:6 Grab Flash Sector D - Uint16 GRAB_SECTE:2; // 9:8 Grab Flash Sector E - Uint16 GRAB_SECTF:2; // 11:10 Grab Flash Sector F - Uint16 GRAB_SECTG:2; // 13:12 Grab Flash Sector G - Uint16 GRAB_SECTH:2; // 15:14 Grab Flash Sector H - Uint16 GRAB_SECTI:2; // 17:16 Grab Flash Sector I - Uint16 GRAB_SECTJ:2; // 19:18 Grab Flash Sector J - Uint16 GRAB_SECTK:2; // 21:20 Grab Flash Sector K - Uint16 GRAB_SECTL:2; // 23:22 Grab Flash Sector L - Uint16 GRAB_SECTM:2; // 25:24 Grab Flash Sector M - Uint16 GRAB_SECTN:2; // 27:26 Grab Flash Sector N - Uint16 rsvd1:2; // 29:28 Reserved - Uint16 rsvd2:2; // 31:30 Reserved -}; - -union Z1_GRABSECTR_REG { - Uint32 all; - struct Z1_GRABSECTR_BITS bit; -}; - -struct Z1_GRABRAMR_BITS { // bits description - Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 - Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 - Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 - Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 - Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 - Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 - Uint16 GRAB_RAM6:2; // 13:12 Grab RAM D0 - Uint16 GRAB_RAM7:2; // 15:14 Grab RAM D1 - Uint16 rsvd1:12; // 27:16 Reserved - Uint16 GRAB_CLA1:2; // 29:28 Grab CLA1 - Uint16 rsvd2:2; // 31:30 Reserved -}; - -union Z1_GRABRAMR_REG { - Uint32 all; - struct Z1_GRABRAMR_BITS bit; -}; - -struct Z1_EXEONLYSECTR_BITS { // bits description - Uint16 EXEONLY_SECTA:1; // 0 Execute-Only Flash Sector A - Uint16 EXEONLY_SECTB:1; // 1 Execute-Only Flash Sector B - Uint16 EXEONLY_SECTC:1; // 2 Execute-Only Flash Sector C - Uint16 EXEONLY_SECTD:1; // 3 Execute-Only Flash Sector D - Uint16 EXEONLY_SECTE:1; // 4 Execute-Only Flash Sector E - Uint16 EXEONLY_SECTF:1; // 5 Execute-Only Flash Sector F - Uint16 EXEONLY_SECTG:1; // 6 Execute-Only Flash Sector G - Uint16 EXEONLY_SECTH:1; // 7 Execute-Only Flash Sector H - Uint16 EXEONLY_SECTI:1; // 8 Execute-Only Flash Sector I - Uint16 EXEONLY_SECTJ:1; // 9 Execute-Only Flash Sector J - Uint16 EXEONLY_SECTK:1; // 10 Execute-Only Flash Sector K - Uint16 EXEONLY_SECTL:1; // 11 Execute-Only Flash Sector L - Uint16 EXEONLY_SECTM:1; // 12 Execute-Only Flash Sector M - Uint16 EXEONLY_SECTN:1; // 13 Execute-Only Flash Sector N - Uint16 rsvd1:1; // 14 Reserved - Uint16 rsvd2:1; // 15 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union Z1_EXEONLYSECTR_REG { - Uint32 all; - struct Z1_EXEONLYSECTR_BITS bit; -}; - -struct Z1_EXEONLYRAMR_BITS { // bits description - Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 - Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 - Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 - Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 - Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 - Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 - Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM D0 - Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM D1 - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union Z1_EXEONLYRAMR_REG { - Uint32 all; - struct Z1_EXEONLYRAMR_BITS bit; -}; - -struct DCSM_Z1_REGS { - union Z1_LINKPOINTER_REG Z1_LINKPOINTER; // Zone 1 Link Pointer - union Z1_OTPSECLOCK_REG Z1_OTPSECLOCK; // Zone 1 OTP Secure JTAG lock - union Z1_BOOTCTRL_REG Z1_BOOTCTRL; // Boot Mode - Uint32 Z1_LINKPOINTERERR; // Link Pointer Error - Uint16 rsvd1[8]; // Reserved - Uint32 Z1_CSMKEY0; // Zone 1 CSM Key 0 - Uint32 Z1_CSMKEY1; // Zone 1 CSM Key 1 - Uint32 Z1_CSMKEY2; // Zone 1 CSM Key 2 - Uint32 Z1_CSMKEY3; // Zone 1 CSM Key 3 - Uint16 rsvd2; // Reserved - union Z1_CR_REG Z1_CR; // Zone 1 CSM Control Register - union Z1_GRABSECTR_REG Z1_GRABSECTR; // Zone 1 Grab Flash Sectors Register - union Z1_GRABRAMR_REG Z1_GRABRAMR; // Zone 1 Grab RAM Blocks Register - union Z1_EXEONLYSECTR_REG Z1_EXEONLYSECTR; // Zone 1 Flash Execute_Only Sector Register - union Z1_EXEONLYRAMR_REG Z1_EXEONLYRAMR; // Zone 1 RAM Execute_Only Block Register - Uint16 rsvd3; // Reserved -}; - -struct Z2_LINKPOINTER_BITS { // bits description - Uint32 LINKPOINTER:29; // 28:0 Zone2 LINK Pointer. - Uint16 rsvd1:3; // 31:29 Reserved -}; - -union Z2_LINKPOINTER_REG { - Uint32 all; - struct Z2_LINKPOINTER_BITS bit; -}; - -struct Z2_OTPSECLOCK_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 PSWDLOCK:4; // 7:4 Zone2 Password Lock. - Uint16 CRCLOCK:4; // 11:8 Zone2 CRC Lock. - Uint16 rsvd2:4; // 15:12 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union Z2_OTPSECLOCK_REG { - Uint32 all; - struct Z2_OTPSECLOCK_BITS bit; -}; - -struct Z2_BOOTCTRL_BITS { // bits description - Uint16 KEY:8; // 7:0 OTP Boot Key - Uint16 BMODE:8; // 15:8 OTP Boot Mode - Uint16 BOOTPIN0:8; // 23:16 OTP Boot Pin 0 Mapping - Uint16 BOOTPIN1:8; // 31:24 OTP Boot Pin 1 Mapping -}; - -union Z2_BOOTCTRL_REG { - Uint32 all; - struct Z2_BOOTCTRL_BITS bit; -}; - -struct Z2_CR_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros - Uint16 ALLONE:1; // 4 CSMPSWD All Ones - Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY - Uint16 ARMED:1; // 6 CSM Armed - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:7; // 14:8 Reserved - Uint16 FORCESEC:1; // 15 Force Secure -}; - -union Z2_CR_REG { - Uint16 all; - struct Z2_CR_BITS bit; -}; - -struct Z2_GRABSECTR_BITS { // bits description - Uint16 GRAB_SECTA:2; // 1:0 Grab Flash Sector A - Uint16 GRAB_SECTB:2; // 3:2 Grab Flash Sector B - Uint16 GRAB_SECTC:2; // 5:4 Grab Flash Sector C - Uint16 GRAB_SECTD:2; // 7:6 Grab Flash Sector D - Uint16 GRAB_SECTE:2; // 9:8 Grab Flash Sector E - Uint16 GRAB_SECTF:2; // 11:10 Grab Flash Sector F - Uint16 GRAB_SECTG:2; // 13:12 Grab Flash Sector G - Uint16 GRAB_SECTH:2; // 15:14 Grab Flash Sector H - Uint16 GRAB_SECTI:2; // 17:16 Grab Flash Sector I - Uint16 GRAB_SECTJ:2; // 19:18 Grab Flash Sector J - Uint16 GRAB_SECTK:2; // 21:20 Grab Flash Sector K - Uint16 GRAB_SECTL:2; // 23:22 Grab Flash Sector L - Uint16 GRAB_SECTM:2; // 25:24 Grab Flash Sector M - Uint16 GRAB_SECTN:2; // 27:26 Grab Flash Sector N - Uint16 rsvd1:2; // 29:28 Reserved - Uint16 rsvd2:2; // 31:30 Reserved -}; - -union Z2_GRABSECTR_REG { - Uint32 all; - struct Z2_GRABSECTR_BITS bit; -}; - -struct Z2_GRABRAMR_BITS { // bits description - Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 - Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 - Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 - Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 - Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 - Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 - Uint16 GRAB_RAM6:2; // 13:12 Grab RAM D0 - Uint16 GRAB_RAM7:2; // 15:14 Grab RAM D1 - Uint16 rsvd1:12; // 27:16 Reserved - Uint16 GRAB_CLA1:2; // 29:28 Grab CLA1 - Uint16 rsvd2:2; // 31:30 Reserved -}; - -union Z2_GRABRAMR_REG { - Uint32 all; - struct Z2_GRABRAMR_BITS bit; -}; - -struct Z2_EXEONLYSECTR_BITS { // bits description - Uint16 EXEONLY_SECTA:1; // 0 Execute-Only Flash Sector A - Uint16 EXEONLY_SECTB:1; // 1 Execute-Only Flash Sector B - Uint16 EXEONLY_SECTC:1; // 2 Execute-Only Flash Sector C - Uint16 EXEONLY_SECTD:1; // 3 Execute-Only Flash Sector D - Uint16 EXEONLY_SECTE:1; // 4 Execute-Only Flash Sector E - Uint16 EXEONLY_SECTF:1; // 5 Execute-Only Flash Sector F - Uint16 EXEONLY_SECTG:1; // 6 Execute-Only Flash Sector G - Uint16 EXEONLY_SECTH:1; // 7 Execute-Only Flash Sector H - Uint16 EXEONLY_SECTI:1; // 8 Execute-Only Flash Sector I - Uint16 EXEONLY_SECTJ:1; // 9 Execute-Only Flash Sector J - Uint16 EXEONLY_SECTK:1; // 10 Execute-Only Flash Sector K - Uint16 EXEONLY_SECTL:1; // 11 Execute-Only Flash Sector L - Uint16 EXEONLY_SECTM:1; // 12 Execute-Only Flash Sector M - Uint16 EXEONLY_SECTN:1; // 13 Execute-Only Flash Sector N - Uint16 rsvd1:1; // 14 Reserved - Uint16 rsvd2:1; // 15 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union Z2_EXEONLYSECTR_REG { - Uint32 all; - struct Z2_EXEONLYSECTR_BITS bit; -}; - -struct Z2_EXEONLYRAMR_BITS { // bits description - Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 - Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 - Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 - Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 - Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 - Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 - Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM D0 - Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM D1 - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union Z2_EXEONLYRAMR_REG { - Uint32 all; - struct Z2_EXEONLYRAMR_BITS bit; -}; - -struct DCSM_Z2_REGS { - union Z2_LINKPOINTER_REG Z2_LINKPOINTER; // Zone 2 Link Pointer - union Z2_OTPSECLOCK_REG Z2_OTPSECLOCK; // Zone 2 OTP Secure JTAG lock - union Z2_BOOTCTRL_REG Z2_BOOTCTRL; // Boot Mode - Uint32 Z2_LINKPOINTERERR; // Link Pointer Error - Uint16 rsvd1[8]; // Reserved - Uint32 Z2_CSMKEY0; // Zone 2 CSM Key 0 - Uint32 Z2_CSMKEY1; // Zone 2 CSM Key 1 - Uint32 Z2_CSMKEY2; // Zone 2 CSM Key 2 - Uint32 Z2_CSMKEY3; // Zone 2 CSM Key 3 - Uint16 rsvd2; // Reserved - union Z2_CR_REG Z2_CR; // Zone 2 CSM Control Register - union Z2_GRABSECTR_REG Z2_GRABSECTR; // Zone 2 Grab Flash Sectors Register - union Z2_GRABRAMR_REG Z2_GRABRAMR; // Zone 2 Grab RAM Blocks Register - union Z2_EXEONLYSECTR_REG Z2_EXEONLYSECTR; // Zone 2 Flash Execute_Only Sector Register - union Z2_EXEONLYRAMR_REG Z2_EXEONLYRAMR; // Zone 2 RAM Execute_Only Block Register - Uint16 rsvd3; // Reserved -}; - -struct FLSEM_BITS { // bits description - Uint16 SEM:2; // 1:0 Flash Semaphore Bit - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 KEY:8; // 15:8 Semaphore Key - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FLSEM_REG { - Uint32 all; - struct FLSEM_BITS bit; -}; - -struct SECTSTAT_BITS { // bits description - Uint16 STATUS_SECTA:2; // 1:0 Zone Status Flash Sector A - Uint16 STATUS_SECTB:2; // 3:2 Zone Status Flash Sector B - Uint16 STATUS_SECTC:2; // 5:4 Zone Status Flash Sector C - Uint16 STATUS_SECTD:2; // 7:6 Zone Status Flash Sector D - Uint16 STATUS_SECTE:2; // 9:8 Zone Status Flash Sector E - Uint16 STATUS_SECTF:2; // 11:10 Zone Status Flash Sector F - Uint16 STATUS_SECTG:2; // 13:12 Zone Status Flash Sector G - Uint16 STATUS_SECTH:2; // 15:14 Zone Status Flash Sector H - Uint16 STATUS_SECTI:2; // 17:16 Zone Status Flash Sector I - Uint16 STATUS_SECTJ:2; // 19:18 Zone Status Flash Sector J - Uint16 STATUS_SECTK:2; // 21:20 Zone Status Flash Sector K - Uint16 STATUS_SECTL:2; // 23:22 Zone Status Flash Sector L - Uint16 STATUS_SECTM:2; // 25:24 Zone Status Flash Sector M - Uint16 STATUS_SECTN:2; // 27:26 Zone Status Flash Sector N - Uint16 rsvd1:2; // 29:28 Reserved - Uint16 rsvd2:2; // 31:30 Reserved -}; - -union SECTSTAT_REG { - Uint32 all; - struct SECTSTAT_BITS bit; -}; - -struct RAMSTAT_BITS { // bits description - Uint16 STATUS_RAM0:2; // 1:0 Zone Status RAM LS0 - Uint16 STATUS_RAM1:2; // 3:2 Zone Status RAM LS1 - Uint16 STATUS_RAM2:2; // 5:4 Zone Status RAM LS2 - Uint16 STATUS_RAM3:2; // 7:6 Zone Status RAM LS3 - Uint16 STATUS_RAM4:2; // 9:8 Zone Status RAM LS4 - Uint16 STATUS_RAM5:2; // 11:10 Zone Status RAM LS5 - Uint16 STATUS_RAM6:2; // 13:12 Zone Status RAM D0 - Uint16 STATUS_RAM7:2; // 15:14 Zone Status RAM D1 - Uint16 rsvd1:12; // 27:16 Reserved - Uint16 STATUS_CLA1:2; // 29:28 Zone Status CLA1 - Uint16 rsvd2:2; // 31:30 Reserved -}; - -union RAMSTAT_REG { - Uint32 all; - struct RAMSTAT_BITS bit; -}; - -struct DCSM_COMMON_REGS { - union FLSEM_REG FLSEM; // Flash Wrapper Semaphore Register - union SECTSTAT_REG SECTSTAT; // Sectors Status Register - union RAMSTAT_REG RAMSTAT; // RAM Status Register - Uint16 rsvd1[2]; // Reserved -}; - -//--------------------------------------------------------------------------- -// DCSM External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct DCSM_Z1_REGS DcsmZ1Regs; -extern volatile struct DCSM_Z2_REGS DcsmZ2Regs; -extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs; -#endif -#ifdef CPU2 -extern volatile struct DCSM_Z1_REGS DcsmZ1Regs; -extern volatile struct DCSM_Z2_REGS DcsmZ2Regs; -extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_device.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_device.h deleted file mode 100644 index 58aee28ebb..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_device.h +++ /dev/null @@ -1,345 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_device.h -// -// TITLE: F2837xD Device Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_DEVICE_H -#define F2837xD_DEVICE_H - -#if (!defined(CPU1) && !defined(CPU2)) -#error "You must define CPU1 or CPU2 in your project properties. Otherwise, the offsets in your header files will be inaccurate." -#endif - -#if (defined(CPU1) && defined(CPU2)) -#error "You have defined both CPU1 and CPU2 in your project properties. Only a single CPU should be defined." -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -#define TARGET 1 - -// -// User To Select Target Device: -// -#define F28_2837xD TARGET - -// -// Common CPU Definitions: -// -extern __cregister volatile unsigned int IFR; -extern __cregister volatile unsigned int IER; - -#define EINT __asm(" clrc INTM") -#define DINT __asm(" setc INTM") -#define ERTM __asm(" clrc DBGM") -#define DRTM __asm(" setc DBGM") -#ifndef EALLOW -#define EALLOW __asm(" EALLOW") -#endif -#ifndef EDIS -#define EDIS __asm(" EDIS") -#endif -#define ESTOP0 __asm(" ESTOP0") - -#define M_INT1 0x0001 -#define M_INT2 0x0002 -#define M_INT3 0x0004 -#define M_INT4 0x0008 -#define M_INT5 0x0010 -#define M_INT6 0x0020 -#define M_INT7 0x0040 -#define M_INT8 0x0080 -#define M_INT9 0x0100 -#define M_INT10 0x0200 -#define M_INT11 0x0400 -#define M_INT12 0x0800 -#define M_INT13 0x1000 -#define M_INT14 0x2000 -#define M_DLOG 0x4000 -#define M_RTOS 0x8000 - -#ifndef C28X_BIT0 -#define C28X_BIT0 0x00000001 -#endif - -#ifndef C28X_BIT1 -#define C28X_BIT1 0x00000002 -#endif - -#ifndef C28X_BIT2 -#define C28X_BIT2 0x00000004 -#endif - -#ifndef C28X_BIT3 -#define C28X_BIT3 0x00000008 -#endif - -#ifndef C28X_BIT4 -#define C28X_BIT4 0x00000010 -#endif - -#ifndef C28X_BIT5 -#define C28X_BIT5 0x00000020 -#endif - -#ifndef C28X_BIT6 -#define C28X_BIT6 0x00000040 -#endif - -#ifndef C28X_BIT7 -#define C28X_BIT7 0x00000080 -#endif - -#ifndef C28X_BIT8 -#define C28X_BIT8 0x00000100 -#endif - -#ifndef C28X_BIT9 -#define C28X_BIT9 0x00000200 -#endif - -#ifndef C28X_BIT10 -#define C28X_BIT10 0x00000400 -#endif - -#ifndef C28X_BIT11 -#define C28X_BIT11 0x00000800 -#endif - -#ifndef C28X_BIT12 -#define C28X_BIT12 0x00001000 -#endif - -#ifndef C28X_BIT13 -#define C28X_BIT13 0x00002000 -#endif - -#ifndef C28X_BIT14 -#define C28X_BIT14 0x00004000 -#endif - -#ifndef C28X_BIT15 -#define C28X_BIT15 0x00008000 -#endif - -#ifndef C28X_BIT16 -#define C28X_BIT16 0x00010000 -#endif - -#ifndef C28X_BIT17 -#define C28X_BIT17 0x00020000 -#endif - -#ifndef C28X_BIT18 -#define C28X_BIT18 0x00040000 -#endif - -#ifndef C28X_BIT19 -#define C28X_BIT19 0x00080000 -#endif - -#ifndef C28X_BIT20 -#define C28X_BIT20 0x00100000 -#endif - -#ifndef C28X_BIT21 -#define C28X_BIT21 0x00200000 -#endif - -#ifndef C28X_BIT22 -#define C28X_BIT22 0x00400000 -#endif - -#ifndef C28X_BIT23 -#define C28X_BIT23 0x00800000 -#endif - -#ifndef C28X_BIT24 -#define C28X_BIT24 0x01000000 -#endif - -#ifndef C28X_BIT25 -#define C28X_BIT25 0x02000000 -#endif - -#ifndef C28X_BIT26 -#define C28X_BIT26 0x04000000 -#endif - -#ifndef C28X_BIT27 -#define C28X_BIT27 0x08000000 -#endif - -#ifndef C28X_BIT28 -#define C28X_BIT28 0x10000000 -#endif - -#ifndef C28X_BIT29 -#define C28X_BIT29 0x20000000 -#endif - -#ifndef C28X_BIT30 -#define C28X_BIT30 0x40000000 -#endif - -#ifndef C28X_BIT31 -#define C28X_BIT31 0x80000000 -#endif - -// -// For Portability, User Is Recommended To Use the C99 Standard integer types -// -#if !defined(__TMS320C28XX_CLA__) -#include -#include -#endif //__TMS320C28XX_CLA__ -#include -#include -#include - -// -// C++ Bool Compatibility -// -#if defined(__cplusplus) -typedef bool _Bool; -#endif - -// -// C99 defines boolean type to be _Bool, but this doesn't match the format of -// the other standard integer types. bool_t has been defined to fill this gap. -// -typedef _Bool bool_t; - -// -//used for a bool function return status -// -typedef _Bool status_t; - -#ifndef SUCCESS -#define SUCCESS true -#endif - -#ifndef FAIL -#define FAIL false -#endif - -// -// The following data types are included for compatibility with legacy code, -// they are not recommended for use in new software. Please use the C99 -// types included above -// -#ifndef DSP28_DATA_TYPES -#define DSP28_DATA_TYPES -typedef int int16; -typedef long int32; -typedef long long int64; -typedef unsigned int Uint16; -typedef unsigned long Uint32; -typedef unsigned long long Uint64; -typedef float float32; -typedef long double float64; -#endif - -// -// The following data types are for use with byte addressable peripherals. -// See compiler documentation on the byte_peripheral type attribute. -// -#ifndef __TMS320C28XX_CLA__ -#if __TI_COMPILER_VERSION__ >= 16006000 -typedef unsigned int bp_16 __attribute__((byte_peripheral)); -typedef unsigned long bp_32 __attribute__((byte_peripheral)); -#endif -#endif - -// -// Include All Peripheral Header Files: -// -#include "F2837xD_adc.h" -#include "F2837xD_analogsubsys.h" -#include "F2837xD_cla.h" -#include "F2837xD_cmpss.h" -#include "F2837xD_cputimer.h" -#include "F2837xD_dac.h" -#include "F2837xD_dcsm.h" -#include "F2837xD_dma.h" -#include "F2837xD_ecap.h" -#include "F2837xD_emif.h" -#include "F2837xD_epwm.h" // Enhanced PWM -#include "F2837xD_epwm_xbar.h" -#include "F2837xD_eqep.h" -#include "F2837xD_flash.h" -#include "F2837xD_gpio.h" // General Purpose I/O Registers -#include "F2837xD_i2c.h" -#include "F2837xD_input_xbar.h" -#include "F2837xD_ipc.h" -#include "F2837xD_mcbsp.h" -#include "F2837xD_memconfig.h" -#include "F2837xD_nmiintrupt.h" // NMI Interrupt Registers -#include "F2837xD_output_xbar.h" -#include "F2837xD_piectrl.h" // PIE Control Registers -#include "F2837xD_pievect.h" -#include "F2837xD_sci.h" -#include "F2837xD_sdfm.h" -#include "F2837xD_spi.h" -#include "F2837xD_sysctrl.h" // System Control/Power Modes -#include "F2837xD_upp.h" -#include "F2837xD_xbar.h" -#include "F2837xD_xint.h" // External Interrupts - -// -// byte_peripheral attribute is only supported on the C28 -// -#ifndef __TMS320C28XX_CLA__ -#if __TI_COMPILER_VERSION__ >= 16006000 -#include "F2837xD_can.h" -#endif -#endif - -#ifdef __cplusplus -} -#endif // extern "C" - -#endif // end of F2837xD_DEVICE_H definition - -// -// End of file. -// diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dma.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dma.h deleted file mode 100644 index 3de5b3ca0f..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_dma.h +++ /dev/null @@ -1,214 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_dma.h -// -// TITLE: DMA Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_DMA_H__ -#define __F2837xD_DMA_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// DMA Individual Register Bit Definitions: - -struct MODE_BITS { // bits description - Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select - Uint16 rsvd1:2; // 6:5 Reserved - Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable - Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable - Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode - Uint16 ONESHOT:1; // 10 One Shot Mode Bit - Uint16 CONTINUOUS:1; // 11 Continuous Mode Bit - Uint16 rsvd2:2; // 13:12 Reserved - Uint16 DATASIZE:1; // 14 Data Size Mode Bit - Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit -}; - -union MODE_REG { - Uint16 all; - struct MODE_BITS bit; -}; - -struct CONTROL_BITS { // bits description - Uint16 RUN:1; // 0 Run Bit - Uint16 HALT:1; // 1 Halt Bit - Uint16 SOFTRESET:1; // 2 Soft Reset Bit - Uint16 PERINTFRC:1; // 3 Interrupt Force Bit - Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit - Uint16 rsvd2:2; // 6:5 Reserved - Uint16 ERRCLR:1; // 7 Error Clear Bit - Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit - Uint16 SYNCFLG:1; // 9 Sync Flag Bit - Uint16 SYNCERR:1; // 10 Sync Error Flag Bit - Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit - Uint16 BURSTSTS:1; // 12 Burst Status Bit - Uint16 RUNSTS:1; // 13 Run Status Bit - Uint16 OVRFLG:1; // 14 Overflow Flag Bit - Uint16 rsvd1:1; // 15 Reserved -}; - -union CONTROL_REG { - Uint16 all; - struct CONTROL_BITS bit; -}; - -struct DMACTRL_BITS { // bits description - Uint16 HARDRESET:1; // 0 Hard Reset Bit - Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union DMACTRL_REG { - Uint16 all; - struct DMACTRL_BITS bit; -}; - -struct DEBUGCTRL_BITS { // bits description - Uint16 rsvd1:15; // 14:0 Reserved - Uint16 FREE:1; // 15 Debug Mode Bit -}; - -union DEBUGCTRL_REG { - Uint16 all; - struct DEBUGCTRL_BITS bit; -}; - -struct PRIORITYCTRL1_BITS { // bits description - Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union PRIORITYCTRL1_REG { - Uint16 all; - struct PRIORITYCTRL1_BITS bit; -}; - -struct PRIORITYSTAT_BITS { // bits description - Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits - Uint16 rsvd1:1; // 3 Reserved - Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union PRIORITYSTAT_REG { - Uint16 all; - struct PRIORITYSTAT_BITS bit; -}; - -struct BURST_SIZE_BITS { // bits description - Uint16 BURSTSIZE:5; // 4:0 Burst Transfer Size - Uint16 rsvd1:11; // 15:5 Reserved -}; - -union BURST_SIZE_REG { - Uint16 all; - struct BURST_SIZE_BITS bit; -}; - -struct BURST_COUNT_BITS { // bits description - Uint16 BURSTCOUNT:5; // 4:0 Burst Transfer Count - Uint16 rsvd1:11; // 15:5 Reserved -}; - -union BURST_COUNT_REG { - Uint16 all; - struct BURST_COUNT_BITS bit; -}; - -struct CH_REGS { - union MODE_REG MODE; // Mode Register - union CONTROL_REG CONTROL; // Control Register - union BURST_SIZE_REG BURST_SIZE; // Burst Size Register - union BURST_COUNT_REG BURST_COUNT; // Burst Count Register - int16 SRC_BURST_STEP; // Source Burst Step Register - int16 DST_BURST_STEP; // Destination Burst Step Register - Uint16 TRANSFER_SIZE; // Transfer Size Register - Uint16 TRANSFER_COUNT; // Transfer Count Register - int16 SRC_TRANSFER_STEP; // Source Transfer Step Register - int16 DST_TRANSFER_STEP; // Destination Transfer Step Register - Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register - Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register - int16 SRC_WRAP_STEP; // Source Wrap Step Register - Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register - Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register - int16 DST_WRAP_STEP; // Destination Wrap Step Register - Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register - Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register - Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register - Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register - Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register - Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register - Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register - Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register -}; - -struct DMA_REGS { - union DMACTRL_REG DMACTRL; // DMA Control Register - union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register - Uint16 rsvd0; // Reserved - Uint16 rsvd1; // Reserved - union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register - Uint16 rsvd2; // Reserved - union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register - Uint16 rsvd3[25]; // Reserved - struct CH_REGS CH1; // DMA Channel 1 Registers - struct CH_REGS CH2; // DMA Channel 2 Registers - struct CH_REGS CH3; // DMA Channel 3 Registers - struct CH_REGS CH4; // DMA Channel 4 Registers - struct CH_REGS CH5; // DMA Channel 5 Registers - struct CH_REGS CH6; // DMA Channel 6 Registers -}; - -//--------------------------------------------------------------------------- -// DMA External References & Function Declarations: -// -extern volatile struct DMA_REGS DmaRegs; -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_ecap.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_ecap.h deleted file mode 100644 index 1fdeb15ec3..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_ecap.h +++ /dev/null @@ -1,203 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_ecap.h -// -// TITLE: ECAP Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_ECAP_H__ -#define __F2837xD_ECAP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// ECAP Individual Register Bit Definitions: - -struct ECCTL1_BITS { // bits description - Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select - Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 - Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select - Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 - Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select - Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 - Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select - Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 - Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event - Uint16 PRESCALE:5; // 13:9 Event Filter prescale select - Uint16 FREE_SOFT:2; // 15:14 Emulation mode -}; - -union ECCTL1_REG { - Uint16 all; - struct ECCTL1_BITS bit; -}; - -struct ECCTL2_BITS { // bits description - Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot - Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous - Uint16 REARM:1; // 3 One-shot re-arm - Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop - Uint16 SYNCI_EN:1; // 5 Counter sync-in select - Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode - Uint16 SWSYNC:1; // 8 SW forced counter sync - Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select - Uint16 APWMPOL:1; // 10 APWM output polarity select - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union ECCTL2_REG { - Uint16 all; - struct ECCTL2_BITS bit; -}; - -struct ECEINT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable - Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable - Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable - Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable - Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable - Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable - Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union ECEINT_REG { - Uint16 all; - struct ECEINT_BITS bit; -}; - -struct ECFLG_BITS { // bits description - Uint16 INT:1; // 0 Global Flag - Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag - Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag - Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag - Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag - Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag - Uint16 CTR_PRD:1; // 6 Period Equal Interrupt Flag - Uint16 CTR_CMP:1; // 7 Compare Equal Interrupt Flag - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union ECFLG_REG { - Uint16 all; - struct ECFLG_BITS bit; -}; - -struct ECCLR_BITS { // bits description - Uint16 INT:1; // 0 ECAP Global Interrupt Status Clear - Uint16 CEVT1:1; // 1 Capture Event 1 Status Clear - Uint16 CEVT2:1; // 2 Capture Event 2 Status Clear - Uint16 CEVT3:1; // 3 Capture Event 3 Status Clear - Uint16 CEVT4:1; // 4 Capture Event 4 Status Clear - Uint16 CTROVF:1; // 5 Counter Overflow Status Clear - Uint16 CTR_PRD:1; // 6 Period Equal Status Clear - Uint16 CTR_CMP:1; // 7 Compare Equal Status Clear - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union ECCLR_REG { - Uint16 all; - struct ECCLR_BITS bit; -}; - -struct ECFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CEVT1:1; // 1 Capture Event 1 Force Interrupt - Uint16 CEVT2:1; // 2 Capture Event 2 Force Interrupt - Uint16 CEVT3:1; // 3 Capture Event 3 Force Interrupt - Uint16 CEVT4:1; // 4 Capture Event 4 Force Interrupt - Uint16 CTROVF:1; // 5 Counter Overflow Force Interrupt - Uint16 CTR_PRD:1; // 6 Period Equal Force Interrupt - Uint16 CTR_CMP:1; // 7 Compare Equal Force Interrupt - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union ECFRC_REG { - Uint16 all; - struct ECFRC_BITS bit; -}; - -struct ECAP_REGS { - Uint32 TSCTR; // Time-Stamp Counter - Uint32 CTRPHS; // Counter Phase Offset Value Register - Uint32 CAP1; // Capture 1 Register - Uint32 CAP2; // Capture 2 Register - Uint32 CAP3; // Capture 3 Register - Uint32 CAP4; // Capture 4 Register - Uint16 rsvd1[8]; // Reserved - union ECCTL1_REG ECCTL1; // Capture Control Register 1 - union ECCTL2_REG ECCTL2; // Capture Control Register 2 - union ECEINT_REG ECEINT; // Capture Interrupt Enable Register - union ECFLG_REG ECFLG; // Capture Interrupt Flag Register - union ECCLR_REG ECCLR; // Capture Interrupt Clear Register - union ECFRC_REG ECFRC; // Capture Interrupt Force Register - Uint16 rsvd2[6]; // Reserved -}; - -//--------------------------------------------------------------------------- -// ECAP External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct ECAP_REGS ECap1Regs; -extern volatile struct ECAP_REGS ECap2Regs; -extern volatile struct ECAP_REGS ECap3Regs; -extern volatile struct ECAP_REGS ECap4Regs; -extern volatile struct ECAP_REGS ECap5Regs; -extern volatile struct ECAP_REGS ECap6Regs; -#endif -#ifdef CPU2 -extern volatile struct ECAP_REGS ECap1Regs; -extern volatile struct ECAP_REGS ECap2Regs; -extern volatile struct ECAP_REGS ECap3Regs; -extern volatile struct ECAP_REGS ECap4Regs; -extern volatile struct ECAP_REGS ECap5Regs; -extern volatile struct ECAP_REGS ECap6Regs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_emif.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_emif.h deleted file mode 100644 index c3246b567c..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_emif.h +++ /dev/null @@ -1,302 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_emif.h -// -// TITLE: EMIF Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_EMIF_H__ -#define __F2837xD_EMIF_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// EMIF Individual Register Bit Definitions: - -struct RCSR_BITS { // bits description - Uint16 MINOR_REVISION:8; // 7:0 Minor Revision. - Uint16 MAJOR_REVISION:8; // 15:8 Major Revision. - Uint16 MODULE_ID:14; // 29:16 EMIF module ID. - Uint16 FR:1; // 30 EMIF is running in full rate or half rate. - Uint16 BE:1; // 31 EMIF endian mode. -}; - -union RCSR_REG { - Uint32 all; - struct RCSR_BITS bit; -}; - -struct ASYNC_WCCR_BITS { // bits description - Uint16 MAX_EXT_WAIT:8; // 7:0 Maximum Extended Wait cycles. - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:2; // 17:16 Reserved - Uint16 rsvd3:2; // 19:18 Reserved - Uint16 rsvd4:2; // 21:20 Reserved - Uint16 rsvd5:2; // 23:22 Reserved - Uint16 rsvd6:4; // 27:24 Reserved - Uint16 WP0:1; // 28 Polarity for EMxWAIT. - Uint16 rsvd7:1; // 29 Reserved - Uint16 rsvd8:1; // 30 Reserved - Uint16 rsvd9:1; // 31 Reserved -}; - -union ASYNC_WCCR_REG { - Uint32 all; - struct ASYNC_WCCR_BITS bit; -}; - -struct SDRAM_CR_BITS { // bits description - Uint16 PAGESIGE:3; // 2:0 Page Size. - Uint16 rsvd1:1; // 3 Reserved - Uint16 IBANK:3; // 6:4 Internal Bank setup of SDRAM devices. - Uint16 rsvd2:1; // 7 Reserved - Uint16 BIT_11_9_LOCK:1; // 8 Bits 11 to 9 are writable only if this bit is set. - Uint16 CL:3; // 11:9 CAS Latency. - Uint16 rsvd3:1; // 12 Reserved - Uint16 rsvd4:1; // 13 Reserved - Uint16 NM:1; // 14 Narrow Mode. - Uint16 rsvd5:1; // 15 Reserved - Uint16 rsvd6:1; // 16 Reserved - Uint16 rsvd7:2; // 18:17 Reserved - Uint16 rsvd8:1; // 19 Reserved - Uint16 rsvd9:3; // 22:20 Reserved - Uint16 rsvd10:3; // 25:23 Reserved - Uint16 rsvd11:3; // 28:26 Reserved - Uint16 PDWR:1; // 29 Perform refreshes during Power Down. - Uint16 PD:1; // 30 Power Down. - Uint16 SR:1; // 31 Self Refresh. -}; - -union SDRAM_CR_REG { - Uint32 all; - struct SDRAM_CR_BITS bit; -}; - -struct SDRAM_RCR_BITS { // bits description - Uint16 REFRESH_RATE:13; // 12:0 Refresh Rate. - Uint16 rsvd1:3; // 15:13 Reserved - Uint16 rsvd2:3; // 18:16 Reserved - Uint16 rsvd3:13; // 31:19 Reserved -}; - -union SDRAM_RCR_REG { - Uint32 all; - struct SDRAM_RCR_BITS bit; -}; - -struct ASYNC_CS2_CR_BITS { // bits description - Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. - Uint16 TA:2; // 3:2 Turn Around cycles. - Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. - Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. - Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. - Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. - Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. - Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. - Uint16 EW:1; // 30 Extend Wait mode. - Uint16 SS:1; // 31 Select Strobe mode. -}; - -union ASYNC_CS2_CR_REG { - Uint32 all; - struct ASYNC_CS2_CR_BITS bit; -}; - -struct ASYNC_CS3_CR_BITS { // bits description - Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. - Uint16 TA:2; // 3:2 Turn Around cycles. - Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. - Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. - Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. - Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. - Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. - Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. - Uint16 EW:1; // 30 Extend Wait mode. - Uint16 SS:1; // 31 Select Strobe mode. -}; - -union ASYNC_CS3_CR_REG { - Uint32 all; - struct ASYNC_CS3_CR_BITS bit; -}; - -struct ASYNC_CS4_CR_BITS { // bits description - Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. - Uint16 TA:2; // 3:2 Turn Around cycles. - Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. - Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. - Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. - Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. - Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. - Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. - Uint16 EW:1; // 30 Extend Wait mode. - Uint16 SS:1; // 31 Select Strobe mode. -}; - -union ASYNC_CS4_CR_REG { - Uint32 all; - struct ASYNC_CS4_CR_BITS bit; -}; - -struct SDRAM_TR_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 T_RRD:3; // 6:4 Activate to Activate timing for different bank. - Uint16 rsvd2:1; // 7 Reserved - Uint16 T_RC:4; // 11:8 Activate to Activate timing . - Uint16 T_RAS:4; // 15:12 Activate to Precharge timing. - Uint16 T_WR:3; // 18:16 Last Write to Precharge timing. - Uint16 rsvd3:1; // 19 Reserved - Uint16 T_RCD:3; // 22:20 Activate to Read/Write timing. - Uint16 rsvd4:1; // 23 Reserved - Uint16 T_RP:3; // 26:24 Precharge to Activate/Refresh timing. - Uint16 T_RFC:5; // 31:27 Refresh/Load Mode to Refresh/Activate timing -}; - -union SDRAM_TR_REG { - Uint32 all; - struct SDRAM_TR_BITS bit; -}; - -struct SDR_EXT_TMNG_BITS { // bits description - Uint16 T_XS:5; // 4:0 Self Refresh exit to new command timing. - Uint16 rsvd1:11; // 15:5 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SDR_EXT_TMNG_REG { - Uint32 all; - struct SDR_EXT_TMNG_BITS bit; -}; - -struct INT_RAW_BITS { // bits description - Uint16 AT:1; // 0 Asynchronous Timeout. - Uint16 LT:1; // 1 Line Trap. - Uint16 WR:4; // 5:2 Wait Rise. - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union INT_RAW_REG { - Uint32 all; - struct INT_RAW_BITS bit; -}; - -struct INT_MSK_BITS { // bits description - Uint16 AT_MASKED:1; // 0 Asynchronous Timeout. - Uint16 LT_MASKED:1; // 1 Line Trap. - Uint16 WR_MASKED:4; // 5:2 Wait Rise. - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union INT_MSK_REG { - Uint32 all; - struct INT_MSK_BITS bit; -}; - -struct INT_MSK_SET_BITS { // bits description - Uint16 AT_MASK_SET:1; // 0 Asynchronous Timeout. - Uint16 LT_MASK_SET:1; // 1 Line Trap. - Uint16 WR_MASK_SET:4; // 5:2 Wait Rise. - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union INT_MSK_SET_REG { - Uint32 all; - struct INT_MSK_SET_BITS bit; -}; - -struct INT_MSK_CLR_BITS { // bits description - Uint16 AT_MASK_CLR:1; // 0 Asynchronous Timeout. - Uint16 LT_MASK_CLR:1; // 1 Line Trap. - Uint16 WR_MASK_CLR:4; // 5:2 Wait Rise. - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union INT_MSK_CLR_REG { - Uint32 all; - struct INT_MSK_CLR_BITS bit; -}; - -struct EMIF_REGS { - union RCSR_REG RCSR; // Revision Code and Status Register - union ASYNC_WCCR_REG ASYNC_WCCR; // Async Wait Cycle Config Register - union SDRAM_CR_REG SDRAM_CR; // SDRAM (EMxCS0n) Config Register - union SDRAM_RCR_REG SDRAM_RCR; // SDRAM Refresh Control Register - union ASYNC_CS2_CR_REG ASYNC_CS2_CR; // Async 1 (EMxCS2n) Config Register - union ASYNC_CS3_CR_REG ASYNC_CS3_CR; // Async 2 (EMxCS3n) Config Register - union ASYNC_CS4_CR_REG ASYNC_CS4_CR; // Async 3 (EMxCS4n) Config Register - Uint16 rsvd1[2]; // Reserved - union SDRAM_TR_REG SDRAM_TR; // SDRAM Timing Register - Uint16 rsvd2[6]; // Reserved - Uint32 TOTAL_SDRAM_AR; // Total SDRAM Accesses Register - Uint32 TOTAL_SDRAM_ACTR; // Total SDRAM Activate Register - Uint16 rsvd3[2]; // Reserved - union SDR_EXT_TMNG_REG SDR_EXT_TMNG; // SDRAM SR/PD Exit Timing Register - union INT_RAW_REG INT_RAW; // Interrupt Raw Register - union INT_MSK_REG INT_MSK; // Interrupt Masked Register - union INT_MSK_SET_REG INT_MSK_SET; // Interrupt Mask Set Register - union INT_MSK_CLR_REG INT_MSK_CLR; // Interrupt Mask Clear Register - Uint16 rsvd4[72]; // Reserved -}; - -//--------------------------------------------------------------------------- -// EMIF External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct EMIF_REGS Emif1Regs; -extern volatile struct EMIF_REGS Emif2Regs; -#endif -#ifdef CPU2 -extern volatile struct EMIF_REGS Emif1Regs; -extern volatile struct EMIF_REGS Emif2Regs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm.h deleted file mode 100644 index bd784afd49..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm.h +++ /dev/null @@ -1,1240 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_epwm.h -// -// TITLE: EPWM Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_EPWM_H__ -#define __F2837xD_EPWM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// EPWM Individual Register Bit Definitions: - -struct TBCTL_BITS { // bits description - Uint16 CTRMODE:2; // 1:0 Counter Mode - Uint16 PHSEN:1; // 2 Phase Load Enable - Uint16 PRDLD:1; // 3 Active Period Load - Uint16 SYNCOSEL:2; // 5:4 Sync Output Select - Uint16 SWFSYNC:1; // 6 Software Force Sync Pulse - Uint16 HSPCLKDIV:3; // 9:7 High Speed TBCLK Pre-scaler - Uint16 CLKDIV:3; // 12:10 Time Base Clock Pre-scaler - Uint16 PHSDIR:1; // 13 Phase Direction Bit - Uint16 FREE_SOFT:2; // 15:14 Emulation Mode Bits -}; - -union TBCTL_REG { - Uint16 all; - struct TBCTL_BITS bit; -}; - -struct TBCTL2_BITS { // bits description - Uint16 rsvd1:5; // 4:0 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 OSHTSYNCMODE:1; // 6 One shot sync mode - Uint16 OSHTSYNC:1; // 7 One shot sync - Uint16 rsvd3:4; // 11:8 Reserved - Uint16 SYNCOSELX:2; // 13:12 Syncout selection - Uint16 PRDLDSYNC:2; // 15:14 PRD Shadow to Active Load on SYNC Event -}; - -union TBCTL2_REG { - Uint16 all; - struct TBCTL2_BITS bit; -}; - -struct TBSTS_BITS { // bits description - Uint16 CTRDIR:1; // 0 Counter Direction Status - Uint16 SYNCI:1; // 1 External Input Sync Status - Uint16 CTRMAX:1; // 2 Counter Max Latched Status - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union TBSTS_REG { - Uint16 all; - struct TBSTS_BITS bit; -}; - -struct CMPCTL_BITS { // bits description - Uint16 LOADAMODE:2; // 1:0 Active Compare A Load - Uint16 LOADBMODE:2; // 3:2 Active Compare B Load - Uint16 SHDWAMODE:1; // 4 Compare A Register Block Operating Mode - Uint16 rsvd1:1; // 5 Reserved - Uint16 SHDWBMODE:1; // 6 Compare B Register Block Operating Mode - Uint16 rsvd2:1; // 7 Reserved - Uint16 SHDWAFULL:1; // 8 Compare A Shadow Register Full Status - Uint16 SHDWBFULL:1; // 9 Compare B Shadow Register Full Status - Uint16 LOADASYNC:2; // 11:10 Active Compare A Load on SYNC - Uint16 LOADBSYNC:2; // 13:12 Active Compare B Load on SYNC - Uint16 rsvd3:2; // 15:14 Reserved -}; - -union CMPCTL_REG { - Uint16 all; - struct CMPCTL_BITS bit; -}; - -struct CMPCTL2_BITS { // bits description - Uint16 LOADCMODE:2; // 1:0 Active Compare C Load - Uint16 LOADDMODE:2; // 3:2 Active Compare D load - Uint16 SHDWCMODE:1; // 4 Compare C Block Operating Mode - Uint16 rsvd1:1; // 5 Reserved - Uint16 SHDWDMODE:1; // 6 Compare D Block Operating Mode - Uint16 rsvd2:3; // 9:7 Reserved - Uint16 LOADCSYNC:2; // 11:10 Active Compare C Load on SYNC - Uint16 LOADDSYNC:2; // 13:12 Active Compare D Load on SYNC - Uint16 rsvd3:2; // 15:14 Reserved -}; - -union CMPCTL2_REG { - Uint16 all; - struct CMPCTL2_BITS bit; -}; - -struct DBCTL_BITS { // bits description - Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control - Uint16 POLSEL:2; // 3:2 Polarity Select Control - Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control - Uint16 LOADREDMODE:2; // 7:6 Active DBRED Load Mode - Uint16 LOADFEDMODE:2; // 9:8 Active DBFED Load Mode - Uint16 SHDWDBREDMODE:1; // 10 DBRED Block Operating Mode - Uint16 SHDWDBFEDMODE:1; // 11 DBFED Block Operating Mode - Uint16 OUTSWAP:2; // 13:12 Dead Band Output Swap Control - Uint16 DEDB_MODE:1; // 14 Dead Band Dual-Edge B Mode Control - Uint16 HALFCYCLE:1; // 15 Half Cycle Clocking Enable -}; - -union DBCTL_REG { - Uint16 all; - struct DBCTL_BITS bit; -}; - -struct DBCTL2_BITS { // bits description - Uint16 LOADDBCTLMODE:2; // 1:0 DBCTL Load from Shadow Mode Select - Uint16 SHDWDBCTLMODE:1; // 2 DBCTL Load mode Select - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union DBCTL2_REG { - Uint16 all; - struct DBCTL2_BITS bit; -}; - -struct AQCTL_BITS { // bits description - Uint16 LDAQAMODE:2; // 1:0 Action Qualifier A Load Select - Uint16 LDAQBMODE:2; // 3:2 Action Qualifier B Load Select - Uint16 SHDWAQAMODE:1; // 4 Action Qualifer A Operating Mode - Uint16 rsvd1:1; // 5 Reserved - Uint16 SHDWAQBMODE:1; // 6 Action Qualifier B Operating Mode - Uint16 rsvd2:1; // 7 Reserved - Uint16 LDAQASYNC:2; // 9:8 AQCTLA Register Load on SYNC - Uint16 LDAQBSYNC:2; // 11:10 AQCTLB Register Load on SYNC - Uint16 rsvd3:4; // 15:12 Reserved -}; - -union AQCTL_REG { - Uint16 all; - struct AQCTL_BITS bit; -}; - -struct AQTSRCSEL_BITS { // bits description - Uint16 T1SEL:4; // 3:0 T1 Event Source Select Bits - Uint16 T2SEL:4; // 7:4 T2 Event Source Select Bits - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union AQTSRCSEL_REG { - Uint16 all; - struct AQTSRCSEL_BITS bit; -}; - -struct PCCTL_BITS { // bits description - Uint16 CHPEN:1; // 0 PWM chopping enable - Uint16 OSHTWTH:4; // 4:1 One-shot pulse width - Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency - Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union PCCTL_REG { - Uint16 all; - struct PCCTL_BITS bit; -}; - -struct VCAPCTL_BITS { // bits description - Uint16 VCAPE:1; // 0 Valley Capture mode - Uint16 VCAPSTART:1; // 1 Valley Capture Start - Uint16 TRIGSEL:3; // 4:2 Capture Trigger Select - Uint16 rsvd1:2; // 6:5 Reserved - Uint16 VDELAYDIV:3; // 9:7 Valley Delay Mode Divide Enable - Uint16 EDGEFILTDLYSEL:1; // 10 Valley Switching Mode Delay Select - Uint16 rsvd2:5; // 15:11 Reserved -}; - -union VCAPCTL_REG { - Uint16 all; - struct VCAPCTL_BITS bit; -}; - -struct VCNTCFG_BITS { // bits description - Uint16 STARTEDGE:4; // 3:0 Counter Start Edge Selection - Uint16 rsvd1:3; // 6:4 Reserved - Uint16 STARTEDGESTS:1; // 7 Start Edge Status Bit - Uint16 STOPEDGE:4; // 11:8 Counter Start Edge Selection - Uint16 rsvd2:3; // 14:12 Reserved - Uint16 STOPEDGESTS:1; // 15 Stop Edge Status Bit -}; - -union VCNTCFG_REG { - Uint16 all; - struct VCNTCFG_BITS bit; -}; - -struct HRCNFG_BITS { // bits description - Uint16 EDGMODE:2; // 1:0 ePWMxA Edge Mode Select Bits - Uint16 CTLMODE:1; // 2 ePWMxA Control Mode Select Bits - Uint16 HRLOAD:2; // 4:3 ePWMxA Shadow Mode Select Bits - Uint16 SELOUTB:1; // 5 EPWMB Output Selection Bit - Uint16 AUTOCONV:1; // 6 Autoconversion Bit - Uint16 SWAPAB:1; // 7 Swap EPWMA and EPWMB Outputs Bit - Uint16 EDGMODEB:2; // 9:8 ePWMxB Edge Mode Select Bits - Uint16 CTLMODEB:1; // 10 ePWMxB Control Mode Select Bits - Uint16 HRLOADB:2; // 12:11 ePWMxB Shadow Mode Select Bits - Uint16 rsvd1:1; // 13 Reserved - Uint16 rsvd2:2; // 15:14 Reserved -}; - -union HRCNFG_REG { - Uint16 all; - struct HRCNFG_BITS bit; -}; - -struct HRPWR_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 rsvd2:1; // 2 Reserved - Uint16 rsvd3:1; // 3 Reserved - Uint16 rsvd4:1; // 4 Reserved - Uint16 rsvd5:1; // 5 Reserved - Uint16 rsvd6:4; // 9:6 Reserved - Uint16 rsvd7:5; // 14:10 Reserved - Uint16 CALPWRON:1; // 15 Calibration Power On -}; - -union HRPWR_REG { - Uint16 all; - struct HRPWR_BITS bit; -}; - -struct HRMSTEP_BITS { // bits description - Uint16 HRMSTEP:8; // 7:0 High Resolution Micro Step Value - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union HRMSTEP_REG { - Uint16 all; - struct HRMSTEP_BITS bit; -}; - -struct HRCNFG2_BITS { // bits description - Uint16 EDGMODEDB:2; // 1:0 Dead-Band Edge-Mode Select Bits - Uint16 CTLMODEDBRED:2; // 3:2 DBRED Control Mode Select Bits - Uint16 CTLMODEDBFED:2; // 5:4 DBFED Control Mode Select Bits - Uint16 rsvd1:8; // 13:6 Reserved - Uint16 rsvd2:1; // 14 Reserved - Uint16 rsvd3:1; // 15 Reserved -}; - -union HRCNFG2_REG { - Uint16 all; - struct HRCNFG2_BITS bit; -}; - -struct HRPCTL_BITS { // bits description - Uint16 HRPE:1; // 0 High Resolution Period Enable - Uint16 PWMSYNCSEL:1; // 1 PWMSYNC Source Select - Uint16 TBPHSHRLOADE:1; // 2 TBPHSHR Load Enable - Uint16 rsvd1:1; // 3 Reserved - Uint16 PWMSYNCSELX:3; // 6:4 PWMSYNCX Source Select Bit: - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union HRPCTL_REG { - Uint16 all; - struct HRPCTL_BITS bit; -}; - -struct TRREM_BITS { // bits description - Uint16 TRREM:11; // 10:0 Translator Remainder Bits - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union TRREM_REG { - Uint16 all; - struct TRREM_BITS bit; -}; - -struct GLDCTL_BITS { // bits description - Uint16 GLD:1; // 0 Global Shadow to Active load event control - Uint16 GLDMODE:4; // 4:1 Shadow to Active Global Load Pulse Selection - Uint16 OSHTMODE:1; // 5 One Shot Load mode control bit - Uint16 rsvd1:1; // 6 Reserved - Uint16 GLDPRD:3; // 9:7 Global Reload Strobe Period Select Register - Uint16 GLDCNT:3; // 12:10 Global Reload Strobe Counter Register - Uint16 rsvd2:3; // 15:13 Reserved -}; - -union GLDCTL_REG { - Uint16 all; - struct GLDCTL_BITS bit; -}; - -struct GLDCFG_BITS { // bits description - Uint16 TBPRD_TBPRDHR:1; // 0 Global load event configuration for TBPRD:TBPRDHR - Uint16 CMPA_CMPAHR:1; // 1 Global load event configuration for CMPA:CMPAHR - Uint16 CMPB_CMPBHR:1; // 2 Global load event configuration for CMPB:CMPBHR - Uint16 CMPC:1; // 3 Global load event configuration for CMPC - Uint16 CMPD:1; // 4 Global load event configuration for CMPD - Uint16 DBRED_DBREDHR:1; // 5 Global load event configuration for DBRED:DBREDHR - Uint16 DBFED_DBFEDHR:1; // 6 Global load event configuration for DBFED:DBFEDHR - Uint16 DBCTL:1; // 7 Global load event configuration for DBCTL - Uint16 AQCTLA_AQCTLA2:1; // 8 Global load event configuration for AQCTLA/A2 - Uint16 AQCTLB_AQCTLB2:1; // 9 Global load event configuration for AQCTLB/B2 - Uint16 AQCSFRC:1; // 10 Global load event configuration for AQCSFRC - Uint16 rsvd1:5; // 15:11 Reserved -}; - -union GLDCFG_REG { - Uint16 all; - struct GLDCFG_BITS bit; -}; - -struct EPWMXLINK_BITS { // bits description - Uint16 TBPRDLINK:4; // 3:0 TBPRD:TBPRDHR Link - Uint16 CMPALINK:4; // 7:4 CMPA:CMPAHR Link - Uint16 CMPBLINK:4; // 11:8 CMPB:CMPBHR Link - Uint16 CMPCLINK:4; // 15:12 CMPC Link - Uint16 CMPDLINK:4; // 19:16 CMPD Link - Uint16 rsvd1:8; // 27:20 Reserved - Uint16 GLDCTL2LINK:4; // 31:28 GLDCTL2 Link -}; - -union EPWMXLINK_REG { - Uint32 all; - struct EPWMXLINK_BITS bit; -}; - -struct EPWMREV_BITS { // bits description - Uint16 REV:8; // 7:0 EPWM Silicon Revision bits - Uint16 TYPE:8; // 15:8 EPWM Type Bits -}; - -union EPWMREV_REG { - Uint16 all; - struct EPWMREV_BITS bit; -}; - -struct AQCTLA_BITS { // bits description - Uint16 ZRO:2; // 1:0 Action Counter = Zero - Uint16 PRD:2; // 3:2 Action Counter = Period - Uint16 CAU:2; // 5:4 Action Counter = Compare A Up - Uint16 CAD:2; // 7:6 Action Counter = Compare A Down - Uint16 CBU:2; // 9:8 Action Counter = Compare B Up - Uint16 CBD:2; // 11:10 Action Counter = Compare B Down - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union AQCTLA_REG { - Uint16 all; - struct AQCTLA_BITS bit; -}; - -struct AQCTLA2_BITS { // bits description - Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count - Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count - Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count - Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union AQCTLA2_REG { - Uint16 all; - struct AQCTLA2_BITS bit; -}; - -struct AQCTLB_BITS { // bits description - Uint16 ZRO:2; // 1:0 Action Counter = Zero - Uint16 PRD:2; // 3:2 Action Counter = Period - Uint16 CAU:2; // 5:4 Action Counter = Compare A Up - Uint16 CAD:2; // 7:6 Action Counter = Compare A Down - Uint16 CBU:2; // 9:8 Action Counter = Compare B Up - Uint16 CBD:2; // 11:10 Action Counter = Compare B Down - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union AQCTLB_REG { - Uint16 all; - struct AQCTLB_BITS bit; -}; - -struct AQCTLB2_BITS { // bits description - Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count - Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count - Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count - Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union AQCTLB2_REG { - Uint16 all; - struct AQCTLB2_BITS bit; -}; - -struct AQSFRC_BITS { // bits description - Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A Invoked - Uint16 OTSFA:1; // 2 One-time SW Force A Output - Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B Invoked - Uint16 OTSFB:1; // 5 One-time SW Force A Output - Uint16 RLDCSF:2; // 7:6 Reload from Shadow Options - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union AQSFRC_REG { - Uint16 all; - struct AQSFRC_BITS bit; -}; - -struct AQCSFRC_BITS { // bits description - Uint16 CSFA:2; // 1:0 Continuous Software Force on output A - Uint16 CSFB:2; // 3:2 Continuous Software Force on output B - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union AQCSFRC_REG { - Uint16 all; - struct AQCSFRC_BITS bit; -}; - -struct DBREDHR_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:7; // 7:1 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 DBREDHR:7; // 15:9 DBREDHR High Resolution Bits -}; - -union DBREDHR_REG { - Uint16 all; - struct DBREDHR_BITS bit; -}; - -struct DBRED_BITS { // bits description - Uint16 DBRED:14; // 13:0 Rising edge delay value - Uint16 rsvd1:2; // 15:14 Reserved -}; - -union DBRED_REG { - Uint16 all; - struct DBRED_BITS bit; -}; - -struct DBFEDHR_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:7; // 7:1 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 DBFEDHR:7; // 15:9 DBFEDHR High Resolution Bits -}; - -union DBFEDHR_REG { - Uint16 all; - struct DBFEDHR_BITS bit; -}; - -struct DBFED_BITS { // bits description - Uint16 DBFED:14; // 13:0 Falling edge delay value - Uint16 rsvd1:2; // 15:14 Reserved -}; - -union DBFED_REG { - Uint16 all; - struct DBFED_BITS bit; -}; - -struct TBPHS_BITS { // bits description - Uint16 TBPHSHR:16; // 15:0 Extension Register for HRPWM Phase (8-bits) - Uint16 TBPHS:16; // 31:16 Phase Offset Register -}; - -union TBPHS_REG { - Uint32 all; - struct TBPHS_BITS bit; -}; - -struct CMPA_BITS { // bits description - Uint16 CMPAHR:16; // 15:0 Compare A HRPWM Extension Register - Uint16 CMPA:16; // 31:16 Compare A Register -}; - -union CMPA_REG { - Uint32 all; - struct CMPA_BITS bit; -}; - -struct CMPB_BITS { // bits description - Uint16 CMPBHR:16; // 15:0 Compare B High Resolution Bits - Uint16 CMPB:16; // 31:16 Compare B Register -}; - -union CMPB_REG { - Uint32 all; - struct CMPB_BITS bit; -}; - -struct GLDCTL2_BITS { // bits description - Uint16 OSHTLD:1; // 0 Enable reload event in one shot mode - Uint16 GFRCLD:1; // 1 Force reload event in one shot mode - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union GLDCTL2_REG { - Uint16 all; - struct GLDCTL2_BITS bit; -}; - -struct TZSEL_BITS { // bits description - Uint16 CBC1:1; // 0 TZ1 CBC select - Uint16 CBC2:1; // 1 TZ2 CBC select - Uint16 CBC3:1; // 2 TZ3 CBC select - Uint16 CBC4:1; // 3 TZ4 CBC select - Uint16 CBC5:1; // 4 TZ5 CBC select - Uint16 CBC6:1; // 5 TZ6 CBC select - Uint16 DCAEVT2:1; // 6 DCAEVT2 CBC select - Uint16 DCBEVT2:1; // 7 DCBEVT2 CBC select - Uint16 OSHT1:1; // 8 One-shot TZ1 select - Uint16 OSHT2:1; // 9 One-shot TZ2 select - Uint16 OSHT3:1; // 10 One-shot TZ3 select - Uint16 OSHT4:1; // 11 One-shot TZ4 select - Uint16 OSHT5:1; // 12 One-shot TZ5 select - Uint16 OSHT6:1; // 13 One-shot TZ6 select - Uint16 DCAEVT1:1; // 14 One-shot DCAEVT1 select - Uint16 DCBEVT1:1; // 15 One-shot DCBEVT1 select -}; - -union TZSEL_REG { - Uint16 all; - struct TZSEL_BITS bit; -}; - -struct TZDCSEL_BITS { // bits description - Uint16 DCAEVT1:3; // 2:0 Digital Compare Output A Event 1 - Uint16 DCAEVT2:3; // 5:3 Digital Compare Output A Event 2 - Uint16 DCBEVT1:3; // 8:6 Digital Compare Output B Event 1 - Uint16 DCBEVT2:3; // 11:9 Digital Compare Output B Event 2 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union TZDCSEL_REG { - Uint16 all; - struct TZDCSEL_BITS bit; -}; - -struct TZCTL_BITS { // bits description - Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA - Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB - Uint16 DCAEVT1:2; // 5:4 EPWMxA action on DCAEVT1 - Uint16 DCAEVT2:2; // 7:6 EPWMxA action on DCAEVT2 - Uint16 DCBEVT1:2; // 9:8 EPWMxB action on DCBEVT1 - Uint16 DCBEVT2:2; // 11:10 EPWMxB action on DCBEVT2 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union TZCTL_REG { - Uint16 all; - struct TZCTL_BITS bit; -}; - -struct TZCTL2_BITS { // bits description - Uint16 TZAU:3; // 2:0 Trip Action On EPWMxA while Count direction is UP - Uint16 TZAD:3; // 5:3 Trip Action On EPWMxA while Count direction is DOWN - Uint16 TZBU:3; // 8:6 Trip Action On EPWMxB while Count direction is UP - Uint16 TZBD:3; // 11:9 Trip Action On EPWMxB while Count direction is DOWN - Uint16 rsvd1:3; // 14:12 Reserved - Uint16 ETZE:1; // 15 TZCTL2 Enable -}; - -union TZCTL2_REG { - Uint16 all; - struct TZCTL2_BITS bit; -}; - -struct TZCTLDCA_BITS { // bits description - Uint16 DCAEVT1U:3; // 2:0 DCAEVT1 Action On EPWMxA while Count direction is UP - Uint16 DCAEVT1D:3; // 5:3 DCAEVT1 Action On EPWMxA while Count direction is DOWN - Uint16 DCAEVT2U:3; // 8:6 DCAEVT2 Action On EPWMxA while Count direction is UP - Uint16 DCAEVT2D:3; // 11:9 DCAEVT2 Action On EPWMxA while Count direction is DOWN - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union TZCTLDCA_REG { - Uint16 all; - struct TZCTLDCA_BITS bit; -}; - -struct TZCTLDCB_BITS { // bits description - Uint16 DCBEVT1U:3; // 2:0 DCBEVT1 Action On EPWMxA while Count direction is UP - Uint16 DCBEVT1D:3; // 5:3 DCBEVT1 Action On EPWMxA while Count direction is DOWN - Uint16 DCBEVT2U:3; // 8:6 DCBEVT2 Action On EPWMxA while Count direction is UP - Uint16 DCBEVT2D:3; // 11:9 DCBEVT2 Action On EPWMxA while Count direction is DOWN - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union TZCTLDCB_REG { - Uint16 all; - struct TZCTLDCB_BITS bit; -}; - -struct TZEINT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable - Uint16 OST:1; // 2 Trip Zones One Shot Int Enable - Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Int Enable - Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Int Enable - Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Int Enable - Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Int Enable - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union TZEINT_REG { - Uint16 all; - struct TZEINT_BITS bit; -}; - -struct TZFLG_BITS { // bits description - Uint16 INT:1; // 0 Global Int Status Flag - Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Flag - Uint16 OST:1; // 2 Trip Zones One Shot Flag - Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Flag - Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Flag - Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Flag - Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Flag - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union TZFLG_REG { - Uint16 all; - struct TZFLG_BITS bit; -}; - -struct TZCBCFLG_BITS { // bits description - Uint16 CBC1:1; // 0 Latched Status Flag for CBC1 Trip Latch - Uint16 CBC2:1; // 1 Latched Status Flag for CBC2 Trip Latch - Uint16 CBC3:1; // 2 Latched Status Flag for CBC3 Trip Latch - Uint16 CBC4:1; // 3 Latched Status Flag for CBC4 Trip Latch - Uint16 CBC5:1; // 4 Latched Status Flag for CBC5 Trip Latch - Uint16 CBC6:1; // 5 Latched Status Flag for CBC6 Trip Latch - Uint16 DCAEVT2:1; // 6 Latched Status Flag for Digital Compare Output A Event 2 - Uint16 DCBEVT2:1; // 7 Latched Status Flag for Digital Compare Output B Event 2 - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TZCBCFLG_REG { - Uint16 all; - struct TZCBCFLG_BITS bit; -}; - -struct TZOSTFLG_BITS { // bits description - Uint16 OST1:1; // 0 Latched Status Flag for OST1 Trip Latch - Uint16 OST2:1; // 1 Latched Status Flag for OST2 Trip Latch - Uint16 OST3:1; // 2 Latched Status Flag for OST3 Trip Latch - Uint16 OST4:1; // 3 Latched Status Flag for OST4 Trip Latch - Uint16 OST5:1; // 4 Latched Status Flag for OST5 Trip Latch - Uint16 OST6:1; // 5 Latched Status Flag for OST6 Trip Latch - Uint16 DCAEVT1:1; // 6 Latched Status Flag for Digital Compare Output A Event 1 - Uint16 DCBEVT1:1; // 7 Latched Status Flag for Digital Compare Output B Event 1 - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TZOSTFLG_REG { - Uint16 all; - struct TZOSTFLG_BITS bit; -}; - -struct TZCLR_BITS { // bits description - Uint16 INT:1; // 0 Global Interrupt Clear Flag - Uint16 CBC:1; // 1 Cycle-By-Cycle Flag Clear - Uint16 OST:1; // 2 One-Shot Flag Clear - Uint16 DCAEVT1:1; // 3 DCAVET1 Flag Clear - Uint16 DCAEVT2:1; // 4 DCAEVT2 Flag Clear - Uint16 DCBEVT1:1; // 5 DCBEVT1 Flag Clear - Uint16 DCBEVT2:1; // 6 DCBEVT2 Flag Clear - Uint16 rsvd1:7; // 13:7 Reserved - Uint16 CBCPULSE:2; // 15:14 Clear Pulse for CBC Trip Latch -}; - -union TZCLR_REG { - Uint16 all; - struct TZCLR_BITS bit; -}; - -struct TZCBCCLR_BITS { // bits description - Uint16 CBC1:1; // 0 Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch - Uint16 CBC2:1; // 1 Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch - Uint16 CBC3:1; // 2 Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch - Uint16 CBC4:1; // 3 Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch - Uint16 CBC5:1; // 4 Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch - Uint16 CBC6:1; // 5 Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch - Uint16 DCAEVT2:1; // 6 Clear Flag forDCAEVT2 selected for CBC - Uint16 DCBEVT2:1; // 7 Clear Flag for DCBEVT2 selected for CBC - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TZCBCCLR_REG { - Uint16 all; - struct TZCBCCLR_BITS bit; -}; - -struct TZOSTCLR_BITS { // bits description - Uint16 OST1:1; // 0 Clear Flag for Oneshot (OST1) Trip Latch - Uint16 OST2:1; // 1 Clear Flag for Oneshot (OST2) Trip Latch - Uint16 OST3:1; // 2 Clear Flag for Oneshot (OST3) Trip Latch - Uint16 OST4:1; // 3 Clear Flag for Oneshot (OST4) Trip Latch - Uint16 OST5:1; // 4 Clear Flag for Oneshot (OST5) Trip Latch - Uint16 OST6:1; // 5 Clear Flag for Oneshot (OST6) Trip Latch - Uint16 DCAEVT1:1; // 6 Clear Flag for DCAEVT1 selected for OST - Uint16 DCBEVT1:1; // 7 Clear Flag for DCBEVT1 selected for OST - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union TZOSTCLR_REG { - Uint16 all; - struct TZOSTCLR_BITS bit; -}; - -struct TZFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CBC:1; // 1 Force Trip Zones Cycle By Cycle Event - Uint16 OST:1; // 2 Force Trip Zones One Shot Event - Uint16 DCAEVT1:1; // 3 Force Digital Compare A Event 1 - Uint16 DCAEVT2:1; // 4 Force Digital Compare A Event 2 - Uint16 DCBEVT1:1; // 5 Force Digital Compare B Event 1 - Uint16 DCBEVT2:1; // 6 Force Digital Compare B Event 2 - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union TZFRC_REG { - Uint16 all; - struct TZFRC_BITS bit; -}; - -struct ETSEL_BITS { // bits description - Uint16 INTSEL:3; // 2:0 EPWMxINTn Select - Uint16 INTEN:1; // 3 EPWMxINTn Enable - Uint16 SOCASELCMP:1; // 4 EPWMxSOCA Compare Select - Uint16 SOCBSELCMP:1; // 5 EPWMxSOCB Compare Select - Uint16 INTSELCMP:1; // 6 EPWMxINT Compare Select - Uint16 rsvd1:1; // 7 Reserved - Uint16 SOCASEL:3; // 10:8 Start of Conversion A Select - Uint16 SOCAEN:1; // 11 Start of Conversion A Enable - Uint16 SOCBSEL:3; // 14:12 Start of Conversion B Select - Uint16 SOCBEN:1; // 15 Start of Conversion B Enable -}; - -union ETSEL_REG { - Uint16 all; - struct ETSEL_BITS bit; -}; - -struct ETPS_BITS { // bits description - Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select - Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register - Uint16 INTPSSEL:1; // 4 EPWMxINTn Pre-Scale Selection Bits - Uint16 SOCPSSEL:1; // 5 EPWMxSOC A/B Pre-Scale Selection Bits - Uint16 rsvd1:2; // 7:6 Reserved - Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select - Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register - Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select - Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter -}; - -union ETPS_REG { - Uint16 all; - struct ETPS_BITS bit; -}; - -struct ETFLG_BITS { // bits description - Uint16 INT:1; // 0 EPWMxINTn Flag - Uint16 rsvd1:1; // 1 Reserved - Uint16 SOCA:1; // 2 EPWMxSOCA Flag - Uint16 SOCB:1; // 3 EPWMxSOCB Flag - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union ETFLG_REG { - Uint16 all; - struct ETFLG_BITS bit; -}; - -struct ETCLR_BITS { // bits description - Uint16 INT:1; // 0 EPWMxINTn Clear - Uint16 rsvd1:1; // 1 Reserved - Uint16 SOCA:1; // 2 EPWMxSOCA Clear - Uint16 SOCB:1; // 3 EPWMxSOCB Clear - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union ETCLR_REG { - Uint16 all; - struct ETCLR_BITS bit; -}; - -struct ETFRC_BITS { // bits description - Uint16 INT:1; // 0 EPWMxINTn Force - Uint16 rsvd1:1; // 1 Reserved - Uint16 SOCA:1; // 2 EPWMxSOCA Force - Uint16 SOCB:1; // 3 EPWMxSOCB Force - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union ETFRC_REG { - Uint16 all; - struct ETFRC_BITS bit; -}; - -struct ETINTPS_BITS { // bits description - Uint16 INTPRD2:4; // 3:0 EPWMxINTn Period Select - Uint16 INTCNT2:4; // 7:4 EPWMxINTn Counter Register - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union ETINTPS_REG { - Uint16 all; - struct ETINTPS_BITS bit; -}; - -struct ETSOCPS_BITS { // bits description - Uint16 SOCAPRD2:4; // 3:0 EPWMxSOCA Period Select - Uint16 SOCACNT2:4; // 7:4 EPWMxSOCA Counter Register - Uint16 SOCBPRD2:4; // 11:8 EPWMxSOCB Period Select - Uint16 SOCBCNT2:4; // 15:12 EPWMxSOCB Counter Register -}; - -union ETSOCPS_REG { - Uint16 all; - struct ETSOCPS_BITS bit; -}; - -struct ETCNTINITCTL_BITS { // bits description - Uint16 rsvd1:10; // 9:0 Reserved - Uint16 INTINITFRC:1; // 10 EPWMxINT Counter Initialization Force - Uint16 SOCAINITFRC:1; // 11 EPWMxSOCA Counter Initialization Force - Uint16 SOCBINITFRC:1; // 12 EPWMxSOCB Counter Initialization Force - Uint16 INTINITEN:1; // 13 EPWMxINT Counter Initialization Enable - Uint16 SOCAINITEN:1; // 14 EPWMxSOCA Counter Initialization Enable - Uint16 SOCBINITEN:1; // 15 EPWMxSOCB Counter Initialization Enable -}; - -union ETCNTINITCTL_REG { - Uint16 all; - struct ETCNTINITCTL_BITS bit; -}; - -struct ETCNTINIT_BITS { // bits description - Uint16 INTINIT:4; // 3:0 EPWMxINT Counter Initialization Bits - Uint16 SOCAINIT:4; // 7:4 EPWMxSOCA Counter Initialization Bits - Uint16 SOCBINIT:4; // 11:8 EPWMxSOCB Counter Initialization Bits - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union ETCNTINIT_REG { - Uint16 all; - struct ETCNTINIT_BITS bit; -}; - -struct DCTRIPSEL_BITS { // bits description - Uint16 DCAHCOMPSEL:4; // 3:0 Digital Compare A High COMP Input Select - Uint16 DCALCOMPSEL:4; // 7:4 Digital Compare A Low COMP Input Select - Uint16 DCBHCOMPSEL:4; // 11:8 Digital Compare B High COMP Input Select - Uint16 DCBLCOMPSEL:4; // 15:12 Digital Compare B Low COMP Input Select -}; - -union DCTRIPSEL_REG { - Uint16 all; - struct DCTRIPSEL_BITS bit; -}; - -struct DCACTL_BITS { // bits description - Uint16 EVT1SRCSEL:1; // 0 DCAEVT1 Source Signal - Uint16 EVT1FRCSYNCSEL:1; // 1 DCAEVT1 Force Sync Signal - Uint16 EVT1SOCE:1; // 2 DCAEVT1 SOC Enable - Uint16 EVT1SYNCE:1; // 3 DCAEVT1 SYNC Enable - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:2; // 6:5 Reserved - Uint16 rsvd3:1; // 7 Reserved - Uint16 EVT2SRCSEL:1; // 8 DCAEVT2 Source Signal - Uint16 EVT2FRCSYNCSEL:1; // 9 DCAEVT2 Force Sync Signal - Uint16 rsvd4:2; // 11:10 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 rsvd6:2; // 14:13 Reserved - Uint16 rsvd7:1; // 15 Reserved -}; - -union DCACTL_REG { - Uint16 all; - struct DCACTL_BITS bit; -}; - -struct DCBCTL_BITS { // bits description - Uint16 EVT1SRCSEL:1; // 0 DCBEVT1 Source Signal - Uint16 EVT1FRCSYNCSEL:1; // 1 DCBEVT1 Force Sync Signal - Uint16 EVT1SOCE:1; // 2 DCBEVT1 SOC Enable - Uint16 EVT1SYNCE:1; // 3 DCBEVT1 SYNC Enable - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:2; // 6:5 Reserved - Uint16 rsvd3:1; // 7 Reserved - Uint16 EVT2SRCSEL:1; // 8 DCBEVT2 Source Signal - Uint16 EVT2FRCSYNCSEL:1; // 9 DCBEVT2 Force Sync Signal - Uint16 rsvd4:2; // 11:10 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 rsvd6:2; // 14:13 Reserved - Uint16 rsvd7:1; // 15 Reserved -}; - -union DCBCTL_REG { - Uint16 all; - struct DCBCTL_BITS bit; -}; - -struct DCFCTL_BITS { // bits description - Uint16 SRCSEL:2; // 1:0 Filter Block Signal Source Select - Uint16 BLANKE:1; // 2 Blanking Enable/Disable - Uint16 BLANKINV:1; // 3 Blanking Window Inversion - Uint16 PULSESEL:2; // 5:4 Pulse Select for Blanking & Capture Alignment - Uint16 EDGEFILTSEL:1; // 6 Edge Filter Select - Uint16 rsvd1:1; // 7 Reserved - Uint16 EDGEMODE:2; // 9:8 Edge Mode - Uint16 EDGECOUNT:3; // 12:10 Edge Count - Uint16 EDGESTATUS:3; // 15:13 Edge Status -}; - -union DCFCTL_REG { - Uint16 all; - struct DCFCTL_BITS bit; -}; - -struct DCCAPCTL_BITS { // bits description - Uint16 CAPE:1; // 0 Counter Capture Enable - Uint16 SHDWMODE:1; // 1 Counter Capture Mode - Uint16 rsvd1:11; // 12:2 Reserved - Uint16 CAPSTS:1; // 13 Latched Status Flag for Capture Event - Uint16 CAPCLR:1; // 14 DC Capture Latched Status Clear Flag - Uint16 CAPMODE:1; // 15 Counter Capture Mode -}; - -union DCCAPCTL_REG { - Uint16 all; - struct DCCAPCTL_BITS bit; -}; - -struct DCAHTRIPSEL_BITS { // bits description - Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAH Mux - Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAH Mux - Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAH Mux - Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAH Mux - Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAH Mux - Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAH Mux - Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAH Mux - Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAH Mux - Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAH Mux - Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAH Mux - Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAH Mux - Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAH Mux - Uint16 rsvd1:1; // 12 Reserved - Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAH Mux - Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAH Mux - Uint16 rsvd2:1; // 15 Reserved -}; - -union DCAHTRIPSEL_REG { - Uint16 all; - struct DCAHTRIPSEL_BITS bit; -}; - -struct DCALTRIPSEL_BITS { // bits description - Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAL Mux - Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAL Mux - Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAL Mux - Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAL Mux - Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAL Mux - Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAL Mux - Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAL Mux - Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAL Mux - Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAL Mux - Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAL Mux - Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAL Mux - Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAL Mux - Uint16 rsvd1:1; // 12 Reserved - Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAL Mux - Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAL Mux - Uint16 rsvd2:1; // 15 Reserved -}; - -union DCALTRIPSEL_REG { - Uint16 all; - struct DCALTRIPSEL_BITS bit; -}; - -struct DCBHTRIPSEL_BITS { // bits description - Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBH Mux - Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBH Mux - Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBH Mux - Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBH Mux - Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBH Mux - Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBH Mux - Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBH Mux - Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBH Mux - Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBH Mux - Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBH Mux - Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBH Mux - Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBH Mux - Uint16 rsvd1:1; // 12 Reserved - Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBH Mux - Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBH Mux - Uint16 rsvd2:1; // 15 Reserved -}; - -union DCBHTRIPSEL_REG { - Uint16 all; - struct DCBHTRIPSEL_BITS bit; -}; - -struct DCBLTRIPSEL_BITS { // bits description - Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBL Mux - Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBL Mux - Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBL Mux - Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBL Mux - Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBL Mux - Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBL Mux - Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBL Mux - Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBL Mux - Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBL Mux - Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBL Mux - Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBL Mux - Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBL Mux - Uint16 rsvd1:1; // 12 Reserved - Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBL Mux - Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBL Mux - Uint16 rsvd2:1; // 15 Reserved -}; - -union DCBLTRIPSEL_REG { - Uint16 all; - struct DCBLTRIPSEL_BITS bit; -}; - -struct EPWM_REGS { - union TBCTL_REG TBCTL; // Time Base Control Register - union TBCTL2_REG TBCTL2; // Time Base Control Register 2 - Uint16 rsvd1[2]; // Reserved - Uint16 TBCTR; // Time Base Counter Register - union TBSTS_REG TBSTS; // Time Base Status Register - Uint16 rsvd2[2]; // Reserved - union CMPCTL_REG CMPCTL; // Counter Compare Control Register - union CMPCTL2_REG CMPCTL2; // Counter Compare Control Register 2 - Uint16 rsvd3[2]; // Reserved - union DBCTL_REG DBCTL; // Dead-Band Generator Control Register - union DBCTL2_REG DBCTL2; // Dead-Band Generator Control Register 2 - Uint16 rsvd4[2]; // Reserved - union AQCTL_REG AQCTL; // Action Qualifier Control Register - union AQTSRCSEL_REG AQTSRCSEL; // Action Qualifier Trigger Event Source Select Register - Uint16 rsvd5[2]; // Reserved - union PCCTL_REG PCCTL; // PWM Chopper Control Register - Uint16 rsvd6[3]; // Reserved - union VCAPCTL_REG VCAPCTL; // Valley Capture Control Register - union VCNTCFG_REG VCNTCFG; // Valley Counter Config Register - Uint16 rsvd7[6]; // Reserved - union HRCNFG_REG HRCNFG; // HRPWM Configuration Register - union HRPWR_REG HRPWR; // HRPWM Power Register - Uint16 rsvd8[4]; // Reserved - union HRMSTEP_REG HRMSTEP; // HRPWM MEP Step Register - union HRCNFG2_REG HRCNFG2; // HRPWM Configuration 2 Register - Uint16 rsvd9[5]; // Reserved - union HRPCTL_REG HRPCTL; // High Resolution Period Control Register - union TRREM_REG TRREM; // Translator High Resolution Remainder Register - Uint16 rsvd10[5]; // Reserved - union GLDCTL_REG GLDCTL; // Global PWM Load Control Register - union GLDCFG_REG GLDCFG; // Global PWM Load Config Register - Uint16 rsvd11[2]; // Reserved - union EPWMXLINK_REG EPWMXLINK; // EPWMx Link Register - Uint16 rsvd12[4]; // Reserved - union EPWMREV_REG EPWMREV; // EPWM Revision Register - Uint16 rsvd13; // Reserved - union AQCTLA_REG AQCTLA; // Action Qualifier Control Register For Output A - union AQCTLA2_REG AQCTLA2; // Additional Action Qualifier Control Register For Output A - union AQCTLB_REG AQCTLB; // Action Qualifier Control Register For Output B - union AQCTLB2_REG AQCTLB2; // Additional Action Qualifier Control Register For Output B - Uint16 rsvd14[3]; // Reserved - union AQSFRC_REG AQSFRC; // Action Qualifier Software Force Register - Uint16 rsvd15; // Reserved - union AQCSFRC_REG AQCSFRC; // Action Qualifier Continuous S/W Force Register - Uint16 rsvd16[6]; // Reserved - union DBREDHR_REG DBREDHR; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register - union DBRED_REG DBRED; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register - union DBFEDHR_REG DBFEDHR; // Dead-Band Generator Falling Edge Delay High Resolution Register - union DBFED_REG DBFED; // Dead-Band Generator Falling Edge Delay Count Register - Uint16 rsvd17[12]; // Reserved - union TBPHS_REG TBPHS; // Time Base Phase High - Uint16 TBPRDHR; // Time Base Period High Resolution Register - Uint16 TBPRD; // Time Base Period Register - Uint16 rsvd18[6]; // Reserved - union CMPA_REG CMPA; // Counter Compare A Register - union CMPB_REG CMPB; // Compare B Register - Uint16 rsvd19; // Reserved - Uint16 CMPC; // Counter Compare C Register - Uint16 rsvd20; // Reserved - Uint16 CMPD; // Counter Compare D Register - Uint16 rsvd21[2]; // Reserved - union GLDCTL2_REG GLDCTL2; // Global PWM Load Control Register 2 - Uint16 rsvd22[2]; // Reserved - Uint16 SWVDELVAL; // Software Valley Mode Delay Register - Uint16 rsvd23[8]; // Reserved - union TZSEL_REG TZSEL; // Trip Zone Select Register - Uint16 rsvd24; // Reserved - union TZDCSEL_REG TZDCSEL; // Trip Zone Digital Comparator Select Register - Uint16 rsvd25; // Reserved - union TZCTL_REG TZCTL; // Trip Zone Control Register - union TZCTL2_REG TZCTL2; // Additional Trip Zone Control Register - union TZCTLDCA_REG TZCTLDCA; // Trip Zone Control Register Digital Compare A - union TZCTLDCB_REG TZCTLDCB; // Trip Zone Control Register Digital Compare B - Uint16 rsvd26[5]; // Reserved - union TZEINT_REG TZEINT; // Trip Zone Enable Interrupt Register - Uint16 rsvd27[5]; // Reserved - union TZFLG_REG TZFLG; // Trip Zone Flag Register - union TZCBCFLG_REG TZCBCFLG; // Trip Zone CBC Flag Register - union TZOSTFLG_REG TZOSTFLG; // Trip Zone OST Flag Register - Uint16 rsvd28; // Reserved - union TZCLR_REG TZCLR; // Trip Zone Clear Register - union TZCBCCLR_REG TZCBCCLR; // Trip Zone CBC Clear Register - union TZOSTCLR_REG TZOSTCLR; // Trip Zone OST Clear Register - Uint16 rsvd29; // Reserved - union TZFRC_REG TZFRC; // Trip Zone Force Register - Uint16 rsvd30[8]; // Reserved - union ETSEL_REG ETSEL; // Event Trigger Selection Register - Uint16 rsvd31; // Reserved - union ETPS_REG ETPS; // Event Trigger Pre-Scale Register - Uint16 rsvd32; // Reserved - union ETFLG_REG ETFLG; // Event Trigger Flag Register - Uint16 rsvd33; // Reserved - union ETCLR_REG ETCLR; // Event Trigger Clear Register - Uint16 rsvd34; // Reserved - union ETFRC_REG ETFRC; // Event Trigger Force Register - Uint16 rsvd35; // Reserved - union ETINTPS_REG ETINTPS; // Event-Trigger Interrupt Pre-Scale Register - Uint16 rsvd36; // Reserved - union ETSOCPS_REG ETSOCPS; // Event-Trigger SOC Pre-Scale Register - Uint16 rsvd37; // Reserved - union ETCNTINITCTL_REG ETCNTINITCTL; // Event-Trigger Counter Initialization Control Register - Uint16 rsvd38; // Reserved - union ETCNTINIT_REG ETCNTINIT; // Event-Trigger Counter Initialization Register - Uint16 rsvd39[11]; // Reserved - union DCTRIPSEL_REG DCTRIPSEL; // Digital Compare Trip Select Register - Uint16 rsvd40[2]; // Reserved - union DCACTL_REG DCACTL; // Digital Compare A Control Register - union DCBCTL_REG DCBCTL; // Digital Compare B Control Register - Uint16 rsvd41[2]; // Reserved - union DCFCTL_REG DCFCTL; // Digital Compare Filter Control Register - union DCCAPCTL_REG DCCAPCTL; // Digital Compare Capture Control Register - Uint16 DCFOFFSET; // Digital Compare Filter Offset Register - Uint16 DCFOFFSETCNT; // Digital Compare Filter Offset Counter Register - Uint16 DCFWINDOW; // Digital Compare Filter Window Register - Uint16 DCFWINDOWCNT; // Digital Compare Filter Window Counter Register - Uint16 rsvd42[2]; // Reserved - Uint16 DCCAP; // Digital Compare Counter Capture Register - Uint16 rsvd43[2]; // Reserved - union DCAHTRIPSEL_REG DCAHTRIPSEL; // Digital Compare AH Trip Select - union DCALTRIPSEL_REG DCALTRIPSEL; // Digital Compare AL Trip Select - union DCBHTRIPSEL_REG DCBHTRIPSEL; // Digital Compare BH Trip Select - union DCBLTRIPSEL_REG DCBLTRIPSEL; // Digital Compare BL Trip Select - Uint16 rsvd44[39]; // Reserved - Uint16 HWVDELVAL; // Hardware Valley Mode Delay Register - Uint16 VCNTVAL; // Hardware Valley Counter Register - Uint16 rsvd45; // Reserved -}; - -//--------------------------------------------------------------------------- -// EPWM External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct EPWM_REGS EPwm1Regs; -extern volatile struct EPWM_REGS EPwm2Regs; -extern volatile struct EPWM_REGS EPwm3Regs; -extern volatile struct EPWM_REGS EPwm4Regs; -extern volatile struct EPWM_REGS EPwm5Regs; -extern volatile struct EPWM_REGS EPwm6Regs; -extern volatile struct EPWM_REGS EPwm7Regs; -extern volatile struct EPWM_REGS EPwm8Regs; -extern volatile struct EPWM_REGS EPwm9Regs; -extern volatile struct EPWM_REGS EPwm10Regs; -extern volatile struct EPWM_REGS EPwm11Regs; -extern volatile struct EPWM_REGS EPwm12Regs; -#endif -#ifdef CPU2 -extern volatile struct EPWM_REGS EPwm1Regs; -extern volatile struct EPWM_REGS EPwm2Regs; -extern volatile struct EPWM_REGS EPwm3Regs; -extern volatile struct EPWM_REGS EPwm4Regs; -extern volatile struct EPWM_REGS EPwm5Regs; -extern volatile struct EPWM_REGS EPwm6Regs; -extern volatile struct EPWM_REGS EPwm7Regs; -extern volatile struct EPWM_REGS EPwm8Regs; -extern volatile struct EPWM_REGS EPwm9Regs; -extern volatile struct EPWM_REGS EPwm10Regs; -extern volatile struct EPWM_REGS EPwm11Regs; -extern volatile struct EPWM_REGS EPwm12Regs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm_xbar.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm_xbar.h deleted file mode 100644 index 47f85e18fe..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm_xbar.h +++ /dev/null @@ -1,832 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_epwm_xbar.h -// -// TITLE: EPWM_XBAR Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_EPWM_XBAR_H__ -#define __F2837xD_EPWM_XBAR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// EPWM_XBAR Individual Register Bit Definitions: - -struct TRIP4MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP4 of EPWM-XBAR -}; - -union TRIP4MUX0TO15CFG_REG { - Uint32 all; - struct TRIP4MUX0TO15CFG_BITS bit; -}; - -struct TRIP4MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP4 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP4 of EPWM-XBAR -}; - -union TRIP4MUX16TO31CFG_REG { - Uint32 all; - struct TRIP4MUX16TO31CFG_BITS bit; -}; - -struct TRIP5MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP5 of EPWM-XBAR -}; - -union TRIP5MUX0TO15CFG_REG { - Uint32 all; - struct TRIP5MUX0TO15CFG_BITS bit; -}; - -struct TRIP5MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP5 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP5 of EPWM-XBAR -}; - -union TRIP5MUX16TO31CFG_REG { - Uint32 all; - struct TRIP5MUX16TO31CFG_BITS bit; -}; - -struct TRIP7MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP7 of EPWM-XBAR -}; - -union TRIP7MUX0TO15CFG_REG { - Uint32 all; - struct TRIP7MUX0TO15CFG_BITS bit; -}; - -struct TRIP7MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP7 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP7 of EPWM-XBAR -}; - -union TRIP7MUX16TO31CFG_REG { - Uint32 all; - struct TRIP7MUX16TO31CFG_BITS bit; -}; - -struct TRIP8MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP8 of EPWM-XBAR -}; - -union TRIP8MUX0TO15CFG_REG { - Uint32 all; - struct TRIP8MUX0TO15CFG_BITS bit; -}; - -struct TRIP8MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP8 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP8 of EPWM-XBAR -}; - -union TRIP8MUX16TO31CFG_REG { - Uint32 all; - struct TRIP8MUX16TO31CFG_BITS bit; -}; - -struct TRIP9MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP9 of EPWM-XBAR -}; - -union TRIP9MUX0TO15CFG_REG { - Uint32 all; - struct TRIP9MUX0TO15CFG_BITS bit; -}; - -struct TRIP9MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP9 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP9 of EPWM-XBAR -}; - -union TRIP9MUX16TO31CFG_REG { - Uint32 all; - struct TRIP9MUX16TO31CFG_BITS bit; -}; - -struct TRIP10MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP10 of EPWM-XBAR -}; - -union TRIP10MUX0TO15CFG_REG { - Uint32 all; - struct TRIP10MUX0TO15CFG_BITS bit; -}; - -struct TRIP10MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP10 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP10 of EPWM-XBAR -}; - -union TRIP10MUX16TO31CFG_REG { - Uint32 all; - struct TRIP10MUX16TO31CFG_BITS bit; -}; - -struct TRIP11MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP11 of EPWM-XBAR -}; - -union TRIP11MUX0TO15CFG_REG { - Uint32 all; - struct TRIP11MUX0TO15CFG_BITS bit; -}; - -struct TRIP11MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP11 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP11 of EPWM-XBAR -}; - -union TRIP11MUX16TO31CFG_REG { - Uint32 all; - struct TRIP11MUX16TO31CFG_BITS bit; -}; - -struct TRIP12MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP12 of EPWM-XBAR -}; - -union TRIP12MUX0TO15CFG_REG { - Uint32 all; - struct TRIP12MUX0TO15CFG_BITS bit; -}; - -struct TRIP12MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP12 of EPWM-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP12 of EPWM-XBAR -}; - -union TRIP12MUX16TO31CFG_REG { - Uint32 all; - struct TRIP12MUX16TO31CFG_BITS bit; -}; - -struct TRIP4MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP4 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP4 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP4 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP4 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP4 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP4 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP4 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP4 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP4 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP4 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP4 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP4 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP4 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP4 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP4 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP4 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP4 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP4 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP4 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP4 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP4 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP4 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP4 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP4 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP4 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP4 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP4 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP4 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP4 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP4 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP4 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP4 of EPWM-XBAR -}; - -union TRIP4MUXENABLE_REG { - Uint32 all; - struct TRIP4MUXENABLE_BITS bit; -}; - -struct TRIP5MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP5 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP5 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP5 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP5 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP5 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP5 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP5 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP5 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP5 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP5 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP5 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP5 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP5 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP5 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP5 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP5 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP5 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP5 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP5 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP5 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP5 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP5 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP5 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP5 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP5 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP5 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP5 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP5 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP5 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP5 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP5 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP5 of EPWM-XBAR -}; - -union TRIP5MUXENABLE_REG { - Uint32 all; - struct TRIP5MUXENABLE_BITS bit; -}; - -struct TRIP7MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP7 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP7 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP7 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP7 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP7 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP7 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP7 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP7 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP7 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP7 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP7 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP7 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP7 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP7 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP7 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP7 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP7 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP7 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP7 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP7 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP7 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP7 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP7 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP7 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP7 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP7 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP7 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP7 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP7 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP7 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP7 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP7 of EPWM-XBAR -}; - -union TRIP7MUXENABLE_REG { - Uint32 all; - struct TRIP7MUXENABLE_BITS bit; -}; - -struct TRIP8MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP8 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP8 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP8 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP8 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP8 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP8 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP8 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP8 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP8 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP8 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP8 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP8 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP8 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP8 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP8 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP8 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP8 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP8 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP8 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP8 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP8 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP8 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP8 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP8 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP8 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP8 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP8 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP8 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP8 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP8 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP8 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP8 of EPWM-XBAR -}; - -union TRIP8MUXENABLE_REG { - Uint32 all; - struct TRIP8MUXENABLE_BITS bit; -}; - -struct TRIP9MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP9 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP9 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP9 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP9 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP9 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP9 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP9 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP9 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP9 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP9 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP9 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP9 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP9 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP9 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP9 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP9 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP9 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP9 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP9 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP9 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP9 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP9 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP9 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP9 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP9 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP9 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP9 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP9 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP9 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP9 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP9 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP9 of EPWM-XBAR -}; - -union TRIP9MUXENABLE_REG { - Uint32 all; - struct TRIP9MUXENABLE_BITS bit; -}; - -struct TRIP10MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP10 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP10 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP10 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP10 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP10 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP10 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP10 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP10 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP10 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP10 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP10 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP10 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP10 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP10 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP10 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP10 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP10 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP10 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP10 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP10 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP10 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP10 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP10 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP10 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP10 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP10 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP10 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP10 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP10 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP10 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP10 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP10 of EPWM-XBAR -}; - -union TRIP10MUXENABLE_REG { - Uint32 all; - struct TRIP10MUXENABLE_BITS bit; -}; - -struct TRIP11MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP11 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP11 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP11 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP11 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP11 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP11 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP11 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP11 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP11 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP11 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP11 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP11 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP11 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP11 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP11 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP11 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP11 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP11 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP11 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP11 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP11 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP11 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP11 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP11 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP11 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP11 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP11 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP11 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP11 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP11 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP11 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP11 of EPWM-XBAR -}; - -union TRIP11MUXENABLE_REG { - Uint32 all; - struct TRIP11MUXENABLE_BITS bit; -}; - -struct TRIP12MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive TRIP12 of EPWM-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive TRIP12 of EPWM-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive TRIP12 of EPWM-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive TRIP12 of EPWM-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive TRIP12 of EPWM-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive TRIP12 of EPWM-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive TRIP12 of EPWM-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive TRIP12 of EPWM-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive TRIP12 of EPWM-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive TRIP12 of EPWM-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive TRIP12 of EPWM-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive TRIP12 of EPWM-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive TRIP12 of EPWM-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive TRIP12 of EPWM-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive TRIP12 of EPWM-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive TRIP12 of EPWM-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive TRIP12 of EPWM-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive TRIP12 of EPWM-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive TRIP12 of EPWM-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive TRIP12 of EPWM-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive TRIP12 of EPWM-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive TRIP12 of EPWM-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive TRIP12 of EPWM-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive TRIP12 of EPWM-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive TRIP12 of EPWM-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive TRIP12 of EPWM-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive TRIP12 of EPWM-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive TRIP12 of EPWM-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive TRIP12 of EPWM-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive TRIP12 of EPWM-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive TRIP12 of EPWM-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive TRIP12 of EPWM-XBAR -}; - -union TRIP12MUXENABLE_REG { - Uint32 all; - struct TRIP12MUXENABLE_BITS bit; -}; - -struct TRIPOUTINV_BITS { // bits description - Uint16 TRIP4:1; // 0 Selects polarity for TRIP4 of EPWM-XBAR - Uint16 TRIP5:1; // 1 Selects polarity for TRIP5 of EPWM-XBAR - Uint16 TRIP7:1; // 2 Selects polarity for TRIP7 of EPWM-XBAR - Uint16 TRIP8:1; // 3 Selects polarity for TRIP8 of EPWM-XBAR - Uint16 TRIP9:1; // 4 Selects polarity for TRIP9 of EPWM-XBAR - Uint16 TRIP10:1; // 5 Selects polarity for TRIP10 of EPWM-XBAR - Uint16 TRIP11:1; // 6 Selects polarity for TRIP11 of EPWM-XBAR - Uint16 TRIP12:1; // 7 Selects polarity for TRIP12 of EPWM-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union TRIPOUTINV_REG { - Uint32 all; - struct TRIPOUTINV_BITS bit; -}; - -struct TRIPLOCK_BITS { // bits description - Uint16 LOCK:1; // 0 Locks the configuration for EPWM-XBAR - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 KEY:16; // 31:16 Write protection KEY -}; - -union TRIPLOCK_REG { - Uint32 all; - struct TRIPLOCK_BITS bit; -}; - -struct EPWM_XBAR_REGS { - union TRIP4MUX0TO15CFG_REG TRIP4MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP4 - union TRIP4MUX16TO31CFG_REG TRIP4MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP4 - union TRIP5MUX0TO15CFG_REG TRIP5MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP5 - union TRIP5MUX16TO31CFG_REG TRIP5MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP5 - union TRIP7MUX0TO15CFG_REG TRIP7MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP7 - union TRIP7MUX16TO31CFG_REG TRIP7MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP7 - union TRIP8MUX0TO15CFG_REG TRIP8MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP8 - union TRIP8MUX16TO31CFG_REG TRIP8MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP8 - union TRIP9MUX0TO15CFG_REG TRIP9MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP9 - union TRIP9MUX16TO31CFG_REG TRIP9MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP9 - union TRIP10MUX0TO15CFG_REG TRIP10MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP10 - union TRIP10MUX16TO31CFG_REG TRIP10MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP10 - union TRIP11MUX0TO15CFG_REG TRIP11MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP11 - union TRIP11MUX16TO31CFG_REG TRIP11MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP11 - union TRIP12MUX0TO15CFG_REG TRIP12MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP12 - union TRIP12MUX16TO31CFG_REG TRIP12MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP12 - union TRIP4MUXENABLE_REG TRIP4MUXENABLE; // ePWM XBAR Mux Enable for TRIP4 - union TRIP5MUXENABLE_REG TRIP5MUXENABLE; // ePWM XBAR Mux Enable for TRIP5 - union TRIP7MUXENABLE_REG TRIP7MUXENABLE; // ePWM XBAR Mux Enable for TRIP7 - union TRIP8MUXENABLE_REG TRIP8MUXENABLE; // ePWM XBAR Mux Enable for TRIP8 - union TRIP9MUXENABLE_REG TRIP9MUXENABLE; // ePWM XBAR Mux Enable for TRIP9 - union TRIP10MUXENABLE_REG TRIP10MUXENABLE; // ePWM XBAR Mux Enable for TRIP10 - union TRIP11MUXENABLE_REG TRIP11MUXENABLE; // ePWM XBAR Mux Enable for TRIP11 - union TRIP12MUXENABLE_REG TRIP12MUXENABLE; // ePWM XBAR Mux Enable for TRIP12 - Uint16 rsvd1[8]; // Reserved - union TRIPOUTINV_REG TRIPOUTINV; // ePWM XBAR Output Inversion Register - Uint16 rsvd2[4]; // Reserved - union TRIPLOCK_REG TRIPLOCK; // ePWM XBAR Configuration Lock register -}; - -//--------------------------------------------------------------------------- -// EPWM_XBAR External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct EPWM_XBAR_REGS EPwmXbarRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_eqep.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_eqep.h deleted file mode 100644 index f37da095a9..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_eqep.h +++ /dev/null @@ -1,267 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_eqep.h -// -// TITLE: EQEP Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_EQEP_H__ -#define __F2837xD_EQEP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// EQEP Individual Register Bit Definitions: - -struct QDECCTL_BITS { // bits description - Uint16 rsvd1:5; // 4:0 Reserved - Uint16 QSP:1; // 5 QEPS input polarity - Uint16 QIP:1; // 6 QEPI input polarity - Uint16 QBP:1; // 7 QEPB input polarity - Uint16 QAP:1; // 8 QEPA input polarity - Uint16 IGATE:1; // 9 Index pulse gating option - Uint16 SWAP:1; // 10 CLK/DIR Signal Source for Position Counter - Uint16 XCR:1; // 11 External Clock Rate - Uint16 SPSEL:1; // 12 Sync output pin selection - Uint16 SOEN:1; // 13 Sync output-enable - Uint16 QSRC:2; // 15:14 Position-counter source selection -}; - -union QDECCTL_REG { - Uint16 all; - struct QDECCTL_BITS bit; -}; - -struct QEPCTL_BITS { // bits description - Uint16 WDE:1; // 0 QEP watchdog enable - Uint16 UTE:1; // 1 QEP unit timer enable - Uint16 QCLM:1; // 2 QEP capture latch mode - Uint16 QPEN:1; // 3 Quadrature postotion counter enable - Uint16 IEL:2; // 5:4 Index event latch - Uint16 SEL:1; // 6 Strobe event latch - Uint16 SWI:1; // 7 Software init position counter - Uint16 IEI:2; // 9:8 Index event init of position count - Uint16 SEI:2; // 11:10 Strobe event init - Uint16 PCRM:2; // 13:12 Postion counter reset - Uint16 FREE_SOFT:2; // 15:14 Emulation mode -}; - -union QEPCTL_REG { - Uint16 all; - struct QEPCTL_BITS bit; -}; - -struct QCAPCTL_BITS { // bits description - Uint16 UPPS:4; // 3:0 Unit position event prescaler - Uint16 CCPS:3; // 6:4 eQEP capture timer clock prescaler - Uint16 rsvd1:8; // 14:7 Reserved - Uint16 CEN:1; // 15 Enable eQEP capture -}; - -union QCAPCTL_REG { - Uint16 all; - struct QCAPCTL_BITS bit; -}; - -struct QPOSCTL_BITS { // bits description - Uint16 PCSPW:12; // 11:0 Position compare sync pulse width - Uint16 PCE:1; // 12 Position compare enable/disable - Uint16 PCPOL:1; // 13 Polarity of sync output - Uint16 PCLOAD:1; // 14 Position compare of shadow load - Uint16 PCSHDW:1; // 15 Position compare of shadow enable -}; - -union QPOSCTL_REG { - Uint16 all; - struct QPOSCTL_BITS bit; -}; - -struct QEINT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 PCE:1; // 1 Position counter error interrupt enable - Uint16 QPE:1; // 2 Quadrature phase error interrupt enable - Uint16 QDC:1; // 3 Quadrature direction change interrupt enable - Uint16 WTO:1; // 4 Watchdog time out interrupt enable - Uint16 PCU:1; // 5 Position counter underflow interrupt enable - Uint16 PCO:1; // 6 Position counter overflow interrupt enable - Uint16 PCR:1; // 7 Position-compare ready interrupt enable - Uint16 PCM:1; // 8 Position-compare match interrupt enable - Uint16 SEL:1; // 9 Strobe event latch interrupt enable - Uint16 IEL:1; // 10 Index event latch interrupt enable - Uint16 UTO:1; // 11 Unit time out interrupt enable - Uint16 rsvd2:4; // 15:12 Reserved -}; - -union QEINT_REG { - Uint16 all; - struct QEINT_BITS bit; -}; - -struct QFLG_BITS { // bits description - Uint16 INT:1; // 0 Global interrupt status flag - Uint16 PCE:1; // 1 Position counter error interrupt flag - Uint16 PHE:1; // 2 Quadrature phase error interrupt flag - Uint16 QDC:1; // 3 Quadrature direction change interrupt flag - Uint16 WTO:1; // 4 Watchdog timeout interrupt flag - Uint16 PCU:1; // 5 Position counter underflow interrupt flag - Uint16 PCO:1; // 6 Position counter overflow interrupt flag - Uint16 PCR:1; // 7 Position-compare ready interrupt flag - Uint16 PCM:1; // 8 eQEP compare match event interrupt flag - Uint16 SEL:1; // 9 Strobe event latch interrupt flag - Uint16 IEL:1; // 10 Index event latch interrupt flag - Uint16 UTO:1; // 11 Unit time out interrupt flag - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union QFLG_REG { - Uint16 all; - struct QFLG_BITS bit; -}; - -struct QCLR_BITS { // bits description - Uint16 INT:1; // 0 Global interrupt clear flag - Uint16 PCE:1; // 1 Clear position counter error interrupt flag - Uint16 PHE:1; // 2 Clear quadrature phase error interrupt flag - Uint16 QDC:1; // 3 Clear quadrature direction change interrupt flag - Uint16 WTO:1; // 4 Clear watchdog timeout interrupt flag - Uint16 PCU:1; // 5 Clear position counter underflow interrupt flag - Uint16 PCO:1; // 6 Clear position counter overflow interrupt flag - Uint16 PCR:1; // 7 Clear position-compare ready interrupt flag - Uint16 PCM:1; // 8 Clear eQEP compare match event interrupt flag - Uint16 SEL:1; // 9 Clear strobe event latch interrupt flag - Uint16 IEL:1; // 10 Clear index event latch interrupt flag - Uint16 UTO:1; // 11 Clear unit time out interrupt flag - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union QCLR_REG { - Uint16 all; - struct QCLR_BITS bit; -}; - -struct QFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 PCE:1; // 1 Force position counter error interrupt - Uint16 PHE:1; // 2 Force quadrature phase error interrupt - Uint16 QDC:1; // 3 Force quadrature direction change interrupt - Uint16 WTO:1; // 4 Force watchdog time out interrupt - Uint16 PCU:1; // 5 Force position counter underflow interrupt - Uint16 PCO:1; // 6 Force position counter overflow interrupt - Uint16 PCR:1; // 7 Force position-compare ready interrupt - Uint16 PCM:1; // 8 Force position-compare match interrupt - Uint16 SEL:1; // 9 Force strobe event latch interrupt - Uint16 IEL:1; // 10 Force index event latch interrupt - Uint16 UTO:1; // 11 Force unit time out interrupt - Uint16 rsvd2:4; // 15:12 Reserved -}; - -union QFRC_REG { - Uint16 all; - struct QFRC_BITS bit; -}; - -struct QEPSTS_BITS { // bits description - Uint16 PCEF:1; // 0 Position counter error flag. - Uint16 FIMF:1; // 1 First index marker flag - Uint16 CDEF:1; // 2 Capture direction error flag - Uint16 COEF:1; // 3 Capture overflow error flag - Uint16 QDLF:1; // 4 eQEP direction latch flag - Uint16 QDF:1; // 5 Quadrature direction flag - Uint16 FIDF:1; // 6 The first index marker - Uint16 UPEVNT:1; // 7 Unit position event flag - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union QEPSTS_REG { - Uint16 all; - struct QEPSTS_BITS bit; -}; - -struct EQEP_REGS { - Uint32 QPOSCNT; // Position Counter - Uint32 QPOSINIT; // Position Counter Init - Uint32 QPOSMAX; // Maximum Position Count - Uint32 QPOSCMP; // Position Compare - Uint32 QPOSILAT; // Index Position Latch - Uint32 QPOSSLAT; // Strobe Position Latch - Uint32 QPOSLAT; // Position Latch - Uint32 QUTMR; // QEP Unit Timer - Uint32 QUPRD; // QEP Unit Period - Uint16 QWDTMR; // QEP Watchdog Timer - Uint16 QWDPRD; // QEP Watchdog Period - union QDECCTL_REG QDECCTL; // Quadrature Decoder Control - union QEPCTL_REG QEPCTL; // QEP Control - union QCAPCTL_REG QCAPCTL; // Qaudrature Capture Control - union QPOSCTL_REG QPOSCTL; // Position Compare Control - union QEINT_REG QEINT; // QEP Interrupt Control - union QFLG_REG QFLG; // QEP Interrupt Flag - union QCLR_REG QCLR; // QEP Interrupt Clear - union QFRC_REG QFRC; // QEP Interrupt Force - union QEPSTS_REG QEPSTS; // QEP Status - Uint16 QCTMR; // QEP Capture Timer - Uint16 QCPRD; // QEP Capture Period - Uint16 QCTMRLAT; // QEP Capture Latch - Uint16 QCPRDLAT; // QEP Capture Period Latch - Uint16 rsvd1; // Reserved -}; - -//--------------------------------------------------------------------------- -// EQEP External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct EQEP_REGS EQep1Regs; -extern volatile struct EQEP_REGS EQep2Regs; -extern volatile struct EQEP_REGS EQep3Regs; -#endif -#ifdef CPU2 -extern volatile struct EQEP_REGS EQep1Regs; -extern volatile struct EQEP_REGS EQep2Regs; -extern volatile struct EQEP_REGS EQep3Regs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_flash.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_flash.h deleted file mode 100644 index 2882c6a96d..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_flash.h +++ /dev/null @@ -1,376 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_flash.h -// -// TITLE: FLASH Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_FLASH_H__ -#define __F2837xD_FLASH_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// FLASH Individual Register Bit Definitions: - -struct FRDCNTL_BITS { // bits description - Uint16 rsvd1:8; // 7:0 Reserved - Uint16 RWAIT:4; // 11:8 Random Read Waitstate - Uint16 rsvd2:4; // 15:12 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union FRDCNTL_REG { - Uint32 all; - struct FRDCNTL_BITS bit; -}; - -struct FBAC_BITS { // bits description - Uint16 VREADST:8; // 7:0 VREAD Setup Time Count - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FBAC_REG { - Uint32 all; - struct FBAC_BITS bit; -}; - -struct FBFALLBACK_BITS { // bits description - Uint16 BNKPWR0:2; // 1:0 Bank Power Mode - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FBFALLBACK_REG { - Uint32 all; - struct FBFALLBACK_BITS bit; -}; - -struct FBPRDY_BITS { // bits description - Uint16 BANKRDY:1; // 0 Flash Bank Active Power State - Uint16 rsvd1:14; // 14:1 Reserved - Uint16 PUMPRDY:1; // 15 Flash Pump Active Power Mode - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FBPRDY_REG { - Uint32 all; - struct FBPRDY_BITS bit; -}; - -struct FPAC1_BITS { // bits description - Uint16 PMPPWR:1; // 0 Charge Pump Fallback Power Mode - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 PSLEEP:12; // 27:16 Pump Sleep Down Count - Uint16 rsvd2:4; // 31:28 Reserved -}; - -union FPAC1_REG { - Uint32 all; - struct FPAC1_BITS bit; -}; - -struct FMSTAT_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 VOLTSTAT:1; // 3 Flash Pump Power Status - Uint16 CSTAT:1; // 4 Command Fail Status - Uint16 INVDAT:1; // 5 Invalid Data - Uint16 PGM:1; // 6 Program Operation Status - Uint16 ERS:1; // 7 Erase Operation Status - Uint16 BUSY:1; // 8 Busy Bit - Uint16 rsvd4:1; // 9 Reserved - Uint16 EV:1; // 10 Erase Verify Status - Uint16 rsvd5:1; // 11 Reserved - Uint16 PGV:1; // 12 Programming Verify Status - Uint16 rsvd6:1; // 13 Reserved - Uint16 rsvd7:1; // 14 Reserved - Uint16 rsvd8:1; // 15 Reserved - Uint16 rsvd9:1; // 16 Reserved - Uint16 rsvd10:1; // 17 Reserved - Uint16 rsvd11:14; // 31:18 Reserved -}; - -union FMSTAT_REG { - Uint32 all; - struct FMSTAT_BITS bit; -}; - -struct FRD_INTF_CTRL_BITS { // bits description - Uint16 PREFETCH_EN:1; // 0 Prefetch Enable - Uint16 DATA_CACHE_EN:1; // 1 Data Cache Enable - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FRD_INTF_CTRL_REG { - Uint32 all; - struct FRD_INTF_CTRL_BITS bit; -}; - -struct FLASH_CTRL_REGS { - union FRDCNTL_REG FRDCNTL; // Flash Read Control Register - Uint16 rsvd1[28]; // Reserved - union FBAC_REG FBAC; // Flash Bank Access Control Register - union FBFALLBACK_REG FBFALLBACK; // Flash Bank Fallback Power Register - union FBPRDY_REG FBPRDY; // Flash Bank Pump Ready Register - union FPAC1_REG FPAC1; // Flash Pump Access Control Register 1 - Uint16 rsvd2[4]; // Reserved - union FMSTAT_REG FMSTAT; // Flash Module Status Register - Uint16 rsvd3[340]; // Reserved - union FRD_INTF_CTRL_REG FRD_INTF_CTRL; // Flash Read Interface Control Register -}; - -struct ECC_ENABLE_BITS { // bits description - Uint16 ENABLE:4; // 3:0 Enable ECC - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ECC_ENABLE_REG { - Uint32 all; - struct ECC_ENABLE_BITS bit; -}; - -struct ERR_STATUS_BITS { // bits description - Uint16 FAIL_0_L:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 - Uint16 FAIL_1_L:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 - Uint16 UNC_ERR_L:1; // 2 Lower 64 bits Uncorrectable error occurred - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 FAIL_0_H:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 - Uint16 FAIL_1_H:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 - Uint16 UNC_ERR_H:1; // 18 Upper 64 bits Uncorrectable error occurred - Uint16 rsvd2:13; // 31:19 Reserved -}; - -union ERR_STATUS_REG { - Uint32 all; - struct ERR_STATUS_BITS bit; -}; - -struct ERR_POS_BITS { // bits description - Uint16 ERR_POS_L:6; // 5:0 Bit Position of Single bit Error in lower 64 bits - Uint16 rsvd1:2; // 7:6 Reserved - Uint16 ERR_TYPE_L:1; // 8 Error Type in lower 64 bits - Uint16 rsvd2:7; // 15:9 Reserved - Uint16 ERR_POS_H:6; // 21:16 Bit Position of Single bit Error in upper 64 bits - Uint16 rsvd3:2; // 23:22 Reserved - Uint16 ERR_TYPE_H:1; // 24 Error Type in upper 64 bits - Uint16 rsvd4:7; // 31:25 Reserved -}; - -union ERR_POS_REG { - Uint32 all; - struct ERR_POS_BITS bit; -}; - -struct ERR_STATUS_CLR_BITS { // bits description - Uint16 FAIL_0_L_CLR:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 Clear - Uint16 FAIL_1_L_CLR:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 Clear - Uint16 UNC_ERR_L_CLR:1; // 2 Lower 64 bits Uncorrectable error occurred Clear - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 FAIL_0_H_CLR:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 Clear - Uint16 FAIL_1_H_CLR:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 Clear - Uint16 UNC_ERR_H_CLR:1; // 18 Upper 64 bits Uncorrectable error occurred Clear - Uint16 rsvd2:13; // 31:19 Reserved -}; - -union ERR_STATUS_CLR_REG { - Uint32 all; - struct ERR_STATUS_CLR_BITS bit; -}; - -struct ERR_CNT_BITS { // bits description - Uint16 ERR_CNT:16; // 15:0 Error counter - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union ERR_CNT_REG { - Uint32 all; - struct ERR_CNT_BITS bit; -}; - -struct ERR_THRESHOLD_BITS { // bits description - Uint16 ERR_THRESHOLD:16; // 15:0 Error Threshold - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union ERR_THRESHOLD_REG { - Uint32 all; - struct ERR_THRESHOLD_BITS bit; -}; - -struct ERR_INTFLG_BITS { // bits description - Uint16 SINGLE_ERR_INTFLG:1; // 0 Single Error Interrupt Flag - Uint16 UNC_ERR_INTFLG:1; // 1 Uncorrectable Interrupt Flag - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ERR_INTFLG_REG { - Uint32 all; - struct ERR_INTFLG_BITS bit; -}; - -struct ERR_INTCLR_BITS { // bits description - Uint16 SINGLE_ERR_INTCLR:1; // 0 Single Error Interrupt Flag Clear - Uint16 UNC_ERR_INTCLR:1; // 1 Uncorrectable Interrupt Flag Clear - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ERR_INTCLR_REG { - Uint32 all; - struct ERR_INTCLR_BITS bit; -}; - -struct FADDR_TEST_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 ADDRL:13; // 15:3 ECC Address Low - Uint16 ADDRH:6; // 21:16 ECC Address High - Uint16 rsvd2:10; // 31:22 Reserved -}; - -union FADDR_TEST_REG { - Uint32 all; - struct FADDR_TEST_BITS bit; -}; - -struct FECC_TEST_BITS { // bits description - Uint16 ECC:8; // 7:0 ECC Control Bits - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FECC_TEST_REG { - Uint32 all; - struct FECC_TEST_BITS bit; -}; - -struct FECC_CTRL_BITS { // bits description - Uint16 ECC_TEST_EN:1; // 0 Enable ECC Test Logic - Uint16 ECC_SELECT:1; // 1 ECC Bit Select - Uint16 DO_ECC_CALC:1; // 2 Enable ECC Calculation - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FECC_CTRL_REG { - Uint32 all; - struct FECC_CTRL_BITS bit; -}; - -struct FECC_STATUS_BITS { // bits description - Uint16 SINGLE_ERR:1; // 0 Test Result is Single Bit Error - Uint16 UNC_ERR:1; // 1 Test Result is Uncorrectable Error - Uint16 DATA_ERR_POS:6; // 7:2 Holds Bit Position of Error - Uint16 ERR_TYPE:1; // 8 Holds Bit Position of 8 Check Bits of Error - Uint16 rsvd1:7; // 15:9 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FECC_STATUS_REG { - Uint32 all; - struct FECC_STATUS_BITS bit; -}; - -struct FLASH_ECC_REGS { - union ECC_ENABLE_REG ECC_ENABLE; // ECC Enable - Uint32 SINGLE_ERR_ADDR_LOW; // Single Error Address Low - Uint32 SINGLE_ERR_ADDR_HIGH; // Single Error Address High - Uint32 UNC_ERR_ADDR_LOW; // Uncorrectable Error Address Low - Uint32 UNC_ERR_ADDR_HIGH; // Uncorrectable Error Address High - union ERR_STATUS_REG ERR_STATUS; // Error Status - union ERR_POS_REG ERR_POS; // Error Position - union ERR_STATUS_CLR_REG ERR_STATUS_CLR; // Error Status Clear - union ERR_CNT_REG ERR_CNT; // Error Control - union ERR_THRESHOLD_REG ERR_THRESHOLD; // Error Threshold - union ERR_INTFLG_REG ERR_INTFLG; // Error Interrupt Flag - union ERR_INTCLR_REG ERR_INTCLR; // Error Interrupt Flag Clear - Uint32 FDATAH_TEST; // Data High Test - Uint32 FDATAL_TEST; // Data Low Test - union FADDR_TEST_REG FADDR_TEST; // ECC Test Address - union FECC_TEST_REG FECC_TEST; // ECC Test Address - union FECC_CTRL_REG FECC_CTRL; // ECC Control - Uint32 FOUTH_TEST; // Test Data Out High - Uint32 FOUTL_TEST; // Test Data Out Low - union FECC_STATUS_REG FECC_STATUS; // ECC Status -}; - -struct PUMPREQUEST_BITS { // bits description - Uint16 PUMP_OWNERSHIP:2; // 1:0 Flash Pump Request Semaphore between CPU1 and CPU2 - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register -}; - -union PUMPREQUEST_REG { - Uint32 all; - struct PUMPREQUEST_BITS bit; -}; - -struct FLASH_PUMP_SEMAPHORE_REGS { - union PUMPREQUEST_REG PUMPREQUEST; // Flash programming semaphore PUMP request register -}; - -//--------------------------------------------------------------------------- -// FLASH External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; -extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; -extern volatile struct FLASH_ECC_REGS Flash0EccRegs; -#endif -#ifdef CPU2 -extern volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; -extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; -extern volatile struct FLASH_ECC_REGS Flash0EccRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_gpio.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_gpio.h deleted file mode 100644 index 7aeb219836..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_gpio.h +++ /dev/null @@ -1,3882 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_gpio.h -// -// TITLE: GPIO Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_GPIO_H__ -#define __F2837xD_GPIO_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// GPIO Individual Register Bit Definitions: - -struct GPACTRL_BITS { // bits description - Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO0 to GPIO7 - Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO8 to GPIO15 - Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO16 to GPIO23 - Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO24 to GPIO31 -}; - -union GPACTRL_REG { - Uint32 all; - struct GPACTRL_BITS bit; -}; - -struct GPAQSEL1_BITS { // bits description - Uint16 GPIO0:2; // 1:0 Select input qualification type for GPIO0 - Uint16 GPIO1:2; // 3:2 Select input qualification type for GPIO1 - Uint16 GPIO2:2; // 5:4 Select input qualification type for GPIO2 - Uint16 GPIO3:2; // 7:6 Select input qualification type for GPIO3 - Uint16 GPIO4:2; // 9:8 Select input qualification type for GPIO4 - Uint16 GPIO5:2; // 11:10 Select input qualification type for GPIO5 - Uint16 GPIO6:2; // 13:12 Select input qualification type for GPIO6 - Uint16 GPIO7:2; // 15:14 Select input qualification type for GPIO7 - Uint16 GPIO8:2; // 17:16 Select input qualification type for GPIO8 - Uint16 GPIO9:2; // 19:18 Select input qualification type for GPIO9 - Uint16 GPIO10:2; // 21:20 Select input qualification type for GPIO10 - Uint16 GPIO11:2; // 23:22 Select input qualification type for GPIO11 - Uint16 GPIO12:2; // 25:24 Select input qualification type for GPIO12 - Uint16 GPIO13:2; // 27:26 Select input qualification type for GPIO13 - Uint16 GPIO14:2; // 29:28 Select input qualification type for GPIO14 - Uint16 GPIO15:2; // 31:30 Select input qualification type for GPIO15 -}; - -union GPAQSEL1_REG { - Uint32 all; - struct GPAQSEL1_BITS bit; -}; - -struct GPAQSEL2_BITS { // bits description - Uint16 GPIO16:2; // 1:0 Select input qualification type for GPIO16 - Uint16 GPIO17:2; // 3:2 Select input qualification type for GPIO17 - Uint16 GPIO18:2; // 5:4 Select input qualification type for GPIO18 - Uint16 GPIO19:2; // 7:6 Select input qualification type for GPIO19 - Uint16 GPIO20:2; // 9:8 Select input qualification type for GPIO20 - Uint16 GPIO21:2; // 11:10 Select input qualification type for GPIO21 - Uint16 GPIO22:2; // 13:12 Select input qualification type for GPIO22 - Uint16 GPIO23:2; // 15:14 Select input qualification type for GPIO23 - Uint16 GPIO24:2; // 17:16 Select input qualification type for GPIO24 - Uint16 GPIO25:2; // 19:18 Select input qualification type for GPIO25 - Uint16 GPIO26:2; // 21:20 Select input qualification type for GPIO26 - Uint16 GPIO27:2; // 23:22 Select input qualification type for GPIO27 - Uint16 GPIO28:2; // 25:24 Select input qualification type for GPIO28 - Uint16 GPIO29:2; // 27:26 Select input qualification type for GPIO29 - Uint16 GPIO30:2; // 29:28 Select input qualification type for GPIO30 - Uint16 GPIO31:2; // 31:30 Select input qualification type for GPIO31 -}; - -union GPAQSEL2_REG { - Uint32 all; - struct GPAQSEL2_BITS bit; -}; - -struct GPAMUX1_BITS { // bits description - Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 - Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 - Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 - Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 - Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 - Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 - Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 - Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 - Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 - Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 - Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 - Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 - Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 - Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 - Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 - Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 -}; - -union GPAMUX1_REG { - Uint32 all; - struct GPAMUX1_BITS bit; -}; - -struct GPAMUX2_BITS { // bits description - Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 - Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 - Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 - Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 - Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 - Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 - Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 - Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 - Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 - Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 - Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 - Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 - Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 - Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 - Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 - Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 -}; - -union GPAMUX2_REG { - Uint32 all; - struct GPAMUX2_BITS bit; -}; - -struct GPADIR_BITS { // bits description - Uint16 GPIO0:1; // 0 Defines direction for this pin in GPIO mode - Uint16 GPIO1:1; // 1 Defines direction for this pin in GPIO mode - Uint16 GPIO2:1; // 2 Defines direction for this pin in GPIO mode - Uint16 GPIO3:1; // 3 Defines direction for this pin in GPIO mode - Uint16 GPIO4:1; // 4 Defines direction for this pin in GPIO mode - Uint16 GPIO5:1; // 5 Defines direction for this pin in GPIO mode - Uint16 GPIO6:1; // 6 Defines direction for this pin in GPIO mode - Uint16 GPIO7:1; // 7 Defines direction for this pin in GPIO mode - Uint16 GPIO8:1; // 8 Defines direction for this pin in GPIO mode - Uint16 GPIO9:1; // 9 Defines direction for this pin in GPIO mode - Uint16 GPIO10:1; // 10 Defines direction for this pin in GPIO mode - Uint16 GPIO11:1; // 11 Defines direction for this pin in GPIO mode - Uint16 GPIO12:1; // 12 Defines direction for this pin in GPIO mode - Uint16 GPIO13:1; // 13 Defines direction for this pin in GPIO mode - Uint16 GPIO14:1; // 14 Defines direction for this pin in GPIO mode - Uint16 GPIO15:1; // 15 Defines direction for this pin in GPIO mode - Uint16 GPIO16:1; // 16 Defines direction for this pin in GPIO mode - Uint16 GPIO17:1; // 17 Defines direction for this pin in GPIO mode - Uint16 GPIO18:1; // 18 Defines direction for this pin in GPIO mode - Uint16 GPIO19:1; // 19 Defines direction for this pin in GPIO mode - Uint16 GPIO20:1; // 20 Defines direction for this pin in GPIO mode - Uint16 GPIO21:1; // 21 Defines direction for this pin in GPIO mode - Uint16 GPIO22:1; // 22 Defines direction for this pin in GPIO mode - Uint16 GPIO23:1; // 23 Defines direction for this pin in GPIO mode - Uint16 GPIO24:1; // 24 Defines direction for this pin in GPIO mode - Uint16 GPIO25:1; // 25 Defines direction for this pin in GPIO mode - Uint16 GPIO26:1; // 26 Defines direction for this pin in GPIO mode - Uint16 GPIO27:1; // 27 Defines direction for this pin in GPIO mode - Uint16 GPIO28:1; // 28 Defines direction for this pin in GPIO mode - Uint16 GPIO29:1; // 29 Defines direction for this pin in GPIO mode - Uint16 GPIO30:1; // 30 Defines direction for this pin in GPIO mode - Uint16 GPIO31:1; // 31 Defines direction for this pin in GPIO mode -}; - -union GPADIR_REG { - Uint32 all; - struct GPADIR_BITS bit; -}; - -struct GPAPUD_BITS { // bits description - Uint16 GPIO0:1; // 0 Pull-Up Disable control for this pin - Uint16 GPIO1:1; // 1 Pull-Up Disable control for this pin - Uint16 GPIO2:1; // 2 Pull-Up Disable control for this pin - Uint16 GPIO3:1; // 3 Pull-Up Disable control for this pin - Uint16 GPIO4:1; // 4 Pull-Up Disable control for this pin - Uint16 GPIO5:1; // 5 Pull-Up Disable control for this pin - Uint16 GPIO6:1; // 6 Pull-Up Disable control for this pin - Uint16 GPIO7:1; // 7 Pull-Up Disable control for this pin - Uint16 GPIO8:1; // 8 Pull-Up Disable control for this pin - Uint16 GPIO9:1; // 9 Pull-Up Disable control for this pin - Uint16 GPIO10:1; // 10 Pull-Up Disable control for this pin - Uint16 GPIO11:1; // 11 Pull-Up Disable control for this pin - Uint16 GPIO12:1; // 12 Pull-Up Disable control for this pin - Uint16 GPIO13:1; // 13 Pull-Up Disable control for this pin - Uint16 GPIO14:1; // 14 Pull-Up Disable control for this pin - Uint16 GPIO15:1; // 15 Pull-Up Disable control for this pin - Uint16 GPIO16:1; // 16 Pull-Up Disable control for this pin - Uint16 GPIO17:1; // 17 Pull-Up Disable control for this pin - Uint16 GPIO18:1; // 18 Pull-Up Disable control for this pin - Uint16 GPIO19:1; // 19 Pull-Up Disable control for this pin - Uint16 GPIO20:1; // 20 Pull-Up Disable control for this pin - Uint16 GPIO21:1; // 21 Pull-Up Disable control for this pin - Uint16 GPIO22:1; // 22 Pull-Up Disable control for this pin - Uint16 GPIO23:1; // 23 Pull-Up Disable control for this pin - Uint16 GPIO24:1; // 24 Pull-Up Disable control for this pin - Uint16 GPIO25:1; // 25 Pull-Up Disable control for this pin - Uint16 GPIO26:1; // 26 Pull-Up Disable control for this pin - Uint16 GPIO27:1; // 27 Pull-Up Disable control for this pin - Uint16 GPIO28:1; // 28 Pull-Up Disable control for this pin - Uint16 GPIO29:1; // 29 Pull-Up Disable control for this pin - Uint16 GPIO30:1; // 30 Pull-Up Disable control for this pin - Uint16 GPIO31:1; // 31 Pull-Up Disable control for this pin -}; - -union GPAPUD_REG { - Uint32 all; - struct GPAPUD_BITS bit; -}; - -struct GPAINV_BITS { // bits description - Uint16 GPIO0:1; // 0 Input inversion control for this pin - Uint16 GPIO1:1; // 1 Input inversion control for this pin - Uint16 GPIO2:1; // 2 Input inversion control for this pin - Uint16 GPIO3:1; // 3 Input inversion control for this pin - Uint16 GPIO4:1; // 4 Input inversion control for this pin - Uint16 GPIO5:1; // 5 Input inversion control for this pin - Uint16 GPIO6:1; // 6 Input inversion control for this pin - Uint16 GPIO7:1; // 7 Input inversion control for this pin - Uint16 GPIO8:1; // 8 Input inversion control for this pin - Uint16 GPIO9:1; // 9 Input inversion control for this pin - Uint16 GPIO10:1; // 10 Input inversion control for this pin - Uint16 GPIO11:1; // 11 Input inversion control for this pin - Uint16 GPIO12:1; // 12 Input inversion control for this pin - Uint16 GPIO13:1; // 13 Input inversion control for this pin - Uint16 GPIO14:1; // 14 Input inversion control for this pin - Uint16 GPIO15:1; // 15 Input inversion control for this pin - Uint16 GPIO16:1; // 16 Input inversion control for this pin - Uint16 GPIO17:1; // 17 Input inversion control for this pin - Uint16 GPIO18:1; // 18 Input inversion control for this pin - Uint16 GPIO19:1; // 19 Input inversion control for this pin - Uint16 GPIO20:1; // 20 Input inversion control for this pin - Uint16 GPIO21:1; // 21 Input inversion control for this pin - Uint16 GPIO22:1; // 22 Input inversion control for this pin - Uint16 GPIO23:1; // 23 Input inversion control for this pin - Uint16 GPIO24:1; // 24 Input inversion control for this pin - Uint16 GPIO25:1; // 25 Input inversion control for this pin - Uint16 GPIO26:1; // 26 Input inversion control for this pin - Uint16 GPIO27:1; // 27 Input inversion control for this pin - Uint16 GPIO28:1; // 28 Input inversion control for this pin - Uint16 GPIO29:1; // 29 Input inversion control for this pin - Uint16 GPIO30:1; // 30 Input inversion control for this pin - Uint16 GPIO31:1; // 31 Input inversion control for this pin -}; - -union GPAINV_REG { - Uint32 all; - struct GPAINV_BITS bit; -}; - -struct GPAODR_BITS { // bits description - Uint16 GPIO0:1; // 0 Outpout Open-Drain control for this pin - Uint16 GPIO1:1; // 1 Outpout Open-Drain control for this pin - Uint16 GPIO2:1; // 2 Outpout Open-Drain control for this pin - Uint16 GPIO3:1; // 3 Outpout Open-Drain control for this pin - Uint16 GPIO4:1; // 4 Outpout Open-Drain control for this pin - Uint16 GPIO5:1; // 5 Outpout Open-Drain control for this pin - Uint16 GPIO6:1; // 6 Outpout Open-Drain control for this pin - Uint16 GPIO7:1; // 7 Outpout Open-Drain control for this pin - Uint16 GPIO8:1; // 8 Outpout Open-Drain control for this pin - Uint16 GPIO9:1; // 9 Outpout Open-Drain control for this pin - Uint16 GPIO10:1; // 10 Outpout Open-Drain control for this pin - Uint16 GPIO11:1; // 11 Outpout Open-Drain control for this pin - Uint16 GPIO12:1; // 12 Outpout Open-Drain control for this pin - Uint16 GPIO13:1; // 13 Outpout Open-Drain control for this pin - Uint16 GPIO14:1; // 14 Outpout Open-Drain control for this pin - Uint16 GPIO15:1; // 15 Outpout Open-Drain control for this pin - Uint16 GPIO16:1; // 16 Outpout Open-Drain control for this pin - Uint16 GPIO17:1; // 17 Outpout Open-Drain control for this pin - Uint16 GPIO18:1; // 18 Outpout Open-Drain control for this pin - Uint16 GPIO19:1; // 19 Outpout Open-Drain control for this pin - Uint16 GPIO20:1; // 20 Outpout Open-Drain control for this pin - Uint16 GPIO21:1; // 21 Outpout Open-Drain control for this pin - Uint16 GPIO22:1; // 22 Outpout Open-Drain control for this pin - Uint16 GPIO23:1; // 23 Outpout Open-Drain control for this pin - Uint16 GPIO24:1; // 24 Outpout Open-Drain control for this pin - Uint16 GPIO25:1; // 25 Outpout Open-Drain control for this pin - Uint16 GPIO26:1; // 26 Outpout Open-Drain control for this pin - Uint16 GPIO27:1; // 27 Outpout Open-Drain control for this pin - Uint16 GPIO28:1; // 28 Outpout Open-Drain control for this pin - Uint16 GPIO29:1; // 29 Outpout Open-Drain control for this pin - Uint16 GPIO30:1; // 30 Outpout Open-Drain control for this pin - Uint16 GPIO31:1; // 31 Outpout Open-Drain control for this pin -}; - -union GPAODR_REG { - Uint32 all; - struct GPAODR_BITS bit; -}; - -struct GPAGMUX1_BITS { // bits description - Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 - Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 - Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 - Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 - Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 - Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 - Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 - Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 - Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 - Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 - Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 - Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 - Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 - Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 - Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 - Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 -}; - -union GPAGMUX1_REG { - Uint32 all; - struct GPAGMUX1_BITS bit; -}; - -struct GPAGMUX2_BITS { // bits description - Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 - Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 - Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 - Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 - Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 - Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 - Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 - Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 - Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 - Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 - Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 - Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 - Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 - Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 - Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 - Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 -}; - -union GPAGMUX2_REG { - Uint32 all; - struct GPAGMUX2_BITS bit; -}; - -struct GPACSEL1_BITS { // bits description - Uint16 GPIO0:4; // 3:0 GPIO0 Master CPU Select - Uint16 GPIO1:4; // 7:4 GPIO1 Master CPU Select - Uint16 GPIO2:4; // 11:8 GPIO2 Master CPU Select - Uint16 GPIO3:4; // 15:12 GPIO3 Master CPU Select - Uint16 GPIO4:4; // 19:16 GPIO4 Master CPU Select - Uint16 GPIO5:4; // 23:20 GPIO5 Master CPU Select - Uint16 GPIO6:4; // 27:24 GPIO6 Master CPU Select - Uint16 GPIO7:4; // 31:28 GPIO7 Master CPU Select -}; - -union GPACSEL1_REG { - Uint32 all; - struct GPACSEL1_BITS bit; -}; - -struct GPACSEL2_BITS { // bits description - Uint16 GPIO8:4; // 3:0 GPIO8 Master CPU Select - Uint16 GPIO9:4; // 7:4 GPIO9 Master CPU Select - Uint16 GPIO10:4; // 11:8 GPIO10 Master CPU Select - Uint16 GPIO11:4; // 15:12 GPIO11 Master CPU Select - Uint16 GPIO12:4; // 19:16 GPIO12 Master CPU Select - Uint16 GPIO13:4; // 23:20 GPIO13 Master CPU Select - Uint16 GPIO14:4; // 27:24 GPIO14 Master CPU Select - Uint16 GPIO15:4; // 31:28 GPIO15 Master CPU Select -}; - -union GPACSEL2_REG { - Uint32 all; - struct GPACSEL2_BITS bit; -}; - -struct GPACSEL3_BITS { // bits description - Uint16 GPIO16:4; // 3:0 GPIO16 Master CPU Select - Uint16 GPIO17:4; // 7:4 GPIO17 Master CPU Select - Uint16 GPIO18:4; // 11:8 GPIO18 Master CPU Select - Uint16 GPIO19:4; // 15:12 GPIO19 Master CPU Select - Uint16 GPIO20:4; // 19:16 GPIO20 Master CPU Select - Uint16 GPIO21:4; // 23:20 GPIO21 Master CPU Select - Uint16 GPIO22:4; // 27:24 GPIO22 Master CPU Select - Uint16 GPIO23:4; // 31:28 GPIO23 Master CPU Select -}; - -union GPACSEL3_REG { - Uint32 all; - struct GPACSEL3_BITS bit; -}; - -struct GPACSEL4_BITS { // bits description - Uint16 GPIO24:4; // 3:0 GPIO24 Master CPU Select - Uint16 GPIO25:4; // 7:4 GPIO25 Master CPU Select - Uint16 GPIO26:4; // 11:8 GPIO26 Master CPU Select - Uint16 GPIO27:4; // 15:12 GPIO27 Master CPU Select - Uint16 GPIO28:4; // 19:16 GPIO28 Master CPU Select - Uint16 GPIO29:4; // 23:20 GPIO29 Master CPU Select - Uint16 GPIO30:4; // 27:24 GPIO30 Master CPU Select - Uint16 GPIO31:4; // 31:28 GPIO31 Master CPU Select -}; - -union GPACSEL4_REG { - Uint32 all; - struct GPACSEL4_BITS bit; -}; - -struct GPALOCK_BITS { // bits description - Uint16 GPIO0:1; // 0 Configuration Lock bit for this pin - Uint16 GPIO1:1; // 1 Configuration Lock bit for this pin - Uint16 GPIO2:1; // 2 Configuration Lock bit for this pin - Uint16 GPIO3:1; // 3 Configuration Lock bit for this pin - Uint16 GPIO4:1; // 4 Configuration Lock bit for this pin - Uint16 GPIO5:1; // 5 Configuration Lock bit for this pin - Uint16 GPIO6:1; // 6 Configuration Lock bit for this pin - Uint16 GPIO7:1; // 7 Configuration Lock bit for this pin - Uint16 GPIO8:1; // 8 Configuration Lock bit for this pin - Uint16 GPIO9:1; // 9 Configuration Lock bit for this pin - Uint16 GPIO10:1; // 10 Configuration Lock bit for this pin - Uint16 GPIO11:1; // 11 Configuration Lock bit for this pin - Uint16 GPIO12:1; // 12 Configuration Lock bit for this pin - Uint16 GPIO13:1; // 13 Configuration Lock bit for this pin - Uint16 GPIO14:1; // 14 Configuration Lock bit for this pin - Uint16 GPIO15:1; // 15 Configuration Lock bit for this pin - Uint16 GPIO16:1; // 16 Configuration Lock bit for this pin - Uint16 GPIO17:1; // 17 Configuration Lock bit for this pin - Uint16 GPIO18:1; // 18 Configuration Lock bit for this pin - Uint16 GPIO19:1; // 19 Configuration Lock bit for this pin - Uint16 GPIO20:1; // 20 Configuration Lock bit for this pin - Uint16 GPIO21:1; // 21 Configuration Lock bit for this pin - Uint16 GPIO22:1; // 22 Configuration Lock bit for this pin - Uint16 GPIO23:1; // 23 Configuration Lock bit for this pin - Uint16 GPIO24:1; // 24 Configuration Lock bit for this pin - Uint16 GPIO25:1; // 25 Configuration Lock bit for this pin - Uint16 GPIO26:1; // 26 Configuration Lock bit for this pin - Uint16 GPIO27:1; // 27 Configuration Lock bit for this pin - Uint16 GPIO28:1; // 28 Configuration Lock bit for this pin - Uint16 GPIO29:1; // 29 Configuration Lock bit for this pin - Uint16 GPIO30:1; // 30 Configuration Lock bit for this pin - Uint16 GPIO31:1; // 31 Configuration Lock bit for this pin -}; - -union GPALOCK_REG { - Uint32 all; - struct GPALOCK_BITS bit; -}; - -struct GPACR_BITS { // bits description - Uint16 GPIO0:1; // 0 Configuration lock commit bit for this pin - Uint16 GPIO1:1; // 1 Configuration lock commit bit for this pin - Uint16 GPIO2:1; // 2 Configuration lock commit bit for this pin - Uint16 GPIO3:1; // 3 Configuration lock commit bit for this pin - Uint16 GPIO4:1; // 4 Configuration lock commit bit for this pin - Uint16 GPIO5:1; // 5 Configuration lock commit bit for this pin - Uint16 GPIO6:1; // 6 Configuration lock commit bit for this pin - Uint16 GPIO7:1; // 7 Configuration lock commit bit for this pin - Uint16 GPIO8:1; // 8 Configuration lock commit bit for this pin - Uint16 GPIO9:1; // 9 Configuration lock commit bit for this pin - Uint16 GPIO10:1; // 10 Configuration lock commit bit for this pin - Uint16 GPIO11:1; // 11 Configuration lock commit bit for this pin - Uint16 GPIO12:1; // 12 Configuration lock commit bit for this pin - Uint16 GPIO13:1; // 13 Configuration lock commit bit for this pin - Uint16 GPIO14:1; // 14 Configuration lock commit bit for this pin - Uint16 GPIO15:1; // 15 Configuration lock commit bit for this pin - Uint16 GPIO16:1; // 16 Configuration lock commit bit for this pin - Uint16 GPIO17:1; // 17 Configuration lock commit bit for this pin - Uint16 GPIO18:1; // 18 Configuration lock commit bit for this pin - Uint16 GPIO19:1; // 19 Configuration lock commit bit for this pin - Uint16 GPIO20:1; // 20 Configuration lock commit bit for this pin - Uint16 GPIO21:1; // 21 Configuration lock commit bit for this pin - Uint16 GPIO22:1; // 22 Configuration lock commit bit for this pin - Uint16 GPIO23:1; // 23 Configuration lock commit bit for this pin - Uint16 GPIO24:1; // 24 Configuration lock commit bit for this pin - Uint16 GPIO25:1; // 25 Configuration lock commit bit for this pin - Uint16 GPIO26:1; // 26 Configuration lock commit bit for this pin - Uint16 GPIO27:1; // 27 Configuration lock commit bit for this pin - Uint16 GPIO28:1; // 28 Configuration lock commit bit for this pin - Uint16 GPIO29:1; // 29 Configuration lock commit bit for this pin - Uint16 GPIO30:1; // 30 Configuration lock commit bit for this pin - Uint16 GPIO31:1; // 31 Configuration lock commit bit for this pin -}; - -union GPACR_REG { - Uint32 all; - struct GPACR_BITS bit; -}; - -struct GPBCTRL_BITS { // bits description - Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO32 to GPIO39 - Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO40 to GPIO47 - Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO48 to GPIO55 - Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO56 to GPIO63 -}; - -union GPBCTRL_REG { - Uint32 all; - struct GPBCTRL_BITS bit; -}; - -struct GPBQSEL1_BITS { // bits description - Uint16 GPIO32:2; // 1:0 Select input qualification type for GPIO32 - Uint16 GPIO33:2; // 3:2 Select input qualification type for GPIO33 - Uint16 GPIO34:2; // 5:4 Select input qualification type for GPIO34 - Uint16 GPIO35:2; // 7:6 Select input qualification type for GPIO35 - Uint16 GPIO36:2; // 9:8 Select input qualification type for GPIO36 - Uint16 GPIO37:2; // 11:10 Select input qualification type for GPIO37 - Uint16 GPIO38:2; // 13:12 Select input qualification type for GPIO38 - Uint16 GPIO39:2; // 15:14 Select input qualification type for GPIO39 - Uint16 GPIO40:2; // 17:16 Select input qualification type for GPIO40 - Uint16 GPIO41:2; // 19:18 Select input qualification type for GPIO41 - Uint16 GPIO42:2; // 21:20 Select input qualification type for GPIO42 - Uint16 GPIO43:2; // 23:22 Select input qualification type for GPIO43 - Uint16 GPIO44:2; // 25:24 Select input qualification type for GPIO44 - Uint16 GPIO45:2; // 27:26 Select input qualification type for GPIO45 - Uint16 GPIO46:2; // 29:28 Select input qualification type for GPIO46 - Uint16 GPIO47:2; // 31:30 Select input qualification type for GPIO47 -}; - -union GPBQSEL1_REG { - Uint32 all; - struct GPBQSEL1_BITS bit; -}; - -struct GPBQSEL2_BITS { // bits description - Uint16 GPIO48:2; // 1:0 Select input qualification type for GPIO48 - Uint16 GPIO49:2; // 3:2 Select input qualification type for GPIO49 - Uint16 GPIO50:2; // 5:4 Select input qualification type for GPIO50 - Uint16 GPIO51:2; // 7:6 Select input qualification type for GPIO51 - Uint16 GPIO52:2; // 9:8 Select input qualification type for GPIO52 - Uint16 GPIO53:2; // 11:10 Select input qualification type for GPIO53 - Uint16 GPIO54:2; // 13:12 Select input qualification type for GPIO54 - Uint16 GPIO55:2; // 15:14 Select input qualification type for GPIO55 - Uint16 GPIO56:2; // 17:16 Select input qualification type for GPIO56 - Uint16 GPIO57:2; // 19:18 Select input qualification type for GPIO57 - Uint16 GPIO58:2; // 21:20 Select input qualification type for GPIO58 - Uint16 GPIO59:2; // 23:22 Select input qualification type for GPIO59 - Uint16 GPIO60:2; // 25:24 Select input qualification type for GPIO60 - Uint16 GPIO61:2; // 27:26 Select input qualification type for GPIO61 - Uint16 GPIO62:2; // 29:28 Select input qualification type for GPIO62 - Uint16 GPIO63:2; // 31:30 Select input qualification type for GPIO63 -}; - -union GPBQSEL2_REG { - Uint32 all; - struct GPBQSEL2_BITS bit; -}; - -struct GPBMUX1_BITS { // bits description - Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 - Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 - Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 - Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 - Uint16 GPIO36:2; // 9:8 Defines pin-muxing selection for GPIO36 - Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 - Uint16 GPIO38:2; // 13:12 Defines pin-muxing selection for GPIO38 - Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 - Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 - Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 - Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 - Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 - Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 - Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 - Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 - Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 -}; - -union GPBMUX1_REG { - Uint32 all; - struct GPBMUX1_BITS bit; -}; - -struct GPBMUX2_BITS { // bits description - Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 - Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 - Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 - Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 - Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 - Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 - Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 - Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 - Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 - Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 - Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 - Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 - Uint16 GPIO60:2; // 25:24 Defines pin-muxing selection for GPIO60 - Uint16 GPIO61:2; // 27:26 Defines pin-muxing selection for GPIO61 - Uint16 GPIO62:2; // 29:28 Defines pin-muxing selection for GPIO62 - Uint16 GPIO63:2; // 31:30 Defines pin-muxing selection for GPIO63 -}; - -union GPBMUX2_REG { - Uint32 all; - struct GPBMUX2_BITS bit; -}; - -struct GPBDIR_BITS { // bits description - Uint16 GPIO32:1; // 0 Defines direction for this pin in GPIO mode - Uint16 GPIO33:1; // 1 Defines direction for this pin in GPIO mode - Uint16 GPIO34:1; // 2 Defines direction for this pin in GPIO mode - Uint16 GPIO35:1; // 3 Defines direction for this pin in GPIO mode - Uint16 GPIO36:1; // 4 Defines direction for this pin in GPIO mode - Uint16 GPIO37:1; // 5 Defines direction for this pin in GPIO mode - Uint16 GPIO38:1; // 6 Defines direction for this pin in GPIO mode - Uint16 GPIO39:1; // 7 Defines direction for this pin in GPIO mode - Uint16 GPIO40:1; // 8 Defines direction for this pin in GPIO mode - Uint16 GPIO41:1; // 9 Defines direction for this pin in GPIO mode - Uint16 GPIO42:1; // 10 Defines direction for this pin in GPIO mode - Uint16 GPIO43:1; // 11 Defines direction for this pin in GPIO mode - Uint16 GPIO44:1; // 12 Defines direction for this pin in GPIO mode - Uint16 GPIO45:1; // 13 Defines direction for this pin in GPIO mode - Uint16 GPIO46:1; // 14 Defines direction for this pin in GPIO mode - Uint16 GPIO47:1; // 15 Defines direction for this pin in GPIO mode - Uint16 GPIO48:1; // 16 Defines direction for this pin in GPIO mode - Uint16 GPIO49:1; // 17 Defines direction for this pin in GPIO mode - Uint16 GPIO50:1; // 18 Defines direction for this pin in GPIO mode - Uint16 GPIO51:1; // 19 Defines direction for this pin in GPIO mode - Uint16 GPIO52:1; // 20 Defines direction for this pin in GPIO mode - Uint16 GPIO53:1; // 21 Defines direction for this pin in GPIO mode - Uint16 GPIO54:1; // 22 Defines direction for this pin in GPIO mode - Uint16 GPIO55:1; // 23 Defines direction for this pin in GPIO mode - Uint16 GPIO56:1; // 24 Defines direction for this pin in GPIO mode - Uint16 GPIO57:1; // 25 Defines direction for this pin in GPIO mode - Uint16 GPIO58:1; // 26 Defines direction for this pin in GPIO mode - Uint16 GPIO59:1; // 27 Defines direction for this pin in GPIO mode - Uint16 GPIO60:1; // 28 Defines direction for this pin in GPIO mode - Uint16 GPIO61:1; // 29 Defines direction for this pin in GPIO mode - Uint16 GPIO62:1; // 30 Defines direction for this pin in GPIO mode - Uint16 GPIO63:1; // 31 Defines direction for this pin in GPIO mode -}; - -union GPBDIR_REG { - Uint32 all; - struct GPBDIR_BITS bit; -}; - -struct GPBPUD_BITS { // bits description - Uint16 GPIO32:1; // 0 Pull-Up Disable control for this pin - Uint16 GPIO33:1; // 1 Pull-Up Disable control for this pin - Uint16 GPIO34:1; // 2 Pull-Up Disable control for this pin - Uint16 GPIO35:1; // 3 Pull-Up Disable control for this pin - Uint16 GPIO36:1; // 4 Pull-Up Disable control for this pin - Uint16 GPIO37:1; // 5 Pull-Up Disable control for this pin - Uint16 GPIO38:1; // 6 Pull-Up Disable control for this pin - Uint16 GPIO39:1; // 7 Pull-Up Disable control for this pin - Uint16 GPIO40:1; // 8 Pull-Up Disable control for this pin - Uint16 GPIO41:1; // 9 Pull-Up Disable control for this pin - Uint16 GPIO42:1; // 10 Pull-Up Disable control for this pin - Uint16 GPIO43:1; // 11 Pull-Up Disable control for this pin - Uint16 GPIO44:1; // 12 Pull-Up Disable control for this pin - Uint16 GPIO45:1; // 13 Pull-Up Disable control for this pin - Uint16 GPIO46:1; // 14 Pull-Up Disable control for this pin - Uint16 GPIO47:1; // 15 Pull-Up Disable control for this pin - Uint16 GPIO48:1; // 16 Pull-Up Disable control for this pin - Uint16 GPIO49:1; // 17 Pull-Up Disable control for this pin - Uint16 GPIO50:1; // 18 Pull-Up Disable control for this pin - Uint16 GPIO51:1; // 19 Pull-Up Disable control for this pin - Uint16 GPIO52:1; // 20 Pull-Up Disable control for this pin - Uint16 GPIO53:1; // 21 Pull-Up Disable control for this pin - Uint16 GPIO54:1; // 22 Pull-Up Disable control for this pin - Uint16 GPIO55:1; // 23 Pull-Up Disable control for this pin - Uint16 GPIO56:1; // 24 Pull-Up Disable control for this pin - Uint16 GPIO57:1; // 25 Pull-Up Disable control for this pin - Uint16 GPIO58:1; // 26 Pull-Up Disable control for this pin - Uint16 GPIO59:1; // 27 Pull-Up Disable control for this pin - Uint16 GPIO60:1; // 28 Pull-Up Disable control for this pin - Uint16 GPIO61:1; // 29 Pull-Up Disable control for this pin - Uint16 GPIO62:1; // 30 Pull-Up Disable control for this pin - Uint16 GPIO63:1; // 31 Pull-Up Disable control for this pin -}; - -union GPBPUD_REG { - Uint32 all; - struct GPBPUD_BITS bit; -}; - -struct GPBINV_BITS { // bits description - Uint16 GPIO32:1; // 0 Input inversion control for this pin - Uint16 GPIO33:1; // 1 Input inversion control for this pin - Uint16 GPIO34:1; // 2 Input inversion control for this pin - Uint16 GPIO35:1; // 3 Input inversion control for this pin - Uint16 GPIO36:1; // 4 Input inversion control for this pin - Uint16 GPIO37:1; // 5 Input inversion control for this pin - Uint16 GPIO38:1; // 6 Input inversion control for this pin - Uint16 GPIO39:1; // 7 Input inversion control for this pin - Uint16 GPIO40:1; // 8 Input inversion control for this pin - Uint16 GPIO41:1; // 9 Input inversion control for this pin - Uint16 GPIO42:1; // 10 Input inversion control for this pin - Uint16 GPIO43:1; // 11 Input inversion control for this pin - Uint16 GPIO44:1; // 12 Input inversion control for this pin - Uint16 GPIO45:1; // 13 Input inversion control for this pin - Uint16 GPIO46:1; // 14 Input inversion control for this pin - Uint16 GPIO47:1; // 15 Input inversion control for this pin - Uint16 GPIO48:1; // 16 Input inversion control for this pin - Uint16 GPIO49:1; // 17 Input inversion control for this pin - Uint16 GPIO50:1; // 18 Input inversion control for this pin - Uint16 GPIO51:1; // 19 Input inversion control for this pin - Uint16 GPIO52:1; // 20 Input inversion control for this pin - Uint16 GPIO53:1; // 21 Input inversion control for this pin - Uint16 GPIO54:1; // 22 Input inversion control for this pin - Uint16 GPIO55:1; // 23 Input inversion control for this pin - Uint16 GPIO56:1; // 24 Input inversion control for this pin - Uint16 GPIO57:1; // 25 Input inversion control for this pin - Uint16 GPIO58:1; // 26 Input inversion control for this pin - Uint16 GPIO59:1; // 27 Input inversion control for this pin - Uint16 GPIO60:1; // 28 Input inversion control for this pin - Uint16 GPIO61:1; // 29 Input inversion control for this pin - Uint16 GPIO62:1; // 30 Input inversion control for this pin - Uint16 GPIO63:1; // 31 Input inversion control for this pin -}; - -union GPBINV_REG { - Uint32 all; - struct GPBINV_BITS bit; -}; - -struct GPBODR_BITS { // bits description - Uint16 GPIO32:1; // 0 Outpout Open-Drain control for this pin - Uint16 GPIO33:1; // 1 Outpout Open-Drain control for this pin - Uint16 GPIO34:1; // 2 Outpout Open-Drain control for this pin - Uint16 GPIO35:1; // 3 Outpout Open-Drain control for this pin - Uint16 GPIO36:1; // 4 Outpout Open-Drain control for this pin - Uint16 GPIO37:1; // 5 Outpout Open-Drain control for this pin - Uint16 GPIO38:1; // 6 Outpout Open-Drain control for this pin - Uint16 GPIO39:1; // 7 Outpout Open-Drain control for this pin - Uint16 GPIO40:1; // 8 Outpout Open-Drain control for this pin - Uint16 GPIO41:1; // 9 Outpout Open-Drain control for this pin - Uint16 GPIO42:1; // 10 Outpout Open-Drain control for this pin - Uint16 GPIO43:1; // 11 Outpout Open-Drain control for this pin - Uint16 GPIO44:1; // 12 Outpout Open-Drain control for this pin - Uint16 GPIO45:1; // 13 Outpout Open-Drain control for this pin - Uint16 GPIO46:1; // 14 Outpout Open-Drain control for this pin - Uint16 GPIO47:1; // 15 Outpout Open-Drain control for this pin - Uint16 GPIO48:1; // 16 Outpout Open-Drain control for this pin - Uint16 GPIO49:1; // 17 Outpout Open-Drain control for this pin - Uint16 GPIO50:1; // 18 Outpout Open-Drain control for this pin - Uint16 GPIO51:1; // 19 Outpout Open-Drain control for this pin - Uint16 GPIO52:1; // 20 Outpout Open-Drain control for this pin - Uint16 GPIO53:1; // 21 Outpout Open-Drain control for this pin - Uint16 GPIO54:1; // 22 Outpout Open-Drain control for this pin - Uint16 GPIO55:1; // 23 Outpout Open-Drain control for this pin - Uint16 GPIO56:1; // 24 Outpout Open-Drain control for this pin - Uint16 GPIO57:1; // 25 Outpout Open-Drain control for this pin - Uint16 GPIO58:1; // 26 Outpout Open-Drain control for this pin - Uint16 GPIO59:1; // 27 Outpout Open-Drain control for this pin - Uint16 GPIO60:1; // 28 Outpout Open-Drain control for this pin - Uint16 GPIO61:1; // 29 Outpout Open-Drain control for this pin - Uint16 GPIO62:1; // 30 Outpout Open-Drain control for this pin - Uint16 GPIO63:1; // 31 Outpout Open-Drain control for this pin -}; - -union GPBODR_REG { - Uint32 all; - struct GPBODR_BITS bit; -}; - -struct GPBAMSEL_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:1; // 4 Reserved - Uint16 rsvd6:1; // 5 Reserved - Uint16 rsvd7:1; // 6 Reserved - Uint16 rsvd8:1; // 7 Reserved - Uint16 rsvd9:1; // 8 Reserved - Uint16 rsvd10:1; // 9 Reserved - Uint16 GPIO42:1; // 10 Analog Mode select for this pin - Uint16 GPIO43:1; // 11 Analog Mode select for this pin - Uint16 rsvd11:1; // 12 Reserved - Uint16 rsvd12:1; // 13 Reserved - Uint16 rsvd13:1; // 14 Reserved - Uint16 rsvd14:1; // 15 Reserved - Uint16 rsvd15:1; // 16 Reserved - Uint16 rsvd16:1; // 17 Reserved - Uint16 rsvd17:1; // 18 Reserved - Uint16 rsvd18:1; // 19 Reserved - Uint16 rsvd19:1; // 20 Reserved - Uint16 rsvd20:1; // 21 Reserved - Uint16 rsvd21:1; // 22 Reserved - Uint16 rsvd22:1; // 23 Reserved - Uint16 rsvd23:1; // 24 Reserved - Uint16 rsvd24:1; // 25 Reserved - Uint16 rsvd25:1; // 26 Reserved - Uint16 rsvd26:1; // 27 Reserved - Uint16 rsvd27:1; // 28 Reserved - Uint16 rsvd28:1; // 29 Reserved - Uint16 rsvd29:1; // 30 Reserved - Uint16 rsvd30:1; // 31 Reserved -}; - -union GPBAMSEL_REG { - Uint32 all; - struct GPBAMSEL_BITS bit; -}; - -struct GPBGMUX1_BITS { // bits description - Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 - Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 - Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 - Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 - Uint16 GPIO36:2; // 9:8 Defines pin-muxing selection for GPIO36 - Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 - Uint16 GPIO38:2; // 13:12 Defines pin-muxing selection for GPIO38 - Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 - Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 - Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 - Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 - Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 - Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 - Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 - Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 - Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 -}; - -union GPBGMUX1_REG { - Uint32 all; - struct GPBGMUX1_BITS bit; -}; - -struct GPBGMUX2_BITS { // bits description - Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 - Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 - Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 - Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 - Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 - Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 - Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 - Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 - Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 - Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 - Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 - Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 - Uint16 GPIO60:2; // 25:24 Defines pin-muxing selection for GPIO60 - Uint16 GPIO61:2; // 27:26 Defines pin-muxing selection for GPIO61 - Uint16 GPIO62:2; // 29:28 Defines pin-muxing selection for GPIO62 - Uint16 GPIO63:2; // 31:30 Defines pin-muxing selection for GPIO63 -}; - -union GPBGMUX2_REG { - Uint32 all; - struct GPBGMUX2_BITS bit; -}; - -struct GPBCSEL1_BITS { // bits description - Uint16 GPIO32:4; // 3:0 GPIO32 Master CPU Select - Uint16 GPIO33:4; // 7:4 GPIO33 Master CPU Select - Uint16 GPIO34:4; // 11:8 GPIO34 Master CPU Select - Uint16 GPIO35:4; // 15:12 GPIO35 Master CPU Select - Uint16 GPIO36:4; // 19:16 GPIO36 Master CPU Select - Uint16 GPIO37:4; // 23:20 GPIO37 Master CPU Select - Uint16 GPIO38:4; // 27:24 GPIO38 Master CPU Select - Uint16 GPIO39:4; // 31:28 GPIO39 Master CPU Select -}; - -union GPBCSEL1_REG { - Uint32 all; - struct GPBCSEL1_BITS bit; -}; - -struct GPBCSEL2_BITS { // bits description - Uint16 GPIO40:4; // 3:0 GPIO40 Master CPU Select - Uint16 GPIO41:4; // 7:4 GPIO41 Master CPU Select - Uint16 GPIO42:4; // 11:8 GPIO42 Master CPU Select - Uint16 GPIO43:4; // 15:12 GPIO43 Master CPU Select - Uint16 GPIO44:4; // 19:16 GPIO44 Master CPU Select - Uint16 GPIO45:4; // 23:20 GPIO45 Master CPU Select - Uint16 GPIO46:4; // 27:24 GPIO46 Master CPU Select - Uint16 GPIO47:4; // 31:28 GPIO47 Master CPU Select -}; - -union GPBCSEL2_REG { - Uint32 all; - struct GPBCSEL2_BITS bit; -}; - -struct GPBCSEL3_BITS { // bits description - Uint16 GPIO48:4; // 3:0 GPIO48 Master CPU Select - Uint16 GPIO49:4; // 7:4 GPIO49 Master CPU Select - Uint16 GPIO50:4; // 11:8 GPIO50 Master CPU Select - Uint16 GPIO51:4; // 15:12 GPIO51 Master CPU Select - Uint16 GPIO52:4; // 19:16 GPIO52 Master CPU Select - Uint16 GPIO53:4; // 23:20 GPIO53 Master CPU Select - Uint16 GPIO54:4; // 27:24 GPIO54 Master CPU Select - Uint16 GPIO55:4; // 31:28 GPIO55 Master CPU Select -}; - -union GPBCSEL3_REG { - Uint32 all; - struct GPBCSEL3_BITS bit; -}; - -struct GPBCSEL4_BITS { // bits description - Uint16 GPIO56:4; // 3:0 GPIO56 Master CPU Select - Uint16 GPIO57:4; // 7:4 GPIO57 Master CPU Select - Uint16 GPIO58:4; // 11:8 GPIO58 Master CPU Select - Uint16 GPIO59:4; // 15:12 GPIO59 Master CPU Select - Uint16 GPIO60:4; // 19:16 GPIO60 Master CPU Select - Uint16 GPIO61:4; // 23:20 GPIO61 Master CPU Select - Uint16 GPIO62:4; // 27:24 GPIO62 Master CPU Select - Uint16 GPIO63:4; // 31:28 GPIO63 Master CPU Select -}; - -union GPBCSEL4_REG { - Uint32 all; - struct GPBCSEL4_BITS bit; -}; - -struct GPBLOCK_BITS { // bits description - Uint16 GPIO32:1; // 0 Configuration Lock bit for this pin - Uint16 GPIO33:1; // 1 Configuration Lock bit for this pin - Uint16 GPIO34:1; // 2 Configuration Lock bit for this pin - Uint16 GPIO35:1; // 3 Configuration Lock bit for this pin - Uint16 GPIO36:1; // 4 Configuration Lock bit for this pin - Uint16 GPIO37:1; // 5 Configuration Lock bit for this pin - Uint16 GPIO38:1; // 6 Configuration Lock bit for this pin - Uint16 GPIO39:1; // 7 Configuration Lock bit for this pin - Uint16 GPIO40:1; // 8 Configuration Lock bit for this pin - Uint16 GPIO41:1; // 9 Configuration Lock bit for this pin - Uint16 GPIO42:1; // 10 Configuration Lock bit for this pin - Uint16 GPIO43:1; // 11 Configuration Lock bit for this pin - Uint16 GPIO44:1; // 12 Configuration Lock bit for this pin - Uint16 GPIO45:1; // 13 Configuration Lock bit for this pin - Uint16 GPIO46:1; // 14 Configuration Lock bit for this pin - Uint16 GPIO47:1; // 15 Configuration Lock bit for this pin - Uint16 GPIO48:1; // 16 Configuration Lock bit for this pin - Uint16 GPIO49:1; // 17 Configuration Lock bit for this pin - Uint16 GPIO50:1; // 18 Configuration Lock bit for this pin - Uint16 GPIO51:1; // 19 Configuration Lock bit for this pin - Uint16 GPIO52:1; // 20 Configuration Lock bit for this pin - Uint16 GPIO53:1; // 21 Configuration Lock bit for this pin - Uint16 GPIO54:1; // 22 Configuration Lock bit for this pin - Uint16 GPIO55:1; // 23 Configuration Lock bit for this pin - Uint16 GPIO56:1; // 24 Configuration Lock bit for this pin - Uint16 GPIO57:1; // 25 Configuration Lock bit for this pin - Uint16 GPIO58:1; // 26 Configuration Lock bit for this pin - Uint16 GPIO59:1; // 27 Configuration Lock bit for this pin - Uint16 GPIO60:1; // 28 Configuration Lock bit for this pin - Uint16 GPIO61:1; // 29 Configuration Lock bit for this pin - Uint16 GPIO62:1; // 30 Configuration Lock bit for this pin - Uint16 GPIO63:1; // 31 Configuration Lock bit for this pin -}; - -union GPBLOCK_REG { - Uint32 all; - struct GPBLOCK_BITS bit; -}; - -struct GPBCR_BITS { // bits description - Uint16 GPIO32:1; // 0 Configuration lock commit bit for this pin - Uint16 GPIO33:1; // 1 Configuration lock commit bit for this pin - Uint16 GPIO34:1; // 2 Configuration lock commit bit for this pin - Uint16 GPIO35:1; // 3 Configuration lock commit bit for this pin - Uint16 GPIO36:1; // 4 Configuration lock commit bit for this pin - Uint16 GPIO37:1; // 5 Configuration lock commit bit for this pin - Uint16 GPIO38:1; // 6 Configuration lock commit bit for this pin - Uint16 GPIO39:1; // 7 Configuration lock commit bit for this pin - Uint16 GPIO40:1; // 8 Configuration lock commit bit for this pin - Uint16 GPIO41:1; // 9 Configuration lock commit bit for this pin - Uint16 GPIO42:1; // 10 Configuration lock commit bit for this pin - Uint16 GPIO43:1; // 11 Configuration lock commit bit for this pin - Uint16 GPIO44:1; // 12 Configuration lock commit bit for this pin - Uint16 GPIO45:1; // 13 Configuration lock commit bit for this pin - Uint16 GPIO46:1; // 14 Configuration lock commit bit for this pin - Uint16 GPIO47:1; // 15 Configuration lock commit bit for this pin - Uint16 GPIO48:1; // 16 Configuration lock commit bit for this pin - Uint16 GPIO49:1; // 17 Configuration lock commit bit for this pin - Uint16 GPIO50:1; // 18 Configuration lock commit bit for this pin - Uint16 GPIO51:1; // 19 Configuration lock commit bit for this pin - Uint16 GPIO52:1; // 20 Configuration lock commit bit for this pin - Uint16 GPIO53:1; // 21 Configuration lock commit bit for this pin - Uint16 GPIO54:1; // 22 Configuration lock commit bit for this pin - Uint16 GPIO55:1; // 23 Configuration lock commit bit for this pin - Uint16 GPIO56:1; // 24 Configuration lock commit bit for this pin - Uint16 GPIO57:1; // 25 Configuration lock commit bit for this pin - Uint16 GPIO58:1; // 26 Configuration lock commit bit for this pin - Uint16 GPIO59:1; // 27 Configuration lock commit bit for this pin - Uint16 GPIO60:1; // 28 Configuration lock commit bit for this pin - Uint16 GPIO61:1; // 29 Configuration lock commit bit for this pin - Uint16 GPIO62:1; // 30 Configuration lock commit bit for this pin - Uint16 GPIO63:1; // 31 Configuration lock commit bit for this pin -}; - -union GPBCR_REG { - Uint32 all; - struct GPBCR_BITS bit; -}; - -struct GPCCTRL_BITS { // bits description - Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO64 to GPIO71 - Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO72 to GPIO79 - Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO80 to GPIO87 - Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO88 to GPIO95 -}; - -union GPCCTRL_REG { - Uint32 all; - struct GPCCTRL_BITS bit; -}; - -struct GPCQSEL1_BITS { // bits description - Uint16 GPIO64:2; // 1:0 Select input qualification type for GPIO64 - Uint16 GPIO65:2; // 3:2 Select input qualification type for GPIO65 - Uint16 GPIO66:2; // 5:4 Select input qualification type for GPIO66 - Uint16 GPIO67:2; // 7:6 Select input qualification type for GPIO67 - Uint16 GPIO68:2; // 9:8 Select input qualification type for GPIO68 - Uint16 GPIO69:2; // 11:10 Select input qualification type for GPIO69 - Uint16 GPIO70:2; // 13:12 Select input qualification type for GPIO70 - Uint16 GPIO71:2; // 15:14 Select input qualification type for GPIO71 - Uint16 GPIO72:2; // 17:16 Select input qualification type for GPIO72 - Uint16 GPIO73:2; // 19:18 Select input qualification type for GPIO73 - Uint16 GPIO74:2; // 21:20 Select input qualification type for GPIO74 - Uint16 GPIO75:2; // 23:22 Select input qualification type for GPIO75 - Uint16 GPIO76:2; // 25:24 Select input qualification type for GPIO76 - Uint16 GPIO77:2; // 27:26 Select input qualification type for GPIO77 - Uint16 GPIO78:2; // 29:28 Select input qualification type for GPIO78 - Uint16 GPIO79:2; // 31:30 Select input qualification type for GPIO79 -}; - -union GPCQSEL1_REG { - Uint32 all; - struct GPCQSEL1_BITS bit; -}; - -struct GPCQSEL2_BITS { // bits description - Uint16 GPIO80:2; // 1:0 Select input qualification type for GPIO80 - Uint16 GPIO81:2; // 3:2 Select input qualification type for GPIO81 - Uint16 GPIO82:2; // 5:4 Select input qualification type for GPIO82 - Uint16 GPIO83:2; // 7:6 Select input qualification type for GPIO83 - Uint16 GPIO84:2; // 9:8 Select input qualification type for GPIO84 - Uint16 GPIO85:2; // 11:10 Select input qualification type for GPIO85 - Uint16 GPIO86:2; // 13:12 Select input qualification type for GPIO86 - Uint16 GPIO87:2; // 15:14 Select input qualification type for GPIO87 - Uint16 GPIO88:2; // 17:16 Select input qualification type for GPIO88 - Uint16 GPIO89:2; // 19:18 Select input qualification type for GPIO89 - Uint16 GPIO90:2; // 21:20 Select input qualification type for GPIO90 - Uint16 GPIO91:2; // 23:22 Select input qualification type for GPIO91 - Uint16 GPIO92:2; // 25:24 Select input qualification type for GPIO92 - Uint16 GPIO93:2; // 27:26 Select input qualification type for GPIO93 - Uint16 GPIO94:2; // 29:28 Select input qualification type for GPIO94 - Uint16 GPIO95:2; // 31:30 Select input qualification type for GPIO95 -}; - -union GPCQSEL2_REG { - Uint32 all; - struct GPCQSEL2_BITS bit; -}; - -struct GPCMUX1_BITS { // bits description - Uint16 GPIO64:2; // 1:0 Defines pin-muxing selection for GPIO64 - Uint16 GPIO65:2; // 3:2 Defines pin-muxing selection for GPIO65 - Uint16 GPIO66:2; // 5:4 Defines pin-muxing selection for GPIO66 - Uint16 GPIO67:2; // 7:6 Defines pin-muxing selection for GPIO67 - Uint16 GPIO68:2; // 9:8 Defines pin-muxing selection for GPIO68 - Uint16 GPIO69:2; // 11:10 Defines pin-muxing selection for GPIO69 - Uint16 GPIO70:2; // 13:12 Defines pin-muxing selection for GPIO70 - Uint16 GPIO71:2; // 15:14 Defines pin-muxing selection for GPIO71 - Uint16 GPIO72:2; // 17:16 Defines pin-muxing selection for GPIO72 - Uint16 GPIO73:2; // 19:18 Defines pin-muxing selection for GPIO73 - Uint16 GPIO74:2; // 21:20 Defines pin-muxing selection for GPIO74 - Uint16 GPIO75:2; // 23:22 Defines pin-muxing selection for GPIO75 - Uint16 GPIO76:2; // 25:24 Defines pin-muxing selection for GPIO76 - Uint16 GPIO77:2; // 27:26 Defines pin-muxing selection for GPIO77 - Uint16 GPIO78:2; // 29:28 Defines pin-muxing selection for GPIO78 - Uint16 GPIO79:2; // 31:30 Defines pin-muxing selection for GPIO79 -}; - -union GPCMUX1_REG { - Uint32 all; - struct GPCMUX1_BITS bit; -}; - -struct GPCMUX2_BITS { // bits description - Uint16 GPIO80:2; // 1:0 Defines pin-muxing selection for GPIO80 - Uint16 GPIO81:2; // 3:2 Defines pin-muxing selection for GPIO81 - Uint16 GPIO82:2; // 5:4 Defines pin-muxing selection for GPIO82 - Uint16 GPIO83:2; // 7:6 Defines pin-muxing selection for GPIO83 - Uint16 GPIO84:2; // 9:8 Defines pin-muxing selection for GPIO84 - Uint16 GPIO85:2; // 11:10 Defines pin-muxing selection for GPIO85 - Uint16 GPIO86:2; // 13:12 Defines pin-muxing selection for GPIO86 - Uint16 GPIO87:2; // 15:14 Defines pin-muxing selection for GPIO87 - Uint16 GPIO88:2; // 17:16 Defines pin-muxing selection for GPIO88 - Uint16 GPIO89:2; // 19:18 Defines pin-muxing selection for GPIO89 - Uint16 GPIO90:2; // 21:20 Defines pin-muxing selection for GPIO90 - Uint16 GPIO91:2; // 23:22 Defines pin-muxing selection for GPIO91 - Uint16 GPIO92:2; // 25:24 Defines pin-muxing selection for GPIO92 - Uint16 GPIO93:2; // 27:26 Defines pin-muxing selection for GPIO93 - Uint16 GPIO94:2; // 29:28 Defines pin-muxing selection for GPIO94 - Uint16 GPIO95:2; // 31:30 Defines pin-muxing selection for GPIO95 -}; - -union GPCMUX2_REG { - Uint32 all; - struct GPCMUX2_BITS bit; -}; - -struct GPCDIR_BITS { // bits description - Uint16 GPIO64:1; // 0 Defines direction for this pin in GPIO mode - Uint16 GPIO65:1; // 1 Defines direction for this pin in GPIO mode - Uint16 GPIO66:1; // 2 Defines direction for this pin in GPIO mode - Uint16 GPIO67:1; // 3 Defines direction for this pin in GPIO mode - Uint16 GPIO68:1; // 4 Defines direction for this pin in GPIO mode - Uint16 GPIO69:1; // 5 Defines direction for this pin in GPIO mode - Uint16 GPIO70:1; // 6 Defines direction for this pin in GPIO mode - Uint16 GPIO71:1; // 7 Defines direction for this pin in GPIO mode - Uint16 GPIO72:1; // 8 Defines direction for this pin in GPIO mode - Uint16 GPIO73:1; // 9 Defines direction for this pin in GPIO mode - Uint16 GPIO74:1; // 10 Defines direction for this pin in GPIO mode - Uint16 GPIO75:1; // 11 Defines direction for this pin in GPIO mode - Uint16 GPIO76:1; // 12 Defines direction for this pin in GPIO mode - Uint16 GPIO77:1; // 13 Defines direction for this pin in GPIO mode - Uint16 GPIO78:1; // 14 Defines direction for this pin in GPIO mode - Uint16 GPIO79:1; // 15 Defines direction for this pin in GPIO mode - Uint16 GPIO80:1; // 16 Defines direction for this pin in GPIO mode - Uint16 GPIO81:1; // 17 Defines direction for this pin in GPIO mode - Uint16 GPIO82:1; // 18 Defines direction for this pin in GPIO mode - Uint16 GPIO83:1; // 19 Defines direction for this pin in GPIO mode - Uint16 GPIO84:1; // 20 Defines direction for this pin in GPIO mode - Uint16 GPIO85:1; // 21 Defines direction for this pin in GPIO mode - Uint16 GPIO86:1; // 22 Defines direction for this pin in GPIO mode - Uint16 GPIO87:1; // 23 Defines direction for this pin in GPIO mode - Uint16 GPIO88:1; // 24 Defines direction for this pin in GPIO mode - Uint16 GPIO89:1; // 25 Defines direction for this pin in GPIO mode - Uint16 GPIO90:1; // 26 Defines direction for this pin in GPIO mode - Uint16 GPIO91:1; // 27 Defines direction for this pin in GPIO mode - Uint16 GPIO92:1; // 28 Defines direction for this pin in GPIO mode - Uint16 GPIO93:1; // 29 Defines direction for this pin in GPIO mode - Uint16 GPIO94:1; // 30 Defines direction for this pin in GPIO mode - Uint16 GPIO95:1; // 31 Defines direction for this pin in GPIO mode -}; - -union GPCDIR_REG { - Uint32 all; - struct GPCDIR_BITS bit; -}; - -struct GPCPUD_BITS { // bits description - Uint16 GPIO64:1; // 0 Pull-Up Disable control for this pin - Uint16 GPIO65:1; // 1 Pull-Up Disable control for this pin - Uint16 GPIO66:1; // 2 Pull-Up Disable control for this pin - Uint16 GPIO67:1; // 3 Pull-Up Disable control for this pin - Uint16 GPIO68:1; // 4 Pull-Up Disable control for this pin - Uint16 GPIO69:1; // 5 Pull-Up Disable control for this pin - Uint16 GPIO70:1; // 6 Pull-Up Disable control for this pin - Uint16 GPIO71:1; // 7 Pull-Up Disable control for this pin - Uint16 GPIO72:1; // 8 Pull-Up Disable control for this pin - Uint16 GPIO73:1; // 9 Pull-Up Disable control for this pin - Uint16 GPIO74:1; // 10 Pull-Up Disable control for this pin - Uint16 GPIO75:1; // 11 Pull-Up Disable control for this pin - Uint16 GPIO76:1; // 12 Pull-Up Disable control for this pin - Uint16 GPIO77:1; // 13 Pull-Up Disable control for this pin - Uint16 GPIO78:1; // 14 Pull-Up Disable control for this pin - Uint16 GPIO79:1; // 15 Pull-Up Disable control for this pin - Uint16 GPIO80:1; // 16 Pull-Up Disable control for this pin - Uint16 GPIO81:1; // 17 Pull-Up Disable control for this pin - Uint16 GPIO82:1; // 18 Pull-Up Disable control for this pin - Uint16 GPIO83:1; // 19 Pull-Up Disable control for this pin - Uint16 GPIO84:1; // 20 Pull-Up Disable control for this pin - Uint16 GPIO85:1; // 21 Pull-Up Disable control for this pin - Uint16 GPIO86:1; // 22 Pull-Up Disable control for this pin - Uint16 GPIO87:1; // 23 Pull-Up Disable control for this pin - Uint16 GPIO88:1; // 24 Pull-Up Disable control for this pin - Uint16 GPIO89:1; // 25 Pull-Up Disable control for this pin - Uint16 GPIO90:1; // 26 Pull-Up Disable control for this pin - Uint16 GPIO91:1; // 27 Pull-Up Disable control for this pin - Uint16 GPIO92:1; // 28 Pull-Up Disable control for this pin - Uint16 GPIO93:1; // 29 Pull-Up Disable control for this pin - Uint16 GPIO94:1; // 30 Pull-Up Disable control for this pin - Uint16 GPIO95:1; // 31 Pull-Up Disable control for this pin -}; - -union GPCPUD_REG { - Uint32 all; - struct GPCPUD_BITS bit; -}; - -struct GPCINV_BITS { // bits description - Uint16 GPIO64:1; // 0 Input inversion control for this pin - Uint16 GPIO65:1; // 1 Input inversion control for this pin - Uint16 GPIO66:1; // 2 Input inversion control for this pin - Uint16 GPIO67:1; // 3 Input inversion control for this pin - Uint16 GPIO68:1; // 4 Input inversion control for this pin - Uint16 GPIO69:1; // 5 Input inversion control for this pin - Uint16 GPIO70:1; // 6 Input inversion control for this pin - Uint16 GPIO71:1; // 7 Input inversion control for this pin - Uint16 GPIO72:1; // 8 Input inversion control for this pin - Uint16 GPIO73:1; // 9 Input inversion control for this pin - Uint16 GPIO74:1; // 10 Input inversion control for this pin - Uint16 GPIO75:1; // 11 Input inversion control for this pin - Uint16 GPIO76:1; // 12 Input inversion control for this pin - Uint16 GPIO77:1; // 13 Input inversion control for this pin - Uint16 GPIO78:1; // 14 Input inversion control for this pin - Uint16 GPIO79:1; // 15 Input inversion control for this pin - Uint16 GPIO80:1; // 16 Input inversion control for this pin - Uint16 GPIO81:1; // 17 Input inversion control for this pin - Uint16 GPIO82:1; // 18 Input inversion control for this pin - Uint16 GPIO83:1; // 19 Input inversion control for this pin - Uint16 GPIO84:1; // 20 Input inversion control for this pin - Uint16 GPIO85:1; // 21 Input inversion control for this pin - Uint16 GPIO86:1; // 22 Input inversion control for this pin - Uint16 GPIO87:1; // 23 Input inversion control for this pin - Uint16 GPIO88:1; // 24 Input inversion control for this pin - Uint16 GPIO89:1; // 25 Input inversion control for this pin - Uint16 GPIO90:1; // 26 Input inversion control for this pin - Uint16 GPIO91:1; // 27 Input inversion control for this pin - Uint16 GPIO92:1; // 28 Input inversion control for this pin - Uint16 GPIO93:1; // 29 Input inversion control for this pin - Uint16 GPIO94:1; // 30 Input inversion control for this pin - Uint16 GPIO95:1; // 31 Input inversion control for this pin -}; - -union GPCINV_REG { - Uint32 all; - struct GPCINV_BITS bit; -}; - -struct GPCODR_BITS { // bits description - Uint16 GPIO64:1; // 0 Outpout Open-Drain control for this pin - Uint16 GPIO65:1; // 1 Outpout Open-Drain control for this pin - Uint16 GPIO66:1; // 2 Outpout Open-Drain control for this pin - Uint16 GPIO67:1; // 3 Outpout Open-Drain control for this pin - Uint16 GPIO68:1; // 4 Outpout Open-Drain control for this pin - Uint16 GPIO69:1; // 5 Outpout Open-Drain control for this pin - Uint16 GPIO70:1; // 6 Outpout Open-Drain control for this pin - Uint16 GPIO71:1; // 7 Outpout Open-Drain control for this pin - Uint16 GPIO72:1; // 8 Outpout Open-Drain control for this pin - Uint16 GPIO73:1; // 9 Outpout Open-Drain control for this pin - Uint16 GPIO74:1; // 10 Outpout Open-Drain control for this pin - Uint16 GPIO75:1; // 11 Outpout Open-Drain control for this pin - Uint16 GPIO76:1; // 12 Outpout Open-Drain control for this pin - Uint16 GPIO77:1; // 13 Outpout Open-Drain control for this pin - Uint16 GPIO78:1; // 14 Outpout Open-Drain control for this pin - Uint16 GPIO79:1; // 15 Outpout Open-Drain control for this pin - Uint16 GPIO80:1; // 16 Outpout Open-Drain control for this pin - Uint16 GPIO81:1; // 17 Outpout Open-Drain control for this pin - Uint16 GPIO82:1; // 18 Outpout Open-Drain control for this pin - Uint16 GPIO83:1; // 19 Outpout Open-Drain control for this pin - Uint16 GPIO84:1; // 20 Outpout Open-Drain control for this pin - Uint16 GPIO85:1; // 21 Outpout Open-Drain control for this pin - Uint16 GPIO86:1; // 22 Outpout Open-Drain control for this pin - Uint16 GPIO87:1; // 23 Outpout Open-Drain control for this pin - Uint16 GPIO88:1; // 24 Outpout Open-Drain control for this pin - Uint16 GPIO89:1; // 25 Outpout Open-Drain control for this pin - Uint16 GPIO90:1; // 26 Outpout Open-Drain control for this pin - Uint16 GPIO91:1; // 27 Outpout Open-Drain control for this pin - Uint16 GPIO92:1; // 28 Outpout Open-Drain control for this pin - Uint16 GPIO93:1; // 29 Outpout Open-Drain control for this pin - Uint16 GPIO94:1; // 30 Outpout Open-Drain control for this pin - Uint16 GPIO95:1; // 31 Outpout Open-Drain control for this pin -}; - -union GPCODR_REG { - Uint32 all; - struct GPCODR_BITS bit; -}; - -struct GPCGMUX1_BITS { // bits description - Uint16 GPIO64:2; // 1:0 Defines pin-muxing selection for GPIO64 - Uint16 GPIO65:2; // 3:2 Defines pin-muxing selection for GPIO65 - Uint16 GPIO66:2; // 5:4 Defines pin-muxing selection for GPIO66 - Uint16 GPIO67:2; // 7:6 Defines pin-muxing selection for GPIO67 - Uint16 GPIO68:2; // 9:8 Defines pin-muxing selection for GPIO68 - Uint16 GPIO69:2; // 11:10 Defines pin-muxing selection for GPIO69 - Uint16 GPIO70:2; // 13:12 Defines pin-muxing selection for GPIO70 - Uint16 GPIO71:2; // 15:14 Defines pin-muxing selection for GPIO71 - Uint16 GPIO72:2; // 17:16 Defines pin-muxing selection for GPIO72 - Uint16 GPIO73:2; // 19:18 Defines pin-muxing selection for GPIO73 - Uint16 GPIO74:2; // 21:20 Defines pin-muxing selection for GPIO74 - Uint16 GPIO75:2; // 23:22 Defines pin-muxing selection for GPIO75 - Uint16 GPIO76:2; // 25:24 Defines pin-muxing selection for GPIO76 - Uint16 GPIO77:2; // 27:26 Defines pin-muxing selection for GPIO77 - Uint16 GPIO78:2; // 29:28 Defines pin-muxing selection for GPIO78 - Uint16 GPIO79:2; // 31:30 Defines pin-muxing selection for GPIO79 -}; - -union GPCGMUX1_REG { - Uint32 all; - struct GPCGMUX1_BITS bit; -}; - -struct GPCGMUX2_BITS { // bits description - Uint16 GPIO80:2; // 1:0 Defines pin-muxing selection for GPIO80 - Uint16 GPIO81:2; // 3:2 Defines pin-muxing selection for GPIO81 - Uint16 GPIO82:2; // 5:4 Defines pin-muxing selection for GPIO82 - Uint16 GPIO83:2; // 7:6 Defines pin-muxing selection for GPIO83 - Uint16 GPIO84:2; // 9:8 Defines pin-muxing selection for GPIO84 - Uint16 GPIO85:2; // 11:10 Defines pin-muxing selection for GPIO85 - Uint16 GPIO86:2; // 13:12 Defines pin-muxing selection for GPIO86 - Uint16 GPIO87:2; // 15:14 Defines pin-muxing selection for GPIO87 - Uint16 GPIO88:2; // 17:16 Defines pin-muxing selection for GPIO88 - Uint16 GPIO89:2; // 19:18 Defines pin-muxing selection for GPIO89 - Uint16 GPIO90:2; // 21:20 Defines pin-muxing selection for GPIO90 - Uint16 GPIO91:2; // 23:22 Defines pin-muxing selection for GPIO91 - Uint16 GPIO92:2; // 25:24 Defines pin-muxing selection for GPIO92 - Uint16 GPIO93:2; // 27:26 Defines pin-muxing selection for GPIO93 - Uint16 GPIO94:2; // 29:28 Defines pin-muxing selection for GPIO94 - Uint16 GPIO95:2; // 31:30 Defines pin-muxing selection for GPIO95 -}; - -union GPCGMUX2_REG { - Uint32 all; - struct GPCGMUX2_BITS bit; -}; - -struct GPCCSEL1_BITS { // bits description - Uint16 GPIO64:4; // 3:0 GPIO64 Master CPU Select - Uint16 GPIO65:4; // 7:4 GPIO65 Master CPU Select - Uint16 GPIO66:4; // 11:8 GPIO66 Master CPU Select - Uint16 GPIO67:4; // 15:12 GPIO67 Master CPU Select - Uint16 GPIO68:4; // 19:16 GPIO68 Master CPU Select - Uint16 GPIO69:4; // 23:20 GPIO69 Master CPU Select - Uint16 GPIO70:4; // 27:24 GPIO70 Master CPU Select - Uint16 GPIO71:4; // 31:28 GPIO71 Master CPU Select -}; - -union GPCCSEL1_REG { - Uint32 all; - struct GPCCSEL1_BITS bit; -}; - -struct GPCCSEL2_BITS { // bits description - Uint16 GPIO72:4; // 3:0 GPIO72 Master CPU Select - Uint16 GPIO73:4; // 7:4 GPIO73 Master CPU Select - Uint16 GPIO74:4; // 11:8 GPIO74 Master CPU Select - Uint16 GPIO75:4; // 15:12 GPIO75 Master CPU Select - Uint16 GPIO76:4; // 19:16 GPIO76 Master CPU Select - Uint16 GPIO77:4; // 23:20 GPIO77 Master CPU Select - Uint16 GPIO78:4; // 27:24 GPIO78 Master CPU Select - Uint16 GPIO79:4; // 31:28 GPIO79 Master CPU Select -}; - -union GPCCSEL2_REG { - Uint32 all; - struct GPCCSEL2_BITS bit; -}; - -struct GPCCSEL3_BITS { // bits description - Uint16 GPIO80:4; // 3:0 GPIO80 Master CPU Select - Uint16 GPIO81:4; // 7:4 GPIO81 Master CPU Select - Uint16 GPIO82:4; // 11:8 GPIO82 Master CPU Select - Uint16 GPIO83:4; // 15:12 GPIO83 Master CPU Select - Uint16 GPIO84:4; // 19:16 GPIO84 Master CPU Select - Uint16 GPIO85:4; // 23:20 GPIO85 Master CPU Select - Uint16 GPIO86:4; // 27:24 GPIO86 Master CPU Select - Uint16 GPIO87:4; // 31:28 GPIO87 Master CPU Select -}; - -union GPCCSEL3_REG { - Uint32 all; - struct GPCCSEL3_BITS bit; -}; - -struct GPCCSEL4_BITS { // bits description - Uint16 GPIO88:4; // 3:0 GPIO88 Master CPU Select - Uint16 GPIO89:4; // 7:4 GPIO89 Master CPU Select - Uint16 GPIO90:4; // 11:8 GPIO90 Master CPU Select - Uint16 GPIO91:4; // 15:12 GPIO91 Master CPU Select - Uint16 GPIO92:4; // 19:16 GPIO92 Master CPU Select - Uint16 GPIO93:4; // 23:20 GPIO93 Master CPU Select - Uint16 GPIO94:4; // 27:24 GPIO94 Master CPU Select - Uint16 GPIO95:4; // 31:28 GPIO95 Master CPU Select -}; - -union GPCCSEL4_REG { - Uint32 all; - struct GPCCSEL4_BITS bit; -}; - -struct GPCLOCK_BITS { // bits description - Uint16 GPIO64:1; // 0 Configuration Lock bit for this pin - Uint16 GPIO65:1; // 1 Configuration Lock bit for this pin - Uint16 GPIO66:1; // 2 Configuration Lock bit for this pin - Uint16 GPIO67:1; // 3 Configuration Lock bit for this pin - Uint16 GPIO68:1; // 4 Configuration Lock bit for this pin - Uint16 GPIO69:1; // 5 Configuration Lock bit for this pin - Uint16 GPIO70:1; // 6 Configuration Lock bit for this pin - Uint16 GPIO71:1; // 7 Configuration Lock bit for this pin - Uint16 GPIO72:1; // 8 Configuration Lock bit for this pin - Uint16 GPIO73:1; // 9 Configuration Lock bit for this pin - Uint16 GPIO74:1; // 10 Configuration Lock bit for this pin - Uint16 GPIO75:1; // 11 Configuration Lock bit for this pin - Uint16 GPIO76:1; // 12 Configuration Lock bit for this pin - Uint16 GPIO77:1; // 13 Configuration Lock bit for this pin - Uint16 GPIO78:1; // 14 Configuration Lock bit for this pin - Uint16 GPIO79:1; // 15 Configuration Lock bit for this pin - Uint16 GPIO80:1; // 16 Configuration Lock bit for this pin - Uint16 GPIO81:1; // 17 Configuration Lock bit for this pin - Uint16 GPIO82:1; // 18 Configuration Lock bit for this pin - Uint16 GPIO83:1; // 19 Configuration Lock bit for this pin - Uint16 GPIO84:1; // 20 Configuration Lock bit for this pin - Uint16 GPIO85:1; // 21 Configuration Lock bit for this pin - Uint16 GPIO86:1; // 22 Configuration Lock bit for this pin - Uint16 GPIO87:1; // 23 Configuration Lock bit for this pin - Uint16 GPIO88:1; // 24 Configuration Lock bit for this pin - Uint16 GPIO89:1; // 25 Configuration Lock bit for this pin - Uint16 GPIO90:1; // 26 Configuration Lock bit for this pin - Uint16 GPIO91:1; // 27 Configuration Lock bit for this pin - Uint16 GPIO92:1; // 28 Configuration Lock bit for this pin - Uint16 GPIO93:1; // 29 Configuration Lock bit for this pin - Uint16 GPIO94:1; // 30 Configuration Lock bit for this pin - Uint16 GPIO95:1; // 31 Configuration Lock bit for this pin -}; - -union GPCLOCK_REG { - Uint32 all; - struct GPCLOCK_BITS bit; -}; - -struct GPCCR_BITS { // bits description - Uint16 GPIO64:1; // 0 Configuration lock commit bit for this pin - Uint16 GPIO65:1; // 1 Configuration lock commit bit for this pin - Uint16 GPIO66:1; // 2 Configuration lock commit bit for this pin - Uint16 GPIO67:1; // 3 Configuration lock commit bit for this pin - Uint16 GPIO68:1; // 4 Configuration lock commit bit for this pin - Uint16 GPIO69:1; // 5 Configuration lock commit bit for this pin - Uint16 GPIO70:1; // 6 Configuration lock commit bit for this pin - Uint16 GPIO71:1; // 7 Configuration lock commit bit for this pin - Uint16 GPIO72:1; // 8 Configuration lock commit bit for this pin - Uint16 GPIO73:1; // 9 Configuration lock commit bit for this pin - Uint16 GPIO74:1; // 10 Configuration lock commit bit for this pin - Uint16 GPIO75:1; // 11 Configuration lock commit bit for this pin - Uint16 GPIO76:1; // 12 Configuration lock commit bit for this pin - Uint16 GPIO77:1; // 13 Configuration lock commit bit for this pin - Uint16 GPIO78:1; // 14 Configuration lock commit bit for this pin - Uint16 GPIO79:1; // 15 Configuration lock commit bit for this pin - Uint16 GPIO80:1; // 16 Configuration lock commit bit for this pin - Uint16 GPIO81:1; // 17 Configuration lock commit bit for this pin - Uint16 GPIO82:1; // 18 Configuration lock commit bit for this pin - Uint16 GPIO83:1; // 19 Configuration lock commit bit for this pin - Uint16 GPIO84:1; // 20 Configuration lock commit bit for this pin - Uint16 GPIO85:1; // 21 Configuration lock commit bit for this pin - Uint16 GPIO86:1; // 22 Configuration lock commit bit for this pin - Uint16 GPIO87:1; // 23 Configuration lock commit bit for this pin - Uint16 GPIO88:1; // 24 Configuration lock commit bit for this pin - Uint16 GPIO89:1; // 25 Configuration lock commit bit for this pin - Uint16 GPIO90:1; // 26 Configuration lock commit bit for this pin - Uint16 GPIO91:1; // 27 Configuration lock commit bit for this pin - Uint16 GPIO92:1; // 28 Configuration lock commit bit for this pin - Uint16 GPIO93:1; // 29 Configuration lock commit bit for this pin - Uint16 GPIO94:1; // 30 Configuration lock commit bit for this pin - Uint16 GPIO95:1; // 31 Configuration lock commit bit for this pin -}; - -union GPCCR_REG { - Uint32 all; - struct GPCCR_BITS bit; -}; - -struct GPDCTRL_BITS { // bits description - Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO96 to GPIO103 - Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO104 to GPIO111 - Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO112 to GPIO119 - Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO120 to GPIO127 -}; - -union GPDCTRL_REG { - Uint32 all; - struct GPDCTRL_BITS bit; -}; - -struct GPDQSEL1_BITS { // bits description - Uint16 GPIO96:2; // 1:0 Select input qualification type for GPIO96 - Uint16 GPIO97:2; // 3:2 Select input qualification type for GPIO97 - Uint16 GPIO98:2; // 5:4 Select input qualification type for GPIO98 - Uint16 GPIO99:2; // 7:6 Select input qualification type for GPIO99 - Uint16 GPIO100:2; // 9:8 Select input qualification type for GPIO100 - Uint16 GPIO101:2; // 11:10 Select input qualification type for GPIO101 - Uint16 GPIO102:2; // 13:12 Select input qualification type for GPIO102 - Uint16 GPIO103:2; // 15:14 Select input qualification type for GPIO103 - Uint16 GPIO104:2; // 17:16 Select input qualification type for GPIO104 - Uint16 GPIO105:2; // 19:18 Select input qualification type for GPIO105 - Uint16 GPIO106:2; // 21:20 Select input qualification type for GPIO106 - Uint16 GPIO107:2; // 23:22 Select input qualification type for GPIO107 - Uint16 GPIO108:2; // 25:24 Select input qualification type for GPIO108 - Uint16 GPIO109:2; // 27:26 Select input qualification type for GPIO109 - Uint16 GPIO110:2; // 29:28 Select input qualification type for GPIO110 - Uint16 GPIO111:2; // 31:30 Select input qualification type for GPIO111 -}; - -union GPDQSEL1_REG { - Uint32 all; - struct GPDQSEL1_BITS bit; -}; - -struct GPDQSEL2_BITS { // bits description - Uint16 GPIO112:2; // 1:0 Select input qualification type for GPIO112 - Uint16 GPIO113:2; // 3:2 Select input qualification type for GPIO113 - Uint16 GPIO114:2; // 5:4 Select input qualification type for GPIO114 - Uint16 GPIO115:2; // 7:6 Select input qualification type for GPIO115 - Uint16 GPIO116:2; // 9:8 Select input qualification type for GPIO116 - Uint16 GPIO117:2; // 11:10 Select input qualification type for GPIO117 - Uint16 GPIO118:2; // 13:12 Select input qualification type for GPIO118 - Uint16 GPIO119:2; // 15:14 Select input qualification type for GPIO119 - Uint16 GPIO120:2; // 17:16 Select input qualification type for GPIO120 - Uint16 GPIO121:2; // 19:18 Select input qualification type for GPIO121 - Uint16 GPIO122:2; // 21:20 Select input qualification type for GPIO122 - Uint16 GPIO123:2; // 23:22 Select input qualification type for GPIO123 - Uint16 GPIO124:2; // 25:24 Select input qualification type for GPIO124 - Uint16 GPIO125:2; // 27:26 Select input qualification type for GPIO125 - Uint16 GPIO126:2; // 29:28 Select input qualification type for GPIO126 - Uint16 GPIO127:2; // 31:30 Select input qualification type for GPIO127 -}; - -union GPDQSEL2_REG { - Uint32 all; - struct GPDQSEL2_BITS bit; -}; - -struct GPDMUX1_BITS { // bits description - Uint16 GPIO96:2; // 1:0 Defines pin-muxing selection for GPIO96 - Uint16 GPIO97:2; // 3:2 Defines pin-muxing selection for GPIO97 - Uint16 GPIO98:2; // 5:4 Defines pin-muxing selection for GPIO98 - Uint16 GPIO99:2; // 7:6 Defines pin-muxing selection for GPIO99 - Uint16 GPIO100:2; // 9:8 Defines pin-muxing selection for GPIO100 - Uint16 GPIO101:2; // 11:10 Defines pin-muxing selection for GPIO101 - Uint16 GPIO102:2; // 13:12 Defines pin-muxing selection for GPIO102 - Uint16 GPIO103:2; // 15:14 Defines pin-muxing selection for GPIO103 - Uint16 GPIO104:2; // 17:16 Defines pin-muxing selection for GPIO104 - Uint16 GPIO105:2; // 19:18 Defines pin-muxing selection for GPIO105 - Uint16 GPIO106:2; // 21:20 Defines pin-muxing selection for GPIO106 - Uint16 GPIO107:2; // 23:22 Defines pin-muxing selection for GPIO107 - Uint16 GPIO108:2; // 25:24 Defines pin-muxing selection for GPIO108 - Uint16 GPIO109:2; // 27:26 Defines pin-muxing selection for GPIO109 - Uint16 GPIO110:2; // 29:28 Defines pin-muxing selection for GPIO110 - Uint16 GPIO111:2; // 31:30 Defines pin-muxing selection for GPIO111 -}; - -union GPDMUX1_REG { - Uint32 all; - struct GPDMUX1_BITS bit; -}; - -struct GPDMUX2_BITS { // bits description - Uint16 GPIO112:2; // 1:0 Defines pin-muxing selection for GPIO112 - Uint16 GPIO113:2; // 3:2 Defines pin-muxing selection for GPIO113 - Uint16 GPIO114:2; // 5:4 Defines pin-muxing selection for GPIO114 - Uint16 GPIO115:2; // 7:6 Defines pin-muxing selection for GPIO115 - Uint16 GPIO116:2; // 9:8 Defines pin-muxing selection for GPIO116 - Uint16 GPIO117:2; // 11:10 Defines pin-muxing selection for GPIO117 - Uint16 GPIO118:2; // 13:12 Defines pin-muxing selection for GPIO118 - Uint16 GPIO119:2; // 15:14 Defines pin-muxing selection for GPIO119 - Uint16 GPIO120:2; // 17:16 Defines pin-muxing selection for GPIO120 - Uint16 GPIO121:2; // 19:18 Defines pin-muxing selection for GPIO121 - Uint16 GPIO122:2; // 21:20 Defines pin-muxing selection for GPIO122 - Uint16 GPIO123:2; // 23:22 Defines pin-muxing selection for GPIO123 - Uint16 GPIO124:2; // 25:24 Defines pin-muxing selection for GPIO124 - Uint16 GPIO125:2; // 27:26 Defines pin-muxing selection for GPIO125 - Uint16 GPIO126:2; // 29:28 Defines pin-muxing selection for GPIO126 - Uint16 GPIO127:2; // 31:30 Defines pin-muxing selection for GPIO127 -}; - -union GPDMUX2_REG { - Uint32 all; - struct GPDMUX2_BITS bit; -}; - -struct GPDDIR_BITS { // bits description - Uint16 GPIO96:1; // 0 Defines direction for this pin in GPIO mode - Uint16 GPIO97:1; // 1 Defines direction for this pin in GPIO mode - Uint16 GPIO98:1; // 2 Defines direction for this pin in GPIO mode - Uint16 GPIO99:1; // 3 Defines direction for this pin in GPIO mode - Uint16 GPIO100:1; // 4 Defines direction for this pin in GPIO mode - Uint16 GPIO101:1; // 5 Defines direction for this pin in GPIO mode - Uint16 GPIO102:1; // 6 Defines direction for this pin in GPIO mode - Uint16 GPIO103:1; // 7 Defines direction for this pin in GPIO mode - Uint16 GPIO104:1; // 8 Defines direction for this pin in GPIO mode - Uint16 GPIO105:1; // 9 Defines direction for this pin in GPIO mode - Uint16 GPIO106:1; // 10 Defines direction for this pin in GPIO mode - Uint16 GPIO107:1; // 11 Defines direction for this pin in GPIO mode - Uint16 GPIO108:1; // 12 Defines direction for this pin in GPIO mode - Uint16 GPIO109:1; // 13 Defines direction for this pin in GPIO mode - Uint16 GPIO110:1; // 14 Defines direction for this pin in GPIO mode - Uint16 GPIO111:1; // 15 Defines direction for this pin in GPIO mode - Uint16 GPIO112:1; // 16 Defines direction for this pin in GPIO mode - Uint16 GPIO113:1; // 17 Defines direction for this pin in GPIO mode - Uint16 GPIO114:1; // 18 Defines direction for this pin in GPIO mode - Uint16 GPIO115:1; // 19 Defines direction for this pin in GPIO mode - Uint16 GPIO116:1; // 20 Defines direction for this pin in GPIO mode - Uint16 GPIO117:1; // 21 Defines direction for this pin in GPIO mode - Uint16 GPIO118:1; // 22 Defines direction for this pin in GPIO mode - Uint16 GPIO119:1; // 23 Defines direction for this pin in GPIO mode - Uint16 GPIO120:1; // 24 Defines direction for this pin in GPIO mode - Uint16 GPIO121:1; // 25 Defines direction for this pin in GPIO mode - Uint16 GPIO122:1; // 26 Defines direction for this pin in GPIO mode - Uint16 GPIO123:1; // 27 Defines direction for this pin in GPIO mode - Uint16 GPIO124:1; // 28 Defines direction for this pin in GPIO mode - Uint16 GPIO125:1; // 29 Defines direction for this pin in GPIO mode - Uint16 GPIO126:1; // 30 Defines direction for this pin in GPIO mode - Uint16 GPIO127:1; // 31 Defines direction for this pin in GPIO mode -}; - -union GPDDIR_REG { - Uint32 all; - struct GPDDIR_BITS bit; -}; - -struct GPDPUD_BITS { // bits description - Uint16 GPIO96:1; // 0 Pull-Up Disable control for this pin - Uint16 GPIO97:1; // 1 Pull-Up Disable control for this pin - Uint16 GPIO98:1; // 2 Pull-Up Disable control for this pin - Uint16 GPIO99:1; // 3 Pull-Up Disable control for this pin - Uint16 GPIO100:1; // 4 Pull-Up Disable control for this pin - Uint16 GPIO101:1; // 5 Pull-Up Disable control for this pin - Uint16 GPIO102:1; // 6 Pull-Up Disable control for this pin - Uint16 GPIO103:1; // 7 Pull-Up Disable control for this pin - Uint16 GPIO104:1; // 8 Pull-Up Disable control for this pin - Uint16 GPIO105:1; // 9 Pull-Up Disable control for this pin - Uint16 GPIO106:1; // 10 Pull-Up Disable control for this pin - Uint16 GPIO107:1; // 11 Pull-Up Disable control for this pin - Uint16 GPIO108:1; // 12 Pull-Up Disable control for this pin - Uint16 GPIO109:1; // 13 Pull-Up Disable control for this pin - Uint16 GPIO110:1; // 14 Pull-Up Disable control for this pin - Uint16 GPIO111:1; // 15 Pull-Up Disable control for this pin - Uint16 GPIO112:1; // 16 Pull-Up Disable control for this pin - Uint16 GPIO113:1; // 17 Pull-Up Disable control for this pin - Uint16 GPIO114:1; // 18 Pull-Up Disable control for this pin - Uint16 GPIO115:1; // 19 Pull-Up Disable control for this pin - Uint16 GPIO116:1; // 20 Pull-Up Disable control for this pin - Uint16 GPIO117:1; // 21 Pull-Up Disable control for this pin - Uint16 GPIO118:1; // 22 Pull-Up Disable control for this pin - Uint16 GPIO119:1; // 23 Pull-Up Disable control for this pin - Uint16 GPIO120:1; // 24 Pull-Up Disable control for this pin - Uint16 GPIO121:1; // 25 Pull-Up Disable control for this pin - Uint16 GPIO122:1; // 26 Pull-Up Disable control for this pin - Uint16 GPIO123:1; // 27 Pull-Up Disable control for this pin - Uint16 GPIO124:1; // 28 Pull-Up Disable control for this pin - Uint16 GPIO125:1; // 29 Pull-Up Disable control for this pin - Uint16 GPIO126:1; // 30 Pull-Up Disable control for this pin - Uint16 GPIO127:1; // 31 Pull-Up Disable control for this pin -}; - -union GPDPUD_REG { - Uint32 all; - struct GPDPUD_BITS bit; -}; - -struct GPDINV_BITS { // bits description - Uint16 GPIO96:1; // 0 Input inversion control for this pin - Uint16 GPIO97:1; // 1 Input inversion control for this pin - Uint16 GPIO98:1; // 2 Input inversion control for this pin - Uint16 GPIO99:1; // 3 Input inversion control for this pin - Uint16 GPIO100:1; // 4 Input inversion control for this pin - Uint16 GPIO101:1; // 5 Input inversion control for this pin - Uint16 GPIO102:1; // 6 Input inversion control for this pin - Uint16 GPIO103:1; // 7 Input inversion control for this pin - Uint16 GPIO104:1; // 8 Input inversion control for this pin - Uint16 GPIO105:1; // 9 Input inversion control for this pin - Uint16 GPIO106:1; // 10 Input inversion control for this pin - Uint16 GPIO107:1; // 11 Input inversion control for this pin - Uint16 GPIO108:1; // 12 Input inversion control for this pin - Uint16 GPIO109:1; // 13 Input inversion control for this pin - Uint16 GPIO110:1; // 14 Input inversion control for this pin - Uint16 GPIO111:1; // 15 Input inversion control for this pin - Uint16 GPIO112:1; // 16 Input inversion control for this pin - Uint16 GPIO113:1; // 17 Input inversion control for this pin - Uint16 GPIO114:1; // 18 Input inversion control for this pin - Uint16 GPIO115:1; // 19 Input inversion control for this pin - Uint16 GPIO116:1; // 20 Input inversion control for this pin - Uint16 GPIO117:1; // 21 Input inversion control for this pin - Uint16 GPIO118:1; // 22 Input inversion control for this pin - Uint16 GPIO119:1; // 23 Input inversion control for this pin - Uint16 GPIO120:1; // 24 Input inversion control for this pin - Uint16 GPIO121:1; // 25 Input inversion control for this pin - Uint16 GPIO122:1; // 26 Input inversion control for this pin - Uint16 GPIO123:1; // 27 Input inversion control for this pin - Uint16 GPIO124:1; // 28 Input inversion control for this pin - Uint16 GPIO125:1; // 29 Input inversion control for this pin - Uint16 GPIO126:1; // 30 Input inversion control for this pin - Uint16 GPIO127:1; // 31 Input inversion control for this pin -}; - -union GPDINV_REG { - Uint32 all; - struct GPDINV_BITS bit; -}; - -struct GPDODR_BITS { // bits description - Uint16 GPIO96:1; // 0 Outpout Open-Drain control for this pin - Uint16 GPIO97:1; // 1 Outpout Open-Drain control for this pin - Uint16 GPIO98:1; // 2 Outpout Open-Drain control for this pin - Uint16 GPIO99:1; // 3 Outpout Open-Drain control for this pin - Uint16 GPIO100:1; // 4 Outpout Open-Drain control for this pin - Uint16 GPIO101:1; // 5 Outpout Open-Drain control for this pin - Uint16 GPIO102:1; // 6 Outpout Open-Drain control for this pin - Uint16 GPIO103:1; // 7 Outpout Open-Drain control for this pin - Uint16 GPIO104:1; // 8 Outpout Open-Drain control for this pin - Uint16 GPIO105:1; // 9 Outpout Open-Drain control for this pin - Uint16 GPIO106:1; // 10 Outpout Open-Drain control for this pin - Uint16 GPIO107:1; // 11 Outpout Open-Drain control for this pin - Uint16 GPIO108:1; // 12 Outpout Open-Drain control for this pin - Uint16 GPIO109:1; // 13 Outpout Open-Drain control for this pin - Uint16 GPIO110:1; // 14 Outpout Open-Drain control for this pin - Uint16 GPIO111:1; // 15 Outpout Open-Drain control for this pin - Uint16 GPIO112:1; // 16 Outpout Open-Drain control for this pin - Uint16 GPIO113:1; // 17 Outpout Open-Drain control for this pin - Uint16 GPIO114:1; // 18 Outpout Open-Drain control for this pin - Uint16 GPIO115:1; // 19 Outpout Open-Drain control for this pin - Uint16 GPIO116:1; // 20 Outpout Open-Drain control for this pin - Uint16 GPIO117:1; // 21 Outpout Open-Drain control for this pin - Uint16 GPIO118:1; // 22 Outpout Open-Drain control for this pin - Uint16 GPIO119:1; // 23 Outpout Open-Drain control for this pin - Uint16 GPIO120:1; // 24 Outpout Open-Drain control for this pin - Uint16 GPIO121:1; // 25 Outpout Open-Drain control for this pin - Uint16 GPIO122:1; // 26 Outpout Open-Drain control for this pin - Uint16 GPIO123:1; // 27 Outpout Open-Drain control for this pin - Uint16 GPIO124:1; // 28 Outpout Open-Drain control for this pin - Uint16 GPIO125:1; // 29 Outpout Open-Drain control for this pin - Uint16 GPIO126:1; // 30 Outpout Open-Drain control for this pin - Uint16 GPIO127:1; // 31 Outpout Open-Drain control for this pin -}; - -union GPDODR_REG { - Uint32 all; - struct GPDODR_BITS bit; -}; - -struct GPDGMUX1_BITS { // bits description - Uint16 GPIO96:2; // 1:0 Defines pin-muxing selection for GPIO96 - Uint16 GPIO97:2; // 3:2 Defines pin-muxing selection for GPIO97 - Uint16 GPIO98:2; // 5:4 Defines pin-muxing selection for GPIO98 - Uint16 GPIO99:2; // 7:6 Defines pin-muxing selection for GPIO99 - Uint16 GPIO100:2; // 9:8 Defines pin-muxing selection for GPIO100 - Uint16 GPIO101:2; // 11:10 Defines pin-muxing selection for GPIO101 - Uint16 GPIO102:2; // 13:12 Defines pin-muxing selection for GPIO102 - Uint16 GPIO103:2; // 15:14 Defines pin-muxing selection for GPIO103 - Uint16 GPIO104:2; // 17:16 Defines pin-muxing selection for GPIO104 - Uint16 GPIO105:2; // 19:18 Defines pin-muxing selection for GPIO105 - Uint16 GPIO106:2; // 21:20 Defines pin-muxing selection for GPIO106 - Uint16 GPIO107:2; // 23:22 Defines pin-muxing selection for GPIO107 - Uint16 GPIO108:2; // 25:24 Defines pin-muxing selection for GPIO108 - Uint16 GPIO109:2; // 27:26 Defines pin-muxing selection for GPIO109 - Uint16 GPIO110:2; // 29:28 Defines pin-muxing selection for GPIO110 - Uint16 GPIO111:2; // 31:30 Defines pin-muxing selection for GPIO111 -}; - -union GPDGMUX1_REG { - Uint32 all; - struct GPDGMUX1_BITS bit; -}; - -struct GPDGMUX2_BITS { // bits description - Uint16 GPIO112:2; // 1:0 Defines pin-muxing selection for GPIO112 - Uint16 GPIO113:2; // 3:2 Defines pin-muxing selection for GPIO113 - Uint16 GPIO114:2; // 5:4 Defines pin-muxing selection for GPIO114 - Uint16 GPIO115:2; // 7:6 Defines pin-muxing selection for GPIO115 - Uint16 GPIO116:2; // 9:8 Defines pin-muxing selection for GPIO116 - Uint16 GPIO117:2; // 11:10 Defines pin-muxing selection for GPIO117 - Uint16 GPIO118:2; // 13:12 Defines pin-muxing selection for GPIO118 - Uint16 GPIO119:2; // 15:14 Defines pin-muxing selection for GPIO119 - Uint16 GPIO120:2; // 17:16 Defines pin-muxing selection for GPIO120 - Uint16 GPIO121:2; // 19:18 Defines pin-muxing selection for GPIO121 - Uint16 GPIO122:2; // 21:20 Defines pin-muxing selection for GPIO122 - Uint16 GPIO123:2; // 23:22 Defines pin-muxing selection for GPIO123 - Uint16 GPIO124:2; // 25:24 Defines pin-muxing selection for GPIO124 - Uint16 GPIO125:2; // 27:26 Defines pin-muxing selection for GPIO125 - Uint16 GPIO126:2; // 29:28 Defines pin-muxing selection for GPIO126 - Uint16 GPIO127:2; // 31:30 Defines pin-muxing selection for GPIO127 -}; - -union GPDGMUX2_REG { - Uint32 all; - struct GPDGMUX2_BITS bit; -}; - -struct GPDCSEL1_BITS { // bits description - Uint16 GPIO96:4; // 3:0 GPIO96 Master CPU Select - Uint16 GPIO97:4; // 7:4 GPIO97 Master CPU Select - Uint16 GPIO98:4; // 11:8 GPIO98 Master CPU Select - Uint16 GPIO99:4; // 15:12 GPIO99 Master CPU Select - Uint16 GPIO100:4; // 19:16 GPIO100 Master CPU Select - Uint16 GPIO101:4; // 23:20 GPIO101 Master CPU Select - Uint16 GPIO102:4; // 27:24 GPIO102 Master CPU Select - Uint16 GPIO103:4; // 31:28 GPIO103 Master CPU Select -}; - -union GPDCSEL1_REG { - Uint32 all; - struct GPDCSEL1_BITS bit; -}; - -struct GPDCSEL2_BITS { // bits description - Uint16 GPIO104:4; // 3:0 GPIO104 Master CPU Select - Uint16 GPIO105:4; // 7:4 GPIO105 Master CPU Select - Uint16 GPIO106:4; // 11:8 GPIO106 Master CPU Select - Uint16 GPIO107:4; // 15:12 GPIO107 Master CPU Select - Uint16 GPIO108:4; // 19:16 GPIO108 Master CPU Select - Uint16 GPIO109:4; // 23:20 GPIO109 Master CPU Select - Uint16 GPIO110:4; // 27:24 GPIO110 Master CPU Select - Uint16 GPIO111:4; // 31:28 GPIO111 Master CPU Select -}; - -union GPDCSEL2_REG { - Uint32 all; - struct GPDCSEL2_BITS bit; -}; - -struct GPDCSEL3_BITS { // bits description - Uint16 GPIO112:4; // 3:0 GPIO112 Master CPU Select - Uint16 GPIO113:4; // 7:4 GPIO113 Master CPU Select - Uint16 GPIO114:4; // 11:8 GPIO114 Master CPU Select - Uint16 GPIO115:4; // 15:12 GPIO115 Master CPU Select - Uint16 GPIO116:4; // 19:16 GPIO116 Master CPU Select - Uint16 GPIO117:4; // 23:20 GPIO117 Master CPU Select - Uint16 GPIO118:4; // 27:24 GPIO118 Master CPU Select - Uint16 GPIO119:4; // 31:28 GPIO119 Master CPU Select -}; - -union GPDCSEL3_REG { - Uint32 all; - struct GPDCSEL3_BITS bit; -}; - -struct GPDCSEL4_BITS { // bits description - Uint16 GPIO120:4; // 3:0 GPIO120 Master CPU Select - Uint16 GPIO121:4; // 7:4 GPIO121 Master CPU Select - Uint16 GPIO122:4; // 11:8 GPIO122 Master CPU Select - Uint16 GPIO123:4; // 15:12 GPIO123 Master CPU Select - Uint16 GPIO124:4; // 19:16 GPIO124 Master CPU Select - Uint16 GPIO125:4; // 23:20 GPIO125 Master CPU Select - Uint16 GPIO126:4; // 27:24 GPIO126 Master CPU Select - Uint16 GPIO127:4; // 31:28 GPIO127 Master CPU Select -}; - -union GPDCSEL4_REG { - Uint32 all; - struct GPDCSEL4_BITS bit; -}; - -struct GPDLOCK_BITS { // bits description - Uint16 GPIO96:1; // 0 Configuration Lock bit for this pin - Uint16 GPIO97:1; // 1 Configuration Lock bit for this pin - Uint16 GPIO98:1; // 2 Configuration Lock bit for this pin - Uint16 GPIO99:1; // 3 Configuration Lock bit for this pin - Uint16 GPIO100:1; // 4 Configuration Lock bit for this pin - Uint16 GPIO101:1; // 5 Configuration Lock bit for this pin - Uint16 GPIO102:1; // 6 Configuration Lock bit for this pin - Uint16 GPIO103:1; // 7 Configuration Lock bit for this pin - Uint16 GPIO104:1; // 8 Configuration Lock bit for this pin - Uint16 GPIO105:1; // 9 Configuration Lock bit for this pin - Uint16 GPIO106:1; // 10 Configuration Lock bit for this pin - Uint16 GPIO107:1; // 11 Configuration Lock bit for this pin - Uint16 GPIO108:1; // 12 Configuration Lock bit for this pin - Uint16 GPIO109:1; // 13 Configuration Lock bit for this pin - Uint16 GPIO110:1; // 14 Configuration Lock bit for this pin - Uint16 GPIO111:1; // 15 Configuration Lock bit for this pin - Uint16 GPIO112:1; // 16 Configuration Lock bit for this pin - Uint16 GPIO113:1; // 17 Configuration Lock bit for this pin - Uint16 GPIO114:1; // 18 Configuration Lock bit for this pin - Uint16 GPIO115:1; // 19 Configuration Lock bit for this pin - Uint16 GPIO116:1; // 20 Configuration Lock bit for this pin - Uint16 GPIO117:1; // 21 Configuration Lock bit for this pin - Uint16 GPIO118:1; // 22 Configuration Lock bit for this pin - Uint16 GPIO119:1; // 23 Configuration Lock bit for this pin - Uint16 GPIO120:1; // 24 Configuration Lock bit for this pin - Uint16 GPIO121:1; // 25 Configuration Lock bit for this pin - Uint16 GPIO122:1; // 26 Configuration Lock bit for this pin - Uint16 GPIO123:1; // 27 Configuration Lock bit for this pin - Uint16 GPIO124:1; // 28 Configuration Lock bit for this pin - Uint16 GPIO125:1; // 29 Configuration Lock bit for this pin - Uint16 GPIO126:1; // 30 Configuration Lock bit for this pin - Uint16 GPIO127:1; // 31 Configuration Lock bit for this pin -}; - -union GPDLOCK_REG { - Uint32 all; - struct GPDLOCK_BITS bit; -}; - -struct GPDCR_BITS { // bits description - Uint16 GPIO96:1; // 0 Configuration lock commit bit for this pin - Uint16 GPIO97:1; // 1 Configuration lock commit bit for this pin - Uint16 GPIO98:1; // 2 Configuration lock commit bit for this pin - Uint16 GPIO99:1; // 3 Configuration lock commit bit for this pin - Uint16 GPIO100:1; // 4 Configuration lock commit bit for this pin - Uint16 GPIO101:1; // 5 Configuration lock commit bit for this pin - Uint16 GPIO102:1; // 6 Configuration lock commit bit for this pin - Uint16 GPIO103:1; // 7 Configuration lock commit bit for this pin - Uint16 GPIO104:1; // 8 Configuration lock commit bit for this pin - Uint16 GPIO105:1; // 9 Configuration lock commit bit for this pin - Uint16 GPIO106:1; // 10 Configuration lock commit bit for this pin - Uint16 GPIO107:1; // 11 Configuration lock commit bit for this pin - Uint16 GPIO108:1; // 12 Configuration lock commit bit for this pin - Uint16 GPIO109:1; // 13 Configuration lock commit bit for this pin - Uint16 GPIO110:1; // 14 Configuration lock commit bit for this pin - Uint16 GPIO111:1; // 15 Configuration lock commit bit for this pin - Uint16 GPIO112:1; // 16 Configuration lock commit bit for this pin - Uint16 GPIO113:1; // 17 Configuration lock commit bit for this pin - Uint16 GPIO114:1; // 18 Configuration lock commit bit for this pin - Uint16 GPIO115:1; // 19 Configuration lock commit bit for this pin - Uint16 GPIO116:1; // 20 Configuration lock commit bit for this pin - Uint16 GPIO117:1; // 21 Configuration lock commit bit for this pin - Uint16 GPIO118:1; // 22 Configuration lock commit bit for this pin - Uint16 GPIO119:1; // 23 Configuration lock commit bit for this pin - Uint16 GPIO120:1; // 24 Configuration lock commit bit for this pin - Uint16 GPIO121:1; // 25 Configuration lock commit bit for this pin - Uint16 GPIO122:1; // 26 Configuration lock commit bit for this pin - Uint16 GPIO123:1; // 27 Configuration lock commit bit for this pin - Uint16 GPIO124:1; // 28 Configuration lock commit bit for this pin - Uint16 GPIO125:1; // 29 Configuration lock commit bit for this pin - Uint16 GPIO126:1; // 30 Configuration lock commit bit for this pin - Uint16 GPIO127:1; // 31 Configuration lock commit bit for this pin -}; - -union GPDCR_REG { - Uint32 all; - struct GPDCR_BITS bit; -}; - -struct GPECTRL_BITS { // bits description - Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO128 to GPIO135 - Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO136 to GPIO143 - Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO144 to GPIO151 - Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO152 to GPIO159 -}; - -union GPECTRL_REG { - Uint32 all; - struct GPECTRL_BITS bit; -}; - -struct GPEQSEL1_BITS { // bits description - Uint16 GPIO128:2; // 1:0 Select input qualification type for GPIO128 - Uint16 GPIO129:2; // 3:2 Select input qualification type for GPIO129 - Uint16 GPIO130:2; // 5:4 Select input qualification type for GPIO130 - Uint16 GPIO131:2; // 7:6 Select input qualification type for GPIO131 - Uint16 GPIO132:2; // 9:8 Select input qualification type for GPIO132 - Uint16 GPIO133:2; // 11:10 Select input qualification type for GPIO133 - Uint16 GPIO134:2; // 13:12 Select input qualification type for GPIO134 - Uint16 GPIO135:2; // 15:14 Select input qualification type for GPIO135 - Uint16 GPIO136:2; // 17:16 Select input qualification type for GPIO136 - Uint16 GPIO137:2; // 19:18 Select input qualification type for GPIO137 - Uint16 GPIO138:2; // 21:20 Select input qualification type for GPIO138 - Uint16 GPIO139:2; // 23:22 Select input qualification type for GPIO139 - Uint16 GPIO140:2; // 25:24 Select input qualification type for GPIO140 - Uint16 GPIO141:2; // 27:26 Select input qualification type for GPIO141 - Uint16 GPIO142:2; // 29:28 Select input qualification type for GPIO142 - Uint16 GPIO143:2; // 31:30 Select input qualification type for GPIO143 -}; - -union GPEQSEL1_REG { - Uint32 all; - struct GPEQSEL1_BITS bit; -}; - -struct GPEQSEL2_BITS { // bits description - Uint16 GPIO144:2; // 1:0 Select input qualification type for GPIO144 - Uint16 GPIO145:2; // 3:2 Select input qualification type for GPIO145 - Uint16 GPIO146:2; // 5:4 Select input qualification type for GPIO146 - Uint16 GPIO147:2; // 7:6 Select input qualification type for GPIO147 - Uint16 GPIO148:2; // 9:8 Select input qualification type for GPIO148 - Uint16 GPIO149:2; // 11:10 Select input qualification type for GPIO149 - Uint16 GPIO150:2; // 13:12 Select input qualification type for GPIO150 - Uint16 GPIO151:2; // 15:14 Select input qualification type for GPIO151 - Uint16 GPIO152:2; // 17:16 Select input qualification type for GPIO152 - Uint16 GPIO153:2; // 19:18 Select input qualification type for GPIO153 - Uint16 GPIO154:2; // 21:20 Select input qualification type for GPIO154 - Uint16 GPIO155:2; // 23:22 Select input qualification type for GPIO155 - Uint16 GPIO156:2; // 25:24 Select input qualification type for GPIO156 - Uint16 GPIO157:2; // 27:26 Select input qualification type for GPIO157 - Uint16 GPIO158:2; // 29:28 Select input qualification type for GPIO158 - Uint16 GPIO159:2; // 31:30 Select input qualification type for GPIO159 -}; - -union GPEQSEL2_REG { - Uint32 all; - struct GPEQSEL2_BITS bit; -}; - -struct GPEMUX1_BITS { // bits description - Uint16 GPIO128:2; // 1:0 Defines pin-muxing selection for GPIO128 - Uint16 GPIO129:2; // 3:2 Defines pin-muxing selection for GPIO129 - Uint16 GPIO130:2; // 5:4 Defines pin-muxing selection for GPIO130 - Uint16 GPIO131:2; // 7:6 Defines pin-muxing selection for GPIO131 - Uint16 GPIO132:2; // 9:8 Defines pin-muxing selection for GPIO132 - Uint16 GPIO133:2; // 11:10 Defines pin-muxing selection for GPIO133 - Uint16 GPIO134:2; // 13:12 Defines pin-muxing selection for GPIO134 - Uint16 GPIO135:2; // 15:14 Defines pin-muxing selection for GPIO135 - Uint16 GPIO136:2; // 17:16 Defines pin-muxing selection for GPIO136 - Uint16 GPIO137:2; // 19:18 Defines pin-muxing selection for GPIO137 - Uint16 GPIO138:2; // 21:20 Defines pin-muxing selection for GPIO138 - Uint16 GPIO139:2; // 23:22 Defines pin-muxing selection for GPIO139 - Uint16 GPIO140:2; // 25:24 Defines pin-muxing selection for GPIO140 - Uint16 GPIO141:2; // 27:26 Defines pin-muxing selection for GPIO141 - Uint16 GPIO142:2; // 29:28 Defines pin-muxing selection for GPIO142 - Uint16 GPIO143:2; // 31:30 Defines pin-muxing selection for GPIO143 -}; - -union GPEMUX1_REG { - Uint32 all; - struct GPEMUX1_BITS bit; -}; - -struct GPEMUX2_BITS { // bits description - Uint16 GPIO144:2; // 1:0 Defines pin-muxing selection for GPIO144 - Uint16 GPIO145:2; // 3:2 Defines pin-muxing selection for GPIO145 - Uint16 GPIO146:2; // 5:4 Defines pin-muxing selection for GPIO146 - Uint16 GPIO147:2; // 7:6 Defines pin-muxing selection for GPIO147 - Uint16 GPIO148:2; // 9:8 Defines pin-muxing selection for GPIO148 - Uint16 GPIO149:2; // 11:10 Defines pin-muxing selection for GPIO149 - Uint16 GPIO150:2; // 13:12 Defines pin-muxing selection for GPIO150 - Uint16 GPIO151:2; // 15:14 Defines pin-muxing selection for GPIO151 - Uint16 GPIO152:2; // 17:16 Defines pin-muxing selection for GPIO152 - Uint16 GPIO153:2; // 19:18 Defines pin-muxing selection for GPIO153 - Uint16 GPIO154:2; // 21:20 Defines pin-muxing selection for GPIO154 - Uint16 GPIO155:2; // 23:22 Defines pin-muxing selection for GPIO155 - Uint16 GPIO156:2; // 25:24 Defines pin-muxing selection for GPIO156 - Uint16 GPIO157:2; // 27:26 Defines pin-muxing selection for GPIO157 - Uint16 GPIO158:2; // 29:28 Defines pin-muxing selection for GPIO158 - Uint16 GPIO159:2; // 31:30 Defines pin-muxing selection for GPIO159 -}; - -union GPEMUX2_REG { - Uint32 all; - struct GPEMUX2_BITS bit; -}; - -struct GPEDIR_BITS { // bits description - Uint16 GPIO128:1; // 0 Defines direction for this pin in GPIO mode - Uint16 GPIO129:1; // 1 Defines direction for this pin in GPIO mode - Uint16 GPIO130:1; // 2 Defines direction for this pin in GPIO mode - Uint16 GPIO131:1; // 3 Defines direction for this pin in GPIO mode - Uint16 GPIO132:1; // 4 Defines direction for this pin in GPIO mode - Uint16 GPIO133:1; // 5 Defines direction for this pin in GPIO mode - Uint16 GPIO134:1; // 6 Defines direction for this pin in GPIO mode - Uint16 GPIO135:1; // 7 Defines direction for this pin in GPIO mode - Uint16 GPIO136:1; // 8 Defines direction for this pin in GPIO mode - Uint16 GPIO137:1; // 9 Defines direction for this pin in GPIO mode - Uint16 GPIO138:1; // 10 Defines direction for this pin in GPIO mode - Uint16 GPIO139:1; // 11 Defines direction for this pin in GPIO mode - Uint16 GPIO140:1; // 12 Defines direction for this pin in GPIO mode - Uint16 GPIO141:1; // 13 Defines direction for this pin in GPIO mode - Uint16 GPIO142:1; // 14 Defines direction for this pin in GPIO mode - Uint16 GPIO143:1; // 15 Defines direction for this pin in GPIO mode - Uint16 GPIO144:1; // 16 Defines direction for this pin in GPIO mode - Uint16 GPIO145:1; // 17 Defines direction for this pin in GPIO mode - Uint16 GPIO146:1; // 18 Defines direction for this pin in GPIO mode - Uint16 GPIO147:1; // 19 Defines direction for this pin in GPIO mode - Uint16 GPIO148:1; // 20 Defines direction for this pin in GPIO mode - Uint16 GPIO149:1; // 21 Defines direction for this pin in GPIO mode - Uint16 GPIO150:1; // 22 Defines direction for this pin in GPIO mode - Uint16 GPIO151:1; // 23 Defines direction for this pin in GPIO mode - Uint16 GPIO152:1; // 24 Defines direction for this pin in GPIO mode - Uint16 GPIO153:1; // 25 Defines direction for this pin in GPIO mode - Uint16 GPIO154:1; // 26 Defines direction for this pin in GPIO mode - Uint16 GPIO155:1; // 27 Defines direction for this pin in GPIO mode - Uint16 GPIO156:1; // 28 Defines direction for this pin in GPIO mode - Uint16 GPIO157:1; // 29 Defines direction for this pin in GPIO mode - Uint16 GPIO158:1; // 30 Defines direction for this pin in GPIO mode - Uint16 GPIO159:1; // 31 Defines direction for this pin in GPIO mode -}; - -union GPEDIR_REG { - Uint32 all; - struct GPEDIR_BITS bit; -}; - -struct GPEPUD_BITS { // bits description - Uint16 GPIO128:1; // 0 Pull-Up Disable control for this pin - Uint16 GPIO129:1; // 1 Pull-Up Disable control for this pin - Uint16 GPIO130:1; // 2 Pull-Up Disable control for this pin - Uint16 GPIO131:1; // 3 Pull-Up Disable control for this pin - Uint16 GPIO132:1; // 4 Pull-Up Disable control for this pin - Uint16 GPIO133:1; // 5 Pull-Up Disable control for this pin - Uint16 GPIO134:1; // 6 Pull-Up Disable control for this pin - Uint16 GPIO135:1; // 7 Pull-Up Disable control for this pin - Uint16 GPIO136:1; // 8 Pull-Up Disable control for this pin - Uint16 GPIO137:1; // 9 Pull-Up Disable control for this pin - Uint16 GPIO138:1; // 10 Pull-Up Disable control for this pin - Uint16 GPIO139:1; // 11 Pull-Up Disable control for this pin - Uint16 GPIO140:1; // 12 Pull-Up Disable control for this pin - Uint16 GPIO141:1; // 13 Pull-Up Disable control for this pin - Uint16 GPIO142:1; // 14 Pull-Up Disable control for this pin - Uint16 GPIO143:1; // 15 Pull-Up Disable control for this pin - Uint16 GPIO144:1; // 16 Pull-Up Disable control for this pin - Uint16 GPIO145:1; // 17 Pull-Up Disable control for this pin - Uint16 GPIO146:1; // 18 Pull-Up Disable control for this pin - Uint16 GPIO147:1; // 19 Pull-Up Disable control for this pin - Uint16 GPIO148:1; // 20 Pull-Up Disable control for this pin - Uint16 GPIO149:1; // 21 Pull-Up Disable control for this pin - Uint16 GPIO150:1; // 22 Pull-Up Disable control for this pin - Uint16 GPIO151:1; // 23 Pull-Up Disable control for this pin - Uint16 GPIO152:1; // 24 Pull-Up Disable control for this pin - Uint16 GPIO153:1; // 25 Pull-Up Disable control for this pin - Uint16 GPIO154:1; // 26 Pull-Up Disable control for this pin - Uint16 GPIO155:1; // 27 Pull-Up Disable control for this pin - Uint16 GPIO156:1; // 28 Pull-Up Disable control for this pin - Uint16 GPIO157:1; // 29 Pull-Up Disable control for this pin - Uint16 GPIO158:1; // 30 Pull-Up Disable control for this pin - Uint16 GPIO159:1; // 31 Pull-Up Disable control for this pin -}; - -union GPEPUD_REG { - Uint32 all; - struct GPEPUD_BITS bit; -}; - -struct GPEINV_BITS { // bits description - Uint16 GPIO128:1; // 0 Input inversion control for this pin - Uint16 GPIO129:1; // 1 Input inversion control for this pin - Uint16 GPIO130:1; // 2 Input inversion control for this pin - Uint16 GPIO131:1; // 3 Input inversion control for this pin - Uint16 GPIO132:1; // 4 Input inversion control for this pin - Uint16 GPIO133:1; // 5 Input inversion control for this pin - Uint16 GPIO134:1; // 6 Input inversion control for this pin - Uint16 GPIO135:1; // 7 Input inversion control for this pin - Uint16 GPIO136:1; // 8 Input inversion control for this pin - Uint16 GPIO137:1; // 9 Input inversion control for this pin - Uint16 GPIO138:1; // 10 Input inversion control for this pin - Uint16 GPIO139:1; // 11 Input inversion control for this pin - Uint16 GPIO140:1; // 12 Input inversion control for this pin - Uint16 GPIO141:1; // 13 Input inversion control for this pin - Uint16 GPIO142:1; // 14 Input inversion control for this pin - Uint16 GPIO143:1; // 15 Input inversion control for this pin - Uint16 GPIO144:1; // 16 Input inversion control for this pin - Uint16 GPIO145:1; // 17 Input inversion control for this pin - Uint16 GPIO146:1; // 18 Input inversion control for this pin - Uint16 GPIO147:1; // 19 Input inversion control for this pin - Uint16 GPIO148:1; // 20 Input inversion control for this pin - Uint16 GPIO149:1; // 21 Input inversion control for this pin - Uint16 GPIO150:1; // 22 Input inversion control for this pin - Uint16 GPIO151:1; // 23 Input inversion control for this pin - Uint16 GPIO152:1; // 24 Input inversion control for this pin - Uint16 GPIO153:1; // 25 Input inversion control for this pin - Uint16 GPIO154:1; // 26 Input inversion control for this pin - Uint16 GPIO155:1; // 27 Input inversion control for this pin - Uint16 GPIO156:1; // 28 Input inversion control for this pin - Uint16 GPIO157:1; // 29 Input inversion control for this pin - Uint16 GPIO158:1; // 30 Input inversion control for this pin - Uint16 GPIO159:1; // 31 Input inversion control for this pin -}; - -union GPEINV_REG { - Uint32 all; - struct GPEINV_BITS bit; -}; - -struct GPEODR_BITS { // bits description - Uint16 GPIO128:1; // 0 Outpout Open-Drain control for this pin - Uint16 GPIO129:1; // 1 Outpout Open-Drain control for this pin - Uint16 GPIO130:1; // 2 Outpout Open-Drain control for this pin - Uint16 GPIO131:1; // 3 Outpout Open-Drain control for this pin - Uint16 GPIO132:1; // 4 Outpout Open-Drain control for this pin - Uint16 GPIO133:1; // 5 Outpout Open-Drain control for this pin - Uint16 GPIO134:1; // 6 Outpout Open-Drain control for this pin - Uint16 GPIO135:1; // 7 Outpout Open-Drain control for this pin - Uint16 GPIO136:1; // 8 Outpout Open-Drain control for this pin - Uint16 GPIO137:1; // 9 Outpout Open-Drain control for this pin - Uint16 GPIO138:1; // 10 Outpout Open-Drain control for this pin - Uint16 GPIO139:1; // 11 Outpout Open-Drain control for this pin - Uint16 GPIO140:1; // 12 Outpout Open-Drain control for this pin - Uint16 GPIO141:1; // 13 Outpout Open-Drain control for this pin - Uint16 GPIO142:1; // 14 Outpout Open-Drain control for this pin - Uint16 GPIO143:1; // 15 Outpout Open-Drain control for this pin - Uint16 GPIO144:1; // 16 Outpout Open-Drain control for this pin - Uint16 GPIO145:1; // 17 Outpout Open-Drain control for this pin - Uint16 GPIO146:1; // 18 Outpout Open-Drain control for this pin - Uint16 GPIO147:1; // 19 Outpout Open-Drain control for this pin - Uint16 GPIO148:1; // 20 Outpout Open-Drain control for this pin - Uint16 GPIO149:1; // 21 Outpout Open-Drain control for this pin - Uint16 GPIO150:1; // 22 Outpout Open-Drain control for this pin - Uint16 GPIO151:1; // 23 Outpout Open-Drain control for this pin - Uint16 GPIO152:1; // 24 Outpout Open-Drain control for this pin - Uint16 GPIO153:1; // 25 Outpout Open-Drain control for this pin - Uint16 GPIO154:1; // 26 Outpout Open-Drain control for this pin - Uint16 GPIO155:1; // 27 Outpout Open-Drain control for this pin - Uint16 GPIO156:1; // 28 Outpout Open-Drain control for this pin - Uint16 GPIO157:1; // 29 Outpout Open-Drain control for this pin - Uint16 GPIO158:1; // 30 Outpout Open-Drain control for this pin - Uint16 GPIO159:1; // 31 Outpout Open-Drain control for this pin -}; - -union GPEODR_REG { - Uint32 all; - struct GPEODR_BITS bit; -}; - -struct GPEGMUX1_BITS { // bits description - Uint16 GPIO128:2; // 1:0 Defines pin-muxing selection for GPIO128 - Uint16 GPIO129:2; // 3:2 Defines pin-muxing selection for GPIO129 - Uint16 GPIO130:2; // 5:4 Defines pin-muxing selection for GPIO130 - Uint16 GPIO131:2; // 7:6 Defines pin-muxing selection for GPIO131 - Uint16 GPIO132:2; // 9:8 Defines pin-muxing selection for GPIO132 - Uint16 GPIO133:2; // 11:10 Defines pin-muxing selection for GPIO133 - Uint16 GPIO134:2; // 13:12 Defines pin-muxing selection for GPIO134 - Uint16 GPIO135:2; // 15:14 Defines pin-muxing selection for GPIO135 - Uint16 GPIO136:2; // 17:16 Defines pin-muxing selection for GPIO136 - Uint16 GPIO137:2; // 19:18 Defines pin-muxing selection for GPIO137 - Uint16 GPIO138:2; // 21:20 Defines pin-muxing selection for GPIO138 - Uint16 GPIO139:2; // 23:22 Defines pin-muxing selection for GPIO139 - Uint16 GPIO140:2; // 25:24 Defines pin-muxing selection for GPIO140 - Uint16 GPIO141:2; // 27:26 Defines pin-muxing selection for GPIO141 - Uint16 GPIO142:2; // 29:28 Defines pin-muxing selection for GPIO142 - Uint16 GPIO143:2; // 31:30 Defines pin-muxing selection for GPIO143 -}; - -union GPEGMUX1_REG { - Uint32 all; - struct GPEGMUX1_BITS bit; -}; - -struct GPEGMUX2_BITS { // bits description - Uint16 GPIO144:2; // 1:0 Defines pin-muxing selection for GPIO144 - Uint16 GPIO145:2; // 3:2 Defines pin-muxing selection for GPIO145 - Uint16 GPIO146:2; // 5:4 Defines pin-muxing selection for GPIO146 - Uint16 GPIO147:2; // 7:6 Defines pin-muxing selection for GPIO147 - Uint16 GPIO148:2; // 9:8 Defines pin-muxing selection for GPIO148 - Uint16 GPIO149:2; // 11:10 Defines pin-muxing selection for GPIO149 - Uint16 GPIO150:2; // 13:12 Defines pin-muxing selection for GPIO150 - Uint16 GPIO151:2; // 15:14 Defines pin-muxing selection for GPIO151 - Uint16 GPIO152:2; // 17:16 Defines pin-muxing selection for GPIO152 - Uint16 GPIO153:2; // 19:18 Defines pin-muxing selection for GPIO153 - Uint16 GPIO154:2; // 21:20 Defines pin-muxing selection for GPIO154 - Uint16 GPIO155:2; // 23:22 Defines pin-muxing selection for GPIO155 - Uint16 GPIO156:2; // 25:24 Defines pin-muxing selection for GPIO156 - Uint16 GPIO157:2; // 27:26 Defines pin-muxing selection for GPIO157 - Uint16 GPIO158:2; // 29:28 Defines pin-muxing selection for GPIO158 - Uint16 GPIO159:2; // 31:30 Defines pin-muxing selection for GPIO159 -}; - -union GPEGMUX2_REG { - Uint32 all; - struct GPEGMUX2_BITS bit; -}; - -struct GPECSEL1_BITS { // bits description - Uint16 GPIO128:4; // 3:0 GPIO128 Master CPU Select - Uint16 GPIO129:4; // 7:4 GPIO129 Master CPU Select - Uint16 GPIO130:4; // 11:8 GPIO130 Master CPU Select - Uint16 GPIO131:4; // 15:12 GPIO131 Master CPU Select - Uint16 GPIO132:4; // 19:16 GPIO132 Master CPU Select - Uint16 GPIO133:4; // 23:20 GPIO133 Master CPU Select - Uint16 GPIO134:4; // 27:24 GPIO134 Master CPU Select - Uint16 GPIO135:4; // 31:28 GPIO135 Master CPU Select -}; - -union GPECSEL1_REG { - Uint32 all; - struct GPECSEL1_BITS bit; -}; - -struct GPECSEL2_BITS { // bits description - Uint16 GPIO136:4; // 3:0 GPIO136 Master CPU Select - Uint16 GPIO137:4; // 7:4 GPIO137 Master CPU Select - Uint16 GPIO138:4; // 11:8 GPIO138 Master CPU Select - Uint16 GPIO139:4; // 15:12 GPIO139 Master CPU Select - Uint16 GPIO140:4; // 19:16 GPIO140 Master CPU Select - Uint16 GPIO141:4; // 23:20 GPIO141 Master CPU Select - Uint16 GPIO142:4; // 27:24 GPIO142 Master CPU Select - Uint16 GPIO143:4; // 31:28 GPIO143 Master CPU Select -}; - -union GPECSEL2_REG { - Uint32 all; - struct GPECSEL2_BITS bit; -}; - -struct GPECSEL3_BITS { // bits description - Uint16 GPIO144:4; // 3:0 GPIO144 Master CPU Select - Uint16 GPIO145:4; // 7:4 GPIO145 Master CPU Select - Uint16 GPIO146:4; // 11:8 GPIO146 Master CPU Select - Uint16 GPIO147:4; // 15:12 GPIO147 Master CPU Select - Uint16 GPIO148:4; // 19:16 GPIO148 Master CPU Select - Uint16 GPIO149:4; // 23:20 GPIO149 Master CPU Select - Uint16 GPIO150:4; // 27:24 GPIO150 Master CPU Select - Uint16 GPIO151:4; // 31:28 GPIO151 Master CPU Select -}; - -union GPECSEL3_REG { - Uint32 all; - struct GPECSEL3_BITS bit; -}; - -struct GPECSEL4_BITS { // bits description - Uint16 GPIO152:4; // 3:0 GPIO152 Master CPU Select - Uint16 GPIO153:4; // 7:4 GPIO153 Master CPU Select - Uint16 GPIO154:4; // 11:8 GPIO154 Master CPU Select - Uint16 GPIO155:4; // 15:12 GPIO155 Master CPU Select - Uint16 GPIO156:4; // 19:16 GPIO156 Master CPU Select - Uint16 GPIO157:4; // 23:20 GPIO157 Master CPU Select - Uint16 GPIO158:4; // 27:24 GPIO158 Master CPU Select - Uint16 GPIO159:4; // 31:28 GPIO159 Master CPU Select -}; - -union GPECSEL4_REG { - Uint32 all; - struct GPECSEL4_BITS bit; -}; - -struct GPELOCK_BITS { // bits description - Uint16 GPIO128:1; // 0 Configuration Lock bit for this pin - Uint16 GPIO129:1; // 1 Configuration Lock bit for this pin - Uint16 GPIO130:1; // 2 Configuration Lock bit for this pin - Uint16 GPIO131:1; // 3 Configuration Lock bit for this pin - Uint16 GPIO132:1; // 4 Configuration Lock bit for this pin - Uint16 GPIO133:1; // 5 Configuration Lock bit for this pin - Uint16 GPIO134:1; // 6 Configuration Lock bit for this pin - Uint16 GPIO135:1; // 7 Configuration Lock bit for this pin - Uint16 GPIO136:1; // 8 Configuration Lock bit for this pin - Uint16 GPIO137:1; // 9 Configuration Lock bit for this pin - Uint16 GPIO138:1; // 10 Configuration Lock bit for this pin - Uint16 GPIO139:1; // 11 Configuration Lock bit for this pin - Uint16 GPIO140:1; // 12 Configuration Lock bit for this pin - Uint16 GPIO141:1; // 13 Configuration Lock bit for this pin - Uint16 GPIO142:1; // 14 Configuration Lock bit for this pin - Uint16 GPIO143:1; // 15 Configuration Lock bit for this pin - Uint16 GPIO144:1; // 16 Configuration Lock bit for this pin - Uint16 GPIO145:1; // 17 Configuration Lock bit for this pin - Uint16 GPIO146:1; // 18 Configuration Lock bit for this pin - Uint16 GPIO147:1; // 19 Configuration Lock bit for this pin - Uint16 GPIO148:1; // 20 Configuration Lock bit for this pin - Uint16 GPIO149:1; // 21 Configuration Lock bit for this pin - Uint16 GPIO150:1; // 22 Configuration Lock bit for this pin - Uint16 GPIO151:1; // 23 Configuration Lock bit for this pin - Uint16 GPIO152:1; // 24 Configuration Lock bit for this pin - Uint16 GPIO153:1; // 25 Configuration Lock bit for this pin - Uint16 GPIO154:1; // 26 Configuration Lock bit for this pin - Uint16 GPIO155:1; // 27 Configuration Lock bit for this pin - Uint16 GPIO156:1; // 28 Configuration Lock bit for this pin - Uint16 GPIO157:1; // 29 Configuration Lock bit for this pin - Uint16 GPIO158:1; // 30 Configuration Lock bit for this pin - Uint16 GPIO159:1; // 31 Configuration Lock bit for this pin -}; - -union GPELOCK_REG { - Uint32 all; - struct GPELOCK_BITS bit; -}; - -struct GPECR_BITS { // bits description - Uint16 GPIO128:1; // 0 Configuration lock commit bit for this pin - Uint16 GPIO129:1; // 1 Configuration lock commit bit for this pin - Uint16 GPIO130:1; // 2 Configuration lock commit bit for this pin - Uint16 GPIO131:1; // 3 Configuration lock commit bit for this pin - Uint16 GPIO132:1; // 4 Configuration lock commit bit for this pin - Uint16 GPIO133:1; // 5 Configuration lock commit bit for this pin - Uint16 GPIO134:1; // 6 Configuration lock commit bit for this pin - Uint16 GPIO135:1; // 7 Configuration lock commit bit for this pin - Uint16 GPIO136:1; // 8 Configuration lock commit bit for this pin - Uint16 GPIO137:1; // 9 Configuration lock commit bit for this pin - Uint16 GPIO138:1; // 10 Configuration lock commit bit for this pin - Uint16 GPIO139:1; // 11 Configuration lock commit bit for this pin - Uint16 GPIO140:1; // 12 Configuration lock commit bit for this pin - Uint16 GPIO141:1; // 13 Configuration lock commit bit for this pin - Uint16 GPIO142:1; // 14 Configuration lock commit bit for this pin - Uint16 GPIO143:1; // 15 Configuration lock commit bit for this pin - Uint16 GPIO144:1; // 16 Configuration lock commit bit for this pin - Uint16 GPIO145:1; // 17 Configuration lock commit bit for this pin - Uint16 GPIO146:1; // 18 Configuration lock commit bit for this pin - Uint16 GPIO147:1; // 19 Configuration lock commit bit for this pin - Uint16 GPIO148:1; // 20 Configuration lock commit bit for this pin - Uint16 GPIO149:1; // 21 Configuration lock commit bit for this pin - Uint16 GPIO150:1; // 22 Configuration lock commit bit for this pin - Uint16 GPIO151:1; // 23 Configuration lock commit bit for this pin - Uint16 GPIO152:1; // 24 Configuration lock commit bit for this pin - Uint16 GPIO153:1; // 25 Configuration lock commit bit for this pin - Uint16 GPIO154:1; // 26 Configuration lock commit bit for this pin - Uint16 GPIO155:1; // 27 Configuration lock commit bit for this pin - Uint16 GPIO156:1; // 28 Configuration lock commit bit for this pin - Uint16 GPIO157:1; // 29 Configuration lock commit bit for this pin - Uint16 GPIO158:1; // 30 Configuration lock commit bit for this pin - Uint16 GPIO159:1; // 31 Configuration lock commit bit for this pin -}; - -union GPECR_REG { - Uint32 all; - struct GPECR_BITS bit; -}; - -struct GPFCTRL_BITS { // bits description - Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO160 to GPIO167 - Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO168 - Uint16 rsvd1:8; // 23:16 Reserved - Uint16 rsvd2:8; // 31:24 Reserved -}; - -union GPFCTRL_REG { - Uint32 all; - struct GPFCTRL_BITS bit; -}; - -struct GPFQSEL1_BITS { // bits description - Uint16 GPIO160:2; // 1:0 Select input qualification type for GPIO160 - Uint16 GPIO161:2; // 3:2 Select input qualification type for GPIO161 - Uint16 GPIO162:2; // 5:4 Select input qualification type for GPIO162 - Uint16 GPIO163:2; // 7:6 Select input qualification type for GPIO163 - Uint16 GPIO164:2; // 9:8 Select input qualification type for GPIO164 - Uint16 GPIO165:2; // 11:10 Select input qualification type for GPIO165 - Uint16 GPIO166:2; // 13:12 Select input qualification type for GPIO166 - Uint16 GPIO167:2; // 15:14 Select input qualification type for GPIO167 - Uint16 GPIO168:2; // 17:16 Select input qualification type for GPIO168 - Uint16 rsvd1:2; // 19:18 Reserved - Uint16 rsvd2:2; // 21:20 Reserved - Uint16 rsvd3:2; // 23:22 Reserved - Uint16 rsvd4:2; // 25:24 Reserved - Uint16 rsvd5:2; // 27:26 Reserved - Uint16 rsvd6:2; // 29:28 Reserved - Uint16 rsvd7:2; // 31:30 Reserved -}; - -union GPFQSEL1_REG { - Uint32 all; - struct GPFQSEL1_BITS bit; -}; - -struct GPFMUX1_BITS { // bits description - Uint16 GPIO160:2; // 1:0 Defines pin-muxing selection for GPIO160 - Uint16 GPIO161:2; // 3:2 Defines pin-muxing selection for GPIO161 - Uint16 GPIO162:2; // 5:4 Defines pin-muxing selection for GPIO162 - Uint16 GPIO163:2; // 7:6 Defines pin-muxing selection for GPIO163 - Uint16 GPIO164:2; // 9:8 Defines pin-muxing selection for GPIO164 - Uint16 GPIO165:2; // 11:10 Defines pin-muxing selection for GPIO165 - Uint16 GPIO166:2; // 13:12 Defines pin-muxing selection for GPIO166 - Uint16 GPIO167:2; // 15:14 Defines pin-muxing selection for GPIO167 - Uint16 GPIO168:2; // 17:16 Defines pin-muxing selection for GPIO168 - Uint16 rsvd1:2; // 19:18 Reserved - Uint16 rsvd2:2; // 21:20 Reserved - Uint16 rsvd3:2; // 23:22 Reserved - Uint16 rsvd4:2; // 25:24 Reserved - Uint16 rsvd5:2; // 27:26 Reserved - Uint16 rsvd6:2; // 29:28 Reserved - Uint16 rsvd7:2; // 31:30 Reserved -}; - -union GPFMUX1_REG { - Uint32 all; - struct GPFMUX1_BITS bit; -}; - -struct GPFDIR_BITS { // bits description - Uint16 GPIO160:1; // 0 Defines direction for this pin in GPIO mode - Uint16 GPIO161:1; // 1 Defines direction for this pin in GPIO mode - Uint16 GPIO162:1; // 2 Defines direction for this pin in GPIO mode - Uint16 GPIO163:1; // 3 Defines direction for this pin in GPIO mode - Uint16 GPIO164:1; // 4 Defines direction for this pin in GPIO mode - Uint16 GPIO165:1; // 5 Defines direction for this pin in GPIO mode - Uint16 GPIO166:1; // 6 Defines direction for this pin in GPIO mode - Uint16 GPIO167:1; // 7 Defines direction for this pin in GPIO mode - Uint16 GPIO168:1; // 8 Defines direction for this pin in GPIO mode - Uint16 rsvd1:1; // 9 Reserved - Uint16 rsvd2:1; // 10 Reserved - Uint16 rsvd3:1; // 11 Reserved - Uint16 rsvd4:1; // 12 Reserved - Uint16 rsvd5:1; // 13 Reserved - Uint16 rsvd6:1; // 14 Reserved - Uint16 rsvd7:1; // 15 Reserved - Uint16 rsvd8:1; // 16 Reserved - Uint16 rsvd9:1; // 17 Reserved - Uint16 rsvd10:1; // 18 Reserved - Uint16 rsvd11:1; // 19 Reserved - Uint16 rsvd12:1; // 20 Reserved - Uint16 rsvd13:1; // 21 Reserved - Uint16 rsvd14:1; // 22 Reserved - Uint16 rsvd15:1; // 23 Reserved - Uint16 rsvd16:1; // 24 Reserved - Uint16 rsvd17:1; // 25 Reserved - Uint16 rsvd18:1; // 26 Reserved - Uint16 rsvd19:1; // 27 Reserved - Uint16 rsvd20:1; // 28 Reserved - Uint16 rsvd21:1; // 29 Reserved - Uint16 rsvd22:1; // 30 Reserved - Uint16 rsvd23:1; // 31 Reserved -}; - -union GPFDIR_REG { - Uint32 all; - struct GPFDIR_BITS bit; -}; - -struct GPFPUD_BITS { // bits description - Uint16 GPIO160:1; // 0 Pull-Up Disable control for this pin - Uint16 GPIO161:1; // 1 Pull-Up Disable control for this pin - Uint16 GPIO162:1; // 2 Pull-Up Disable control for this pin - Uint16 GPIO163:1; // 3 Pull-Up Disable control for this pin - Uint16 GPIO164:1; // 4 Pull-Up Disable control for this pin - Uint16 GPIO165:1; // 5 Pull-Up Disable control for this pin - Uint16 GPIO166:1; // 6 Pull-Up Disable control for this pin - Uint16 GPIO167:1; // 7 Pull-Up Disable control for this pin - Uint16 GPIO168:1; // 8 Pull-Up Disable control for this pin - Uint16 rsvd1:1; // 9 Reserved - Uint16 rsvd2:1; // 10 Reserved - Uint16 rsvd3:1; // 11 Reserved - Uint16 rsvd4:1; // 12 Reserved - Uint16 rsvd5:1; // 13 Reserved - Uint16 rsvd6:1; // 14 Reserved - Uint16 rsvd7:1; // 15 Reserved - Uint16 rsvd8:1; // 16 Reserved - Uint16 rsvd9:1; // 17 Reserved - Uint16 rsvd10:1; // 18 Reserved - Uint16 rsvd11:1; // 19 Reserved - Uint16 rsvd12:1; // 20 Reserved - Uint16 rsvd13:1; // 21 Reserved - Uint16 rsvd14:1; // 22 Reserved - Uint16 rsvd15:1; // 23 Reserved - Uint16 rsvd16:1; // 24 Reserved - Uint16 rsvd17:1; // 25 Reserved - Uint16 rsvd18:1; // 26 Reserved - Uint16 rsvd19:1; // 27 Reserved - Uint16 rsvd20:1; // 28 Reserved - Uint16 rsvd21:1; // 29 Reserved - Uint16 rsvd22:1; // 30 Reserved - Uint16 rsvd23:1; // 31 Reserved -}; - -union GPFPUD_REG { - Uint32 all; - struct GPFPUD_BITS bit; -}; - -struct GPFINV_BITS { // bits description - Uint16 GPIO160:1; // 0 Input inversion control for this pin - Uint16 GPIO161:1; // 1 Input inversion control for this pin - Uint16 GPIO162:1; // 2 Input inversion control for this pin - Uint16 GPIO163:1; // 3 Input inversion control for this pin - Uint16 GPIO164:1; // 4 Input inversion control for this pin - Uint16 GPIO165:1; // 5 Input inversion control for this pin - Uint16 GPIO166:1; // 6 Input inversion control for this pin - Uint16 GPIO167:1; // 7 Input inversion control for this pin - Uint16 GPIO168:1; // 8 Input inversion control for this pin - Uint16 rsvd1:1; // 9 Reserved - Uint16 rsvd2:1; // 10 Reserved - Uint16 rsvd3:1; // 11 Reserved - Uint16 rsvd4:1; // 12 Reserved - Uint16 rsvd5:1; // 13 Reserved - Uint16 rsvd6:1; // 14 Reserved - Uint16 rsvd7:1; // 15 Reserved - Uint16 rsvd8:1; // 16 Reserved - Uint16 rsvd9:1; // 17 Reserved - Uint16 rsvd10:1; // 18 Reserved - Uint16 rsvd11:1; // 19 Reserved - Uint16 rsvd12:1; // 20 Reserved - Uint16 rsvd13:1; // 21 Reserved - Uint16 rsvd14:1; // 22 Reserved - Uint16 rsvd15:1; // 23 Reserved - Uint16 rsvd16:1; // 24 Reserved - Uint16 rsvd17:1; // 25 Reserved - Uint16 rsvd18:1; // 26 Reserved - Uint16 rsvd19:1; // 27 Reserved - Uint16 rsvd20:1; // 28 Reserved - Uint16 rsvd21:1; // 29 Reserved - Uint16 rsvd22:1; // 30 Reserved - Uint16 rsvd23:1; // 31 Reserved -}; - -union GPFINV_REG { - Uint32 all; - struct GPFINV_BITS bit; -}; - -struct GPFODR_BITS { // bits description - Uint16 GPIO160:1; // 0 Outpout Open-Drain control for this pin - Uint16 GPIO161:1; // 1 Outpout Open-Drain control for this pin - Uint16 GPIO162:1; // 2 Outpout Open-Drain control for this pin - Uint16 GPIO163:1; // 3 Outpout Open-Drain control for this pin - Uint16 GPIO164:1; // 4 Outpout Open-Drain control for this pin - Uint16 GPIO165:1; // 5 Outpout Open-Drain control for this pin - Uint16 GPIO166:1; // 6 Outpout Open-Drain control for this pin - Uint16 GPIO167:1; // 7 Outpout Open-Drain control for this pin - Uint16 GPIO168:1; // 8 Outpout Open-Drain control for this pin - Uint16 rsvd1:1; // 9 Reserved - Uint16 rsvd2:1; // 10 Reserved - Uint16 rsvd3:1; // 11 Reserved - Uint16 rsvd4:1; // 12 Reserved - Uint16 rsvd5:1; // 13 Reserved - Uint16 rsvd6:1; // 14 Reserved - Uint16 rsvd7:1; // 15 Reserved - Uint16 rsvd8:1; // 16 Reserved - Uint16 rsvd9:1; // 17 Reserved - Uint16 rsvd10:1; // 18 Reserved - Uint16 rsvd11:1; // 19 Reserved - Uint16 rsvd12:1; // 20 Reserved - Uint16 rsvd13:1; // 21 Reserved - Uint16 rsvd14:1; // 22 Reserved - Uint16 rsvd15:1; // 23 Reserved - Uint16 rsvd16:1; // 24 Reserved - Uint16 rsvd17:1; // 25 Reserved - Uint16 rsvd18:1; // 26 Reserved - Uint16 rsvd19:1; // 27 Reserved - Uint16 rsvd20:1; // 28 Reserved - Uint16 rsvd21:1; // 29 Reserved - Uint16 rsvd22:1; // 30 Reserved - Uint16 rsvd23:1; // 31 Reserved -}; - -union GPFODR_REG { - Uint32 all; - struct GPFODR_BITS bit; -}; - -struct GPFGMUX1_BITS { // bits description - Uint16 GPIO160:2; // 1:0 Defines pin-muxing selection for GPIO160 - Uint16 GPIO161:2; // 3:2 Defines pin-muxing selection for GPIO161 - Uint16 GPIO162:2; // 5:4 Defines pin-muxing selection for GPIO162 - Uint16 GPIO163:2; // 7:6 Defines pin-muxing selection for GPIO163 - Uint16 GPIO164:2; // 9:8 Defines pin-muxing selection for GPIO164 - Uint16 GPIO165:2; // 11:10 Defines pin-muxing selection for GPIO165 - Uint16 GPIO166:2; // 13:12 Defines pin-muxing selection for GPIO166 - Uint16 GPIO167:2; // 15:14 Defines pin-muxing selection for GPIO167 - Uint16 GPIO168:2; // 17:16 Defines pin-muxing selection for GPIO168 - Uint16 rsvd1:2; // 19:18 Reserved - Uint16 rsvd2:2; // 21:20 Reserved - Uint16 rsvd3:2; // 23:22 Reserved - Uint16 rsvd4:2; // 25:24 Reserved - Uint16 rsvd5:2; // 27:26 Reserved - Uint16 rsvd6:2; // 29:28 Reserved - Uint16 rsvd7:2; // 31:30 Reserved -}; - -union GPFGMUX1_REG { - Uint32 all; - struct GPFGMUX1_BITS bit; -}; - -struct GPFCSEL1_BITS { // bits description - Uint16 GPIO160:4; // 3:0 GPIO160 Master CPU Select - Uint16 GPIO161:4; // 7:4 GPIO161 Master CPU Select - Uint16 GPIO162:4; // 11:8 GPIO162 Master CPU Select - Uint16 GPIO163:4; // 15:12 GPIO163 Master CPU Select - Uint16 GPIO164:4; // 19:16 GPIO164 Master CPU Select - Uint16 GPIO165:4; // 23:20 GPIO165 Master CPU Select - Uint16 GPIO166:4; // 27:24 GPIO166 Master CPU Select - Uint16 GPIO167:4; // 31:28 GPIO167 Master CPU Select -}; - -union GPFCSEL1_REG { - Uint32 all; - struct GPFCSEL1_BITS bit; -}; - -struct GPFCSEL2_BITS { // bits description - Uint16 GPIO168:4; // 3:0 GPIO168 Master CPU Select - Uint16 rsvd1:4; // 7:4 Reserved - Uint16 rsvd2:4; // 11:8 Reserved - Uint16 rsvd3:4; // 15:12 Reserved - Uint16 rsvd4:4; // 19:16 Reserved - Uint16 rsvd5:4; // 23:20 Reserved - Uint16 rsvd6:4; // 27:24 Reserved - Uint16 rsvd7:4; // 31:28 Reserved -}; - -union GPFCSEL2_REG { - Uint32 all; - struct GPFCSEL2_BITS bit; -}; - -struct GPFLOCK_BITS { // bits description - Uint16 GPIO160:1; // 0 Configuration Lock bit for this pin - Uint16 GPIO161:1; // 1 Configuration Lock bit for this pin - Uint16 GPIO162:1; // 2 Configuration Lock bit for this pin - Uint16 GPIO163:1; // 3 Configuration Lock bit for this pin - Uint16 GPIO164:1; // 4 Configuration Lock bit for this pin - Uint16 GPIO165:1; // 5 Configuration Lock bit for this pin - Uint16 GPIO166:1; // 6 Configuration Lock bit for this pin - Uint16 GPIO167:1; // 7 Configuration Lock bit for this pin - Uint16 GPIO168:1; // 8 Configuration Lock bit for this pin - Uint16 rsvd1:1; // 9 Reserved - Uint16 rsvd2:1; // 10 Reserved - Uint16 rsvd3:1; // 11 Reserved - Uint16 rsvd4:1; // 12 Reserved - Uint16 rsvd5:1; // 13 Reserved - Uint16 rsvd6:1; // 14 Reserved - Uint16 rsvd7:1; // 15 Reserved - Uint16 rsvd8:1; // 16 Reserved - Uint16 rsvd9:1; // 17 Reserved - Uint16 rsvd10:1; // 18 Reserved - Uint16 rsvd11:1; // 19 Reserved - Uint16 rsvd12:1; // 20 Reserved - Uint16 rsvd13:1; // 21 Reserved - Uint16 rsvd14:1; // 22 Reserved - Uint16 rsvd15:1; // 23 Reserved - Uint16 rsvd16:1; // 24 Reserved - Uint16 rsvd17:1; // 25 Reserved - Uint16 rsvd18:1; // 26 Reserved - Uint16 rsvd19:1; // 27 Reserved - Uint16 rsvd20:1; // 28 Reserved - Uint16 rsvd21:1; // 29 Reserved - Uint16 rsvd22:1; // 30 Reserved - Uint16 rsvd23:1; // 31 Reserved -}; - -union GPFLOCK_REG { - Uint32 all; - struct GPFLOCK_BITS bit; -}; - -struct GPFCR_BITS { // bits description - Uint16 GPIO160:1; // 0 Configuration lock commit bit for this pin - Uint16 GPIO161:1; // 1 Configuration lock commit bit for this pin - Uint16 GPIO162:1; // 2 Configuration lock commit bit for this pin - Uint16 GPIO163:1; // 3 Configuration lock commit bit for this pin - Uint16 GPIO164:1; // 4 Configuration lock commit bit for this pin - Uint16 GPIO165:1; // 5 Configuration lock commit bit for this pin - Uint16 GPIO166:1; // 6 Configuration lock commit bit for this pin - Uint16 GPIO167:1; // 7 Configuration lock commit bit for this pin - Uint16 GPIO168:1; // 8 Configuration lock commit bit for this pin - Uint16 rsvd1:1; // 9 Reserved - Uint16 rsvd2:1; // 10 Reserved - Uint16 rsvd3:1; // 11 Reserved - Uint16 rsvd4:1; // 12 Reserved - Uint16 rsvd5:1; // 13 Reserved - Uint16 rsvd6:1; // 14 Reserved - Uint16 rsvd7:1; // 15 Reserved - Uint16 rsvd8:1; // 16 Reserved - Uint16 rsvd9:1; // 17 Reserved - Uint16 rsvd10:1; // 18 Reserved - Uint16 rsvd11:1; // 19 Reserved - Uint16 rsvd12:1; // 20 Reserved - Uint16 rsvd13:1; // 21 Reserved - Uint16 rsvd14:1; // 22 Reserved - Uint16 rsvd15:1; // 23 Reserved - Uint16 rsvd16:1; // 24 Reserved - Uint16 rsvd17:1; // 25 Reserved - Uint16 rsvd18:1; // 26 Reserved - Uint16 rsvd19:1; // 27 Reserved - Uint16 rsvd20:1; // 28 Reserved - Uint16 rsvd21:1; // 29 Reserved - Uint16 rsvd22:1; // 30 Reserved - Uint16 rsvd23:1; // 31 Reserved -}; - -union GPFCR_REG { - Uint32 all; - struct GPFCR_BITS bit; -}; - -struct GPIO_CTRL_REGS { - union GPACTRL_REG GPACTRL; // GPIO A Qualification Sampling Period Control (GPIO0 to 31) - union GPAQSEL1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15) - union GPAQSEL2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31) - union GPAMUX1_REG GPAMUX1; // GPIO A Mux 1 Register (GPIO0 to 15) - union GPAMUX2_REG GPAMUX2; // GPIO A Mux 2 Register (GPIO16 to 31) - union GPADIR_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) - union GPAPUD_REG GPAPUD; // GPIO A Pull Up Disable Register (GPIO0 to 31) - Uint16 rsvd1[2]; // Reserved - union GPAINV_REG GPAINV; // GPIO A Input Polarity Invert Registers (GPIO0 to 31) - union GPAODR_REG GPAODR; // GPIO A Open Drain Output Register (GPIO0 to GPIO31) - Uint16 rsvd2[12]; // Reserved - union GPAGMUX1_REG GPAGMUX1; // GPIO A Peripheral Group Mux (GPIO0 to 15) - union GPAGMUX2_REG GPAGMUX2; // GPIO A Peripheral Group Mux (GPIO16 to 31) - Uint16 rsvd3[4]; // Reserved - union GPACSEL1_REG GPACSEL1; // GPIO A Core Select Register (GPIO0 to 7) - union GPACSEL2_REG GPACSEL2; // GPIO A Core Select Register (GPIO8 to 15) - union GPACSEL3_REG GPACSEL3; // GPIO A Core Select Register (GPIO16 to 23) - union GPACSEL4_REG GPACSEL4; // GPIO A Core Select Register (GPIO24 to 31) - Uint16 rsvd4[12]; // Reserved - union GPALOCK_REG GPALOCK; // GPIO A Lock Configuration Register (GPIO0 to 31) - union GPACR_REG GPACR; // GPIO A Lock Commit Register (GPIO0 to 31) - union GPBCTRL_REG GPBCTRL; // GPIO B Qualification Sampling Period Control (GPIO32 to 63) - union GPBQSEL1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 47) - union GPBQSEL2_REG GPBQSEL2; // GPIO B Qualifier Select 2 Register (GPIO48 to 63) - union GPBMUX1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) - union GPBMUX2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) - union GPBDIR_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) - union GPBPUD_REG GPBPUD; // GPIO B Pull Up Disable Register (GPIO32 to 63) - Uint16 rsvd5[2]; // Reserved - union GPBINV_REG GPBINV; // GPIO B Input Polarity Invert Registers (GPIO32 to 63) - union GPBODR_REG GPBODR; // GPIO B Open Drain Output Register (GPIO32 to GPIO63) - union GPBAMSEL_REG GPBAMSEL; // GPIO B Analog Mode Select register (GPIO32 to GPIO63) - Uint16 rsvd6[10]; // Reserved - union GPBGMUX1_REG GPBGMUX1; // GPIO B Peripheral Group Mux (GPIO32 to 47) - union GPBGMUX2_REG GPBGMUX2; // GPIO B Peripheral Group Mux (GPIO48 to 63) - Uint16 rsvd7[4]; // Reserved - union GPBCSEL1_REG GPBCSEL1; // GPIO B Core Select Register (GPIO32 to 39) - union GPBCSEL2_REG GPBCSEL2; // GPIO B Core Select Register (GPIO40 to 47) - union GPBCSEL3_REG GPBCSEL3; // GPIO B Core Select Register (GPIO48 to 55) - union GPBCSEL4_REG GPBCSEL4; // GPIO B Core Select Register (GPIO56 to 63) - Uint16 rsvd8[12]; // Reserved - union GPBLOCK_REG GPBLOCK; // GPIO B Lock Configuration Register (GPIO32 to 63) - union GPBCR_REG GPBCR; // GPIO B Lock Commit Register (GPIO32 to 63) - union GPCCTRL_REG GPCCTRL; // GPIO C Qualification Sampling Period Control (GPIO64 to 95) - union GPCQSEL1_REG GPCQSEL1; // GPIO C Qualifier Select 1 Register (GPIO64 to 79) - union GPCQSEL2_REG GPCQSEL2; // GPIO C Qualifier Select 2 Register (GPIO80 to 95) - union GPCMUX1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) - union GPCMUX2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) - union GPCDIR_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) - union GPCPUD_REG GPCPUD; // GPIO C Pull Up Disable Register (GPIO64 to 95) - Uint16 rsvd9[2]; // Reserved - union GPCINV_REG GPCINV; // GPIO C Input Polarity Invert Registers (GPIO64 to 95) - union GPCODR_REG GPCODR; // GPIO C Open Drain Output Register (GPIO64 to GPIO95) - Uint16 rsvd10[12]; // Reserved - union GPCGMUX1_REG GPCGMUX1; // GPIO C Peripheral Group Mux (GPIO64 to 79) - union GPCGMUX2_REG GPCGMUX2; // GPIO C Peripheral Group Mux (GPIO80 to 95) - Uint16 rsvd11[4]; // Reserved - union GPCCSEL1_REG GPCCSEL1; // GPIO C Core Select Register (GPIO64 to 71) - union GPCCSEL2_REG GPCCSEL2; // GPIO C Core Select Register (GPIO72 to 79) - union GPCCSEL3_REG GPCCSEL3; // GPIO C Core Select Register (GPIO80 to 87) - union GPCCSEL4_REG GPCCSEL4; // GPIO C Core Select Register (GPIO88 to 95) - Uint16 rsvd12[12]; // Reserved - union GPCLOCK_REG GPCLOCK; // GPIO C Lock Configuration Register (GPIO64 to 95) - union GPCCR_REG GPCCR; // GPIO C Lock Commit Register (GPIO64 to 95) - union GPDCTRL_REG GPDCTRL; // GPIO D Qualification Sampling Period Control (GPIO96 to 127) - union GPDQSEL1_REG GPDQSEL1; // GPIO D Qualifier Select 1 Register (GPIO96 to 111) - union GPDQSEL2_REG GPDQSEL2; // GPIO D Qualifier Select 2 Register (GPIO112 to 127) - union GPDMUX1_REG GPDMUX1; // GPIO D Mux 1 Register (GPIO96 to 111) - union GPDMUX2_REG GPDMUX2; // GPIO D Mux 2 Register (GPIO112 to 127) - union GPDDIR_REG GPDDIR; // GPIO D Direction Register (GPIO96 to 127) - union GPDPUD_REG GPDPUD; // GPIO D Pull Up Disable Register (GPIO96 to 127) - Uint16 rsvd13[2]; // Reserved - union GPDINV_REG GPDINV; // GPIO D Input Polarity Invert Registers (GPIO96 to 127) - union GPDODR_REG GPDODR; // GPIO D Open Drain Output Register (GPIO96 to GPIO127) - Uint16 rsvd14[12]; // Reserved - union GPDGMUX1_REG GPDGMUX1; // GPIO D Peripheral Group Mux (GPIO96 to 111) - union GPDGMUX2_REG GPDGMUX2; // GPIO D Peripheral Group Mux (GPIO112 to 127) - Uint16 rsvd15[4]; // Reserved - union GPDCSEL1_REG GPDCSEL1; // GPIO D Core Select Register (GPIO96 to 103) - union GPDCSEL2_REG GPDCSEL2; // GPIO D Core Select Register (GPIO104 to 111) - union GPDCSEL3_REG GPDCSEL3; // GPIO D Core Select Register (GPIO112 to 119) - union GPDCSEL4_REG GPDCSEL4; // GPIO D Core Select Register (GPIO120 to 127) - Uint16 rsvd16[12]; // Reserved - union GPDLOCK_REG GPDLOCK; // GPIO D Lock Configuration Register (GPIO96 to 127) - union GPDCR_REG GPDCR; // GPIO D Lock Commit Register (GPIO96 to 127) - union GPECTRL_REG GPECTRL; // GPIO E Qualification Sampling Period Control (GPIO128 to 159) - union GPEQSEL1_REG GPEQSEL1; // GPIO E Qualifier Select 1 Register (GPIO128 to 143) - union GPEQSEL2_REG GPEQSEL2; // GPIO E Qualifier Select 2 Register (GPIO144 to 159) - union GPEMUX1_REG GPEMUX1; // GPIO E Mux 1 Register (GPIO128 to 143) - union GPEMUX2_REG GPEMUX2; // GPIO E Mux 2 Register (GPIO144 to 159) - union GPEDIR_REG GPEDIR; // GPIO E Direction Register (GPIO128 to 159) - union GPEPUD_REG GPEPUD; // GPIO E Pull Up Disable Register (GPIO128 to 159) - Uint16 rsvd17[2]; // Reserved - union GPEINV_REG GPEINV; // GPIO E Input Polarity Invert Registers (GPIO128 to 159) - union GPEODR_REG GPEODR; // GPIO E Open Drain Output Register (GPIO128 to GPIO159) - Uint16 rsvd18[12]; // Reserved - union GPEGMUX1_REG GPEGMUX1; // GPIO E Peripheral Group Mux (GPIO128 to 143) - union GPEGMUX2_REG GPEGMUX2; // GPIO E Peripheral Group Mux (GPIO144 to 159) - Uint16 rsvd19[4]; // Reserved - union GPECSEL1_REG GPECSEL1; // GPIO E Core Select Register (GPIO128 to 135) - union GPECSEL2_REG GPECSEL2; // GPIO E Core Select Register (GPIO136 to 143) - union GPECSEL3_REG GPECSEL3; // GPIO E Core Select Register (GPIO144 to 151) - union GPECSEL4_REG GPECSEL4; // GPIO E Core Select Register (GPIO152 to 159) - Uint16 rsvd20[12]; // Reserved - union GPELOCK_REG GPELOCK; // GPIO E Lock Configuration Register (GPIO128 to 159) - union GPECR_REG GPECR; // GPIO E Lock Commit Register (GPIO128 to 159) - union GPFCTRL_REG GPFCTRL; // GPIO F Qualification Sampling Period Control (GPIO160 to 168) - union GPFQSEL1_REG GPFQSEL1; // GPIO F Qualifier Select 1 Register (GPIO160 to 168) - Uint16 rsvd21[2]; // Reserved - union GPFMUX1_REG GPFMUX1; // GPIO F Mux 1 Register (GPIO160 to 168) - Uint16 rsvd22[2]; // Reserved - union GPFDIR_REG GPFDIR; // GPIO F Direction Register (GPIO160 to 168) - union GPFPUD_REG GPFPUD; // GPIO F Pull Up Disable Register (GPIO160 to 168) - Uint16 rsvd23[2]; // Reserved - union GPFINV_REG GPFINV; // GPIO F Input Polarity Invert Registers (GPIO160 to 168) - union GPFODR_REG GPFODR; // GPIO F Open Drain Output Register (GPIO160 to GPIO168) - Uint16 rsvd24[12]; // Reserved - union GPFGMUX1_REG GPFGMUX1; // GPIO F Peripheral Group Mux (GPIO160 to 168) - Uint16 rsvd25[6]; // Reserved - union GPFCSEL1_REG GPFCSEL1; // GPIO F Core Select Register (GPIO160 to 167) - union GPFCSEL2_REG GPFCSEL2; // GPIO F Core Select Register (GPIO168) - Uint16 rsvd26[16]; // Reserved - union GPFLOCK_REG GPFLOCK; // GPIO F Lock Configuration Register (GPIO160 to 168) - union GPFCR_REG GPFCR; // GPIO F Lock Commit Register (GPIO160 to 168) -}; - -struct GPADAT_BITS { // bits description - Uint16 GPIO0:1; // 0 Data Register for this pin - Uint16 GPIO1:1; // 1 Data Register for this pin - Uint16 GPIO2:1; // 2 Data Register for this pin - Uint16 GPIO3:1; // 3 Data Register for this pin - Uint16 GPIO4:1; // 4 Data Register for this pin - Uint16 GPIO5:1; // 5 Data Register for this pin - Uint16 GPIO6:1; // 6 Data Register for this pin - Uint16 GPIO7:1; // 7 Data Register for this pin - Uint16 GPIO8:1; // 8 Data Register for this pin - Uint16 GPIO9:1; // 9 Data Register for this pin - Uint16 GPIO10:1; // 10 Data Register for this pin - Uint16 GPIO11:1; // 11 Data Register for this pin - Uint16 GPIO12:1; // 12 Data Register for this pin - Uint16 GPIO13:1; // 13 Data Register for this pin - Uint16 GPIO14:1; // 14 Data Register for this pin - Uint16 GPIO15:1; // 15 Data Register for this pin - Uint16 GPIO16:1; // 16 Data Register for this pin - Uint16 GPIO17:1; // 17 Data Register for this pin - Uint16 GPIO18:1; // 18 Data Register for this pin - Uint16 GPIO19:1; // 19 Data Register for this pin - Uint16 GPIO20:1; // 20 Data Register for this pin - Uint16 GPIO21:1; // 21 Data Register for this pin - Uint16 GPIO22:1; // 22 Data Register for this pin - Uint16 GPIO23:1; // 23 Data Register for this pin - Uint16 GPIO24:1; // 24 Data Register for this pin - Uint16 GPIO25:1; // 25 Data Register for this pin - Uint16 GPIO26:1; // 26 Data Register for this pin - Uint16 GPIO27:1; // 27 Data Register for this pin - Uint16 GPIO28:1; // 28 Data Register for this pin - Uint16 GPIO29:1; // 29 Data Register for this pin - Uint16 GPIO30:1; // 30 Data Register for this pin - Uint16 GPIO31:1; // 31 Data Register for this pin -}; - -union GPADAT_REG { - Uint32 all; - struct GPADAT_BITS bit; -}; - -struct GPASET_BITS { // bits description - Uint16 GPIO0:1; // 0 Output Set bit for this pin - Uint16 GPIO1:1; // 1 Output Set bit for this pin - Uint16 GPIO2:1; // 2 Output Set bit for this pin - Uint16 GPIO3:1; // 3 Output Set bit for this pin - Uint16 GPIO4:1; // 4 Output Set bit for this pin - Uint16 GPIO5:1; // 5 Output Set bit for this pin - Uint16 GPIO6:1; // 6 Output Set bit for this pin - Uint16 GPIO7:1; // 7 Output Set bit for this pin - Uint16 GPIO8:1; // 8 Output Set bit for this pin - Uint16 GPIO9:1; // 9 Output Set bit for this pin - Uint16 GPIO10:1; // 10 Output Set bit for this pin - Uint16 GPIO11:1; // 11 Output Set bit for this pin - Uint16 GPIO12:1; // 12 Output Set bit for this pin - Uint16 GPIO13:1; // 13 Output Set bit for this pin - Uint16 GPIO14:1; // 14 Output Set bit for this pin - Uint16 GPIO15:1; // 15 Output Set bit for this pin - Uint16 GPIO16:1; // 16 Output Set bit for this pin - Uint16 GPIO17:1; // 17 Output Set bit for this pin - Uint16 GPIO18:1; // 18 Output Set bit for this pin - Uint16 GPIO19:1; // 19 Output Set bit for this pin - Uint16 GPIO20:1; // 20 Output Set bit for this pin - Uint16 GPIO21:1; // 21 Output Set bit for this pin - Uint16 GPIO22:1; // 22 Output Set bit for this pin - Uint16 GPIO23:1; // 23 Output Set bit for this pin - Uint16 GPIO24:1; // 24 Output Set bit for this pin - Uint16 GPIO25:1; // 25 Output Set bit for this pin - Uint16 GPIO26:1; // 26 Output Set bit for this pin - Uint16 GPIO27:1; // 27 Output Set bit for this pin - Uint16 GPIO28:1; // 28 Output Set bit for this pin - Uint16 GPIO29:1; // 29 Output Set bit for this pin - Uint16 GPIO30:1; // 30 Output Set bit for this pin - Uint16 GPIO31:1; // 31 Output Set bit for this pin -}; - -union GPASET_REG { - Uint32 all; - struct GPASET_BITS bit; -}; - -struct GPACLEAR_BITS { // bits description - Uint16 GPIO0:1; // 0 Output Clear bit for this pin - Uint16 GPIO1:1; // 1 Output Clear bit for this pin - Uint16 GPIO2:1; // 2 Output Clear bit for this pin - Uint16 GPIO3:1; // 3 Output Clear bit for this pin - Uint16 GPIO4:1; // 4 Output Clear bit for this pin - Uint16 GPIO5:1; // 5 Output Clear bit for this pin - Uint16 GPIO6:1; // 6 Output Clear bit for this pin - Uint16 GPIO7:1; // 7 Output Clear bit for this pin - Uint16 GPIO8:1; // 8 Output Clear bit for this pin - Uint16 GPIO9:1; // 9 Output Clear bit for this pin - Uint16 GPIO10:1; // 10 Output Clear bit for this pin - Uint16 GPIO11:1; // 11 Output Clear bit for this pin - Uint16 GPIO12:1; // 12 Output Clear bit for this pin - Uint16 GPIO13:1; // 13 Output Clear bit for this pin - Uint16 GPIO14:1; // 14 Output Clear bit for this pin - Uint16 GPIO15:1; // 15 Output Clear bit for this pin - Uint16 GPIO16:1; // 16 Output Clear bit for this pin - Uint16 GPIO17:1; // 17 Output Clear bit for this pin - Uint16 GPIO18:1; // 18 Output Clear bit for this pin - Uint16 GPIO19:1; // 19 Output Clear bit for this pin - Uint16 GPIO20:1; // 20 Output Clear bit for this pin - Uint16 GPIO21:1; // 21 Output Clear bit for this pin - Uint16 GPIO22:1; // 22 Output Clear bit for this pin - Uint16 GPIO23:1; // 23 Output Clear bit for this pin - Uint16 GPIO24:1; // 24 Output Clear bit for this pin - Uint16 GPIO25:1; // 25 Output Clear bit for this pin - Uint16 GPIO26:1; // 26 Output Clear bit for this pin - Uint16 GPIO27:1; // 27 Output Clear bit for this pin - Uint16 GPIO28:1; // 28 Output Clear bit for this pin - Uint16 GPIO29:1; // 29 Output Clear bit for this pin - Uint16 GPIO30:1; // 30 Output Clear bit for this pin - Uint16 GPIO31:1; // 31 Output Clear bit for this pin -}; - -union GPACLEAR_REG { - Uint32 all; - struct GPACLEAR_BITS bit; -}; - -struct GPATOGGLE_BITS { // bits description - Uint16 GPIO0:1; // 0 Output Toggle bit for this pin - Uint16 GPIO1:1; // 1 Output Toggle bit for this pin - Uint16 GPIO2:1; // 2 Output Toggle bit for this pin - Uint16 GPIO3:1; // 3 Output Toggle bit for this pin - Uint16 GPIO4:1; // 4 Output Toggle bit for this pin - Uint16 GPIO5:1; // 5 Output Toggle bit for this pin - Uint16 GPIO6:1; // 6 Output Toggle bit for this pin - Uint16 GPIO7:1; // 7 Output Toggle bit for this pin - Uint16 GPIO8:1; // 8 Output Toggle bit for this pin - Uint16 GPIO9:1; // 9 Output Toggle bit for this pin - Uint16 GPIO10:1; // 10 Output Toggle bit for this pin - Uint16 GPIO11:1; // 11 Output Toggle bit for this pin - Uint16 GPIO12:1; // 12 Output Toggle bit for this pin - Uint16 GPIO13:1; // 13 Output Toggle bit for this pin - Uint16 GPIO14:1; // 14 Output Toggle bit for this pin - Uint16 GPIO15:1; // 15 Output Toggle bit for this pin - Uint16 GPIO16:1; // 16 Output Toggle bit for this pin - Uint16 GPIO17:1; // 17 Output Toggle bit for this pin - Uint16 GPIO18:1; // 18 Output Toggle bit for this pin - Uint16 GPIO19:1; // 19 Output Toggle bit for this pin - Uint16 GPIO20:1; // 20 Output Toggle bit for this pin - Uint16 GPIO21:1; // 21 Output Toggle bit for this pin - Uint16 GPIO22:1; // 22 Output Toggle bit for this pin - Uint16 GPIO23:1; // 23 Output Toggle bit for this pin - Uint16 GPIO24:1; // 24 Output Toggle bit for this pin - Uint16 GPIO25:1; // 25 Output Toggle bit for this pin - Uint16 GPIO26:1; // 26 Output Toggle bit for this pin - Uint16 GPIO27:1; // 27 Output Toggle bit for this pin - Uint16 GPIO28:1; // 28 Output Toggle bit for this pin - Uint16 GPIO29:1; // 29 Output Toggle bit for this pin - Uint16 GPIO30:1; // 30 Output Toggle bit for this pin - Uint16 GPIO31:1; // 31 Output Toggle bit for this pin -}; - -union GPATOGGLE_REG { - Uint32 all; - struct GPATOGGLE_BITS bit; -}; - -struct GPBDAT_BITS { // bits description - Uint16 GPIO32:1; // 0 Data Register for this pin - Uint16 GPIO33:1; // 1 Data Register for this pin - Uint16 GPIO34:1; // 2 Data Register for this pin - Uint16 GPIO35:1; // 3 Data Register for this pin - Uint16 GPIO36:1; // 4 Data Register for this pin - Uint16 GPIO37:1; // 5 Data Register for this pin - Uint16 GPIO38:1; // 6 Data Register for this pin - Uint16 GPIO39:1; // 7 Data Register for this pin - Uint16 GPIO40:1; // 8 Data Register for this pin - Uint16 GPIO41:1; // 9 Data Register for this pin - Uint16 GPIO42:1; // 10 Data Register for this pin - Uint16 GPIO43:1; // 11 Data Register for this pin - Uint16 GPIO44:1; // 12 Data Register for this pin - Uint16 GPIO45:1; // 13 Data Register for this pin - Uint16 GPIO46:1; // 14 Data Register for this pin - Uint16 GPIO47:1; // 15 Data Register for this pin - Uint16 GPIO48:1; // 16 Data Register for this pin - Uint16 GPIO49:1; // 17 Data Register for this pin - Uint16 GPIO50:1; // 18 Data Register for this pin - Uint16 GPIO51:1; // 19 Data Register for this pin - Uint16 GPIO52:1; // 20 Data Register for this pin - Uint16 GPIO53:1; // 21 Data Register for this pin - Uint16 GPIO54:1; // 22 Data Register for this pin - Uint16 GPIO55:1; // 23 Data Register for this pin - Uint16 GPIO56:1; // 24 Data Register for this pin - Uint16 GPIO57:1; // 25 Data Register for this pin - Uint16 GPIO58:1; // 26 Data Register for this pin - Uint16 GPIO59:1; // 27 Data Register for this pin - Uint16 GPIO60:1; // 28 Data Register for this pin - Uint16 GPIO61:1; // 29 Data Register for this pin - Uint16 GPIO62:1; // 30 Data Register for this pin - Uint16 GPIO63:1; // 31 Data Register for this pin -}; - -union GPBDAT_REG { - Uint32 all; - struct GPBDAT_BITS bit; -}; - -struct GPBSET_BITS { // bits description - Uint16 GPIO32:1; // 0 Output Set bit for this pin - Uint16 GPIO33:1; // 1 Output Set bit for this pin - Uint16 GPIO34:1; // 2 Output Set bit for this pin - Uint16 GPIO35:1; // 3 Output Set bit for this pin - Uint16 GPIO36:1; // 4 Output Set bit for this pin - Uint16 GPIO37:1; // 5 Output Set bit for this pin - Uint16 GPIO38:1; // 6 Output Set bit for this pin - Uint16 GPIO39:1; // 7 Output Set bit for this pin - Uint16 GPIO40:1; // 8 Output Set bit for this pin - Uint16 GPIO41:1; // 9 Output Set bit for this pin - Uint16 GPIO42:1; // 10 Output Set bit for this pin - Uint16 GPIO43:1; // 11 Output Set bit for this pin - Uint16 GPIO44:1; // 12 Output Set bit for this pin - Uint16 GPIO45:1; // 13 Output Set bit for this pin - Uint16 GPIO46:1; // 14 Output Set bit for this pin - Uint16 GPIO47:1; // 15 Output Set bit for this pin - Uint16 GPIO48:1; // 16 Output Set bit for this pin - Uint16 GPIO49:1; // 17 Output Set bit for this pin - Uint16 GPIO50:1; // 18 Output Set bit for this pin - Uint16 GPIO51:1; // 19 Output Set bit for this pin - Uint16 GPIO52:1; // 20 Output Set bit for this pin - Uint16 GPIO53:1; // 21 Output Set bit for this pin - Uint16 GPIO54:1; // 22 Output Set bit for this pin - Uint16 GPIO55:1; // 23 Output Set bit for this pin - Uint16 GPIO56:1; // 24 Output Set bit for this pin - Uint16 GPIO57:1; // 25 Output Set bit for this pin - Uint16 GPIO58:1; // 26 Output Set bit for this pin - Uint16 GPIO59:1; // 27 Output Set bit for this pin - Uint16 GPIO60:1; // 28 Output Set bit for this pin - Uint16 GPIO61:1; // 29 Output Set bit for this pin - Uint16 GPIO62:1; // 30 Output Set bit for this pin - Uint16 GPIO63:1; // 31 Output Set bit for this pin -}; - -union GPBSET_REG { - Uint32 all; - struct GPBSET_BITS bit; -}; - -struct GPBCLEAR_BITS { // bits description - Uint16 GPIO32:1; // 0 Output Clear bit for this pin - Uint16 GPIO33:1; // 1 Output Clear bit for this pin - Uint16 GPIO34:1; // 2 Output Clear bit for this pin - Uint16 GPIO35:1; // 3 Output Clear bit for this pin - Uint16 GPIO36:1; // 4 Output Clear bit for this pin - Uint16 GPIO37:1; // 5 Output Clear bit for this pin - Uint16 GPIO38:1; // 6 Output Clear bit for this pin - Uint16 GPIO39:1; // 7 Output Clear bit for this pin - Uint16 GPIO40:1; // 8 Output Clear bit for this pin - Uint16 GPIO41:1; // 9 Output Clear bit for this pin - Uint16 GPIO42:1; // 10 Output Clear bit for this pin - Uint16 GPIO43:1; // 11 Output Clear bit for this pin - Uint16 GPIO44:1; // 12 Output Clear bit for this pin - Uint16 GPIO45:1; // 13 Output Clear bit for this pin - Uint16 GPIO46:1; // 14 Output Clear bit for this pin - Uint16 GPIO47:1; // 15 Output Clear bit for this pin - Uint16 GPIO48:1; // 16 Output Clear bit for this pin - Uint16 GPIO49:1; // 17 Output Clear bit for this pin - Uint16 GPIO50:1; // 18 Output Clear bit for this pin - Uint16 GPIO51:1; // 19 Output Clear bit for this pin - Uint16 GPIO52:1; // 20 Output Clear bit for this pin - Uint16 GPIO53:1; // 21 Output Clear bit for this pin - Uint16 GPIO54:1; // 22 Output Clear bit for this pin - Uint16 GPIO55:1; // 23 Output Clear bit for this pin - Uint16 GPIO56:1; // 24 Output Clear bit for this pin - Uint16 GPIO57:1; // 25 Output Clear bit for this pin - Uint16 GPIO58:1; // 26 Output Clear bit for this pin - Uint16 GPIO59:1; // 27 Output Clear bit for this pin - Uint16 GPIO60:1; // 28 Output Clear bit for this pin - Uint16 GPIO61:1; // 29 Output Clear bit for this pin - Uint16 GPIO62:1; // 30 Output Clear bit for this pin - Uint16 GPIO63:1; // 31 Output Clear bit for this pin -}; - -union GPBCLEAR_REG { - Uint32 all; - struct GPBCLEAR_BITS bit; -}; - -struct GPBTOGGLE_BITS { // bits description - Uint16 GPIO32:1; // 0 Output Toggle bit for this pin - Uint16 GPIO33:1; // 1 Output Toggle bit for this pin - Uint16 GPIO34:1; // 2 Output Toggle bit for this pin - Uint16 GPIO35:1; // 3 Output Toggle bit for this pin - Uint16 GPIO36:1; // 4 Output Toggle bit for this pin - Uint16 GPIO37:1; // 5 Output Toggle bit for this pin - Uint16 GPIO38:1; // 6 Output Toggle bit for this pin - Uint16 GPIO39:1; // 7 Output Toggle bit for this pin - Uint16 GPIO40:1; // 8 Output Toggle bit for this pin - Uint16 GPIO41:1; // 9 Output Toggle bit for this pin - Uint16 GPIO42:1; // 10 Output Toggle bit for this pin - Uint16 GPIO43:1; // 11 Output Toggle bit for this pin - Uint16 GPIO44:1; // 12 Output Toggle bit for this pin - Uint16 GPIO45:1; // 13 Output Toggle bit for this pin - Uint16 GPIO46:1; // 14 Output Toggle bit for this pin - Uint16 GPIO47:1; // 15 Output Toggle bit for this pin - Uint16 GPIO48:1; // 16 Output Toggle bit for this pin - Uint16 GPIO49:1; // 17 Output Toggle bit for this pin - Uint16 GPIO50:1; // 18 Output Toggle bit for this pin - Uint16 GPIO51:1; // 19 Output Toggle bit for this pin - Uint16 GPIO52:1; // 20 Output Toggle bit for this pin - Uint16 GPIO53:1; // 21 Output Toggle bit for this pin - Uint16 GPIO54:1; // 22 Output Toggle bit for this pin - Uint16 GPIO55:1; // 23 Output Toggle bit for this pin - Uint16 GPIO56:1; // 24 Output Toggle bit for this pin - Uint16 GPIO57:1; // 25 Output Toggle bit for this pin - Uint16 GPIO58:1; // 26 Output Toggle bit for this pin - Uint16 GPIO59:1; // 27 Output Toggle bit for this pin - Uint16 GPIO60:1; // 28 Output Toggle bit for this pin - Uint16 GPIO61:1; // 29 Output Toggle bit for this pin - Uint16 GPIO62:1; // 30 Output Toggle bit for this pin - Uint16 GPIO63:1; // 31 Output Toggle bit for this pin -}; - -union GPBTOGGLE_REG { - Uint32 all; - struct GPBTOGGLE_BITS bit; -}; - -struct GPCDAT_BITS { // bits description - Uint16 GPIO64:1; // 0 Data Register for this pin - Uint16 GPIO65:1; // 1 Data Register for this pin - Uint16 GPIO66:1; // 2 Data Register for this pin - Uint16 GPIO67:1; // 3 Data Register for this pin - Uint16 GPIO68:1; // 4 Data Register for this pin - Uint16 GPIO69:1; // 5 Data Register for this pin - Uint16 GPIO70:1; // 6 Data Register for this pin - Uint16 GPIO71:1; // 7 Data Register for this pin - Uint16 GPIO72:1; // 8 Data Register for this pin - Uint16 GPIO73:1; // 9 Data Register for this pin - Uint16 GPIO74:1; // 10 Data Register for this pin - Uint16 GPIO75:1; // 11 Data Register for this pin - Uint16 GPIO76:1; // 12 Data Register for this pin - Uint16 GPIO77:1; // 13 Data Register for this pin - Uint16 GPIO78:1; // 14 Data Register for this pin - Uint16 GPIO79:1; // 15 Data Register for this pin - Uint16 GPIO80:1; // 16 Data Register for this pin - Uint16 GPIO81:1; // 17 Data Register for this pin - Uint16 GPIO82:1; // 18 Data Register for this pin - Uint16 GPIO83:1; // 19 Data Register for this pin - Uint16 GPIO84:1; // 20 Data Register for this pin - Uint16 GPIO85:1; // 21 Data Register for this pin - Uint16 GPIO86:1; // 22 Data Register for this pin - Uint16 GPIO87:1; // 23 Data Register for this pin - Uint16 GPIO88:1; // 24 Data Register for this pin - Uint16 GPIO89:1; // 25 Data Register for this pin - Uint16 GPIO90:1; // 26 Data Register for this pin - Uint16 GPIO91:1; // 27 Data Register for this pin - Uint16 GPIO92:1; // 28 Data Register for this pin - Uint16 GPIO93:1; // 29 Data Register for this pin - Uint16 GPIO94:1; // 30 Data Register for this pin - Uint16 GPIO95:1; // 31 Data Register for this pin -}; - -union GPCDAT_REG { - Uint32 all; - struct GPCDAT_BITS bit; -}; - -struct GPCSET_BITS { // bits description - Uint16 GPIO64:1; // 0 Output Set bit for this pin - Uint16 GPIO65:1; // 1 Output Set bit for this pin - Uint16 GPIO66:1; // 2 Output Set bit for this pin - Uint16 GPIO67:1; // 3 Output Set bit for this pin - Uint16 GPIO68:1; // 4 Output Set bit for this pin - Uint16 GPIO69:1; // 5 Output Set bit for this pin - Uint16 GPIO70:1; // 6 Output Set bit for this pin - Uint16 GPIO71:1; // 7 Output Set bit for this pin - Uint16 GPIO72:1; // 8 Output Set bit for this pin - Uint16 GPIO73:1; // 9 Output Set bit for this pin - Uint16 GPIO74:1; // 10 Output Set bit for this pin - Uint16 GPIO75:1; // 11 Output Set bit for this pin - Uint16 GPIO76:1; // 12 Output Set bit for this pin - Uint16 GPIO77:1; // 13 Output Set bit for this pin - Uint16 GPIO78:1; // 14 Output Set bit for this pin - Uint16 GPIO79:1; // 15 Output Set bit for this pin - Uint16 GPIO80:1; // 16 Output Set bit for this pin - Uint16 GPIO81:1; // 17 Output Set bit for this pin - Uint16 GPIO82:1; // 18 Output Set bit for this pin - Uint16 GPIO83:1; // 19 Output Set bit for this pin - Uint16 GPIO84:1; // 20 Output Set bit for this pin - Uint16 GPIO85:1; // 21 Output Set bit for this pin - Uint16 GPIO86:1; // 22 Output Set bit for this pin - Uint16 GPIO87:1; // 23 Output Set bit for this pin - Uint16 GPIO88:1; // 24 Output Set bit for this pin - Uint16 GPIO89:1; // 25 Output Set bit for this pin - Uint16 GPIO90:1; // 26 Output Set bit for this pin - Uint16 GPIO91:1; // 27 Output Set bit for this pin - Uint16 GPIO92:1; // 28 Output Set bit for this pin - Uint16 GPIO93:1; // 29 Output Set bit for this pin - Uint16 GPIO94:1; // 30 Output Set bit for this pin - Uint16 GPIO95:1; // 31 Output Set bit for this pin -}; - -union GPCSET_REG { - Uint32 all; - struct GPCSET_BITS bit; -}; - -struct GPCCLEAR_BITS { // bits description - Uint16 GPIO64:1; // 0 Output Clear bit for this pin - Uint16 GPIO65:1; // 1 Output Clear bit for this pin - Uint16 GPIO66:1; // 2 Output Clear bit for this pin - Uint16 GPIO67:1; // 3 Output Clear bit for this pin - Uint16 GPIO68:1; // 4 Output Clear bit for this pin - Uint16 GPIO69:1; // 5 Output Clear bit for this pin - Uint16 GPIO70:1; // 6 Output Clear bit for this pin - Uint16 GPIO71:1; // 7 Output Clear bit for this pin - Uint16 GPIO72:1; // 8 Output Clear bit for this pin - Uint16 GPIO73:1; // 9 Output Clear bit for this pin - Uint16 GPIO74:1; // 10 Output Clear bit for this pin - Uint16 GPIO75:1; // 11 Output Clear bit for this pin - Uint16 GPIO76:1; // 12 Output Clear bit for this pin - Uint16 GPIO77:1; // 13 Output Clear bit for this pin - Uint16 GPIO78:1; // 14 Output Clear bit for this pin - Uint16 GPIO79:1; // 15 Output Clear bit for this pin - Uint16 GPIO80:1; // 16 Output Clear bit for this pin - Uint16 GPIO81:1; // 17 Output Clear bit for this pin - Uint16 GPIO82:1; // 18 Output Clear bit for this pin - Uint16 GPIO83:1; // 19 Output Clear bit for this pin - Uint16 GPIO84:1; // 20 Output Clear bit for this pin - Uint16 GPIO85:1; // 21 Output Clear bit for this pin - Uint16 GPIO86:1; // 22 Output Clear bit for this pin - Uint16 GPIO87:1; // 23 Output Clear bit for this pin - Uint16 GPIO88:1; // 24 Output Clear bit for this pin - Uint16 GPIO89:1; // 25 Output Clear bit for this pin - Uint16 GPIO90:1; // 26 Output Clear bit for this pin - Uint16 GPIO91:1; // 27 Output Clear bit for this pin - Uint16 GPIO92:1; // 28 Output Clear bit for this pin - Uint16 GPIO93:1; // 29 Output Clear bit for this pin - Uint16 GPIO94:1; // 30 Output Clear bit for this pin - Uint16 GPIO95:1; // 31 Output Clear bit for this pin -}; - -union GPCCLEAR_REG { - Uint32 all; - struct GPCCLEAR_BITS bit; -}; - -struct GPCTOGGLE_BITS { // bits description - Uint16 GPIO64:1; // 0 Output Toggle bit for this pin - Uint16 GPIO65:1; // 1 Output Toggle bit for this pin - Uint16 GPIO66:1; // 2 Output Toggle bit for this pin - Uint16 GPIO67:1; // 3 Output Toggle bit for this pin - Uint16 GPIO68:1; // 4 Output Toggle bit for this pin - Uint16 GPIO69:1; // 5 Output Toggle bit for this pin - Uint16 GPIO70:1; // 6 Output Toggle bit for this pin - Uint16 GPIO71:1; // 7 Output Toggle bit for this pin - Uint16 GPIO72:1; // 8 Output Toggle bit for this pin - Uint16 GPIO73:1; // 9 Output Toggle bit for this pin - Uint16 GPIO74:1; // 10 Output Toggle bit for this pin - Uint16 GPIO75:1; // 11 Output Toggle bit for this pin - Uint16 GPIO76:1; // 12 Output Toggle bit for this pin - Uint16 GPIO77:1; // 13 Output Toggle bit for this pin - Uint16 GPIO78:1; // 14 Output Toggle bit for this pin - Uint16 GPIO79:1; // 15 Output Toggle bit for this pin - Uint16 GPIO80:1; // 16 Output Toggle bit for this pin - Uint16 GPIO81:1; // 17 Output Toggle bit for this pin - Uint16 GPIO82:1; // 18 Output Toggle bit for this pin - Uint16 GPIO83:1; // 19 Output Toggle bit for this pin - Uint16 GPIO84:1; // 20 Output Toggle bit for this pin - Uint16 GPIO85:1; // 21 Output Toggle bit for this pin - Uint16 GPIO86:1; // 22 Output Toggle bit for this pin - Uint16 GPIO87:1; // 23 Output Toggle bit for this pin - Uint16 GPIO88:1; // 24 Output Toggle bit for this pin - Uint16 GPIO89:1; // 25 Output Toggle bit for this pin - Uint16 GPIO90:1; // 26 Output Toggle bit for this pin - Uint16 GPIO91:1; // 27 Output Toggle bit for this pin - Uint16 GPIO92:1; // 28 Output Toggle bit for this pin - Uint16 GPIO93:1; // 29 Output Toggle bit for this pin - Uint16 GPIO94:1; // 30 Output Toggle bit for this pin - Uint16 GPIO95:1; // 31 Output Toggle bit for this pin -}; - -union GPCTOGGLE_REG { - Uint32 all; - struct GPCTOGGLE_BITS bit; -}; - -struct GPDDAT_BITS { // bits description - Uint16 GPIO96:1; // 0 Data Register for this pin - Uint16 GPIO97:1; // 1 Data Register for this pin - Uint16 GPIO98:1; // 2 Data Register for this pin - Uint16 GPIO99:1; // 3 Data Register for this pin - Uint16 GPIO100:1; // 4 Data Register for this pin - Uint16 GPIO101:1; // 5 Data Register for this pin - Uint16 GPIO102:1; // 6 Data Register for this pin - Uint16 GPIO103:1; // 7 Data Register for this pin - Uint16 GPIO104:1; // 8 Data Register for this pin - Uint16 GPIO105:1; // 9 Data Register for this pin - Uint16 GPIO106:1; // 10 Data Register for this pin - Uint16 GPIO107:1; // 11 Data Register for this pin - Uint16 GPIO108:1; // 12 Data Register for this pin - Uint16 GPIO109:1; // 13 Data Register for this pin - Uint16 GPIO110:1; // 14 Data Register for this pin - Uint16 GPIO111:1; // 15 Data Register for this pin - Uint16 GPIO112:1; // 16 Data Register for this pin - Uint16 GPIO113:1; // 17 Data Register for this pin - Uint16 GPIO114:1; // 18 Data Register for this pin - Uint16 GPIO115:1; // 19 Data Register for this pin - Uint16 GPIO116:1; // 20 Data Register for this pin - Uint16 GPIO117:1; // 21 Data Register for this pin - Uint16 GPIO118:1; // 22 Data Register for this pin - Uint16 GPIO119:1; // 23 Data Register for this pin - Uint16 GPIO120:1; // 24 Data Register for this pin - Uint16 GPIO121:1; // 25 Data Register for this pin - Uint16 GPIO122:1; // 26 Data Register for this pin - Uint16 GPIO123:1; // 27 Data Register for this pin - Uint16 GPIO124:1; // 28 Data Register for this pin - Uint16 GPIO125:1; // 29 Data Register for this pin - Uint16 GPIO126:1; // 30 Data Register for this pin - Uint16 GPIO127:1; // 31 Data Register for this pin -}; - -union GPDDAT_REG { - Uint32 all; - struct GPDDAT_BITS bit; -}; - -struct GPDSET_BITS { // bits description - Uint16 GPIO96:1; // 0 Output Set bit for this pin - Uint16 GPIO97:1; // 1 Output Set bit for this pin - Uint16 GPIO98:1; // 2 Output Set bit for this pin - Uint16 GPIO99:1; // 3 Output Set bit for this pin - Uint16 GPIO100:1; // 4 Output Set bit for this pin - Uint16 GPIO101:1; // 5 Output Set bit for this pin - Uint16 GPIO102:1; // 6 Output Set bit for this pin - Uint16 GPIO103:1; // 7 Output Set bit for this pin - Uint16 GPIO104:1; // 8 Output Set bit for this pin - Uint16 GPIO105:1; // 9 Output Set bit for this pin - Uint16 GPIO106:1; // 10 Output Set bit for this pin - Uint16 GPIO107:1; // 11 Output Set bit for this pin - Uint16 GPIO108:1; // 12 Output Set bit for this pin - Uint16 GPIO109:1; // 13 Output Set bit for this pin - Uint16 GPIO110:1; // 14 Output Set bit for this pin - Uint16 GPIO111:1; // 15 Output Set bit for this pin - Uint16 GPIO112:1; // 16 Output Set bit for this pin - Uint16 GPIO113:1; // 17 Output Set bit for this pin - Uint16 GPIO114:1; // 18 Output Set bit for this pin - Uint16 GPIO115:1; // 19 Output Set bit for this pin - Uint16 GPIO116:1; // 20 Output Set bit for this pin - Uint16 GPIO117:1; // 21 Output Set bit for this pin - Uint16 GPIO118:1; // 22 Output Set bit for this pin - Uint16 GPIO119:1; // 23 Output Set bit for this pin - Uint16 GPIO120:1; // 24 Output Set bit for this pin - Uint16 GPIO121:1; // 25 Output Set bit for this pin - Uint16 GPIO122:1; // 26 Output Set bit for this pin - Uint16 GPIO123:1; // 27 Output Set bit for this pin - Uint16 GPIO124:1; // 28 Output Set bit for this pin - Uint16 GPIO125:1; // 29 Output Set bit for this pin - Uint16 GPIO126:1; // 30 Output Set bit for this pin - Uint16 GPIO127:1; // 31 Output Set bit for this pin -}; - -union GPDSET_REG { - Uint32 all; - struct GPDSET_BITS bit; -}; - -struct GPDCLEAR_BITS { // bits description - Uint16 GPIO96:1; // 0 Output Clear bit for this pin - Uint16 GPIO97:1; // 1 Output Clear bit for this pin - Uint16 GPIO98:1; // 2 Output Clear bit for this pin - Uint16 GPIO99:1; // 3 Output Clear bit for this pin - Uint16 GPIO100:1; // 4 Output Clear bit for this pin - Uint16 GPIO101:1; // 5 Output Clear bit for this pin - Uint16 GPIO102:1; // 6 Output Clear bit for this pin - Uint16 GPIO103:1; // 7 Output Clear bit for this pin - Uint16 GPIO104:1; // 8 Output Clear bit for this pin - Uint16 GPIO105:1; // 9 Output Clear bit for this pin - Uint16 GPIO106:1; // 10 Output Clear bit for this pin - Uint16 GPIO107:1; // 11 Output Clear bit for this pin - Uint16 GPIO108:1; // 12 Output Clear bit for this pin - Uint16 GPIO109:1; // 13 Output Clear bit for this pin - Uint16 GPIO110:1; // 14 Output Clear bit for this pin - Uint16 GPIO111:1; // 15 Output Clear bit for this pin - Uint16 GPIO112:1; // 16 Output Clear bit for this pin - Uint16 GPIO113:1; // 17 Output Clear bit for this pin - Uint16 GPIO114:1; // 18 Output Clear bit for this pin - Uint16 GPIO115:1; // 19 Output Clear bit for this pin - Uint16 GPIO116:1; // 20 Output Clear bit for this pin - Uint16 GPIO117:1; // 21 Output Clear bit for this pin - Uint16 GPIO118:1; // 22 Output Clear bit for this pin - Uint16 GPIO119:1; // 23 Output Clear bit for this pin - Uint16 GPIO120:1; // 24 Output Clear bit for this pin - Uint16 GPIO121:1; // 25 Output Clear bit for this pin - Uint16 GPIO122:1; // 26 Output Clear bit for this pin - Uint16 GPIO123:1; // 27 Output Clear bit for this pin - Uint16 GPIO124:1; // 28 Output Clear bit for this pin - Uint16 GPIO125:1; // 29 Output Clear bit for this pin - Uint16 GPIO126:1; // 30 Output Clear bit for this pin - Uint16 GPIO127:1; // 31 Output Clear bit for this pin -}; - -union GPDCLEAR_REG { - Uint32 all; - struct GPDCLEAR_BITS bit; -}; - -struct GPDTOGGLE_BITS { // bits description - Uint16 GPIO96:1; // 0 Output Toggle bit for this pin - Uint16 GPIO97:1; // 1 Output Toggle bit for this pin - Uint16 GPIO98:1; // 2 Output Toggle bit for this pin - Uint16 GPIO99:1; // 3 Output Toggle bit for this pin - Uint16 GPIO100:1; // 4 Output Toggle bit for this pin - Uint16 GPIO101:1; // 5 Output Toggle bit for this pin - Uint16 GPIO102:1; // 6 Output Toggle bit for this pin - Uint16 GPIO103:1; // 7 Output Toggle bit for this pin - Uint16 GPIO104:1; // 8 Output Toggle bit for this pin - Uint16 GPIO105:1; // 9 Output Toggle bit for this pin - Uint16 GPIO106:1; // 10 Output Toggle bit for this pin - Uint16 GPIO107:1; // 11 Output Toggle bit for this pin - Uint16 GPIO108:1; // 12 Output Toggle bit for this pin - Uint16 GPIO109:1; // 13 Output Toggle bit for this pin - Uint16 GPIO110:1; // 14 Output Toggle bit for this pin - Uint16 GPIO111:1; // 15 Output Toggle bit for this pin - Uint16 GPIO112:1; // 16 Output Toggle bit for this pin - Uint16 GPIO113:1; // 17 Output Toggle bit for this pin - Uint16 GPIO114:1; // 18 Output Toggle bit for this pin - Uint16 GPIO115:1; // 19 Output Toggle bit for this pin - Uint16 GPIO116:1; // 20 Output Toggle bit for this pin - Uint16 GPIO117:1; // 21 Output Toggle bit for this pin - Uint16 GPIO118:1; // 22 Output Toggle bit for this pin - Uint16 GPIO119:1; // 23 Output Toggle bit for this pin - Uint16 GPIO120:1; // 24 Output Toggle bit for this pin - Uint16 GPIO121:1; // 25 Output Toggle bit for this pin - Uint16 GPIO122:1; // 26 Output Toggle bit for this pin - Uint16 GPIO123:1; // 27 Output Toggle bit for this pin - Uint16 GPIO124:1; // 28 Output Toggle bit for this pin - Uint16 GPIO125:1; // 29 Output Toggle bit for this pin - Uint16 GPIO126:1; // 30 Output Toggle bit for this pin - Uint16 GPIO127:1; // 31 Output Toggle bit for this pin -}; - -union GPDTOGGLE_REG { - Uint32 all; - struct GPDTOGGLE_BITS bit; -}; - -struct GPEDAT_BITS { // bits description - Uint16 GPIO128:1; // 0 Data Register for this pin - Uint16 GPIO129:1; // 1 Data Register for this pin - Uint16 GPIO130:1; // 2 Data Register for this pin - Uint16 GPIO131:1; // 3 Data Register for this pin - Uint16 GPIO132:1; // 4 Data Register for this pin - Uint16 GPIO133:1; // 5 Data Register for this pin - Uint16 GPIO134:1; // 6 Data Register for this pin - Uint16 GPIO135:1; // 7 Data Register for this pin - Uint16 GPIO136:1; // 8 Data Register for this pin - Uint16 GPIO137:1; // 9 Data Register for this pin - Uint16 GPIO138:1; // 10 Data Register for this pin - Uint16 GPIO139:1; // 11 Data Register for this pin - Uint16 GPIO140:1; // 12 Data Register for this pin - Uint16 GPIO141:1; // 13 Data Register for this pin - Uint16 GPIO142:1; // 14 Data Register for this pin - Uint16 GPIO143:1; // 15 Data Register for this pin - Uint16 GPIO144:1; // 16 Data Register for this pin - Uint16 GPIO145:1; // 17 Data Register for this pin - Uint16 GPIO146:1; // 18 Data Register for this pin - Uint16 GPIO147:1; // 19 Data Register for this pin - Uint16 GPIO148:1; // 20 Data Register for this pin - Uint16 GPIO149:1; // 21 Data Register for this pin - Uint16 GPIO150:1; // 22 Data Register for this pin - Uint16 GPIO151:1; // 23 Data Register for this pin - Uint16 GPIO152:1; // 24 Data Register for this pin - Uint16 GPIO153:1; // 25 Data Register for this pin - Uint16 GPIO154:1; // 26 Data Register for this pin - Uint16 GPIO155:1; // 27 Data Register for this pin - Uint16 GPIO156:1; // 28 Data Register for this pin - Uint16 GPIO157:1; // 29 Data Register for this pin - Uint16 GPIO158:1; // 30 Data Register for this pin - Uint16 GPIO159:1; // 31 Data Register for this pin -}; - -union GPEDAT_REG { - Uint32 all; - struct GPEDAT_BITS bit; -}; - -struct GPESET_BITS { // bits description - Uint16 GPIO128:1; // 0 Output Set bit for this pin - Uint16 GPIO129:1; // 1 Output Set bit for this pin - Uint16 GPIO130:1; // 2 Output Set bit for this pin - Uint16 GPIO131:1; // 3 Output Set bit for this pin - Uint16 GPIO132:1; // 4 Output Set bit for this pin - Uint16 GPIO133:1; // 5 Output Set bit for this pin - Uint16 GPIO134:1; // 6 Output Set bit for this pin - Uint16 GPIO135:1; // 7 Output Set bit for this pin - Uint16 GPIO136:1; // 8 Output Set bit for this pin - Uint16 GPIO137:1; // 9 Output Set bit for this pin - Uint16 GPIO138:1; // 10 Output Set bit for this pin - Uint16 GPIO139:1; // 11 Output Set bit for this pin - Uint16 GPIO140:1; // 12 Output Set bit for this pin - Uint16 GPIO141:1; // 13 Output Set bit for this pin - Uint16 GPIO142:1; // 14 Output Set bit for this pin - Uint16 GPIO143:1; // 15 Output Set bit for this pin - Uint16 GPIO144:1; // 16 Output Set bit for this pin - Uint16 GPIO145:1; // 17 Output Set bit for this pin - Uint16 GPIO146:1; // 18 Output Set bit for this pin - Uint16 GPIO147:1; // 19 Output Set bit for this pin - Uint16 GPIO148:1; // 20 Output Set bit for this pin - Uint16 GPIO149:1; // 21 Output Set bit for this pin - Uint16 GPIO150:1; // 22 Output Set bit for this pin - Uint16 GPIO151:1; // 23 Output Set bit for this pin - Uint16 GPIO152:1; // 24 Output Set bit for this pin - Uint16 GPIO153:1; // 25 Output Set bit for this pin - Uint16 GPIO154:1; // 26 Output Set bit for this pin - Uint16 GPIO155:1; // 27 Output Set bit for this pin - Uint16 GPIO156:1; // 28 Output Set bit for this pin - Uint16 GPIO157:1; // 29 Output Set bit for this pin - Uint16 GPIO158:1; // 30 Output Set bit for this pin - Uint16 GPIO159:1; // 31 Output Set bit for this pin -}; - -union GPESET_REG { - Uint32 all; - struct GPESET_BITS bit; -}; - -struct GPECLEAR_BITS { // bits description - Uint16 GPIO128:1; // 0 Output Clear bit for this pin - Uint16 GPIO129:1; // 1 Output Clear bit for this pin - Uint16 GPIO130:1; // 2 Output Clear bit for this pin - Uint16 GPIO131:1; // 3 Output Clear bit for this pin - Uint16 GPIO132:1; // 4 Output Clear bit for this pin - Uint16 GPIO133:1; // 5 Output Clear bit for this pin - Uint16 GPIO134:1; // 6 Output Clear bit for this pin - Uint16 GPIO135:1; // 7 Output Clear bit for this pin - Uint16 GPIO136:1; // 8 Output Clear bit for this pin - Uint16 GPIO137:1; // 9 Output Clear bit for this pin - Uint16 GPIO138:1; // 10 Output Clear bit for this pin - Uint16 GPIO139:1; // 11 Output Clear bit for this pin - Uint16 GPIO140:1; // 12 Output Clear bit for this pin - Uint16 GPIO141:1; // 13 Output Clear bit for this pin - Uint16 GPIO142:1; // 14 Output Clear bit for this pin - Uint16 GPIO143:1; // 15 Output Clear bit for this pin - Uint16 GPIO144:1; // 16 Output Clear bit for this pin - Uint16 GPIO145:1; // 17 Output Clear bit for this pin - Uint16 GPIO146:1; // 18 Output Clear bit for this pin - Uint16 GPIO147:1; // 19 Output Clear bit for this pin - Uint16 GPIO148:1; // 20 Output Clear bit for this pin - Uint16 GPIO149:1; // 21 Output Clear bit for this pin - Uint16 GPIO150:1; // 22 Output Clear bit for this pin - Uint16 GPIO151:1; // 23 Output Clear bit for this pin - Uint16 GPIO152:1; // 24 Output Clear bit for this pin - Uint16 GPIO153:1; // 25 Output Clear bit for this pin - Uint16 GPIO154:1; // 26 Output Clear bit for this pin - Uint16 GPIO155:1; // 27 Output Clear bit for this pin - Uint16 GPIO156:1; // 28 Output Clear bit for this pin - Uint16 GPIO157:1; // 29 Output Clear bit for this pin - Uint16 GPIO158:1; // 30 Output Clear bit for this pin - Uint16 GPIO159:1; // 31 Output Clear bit for this pin -}; - -union GPECLEAR_REG { - Uint32 all; - struct GPECLEAR_BITS bit; -}; - -struct GPETOGGLE_BITS { // bits description - Uint16 GPIO128:1; // 0 Output Toggle bit for this pin - Uint16 GPIO129:1; // 1 Output Toggle bit for this pin - Uint16 GPIO130:1; // 2 Output Toggle bit for this pin - Uint16 GPIO131:1; // 3 Output Toggle bit for this pin - Uint16 GPIO132:1; // 4 Output Toggle bit for this pin - Uint16 GPIO133:1; // 5 Output Toggle bit for this pin - Uint16 GPIO134:1; // 6 Output Toggle bit for this pin - Uint16 GPIO135:1; // 7 Output Toggle bit for this pin - Uint16 GPIO136:1; // 8 Output Toggle bit for this pin - Uint16 GPIO137:1; // 9 Output Toggle bit for this pin - Uint16 GPIO138:1; // 10 Output Toggle bit for this pin - Uint16 GPIO139:1; // 11 Output Toggle bit for this pin - Uint16 GPIO140:1; // 12 Output Toggle bit for this pin - Uint16 GPIO141:1; // 13 Output Toggle bit for this pin - Uint16 GPIO142:1; // 14 Output Toggle bit for this pin - Uint16 GPIO143:1; // 15 Output Toggle bit for this pin - Uint16 GPIO144:1; // 16 Output Toggle bit for this pin - Uint16 GPIO145:1; // 17 Output Toggle bit for this pin - Uint16 GPIO146:1; // 18 Output Toggle bit for this pin - Uint16 GPIO147:1; // 19 Output Toggle bit for this pin - Uint16 GPIO148:1; // 20 Output Toggle bit for this pin - Uint16 GPIO149:1; // 21 Output Toggle bit for this pin - Uint16 GPIO150:1; // 22 Output Toggle bit for this pin - Uint16 GPIO151:1; // 23 Output Toggle bit for this pin - Uint16 GPIO152:1; // 24 Output Toggle bit for this pin - Uint16 GPIO153:1; // 25 Output Toggle bit for this pin - Uint16 GPIO154:1; // 26 Output Toggle bit for this pin - Uint16 GPIO155:1; // 27 Output Toggle bit for this pin - Uint16 GPIO156:1; // 28 Output Toggle bit for this pin - Uint16 GPIO157:1; // 29 Output Toggle bit for this pin - Uint16 GPIO158:1; // 30 Output Toggle bit for this pin - Uint16 GPIO159:1; // 31 Output Toggle bit for this pin -}; - -union GPETOGGLE_REG { - Uint32 all; - struct GPETOGGLE_BITS bit; -}; - -struct GPFDAT_BITS { // bits description - Uint16 GPIO160:1; // 0 Data Register for this pin - Uint16 GPIO161:1; // 1 Data Register for this pin - Uint16 GPIO162:1; // 2 Data Register for this pin - Uint16 GPIO163:1; // 3 Data Register for this pin - Uint16 GPIO164:1; // 4 Data Register for this pin - Uint16 GPIO165:1; // 5 Data Register for this pin - Uint16 GPIO166:1; // 6 Data Register for this pin - Uint16 GPIO167:1; // 7 Data Register for this pin - Uint16 GPIO168:1; // 8 Data Register for this pin - Uint16 rsvd1:1; // 9 Reserved - Uint16 rsvd2:1; // 10 Reserved - Uint16 rsvd3:1; // 11 Reserved - Uint16 rsvd4:1; // 12 Reserved - Uint16 rsvd5:1; // 13 Reserved - Uint16 rsvd6:1; // 14 Reserved - Uint16 rsvd7:1; // 15 Reserved - Uint16 rsvd8:1; // 16 Reserved - Uint16 rsvd9:1; // 17 Reserved - Uint16 rsvd10:1; // 18 Reserved - Uint16 rsvd11:1; // 19 Reserved - Uint16 rsvd12:1; // 20 Reserved - Uint16 rsvd13:1; // 21 Reserved - Uint16 rsvd14:1; // 22 Reserved - Uint16 rsvd15:1; // 23 Reserved - Uint16 rsvd16:1; // 24 Reserved - Uint16 rsvd17:1; // 25 Reserved - Uint16 rsvd18:1; // 26 Reserved - Uint16 rsvd19:1; // 27 Reserved - Uint16 rsvd20:1; // 28 Reserved - Uint16 rsvd21:1; // 29 Reserved - Uint16 rsvd22:1; // 30 Reserved - Uint16 rsvd23:1; // 31 Reserved -}; - -union GPFDAT_REG { - Uint32 all; - struct GPFDAT_BITS bit; -}; - -struct GPFSET_BITS { // bits description - Uint16 GPIO160:1; // 0 Output Set bit for this pin - Uint16 GPIO161:1; // 1 Output Set bit for this pin - Uint16 GPIO162:1; // 2 Output Set bit for this pin - Uint16 GPIO163:1; // 3 Output Set bit for this pin - Uint16 GPIO164:1; // 4 Output Set bit for this pin - Uint16 GPIO165:1; // 5 Output Set bit for this pin - Uint16 GPIO166:1; // 6 Output Set bit for this pin - Uint16 GPIO167:1; // 7 Output Set bit for this pin - Uint16 GPIO168:1; // 8 Output Set bit for this pin - Uint16 rsvd1:1; // 9 Reserved - Uint16 rsvd2:1; // 10 Reserved - Uint16 rsvd3:1; // 11 Reserved - Uint16 rsvd4:1; // 12 Reserved - Uint16 rsvd5:1; // 13 Reserved - Uint16 rsvd6:1; // 14 Reserved - Uint16 rsvd7:1; // 15 Reserved - Uint16 rsvd8:1; // 16 Reserved - Uint16 rsvd9:1; // 17 Reserved - Uint16 rsvd10:1; // 18 Reserved - Uint16 rsvd11:1; // 19 Reserved - Uint16 rsvd12:1; // 20 Reserved - Uint16 rsvd13:1; // 21 Reserved - Uint16 rsvd14:1; // 22 Reserved - Uint16 rsvd15:1; // 23 Reserved - Uint16 rsvd16:1; // 24 Reserved - Uint16 rsvd17:1; // 25 Reserved - Uint16 rsvd18:1; // 26 Reserved - Uint16 rsvd19:1; // 27 Reserved - Uint16 rsvd20:1; // 28 Reserved - Uint16 rsvd21:1; // 29 Reserved - Uint16 rsvd22:1; // 30 Reserved - Uint16 rsvd23:1; // 31 Reserved -}; - -union GPFSET_REG { - Uint32 all; - struct GPFSET_BITS bit; -}; - -struct GPFCLEAR_BITS { // bits description - Uint16 GPIO160:1; // 0 Output Clear bit for this pin - Uint16 GPIO161:1; // 1 Output Clear bit for this pin - Uint16 GPIO162:1; // 2 Output Clear bit for this pin - Uint16 GPIO163:1; // 3 Output Clear bit for this pin - Uint16 GPIO164:1; // 4 Output Clear bit for this pin - Uint16 GPIO165:1; // 5 Output Clear bit for this pin - Uint16 GPIO166:1; // 6 Output Clear bit for this pin - Uint16 GPIO167:1; // 7 Output Clear bit for this pin - Uint16 GPIO168:1; // 8 Output Clear bit for this pin - Uint16 rsvd1:1; // 9 Reserved - Uint16 rsvd2:1; // 10 Reserved - Uint16 rsvd3:1; // 11 Reserved - Uint16 rsvd4:1; // 12 Reserved - Uint16 rsvd5:1; // 13 Reserved - Uint16 rsvd6:1; // 14 Reserved - Uint16 rsvd7:1; // 15 Reserved - Uint16 rsvd8:1; // 16 Reserved - Uint16 rsvd9:1; // 17 Reserved - Uint16 rsvd10:1; // 18 Reserved - Uint16 rsvd11:1; // 19 Reserved - Uint16 rsvd12:1; // 20 Reserved - Uint16 rsvd13:1; // 21 Reserved - Uint16 rsvd14:1; // 22 Reserved - Uint16 rsvd15:1; // 23 Reserved - Uint16 rsvd16:1; // 24 Reserved - Uint16 rsvd17:1; // 25 Reserved - Uint16 rsvd18:1; // 26 Reserved - Uint16 rsvd19:1; // 27 Reserved - Uint16 rsvd20:1; // 28 Reserved - Uint16 rsvd21:1; // 29 Reserved - Uint16 rsvd22:1; // 30 Reserved - Uint16 rsvd23:1; // 31 Reserved -}; - -union GPFCLEAR_REG { - Uint32 all; - struct GPFCLEAR_BITS bit; -}; - -struct GPFTOGGLE_BITS { // bits description - Uint16 GPIO160:1; // 0 Output Toggle bit for this pin - Uint16 GPIO161:1; // 1 Output Toggle bit for this pin - Uint16 GPIO162:1; // 2 Output Toggle bit for this pin - Uint16 GPIO163:1; // 3 Output Toggle bit for this pin - Uint16 GPIO164:1; // 4 Output Toggle bit for this pin - Uint16 GPIO165:1; // 5 Output Toggle bit for this pin - Uint16 GPIO166:1; // 6 Output Toggle bit for this pin - Uint16 GPIO167:1; // 7 Output Toggle bit for this pin - Uint16 GPIO168:1; // 8 Output Toggle bit for this pin - Uint16 rsvd1:1; // 9 Reserved - Uint16 rsvd2:1; // 10 Reserved - Uint16 rsvd3:1; // 11 Reserved - Uint16 rsvd4:1; // 12 Reserved - Uint16 rsvd5:1; // 13 Reserved - Uint16 rsvd6:1; // 14 Reserved - Uint16 rsvd7:1; // 15 Reserved - Uint16 rsvd8:1; // 16 Reserved - Uint16 rsvd9:1; // 17 Reserved - Uint16 rsvd10:1; // 18 Reserved - Uint16 rsvd11:1; // 19 Reserved - Uint16 rsvd12:1; // 20 Reserved - Uint16 rsvd13:1; // 21 Reserved - Uint16 rsvd14:1; // 22 Reserved - Uint16 rsvd15:1; // 23 Reserved - Uint16 rsvd16:1; // 24 Reserved - Uint16 rsvd17:1; // 25 Reserved - Uint16 rsvd18:1; // 26 Reserved - Uint16 rsvd19:1; // 27 Reserved - Uint16 rsvd20:1; // 28 Reserved - Uint16 rsvd21:1; // 29 Reserved - Uint16 rsvd22:1; // 30 Reserved - Uint16 rsvd23:1; // 31 Reserved -}; - -union GPFTOGGLE_REG { - Uint32 all; - struct GPFTOGGLE_BITS bit; -}; - -struct GPIO_DATA_REGS { - union GPADAT_REG GPADAT; // GPIO A Data Register (GPIO0 to 31) - union GPASET_REG GPASET; // GPIO A Data Set Register (GPIO0 to 31) - union GPACLEAR_REG GPACLEAR; // GPIO A Data Clear Register (GPIO0 to 31) - union GPATOGGLE_REG GPATOGGLE; // GPIO A Data Toggle Register (GPIO0 to 31) - union GPBDAT_REG GPBDAT; // GPIO B Data Register (GPIO32 to 63) - union GPBSET_REG GPBSET; // GPIO B Data Set Register (GPIO32 to 63) - union GPBCLEAR_REG GPBCLEAR; // GPIO B Data Clear Register (GPIO32 to 63) - union GPBTOGGLE_REG GPBTOGGLE; // GPIO B Data Toggle Register (GPIO32 to 63) - union GPCDAT_REG GPCDAT; // GPIO C Data Register (GPIO64 to 95) - union GPCSET_REG GPCSET; // GPIO C Data Set Register (GPIO64 to 95) - union GPCCLEAR_REG GPCCLEAR; // GPIO C Data Clear Register (GPIO64 to 95) - union GPCTOGGLE_REG GPCTOGGLE; // GPIO C Data Toggle Register (GPIO64 to 95) - union GPDDAT_REG GPDDAT; // GPIO D Data Register (GPIO96 to 127) - union GPDSET_REG GPDSET; // GPIO D Data Set Register (GPIO96 to 127) - union GPDCLEAR_REG GPDCLEAR; // GPIO D Data Clear Register (GPIO96 to 127) - union GPDTOGGLE_REG GPDTOGGLE; // GPIO D Data Toggle Register (GPIO96 to 127) - union GPEDAT_REG GPEDAT; // GPIO E Data Register (GPIO128 to 159) - union GPESET_REG GPESET; // GPIO E Data Set Register (GPIO128 to 159) - union GPECLEAR_REG GPECLEAR; // GPIO E Data Clear Register (GPIO128 to 159) - union GPETOGGLE_REG GPETOGGLE; // GPIO E Data Toggle Register (GPIO128 to 159) - union GPFDAT_REG GPFDAT; // GPIO F Data Register (GPIO160 to 168) - union GPFSET_REG GPFSET; // GPIO F Data Set Register (GPIO160 to 168) - union GPFCLEAR_REG GPFCLEAR; // GPIO F Data Clear Register (GPIO160 to 168) - union GPFTOGGLE_REG GPFTOGGLE; // GPIO F Data Toggle Register (GPIO160 to 168) -}; - -//--------------------------------------------------------------------------- -// GPIO External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; -extern volatile struct GPIO_DATA_REGS GpioDataRegs; -#endif -#ifdef CPU2 -extern volatile struct GPIO_DATA_REGS GpioDataRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_i2c.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_i2c.h deleted file mode 100644 index 470f5a398d..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_i2c.h +++ /dev/null @@ -1,256 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_i2c.h -// -// TITLE: I2C Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_I2C_H__ -#define __F2837xD_I2C_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// I2C Individual Register Bit Definitions: - -struct I2COAR_BITS { // bits description - Uint16 OAR:10; // 9:0 I2C Own address - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union I2COAR_REG { - Uint16 all; - struct I2COAR_BITS bit; -}; - -struct I2CIER_BITS { // bits description - Uint16 ARBL:1; // 0 Arbitration-lost interrupt enable - Uint16 NACK:1; // 1 No-acknowledgment interrupt enable - Uint16 ARDY:1; // 2 Register-access-ready interrupt enable - Uint16 RRDY:1; // 3 Receive-data-ready interrupt enable - Uint16 XRDY:1; // 4 Transmit-data-ready interrupt enable - Uint16 SCD:1; // 5 Stop condition detected interrupt enable - Uint16 AAS:1; // 6 Addressed as slave interrupt enable - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union I2CIER_REG { - Uint16 all; - struct I2CIER_BITS bit; -}; - -struct I2CSTR_BITS { // bits description - Uint16 ARBL:1; // 0 Arbitration-lost interrupt flag bit - Uint16 NACK:1; // 1 No-acknowledgment interrupt flag bit. - Uint16 ARDY:1; // 2 Register-access-ready interrupt flag bit - Uint16 RRDY:1; // 3 Receive-data-ready interrupt flag bit. - Uint16 XRDY:1; // 4 Transmit-data-ready interrupt flag bit. - Uint16 SCD:1; // 5 Stop condition detected bit. - Uint16 rsvd1:2; // 7:6 Reserved - Uint16 AD0:1; // 8 Address 0 bits - Uint16 AAS:1; // 9 Addressed-as-slave bit - Uint16 XSMT:1; // 10 Transmit shift register empty bit. - Uint16 RSFULL:1; // 11 Receive shift register full bit. - Uint16 BB:1; // 12 Bus busy bit. - Uint16 NACKSNT:1; // 13 NACK sent bit. - Uint16 SDIR:1; // 14 Slave direction bit - Uint16 rsvd2:1; // 15 Reserved -}; - -union I2CSTR_REG { - Uint16 all; - struct I2CSTR_BITS bit; -}; - -struct I2CDRR_BITS { // bits description - Uint16 DATA:8; // 7:0 Receive data - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union I2CDRR_REG { - Uint16 all; - struct I2CDRR_BITS bit; -}; - -struct I2CSAR_BITS { // bits description - Uint16 SAR:10; // 9:0 Slave Address - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union I2CSAR_REG { - Uint16 all; - struct I2CSAR_BITS bit; -}; - -struct I2CDXR_BITS { // bits description - Uint16 DATA:8; // 7:0 Transmit data - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union I2CDXR_REG { - Uint16 all; - struct I2CDXR_BITS bit; -}; - -struct I2CMDR_BITS { // bits description - Uint16 BC:3; // 2:0 Bit count bits. - Uint16 FDF:1; // 3 Free Data Format - Uint16 STB:1; // 4 START Byte Mode - Uint16 IRS:1; // 5 I2C Module Reset - Uint16 DLB:1; // 6 Digital Loopback Mode - Uint16 RM:1; // 7 Repeat Mode - Uint16 XA:1; // 8 Expanded Address Mode - Uint16 TRX:1; // 9 Transmitter Mode - Uint16 MST:1; // 10 Master Mode - Uint16 STP:1; // 11 STOP Condition - Uint16 rsvd1:1; // 12 Reserved - Uint16 STT:1; // 13 START condition bit - Uint16 FREE:1; // 14 Debug Action - Uint16 NACKMOD:1; // 15 NACK mode bit -}; - -union I2CMDR_REG { - Uint16 all; - struct I2CMDR_BITS bit; -}; - -struct I2CISRC_BITS { // bits description - Uint16 INTCODE:3; // 2:0 Interrupt code bits. - Uint16 rsvd1:5; // 7:3 Reserved - Uint16 WRITE_ZEROS:4; // 11:8 Reserved - Uint16 rsvd2:4; // 15:12 Reserved -}; - -union I2CISRC_REG { - Uint16 all; - struct I2CISRC_BITS bit; -}; - -struct I2CEMDR_BITS { // bits description - Uint16 BC:1; // 0 Backwards compatibility mode - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union I2CEMDR_REG { - Uint16 all; - struct I2CEMDR_BITS bit; -}; - -struct I2CPSC_BITS { // bits description - Uint16 IPSC:8; // 7:0 I2C Prescaler Divide Down - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union I2CPSC_REG { - Uint16 all; - struct I2CPSC_BITS bit; -}; - -struct I2CFFTX_BITS { // bits description - Uint16 TXFFIL:5; // 4:0 Transmit FIFO Interrupt Level - Uint16 TXFFIENA:1; // 5 Transmit FIFO Interrupt Enable - Uint16 TXFFINTCLR:1; // 6 Transmit FIFO Interrupt Flag Clear - Uint16 TXFFINT:1; // 7 Transmit FIFO Interrupt Flag - Uint16 TXFFST:5; // 12:8 Transmit FIFO Status - Uint16 TXFFRST:1; // 13 Transmit FIFO Reset - Uint16 I2CFFEN:1; // 14 Transmit FIFO Enable - Uint16 rsvd1:1; // 15 Reserved -}; - -union I2CFFTX_REG { - Uint16 all; - struct I2CFFTX_BITS bit; -}; - -struct I2CFFRX_BITS { // bits description - Uint16 RXFFIL:5; // 4:0 Receive FIFO Interrupt Level - Uint16 RXFFIENA:1; // 5 Receive FIFO Interrupt Enable - Uint16 RXFFINTCLR:1; // 6 Receive FIFO Interrupt Flag Clear - Uint16 RXFFINT:1; // 7 Receive FIFO Interrupt Flag - Uint16 RXFFST:5; // 12:8 Receive FIFO Status - Uint16 RXFFRST:1; // 13 Receive FIFO Reset - Uint16 rsvd1:2; // 15:14 Reserved -}; - -union I2CFFRX_REG { - Uint16 all; - struct I2CFFRX_BITS bit; -}; - -struct I2C_REGS { - union I2COAR_REG I2COAR; // I2C Own address - union I2CIER_REG I2CIER; // I2C Interrupt Enable - union I2CSTR_REG I2CSTR; // I2C Status - Uint16 I2CCLKL; // I2C Clock low-time divider - Uint16 I2CCLKH; // I2C Clock high-time divider - Uint16 I2CCNT; // I2C Data count - union I2CDRR_REG I2CDRR; // I2C Data receive - union I2CSAR_REG I2CSAR; // I2C Slave address - union I2CDXR_REG I2CDXR; // I2C Data Transmit - union I2CMDR_REG I2CMDR; // I2C Mode - union I2CISRC_REG I2CISRC; // I2C Interrupt Source - union I2CEMDR_REG I2CEMDR; // I2C Extended Mode - union I2CPSC_REG I2CPSC; // I2C Prescaler - Uint16 rsvd1[19]; // Reserved - union I2CFFTX_REG I2CFFTX; // I2C FIFO Transmit - union I2CFFRX_REG I2CFFRX; // I2C FIFO Receive -}; - -//--------------------------------------------------------------------------- -// I2C External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct I2C_REGS I2caRegs; -extern volatile struct I2C_REGS I2cbRegs; -#endif -#ifdef CPU2 -extern volatile struct I2C_REGS I2caRegs; -extern volatile struct I2C_REGS I2cbRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_input_xbar.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_input_xbar.h deleted file mode 100644 index ef3abbe3ab..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_input_xbar.h +++ /dev/null @@ -1,112 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_input_xbar.h -// -// TITLE: INPUT_XBAR Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_INPUT_XBAR_H__ -#define __F2837xD_INPUT_XBAR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// INPUT_XBAR Individual Register Bit Definitions: - -struct INPUTSELECTLOCK_BITS { // bits description - Uint16 INPUT1SELECT:1; // 0 Lock bit for INPUT1SEL Register - Uint16 INPUT2SELECT:1; // 1 Lock bit for INPUT2SEL Register - Uint16 INPUT3SELECT:1; // 2 Lock bit for INPUT3SEL Register - Uint16 INPUT4SELECT:1; // 3 Lock bit for INPUT4SEL Register - Uint16 INPUT5SELECT:1; // 4 Lock bit for INPUT5SEL Register - Uint16 INPUT6SELECT:1; // 5 Lock bit for INPUT7SEL Register - Uint16 INPUT7SELECT:1; // 6 Lock bit for INPUT8SEL Register - Uint16 INPUT8SELECT:1; // 7 Lock bit for INPUT9SEL Register - Uint16 INPUT9SELECT:1; // 8 Lock bit for INPUT10SEL Register - Uint16 INPUT10SELECT:1; // 9 Lock bit for INPUT11SEL Register - Uint16 INPUT11SELECT:1; // 10 Lock bit for INPUT11SEL Register - Uint16 INPUT12SELECT:1; // 11 Lock bit for INPUT12SEL Register - Uint16 INPUT13SELECT:1; // 12 Lock bit for INPUT13SEL Register - Uint16 INPUT14SELECT:1; // 13 Lock bit for INPUT14SEL Register - Uint16 INPUT15SELECT:1; // 14 Lock bit for INPUT15SEL Register - Uint16 INPUT16SELECT:1; // 15 Lock bit for INPUT16SEL Register - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union INPUTSELECTLOCK_REG { - Uint32 all; - struct INPUTSELECTLOCK_BITS bit; -}; - -struct INPUT_XBAR_REGS { - Uint16 INPUT1SELECT; // INPUT1 Input Select Register (GPIO0 to x) - Uint16 INPUT2SELECT; // INPUT2 Input Select Register (GPIO0 to x) - Uint16 INPUT3SELECT; // INPUT3 Input Select Register (GPIO0 to x) - Uint16 INPUT4SELECT; // INPUT4 Input Select Register (GPIO0 to x) - Uint16 INPUT5SELECT; // INPUT5 Input Select Register (GPIO0 to x) - Uint16 INPUT6SELECT; // INPUT6 Input Select Register (GPIO0 to x) - Uint16 INPUT7SELECT; // INPUT7 Input Select Register (GPIO0 to x) - Uint16 INPUT8SELECT; // INPUT8 Input Select Register (GPIO0 to x) - Uint16 INPUT9SELECT; // INPUT9 Input Select Register (GPIO0 to x) - Uint16 INPUT10SELECT; // INPUT10 Input Select Register (GPIO0 to x) - Uint16 INPUT11SELECT; // INPUT11 Input Select Register (GPIO0 to x) - Uint16 INPUT12SELECT; // INPUT12 Input Select Register (GPIO0 to x) - Uint16 INPUT13SELECT; // INPUT13 Input Select Register (GPIO0 to x) - Uint16 INPUT14SELECT; // INPUT14 Input Select Register (GPIO0 to x) - Uint16 rsvd1[16]; // Reserved - union INPUTSELECTLOCK_REG INPUTSELECTLOCK; // Input Select Lock Register -}; - -//--------------------------------------------------------------------------- -// INPUT_XBAR External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct INPUT_XBAR_REGS InputXbarRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_ipc.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_ipc.h deleted file mode 100644 index 411ef4c80b..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_ipc.h +++ /dev/null @@ -1,313 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_ipc.h -// -// TITLE: IPC Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_IPC_H__ -#define __F2837xD_IPC_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// IPC Individual Register Bit Definitions: - -struct IPCACK_BITS { // bits description - Uint16 IPC0:1; // 0 Local IPC Flag 0 Acknowledgement - Uint16 IPC1:1; // 1 Local IPC Flag 1 Acknowledgement - Uint16 IPC2:1; // 2 Local IPC Flag 2 Acknowledgement - Uint16 IPC3:1; // 3 Local IPC Flag 3 Acknowledgement - Uint16 IPC4:1; // 4 Local IPC Flag 4 Acknowledgement - Uint16 IPC5:1; // 5 Local IPC Flag 5 Acknowledgement - Uint16 IPC6:1; // 6 Local IPC Flag 6 Acknowledgement - Uint16 IPC7:1; // 7 Local IPC Flag 7 Acknowledgement - Uint16 IPC8:1; // 8 Local IPC Flag 8 Acknowledgement - Uint16 IPC9:1; // 9 Local IPC Flag 9 Acknowledgement - Uint16 IPC10:1; // 10 Local IPC Flag 10 Acknowledgement - Uint16 IPC11:1; // 11 Local IPC Flag 11 Acknowledgement - Uint16 IPC12:1; // 12 Local IPC Flag 12 Acknowledgement - Uint16 IPC13:1; // 13 Local IPC Flag 13 Acknowledgement - Uint16 IPC14:1; // 14 Local IPC Flag 14 Acknowledgement - Uint16 IPC15:1; // 15 Local IPC Flag 15 Acknowledgement - Uint16 IPC16:1; // 16 Local IPC Flag 16 Acknowledgement - Uint16 IPC17:1; // 17 Local IPC Flag 17 Acknowledgement - Uint16 IPC18:1; // 18 Local IPC Flag 18 Acknowledgement - Uint16 IPC19:1; // 19 Local IPC Flag 19 Acknowledgement - Uint16 IPC20:1; // 20 Local IPC Flag 20 Acknowledgement - Uint16 IPC21:1; // 21 Local IPC Flag 21 Acknowledgement - Uint16 IPC22:1; // 22 Local IPC Flag 22 Acknowledgement - Uint16 IPC23:1; // 23 Local IPC Flag 23 Acknowledgement - Uint16 IPC24:1; // 24 Local IPC Flag 24 Acknowledgement - Uint16 IPC25:1; // 25 Local IPC Flag 25 Acknowledgement - Uint16 IPC26:1; // 26 Local IPC Flag 26 Acknowledgement - Uint16 IPC27:1; // 27 Local IPC Flag 27 Acknowledgement - Uint16 IPC28:1; // 28 Local IPC Flag 28 Acknowledgement - Uint16 IPC29:1; // 29 Local IPC Flag 29 Acknowledgement - Uint16 IPC30:1; // 30 Local IPC Flag 30 Acknowledgement - Uint16 IPC31:1; // 31 Local IPC Flag 31 Acknowledgement -}; - -union IPCACK_REG { - Uint32 all; - struct IPCACK_BITS bit; -}; - -struct IPCSTS_BITS { // bits description - Uint16 IPC0:1; // 0 Local IPC Flag 0 Status - Uint16 IPC1:1; // 1 Local IPC Flag 1 Status - Uint16 IPC2:1; // 2 Local IPC Flag 2 Status - Uint16 IPC3:1; // 3 Local IPC Flag 3 Status - Uint16 IPC4:1; // 4 Local IPC Flag 4 Status - Uint16 IPC5:1; // 5 Local IPC Flag 5 Status - Uint16 IPC6:1; // 6 Local IPC Flag 6 Status - Uint16 IPC7:1; // 7 Local IPC Flag 7 Status - Uint16 IPC8:1; // 8 Local IPC Flag 8 Status - Uint16 IPC9:1; // 9 Local IPC Flag 9 Status - Uint16 IPC10:1; // 10 Local IPC Flag 10 Status - Uint16 IPC11:1; // 11 Local IPC Flag 11 Status - Uint16 IPC12:1; // 12 Local IPC Flag 12 Status - Uint16 IPC13:1; // 13 Local IPC Flag 13 Status - Uint16 IPC14:1; // 14 Local IPC Flag 14 Status - Uint16 IPC15:1; // 15 Local IPC Flag 15 Status - Uint16 IPC16:1; // 16 Local IPC Flag 16 Status - Uint16 IPC17:1; // 17 Local IPC Flag 17 Status - Uint16 IPC18:1; // 18 Local IPC Flag 18 Status - Uint16 IPC19:1; // 19 Local IPC Flag 19 Status - Uint16 IPC20:1; // 20 Local IPC Flag 20 Status - Uint16 IPC21:1; // 21 Local IPC Flag 21 Status - Uint16 IPC22:1; // 22 Local IPC Flag 22 Status - Uint16 IPC23:1; // 23 Local IPC Flag 23 Status - Uint16 IPC24:1; // 24 Local IPC Flag 24 Status - Uint16 IPC25:1; // 25 Local IPC Flag 25 Status - Uint16 IPC26:1; // 26 Local IPC Flag 26 Status - Uint16 IPC27:1; // 27 Local IPC Flag 27 Status - Uint16 IPC28:1; // 28 Local IPC Flag 28 Status - Uint16 IPC29:1; // 29 Local IPC Flag 29 Status - Uint16 IPC30:1; // 30 Local IPC Flag 30 Status - Uint16 IPC31:1; // 31 Local IPC Flag 31 Status -}; - -union IPCSTS_REG { - Uint32 all; - struct IPCSTS_BITS bit; -}; - -struct IPCSET_BITS { // bits description - Uint16 IPC0:1; // 0 Set Remote IPC0 Flag - Uint16 IPC1:1; // 1 Set Remote IPC1 Flag - Uint16 IPC2:1; // 2 Set Remote IPC2 Flag - Uint16 IPC3:1; // 3 Set Remote IPC3 Flag - Uint16 IPC4:1; // 4 Set Remote IPC4 Flag - Uint16 IPC5:1; // 5 Set Remote IPC5 Flag - Uint16 IPC6:1; // 6 Set Remote IPC6 Flag - Uint16 IPC7:1; // 7 Set Remote IPC7 Flag - Uint16 IPC8:1; // 8 Set Remote IPC8 Flag - Uint16 IPC9:1; // 9 Set Remote IPC9 Flag - Uint16 IPC10:1; // 10 Set Remote IPC10 Flag - Uint16 IPC11:1; // 11 Set Remote IPC11 Flag - Uint16 IPC12:1; // 12 Set Remote IPC12 Flag - Uint16 IPC13:1; // 13 Set Remote IPC13 Flag - Uint16 IPC14:1; // 14 Set Remote IPC14 Flag - Uint16 IPC15:1; // 15 Set Remote IPC15 Flag - Uint16 IPC16:1; // 16 Set Remote IPC16 Flag - Uint16 IPC17:1; // 17 Set Remote IPC17 Flag - Uint16 IPC18:1; // 18 Set Remote IPC18 Flag - Uint16 IPC19:1; // 19 Set Remote IPC19 Flag - Uint16 IPC20:1; // 20 Set Remote IPC20 Flag - Uint16 IPC21:1; // 21 Set Remote IPC21 Flag - Uint16 IPC22:1; // 22 Set Remote IPC22 Flag - Uint16 IPC23:1; // 23 Set Remote IPC23 Flag - Uint16 IPC24:1; // 24 Set Remote IPC24 Flag - Uint16 IPC25:1; // 25 Set Remote IPC25 Flag - Uint16 IPC26:1; // 26 Set Remote IPC26 Flag - Uint16 IPC27:1; // 27 Set Remote IPC27 Flag - Uint16 IPC28:1; // 28 Set Remote IPC28 Flag - Uint16 IPC29:1; // 29 Set Remote IPC29 Flag - Uint16 IPC30:1; // 30 Set Remote IPC30 Flag - Uint16 IPC31:1; // 31 Set Remote IPC31 Flag -}; - -union IPCSET_REG { - Uint32 all; - struct IPCSET_BITS bit; -}; - -struct IPCCLR_BITS { // bits description - Uint16 IPC0:1; // 0 Clear Remote IPC0 Flag - Uint16 IPC1:1; // 1 Clear Remote IPC1 Flag - Uint16 IPC2:1; // 2 Clear Remote IPC2 Flag - Uint16 IPC3:1; // 3 Clear Remote IPC3 Flag - Uint16 IPC4:1; // 4 Clear Remote IPC4 Flag - Uint16 IPC5:1; // 5 Clear Remote IPC5 Flag - Uint16 IPC6:1; // 6 Clear Remote IPC6 Flag - Uint16 IPC7:1; // 7 Clear Remote IPC7 Flag - Uint16 IPC8:1; // 8 Clear Remote IPC8 Flag - Uint16 IPC9:1; // 9 Clear Remote IPC9 Flag - Uint16 IPC10:1; // 10 Clear Remote IPC10 Flag - Uint16 IPC11:1; // 11 Clear Remote IPC11 Flag - Uint16 IPC12:1; // 12 Clear Remote IPC12 Flag - Uint16 IPC13:1; // 13 Clear Remote IPC13 Flag - Uint16 IPC14:1; // 14 Clear Remote IPC14 Flag - Uint16 IPC15:1; // 15 Clear Remote IPC15 Flag - Uint16 IPC16:1; // 16 Clear Remote IPC16 Flag - Uint16 IPC17:1; // 17 Clear Remote IPC17 Flag - Uint16 IPC18:1; // 18 Clear Remote IPC18 Flag - Uint16 IPC19:1; // 19 Clear Remote IPC19 Flag - Uint16 IPC20:1; // 20 Clear Remote IPC20 Flag - Uint16 IPC21:1; // 21 Clear Remote IPC21 Flag - Uint16 IPC22:1; // 22 Clear Remote IPC22 Flag - Uint16 IPC23:1; // 23 Clear Remote IPC23 Flag - Uint16 IPC24:1; // 24 Clear Remote IPC24 Flag - Uint16 IPC25:1; // 25 Clear Remote IPC25 Flag - Uint16 IPC26:1; // 26 Clear Remote IPC26 Flag - Uint16 IPC27:1; // 27 Clear Remote IPC27 Flag - Uint16 IPC28:1; // 28 Clear Remote IPC28 Flag - Uint16 IPC29:1; // 29 Clear Remote IPC29 Flag - Uint16 IPC30:1; // 30 Clear Remote IPC30 Flag - Uint16 IPC31:1; // 31 Clear Remote IPC31 Flag -}; - -union IPCCLR_REG { - Uint32 all; - struct IPCCLR_BITS bit; -}; - -struct IPCFLG_BITS { // bits description - Uint16 IPC0:1; // 0 Remote IPC0 Flag Status - Uint16 IPC1:1; // 1 Remote IPC1 Flag Status - Uint16 IPC2:1; // 2 Remote IPC2 Flag Status - Uint16 IPC3:1; // 3 Remote IPC3 Flag Status - Uint16 IPC4:1; // 4 Remote IPC4 Flag Status - Uint16 IPC5:1; // 5 Remote IPC5 Flag Status - Uint16 IPC6:1; // 6 Remote IPC6 Flag Status - Uint16 IPC7:1; // 7 Remote IPC7 Flag Status - Uint16 IPC8:1; // 8 Remote IPC8 Flag Status - Uint16 IPC9:1; // 9 Remote IPC9 Flag Status - Uint16 IPC10:1; // 10 Remote IPC10 Flag Status - Uint16 IPC11:1; // 11 Remote IPC11 Flag Status - Uint16 IPC12:1; // 12 Remote IPC12 Flag Status - Uint16 IPC13:1; // 13 Remote IPC13 Flag Status - Uint16 IPC14:1; // 14 Remote IPC14 Flag Status - Uint16 IPC15:1; // 15 Remote IPC15 Flag Status - Uint16 IPC16:1; // 16 Remote IPC16 Flag Status - Uint16 IPC17:1; // 17 Remote IPC17 Flag Status - Uint16 IPC18:1; // 18 Remote IPC18 Flag Status - Uint16 IPC19:1; // 19 Remote IPC19 Flag Status - Uint16 IPC20:1; // 20 Remote IPC20 Flag Status - Uint16 IPC21:1; // 21 Remote IPC21 Flag Status - Uint16 IPC22:1; // 22 Remote IPC22 Flag Status - Uint16 IPC23:1; // 23 Remote IPC23 Flag Status - Uint16 IPC24:1; // 24 Remote IPC24 Flag Status - Uint16 IPC25:1; // 25 Remote IPC25 Flag Status - Uint16 IPC26:1; // 26 Remote IPC26 Flag Status - Uint16 IPC27:1; // 27 Remote IPC27 Flag Status - Uint16 IPC28:1; // 28 Remote IPC28 Flag Status - Uint16 IPC29:1; // 29 Remote IPC29 Flag Status - Uint16 IPC30:1; // 30 Remote IPC30 Flag Status - Uint16 IPC31:1; // 31 Remote IPC31 Flag Status -}; - -union IPCFLG_REG { - Uint32 all; - struct IPCFLG_BITS bit; -}; - -struct IPC_REGS_CPU1 { - union IPCACK_REG IPCACK; // IPC incoming flag clear (acknowledge) register - union IPCSTS_REG IPCSTS; // IPC incoming flag status register - union IPCSET_REG IPCSET; // IPC remote flag set register - union IPCCLR_REG IPCCLR; // IPC remote flag clear register - union IPCFLG_REG IPCFLG; // IPC remote flag status register - Uint16 rsvd1[2]; // Reserved - Uint32 IPCCOUNTERL; // IPC Counter Low Register - Uint32 IPCCOUNTERH; // IPC Counter High Register - Uint32 IPCSENDCOM; // Local to Remote IPC Command Register - Uint32 IPCSENDADDR; // Local to Remote IPC Address Register - Uint32 IPCSENDDATA; // Local to Remote IPC Data Register - Uint32 IPCREMOTEREPLY; // Remote to Local IPC Reply Data Register - Uint32 IPCRECVCOM; // Remote to Local IPC Command Register - Uint32 IPCRECVADDR; // Remote to Local IPC Address Register - Uint32 IPCRECVDATA; // Remote to Local IPC Data Register - Uint32 IPCLOCALREPLY; // Local to Remote IPC Reply Data Register - Uint32 IPCBOOTSTS; // CPU2 to CPU1 IPC Boot Status Register - Uint32 IPCBOOTMODE; // CPU1 to CPU2 IPC Boot Mode Register -}; - -struct IPC_REGS_CPU2 { - union IPCACK_REG IPCACK; // IPC incoming flag clear (acknowledge) register - union IPCSTS_REG IPCSTS; // IPC incoming flag status register - union IPCSET_REG IPCSET; // IPC remote flag set register - union IPCCLR_REG IPCCLR; // IPC remote flag clear register - union IPCFLG_REG IPCFLG; // IPC remote flag status register - Uint16 rsvd1[2]; // Reserved - Uint32 IPCCOUNTERL; // IPC Counter Low Register - Uint32 IPCCOUNTERH; // IPC Counter High Register - Uint32 IPCRECVCOM; // Remote to Local IPC Command Register - Uint32 IPCRECVADDR; // Remote to Local IPC Address Register - Uint32 IPCRECVDATA; // Remote to Local IPC Data Register - Uint32 IPCLOCALREPLY; // Local to Remote IPC Reply Data Register - Uint32 IPCSENDCOM; // Local to Remote IPC Command Register - Uint32 IPCSENDADDR; // Local to Remote IPC Address Register - Uint32 IPCSENDDATA; // Local to Remote IPC Data Register - Uint32 IPCREMOTEREPLY; // Remote to Local IPC Reply Data Register - Uint32 IPCBOOTSTS; // CPU2 to CPU1 IPC Boot Status Register - Uint32 IPCBOOTMODE; // CPU1 to CPU2 IPC Boot Mode Register -}; - -//--------------------------------------------------------------------------- -// IPC External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct IPC_REGS_CPU1 IpcRegs; -#endif -#ifdef CPU2 -extern volatile struct IPC_REGS_CPU2 IpcRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_mcbsp.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_mcbsp.h deleted file mode 100644 index 0f94e76030..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_mcbsp.h +++ /dev/null @@ -1,323 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_mcbsp.h -// -// TITLE: MCBSP Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_MCBSP_H__ -#define __F2837xD_MCBSP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// MCBSP Individual Register Bit Definitions: - -struct DRR2_BITS { // bits description - Uint16 HWLB:8; // 7:0 High word low byte - Uint16 HWHB:8; // 15:8 High word high byte -}; - -union DRR2_REG { - Uint16 all; - struct DRR2_BITS bit; -}; - -struct DRR1_BITS { // bits description - Uint16 LWLB:8; // 7:0 Low word low byte - Uint16 LWHB:8; // 15:8 Low word high byte -}; - -union DRR1_REG { - Uint16 all; - struct DRR1_BITS bit; -}; - -struct DXR2_BITS { // bits description - Uint16 HWLB:8; // 7:0 High word low byte - Uint16 HWHB:8; // 15:8 High word high byte -}; - -union DXR2_REG { - Uint16 all; - struct DXR2_BITS bit; -}; - -struct DXR1_BITS { // bits description - Uint16 LWLB:8; // 7:0 Low word low byte - Uint16 LWHB:8; // 15:8 Low word high byte -}; - -union DXR1_REG { - Uint16 all; - struct DXR1_BITS bit; -}; - -struct SPCR2_BITS { // bits description - Uint16 XRST:1; // 0 Transmitter reset - Uint16 XRDY:1; // 1 Transmitter ready - Uint16 XEMPTY:1; // 2 Transmitter empty - Uint16 XSYNCERR:1; // 3 Transmit sync error INT flag - Uint16 XINTM:2; // 5:4 Transmit Interupt mode bits - Uint16 GRST:1; // 6 Sample rate generator reset - Uint16 FRST:1; // 7 Frame sync logic reset - Uint16 SOFT:1; // 8 SOFT bit - Uint16 FREE:1; // 9 FREE bit - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union SPCR2_REG { - Uint16 all; - struct SPCR2_BITS bit; -}; - -struct SPCR1_BITS { // bits description - Uint16 RRST:1; // 0 Receiver reset - Uint16 RRDY:1; // 1 Receiver ready - Uint16 RFULL:1; // 2 Receiver full - Uint16 RSYNCERR:1; // 3 Receive sync error INT flag - Uint16 RINTM:2; // 5:4 Receive Interupt mode bits - Uint16 rsvd1:1; // 6 Reserved - Uint16 DXENA:1; // 7 DX delay enable - Uint16 rsvd2:3; // 10:8 Reserved - Uint16 CLKSTP:2; // 12:11 Clock stop mode - Uint16 RJUST:2; // 14:13 Rx sign extension and justification mode - Uint16 DLB:1; // 15 Digital loopback -}; - -union SPCR1_REG { - Uint16 all; - struct SPCR1_BITS bit; -}; - -struct RCR2_BITS { // bits description - Uint16 RDATDLY:2; // 1:0 Receive data delay - Uint16 RFIG:1; // 2 Receive frame sync ignore - Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects - Uint16 RWDLEN2:3; // 7:5 Receive word length 2 - Uint16 RFRLEN2:7; // 14:8 Receive Frame length 2 - Uint16 RPHASE:1; // 15 Receive Phase -}; - -union RCR2_REG { - Uint16 all; - struct RCR2_BITS bit; -}; - -struct RCR1_BITS { // bits description - Uint16 rsvd1:5; // 4:0 Reserved - Uint16 RWDLEN1:3; // 7:5 Receive word length 1 - Uint16 RFRLEN1:7; // 14:8 Receive Frame length 1 - Uint16 rsvd2:1; // 15 Reserved -}; - -union RCR1_REG { - Uint16 all; - struct RCR1_BITS bit; -}; - -struct XCR2_BITS { // bits description - Uint16 XDATDLY:2; // 1:0 Transmit data delay - Uint16 XFIG:1; // 2 Transmit frame sync ignore - Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects - Uint16 XWDLEN2:3; // 7:5 Transmit word length 2 - Uint16 XFRLEN2:7; // 14:8 Transmit Frame length 2 - Uint16 XPHASE:1; // 15 Transmit Phase -}; - -union XCR2_REG { - Uint16 all; - struct XCR2_BITS bit; -}; - -struct XCR1_BITS { // bits description - Uint16 rsvd1:5; // 4:0 Reserved - Uint16 XWDLEN1:3; // 7:5 Transmit word length 1 - Uint16 XFRLEN1:7; // 14:8 Transmit Frame length 1 - Uint16 rsvd2:1; // 15 Reserved -}; - -union XCR1_REG { - Uint16 all; - struct XCR1_BITS bit; -}; - -struct SRGR2_BITS { // bits description - Uint16 FPER:12; // 11:0 Frame-sync period - Uint16 FSGM:1; // 12 Frame sync generator mode - Uint16 CLKSM:1; // 13 Sample rate generator mode - Uint16 rsvd1:1; // 14 Reserved - Uint16 GSYNC:1; // 15 CLKG sync -}; - -union SRGR2_REG { - Uint16 all; - struct SRGR2_BITS bit; -}; - -struct SRGR1_BITS { // bits description - Uint16 CLKGDV:8; // 7:0 CLKG divider - Uint16 FWID:8; // 15:8 Frame width -}; - -union SRGR1_REG { - Uint16 all; - struct SRGR1_BITS bit; -}; - -struct MCR2_BITS { // bits description - Uint16 XMCM:2; // 1:0 Transmit data delay - Uint16 XCBLK:3; // 4:2 Transmit frame sync ignore - Uint16 XPABLK:2; // 6:5 Transmit Companding Mode selects - Uint16 XPBBLK:2; // 8:7 Transmit word length 2 - Uint16 XMCME:1; // 9 Transmit Frame length 2 - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union MCR2_REG { - Uint16 all; - struct MCR2_BITS bit; -}; - -struct MCR1_BITS { // bits description - Uint16 RMCM:1; // 0 Receive multichannel mode - Uint16 rsvd1:1; // 1 Reserved - Uint16 RCBLK:3; // 4:2 eceive current block - Uint16 RPABLK:2; // 6:5 Receive partition A Block - Uint16 RPBBLK:2; // 8:7 Receive partition B Block - Uint16 RMCME:1; // 9 Receive multi-channel enhance mode - Uint16 rsvd2:6; // 15:10 Reserved -}; - -union MCR1_REG { - Uint16 all; - struct MCR1_BITS bit; -}; - -struct PCR_BITS { // bits description - Uint16 CLKRP:1; // 0 Receive Clock polarity - Uint16 CLKXP:1; // 1 Transmit clock polarity - Uint16 FSRP:1; // 2 Receive Frame synchronization polarity - Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 SCLKME:1; // 7 Sample clock mode selection - Uint16 CLKRM:1; // 8 Receiver Clock Mode - Uint16 CLKXM:1; // 9 Transmit Clock Mode. - Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode - Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode - Uint16 rsvd4:4; // 15:12 Reserved -}; - -union PCR_REG { - Uint16 all; - struct PCR_BITS bit; -}; - -struct MFFINT_BITS { // bits description - Uint16 XINT:1; // 0 Enable for Receive Interrupt - Uint16 rsvd1:1; // 1 Reserved - Uint16 RINT:1; // 2 Enable for transmit Interrupt - Uint16 rsvd2:13; // 15:3 Reserved -}; - -union MFFINT_REG { - Uint16 all; - struct MFFINT_BITS bit; -}; - -struct McBSP_REGS { - union DRR2_REG DRR2; // Data receive register bits 31-16 - union DRR1_REG DRR1; // Data receive register bits 15-0 - union DXR2_REG DXR2; // Data transmit register bits 31-16 - union DXR1_REG DXR1; // Data transmit register bits 15-0 - union SPCR2_REG SPCR2; // Control register 2 - union SPCR1_REG SPCR1; // Control register 1 - union RCR2_REG RCR2; // Receive Control register 2 - union RCR1_REG RCR1; // Receive Control register 1 - union XCR2_REG XCR2; // Transmit Control register 2 - union XCR1_REG XCR1; // Transmit Control register 1 - union SRGR2_REG SRGR2; // Sample rate generator register 2 - union SRGR1_REG SRGR1; // Sample rate generator register 1 - union MCR2_REG MCR2; // Multi-channel register 2 - union MCR1_REG MCR1; // Multi-channel register 1 - Uint16 RCERA; // Receive channel enable partition A - Uint16 RCERB; // Receive channel enable partition B - Uint16 XCERA; // Transmit channel enable partition A - Uint16 XCERB; // Transmit channel enable partition B - union PCR_REG PCR; // Pin Control register - Uint16 RCERC; // Receive channel enable partition C - Uint16 RCERD; // Receive channel enable partition D - Uint16 XCERC; // Transmit channel enable partition C - Uint16 XCERD; // Transmit channel enable partition D - Uint16 RCERE; // Receive channel enable partition E - Uint16 RCERF; // Receive channel enable partition F - Uint16 XCERE; // Transmit channel enable partition E - Uint16 XCERF; // Transmit channel enable partition F - Uint16 RCERG; // Receive channel enable partition G - Uint16 RCERH; // Receive channel enable partition H - Uint16 XCERG; // Transmit channel enable partition G - Uint16 XCERH; // Transmit channel enable partition H - Uint16 rsvd1[4]; // Reserved - union MFFINT_REG MFFINT; // Interrupt enable -}; - -//--------------------------------------------------------------------------- -// MCBSP External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct McBSP_REGS McbspaRegs; -extern volatile struct McBSP_REGS McbspbRegs; -#endif -#ifdef CPU2 -extern volatile struct McBSP_REGS McbspaRegs; -extern volatile struct McBSP_REGS McbspbRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_memconfig.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_memconfig.h deleted file mode 100644 index 9dcf877d3c..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_memconfig.h +++ /dev/null @@ -1,1071 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_memconfig.h -// -// TITLE: MEMCONFIG Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_MEMCONFIG_H__ -#define __F2837xD_MEMCONFIG_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// MEMCONFIG Individual Register Bit Definitions: - -struct DxLOCK_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 LOCK_D0:1; // 2 D0 RAM access protection and master select fields lock bit - Uint16 LOCK_D1:1; // 3 D1 RAM access protection and master select fields lock bit - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union DxLOCK_REG { - Uint32 all; - struct DxLOCK_BITS bit; -}; - -struct DxCOMMIT_BITS { // bits description - Uint16 rsvd1:2; // 1:0 Reserved - Uint16 COMMIT_D0:1; // 2 D0 RAM access protection and master select permanent lock - Uint16 COMMIT_D1:1; // 3 D1 RAM access protection and master select permanent lock - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union DxCOMMIT_REG { - Uint32 all; - struct DxCOMMIT_BITS bit; -}; - -struct DxACCPROT0_BITS { // bits description - Uint16 rsvd1:16; // 15:0 Reserved - Uint16 FETCHPROT_D0:1; // 16 Fetch Protection For D0 RAM - Uint16 CPUWRPROT_D0:1; // 17 CPU WR Protection For D0 RAM - Uint16 rsvd2:6; // 23:18 Reserved - Uint16 FETCHPROT_D1:1; // 24 Fetch Protection For D1 RAM - Uint16 CPUWRPROT_D1:1; // 25 CPU WR Protection For D1 RAM - Uint16 rsvd3:6; // 31:26 Reserved -}; - -union DxACCPROT0_REG { - Uint32 all; - struct DxACCPROT0_BITS bit; -}; - -struct DxTEST_BITS { // bits description - Uint16 TEST_M0:2; // 1:0 Selects the different modes for M0 RAM - Uint16 TEST_M1:2; // 3:2 Selects the different modes for M1 RAM - Uint16 TEST_D0:2; // 5:4 Selects the different modes for D0 RAM - Uint16 TEST_D1:2; // 7:6 Selects the different modes for D1 RAM - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DxTEST_REG { - Uint32 all; - struct DxTEST_BITS bit; -}; - -struct DxINIT_BITS { // bits description - Uint16 INIT_M0:1; // 0 RAM Initialization control for M0 RAM. - Uint16 INIT_M1:1; // 1 RAM Initialization control for M1 RAM. - Uint16 INIT_D0:1; // 2 RAM Initialization control for D0 RAM. - Uint16 INIT_D1:1; // 3 RAM Initialization control for D1 RAM. - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DxINIT_REG { - Uint32 all; - struct DxINIT_BITS bit; -}; - -struct DxINITDONE_BITS { // bits description - Uint16 INITDONE_M0:1; // 0 RAM Initialization status for M0 RAM. - Uint16 INITDONE_M1:1; // 1 RAM Initialization status for M1 RAM. - Uint16 INITDONE_D0:1; // 2 RAM Initialization status for D0 RAM. - Uint16 INITDONE_D1:1; // 3 RAM Initialization status for D1 RAM. - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DxINITDONE_REG { - Uint32 all; - struct DxINITDONE_BITS bit; -}; - -struct LSxLOCK_BITS { // bits description - Uint16 LOCK_LS0:1; // 0 LS0 RAM access protection and master select fields lock bit - Uint16 LOCK_LS1:1; // 1 LS1 RAM access protection and master select fields lock bit - Uint16 LOCK_LS2:1; // 2 LS2 RAM access protection and master select fields lock bit - Uint16 LOCK_LS3:1; // 3 LS3 RAM access protection and master select fields lock bit - Uint16 LOCK_LS4:1; // 4 LS4 RAM access protection and master select fields lock bit - Uint16 LOCK_LS5:1; // 5 LS5 RAM access protection and master select fields lock bit - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxLOCK_REG { - Uint32 all; - struct LSxLOCK_BITS bit; -}; - -struct LSxCOMMIT_BITS { // bits description - Uint16 COMMIT_LS0:1; // 0 LS0 RAM access protection and master select permanent lock - Uint16 COMMIT_LS1:1; // 1 LS1 RAM access protection and master select permanent lock - Uint16 COMMIT_LS2:1; // 2 LS2 RAM access protection and master select permanent lock - Uint16 COMMIT_LS3:1; // 3 LS3 RAM access protection and master select permanent lock - Uint16 COMMIT_LS4:1; // 4 LS4 RAM access protection and master select permanent lock - Uint16 COMMIT_LS5:1; // 5 LS5 RAM access protection and master select permanent lock - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxCOMMIT_REG { - Uint32 all; - struct LSxCOMMIT_BITS bit; -}; - -struct LSxMSEL_BITS { // bits description - Uint16 MSEL_LS0:2; // 1:0 Master Select for LS0 RAM - Uint16 MSEL_LS1:2; // 3:2 Master Select for LS1 RAM - Uint16 MSEL_LS2:2; // 5:4 Master Select for LS2 RAM - Uint16 MSEL_LS3:2; // 7:6 Master Select for LS3 RAM - Uint16 MSEL_LS4:2; // 9:8 Master Select for LS4 RAM - Uint16 MSEL_LS5:2; // 11:10 Master Select for LS5 RAM - Uint16 rsvd1:4; // 15:12 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxMSEL_REG { - Uint32 all; - struct LSxMSEL_BITS bit; -}; - -struct LSxCLAPGM_BITS { // bits description - Uint16 CLAPGM_LS0:1; // 0 Selects LS0 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS1:1; // 1 Selects LS1 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS2:1; // 2 Selects LS2 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS3:1; // 3 Selects LS3 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS4:1; // 4 Selects LS4 RAM as program vs data memory for CLA - Uint16 CLAPGM_LS5:1; // 5 Selects LS5 RAM as program vs data memory for CLA - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxCLAPGM_REG { - Uint32 all; - struct LSxCLAPGM_BITS bit; -}; - -struct LSxACCPROT0_BITS { // bits description - Uint16 FETCHPROT_LS0:1; // 0 Fetch Protection For LS0 RAM - Uint16 CPUWRPROT_LS0:1; // 1 CPU WR Protection For LS0 RAM - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 FETCHPROT_LS1:1; // 8 Fetch Protection For LS1 RAM - Uint16 CPUWRPROT_LS1:1; // 9 CPU WR Protection For LS1 RAM - Uint16 rsvd2:6; // 15:10 Reserved - Uint16 FETCHPROT_LS2:1; // 16 Fetch Protection For LS2 RAM - Uint16 CPUWRPROT_LS2:1; // 17 CPU WR Protection For LS2 RAM - Uint16 rsvd3:6; // 23:18 Reserved - Uint16 FETCHPROT_LS3:1; // 24 Fetch Protection For LS3 RAM - Uint16 CPUWRPROT_LS3:1; // 25 CPU WR Protection For LS3 RAM - Uint16 rsvd4:6; // 31:26 Reserved -}; - -union LSxACCPROT0_REG { - Uint32 all; - struct LSxACCPROT0_BITS bit; -}; - -struct LSxACCPROT1_BITS { // bits description - Uint16 FETCHPROT_LS4:1; // 0 Fetch Protection For LS4 RAM - Uint16 CPUWRPROT_LS4:1; // 1 CPU WR Protection For LS4 RAM - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 FETCHPROT_LS5:1; // 8 Fetch Protection For LS5 RAM - Uint16 CPUWRPROT_LS5:1; // 9 CPU WR Protection For LS5 RAM - Uint16 rsvd2:6; // 15:10 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union LSxACCPROT1_REG { - Uint32 all; - struct LSxACCPROT1_BITS bit; -}; - -struct LSxTEST_BITS { // bits description - Uint16 TEST_LS0:2; // 1:0 Selects the different modes for LS0 RAM - Uint16 TEST_LS1:2; // 3:2 Selects the different modes for LS1 RAM - Uint16 TEST_LS2:2; // 5:4 Selects the different modes for LS2 RAM - Uint16 TEST_LS3:2; // 7:6 Selects the different modes for LS3 RAM - Uint16 TEST_LS4:2; // 9:8 Selects the different modes for LS4 RAM - Uint16 TEST_LS5:2; // 11:10 Selects the different modes for LS5 RAM - Uint16 rsvd1:4; // 15:12 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxTEST_REG { - Uint32 all; - struct LSxTEST_BITS bit; -}; - -struct LSxINIT_BITS { // bits description - Uint16 INIT_LS0:1; // 0 RAM Initialization control for LS0 RAM. - Uint16 INIT_LS1:1; // 1 RAM Initialization control for LS1 RAM. - Uint16 INIT_LS2:1; // 2 RAM Initialization control for LS2 RAM. - Uint16 INIT_LS3:1; // 3 RAM Initialization control for LS3 RAM. - Uint16 INIT_LS4:1; // 4 RAM Initialization control for LS4 RAM. - Uint16 INIT_LS5:1; // 5 RAM Initialization control for LS5 RAM. - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxINIT_REG { - Uint32 all; - struct LSxINIT_BITS bit; -}; - -struct LSxINITDONE_BITS { // bits description - Uint16 INITDONE_LS0:1; // 0 RAM Initialization status for LS0 RAM. - Uint16 INITDONE_LS1:1; // 1 RAM Initialization status for LS1 RAM. - Uint16 INITDONE_LS2:1; // 2 RAM Initialization status for LS2 RAM. - Uint16 INITDONE_LS3:1; // 3 RAM Initialization status for LS3 RAM. - Uint16 INITDONE_LS4:1; // 4 RAM Initialization status for LS4 RAM. - Uint16 INITDONE_LS5:1; // 5 RAM Initialization status for LS5 RAM. - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LSxINITDONE_REG { - Uint32 all; - struct LSxINITDONE_BITS bit; -}; - -struct GSxLOCK_BITS { // bits description - Uint16 LOCK_GS0:1; // 0 GS0 RAM access protection and master select fields lock bit - Uint16 LOCK_GS1:1; // 1 GS1 RAM access protection and master select fields lock bit - Uint16 LOCK_GS2:1; // 2 GS2 RAM access protection and master select fields lock bit - Uint16 LOCK_GS3:1; // 3 GS3 RAM access protection and master select fields lock bit - Uint16 LOCK_GS4:1; // 4 GS4 RAM access protection and master select fields lock bit - Uint16 LOCK_GS5:1; // 5 GS5 RAM access protection and master select fields lock bit - Uint16 LOCK_GS6:1; // 6 GS6 RAM access protection and master select fields lock bit - Uint16 LOCK_GS7:1; // 7 GS7 RAM access protection and master select fields lock bit - Uint16 LOCK_GS8:1; // 8 GS8 RAM access protection and master select fields lock bit - Uint16 LOCK_GS9:1; // 9 GS9 RAM access protection and master select fields lock bit - Uint16 LOCK_GS10:1; // 10 GS10 RAM access protection and master select fields lock bit - Uint16 LOCK_GS11:1; // 11 GS11 RAM access protection and master select fields lock bit - Uint16 LOCK_GS12:1; // 12 GS12 RAM access protection and master select fields lock bit - Uint16 LOCK_GS13:1; // 13 GS13 RAM access protection and master select fields lock bit - Uint16 LOCK_GS14:1; // 14 GS14 RAM access protection and master select fields lock bit - Uint16 LOCK_GS15:1; // 15 GS15 RAM access protection and master select fields lock bit - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union GSxLOCK_REG { - Uint32 all; - struct GSxLOCK_BITS bit; -}; - -struct GSxCOMMIT_BITS { // bits description - Uint16 COMMIT_GS0:1; // 0 GS0 RAM access protection and master select permanent lock - Uint16 COMMIT_GS1:1; // 1 GS1 RAM access protection and master select permanent lock - Uint16 COMMIT_GS2:1; // 2 GS2 RAM access protection and master select permanent lock - Uint16 COMMIT_GS3:1; // 3 GS3 RAM access protection and master select permanent lock - Uint16 COMMIT_GS4:1; // 4 GS4 RAM access protection and master select permanent lock - Uint16 COMMIT_GS5:1; // 5 GS5 RAM access protection and master select permanent lock - Uint16 COMMIT_GS6:1; // 6 GS6 RAM access protection and master select permanent lock - Uint16 COMMIT_GS7:1; // 7 GS7 RAM access protection and master select permanent lock - Uint16 COMMIT_GS8:1; // 8 GS8 RAM access protection and master select permanent lock - Uint16 COMMIT_GS9:1; // 9 GS9 RAM access protection and master select permanent lock - Uint16 COMMIT_GS10:1; // 10 GS10 RAM access protection and master select permanent lock - Uint16 COMMIT_GS11:1; // 11 GS11 RAM access protection and master select permanent lock - Uint16 COMMIT_GS12:1; // 12 GS12 RAM access protection and master select permanent lock - Uint16 COMMIT_GS13:1; // 13 GS13 RAM access protection and master select permanent lock - Uint16 COMMIT_GS14:1; // 14 GS14 RAM access protection and master select permanent lock - Uint16 COMMIT_GS15:1; // 15 GS15 RAM access protection and master select permanent lock - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union GSxCOMMIT_REG { - Uint32 all; - struct GSxCOMMIT_BITS bit; -}; - -struct GSxMSEL_BITS { // bits description - Uint16 MSEL_GS0:1; // 0 Master Select for GS0 RAM - Uint16 MSEL_GS1:1; // 1 Master Select for GS1 RAM - Uint16 MSEL_GS2:1; // 2 Master Select for GS2 RAM - Uint16 MSEL_GS3:1; // 3 Master Select for GS3 RAM - Uint16 MSEL_GS4:1; // 4 Master Select for GS4 RAM - Uint16 MSEL_GS5:1; // 5 Master Select for GS5 RAM - Uint16 MSEL_GS6:1; // 6 Master Select for GS6 RAM - Uint16 MSEL_GS7:1; // 7 Master Select for GS7 RAM - Uint16 MSEL_GS8:1; // 8 Master Select for GS8 RAM - Uint16 MSEL_GS9:1; // 9 Master Select for GS9 RAM - Uint16 MSEL_GS10:1; // 10 Master Select for GS10 RAM - Uint16 MSEL_GS11:1; // 11 Master Select for GS11 RAM - Uint16 MSEL_GS12:1; // 12 Master Select for GS12 RAM - Uint16 MSEL_GS13:1; // 13 Master Select for GS13 RAM - Uint16 MSEL_GS14:1; // 14 Master Select for GS14 RAM - Uint16 MSEL_GS15:1; // 15 Master Select for GS15 RAM - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union GSxMSEL_REG { - Uint32 all; - struct GSxMSEL_BITS bit; -}; - -struct GSxACCPROT0_BITS { // bits description - Uint16 FETCHPROT_GS0:1; // 0 Fetch Protection For GS0 RAM - Uint16 CPUWRPROT_GS0:1; // 1 CPU WR Protection For GS0 RAM - Uint16 DMAWRPROT_GS0:1; // 2 DMA WR Protection For GS0 RAM - Uint16 rsvd1:5; // 7:3 Reserved - Uint16 FETCHPROT_GS1:1; // 8 Fetch Protection For GS1 RAM - Uint16 CPUWRPROT_GS1:1; // 9 CPU WR Protection For GS1 RAM - Uint16 DMAWRPROT_GS1:1; // 10 DMA WR Protection For GS1 RAM - Uint16 rsvd2:5; // 15:11 Reserved - Uint16 FETCHPROT_GS2:1; // 16 Fetch Protection For GS2 RAM - Uint16 CPUWRPROT_GS2:1; // 17 CPU WR Protection For GS2 RAM - Uint16 DMAWRPROT_GS2:1; // 18 DMA WR Protection For GS2 RAM - Uint16 rsvd3:5; // 23:19 Reserved - Uint16 FETCHPROT_GS3:1; // 24 Fetch Protection For GS3 RAM - Uint16 CPUWRPROT_GS3:1; // 25 CPU WR Protection For GS3 RAM - Uint16 DMAWRPROT_GS3:1; // 26 DMA WR Protection For GS3 RAM - Uint16 rsvd4:5; // 31:27 Reserved -}; - -union GSxACCPROT0_REG { - Uint32 all; - struct GSxACCPROT0_BITS bit; -}; - -struct GSxACCPROT1_BITS { // bits description - Uint16 FETCHPROT_GS4:1; // 0 Fetch Protection For GS4 RAM - Uint16 CPUWRPROT_GS4:1; // 1 CPU WR Protection For GS4 RAM - Uint16 DMAWRPROT_GS4:1; // 2 DMA WR Protection For GS4 RAM - Uint16 rsvd1:5; // 7:3 Reserved - Uint16 FETCHPROT_GS5:1; // 8 Fetch Protection For GS5 RAM - Uint16 CPUWRPROT_GS5:1; // 9 CPU WR Protection For GS5 RAM - Uint16 DMAWRPROT_GS5:1; // 10 DMA WR Protection For GS5RAM - Uint16 rsvd2:5; // 15:11 Reserved - Uint16 FETCHPROT_GS6:1; // 16 Fetch Protection For GS6 RAM - Uint16 CPUWRPROT_GS6:1; // 17 CPU WR Protection For GS6 RAM - Uint16 DMAWRPROT_GS6:1; // 18 DMA WR Protection For GS6RAM - Uint16 rsvd3:5; // 23:19 Reserved - Uint16 FETCHPROT_GS7:1; // 24 Fetch Protection For GS7 RAM - Uint16 CPUWRPROT_GS7:1; // 25 CPU WR Protection For GS7 RAM - Uint16 DMAWRPROT_GS7:1; // 26 DMA WR Protection For GS7RAM - Uint16 rsvd4:5; // 31:27 Reserved -}; - -union GSxACCPROT1_REG { - Uint32 all; - struct GSxACCPROT1_BITS bit; -}; - -struct GSxACCPROT2_BITS { // bits description - Uint16 FETCHPROT_GS8:1; // 0 Fetch Protection For GS8 RAM - Uint16 CPUWRPROT_GS8:1; // 1 CPU WR Protection For GS8 RAM - Uint16 DMAWRPROT_GS8:1; // 2 DMA WR Protection For GS8 RAM - Uint16 rsvd1:5; // 7:3 Reserved - Uint16 FETCHPROT_GS9:1; // 8 Fetch Protection For GS9 RAM - Uint16 CPUWRPROT_GS9:1; // 9 CPU WR Protection For GS9 RAM - Uint16 DMAWRPROT_GS9:1; // 10 DMA WR Protection For GS9RAM - Uint16 rsvd2:5; // 15:11 Reserved - Uint16 FETCHPROT_GS10:1; // 16 Fetch Protection For GS10 RAM - Uint16 CPUWRPROT_GS10:1; // 17 CPU WR Protection For GS10 RAM - Uint16 DMAWRPROT_GS10:1; // 18 DMA WR Protection For GS10RAM - Uint16 rsvd3:5; // 23:19 Reserved - Uint16 FETCHPROT_GS11:1; // 24 Fetch Protection For GS11 RAM - Uint16 CPUWRPROT_GS11:1; // 25 CPU WR Protection For GS11 RAM - Uint16 DMAWRPROT_GS11:1; // 26 DMA WR Protection For GS11RAM - Uint16 rsvd4:5; // 31:27 Reserved -}; - -union GSxACCPROT2_REG { - Uint32 all; - struct GSxACCPROT2_BITS bit; -}; - -struct GSxACCPROT3_BITS { // bits description - Uint16 FETCHPROT_GS12:1; // 0 Fetch Protection For GS12 RAM - Uint16 CPUWRPROT_GS12:1; // 1 CPU WR Protection For GS12 RAM - Uint16 DMAWRPROT_GS12:1; // 2 DMA WR Protection For GS12 RAM - Uint16 rsvd1:5; // 7:3 Reserved - Uint16 FETCHPROT_GS13:1; // 8 Fetch Protection For GS13 RAM - Uint16 CPUWRPROT_GS13:1; // 9 CPU WR Protection For GS13 RAM - Uint16 DMAWRPROT_GS13:1; // 10 DMA WR Protection For GS13RAM - Uint16 rsvd2:5; // 15:11 Reserved - Uint16 FETCHPROT_GS14:1; // 16 Fetch Protection For GS14 RAM - Uint16 CPUWRPROT_GS14:1; // 17 CPU WR Protection For GS14 RAM - Uint16 DMAWRPROT_GS14:1; // 18 DMA WR Protection For GS14RAM - Uint16 rsvd3:5; // 23:19 Reserved - Uint16 FETCHPROT_GS15:1; // 24 Fetch Protection For GS15 RAM - Uint16 CPUWRPROT_GS15:1; // 25 CPU WR Protection For GS15 RAM - Uint16 DMAWRPROT_GS15:1; // 26 DMA WR Protection For GS15RAM - Uint16 rsvd4:5; // 31:27 Reserved -}; - -union GSxACCPROT3_REG { - Uint32 all; - struct GSxACCPROT3_BITS bit; -}; - -struct GSxTEST_BITS { // bits description - Uint16 TEST_GS0:2; // 1:0 Selects the different modes for GS0 RAM - Uint16 TEST_GS1:2; // 3:2 Selects the different modes for GS1 RAM - Uint16 TEST_GS2:2; // 5:4 Selects the different modes for GS2 RAM - Uint16 TEST_GS3:2; // 7:6 Selects the different modes for GS3 RAM - Uint16 TEST_GS4:2; // 9:8 Selects the different modes for GS4 RAM - Uint16 TEST_GS5:2; // 11:10 Selects the different modes for GS5 RAM - Uint16 TEST_GS6:2; // 13:12 Selects the different modes for GS6 RAM - Uint16 TEST_GS7:2; // 15:14 Selects the different modes for GS7 RAM - Uint16 TEST_GS8:2; // 17:16 Selects the different modes for GS8 RAM - Uint16 TEST_GS9:2; // 19:18 Selects the different modes for GS9 RAM - Uint16 TEST_GS10:2; // 21:20 Selects the different modes for GS10 RAM - Uint16 TEST_GS11:2; // 23:22 Selects the different modes for GS11 RAM - Uint16 TEST_GS12:2; // 25:24 Selects the different modes for GS12 RAM - Uint16 TEST_GS13:2; // 27:26 Selects the different modes for GS13 RAM - Uint16 TEST_GS14:2; // 29:28 Selects the different modes for GS14 RAM - Uint16 TEST_GS15:2; // 31:30 Selects the different modes for GS15 RAM -}; - -union GSxTEST_REG { - Uint32 all; - struct GSxTEST_BITS bit; -}; - -struct GSxINIT_BITS { // bits description - Uint16 INIT_GS0:1; // 0 RAM Initialization control for GS0 RAM. - Uint16 INIT_GS1:1; // 1 RAM Initialization control for GS1 RAM. - Uint16 INIT_GS2:1; // 2 RAM Initialization control for GS2 RAM. - Uint16 INIT_GS3:1; // 3 RAM Initialization control for GS3 RAM. - Uint16 INIT_GS4:1; // 4 RAM Initialization control for GS4 RAM. - Uint16 INIT_GS5:1; // 5 RAM Initialization control for GS5 RAM. - Uint16 INIT_GS6:1; // 6 RAM Initialization control for GS6 RAM. - Uint16 INIT_GS7:1; // 7 RAM Initialization control for GS7 RAM. - Uint16 INIT_GS8:1; // 8 RAM Initialization control for GS8 RAM. - Uint16 INIT_GS9:1; // 9 RAM Initialization control for GS9 RAM. - Uint16 INIT_GS10:1; // 10 RAM Initialization control for GS10 RAM. - Uint16 INIT_GS11:1; // 11 RAM Initialization control for GS11 RAM. - Uint16 INIT_GS12:1; // 12 RAM Initialization control for GS12 RAM. - Uint16 INIT_GS13:1; // 13 RAM Initialization control for GS13 RAM. - Uint16 INIT_GS14:1; // 14 RAM Initialization control for GS14 RAM. - Uint16 INIT_GS15:1; // 15 RAM Initialization control for GS15 RAM. - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union GSxINIT_REG { - Uint32 all; - struct GSxINIT_BITS bit; -}; - -struct GSxINITDONE_BITS { // bits description - Uint16 INITDONE_GS0:1; // 0 RAM Initialization status for GS0 RAM. - Uint16 INITDONE_GS1:1; // 1 RAM Initialization status for GS1 RAM. - Uint16 INITDONE_GS2:1; // 2 RAM Initialization status for GS2 RAM. - Uint16 INITDONE_GS3:1; // 3 RAM Initialization status for GS3 RAM. - Uint16 INITDONE_GS4:1; // 4 RAM Initialization status for GS4 RAM. - Uint16 INITDONE_GS5:1; // 5 RAM Initialization status for GS5 RAM. - Uint16 INITDONE_GS6:1; // 6 RAM Initialization status for GS6 RAM. - Uint16 INITDONE_GS7:1; // 7 RAM Initialization status for GS7 RAM. - Uint16 INITDONE_GS8:1; // 8 RAM Initialization status for GS8 RAM. - Uint16 INITDONE_GS9:1; // 9 RAM Initialization status for GS9 RAM. - Uint16 INITDONE_GS10:1; // 10 RAM Initialization status for GS10 RAM. - Uint16 INITDONE_GS11:1; // 11 RAM Initialization status for GS11 RAM. - Uint16 INITDONE_GS12:1; // 12 RAM Initialization status for GS12 RAM. - Uint16 INITDONE_GS13:1; // 13 RAM Initialization status for GS13 RAM. - Uint16 INITDONE_GS14:1; // 14 RAM Initialization status for GS14 RAM. - Uint16 INITDONE_GS15:1; // 15 RAM Initialization status for GS15 RAM. - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union GSxINITDONE_REG { - Uint32 all; - struct GSxINITDONE_BITS bit; -}; - -struct MSGxTEST_BITS { // bits description - Uint16 TEST_CPUTOCPU:2; // 1:0 CPU to CPU Mode Select - Uint16 TEST_CPUTOCLA1:2; // 3:2 CPU to CLA1 MSG RAM Mode Select - Uint16 TEST_CLA1TOCPU:2; // 5:4 CLA1 to CPU MSG RAM Mode Select - Uint16 rsvd1:2; // 7:6 Reserved - Uint16 rsvd2:2; // 9:8 Reserved - Uint16 rsvd3:6; // 15:10 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union MSGxTEST_REG { - Uint32 all; - struct MSGxTEST_BITS bit; -}; - -struct MSGxINIT_BITS { // bits description - Uint16 INIT_CPUTOCPU:1; // 0 Initialization control for CPU to CPU MSG RAM - Uint16 INIT_CPUTOCLA1:1; // 1 Initialization control for CPUTOCLA1 MSG RAM - Uint16 INIT_CLA1TOCPU:1; // 2 Initialization control for CLA1TOCPU MSG RAM - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:1; // 4 Reserved - Uint16 rsvd3:11; // 15:5 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union MSGxINIT_REG { - Uint32 all; - struct MSGxINIT_BITS bit; -}; - -struct MSGxINITDONE_BITS { // bits description - Uint16 INITDONE_CPUTOCPU:1; // 0 Initialization status for CPU to CPU MSG RAM - Uint16 INITDONE_CPUTOCLA1:1; // 1 Initialization status for CPU to CLA1 MSG RAM - Uint16 INITDONE_CLA1TOCPU:1; // 2 Initialization status for CLA1 to CPU MSG RAM - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:1; // 4 Reserved - Uint16 rsvd3:11; // 15:5 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union MSGxINITDONE_REG { - Uint32 all; - struct MSGxINITDONE_BITS bit; -}; - -struct MEM_CFG_REGS { - union DxLOCK_REG DxLOCK; // Dedicated RAM Config Lock Register - union DxCOMMIT_REG DxCOMMIT; // Dedicated RAM Config Lock Commit Register - Uint16 rsvd1[4]; // Reserved - union DxACCPROT0_REG DxACCPROT0; // Dedicated RAM Config Register - Uint16 rsvd2[6]; // Reserved - union DxTEST_REG DxTEST; // Dedicated RAM TEST Register - union DxINIT_REG DxINIT; // Dedicated RAM Init Register - union DxINITDONE_REG DxINITDONE; // Dedicated RAM InitDone Status Register - Uint16 rsvd3[10]; // Reserved - union LSxLOCK_REG LSxLOCK; // Local Shared RAM Config Lock Register - union LSxCOMMIT_REG LSxCOMMIT; // Local Shared RAM Config Lock Commit Register - union LSxMSEL_REG LSxMSEL; // Local Shared RAM Master Sel Register - union LSxCLAPGM_REG LSxCLAPGM; // Local Shared RAM Prog/Exe control Register - union LSxACCPROT0_REG LSxACCPROT0; // Local Shared RAM Config Register 0 - union LSxACCPROT1_REG LSxACCPROT1; // Local Shared RAM Config Register 1 - Uint16 rsvd4[4]; // Reserved - union LSxTEST_REG LSxTEST; // Local Shared RAM TEST Register - union LSxINIT_REG LSxINIT; // Local Shared RAM Init Register - union LSxINITDONE_REG LSxINITDONE; // Local Shared RAM InitDone Status Register - Uint16 rsvd5[10]; // Reserved - union GSxLOCK_REG GSxLOCK; // Global Shared RAM Config Lock Register - union GSxCOMMIT_REG GSxCOMMIT; // Global Shared RAM Config Lock Commit Register - union GSxMSEL_REG GSxMSEL; // Global Shared RAM Master Sel Register - Uint16 rsvd6[2]; // Reserved - union GSxACCPROT0_REG GSxACCPROT0; // Global Shared RAM Config Register 0 - union GSxACCPROT1_REG GSxACCPROT1; // Global Shared RAM Config Register 1 - union GSxACCPROT2_REG GSxACCPROT2; // Global Shared RAM Config Register 2 - union GSxACCPROT3_REG GSxACCPROT3; // Global Shared RAM Config Register 3 - union GSxTEST_REG GSxTEST; // Global Shared RAM TEST Register - union GSxINIT_REG GSxINIT; // Global Shared RAM Init Register - union GSxINITDONE_REG GSxINITDONE; // Global Shared RAM InitDone Status Register - Uint16 rsvd7[26]; // Reserved - union MSGxTEST_REG MSGxTEST; // Message RAM TEST Register - union MSGxINIT_REG MSGxINIT; // Message RAM Init Register - union MSGxINITDONE_REG MSGxINITDONE; // Message RAM InitDone Status Register - Uint16 rsvd8[10]; // Reserved -}; - -struct EMIF1LOCK_BITS { // bits description - Uint16 LOCK_EMIF1:1; // 0 EMIF1 access protection and master select fields lock bit - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EMIF1LOCK_REG { - Uint32 all; - struct EMIF1LOCK_BITS bit; -}; - -struct EMIF1COMMIT_BITS { // bits description - Uint16 COMMIT_EMIF1:1; // 0 EMIF1 access protection and master select permanent lock - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EMIF1COMMIT_REG { - Uint32 all; - struct EMIF1COMMIT_BITS bit; -}; - -struct EMIF1MSEL_BITS { // bits description - Uint16 MSEL_EMIF1:2; // 1:0 Master Select for EMIF1. - Uint16 rsvd1:2; // 3:2 Reserved - Uint32 KEY:28; // 31:4 KEY to enable the write into MSEL_EMIF1 bits -}; - -union EMIF1MSEL_REG { - Uint32 all; - struct EMIF1MSEL_BITS bit; -}; - -struct EMIF1ACCPROT0_BITS { // bits description - Uint16 FETCHPROT_EMIF1:1; // 0 Fetch Protection For EMIF1 - Uint16 CPUWRPROT_EMIF1:1; // 1 CPU WR Protection For EMIF1 - Uint16 DMAWRPROT_EMIF1:1; // 2 DMA WR Protection For EMIF1 - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EMIF1ACCPROT0_REG { - Uint32 all; - struct EMIF1ACCPROT0_BITS bit; -}; - -struct EMIF1_CONFIG_REGS { - union EMIF1LOCK_REG EMIF1LOCK; // EMIF1 Config Lock Register - union EMIF1COMMIT_REG EMIF1COMMIT; // EMIF1 Config Lock Commit Register - union EMIF1MSEL_REG EMIF1MSEL; // EMIF1 Master Sel Register - Uint16 rsvd1[2]; // Reserved - union EMIF1ACCPROT0_REG EMIF1ACCPROT0; // EMIF1 Config Register 0 - Uint16 rsvd2[22]; // Reserved -}; - -struct EMIF2LOCK_BITS { // bits description - Uint16 LOCK_EMIF2:1; // 0 EMIF2 access protection and master select permanent lock - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EMIF2LOCK_REG { - Uint32 all; - struct EMIF2LOCK_BITS bit; -}; - -struct EMIF2COMMIT_BITS { // bits description - Uint16 COMMIT_EMIF2:1; // 0 EMIF2 access protection and master select permanent lock - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EMIF2COMMIT_REG { - Uint32 all; - struct EMIF2COMMIT_BITS bit; -}; - -struct EMIF2ACCPROT0_BITS { // bits description - Uint16 FETCHPROT_EMIF2:1; // 0 Fetch Protection For EMIF2 - Uint16 CPUWRPROT_EMIF2:1; // 1 CPU WR Protection For EMIF2 - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union EMIF2ACCPROT0_REG { - Uint32 all; - struct EMIF2ACCPROT0_BITS bit; -}; - -struct EMIF2_CONFIG_REGS { - union EMIF2LOCK_REG EMIF2LOCK; // EMIF2 Config Lock Register - union EMIF2COMMIT_REG EMIF2COMMIT; // EMIF2 Config Lock Commit Register - Uint16 rsvd1[4]; // Reserved - union EMIF2ACCPROT0_REG EMIF2ACCPROT0; // EMIF2 Config Register 0 - Uint16 rsvd2[22]; // Reserved -}; - -struct NMAVFLG_BITS { // bits description - Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag - Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag - Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag - Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag - Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag - Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag - Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union NMAVFLG_REG { - Uint32 all; - struct NMAVFLG_BITS bit; -}; - -struct NMAVSET_BITS { // bits description - Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Set - Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Set - Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Set - Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Set - Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Set - Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Set - Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Set - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union NMAVSET_REG { - Uint32 all; - struct NMAVSET_BITS bit; -}; - -struct NMAVCLR_BITS { // bits description - Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Clear - Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Clear - Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Clear - Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Clear - Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Clear - Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Clear - Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Clear - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union NMAVCLR_REG { - Uint32 all; - struct NMAVCLR_BITS bit; -}; - -struct NMAVINTEN_BITS { // bits description - Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Interrupt Enable - Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Interrupt Enable - Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Interrupt Enable - Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Interrupt Enable - Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Interrupt Enable - Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Interrupt Enable - Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Interrupt Enable - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union NMAVINTEN_REG { - Uint32 all; - struct NMAVINTEN_BITS bit; -}; - -struct MAVFLG_BITS { // bits description - Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag - Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag - Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MAVFLG_REG { - Uint32 all; - struct MAVFLG_BITS bit; -}; - -struct MAVSET_BITS { // bits description - Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Set - Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Set - Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Set - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MAVSET_REG { - Uint32 all; - struct MAVSET_BITS bit; -}; - -struct MAVCLR_BITS { // bits description - Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Clear - Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Clear - Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Clear - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MAVCLR_REG { - Uint32 all; - struct MAVCLR_BITS bit; -}; - -struct MAVINTEN_BITS { // bits description - Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Interrupt Enable - Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Interrupt Enable - Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Interrupt Enable - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MAVINTEN_REG { - Uint32 all; - struct MAVINTEN_BITS bit; -}; - -struct ACCESS_PROTECTION_REGS { - union NMAVFLG_REG NMAVFLG; // Non-Master Access Violation Flag Register - union NMAVSET_REG NMAVSET; // Non-Master Access Violation Flag Set Register - union NMAVCLR_REG NMAVCLR; // Non-Master Access Violation Flag Clear Register - union NMAVINTEN_REG NMAVINTEN; // Non-Master Access Violation Interrupt Enable Register - Uint32 NMCPURDAVADDR; // Non-Master CPU Read Access Violation Address - Uint32 NMCPUWRAVADDR; // Non-Master CPU Write Access Violation Address - Uint32 NMCPUFAVADDR; // Non-Master CPU Fetch Access Violation Address - Uint32 NMDMAWRAVADDR; // Non-Master DMA Write Access Violation Address - Uint32 NMCLA1RDAVADDR; // Non-Master CLA1 Read Access Violation Address - Uint32 NMCLA1WRAVADDR; // Non-Master CLA1 Write Access Violation Address - Uint32 NMCLA1FAVADDR; // Non-Master CLA1 Fetch Access Violation Address - Uint16 rsvd1[10]; // Reserved - union MAVFLG_REG MAVFLG; // Master Access Violation Flag Register - union MAVSET_REG MAVSET; // Master Access Violation Flag Set Register - union MAVCLR_REG MAVCLR; // Master Access Violation Flag Clear Register - union MAVINTEN_REG MAVINTEN; // Master Access Violation Interrupt Enable Register - Uint32 MCPUFAVADDR; // Master CPU Fetch Access Violation Address - Uint32 MCPUWRAVADDR; // Master CPU Write Access Violation Address - Uint32 MDMAWRAVADDR; // Master DMA Write Access Violation Address - Uint16 rsvd2[18]; // Reserved -}; - -struct UCERRFLG_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag - Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag - Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union UCERRFLG_REG { - Uint32 all; - struct UCERRFLG_BITS bit; -}; - -struct UCERRSET_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Set - Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Set - Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Set - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union UCERRSET_REG { - Uint32 all; - struct UCERRSET_BITS bit; -}; - -struct UCERRCLR_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Clear - Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Clear - Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Clear - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union UCERRCLR_REG { - Uint32 all; - struct UCERRCLR_BITS bit; -}; - -struct CERRFLG_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag - Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag - Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CERRFLG_REG { - Uint32 all; - struct CERRFLG_BITS bit; -}; - -struct CERRSET_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Set - Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Set - Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Set - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CERRSET_REG { - Uint32 all; - struct CERRSET_BITS bit; -}; - -struct CERRCLR_BITS { // bits description - Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Clear - Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Clear - Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Clear - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CERRCLR_REG { - Uint32 all; - struct CERRCLR_BITS bit; -}; - -struct CEINTFLG_BITS { // bits description - Uint16 CEINTFLAG:1; // 0 Total corrected error count exceeded threshold flag. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CEINTFLG_REG { - Uint32 all; - struct CEINTFLG_BITS bit; -}; - -struct CEINTCLR_BITS { // bits description - Uint16 CEINTCLR:1; // 0 CPU Corrected Error Threshold Exceeded Error Clear. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CEINTCLR_REG { - Uint32 all; - struct CEINTCLR_BITS bit; -}; - -struct CEINTSET_BITS { // bits description - Uint16 CEINTSET:1; // 0 Total corrected error count exceeded flag set. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CEINTSET_REG { - Uint32 all; - struct CEINTSET_BITS bit; -}; - -struct CEINTEN_BITS { // bits description - Uint16 CEINTEN:1; // 0 CPU/DMA Correctable Error Interrupt Enable. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CEINTEN_REG { - Uint32 all; - struct CEINTEN_BITS bit; -}; - -struct MEMORY_ERROR_REGS { - union UCERRFLG_REG UCERRFLG; // Uncorrectable Error Flag Register - union UCERRSET_REG UCERRSET; // Uncorrectable Error Flag Set Register - union UCERRCLR_REG UCERRCLR; // Uncorrectable Error Flag Clear Register - Uint32 UCCPUREADDR; // Uncorrectable CPU Read Error Address - Uint32 UCDMAREADDR; // Uncorrectable DMA Read Error Address - Uint32 UCCLA1READDR; // Uncorrectable CLA1 Read Error Address - Uint16 rsvd1[20]; // Reserved - union CERRFLG_REG CERRFLG; // Correctable Error Flag Register - union CERRSET_REG CERRSET; // Correctable Error Flag Set Register - union CERRCLR_REG CERRCLR; // Correctable Error Flag Clear Register - Uint32 CCPUREADDR; // Correctable CPU Read Error Address - Uint16 rsvd2[6]; // Reserved - Uint32 CERRCNT; // Correctable Error Count Register - Uint32 CERRTHRES; // Correctable Error Threshold Value Register - union CEINTFLG_REG CEINTFLG; // Correctable Error Interrupt Flag Status Register - union CEINTCLR_REG CEINTCLR; // Correctable Error Interrupt Flag Clear Register - union CEINTSET_REG CEINTSET; // Correctable Error Interrupt Flag Set Register - union CEINTEN_REG CEINTEN; // Correctable Error Interrupt Enable Register - Uint16 rsvd3[6]; // Reserved -}; - -struct ROMWAITSTATE_BITS { // bits description - Uint16 WSDISABLE:1; // 0 ROM Wait State Enable/Disable Control - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ROMWAITSTATE_REG { - Uint32 all; - struct ROMWAITSTATE_BITS bit; -}; - -struct ROM_WAIT_STATE_REGS { - union ROMWAITSTATE_REG ROMWAITSTATE; // ROM Wait State Configuration Register -}; - -struct ROMPREFETCH_BITS { // bits description - Uint16 PFENABLE:1; // 0 ROM Prefetch Enable/Disable Control - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union ROMPREFETCH_REG { - Uint32 all; - struct ROMPREFETCH_BITS bit; -}; - -struct ROM_PREFETCH_REGS { - union ROMPREFETCH_REG ROMPREFETCH; // ROM Prefetch Configuration Register -}; - -//--------------------------------------------------------------------------- -// MEMCONFIG External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct ROM_PREFETCH_REGS RomPrefetchRegs; -extern volatile struct MEM_CFG_REGS MemCfgRegs; -extern volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; -extern volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs; -extern volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; -extern volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; -extern volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs; -#endif -#ifdef CPU2 -extern volatile struct MEM_CFG_REGS MemCfgRegs; -extern volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; -extern volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; -extern volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_nmiintrupt.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_nmiintrupt.h deleted file mode 100644 index 0bbe21fe21..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_nmiintrupt.h +++ /dev/null @@ -1,175 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_nmiintrupt.h -// -// TITLE: NMIINTRUPT Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_NMIINTRUPT_H__ -#define __F2837xD_NMIINTRUPT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// NMIINTRUPT Individual Register Bit Definitions: - -struct NMICFG_BITS { // bits description - Uint16 NMIE:1; // 0 Global NMI Enable - Uint16 rsvd1:15; // 15:1 Reserved -}; - -union NMICFG_REG { - Uint16 all; - struct NMICFG_BITS bit; -}; - -struct NMIFLG_BITS { // bits description - Uint16 NMIINT:1; // 0 NMI Interrupt Flag - Uint16 CLOCKFAIL:1; // 1 Clock Fail Interrupt Flag - Uint16 RAMUNCERR:1; // 2 RAM Uncorrectable Error NMI Flag - Uint16 FLUNCERR:1; // 3 Flash Uncorrectable Error NMI Flag - Uint16 CPU1HWBISTERR:1; // 4 HW BIST Error NMI Flag - Uint16 CPU2HWBISTERR:1; // 5 HW BIST Error NMI Flag - Uint16 PIEVECTERR:1; // 6 PIE Vector Fetch Error Flag - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 CPU2WDRSn:1; // 9 CPU2 WDRSn Reset Indication Flag - Uint16 CPU2NMIWDRSn:1; // 10 CPU2 NMIWDRSn Reset Indication Flag - Uint16 rsvd3:1; // 11 Reserved - Uint16 rsvd4:4; // 15:12 Reserved -}; - -union NMIFLG_REG { - Uint16 all; - struct NMIFLG_BITS bit; -}; - -struct NMIFLGCLR_BITS { // bits description - Uint16 NMIINT:1; // 0 NMIINT Flag Clear - Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Clear - Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Clear - Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Clear - Uint16 CPU1HWBISTERR:1; // 4 CPU1HWBISTERR Flag Clear - Uint16 CPU2HWBISTERR:1; // 5 CPU2HWBISTERR Flag Clear - Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Clear - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:1; // 8 Reserved - Uint16 CPU2WDRSn:1; // 9 CPU2WDRSn Flag Clear - Uint16 CPU2NMIWDRSn:1; // 10 CPU2NMIWDRSn Flag Clear - Uint16 OVF:1; // 11 OVF Flag Clear - Uint16 rsvd3:4; // 15:12 Reserved -}; - -union NMIFLGCLR_REG { - Uint16 all; - struct NMIFLGCLR_BITS bit; -}; - -struct NMIFLGFRC_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Force - Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Force - Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Force - Uint16 CPU1HWBISTERR:1; // 4 CPU1HWBISTERR Flag Force - Uint16 CPU2HWBISTERR:1; // 5 CPU2HWBISTERR Flag Force - Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Force - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 CPU2WDRSn:1; // 9 CPU2WDRSn Flag Force - Uint16 CPU2NMIWDRSn:1; // 10 CPU2NMIWDRSn Flag Force - Uint16 OVF:1; // 11 OVF Flag Force - Uint16 rsvd4:4; // 15:12 Reserved -}; - -union NMIFLGFRC_REG { - Uint16 all; - struct NMIFLGFRC_BITS bit; -}; - -struct NMISHDFLG_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 CLOCKFAIL:1; // 1 Shadow CLOCKFAIL Flag - Uint16 RAMUNCERR:1; // 2 Shadow RAMUNCERR Flag - Uint16 FLUNCERR:1; // 3 Shadow FLUNCERR Flag - Uint16 CPU1HWBISTERR:1; // 4 Shadow CPU1HWBISTERR Flag - Uint16 CPU2HWBISTERR:1; // 5 Shadow CPU2HWBISTERR Flag - Uint16 PIEVECTERR:1; // 6 Shadow PIEVECTERR Flag - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 CPU2WDRSn:1; // 9 Shadow CPU2WDRSn Flag - Uint16 CPU2NMIWDRSn:1; // 10 Shadow CPU2NMIWDRSn Flag - Uint16 OVF:1; // 11 Shadow OVF Flag - Uint16 rsvd4:4; // 15:12 Reserved -}; - -union NMISHDFLG_REG { - Uint16 all; - struct NMISHDFLG_BITS bit; -}; - -struct NMI_INTRUPT_REGS { - union NMICFG_REG NMICFG; // NMI Configuration Register - union NMIFLG_REG NMIFLG; // NMI Flag Register (XRSn Clear) - union NMIFLGCLR_REG NMIFLGCLR; // NMI Flag Clear Register - union NMIFLGFRC_REG NMIFLGFRC; // NMI Flag Force Register - Uint16 NMIWDCNT; // NMI Watchdog Counter Register - Uint16 NMIWDPRD; // NMI Watchdog Period Register - union NMISHDFLG_REG NMISHDFLG; // NMI Shadow Flag Register -}; - -//--------------------------------------------------------------------------- -// NMIINTRUPT External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; -#endif -#ifdef CPU2 -extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_output_xbar.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_output_xbar.h deleted file mode 100644 index aad7cada65..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_output_xbar.h +++ /dev/null @@ -1,907 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_output_xbar.h -// -// TITLE: OUTPUT_XBAR Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_OUTPUT_XBAR_H__ -#define __F2837xD_OUTPUT_XBAR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// OUTPUT_XBAR Individual Register Bit Definitions: - -struct OUTPUT1MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT1 of OUTPUT-XBAR -}; - -union OUTPUT1MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT1MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT1MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT1 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT1 of OUTPUT-XBAR -}; - -union OUTPUT1MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT1MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT2MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT2 of OUTPUT-XBAR -}; - -union OUTPUT2MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT2MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT2MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT2 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT2 of OUTPUT-XBAR -}; - -union OUTPUT2MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT2MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT3MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT3 of OUTPUT-XBAR -}; - -union OUTPUT3MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT3MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT3MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT3 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT3 of OUTPUT-XBAR -}; - -union OUTPUT3MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT3MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT4MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT4 of OUTPUT-XBAR -}; - -union OUTPUT4MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT4MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT4MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT4 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT4 of OUTPUT-XBAR -}; - -union OUTPUT4MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT4MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT5MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT5 of OUTPUT-XBAR -}; - -union OUTPUT5MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT5MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT5MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT5 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT5 of OUTPUT-XBAR -}; - -union OUTPUT5MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT5MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT6MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT6 of OUTPUT-XBAR -}; - -union OUTPUT6MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT6MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT6MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT6 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT6 of OUTPUT-XBAR -}; - -union OUTPUT6MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT6MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT7MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT7 of OUTPUT-XBAR -}; - -union OUTPUT7MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT7MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT7MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT7 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT7 of OUTPUT-XBAR -}; - -union OUTPUT7MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT7MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT8MUX0TO15CFG_BITS { // bits description - Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT8 of OUTPUT-XBAR -}; - -union OUTPUT8MUX0TO15CFG_REG { - Uint32 all; - struct OUTPUT8MUX0TO15CFG_BITS bit; -}; - -struct OUTPUT8MUX16TO31CFG_BITS { // bits description - Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT8 of OUTPUT-XBAR - Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT8 of OUTPUT-XBAR -}; - -union OUTPUT8MUX16TO31CFG_REG { - Uint32 all; - struct OUTPUT8MUX16TO31CFG_BITS bit; -}; - -struct OUTPUT1MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT1 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT1 of OUTPUT-XBAR -}; - -union OUTPUT1MUXENABLE_REG { - Uint32 all; - struct OUTPUT1MUXENABLE_BITS bit; -}; - -struct OUTPUT2MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT2 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT2 of OUTPUT-XBAR -}; - -union OUTPUT2MUXENABLE_REG { - Uint32 all; - struct OUTPUT2MUXENABLE_BITS bit; -}; - -struct OUTPUT3MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT3 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT3 of OUTPUT-XBAR -}; - -union OUTPUT3MUXENABLE_REG { - Uint32 all; - struct OUTPUT3MUXENABLE_BITS bit; -}; - -struct OUTPUT4MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT4 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT4 of OUTPUT-XBAR -}; - -union OUTPUT4MUXENABLE_REG { - Uint32 all; - struct OUTPUT4MUXENABLE_BITS bit; -}; - -struct OUTPUT5MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT5 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT5 of OUTPUT-XBAR -}; - -union OUTPUT5MUXENABLE_REG { - Uint32 all; - struct OUTPUT5MUXENABLE_BITS bit; -}; - -struct OUTPUT6MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to OUTPUT6 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT6 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT6 of OUTPUT-XBAR -}; - -union OUTPUT6MUXENABLE_REG { - Uint32 all; - struct OUTPUT6MUXENABLE_BITS bit; -}; - -struct OUTPUT7MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT7 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT7 of OUTPUT-XBAR -}; - -union OUTPUT7MUXENABLE_REG { - Uint32 all; - struct OUTPUT7MUXENABLE_BITS bit; -}; - -struct OUTPUT8MUXENABLE_BITS { // bits description - Uint16 MUX0:1; // 0 mux0 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT8 of OUTPUT-XBAR - Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT8 of OUTPUT-XBAR -}; - -union OUTPUT8MUXENABLE_REG { - Uint32 all; - struct OUTPUT8MUXENABLE_BITS bit; -}; - -struct OUTPUTLATCH_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Records the OUTPUT1 of OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Records the OUTPUT2 of OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Records the OUTPUT3 of OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Records the OUTPUT4 of OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Records the OUTPUT5 of OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Records the OUTPUT6 of OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Records the OUTPUT7 of OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Records the OUTPUT8 of OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTLATCH_REG { - Uint32 all; - struct OUTPUTLATCH_BITS bit; -}; - -struct OUTPUTLATCHCLR_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTLATCHCLR_REG { - Uint32 all; - struct OUTPUTLATCHCLR_BITS bit; -}; - -struct OUTPUTLATCHFRC_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTLATCHFRC_REG { - Uint32 all; - struct OUTPUTLATCHFRC_BITS bit; -}; - -struct OUTPUTLATCHENABLE_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Selects the output latch to drive OUTPUT1 for OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Selects the output latch to drive OUTPUT2 for OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Selects the output latch to drive OUTPUT3 for OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Selects the output latch to drive OUTPUT4 for OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Selects the output latch to drive OUTPUT5 for OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Selects the output latch to drive OUTPUT6 for OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Selects the output latch to drive OUTPUT7 for OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Selects the output latch to drive OUTPUT8 for OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTLATCHENABLE_REG { - Uint32 all; - struct OUTPUTLATCHENABLE_BITS bit; -}; - -struct OUTPUTINV_BITS { // bits description - Uint16 OUTPUT1:1; // 0 Selects polarity for OUTPUT1 of OUTPUT-XBAR - Uint16 OUTPUT2:1; // 1 Selects polarity for OUTPUT2 of OUTPUT-XBAR - Uint16 OUTPUT3:1; // 2 Selects polarity for OUTPUT3 of OUTPUT-XBAR - Uint16 OUTPUT4:1; // 3 Selects polarity for OUTPUT4 of OUTPUT-XBAR - Uint16 OUTPUT5:1; // 4 Selects polarity for OUTPUT5 of OUTPUT-XBAR - Uint16 OUTPUT6:1; // 5 Selects polarity for OUTPUT6 of OUTPUT-XBAR - Uint16 OUTPUT7:1; // 6 Selects polarity for OUTPUT7 of OUTPUT-XBAR - Uint16 OUTPUT8:1; // 7 Selects polarity for OUTPUT8 of OUTPUT-XBAR - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union OUTPUTINV_REG { - Uint32 all; - struct OUTPUTINV_BITS bit; -}; - -struct OUTPUTLOCK_BITS { // bits description - Uint16 LOCK:1; // 0 Locks the configuration for OUTPUT-XBAR - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 KEY:16; // 31:16 Write Protection KEY -}; - -union OUTPUTLOCK_REG { - Uint32 all; - struct OUTPUTLOCK_BITS bit; -}; - -struct OUTPUT_XBAR_REGS { - union OUTPUT1MUX0TO15CFG_REG OUTPUT1MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 1 - union OUTPUT1MUX16TO31CFG_REG OUTPUT1MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 1 - union OUTPUT2MUX0TO15CFG_REG OUTPUT2MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 2 - union OUTPUT2MUX16TO31CFG_REG OUTPUT2MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 2 - union OUTPUT3MUX0TO15CFG_REG OUTPUT3MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 3 - union OUTPUT3MUX16TO31CFG_REG OUTPUT3MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 3 - union OUTPUT4MUX0TO15CFG_REG OUTPUT4MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 4 - union OUTPUT4MUX16TO31CFG_REG OUTPUT4MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 4 - union OUTPUT5MUX0TO15CFG_REG OUTPUT5MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 5 - union OUTPUT5MUX16TO31CFG_REG OUTPUT5MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 5 - union OUTPUT6MUX0TO15CFG_REG OUTPUT6MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 6 - union OUTPUT6MUX16TO31CFG_REG OUTPUT6MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 6 - union OUTPUT7MUX0TO15CFG_REG OUTPUT7MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 7 - union OUTPUT7MUX16TO31CFG_REG OUTPUT7MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 7 - union OUTPUT8MUX0TO15CFG_REG OUTPUT8MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 8 - union OUTPUT8MUX16TO31CFG_REG OUTPUT8MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 8 - union OUTPUT1MUXENABLE_REG OUTPUT1MUXENABLE; // Output X-BAR Mux Enable for Output 1 - union OUTPUT2MUXENABLE_REG OUTPUT2MUXENABLE; // Output X-BAR Mux Enable for Output 2 - union OUTPUT3MUXENABLE_REG OUTPUT3MUXENABLE; // Output X-BAR Mux Enable for Output 3 - union OUTPUT4MUXENABLE_REG OUTPUT4MUXENABLE; // Output X-BAR Mux Enable for Output 4 - union OUTPUT5MUXENABLE_REG OUTPUT5MUXENABLE; // Output X-BAR Mux Enable for Output 5 - union OUTPUT6MUXENABLE_REG OUTPUT6MUXENABLE; // Output X-BAR Mux Enable for Output 6 - union OUTPUT7MUXENABLE_REG OUTPUT7MUXENABLE; // Output X-BAR Mux Enable for Output 7 - union OUTPUT8MUXENABLE_REG OUTPUT8MUXENABLE; // Output X-BAR Mux Enable for Output 8 - union OUTPUTLATCH_REG OUTPUTLATCH; // Output X-BAR Output Latch - union OUTPUTLATCHCLR_REG OUTPUTLATCHCLR; // Output X-BAR Output Latch Clear - union OUTPUTLATCHFRC_REG OUTPUTLATCHFRC; // Output X-BAR Output Latch Clear - union OUTPUTLATCHENABLE_REG OUTPUTLATCHENABLE; // Output X-BAR Output Latch Enable - union OUTPUTINV_REG OUTPUTINV; // Output X-BAR Output Inversion - Uint16 rsvd1[4]; // Reserved - union OUTPUTLOCK_REG OUTPUTLOCK; // Output X-BAR Configuration Lock register -}; - -//--------------------------------------------------------------------------- -// OUTPUT_XBAR External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_piectrl.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_piectrl.h deleted file mode 100644 index 75f9303244..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_piectrl.h +++ /dev/null @@ -1,707 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_piectrl.h -// -// TITLE: PIECTRL Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_PIECTRL_H__ -#define __F2837xD_PIECTRL_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// PIECTRL Individual Register Bit Definitions: - -struct PIECTRL_BITS { // bits description - Uint16 ENPIE:1; // 0 PIE Enable - Uint16 PIEVECT:15; // 15:1 PIE Vector Address -}; - -union PIECTRL_REG { - Uint16 all; - struct PIECTRL_BITS bit; -}; - -struct PIEACK_BITS { // bits description - Uint16 ACK1:1; // 0 Acknowledge PIE Interrupt Group 1 - Uint16 ACK2:1; // 1 Acknowledge PIE Interrupt Group 2 - Uint16 ACK3:1; // 2 Acknowledge PIE Interrupt Group 3 - Uint16 ACK4:1; // 3 Acknowledge PIE Interrupt Group 4 - Uint16 ACK5:1; // 4 Acknowledge PIE Interrupt Group 5 - Uint16 ACK6:1; // 5 Acknowledge PIE Interrupt Group 6 - Uint16 ACK7:1; // 6 Acknowledge PIE Interrupt Group 7 - Uint16 ACK8:1; // 7 Acknowledge PIE Interrupt Group 8 - Uint16 ACK9:1; // 8 Acknowledge PIE Interrupt Group 9 - Uint16 ACK10:1; // 9 Acknowledge PIE Interrupt Group 10 - Uint16 ACK11:1; // 10 Acknowledge PIE Interrupt Group 11 - Uint16 ACK12:1; // 11 Acknowledge PIE Interrupt Group 12 - Uint16 rsvd1:4; // 15:12 Reserved -}; - -union PIEACK_REG { - Uint16 all; - struct PIEACK_BITS bit; -}; - -struct PIEIER1_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 1.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 1.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 1.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 1.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 1.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 1.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 1.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 1.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 1.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 1.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 1.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 1.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 1.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 1.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 1.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 1.16 -}; - -union PIEIER1_REG { - Uint16 all; - struct PIEIER1_BITS bit; -}; - -struct PIEIFR1_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 1.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 1.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 1.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 1.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 1.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 1.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 1.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 1.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 1.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 1.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 1.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 1.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 1.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 1.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 1.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 1.16 -}; - -union PIEIFR1_REG { - Uint16 all; - struct PIEIFR1_BITS bit; -}; - -struct PIEIER2_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 2.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 2.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 2.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 2.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 2.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 2.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 2.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 2.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 2.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 2.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 2.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 2.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 2.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 2.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 2.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 2.16 -}; - -union PIEIER2_REG { - Uint16 all; - struct PIEIER2_BITS bit; -}; - -struct PIEIFR2_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 2.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 2.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 2.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 2.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 2.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 2.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 2.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 2.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 2.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 2.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 2.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 2.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 2.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 2.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 2.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 2.16 -}; - -union PIEIFR2_REG { - Uint16 all; - struct PIEIFR2_BITS bit; -}; - -struct PIEIER3_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 3.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 3.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 3.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 3.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 3.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 3.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 3.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 3.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 3.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 3.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 3.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 3.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 3.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 3.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 3.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 3.16 -}; - -union PIEIER3_REG { - Uint16 all; - struct PIEIER3_BITS bit; -}; - -struct PIEIFR3_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 3.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 3.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 3.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 3.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 3.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 3.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 3.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 3.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 3.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 3.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 3.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 3.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 3.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 3.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 3.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 3.16 -}; - -union PIEIFR3_REG { - Uint16 all; - struct PIEIFR3_BITS bit; -}; - -struct PIEIER4_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 4.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 4.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 4.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 4.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 4.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 4.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 4.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 4.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 4.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 4.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 4.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 4.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 4.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 4.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 4.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 4.16 -}; - -union PIEIER4_REG { - Uint16 all; - struct PIEIER4_BITS bit; -}; - -struct PIEIFR4_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 4.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 4.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 4.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 4.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 4.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 4.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 4.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 4.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 4.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 4.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 4.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 4.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 4.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 4.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 4.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 4.16 -}; - -union PIEIFR4_REG { - Uint16 all; - struct PIEIFR4_BITS bit; -}; - -struct PIEIER5_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 5.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 5.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 5.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 5.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 5.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 5.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 5.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 5.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 5.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 5.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 5.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 5.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 5.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 5.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 5.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 5.16 -}; - -union PIEIER5_REG { - Uint16 all; - struct PIEIER5_BITS bit; -}; - -struct PIEIFR5_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 5.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 5.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 5.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 5.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 5.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 5.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 5.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 5.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 5.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 5.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 5.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 5.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 5.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 5.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 5.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 5.16 -}; - -union PIEIFR5_REG { - Uint16 all; - struct PIEIFR5_BITS bit; -}; - -struct PIEIER6_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 6.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 6.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 6.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 6.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 6.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 6.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 6.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 6.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 6.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 6.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 6.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 6.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 6.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 6.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 6.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 6.16 -}; - -union PIEIER6_REG { - Uint16 all; - struct PIEIER6_BITS bit; -}; - -struct PIEIFR6_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 6.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 6.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 6.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 6.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 6.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 6.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 6.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 6.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 6.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 6.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 6.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 6.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 6.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 6.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 6.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 6.16 -}; - -union PIEIFR6_REG { - Uint16 all; - struct PIEIFR6_BITS bit; -}; - -struct PIEIER7_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 7.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 7.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 7.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 7.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 7.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 7.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 7.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 7.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 7.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 7.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 7.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 7.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 7.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 7.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 7.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 7.16 -}; - -union PIEIER7_REG { - Uint16 all; - struct PIEIER7_BITS bit; -}; - -struct PIEIFR7_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 7.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 7.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 7.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 7.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 7.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 7.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 7.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 7.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 7.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 7.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 7.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 7.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 7.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 7.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 7.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 7.16 -}; - -union PIEIFR7_REG { - Uint16 all; - struct PIEIFR7_BITS bit; -}; - -struct PIEIER8_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 8.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 8.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 8.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 8.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 8.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 8.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 8.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 8.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 8.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 8.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 8.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 8.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 8.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 8.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 8.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 8.16 -}; - -union PIEIER8_REG { - Uint16 all; - struct PIEIER8_BITS bit; -}; - -struct PIEIFR8_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 8.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 8.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 8.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 8.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 8.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 8.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 8.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 8.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 8.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 8.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 8.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 8.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 8.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 8.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 8.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 8.16 -}; - -union PIEIFR8_REG { - Uint16 all; - struct PIEIFR8_BITS bit; -}; - -struct PIEIER9_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 9.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 9.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 9.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 9.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 9.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 9.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 9.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 9.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 9.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 9.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 9.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 9.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 9.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 9.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 9.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 9.16 -}; - -union PIEIER9_REG { - Uint16 all; - struct PIEIER9_BITS bit; -}; - -struct PIEIFR9_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 9.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 9.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 9.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 9.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 9.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 9.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 9.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 9.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 9.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 9.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 9.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 9.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 9.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 9.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 9.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 9.16 -}; - -union PIEIFR9_REG { - Uint16 all; - struct PIEIFR9_BITS bit; -}; - -struct PIEIER10_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 10.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 10.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 10.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 10.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 10.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 10.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 10.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 10.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 10.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 10.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 10.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 10.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 10.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 10.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 10.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 10.16 -}; - -union PIEIER10_REG { - Uint16 all; - struct PIEIER10_BITS bit; -}; - -struct PIEIFR10_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 10.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 10.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 10.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 10.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 10.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 10.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 10.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 10.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 10.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 10.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 10.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 10.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 10.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 10.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 10.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 10.16 -}; - -union PIEIFR10_REG { - Uint16 all; - struct PIEIFR10_BITS bit; -}; - -struct PIEIER11_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 11.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 11.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 11.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 11.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 11.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 11.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 11.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 11.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 11.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 11.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 11.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 11.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 11.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 11.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 11.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 11.16 -}; - -union PIEIER11_REG { - Uint16 all; - struct PIEIER11_BITS bit; -}; - -struct PIEIFR11_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 11.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 11.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 11.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 11.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 11.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 11.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 11.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 11.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 11.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 11.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 11.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 11.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 11.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 11.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 11.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 11.16 -}; - -union PIEIFR11_REG { - Uint16 all; - struct PIEIFR11_BITS bit; -}; - -struct PIEIER12_BITS { // bits description - Uint16 INTx1:1; // 0 Enable for Interrupt 12.1 - Uint16 INTx2:1; // 1 Enable for Interrupt 12.2 - Uint16 INTx3:1; // 2 Enable for Interrupt 12.3 - Uint16 INTx4:1; // 3 Enable for Interrupt 12.4 - Uint16 INTx5:1; // 4 Enable for Interrupt 12.5 - Uint16 INTx6:1; // 5 Enable for Interrupt 12.6 - Uint16 INTx7:1; // 6 Enable for Interrupt 12.7 - Uint16 INTx8:1; // 7 Enable for Interrupt 12.8 - Uint16 INTx9:1; // 8 Enable for Interrupt 12.9 - Uint16 INTx10:1; // 9 Enable for Interrupt 12.10 - Uint16 INTx11:1; // 10 Enable for Interrupt 12.11 - Uint16 INTx12:1; // 11 Enable for Interrupt 12.12 - Uint16 INTx13:1; // 12 Enable for Interrupt 12.13 - Uint16 INTx14:1; // 13 Enable for Interrupt 12.14 - Uint16 INTx15:1; // 14 Enable for Interrupt 12.15 - Uint16 INTx16:1; // 15 Enable for Interrupt 12.16 -}; - -union PIEIER12_REG { - Uint16 all; - struct PIEIER12_BITS bit; -}; - -struct PIEIFR12_BITS { // bits description - Uint16 INTx1:1; // 0 Flag for Interrupt 12.1 - Uint16 INTx2:1; // 1 Flag for Interrupt 12.2 - Uint16 INTx3:1; // 2 Flag for Interrupt 12.3 - Uint16 INTx4:1; // 3 Flag for Interrupt 12.4 - Uint16 INTx5:1; // 4 Flag for Interrupt 12.5 - Uint16 INTx6:1; // 5 Flag for Interrupt 12.6 - Uint16 INTx7:1; // 6 Flag for Interrupt 12.7 - Uint16 INTx8:1; // 7 Flag for Interrupt 12.8 - Uint16 INTx9:1; // 8 Flag for Interrupt 12.9 - Uint16 INTx10:1; // 9 Flag for Interrupt 12.10 - Uint16 INTx11:1; // 10 Flag for Interrupt 12.11 - Uint16 INTx12:1; // 11 Flag for Interrupt 12.12 - Uint16 INTx13:1; // 12 Flag for Interrupt 12.13 - Uint16 INTx14:1; // 13 Flag for Interrupt 12.14 - Uint16 INTx15:1; // 14 Flag for Interrupt 12.15 - Uint16 INTx16:1; // 15 Flag for Interrupt 12.16 -}; - -union PIEIFR12_REG { - Uint16 all; - struct PIEIFR12_BITS bit; -}; - -struct PIE_CTRL_REGS { - union PIECTRL_REG PIECTRL; // ePIE Control Register - union PIEACK_REG PIEACK; // Interrupt Acknowledge Register - union PIEIER1_REG PIEIER1; // Interrupt Group 1 Enable Register - union PIEIFR1_REG PIEIFR1; // Interrupt Group 1 Flag Register - union PIEIER2_REG PIEIER2; // Interrupt Group 2 Enable Register - union PIEIFR2_REG PIEIFR2; // Interrupt Group 2 Flag Register - union PIEIER3_REG PIEIER3; // Interrupt Group 3 Enable Register - union PIEIFR3_REG PIEIFR3; // Interrupt Group 3 Flag Register - union PIEIER4_REG PIEIER4; // Interrupt Group 4 Enable Register - union PIEIFR4_REG PIEIFR4; // Interrupt Group 4 Flag Register - union PIEIER5_REG PIEIER5; // Interrupt Group 5 Enable Register - union PIEIFR5_REG PIEIFR5; // Interrupt Group 5 Flag Register - union PIEIER6_REG PIEIER6; // Interrupt Group 6 Enable Register - union PIEIFR6_REG PIEIFR6; // Interrupt Group 6 Flag Register - union PIEIER7_REG PIEIER7; // Interrupt Group 7 Enable Register - union PIEIFR7_REG PIEIFR7; // Interrupt Group 7 Flag Register - union PIEIER8_REG PIEIER8; // Interrupt Group 8 Enable Register - union PIEIFR8_REG PIEIFR8; // Interrupt Group 8 Flag Register - union PIEIER9_REG PIEIER9; // Interrupt Group 9 Enable Register - union PIEIFR9_REG PIEIFR9; // Interrupt Group 9 Flag Register - union PIEIER10_REG PIEIER10; // Interrupt Group 10 Enable Register - union PIEIFR10_REG PIEIFR10; // Interrupt Group 10 Flag Register - union PIEIER11_REG PIEIER11; // Interrupt Group 11 Enable Register - union PIEIFR11_REG PIEIFR11; // Interrupt Group 11 Flag Register - union PIEIER12_REG PIEIER12; // Interrupt Group 12 Enable Register - union PIEIFR12_REG PIEIFR12; // Interrupt Group 12 Flag Register -}; - -//--------------------------------------------------------------------------- -// PIECTRL External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct PIE_CTRL_REGS PieCtrlRegs; -#endif -#ifdef CPU2 -extern volatile struct PIE_CTRL_REGS PieCtrlRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_pievect.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_pievect.h deleted file mode 100644 index 7772256c78..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_pievect.h +++ /dev/null @@ -1,306 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_pievect.h -// -// TITLE: F2837xD Device PIE Vector Table Definitions -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef F2837xD_PIE_VECT_H -#define F2837xD_PIE_VECT_H -#ifdef __cplusplus -extern "C" { -#endif - -//--------------------------------------------------------------------------- -// PIE Interrupt Vector Table Definition: -// Create a user type called PINT (pointer to interrupt): - -typedef __interrupt void (*PINT)(void); - -// Define Vector Table: -struct PIE_VECT_TABLE { - PINT PIE1_RESERVED_INT; // Reserved - PINT PIE2_RESERVED_INT; // Reserved - PINT PIE3_RESERVED_INT; // Reserved - PINT PIE4_RESERVED_INT; // Reserved - PINT PIE5_RESERVED_INT; // Reserved - PINT PIE6_RESERVED_INT; // Reserved - PINT PIE7_RESERVED_INT; // Reserved - PINT PIE8_RESERVED_INT; // Reserved - PINT PIE9_RESERVED_INT; // Reserved - PINT PIE10_RESERVED_INT; // Reserved - PINT PIE11_RESERVED_INT; // Reserved - PINT PIE12_RESERVED_INT; // Reserved - PINT PIE13_RESERVED_INT; // Reserved - PINT TIMER1_INT; // CPU Timer 1 Interrupt - PINT TIMER2_INT; // CPU Timer 2 Interrupt - PINT DATALOG_INT; // Datalogging Interrupt - PINT RTOS_INT; // RTOS Interrupt - PINT EMU_INT; // Emulation Interrupt - PINT NMI_INT; // Non-Maskable Interrupt - PINT ILLEGAL_INT; // Illegal Operation Trap - PINT USER1_INT; // User Defined Trap 1 - PINT USER2_INT; // User Defined Trap 2 - PINT USER3_INT; // User Defined Trap 3 - PINT USER4_INT; // User Defined Trap 4 - PINT USER5_INT; // User Defined Trap 5 - PINT USER6_INT; // User Defined Trap 6 - PINT USER7_INT; // User Defined Trap 7 - PINT USER8_INT; // User Defined Trap 8 - PINT USER9_INT; // User Defined Trap 9 - PINT USER10_INT; // User Defined Trap 10 - PINT USER11_INT; // User Defined Trap 11 - PINT USER12_INT; // User Defined Trap 12 - PINT ADCA1_INT; // 1.1 - ADCA Interrupt 1 - PINT ADCB1_INT; // 1.2 - ADCB Interrupt 1 - PINT ADCC1_INT; // 1.3 - ADCC Interrupt 1 - PINT XINT1_INT; // 1.4 - XINT1 Interrupt - PINT XINT2_INT; // 1.5 - XINT2 Interrupt - PINT ADCD1_INT; // 1.6 - ADCD Interrupt 1 - PINT TIMER0_INT; // 1.7 - Timer 0 Interrupt - PINT WAKE_INT; // 1.8 - Standby and Halt Wakeup Interrupt - PINT EPWM1_TZ_INT; // 2.1 - ePWM1 Trip Zone Interrupt - PINT EPWM2_TZ_INT; // 2.2 - ePWM2 Trip Zone Interrupt - PINT EPWM3_TZ_INT; // 2.3 - ePWM3 Trip Zone Interrupt - PINT EPWM4_TZ_INT; // 2.4 - ePWM4 Trip Zone Interrupt - PINT EPWM5_TZ_INT; // 2.5 - ePWM5 Trip Zone Interrupt - PINT EPWM6_TZ_INT; // 2.6 - ePWM6 Trip Zone Interrupt - PINT EPWM7_TZ_INT; // 2.7 - ePWM7 Trip Zone Interrupt - PINT EPWM8_TZ_INT; // 2.8 - ePWM8 Trip Zone Interrupt - PINT EPWM1_INT; // 3.1 - ePWM1 Interrupt - PINT EPWM2_INT; // 3.2 - ePWM2 Interrupt - PINT EPWM3_INT; // 3.3 - ePWM3 Interrupt - PINT EPWM4_INT; // 3.4 - ePWM4 Interrupt - PINT EPWM5_INT; // 3.5 - ePWM5 Interrupt - PINT EPWM6_INT; // 3.6 - ePWM6 Interrupt - PINT EPWM7_INT; // 3.7 - ePWM7 Interrupt - PINT EPWM8_INT; // 3.8 - ePWM8 Interrupt - PINT ECAP1_INT; // 4.1 - eCAP1 Interrupt - PINT ECAP2_INT; // 4.2 - eCAP2 Interrupt - PINT ECAP3_INT; // 4.3 - eCAP3 Interrupt - PINT ECAP4_INT; // 4.4 - eCAP4 Interrupt - PINT ECAP5_INT; // 4.5 - eCAP5 Interrupt - PINT ECAP6_INT; // 4.6 - eCAP6 Interrupt - PINT PIE14_RESERVED_INT; // 4.7 - Reserved - PINT PIE15_RESERVED_INT; // 4.8 - Reserved - PINT EQEP1_INT; // 5.1 - eQEP1 Interrupt - PINT EQEP2_INT; // 5.2 - eQEP2 Interrupt - PINT EQEP3_INT; // 5.3 - eQEP3 Interrupt - PINT PIE16_RESERVED_INT; // 5.4 - Reserved - PINT PIE17_RESERVED_INT; // 5.5 - Reserved - PINT PIE18_RESERVED_INT; // 5.6 - Reserved - PINT PIE19_RESERVED_INT; // 5.7 - Reserved - PINT PIE20_RESERVED_INT; // 5.8 - Reserved - PINT SPIA_RX_INT; // 6.1 - SPIA Receive Interrupt - PINT SPIA_TX_INT; // 6.2 - SPIA Transmit Interrupt - PINT SPIB_RX_INT; // 6.3 - SPIB Receive Interrupt - PINT SPIB_TX_INT; // 6.4 - SPIB Transmit Interrupt - PINT MCBSPA_RX_INT; // 6.5 - McBSPA Receive Interrupt - PINT MCBSPA_TX_INT; // 6.6 - McBSPA Transmit Interrupt - PINT MCBSPB_RX_INT; // 6.7 - McBSPB Receive Interrupt - PINT MCBSPB_TX_INT; // 6.8 - McBSPB Transmit Interrupt - PINT DMA_CH1_INT; // 7.1 - DMA Channel 1 Interrupt - PINT DMA_CH2_INT; // 7.2 - DMA Channel 2 Interrupt - PINT DMA_CH3_INT; // 7.3 - DMA Channel 3 Interrupt - PINT DMA_CH4_INT; // 7.4 - DMA Channel 4 Interrupt - PINT DMA_CH5_INT; // 7.5 - DMA Channel 5 Interrupt - PINT DMA_CH6_INT; // 7.6 - DMA Channel 6 Interrupt - PINT PIE21_RESERVED_INT; // 7.7 - Reserved - PINT PIE22_RESERVED_INT; // 7.8 - Reserved - PINT I2CA_INT; // 8.1 - I2CA Interrupt 1 - PINT I2CA_FIFO_INT; // 8.2 - I2CA Interrupt 2 - PINT I2CB_INT; // 8.3 - I2CB Interrupt 1 - PINT I2CB_FIFO_INT; // 8.4 - I2CB Interrupt 2 - PINT SCIC_RX_INT; // 8.5 - SCIC Receive Interrupt - PINT SCIC_TX_INT; // 8.6 - SCIC Transmit Interrupt - PINT SCID_RX_INT; // 8.7 - SCID Receive Interrupt - PINT SCID_TX_INT; // 8.8 - SCID Transmit Interrupt - PINT SCIA_RX_INT; // 9.1 - SCIA Receive Interrupt - PINT SCIA_TX_INT; // 9.2 - SCIA Transmit Interrupt - PINT SCIB_RX_INT; // 9.3 - SCIB Receive Interrupt - PINT SCIB_TX_INT; // 9.4 - SCIB Transmit Interrupt - PINT CANA0_INT; // 9.5 - CANA Interrupt 0 - PINT CANA1_INT; // 9.6 - CANA Interrupt 1 - PINT CANB0_INT; // 9.7 - CANB Interrupt 0 - PINT CANB1_INT; // 9.8 - CANB Interrupt 1 - PINT ADCA_EVT_INT; // 10.1 - ADCA Event Interrupt - PINT ADCA2_INT; // 10.2 - ADCA Interrupt 2 - PINT ADCA3_INT; // 10.3 - ADCA Interrupt 3 - PINT ADCA4_INT; // 10.4 - ADCA Interrupt 4 - PINT ADCB_EVT_INT; // 10.5 - ADCB Event Interrupt - PINT ADCB2_INT; // 10.6 - ADCB Interrupt 2 - PINT ADCB3_INT; // 10.7 - ADCB Interrupt 3 - PINT ADCB4_INT; // 10.8 - ADCB Interrupt 4 - PINT CLA1_1_INT; // 11.1 - CLA1 Interrupt 1 - PINT CLA1_2_INT; // 11.2 - CLA1 Interrupt 2 - PINT CLA1_3_INT; // 11.3 - CLA1 Interrupt 3 - PINT CLA1_4_INT; // 11.4 - CLA1 Interrupt 4 - PINT CLA1_5_INT; // 11.5 - CLA1 Interrupt 5 - PINT CLA1_6_INT; // 11.6 - CLA1 Interrupt 6 - PINT CLA1_7_INT; // 11.7 - CLA1 Interrupt 7 - PINT CLA1_8_INT; // 11.8 - CLA1 Interrupt 8 - PINT XINT3_INT; // 12.1 - XINT3 Interrupt - PINT XINT4_INT; // 12.2 - XINT4 Interrupt - PINT XINT5_INT; // 12.3 - XINT5 Interrupt - PINT PIE23_RESERVED_INT; // 12.4 - Reserved - PINT PIE24_RESERVED_INT; // 12.5 - Reserved - PINT VCU_INT; // 12.6 - VCU Interrupt - PINT FPU_OVERFLOW_INT; // 12.7 - FPU Overflow Interrupt - PINT FPU_UNDERFLOW_INT; // 12.8 - FPU Underflow Interrupt - PINT PIE25_RESERVED_INT; // 1.9 - Reserved - PINT PIE26_RESERVED_INT; // 1.10 - Reserved - PINT PIE27_RESERVED_INT; // 1.11 - Reserved - PINT PIE28_RESERVED_INT; // 1.12 - Reserved - PINT IPC0_INT; // 1.13 - IPC Interrupt 0 - PINT IPC1_INT; // 1.14 - IPC Interrupt 1 - PINT IPC2_INT; // 1.15 - IPC Interrupt 2 - PINT IPC3_INT; // 1.16 - IPC Interrupt 3 - PINT EPWM9_TZ_INT; // 2.9 - ePWM9 Trip Zone Interrupt - PINT EPWM10_TZ_INT; // 2.10 - ePWM10 Trip Zone Interrupt - PINT EPWM11_TZ_INT; // 2.11 - ePWM11 Trip Zone Interrupt - PINT EPWM12_TZ_INT; // 2.12 - ePWM12 Trip Zone Interrupt - PINT PIE29_RESERVED_INT; // 2.13 - Reserved - PINT PIE30_RESERVED_INT; // 2.14 - Reserved - PINT PIE31_RESERVED_INT; // 2.15 - Reserved - PINT PIE32_RESERVED_INT; // 2.16 - Reserved - PINT EPWM9_INT; // 3.9 - ePWM9 Interrupt - PINT EPWM10_INT; // 3.10 - ePWM10 Interrupt - PINT EPWM11_INT; // 3.11 - ePWM11 Interrupt - PINT EPWM12_INT; // 3.12 - ePWM12 Interrupt - PINT PIE33_RESERVED_INT; // 3.13 - Reserved - PINT PIE34_RESERVED_INT; // 3.14 - Reserved - PINT PIE35_RESERVED_INT; // 3.15 - Reserved - PINT PIE36_RESERVED_INT; // 3.16 - Reserved - PINT PIE37_RESERVED_INT; // 4.9 - Reserved - PINT PIE38_RESERVED_INT; // 4.10 - Reserved - PINT PIE39_RESERVED_INT; // 4.11 - Reserved - PINT PIE40_RESERVED_INT; // 4.12 - Reserved - PINT PIE41_RESERVED_INT; // 4.13 - Reserved - PINT PIE42_RESERVED_INT; // 4.14 - Reserved - PINT PIE43_RESERVED_INT; // 4.15 - Reserved - PINT PIE44_RESERVED_INT; // 4.16 - Reserved - PINT SD1_INT; // 5.9 - SD1 Interrupt - PINT SD2_INT; // 5.10 - SD2 Interrupt - PINT PIE45_RESERVED_INT; // 5.11 - Reserved - PINT PIE46_RESERVED_INT; // 5.12 - Reserved - PINT PIE47_RESERVED_INT; // 5.13 - Reserved - PINT PIE48_RESERVED_INT; // 5.14 - Reserved - PINT PIE49_RESERVED_INT; // 5.15 - Reserved - PINT PIE50_RESERVED_INT; // 5.16 - Reserved - PINT SPIC_RX_INT; // 6.9 - SPIC Receive Interrupt - PINT SPIC_TX_INT; // 6.10 - SPIC Transmit Interrupt - PINT PIE51_RESERVED_INT; // 6.11 - Reserved - PINT PIE52_RESERVED_INT; // 6.12 - Reserved - PINT PIE53_RESERVED_INT; // 6.13 - Reserved - PINT PIE54_RESERVED_INT; // 6.14 - Reserved - PINT PIE55_RESERVED_INT; // 6.15 - Reserved - PINT PIE56_RESERVED_INT; // 6.16 - Reserved - PINT PIE57_RESERVED_INT; // 7.9 - Reserved - PINT PIE58_RESERVED_INT; // 7.10 - Reserved - PINT PIE59_RESERVED_INT; // 7.11 - Reserved - PINT PIE60_RESERVED_INT; // 7.12 - Reserved - PINT PIE61_RESERVED_INT; // 7.13 - Reserved - PINT PIE62_RESERVED_INT; // 7.14 - Reserved - PINT PIE63_RESERVED_INT; // 7.15 - Reserved - PINT PIE64_RESERVED_INT; // 7.16 - Reserved - PINT PIE65_RESERVED_INT; // 8.9 - Reserved - PINT PIE66_RESERVED_INT; // 8.10 - Reserved - PINT PIE67_RESERVED_INT; // 8.11 - Reserved - PINT PIE68_RESERVED_INT; // 8.12 - Reserved - PINT PIE69_RESERVED_INT; // 8.13 - Reserved - PINT PIE70_RESERVED_INT; // 8.14 - Reserved -#ifdef CPU1 - PINT UPPA_INT; // 8.15 - uPPA Interrupt - PINT PIE72_RESERVED_INT; // 8.16 - Reserved -#elif defined(CPU2) - PINT PIE71_RESERVED_INT; // 8.15 - Reserved - PINT PIE72_RESERVED_INT; // 8.16 - Reserved -#endif - PINT PIE73_RESERVED_INT; // 9.9 - Reserved - PINT PIE74_RESERVED_INT; // 9.10 - Reserved - PINT PIE75_RESERVED_INT; // 9.11 - Reserved - PINT PIE76_RESERVED_INT; // 9.12 - Reserved - PINT PIE77_RESERVED_INT; // 9.13 - Reserved - PINT PIE78_RESERVED_INT; // 9.14 - Reserved -#ifdef CPU1 - PINT USBA_INT; // 9.15 - USBA Interrupt -#elif defined(CPU2) - PINT PIE79_RESERVED_INT; // 9.15 - Reserved -#endif - PINT PIE80_RESERVED_INT; // 9.16 - Reserved - PINT ADCC_EVT_INT; // 10.9 - ADCC Event Interrupt - PINT ADCC2_INT; // 10.10 - ADCC Interrupt 2 - PINT ADCC3_INT; // 10.11 - ADCC Interrupt 3 - PINT ADCC4_INT; // 10.12 - ADCC Interrupt 4 - PINT ADCD_EVT_INT; // 10.13 - ADCD Event Interrupt - PINT ADCD2_INT; // 10.14 - ADCD Interrupt 2 - PINT ADCD3_INT; // 10.15 - ADCD Interrupt 3 - PINT ADCD4_INT; // 10.16 - ADCD Interrupt 4 - PINT PIE81_RESERVED_INT; // 11.9 - Reserved - PINT PIE82_RESERVED_INT; // 11.10 - Reserved - PINT PIE83_RESERVED_INT; // 11.11 - Reserved - PINT PIE84_RESERVED_INT; // 11.12 - Reserved - PINT PIE85_RESERVED_INT; // 11.13 - Reserved - PINT PIE86_RESERVED_INT; // 11.14 - Reserved - PINT PIE87_RESERVED_INT; // 11.15 - Reserved - PINT PIE88_RESERVED_INT; // 11.16 - Reserved - PINT EMIF_ERROR_INT; // 12.9 - EMIF Error Interrupt - PINT RAM_CORRECTABLE_ERROR_INT; // 12.10 - RAM Correctable Error Interrupt - PINT FLASH_CORRECTABLE_ERROR_INT; // 12.11 - Flash Correctable Error Interrupt - PINT RAM_ACCESS_VIOLATION_INT; // 12.12 - RAM Access Violation Interrupt - PINT SYS_PLL_SLIP_INT; // 12.13 - System PLL Slip Interrupt - PINT AUX_PLL_SLIP_INT; // 12.14 - Auxiliary PLL Slip Interrupt - PINT CLA_OVERFLOW_INT; // 12.15 - CLA Overflow Interrupt - PINT CLA_UNDERFLOW_INT; // 12.16 - CLA Underflow Interrupt -}; - -//--------------------------------------------------------------------------- -// PieVect External References & Function Declarations: -// - -extern volatile struct PIE_VECT_TABLE PieVectTable; - -#ifdef __cplusplus -} -#endif /* extern "C" */ - - -#endif // end of F2837xD_PIEVECT_H definition -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sci.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sci.h deleted file mode 100644 index ae1cf3c422..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sci.h +++ /dev/null @@ -1,266 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_sci.h -// -// TITLE: SCI Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_SCI_H__ -#define __F2837xD_SCI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// SCI Individual Register Bit Definitions: - -struct SCICCR_BITS { // bits description - Uint16 SCICHAR:3; // 2:0 Character length control - Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control - Uint16 LOOPBKENA:1; // 4 Loop Back enable - Uint16 PARITYENA:1; // 5 Parity enable - Uint16 PARITY:1; // 6 Even or Odd Parity - Uint16 STOPBITS:1; // 7 Number of Stop Bits - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCICCR_REG { - Uint16 all; - struct SCICCR_BITS bit; -}; - -struct SCICTL1_BITS { // bits description - Uint16 RXENA:1; // 0 SCI receiver enable - Uint16 TXENA:1; // 1 SCI transmitter enable - Uint16 SLEEP:1; // 2 SCI sleep - Uint16 TXWAKE:1; // 3 Transmitter wakeup method - Uint16 rsvd1:1; // 4 Reserved - Uint16 SWRESET:1; // 5 Software reset - Uint16 RXERRINTENA:1; // 6 Recieve __interrupt enable - Uint16 rsvd2:9; // 15:7 Reserved -}; - -union SCICTL1_REG { - Uint16 all; - struct SCICTL1_BITS bit; -}; - -struct SCIHBAUD_BITS { // bits description - Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCIHBAUD - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCIHBAUD_REG { - Uint16 all; - struct SCIHBAUD_BITS bit; -}; - -struct SCILBAUD_BITS { // bits description - Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCILBAUD - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCILBAUD_REG { - Uint16 all; - struct SCILBAUD_BITS bit; -}; - -struct SCICTL2_BITS { // bits description - Uint16 TXINTENA:1; // 0 Transmit __interrupt enable - Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable - Uint16 rsvd1:4; // 5:2 Reserved - Uint16 TXEMPTY:1; // 6 Transmitter empty flag - Uint16 TXRDY:1; // 7 Transmitter ready flag - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union SCICTL2_REG { - Uint16 all; - struct SCICTL2_BITS bit; -}; - -struct SCIRXST_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag - Uint16 PE:1; // 2 Parity error flag - Uint16 OE:1; // 3 Overrun error flag - Uint16 FE:1; // 4 Framing error flag - Uint16 BRKDT:1; // 5 Break-detect flag - Uint16 RXRDY:1; // 6 Receiver ready flag - Uint16 RXERROR:1; // 7 Receiver error flag - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union SCIRXST_REG { - Uint16 all; - struct SCIRXST_BITS bit; -}; - -struct SCIRXEMU_BITS { // bits description - Uint16 ERXDT:8; // 7:0 Receive emulation buffer data - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCIRXEMU_REG { - Uint16 all; - struct SCIRXEMU_BITS bit; -}; - -struct SCIRXBUF_BITS { // bits description - Uint16 SAR:8; // 7:0 Receive Character bits - Uint16 rsvd1:6; // 13:8 Reserved - Uint16 SCIFFPE:1; // 14 Receiver error flag - Uint16 SCIFFFE:1; // 15 Receiver error flag -}; - -union SCIRXBUF_REG { - Uint16 all; - struct SCIRXBUF_BITS bit; -}; - -struct SCITXBUF_BITS { // bits description - Uint16 TXDT:8; // 7:0 Transmit data buffer - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SCITXBUF_REG { - Uint16 all; - struct SCITXBUF_BITS bit; -}; - -struct SCIFFTX_BITS { // bits description - Uint16 TXFFIL:5; // 4:0 Interrupt level - Uint16 TXFFIENA:1; // 5 Interrupt enable - Uint16 TXFFINTCLR:1; // 6 Clear INT flag - Uint16 TXFFINT:1; // 7 INT flag - Uint16 TXFFST:5; // 12:8 FIFO status - Uint16 TXFIFORESET:1; // 13 FIFO reset - Uint16 SCIFFENA:1; // 14 Enhancement enable - Uint16 SCIRST:1; // 15 SCI reset rx/tx channels -}; - -union SCIFFTX_REG { - Uint16 all; - struct SCIFFTX_BITS bit; -}; - -struct SCIFFRX_BITS { // bits description - Uint16 RXFFIL:5; // 4:0 Interrupt level - Uint16 RXFFIENA:1; // 5 Interrupt enable - Uint16 RXFFINTCLR:1; // 6 Clear INT flag - Uint16 RXFFINT:1; // 7 INT flag - Uint16 RXFFST:5; // 12:8 FIFO status - Uint16 RXFIFORESET:1; // 13 FIFO reset - Uint16 RXFFOVRCLR:1; // 14 Clear overflow - Uint16 RXFFOVF:1; // 15 FIFO overflow -}; - -union SCIFFRX_REG { - Uint16 all; - struct SCIFFRX_BITS bit; -}; - -struct SCIFFCT_BITS { // bits description - Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay - Uint16 rsvd1:5; // 12:8 Reserved - Uint16 CDC:1; // 13 Auto baud mode enable - Uint16 ABDCLR:1; // 14 Auto baud clear - Uint16 ABD:1; // 15 Auto baud detect -}; - -union SCIFFCT_REG { - Uint16 all; - struct SCIFFCT_BITS bit; -}; - -struct SCIPRI_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 FREESOFT:2; // 4:3 Emulation modes - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 rsvd3:8; // 15:8 Reserved -}; - -union SCIPRI_REG { - Uint16 all; - struct SCIPRI_BITS bit; -}; - -struct SCI_REGS { - union SCICCR_REG SCICCR; // Communications control register - union SCICTL1_REG SCICTL1; // Control register 1 - union SCIHBAUD_REG SCIHBAUD; // Baud rate (high) register - union SCILBAUD_REG SCILBAUD; // Baud rate (low) register - union SCICTL2_REG SCICTL2; // Control register 2 - union SCIRXST_REG SCIRXST; // Recieve status register - union SCIRXEMU_REG SCIRXEMU; // Recieve emulation buffer register - union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer - Uint16 rsvd1; // Reserved - union SCITXBUF_REG SCITXBUF; // Transmit data buffer - union SCIFFTX_REG SCIFFTX; // FIFO transmit register - union SCIFFRX_REG SCIFFRX; // FIFO recieve register - union SCIFFCT_REG SCIFFCT; // FIFO control register - Uint16 rsvd2[2]; // Reserved - union SCIPRI_REG SCIPRI; // SCI Priority control -}; - -//--------------------------------------------------------------------------- -// SCI External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct SCI_REGS SciaRegs; -extern volatile struct SCI_REGS ScibRegs; -extern volatile struct SCI_REGS ScicRegs; -extern volatile struct SCI_REGS ScidRegs; -#endif -#ifdef CPU2 -extern volatile struct SCI_REGS SciaRegs; -extern volatile struct SCI_REGS ScibRegs; -extern volatile struct SCI_REGS ScicRegs; -extern volatile struct SCI_REGS ScidRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sdfm.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sdfm.h deleted file mode 100644 index 7506115073..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sdfm.h +++ /dev/null @@ -1,534 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_sdfm.h -// -// TITLE: SDFM Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_SDFM_H__ -#define __F2837xD_SDFM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// SDFM Individual Register Bit Definitions: - -struct SDIFLG_BITS { // bits description - Uint16 IFH1:1; // 0 High-level Interrupt flag Filter 1 - Uint16 IFL1:1; // 1 Low-Level Interrupt flag Filter 1 - Uint16 IFH2:1; // 2 High-level Interrupt flag Filter 2 - Uint16 IFL2:1; // 3 Low-Level Interrupt flag Filter 2 - Uint16 IFH3:1; // 4 High-level Interrupt flag Filter 3 - Uint16 IFL3:1; // 5 Low-Level Interrupt flag Filter 3 - Uint16 IFH4:1; // 6 High-level Interrupt flag Filter 4 - Uint16 IFL4:1; // 7 Low-Level Interrupt flag Filter 4 - Uint16 MF1:1; // 8 Modulator Failure for Filter 1 - Uint16 MF2:1; // 9 Modulator Failure for Filter 2 - Uint16 MF3:1; // 10 Modulator Failure for Filter 3 - Uint16 MF4:1; // 11 Modulator Failure for Filter 4 - Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 - Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 - Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 - Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 - Uint16 rsvd1:15; // 30:16 Reserved - Uint16 MIF:1; // 31 Master Interrupt Flag -}; - -union SDIFLG_REG { - Uint32 all; - struct SDIFLG_BITS bit; -}; - -struct SDIFLGCLR_BITS { // bits description - Uint16 IFH1:1; // 0 High-level Interrupt flag Filter 1 - Uint16 IFL1:1; // 1 Low-Level Interrupt flag Filter 1 - Uint16 IFH2:1; // 2 High-level Interrupt flag Filter 2 - Uint16 IFL2:1; // 3 Low-Level Interrupt flag Filter 2 - Uint16 IFH3:1; // 4 High-level Interrupt flag Filter 3 - Uint16 IFL3:1; // 5 Low-Level Interrupt flag Filter 3 - Uint16 IFH4:1; // 6 High-level Interrupt flag Filter 4 - Uint16 IFL4:1; // 7 Low-Level Interrupt flag Filter 4 - Uint16 MF1:1; // 8 Modulator Failure for Filter 1 - Uint16 MF2:1; // 9 Modulator Failure for Filter 2 - Uint16 MF3:1; // 10 Modulator Failure for Filter 3 - Uint16 MF4:1; // 11 Modulator Failure for Filter 4 - Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 - Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 - Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 - Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 - Uint16 rsvd1:15; // 30:16 Reserved - Uint16 MIF:1; // 31 Master Interrupt Flag -}; - -union SDIFLGCLR_REG { - Uint32 all; - struct SDIFLGCLR_BITS bit; -}; - -struct SDCTL_BITS { // bits description - Uint16 rsvd1:13; // 12:0 Reserved - Uint16 MIE:1; // 13 Master Interrupt enable - Uint16 rsvd2:1; // 14 Reserved - Uint16 rsvd3:1; // 15 Reserved -}; - -union SDCTL_REG { - Uint16 all; - struct SDCTL_BITS bit; -}; - -struct SDMFILEN_BITS { // bits description - Uint16 rsvd1:4; // 3:0 Reserved - Uint16 rsvd2:3; // 6:4 Reserved - Uint16 rsvd3:2; // 8:7 Reserved - Uint16 rsvd4:1; // 9 Reserved - Uint16 rsvd5:1; // 10 Reserved - Uint16 MFE:1; // 11 Master Filter Enable. - Uint16 rsvd6:1; // 12 Reserved - Uint16 rsvd7:3; // 15:13 Reserved -}; - -union SDMFILEN_REG { - Uint16 all; - struct SDMFILEN_BITS bit; -}; - -struct SDCTLPARM1_BITS { // bits description - Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved -}; - -union SDCTLPARM1_REG { - Uint16 all; - struct SDCTLPARM1_BITS bit; -}; - -struct SDDFPARM1_BITS { // bits description - Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 - Uint16 FEN:1; // 8 Filter Enable - Uint16 AE:1; // 9 Ack Enable - Uint16 SST:2; // 11:10 Data Filter Structure (DataFast/1/2/3) - Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union SDDFPARM1_REG { - Uint16 all; - struct SDDFPARM1_BITS bit; -}; - -struct SDDPARM1_BITS { // bits description - Uint16 rsvd1:7; // 6:0 Reserved - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 rsvd4:1; // 9 Reserved - Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) - Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) -}; - -union SDDPARM1_REG { - Uint16 all; - struct SDDPARM1_BITS bit; -}; - -struct SDCMPH1_BITS { // bits description - Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPH1_REG { - Uint16 all; - struct SDCMPH1_BITS bit; -}; - -struct SDCMPL1_BITS { // bits description - Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPL1_REG { - Uint16 all; - struct SDCMPL1_BITS bit; -}; - -struct SDCPARM1_BITS { // bits description - Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 - Uint16 IEH:1; // 5 High-level interrupt enable - Uint16 IEL:1; // 6 Low-level interrupt enable - Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 - Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union SDCPARM1_REG { - Uint16 all; - struct SDCPARM1_BITS bit; -}; - -struct SDDATA1_BITS { // bits description - Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode -}; - -union SDDATA1_REG { - Uint32 all; - struct SDDATA1_BITS bit; -}; - -struct SDCTLPARM2_BITS { // bits description - Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved -}; - -union SDCTLPARM2_REG { - Uint16 all; - struct SDCTLPARM2_BITS bit; -}; - -struct SDDFPARM2_BITS { // bits description - Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 - Uint16 FEN:1; // 8 Filter Enable - Uint16 AE:1; // 9 Ack Enable - Uint16 SST:2; // 11:10 Data Filter Structure (SincFast/1/2/3) - Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union SDDFPARM2_REG { - Uint16 all; - struct SDDFPARM2_BITS bit; -}; - -struct SDDPARM2_BITS { // bits description - Uint16 rsvd1:7; // 6:0 Reserved - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 rsvd4:1; // 9 Reserved - Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) - Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) -}; - -union SDDPARM2_REG { - Uint16 all; - struct SDDPARM2_BITS bit; -}; - -struct SDCMPH2_BITS { // bits description - Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPH2_REG { - Uint16 all; - struct SDCMPH2_BITS bit; -}; - -struct SDCMPL2_BITS { // bits description - Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPL2_REG { - Uint16 all; - struct SDCMPL2_BITS bit; -}; - -struct SDCPARM2_BITS { // bits description - Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 - Uint16 IEH:1; // 5 High-level interrupt enable - Uint16 IEL:1; // 6 Low-level interrupt enable - Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 - Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union SDCPARM2_REG { - Uint16 all; - struct SDCPARM2_BITS bit; -}; - -struct SDDATA2_BITS { // bits description - Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode -}; - -union SDDATA2_REG { - Uint32 all; - struct SDDATA2_BITS bit; -}; - -struct SDCTLPARM3_BITS { // bits description - Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved -}; - -union SDCTLPARM3_REG { - Uint16 all; - struct SDCTLPARM3_BITS bit; -}; - -struct SDDFPARM3_BITS { // bits description - Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 - Uint16 FEN:1; // 8 Filter Enable - Uint16 AE:1; // 9 Ack Enable - Uint16 SST:2; // 11:10 Data filter structure (SincFast/1/2/3) - Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union SDDFPARM3_REG { - Uint16 all; - struct SDDFPARM3_BITS bit; -}; - -struct SDDPARM3_BITS { // bits description - Uint16 rsvd1:7; // 6:0 Reserved - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 rsvd4:1; // 9 Reserved - Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) - Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) -}; - -union SDDPARM3_REG { - Uint16 all; - struct SDDPARM3_BITS bit; -}; - -struct SDCMPH3_BITS { // bits description - Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPH3_REG { - Uint16 all; - struct SDCMPH3_BITS bit; -}; - -struct SDCMPL3_BITS { // bits description - Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPL3_REG { - Uint16 all; - struct SDCMPL3_BITS bit; -}; - -struct SDCPARM3_BITS { // bits description - Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 - Uint16 IEH:1; // 5 High-level interrupt enable - Uint16 IEL:1; // 6 Low-level interrupt enable - Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 - Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union SDCPARM3_REG { - Uint16 all; - struct SDCPARM3_BITS bit; -}; - -struct SDDATA3_BITS { // bits description - Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode -}; - -union SDDATA3_REG { - Uint32 all; - struct SDDATA3_BITS bit; -}; - -struct SDCTLPARM4_BITS { // bits description - Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:11; // 15:5 Reserved -}; - -union SDCTLPARM4_REG { - Uint16 all; - struct SDCTLPARM4_BITS bit; -}; - -struct SDDFPARM4_BITS { // bits description - Uint16 DOSR:8; // 7:0 SINC Filter Oversample Ratio= DOSR+1 - Uint16 FEN:1; // 8 Filter Enable - Uint16 AE:1; // 9 Ack Enable - Uint16 SST:2; // 11:10 Data filter structure (SincFast/1/2/3) - Uint16 SDSYNCEN:1; // 12 SINC FILTER Reset Enable - Uint16 rsvd1:3; // 15:13 Reserved -}; - -union SDDFPARM4_REG { - Uint16 all; - struct SDDFPARM4_BITS bit; -}; - -struct SDDPARM4_BITS { // bits description - Uint16 rsvd1:7; // 6:0 Reserved - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:1; // 8 Reserved - Uint16 rsvd4:1; // 9 Reserved - Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) - Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) -}; - -union SDDPARM4_REG { - Uint16 all; - struct SDDPARM4_BITS bit; -}; - -struct SDCMPH4_BITS { // bits description - Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPH4_REG { - Uint16 all; - struct SDCMPH4_BITS bit; -}; - -struct SDCMPL4_BITS { // bits description - Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. - Uint16 rsvd1:1; // 15 Reserved -}; - -union SDCMPL4_REG { - Uint16 all; - struct SDCMPL4_BITS bit; -}; - -struct SDCPARM4_BITS { // bits description - Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 - Uint16 IEH:1; // 5 High-level interrupt enable - Uint16 IEL:1; // 6 Low-level interrupt enable - Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 - Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable - Uint16 rsvd1:6; // 15:10 Reserved -}; - -union SDCPARM4_REG { - Uint16 all; - struct SDCPARM4_BITS bit; -}; - -struct SDDATA4_BITS { // bits description - Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode - Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode -}; - -union SDDATA4_REG { - Uint32 all; - struct SDDATA4_BITS bit; -}; - -struct SDFM_REGS { - union SDIFLG_REG SDIFLG; // Interrupt Flag Register - union SDIFLGCLR_REG SDIFLGCLR; // Interrupt Flag Clear Register - union SDCTL_REG SDCTL; // SD Control Register - Uint16 rsvd1; // Reserved - union SDMFILEN_REG SDMFILEN; // SD Master Filter Enable - Uint16 rsvd2[9]; // Reserved - union SDCTLPARM1_REG SDCTLPARM1; // Control Parameter Register for Ch1 - union SDDFPARM1_REG SDDFPARM1; // Data Filter Parameter Register for Ch1 - union SDDPARM1_REG SDDPARM1; // Integer Parameter Register for Ch1 - union SDCMPH1_REG SDCMPH1; // High-level Threshold Register for Ch1 - union SDCMPL1_REG SDCMPL1; // Low-level Threshold Register for Ch1 - union SDCPARM1_REG SDCPARM1; // Comparator Parameter Register for Ch1 - union SDDATA1_REG SDDATA1; // Filter Data Register (16 or 32bit) for Ch1 - Uint16 rsvd3[8]; // Reserved - union SDCTLPARM2_REG SDCTLPARM2; // Control Parameter Register for Ch2 - union SDDFPARM2_REG SDDFPARM2; // Data Filter Parameter Register for Ch2 - union SDDPARM2_REG SDDPARM2; // Integer Parameter Register for Ch2 - union SDCMPH2_REG SDCMPH2; // High-level Threshold Register for Ch2 - union SDCMPL2_REG SDCMPL2; // Low-level Threshold Register for Ch2 - union SDCPARM2_REG SDCPARM2; // Comparator Parameter Register for Ch2 - union SDDATA2_REG SDDATA2; // Filter Data Register (16 or 32bit) for Ch2 - Uint16 rsvd4[8]; // Reserved - union SDCTLPARM3_REG SDCTLPARM3; // Control Parameter Register for Ch3 - union SDDFPARM3_REG SDDFPARM3; // Data Filter Parameter Register for Ch3 - union SDDPARM3_REG SDDPARM3; // Integer Parameter Register for Ch3 - union SDCMPH3_REG SDCMPH3; // High-level Threshold Register for Ch3 - union SDCMPL3_REG SDCMPL3; // Low-level Threshold Register for Ch3 - union SDCPARM3_REG SDCPARM3; // Comparator Parameter Register for Ch3 - union SDDATA3_REG SDDATA3; // Filter Data Register (16 or 32bit) for Ch3 - Uint16 rsvd5[8]; // Reserved - union SDCTLPARM4_REG SDCTLPARM4; // Control Parameter Register for Ch4 - union SDDFPARM4_REG SDDFPARM4; // Data Filter Parameter Register for Ch4 - union SDDPARM4_REG SDDPARM4; // Integer Parameter Register for Ch4 - union SDCMPH4_REG SDCMPH4; // High-level Threshold Register for Ch4 - union SDCMPL4_REG SDCMPL4; // Low-level Threshold Register for Ch4 - union SDCPARM4_REG SDCPARM4; // Comparator Parameter Register for Ch4 - union SDDATA4_REG SDDATA4; // Filter Data Register (16 or 32bit) for Ch4 - Uint16 rsvd6[56]; // Reserved -}; - -//--------------------------------------------------------------------------- -// SDFM External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct SDFM_REGS Sdfm1Regs; -extern volatile struct SDFM_REGS Sdfm2Regs; -#endif -#ifdef CPU2 -extern volatile struct SDFM_REGS Sdfm1Regs; -extern volatile struct SDFM_REGS Sdfm2Regs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_spi.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_spi.h deleted file mode 100644 index 30e2e6babb..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_spi.h +++ /dev/null @@ -1,201 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_spi.h -// -// TITLE: SPI Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_SPI_H__ -#define __F2837xD_SPI_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// SPI Individual Register Bit Definitions: - -struct SPICCR_BITS { // bits description - Uint16 SPICHAR:4; // 3:0 Character Length Control - Uint16 SPILBK:1; // 4 SPI Loopback - Uint16 HS_MODE:1; // 5 High Speed mode control - Uint16 CLKPOLARITY:1; // 6 Shift Clock Polarity - Uint16 SPISWRESET:1; // 7 SPI Software Reset - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SPICCR_REG { - Uint16 all; - struct SPICCR_BITS bit; -}; - -struct SPICTL_BITS { // bits description - Uint16 SPIINTENA:1; // 0 SPI Interupt Enable - Uint16 TALK:1; // 1 Master/Slave Transmit Enable - Uint16 MASTER_SLAVE:1; // 2 SPI Network Mode Control - Uint16 CLK_PHASE:1; // 3 SPI Clock Phase - Uint16 OVERRUNINTENA:1; // 4 Overrun Interrupt Enable - Uint16 rsvd1:11; // 15:5 Reserved -}; - -union SPICTL_REG { - Uint16 all; - struct SPICTL_BITS bit; -}; - -struct SPISTS_BITS { // bits description - Uint16 rsvd1:5; // 4:0 Reserved - Uint16 BUFFULL_FLAG:1; // 5 SPI Transmit Buffer Full Flag - Uint16 INT_FLAG:1; // 6 SPI Interrupt Flag - Uint16 OVERRUN_FLAG:1; // 7 SPI Receiver Overrun Flag - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union SPISTS_REG { - Uint16 all; - struct SPISTS_BITS bit; -}; - -struct SPIBRR_BITS { // bits description - Uint16 SPI_BIT_RATE:7; // 6:0 SPI Bit Rate Control - Uint16 rsvd1:9; // 15:7 Reserved -}; - -union SPIBRR_REG { - Uint16 all; - struct SPIBRR_BITS bit; -}; - -struct SPIFFTX_BITS { // bits description - Uint16 TXFFIL:5; // 4:0 TXFIFO Interrupt Level - Uint16 TXFFIENA:1; // 5 TXFIFO Interrupt Enable - Uint16 TXFFINTCLR:1; // 6 TXFIFO Interrupt Clear - Uint16 TXFFINT:1; // 7 TXFIFO Interrupt Flag - Uint16 TXFFST:5; // 12:8 Transmit FIFO Status - Uint16 TXFIFO:1; // 13 TXFIFO Reset - Uint16 SPIFFENA:1; // 14 FIFO Enhancements Enable - Uint16 SPIRST:1; // 15 SPI Reset -}; - -union SPIFFTX_REG { - Uint16 all; - struct SPIFFTX_BITS bit; -}; - -struct SPIFFRX_BITS { // bits description - Uint16 RXFFIL:5; // 4:0 RXFIFO Interrupt Level - Uint16 RXFFIENA:1; // 5 RXFIFO Interrupt Enable - Uint16 RXFFINTCLR:1; // 6 RXFIFO Interupt Clear - Uint16 RXFFINT:1; // 7 RXFIFO Interrupt Flag - Uint16 RXFFST:5; // 12:8 Receive FIFO Status - Uint16 RXFIFORESET:1; // 13 RXFIFO Reset - Uint16 RXFFOVFCLR:1; // 14 Receive FIFO Overflow Clear - Uint16 RXFFOVF:1; // 15 Receive FIFO Overflow Flag -}; - -union SPIFFRX_REG { - Uint16 all; - struct SPIFFRX_BITS bit; -}; - -struct SPIFFCT_BITS { // bits description - Uint16 TXDLY:8; // 7:0 FIFO Transmit Delay Bits - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union SPIFFCT_REG { - Uint16 all; - struct SPIFFCT_BITS bit; -}; - -struct SPIPRI_BITS { // bits description - Uint16 TRIWIRE:1; // 0 3-wire mode select bit - Uint16 STEINV:1; // 1 SPISTE inversion bit - Uint16 rsvd1:2; // 3:2 Reserved - Uint16 FREE:1; // 4 Free emulation mode - Uint16 SOFT:1; // 5 Soft emulation mode - Uint16 rsvd2:1; // 6 Reserved - Uint16 rsvd3:9; // 15:7 Reserved -}; - -union SPIPRI_REG { - Uint16 all; - struct SPIPRI_BITS bit; -}; - -struct SPI_REGS { - union SPICCR_REG SPICCR; // SPI Configuration Control Register - union SPICTL_REG SPICTL; // SPI Operation Control Register - union SPISTS_REG SPISTS; // SPI Status Register - Uint16 rsvd1; // Reserved - union SPIBRR_REG SPIBRR; // SPI Baud Rate Register - Uint16 rsvd2; // Reserved - Uint16 SPIRXEMU; // SPI Emulation Buffer Register - Uint16 SPIRXBUF; // SPI Serial Input Buffer Register - Uint16 SPITXBUF; // SPI Serial Output Buffer Register - Uint16 SPIDAT; // SPI Serial Data Register - union SPIFFTX_REG SPIFFTX; // SPI FIFO Transmit Register - union SPIFFRX_REG SPIFFRX; // SPI FIFO Receive Register - union SPIFFCT_REG SPIFFCT; // SPI FIFO Control Register - Uint16 rsvd3[2]; // Reserved - union SPIPRI_REG SPIPRI; // SPI Priority Control Register -}; - -//--------------------------------------------------------------------------- -// SPI External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct SPI_REGS SpiaRegs; -extern volatile struct SPI_REGS SpibRegs; -extern volatile struct SPI_REGS SpicRegs; -#endif -#ifdef CPU2 -extern volatile struct SPI_REGS SpiaRegs; -extern volatile struct SPI_REGS SpibRegs; -extern volatile struct SPI_REGS SpicRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sysctrl.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sysctrl.h deleted file mode 100644 index dd438aed5f..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_sysctrl.h +++ /dev/null @@ -1,1964 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_sysctrl.h -// -// TITLE: SYSCTRL Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_SYSCTRL_H__ -#define __F2837xD_SYSCTRL_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// SYSCTRL Individual Register Bit Definitions: - -struct DEVCFGLOCK1_BITS { // bits description - Uint16 CPUSEL0:1; // 0 Lock bit for CPUSEL0 register - Uint16 CPUSEL1:1; // 1 Lock bit for CPUSEL1 register - Uint16 CPUSEL2:1; // 2 Lock bit for CPUSEL2 register - Uint16 CPUSEL3:1; // 3 Lock bit for CPUSEL3 register - Uint16 CPUSEL4:1; // 4 Lock bit for CPUSEL4 register - Uint16 CPUSEL5:1; // 5 Lock bit for CPUSEL5 register - Uint16 CPUSEL6:1; // 6 Lock bit for CPUSEL6 register - Uint16 CPUSEL7:1; // 7 Lock bit for CPUSEL7 register - Uint16 CPUSEL8:1; // 8 Lock bit for CPUSEL8 register - Uint16 CPUSEL9:1; // 9 Lock bit for CPUSEL9 register - Uint16 CPUSEL10:1; // 10 Lock bit for CPUSEL10 register - Uint16 CPUSEL11:1; // 11 Lock bit for CPUSEL11 register - Uint16 CPUSEL12:1; // 12 Lock bit for CPUSEL12 register - Uint16 CPUSEL13:1; // 13 Lock bit for CPUSEL13 register - Uint16 CPUSEL14:1; // 14 Lock bit for CPUSEL14 register - Uint16 rsvd1:1; // 15 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DEVCFGLOCK1_REG { - Uint32 all; - struct DEVCFGLOCK1_BITS bit; -}; - -struct PARTIDL_BITS { // bits description - Uint16 rsvd1:3; // 2:0 Reserved - Uint16 rsvd2:2; // 4:3 Reserved - Uint16 rsvd3:1; // 5 Reserved - Uint16 QUAL:2; // 7:6 Qualification Status - Uint16 PIN_COUNT:3; // 10:8 Device Pin Count - Uint16 rsvd4:1; // 11 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 INSTASPIN:2; // 14:13 Motorware feature set - Uint16 rsvd6:1; // 15 Reserved - Uint16 FLASH_SIZE:8; // 23:16 Flash size in KB - Uint16 rsvd7:4; // 27:24 Reserved - Uint16 PARTID_FORMAT_REVISION:4; // 31:28 Revision of the PARTID format -}; - -union PARTIDL_REG { - Uint32 all; - struct PARTIDL_BITS bit; -}; - -struct PARTIDH_BITS { // bits description - Uint16 rsvd1:8; // 7:0 Reserved - Uint16 FAMILY:8; // 15:8 Device family - Uint16 PARTNO:8; // 23:16 Device part number - Uint16 DEVICE_CLASS_ID:8; // 31:24 Device class ID -}; - -union PARTIDH_REG { - Uint32 all; - struct PARTIDH_BITS bit; -}; - -struct DC0_BITS { // bits description - Uint16 SINGLE_CORE:1; // 0 Single Core vs Dual Core - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DC0_REG { - Uint32 all; - struct DC0_BITS bit; -}; - -struct DC1_BITS { // bits description - Uint16 CPU1_FPU_TMU:1; // 0 CPU1's FPU1+TMU1 - Uint16 CPU2_FPU_TMU:1; // 1 CPU2's FPU2+TMU2 - Uint16 CPU1_VCU:1; // 2 CPU1's VCU - Uint16 CPU2_VCU:1; // 3 CPU2's VCU - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 CPU1_CLA1:1; // 6 CPU1.CLA1 - Uint16 rsvd2:1; // 7 Reserved - Uint16 CPU2_CLA1:1; // 8 CPU2.CLA1 - Uint16 rsvd3:1; // 9 Reserved - Uint16 rsvd4:6; // 15:10 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union DC1_REG { - Uint32 all; - struct DC1_BITS bit; -}; - -struct DC2_BITS { // bits description - Uint16 EMIF1:1; // 0 EMIF1 - Uint16 EMIF2:1; // 1 EMIF2 - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DC2_REG { - Uint32 all; - struct DC2_BITS bit; -}; - -struct DC3_BITS { // bits description - Uint16 EPWM1:1; // 0 EPWM1 - Uint16 EPWM2:1; // 1 EPWM2 - Uint16 EPWM3:1; // 2 EPWM3 - Uint16 EPWM4:1; // 3 EPWM4 - Uint16 EPWM5:1; // 4 EPWM5 - Uint16 EPWM6:1; // 5 EPWM6 - Uint16 EPWM7:1; // 6 EPWM7 - Uint16 EPWM8:1; // 7 EPWM8 - Uint16 EPWM9:1; // 8 EPWM9 - Uint16 EPWM10:1; // 9 EPWM10 - Uint16 EPWM11:1; // 10 EPWM11 - Uint16 EPWM12:1; // 11 EPWM12 - Uint16 rsvd1:1; // 12 Reserved - Uint16 rsvd2:1; // 13 Reserved - Uint16 rsvd3:1; // 14 Reserved - Uint16 rsvd4:1; // 15 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union DC3_REG { - Uint32 all; - struct DC3_BITS bit; -}; - -struct DC4_BITS { // bits description - Uint16 ECAP1:1; // 0 ECAP1 - Uint16 ECAP2:1; // 1 ECAP2 - Uint16 ECAP3:1; // 2 ECAP3 - Uint16 ECAP4:1; // 3 ECAP4 - Uint16 ECAP5:1; // 4 ECAP5 - Uint16 ECAP6:1; // 5 ECAP6 - Uint16 rsvd1:1; // 6 Reserved - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:8; // 15:8 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DC4_REG { - Uint32 all; - struct DC4_BITS bit; -}; - -struct DC5_BITS { // bits description - Uint16 EQEP1:1; // 0 EQEP1 - Uint16 EQEP2:1; // 1 EQEP2 - Uint16 EQEP3:1; // 2 EQEP3 - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union DC5_REG { - Uint32 all; - struct DC5_BITS bit; -}; - -struct DC6_BITS { // bits description - Uint16 CLB1:1; // 0 CLB1 - Uint16 CLB2:1; // 1 CLB2 - Uint16 CLB3:1; // 2 CLB3 - Uint16 CLB4:1; // 3 CLB4 - Uint16 rsvd1:1; // 4 Reserved - Uint16 rsvd2:1; // 5 Reserved - Uint16 rsvd3:1; // 6 Reserved - Uint16 rsvd4:1; // 7 Reserved - Uint16 rsvd5:8; // 15:8 Reserved - Uint16 rsvd6:16; // 31:16 Reserved -}; - -union DC6_REG { - Uint32 all; - struct DC6_BITS bit; -}; - -struct DC7_BITS { // bits description - Uint16 SD1:1; // 0 SD1 - Uint16 SD2:1; // 1 SD2 - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:1; // 5 Reserved - Uint16 rsvd5:1; // 6 Reserved - Uint16 rsvd6:1; // 7 Reserved - Uint16 rsvd7:8; // 15:8 Reserved - Uint16 rsvd8:16; // 31:16 Reserved -}; - -union DC7_REG { - Uint32 all; - struct DC7_BITS bit; -}; - -struct DC8_BITS { // bits description - Uint16 SCI_A:1; // 0 SCI_A - Uint16 SCI_B:1; // 1 SCI_B - Uint16 SCI_C:1; // 2 SCI_C - Uint16 SCI_D:1; // 3 SCI_D - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DC8_REG { - Uint32 all; - struct DC8_BITS bit; -}; - -struct DC9_BITS { // bits description - Uint16 SPI_A:1; // 0 SPI_A - Uint16 SPI_B:1; // 1 SPI_B - Uint16 SPI_C:1; // 2 SPI_C - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:1; // 16 Reserved - Uint16 rsvd4:1; // 17 Reserved - Uint16 rsvd5:14; // 31:18 Reserved -}; - -union DC9_REG { - Uint32 all; - struct DC9_BITS bit; -}; - -struct DC10_BITS { // bits description - Uint16 I2C_A:1; // 0 I2C_A - Uint16 I2C_B:1; // 1 I2C_B - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:1; // 16 Reserved - Uint16 rsvd3:1; // 17 Reserved - Uint16 rsvd4:14; // 31:18 Reserved -}; - -union DC10_REG { - Uint32 all; - struct DC10_BITS bit; -}; - -struct DC11_BITS { // bits description - Uint16 CAN_A:1; // 0 CAN_A - Uint16 CAN_B:1; // 1 CAN_B - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union DC11_REG { - Uint32 all; - struct DC11_BITS bit; -}; - -struct DC12_BITS { // bits description - Uint16 McBSP_A:1; // 0 McBSP_A - Uint16 McBSP_B:1; // 1 McBSP_B - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 USB_A:2; // 17:16 Decides the capability of the USB_A Module - Uint16 rsvd2:2; // 19:18 Reserved - Uint16 rsvd3:12; // 31:20 Reserved -}; - -union DC12_REG { - Uint32 all; - struct DC12_BITS bit; -}; - -struct DC13_BITS { // bits description - Uint16 uPP_A:1; // 0 uPP_A - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union DC13_REG { - Uint32 all; - struct DC13_BITS bit; -}; - -struct DC14_BITS { // bits description - Uint16 ADC_A:1; // 0 ADC_A - Uint16 ADC_B:1; // 1 ADC_B - Uint16 ADC_C:1; // 2 ADC_C - Uint16 ADC_D:1; // 3 ADC_D - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DC14_REG { - Uint32 all; - struct DC14_BITS bit; -}; - -struct DC15_BITS { // bits description - Uint16 CMPSS1:1; // 0 CMPSS1 - Uint16 CMPSS2:1; // 1 CMPSS2 - Uint16 CMPSS3:1; // 2 CMPSS3 - Uint16 CMPSS4:1; // 3 CMPSS4 - Uint16 CMPSS5:1; // 4 CMPSS5 - Uint16 CMPSS6:1; // 5 CMPSS6 - Uint16 CMPSS7:1; // 6 CMPSS7 - Uint16 CMPSS8:1; // 7 CMPSS8 - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DC15_REG { - Uint32 all; - struct DC15_BITS bit; -}; - -struct DC17_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:12; // 15:4 Reserved - Uint16 DAC_A:1; // 16 Buffered-DAC_A - Uint16 DAC_B:1; // 17 Buffered-DAC_B - Uint16 DAC_C:1; // 18 Buffered-DAC_C - Uint16 rsvd6:1; // 19 Reserved - Uint16 rsvd7:12; // 31:20 Reserved -}; - -union DC17_REG { - Uint32 all; - struct DC17_BITS bit; -}; - -struct DC18_BITS { // bits description - Uint16 LS0_1:1; // 0 LS0_1 - Uint16 LS1_1:1; // 1 LS1_1 - Uint16 LS2_1:1; // 2 LS2_1 - Uint16 LS3_1:1; // 3 LS3_1 - Uint16 LS4_1:1; // 4 LS4_1 - Uint16 LS5_1:1; // 5 LS5_1 - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DC18_REG { - Uint32 all; - struct DC18_BITS bit; -}; - -struct DC19_BITS { // bits description - Uint16 LS0_2:1; // 0 LS0_2 - Uint16 LS1_2:1; // 1 LS1_2 - Uint16 LS2_2:1; // 2 LS2_2 - Uint16 LS3_2:1; // 3 LS3_2 - Uint16 LS4_2:1; // 4 LS4_2 - Uint16 LS5_2:1; // 5 LS5_2 - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DC19_REG { - Uint32 all; - struct DC19_BITS bit; -}; - -struct DC20_BITS { // bits description - Uint16 GS0:1; // 0 GS0 - Uint16 GS1:1; // 1 GS1 - Uint16 GS2:1; // 2 GS2 - Uint16 GS3:1; // 3 GS3 - Uint16 GS4:1; // 4 GS4 - Uint16 GS5:1; // 5 GS5 - Uint16 GS6:1; // 6 GS6 - Uint16 GS7:1; // 7 GS7 - Uint16 GS8:1; // 8 GS8 - Uint16 GS9:1; // 9 GS9 - Uint16 GS10:1; // 10 GS10 - Uint16 GS11:1; // 11 GS11 - Uint16 GS12:1; // 12 GS12 - Uint16 GS13:1; // 13 GS13 - Uint16 GS14:1; // 14 GS14 - Uint16 GS15:1; // 15 GS15 - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union DC20_REG { - Uint32 all; - struct DC20_BITS bit; -}; - -struct PERCNF1_BITS { // bits description - Uint16 ADC_A_MODE:1; // 0 ADC_A mode setting bit - Uint16 ADC_B_MODE:1; // 1 ADC_B mode setting bit - Uint16 ADC_C_MODE:1; // 2 ADC_C mode setting bit - Uint16 ADC_D_MODE:1; // 3 ADC_D mode setting bit - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 USB_A_PHY:1; // 16 USB_A_PHY - Uint16 rsvd2:1; // 17 Reserved - Uint16 rsvd3:14; // 31:18 Reserved -}; - -union PERCNF1_REG { - Uint32 all; - struct PERCNF1_BITS bit; -}; - -struct FUSEERR_BITS { // bits description - Uint16 ALERR:5; // 4:0 Efuse Autoload Error Status - Uint16 ERR:1; // 5 Efuse Self Test Error Status - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union FUSEERR_REG { - Uint32 all; - struct FUSEERR_BITS bit; -}; - -struct SOFTPRES0_BITS { // bits description - Uint16 CPU1_CLA1:1; // 0 CPU1_CLA1 software reset bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 CPU2_CLA1:1; // 2 CPU2_CLA1 software reset bit - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union SOFTPRES0_REG { - Uint32 all; - struct SOFTPRES0_BITS bit; -}; - -struct SOFTPRES1_BITS { // bits description - Uint16 EMIF1:1; // 0 EMIF1 software reset bit - Uint16 EMIF2:1; // 1 EMIF2 software reset bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SOFTPRES1_REG { - Uint32 all; - struct SOFTPRES1_BITS bit; -}; - -struct SOFTPRES2_BITS { // bits description - Uint16 EPWM1:1; // 0 EPWM1 software reset bit - Uint16 EPWM2:1; // 1 EPWM2 software reset bit - Uint16 EPWM3:1; // 2 EPWM3 software reset bit - Uint16 EPWM4:1; // 3 EPWM4 software reset bit - Uint16 EPWM5:1; // 4 EPWM5 software reset bit - Uint16 EPWM6:1; // 5 EPWM6 software reset bit - Uint16 EPWM7:1; // 6 EPWM7 software reset bit - Uint16 EPWM8:1; // 7 EPWM8 software reset bit - Uint16 EPWM9:1; // 8 EPWM9 software reset bit - Uint16 EPWM10:1; // 9 EPWM10 software reset bit - Uint16 EPWM11:1; // 10 EPWM11 software reset bit - Uint16 EPWM12:1; // 11 EPWM12 software reset bit - Uint16 rsvd1:1; // 12 Reserved - Uint16 rsvd2:1; // 13 Reserved - Uint16 rsvd3:1; // 14 Reserved - Uint16 rsvd4:1; // 15 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union SOFTPRES2_REG { - Uint32 all; - struct SOFTPRES2_BITS bit; -}; - -struct SOFTPRES3_BITS { // bits description - Uint16 ECAP1:1; // 0 ECAP1 software reset bit - Uint16 ECAP2:1; // 1 ECAP2 software reset bit - Uint16 ECAP3:1; // 2 ECAP3 software reset bit - Uint16 ECAP4:1; // 3 ECAP4 software reset bit - Uint16 ECAP5:1; // 4 ECAP5 software reset bit - Uint16 ECAP6:1; // 5 ECAP6 software reset bit - Uint16 rsvd1:1; // 6 Reserved - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:8; // 15:8 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union SOFTPRES3_REG { - Uint32 all; - struct SOFTPRES3_BITS bit; -}; - -struct SOFTPRES4_BITS { // bits description - Uint16 EQEP1:1; // 0 EQEP1 software reset bit - Uint16 EQEP2:1; // 1 EQEP2 software reset bit - Uint16 EQEP3:1; // 2 EQEP3 software reset bit - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SOFTPRES4_REG { - Uint32 all; - struct SOFTPRES4_BITS bit; -}; - -struct SOFTPRES6_BITS { // bits description - Uint16 SD1:1; // 0 SD1 software reset bit - Uint16 SD2:1; // 1 SD2 software reset bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:1; // 5 Reserved - Uint16 rsvd5:1; // 6 Reserved - Uint16 rsvd6:1; // 7 Reserved - Uint16 rsvd7:8; // 15:8 Reserved - Uint16 rsvd8:16; // 31:16 Reserved -}; - -union SOFTPRES6_REG { - Uint32 all; - struct SOFTPRES6_BITS bit; -}; - -struct SOFTPRES7_BITS { // bits description - Uint16 SCI_A:1; // 0 SCI_A software reset bit - Uint16 SCI_B:1; // 1 SCI_B software reset bit - Uint16 SCI_C:1; // 2 SCI_C software reset bit - Uint16 SCI_D:1; // 3 SCI_D software reset bit - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SOFTPRES7_REG { - Uint32 all; - struct SOFTPRES7_BITS bit; -}; - -struct SOFTPRES8_BITS { // bits description - Uint16 SPI_A:1; // 0 SPI_A software reset bit - Uint16 SPI_B:1; // 1 SPI_B software reset bit - Uint16 SPI_C:1; // 2 SPI_C software reset bit - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:1; // 16 Reserved - Uint16 rsvd4:1; // 17 Reserved - Uint16 rsvd5:14; // 31:18 Reserved -}; - -union SOFTPRES8_REG { - Uint32 all; - struct SOFTPRES8_BITS bit; -}; - -struct SOFTPRES9_BITS { // bits description - Uint16 I2C_A:1; // 0 I2C_A software reset bit - Uint16 I2C_B:1; // 1 I2C_B software reset bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:1; // 16 Reserved - Uint16 rsvd3:1; // 17 Reserved - Uint16 rsvd4:14; // 31:18 Reserved -}; - -union SOFTPRES9_REG { - Uint32 all; - struct SOFTPRES9_BITS bit; -}; - -struct SOFTPRES11_BITS { // bits description - Uint16 McBSP_A:1; // 0 McBSP_A software reset bit - Uint16 McBSP_B:1; // 1 McBSP_B software reset bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 USB_A:1; // 16 USB_A software reset bit - Uint16 rsvd2:1; // 17 Reserved - Uint16 rsvd3:14; // 31:18 Reserved -}; - -union SOFTPRES11_REG { - Uint32 all; - struct SOFTPRES11_BITS bit; -}; - -struct SOFTPRES13_BITS { // bits description - Uint16 ADC_A:1; // 0 ADC_A software reset bit - Uint16 ADC_B:1; // 1 ADC_B software reset bit - Uint16 ADC_C:1; // 2 ADC_C software reset bit - Uint16 ADC_D:1; // 3 ADC_D software reset bit - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SOFTPRES13_REG { - Uint32 all; - struct SOFTPRES13_BITS bit; -}; - -struct SOFTPRES14_BITS { // bits description - Uint16 CMPSS1:1; // 0 CMPSS1 software reset bit - Uint16 CMPSS2:1; // 1 CMPSS2 software reset bit - Uint16 CMPSS3:1; // 2 CMPSS3 software reset bit - Uint16 CMPSS4:1; // 3 CMPSS4 software reset bit - Uint16 CMPSS5:1; // 4 CMPSS5 software reset bit - Uint16 CMPSS6:1; // 5 CMPSS6 software reset bit - Uint16 CMPSS7:1; // 6 CMPSS7 software reset bit - Uint16 CMPSS8:1; // 7 CMPSS8 software reset bit - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SOFTPRES14_REG { - Uint32 all; - struct SOFTPRES14_BITS bit; -}; - -struct SOFTPRES16_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:12; // 15:4 Reserved - Uint16 DAC_A:1; // 16 Buffered_DAC_A software reset bit - Uint16 DAC_B:1; // 17 Buffered_DAC_B software reset bit - Uint16 DAC_C:1; // 18 Buffered_DAC_C software reset bit - Uint16 rsvd6:1; // 19 Reserved - Uint16 rsvd7:12; // 31:20 Reserved -}; - -union SOFTPRES16_REG { - Uint32 all; - struct SOFTPRES16_BITS bit; -}; - -struct CPUSEL0_BITS { // bits description - Uint16 EPWM1:1; // 0 EPWM1 CPU select bit - Uint16 EPWM2:1; // 1 EPWM2 CPU select bit - Uint16 EPWM3:1; // 2 EPWM3 CPU select bit - Uint16 EPWM4:1; // 3 EPWM4 CPU select bit - Uint16 EPWM5:1; // 4 EPWM5 CPU select bit - Uint16 EPWM6:1; // 5 EPWM6 CPU select bit - Uint16 EPWM7:1; // 6 EPWM7 CPU select bit - Uint16 EPWM8:1; // 7 EPWM8 CPU select bit - Uint16 EPWM9:1; // 8 EPWM9 CPU select bit - Uint16 EPWM10:1; // 9 EPWM10 CPU select bit - Uint16 EPWM11:1; // 10 EPWM11 CPU select bit - Uint16 EPWM12:1; // 11 EPWM12 CPU select bit - Uint16 rsvd1:1; // 12 Reserved - Uint16 rsvd2:1; // 13 Reserved - Uint16 rsvd3:1; // 14 Reserved - Uint16 rsvd4:1; // 15 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union CPUSEL0_REG { - Uint32 all; - struct CPUSEL0_BITS bit; -}; - -struct CPUSEL1_BITS { // bits description - Uint16 ECAP1:1; // 0 ECAP1 CPU select bit - Uint16 ECAP2:1; // 1 ECAP2 CPU select bit - Uint16 ECAP3:1; // 2 ECAP3 CPU select bit - Uint16 ECAP4:1; // 3 ECAP4 CPU select bit - Uint16 ECAP5:1; // 4 ECAP5 CPU select bit - Uint16 ECAP6:1; // 5 ECAP6 CPU select bit - Uint16 rsvd1:1; // 6 Reserved - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:8; // 15:8 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union CPUSEL1_REG { - Uint32 all; - struct CPUSEL1_BITS bit; -}; - -struct CPUSEL2_BITS { // bits description - Uint16 EQEP1:1; // 0 EQEP1 CPU select bit - Uint16 EQEP2:1; // 1 EQEP2 CPU select bit - Uint16 EQEP3:1; // 2 EQEP3 CPU select bit - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CPUSEL2_REG { - Uint32 all; - struct CPUSEL2_BITS bit; -}; - -struct CPUSEL4_BITS { // bits description - Uint16 SD1:1; // 0 SD1 CPU select bit - Uint16 SD2:1; // 1 SD2 CPU select bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:1; // 5 Reserved - Uint16 rsvd5:1; // 6 Reserved - Uint16 rsvd6:1; // 7 Reserved - Uint16 rsvd7:8; // 15:8 Reserved - Uint16 rsvd8:16; // 31:16 Reserved -}; - -union CPUSEL4_REG { - Uint32 all; - struct CPUSEL4_BITS bit; -}; - -struct CPUSEL5_BITS { // bits description - Uint16 SCI_A:1; // 0 SCI_A CPU select bit - Uint16 SCI_B:1; // 1 SCI_B CPU select bit - Uint16 SCI_C:1; // 2 SCI_C CPU select bit - Uint16 SCI_D:1; // 3 SCI_D CPU select bit - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CPUSEL5_REG { - Uint32 all; - struct CPUSEL5_BITS bit; -}; - -struct CPUSEL6_BITS { // bits description - Uint16 SPI_A:1; // 0 SPI_A CPU select bit - Uint16 SPI_B:1; // 1 SPI_B CPU select bit - Uint16 SPI_C:1; // 2 SPI_C CPU select bit - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:1; // 16 Reserved - Uint16 rsvd4:1; // 17 Reserved - Uint16 rsvd5:14; // 31:18 Reserved -}; - -union CPUSEL6_REG { - Uint32 all; - struct CPUSEL6_BITS bit; -}; - -struct CPUSEL7_BITS { // bits description - Uint16 I2C_A:1; // 0 I2C_A CPU select bit - Uint16 I2C_B:1; // 1 I2C_B CPU select bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:1; // 16 Reserved - Uint16 rsvd3:1; // 17 Reserved - Uint16 rsvd4:14; // 31:18 Reserved -}; - -union CPUSEL7_REG { - Uint32 all; - struct CPUSEL7_BITS bit; -}; - -struct CPUSEL8_BITS { // bits description - Uint16 CAN_A:1; // 0 CAN_A CPU select bit - Uint16 CAN_B:1; // 1 CAN_B CPU select bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union CPUSEL8_REG { - Uint32 all; - struct CPUSEL8_BITS bit; -}; - -struct CPUSEL9_BITS { // bits description - Uint16 McBSP_A:1; // 0 McBSP_A CPU select bit - Uint16 McBSP_B:1; // 1 McBSP_B CPU select bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CPUSEL9_REG { - Uint32 all; - struct CPUSEL9_BITS bit; -}; - -struct CPUSEL11_BITS { // bits description - Uint16 ADC_A:1; // 0 ADC_A CPU select bit - Uint16 ADC_B:1; // 1 ADC_B CPU select bit - Uint16 ADC_C:1; // 2 ADC_C CPU select bit - Uint16 ADC_D:1; // 3 ADC_D CPU select bit - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CPUSEL11_REG { - Uint32 all; - struct CPUSEL11_BITS bit; -}; - -struct CPUSEL12_BITS { // bits description - Uint16 CMPSS1:1; // 0 CMPSS1 CPU select bit - Uint16 CMPSS2:1; // 1 CMPSS2 CPU select bit - Uint16 CMPSS3:1; // 2 CMPSS3 CPU select bit - Uint16 CMPSS4:1; // 3 CMPSS4 CPU select bit - Uint16 CMPSS5:1; // 4 CMPSS5 CPU select bit - Uint16 CMPSS6:1; // 5 CMPSS6 CPU select bit - Uint16 CMPSS7:1; // 6 CMPSS7 CPU select bit - Uint16 CMPSS8:1; // 7 CMPSS8 CPU select bit - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CPUSEL12_REG { - Uint32 all; - struct CPUSEL12_BITS bit; -}; - -struct CPUSEL14_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:12; // 15:4 Reserved - Uint16 DAC_A:1; // 16 Buffered_DAC_A CPU select bit - Uint16 DAC_B:1; // 17 Buffered_DAC_B CPU select bit - Uint16 DAC_C:1; // 18 Buffered_DAC_C CPU select bit - Uint16 rsvd6:1; // 19 Reserved - Uint16 rsvd7:12; // 31:20 Reserved -}; - -union CPUSEL14_REG { - Uint32 all; - struct CPUSEL14_BITS bit; -}; - -struct CPU2RESCTL_BITS { // bits description - Uint16 RESET:1; // 0 CPU2 Reset Control bit - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register -}; - -union CPU2RESCTL_REG { - Uint32 all; - struct CPU2RESCTL_BITS bit; -}; - -struct RSTSTAT_BITS { // bits description - Uint16 CPU2RES:1; // 0 CPU2 Reset Status bit - Uint16 CPU2NMIWDRST:1; // 1 Indicates whether a CPU2.NMIWD reset was issued to CPU2 - Uint16 CPU2HWBISTRST0:1; // 2 Indicates whether a HWBIST reset was issued to CPU2 - Uint16 CPU2HWBISTRST1:1; // 3 Indicates whether a HWBIST reset was issued to CPU2 - Uint16 rsvd1:12; // 15:4 Reserved -}; - -union RSTSTAT_REG { - Uint16 all; - struct RSTSTAT_BITS bit; -}; - -struct LPMSTAT_BITS { // bits description - Uint16 CPU2LPMSTAT:2; // 1:0 CPU2 LPM Status - Uint16 rsvd1:14; // 15:2 Reserved -}; - -union LPMSTAT_REG { - Uint16 all; - struct LPMSTAT_BITS bit; -}; - -struct SYSDBGCTL_BITS { // bits description - Uint16 BIT_0:1; // 0 Used in PLL startup. Only reset by POR. - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYSDBGCTL_REG { - Uint32 all; - struct SYSDBGCTL_BITS bit; -}; - -struct DEV_CFG_REGS { - union DEVCFGLOCK1_REG DEVCFGLOCK1; // Lock bit for CPUSELx registers - Uint16 rsvd1[6]; // Reserved - union PARTIDL_REG PARTIDL; // Lower 32-bit of Device PART Identification Number - union PARTIDH_REG PARTIDH; // Upper 32-bit of Device PART Identification Number - Uint32 REVID; // Device Revision Number - Uint16 rsvd2[2]; // Reserved - union DC0_REG DC0; // Device Capability: Device Information - union DC1_REG DC1; // Device Capability: Processing Block Customization - union DC2_REG DC2; // Device Capability: EMIF Customization - union DC3_REG DC3; // Device Capability: Peripheral Customization - union DC4_REG DC4; // Device Capability: Peripheral Customization - union DC5_REG DC5; // Device Capability: Peripheral Customization - union DC6_REG DC6; // Device Capability: Peripheral Customization - union DC7_REG DC7; // Device Capability: Peripheral Customization - union DC8_REG DC8; // Device Capability: Peripheral Customization - union DC9_REG DC9; // Device Capability: Peripheral Customization - union DC10_REG DC10; // Device Capability: Peripheral Customization - union DC11_REG DC11; // Device Capability: Peripheral Customization - union DC12_REG DC12; // Device Capability: Peripheral Customization - union DC13_REG DC13; // Device Capability: Peripheral Customization - union DC14_REG DC14; // Device Capability: Analog Modules Customization - union DC15_REG DC15; // Device Capability: Analog Modules Customization - Uint16 rsvd3[2]; // Reserved - union DC17_REG DC17; // Device Capability: Analog Modules Customization - union DC18_REG DC18; // Device Capability: CPU1 Lx SRAM Customization - union DC19_REG DC19; // Device Capability: CPU2 Lx SRAM Customization - union DC20_REG DC20; // Device Capability: GSx SRAM Customization - Uint16 rsvd4[38]; // Reserved - union PERCNF1_REG PERCNF1; // Peripheral Configuration register - Uint16 rsvd5[18]; // Reserved - union FUSEERR_REG FUSEERR; // e-Fuse error Status register - Uint16 rsvd6[12]; // Reserved - union SOFTPRES0_REG SOFTPRES0; // Processing Block Software Reset register - union SOFTPRES1_REG SOFTPRES1; // EMIF Software Reset register - union SOFTPRES2_REG SOFTPRES2; // Peripheral Software Reset register - union SOFTPRES3_REG SOFTPRES3; // Peripheral Software Reset register - union SOFTPRES4_REG SOFTPRES4; // Peripheral Software Reset register - Uint16 rsvd7[2]; // Reserved - union SOFTPRES6_REG SOFTPRES6; // Peripheral Software Reset register - union SOFTPRES7_REG SOFTPRES7; // Peripheral Software Reset register - union SOFTPRES8_REG SOFTPRES8; // Peripheral Software Reset register - union SOFTPRES9_REG SOFTPRES9; // Peripheral Software Reset register - Uint16 rsvd8[2]; // Reserved - union SOFTPRES11_REG SOFTPRES11; // Peripheral Software Reset register - Uint16 rsvd9[2]; // Reserved - union SOFTPRES13_REG SOFTPRES13; // Peripheral Software Reset register - union SOFTPRES14_REG SOFTPRES14; // Peripheral Software Reset register - Uint16 rsvd10[2]; // Reserved - union SOFTPRES16_REG SOFTPRES16; // Peripheral Software Reset register - Uint16 rsvd11[50]; // Reserved - union CPUSEL0_REG CPUSEL0; // CPU Select register for common peripherals - union CPUSEL1_REG CPUSEL1; // CPU Select register for common peripherals - union CPUSEL2_REG CPUSEL2; // CPU Select register for common peripherals - Uint16 rsvd12[2]; // Reserved - union CPUSEL4_REG CPUSEL4; // CPU Select register for common peripherals - union CPUSEL5_REG CPUSEL5; // CPU Select register for common peripherals - union CPUSEL6_REG CPUSEL6; // CPU Select register for common peripherals - union CPUSEL7_REG CPUSEL7; // CPU Select register for common peripherals - union CPUSEL8_REG CPUSEL8; // CPU Select register for common peripherals - union CPUSEL9_REG CPUSEL9; // CPU Select register for common peripherals - Uint16 rsvd13[2]; // Reserved - union CPUSEL11_REG CPUSEL11; // CPU Select register for common peripherals - union CPUSEL12_REG CPUSEL12; // CPU Select register for common peripherals - Uint16 rsvd14[2]; // Reserved - union CPUSEL14_REG CPUSEL14; // CPU Select register for common peripherals - Uint16 rsvd15[46]; // Reserved - union CPU2RESCTL_REG CPU2RESCTL; // CPU2 Reset Control Register - union RSTSTAT_REG RSTSTAT; // Reset Status register for secondary C28x CPUs - union LPMSTAT_REG LPMSTAT; // LPM Status Register for secondary C28x CPUs - Uint16 rsvd16[6]; // Reserved - union SYSDBGCTL_REG SYSDBGCTL; // System Debug Control register -}; - -struct CLKSEM_BITS { // bits description - Uint16 SEM:2; // 1:0 Semaphore for CLKCFG Ownership by CPU1 or CPU2 - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register -}; - -union CLKSEM_REG { - Uint32 all; - struct CLKSEM_BITS bit; -}; - -struct CLKCFGLOCK1_BITS { // bits description - Uint16 CLKSRCCTL1:1; // 0 Lock bit for CLKSRCCTL1 register - Uint16 CLKSRCCTL2:1; // 1 Lock bit for CLKSRCCTL2 register - Uint16 CLKSRCCTL3:1; // 2 Lock bit for CLKSRCCTL3 register - Uint16 SYSPLLCTL1:1; // 3 Lock bit for SYSPLLCTL1 register - Uint16 SYSPLLCTL2:1; // 4 Lock bit for SYSPLLCTL2 register - Uint16 SYSPLLCTL3:1; // 5 Lock bit for SYSPLLCTL3 register - Uint16 SYSPLLMULT:1; // 6 Lock bit for SYSPLLMULT register - Uint16 AUXPLLCTL1:1; // 7 Lock bit for AUXPLLCTL1 register - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:1; // 9 Reserved - Uint16 AUXPLLMULT:1; // 10 Lock bit for AUXPLLMULT register - Uint16 SYSCLKDIVSEL:1; // 11 Lock bit for SYSCLKDIVSEL register - Uint16 AUXCLKDIVSEL:1; // 12 Lock bit for AUXCLKDIVSEL register - Uint16 PERCLKDIVSEL:1; // 13 Lock bit for PERCLKDIVSEL register - Uint16 rsvd3:1; // 14 Reserved - Uint16 LOSPCP:1; // 15 Lock bit for LOSPCP register - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union CLKCFGLOCK1_REG { - Uint32 all; - struct CLKCFGLOCK1_BITS bit; -}; - -struct CLKSRCCTL1_BITS { // bits description - Uint16 OSCCLKSRCSEL:2; // 1:0 OSCCLK Source Select Bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 INTOSC2OFF:1; // 3 Internal Oscillator 2 Off Bit - Uint16 XTALOFF:1; // 4 Crystal (External) Oscillator Off Bit - Uint16 WDHALTI:1; // 5 Watchdog HALT Mode Ignore Bit - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CLKSRCCTL1_REG { - Uint32 all; - struct CLKSRCCTL1_BITS bit; -}; - -struct CLKSRCCTL2_BITS { // bits description - Uint16 AUXOSCCLKSRCSEL:2; // 1:0 AUXOSCCLK Source Select Bit - Uint16 CANABCLKSEL:2; // 3:2 CANA Bit Clock Source Select Bit - Uint16 CANBBCLKSEL:2; // 5:4 CANB Bit Clock Source Select Bit - Uint16 rsvd1:2; // 7:6 Reserved - Uint16 rsvd2:2; // 9:8 Reserved - Uint16 rsvd3:6; // 15:10 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union CLKSRCCTL2_REG { - Uint32 all; - struct CLKSRCCTL2_BITS bit; -}; - -struct CLKSRCCTL3_BITS { // bits description - Uint16 XCLKOUTSEL:3; // 2:0 XCLKOUT Source Select Bit - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CLKSRCCTL3_REG { - Uint32 all; - struct CLKSRCCTL3_BITS bit; -}; - -struct SYSPLLCTL1_BITS { // bits description - Uint16 PLLEN:1; // 0 SYSPLL enable/disable bit - Uint16 PLLCLKEN:1; // 1 SYSPLL bypassed or included in the PLLSYSCLK path - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYSPLLCTL1_REG { - Uint32 all; - struct SYSPLLCTL1_BITS bit; -}; - -struct SYSPLLMULT_BITS { // bits description - Uint16 IMULT:7; // 6:0 SYSPLL Integer Multiplier - Uint16 rsvd1:1; // 7 Reserved - Uint16 FMULT:2; // 9:8 SYSPLL Fractional Multiplier - Uint16 rsvd2:6; // 15:10 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union SYSPLLMULT_REG { - Uint32 all; - struct SYSPLLMULT_BITS bit; -}; - -struct SYSPLLSTS_BITS { // bits description - Uint16 LOCKS:1; // 0 SYSPLL Lock Status Bit - Uint16 SLIPS:1; // 1 SYSPLL Slip Status Bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYSPLLSTS_REG { - Uint32 all; - struct SYSPLLSTS_BITS bit; -}; - -struct AUXPLLCTL1_BITS { // bits description - Uint16 PLLEN:1; // 0 AUXPLL enable/disable bit - Uint16 PLLCLKEN:1; // 1 AUXPLL bypassed or included in the AUXPLLCLK path - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union AUXPLLCTL1_REG { - Uint32 all; - struct AUXPLLCTL1_BITS bit; -}; - -struct AUXPLLMULT_BITS { // bits description - Uint16 IMULT:7; // 6:0 AUXPLL Integer Multiplier - Uint16 rsvd1:1; // 7 Reserved - Uint16 FMULT:2; // 9:8 AUXPLL Fractional Multiplier - Uint16 rsvd2:6; // 15:10 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union AUXPLLMULT_REG { - Uint32 all; - struct AUXPLLMULT_BITS bit; -}; - -struct AUXPLLSTS_BITS { // bits description - Uint16 LOCKS:1; // 0 AUXPLL Lock Status Bit - Uint16 SLIPS:1; // 1 AUXPLL Slip Status Bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union AUXPLLSTS_REG { - Uint32 all; - struct AUXPLLSTS_BITS bit; -}; - -struct SYSCLKDIVSEL_BITS { // bits description - Uint16 PLLSYSCLKDIV:6; // 5:0 PLLSYSCLK Divide Select - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYSCLKDIVSEL_REG { - Uint32 all; - struct SYSCLKDIVSEL_BITS bit; -}; - -struct AUXCLKDIVSEL_BITS { // bits description - Uint16 AUXPLLDIV:2; // 1:0 AUXPLLCLK Divide Select - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union AUXCLKDIVSEL_REG { - Uint32 all; - struct AUXCLKDIVSEL_BITS bit; -}; - -struct PERCLKDIVSEL_BITS { // bits description - Uint16 EPWMCLKDIV:2; // 1:0 EPWM Clock Divide Select - Uint16 rsvd1:2; // 3:2 Reserved - Uint16 EMIF1CLKDIV:1; // 4 EMIF1 Clock Divide Select - Uint16 rsvd2:1; // 5 Reserved - Uint16 EMIF2CLKDIV:1; // 6 EMIF2 Clock Divide Select - Uint16 rsvd3:9; // 15:7 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union PERCLKDIVSEL_REG { - Uint32 all; - struct PERCLKDIVSEL_BITS bit; -}; - -struct XCLKOUTDIVSEL_BITS { // bits description - Uint16 XCLKOUTDIV:2; // 1:0 XCLKOUT Divide Select - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union XCLKOUTDIVSEL_REG { - Uint32 all; - struct XCLKOUTDIVSEL_BITS bit; -}; - -struct LOSPCP_BITS { // bits description - Uint16 LSPCLKDIV:3; // 2:0 LSPCLK Divide Select - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union LOSPCP_REG { - Uint32 all; - struct LOSPCP_BITS bit; -}; - -struct MCDCR_BITS { // bits description - Uint16 MCLKSTS:1; // 0 Missing Clock Status Bit - Uint16 MCLKCLR:1; // 1 Missing Clock Clear Bit - Uint16 MCLKOFF:1; // 2 Missing Clock Detect Off Bit - Uint16 OSCOFF:1; // 3 Oscillator Clock Off Bit - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union MCDCR_REG { - Uint32 all; - struct MCDCR_BITS bit; -}; - -struct X1CNT_BITS { // bits description - Uint16 X1CNT:10; // 9:0 X1 Counter - Uint16 rsvd1:6; // 15:10 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union X1CNT_REG { - Uint32 all; - struct X1CNT_BITS bit; -}; - -struct CLK_CFG_REGS { - union CLKSEM_REG CLKSEM; // Clock Control Semaphore Register - union CLKCFGLOCK1_REG CLKCFGLOCK1; // Lock bit for CLKCFG registers - Uint16 rsvd1[4]; // Reserved - union CLKSRCCTL1_REG CLKSRCCTL1; // Clock Source Control register-1 - union CLKSRCCTL2_REG CLKSRCCTL2; // Clock Source Control register-2 - union CLKSRCCTL3_REG CLKSRCCTL3; // Clock Source Control register-3 - union SYSPLLCTL1_REG SYSPLLCTL1; // SYSPLL Control register-1 - Uint16 rsvd2[4]; // Reserved - union SYSPLLMULT_REG SYSPLLMULT; // SYSPLL Multiplier register - union SYSPLLSTS_REG SYSPLLSTS; // SYSPLL Status register - union AUXPLLCTL1_REG AUXPLLCTL1; // AUXPLL Control register-1 - Uint16 rsvd3[4]; // Reserved - union AUXPLLMULT_REG AUXPLLMULT; // AUXPLL Multiplier register - union AUXPLLSTS_REG AUXPLLSTS; // AUXPLL Status register - union SYSCLKDIVSEL_REG SYSCLKDIVSEL; // System Clock Divider Select register - union AUXCLKDIVSEL_REG AUXCLKDIVSEL; // Auxillary Clock Divider Select register - union PERCLKDIVSEL_REG PERCLKDIVSEL; // Peripheral Clock Divider Selet register - union XCLKOUTDIVSEL_REG XCLKOUTDIVSEL; // XCLKOUT Divider Select register - Uint16 rsvd4[2]; // Reserved - union LOSPCP_REG LOSPCP; // Low Speed Clock Source Prescalar - union MCDCR_REG MCDCR; // Missing Clock Detect Control Register - union X1CNT_REG X1CNT; // 10-bit Counter on X1 Clock -}; - -struct CPUSYSLOCK1_BITS { // bits description - Uint16 HIBBOOTMODE:1; // 0 Lock bit for HIBBOOTMODE register - Uint16 IORESTOREADDR:1; // 1 Lock bit for IORESTOREADDR Register - Uint16 PIEVERRADDR:1; // 2 Lock bit for PIEVERRADDR Register - Uint16 PCLKCR0:1; // 3 Lock bit for PCLKCR0 Register - Uint16 PCLKCR1:1; // 4 Lock bit for PCLKCR1 Register - Uint16 PCLKCR2:1; // 5 Lock bit for PCLKCR2 Register - Uint16 PCLKCR3:1; // 6 Lock bit for PCLKCR3 Register - Uint16 PCLKCR4:1; // 7 Lock bit for PCLKCR4 Register - Uint16 PCLKCR5:1; // 8 Lock bit for PCLKCR5 Register - Uint16 PCLKCR6:1; // 9 Lock bit for PCLKCR6 Register - Uint16 PCLKCR7:1; // 10 Lock bit for PCLKCR7 Register - Uint16 PCLKCR8:1; // 11 Lock bit for PCLKCR8 Register - Uint16 PCLKCR9:1; // 12 Lock bit for PCLKCR9 Register - Uint16 PCLKCR10:1; // 13 Lock bit for PCLKCR10 Register - Uint16 PCLKCR11:1; // 14 Lock bit for PCLKCR11 Register - Uint16 PCLKCR12:1; // 15 Lock bit for PCLKCR12 Register - Uint16 PCLKCR13:1; // 16 Lock bit for PCLKCR13 Register - Uint16 PCLKCR14:1; // 17 Lock bit for PCLKCR14 Register - Uint16 PCLKCR15:1; // 18 Lock bit for PCLKCR15 Register - Uint16 PCLKCR16:1; // 19 Lock bit for PCLKCR16 Register - Uint16 SECMSEL:1; // 20 Lock bit for SECMSEL Register - Uint16 LPMCR:1; // 21 Lock bit for LPMCR Register - Uint16 GPIOLPMSEL0:1; // 22 Lock bit for GPIOLPMSEL0 Register - Uint16 GPIOLPMSEL1:1; // 23 Lock bit for GPIOLPMSEL1 Register - Uint16 rsvd1:8; // 31:24 Reserved -}; - -union CPUSYSLOCK1_REG { - Uint32 all; - struct CPUSYSLOCK1_BITS bit; -}; - -struct IORESTOREADDR_BITS { // bits description - Uint32 ADDR:22; // 21:0 restoreIO() routine address - Uint16 rsvd1:10; // 31:22 Reserved -}; - -union IORESTOREADDR_REG { - Uint32 all; - struct IORESTOREADDR_BITS bit; -}; - -struct PIEVERRADDR_BITS { // bits description - Uint32 ADDR:22; // 21:0 PIE Vector Fetch Error Handler Routine Address - Uint16 rsvd1:10; // 31:22 Reserved -}; - -union PIEVERRADDR_REG { - Uint32 all; - struct PIEVERRADDR_BITS bit; -}; - -struct PCLKCR0_BITS { // bits description - Uint16 CLA1:1; // 0 CLA1 Clock Enable Bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 DMA:1; // 2 DMA Clock Enable bit - Uint16 CPUTIMER0:1; // 3 CPUTIMER0 Clock Enable bit - Uint16 CPUTIMER1:1; // 4 CPUTIMER1 Clock Enable bit - Uint16 CPUTIMER2:1; // 5 CPUTIMER2 Clock Enable bit - Uint16 rsvd2:10; // 15:6 Reserved - Uint16 HRPWM:1; // 16 HRPWM Clock Enable Bit - Uint16 rsvd3:1; // 17 Reserved - Uint16 TBCLKSYNC:1; // 18 EPWM Time Base Clock sync - Uint16 GTBCLKSYNC:1; // 19 EPWM Time Base Clock Global sync - Uint16 rsvd4:12; // 31:20 Reserved -}; - -union PCLKCR0_REG { - Uint32 all; - struct PCLKCR0_BITS bit; -}; - -struct PCLKCR1_BITS { // bits description - Uint16 EMIF1:1; // 0 EMIF1 Clock Enable bit - Uint16 EMIF2:1; // 1 EMIF2 Clock Enable bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PCLKCR1_REG { - Uint32 all; - struct PCLKCR1_BITS bit; -}; - -struct PCLKCR2_BITS { // bits description - Uint16 EPWM1:1; // 0 EPWM1 Clock Enable bit - Uint16 EPWM2:1; // 1 EPWM2 Clock Enable bit - Uint16 EPWM3:1; // 2 EPWM3 Clock Enable bit - Uint16 EPWM4:1; // 3 EPWM4 Clock Enable bit - Uint16 EPWM5:1; // 4 EPWM5 Clock Enable bit - Uint16 EPWM6:1; // 5 EPWM6 Clock Enable bit - Uint16 EPWM7:1; // 6 EPWM7 Clock Enable bit - Uint16 EPWM8:1; // 7 EPWM8 Clock Enable bit - Uint16 EPWM9:1; // 8 EPWM9 Clock Enable bit - Uint16 EPWM10:1; // 9 EPWM10 Clock Enable bit - Uint16 EPWM11:1; // 10 EPWM11 Clock Enable bit - Uint16 EPWM12:1; // 11 EPWM12 Clock Enable bit - Uint16 rsvd1:1; // 12 Reserved - Uint16 rsvd2:1; // 13 Reserved - Uint16 rsvd3:1; // 14 Reserved - Uint16 rsvd4:1; // 15 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union PCLKCR2_REG { - Uint32 all; - struct PCLKCR2_BITS bit; -}; - -struct PCLKCR3_BITS { // bits description - Uint16 ECAP1:1; // 0 ECAP1 Clock Enable bit - Uint16 ECAP2:1; // 1 ECAP2 Clock Enable bit - Uint16 ECAP3:1; // 2 ECAP3 Clock Enable bit - Uint16 ECAP4:1; // 3 ECAP4 Clock Enable bit - Uint16 ECAP5:1; // 4 ECAP5 Clock Enable bit - Uint16 ECAP6:1; // 5 ECAP6 Clock Enable bit - Uint16 rsvd1:1; // 6 Reserved - Uint16 rsvd2:1; // 7 Reserved - Uint16 rsvd3:8; // 15:8 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union PCLKCR3_REG { - Uint32 all; - struct PCLKCR3_BITS bit; -}; - -struct PCLKCR4_BITS { // bits description - Uint16 EQEP1:1; // 0 EQEP1 Clock Enable bit - Uint16 EQEP2:1; // 1 EQEP2 Clock Enable bit - Uint16 EQEP3:1; // 2 EQEP3 Clock Enable bit - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR4_REG { - Uint32 all; - struct PCLKCR4_BITS bit; -}; - -struct PCLKCR6_BITS { // bits description - Uint16 SD1:1; // 0 SD1 Clock Enable bit - Uint16 SD2:1; // 1 SD2 Clock Enable bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:1; // 4 Reserved - Uint16 rsvd4:1; // 5 Reserved - Uint16 rsvd5:1; // 6 Reserved - Uint16 rsvd6:1; // 7 Reserved - Uint16 rsvd7:8; // 15:8 Reserved - Uint16 rsvd8:16; // 31:16 Reserved -}; - -union PCLKCR6_REG { - Uint32 all; - struct PCLKCR6_BITS bit; -}; - -struct PCLKCR7_BITS { // bits description - Uint16 SCI_A:1; // 0 SCI_A Clock Enable bit - Uint16 SCI_B:1; // 1 SCI_B Clock Enable bit - Uint16 SCI_C:1; // 2 SCI_C Clock Enable bit - Uint16 SCI_D:1; // 3 SCI_D Clock Enable bit - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PCLKCR7_REG { - Uint32 all; - struct PCLKCR7_BITS bit; -}; - -struct PCLKCR8_BITS { // bits description - Uint16 SPI_A:1; // 0 SPI_A Clock Enable bit - Uint16 SPI_B:1; // 1 SPI_B Clock Enable bit - Uint16 SPI_C:1; // 2 SPI_C Clock Enable bit - Uint16 rsvd1:1; // 3 Reserved - Uint16 rsvd2:12; // 15:4 Reserved - Uint16 rsvd3:1; // 16 Reserved - Uint16 rsvd4:1; // 17 Reserved - Uint16 rsvd5:14; // 31:18 Reserved -}; - -union PCLKCR8_REG { - Uint32 all; - struct PCLKCR8_BITS bit; -}; - -struct PCLKCR9_BITS { // bits description - Uint16 I2C_A:1; // 0 I2C_A Clock Enable bit - Uint16 I2C_B:1; // 1 I2C_B Clock Enable bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:1; // 16 Reserved - Uint16 rsvd3:1; // 17 Reserved - Uint16 rsvd4:14; // 31:18 Reserved -}; - -union PCLKCR9_REG { - Uint32 all; - struct PCLKCR9_BITS bit; -}; - -struct PCLKCR10_BITS { // bits description - Uint16 CAN_A:1; // 0 CAN_A Clock Enable bit - Uint16 CAN_B:1; // 1 CAN_B Clock Enable bit - Uint16 rsvd1:1; // 2 Reserved - Uint16 rsvd2:1; // 3 Reserved - Uint16 rsvd3:12; // 15:4 Reserved - Uint16 rsvd4:16; // 31:16 Reserved -}; - -union PCLKCR10_REG { - Uint32 all; - struct PCLKCR10_BITS bit; -}; - -struct PCLKCR11_BITS { // bits description - Uint16 McBSP_A:1; // 0 McBSP_A Clock Enable bit - Uint16 McBSP_B:1; // 1 McBSP_B Clock Enable bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 USB_A:1; // 16 USB_A Clock Enable bit - Uint16 rsvd2:1; // 17 Reserved - Uint16 rsvd3:14; // 31:18 Reserved -}; - -union PCLKCR11_REG { - Uint32 all; - struct PCLKCR11_BITS bit; -}; - -struct PCLKCR12_BITS { // bits description - Uint16 uPP_A:1; // 0 uPP_A Clock Enable bit - Uint16 rsvd1:1; // 1 Reserved - Uint16 rsvd2:14; // 15:2 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PCLKCR12_REG { - Uint32 all; - struct PCLKCR12_BITS bit; -}; - -struct PCLKCR13_BITS { // bits description - Uint16 ADC_A:1; // 0 ADC_A Clock Enable bit - Uint16 ADC_B:1; // 1 ADC_B Clock Enable bit - Uint16 ADC_C:1; // 2 ADC_C Clock Enable bit - Uint16 ADC_D:1; // 3 ADC_D Clock Enable bit - Uint16 rsvd1:12; // 15:4 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PCLKCR13_REG { - Uint32 all; - struct PCLKCR13_BITS bit; -}; - -struct PCLKCR14_BITS { // bits description - Uint16 CMPSS1:1; // 0 CMPSS1 Clock Enable bit - Uint16 CMPSS2:1; // 1 CMPSS2 Clock Enable bit - Uint16 CMPSS3:1; // 2 CMPSS3 Clock Enable bit - Uint16 CMPSS4:1; // 3 CMPSS4 Clock Enable bit - Uint16 CMPSS5:1; // 4 CMPSS5 Clock Enable bit - Uint16 CMPSS6:1; // 5 CMPSS6 Clock Enable bit - Uint16 CMPSS7:1; // 6 CMPSS7 Clock Enable bit - Uint16 CMPSS8:1; // 7 CMPSS8 Clock Enable bit - Uint16 rsvd1:8; // 15:8 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union PCLKCR14_REG { - Uint32 all; - struct PCLKCR14_BITS bit; -}; - -struct PCLKCR16_BITS { // bits description - Uint16 rsvd1:1; // 0 Reserved - Uint16 rsvd2:1; // 1 Reserved - Uint16 rsvd3:1; // 2 Reserved - Uint16 rsvd4:1; // 3 Reserved - Uint16 rsvd5:12; // 15:4 Reserved - Uint16 DAC_A:1; // 16 Buffered_DAC_A Clock Enable Bit - Uint16 DAC_B:1; // 17 Buffered_DAC_B Clock Enable Bit - Uint16 DAC_C:1; // 18 Buffered_DAC_C Clock Enable Bit - Uint16 rsvd6:1; // 19 Reserved - Uint16 rsvd7:12; // 31:20 Reserved -}; - -union PCLKCR16_REG { - Uint32 all; - struct PCLKCR16_BITS bit; -}; - -struct SECMSEL_BITS { // bits description - Uint16 PF1SEL:2; // 1:0 Secondary Master Select for VBUS32_1 Bridge - Uint16 PF2SEL:2; // 3:2 Secondary Master Select for VBUS32_2 Bridge - Uint16 rsvd1:2; // 5:4 Reserved - Uint16 rsvd2:2; // 7:6 Reserved - Uint16 rsvd3:2; // 9:8 Reserved - Uint16 rsvd4:2; // 11:10 Reserved - Uint16 rsvd5:2; // 13:12 Reserved - Uint16 rsvd6:2; // 15:14 Reserved - Uint16 rsvd7:16; // 31:16 Reserved -}; - -union SECMSEL_REG { - Uint32 all; - struct SECMSEL_BITS bit; -}; - -struct LPMCR_BITS { // bits description - Uint16 LPM:2; // 1:0 Low Power Mode setting - Uint16 QUALSTDBY:6; // 7:2 STANDBY Wakeup Pin Qualification Setting - Uint16 rsvd1:7; // 14:8 Reserved - Uint16 WDINTE:1; // 15 Enable for WDINT wakeup from STANDBY - Uint16 M0M1MODE:2; // 17:16 Configuration for M0 and M1 mode during HIB - Uint16 rsvd2:13; // 30:18 Reserved - Uint16 IOISODIS:1; // 31 IO Isolation Disable -}; - -union LPMCR_REG { - Uint32 all; - struct LPMCR_BITS bit; -}; - -struct GPIOLPMSEL0_BITS { // bits description - Uint16 GPIO0:1; // 0 GPIO0 Enable for LPM Wakeup - Uint16 GPIO1:1; // 1 GPIO1 Enable for LPM Wakeup - Uint16 GPIO2:1; // 2 GPIO2 Enable for LPM Wakeup - Uint16 GPIO3:1; // 3 GPIO3 Enable for LPM Wakeup - Uint16 GPIO4:1; // 4 GPIO4 Enable for LPM Wakeup - Uint16 GPIO5:1; // 5 GPIO5 Enable for LPM Wakeup - Uint16 GPIO6:1; // 6 GPIO6 Enable for LPM Wakeup - Uint16 GPIO7:1; // 7 GPIO7 Enable for LPM Wakeup - Uint16 GPIO8:1; // 8 GPIO8 Enable for LPM Wakeup - Uint16 GPIO9:1; // 9 GPIO9 Enable for LPM Wakeup - Uint16 GPIO10:1; // 10 GPIO10 Enable for LPM Wakeup - Uint16 GPIO11:1; // 11 GPIO11 Enable for LPM Wakeup - Uint16 GPIO12:1; // 12 GPIO12 Enable for LPM Wakeup - Uint16 GPIO13:1; // 13 GPIO13 Enable for LPM Wakeup - Uint16 GPIO14:1; // 14 GPIO14 Enable for LPM Wakeup - Uint16 GPIO15:1; // 15 GPIO15 Enable for LPM Wakeup - Uint16 GPIO16:1; // 16 GPIO16 Enable for LPM Wakeup - Uint16 GPIO17:1; // 17 GPIO17 Enable for LPM Wakeup - Uint16 GPIO18:1; // 18 GPIO18 Enable for LPM Wakeup - Uint16 GPIO19:1; // 19 GPIO19 Enable for LPM Wakeup - Uint16 GPIO20:1; // 20 GPIO20 Enable for LPM Wakeup - Uint16 GPIO21:1; // 21 GPIO21 Enable for LPM Wakeup - Uint16 GPIO22:1; // 22 GPIO22 Enable for LPM Wakeup - Uint16 GPIO23:1; // 23 GPIO23 Enable for LPM Wakeup - Uint16 GPIO24:1; // 24 GPIO24 Enable for LPM Wakeup - Uint16 GPIO25:1; // 25 GPIO25 Enable for LPM Wakeup - Uint16 GPIO26:1; // 26 GPIO26 Enable for LPM Wakeup - Uint16 GPIO27:1; // 27 GPIO27 Enable for LPM Wakeup - Uint16 GPIO28:1; // 28 GPIO28 Enable for LPM Wakeup - Uint16 GPIO29:1; // 29 GPIO29 Enable for LPM Wakeup - Uint16 GPIO30:1; // 30 GPIO30 Enable for LPM Wakeup - Uint16 GPIO31:1; // 31 GPIO31 Enable for LPM Wakeup -}; - -union GPIOLPMSEL0_REG { - Uint32 all; - struct GPIOLPMSEL0_BITS bit; -}; - -struct GPIOLPMSEL1_BITS { // bits description - Uint16 GPIO32:1; // 0 GPIO32 Enable for LPM Wakeup - Uint16 GPIO33:1; // 1 GPIO33 Enable for LPM Wakeup - Uint16 GPIO34:1; // 2 GPIO34 Enable for LPM Wakeup - Uint16 GPIO35:1; // 3 GPIO35 Enable for LPM Wakeup - Uint16 GPIO36:1; // 4 GPIO36 Enable for LPM Wakeup - Uint16 GPIO37:1; // 5 GPIO37 Enable for LPM Wakeup - Uint16 GPIO38:1; // 6 GPIO38 Enable for LPM Wakeup - Uint16 GPIO39:1; // 7 GPIO39 Enable for LPM Wakeup - Uint16 GPIO40:1; // 8 GPIO40 Enable for LPM Wakeup - Uint16 GPIO41:1; // 9 GPIO41 Enable for LPM Wakeup - Uint16 GPIO42:1; // 10 GPIO42 Enable for LPM Wakeup - Uint16 GPIO43:1; // 11 GPIO43 Enable for LPM Wakeup - Uint16 GPIO44:1; // 12 GPIO44 Enable for LPM Wakeup - Uint16 GPIO45:1; // 13 GPIO45 Enable for LPM Wakeup - Uint16 GPIO46:1; // 14 GPIO46 Enable for LPM Wakeup - Uint16 GPIO47:1; // 15 GPIO47 Enable for LPM Wakeup - Uint16 GPIO48:1; // 16 GPIO48 Enable for LPM Wakeup - Uint16 GPIO49:1; // 17 GPIO49 Enable for LPM Wakeup - Uint16 GPIO50:1; // 18 GPIO50 Enable for LPM Wakeup - Uint16 GPIO51:1; // 19 GPIO51 Enable for LPM Wakeup - Uint16 GPIO52:1; // 20 GPIO52 Enable for LPM Wakeup - Uint16 GPIO53:1; // 21 GPIO53 Enable for LPM Wakeup - Uint16 GPIO54:1; // 22 GPIO54 Enable for LPM Wakeup - Uint16 GPIO55:1; // 23 GPIO55 Enable for LPM Wakeup - Uint16 GPIO56:1; // 24 GPIO56 Enable for LPM Wakeup - Uint16 GPIO57:1; // 25 GPIO57 Enable for LPM Wakeup - Uint16 GPIO58:1; // 26 GPIO58 Enable for LPM Wakeup - Uint16 GPIO59:1; // 27 GPIO59 Enable for LPM Wakeup - Uint16 GPIO60:1; // 28 GPIO60 Enable for LPM Wakeup - Uint16 GPIO61:1; // 29 GPIO61 Enable for LPM Wakeup - Uint16 GPIO62:1; // 30 GPIO62 Enable for LPM Wakeup - Uint16 GPIO63:1; // 31 GPIO63 Enable for LPM Wakeup -}; - -union GPIOLPMSEL1_REG { - Uint32 all; - struct GPIOLPMSEL1_BITS bit; -}; - -struct TMR2CLKCTL_BITS { // bits description - Uint16 TMR2CLKSRCSEL:3; // 2:0 CPU Timer 2 Clock Source Select Bit - Uint16 TMR2CLKPRESCALE:3; // 5:3 CPU Timer 2 Clock Pre-Scale Value - Uint16 rsvd1:10; // 15:6 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union TMR2CLKCTL_REG { - Uint32 all; - struct TMR2CLKCTL_BITS bit; -}; - -struct RESC_BITS { // bits description - Uint16 POR:1; // 0 POR Reset Cause Indication Bit - Uint16 XRSn:1; // 1 XRSn Reset Cause Indication Bit - Uint16 WDRSn:1; // 2 WDRSn Reset Cause Indication Bit - Uint16 NMIWDRSn:1; // 3 NMIWDRSn Reset Cause Indication Bit - Uint16 rsvd1:1; // 4 Reserved - Uint16 HWBISTn:1; // 5 HWBISTn Reset Cause Indication Bit - Uint16 HIBRESETn:1; // 6 HIBRESETn Reset Cause Indication Bit - Uint16 rsvd2:1; // 7 Reserved - Uint16 SCCRESETn:1; // 8 SCCRESETn Reset Cause Indication Bit - Uint16 rsvd3:7; // 15:9 Reserved - Uint16 rsvd4:14; // 29:16 Reserved - Uint16 XRSn_pin_status:1; // 30 XRSN Pin Status - Uint16 TRSTn_pin_status:1; // 31 TRSTn Status -}; - -union RESC_REG { - Uint32 all; - struct RESC_BITS bit; -}; - -struct CPU_SYS_REGS { - union CPUSYSLOCK1_REG CPUSYSLOCK1; // Lock bit for CPUSYS registers - Uint16 rsvd1[4]; // Reserved - Uint32 HIBBOOTMODE; // HIB Boot Mode Register - union IORESTOREADDR_REG IORESTOREADDR; // IORestore() routine Address Register - union PIEVERRADDR_REG PIEVERRADDR; // PIE Vector Fetch Error Address register - Uint16 rsvd2[22]; // Reserved - union PCLKCR0_REG PCLKCR0; // Peripheral Clock Gating Registers - union PCLKCR1_REG PCLKCR1; // Peripheral Clock Gating Registers - union PCLKCR2_REG PCLKCR2; // Peripheral Clock Gating Registers - union PCLKCR3_REG PCLKCR3; // Peripheral Clock Gating Registers - union PCLKCR4_REG PCLKCR4; // Peripheral Clock Gating Registers - Uint16 rsvd3[2]; // Reserved - union PCLKCR6_REG PCLKCR6; // Peripheral Clock Gating Registers - union PCLKCR7_REG PCLKCR7; // Peripheral Clock Gating Registers - union PCLKCR8_REG PCLKCR8; // Peripheral Clock Gating Registers - union PCLKCR9_REG PCLKCR9; // Peripheral Clock Gating Registers - union PCLKCR10_REG PCLKCR10; // Peripheral Clock Gating Registers - union PCLKCR11_REG PCLKCR11; // Peripheral Clock Gating Registers - union PCLKCR12_REG PCLKCR12; // Peripheral Clock Gating Registers - union PCLKCR13_REG PCLKCR13; // Peripheral Clock Gating Registers - union PCLKCR14_REG PCLKCR14; // Peripheral Clock Gating Registers - Uint16 rsvd4[2]; // Reserved - union PCLKCR16_REG PCLKCR16; // Peripheral Clock Gating Registers - Uint16 rsvd5[48]; // Reserved - union SECMSEL_REG SECMSEL; // Secondary Master Select register for common peripherals: Selects between CLA & DMA - union LPMCR_REG LPMCR; // LPM Control Register - union GPIOLPMSEL0_REG GPIOLPMSEL0; // GPIO LPM Wakeup select registers - union GPIOLPMSEL1_REG GPIOLPMSEL1; // GPIO LPM Wakeup select registers - union TMR2CLKCTL_REG TMR2CLKCTL; // Timer2 Clock Measurement functionality control register - Uint16 rsvd6[2]; // Reserved - union RESC_REG RESC; // Reset Cause register -}; - -struct SCSR_BITS { // bits description - Uint16 WDOVERRIDE:1; // 0 WD Override for WDDIS bit - Uint16 WDENINT:1; // 1 WD Interrupt Enable - Uint16 WDINTS:1; // 2 WD Interrupt Status - Uint16 rsvd1:13; // 15:3 Reserved -}; - -union SCSR_REG { - Uint16 all; - struct SCSR_BITS bit; -}; - -struct WDCNTR_BITS { // bits description - Uint16 WDCNTR:8; // 7:0 WD Counter - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union WDCNTR_REG { - Uint16 all; - struct WDCNTR_BITS bit; -}; - -struct WDKEY_BITS { // bits description - Uint16 WDKEY:8; // 7:0 WD KEY - Uint16 rsvd1:8; // 15:8 Reserved -}; - -union WDKEY_REG { - Uint16 all; - struct WDKEY_BITS bit; -}; - -struct WDCR_BITS { // bits description - Uint16 WDPS:3; // 2:0 WD Clock Prescalar - Uint16 WDCHK:3; // 5:3 WD Check Bits - Uint16 WDDIS:1; // 6 WD Disable - Uint16 rsvd1:1; // 7 Reserved - Uint16 rsvd2:8; // 15:8 Reserved -}; - -union WDCR_REG { - Uint16 all; - struct WDCR_BITS bit; -}; - -struct WDWCR_BITS { // bits description - Uint16 MIN:8; // 7:0 WD Min Threshold setting for Windowed Watchdog functionality - Uint16 FIRSTKEY:1; // 8 First Key Detect Flag - Uint16 rsvd1:7; // 15:9 Reserved -}; - -union WDWCR_REG { - Uint16 all; - struct WDWCR_BITS bit; -}; - -struct WD_REGS { - Uint16 rsvd1[34]; // Reserved - union SCSR_REG SCSR; // System Control & Status Register - union WDCNTR_REG WDCNTR; // Watchdog Counter Register - Uint16 rsvd2; // Reserved - union WDKEY_REG WDKEY; // Watchdog Reset Key Register - Uint16 rsvd3[3]; // Reserved - union WDCR_REG WDCR; // Watchdog Control Register - union WDWCR_REG WDWCR; // Watchdog Windowed Control Register -}; - -struct CLA1TASKSRCSELLOCK_BITS { // bits description - Uint16 CLA1TASKSRCSEL1:1; // 0 CLA1TASKSRCSEL1 Register Lock bit - Uint16 CLA1TASKSRCSEL2:1; // 1 CLA1TASKSRCSEL2 Register Lock bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union CLA1TASKSRCSELLOCK_REG { - Uint32 all; - struct CLA1TASKSRCSELLOCK_BITS bit; -}; - -struct DMACHSRCSELLOCK_BITS { // bits description - Uint16 DMACHSRCSEL1:1; // 0 DMACHSRCSEL1 Register Lock bit - Uint16 DMACHSRCSEL2:1; // 1 DMACHSRCSEL2 Register Lock bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DMACHSRCSELLOCK_REG { - Uint32 all; - struct DMACHSRCSELLOCK_BITS bit; -}; - -struct CLA1TASKSRCSEL1_BITS { // bits description - Uint16 TASK1:8; // 7:0 Selects the Trigger Source for TASK1 of CLA1 - Uint16 TASK2:8; // 15:8 Selects the Trigger Source for TASK2 of CLA1 - Uint16 TASK3:8; // 23:16 Selects the Trigger Source for TASK3 of CLA1 - Uint16 TASK4:8; // 31:24 Selects the Trigger Source for TASK4 of CLA1 -}; - -union CLA1TASKSRCSEL1_REG { - Uint32 all; - struct CLA1TASKSRCSEL1_BITS bit; -}; - -struct CLA1TASKSRCSEL2_BITS { // bits description - Uint16 TASK5:8; // 7:0 Selects the Trigger Source for TASK5 of CLA1 - Uint16 TASK6:8; // 15:8 Selects the Trigger Source for TASK6 of CLA1 - Uint16 TASK7:8; // 23:16 Selects the Trigger Source for TASK7 of CLA1 - Uint16 TASK8:8; // 31:24 Selects the Trigger Source for TASK8 of CLA1 -}; - -union CLA1TASKSRCSEL2_REG { - Uint32 all; - struct CLA1TASKSRCSEL2_BITS bit; -}; - -struct DMACHSRCSEL1_BITS { // bits description - Uint16 CH1:8; // 7:0 Selects the Trigger and Sync Source CH1 of DMA - Uint16 CH2:8; // 15:8 Selects the Trigger and Sync Source CH2 of DMA - Uint16 CH3:8; // 23:16 Selects the Trigger and Sync Source CH3 of DMA - Uint16 CH4:8; // 31:24 Selects the Trigger and Sync Source CH4 of DMA -}; - -union DMACHSRCSEL1_REG { - Uint32 all; - struct DMACHSRCSEL1_BITS bit; -}; - -struct DMACHSRCSEL2_BITS { // bits description - Uint16 CH5:8; // 7:0 Selects the Trigger and Sync Source CH5 of DMA - Uint16 CH6:8; // 15:8 Selects the Trigger and Sync Source CH6 of DMA - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union DMACHSRCSEL2_REG { - Uint32 all; - struct DMACHSRCSEL2_BITS bit; -}; - -struct DMA_CLA_SRC_SEL_REGS { - union CLA1TASKSRCSELLOCK_REG CLA1TASKSRCSELLOCK; // CLA1 Task Trigger Source Select Lock Register - Uint16 rsvd1[2]; // Reserved - union DMACHSRCSELLOCK_REG DMACHSRCSELLOCK; // DMA Channel Triger Source Select Lock Register - union CLA1TASKSRCSEL1_REG CLA1TASKSRCSEL1; // CLA1 Task Trigger Source Select Register-1 - union CLA1TASKSRCSEL2_REG CLA1TASKSRCSEL2; // CLA1 Task Trigger Source Select Register-2 - Uint16 rsvd2[12]; // Reserved - union DMACHSRCSEL1_REG DMACHSRCSEL1; // DMA Channel Trigger Source Select Register-1 - union DMACHSRCSEL2_REG DMACHSRCSEL2; // DMA Channel Trigger Source Select Register-2 -}; - -struct SYNCSELECT_BITS { // bits description - Uint16 EPWM4SYNCIN:3; // 2:0 Selects Sync Input Source for EPWM4 - Uint16 EPWM7SYNCIN:3; // 5:3 Selects Sync Input Source for EPWM7 - Uint16 EPWM10SYNCIN:3; // 8:6 Selects Sync Input Source for EPWM10 - Uint16 ECAP1SYNCIN:3; // 11:9 Selects Sync Input Source for ECAP1 - Uint16 ECAP4SYNCIN:3; // 14:12 Selects Sync Input Source for ECAP4 - Uint16 rsvd1:1; // 15 Reserved - Uint16 rsvd2:11; // 26:16 Reserved - Uint16 SYNCOUT:2; // 28:27 Select Syncout Source - Uint16 rsvd3:3; // 31:29 Reserved -}; - -union SYNCSELECT_REG { - Uint32 all; - struct SYNCSELECT_BITS bit; -}; - -struct ADCSOCOUTSELECT_BITS { // bits description - Uint16 PWM1SOCAEN:1; // 0 PWM1SOCAEN Enable for ADCSOCAO - Uint16 PWM2SOCAEN:1; // 1 PWM2SOCAEN Enable for ADCSOCAO - Uint16 PWM3SOCAEN:1; // 2 PWM3SOCAEN Enable for ADCSOCAO - Uint16 PWM4SOCAEN:1; // 3 PWM4SOCAEN Enable for ADCSOCAO - Uint16 PWM5SOCAEN:1; // 4 PWM5SOCAEN Enable for ADCSOCAO - Uint16 PWM6SOCAEN:1; // 5 PWM6SOCAEN Enable for ADCSOCAO - Uint16 PWM7SOCAEN:1; // 6 PWM7SOCAEN Enable for ADCSOCAO - Uint16 PWM8SOCAEN:1; // 7 PWM8SOCAEN Enable for ADCSOCAO - Uint16 PWM9SOCAEN:1; // 8 PWM9SOCAEN Enable for ADCSOCAO - Uint16 PWM10SOCAEN:1; // 9 PWM10SOCAEN Enable for ADCSOCAO - Uint16 PWM11SOCAEN:1; // 10 PWM11SOCAEN Enable for ADCSOCAO - Uint16 PWM12SOCAEN:1; // 11 PWM12SOCAEN Enable for ADCSOCAO - Uint16 rsvd1:4; // 15:12 Reserved - Uint16 PWM1SOCBEN:1; // 16 PWM1SOCBEN Enable for ADCSOCBO - Uint16 PWM2SOCBEN:1; // 17 PWM2SOCBEN Enable for ADCSOCBO - Uint16 PWM3SOCBEN:1; // 18 PWM3SOCBEN Enable for ADCSOCBO - Uint16 PWM4SOCBEN:1; // 19 PWM4SOCBEN Enable for ADCSOCBO - Uint16 PWM5SOCBEN:1; // 20 PWM5SOCBEN Enable for ADCSOCBO - Uint16 PWM6SOCBEN:1; // 21 PWM6SOCBEN Enable for ADCSOCBO - Uint16 PWM7SOCBEN:1; // 22 PWM7SOCBEN Enable for ADCSOCBO - Uint16 PWM8SOCBEN:1; // 23 PWM8SOCBEN Enable for ADCSOCBO - Uint16 PWM9SOCBEN:1; // 24 PWM9SOCBEN Enable for ADCSOCBO - Uint16 PWM10SOCBEN:1; // 25 PWM10SOCBEN Enable for ADCSOCBO - Uint16 PWM11SOCBEN:1; // 26 PWM11SOCBEN Enable for ADCSOCBO - Uint16 PWM12SOCBEN:1; // 27 PWM12SOCBEN Enable for ADCSOCBO - Uint16 rsvd2:4; // 31:28 Reserved -}; - -union ADCSOCOUTSELECT_REG { - Uint32 all; - struct ADCSOCOUTSELECT_BITS bit; -}; - -struct SYNCSOCLOCK_BITS { // bits description - Uint16 SYNCSELECT:1; // 0 SYNCSEL Register Lock bit - Uint16 ADCSOCOUTSELECT:1; // 1 ADCSOCOUTSELECT Register Lock bit - Uint16 rsvd1:14; // 15:2 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union SYNCSOCLOCK_REG { - Uint32 all; - struct SYNCSOCLOCK_BITS bit; -}; - -struct SYNC_SOC_REGS { - union SYNCSELECT_REG SYNCSELECT; // Sync Input and Output Select Register - union ADCSOCOUTSELECT_REG ADCSOCOUTSELECT; // External ADC (Off Chip) SOC Select Register - union SYNCSOCLOCK_REG SYNCSOCLOCK; // SYNCSEL and EXTADCSOC Select Lock register -}; - -//--------------------------------------------------------------------------- -// SYSCTRL External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct WD_REGS WdRegs; -extern volatile struct SYNC_SOC_REGS SyncSocRegs; -extern volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; -extern volatile struct DEV_CFG_REGS DevCfgRegs; -extern volatile struct CLK_CFG_REGS ClkCfgRegs; -extern volatile struct CPU_SYS_REGS CpuSysRegs; -#endif -#ifdef CPU2 -extern volatile struct WD_REGS WdRegs; -extern volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; -extern volatile struct CLK_CFG_REGS ClkCfgRegs; -extern volatile struct CPU_SYS_REGS CpuSysRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_upp.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_upp.h deleted file mode 100644 index c33bcc90f2..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_upp.h +++ /dev/null @@ -1,403 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_upp.h -// -// TITLE: UPP Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_UPP_H__ -#define __F2837xD_UPP_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// UPP Individual Register Bit Definitions: - -struct PERCTL_BITS { // bits description - Uint16 FREE:1; // 0 Emulation control. - Uint16 SOFT:1; // 1 Emulation control. - Uint16 RTEMU:1; // 2 Realtime emulation control. - Uint16 PEREN:1; // 3 Peripheral Enable - Uint16 SOFTRST:1; // 4 Software Reset - Uint16 rsvd1:2; // 6:5 Reserved - Uint16 DMAST:1; // 7 DMA Burst transaction status - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union PERCTL_REG { - Uint32 all; - struct PERCTL_BITS bit; -}; - -struct CHCTL_BITS { // bits description - Uint16 MODE:2; // 1:0 Operating mode - Uint16 rsvd1:1; // 2 Reserved - Uint16 SDRTXILA:1; // 3 SDR TX Interleve mode - Uint16 DEMUXA:1; // 4 DDR de-multiplexing mode - Uint16 rsvd2:11; // 15:5 Reserved - Uint16 DRA:1; // 16 Data rate - Uint16 rsvd3:14; // 30:17 Reserved - Uint16 rsvd4:1; // 31 Reserved -}; - -union CHCTL_REG { - Uint32 all; - struct CHCTL_BITS bit; -}; - -struct IFCFG_BITS { // bits description - Uint16 STARTPOLA:1; // 0 Polarity of START(SELECT) signal - Uint16 ENAPOLA:1; // 1 Polarity of ENABLE(WRITE) signal - Uint16 WAITPOLA:1; // 2 Polarity of WAIT signal. - Uint16 STARTA:1; // 3 Enable Usage of START (SELECT) signal - Uint16 ENAA:1; // 4 Enable Usage of ENABLE (WRITE) signal - Uint16 WAITA:1; // 5 Enable Usage of WAIT signal - Uint16 rsvd1:2; // 7:6 Reserved - Uint16 CLKDIVA:4; // 11:8 Clock divider for tx mode - Uint16 CLKINVA:1; // 12 Clock inversion - Uint16 TRISENA:1; // 13 Pin Tri-state Control - Uint16 rsvd2:2; // 15:14 Reserved - Uint16 rsvd3:6; // 21:16 Reserved - Uint16 rsvd4:2; // 23:22 Reserved - Uint16 rsvd5:6; // 29:24 Reserved - Uint16 rsvd6:2; // 31:30 Reserved -}; - -union IFCFG_REG { - Uint32 all; - struct IFCFG_BITS bit; -}; - -struct IFIVAL_BITS { // bits description - Uint16 VALA:9; // 8:0 Idle Value - Uint16 rsvd1:7; // 15:9 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union IFIVAL_REG { - Uint32 all; - struct IFIVAL_BITS bit; -}; - -struct THCFG_BITS { // bits description - Uint16 RDSIZEI:2; // 1:0 DMA Read Threshold for DMA Channel I - Uint16 rsvd1:6; // 7:2 Reserved - Uint16 RDSIZEQ:2; // 9:8 DMA Read Threshold for DMA Channel Q - Uint16 rsvd2:6; // 15:10 Reserved - Uint16 TXSIZEA:2; // 17:16 I/O Transmit Threshold Value - Uint16 rsvd3:6; // 23:18 Reserved - Uint16 rsvd4:2; // 25:24 Reserved - Uint16 rsvd5:6; // 31:26 Reserved -}; - -union THCFG_REG { - Uint32 all; - struct THCFG_BITS bit; -}; - -struct RAWINTST_BITS { // bits description - Uint16 DPEI:1; // 0 Interrupt raw status for DMA programming error - Uint16 UOEI:1; // 1 Interrupt raw status for DMA under-run or over-run - Uint16 rsvd1:1; // 2 Reserved - Uint16 EOWI:1; // 3 Interrupt raw status for end-of window condition - Uint16 EOLI:1; // 4 Interrupt raw status for end-of-line condition - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 DPEQ:1; // 8 Interrupt raw status for DMA programming error - Uint16 UOEQ:1; // 9 Interrupt raw status for DMA under-run or over-run - Uint16 rsvd3:1; // 10 Reserved - Uint16 EOWQ:1; // 11 Interrupt raw status for end-of window condition - Uint16 EOLQ:1; // 12 Interrupt raw status for end-of-line condition - Uint16 rsvd4:3; // 15:13 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union RAWINTST_REG { - Uint32 all; - struct RAWINTST_BITS bit; -}; - -struct ENINTST_BITS { // bits description - Uint16 DPEI:1; // 0 Interrupt enable status for DMA programming error - Uint16 UOEI:1; // 1 Interrupt enable status for DMA under-run or over-run - Uint16 rsvd1:1; // 2 Reserved - Uint16 EOWI:1; // 3 Interrupt enable status for end-of window condition - Uint16 EOLI:1; // 4 Interrupt enable status for end-of-line condition - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 DPEQ:1; // 8 Interrupt enable status for DMA programming error - Uint16 UOEQ:1; // 9 Interrupt enable status for DMA under-run or over-run - Uint16 rsvd3:1; // 10 Reserved - Uint16 EOWQ:1; // 11 Interrupt enable status for end-of window condition - Uint16 EOLQ:1; // 12 Interrupt enable status for end-of-line condition - Uint16 rsvd4:3; // 15:13 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union ENINTST_REG { - Uint32 all; - struct ENINTST_BITS bit; -}; - -struct INTENSET_BITS { // bits description - Uint16 DPEI:1; // 0 Interrupt enable for DMA programming error - Uint16 UOEI:1; // 1 Interrupt enable for DMA under-run or over-run - Uint16 rsvd1:1; // 2 Reserved - Uint16 EOWI:1; // 3 Interrupt enable for end-of window condition - Uint16 EOLI:1; // 4 Interrupt enable for end-of-line condition - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 DPEQ:1; // 8 Interrupt enable for DMA programming error - Uint16 UOEQ:1; // 9 Interrupt enable for DMA under-run or over-run - Uint16 rsvd3:1; // 10 Reserved - Uint16 EOWQ:1; // 11 Interrupt enable for end-of window condition - Uint16 EOLQ:1; // 12 Interrupt enable for end-of-line condition - Uint16 rsvd4:3; // 15:13 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union INTENSET_REG { - Uint32 all; - struct INTENSET_BITS bit; -}; - -struct INTENCLR_BITS { // bits description - Uint16 DPEI:1; // 0 Interrupt clear for DMA programming error - Uint16 UOEI:1; // 1 Interrupt clear for DMA under-run or over-run - Uint16 rsvd1:1; // 2 Reserved - Uint16 EOWI:1; // 3 Interrupt clear for end-of window condition - Uint16 EOLI:1; // 4 Interrupt clear for end-of-line condition - Uint16 rsvd2:3; // 7:5 Reserved - Uint16 DPEQ:1; // 8 Interrupt clear for DMA programming error - Uint16 UOEQ:1; // 9 Interrupt clear for DMA under-run or over-run - Uint16 rsvd3:1; // 10 Reserved - Uint16 EOWQ:1; // 11 Interrupt clear for end-of window condition - Uint16 EOLQ:1; // 12 Interrupt clear for end-of-line condition - Uint16 rsvd4:3; // 15:13 Reserved - Uint16 rsvd5:16; // 31:16 Reserved -}; - -union INTENCLR_REG { - Uint32 all; - struct INTENCLR_BITS bit; -}; - -struct CHIDESC1_BITS { // bits description - Uint16 BCNT:16; // 15:0 Number of bytes in a line for DMA Channel I transfer. - Uint16 LCNT:16; // 31:16 Number of lines in a window for DMA Channel I transfer. -}; - -union CHIDESC1_REG { - Uint32 all; - struct CHIDESC1_BITS bit; -}; - -struct CHIDESC2_BITS { // bits description - Uint16 LOFFSET:16; // 15:0 Current start address to next start address offset. - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union CHIDESC2_REG { - Uint32 all; - struct CHIDESC2_BITS bit; -}; - -struct CHIST1_BITS { // bits description - Uint16 BCNT:16; // 15:0 Current byte number. - Uint16 LCNT:16; // 31:16 Current line number. -}; - -union CHIST1_REG { - Uint32 all; - struct CHIST1_BITS bit; -}; - -struct CHIST2_BITS { // bits description - Uint16 ACT:1; // 0 Status of DMA descriptor. - Uint16 PEND:1; // 1 Status of DMA. - Uint16 rsvd1:2; // 3:2 Reserved - Uint16 WM:4; // 7:4 Watermark for FIFO block count for DMA Channel I tranfer. - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CHIST2_REG { - Uint32 all; - struct CHIST2_BITS bit; -}; - -struct CHQDESC1_BITS { // bits description - Uint16 BCNT:16; // 15:0 Number of bytes in a line for DMA Channel Q transfer. - Uint16 LCNT:16; // 31:16 Number of lines in a window for DMA Channel Q transfer. -}; - -union CHQDESC1_REG { - Uint32 all; - struct CHQDESC1_BITS bit; -}; - -struct CHQDESC2_BITS { // bits description - Uint16 LOFFSET:16; // 15:0 Current start address to next start address offset. - Uint16 rsvd1:16; // 31:16 Reserved -}; - -union CHQDESC2_REG { - Uint32 all; - struct CHQDESC2_BITS bit; -}; - -struct CHQST1_BITS { // bits description - Uint16 BCNT:16; // 15:0 Current byte number. - Uint16 LCNT:16; // 31:16 Current line number. -}; - -union CHQST1_REG { - Uint32 all; - struct CHQST1_BITS bit; -}; - -struct CHQST2_BITS { // bits description - Uint16 ACT:1; // 0 Status of DMA descriptor. - Uint16 PEND:1; // 1 Status of DMA. - Uint16 rsvd1:2; // 3:2 Reserved - Uint16 WM:4; // 7:4 Watermark for FIFO block count for DMA Channel Q tranfer. - Uint16 rsvd2:8; // 15:8 Reserved - Uint16 rsvd3:16; // 31:16 Reserved -}; - -union CHQST2_REG { - Uint32 all; - struct CHQST2_BITS bit; -}; - -struct GINTEN_BITS { // bits description - Uint16 GINTEN:1; // 0 Global Interrupt Enable - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union GINTEN_REG { - Uint32 all; - struct GINTEN_BITS bit; -}; - -struct GINTFLG_BITS { // bits description - Uint16 GINTFLG:1; // 0 Global Interrupt Flag - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union GINTFLG_REG { - Uint32 all; - struct GINTFLG_BITS bit; -}; - -struct GINTCLR_BITS { // bits description - Uint16 GINTCLR:1; // 0 Global Interrupt Clear - Uint16 rsvd1:15; // 15:1 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union GINTCLR_REG { - Uint32 all; - struct GINTCLR_BITS bit; -}; - -struct DLYCTL_BITS { // bits description - Uint16 DLYDIS:1; // 0 IO dealy control disable. - Uint16 DLYCTL:2; // 2:1 IO delay control. - Uint16 rsvd1:13; // 15:3 Reserved - Uint16 rsvd2:16; // 31:16 Reserved -}; - -union DLYCTL_REG { - Uint32 all; - struct DLYCTL_BITS bit; -}; - -struct UPP_REGS { - Uint32 PID; // Peripheral ID Register - union PERCTL_REG PERCTL; // Peripheral Control Register - Uint16 rsvd1[4]; // Reserved - union CHCTL_REG CHCTL; // General Control Register - union IFCFG_REG IFCFG; // Interface Configuration Register - union IFIVAL_REG IFIVAL; // Interface Idle Value Register - union THCFG_REG THCFG; // Threshold Configuration Register - union RAWINTST_REG RAWINTST; // Raw Interrupt Status Register - union ENINTST_REG ENINTST; // Enable Interrupt Status Register - union INTENSET_REG INTENSET; // Interrupt Enable Set Register - union INTENCLR_REG INTENCLR; // Interrupt Enable Clear Register - Uint16 rsvd2[8]; // Reserved - Uint32 CHIDESC0; // DMA Channel I Descriptor 0 Register - union CHIDESC1_REG CHIDESC1; // DMA Channel I Descriptor 1 Register - union CHIDESC2_REG CHIDESC2; // DMA Channel I Descriptor 2 Register - Uint16 rsvd3[2]; // Reserved - Uint32 CHIST0; // DMA Channel I Status 0 Register - union CHIST1_REG CHIST1; // DMA Channel I Status 1 Register - union CHIST2_REG CHIST2; // DMA Channel I Status 2 Register - Uint16 rsvd4[2]; // Reserved - Uint32 CHQDESC0; // DMA Channel Q Descriptor 0 Register - union CHQDESC1_REG CHQDESC1; // DMA Channel Q Descriptor 1 Register - union CHQDESC2_REG CHQDESC2; // DMA Channel Q Descriptor 2 Register - Uint16 rsvd5[2]; // Reserved - Uint32 CHQST0; // DMA Channel Q Status 0 Register - union CHQST1_REG CHQST1; // DMA Channel Q Status 1 Register - union CHQST2_REG CHQST2; // DMA Channel Q Status 2 Register - Uint16 rsvd6[2]; // Reserved - union GINTEN_REG GINTEN; // Global Peripheral Interrupt Enable Register - union GINTFLG_REG GINTFLG; // Global Peripheral Interrupt Flag Register - union GINTCLR_REG GINTCLR; // Global Peripheral Interrupt Clear Register - union DLYCTL_REG DLYCTL; // IO clock data skew control Register -}; - -//--------------------------------------------------------------------------- -// UPP External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct UPP_REGS UppRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_xbar.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_xbar.h deleted file mode 100644 index d201fda67c..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_xbar.h +++ /dev/null @@ -1,303 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_xbar.h -// -// TITLE: XBAR Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_XBAR_H__ -#define __F2837xD_XBAR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// XBAR Individual Register Bit Definitions: - -struct XBARFLG1_BITS { // bits description - Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag for CMPSS1.CTRIPL Signal - Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag for CMPSS1.CTRIPH Signal - Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag for CMPSS2.CTRIPL Signal - Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag for CMPSS2.CTRIPH Signal - Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag for CMPSS3.CTRIPL Signal - Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag for CMPSS3.CTRIPH Signal - Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag for CMPSS4.CTRIPL Signal - Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag for CMPSS4.CTRIPH Signal - Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag for CMPSS5.CTRIPL Signal - Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag for CMPSS5.CTRIPH Signal - Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag for CMPSS6.CTRIPL Signal - Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag for CMPSS6.CTRIPH Signal - Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag for CMPSS7.CTRIPL Signal - Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag for CMPSS7.CTRIPH Signal - Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag for CMPSS8.CTRIPL Signal - Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag for CMPSS8.CTRIPH Signal - Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag for CMPSS1.CTRIPOUTL Signal - Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag for CMPSS1.CTRIPOUTH Signal - Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag for CMPSS2.CTRIPOUTL Signal - Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag for CMPSS2.CTRIPOUTH Signal - Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag for CMPSS3.CTRIPOUTL Signal - Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag for CMPSS3.CTRIPOUTH Signal - Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag for CMPSS4.CTRIPOUTL Signal - Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag for CMPSS4.CTRIPOUTH Signal - Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag for CMPSS5.CTRIPOUTL Signal - Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag for CMPSS5.CTRIPOUTH Signal - Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag for CMPSS6.CTRIPOUTL Signal - Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag for CMPSS6.CTRIPOUTH Signal - Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag for CMPSS7.CTRIPOUTL Signal - Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag for CMPSS7.CTRIPOUTH Signal - Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag for CMPSS8.CTRIPOUTL Signal - Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag for CMPSS8.CTRIPOUTH Signal -}; - -union XBARFLG1_REG { - Uint32 all; - struct XBARFLG1_BITS bit; -}; - -struct XBARFLG2_BITS { // bits description - Uint16 INPUT1:1; // 0 Input Flag for INPUT1 Signal - Uint16 INPUT2:1; // 1 Input Flag for INPUT2 Signal - Uint16 INPUT3:1; // 2 Input Flag for INPUT3 Signal - Uint16 INPUT4:1; // 3 Input Flag for INPUT4 Signal - Uint16 INPUT5:1; // 4 Input Flag for INPUT5 Signal - Uint16 INPUT6:1; // 5 Input Flag for INPUT6 Signal - Uint16 ADCSOCAO:1; // 6 Input Flag for ADCSOCAO Signal - Uint16 ADCSOCBO:1; // 7 Input Flag for ADCSOCBO Signal - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:1; // 9 Reserved - Uint16 rsvd3:1; // 10 Reserved - Uint16 rsvd4:1; // 11 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 rsvd6:1; // 13 Reserved - Uint16 rsvd7:1; // 14 Reserved - Uint16 rsvd8:1; // 15 Reserved - Uint16 ECAP1_OUT:1; // 16 Input Flag for ECAP1.OUT Signal - Uint16 ECAP2_OUT:1; // 17 Input Flag for ECAP2.OUT Signal - Uint16 ECAP3_OUT:1; // 18 Input Flag for ECAP3.OUT Signal - Uint16 ECAP4_OUT:1; // 19 Input Flag for ECAP4.OUT Signal - Uint16 ECAP5_OUT:1; // 20 Input Flag for ECAP5.OUT Signal - Uint16 ECAP6_OUT:1; // 21 Input Flag for ECAP6.OUT Signal - Uint16 EXTSYNCOUT:1; // 22 Input Flag for EXTSYNCOUT Signal - Uint16 ADCAEVT1:1; // 23 Input Flag for ADCAEVT1 Signal - Uint16 ADCAEVT2:1; // 24 Input Flag for ADCAEVT2 Signal - Uint16 ADCAEVT3:1; // 25 Input Flag for ADCAEVT3 Signal - Uint16 ADCAEVT4:1; // 26 Input Flag for ADCAEVT4 Signal - Uint16 ADCBEVT1:1; // 27 Input Flag for ADCBEVT1 Signal - Uint16 ADCBEVT2:1; // 28 Input Flag for ADCBEVT2 Signal - Uint16 ADCBEVT3:1; // 29 Input Flag for ADCBEVT3 Signal - Uint16 ADCBEVT4:1; // 30 Input Flag for ADCBEVT4 Signal - Uint16 ADCCEVT1:1; // 31 Input Flag for ADCCEVT1 Signal -}; - -union XBARFLG2_REG { - Uint32 all; - struct XBARFLG2_BITS bit; -}; - -struct XBARFLG3_BITS { // bits description - Uint16 ADCCEVT2:1; // 0 Input Flag for ADCCEVT2 Signal - Uint16 ADCCEVT3:1; // 1 Input Flag for ADCCEVT3 Signal - Uint16 ADCCEVT4:1; // 2 Input Flag for ADCCEVT4 Signal - Uint16 ADCDEVT1:1; // 3 Input Flag for ADCDEVT1 Signal - Uint16 ADCDEVT2:1; // 4 Input Flag for ADCDEVT2 Signal - Uint16 ADCDEVT3:1; // 5 Input Flag for ADCDEVT3 Signal - Uint16 ADCDEVT4:1; // 6 Input Flag for ADCDEVT4 Signal - Uint16 SD1FLT1_COMPL:1; // 7 Input Flag for SD1FLT1.COMPL Signal - Uint16 SD1FLT1_COMPH:1; // 8 Input Flag for SD1FLT1.COMPH Signal - Uint16 SD1FLT2_COMPL:1; // 9 Input Flag for SD1FLT2.COMPL Signal - Uint16 SD1FLT2_COMPH:1; // 10 Input Flag for SD1FLT2.COMPH Signal - Uint16 SD1FLT3_COMPL:1; // 11 Input Flag for SD1FLT3.COMPL Signal - Uint16 SD1FLT3_COMPH:1; // 12 Input Flag for SD1FLT3.COMPH Signal - Uint16 SD1FLT4_COMPL:1; // 13 Input Flag for SD1FLT4.COMPL Signal - Uint16 SD1FLT4_COMPH:1; // 14 Input Flag for SD1FLT4.COMPH Signal - Uint16 SD2FLT1_COMPL:1; // 15 Input Flag for SD2FLT1.COMPL Signal - Uint16 SD2FLT1_COMPH:1; // 16 Input Flag for SD2FLT1.COMPH Signal - Uint16 SD2FLT2_COMPL:1; // 17 Input Flag for SD2FLT2.COMPL Signal - Uint16 SD2FLT2_COMPH:1; // 18 Input Flag for SD2FLT2.COMPH Signal - Uint16 SD2FLT3_COMPL:1; // 19 Input Flag for SD2FLT3.COMPL Signal - Uint16 SD2FLT3_COMPH:1; // 20 Input Flag for SD2FLT3.COMPH Signal - Uint16 SD2FLT4_COMPL:1; // 21 Input Flag for SD2FLT4.COMPL Signal - Uint16 SD2FLT4_COMPH:1; // 22 Input Flag for SD2FLT4.COMPH Signal - Uint16 rsvd1:9; // 31:23 Reserved -}; - -union XBARFLG3_REG { - Uint32 all; - struct XBARFLG3_BITS bit; -}; - -struct XBARCLR1_BITS { // bits description - Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag Clear for CMPSS1.CTRIPL Signal - Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag Clear for CMPSS1.CTRIPH Signal - Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag Clear for CMPSS2.CTRIPL Signal - Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag Clear for CMPSS2.CTRIPH Signal - Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag Clear for CMPSS3.CTRIPL Signal - Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag Clear for CMPSS3.CTRIPH Signal - Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag Clear for CMPSS4.CTRIPL Signal - Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag Clear for CMPSS4.CTRIPH Signal - Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag Clear for CMPSS5.CTRIPL Signal - Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag Clear for CMPSS5.CTRIPH Signal - Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag Clear for CMPSS6.CTRIPL Signal - Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag Clear for CMPSS6.CTRIPH Signal - Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag Clear for CMPSS7.CTRIPL Signal - Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag Clear for CMPSS7.CTRIPH Signal - Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag Clear for CMPSS8.CTRIPL Signal - Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag Clear for CMPSS8.CTRIPH Signal - Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag Clear for CMPSS1.CTRIPOUTL Signal - Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag Clear for CMPSS1.CTRIPOUTH Signal - Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag Clear for CMPSS2.CTRIPOUTL Signal - Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag Clear for CMPSS2.CTRIPOUTH Signal - Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag Clear for CMPSS3.CTRIPOUTL Signal - Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag Clear for CMPSS3.CTRIPOUTH Signal - Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag Clear for CMPSS4.CTRIPOUTL Signal - Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag Clear for CMPSS4.CTRIPOUTH Signal - Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag Clear for CMPSS5.CTRIPOUTL Signal - Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag Clear for CMPSS5.CTRIPOUTH Signal - Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag Clear for CMPSS6.CTRIPOUTL Signal - Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag Clear for CMPSS6.CTRIPOUTH Signal - Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag Clear for CMPSS7.CTRIPOUTL Signal - Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag Clear for CMPSS7.CTRIPOUTH Signal - Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag Clear for CMPSS8.CTRIPOUTL Signal - Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag Clear for CMPSS8.CTRIPOUTH Signal -}; - -union XBARCLR1_REG { - Uint32 all; - struct XBARCLR1_BITS bit; -}; - -struct XBARCLR2_BITS { // bits description - Uint16 INPUT1:1; // 0 Input Flag Clear for INPUT1 Signal - Uint16 INPUT2:1; // 1 Input Flag Clear for INPUT2 Signal - Uint16 INPUT3:1; // 2 Input Flag Clear for INPUT3 Signal - Uint16 INPUT4:1; // 3 Input Flag Clear for INPUT4 Signal - Uint16 INPUT5:1; // 4 Input Flag Clear for INPUT5 Signal - Uint16 INPUT7:1; // 5 Input Flag Clear for INPUT7 Signal - Uint16 ADCSOCAO:1; // 6 Input Flag Clear for ADCSOCAO Signal - Uint16 ADCSOCBO:1; // 7 Input Flag Clear for ADCSOCBO Signal - Uint16 rsvd1:1; // 8 Reserved - Uint16 rsvd2:1; // 9 Reserved - Uint16 rsvd3:1; // 10 Reserved - Uint16 rsvd4:1; // 11 Reserved - Uint16 rsvd5:1; // 12 Reserved - Uint16 rsvd6:1; // 13 Reserved - Uint16 rsvd7:1; // 14 Reserved - Uint16 rsvd8:1; // 15 Reserved - Uint16 ECAP1_OUT:1; // 16 Input Flag Clear for ECAP1.OUT Signal - Uint16 ECAP2_OUT:1; // 17 Input Flag Clear for ECAP2.OUT Signal - Uint16 ECAP3_OUT:1; // 18 Input Flag Clear for ECAP3.OUT Signal - Uint16 ECAP4_OUT:1; // 19 Input Flag Clear for ECAP4.OUT Signal - Uint16 ECAP5_OUT:1; // 20 Input Flag Clear for ECAP5.OUT Signal - Uint16 ECAP6_OUT:1; // 21 Input Flag Clear for ECAP6.OUT Signal - Uint16 EXTSYNCOUT:1; // 22 Input Flag Clear for EXTSYNCOUT Signal - Uint16 ADCAEVT1:1; // 23 Input Flag Clear for ADCAEVT1 Signal - Uint16 ADCAEVT2:1; // 24 Input Flag Clear for ADCAEVT2 Signal - Uint16 ADCAEVT3:1; // 25 Input Flag Clear for ADCAEVT3 Signal - Uint16 ADCAEVT4:1; // 26 Input Flag Clear for ADCAEVT4 Signal - Uint16 ADCBEVT1:1; // 27 Input Flag Clear for ADCBEVT1 Signal - Uint16 ADCBEVT2:1; // 28 Input Flag Clear for ADCBEVT2 Signal - Uint16 ADCBEVT3:1; // 29 Input Flag Clear for ADCBEVT3 Signal - Uint16 ADCBEVT4:1; // 30 Input Flag Clear for ADCBEVT4 Signal - Uint16 ADCCEVT1:1; // 31 Input Flag Clear for ADCCEVT1 Signal -}; - -union XBARCLR2_REG { - Uint32 all; - struct XBARCLR2_BITS bit; -}; - -struct XBARCLR3_BITS { // bits description - Uint16 ADCCEVT2:1; // 0 Input Flag Clear for ADCCEVT2 Signal - Uint16 ADCCEVT3:1; // 1 Input Flag Clear for ADCCEVT3 Signal - Uint16 ADCCEVT4:1; // 2 Input Flag Clear for ADCCEVT4 Signal - Uint16 ADCDEVT1:1; // 3 Input Flag Clear for ADCDEVT1 Signal - Uint16 ADCDEVT2:1; // 4 Input Flag Clear for ADCDEVT2 Signal - Uint16 ADCDEVT3:1; // 5 Input Flag Clear for ADCDEVT3 Signal - Uint16 ADCDEVT4:1; // 6 Input Flag Clear for ADCDEVT4 Signal - Uint16 SD1FLT1_COMPL:1; // 7 Input Flag Clear for SD1FLT1.COMPL Signal - Uint16 SD1FLT1_COMPH:1; // 8 Input Flag Clear for SD1FLT1.COMPH Signal - Uint16 SD1FLT2_COMPL:1; // 9 Input Flag Clear for SD1FLT2.COMPL Signal - Uint16 SD1FLT2_COMPH:1; // 10 Input Flag Clear for SD1FLT2.COMPH Signal - Uint16 SD1FLT3_COMPL:1; // 11 Input Flag Clear for SD1FLT3.COMPL Signal - Uint16 SD1FLT3_COMPH:1; // 12 Input Flag Clear for SD1FLT3.COMPH Signal - Uint16 SD1FLT4_COMPL:1; // 13 Input Flag Clear for SD1FLT4.COMPL Signal - Uint16 SD1FLT4_COMPH:1; // 14 Input Flag Clear for SD1FLT4.COMPH Signal - Uint16 SD2FLT1_COMPL:1; // 15 Input Flag Clear for SD2FLT1.COMPL Signal - Uint16 SD2FLT1_COMPH:1; // 16 Input Flag Clear for SD2FLT1.COMPH Signal - Uint16 SD2FLT2_COMPL:1; // 17 Input Flag Clear for SD2FLT2.COMPL Signal - Uint16 SD2FLT2_COMPH:1; // 18 Input Flag Clear for SD2FLT2.COMPH Signal - Uint16 SD2FLT3_COMPL:1; // 19 Input Flag Clear for SD2FLT3.COMPL Signal - Uint16 SD2FLT3_COMPH:1; // 20 Input Flag Clear for SD2FLT3.COMPH Signal - Uint16 SD2FLT4_COMPL:1; // 21 Input Flag Clear for SD2FLT4.COMPL Signal - Uint16 SD2FLT4_COMPH:1; // 22 Input Flag Clear for SD2FLT4.COMPH Signal - Uint16 rsvd1:9; // 31:23 Reserved -}; - -union XBARCLR3_REG { - Uint32 all; - struct XBARCLR3_BITS bit; -}; - -struct XBAR_REGS { - union XBARFLG1_REG XBARFLG1; // X-Bar Input Flag Register 1 - union XBARFLG2_REG XBARFLG2; // X-Bar Input Flag Register 2 - union XBARFLG3_REG XBARFLG3; // X-Bar Input Flag Register 3 - Uint16 rsvd1[2]; // Reserved - union XBARCLR1_REG XBARCLR1; // X-Bar Input Flag Clear Register 1 - union XBARCLR2_REG XBARCLR2; // X-Bar Input Flag Clear Register 2 - union XBARCLR3_REG XBARCLR3; // X-Bar Input Flag Clear Register 3 - Uint16 rsvd2[18]; // Reserved -}; - -//--------------------------------------------------------------------------- -// XBAR External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct XBAR_REGS XbarRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_xint.h b/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_xint.h deleted file mode 100644 index f647e68b06..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/include/F2837xD_xint.h +++ /dev/null @@ -1,143 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_xint.h -// -// TITLE: XINT Register Definitions. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#ifndef __F2837xD_XINT_H__ -#define __F2837xD_XINT_H__ - -#ifdef __cplusplus -extern "C" { -#endif - - -//--------------------------------------------------------------------------- -// XINT Individual Register Bit Definitions: - -struct XINT1CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT1 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT1 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT1CR_REG { - Uint16 all; - struct XINT1CR_BITS bit; -}; - -struct XINT2CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT2 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT2 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT2CR_REG { - Uint16 all; - struct XINT2CR_BITS bit; -}; - -struct XINT3CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT3 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT3 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT3CR_REG { - Uint16 all; - struct XINT3CR_BITS bit; -}; - -struct XINT4CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT4 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT4 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT4CR_REG { - Uint16 all; - struct XINT4CR_BITS bit; -}; - -struct XINT5CR_BITS { // bits description - Uint16 ENABLE:1; // 0 XINT5 Enable - Uint16 rsvd1:1; // 1 Reserved - Uint16 POLARITY:2; // 3:2 XINT5 Polarity - Uint16 rsvd2:12; // 15:4 Reserved -}; - -union XINT5CR_REG { - Uint16 all; - struct XINT5CR_BITS bit; -}; - -struct XINT_REGS { - union XINT1CR_REG XINT1CR; // XINT1 configuration register - union XINT2CR_REG XINT2CR; // XINT2 configuration register - union XINT3CR_REG XINT3CR; // XINT3 configuration register - union XINT4CR_REG XINT4CR; // XINT4 configuration register - union XINT5CR_REG XINT5CR; // XINT5 configuration register - Uint16 rsvd1[3]; // Reserved - Uint16 XINT1CTR; // XINT1 counter register - Uint16 XINT2CTR; // XINT2 counter register - Uint16 XINT3CTR; // XINT3 counter register -}; - -//--------------------------------------------------------------------------- -// XINT External References & Function Declarations: -// -#ifdef CPU1 -extern volatile struct XINT_REGS XintRegs; -#endif -#ifdef CPU2 -extern volatile struct XINT_REGS XintRegs; -#endif -#ifdef __cplusplus -} -#endif /* extern "C" */ - -#endif - -//=========================================================================== -// End of file. -//=========================================================================== diff --git a/bsp/c28x/libraries/tms320f28379d/headers/source/F2837xD_GlobalVariableDefs.c b/bsp/c28x/libraries/tms320f28379d/headers/source/F2837xD_GlobalVariableDefs.c deleted file mode 100644 index 270b63815a..0000000000 --- a/bsp/c28x/libraries/tms320f28379d/headers/source/F2837xD_GlobalVariableDefs.c +++ /dev/null @@ -1,876 +0,0 @@ -//########################################################################### -// -// FILE: F2837xD_GlobalVariableDefs.c -// -// TITLE: F2837xD Global Variables and Data Section Pragmas. -// -//########################################################################### -// $TI Release: F2837xD Support Library v3.05.00.00 $ -// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ -// $Copyright: -// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions -// are met: -// -// Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// -// Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the -// distribution. -// -// Neither the name of Texas Instruments Incorporated nor the names of -// its contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// $ -//########################################################################### - -#include "F2837xD_device.h" // F2837xD Headerfile Include File - -//--------------------------------------------------------------------------- -// Define Global Peripheral Variables: -// -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdcaRegsFile") -#else -#pragma DATA_SECTION(AdcaRegs,"AdcaRegsFile"); -#endif -volatile struct ADC_REGS AdcaRegs; - -#ifdef __cplusplus -#pragma DATA_SECTION("AdcbRegsFile") -#else -#pragma DATA_SECTION(AdcbRegs,"AdcbRegsFile"); -#endif -volatile struct ADC_REGS AdcbRegs; - -#ifdef __cplusplus -#pragma DATA_SECTION("AdccRegsFile") -#else -#pragma DATA_SECTION(AdccRegs,"AdccRegsFile"); -#endif -volatile struct ADC_REGS AdccRegs; - -#ifdef __cplusplus -#pragma DATA_SECTION("AdcdRegsFile") -#else -#pragma DATA_SECTION(AdcdRegs,"AdcdRegsFile"); -#endif -volatile struct ADC_REGS AdcdRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdcaResultFile") -#else -#pragma DATA_SECTION(AdcaResultRegs,"AdcaResultFile"); -#endif -volatile struct ADC_RESULT_REGS AdcaResultRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdcbResultFile") -#else -#pragma DATA_SECTION(AdcbResultRegs,"AdcbResultFile"); -#endif -volatile struct ADC_RESULT_REGS AdcbResultRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdccResultFile") -#else -#pragma DATA_SECTION(AdccResultRegs,"AdccResultFile"); -#endif -volatile struct ADC_RESULT_REGS AdccResultRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AdcdResultFile") -#else -#pragma DATA_SECTION(AdcdResultRegs,"AdcdResultFile"); -#endif -volatile struct ADC_RESULT_REGS AdcdResultRegs; - -//---------------------------------------- -#ifdef CPU1 -#ifdef __cplusplus -#pragma DATA_SECTION("AnalogSubsysRegsFile") -#else -#pragma DATA_SECTION(AnalogSubsysRegs,"AnalogSubsysRegsFile"); -#endif -volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; -#endif - -#if __TI_COMPILER_VERSION__ >= 16006000 -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CanaRegsFile") -#else -#pragma DATA_SECTION(CanaRegs,"CanaRegsFile"); -#endif -volatile struct CAN_REGS CanaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CanbRegsFile") -#else -#pragma DATA_SECTION(CanbRegs,"CanbRegsFile"); -#endif -volatile struct CAN_REGS CanbRegs; -#endif - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss1RegsFile") -#else -#pragma DATA_SECTION(Cmpss1Regs,"Cmpss1RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss2RegsFile") -#else -#pragma DATA_SECTION(Cmpss2Regs,"Cmpss2RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss3RegsFile") -#else -#pragma DATA_SECTION(Cmpss3Regs,"Cmpss3RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss4RegsFile") -#else -#pragma DATA_SECTION(Cmpss4Regs,"Cmpss4RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss5RegsFile") -#else -#pragma DATA_SECTION(Cmpss5Regs,"Cmpss5RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss6RegsFile") -#else -#pragma DATA_SECTION(Cmpss6Regs,"Cmpss6RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss7RegsFile") -#else -#pragma DATA_SECTION(Cmpss7Regs,"Cmpss7RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cmpss8RegsFile") -#else -#pragma DATA_SECTION(Cmpss8Regs,"Cmpss8RegsFile"); -#endif -volatile struct CMPSS_REGS Cmpss8Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DacaRegsFile") -#else -#pragma DATA_SECTION(DacaRegs,"DacaRegsFile"); -#endif -volatile struct DAC_REGS DacaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DacbRegsFile") -#else -#pragma DATA_SECTION(DacbRegs,"DacbRegsFile"); -#endif -volatile struct DAC_REGS DacbRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DaccRegsFile") -#else -#pragma DATA_SECTION(DaccRegs,"DaccRegsFile"); -#endif -volatile struct DAC_REGS DaccRegs; -//---------------------------------------- - -#ifdef __cplusplus -#pragma DATA_SECTION("Cla1RegsFile") -#else -#pragma DATA_SECTION(Cla1Regs,"Cla1RegsFile"); -#endif -volatile struct CLA_REGS Cla1Regs; -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Cla1SoftIntRegsFile") -#else -#pragma DATA_SECTION(Cla1SoftIntRegs,"Cla1SoftIntRegsFile"); -#endif -volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ClkCfgRegsFile") -#else -#pragma DATA_SECTION(ClkCfgRegs,"ClkCfgRegsFile"); -#endif -volatile struct CLK_CFG_REGS ClkCfgRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CpuSysRegsFile") -#else -#pragma DATA_SECTION(CpuSysRegs,"CpuSysRegsFile"); -#endif -volatile struct CPU_SYS_REGS CpuSysRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CpuTimer0RegsFile") -#else -#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); -#endif -volatile struct CPUTIMER_REGS CpuTimer0Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CpuTimer1RegsFile") -#else -#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); -#endif -volatile struct CPUTIMER_REGS CpuTimer1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("CpuTimer2RegsFile") -#else -#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); -#endif -volatile struct CPUTIMER_REGS CpuTimer2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmZ1RegsFile") -#else -#pragma DATA_SECTION(DcsmZ1Regs,"DcsmZ1RegsFile"); -#endif -volatile struct DCSM_Z1_REGS DcsmZ1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmZ2RegsFile") -#else -#pragma DATA_SECTION(DcsmZ2Regs,"DcsmZ2RegsFile"); -#endif -volatile struct DCSM_Z2_REGS DcsmZ2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DcsmCommonRegsFile") -#else -#pragma DATA_SECTION(DcsmCommonRegs,"DcsmCommonRegsFile"); -#endif -volatile struct DCSM_COMMON_REGS DcsmCommonRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DmaRegsFile") -#else -#pragma DATA_SECTION(DmaRegs,"DmaRegsFile"); -#endif -volatile struct DMA_REGS DmaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("DmaClaSrcSelRegsFile") -#else -#pragma DATA_SECTION(DmaClaSrcSelRegs,"DmaClaSrcSelRegsFile"); -#endif -volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; - -//---------------------------------------- -#ifdef CPU1 -#ifdef __cplusplus -#pragma DATA_SECTION("DevCfgRegsFile") -#else -#pragma DATA_SECTION(DevCfgRegs,"DevCfgRegsFile"); -#endif -volatile struct DEV_CFG_REGS DevCfgRegs; -#endif - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap1RegsFile") -#else -#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile"); -#endif -volatile struct ECAP_REGS ECap1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap2RegsFile") -#else -#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile"); -#endif -volatile struct ECAP_REGS ECap2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap3RegsFile") -#else -#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile"); -#endif -volatile struct ECAP_REGS ECap3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap4RegsFile") -#else -#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile"); -#endif -volatile struct ECAP_REGS ECap4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap5RegsFile") -#else -#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile"); -#endif -volatile struct ECAP_REGS ECap5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ECap6RegsFile") -#else -#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile"); -#endif -volatile struct ECAP_REGS ECap6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Emif1RegsFile") -#else -#pragma DATA_SECTION(Emif1Regs,"Emif1RegsFile"); -#endif -volatile struct EMIF_REGS Emif1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Emif2RegsFile") -#else -#pragma DATA_SECTION(Emif2Regs,"Emif2RegsFile"); -#endif -volatile struct EMIF_REGS Emif2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EQep1RegsFile") -#else -#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile"); -#endif -volatile struct EQEP_REGS EQep1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EQep2RegsFile") -#else -#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile"); -#endif -volatile struct EQEP_REGS EQep2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EQep3RegsFile") -#else -#pragma DATA_SECTION(EQep3Regs,"EQep3RegsFile"); -#endif -volatile struct EQEP_REGS EQep3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm1RegsFile") -#else -#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile"); -#endif -volatile struct EPWM_REGS EPwm1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm2RegsFile") -#else -#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile"); -#endif -volatile struct EPWM_REGS EPwm2Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm3RegsFile") -#else -#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile"); -#endif -volatile struct EPWM_REGS EPwm3Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm4RegsFile") -#else -#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile"); -#endif -volatile struct EPWM_REGS EPwm4Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm5RegsFile") -#else -#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile"); -#endif -volatile struct EPWM_REGS EPwm5Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm6RegsFile") -#else -#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile"); -#endif -volatile struct EPWM_REGS EPwm6Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm7RegsFile") -#else -#pragma DATA_SECTION(EPwm7Regs,"EPwm7RegsFile"); -#endif -volatile struct EPWM_REGS EPwm7Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm8RegsFile") -#else -#pragma DATA_SECTION(EPwm8Regs,"EPwm8RegsFile"); -#endif -volatile struct EPWM_REGS EPwm8Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm9RegsFile") -#else -#pragma DATA_SECTION(EPwm9Regs,"EPwm9RegsFile"); -#endif -volatile struct EPWM_REGS EPwm9Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm10RegsFile") -#else -#pragma DATA_SECTION(EPwm10Regs,"EPwm10RegsFile"); -#endif -volatile struct EPWM_REGS EPwm10Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm11RegsFile") -#else -#pragma DATA_SECTION(EPwm11Regs,"EPwm11RegsFile"); -#endif -volatile struct EPWM_REGS EPwm11Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EPwm12RegsFile") -#else -#pragma DATA_SECTION(EPwm12Regs,"EPwm12RegsFile"); -#endif -volatile struct EPWM_REGS EPwm12Regs; - -//---------------------------------------- -#ifdef CPU1 -#ifdef __cplusplus -#pragma DATA_SECTION("EPwmXbarRegsFile") -#else -#pragma DATA_SECTION(EPwmXbarRegs,"EPwmXbarRegsFile"); -#endif -volatile struct EPWM_XBAR_REGS EPwmXbarRegs; -#endif - -//---------------------------------------- -#ifdef CPU1 -#ifdef __cplusplus -#pragma DATA_SECTION("GpioCtrlRegsFile") -#else -#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile"); -#endif -volatile struct GPIO_CTRL_REGS GpioCtrlRegs; -#endif - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("GpioDataRegsFile") -#else -#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); -#endif -volatile struct GPIO_DATA_REGS GpioDataRegs; - -//---------------------------------------- -#ifdef CPU1 -#ifdef __cplusplus -#pragma DATA_SECTION("InputXbarRegsFile") -#else -#pragma DATA_SECTION(InputXbarRegs,"InputXbarRegsFile"); -#endif -volatile struct INPUT_XBAR_REGS InputXbarRegs; -#endif - -//---------------------------------------- -#ifdef CPU1 -#ifdef __cplusplus -#pragma DATA_SECTION("XbarRegsFile") -#else -#pragma DATA_SECTION(XbarRegs,"XbarRegsFile"); -#endif -volatile struct XBAR_REGS XbarRegs; -#endif - -//---------------------------------------- -#ifdef CPU1 -#ifdef __cplusplus -#pragma DATA_SECTION("OutputXbarRegsFile") -#else -#pragma DATA_SECTION(OutputXbarRegs,"OutputXbarRegsFile"); -#endif -volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; -#endif - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("I2caRegsFile") -#else -#pragma DATA_SECTION(I2caRegs,"I2caRegsFile"); -#endif -volatile struct I2C_REGS I2caRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("I2cbRegsFile") -#else -#pragma DATA_SECTION(I2cbRegs,"I2cbRegsFile"); -#endif -volatile struct I2C_REGS I2cbRegs; - -//---------------------------------------- -#ifdef CPU1 -#ifdef __cplusplus -#pragma DATA_SECTION("IpcRegsFile") -#else -#pragma DATA_SECTION(IpcRegs,"IpcRegsFile"); -#endif -volatile struct IPC_REGS_CPU1 IpcRegs; -#endif - -//---------------------------------------- -#ifdef CPU2 -#ifdef __cplusplus -#pragma DATA_SECTION("IpcRegsFile") -#else -#pragma DATA_SECTION(IpcRegs,"IpcRegsFile"); -#endif -volatile struct IPC_REGS_CPU2 IpcRegs; -#endif - -//---------------------------------------- -#ifdef CPU1 -#ifdef __cplusplus -#pragma DATA_SECTION("FlashPumpSemaphoreRegsFile") -#else -#pragma DATA_SECTION(FlashPumpSemaphoreRegs,"FlashPumpSemaphoreRegsFile"); -#endif -volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; -#endif - -//---------------------------------------- -#ifdef CPU2 -#ifdef __cplusplus -#pragma DATA_SECTION("FlashPumpSemaphoreRegsFile") -#else -#pragma DATA_SECTION(FlashPumpSemaphoreRegs,"FlashPumpSemaphoreRegsFile"); -#endif -volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; -#endif - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("McbspaRegsFile") -#else -#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile"); -#endif -volatile struct McBSP_REGS McbspaRegs; - -//---------------------------------------- -#ifdef CPU1 -#ifdef __cplusplus -#pragma DATA_SECTION("RomPrefetchRegsFile") -#else -#pragma DATA_SECTION(RomPrefetchRegs,"RomPrefetchRegsFile"); -#endif -volatile struct ROM_PREFETCH_REGS RomPrefetchRegs; -#endif - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("MemCfgRegsFile") -#else -#pragma DATA_SECTION(MemCfgRegs,"MemCfgRegsFile"); -#endif -volatile struct MEM_CFG_REGS MemCfgRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Emif1ConfigRegsFile") -#else -#pragma DATA_SECTION(Emif1ConfigRegs,"Emif1ConfigRegsFile"); -#endif -volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; - -//---------------------------------------- -#ifdef CPU1 -#ifdef __cplusplus -#pragma DATA_SECTION("Emif2ConfigRegsFile") -#else -#pragma DATA_SECTION(Emif2ConfigRegs,"Emif2ConfigRegsFile"); -#endif -volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs; -#endif - -//---------------------------------------- -#ifdef CPU1 -#ifdef __cplusplus -#pragma DATA_SECTION("RomWaitStateRegsFile") -#else -#pragma DATA_SECTION(RomWaitStateRegs,"RomWaitStateRegsFile"); -#endif -volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs; -#endif - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("AccessProtectionRegsFile") -#else -#pragma DATA_SECTION(AccessProtectionRegs,"AccessProtectionRegsFile"); -#endif -volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("MemoryErrorRegsFile") -#else -#pragma DATA_SECTION(MemoryErrorRegs,"MemoryErrorRegsFile"); -#endif -volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("McbspbRegsFile") -#else -#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile"); -#endif -volatile struct McBSP_REGS McbspbRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("NmiIntruptRegsFile") -#else -#pragma DATA_SECTION(NmiIntruptRegs,"NmiIntruptRegsFile"); -#endif -volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("PieCtrlRegsFile") -#else -#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); -#endif -volatile struct PIE_CTRL_REGS PieCtrlRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("PieVectTableFile") -#else -#pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); -#endif -volatile struct PIE_VECT_TABLE PieVectTable; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SciaRegsFile") -#else -#pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); -#endif -volatile struct SCI_REGS SciaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ScibRegsFile") -#else -#pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); -#endif -volatile struct SCI_REGS ScibRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ScicRegsFile") -#else -#pragma DATA_SECTION(ScicRegs,"ScicRegsFile"); -#endif -volatile struct SCI_REGS ScicRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("ScidRegsFile") -#else -#pragma DATA_SECTION(ScidRegs,"ScidRegsFile"); -#endif -volatile struct SCI_REGS ScidRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SpiaRegsFile") -#else -#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); -#endif -volatile struct SPI_REGS SpiaRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SpibRegsFile") -#else -#pragma DATA_SECTION(SpibRegs,"SpibRegsFile"); -#endif -volatile struct SPI_REGS SpibRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("SpicRegsFile") -#else -#pragma DATA_SECTION(SpicRegs,"SpicRegsFile"); -#endif -volatile struct SPI_REGS SpicRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Sdfm1RegsFile") -#else -#pragma DATA_SECTION(Sdfm1Regs,"Sdfm1RegsFile"); -#endif -volatile struct SDFM_REGS Sdfm1Regs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Sdfm2RegsFile") -#else -#pragma DATA_SECTION(Sdfm2Regs,"Sdfm2RegsFile"); -#endif -volatile struct SDFM_REGS Sdfm2Regs; - - -//---------------------------------------- -#ifdef CPU1 -#ifdef __cplusplus -#pragma DATA_SECTION("SyncSocRegsFile") -#else -#pragma DATA_SECTION(SyncSocRegs,"SyncSocRegsFile"); -#endif -volatile struct SYNC_SOC_REGS SyncSocRegs; -#endif - -//---------------------------------------- -#if defined(CPU1) -#ifdef __cplusplus -#pragma DATA_SECTION("UppRegsFile") -#else -#pragma DATA_SECTION(UppRegs,"UppRegsFile"); -#endif -volatile struct UPP_REGS UppRegs; -#endif //defined(CPU1) - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("WdRegsFile") -#else -#pragma DATA_SECTION(WdRegs,"WdRegsFile"); -#endif -volatile struct WD_REGS WdRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("XintRegsFile") -#else -#pragma DATA_SECTION(XintRegs,"XintRegsFile"); -#endif -volatile struct XINT_REGS XintRegs; - -//-------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("EmuBModeVar"); -#else -#pragma DATA_SECTION(EmuBMode,"EmuBModeVar"); -#endif -Uint16 EmuBMode; - -//---------------------------------------- -#ifdef CPU1 -#ifdef __cplusplus -#pragma DATA_SECTION("EmuBootPinsVar"); -#else -#pragma DATA_SECTION(EmuBootPins,"EmuBootPinsVar"); -#endif -Uint16 EmuBootPins; -#endif - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Flash0EccRegsFile") -#else -#pragma DATA_SECTION(Flash0EccRegs,"Flash0EccRegsFile"); -#endif -volatile struct FLASH_ECC_REGS Flash0EccRegs; - -//---------------------------------------- -#ifdef __cplusplus -#pragma DATA_SECTION("Flash0CtrlRegsFile") -#else -#pragma DATA_SECTION(Flash0CtrlRegs,"Flash0CtrlRegsFile"); -#endif -volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; - - -//=========================================================================== -// End of file. -//=========================================================================== - diff --git a/bsp/c28x/tms320f28379d/.ccsproject b/bsp/c28x/tms320f28379d/.ccsproject deleted file mode 100644 index 028ef9f5ea..0000000000 --- a/bsp/c28x/tms320f28379d/.ccsproject +++ /dev/null @@ -1,17 +0,0 @@ - - - - - - - - - - - - - - - - - diff --git a/bsp/c28x/tms320f28379d/.config b/bsp/c28x/tms320f28379d/.config deleted file mode 100644 index 15627f816e..0000000000 --- a/bsp/c28x/tms320f28379d/.config +++ /dev/null @@ -1,684 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# -CONFIG_SOC_TMS320F28X=y - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=8 -# CONFIG_RT_USING_ARCH_DATA_TYPE is not set -# CONFIG_RT_USING_SMP is not set -CONFIG_RT_ALIGN_SIZE=4 -CONFIG_RT_THREAD_PRIORITY_8=y -# CONFIG_RT_THREAD_PRIORITY_32 is not set -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=8 -CONFIG_RT_TICK_PER_SECOND=100 -# CONFIG_RT_USING_OVERFLOW_CHECK is not set -CONFIG_RT_USING_HOOK=y -CONFIG_RT_HOOK_USING_FUNC_PTR=y -CONFIG_RT_USING_IDLE_HOOK=y -CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=1024 -# CONFIG_RT_USING_TIMER_SOFT is not set - -# -# kservice optimization -# -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set -# CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMHEAP is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y -# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set -# CONFIG_RT_USING_USERHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -# CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -# CONFIG_RT_USING_INTERRUPT_INFO is not set -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="scia" -CONFIG_RT_VER_NUM=0x50000 -# CONFIG_RT_USING_CPU_FFS is not set -CONFIG_ARCH_TIDSP=y -CONFIG_ARCH_TIDSP_C28X=y -CONFIG_ARCH_CPU_STACK_GROWS_UPWARD=y - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=4 -# CONFIG_RT_USING_LEGACY is not set -CONFIG_RT_USING_MSH=y -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_THREAD_PRIORITY=4 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_CMD_SIZE=80 -CONFIG_MSH_USING_BUILT_IN_COMMANDS=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_ARG_MAX=10 -# CONFIG_RT_USING_DFS is not set -# CONFIG_RT_USING_FAL is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set -CONFIG_RT_USING_SERIAL=y -CONFIG_RT_USING_SERIAL_V1=y -# CONFIG_RT_USING_SERIAL_V2 is not set -# CONFIG_RT_SERIAL_USING_DMA is not set -CONFIG_RT_SERIAL_RB_BUFSZ=64 -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set -# CONFIG_RT_USING_PHY is not set -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_ADC is not set -# CONFIG_RT_USING_DAC is not set -CONFIG_RT_USING_PWM=y -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_PM is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_AUDIO is not set -# CONFIG_RT_USING_SENSOR is not set -# CONFIG_RT_USING_TOUCH is not set -# CONFIG_RT_USING_HWCRYPTO is not set -# CONFIG_RT_USING_PULSE_ENCODER is not set -# CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_WIFI is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# C/C++ and POSIX layer -# -CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 - -# -# POSIX (Portable Operating System Interface) layer -# -# CONFIG_RT_USING_POSIX_FS is not set -# CONFIG_RT_USING_POSIX_DELAY is not set -# CONFIG_RT_USING_POSIX_CLOCK is not set -# CONFIG_RT_USING_POSIX_TIMER is not set -# CONFIG_RT_USING_PTHREADS is not set -# CONFIG_RT_USING_MODULE is not set - -# -# Interprocess Communication (IPC) -# -# CONFIG_RT_USING_POSIX_PIPE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set -# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set - -# -# Socket is in the 'Network' category -# -# CONFIG_RT_USING_CPLUSPLUS is not set - -# -# Network -# -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set -# CONFIG_RT_USING_AT is not set - -# -# Utilities -# -# CONFIG_RT_USING_RYM is not set -# CONFIG_RT_USING_ULOG is not set -# CONFIG_RT_USING_UTEST is not set -# CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_RT_LINK is not set -# CONFIG_RT_USING_VBUS is not set - -# -# RT-Thread Utestcases -# -# CONFIG_RT_USING_UTESTCASES is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_LWIP is not set -# CONFIG_PKG_USING_LORAWAN_DRIVER is not set -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_UMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_WEBNET is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_MYMQTT is not set -# CONFIG_PKG_USING_KAWAII_MQTT is not set -# CONFIG_PKG_USING_BC28_MQTT is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set -# CONFIG_PKG_USING_FREEMODBUS is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_RW007 is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_CMUX is not set -# CONFIG_PKG_USING_PPP_DEVICE is not set -# CONFIG_PKG_USING_AT_DEVICE is not set -# CONFIG_PKG_USING_ATSRV_SOCKET is not set -# CONFIG_PKG_USING_WIZNET is not set -# CONFIG_PKG_USING_ZB_COORDINATOR is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set -# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set -# CONFIG_PKG_USING_JIOT-C-SDK is not set -# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set -# CONFIG_PKG_USING_JOYLINK is not set -# CONFIG_PKG_USING_EZ_IOT_OS is not set -# CONFIG_PKG_USING_IOTSHARP_SDK is not set -# CONFIG_PKG_USING_NIMBLE is not set -# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set -# CONFIG_PKG_USING_OTA_DOWNLOADER is not set -# CONFIG_PKG_USING_IPMSG is not set -# CONFIG_PKG_USING_LSSDP is not set -# CONFIG_PKG_USING_AIRKISS_OPEN is not set -# CONFIG_PKG_USING_LIBRWS is not set -# CONFIG_PKG_USING_TCPSERVER is not set -# CONFIG_PKG_USING_PROTOBUF_C is not set -# CONFIG_PKG_USING_DLT645 is not set -# CONFIG_PKG_USING_QXWZ is not set -# CONFIG_PKG_USING_SMTP_CLIENT is not set -# CONFIG_PKG_USING_ABUP_FOTA is not set -# CONFIG_PKG_USING_LIBCURL2RTT is not set -# CONFIG_PKG_USING_CAPNP is not set -# CONFIG_PKG_USING_AGILE_TELNET is not set -# CONFIG_PKG_USING_NMEALIB is not set -# CONFIG_PKG_USING_PDULIB is not set -# CONFIG_PKG_USING_BTSTACK is not set -# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set -# CONFIG_PKG_USING_WAYZ_IOTKIT is not set -# CONFIG_PKG_USING_MAVLINK is not set -# CONFIG_PKG_USING_BSAL is not set -# CONFIG_PKG_USING_AGILE_MODBUS is not set -# CONFIG_PKG_USING_AGILE_FTP is not set -# CONFIG_PKG_USING_EMBEDDEDPROTO is not set -# CONFIG_PKG_USING_RT_LINK_HW is not set -# CONFIG_PKG_USING_LORA_PKT_FWD is not set -# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set -# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set -# CONFIG_PKG_USING_HM is not set -# CONFIG_PKG_USING_SMALL_MODBUS is not set -# CONFIG_PKG_USING_NET_SERVER is not set -# CONFIG_PKG_USING_ZFTP is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_LIBSODIUM is not set -# CONFIG_PKG_USING_LIBHYDROGEN is not set -# CONFIG_PKG_USING_TINYCRYPT is not set -# CONFIG_PKG_USING_TFM is not set -# CONFIG_PKG_USING_YD_CRYPTO is not set - -# -# language packages -# - -# -# JSON: JavaScript Object Notation, a lightweight data-interchange format -# -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set -# CONFIG_PKG_USING_RAPIDJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_AGILE_JSMN is not set -# CONFIG_PKG_USING_PARSON is not set - -# -# XML: Extensible Markup Language -# -# CONFIG_PKG_USING_SIMPLE_XML is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_LUATOS_SOC is not set -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set -# CONFIG_PKG_USING_PIKASCRIPT is not set -# CONFIG_PKG_USING_RTT_RUST is not set - -# -# multimedia packages -# - -# -# LVGL: powerful and easy-to-use embedded GUI library -# -# CONFIG_PKG_USING_LVGL is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set -# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set -# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set - -# -# u8g2: a monochrome graphic library -# -# CONFIG_PKG_USING_U8G2_OFFICIAL is not set -# CONFIG_PKG_USING_U8G2 is not set -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set -# CONFIG_PKG_USING_STEMWIN is not set -# CONFIG_PKG_USING_WAVPLAYER is not set -# CONFIG_PKG_USING_TJPGD is not set -# CONFIG_PKG_USING_PDFGEN is not set -# CONFIG_PKG_USING_HELIX is not set -# CONFIG_PKG_USING_AZUREGUIX is not set -# CONFIG_PKG_USING_TOUCHGFX2RTT is not set -# CONFIG_PKG_USING_NUEMWIN is not set -# CONFIG_PKG_USING_MP3PLAYER is not set -# CONFIG_PKG_USING_TINYJPEG is not set -# CONFIG_PKG_USING_UGUI is not set - -# -# PainterEngine: A cross-platform graphics application framework written in C language -# -# CONFIG_PKG_USING_PAINTERENGINE is not set -# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set -# CONFIG_PKG_USING_MCURSES is not set -# CONFIG_PKG_USING_TERMBOX is not set -# CONFIG_PKG_USING_VT100 is not set -# CONFIG_PKG_USING_QRCODE is not set -# CONFIG_PKG_USING_GUIENGINE is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set -# CONFIG_PKG_USING_SEGGER_RTT is not set -# CONFIG_PKG_USING_RDB is not set -# CONFIG_PKG_USING_ULOG_EASYFLASH is not set -# CONFIG_PKG_USING_ULOG_FILE is not set -# CONFIG_PKG_USING_LOGMGR is not set -# CONFIG_PKG_USING_ADBD is not set -# CONFIG_PKG_USING_COREMARK is not set -# CONFIG_PKG_USING_DHRYSTONE is not set -# CONFIG_PKG_USING_MEMORYPERF is not set -# CONFIG_PKG_USING_NR_MICRO_SHELL is not set -# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set -# CONFIG_PKG_USING_LUNAR_CALENDAR is not set -# CONFIG_PKG_USING_BS8116A is not set -# CONFIG_PKG_USING_GPS_RMC is not set -# CONFIG_PKG_USING_URLENCODE is not set -# CONFIG_PKG_USING_UMCN is not set -# CONFIG_PKG_USING_LWRB2RTT is not set -# CONFIG_PKG_USING_CPU_USAGE is not set -# CONFIG_PKG_USING_GBK2UTF8 is not set -# CONFIG_PKG_USING_VCONSOLE is not set -# CONFIG_PKG_USING_KDB is not set -# CONFIG_PKG_USING_WAMR is not set -# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set -# CONFIG_PKG_USING_LWLOG is not set -# CONFIG_PKG_USING_ANV_TRACE is not set -# CONFIG_PKG_USING_ANV_MEMLEAK is not set -# CONFIG_PKG_USING_ANV_TESTSUIT is not set -# CONFIG_PKG_USING_ANV_BENCH is not set -# CONFIG_PKG_USING_DEVMEM is not set -# CONFIG_PKG_USING_REGEX is not set -# CONFIG_PKG_USING_MEM_SANDBOX is not set -# CONFIG_PKG_USING_SOLAR_TERMS is not set -# CONFIG_PKG_USING_GAN_ZHI is not set -# CONFIG_PKG_USING_FDT is not set -# CONFIG_PKG_USING_CBOX is not set -# CONFIG_PKG_USING_SNOWFLAKE is not set -# CONFIG_PKG_USING_HASH_MATCH is not set -# CONFIG_PKG_USING_FIRE_PID_CURVE is not set -# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set - -# -# system packages -# - -# -# enhanced kernel services -# -# CONFIG_PKG_USING_RT_MEMCPY_CM is not set -# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set -# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set - -# -# acceleration: Assembly language or algorithmic acceleration packages -# -# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set -# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set -# CONFIG_PKG_USING_QFPLIB_M3 is not set - -# -# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard -# -# CONFIG_PKG_USING_CMSIS_5 is not set -# CONFIG_PKG_USING_CMSIS_RTOS1 is not set -# CONFIG_PKG_USING_CMSIS_RTOS2 is not set - -# -# Micrium: Micrium software products porting for RT-Thread -# -# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set -# CONFIG_PKG_USING_UCOSII_WRAPPER is not set -# CONFIG_PKG_USING_UC_CRC is not set -# CONFIG_PKG_USING_UC_CLK is not set -# CONFIG_PKG_USING_UC_COMMON is not set -# CONFIG_PKG_USING_UC_MODBUS is not set -# CONFIG_PKG_USING_RTDUINO is not set -# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_PERF_COUNTER is not set -# CONFIG_PKG_USING_FLASHDB is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_DFS_YAFFS is not set -# CONFIG_PKG_USING_LITTLEFS is not set -# CONFIG_PKG_USING_DFS_JFFS2 is not set -# CONFIG_PKG_USING_DFS_UFFS is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_THREAD_POOL is not set -# CONFIG_PKG_USING_ROBOTS is not set -# CONFIG_PKG_USING_EV is not set -# CONFIG_PKG_USING_SYSWATCH is not set -# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set -# CONFIG_PKG_USING_PLCCORE is not set -# CONFIG_PKG_USING_RAMDISK is not set -# CONFIG_PKG_USING_MININI is not set -# CONFIG_PKG_USING_QBOOT is not set -# CONFIG_PKG_USING_PPOOL is not set -# CONFIG_PKG_USING_OPENAMP is not set -# CONFIG_PKG_USING_LPM is not set -# CONFIG_PKG_USING_TLSF is not set -# CONFIG_PKG_USING_EVENT_RECORDER is not set -# CONFIG_PKG_USING_ARM_2D is not set -# CONFIG_PKG_USING_MCUBOOT is not set -# CONFIG_PKG_USING_TINYUSB is not set -# CONFIG_PKG_USING_CHERRYUSB is not set -# CONFIG_PKG_USING_KMULTI_RTIMER is not set -# CONFIG_PKG_USING_TFDB is not set -# CONFIG_PKG_USING_QPC is not set - -# -# peripheral libraries and drivers -# -# CONFIG_PKG_USING_SENSORS_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_SHT3X is not set -# CONFIG_PKG_USING_ADT74XX is not set -# CONFIG_PKG_USING_AS7341 is not set -# CONFIG_PKG_USING_STM32_SDIO is not set -# CONFIG_PKG_USING_RTT_ESP_IDF is not set -# CONFIG_PKG_USING_ICM20608 is not set -# CONFIG_PKG_USING_BUTTON is not set -# CONFIG_PKG_USING_PCF8574 is not set -# CONFIG_PKG_USING_SX12XX is not set -# CONFIG_PKG_USING_SIGNAL_LED is not set -# CONFIG_PKG_USING_LEDBLINK is not set -# CONFIG_PKG_USING_LITTLED is not set -# CONFIG_PKG_USING_LKDGUI is not set -# CONFIG_PKG_USING_NRF5X_SDK is not set -# CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set - -# -# Kendryte SDK -# -# CONFIG_PKG_USING_K210_SDK is not set -# CONFIG_PKG_USING_KENDRYTE_SDK is not set -# CONFIG_PKG_USING_INFRARED is not set -# CONFIG_PKG_USING_MULTI_INFRARED is not set -# CONFIG_PKG_USING_AGILE_BUTTON is not set -# CONFIG_PKG_USING_AGILE_LED is not set -# CONFIG_PKG_USING_AT24CXX is not set -# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set -# CONFIG_PKG_USING_AD7746 is not set -# CONFIG_PKG_USING_PCA9685 is not set -# CONFIG_PKG_USING_I2C_TOOLS is not set -# CONFIG_PKG_USING_NRF24L01 is not set -# CONFIG_PKG_USING_TOUCH_DRIVERS is not set -# CONFIG_PKG_USING_MAX17048 is not set -# CONFIG_PKG_USING_RPLIDAR is not set -# CONFIG_PKG_USING_AS608 is not set -# CONFIG_PKG_USING_RC522 is not set -# CONFIG_PKG_USING_WS2812B is not set -# CONFIG_PKG_USING_EMBARC_BSP is not set -# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set -# CONFIG_PKG_USING_MULTI_RTIMER is not set -# CONFIG_PKG_USING_MAX7219 is not set -# CONFIG_PKG_USING_BEEP is not set -# CONFIG_PKG_USING_EASYBLINK is not set -# CONFIG_PKG_USING_PMS_SERIES is not set -# CONFIG_PKG_USING_CAN_YMODEM is not set -# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set -# CONFIG_PKG_USING_QLED is not set -# CONFIG_PKG_USING_PAJ7620 is not set -# CONFIG_PKG_USING_AGILE_CONSOLE is not set -# CONFIG_PKG_USING_LD3320 is not set -# CONFIG_PKG_USING_WK2124 is not set -# CONFIG_PKG_USING_LY68L6400 is not set -# CONFIG_PKG_USING_DM9051 is not set -# CONFIG_PKG_USING_SSD1306 is not set -# CONFIG_PKG_USING_QKEY is not set -# CONFIG_PKG_USING_RS485 is not set -# CONFIG_PKG_USING_RS232 is not set -# CONFIG_PKG_USING_NES is not set -# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set -# CONFIG_PKG_USING_VDEVICE is not set -# CONFIG_PKG_USING_SGM706 is not set -# CONFIG_PKG_USING_STM32WB55_SDK is not set -# CONFIG_PKG_USING_RDA58XX is not set -# CONFIG_PKG_USING_LIBNFC is not set -# CONFIG_PKG_USING_MFOC is not set -# CONFIG_PKG_USING_TMC51XX is not set -# CONFIG_PKG_USING_TCA9534 is not set -# CONFIG_PKG_USING_KOBUKI is not set -# CONFIG_PKG_USING_ROSSERIAL is not set -# CONFIG_PKG_USING_MICRO_ROS is not set -# CONFIG_PKG_USING_MCP23008 is not set -# CONFIG_PKG_USING_BLUETRUM_SDK is not set -# CONFIG_PKG_USING_MISAKA_AT24CXX is not set -# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set -# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set -# CONFIG_PKG_USING_SOFT_SERIAL is not set -# CONFIG_PKG_USING_MB85RS16 is not set -# CONFIG_PKG_USING_CW2015 is not set -# CONFIG_PKG_USING_RFM300 is not set -# CONFIG_PKG_USING_IO_INPUT_FILTER is not set - -# -# AI packages -# -# CONFIG_PKG_USING_LIBANN is not set -# CONFIG_PKG_USING_NNOM is not set -# CONFIG_PKG_USING_ONNX_BACKEND is not set -# CONFIG_PKG_USING_ONNX_PARSER is not set -# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set -# CONFIG_PKG_USING_ELAPACK is not set -# CONFIG_PKG_USING_ULAPACK is not set -# CONFIG_PKG_USING_QUEST is not set -# CONFIG_PKG_USING_NAXOS is not set - -# -# miscellaneous packages -# - -# -# project laboratory -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# entertainment: terminal games and other interesting software packages -# -# CONFIG_PKG_USING_CMATRIX is not set -# CONFIG_PKG_USING_SL is not set -# CONFIG_PKG_USING_CAL is not set -# CONFIG_PKG_USING_ACLOCK is not set -# CONFIG_PKG_USING_THREES is not set -# CONFIG_PKG_USING_2048 is not set -# CONFIG_PKG_USING_SNAKE is not set -# CONFIG_PKG_USING_TETRIS is not set -# CONFIG_PKG_USING_DONUT is not set -# CONFIG_PKG_USING_COWSAY is not set -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_LZMA is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_MINIZIP is not set -# CONFIG_PKG_USING_HEATSHRINK is not set -# CONFIG_PKG_USING_DSTR is not set -# CONFIG_PKG_USING_TINYFRAME is not set -# CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set -# CONFIG_PKG_USING_UPACKER is not set -# CONFIG_PKG_USING_UPARAM is not set -# CONFIG_PKG_USING_HELLO is not set -# CONFIG_PKG_USING_VI is not set -# CONFIG_PKG_USING_KI is not set -# CONFIG_PKG_USING_ARMv7M_DWT is not set -# CONFIG_PKG_USING_UKAL is not set -# CONFIG_PKG_USING_CRCLIB is not set -# CONFIG_PKG_USING_LWGPS is not set -# CONFIG_PKG_USING_STATE_MACHINE is not set -# CONFIG_PKG_USING_DESIGN_PATTERN is not set -# CONFIG_PKG_USING_CONTROLLER is not set -# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set -# CONFIG_PKG_USING_MFBD is not set -# CONFIG_PKG_USING_SLCAN2RTT is not set -# CONFIG_PKG_USING_SOEM is not set - -# -# Hardware Drivers Config -# - -# -# Onboard Peripheral Drivers -# - -# -# On-chip Peripheral Drivers -# -CONFIG_BSP_USING_GPIO=y -# CONFIG_BSP_USING_XINT is not set -CONFIG_BSP_USING_UART=y -CONFIG_BSP_USING_UART1=y -# CONFIG_BSP_USING_PWM is not set -# CONFIG_BSP_USING_ADC is not set -# CONFIG_BSP_USING_ONCHIP_RTC is not set -# CONFIG_BSP_USING_WDT is not set -# CONFIG_BSP_USING_SDIO is not set -# CONFIG_BSP_USING_CAN is not set -# CONFIG_BSP_USING_USBD is not set - -# -# Board extended module Drivers -# diff --git a/bsp/c28x/tms320f28379d/.cproject b/bsp/c28x/tms320f28379d/.cproject deleted file mode 100644 index 36f16276d4..0000000000 --- a/bsp/c28x/tms320f28379d/.cproject +++ /dev/null @@ -1,224 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/c28x/tms320f28379d/.gitignore b/bsp/c28x/tms320f28379d/.gitignore deleted file mode 100644 index 025af2b856..0000000000 --- a/bsp/c28x/tms320f28379d/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -.launches/ -FLASH -RAM diff --git a/bsp/c28x/tms320f28379d/.project b/bsp/c28x/tms320f28379d/.project deleted file mode 100644 index fe05f8c849..0000000000 --- a/bsp/c28x/tms320f28379d/.project +++ /dev/null @@ -1,869 +0,0 @@ - - - rt-thread - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - com.ti.ccstudio.core.ccsNature - org.eclipse.cdt.core.cnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - - - - DeviceDrivers - 2 - virtual:/virtual - - - Kernel - 2 - PARENT-2-PROJECT_LOC/src - - - c28x - 2 - virtual:/virtual - - - finsh - 2 - PARENT-2-PROJECT_LOC/components/finsh - - - libraries - 2 - virtual:/virtual - - - DeviceDrivers/ipc - 2 - PARENT-2-PROJECT_LOC/components/drivers/ipc - - - DeviceDrivers/pin.c - 1 - PARENT-3-PROJECT_LOC/components/drivers/misc/pin.c - - - DeviceDrivers/rt_drv_pwm.c - 1 - PARENT-3-PROJECT_LOC/components/drivers/misc/rt_drv_pwm.c - - - DeviceDrivers/serial.c - 1 - PARENT-3-PROJECT_LOC/components/drivers/serial/serial.c - - - Kernel/Kconfig - 1 - PARENT-3-PROJECT_LOC/src/Kconfig - - - Kernel/SConscript - 1 - PARENT-3-PROJECT_LOC/src/SConscript - - - Kernel/clock.c - 1 - PARENT-3-PROJECT_LOC/src/clock.c - - - Kernel/components.c - 1 - PARENT-3-PROJECT_LOC/src/components.c - - - Kernel/cpu.c - 1 - PARENT-3-PROJECT_LOC/src/cpu.c - - - Kernel/device.c - 1 - PARENT-3-PROJECT_LOC/src/device.c - - - Kernel/idle.c - 1 - PARENT-3-PROJECT_LOC/src/idle.c - - - Kernel/ipc.c - 1 - PARENT-3-PROJECT_LOC/src/ipc.c - - - Kernel/irq.c - 1 - PARENT-3-PROJECT_LOC/src/irq.c - - - Kernel/kservice.c - 1 - PARENT-3-PROJECT_LOC/src/kservice.c - - - Kernel/mem.c - 1 - PARENT-3-PROJECT_LOC/src/mem.c - - - Kernel/memheap.c - 1 - PARENT-3-PROJECT_LOC/src/memheap.c - - - Kernel/mempool.c - 1 - PARENT-3-PROJECT_LOC/src/mempool.c - - - Kernel/object.c - 1 - PARENT-3-PROJECT_LOC/src/object.c - - - Kernel/scheduler.c - 1 - PARENT-3-PROJECT_LOC/src/scheduler.c - - - Kernel/signal.c - 1 - PARENT-3-PROJECT_LOC/src/signal.c - - - Kernel/slab.c - 1 - PARENT-3-PROJECT_LOC/src/slab.c - - - Kernel/thread.c - 1 - PARENT-3-PROJECT_LOC/src/thread.c - - - Kernel/timer.c - 1 - PARENT-3-PROJECT_LOC/src/timer.c - - - c28x/SConscript - 1 - PARENT-3-PROJECT_LOC/libcpu/ti-dsp/c28x/SConscript - - - c28x/context.s - 1 - PARENT-3-PROJECT_LOC/libcpu/ti-dsp/c28x/context.s - - - c28x/cpuport.c - 1 - PARENT-3-PROJECT_LOC/libcpu/ti-dsp/c28x/cpuport.c - - - finsh/Kconfig - 1 - PARENT-3-PROJECT_LOC/components/finsh/Kconfig - - - finsh/SConscript - 1 - PARENT-3-PROJECT_LOC/components/finsh/SConscript - - - finsh/cmd.c - 1 - PARENT-3-PROJECT_LOC/components/finsh/cmd.c - - - finsh/finsh.h - 1 - PARENT-3-PROJECT_LOC/components/finsh/finsh.h - - - finsh/msh.c - 1 - PARENT-3-PROJECT_LOC/components/finsh/msh.c - - - finsh/msh.h - 1 - PARENT-3-PROJECT_LOC/components/finsh/msh.h - - - finsh/msh_file.c - 1 - PARENT-3-PROJECT_LOC/components/finsh/msh_file.c - - - finsh/msh_parse.c - 1 - PARENT-3-PROJECT_LOC/components/finsh/msh_parse.c - - - finsh/msh_parse.h - 1 - PARENT-3-PROJECT_LOC/components/finsh/msh_parse.h - - - finsh/shell.c - 1 - PARENT-3-PROJECT_LOC/components/finsh/shell.c - - - finsh/shell.h - 1 - PARENT-3-PROJECT_LOC/components/finsh/shell.h - - - libraries/HAL_Drivers - 2 - virtual:/virtual - - - libraries/tms320f28379d - 2 - virtual:/virtual - - - DeviceDrivers/ipc/SConscript - 1 - PARENT-3-PROJECT_LOC/components/drivers/ipc/SConscript - - - DeviceDrivers/ipc/completion.c - 1 - PARENT-3-PROJECT_LOC/components/drivers/ipc/completion.c - - - DeviceDrivers/ipc/dataqueue.c - 1 - PARENT-3-PROJECT_LOC/components/drivers/ipc/dataqueue.c - - - DeviceDrivers/ipc/pipe.c - 1 - PARENT-3-PROJECT_LOC/components/drivers/ipc/pipe.c - - - DeviceDrivers/ipc/ringblk_buf.c - 1 - PARENT-3-PROJECT_LOC/components/drivers/ipc/ringblk_buf.c - - - DeviceDrivers/ipc/ringbuffer.c - 1 - PARENT-3-PROJECT_LOC/components/drivers/ipc/ringbuffer.c - - - DeviceDrivers/ipc/waitqueue.c - 1 - PARENT-3-PROJECT_LOC/components/drivers/ipc/waitqueue.c - - - DeviceDrivers/ipc/workqueue.c - 1 - PARENT-3-PROJECT_LOC/components/drivers/ipc/workqueue.c - - - libraries/HAL_Drivers/config - 2 - virtual:/virtual - - - libraries/HAL_Drivers/drv_config.h - 1 - PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/drv_config.h - - - libraries/HAL_Drivers/drv_gpio.c - 1 - PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/drv_gpio.c - - - libraries/HAL_Drivers/drv_gpio.h - 1 - PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/drv_gpio.h - - - libraries/HAL_Drivers/drv_pwm.c - 1 - PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/drv_pwm.c - - - libraries/HAL_Drivers/drv_pwm.h - 1 - PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/drv_pwm.h - - - libraries/HAL_Drivers/drv_sci.c - 1 - PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/drv_sci.c - - - libraries/HAL_Drivers/drv_sci.h - 1 - PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/drv_sci.h - - - libraries/tms320f28379d/common - 2 - virtual:/virtual - - - libraries/tms320f28379d/headers - 2 - virtual:/virtual - - - libraries/HAL_Drivers/config/pwm_config.h - 1 - PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/config/pwm_config.h - - - libraries/tms320f28379d/common/include - 2 - virtual:/virtual - - - libraries/tms320f28379d/common/source - 2 - virtual:/virtual - - - libraries/tms320f28379d/headers/cmd - 2 - virtual:/virtual - - - libraries/tms320f28379d/headers/include - 2 - virtual:/virtual - - - libraries/tms320f28379d/headers/source - 2 - virtual:/virtual - - - libraries/tms320f28379d/common/include/F2837xD_Adc_defines.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Adc_defines.h - - - libraries/tms320f28379d/common/include/F2837xD_Can_defines.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Can_defines.h - - - libraries/tms320f28379d/common/include/F2837xD_Cla_defines.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Cla_defines.h - - - libraries/tms320f28379d/common/include/F2837xD_Cla_typedefs.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Cla_typedefs.h - - - libraries/tms320f28379d/common/include/F2837xD_Dma_defines.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Dma_defines.h - - - libraries/tms320f28379d/common/include/F2837xD_EPwm_defines.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_EPwm_defines.h - - - libraries/tms320f28379d/common/include/F2837xD_Emif_defines.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Emif_defines.h - - - libraries/tms320f28379d/common/include/F2837xD_Examples.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Examples.h - - - libraries/tms320f28379d/common/include/F2837xD_GlobalPrototypes.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_GlobalPrototypes.h - - - libraries/tms320f28379d/common/include/F2837xD_Gpio_defines.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Gpio_defines.h - - - libraries/tms320f28379d/common/include/F2837xD_I2c_defines.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_I2c_defines.h - - - libraries/tms320f28379d/common/include/F2837xD_Ipc_defines.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Ipc_defines.h - - - libraries/tms320f28379d/common/include/F2837xD_Ipc_drivers.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Ipc_drivers.h - - - libraries/tms320f28379d/common/include/F2837xD_Pie_defines.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Pie_defines.h - - - libraries/tms320f28379d/common/include/F2837xD_SWPrioritizedIsrLevels.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_SWPrioritizedIsrLevels.h - - - libraries/tms320f28379d/common/include/F2837xD_SysCtrl_defines.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_SysCtrl_defines.h - - - libraries/tms320f28379d/common/include/F2837xD_Systick_defines.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Systick_defines.h - - - libraries/tms320f28379d/common/include/F2837xD_Upp_defines.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Upp_defines.h - - - libraries/tms320f28379d/common/include/F2837xD_cputimervars.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_cputimervars.h - - - libraries/tms320f28379d/common/include/F2837xD_defaultisr.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_defaultisr.h - - - libraries/tms320f28379d/common/include/F2837xD_sci_io.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_sci_io.h - - - libraries/tms320f28379d/common/include/F2837xD_sdfm_drivers.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_sdfm_drivers.h - - - libraries/tms320f28379d/common/include/F2837xD_struct.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_struct.h - - - libraries/tms320f28379d/common/include/F28x_Project.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F28x_Project.h - - - libraries/tms320f28379d/common/include/device.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/device.h - - - libraries/tms320f28379d/common/include/driverlib.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/driverlib.h - - - libraries/tms320f28379d/common/include/stdint.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/stdint.h - - - libraries/tms320f28379d/common/include/usb.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/usb.h - - - libraries/tms320f28379d/common/include/usb_hal.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/usb_hal.h - - - libraries/tms320f28379d/common/source/F2837xD_Adc.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Adc.c - - - libraries/tms320f28379d/common/source/F2837xD_CodeStartBranch.asm - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_CodeStartBranch.asm - - - libraries/tms320f28379d/common/source/F2837xD_CpuTimers.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_CpuTimers.c - - - libraries/tms320f28379d/common/source/F2837xD_DBGIER.asm - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_DBGIER.asm - - - libraries/tms320f28379d/common/source/F2837xD_DefaultISR.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_DefaultISR.c - - - libraries/tms320f28379d/common/source/F2837xD_Dma.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Dma.c - - - libraries/tms320f28379d/common/source/F2837xD_ECap.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_ECap.c - - - libraries/tms320f28379d/common/source/F2837xD_EPwm.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_EPwm.c - - - libraries/tms320f28379d/common/source/F2837xD_EQep.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_EQep.c - - - libraries/tms320f28379d/common/source/F2837xD_Emif.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Emif.c - - - libraries/tms320f28379d/common/source/F2837xD_Gpio.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Gpio.c - - - libraries/tms320f28379d/common/source/F2837xD_I2C.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_I2C.c - - - libraries/tms320f28379d/common/source/F2837xD_Ipc.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Ipc.c - - - libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver.c - - - libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Lite.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Lite.c - - - libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Util.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Util.c - - - libraries/tms320f28379d/common/source/F2837xD_Mcbsp.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Mcbsp.c - - - libraries/tms320f28379d/common/source/F2837xD_PieCtrl.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_PieCtrl.c - - - libraries/tms320f28379d/common/source/F2837xD_PieVect.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_PieVect.c - - - libraries/tms320f28379d/common/source/F2837xD_SWPrioritizedPieVect.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_SWPrioritizedPieVect.c - - - libraries/tms320f28379d/common/source/F2837xD_Sci.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Sci.c - - - libraries/tms320f28379d/common/source/F2837xD_Spi.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Spi.c - - - libraries/tms320f28379d/common/source/F2837xD_SysCtrl.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_SysCtrl.c - - - libraries/tms320f28379d/common/source/F2837xD_TempSensorConv.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_TempSensorConv.c - - - libraries/tms320f28379d/common/source/F2837xD_Upp.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Upp.c - - - libraries/tms320f28379d/common/source/F2837xD_can.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_can.c - - - libraries/tms320f28379d/common/source/F2837xD_sci_io.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_sci_io.c - - - libraries/tms320f28379d/common/source/F2837xD_sdfm_drivers.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_sdfm_drivers.c - - - libraries/tms320f28379d/common/source/F2837xD_struct.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_struct.c - - - libraries/tms320f28379d/common/source/F2837xD_usDelay.asm - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_usDelay.asm - - - libraries/tms320f28379d/common/source/device.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/device.c - - - libraries/tms320f28379d/common/source/usb.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/usb.c - - - libraries/tms320f28379d/common/source/usb_hal.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/usb_hal.c - - - libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd - - - libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd - - - libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd - - - libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd - - - libraries/tms320f28379d/headers/include/F2837xD_adc.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_adc.h - - - libraries/tms320f28379d/headers/include/F2837xD_analogsubsys.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_analogsubsys.h - - - libraries/tms320f28379d/headers/include/F2837xD_can.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_can.h - - - libraries/tms320f28379d/headers/include/F2837xD_cla.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_cla.h - - - libraries/tms320f28379d/headers/include/F2837xD_cmpss.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_cmpss.h - - - libraries/tms320f28379d/headers/include/F2837xD_cputimer.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_cputimer.h - - - libraries/tms320f28379d/headers/include/F2837xD_dac.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_dac.h - - - libraries/tms320f28379d/headers/include/F2837xD_dcsm.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_dcsm.h - - - libraries/tms320f28379d/headers/include/F2837xD_device.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_device.h - - - libraries/tms320f28379d/headers/include/F2837xD_dma.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_dma.h - - - libraries/tms320f28379d/headers/include/F2837xD_ecap.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_ecap.h - - - libraries/tms320f28379d/headers/include/F2837xD_emif.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_emif.h - - - libraries/tms320f28379d/headers/include/F2837xD_epwm.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_epwm.h - - - libraries/tms320f28379d/headers/include/F2837xD_epwm_xbar.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_epwm_xbar.h - - - libraries/tms320f28379d/headers/include/F2837xD_eqep.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_eqep.h - - - libraries/tms320f28379d/headers/include/F2837xD_flash.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_flash.h - - - libraries/tms320f28379d/headers/include/F2837xD_gpio.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_gpio.h - - - libraries/tms320f28379d/headers/include/F2837xD_i2c.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_i2c.h - - - libraries/tms320f28379d/headers/include/F2837xD_input_xbar.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_input_xbar.h - - - libraries/tms320f28379d/headers/include/F2837xD_ipc.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_ipc.h - - - libraries/tms320f28379d/headers/include/F2837xD_mcbsp.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_mcbsp.h - - - libraries/tms320f28379d/headers/include/F2837xD_memconfig.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_memconfig.h - - - libraries/tms320f28379d/headers/include/F2837xD_nmiintrupt.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_nmiintrupt.h - - - libraries/tms320f28379d/headers/include/F2837xD_output_xbar.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_output_xbar.h - - - libraries/tms320f28379d/headers/include/F2837xD_piectrl.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_piectrl.h - - - libraries/tms320f28379d/headers/include/F2837xD_pievect.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_pievect.h - - - libraries/tms320f28379d/headers/include/F2837xD_sci.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_sci.h - - - libraries/tms320f28379d/headers/include/F2837xD_sdfm.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_sdfm.h - - - libraries/tms320f28379d/headers/include/F2837xD_spi.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_spi.h - - - libraries/tms320f28379d/headers/include/F2837xD_sysctrl.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_sysctrl.h - - - libraries/tms320f28379d/headers/include/F2837xD_upp.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_upp.h - - - libraries/tms320f28379d/headers/include/F2837xD_xbar.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_xbar.h - - - libraries/tms320f28379d/headers/include/F2837xD_xint.h - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_xint.h - - - libraries/tms320f28379d/headers/source/F2837xD_GlobalVariableDefs.c - 1 - PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/source/F2837xD_GlobalVariableDefs.c - - - diff --git a/bsp/c28x/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs b/bsp/c28x/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs deleted file mode 100644 index f653028c53..0000000000 --- a/bsp/c28x/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs +++ /dev/null @@ -1,3 +0,0 @@ -eclipse.preferences.version=1 -inEditor=false -onBuild=false diff --git a/bsp/c28x/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs b/bsp/c28x/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs deleted file mode 100644 index 2adc7b1dde..0000000000 --- a/bsp/c28x/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs +++ /dev/null @@ -1,2 +0,0 @@ -eclipse.preferences.version=1 -org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/bsp/c28x/tms320f28379d/.settings/org.eclipse.core.resources.prefs b/bsp/c28x/tms320f28379d/.settings/org.eclipse.core.resources.prefs deleted file mode 100644 index 814522b6df..0000000000 --- a/bsp/c28x/tms320f28379d/.settings/org.eclipse.core.resources.prefs +++ /dev/null @@ -1,91 +0,0 @@ -eclipse.preferences.version=1 -encoding//Debug/drivers/subdir_rules.mk=UTF-8 -encoding//Debug/drivers/subdir_vars.mk=UTF-8 -encoding//Debug/libraries/common/source/subdir_rules.mk=UTF-8 -encoding//Debug/libraries/common/source/subdir_vars.mk=UTF-8 -encoding//Debug/libraries/headers/cmd/subdir_rules.mk=UTF-8 -encoding//Debug/libraries/headers/cmd/subdir_vars.mk=UTF-8 -encoding//Debug/libraries/headers/source/subdir_rules.mk=UTF-8 -encoding//Debug/libraries/headers/source/subdir_vars.mk=UTF-8 -encoding//FLASH/DeviceDrivers/ipc/subdir_rules.mk=UTF-8 -encoding//FLASH/DeviceDrivers/ipc/subdir_vars.mk=UTF-8 -encoding//FLASH/DeviceDrivers/subdir_rules.mk=UTF-8 -encoding//FLASH/DeviceDrivers/subdir_vars.mk=UTF-8 -encoding//FLASH/Kernel/subdir_rules.mk=UTF-8 -encoding//FLASH/Kernel/subdir_vars.mk=UTF-8 -encoding//FLASH/applications/subdir_rules.mk=UTF-8 -encoding//FLASH/applications/subdir_vars.mk=UTF-8 -encoding//FLASH/board/subdir_rules.mk=UTF-8 -encoding//FLASH/board/subdir_vars.mk=UTF-8 -encoding//FLASH/c28x/subdir_rules.mk=UTF-8 -encoding//FLASH/c28x/subdir_vars.mk=UTF-8 -encoding//FLASH/drivers/subdir_rules.mk=UTF-8 -encoding//FLASH/drivers/subdir_vars.mk=UTF-8 -encoding//FLASH/finsh/subdir_rules.mk=UTF-8 -encoding//FLASH/finsh/subdir_vars.mk=UTF-8 -encoding//FLASH/libraries/HAL_Drivers/subdir_rules.mk=UTF-8 -encoding//FLASH/libraries/HAL_Drivers/subdir_vars.mk=UTF-8 -encoding//FLASH/libraries/common/source/subdir_rules.mk=UTF-8 -encoding//FLASH/libraries/common/source/subdir_vars.mk=UTF-8 -encoding//FLASH/libraries/headers/cmd/subdir_rules.mk=UTF-8 -encoding//FLASH/libraries/headers/cmd/subdir_vars.mk=UTF-8 -encoding//FLASH/libraries/headers/source/subdir_rules.mk=UTF-8 -encoding//FLASH/libraries/headers/source/subdir_vars.mk=UTF-8 -encoding//FLASH/libraries/tms320f28379d/common/cmd/subdir_rules.mk=UTF-8 -encoding//FLASH/libraries/tms320f28379d/common/cmd/subdir_vars.mk=UTF-8 -encoding//FLASH/libraries/tms320f28379d/common/deprecated/driverlib/subdir_rules.mk=UTF-8 -encoding//FLASH/libraries/tms320f28379d/common/deprecated/driverlib/subdir_vars.mk=UTF-8 -encoding//FLASH/libraries/tms320f28379d/common/deprecated/utils/subdir_rules.mk=UTF-8 -encoding//FLASH/libraries/tms320f28379d/common/deprecated/utils/subdir_vars.mk=UTF-8 -encoding//FLASH/libraries/tms320f28379d/common/source/subdir_rules.mk=UTF-8 -encoding//FLASH/libraries/tms320f28379d/common/source/subdir_vars.mk=UTF-8 -encoding//FLASH/libraries/tms320f28379d/headers/cmd/subdir_rules.mk=UTF-8 -encoding//FLASH/libraries/tms320f28379d/headers/cmd/subdir_vars.mk=UTF-8 -encoding//FLASH/libraries/tms320f28379d/headers/source/subdir_rules.mk=UTF-8 -encoding//FLASH/libraries/tms320f28379d/headers/source/subdir_vars.mk=UTF-8 -encoding//FLASH/makefile=UTF-8 -encoding//FLASH/objects.mk=UTF-8 -encoding//FLASH/sources.mk=UTF-8 -encoding//FLASH/subdir_rules.mk=UTF-8 -encoding//FLASH/subdir_vars.mk=UTF-8 -encoding//RAM/DeviceDrivers/ipc/subdir_rules.mk=UTF-8 -encoding//RAM/DeviceDrivers/ipc/subdir_vars.mk=UTF-8 -encoding//RAM/DeviceDrivers/subdir_rules.mk=UTF-8 -encoding//RAM/DeviceDrivers/subdir_vars.mk=UTF-8 -encoding//RAM/Kernel/subdir_rules.mk=UTF-8 -encoding//RAM/Kernel/subdir_vars.mk=UTF-8 -encoding//RAM/applications/subdir_rules.mk=UTF-8 -encoding//RAM/applications/subdir_vars.mk=UTF-8 -encoding//RAM/board/subdir_rules.mk=UTF-8 -encoding//RAM/board/subdir_vars.mk=UTF-8 -encoding//RAM/c28x/subdir_rules.mk=UTF-8 -encoding//RAM/c28x/subdir_vars.mk=UTF-8 -encoding//RAM/drivers/subdir_rules.mk=UTF-8 -encoding//RAM/drivers/subdir_vars.mk=UTF-8 -encoding//RAM/finsh/subdir_rules.mk=UTF-8 -encoding//RAM/finsh/subdir_vars.mk=UTF-8 -encoding//RAM/libraries/HAL_Drivers/subdir_rules.mk=UTF-8 -encoding//RAM/libraries/HAL_Drivers/subdir_vars.mk=UTF-8 -encoding//RAM/libraries/common/source/subdir_rules.mk=UTF-8 -encoding//RAM/libraries/common/source/subdir_vars.mk=UTF-8 -encoding//RAM/libraries/headers/cmd/subdir_rules.mk=UTF-8 -encoding//RAM/libraries/headers/cmd/subdir_vars.mk=UTF-8 -encoding//RAM/libraries/headers/source/subdir_rules.mk=UTF-8 -encoding//RAM/libraries/headers/source/subdir_vars.mk=UTF-8 -encoding//RAM/libraries/tms320f28379d/common/cmd/subdir_rules.mk=UTF-8 -encoding//RAM/libraries/tms320f28379d/common/cmd/subdir_vars.mk=UTF-8 -encoding//RAM/libraries/tms320f28379d/common/deprecated/driverlib/subdir_rules.mk=UTF-8 -encoding//RAM/libraries/tms320f28379d/common/deprecated/driverlib/subdir_vars.mk=UTF-8 -encoding//RAM/libraries/tms320f28379d/common/deprecated/utils/subdir_rules.mk=UTF-8 -encoding//RAM/libraries/tms320f28379d/common/deprecated/utils/subdir_vars.mk=UTF-8 -encoding//RAM/libraries/tms320f28379d/common/source/subdir_rules.mk=UTF-8 -encoding//RAM/libraries/tms320f28379d/common/source/subdir_vars.mk=UTF-8 -encoding//RAM/libraries/tms320f28379d/headers/cmd/subdir_rules.mk=UTF-8 -encoding//RAM/libraries/tms320f28379d/headers/cmd/subdir_vars.mk=UTF-8 -encoding//RAM/libraries/tms320f28379d/headers/source/subdir_rules.mk=UTF-8 -encoding//RAM/libraries/tms320f28379d/headers/source/subdir_vars.mk=UTF-8 -encoding//RAM/makefile=UTF-8 -encoding//RAM/objects.mk=UTF-8 -encoding//RAM/sources.mk=UTF-8 -encoding//RAM/subdir_rules.mk=UTF-8 -encoding//RAM/subdir_vars.mk=UTF-8 diff --git a/bsp/c28x/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd b/bsp/c28x/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd deleted file mode 100644 index 9787987d30..0000000000 --- a/bsp/c28x/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd +++ /dev/null @@ -1,119 +0,0 @@ -___heap_end = 0x010000; -MEMORY -{ -PAGE 0 : /* Program Memory */ - /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ - /* BEGIN is used for the "boot to Flash" bootloader mode */ - - BEGIN : origin = 0x080000, length = 0x000002 - RESET : origin = 0x3FFFC0, length = 0x000002 - RAMGS8_15 : origin = 0x013000, length = 0x009000 - - /* Flash sectors */ - FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ - FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ - FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ - FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ - FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ - FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ - FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ - FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ - FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ - FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ - FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ - FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ - FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ - FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ - -PAGE 1 : /* Data Memory */ - /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ - BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ - RAMM0 : origin = 0x000122, length = 0x0002DE - RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ - EBSS : origin = 0x008000, length = 0x008000 /* RAMLS0-4, 5*0x0800 */ - CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 - CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 -} - - -SECTIONS -{ - /* Allocate program areas: */ - .cinit : > FLASHF PAGE = 0, ALIGN(4) - .pinit : > FLASHF, PAGE = 0, ALIGN(4) - .text : >> FLASHE PAGE = 0, ALIGN(4) - codestart : > BEGIN PAGE = 0, ALIGN(4) - -#ifdef __TI_COMPILER_VERSION__ - #if __TI_COMPILER_VERSION__ >= 15009000 - .TI.ramfunc : {} LOAD = FLASHF, - RUN = RAMGS8_15, - LOAD_START(_RamfuncsLoadStart), - LOAD_SIZE(_RamfuncsLoadSize), - LOAD_END(_RamfuncsLoadEnd), - RUN_START(_RamfuncsRunStart), - RUN_SIZE(_RamfuncsRunSize), - RUN_END(_RamfuncsRunEnd), - PAGE = 0, ALIGN(4) - #else - ramfuncs : LOAD = FLASHF, - RUN = RAMGS8_15, - LOAD_START(_RamfuncsLoadStart), - LOAD_SIZE(_RamfuncsLoadSize), - LOAD_END(_RamfuncsLoadEnd), - RUN_START(_RamfuncsRunStart), - RUN_SIZE(_RamfuncsRunSize), - RUN_END(_RamfuncsRunEnd), - PAGE = 0, ALIGN(4) - #endif -#endif - - FSymTab : > RAMM1, PAGE = 1, ALIGN(4) - LOAD_START(___fsymtab_start) - LOAD_END(___fsymtab_end) - .rti_fn.0.end : > RAMM1, PAGE = 1 - .rti_fn.0 : > RAMM1, PAGE = 1 - .rti_fn.1 : > RAMM1, PAGE = 1 - .rti_fn.2 : > RAMM1, PAGE = 1 - .rti_fn.3 : > RAMM1, PAGE = 1 - .rti_fn.4 : > RAMM1, PAGE = 1 - .rti_fn.5 : > RAMM1, PAGE = 1 - .rti_fn.1.end : > RAMM1, PAGE = 1 - .rti_fn.6.end : > RAMM1, PAGE = 1 - .rti_fn.6 : > RAMM1, PAGE = 1 - /* Allocate uninitalized data sections: */ - .stack : > RAMM1 PAGE = 1 - .ebss : > EBSS, - LOAD_START(___ebss_start), - LOAD_END(___ebss_end), - PAGE = 1 - .esysmem : >> RAMM1 PAGE = 1 - - /* Initalized sections go in Flash */ - .econst : >> FLASHF PAGE = 0, ALIGN(4) - .switch : > FLASHF PAGE = 0, ALIGN(4) - - .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ - - /* The following section definitions are required when using the IPC API Drivers */ - GROUP : > CPU1TOCPU2RAM, PAGE = 1 - { - PUTBUFFER - PUTWRITEIDX - GETREADIDX - } - - GROUP : > CPU2TOCPU1RAM, PAGE = 1 - { - GETBUFFER : TYPE = DSECT - GETWRITEIDX : TYPE = DSECT - PUTREADIDX : TYPE = DSECT - } - -} - -/* -//=========================================================================== -// End of file. -//=========================================================================== -*/ diff --git a/bsp/c28x/tms320f28379d/2837x_RAM_lnk_cpu1.cmd b/bsp/c28x/tms320f28379d/2837x_RAM_lnk_cpu1.cmd deleted file mode 100644 index 5eae476e44..0000000000 --- a/bsp/c28x/tms320f28379d/2837x_RAM_lnk_cpu1.cmd +++ /dev/null @@ -1,83 +0,0 @@ -___heap_end = 0x00F000; - -MEMORY -{ -PAGE 0 : - /* BEGIN is used for the "boot to SARAM" bootloader mode */ - - BEGIN : origin = 0x000000, length = 0x000002 - RAMM0 : origin = 0x000122, length = 0x0002DE - RESET : origin = 0x3FFFC0, length = 0x000002 - RAMGS8_15 : origin = 0x013000, length = 0x009000 - -PAGE 1 : - RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ - BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ - EBSS : origin = 0x008000, length = 0x007000 /* RAMLS0-4, 5*0x0800 */ - ECONST : origin = 0x00F000, length = 0x004000 /* RAMGS0-2, 3*0x1000 */ - CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 - CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 -} - -SECTIONS -{ - codestart : > BEGIN, PAGE = 0 - -#ifdef __TI_COMPILER_VERSION__ - #if __TI_COMPILER_VERSION__ >= 15009000 - .TI.ramfunc : {} > RAMM0, PAGE = 0 - #else - ramfuncs : > RAMM0 PAGE = 0 - #endif -#endif - .text : > RAMGS8_15, PAGE = 0 - .cinit : > RAMM0, PAGE = 0 - .pinit : > RAMM0, PAGE = 0 - .switch : > RAMM0, PAGE = 0 - .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ - .rti_fn.0.end : > RAMM1, PAGE = 1 - .rti_fn.0 : > RAMM1, PAGE = 1 - .rti_fn.1 : > RAMM1, PAGE = 1 - .rti_fn.2 : > RAMM1, PAGE = 1 - .rti_fn.3 : > RAMM1, PAGE = 1 - .rti_fn.4 : > RAMM1, PAGE = 1 - .rti_fn.5 : > RAMM1, PAGE = 1 - .rti_fn.1.end : > RAMM1, PAGE = 1 - .rti_fn.6.end : > RAMM1, PAGE = 1 - .rti_fn.6 : > RAMM1, PAGE = 1 - .stack : > RAMM1, PAGE = 1 - .esysmem : > RAMM1, PAGE = 1 - - .ebss : > EBSS, - LOAD_START(___ebss_start), - LOAD_END(___ebss_end), - PAGE = 1 - - .econst : > ECONST, PAGE = 1 - - /* finsh symbol table */ - FSymTab : > RAMM1, PAGE = 1, ALIGN(4) - LOAD_START(___fsymtab_start) - LOAD_END(___fsymtab_end) - - /* The following section definitions are required when using the IPC API Drivers */ - GROUP : > CPU1TOCPU2RAM, PAGE = 1 - { - PUTBUFFER - PUTWRITEIDX - GETREADIDX - } - - GROUP : > CPU2TOCPU1RAM, PAGE = 1 - { - GETBUFFER : TYPE = DSECT - GETWRITEIDX : TYPE = DSECT - PUTREADIDX : TYPE = DSECT - } -} - -/* -//=========================================================================== -// End of file. -//=========================================================================== -*/ diff --git a/bsp/c28x/tms320f28379d/Kconfig b/bsp/c28x/tms320f28379d/Kconfig deleted file mode 100644 index e832d7eb6d..0000000000 --- a/bsp/c28x/tms320f28379d/Kconfig +++ /dev/null @@ -1,30 +0,0 @@ -mainmenu "RT-Thread Configuration" - -config BSP_DIR - string - option env="BSP_ROOT" - default "." - -config RTT_DIR - string - option env="RTT_ROOT" - default "../../.." - -# you can change the RTT_ROOT default "../.." to your rtthread_root, -# example : default "F:/git_repositories/rt-thread" - -config PKGS_DIR - string - option env="PKGS_ROOT" - default "packages" - -config SOC_TMS320F28X - bool - select ARCH_TIDSP_C28X - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - default y - -source "$RTT_DIR/Kconfig" -source "$PKGS_DIR/Kconfig" -source "board/Kconfig" diff --git a/bsp/c28x/tms320f28379d/README.md b/bsp/c28x/tms320f28379d/README.md deleted file mode 100644 index 42ffc1ee89..0000000000 --- a/bsp/c28x/tms320f28379d/README.md +++ /dev/null @@ -1,107 +0,0 @@ -# TMS320F28379D - - -## 1. 简介 - -TMS320F28379D BSP 基于 C2000 Delfino MCU F28379D LaunchPad 开发套件开发。 -TMS320F28379D 是一款功能强大的 32 位浮点微控制器单元 (MCU)，针对高级闭环控制应用而设计，例如工业驱动器和伺服电机控制、太阳能逆变器和转换器、数字电源、电力输送以及电力线通信。 - -![launch-28379d](figures/launch-28379d.png) - -包括如下硬件特性： - -| 硬件 | 描述 | -| -- | -- | -|芯片型号| TMS320F28379D | -|多核 CPU| 两个 TMS320C28x 32 位 CPU | -|| 两个可编程控制律加速器 (CLA) | -|主频| 200MHz | -|CLA 频率| 200MHz | -|总处理能力| 800MIPS | -|片内SRAM| 204kB | -|片内Flash| 1MB | - -F28379D LaunchPad 板载资源如下： -* USB 调试和下载接口通过电气隔离的高速 XDS100v2 调试器实现，同时包含虚拟串口功能 -* TMS320F28379D CPU -* 两个 LED -* 设备复位按钮 -* 易于使用的引出引脚，用于调试或用作扩展板的接口 -* 双 5V 正交编码接口 -* 带集成收发器的 CAN 接口 -* 拨码开关用于启动模式选择 -* 差分放大器向差分模式 ADC 提供 16 位模式的缓冲信号 -* 可选的 SMA 连接点 -* 四个 Sigma-Delta 解调器输入到 BP 接口 - -## 2. 编译说明 -TMS320F28379D 程序的编译和下载要使用的是 TI 官方提供的 Code Composer Studio，TMS320F28379D 至少需要 CCS6.0 以上的版本才能正常编译调试。本 BSP 在 CCS7/CCS8 版本上测试通过，其他版本未做测试。可以在 TI 的官方站点上下载最新版本的 CCS。[CCS 官方下载站点][3] -### 2.1 导入工程 -首先打开 Code Composer Studio，点击 Project -> Import CCS Projects... - -![import](figures/import.png) - -在打开的对话框中，点击 Select search -> directory 右边的 Browse... 选择 TMS320F28379D BSP 所在文件夹，如图所示。选择完成后点击 Finish 完成导入。 - -![import_dia](figures/import_dia.png) - -### 2.2 编译工程 -使用 CCS 内置的 C 编译器可以进行工程的编译。CCS 8 需要使用 TI v18.1.3.LTS 编译器。CCS 10 需要使用 TI v20.2.1.LTS 及以上版本编译器（v20.2.0.LTS及以下版本的编译器有bug编译时会出现segmentation fault）。本文使用的是 Code Composer Studio 10.1.1 和 TI v20.2.4.LTS 编译器的组合（已经配置在工程文件中）。导入工程后，在右边的 Project Explorer 列表里可以看到刚刚导入的 rt-thread 工程。本BSP提供两种编译的方式，分别用于在RAM中执行和在FLASH中执行。 -如图所示可以选择RAM和FLASH进行build。 -![](figures/build.png) -## 3. 烧写及执行 - -编译完成后，可以开始下载和调试。把开发板和电脑通过 Mini-USB 线连接，使用 CCS 中的烧写功能可直接通过板载 XDS100v2 仿真器烧写并执行。 - -![debug_as](figures/debug_as.png) - -在右边的 Project Explorer 的列表中右键点击 rt-thread 工程，在弹出的菜单中选择 Debug As -> 1 Code Composer Debug Session。 - -![launching](figures/launching.png) - -在弹出的 Launching Debug Session 对话框中可以选择要调试的 CPU 核和 CLA 核，这里我们只选择 C28xx_CPU1，点击 OK 开始下载和调试。 - -下载完成后，CCS 将进入调试模式，可以选择继续运行、单步调试、复位等操作。 - -退出 CCS 调试模式，在终端工具里打开相应的串口（115200-8-1-N），按下板子上的复位按钮执行复位操作后，可以看到 RT-Thread 的输出信息: -```bash - \ | / -- RT - Thread Operating System - / | \ 4.1.1 build Jul 4 2022 22:33:37 - 2006 - 2022 Copyright by RT-Thread team - msh > - ``` - -## 4. 注意事项 - -* 由于当前还暂未编写 Scons 编译系统对 CCS 开发环境的支持，所以在使用 env 中的 menuconfig 进行配置后，如果添加了新的组件或软件包，需要手动在 CCS 中添加相应的 C 源文件和头文件。 - -## 5. 驱动支持情况及计划 - -| 驱动 | 支持情况 | 备注 | -| ------ | ---- | :------: | -| CPU Timer | 支持 | | -| GPIO | 支持 | | -| SCI | 支持 | SCIA/B/C | -| ePWM | | | -| ADC | | | -| DAC | | | -| I2C | | | -| SPI | | | -| CAN | | | -| eCAP | | | - -## 6. 联系人信息 - -维护人： -1. guyunjie < yunjie.gu1@gmail.com > -2. qiyu < qiyu_sjtu@163.com > - -## 7. 参考 - -* [C2000 Delfino MCU F28379D LaunchPad 开发套件][1] -* TMS320F28379D [相关技术文档][2] - - [1]: http://www.ti.com.cn/tool/cn/launchxl-f28379d - [2]: http://www.ti.com.cn/product/cn/tms320f28379d/technicaldocuments - [3]: http://processors.wiki.ti.com/index.php/Download_CCS#Download_the_latest_CCS diff --git a/bsp/c28x/tms320f28379d/applications/startup.c b/bsp/c28x/tms320f28379d/applications/startup.c deleted file mode 100644 index def94440fd..0000000000 --- a/bsp/c28x/tms320f28379d/applications/startup.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2006-08-31 Bernard first implementation - * 2018-09-02 xuzhuoyi modify for TMS320F28379D version - * 2022-08-21 yuqi modify the entry function - */ - -#include -#include -#include -#include "board.h" - -int main(void) -{ - unsigned long x=10000; - - while(x) - { - x--; - } -} - -/*@}*/ diff --git a/bsp/c28x/tms320f28379d/board/Kconfig b/bsp/c28x/tms320f28379d/board/Kconfig deleted file mode 100644 index 740e3073ea..0000000000 --- a/bsp/c28x/tms320f28379d/board/Kconfig +++ /dev/null @@ -1,1045 +0,0 @@ -menu "Hardware Drivers Config" - -menu "Onboard Peripheral Drivers" -endmenu - -menu "On-chip Peripheral Drivers" - config BSP_USING_GPIO - bool "Enable GPIO" - select RT_USING_PIN - default y - menuconfig BSP_USING_XINT - bool "Enable external interrupt" - default n - if BSP_USING_XINT - menuconfig BSP_USING_XINT1 - bool "Enable XINT1" - if BSP_USING_XINT1 - config BSP_XINT1_PIN - int "Interrupt pin" - range 0 168 - default 0 - endif - if !BSP_USING_XINT1 - config BSP_XINT1_PIN - int - default -1 - endif - menuconfig BSP_USING_XINT2 - bool "Enable XINT2" - if BSP_USING_XINT2 - config BSP_XINT2_PIN - int "Interrupt pin" - range 0 168 - default 0 - endif - if !BSP_USING_XINT2 - config BSP_XINT2_PIN - int - default -1 - endif - menuconfig BSP_USING_XINT3 - bool "Enable XINT3" - if BSP_USING_XINT3 - config BSP_XINT3_PIN - int "Interrupt pin" - range 0 168 - default 0 - endif - if !BSP_USING_XINT3 - config BSP_XINT3_PIN - int - default -1 - endif - menuconfig BSP_USING_XINT4 - bool "Enable XINT4" - if BSP_USING_XINT4 - config BSP_XINT4_PIN - int "Interrupt pin" - range 0 168 - default 0 - endif - if !BSP_USING_XINT4 - config BSP_XINT4_PIN - int - default -1 - endif - if !BSP_USING_XINT5 - config BSP_XINT5_PIN - int - default -1 - endif - menuconfig BSP_USING_XINT5 - bool "Enable XINT5" - if BSP_USING_XINT5 - config BSP_XINT5_PIN - int "Interrupt pin" - range 0 168 - default 0 - endif - endif - menuconfig BSP_USING_UART - bool "Enable UART" - default y - select RT_USING_SERIAL - if BSP_USING_UART - config BSP_USING_UART1 - bool "Enable UART1" - default y - endif - menuconfig BSP_USING_PWM - bool "Enable PWM" - default n - select RT_USING_PWM - - if BSP_USING_PWM - menuconfig BSP_USING_PWM1 - bool "Enable ePWM1" - default n - if BSP_USING_PWM1 - menu "Basic settings for PWM1" - config BSP_PWM1_INIT_PERIOD - int "Initial period for PWM1(ns)" - default 10000 - config BSP_PWM1_INIT_PULSE - int "Initial pulse for PWM1(ns)" - default 1000 - endmenu - menu "Advanced Settings for PWM1" - menuconfig BSP_PWM1_PHASE_ENABLE - bool "Enable phase" - default n - if BSP_PWM1_PHASE_ENABLE - choice - prompt "Select master or slave" - default BSP_PWM1_MASTER - config BSP_PWM1_MASTER - bool "Master" - config BSP_PWM1_SLAVE - bool "Slave" - endchoice - if BSP_PWM1_MASTER - config BSP_PWM1_PHASE - int - default 0 - endif - if BSP_PWM1_SLAVE - config BSP_PWM1_PHASE - int "Phase, 0~360" - range 0 360 - default 0 - help - the phase for PWM1 module - endif - endif - - menuconfig BSP_PWM1_IT_ENABLE - bool "Enable interrupt service" - default n - if BSP_PWM1_IT_ENABLE - choice - prompt "Select interrupt time" - default BSP_PWM1_INTSEL_ET_CTR_ZERO - config BSP_PWM1_INTSEL_ET_DCAEVT1SOC - bool "DCAEVT1SOC" - config BSP_PWM1_INTSEL_ET_CTR_ZERO - bool "ctr == zero" - config BSP_PWM1_INTSEL_ET_CTR_PRD - bool "ctr == prd" - config BSP_PWM1_INTSEL_ET_CTR_PRDZERO - bool "ctr == prd or ctr == zero" - config BSP_PWM1_INTSEL_ET_CTRU_CMPA - bool "ctr == compa when counting up" - config BSP_PWM1_INTSEL_ET_CTRD_CMPA - bool "ctr == compa when counting down" - config BSP_PWM1_INTSEL_ET_CTRU_CMPB - bool "ctr == compb when counting up" - config BSP_PWM1_INTSEL_ET_CTRD_CMPB - bool "ctr == compb when counting down" - endchoice - - config BSP_PWM1_INTSEL - int - default 0 if BSP_PWM1_INTSEL_ET_DCAEVT1SOC - default 1 if BSP_PWM1_INTSEL_ET_CTR_ZERO - default 2 if BSP_PWM1_INTSEL_ET_CTR_PRD - default 3 if BSP_PWM1_INTSEL_ET_CTR_PRDZERO - default 4 if BSP_PWM1_INTSEL_ET_CTRU_CMPA - default 5 if BSP_PWM1_INTSEL_ET_CTRD_CMPA - default 6 if BSP_PWM1_INTSEL_ET_CTRU_CMPB - default 7 if BSP_PWM1_INTSEL_ET_CTRD_CMPB - choice - prompt "Interrupt generation time" - default BSP_PWM1_INT_ET_1ST - config BSP_PWM1_INT_ET_DISABLE - bool "disable PWM interrupt" - config BSP_PWM1_INT_ET_1ST - bool "generate interrupt at the first time" - config BSP_PWM1_INT_ET_2ND - bool "generate interrupt at the second time" - config BSP_PWM1_INT_ET_3RD - bool "generate interrupt at the third time" - endchoice - config BSP_PWM1_INTPRD - int - default 0 if BSP_PWM1_INT_ET_DISABLE - default 1 if BSP_PWM1_INT_ET_1ST - default 2 if BSP_PWM1_INT_ET_2ND - default 3 if BSP_PWM1_INT_ET_3RD - endif - choice - prompt "HSP Clock division" - default BSP_PWM1_HSPCLKDIV1 - config BSP_PWM1_HSPCLKDIV1 - bool "Clock Divided by 1" - config BSP_PWM1_HSPCLKDIV2 - bool "Clock Divided by 2" - config BSP_PWM1_HSPCLKDIV4 - bool "Clock Divided by 4" - endchoice - config BSP_PWM1_HSPCLKDIV - int - default 0 if BSP_PWM1_HSPCLKDIV1 - default 1 if BSP_PWM1_HSPCLKDIV2 - default 2 if BSP_PWM1_HSPCLKDIV4 - choice - prompt "Clock division" - default BSP_PWM1_CLKDIV1 - config BSP_PWM1_CLKDIV1 - bool "Clock Divided by 1" - config BSP_PWM1_CLKDIV2 - bool "Clock Divided by 2" - config BSP_PWM1_CLKDIV4 - bool "Clock Divided by 4" - endchoice - config BSP_PWM1_CLKDIV - int - default 0 if BSP_PWM1_CLKDIV1 - default 1 if BSP_PWM1_CLKDIV2 - default 2 if BSP_PWM1_CLKDIV4 - choice - default BSP_PWM1_CTR_MODE_UPDOWN - prompt "Select counter mode" - config BSP_PWM1_CTR_MODE_UPDOWN - bool "Up-down mode" - config BSP_PWM1_CTR_MODE_UP - bool "Up mode" - config BSP_PWM1_CTR_MODE_DOWN - bool "Down mode" - config BSP_PWM1_CTR_FREEZE - bool "Freezing Counter" - endchoice - config BSP_PWM1_CTRMODE - int - default 0 if BSP_PWM1_CTR_MODE_UP - default 1 if BSP_PWM1_CTR_MODE_DOWN - default 2 if BSP_PWM1_CTR_MODE_UPDOWN - default 3 if BSP_PWM1_CTR_FREEZE - choice - prompt "Register load mode" - config BSP_PWM1_CC_CTR_ZERO - bool "Load when counter == 0" - config BSP_PWM1_CC_CTR_PRD - bool "Load when counter == prd" - config BSP_PWM1_CC_CTR_ZERO_PRD - bool "load when counter ==0 or counter == prd" - config BSP_PWM1_CC_LD_DISABLE - bool "disable load" - endchoice - - config BSP_PWM1_LOADAMODE - int - default 0 if BSP_PWM1_CC_CTR_ZERO - default 1 if BSP_PWM1_CC_CTR_PRD - default 2 if BSP_PWM1_CC_CTR_ZERO_PRD - default 3 if BSP_PWM1_CC_LD_DISABLE - - config BSP_PWM1_DB - int "Dead time(ns)" - default 100 - range 0 100000 - menuconfig BSP_PWM1_ADC_TRIGGER - bool "Enable ADC trigger from PWM1" - if BSP_PWM1_ADC_TRIGGER - choice - prompt "Select soc triggering time" - default BSP_PWM1_SOCASEL_ET_CTR_ZERO - config BSP_PWM1_SOCASEL_ET_DCAEVT1SOC - bool "DCAEVT1SOC" - config BSP_PWM1_SOCASEL_ET_CTR_ZERO - bool "ctr == zero" - config BSP_PWM1_SOCASEL_ET_CTR_PRD - bool "ctr == prd" - config BSP_PWM1_SOCASEL_ET_CTR_PRDZERO - bool "ctr == prd or ctr == zero" - config BSP_PWM1_SOCASEL_ET_CTRU_CMPA - bool "ctr == compa when counting up" - config BSP_PWM1_SOCASEL_ET_CTRD_CMPA - bool "ctr == compa when counting down" - config BSP_PWM1_SOCASEL_ET_CTRU_CMPB - bool "ctr == compb when counting up" - config BSP_PWM1_SOCASEL_ET_CTRD_CMPB - bool "ctr == compb when counting down" - endchoice - - config BSP_PWM1_SOCASEL - int - default 0 if BSP_PWM1_SOCASEL_ET_DCAEVT1SOC - default 1 if BSP_PWM1_SOCASEL_ET_CTR_ZERO - default 2 if BSP_PWM1_SOCASEL_ET_CTR_PRD - default 3 if BSP_PWM1_SOCASEL_ET_CTR_PRDZERO - default 4 if BSP_PWM1_SOCASEL_ET_CTRU_CMPA - default 5 if BSP_PWM1_SOCASEL_ET_CTRD_CMPA - default 6 if BSP_PWM1_SOCASEL_ET_CTRU_CMPB - default 7 if BSP_PWM1_SOCASEL_ET_CTRD_CMPB - choice - prompt "SOCA generation time" - default BSP_PWM1_SOCA_ET_1ST - config BSP_PWM1_SOCA_ET_DISABLE - bool "disable soc generation" - config BSP_PWM1_SOCA_ET_1ST - bool "generate soc at the first time" - config BSP_PWM1_SOCA_ET_2ND - bool "generate soc at the second time" - config BSP_PWM1_SOCA_ET_3RD - bool "generate soc at the third time" - endchoice - config BSP_PWM1_SOCAPRD - int - default 0 if BSP_PWM1_SOCA_ET_DISABLE - default 1 if BSP_PWM1_SOCA_ET_1ST - default 2 if BSP_PWM1_SOCA_ET_2ND - default 3 if BSP_PWM1_SOCA_ET_3RD - endif - endmenu - endif - menuconfig BSP_USING_PWM2 - bool "Enable ePWM2" - default n - if BSP_USING_PWM2 - menu "Basic settings for PWM2" - config BSP_PWM2_INIT_PERIOD - int "Initial period for PWM2(ns)" - default 10000 - config BSP_PWM2_INIT_PULSE - int "Initial pulse for PWM2(ns)" - default 1000 - endmenu - menu "Advanced Settings for PWM2" - menuconfig BSP_PWM2_PHASE_ENABLE - bool "Enable phase" - default n - if BSP_PWM2_PHASE_ENABLE - choice - prompt "Select master or slave" - default BSP_PWM2_SLAVE - config BSP_PWM2_MASTER - bool "Master" - config BSP_PWM2_SLAVE - bool "Slave" - endchoice - if BSP_PWM2_MASTER - config BSP_PWM2_PHASE - int - default 0 - endif - if BSP_PWM2_SLAVE - config BSP_PWM2_PHASE - int "Phase, 0~360" - range 0 360 - default 0 - help - the phase for PWM2 module - endif - endif - - menuconfig BSP_PWM2_IT_ENABLE - bool "Enable interrupt service" - default n - if BSP_PWM2_IT_ENABLE - choice - prompt "Select interrupt time" - default BSP_PWM2_INTSEL_ET_CTR_ZERO - config BSP_PWM2_INTSEL_ET_DCAEVT1SOC - bool "DCAEVT1SOC" - config BSP_PWM2_INTSEL_ET_CTR_ZERO - bool "ctr == zero" - config BSP_PWM2_INTSEL_ET_CTR_PRD - bool "ctr == prd" - config BSP_PWM2_INTSEL_ET_CTR_PRDZERO - bool "ctr == prd or ctr == zero" - config BSP_PWM2_INTSEL_ET_CTRU_CMPA - bool "ctr == compa when counting up" - config BSP_PWM2_INTSEL_ET_CTRD_CMPA - bool "ctr == compa when counting down" - config BSP_PWM2_INTSEL_ET_CTRU_CMPB - bool "ctr == compb when counting up" - config BSP_PWM2_INTSEL_ET_CTRD_CMPB - bool "ctr == compb when counting down" - endchoice - - config BSP_PWM2_INTSEL - int - default 0 if BSP_PWM2_INTSEL_ET_DCAEVT1SOC - default 1 if BSP_PWM2_INTSEL_ET_CTR_ZERO - default 2 if BSP_PWM2_INTSEL_ET_CTR_PRD - default 3 if BSP_PWM2_INTSEL_ET_CTR_PRDZERO - default 4 if BSP_PWM2_INTSEL_ET_CTRU_CMPA - default 5 if BSP_PWM2_INTSEL_ET_CTRD_CMPA - default 6 if BSP_PWM2_INTSEL_ET_CTRU_CMPB - default 7 if BSP_PWM2_INTSEL_ET_CTRD_CMPB - choice - prompt "Interrupt generation time" - default BSP_PWM2_INT_ET_1ST - config BSP_PWM2_INT_ET_DISABLE - bool "disable PWM interrupt" - config BSP_PWM2_INT_ET_1ST - bool "generate interrupt at the first time" - config BSP_PWM2_INT_ET_2ND - bool "generate interrupt at the second time" - config BSP_PWM2_INT_ET_3RD - bool "generate interrupt at the third time" - endchoice - config BSP_PWM2_INTPRD - int - default 0 if BSP_PWM2_INT_ET_DISABLE - default 1 if BSP_PWM2_INT_ET_1ST - default 2 if BSP_PWM2_INT_ET_2ND - default 3 if BSP_PWM2_INT_ET_3RD - endif - choice - prompt "HSP Clock division" - default BSP_PWM2_HSPCLKDIV1 - config BSP_PWM2_HSPCLKDIV1 - bool "Clock Divided by 1" - config BSP_PWM2_HSPCLKDIV2 - bool "Clock Divided by 2" - config BSP_PWM2_HSPCLKDIV4 - bool "Clock Divided by 4" - endchoice - config BSP_PWM2_HSPCLKDIV - int - default 0 if BSP_PWM2_HSPCLKDIV1 - default 1 if BSP_PWM2_HSPCLKDIV2 - default 2 if BSP_PWM2_HSPCLKDIV4 - choice - prompt "Clock division" - default BSP_PWM2_CLKDIV1 - config BSP_PWM2_CLKDIV1 - bool "Clock Divided by 1" - config BSP_PWM2_CLKDIV2 - bool "Clock Divided by 2" - config BSP_PWM2_CLKDIV4 - bool "Clock Divided by 4" - endchoice - config BSP_PWM2_CLKDIV - int - default 0 if BSP_PWM2_CLKDIV1 - default 1 if BSP_PWM2_CLKDIV2 - default 2 if BSP_PWM2_CLKDIV4 - choice - default BSP_PWM2_CTR_MODE_UPDOWN - prompt "Select counter mode" - config BSP_PWM2_CTR_MODE_UPDOWN - bool "Up-down mode" - config BSP_PWM2_CTR_MODE_UP - bool "Up mode" - config BSP_PWM2_CTR_MODE_DOWN - bool "Down mode" - config BSP_PWM2_CTR_FREEZE - bool "Freezing Counter" - endchoice - config BSP_PWM2_CTRMODE - int - default 0 if BSP_PWM2_CTR_MODE_UP - default 1 if BSP_PWM2_CTR_MODE_DOWN - default 2 if BSP_PWM2_CTR_MODE_UPDOWN - default 3 if BSP_PWM2_CTR_FREEZE - choice - prompt "Register load mode" - config BSP_PWM2_CC_CTR_ZERO - bool "Load when counter == 0" - config BSP_PWM2_CC_CTR_PRD - bool "Load when counter == prd" - config BSP_PWM2_CC_CTR_ZERO_PRD - bool "load when counter ==0 or counter == prd" - config BSP_PWM2_CC_LD_DISABLE - bool "disable load" - endchoice - - config BSP_PWM2_LOADAMODE - int - default 0 if BSP_PWM2_CC_CTR_ZERO - default 1 if BSP_PWM2_CC_CTR_PRD - default 2 if BSP_PWM2_CC_CTR_ZERO_PRD - default 3 if BSP_PWM2_CC_LD_DISABLE - - config BSP_PWM2_DB - int "Dead time(ns)" - default 100 - range 0 100000 - menuconfig BSP_PWM2_ADC_TRIGGER - bool "Enable ADC trigger from PWM2" - if BSP_PWM2_ADC_TRIGGER - choice - prompt "Select soc triggering time" - default BSP_PWM2_SOCASEL_ET_CTR_ZERO - config BSP_PWM2_SOCASEL_ET_DCAEVT1SOC - bool "DCAEVT1SOC" - config BSP_PWM2_SOCASEL_ET_CTR_ZERO - bool "ctr == zero" - config BSP_PWM2_SOCASEL_ET_CTR_PRD - bool "ctr == prd" - config BSP_PWM2_SOCASEL_ET_CTR_PRDZERO - bool "ctr == prd or ctr == zero" - config BSP_PWM2_SOCASEL_ET_CTRU_CMPA - bool "ctr == compa when counting up" - config BSP_PWM2_SOCASEL_ET_CTRD_CMPA - bool "ctr == compa when counting down" - config BSP_PWM2_SOCASEL_ET_CTRU_CMPB - bool "ctr == compb when counting up" - config BSP_PWM2_SOCASEL_ET_CTRD_CMPB - bool "ctr == compb when counting down" - endchoice - - config BSP_PWM2_SOCASEL - int - default 0 if BSP_PWM2_SOCASEL_ET_DCAEVT1SOC - default 1 if BSP_PWM2_SOCASEL_ET_CTR_ZERO - default 2 if BSP_PWM2_SOCASEL_ET_CTR_PRD - default 3 if BSP_PWM2_SOCASEL_ET_CTR_PRDZERO - default 4 if BSP_PWM2_SOCASEL_ET_CTRU_CMPA - default 5 if BSP_PWM2_SOCASEL_ET_CTRD_CMPA - default 6 if BSP_PWM2_SOCASEL_ET_CTRU_CMPB - default 7 if BSP_PWM2_SOCASEL_ET_CTRD_CMPB - choice - prompt "SOCA generation time" - default BSP_PWM2_SOCA_ET_1ST - config BSP_PWM2_SOCA_ET_DISABLE - bool "disable soc generation" - config BSP_PWM2_SOCA_ET_1ST - bool "generate soc at the first time" - config BSP_PWM2_SOCA_ET_2ND - bool "generate soc at the second time" - config BSP_PWM2_SOCA_ET_3RD - bool "generate soc at the third time" - endchoice - config BSP_PWM2_SOCAPRD - int - default 0 if BSP_PWM2_SOCA_ET_DISABLE - default 1 if BSP_PWM2_SOCA_ET_1ST - default 2 if BSP_PWM2_SOCA_ET_2ND - default 3 if BSP_PWM2_SOCA_ET_3RD - endif - endmenu - endif - menuconfig BSP_USING_PWM3 - bool "Enable ePWM3" - default n - if BSP_USING_PWM3 - menu "Basic settings for PWM3" - config BSP_PWM3_INIT_PERIOD - int "Initial period for PWM3(ns)" - default 10000 - config BSP_PWM3_INIT_PULSE - int "Initial pulse for PWM3(ns)" - default 1000 - endmenu - menu "Advanced Settings for PWM3" - menuconfig BSP_PWM3_PHASE_ENABLE - bool "Enable phase" - default n - if BSP_PWM3_PHASE_ENABLE - choice - prompt "Select master or slave" - default BSP_PWM3_SLAVE - config BSP_PWM3_MASTER - bool "Master" - config BSP_PWM3_SLAVE - bool "Slave" - endchoice - if BSP_PWM3_MASTER - config BSP_PWM3_PHASE - int - default 0 - endif - if BSP_PWM3_SLAVE - config BSP_PWM3_PHASE - int "Phase, 0~360" - range 0 360 - default 0 - help - the phase for PWM3 module - endif - endif - - menuconfig BSP_PWM3_IT_ENABLE - bool "Enable interrupt service" - default n - if BSP_PWM3_IT_ENABLE - choice - prompt "Select interrupt time" - default BSP_PWM3_INTSEL_ET_CTR_ZERO - config BSP_PWM3_INTSEL_ET_DCAEVT1SOC - bool "DCAEVT1SOC" - config BSP_PWM3_INTSEL_ET_CTR_ZERO - bool "ctr == zero" - config BSP_PWM3_INTSEL_ET_CTR_PRD - bool "ctr == prd" - config BSP_PWM3_INTSEL_ET_CTR_PRDZERO - bool "ctr == prd or ctr == zero" - config BSP_PWM3_INTSEL_ET_CTRU_CMPA - bool "ctr == compa when counting up" - config BSP_PWM3_INTSEL_ET_CTRD_CMPA - bool "ctr == compa when counting down" - config BSP_PWM3_INTSEL_ET_CTRU_CMPB - bool "ctr == compb when counting up" - config BSP_PWM3_INTSEL_ET_CTRD_CMPB - bool "ctr == compb when counting down" - endchoice - - config BSP_PWM3_INTSEL - int - default 0 if BSP_PWM3_INTSEL_ET_DCAEVT1SOC - default 1 if BSP_PWM3_INTSEL_ET_CTR_ZERO - default 2 if BSP_PWM3_INTSEL_ET_CTR_PRD - default 3 if BSP_PWM3_INTSEL_ET_CTR_PRDZERO - default 4 if BSP_PWM3_INTSEL_ET_CTRU_CMPA - default 5 if BSP_PWM3_INTSEL_ET_CTRD_CMPA - default 6 if BSP_PWM3_INTSEL_ET_CTRU_CMPB - default 7 if BSP_PWM3_INTSEL_ET_CTRD_CMPB - choice - prompt "Interrupt generation time" - default BSP_PWM3_INT_ET_1ST - config BSP_PWM3_INT_ET_DISABLE - bool "disable PWM interrupt" - config BSP_PWM3_INT_ET_1ST - bool "generate interrupt at the first time" - config BSP_PWM3_INT_ET_2ND - bool "generate interrupt at the second time" - config BSP_PWM3_INT_ET_3RD - bool "generate interrupt at the third time" - endchoice - config BSP_PWM3_INTPRD - int - default 0 if BSP_PWM3_INT_ET_DISABLE - default 1 if BSP_PWM3_INT_ET_1ST - default 2 if BSP_PWM3_INT_ET_2ND - default 3 if BSP_PWM3_INT_ET_3RD - endif - choice - prompt "HSP Clock division" - default BSP_PWM3_HSPCLKDIV1 - config BSP_PWM3_HSPCLKDIV1 - bool "Clock Divided by 1" - config BSP_PWM3_HSPCLKDIV2 - bool "Clock Divided by 2" - config BSP_PWM3_HSPCLKDIV4 - bool "Clock Divided by 4" - endchoice - config BSP_PWM3_HSPCLKDIV - int - default 0 if BSP_PWM3_HSPCLKDIV1 - default 1 if BSP_PWM3_HSPCLKDIV2 - default 2 if BSP_PWM3_HSPCLKDIV4 - choice - prompt "Clock division" - default BSP_PWM3_CLKDIV1 - config BSP_PWM3_CLKDIV1 - bool "Clock Divided by 1" - config BSP_PWM3_CLKDIV2 - bool "Clock Divided by 2" - config BSP_PWM3_CLKDIV4 - bool "Clock Divided by 4" - endchoice - config BSP_PWM3_CLKDIV - int - default 0 if BSP_PWM3_CLKDIV1 - default 1 if BSP_PWM3_CLKDIV2 - default 2 if BSP_PWM3_CLKDIV4 - choice - default BSP_PWM3_CTR_MODE_UPDOWN - prompt "Select counter mode" - config BSP_PWM3_CTR_MODE_UPDOWN - bool "Up-down mode" - config BSP_PWM3_CTR_MODE_UP - bool "Up mode" - config BSP_PWM3_CTR_MODE_DOWN - bool "Down mode" - config BSP_PWM3_CTR_FREEZE - bool "Freezing Counter" - endchoice - config BSP_PWM3_CTRMODE - int - default 0 if BSP_PWM3_CTR_MODE_UP - default 1 if BSP_PWM3_CTR_MODE_DOWN - default 2 if BSP_PWM3_CTR_MODE_UPDOWN - default 3 if BSP_PWM3_CTR_FREEZE - choice - prompt "Register load mode" - config BSP_PWM3_CC_CTR_ZERO - bool "Load when counter == 0" - config BSP_PWM3_CC_CTR_PRD - bool "Load when counter == prd" - config BSP_PWM3_CC_CTR_ZERO_PRD - bool "load when counter ==0 or counter == prd" - config BSP_PWM3_CC_LD_DISABLE - bool "disable load" - endchoice - - config BSP_PWM3_LOADAMODE - int - default 0 if BSP_PWM3_CC_CTR_ZERO - default 1 if BSP_PWM3_CC_CTR_PRD - default 2 if BSP_PWM3_CC_CTR_ZERO_PRD - default 3 if BSP_PWM3_CC_LD_DISABLE - - config BSP_PWM3_DB - int "Dead time(ns)" - default 100 - range 0 100000 - menuconfig BSP_PWM3_ADC_TRIGGER - bool "Enable ADC trigger from PWM3" - if BSP_PWM3_ADC_TRIGGER - choice - prompt "Select soc triggering time" - default BSP_PWM3_SOCASEL_ET_CTR_ZERO - config BSP_PWM3_SOCASEL_ET_DCAEVT1SOC - bool "DCAEVT1SOC" - config BSP_PWM3_SOCASEL_ET_CTR_ZERO - bool "ctr == zero" - config BSP_PWM3_SOCASEL_ET_CTR_PRD - bool "ctr == prd" - config BSP_PWM3_SOCASEL_ET_CTR_PRDZERO - bool "ctr == prd or ctr == zero" - config BSP_PWM3_SOCASEL_ET_CTRU_CMPA - bool "ctr == compa when counting up" - config BSP_PWM3_SOCASEL_ET_CTRD_CMPA - bool "ctr == compa when counting down" - config BSP_PWM3_SOCASEL_ET_CTRU_CMPB - bool "ctr == compb when counting up" - config BSP_PWM3_SOCASEL_ET_CTRD_CMPB - bool "ctr == compb when counting down" - endchoice - - config BSP_PWM3_SOCASEL - int - default 0 if BSP_PWM3_SOCASEL_ET_DCAEVT1SOC - default 1 if BSP_PWM3_SOCASEL_ET_CTR_ZERO - default 2 if BSP_PWM3_SOCASEL_ET_CTR_PRD - default 3 if BSP_PWM3_SOCASEL_ET_CTR_PRDZERO - default 4 if BSP_PWM3_SOCASEL_ET_CTRU_CMPA - default 5 if BSP_PWM3_SOCASEL_ET_CTRD_CMPA - default 6 if BSP_PWM3_SOCASEL_ET_CTRU_CMPB - default 7 if BSP_PWM3_SOCASEL_ET_CTRD_CMPB - choice - prompt "SOCA generation time" - default BSP_PWM3_SOCA_ET_1ST - config BSP_PWM3_SOCA_ET_DISABLE - bool "disable soc generation" - config BSP_PWM3_SOCA_ET_1ST - bool "generate soc at the first time" - config BSP_PWM3_SOCA_ET_2ND - bool "generate soc at the second time" - config BSP_PWM3_SOCA_ET_3RD - bool "generate soc at the third time" - endchoice - config BSP_PWM3_SOCAPRD - int - default 0 if BSP_PWM3_SOCA_ET_DISABLE - default 1 if BSP_PWM3_SOCA_ET_1ST - default 2 if BSP_PWM3_SOCA_ET_2ND - default 3 if BSP_PWM3_SOCA_ET_3RD - endif - endmenu - endif - menuconfig BSP_USING_PWM4 - bool "Enable ePWM4" - default n - if BSP_USING_PWM4 - menu "Basic settings for PWM4" - config BSP_PWM4_INIT_PERIOD - int "Initial period for PWM4(ns)" - default 10000 - config BSP_PWM4_INIT_PULSE - int "Initial pulse for PWM4(ns)" - default 1000 - endmenu - menu "Advanced Settings for PWM4" - menuconfig BSP_PWM4_PHASE_ENABLE - bool "Enable phase" - default n - if BSP_PWM4_PHASE_ENABLE - choice - prompt "Select master or slave" - default BSP_PWM4_SLAVE - config BSP_PWM4_MASTER - bool "Master" - config BSP_PWM4_SLAVE - bool "Slave" - endchoice - if BSP_PWM4_MASTER - config BSP_PWM4_PHASE - int - default 0 - endif - if BSP_PWM4_SLAVE - config BSP_PWM4_PHASE - int "Phase, 0~360" - range 0 360 - default 0 - help - the phase for PWM4 module - endif - endif - - menuconfig BSP_PWM4_IT_ENABLE - bool "Enable interrupt service" - default n - if BSP_PWM4_IT_ENABLE - choice - prompt "Select interrupt time" - default BSP_PWM4_INTSEL_ET_CTR_ZERO - config BSP_PWM4_INTSEL_ET_DCAEVT1SOC - bool "DCAEVT1SOC" - config BSP_PWM4_INTSEL_ET_CTR_ZERO - bool "ctr == zero" - config BSP_PWM4_INTSEL_ET_CTR_PRD - bool "ctr == prd" - config BSP_PWM4_INTSEL_ET_CTR_PRDZERO - bool "ctr == prd or ctr == zero" - config BSP_PWM4_INTSEL_ET_CTRU_CMPA - bool "ctr == compa when counting up" - config BSP_PWM4_INTSEL_ET_CTRD_CMPA - bool "ctr == compa when counting down" - config BSP_PWM4_INTSEL_ET_CTRU_CMPB - bool "ctr == compb when counting up" - config BSP_PWM4_INTSEL_ET_CTRD_CMPB - bool "ctr == compb when counting down" - endchoice - - config BSP_PWM4_INTSEL - int - default 0 if BSP_PWM4_INTSEL_ET_DCAEVT1SOC - default 1 if BSP_PWM4_INTSEL_ET_CTR_ZERO - default 2 if BSP_PWM4_INTSEL_ET_CTR_PRD - default 3 if BSP_PWM4_INTSEL_ET_CTR_PRDZERO - default 4 if BSP_PWM4_INTSEL_ET_CTRU_CMPA - default 5 if BSP_PWM4_INTSEL_ET_CTRD_CMPA - default 6 if BSP_PWM4_INTSEL_ET_CTRU_CMPB - default 7 if BSP_PWM4_INTSEL_ET_CTRD_CMPB - choice - prompt "Interrupt generation time" - default BSP_PWM4_INT_ET_1ST - config BSP_PWM4_INT_ET_DISABLE - bool "disable PWM interrupt" - config BSP_PWM4_INT_ET_1ST - bool "generate interrupt at the first time" - config BSP_PWM4_INT_ET_2ND - bool "generate interrupt at the second time" - config BSP_PWM4_INT_ET_3RD - bool "generate interrupt at the third time" - endchoice - config BSP_PWM4_INTPRD - int - default 0 if BSP_PWM4_INT_ET_DISABLE - default 1 if BSP_PWM4_INT_ET_1ST - default 2 if BSP_PWM4_INT_ET_2ND - default 3 if BSP_PWM4_INT_ET_3RD - endif - choice - prompt "HSP Clock division" - default BSP_PWM4_HSPCLKDIV1 - config BSP_PWM4_HSPCLKDIV1 - bool "Clock Divided by 1" - config BSP_PWM4_HSPCLKDIV2 - bool "Clock Divided by 2" - config BSP_PWM4_HSPCLKDIV4 - bool "Clock Divided by 4" - endchoice - config BSP_PWM4_HSPCLKDIV - int - default 0 if BSP_PWM4_HSPCLKDIV1 - default 1 if BSP_PWM4_HSPCLKDIV2 - default 2 if BSP_PWM4_HSPCLKDIV4 - choice - prompt "Clock division" - default BSP_PWM4_CLKDIV1 - config BSP_PWM4_CLKDIV1 - bool "Clock Divided by 1" - config BSP_PWM4_CLKDIV2 - bool "Clock Divided by 2" - config BSP_PWM4_CLKDIV4 - bool "Clock Divided by 4" - endchoice - config BSP_PWM4_CLKDIV - int - default 0 if BSP_PWM4_CLKDIV1 - default 1 if BSP_PWM4_CLKDIV2 - default 2 if BSP_PWM4_CLKDIV4 - choice - default BSP_PWM4_CTR_MODE_UPDOWN - prompt "Select counter mode" - config BSP_PWM4_CTR_MODE_UPDOWN - bool "Up-down mode" - config BSP_PWM4_CTR_MODE_UP - bool "Up mode" - config BSP_PWM4_CTR_MODE_DOWN - bool "Down mode" - config BSP_PWM4_CTR_FREEZE - bool "Freezing Counter" - endchoice - config BSP_PWM4_CTRMODE - int - default 0 if BSP_PWM4_CTR_MODE_UP - default 1 if BSP_PWM4_CTR_MODE_DOWN - default 2 if BSP_PWM4_CTR_MODE_UPDOWN - default 3 if BSP_PWM4_CTR_FREEZE - choice - prompt "Register load mode" - config BSP_PWM4_CC_CTR_ZERO - bool "Load when counter == 0" - config BSP_PWM4_CC_CTR_PRD - bool "Load when counter == prd" - config BSP_PWM4_CC_CTR_ZERO_PRD - bool "load when counter ==0 or counter == prd" - config BSP_PWM4_CC_LD_DISABLE - bool "disable load" - endchoice - - config BSP_PWM4_LOADAMODE - int - default 0 if BSP_PWM4_CC_CTR_ZERO - default 1 if BSP_PWM4_CC_CTR_PRD - default 2 if BSP_PWM4_CC_CTR_ZERO_PRD - default 3 if BSP_PWM4_CC_LD_DISABLE - - config BSP_PWM4_DB - int "Dead time(ns)" - default 100 - range 0 100000 - menuconfig BSP_PWM4_ADC_TRIGGER - bool "Enable ADC trigger from PWM4" - if BSP_PWM4_ADC_TRIGGER - choice - prompt "Select soc triggering time" - default BSP_PWM4_SOCASEL_ET_CTR_ZERO - config BSP_PWM4_SOCASEL_ET_DCAEVT1SOC - bool "DCAEVT1SOC" - config BSP_PWM4_SOCASEL_ET_CTR_ZERO - bool "ctr == zero" - config BSP_PWM4_SOCASEL_ET_CTR_PRD - bool "ctr == prd" - config BSP_PWM4_SOCASEL_ET_CTR_PRDZERO - bool "ctr == prd or ctr == zero" - config BSP_PWM4_SOCASEL_ET_CTRU_CMPA - bool "ctr == compa when counting up" - config BSP_PWM4_SOCASEL_ET_CTRD_CMPA - bool "ctr == compa when counting down" - config BSP_PWM4_SOCASEL_ET_CTRU_CMPB - bool "ctr == compb when counting up" - config BSP_PWM4_SOCASEL_ET_CTRD_CMPB - bool "ctr == compb when counting down" - endchoice - - config BSP_PWM4_SOCASEL - int - default 0 if BSP_PWM4_SOCASEL_ET_DCAEVT1SOC - default 1 if BSP_PWM4_SOCASEL_ET_CTR_ZERO - default 2 if BSP_PWM4_SOCASEL_ET_CTR_PRD - default 3 if BSP_PWM4_SOCASEL_ET_CTR_PRDZERO - default 4 if BSP_PWM4_SOCASEL_ET_CTRU_CMPA - default 5 if BSP_PWM4_SOCASEL_ET_CTRD_CMPA - default 6 if BSP_PWM4_SOCASEL_ET_CTRU_CMPB - default 7 if BSP_PWM4_SOCASEL_ET_CTRD_CMPB - choice - prompt "SOCA generation time" - default BSP_PWM4_SOCA_ET_1ST - config BSP_PWM4_SOCA_ET_DISABLE - bool "disable soc generation" - config BSP_PWM4_SOCA_ET_1ST - bool "generate soc at the first time" - config BSP_PWM4_SOCA_ET_2ND - bool "generate soc at the second time" - config BSP_PWM4_SOCA_ET_3RD - bool "generate soc at the third time" - endchoice - config BSP_PWM4_SOCAPRD - int - default 0 if BSP_PWM4_SOCA_ET_DISABLE - default 1 if BSP_PWM4_SOCA_ET_1ST - default 2 if BSP_PWM4_SOCA_ET_2ND - default 3 if BSP_PWM4_SOCA_ET_3RD - endif - endmenu - endif - endif - - menuconfig BSP_USING_ADC - bool "Enable ADC" - default n - select RT_USING_ADC - if BSP_USING_ADC - config BSP_USING_ADC1 - bool "Enable ADC1" - default n - endif - - menuconfig BSP_USING_ONCHIP_RTC - bool "Enable RTC" - select RT_USING_RTC - default n - if BSP_USING_ONCHIP_RTC - choice - prompt "Select clock source" - default BSP_RTC_USING_LSE - - config BSP_RTC_USING_LSE - bool "RTC USING LSE" - - config BSP_RTC_USING_LSI - bool "RTC USING LSI" - endchoice - endif - - config BSP_USING_WDT - bool "Enable Watchdog Timer" - select RT_USING_WDT - default n - - config BSP_USING_SDIO - bool "Enable SDIO" - select RT_USING_SDIO - select RT_USING_DFS - default n - - menuconfig BSP_USING_CAN - bool "Enable CAN" - default n - select RT_USING_CAN - if BSP_USING_CAN - config BSP_USING_CAN1 - bool "using CAN1" - default n - endif - - config BSP_USING_USBD - bool "Enable USB device" - select RT_USING_USB_DEVICE - default n - if BSP_USING_USBD - config BSP_USB_CONNECT_PIN - int "USB connect pin" - default 67 - - config BSP_USB_PULL_UP_STATUS - int "USB PULL UP STATUS" - default 0 - endif -endmenu - -menu "Board extended module Drivers" - -endmenu - -endmenu diff --git a/bsp/c28x/tms320f28379d/board/board.c b/bsp/c28x/tms320f28379d/board/board.c deleted file mode 100644 index c391a2589e..0000000000 --- a/bsp/c28x/tms320f28379d/board/board.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-09-22 Bernard add board.h to this bsp - * 2018-09-02 xuzhuoyi modify for TMS320F28379D version - * 2022-06-21 guyunjie fix bugs in trap_rtosint and enable interrupt nesting - * 2022-08-21 yuqi adding onboard devices initialization code - */ -#include -#include "board.h" -#include "drv_sci.h" -#include "drv_gpio.h" -#include "F28x_Project.h" - -#ifndef RT_USING_SMP -extern volatile rt_uint8_t rt_interrupt_nest; -#endif - -extern rt_uint32_t rt_thread_switch_interrupt_flag; - -extern interrupt void RTOSINT_Handler(); -void trap_rtosint() -{ - if(rt_thread_switch_interrupt_flag) - { - /* only do pendsv at the end of the last level of interrupt nesting, - * so that threads do not preempt any isrs. */ - if(rt_interrupt_nest == 1) - { - /* rt_interrupt_leave_hook is called before rt_interrupt_nest -- - * in rt_interrupt_leave. We need to do this manually here to indicate - * that all isrs have been cleared before we switch to thread. */ - rt_interrupt_nest --; - asm(" trap #16"); - /* increment rt_interrupt_nest to compensate for the previous decrement. */ - rt_interrupt_nest ++; - } - } -} - -/** - * This is the timer interrupt service routine. - * - */ -interrupt void cpu_timer2_isr(void) -{ - CpuTimer2Regs.TCR.all = 0xC000; - - ALLOW_ISR_PREEMPT(); - - /* enter interrupt */ - rt_interrupt_enter(); - - rt_tick_increase(); - /* leave interrupt */ - rt_interrupt_leave(); -} - -extern interrupt void XINT1_Handler(void); -extern interrupt void XINT2_Handler(void); -/** - * This function will initial TMS320F28379D board. - */ -void rt_hw_board_init() -{ - /* Configure the system clock @ 84 Mhz */ - InitSysCtrl(); - - DINT; - InitPieCtrl(); - - IER = 0x0000; - IFR = 0x0000; - - InitPieVectTable(); - -#ifdef _FLASH - memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (Uint32)&RamfuncsLoadSize); - InitFlash(); -#endif - EALLOW; // This is needed to write to EALLOW protected registers - PieVectTable.TIMER2_INT = &cpu_timer2_isr; - PieVectTable.RTOS_INT = &RTOSINT_Handler; - -#ifdef BSP_USING_XINT1 - PieVectTable.XINT1_INT = &XINT1_Handler; -#endif -#ifdef BSP_USING_XINT2 - PieVectTable.XINT2_INT = &XINT2_Handler; -#endif -#ifdef BSP_USING_XINT3 - PieVectTable.XINT3_INT = &XINT3_Handler; -#endif -#ifdef BSP_USING_XINT4 - PieVectTable.XINT4_INT = &XINT4_Handler; -#endif -#ifdef BSP_USING_XINT5 - PieVectTable.XINT5_INT = &XINT5_Handler; -#endif - EDIS; - - InitCpuTimers(); - ConfigCpuTimer(&CpuTimer2, 200, 1000000 / RT_TICK_PER_SECOND); - CpuTimer2Regs.TCR.all = 0x4000; - IER |= M_INT14; - IER |= M_INT1; - -#ifdef RT_USING_HEAP - rt_system_heap_init(&__ebss_end, &(__heap_end)); -#endif - -#ifdef RT_USING_SERIAL - rt_hw_sci_init(); -#endif - -#ifdef RT_USING_PIN - rt_hw_pin_init(); -#endif - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif -#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif - - rt_interrupt_leave_sethook((void (*)(void))trap_rtosint); -} - -int _args_main() -{ - /* _args_main is the entry point called by _c_int00. We define it - * here to override the one defined by the compiler in args_main.c */ - - extern int rtthread_startup(); - - /* startup RT-Thread RTOS */ - rtthread_startup(); - /* never reach here*/ - return 0; -} diff --git a/bsp/c28x/tms320f28379d/board/board.h b/bsp/c28x/tms320f28379d/board/board.h deleted file mode 100644 index 1cf7ac7134..0000000000 --- a/bsp/c28x/tms320f28379d/board/board.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-09-22 Bernard add board.h to this bsp - * 2018-09-02 xuzhuoyi modify for TMS320F28379D version - */ - -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include - - -extern int __ebss_end; -extern int __heap_end; - -extern void rt_hw_board_init(void); - -#endif - diff --git a/bsp/c28x/tms320f28379d/figures/build.png b/bsp/c28x/tms320f28379d/figures/build.png deleted file mode 100644 index 4f6db2913d..0000000000 Binary files a/bsp/c28x/tms320f28379d/figures/build.png and /dev/null differ diff --git a/bsp/c28x/tms320f28379d/figures/debug_as.png b/bsp/c28x/tms320f28379d/figures/debug_as.png deleted file mode 100644 index 6a2abb3119..0000000000 Binary files a/bsp/c28x/tms320f28379d/figures/debug_as.png and /dev/null differ diff --git a/bsp/c28x/tms320f28379d/figures/import.png b/bsp/c28x/tms320f28379d/figures/import.png deleted file mode 100644 index db7c314b67..0000000000 Binary files a/bsp/c28x/tms320f28379d/figures/import.png and /dev/null differ diff --git a/bsp/c28x/tms320f28379d/figures/import_dia.png b/bsp/c28x/tms320f28379d/figures/import_dia.png deleted file mode 100644 index 8098424824..0000000000 Binary files a/bsp/c28x/tms320f28379d/figures/import_dia.png and /dev/null differ diff --git a/bsp/c28x/tms320f28379d/figures/launch-28379d.png b/bsp/c28x/tms320f28379d/figures/launch-28379d.png deleted file mode 100644 index 6db1ebdae0..0000000000 Binary files a/bsp/c28x/tms320f28379d/figures/launch-28379d.png and /dev/null differ diff --git a/bsp/c28x/tms320f28379d/figures/launching.png b/bsp/c28x/tms320f28379d/figures/launching.png deleted file mode 100644 index 832c6687ce..0000000000 Binary files a/bsp/c28x/tms320f28379d/figures/launching.png and /dev/null differ diff --git a/bsp/c28x/tms320f28379d/rtconfig.h b/bsp/c28x/tms320f28379d/rtconfig.h deleted file mode 100644 index fc87483220..0000000000 --- a/bsp/c28x/tms320f28379d/rtconfig.h +++ /dev/null @@ -1,195 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -#define SOC_TMS320F28X - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 8 -#define RT_ALIGN_SIZE 4 -#define RT_THREAD_PRIORITY_8 -#define RT_THREAD_PRIORITY_MAX 8 -#define RT_TICK_PER_SECOND 100 -#define RT_USING_HOOK -#define RT_HOOK_USING_FUNC_PTR -#define RT_USING_IDLE_HOOK -#define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 1024 - -/* kservice optimization */ - -#define RT_DEBUG -#define RT_DEBUG_COLOR - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_SMALL_MEM_AS_HEAP -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "scia" -#define RT_VER_NUM 0x50000 -#define ARCH_TIDSP -#define ARCH_TIDSP_C28X -#define ARCH_CPU_STACK_GROWS_UPWARD - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 4 -#define RT_USING_MSH -#define RT_USING_FINSH -#define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 4 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_CMD_SIZE 80 -#define MSH_USING_BUILT_IN_COMMANDS -#define FINSH_USING_DESCRIPTION -#define FINSH_ARG_MAX 10 - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_USING_SERIAL -#define RT_USING_SERIAL_V1 -#define RT_SERIAL_RB_BUFSZ 64 -#define RT_USING_PIN -#define RT_USING_PWM - -/* Using USB */ - - -/* C/C++ and POSIX layer */ - -#define RT_LIBC_DEFAULT_TIMEZONE 8 - -/* POSIX (Portable Operating System Interface) layer */ - - -/* Interprocess Communication (IPC) */ - - -/* Socket is in the 'Network' category */ - - -/* Network */ - - -/* Utilities */ - - -/* RT-Thread Utestcases */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - -/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ - - -/* XML: Extensible Markup Language */ - - -/* multimedia packages */ - -/* LVGL: powerful and easy-to-use embedded GUI library */ - - -/* u8g2: a monochrome graphic library */ - - -/* PainterEngine: A cross-platform graphics application framework written in C language */ - - -/* tools packages */ - - -/* system packages */ - -/* enhanced kernel services */ - - -/* acceleration: Assembly language or algorithmic acceleration packages */ - - -/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ - - -/* Micrium: Micrium software products porting for RT-Thread */ - - -/* peripheral libraries and drivers */ - - -/* Kendryte SDK */ - - -/* AI packages */ - - -/* miscellaneous packages */ - -/* project laboratory */ - -/* samples: kernel and components samples */ - - -/* entertainment: terminal games and other interesting software packages */ - - -/* Hardware Drivers Config */ - -/* Onboard Peripheral Drivers */ - -/* On-chip Peripheral Drivers */ - -#define BSP_USING_GPIO -#define BSP_USING_UART -#define BSP_USING_UART1 - -/* Board extended module Drivers */ - -#include "rtconfig_project.h" - -#endif diff --git a/bsp/c28x/tms320f28379d/rtconfig_project.h b/bsp/c28x/tms320f28379d/rtconfig_project.h deleted file mode 100644 index fb6a3dffbb..0000000000 --- a/bsp/c28x/tms320f28379d/rtconfig_project.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2019-03-27 xuzhuoyi the first version - * 2022-08-22 guyunjie remove data types other than 8bit for compatibility with libc - */ - -#ifndef __RTCONFIG_PROJECT_H__ -#define __RTCONFIG_PROJECT_H__ - -/* C28X does not support 8bit data type by hardward (char = 16bit) so - * 8bit data types are not defined in its standard libs. We define them - * here. Be careful that the 8bit is actually 16bit. */ -#define UINT8_MAX 0xff /**< Maximum number of UINT8 */ -typedef signed char int8_t; /**< 8bit integer type */ -typedef unsigned char uint8_t; /**< 8bit unsigned integer type */ - -/* C28X automatically disable interrupt in interrupt service routine. - * We need to enable manually to allow for interrupt nesting by calling - * this macro at the start of preemptible interrupt service routines*/ -#define ALLOW_ISR_PREEMPT() __asm(" CLRC INTM") - -#endif diff --git a/bsp/c28x/tms320f28379d/targetConfigs/TMS320F28379D.ccxml b/bsp/c28x/tms320f28379d/targetConfigs/TMS320F28379D.ccxml deleted file mode 100644 index 42eb492f1f..0000000000 --- a/bsp/c28x/tms320f28379d/targetConfigs/TMS320F28379D.ccxml +++ /dev/null @@ -1,22 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - diff --git a/bsp/c28x/tms320f28379d/targetConfigs/readme.txt b/bsp/c28x/tms320f28379d/targetConfigs/readme.txt deleted file mode 100644 index d783fef4d6..0000000000 --- a/bsp/c28x/tms320f28379d/targetConfigs/readme.txt +++ /dev/null @@ -1,9 +0,0 @@ -The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based -on the device and connection settings specified in your project on the Properties > General page. - -Please note that in automatic target-configuration management, changes to the project's device and/or -connection settings will either modify an existing or generate a new target-configuration file. Thus, -if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, -you may create your own target-configuration file for this project and manage it manually. You can -always switch back to automatic target-configuration management by checking the "Manage the project's -target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/bsp/ti/c28x/libraries/HAL_Drivers/config/adc_config.h b/bsp/ti/c28x/libraries/HAL_Drivers/config/adc_config.h new file mode 100644 index 0000000000..72da2569a5 --- /dev/null +++ b/bsp/ti/c28x/libraries/HAL_Drivers/config/adc_config.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-07 qiyu first version + */ + +#ifndef DRIVERS_CONFIG_ADC_CONFIG_H_ +#define DRIVERS_CONFIG_ADC_CONFIG_H_ +#include "F28x_Project.h" // Device Headerfile and Examples Include File +#include "F2837xD_adc.h" +#include "rtthread.h" +#include "drv_config.h" +#define BSP_USING_ADC1 +#ifdef __cplusplus +extern "C" { +#endif +#ifdef BSP_USING_ADC1 + #ifndef ADC1_CONFIG + #define ADC1_CONFIG \ + { \ + .name = "adc1", \ + .adc_regs = &AdcaRegs, \ + .adc_results = &AdcaResultRegs, \ + } + #endif +#endif +#ifdef BSP_USING_ADC2 + #ifndef ADC2_CONFIG + #define ADC2_CONFIG \ + { \ + .name = "adc2", \ + .adc_regs = &AdcbRegs, \ + .adc_results = &AdcbResultRegs \ + } + #endif +#endif +#ifdef BSP_USING_ADC3 + #ifndef ADC3_CONFIG + #define ADC3_CONFIG \ + { \ + .name = "adc3", \ + .adc_regs = &AdccRegs, \ + .adc_results = &AdccResultRegs \ + } + #endif +#endif +#ifdef __cplusplus +} +#endif +#endif /* DRIVERS_CONFIG_ADC_CONFIG_H_ */ diff --git a/bsp/ti/c28x/libraries/HAL_Drivers/config/pwm_config.h b/bsp/ti/c28x/libraries/HAL_Drivers/config/pwm_config.h new file mode 100644 index 0000000000..d490cb4d71 --- /dev/null +++ b/bsp/ti/c28x/libraries/HAL_Drivers/config/pwm_config.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-09-21 yuqi created + */ + +#ifndef DRIVERS_CONFIG_PWM_CONFIG_H_ +#define DRIVERS_CONFIG_PWM_CONFIG_H_ +#include "F28x_Project.h" // Device Headerfile and Examples Include File +#include "F2837xD_epwm.h" +#include "rtthread.h" +#include "drv_config.h" + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef BSP_USING_PWM1 + #ifndef PWM1_CONFIG + #define PWM1_CONFIG \ + { \ + .name = "pwm1", \ + .pwm_regs = &EPwm1Regs, \ + } + #endif +#endif +#ifdef BSP_USING_PWM2 + #ifndef PWM2_CONFIG + #define PWM2_CONFIG \ + { \ + .name = "pwm2", \ + .pwm_regs = &EPwm2Regs, \ + } + #endif +#endif +#ifdef BSP_USING_PWM3 + #ifndef PWM3_CONFIG + #define PWM3_CONFIG \ + { \ + .name = "pwm3", \ + .pwm_regs = &EPwm3Regs, \ + } + #endif +#endif +#ifdef BSP_USING_PWM4 + #ifndef PWM4_CONFIG + #define PWM4_CONFIG \ + { \ + .name = "pwm4", \ + .pwm_regs = &EPwm4Regs, \ + } + #endif +#endif + +#define TZ_OFF 2 +#define TZ_ON 1 +#ifdef __cplusplus +} +#endif + + +#define RT_SHADOW_MODE CC_SHADOW +#define RT_LOAD_TIME CC_CTR_ZERO +#define RT_CTRMODE TB_COUNT_UPDOWN +#endif /* DRIVERS_CONFIG_PWM_CONFIG_H_ */ + diff --git a/bsp/ti/c28x/libraries/HAL_Drivers/drv_adc.c b/bsp/ti/c28x/libraries/HAL_Drivers/drv_adc.c new file mode 100644 index 0000000000..fb6b0250c6 --- /dev/null +++ b/bsp/ti/c28x/libraries/HAL_Drivers/drv_adc.c @@ -0,0 +1,229 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-07 qiyu first version + */ + +#include +#ifdef BSP_USING_ADC +#include "drv_config.h" + +#include "drv_adc.h" +#include "rtdbg.h" + + +static struct c28x_adc c28x_adc_obj[] = +{ +#ifdef BSP_USING_ADC1 + ADC1_CONFIG, +#endif + +#ifdef BSP_USING_ADC2 + ADC2_CONFIG, +#endif + +#ifdef BSP_USING_ADC3 + ADC3_CONFIG, +#endif +}; + + +static rt_err_t c28x_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled) +{ + volatile struct ADC_REGS *c28x_adc_regs; + RT_ASSERT(device != RT_NULL); + volatile struct c28x_adc *c28x_adc_handler; + c28x_adc_handler = (struct c28x_adc *)device->parent.user_data; + c28x_adc_regs = c28x_adc_handler->adc_regs; + + if (enabled) + { + /* + * power up the ADC + */ + EALLOW; + c28x_adc_regs->ADCCTL1.bit.ADCPWDNZ = 1; + EDIS; + /* + * delay for 1ms to allow ADC time to power up + */ + DELAY_US(1000); + } + else + { + /* + * power down the ADC + */ + EALLOW; + c28x_adc_regs->ADCCTL1.bit.ADCPWDNZ = 0; + EDIS; + } + + return RT_EOK; +} + +static rt_uint8_t c28x_adc_get_resolution(struct rt_adc_device *device) +{ + struct c28x_adc *c28x_adc_handler; + volatile struct ADC_REGS *c28x_adc_regs; + c28x_adc_handler = (struct c28x_adc *)device->parent.user_data; + c28x_adc_regs = c28x_adc_handler->adc_regs; + RT_ASSERT(device != RT_NULL); + switch(c28x_adc_regs->ADCCTL2.bit.RESOLUTION) + { + case ADC_RESOLUTION_12BIT: + return 12; + case ADC_RESOLUTION_16BIT: + return 16; + default: + return 0; + } +} + +static rt_int16_t c28x_adc_get_vref (struct rt_adc_device *device) +{ + /* + * TODO + * Get Vref + */ + RT_ASSERT(device); + return 3300; +} + +static rt_err_t c28x_adc_get_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(value != RT_NULL); + + struct c28x_adc *c28x_adc_handler = (struct c28x_adc*)device->parent.user_data; + volatile struct ADC_REGS *c28x_adc_regs = c28x_adc_handler->adc_regs; + volatile struct ADC_RESULT_REGS *c28x_adc_result_regs = c28x_adc_handler->adc_results; + + /* + * configure channel + * only use SOC0 for now + */ + EALLOW; + c28x_adc_regs->ADCSOC0CTL.bit.CHSEL = channel; /* SOC0 will convert pin A0 */ + EDIS; + /* + * start conversions immediately via software, ADCA + */ + c28x_adc_regs->ADCSOCFRC1.all = 0x0001; //SOC0 + /* + * wait for ADCA to complete, then acknowledge flag + */ + while(c28x_adc_regs->ADCINTFLG.bit.ADCINT1 == 0); + c28x_adc_regs->ADCINTFLGCLR.bit.ADCINT1 = 1; + + /* + * store results + */ + *value = (rt_uint32_t)c28x_adc_result_regs->ADCRESULT0; + + return RT_EOK; +} + +static const struct rt_adc_ops stm_adc_ops = +{ + .enabled = c28x_adc_enabled, + .convert = c28x_adc_get_value, + .get_resolution = c28x_adc_get_resolution, + .get_vref = c28x_adc_get_vref, +}; + +static rt_err_t HAL_ADC_Init(volatile struct ADC_REGS *c28x_adc_handler) +{ + int adc_controller_num = 0; + Uint16 acqps; + + EALLOW; + /* + * write configurations + */ + c28x_adc_handler->ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4 + if(c28x_adc_handler == &AdcaRegs) + { + adc_controller_num = 0; + }else if(c28x_adc_handler == &AdcbRegs) + { + adc_controller_num = 1; + } + else if(c28x_adc_handler == &AdccRegs) + { + adc_controller_num = 2; + } + else if(c28x_adc_handler == &AdcdRegs) + { + adc_controller_num = 3; + } + AdcSetMode(adc_controller_num, ADC_RESOLUTION, ADC_SIGNALMODE_SINGLE); + c28x_adc_handler->ADCCTL1.bit.INTPULSEPOS = 1; + EDIS; + + /* + * determine minimum acquisition window (in SYSCLKS) based on resolution + */ + if(ADC_RESOLUTION_12BIT == AdcaRegs.ADCCTL2.bit.RESOLUTION) + { + acqps = 14; //75ns + } + else + { + /* + * resolution is 16-bit + */ + acqps = 63; //320ns + } + + /* + * Select the channels to convert and end of conversion flag + */ + EALLOW; + c28x_adc_handler->ADCSOC0CTL.bit.ACQPS = acqps; //sample window is acqps + 1 SYSCLK cycles + c28x_adc_handler->ADCINTSEL1N2.bit.INT1SEL = 0; //end of SOC0 will set INT1 flag + c28x_adc_handler->ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag + c28x_adc_handler->ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared + EDIS; + return RT_EOK; +} + +static int c28x_adc_init(void) +{ + int result = RT_EOK; + /* + * save adc name + */ + int i = 0; + /* ADC init */ + for (i = 0; i < sizeof(c28x_adc_obj) / sizeof(c28x_adc_obj[0]); i++) + { + if (HAL_ADC_Init(c28x_adc_obj[i].adc_regs) != RT_EOK) + { + LOG_E("%s init failed", c28x_adc_obj[i].name); + result = -RT_ERROR; + } + else + { + /* register ADC device */ + if (rt_hw_adc_register(&c28x_adc_obj[i].c28x_adc_device, c28x_adc_obj[i].name, &stm_adc_ops, &c28x_adc_obj[i]) == RT_EOK) + { + LOG_D("%s init success", c28x_adc_obj[i].name); + } + else + { + LOG_E("%s register failed", c28x_adc_obj[i].name); + result = -RT_ERROR; + } + } + } + + return result; +} +INIT_BOARD_EXPORT(c28x_adc_init); + +#endif /* BSP_USING_ADC */ diff --git a/bsp/ti/c28x/libraries/HAL_Drivers/drv_adc.h b/bsp/ti/c28x/libraries/HAL_Drivers/drv_adc.h new file mode 100644 index 0000000000..7cbd14bbfe --- /dev/null +++ b/bsp/ti/c28x/libraries/HAL_Drivers/drv_adc.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-10-07 qiyu first version + */ + +#ifndef DRIVERS_DRV_ADC_H_ +#define DRIVERS_DRV_ADC_H_ +#ifdef BSP_ADC_USING_12BIT +#define ADC_RESOLUTION ADC_RESOLUTION_12BIT +#else +#define ADC_RESOLUTION ADC_RESOLUTION_16BIT +#endif +#include "rtdevice.h" +#ifdef BSP_USING_ADC + +struct c28x_adc +{ + struct rt_adc_device c28x_adc_device; + volatile struct ADC_REGS *adc_regs; + volatile struct ADC_RESULT_REGS *adc_results; + const char *name; +}; +#endif /* BSP_USING_ADC */ + +#endif /* DRIVERS_DRV_ADC_H_ */ diff --git a/bsp/ti/c28x/libraries/HAL_Drivers/drv_config.h b/bsp/ti/c28x/libraries/HAL_Drivers/drv_config.h new file mode 100644 index 0000000000..b73ec398a2 --- /dev/null +++ b/bsp/ti/c28x/libraries/HAL_Drivers/drv_config.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-09-24 qiyu first version + */ + +#ifndef DRIVERS_DRV_CONFIG_H_ +#define DRIVERS_DRV_CONFIG_H_ + +#include "config/pwm_config.h" +#include "config/adc_config.h" + +#endif /* DRIVERS_DRV_CONFIG_H_ */ diff --git a/bsp/ti/c28x/libraries/HAL_Drivers/drv_gpio.c b/bsp/ti/c28x/libraries/HAL_Drivers/drv_gpio.c new file mode 100644 index 0000000000..89d5931799 --- /dev/null +++ b/bsp/ti/c28x/libraries/HAL_Drivers/drv_gpio.c @@ -0,0 +1,439 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-08-28 qiyu first version + */ +#include +#include "drv_gpio.h" +#include "F2837xD_device.h" +#include "F28x_Project.h" // Device Headerfile and Examples Include File +#ifdef RT_USING_PIN + +// the gpio pin number for each port is 32, while it is 16 for ARM +#define PIN_NUM(port, no) (((((port) & 0xFu) << 5) | ((no) & 0x1F))) +#define PIN_PORT(pin) ((rt_uint16_t)(((pin) >> 5) & 0xFu)) +#define PIN_NO(pin) ((rt_uint16_t)((pin) & 0x1Fu)) + +#define PIN_c28x_PORT(pin) (volatile Uint32 *)&GpioDataRegs + (PIN_PORT(pin))*GPY_DATA_OFFSET +#define PIN_c28x_PIN(pin) ((rt_uint32_t)(1u << PIN_NO(pin))) + +#define PIN_c28x_PORT_MAX 6 /* gpioA to GPIOF in total*/ +#define PIN_IRQ_MAX 5 /* XINT1 to XINT5 in total */ + +static rt_err_t c28x_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args); +static rt_err_t c28x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin); +static rt_err_t c28x_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled); + +static rt_base_t c28x_pin_get(const char *name) +{ + int hw_pin_num = 0; + int i, name_len; + + name_len = rt_strlen(name); + + if ((name_len < 3) || (name_len >= 7)) + { + return -RT_EINVAL; + } + /* + * PX.y + */ + if ((name[0] != 'P') || (name[2] != '.')) + { + return -RT_EINVAL; + } + + for (i = 3; i < name_len; i++) + { + hw_pin_num *= 10; + hw_pin_num += name[i] - '0'; + } + return hw_pin_num; +} + +static void c28x_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + volatile Uint32 *gpioDataReg; + Uint32 pinMask; + if (PIN_PORT(pin) < PIN_c28x_PORT_MAX) + { + gpioDataReg = PIN_c28x_PORT(pin); + pinMask = 1UL << (PIN_NO(pin)); + if (value == 0) + { + gpioDataReg[GPYCLEAR] = pinMask; + } + else + { + gpioDataReg[GPYSET] = pinMask; + } + } +} + +static int c28x_pin_read(rt_device_t dev, rt_base_t pin) +{ + volatile Uint32 *gpioDataReg; + int value = PIN_LOW; + + if (PIN_PORT(pin) < PIN_c28x_PORT_MAX) + { + gpioDataReg = PIN_c28x_PORT(pin); + value = (gpioDataReg[GPYDAT] >> PIN_NO(pin)) & 0x1; + } + + return value; +} + +static void c28x_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *dir, *pud, *odr; + if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX) + { + return; + } + rt_uint32_t pinMask; + pinMask = 1UL << PIN_NO(pin); + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (PIN_PORT(pin))*GPY_CTRL_OFFSET; + + dir = gpioBaseAddr + GPYDIR; + pud = gpioBaseAddr + GPYPUD; + odr = gpioBaseAddr + GPYODR; + + EALLOW; + if (mode == PIN_MODE_OUTPUT) + { + *dir |= pinMask; + } + else if (mode == PIN_MODE_INPUT) + { + *dir &= ~pinMask; + } + else if (mode == PIN_MODE_INPUT_PULLUP) + { + *dir &= ~pinMask; + *pud &= ~pinMask; + } + else if (mode == PIN_MODE_INPUT_PULLDOWN) + { + /* input setting: pull down. */ + *dir &= ~pinMask; + *pud |= pinMask; + } + else if (mode == PIN_MODE_OUTPUT_OD) + { + /* output setting: od. */ + *dir |= pinMask; + *odr |= pinMask; + } + EDIS; +} + +const static struct rt_pin_ops _c28x_pin_ops = +{ + c28x_pin_mode, + c28x_pin_write, + c28x_pin_read, + c28x_pin_attach_irq, + c28x_pin_dettach_irq, + c28x_pin_irq_enable, + c28x_pin_get, +}; + +int rt_hw_pin_init(void) +{ + return rt_device_pin_register("pin", &_c28x_pin_ops, RT_NULL); +} + +static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +static rt_int16_t pin_irq_xint_tab[] = +{ + BSP_XINT1_PIN, + BSP_XINT2_PIN, + BSP_XINT3_PIN, + BSP_XINT4_PIN, + BSP_XINT5_PIN +}; +rt_inline rt_int32_t get_irq_index(rt_uint32_t pin) +{ + int i; + for(i = 0 ; i < PIN_IRQ_MAX ; i++) + { + if(pin_irq_xint_tab[i] == pin) + { + return i; + } + } + return -1; +} + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) + +static rt_err_t c28x_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX) + { + return -RT_ENOSYS; + } + irqindex = get_irq_index(pin); + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return -RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t c28x_pin_dettach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + rt_uint16_t i; + if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX) + { + return -RT_ENOSYS; + } + + for(i = 0 ; i < PIN_IRQ_MAX ; i++) + { + if(pin_irq_hdr_tab[i].pin == pin) + { + irqindex = i; + break; + } + } + if (irqindex == -1) + { + return -RT_ENOSYS; + } + level = rt_hw_interrupt_disable(); + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t c28x_pin_irq_enable(struct rt_device *device, rt_base_t pin, + rt_uint32_t enabled) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + rt_uint16_t channel; + rt_uint16_t edge_mode,pin_mode; + + if (PIN_PORT(pin) >= PIN_c28x_PORT_MAX) + { + return -RT_ENOSYS; + } + + irqindex = get_irq_index(pin); + + /* irqindex+1 = channel*/ + if (irqindex < 0 || irqindex >= PIN_IRQ_MAX) + { + return -RT_ENOSYS; + } + + if (enabled == PIN_IRQ_ENABLE) + { + level = rt_hw_interrupt_disable(); + + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return -RT_ENOSYS; + } + + /* + * 1. set the edge mode of interrupt triggering + * 2. set the GPIO mode + * 3. enable XINT channel and set the input source + */ + channel = irqindex+1; + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + edge_mode = 1; + pin_mode = PIN_MODE_INPUT_PULLDOWN; + break; + case PIN_IRQ_MODE_FALLING: + edge_mode = 0; + pin_mode = PIN_MODE_INPUT_PULLUP; + break; + case PIN_IRQ_MODE_RISING_FALLING: + edge_mode = 3; + pin_mode = PIN_MODE_INPUT; + break; + } + if(channel == 1) + { + XintRegs.XINT1CR.bit.ENABLE = 1; // Enable XINT1 + EALLOW; + InputXbarRegs.INPUT4SELECT = pin; //Set XINT1 source to GPIO-pin + EDIS; + XintRegs.XINT1CR.bit.POLARITY = edge_mode; // Falling edge interrupt + } + else if(channel == 2) + { + XintRegs.XINT2CR.bit.ENABLE = 1; // Enable XINT2 + EALLOW; + InputXbarRegs.INPUT5SELECT = pin; //Set XINT1 source to GPIO-pin + EDIS; + XintRegs.XINT2CR.bit.POLARITY = edge_mode; // Falling edge interrupt + } + else if(channel == 3) + { + XintRegs.XINT3CR.bit.ENABLE = 1; // Enable XINT2 + EALLOW; + InputXbarRegs.INPUT6SELECT = pin; //Set XINT1 source to GPIO-pin + EDIS; + XintRegs.XINT3CR.bit.POLARITY = edge_mode; // Falling edge interrupt + } + else if(channel == 4) + { + XintRegs.XINT4CR.bit.ENABLE = 1; // Enable XINT2 + EALLOW; + InputXbarRegs.INPUT13SELECT = pin; //Set XINT1 source to GPIO-pin + EDIS; + XintRegs.XINT4CR.bit.POLARITY = edge_mode; // Falling edge interrupt + } + else if(channel == 5) + { + XintRegs.XINT5CR.bit.ENABLE = 1; // Enable XINT2 + EALLOW; + InputXbarRegs.INPUT14SELECT = pin; //Set XINT1 source to GPIO-pin + EDIS; + XintRegs.XINT5CR.bit.POLARITY = edge_mode; // Falling edge interrupt + } + + c28x_pin_mode(device, pin, pin_mode); + rt_hw_interrupt_enable(level); + } + else if (enabled == PIN_IRQ_DISABLE) + { + level = rt_hw_interrupt_disable(); + channel = irqindex+1; + /* + * TODO modify this simpler + */ + if(channel == 1) + { + XintRegs.XINT1CR.bit.ENABLE = 0; // Disable XINT1 + } + else if(channel == 2) + { + XintRegs.XINT2CR.bit.ENABLE = 0; // Disable XINT2 + } + else if(channel == 3) + { + XintRegs.XINT3CR.bit.ENABLE = 0; // Disable XINT2 + } + else if(channel == 4) + { + XintRegs.XINT4CR.bit.ENABLE = 0; // Disable XINT2 + } + else if(channel == 5) + { + XintRegs.XINT5CR.bit.ENABLE = 0; // Disable XINT2 + } + rt_hw_interrupt_enable(level); + } + else + { + return -RT_ENOSYS; + } + + return RT_EOK; +} + +void GPIO_XINT_Callback(rt_int16_t XINT_number); + +interrupt void XINT1_Handler(void) +{ + rt_interrupt_enter(); + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + GPIO_XINT_Callback(1); + rt_interrupt_leave(); +} + +interrupt void XINT2_Handler(void) +{ + rt_interrupt_enter(); + GPIO_XINT_Callback(2); + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + rt_interrupt_leave(); +} + +interrupt void XINT3_Handler(void) +{ + rt_interrupt_enter(); + GPIO_XINT_Callback(3); + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + rt_interrupt_leave(); +} + +interrupt void XINT4_Handler(void) +{ + rt_interrupt_enter(); + GPIO_XINT_Callback(4); + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + rt_interrupt_leave(); +} + +interrupt void XINT5_Handler(void) +{ + rt_interrupt_enter(); + GPIO_XINT_Callback(5); + PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + rt_interrupt_leave(); +} + +void GPIO_XINT_Callback(rt_int16_t XINT_number) +{ + rt_int32_t irqindex = XINT_number - 1; + if(pin_irq_hdr_tab[irqindex].hdr) + { + pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args); + } +} + +#endif /* RT_USING_PIN */ + + + diff --git a/bsp/ti/c28x/libraries/HAL_Drivers/drv_gpio.h b/bsp/ti/c28x/libraries/HAL_Drivers/drv_gpio.h new file mode 100644 index 0000000000..ceb1cc1cfa --- /dev/null +++ b/bsp/ti/c28x/libraries/HAL_Drivers/drv_gpio.h @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-08-28 qiyu first version + */ + +#ifndef DRIVERS_DRV_GPIO_H_ +#define DRIVERS_DRV_GPIO_H_ + +#include +#include "rtdevice.h" + +#ifdef __cplusplus +extern "C" { +#endif + +int rt_hw_pin_init(void); + +#ifndef BSP_XINT1_PIN +#define BSP_XINT1_PIN -1 +#endif +#ifndef BSP_XINT2_PIN +#define BSP_XINT2_PIN -1 +#endif +#ifndef BSP_XINT3_PIN +#define BSP_XINT3_PIN -1 +#endif +#ifndef BSP_XINT4_PIN +#define BSP_XINT4_PIN -1 +#endif +#ifndef BSP_XINT5_PIN +#define BSP_XINT5_PIN -1 +#endif + +#ifdef __cplusplus +} +#endif + + +#endif /* DRIVERS_DRV_GPIO_H_ */ diff --git a/bsp/ti/c28x/libraries/HAL_Drivers/drv_pwm.c b/bsp/ti/c28x/libraries/HAL_Drivers/drv_pwm.c new file mode 100644 index 0000000000..336e7f6e57 --- /dev/null +++ b/bsp/ti/c28x/libraries/HAL_Drivers/drv_pwm.c @@ -0,0 +1,587 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-09-24 qiyu first version + */ + +#include "rtdbg.h" +#include "drv_pwm.h" +#include "F2837xD_device.h" +#include "F28x_Project.h" /* Device Headerfile and Examples Include File */ +#include "drv_config.h" +#include "F2837xD_epwm.h" +/* + * for now, cpu rate is a fixed value, waiting to be modified to an auto-ajustable variable. +*/ +#ifdef BSP_USING_PWM +rt_err_t rt_device_pwm_register(struct rt_device_pwm *device, const char *name, const struct rt_pwm_ops *ops, const void *user_data); + +#define CPU_FREQUENCY 200e6 +/* + * TODO unknown issue, according to the configuration, + * this division should be 2, + * while 2 is inconsistent with the measured result + */ +#define PWM_DIVISION 2 +#define CHANNEL_A 1 +#define CHANNEL_B 2 +#define UPDOWN 1 + +enum +{ +#ifdef BSP_USING_PWM1 + PWM1_INDEX, +#endif +#ifdef BSP_USING_PWM2 + PWM2_INDEX, +#endif +#ifdef BSP_USING_PWM3 + PWM3_INDEX, +#endif +#ifdef BSP_USING_PWM4 + PWM4_INDEX, +#endif +#ifdef BSP_USING_PWM5 + PWM5_INDEX, +#endif +#ifdef BSP_USING_PWM6 + PWM6_INDEX, +#endif +#ifdef BSP_USING_PWM7 + PWM7_INDEX, +#endif +#ifdef BSP_USING_PWM8 + PWM8_INDEX, +#endif +#ifdef BSP_USING_PWM9 + PWM9_INDEX, +#endif +#ifdef BSP_USING_PWM10 + PWM10_INDEX, +#endif +#ifdef BSP_USING_PWM11 + PWM11_INDEX, +#endif +#ifdef BSP_USING_PWM12 + PWM12_INDEX, +#endif +}; + +static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg); + +static struct rt_pwm_ops rt_pwm_ops = +{ + drv_pwm_control +}; + +static struct c28x_pwm c28x_pwm_obj[] = +{ +#ifdef BSP_USING_PWM1 + PWM1_CONFIG, +#endif + +#ifdef BSP_USING_PWM2 + PWM2_CONFIG, +#endif + +#ifdef BSP_USING_PWM3 + PWM3_CONFIG, +#endif + +#ifdef BSP_USING_PWM4 + PWM4_CONFIG, +#endif + +#ifdef BSP_USING_PWM5 + PWM5_CONFIG, +#endif + +#ifdef BSP_USING_PWM6 + PWM6_CONFIG, +#endif + +#ifdef BSP_USING_PWM7 + PWM7_CONFIG, +#endif + +#ifdef BSP_USING_PWM8 + PWM8_CONFIG, +#endif + +}; + +static rt_err_t drv_pwm_set(volatile struct EPWM_REGS *epwm,struct rt_pwm_configuration *configuration) +{ + if(epwm == RT_NULL) + { + return -RT_ERROR; + } + /* + * TODO Unknown problem + * the clock division configuration of PWM module is 1 + * however, the experiment result shows the division is 2 + */ + + /* Set the configuration of PWM according to the parameter*/ + rt_uint32_t prd = configuration->period/(1e9/(CPU_FREQUENCY/PWM_DIVISION))/2; + rt_uint32_t comp = prd*configuration->pulse/configuration->period; + rt_uint32_t dead_time = configuration->dead_time/(1e9/(CPU_FREQUENCY/PWM_DIVISION)); + rt_uint32_t phase = configuration->phase; + + epwm->TBPRD = prd; /* Set timer period*/ + epwm->TBCTR = 0x0000; /* Clear counter*/ + epwm->CMPCTL.bit.SHDWAMODE = RT_SHADOW_MODE; /* Load registers every ZERO*/ + epwm->CMPCTL.bit.SHDWBMODE = RT_SHADOW_MODE; + /* Setup compare */ + if(configuration->channel == CHANNEL_A) + { + epwm->CMPA.bit.CMPA = comp; + }else + { + epwm->CMPB.bit.CMPB = comp; + } + + /* Set actions */ + epwm->AQCTLA.bit.CAU = AQ_CLEAR; /* Set PWMA on Zero*/ + epwm->AQCTLA.bit.CAD = AQ_SET; + epwm->AQCTLB.bit.CBU = AQ_CLEAR; /* Set PWMB on Zero*/ + epwm->AQCTLB.bit.CBD = AQ_SET; + + /* Active Low PWMs - Setup Deadband */ + /* TODO finish complementary setting */ + epwm->DBCTL.bit.POLSEL = DB_ACTV_HIC; + epwm->DBRED.bit.DBRED = dead_time; + epwm->DBFED.bit.DBFED = dead_time; + epwm->DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; + /* + if(configuration->complementary) + { + } + else + { + epwm->DBRED.bit.DBRED = 0; + epwm->DBFED.bit.DBFED = 0; + epwm->DBCTL.bit.POLSEL = DB_ACTV_HI; + epwm->DBCTL.bit.OUT_MODE = DB_DISABLE; + } + */ + + epwm->DBCTL.bit.IN_MODE = DBA_ALL; + /* if disable dead time, set dead_time to 0 */ + +#ifdef BSP_PWM1_CTR_MODE_UPDOWN + if(phase<180) + { + epwm->TBPHS.bit.TBPHS = prd * phase/180; + epwm->TBCTL.bit.PHSDIR = 0; /* count up */ + }else + { + epwm->TBPHS.bit.TBPHS = prd-prd * (phase-180)/180; + epwm->TBCTL.bit.PHSDIR = 1; /* count up*/ + } +#endif + if(epwm == &EPwm1Regs) + { + epwm->TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */ + epwm->TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; + }else + { + epwm->TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */ + epwm->TBCTL.bit.SYNCOSEL = TB_SYNC_IN; + } + return RT_EOK; +} + +static rt_err_t drv_pwm_get(struct EPWM_REGS *epwm,struct rt_pwm_configuration *configuration) +{ + /* Retrieve the pwm configuration */ + if(epwm == RT_NULL) + { + return -RT_ERROR; + } + rt_uint32_t prd = epwm->TBPRD; + rt_uint32_t comp = epwm->CMPA.bit.CMPA; + if(UPDOWN) + { + /* if in updown mode, period in configuration has to be doubled */ + configuration->period = prd*(1e9/(CPU_FREQUENCY/PWM_DIVISION))*2; + } + else + { + configuration->period = prd*(1e9/(CPU_FREQUENCY/PWM_DIVISION)); + } + configuration->pulse = comp*configuration->period/prd; + return RT_EOK; +} + +static rt_err_t drv_pwm_set_period(struct EPWM_REGS *epwm, rt_uint32_t period) +{ + if(epwm == RT_NULL) + { + return -RT_ERROR; + } + rt_uint32_t prd = period/(1e9/(CPU_FREQUENCY/PWM_DIVISION))/2; + epwm->TBPRD = prd; /* Set timer period */ + return RT_EOK; +} + +static rt_err_t drv_pwm_set_pulse(struct EPWM_REGS *epwm, int channel, rt_uint32_t pulse) +{ + if(epwm == RT_NULL) + { + return -RT_ERROR; + } + rt_uint32_t comp = pulse/(1e9/(CPU_FREQUENCY/PWM_DIVISION)); + if(channel == CHANNEL_A) + { + epwm->CMPA.bit.CMPA = comp; /* set comparator value */ + }else + { + epwm->CMPB.bit.CMPB = comp; /* set comparator value */ + } + return RT_EOK; +} + +static rt_err_t drv_pwm_set_dead_time(struct EPWM_REGS *epwm, rt_uint32_t dead_time) +{ + if(epwm == RT_NULL) + { + return -RT_ERROR; + } + rt_uint32_t _dead_time = dead_time/(1e9/(CPU_FREQUENCY/PWM_DIVISION)); + epwm->DBRED.bit.DBRED = _dead_time; /* rising dead time */ + epwm->DBFED.bit.DBFED = _dead_time; /* falling dead time */ + return RT_EOK; +} + +static rt_err_t drv_pwm_set_phase(struct EPWM_REGS *epwm, rt_uint32_t phase) +{ + if(epwm == RT_NULL) + { + return -RT_ERROR; + } + if(phase<180) + { + epwm->TBPHS.bit.TBPHS = epwm->TBPRD * phase/180; + epwm->TBCTL.bit.PHSDIR = 0;/* count up */ + }else + { + epwm->TBPHS.bit.TBPHS = epwm->TBPRD-epwm->TBPRD * (phase-180)/180; + epwm->TBCTL.bit.PHSDIR = 1;/* count up */ + } + + return RT_EOK; +} + +static rt_err_t drv_pwm_enable_irq(volatile struct EPWM_REGS *epwm,rt_bool_t enable) +{ + if(epwm == RT_NULL) + { + return -RT_ERROR; + } + if(enable == RT_TRUE) + { + /* Interrupt setting */ + epwm->ETSEL.bit.INTEN = 1; /* Enable INT */ + }else{ + epwm->ETSEL.bit.INTEN = 0; /* Enable INT */ + } + return RT_EOK; +} + +static rt_err_t drv_pwm_enable(volatile struct EPWM_REGS *epwm,rt_bool_t enable) +{ + /* + * TODO + * Still not sure about how to stop PWM in C2000 + */ + if(epwm == RT_NULL) + { + return -RT_ERROR; + } + if(enable == RT_TRUE) + { + /* clear trip zone flag */ + EALLOW; + epwm->TZCLR.bit.OST = 1; + EDIS; + } + else + { + /* set trip zone flag */ + EALLOW; + epwm->TZFRC.bit.OST = 1; + EDIS; + } + return RT_EOK; +} + +static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + struct c28x_pwm *pwm = (struct c28x_pwm *)device->parent.user_data; + + switch (cmd) + { + case PWM_CMD_ENABLE: + return drv_pwm_enable((struct EPWM_REGS *)(pwm->pwm_regs), RT_TRUE); + case PWM_CMD_DISABLE: + return drv_pwm_enable((struct EPWM_REGS *)(pwm->pwm_regs), RT_FALSE); + case PWM_CMD_SET: + return drv_pwm_set((struct EPWM_REGS *)(pwm->pwm_regs), configuration); + case PWM_CMD_GET: + return drv_pwm_get((struct EPWM_REGS *)(pwm->pwm_regs), configuration); + case PWM_CMD_SET_PERIOD: + return drv_pwm_set_period((struct EPWM_REGS *)(pwm->pwm_regs), configuration->period); + case PWM_CMD_SET_PULSE: + return drv_pwm_set_pulse((struct EPWM_REGS *)(pwm->pwm_regs), configuration->channel,configuration->pulse); + case PWM_CMD_SET_DEAD_TIME: + return drv_pwm_set_dead_time((struct EPWM_REGS *)(pwm->pwm_regs), configuration->dead_time); + case PWM_CMD_SET_PHASE: + return drv_pwm_set_phase((struct EPWM_REGS *)(pwm->pwm_regs), configuration->phase); + case PWM_CMD_ENABLE_IRQ: + return drv_pwm_enable_irq((struct EPWM_REGS *)(pwm->pwm_regs), RT_TRUE); + case PWM_CMD_DISABLE_IRQ: + return drv_pwm_enable_irq((struct EPWM_REGS *)(pwm->pwm_regs), RT_FALSE); + default: + return RT_EINVAL; + } +} + +static void pwm_isr(struct rt_device_pwm *rt_pwm) +{ + struct c28x_pwm *pwm; + pwm = (struct c28x_pwm *)rt_pwm->parent.user_data; + PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + pwm->pwm_regs->ETCLR.bit.INT = 1; +} + +#define EPWM_ISR_DEFINE(i) void EPWM##i##_Isr(){\ + rt_interrupt_enter(); \ + pwm_isr(&(c28x_pwm_obj[PWM##i##_INDEX].pwm_device)); \ + rt_interrupt_leave(); \ +} + +#ifdef BSP_PWM1_IT_ENABLE +EPWM_ISR_DEFINE(1) +void EPWM1_Isr(); +#endif +#ifdef BSP_PWM2_IT_ENABLE +EPWM_ISR_DEFINE(2) +void EPWM2_Isr(); +#endif +#ifdef BSP_PWM3_IT_ENABLE +EPWM_ISR_DEFINE(3) +void EPWM3_Isr(); +#endif +#ifdef BSP_PWM4_IT_ENABLE +EPWM_ISR_DEFINE(4) +void EPWM4_Isr(); +#endif + + +static int c28x_hw_pwm_init(struct c28x_pwm *device) +{ + IER |= M_INT3; + rt_err_t result = 0; + EALLOW; +#ifdef BSP_USING_PWM1 + GpioCtrlRegs.GPAPUD.all |= 5<<(1-1)*4; /* Disable pull-up(EPWM1A) */ + GpioCtrlRegs.GPAMUX1.all|= 5<<(1-1)*4; /* Configure as EPWM1A */ + EPwm1Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */ + EPwm1Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */ + EPwm1Regs.TBCTL.bit.CTRMODE = BSP_PWM1_CTRMODE; + EPwm1Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM1_HSPCLKDIV; /* Clock ratio to SYSCLKOUT*/ + EPwm1Regs.TBCTL.bit.CLKDIV = BSP_PWM1_CLKDIV; + EPwm1Regs.CMPCTL.bit.LOADAMODE = BSP_PWM1_LOADAMODE; + EPwm1Regs.CMPCTL.bit.LOADBMODE = BSP_PWM1_LOADAMODE; + #ifdef BSP_PWM1_IT_ENABLE + EPwm1Regs.ETSEL.bit.INTEN = 1; /* Enable INT */ + EPwm1Regs.ETSEL.bit.INTSEL = BSP_PWM1_INTSEL; + EPwm1Regs.ETPS.bit.INTPRD = BSP_PWM1_INTPRD; + /* Assigning ISR to PIE */ + PieVectTable.EPWM1_INT = &EPWM1_Isr; + /* ENABLE Interrupt */ + #else + EPwm1Regs.ETSEL.bit.INTEN = 0; /* Disable INT */ + #endif + #ifdef BSP_PWM1_ADC_TRIGGER + EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group + EPwm1Regs.ETSEL.bit.SOCASEL = BSP_PWM1_SOCASEL; // Select SOC from zero + EPwm1Regs.ETPS.bit.SOCAPRD = BSP_PWM1_SOCAPRD; // Generate pulse on 1st event + #else + EPwm1Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group + #endif + #ifdef BSP_PWM1_MASTER + EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */ + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; + #else + EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */ + EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; + #endif +#endif +#ifdef BSP_USING_PWM2 + GpioCtrlRegs.GPAPUD.all |= 5<<(2-1)*4; /* Disable pull-up on (EPWM2A) */ + GpioCtrlRegs.GPAMUX1.all|= 5<<(2-1)*4; /* Configure as EPWM2A */ + EPwm2Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */ + EPwm2Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */ + EPwm2Regs.TBCTL.bit.CTRMODE = BSP_PWM2_CTRMODE; + EPwm2Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM2_HSPCLKDIV; /* Clock ratio to SYSCLKOUT*/ + EPwm2Regs.TBCTL.bit.CLKDIV = BSP_PWM2_CLKDIV; + EPwm2Regs.CMPCTL.bit.LOADAMODE = BSP_PWM2_LOADAMODE; + EPwm2Regs.CMPCTL.bit.LOADBMODE = BSP_PWM2_LOADAMODE; + #ifdef BSP_PWM2_IT_ENABLE + EPwm2Regs.ETSEL.bit.INTEN = 1; /* Enable INT */ + EPwm2Regs.ETSEL.bit.INTSEL = BSP_PWM2_INTSEL; + EPwm2Regs.ETPS.bit.INTPRD = BSP_PWM2_INTPRD; + /* Assigning ISR to PIE */ + PieVectTable.EPWM2_INT = &EPWM2_Isr; + /* ENABLE Interrupt */ + #else + EPwm2Regs.ETSEL.bit.INTEN = 0; /* Disable INT */ + #endif + #ifdef BSP_PWM2_ADC_TRIGGER + EPwm2Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group + EPwm2Regs.ETSEL.bit.SOCASEL = BSP_PWM2_SOCASEL; // Select SOC from zero + EPwm2Regs.ETPS.bit.SOCAPRD = BSP_PWM2_SOCAPRD; // Generate pulse on 1st event + #else + EPwm2Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group + #endif + #ifdef BSP_PWM2_MASTER + EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */ + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; + #else + EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */ + EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; + #endif +#endif +#ifdef BSP_USING_PWM3 + GpioCtrlRegs.GPAPUD.all |= 5<<(3-1)*4; /* Disable pull-up on (EPWM3A) */ + GpioCtrlRegs.GPAMUX1.all|= 5<<(3-1)*4; /* Configure as EPWM3A */ + EPwm3Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */ + EPwm3Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */ + EPwm3Regs.TBCTL.bit.CTRMODE = BSP_PWM3_CTRMODE; + EPwm3Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM3_HSPCLKDIV; /* Clock ratio to SYSCLKOUT*/ + EPwm3Regs.TBCTL.bit.CLKDIV = BSP_PWM3_CLKDIV; + EPwm3Regs.CMPCTL.bit.LOADAMODE = BSP_PWM3_LOADAMODE; + EPwm3Regs.CMPCTL.bit.LOADBMODE = BSP_PWM3_LOADAMODE; + #ifdef BSP_PWM3_IT_ENABLE + EPwm3Regs.ETSEL.bit.INTEN = 1; /* Enable INT */ + EPwm3Regs.ETSEL.bit.INTSEL = BSP_PWM3_INTSEL; + EPwm3Regs.ETPS.bit.INTPRD = BSP_PWM3_INTPRD; + /* Assigning ISR to PIE */ + PieVectTable.EPWM3_INT = &EPWM3_Isr; + /* ENABLE Interrupt */ + #else + EPwm3Regs.ETSEL.bit.INTEN = 0; /* Disable INT */ + #endif + #ifdef BSP_PWM3_ADC_TRIGGER + EPwm3Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group + EPwm3Regs.ETSEL.bit.SOCASEL = BSP_PWM3_SOCASEL; // Select SOC from zero + EPwm3Regs.ETPS.bit.SOCAPRD = BSP_PWM3_SOCAPRD; // Generate pulse on 1st event + #else + EPwm3Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group + #endif + #ifdef BSP_PWM3_MASTER + EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */ + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; + #else + EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */ + EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; + #endif +#endif +#ifdef BSP_USING_PWM4 + GpioCtrlRegs.GPAPUD.all |= 5<<(4-1)*4; /* Disable pull-up on (EPWM4A) */ + GpioCtrlRegs.GPAMUX1.all|= 5<<(4-1)*4; /* Configure as EPWM4A */ + EPwm4Regs.TZCTL.bit.TZA = TZ_OFF; /* diable A when trip zone */ + EPwm4Regs.TZCTL.bit.TZB = TZ_OFF; /* diable B when trip zone */ + EPwm4Regs.TBCTL.bit.CTRMODE = BSP_PWM4_CTRMODE; + EPwm4Regs.TBCTL.bit.HSPCLKDIV = BSP_PWM4_HSPCLKDIV; /* Clock ratio to SYSCLKOUT*/ + EPwm4Regs.TBCTL.bit.CLKDIV = BSP_PWM4_CLKDIV; + EPwm4Regs.CMPCTL.bit.LOADAMODE = BSP_PWM4_LOADAMODE; + EPwm4Regs.CMPCTL.bit.LOADBMODE = BSP_PWM4_LOADAMODE; + #ifdef BSP_PWM4_IT_ENABLE + EPwm4Regs.ETSEL.bit.INTEN = 1; /* Enable INT */ + EPwm4Regs.ETSEL.bit.INTSEL = BSP_PWM4_INTSEL; + EPwm4Regs.ETPS.bit.INTPRD = BSP_PWM4_INTPRD; + /* Assigning ISR to PIE */ + PieVectTable.EPWM4_INT = &EPWM4_Isr; + /* ENABLE Interrupt */ + #else + EPwm4Regs.ETSEL.bit.INTEN = 0; /* Disable INT */ + #endif + #ifdef BSP_PWM4_ADC_TRIGGER + EPwm4Regs.ETSEL.bit.SOCAEN = 1; // Enable SOC on A group + EPwm4Regs.ETSEL.bit.SOCASEL = BSP_PWM4_SOCASEL; // Select SOC from zero + EPwm4Regs.ETPS.bit.SOCAPRD = BSP_PWM4_SOCAPRD; // Generate pulse on 1st event + #else + EPwm4Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group + #endif + #ifdef BSP_PWM4_MASTER + EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE; /* Disable phase loading */ + EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; + #else + EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; /* Disable phase loading */ + EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; + #endif +#endif + EDIS; + + return result; +} + +int c28x_pwm_init(void) +{ + int i = 0; + int result = RT_EOK; + + for (i = 0; i < sizeof(c28x_pwm_obj) / sizeof(c28x_pwm_obj[0]); i++) + { + /* pwm init */ + if (c28x_hw_pwm_init(&c28x_pwm_obj[i]) != RT_EOK) + { + LOG_E("%s init failed", c28x_pwm_obj[i].name); + result = -RT_ERROR; + return result; + } + else + { + LOG_D("%s init success", c28x_pwm_obj[i].name); + + /* register pwm device */ + if (rt_device_pwm_register(&c28x_pwm_obj[i].pwm_device, c28x_pwm_obj[i].name, &rt_pwm_ops, &c28x_pwm_obj[i]) == RT_EOK) + { + LOG_D("%s register success", c28x_pwm_obj[i].name); + } + else + { + LOG_E("%s register failed", c28x_pwm_obj[i].name); + result = -RT_ERROR; + } + } + } + struct rt_pwm_configuration config_tmp1 = + { + .channel = CHANNEL_A, + .period = BSP_PWM1_INIT_PERIOD, + .pulse = BSP_PWM1_INIT_PULSE, + .dead_time = BSP_PWM1_DB, + .phase = 0, + .complementary = RT_TRUE + }; + drv_pwm_set(c28x_pwm_obj[0].pwm_regs,&config_tmp1); +// config_tmp1.phase = BSP_PWM2_PHASE; +// drv_pwm_set(c28x_pwm_obj[1].pwm_regs,&config_tmp1); +// config_tmp1.phase = BSP_PWM3_PHASE; +// drv_pwm_set(c28x_pwm_obj[2].pwm_regs,&config_tmp1); +// config_tmp1.phase = BSP_PWM4_PHASE; +// drv_pwm_set(c28x_pwm_obj[3].pwm_regs,&config_tmp1); + return result; + +} +INIT_DEVICE_EXPORT(c28x_pwm_init); +#endif /* BSP_USING_PWM */ diff --git a/bsp/ti/c28x/libraries/HAL_Drivers/drv_pwm.h b/bsp/ti/c28x/libraries/HAL_Drivers/drv_pwm.h new file mode 100644 index 0000000000..d3ef2ccddd --- /dev/null +++ b/bsp/ti/c28x/libraries/HAL_Drivers/drv_pwm.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-09-24 qiyu first version + */ + +#ifndef DRIVERS_DRV_PWM_H_ +#define DRIVERS_DRV_PWM_H_ +#include +#include "rtdevice.h" + +#ifdef BSP_USING_PWM +struct c28x_pwm +{ + struct rt_device_pwm pwm_device; + volatile struct EPWM_REGS *pwm_regs; + const char *name; +}; + +int c28x_pwm_init(void); +#endif /* BSP_USING_PWM */ +#endif /* DRIVERS_DRV_PWM_H_ */ diff --git a/bsp/ti/c28x/libraries/HAL_Drivers/drv_sci.c b/bsp/ti/c28x/libraries/HAL_Drivers/drv_sci.c new file mode 100644 index 0000000000..f1ba3f26d3 --- /dev/null +++ b/bsp/ti/c28x/libraries/HAL_Drivers/drv_sci.c @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-02 xuzhuoyi first version + */ + +#include "rtdevice.h" +#include "board.h" +#include "drv_sci.h" +#include "F2837xD_device.h" +#include "F2837xD_sci.h" + +//typedef long off_t; +#include "F2837xD_sci_io.h" + +#ifdef RT_USING_SERIAL + +#define LOG_TAG "drv.sci" + +/* c28x uart driver class */ +struct c28x_uart +{ + const char *name; + volatile struct SCI_REGS *sci_regs; + struct rt_serial_device serial; +}; + +static struct c28x_uart uart_obj[3] = {0}; + +static rt_err_t c28x_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct c28x_uart *uart; + RT_ASSERT(serial != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + uart = (struct c28x_uart *)serial->parent.user_data; + RT_ASSERT(uart != RT_NULL); + + EALLOW; + + // default config + + // 1 stop bit, No loopback + // No parity,8 char bits, + // async mode, idle-line protocol + uart->sci_regs->SCICCR.all = 0x0007; + + // enable TX, RX, internal SCICLK, + // Disable RX ERR, SLEEP, TXWAKE + uart->sci_regs->SCICTL1.all = 0x0003; + + uart->sci_regs->SCICTL2.bit.TXINTENA = 1; + uart->sci_regs->SCICTL2.bit.RXBKINTENA = 1; + + uart->sci_regs->SCIHBAUD.all = 0x0000; // 115200 baud @LSPCLK = 22.5MHz (90 MHz SYSCLK). + uart->sci_regs->SCILBAUD.all = 53; + + uart->sci_regs->SCICTL1.all = 0x0023; // Relinquish SCI from Reset + + switch (cfg->data_bits) + { + case DATA_BITS_5: + uart->sci_regs->SCICCR.bit.SCICHAR = 4; + break; + case DATA_BITS_6: + uart->sci_regs->SCICCR.bit.SCICHAR = 5; + break; + case DATA_BITS_7: + uart->sci_regs->SCICCR.bit.SCICHAR = 6; + break; + case DATA_BITS_8: + uart->sci_regs->SCICCR.bit.SCICHAR = 7; + break; + default: + uart->sci_regs->SCICCR.bit.SCICHAR = 7; + break; + } + switch (cfg->stop_bits) + { + case STOP_BITS_1: + uart->sci_regs->SCICCR.bit.STOPBITS = 0; + break; + case STOP_BITS_2: + uart->sci_regs->SCICCR.bit.STOPBITS = 1; + break; + default: + uart->sci_regs->SCICCR.bit.STOPBITS = 0; + break; + } + switch (cfg->parity) + { + case PARITY_NONE: + uart->sci_regs->SCICCR.bit.PARITYENA = 0; + break; + case PARITY_ODD: + uart->sci_regs->SCICCR.bit.PARITYENA = 1; + uart->sci_regs->SCICCR.bit.PARITY = 0; + break; + case PARITY_EVEN: + uart->sci_regs->SCICCR.bit.PARITYENA = 1; + uart->sci_regs->SCICCR.bit.PARITY = 1; + break; + default: + uart->sci_regs->SCICCR.bit.PARITYENA = 0; + break; + } + + EDIS; + + return RT_EOK; +} + +static rt_err_t c28x_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct c28x_uart *uart; + uart = (struct c28x_uart *)serial->parent.user_data; + + EALLOW; + + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + /* disable interrupt */ + uart->sci_regs->SCICTL2.bit.TXINTENA = 0; + uart->sci_regs->SCICTL2.bit.RXBKINTENA = 0; + break; + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + /* enable interrupt */ + uart->sci_regs->SCICTL2.bit.TXINTENA = 1; + uart->sci_regs->SCICTL2.bit.RXBKINTENA = 1; + break; + } + return RT_EOK; +} + +static int c28x_putc(struct rt_serial_device *serial, char c) +{ + SCI_write(0, &c, 1); + return 1; +} + +static int c28x_getc(struct rt_serial_device *serial) +{ + char ch; + if(SCI_read(0, &ch, 1)) + return ch; + else + return -1; +} + +/** + * Uart common interrupt process. This need add to uart ISR. + * + * @param serial serial device + */ +static void uart_isr(struct rt_serial_device *serial) { + struct c28x_uart *uart = (struct c28x_uart *) serial->parent.user_data; + + RT_ASSERT(uart != RT_NULL); + + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); + SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; // Clear Interrupt flag + PieCtrlRegs.PIEACK.all |= 0x100; // Issue PIE ack +} + +static const struct rt_uart_ops c28x_uart_ops = +{ + .configure = c28x_configure, + .control = c28x_control, + .putc = c28x_putc, + .getc = c28x_getc, +}; + +// +// sciaRxFifoIsr - SCIA Receive FIFO ISR +// +interrupt void sciaRxFifoIsr(void) +{ + ALLOW_ISR_PREEMPT(); + + /* enter interrupt */ + rt_interrupt_enter(); + + uart_isr(&uart_obj[0].serial); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +int rt_hw_sci_init(void) +{ + EALLOW; + + GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; + GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; + GpioCtrlRegs.GPBGMUX1.bit.GPIO42 = 3; + GpioCtrlRegs.GPBGMUX1.bit.GPIO43 = 3; + + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 2; + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 2; + GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 0; + GpioCtrlRegs.GPAGMUX2.bit.GPIO19 = 0; + + GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 2; + GpioCtrlRegs.GPEMUX1.bit.GPIO139 = 2; + GpioCtrlRegs.GPBGMUX2.bit.GPIO56 = 1; + GpioCtrlRegs.GPEGMUX1.bit.GPIO139 = 1; + + CpuSysRegs.PCLKCR7.bit.SCI_A = 1; + CpuSysRegs.PCLKCR7.bit.SCI_B = 1; + CpuSysRegs.PCLKCR7.bit.SCI_C = 1; + + PieVectTable.SCIA_RX_INT = &sciaRxFifoIsr; + + EDIS; + + // + // Enable interrupts required for this example + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block + PieCtrlRegs.PIEIER9.bit.INTx1 = 1; // PIE Group 9, INT1 + IER |= 0x100; // Enable CPU INT + + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t result = 0; + + uart_obj[0].serial.ops = &c28x_uart_ops; + uart_obj[0].serial.config = config; + uart_obj[0].name = "scia"; + uart_obj[0].sci_regs = &SciaRegs; + + uart_obj[1].serial.ops = &c28x_uart_ops; + uart_obj[1].serial.config = config; + uart_obj[1].name = "scib"; + uart_obj[1].sci_regs = &ScibRegs; + + uart_obj[2].serial.ops = &c28x_uart_ops; + uart_obj[2].serial.config = config; + uart_obj[2].name = "scic"; + uart_obj[2].sci_regs = &ScicRegs; + + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[0].serial, uart_obj[0].name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + &uart_obj[0]); + + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[1].serial, uart_obj[1].name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + &uart_obj[1]); + + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[2].serial, uart_obj[2].name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + &uart_obj[2]); + + return result; +} + +#endif /* RT_USING_SERIAL */ diff --git a/bsp/ti/c28x/libraries/HAL_Drivers/drv_sci.h b/bsp/ti/c28x/libraries/HAL_Drivers/drv_sci.h new file mode 100644 index 0000000000..60fb12bd9b --- /dev/null +++ b/bsp/ti/c28x/libraries/HAL_Drivers/drv_sci.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-02-02 xuzhuoyi first version + */ + +#ifndef __DRV_SCI_H__ +#define __DRV_SCI_H__ + +int rt_hw_sci_init(void); + +#endif /* __DRV_SCI_H__ */ diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Adc_defines.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Adc_defines.h new file mode 100644 index 0000000000..78ff34a237 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Adc_defines.h @@ -0,0 +1,87 @@ +//########################################################################### +// +// FILE: F2837xD_Adc_defines.h +// +// TITLE: #defines used in ADC examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_ADC_DEFINES_H +#define F2837xD_ADC_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +//definitions for specifying an ADC +// +#define ADC_ADCA 0 +#define ADC_ADCB 1 +#define ADC_ADCC 2 +#define ADC_ADCD 3 + +// +//definitions for selecting ADC resolution +// +#ifndef _DUAL_HEADERS +#define ADC_RESOLUTION_12BIT 0 +#define ADC_RESOLUTION_16BIT 1 +#else +#define ADC_BITRESOLUTION_12BIT 0 +#define ADC_BITRESOLUTION_16BIT 1 +#endif +// +//definitions for selecting ADC signal mode +//(single-ended mode is only a valid mode for 12-bit resolution) +// +#define ADC_SIGNALMODE_SINGLE 0 +#define ADC_SIGNALMODE_DIFFERENTIAL 1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_ADC_DEFINES_H + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Can_defines.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Can_defines.h new file mode 100644 index 0000000000..a784ef475d --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Can_defines.h @@ -0,0 +1,129 @@ +//############################################################################# +// +// FILE: F2837xD_Can_defines.h +// +// TITLE: Common defines used in CAN Test Cases +// +//############################################################################# +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef F2837xD_CAN_DEFINES_H +#define F2837xD_CAN_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// Reset Values +// +#define CAN_RESET_VALUE_ZERO 0x00000000 +#define CAN_CTL_RESET_VALUE 0x00001401 +#define CAN_ES_RESET_VALUE 0x00000007 +#define CAN_BTR_RESET_VALUE 0x00002301 +#define CAN_REL_RESET_VALUE 0xA3170504 +#define CAN_RAM_INIT_RESET_VALUE 0x00000005 +#define CAN_IF_CMD_RESET_VALUE 0x00000001 +#define CAN_IF_MASK_RESET_VALUE 0xFFFFFFFF + +// +// Register value when Peripheral Clock is Disabled +// +#define CAN_MODULE_CLK_DISABLE_VALUE 0x00000000 + +// +// Bit field definition of CAN_CTL register. +// +#define CAN_CTL_INIT 0x00000001 // Initialization +#define CAN_CTL_IE0 0x00000002 // Interrupt Enable 0 +#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable +#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable +#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission +#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable +#define CAN_CTL_TEST 0x00000080 // Test Mode Enable +#define CAN_CTL_IDS 0x00000100 // Interruption Debug Support Enable +#define CAN_CTL_ABO 0x00000200 // Auto-Bus On Enable +#define CAN_CTL_PMD_S 10 +#define CAN_CTL_PMD_M 0x00003C00 // Parity/SECDED Enable +#define CAN_CTL_SWR 0x00008000 // Software Reset Enable +#define CAN_CTL_INITDBG 0x00010000 // Debug Mode Status +#define CAN_CTL_IE1 0x00020000 // Interrupt Enable 1 +#define CAN_CTL_PDR 0x01000000 // Power Down Mode Request +#define CAN_CTL_WUBA 0x02000000 // Wake Up on Bus Activity + +// +// Bit field definition of CAN_IF1_CMD register. +// +#define CAN_IF1_CMD_MESSNUM_S 0 +#define CAN_IF1_CMD_MESSNUM_M 0x000000FF // Message Number +#define CAN_IF1_CMD_BUSY 0x00008000 // Busy Flag +#define CAN_IF1_CMD_DATAB 0x00010000 // Access Data B +#define CAN_IF1_CMD_DATAA 0x00020000 // Access Data A +#define CAN_IF1_CMD_TXRQSTNDAT 0x00040000 // Transmission Request Bit +#define CAN_IF1_CMD_CLRINTPND 0x00080000 // Clear Interrupt Pending Bit +#define CAN_IF1_CMD_CONTROL 0x00100000 // Access Control Bits +#define CAN_IF1_CMD_ARB 0x00200000 // Access Arbitration Bits +#define CAN_IF1_CMD_MASK 0x00400000 // Access Mask Bits +#define CAN_IF1_CMD_WR_RD 0x00800000 // Write and Read + +// +// Bit field definition of CAN_IF2_CMD register. +// +#define CAN_IF2_CMD_MESSNUM_S 0 +#define CAN_IF2_CMD_MESSNUM_M 0x000000FF // Message Number +#define CAN_IF2_CMD_BUSY 0x00008000 // Busy Flag +#define CAN_IF2_CMD_DATAB 0x00010000 // Access Data B +#define CAN_IF2_CMD_DATAA 0x00020000 // Access Data A +#define CAN_IF2_CMD_TXRQSTNDAT 0x00040000 // Transmission Request Bit +#define CAN_IF2_CMD_CLRINTPND 0x00080000 // Clear Interrupt Pending Bit +#define CAN_IF2_CMD_CONTROL 0x00100000 // Access Control Bits +#define CAN_IF2_CMD_ARB 0x00200000 // Access Arbitration Bits +#define CAN_IF2_CMD_MASK 0x00400000 // Access Mask Bits +#define CAN_IF2_CMD_WR_RD 0x00800000 // Write and Read + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_CAN_DEFINES_H + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_defines.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_defines.h new file mode 100644 index 0000000000..2df82d7929 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_defines.h @@ -0,0 +1,201 @@ +//########################################################################### +// +// FILE: F2837xD_Cla_defines.h +// +// TITLE: #defines used in CLA examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_CLA_DEFINES_H +#define F2837xD_CLA_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// MCTL Register +// +#define CLA_FORCE_RESET 0x1 +#define CLA_IACK_ENABLE 0x1 +#define CLA_IACK_DISABLE 0x0 + +// +// MMEMCFG Register +// +#define CLA_CLA_SPACE 0x1 +#define CLA_CPU_SPACE 0x0 + +// +// MIER Interrupt Enable Register +// +#define CLA_INT_ENABLE 0x1 +#define CLA_INT_DISABLE 0x0 + +// +// Peripheral Interrupt Source Select define for DMAnCLASourceSelect Register +// +#define CLA_TRIG_NOPERPH 0 +#define CLA_TRIG_ADCAINT1 1 +#define CLA_TRIG_ADCAINT2 2 +#define CLA_TRIG_ADCAINT3 3 +#define CLA_TRIG_ADCAINT4 4 +#define CLA_TRIG_ADCAEVT 5 +#define CLA_TRIG_ADCBINT1 6 +#define CLA_TRIG_ADCBINT2 7 +#define CLA_TRIG_ADCBINT3 8 +#define CLA_TRIG_ADCBINT4 9 +#define CLA_TRIG_ADCBEVT 10 +#define CLA_TRIG_ADCCINT1 11 +#define CLA_TRIG_ADCCINT2 12 +#define CLA_TRIG_ADCCINT3 13 +#define CLA_TRIG_ADCCINT4 14 +#define CLA_TRIG_ADCCEVT 15 +#define CLA_TRIG_ADCDINT1 16 +#define CLA_TRIG_ADCDINT2 17 +#define CLA_TRIG_ADCDINT3 18 +#define CLA_TRIG_ADCDINT4 19 +#define CLA_TRIG_ADCDEVT 20 + +#define CLA_TRIG_XINT1 29 +#define CLA_TRIG_XINT2 30 +#define CLA_TRIG_XINT3 31 +#define CLA_TRIG_XINT4 32 +#define CLA_TRIG_XINT5 33 + +#define CLA_TRIG_EPWM1INT 36 +#define CLA_TRIG_EPWM2INT 37 +#define CLA_TRIG_EPWM3INT 38 +#define CLA_TRIG_EPWM4INT 39 +#define CLA_TRIG_EPWM5INT 40 +#define CLA_TRIG_EPWM6INT 41 +#define CLA_TRIG_EPWM7INT 42 +#define CLA_TRIG_EPWM8INT 43 +#define CLA_TRIG_EPWM9INT 44 +#define CLA_TRIG_EPWM10INT 45 +#define CLA_TRIG_EPWM11INT 46 +#define CLA_TRIG_EPWM12INT 47 + +#define CLA_TRIG_TINT0 68 +#define CLA_TRIG_TINT1 69 +#define CLA_TRIG_TINT2 70 + +#define CLA_TRIG_MXEVTA 71 +#define CLA_TRIG_MREVTA 72 +#define CLA_TRIG_MXEVTB 73 +#define CLA_TRIG_MREVTB 74 + +#define CLA_TRIG_ECAP1INT 75 +#define CLA_TRIG_ECAP2INT 76 +#define CLA_TRIG_ECAP3INT 77 +#define CLA_TRIG_ECAP4INT 78 +#define CLA_TRIG_ECAP5INT 79 +#define CLA_TRIG_ECAP6INT 80 + +#define CLA_TRIG_EQEP1INT 83 +#define CLA_TRIG_EQEP2INT 84 +#define CLA_TRIG_EQEP3INT 85 + +#define CLA_TRIG_HRCAP1INT 87 +#define CLA_TRIG_HRCAP2INT 88 + +#define CLA_TRIG_SD1INT 95 +#define CLA_TRIG_SD2INT 96 + +#define CLA_TRIG_UPP1_INT 107 + +#define CLA_TRIG_SPITXINTA 109 +#define CLA_TRIG_SPIRXINTA 110 +#define CLA_TRIG_SPITXINTB 111 +#define CLA_TRIG_SPIRXINTB 112 +#define CLA_TRIG_SPITXINTC 113 +#define CLA_TRIG_SPIRXINTC 114 + +#define Cla1ForceTask1andWait()asm(" IACK #0x0001"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT1 == 1); + +#define Cla1ForceTask2andWait()asm(" IACK #0x0002"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT2 == 1); + +#define Cla1ForceTask3andWait()asm(" IACK #0x0004"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT3 == 1); + +#define Cla1ForceTask4andWait()asm(" IACK #0x0008"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT4 == 1); + +#define Cla1ForceTask5andWait()asm(" IACK #0x0010"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT5 == 1); + +#define Cla1ForceTask6andWait()asm(" IACK #0x0020"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT6 == 1); + +#define Cla1ForceTask7andWait()asm(" IACK #0x0040"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT7 == 1); + +#define Cla1ForceTask8andWait()asm(" IACK #0x0080"); \ + asm(" RPT #3 || NOP"); \ + while(Cla1Regs.MIRUN.bit.INT8 == 1); + +#define Cla1ForceTask1() asm(" IACK #0x0001") +#define Cla1ForceTask2() asm(" IACK #0x0002") +#define Cla1ForceTask3() asm(" IACK #0x0004") +#define Cla1ForceTask4() asm(" IACK #0x0008") +#define Cla1ForceTask5() asm(" IACK #0x0010") +#define Cla1ForceTask6() asm(" IACK #0x0020") +#define Cla1ForceTask7() asm(" IACK #0x0040") +#define Cla1ForceTask8() asm(" IACK #0x0080") + +#ifdef __cplusplus +} +#endif + +#endif // - end of F2837xD_CLA_DEFINES_H + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_typedefs.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_typedefs.h new file mode 100644 index 0000000000..5a4650cbaa --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Cla_typedefs.h @@ -0,0 +1,128 @@ +//########################################################################### +// +// FILE: F2837xD_Cla_typedefs.h +// +// TITLE: Variable type definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_CLA_TYPEDEFS_H_ +#define F2837xD_CLA_TYPEDEFS_H_ + +// +// Macros to manipulate pre-processor to generate a header file name +// at compile time that is based on the test name and can be used as +// an argument to #include +// +#define XSTRINGIZE(s) STRINGIZE(s) +#define STRINGIZE(s) #s +#define XCONCAT(x,y) CONCAT(x,y) +#define CONCAT(x,y) x##y + +// +// Suppress warnings casting CLA pointers +// +#pragma diag_suppress 70,770,232 + +#ifdef __TMS320C28XX_CLA__ +// +// For Portability, User Is Recommended To Use Following Data Type Size +// Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: +// +// CLA does not support 64-bit types +// This definition is only to allow inclusion of the standard header files +// which do use 64-bit types +// + +#if (!defined(F28_DATA_TYPES) && !defined(DSP28_DATA_TYPES)) +#define F28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef short int16; +typedef long int32; +typedef unsigned char Uint8; +typedef unsigned short Uint16; +typedef unsigned long Uint32; +typedef float float32; +typedef long double float64; +typedef struct { Uint32 low32; Uint32 high32; } Uint64; +typedef struct { int32 low32; int32 high32; } int64; +#else +#error F2837xD_Cla_Typedefs.h must be included before F2837xD_Device.h or any other header \ +file that redefines data types using the guard macros F28_DATA_TYPES or DSP28_DATA_TYPES +#endif //(!defined(F28_DATA_TYPES) && !defined(DSP28_DATA_TYPES)) + +#ifndef _TI_STD_TYPES +#define _TI_STD_TYPES +// +//These types are also defined in DSP/BIOS 5.x's and the +//SYS/BIOS 6.x's files. We need to protect their +//definition with the #ifndef/#define guard to avoid the duplicate +//definition warning. +// +//SYS/BIOS requires that the file be included before +//any other .h files. +// +#endif + +struct MSTF_SHADOW_BITS { // bits description + Uint16 LVF:1; // 0 Latched Overflow Flag + Uint16 LUF:1; // 1 Latched Underflow Flag + Uint16 NF:1; // 2 Negative Float Flag + Uint16 ZF:1; // 3 Zero Float Flag + Uint16 rsvd1:2; // 5:4 Reserved + Uint16 TF:1; // 6 Test Flag + Uint16 rsvd2:2; // 8:7 Reserved + Uint16 RNDF32:1; // 9 Rounding Mode + Uint16 rsvd3:1; // 10 Reserved + Uint16 MEALLOW:1; // 11 MEALLOW Status + Uint16 RPCL:4; // 15:12 Return PC: Low Portion + Uint16 RPCH:8; // 23:16 Return PC: High Portion + Uint16 rsvd4:8; // 31:24 Reserved +}; +extern __cregister volatile unsigned int MSTF; + +#endif //__TMS320C28XX_CLA__ + +#ifndef __TMS320C28XX__ +#define __cregister +#endif //__TMS320C28xx__ + +#endif //F2837xD_CLA_TYPEDEFS_H_ + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Dma_defines.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Dma_defines.h new file mode 100644 index 0000000000..ef6a245b93 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Dma_defines.h @@ -0,0 +1,212 @@ +//########################################################################### +// +// FILE: F2837xD_Dma_defines.h +// +// TITLE: #defines used in DMA examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_DMA_DEFINES_H +#define F2837xD_DMA_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// PERINTSEL bits +// +#define DMA_ADCAINT1 1 +#define DMA_ADCAINT2 2 +#define DMA_ADCAINT3 3 +#define DMA_ADCAINT4 4 +#define DMA_ADCAEVT 5 +#define DMA_ADCBINT1 6 +#define DMA_ADCBINT2 7 +#define DMA_ADCBINT3 8 +#define DMA_ADCBINT4 9 +#define DMA_ADCBEVT 10 +#define DMA_ADCCINT1 11 +#define DMA_ADCCINT2 12 +#define DMA_ADCCINT3 13 +#define DMA_ADCCINT4 14 +#define DMA_ADCCEVT 15 +#define DMA_ADCDINT1 16 +#define DMA_ADCDINT2 17 +#define DMA_ADCDINT3 18 +#define DMA_ADCDINT4 19 +#define DMA_ADCDEVT 20 + +#define DMA_XINT1 29 +#define DMA_XINT2 30 +#define DMA_XINT3 31 +#define DMA_XINT4 32 +#define DMA_XINT5 33 + +#define DMA_EPWM1A 36 +#define DMA_EPWM1B 37 +#define DMA_EPWM2A 38 +#define DMA_EPWM2B 39 +#define DMA_EPWM3A 40 +#define DMA_EPWM3B 41 +#define DMA_EPWM4A 42 +#define DMA_EPWM4B 43 +#define DMA_EPWM5A 44 +#define DMA_EPWM5B 45 +#define DMA_EPWM6A 46 +#define DMA_EPWM6B 47 +#define DMA_EPWM7A 48 +#define DMA_EPWM7B 49 +#define DMA_EPWM8A 50 +#define DMA_EPWM8B 51 +#define DMA_EPWM9A 52 +#define DMA_EPWM9B 53 +#define DMA_EPWM10A 54 +#define DMA_EPWM10B 55 +#define DMA_EPWM11A 56 +#define DMA_EPWM11B 57 +#define DMA_EPWM12A 58 +#define DMA_EPWM12B 59 +#define DMA_EPWM13A 60 +#define DMA_EPWM13B 61 +#define DMA_EPWM14A 62 +#define DMA_EPWM14B 63 +#define DMA_EPWM15A 64 +#define DMA_EPWM15B 65 +#define DMA_EPWM16A 66 +#define DMA_EPWM16B 67 + +#define DMA_TINT0 68 +#define DMA_TINT1 69 +#define DMA_TINT2 70 + +#define DMA_MXEVTA 71 +#define DMA_MREVTA 72 +#define DMA_MXEVTB 73 +#define DMA_MREVTB 74 + +#define DMA_SD1FLT1 95 +#define DMA_SD1FLT2 96 +#define DMA_SD1FLT3 97 +#define DMA_SD1FLT4 98 + +#define DMA_SD2FLT1 99 +#define DMA_SD2FLT2 100 +#define DMA_SD2FLT3 101 +#define DMA_SD2FLT4 102 + +#define DMA_SPIATX 109 +#define DMA_SPIARX 110 +#define DMA_SPIBTX 111 +#define DMA_SPIBRX 112 +#define DMA_SPICTX 113 +#define DMA_SPICRX 114 + +#define DMA_USBRX1 131 +#define DMA_USBTX1 132 +#define DMA_USBRX2 133 +#define DMA_USBTX2 134 +#define DMA_USBRX3 135 +#define DMA_USBTX3 136 + +// +// OVERINTE bit +// +#define OVRFLOW_DISABLE 0x0 +#define OVEFLOW_ENABLE 0x1 + +// +// PERINTE bit +// +#define PERINT_DISABLE 0x0 +#define PERINT_ENABLE 0x1 + +// +// CHINTMODE bits +// +#define CHINT_BEGIN 0x0 +#define CHINT_END 0x1 + +// +// ONESHOT bits +// +#define ONESHOT_DISABLE 0x0 +#define ONESHOT_ENABLE 0x1 + +// +// CONTINOUS bit +// +#define CONT_DISABLE 0x0 +#define CONT_ENABLE 0x1 + +// +// SYNCE bit +// +#define SYNC_DISABLE 0x0 +#define SYNC_ENABLE 0x1 + +// +// SYNCSEL bit +// +#define SYNC_SRC 0x0 +#define SYNC_DST 0x1 + +// +// DATASIZE bit +// +#define SIXTEEN_BIT 0x0 +#define THIRTYTWO_BIT 0x1 + +// +// CHINTE bit +// +#define CHINT_DISABLE 0x0 +#define CHINT_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif + +#endif // - end of F2837xD_DMA_DEFINES_H + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_EPwm_defines.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_EPwm_defines.h new file mode 100644 index 0000000000..a45ae46f62 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_EPwm_defines.h @@ -0,0 +1,342 @@ +//########################################################################### +// +// FILE: F2837xD_EPwm_defines.h +// +// TITLE: #defines used in EPwm examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_EPWM_DEFINES_H +#define F2837xD_EPWM_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// TBCTL (Time-Base Control) +// + +// +// CTRMODE bits +// +#define TB_COUNT_UP 0x0 +#define TB_COUNT_DOWN 0x1 +#define TB_COUNT_UPDOWN 0x2 +#define TB_FREEZE 0x3 + +// +// PHSEN bit +// +#define TB_DISABLE 0x0 +#define TB_ENABLE 0x1 + +// +// PRDLD bit +// +#define TB_SHADOW 0x0 +#define TB_IMMEDIATE 0x1 + +// +// SYNCOSEL bits +// +#define TB_SYNC_IN 0x0 +#define TB_CTR_ZERO 0x1 +#define TB_CTR_CMPB 0x2 +#define TB_SYNC_DISABLE 0x3 + +// +// HSPCLKDIV and CLKDIV bits +// +#define TB_DIV1 0x0 +#define TB_DIV2 0x1 +#define TB_DIV4 0x2 + +// +// PHSDIR bit +// +#define TB_DOWN 0x0 +#define TB_UP 0x1 + +// +// CMPCTL (Compare Control) +// + +// +// LOADAMODE and LOADBMODE bits +// +#define CC_CTR_ZERO 0x0 +#define CC_CTR_PRD 0x1 +#define CC_CTR_ZERO_PRD 0x2 +#define CC_LD_DISABLE 0x3 + +// +// SHDWAMODE and SHDWBMODE bits +// +#define CC_SHADOW 0x0 +#define CC_IMMEDIATE 0x1 + +// +// AQCTLA and AQCTLB (Action Qualifier Control) +// + +// +// ZRO, PRD, CAU, CAD, CBU, CBD bits +// +#define AQ_NO_ACTION 0x0 +#define AQ_CLEAR 0x1 +#define AQ_SET 0x2 +#define AQ_TOGGLE 0x3 + +// +// DBCTL (Dead-Band Control) +// + +// +// OUT MODE bits +// +#define DB_DISABLE 0x0 +#define DBB_ENABLE 0x1 +#define DBA_ENABLE 0x2 +#define DB_FULL_ENABLE 0x3 + +// +// POLSEL bits +// +#define DB_ACTV_HI 0x0 +#define DB_ACTV_LOC 0x1 +#define DB_ACTV_HIC 0x2 +#define DB_ACTV_LO 0x3 + +// +// IN MODE +// +#define DBA_ALL 0x0 +#define DBB_RED_DBA_FED 0x1 +#define DBA_RED_DBB_FED 0x2 +#define DBB_ALL 0x3 + +// +// CHPCTL (chopper control) +// + +// +// CHPEN bit +// +#define CHP_DISABLE 0x0 +#define CHP_ENABLE 0x1 + +// +// CHPFREQ bits +// +#define CHP_DIV1 0x0 +#define CHP_DIV2 0x1 +#define CHP_DIV3 0x2 +#define CHP_DIV4 0x3 +#define CHP_DIV5 0x4 +#define CHP_DIV6 0x5 +#define CHP_DIV7 0x6 +#define CHP_DIV8 0x7 + +// +// CHPDUTY bits +// +#define CHP1_8TH 0x0 +#define CHP2_8TH 0x1 +#define CHP3_8TH 0x2 +#define CHP4_8TH 0x3 +#define CHP5_8TH 0x4 +#define CHP6_8TH 0x5 +#define CHP7_8TH 0x6 + +// +// TZSEL (Trip Zone Select) +// + +// +// CBCn and OSHTn bits +// +#define TZ_DISABLE 0x0 +#define TZ_ENABLE 0x1 + +// +// TZCTL (Trip Zone Control) +// + +// +// TZA and TZB bits +// +#define TZ_HIZ 0x0 +#define TZ_FORCE_HI 0x1 +#define TZ_FORCE_LO 0x2 +#define TZ_NO_CHANGE 0x3 + +// +// TZDCSEL (Trip Zone Digital Compare) +// + +// +// DCAEVT1, DCAEVT2, DCBEVT1, DCBEVT2 bits +// +#define TZ_EVT_DISABLE 0x0 +#define TZ_DCAH_LOW 0x1 +#define TZ_DCAH_HI 0x2 +#define TZ_DCAL_LOW 0x3 +#define TZ_DCAL_HI 0x4 +#define TZ_DCAL_HI_DCAH_LOW 0x5 + +#define TZ_DCBH_LOW 0x1 +#define TZ_DCBH_HI 0x2 +#define TZ_DCBL_LOW 0x3 +#define TZ_DCBL_HI 0x4 +#define TZ_DCBL_HI_DCBH_LOW 0x5 + +// +// ETSEL (Event Trigger Select) +// +#define ET_DCAEVT1SOC 0x0 +#define ET_CTR_ZERO 0x1 +#define ET_CTR_PRD 0x2 +#define ET_CTR_PRDZERO 0x3 +#define ET_CTRU_CMPA 0x4 +#define ET_CTRD_CMPA 0x5 +#define ET_CTRU_CMPB 0x6 +#define ET_CTRD_CMPB 0x7 + +// +// ETPS (Event Trigger Pre-scale) +// + +// +// INTPRD, SOCAPRD, SOCBPRD bits +// +#define ET_DISABLE 0x0 +#define ET_1ST 0x1 +#define ET_2ND 0x2 +#define ET_3RD 0x3 + +// +// HRPWM (High Resolution PWM) +// + +// +// HRCNFG +// +#define HR_DISABLE 0x0 +#define HR_REP 0x1 +#define HR_FEP 0x2 +#define HR_BEP 0x3 + +#define HR_CMP 0x0 +#define HR_PHS 0x1 + +#define HR_CTR_ZERO 0x0 +#define HR_CTR_PRD 0x1 +#define HR_CTR_ZERO_PRD 0x2 + +#define HR_NORM_B 0x0 +#define HR_INVERT_B 0x1 + +// +// DC (Digital Compare) +// + +// +// DCTRIPSEL +// +#define DC_TZ1 0x0 +#define DC_TZ2 0x1 +#define DC_TZ3 0x2 +#define DC_TRIPIN1 0x0 +#define DC_TRIPIN2 0x1 +#define DC_TRIPIN3 0x2 +#define DC_TRIPIN4 0x3 +#define DC_TRIPIN5 0x4 +#define DC_TRIPIN6 0x5 +#define DC_TRIPIN7 0x6 +#define DC_TRIPIN8 0x7 +#define DC_TRIPIN9 0x8 +#define DC_TRIPIN10 0x9 +#define DC_TRIPIN11 0xA +#define DC_TRIPIN12 0xB +// Reserved 0xC +#define DC_TRIPIN14 0xD +#define DC_TRIPIN15 0xE +#define DC_COMBINATION 0xF + +// +// DCFCTL +// +#define DC_SRC_DCAEVT1 0x0 +#define DC_SRC_DCAEVT2 0x1 +#define DC_SRC_DCBEVT1 0x2 +#define DC_SRC_DCBEVT2 0x3 + +#define DC_PULSESEL_PRD 0x0 +#define DC_PULSESEL_ZERO 0x1 +#define DC_PULSESEL_ZERO_PRD 0x2 + +#define DC_BLANK_DISABLE 0x0 +#define DC_BLANK_ENABLE 0x1 + +#define DC_BLANK_NOTINV 0x0 +#define DC_BLANK_INV 0x1 + +// +//DCACTL/DCBCTL +// +#define DC_EVT1 0x0 +#define DC_EVT2 0x0 +#define DC_EVT_FLT 0x1 +#define DC_EVT_SYNC 0x0 +#define DC_EVT_ASYNC 0x1 +#define DC_SOC_DISABLE 0x0 +#define DC_SOC_ENABLE 0x1 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_EPWM_DEFINES_H + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Emif_defines.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Emif_defines.h new file mode 100644 index 0000000000..cb11472b04 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Emif_defines.h @@ -0,0 +1,319 @@ +//########################################################################### +// +// FILE: F2837xD_Emif_defines.h +// +// TITLE: #defines used in EMIF examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_EMIF_DEFINES_H +#define F2837xD_EMIF_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +//cpu1 to cpu2 message for handshaking +// +#define CPU1_CPU2_MSG 0x3fd00 + +// +//cpu2_to_cpu1 message ram for handshaking +// +#define CPU2_CPU1_MSG 0x3fb00 + +#define MSEL_EMIF1_CPU1 0x93A5CE71 +#define MSEL_EMIF1_CPU2 0x93A5CE72 +#define MSEL_DEF_3 0x93A5CE73 +#define MSEL_DEF_0 0x93A5CE70 +#define MSEL_DEF_1 0x93A5CE71 +#define MSEL_DEF_2 0x93A5CE72 + +// +//soft reset bit register +// +#define EMIF_SOFT_PRES_REG 0x5D084 + +// +//Device capability/EMIF customization register +// +#define EMIF_DEV_DC_REG 0x5D014 + +// +// Values for ASYNC_CSx_CR Registers +// +#define EMIF_ASYNC_ASIZE_8 0x0 +#define EMIF_ASYNC_ASIZE_16 0x1 +#define EMIF_ASYNC_ASIZE_32 0x2 + +#define EMIF_ASYNC_TA_1 0x0 +#define EMIF_ASYNC_TA_2 0x4 +#define EMIF_ASYNC_TA_3 0x8 +#define EMIF_ASYNC_TA_4 0xC + +#define EMIF_ASYNC_RHOLD_1 0x00 +#define EMIF_ASYNC_RHOLD_2 0x10 +#define EMIF_ASYNC_RHOLD_3 0x20 +#define EMIF_ASYNC_RHOLD_4 0x30 +#define EMIF_ASYNC_RHOLD_5 0x40 +#define EMIF_ASYNC_RHOLD_6 0x50 +#define EMIF_ASYNC_RHOLD_7 0x60 +#define EMIF_ASYNC_RHOLD_8 0x70 + +#define EMIF_ASYNC_RSTROBE_1 0x0000 +#define EMIF_ASYNC_RSTROBE_2 0x0080 +#define EMIF_ASYNC_RSTROBE_3 0x0100 +#define EMIF_ASYNC_RSTROBE_4 0x0180 +#define EMIF_ASYNC_RSTROBE_5 0x0200 +#define EMIF_ASYNC_RSTROBE_6 0x0280 +#define EMIF_ASYNC_RSTROBE_7 0x0300 +#define EMIF_ASYNC_RSTROBE_8 0x0380 +#define EMIF_ASYNC_RSTROBE_9 0x0400 +#define EMIF_ASYNC_RSTROBE_10 0x0480 +#define EMIF_ASYNC_RSTROBE_11 0x0500 +#define EMIF_ASYNC_RSTROBE_12 0x0580 +#define EMIF_ASYNC_RSTROBE_13 0x0600 +#define EMIF_ASYNC_RSTROBE_14 0x0680 +#define EMIF_ASYNC_RSTROBE_15 0x0700 +#define EMIF_ASYNC_RSTROBE_16 0x0780 +#define EMIF_ASYNC_RSTROBE_17 0x0800 +#define EMIF_ASYNC_RSTROBE_18 0x0880 +#define EMIF_ASYNC_RSTROBE_19 0x0900 +#define EMIF_ASYNC_RSTROBE_20 0x0980 +#define EMIF_ASYNC_RSTROBE_21 0x0A00 +#define EMIF_ASYNC_RSTROBE_22 0x0A80 +#define EMIF_ASYNC_RSTROBE_23 0x0B00 +#define EMIF_ASYNC_RSTROBE_24 0x0B80 +#define EMIF_ASYNC_RSTROBE_25 0x0C00 +#define EMIF_ASYNC_RSTROBE_26 0x0C80 +#define EMIF_ASYNC_RSTROBE_27 0x0D00 +#define EMIF_ASYNC_RSTROBE_28 0x0D80 +#define EMIF_ASYNC_RSTROBE_29 0x0E00 +#define EMIF_ASYNC_RSTROBE_30 0x0E80 +#define EMIF_ASYNC_RSTROBE_31 0x0F00 +#define EMIF_ASYNC_RSTROBE_32 0x0F80 +#define EMIF_ASYNC_RSTROBE_33 0x1000 +#define EMIF_ASYNC_RSTROBE_34 0x1080 +#define EMIF_ASYNC_RSTROBE_35 0x1100 +#define EMIF_ASYNC_RSTROBE_36 0x1180 +#define EMIF_ASYNC_RSTROBE_37 0x1200 +#define EMIF_ASYNC_RSTROBE_38 0x1280 +#define EMIF_ASYNC_RSTROBE_39 0x1300 +#define EMIF_ASYNC_RSTROBE_40 0x1380 +#define EMIF_ASYNC_RSTROBE_41 0x1400 +#define EMIF_ASYNC_RSTROBE_42 0x1480 +#define EMIF_ASYNC_RSTROBE_43 0x1500 +#define EMIF_ASYNC_RSTROBE_44 0x1580 +#define EMIF_ASYNC_RSTROBE_45 0x1600 +#define EMIF_ASYNC_RSTROBE_46 0x1680 +#define EMIF_ASYNC_RSTROBE_47 0x1700 +#define EMIF_ASYNC_RSTROBE_48 0x1780 +#define EMIF_ASYNC_RSTROBE_49 0x1800 +#define EMIF_ASYNC_RSTROBE_50 0x1880 +#define EMIF_ASYNC_RSTROBE_51 0x1900 +#define EMIF_ASYNC_RSTROBE_52 0x1980 +#define EMIF_ASYNC_RSTROBE_53 0x1A00 +#define EMIF_ASYNC_RSTROBE_54 0x1A80 +#define EMIF_ASYNC_RSTROBE_55 0x1B00 +#define EMIF_ASYNC_RSTROBE_56 0x1B80 +#define EMIF_ASYNC_RSTROBE_57 0x1C00 +#define EMIF_ASYNC_RSTROBE_58 0x1C80 +#define EMIF_ASYNC_RSTROBE_59 0x1D00 +#define EMIF_ASYNC_RSTROBE_60 0x1D80 +#define EMIF_ASYNC_RSTROBE_61 0x1E00 +#define EMIF_ASYNC_RSTROBE_62 0x1E80 +#define EMIF_ASYNC_RSTROBE_63 0x1F00 +#define EMIF_ASYNC_RSTROBE_64 0x1F80 + +#define EMIF_ASYNC_RSETUP_1 0x0000 +#define EMIF_ASYNC_RSETUP_2 0x2000 +#define EMIF_ASYNC_RSETUP_3 0x4000 +#define EMIF_ASYNC_RSETUP_4 0x6000 +#define EMIF_ASYNC_RSETUP_5 0x8000 +#define EMIF_ASYNC_RSETUP_6 0xA000 +#define EMIF_ASYNC_RSETUP_7 0xC000 +#define EMIF_ASYNC_RSETUP_8 0xE000 +#define EMIF_ASYNC_RSETUP_9 0x10000 +#define EMIF_ASYNC_RSETUP_10 0x12000 +#define EMIF_ASYNC_RSETUP_11 0x14000 +#define EMIF_ASYNC_RSETUP_12 0x16000 +#define EMIF_ASYNC_RSETUP_13 0x18000 +#define EMIF_ASYNC_RSETUP_14 0x1A000 +#define EMIF_ASYNC_RSETUP_15 0x1C000 +#define EMIF_ASYNC_RSETUP_16 0x1E000 + +#define EMIF_ASYNC_WHOLD_1 0x00000 +#define EMIF_ASYNC_WHOLD_2 0x20000 +#define EMIF_ASYNC_WHOLD_3 0x40000 +#define EMIF_ASYNC_WHOLD_4 0x60000 +#define EMIF_ASYNC_WHOLD_5 0x80000 +#define EMIF_ASYNC_WHOLD_6 0xA0000 +#define EMIF_ASYNC_WHOLD_7 0xC0000 +#define EMIF_ASYNC_WHOLD_8 0xE0000 + +#define EMIF_ASYNC_WSTROBE_1 0x0000000 +#define EMIF_ASYNC_WSTROBE_2 0x0100000 +#define EMIF_ASYNC_WSTROBE_3 0x0200000 +#define EMIF_ASYNC_WSTROBE_4 0x0300000 +#define EMIF_ASYNC_WSTROBE_5 0x0400000 +#define EMIF_ASYNC_WSTROBE_6 0x0500000 +#define EMIF_ASYNC_WSTROBE_7 0x0600000 +#define EMIF_ASYNC_WSTROBE_8 0x0700000 +#define EMIF_ASYNC_WSTROBE_9 0x0800000 +#define EMIF_ASYNC_WSTROBE_10 0x0900000 +#define EMIF_ASYNC_WSTROBE_11 0x0A00000 +#define EMIF_ASYNC_WSTROBE_12 0x0B00000 +#define EMIF_ASYNC_WSTROBE_13 0x0C00000 +#define EMIF_ASYNC_WSTROBE_14 0x0D00000 +#define EMIF_ASYNC_WSTROBE_15 0x0E00000 +#define EMIF_ASYNC_WSTROBE_16 0x0F00000 +#define EMIF_ASYNC_WSTROBE_17 0x1000000 +#define EMIF_ASYNC_WSTROBE_18 0x1100000 +#define EMIF_ASYNC_WSTROBE_19 0x1200000 +#define EMIF_ASYNC_WSTROBE_20 0x1300000 +#define EMIF_ASYNC_WSTROBE_21 0x1400000 +#define EMIF_ASYNC_WSTROBE_22 0x1500000 +#define EMIF_ASYNC_WSTROBE_23 0x1600000 +#define EMIF_ASYNC_WSTROBE_24 0x1700000 +#define EMIF_ASYNC_WSTROBE_25 0x1800000 +#define EMIF_ASYNC_WSTROBE_26 0x1900000 +#define EMIF_ASYNC_WSTROBE_27 0x1A00000 +#define EMIF_ASYNC_WSTROBE_28 0x1B00000 +#define EMIF_ASYNC_WSTROBE_29 0x1C00000 +#define EMIF_ASYNC_WSTROBE_30 0x1D00000 +#define EMIF_ASYNC_WSTROBE_31 0x1E00000 +#define EMIF_ASYNC_WSTROBE_32 0x1F00000 +#define EMIF_ASYNC_WSTROBE_33 0x2000000 +#define EMIF_ASYNC_WSTROBE_34 0x2100000 +#define EMIF_ASYNC_WSTROBE_35 0x2200000 +#define EMIF_ASYNC_WSTROBE_36 0x2300000 +#define EMIF_ASYNC_WSTROBE_37 0x2400000 +#define EMIF_ASYNC_WSTROBE_38 0x2500000 +#define EMIF_ASYNC_WSTROBE_39 0x2600000 +#define EMIF_ASYNC_WSTROBE_40 0x2700000 +#define EMIF_ASYNC_WSTROBE_41 0x2800000 +#define EMIF_ASYNC_WSTROBE_42 0x2900000 +#define EMIF_ASYNC_WSTROBE_43 0x2A00000 +#define EMIF_ASYNC_WSTROBE_44 0x2B00000 +#define EMIF_ASYNC_WSTROBE_45 0x2C00000 +#define EMIF_ASYNC_WSTROBE_46 0x2D00000 +#define EMIF_ASYNC_WSTROBE_47 0x2E00000 +#define EMIF_ASYNC_WSTROBE_48 0x2F00000 +#define EMIF_ASYNC_WSTROBE_49 0x3000000 +#define EMIF_ASYNC_WSTROBE_50 0x3100000 +#define EMIF_ASYNC_WSTROBE_51 0x3200000 +#define EMIF_ASYNC_WSTROBE_52 0x3300000 +#define EMIF_ASYNC_WSTROBE_53 0x3400000 +#define EMIF_ASYNC_WSTROBE_54 0x3500000 +#define EMIF_ASYNC_WSTROBE_55 0x3600000 +#define EMIF_ASYNC_WSTROBE_56 0x3700000 +#define EMIF_ASYNC_WSTROBE_57 0x3800000 +#define EMIF_ASYNC_WSTROBE_58 0x3900000 +#define EMIF_ASYNC_WSTROBE_59 0x3A00000 +#define EMIF_ASYNC_WSTROBE_60 0x3B00000 +#define EMIF_ASYNC_WSTROBE_61 0x3C00000 +#define EMIF_ASYNC_WSTROBE_62 0x3D00000 +#define EMIF_ASYNC_WSTROBE_63 0x3E00000 +#define EMIF_ASYNC_WSTROBE_64 0x3F00000 + +#define EMIF_ASYNC_WSETUP_1 0x00000000 +#define EMIF_ASYNC_WSETUP_2 0x04000000 +#define EMIF_ASYNC_WSETUP_3 0x08000000 +#define EMIF_ASYNC_WSETUP_4 0x0C000000 +#define EMIF_ASYNC_WSETUP_5 0x10000000 +#define EMIF_ASYNC_WSETUP_6 0x14000000 +#define EMIF_ASYNC_WSETUP_7 0x18000000 +#define EMIF_ASYNC_WSETUP_8 0x1C000000 +#define EMIF_ASYNC_WSETUP_9 0x20000000 +#define EMIF_ASYNC_WSETUP_10 0x24000000 +#define EMIF_ASYNC_WSETUP_11 0x28000000 +#define EMIF_ASYNC_WSETUP_12 0x2C000000 +#define EMIF_ASYNC_WSETUP_13 0x30000000 +#define EMIF_ASYNC_WSETUP_14 0x34000000 +#define EMIF_ASYNC_WSETUP_15 0x38000000 +#define EMIF_ASYNC_WSETUP_16 0x3C000000 + +#define EMIF_ASYNC_EW_DISABLE 0x00000000 +#define EMIF_ASYNC_EW_ENABLE 0x40000000 + +#define EMIF_ASYNC_SS_DISABLE 0x00000000 +#define EMIF_ASYNC_SS_ENABLE 0x80000000 + +// +// Values for ASYNC_WCCR Register +// +#define EMIF_ASYNC_WCCR_WP_LOW 0x00000000 +#define EMIF_ASYNC_WCCR_WP_HIGH 0x01000000 + +// +// Read mask for the registers which has reserved bits. +// +#define ASYNC_WCCR_RDMASK 0xF0FF00FF +#define SDRAM_CR_RDMASK 0xE3FF7F7F +#define SDRAM_RCR_RDMASK 0x00071FFF +#define SDRAM_TR_RDMASK 0xFF77FF70 +#define SDR_EXT_TMNG_RDMASK 0x1F +#define INT_RAW_RDMASK 0x3F +#define INT_MASK_RDMASK 0x3F +#define IO_CTRL_RDMASK_RDMASK 0xFFFF +#define IO_STAT_RDMASK_RDMASK 0xF +#define NAND_FLASH_CTRL_RDMASK 0x3F3F +#define NAND_FLASH_STAT_RDMASK 0x30F0F +#define IODFT_TLECR_REG_RDMASK 0xFFFF +#define IODFT_TLGCR_REG_RDMASK 0x71FF +#define IODFT_TLAMR_REG_RDMASK 0x0FFFFFFF +#define IODFT_TLDCMR_REG_RDMASK 0x3fff3f07 +#define MODEL_REL_NUM_REG_RDMASK 0xFF +#define NAND_FLASH_4BIT_ECCLR_RDMASK 0x3F +#define NAND_FLASH_4BIT_ECCx_RDMASK 0x03ff03ff +#define NAND_FLASH_ERR_ADDRx_RDMASK 0x03ff03ff +#define NAND_FLASH_ERR_VALx_RDMASK 0x03ff03ff + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_EMIF_DEFINES_H + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Examples.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Examples.h new file mode 100644 index 0000000000..bd3a3994b0 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Examples.h @@ -0,0 +1,448 @@ +//########################################################################### +// +// FILE: F2837xD_Examples.h +// +// TITLE: F2837xD Device Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_EXAMPLES_H +#define F2837xD_EXAMPLES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// The following are values that can be passed to the +// InitSysPll() & InitAuxPll() to select SYSPLL/AUXPLL integer multiplier +// +#define IMULT_0 0 +#define IMULT_1 1 +#define IMULT_2 2 +#define IMULT_3 3 +#define IMULT_4 4 +#define IMULT_5 5 +#define IMULT_6 6 +#define IMULT_7 7 +#define IMULT_8 8 +#define IMULT_9 9 +#define IMULT_10 10 +#define IMULT_11 11 +#define IMULT_12 12 +#define IMULT_13 13 +#define IMULT_14 14 +#define IMULT_15 15 +#define IMULT_16 16 +#define IMULT_17 17 +#define IMULT_18 18 +#define IMULT_19 19 +#define IMULT_20 20 +#define IMULT_21 21 +#define IMULT_22 22 +#define IMULT_23 23 +#define IMULT_24 24 +#define IMULT_25 25 +#define IMULT_26 26 +#define IMULT_27 27 +#define IMULT_28 28 +#define IMULT_29 29 +#define IMULT_30 30 +#define IMULT_31 31 +#define IMULT_32 32 +#define IMULT_33 33 +#define IMULT_34 34 +#define IMULT_35 35 +#define IMULT_36 36 +#define IMULT_37 37 +#define IMULT_38 38 +#define IMULT_39 39 +#define IMULT_40 40 +#define IMULT_41 41 +#define IMULT_42 42 +#define IMULT_43 43 +#define IMULT_44 44 +#define IMULT_45 45 +#define IMULT_46 46 +#define IMULT_47 47 +#define IMULT_48 48 +#define IMULT_49 49 +#define IMULT_50 50 +#define IMULT_51 51 +#define IMULT_52 52 +#define IMULT_53 53 +#define IMULT_54 54 +#define IMULT_55 55 +#define IMULT_56 56 +#define IMULT_57 57 +#define IMULT_58 58 +#define IMULT_59 59 +#define IMULT_60 60 +#define IMULT_61 61 +#define IMULT_62 62 +#define IMULT_63 63 +#define IMULT_64 64 +#define IMULT_65 65 +#define IMULT_66 66 +#define IMULT_67 67 +#define IMULT_68 68 +#define IMULT_69 69 +#define IMULT_70 70 +#define IMULT_71 71 +#define IMULT_72 72 +#define IMULT_73 73 +#define IMULT_74 74 +#define IMULT_75 75 +#define IMULT_76 76 +#define IMULT_77 77 +#define IMULT_78 78 +#define IMULT_79 79 +#define IMULT_80 80 +#define IMULT_81 81 +#define IMULT_82 82 +#define IMULT_83 83 +#define IMULT_84 84 +#define IMULT_85 85 +#define IMULT_86 86 +#define IMULT_87 87 +#define IMULT_88 88 +#define IMULT_89 89 +#define IMULT_90 90 +#define IMULT_91 91 +#define IMULT_92 92 +#define IMULT_93 93 +#define IMULT_94 94 +#define IMULT_95 95 +#define IMULT_96 96 +#define IMULT_97 97 +#define IMULT_98 98 +#define IMULT_99 99 +#define IMULT_100 100 +#define IMULT_101 101 +#define IMULT_102 102 +#define IMULT_103 103 +#define IMULT_104 104 +#define IMULT_105 105 +#define IMULT_106 106 +#define IMULT_107 107 +#define IMULT_108 108 +#define IMULT_109 109 +#define IMULT_110 110 +#define IMULT_111 111 +#define IMULT_112 112 +#define IMULT_113 113 +#define IMULT_114 114 +#define IMULT_115 115 +#define IMULT_116 116 +#define IMULT_117 117 +#define IMULT_118 118 +#define IMULT_119 119 +#define IMULT_120 120 +#define IMULT_121 121 +#define IMULT_122 122 +#define IMULT_123 123 +#define IMULT_124 124 +#define IMULT_125 125 +#define IMULT_126 126 +#define IMULT_127 127 + +// +// The following are values that can be passed to the +// InitSysPll() & InitAuxPll() to select SYSPLL/AUXPLL fractional multiplier +// +#define FMULT_0 0 +#define FMULT_0pt25 1 +#define FMULT_0pt5 2 +#define FMULT_0pt75 3 + +// +// The following are values that can be passed to the +// InitSysPll() to select divsel for SYSPLL +// +#define PLLCLK_BY_1 0 +#define PLLCLK_BY_2 1 +#define PLLCLK_BY_4 2 +#define PLLCLK_BY_6 3 +#define PLLCLK_BY_8 4 +#define PLLCLK_BY_10 5 +#define PLLCLK_BY_12 6 +#define PLLCLK_BY_14 7 +#define PLLCLK_BY_16 8 +#define PLLCLK_BY_18 9 +#define PLLCLK_BY_20 10 +#define PLLCLK_BY_22 11 +#define PLLCLK_BY_24 12 +#define PLLCLK_BY_26 13 +#define PLLCLK_BY_28 14 +#define PLLCLK_BY_30 15 +#define PLLCLK_BY_32 16 +#define PLLCLK_BY_34 17 +#define PLLCLK_BY_36 18 +#define PLLCLK_BY_38 19 +#define PLLCLK_BY_40 20 +#define PLLCLK_BY_42 21 +#define PLLCLK_BY_44 22 +#define PLLCLK_BY_46 23 +#define PLLCLK_BY_48 24 +#define PLLCLK_BY_50 25 +#define PLLCLK_BY_52 26 +#define PLLCLK_BY_54 27 +#define PLLCLK_BY_56 28 +#define PLLCLK_BY_58 29 +#define PLLCLK_BY_60 30 +#define PLLCLK_BY_62 31 +#define PLLCLK_BY_64 32 +#define PLLCLK_BY_66 33 +#define PLLCLK_BY_68 34 +#define PLLCLK_BY_70 35 +#define PLLCLK_BY_72 36 +#define PLLCLK_BY_74 37 +#define PLLCLK_BY_76 38 +#define PLLCLK_BY_78 39 +#define PLLCLK_BY_80 40 +#define PLLCLK_BY_82 41 +#define PLLCLK_BY_84 42 +#define PLLCLK_BY_86 43 +#define PLLCLK_BY_88 44 +#define PLLCLK_BY_90 45 +#define PLLCLK_BY_92 46 +#define PLLCLK_BY_94 47 +#define PLLCLK_BY_96 48 +#define PLLCLK_BY_98 49 +#define PLLCLK_BY_100 50 +#define PLLCLK_BY_102 51 +#define PLLCLK_BY_104 52 +#define PLLCLK_BY_106 53 +#define PLLCLK_BY_108 54 +#define PLLCLK_BY_110 55 +#define PLLCLK_BY_112 56 +#define PLLCLK_BY_114 57 +#define PLLCLK_BY_116 58 +#define PLLCLK_BY_118 59 +#define PLLCLK_BY_120 60 +#define PLLCLK_BY_122 61 +#define PLLCLK_BY_124 62 +#define PLLCLK_BY_126 63 + +// +// The following are values that can be passed to the +// InitAuxPll() to select divsel for AUXPLL +// +#define AUXPLLRAWCLK_BY_1 0 +#define AUXPLLRAWCLK_BY_2 1 +#define AUXPLLRAWCLK_BY_4 2 +#define AUXPLLRAWCLK_BY_8 3 + +// +// The following are values that can be passed to the +// IntOsc2Sel() & XtalOscSel() to select system PLL (or) AUX PLL +// +#define SYSTEM_PLL (Uint16) 0 +#define AUX_PLL (Uint16) 1 + +// +// The following are values that can be passed to the +// InitSysPll() & InitAuxPll() to select clock source +// +#define INT_OSC2 0 +#define XTAL_OSC 1 +#define INT_OSC1 2 +#define AUXCLKIN 4 + +// +// Specify the clock rate of the CPU (SYSCLKOUT) in nS. +// +// Take into account the input clock frequency and the PLL multiplier +// selected in step 1. +// +// Use one of the values provided, or define your own. +// The trailing L is required tells the compiler to treat +// the number as a 64-bit value. +// +// Only one statement should be uncommented. +// +// Example: 200 MHz devices: +// CLKIN is a 10 MHz crystal or internal 10 MHz oscillator +// +// In step 1 the user specified the PLL multiplier = 40 for a +// 200 MHz CPU clock (SYSCLKOUT = 200 MHz). +// +// In this case, the CPU_RATE will be 5.000L +// Uncomment the line: #define CPU_RATE 5.000L +// + +#define CPU_RATE 5.00L // for a 200MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 5.263L // for a 190MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 5.556L // for a 180MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 5.882L // for a 170MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 6.250L // for a 160MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 6.667L // for a 150MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.143L // for a 140MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 7.692L // for a 130MHz CPU clock speed (SYSCLKOUT) +//#define CPU_RATE 8.333L // for a 120MHz CPU clock speed (SYSCLKOUT) + +// +// The following pointer to a function call calibrates the ADC reference, +// DAC offset, and internal oscillators +// +#define Device_cal (void (*)(void))0x070282 + +// +// The following pointers to functions calibrate the ADC linearity. Use this +// in the AdcSetMode(...) function only +// +#define CalAdcaINL (void (*)(void))0x0703B4 +#define CalAdcbINL (void (*)(void))0x0703B2 +#define CalAdccINL (void (*)(void))0x0703B0 +#define CalAdcdINL (void (*)(void))0x0703AE + +// +// The following pointer to a function call looks up the ADC offset trim for a +// given condition. Use this in the AdcSetMode(...) function only. +// +#define GetAdcOffsetTrimOTP (Uint16 (*)(Uint16 OTPoffset))0x0703AC + +// +// Includes +// +#include "F2837xD_GlobalPrototypes.h" // Prototypes for global functions + // within the .c files. +#include "F2837xD_cputimervars.h" +#include "F2837xD_Cla_defines.h" // Macros used for CLA examples. +#include "F2837xD_EPwm_defines.h" // Macros used for PWM examples. +#include "F2837xD_Adc_defines.h" // Macros used for ADC examples. +#include "F2837xD_Emif_defines.h" // Macros used for EMIF examples. +#include "F2837xD_Gpio_defines.h" // Macros used for GPIO support code +#include "F2837xD_I2c_defines.h" // Macros used for I2C examples. +#include "F2837xD_Ipc_defines.h" // Macros used for IPC support code. +#include "F2837xD_Pie_defines.h" // Macros used for PIE examples. +#include "F2837xD_Dma_defines.h" // Macros used for DMA examples. +#include "F2837xD_SysCtrl_defines.h" // Macros used for LPM support code +#include "F2837xD_Upp_defines.h" // Macros used for UPP examples. + +#define PARTNO_2837xPACKAGEHERE 0x00 + +#define CPU_FRQ_200MHZ 1 +#define CPU_FRQ_150MHZ 0 +#define CPU_FRQ_120MHZ 0 + +// +// Include files not used with F/BIOS +// +#ifndef F28_BIOS +#include "F2837xD_defaultisr.h" +#endif + +extern void F28x_usDelay(long LoopCount); + +// +// DO NOT MODIFY THIS LINE. +// +#define DELAY_US(A) F28x_usDelay(((((long double) A * 1000.0L) / (long double)CPU_RATE) - 9.0L) / 5.0L) + +// +// Timer Operations: +// + +// +// Start Timer: +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer: +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value: +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value: +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value: +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// Start Timer: +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer: +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value: +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value: +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value: +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of F2837xD_EXAMPLES_H definition + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_GlobalPrototypes.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_GlobalPrototypes.h new file mode 100644 index 0000000000..1b63dc48ee --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_GlobalPrototypes.h @@ -0,0 +1,363 @@ +//########################################################################### +// +// FILE: F2837xD_GlobalPrototypes.h +// +// TITLE: Global prototypes for F2837xD Examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_GLOBALPROTOTYPES_H +#define F2837xD_GLOBALPROTOTYPES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Function Prototypes (Shared) +// +extern void EnableInterrupts(void); +extern void InitAPwm1Gpio(void); +extern void InitCAN(void); +extern void InitECap(void); +extern void InitECapGpio(void); +extern void InitECap1Gpio(Uint16 pin); +extern void InitECap2Gpio(Uint16 pin); +extern void InitECap3Gpio(Uint16 pin); +extern void InitECap4Gpio(Uint16 pin); +extern void InitECap5Gpio(Uint16 pin); +extern void InitECap6Gpio(Uint16 pin); +extern void InitEQep1Gpio(void); +extern void InitEQep2Gpio(void); +extern void InitEQep3Gpio(void); +extern void InitEPwmGpio(void); +extern void InitEPwm1Gpio(void); +extern void InitEPwm2Gpio(void); +extern void InitEPwm3Gpio(void); +extern void InitEPwm4Gpio(void); +extern void InitEPwm5Gpio(void); +extern void InitEPwm6Gpio(void); +extern void InitEPwm7Gpio(void); +extern void InitEPwm8Gpio(void); +extern void InitEPwm9Gpio(void); +extern void InitEPwm10Gpio(void); +extern void InitEPwm11Gpio(void); +extern void InitEPwm12Gpio(void); +extern void InitPeripheralClocks(void); +extern void DisablePeripheralClocks(void); +extern void InitPieCtrl(void); +extern void InitPieVectTable(void); +extern void InitSpi(void); +extern void InitSpiGpio(void); +extern void InitSpiaGpio(void); +extern void InitSysCtrl(void); +extern void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, + Uint16 divsel); +extern void InitAuxPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, + Uint16 divsel); + +#define KickDog ServiceDog // For compatibility with previous versions +extern void ServiceDog(void); +extern void DisableDog(void); + +extern Uint16 CsmUnlock(void); +extern void SysIntOsc1Sel (void); +extern void SysIntOsc2Sel (void); +extern void SysXtalOscSel (void); + +extern void AuxIntOsc2Sel (void); +extern void AuxXtalOscSel (void); +extern void AuxAuxClkSel (void); + +extern void SetDBGIER(Uint16 dbgier); + +// +// CAUTION +// This function MUST be executed out of RAM. Executing it +// out of OTP/Flash will yield unpredictable results +// +extern void InitFlash(void); +extern void InitFlash_Bank0(void); +extern void InitFlash_Bank1(void); +extern void FlashOff(void); +extern void FlashOff_Bank0(void); +extern void FlashOff_Bank1(void); +extern void SeizeFlashPump(void); +extern void SeizeFlashPump_Bank0(void); +extern void SeizeFlashPump_Bank1(void); +extern void ReleaseFlashPump(void); + +// +//LPM functions in F2837xD_SysCtrl.c +// +void IDLE(); +void STANDBY(); +void HALT(); +void HIB(); + +// +//ADC functions +// +extern void AdcSetMode(Uint16 adc, Uint16 resolution, Uint16 signalmode); +extern void CalAdcINL(Uint16 adc); + +// +// DMA Functions +// +extern void DMAInitialize(void); + +// +// DMA Channel 1 +// +extern void DMACH1AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH1(void); + +// +// DMA Channel 2 +// +extern void DMACH2AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH2(void); + +// +// DMA Channel 3 +// +extern void DMACH3AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH3(void); + +// +// DMA Channel 4 +// +extern void DMACH4AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH4(void); + +// +// DMA Channel 5 +// +extern void DMACH5AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep); +extern void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH5(void); + +// +// DMA Channel 6 +// +extern void DMACH6AddrConfig(volatile Uint16 *DMA_Dest, + volatile Uint16 *DMA_Source); +extern void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source); +extern void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep); +extern void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep); +extern void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep); +extern void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, + Uint16 chintmode, + Uint16 chinte); +extern void StartDMACH6(void); + +// +//GPIO Functions +// +extern void InitGpio(); +extern void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition); +extern void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags); +extern void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags); +extern void GPIO_SetupXINT1Gpio(Uint16 gpioNumber); +extern void GPIO_SetupXINT2Gpio(Uint16 gpioNumber); +extern void GPIO_SetupXINT3Gpio(Uint16 gpioNumber); +extern void GPIO_SetupXINT4Gpio(Uint16 gpioNumber); +extern void GPIO_SetupXINT5Gpio(Uint16 gpioNumber); +extern void GPIO_SelectIpcInt(Uint16 newFlag); +extern void GPIO_EnableUnbondedIOPullupsFor100Pin(void); +extern void GPIO_EnableUnbondedIOPullupsFor100Pin(void); +extern void GPIO_EnableUnbondedIOPullups(void); +Uint16 GPIO_ReadPin(Uint16 gpioNumber); +void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal); + +// +//IPC Functions +// +extern void InitIpc(); +extern Uint64 ReadIpcTimer(); +extern void SendIpcData(void *data, Uint16 word_length, Uint16 flag); +extern void RecvIpcData(void *recv_buf, Uint16 word_length); +extern void FillIpcSendData(Uint16 fill_data); +extern void SendIpcCommand(Uint32 command, Uint32 address, Uint32 data, + Uint16 flag); +extern void SendIpcFlag(Uint16 flag); +extern void AckIpcFlag(Uint16 flag); +extern void CancelIpcFlag(Uint16 flag); +extern void WaitForIpcFlag(Uint16 flag); +extern void WaitForIpcAck(Uint16 flag); +extern void IpcSync(Uint16 flag); + +// +// CAN Functions +// +extern void CanGpioPinMuxing(Uint32 ulBase, Uint16 canTxRxPin); +extern void CanAGpioConfig(Uint16 canaTxRxPin); +extern void CanBGpioConfig(Uint16 canbTxRxPin); +extern void CanModuleClkSelect(Uint32 ulBase, Uint16 ucSource); + +// +// I2C Functions +// +extern void I2cAGpioConfig(Uint16 I2caDataClkPin); +extern void I2cBGpioConfig(Uint16 I2cbDataClkPin); + +// +// McBSP functions +// McBSPA +// +extern void InitMcbspa(void); +extern void InitMcbspaInt(void); +extern void InitMcbspa8bit(void); +extern void InitMcbspa12bit(void); +extern void InitMcbspa16bit(void); +extern void InitMcbspa20bit(void); +extern void InitMcbspa24bit(void); +extern void InitMcbspa32bit(void); +extern void InitMcbspaGpio(void); +extern void delay_loop(void); + +// +// McBSPB +// +extern void InitMcbspb(void); +extern void InitMcbspbInt(void); +extern void InitMcbspb8bit(void); +extern void InitMcbspb12bit(void); +extern void InitMcbspb16bit(void); +extern void InitMcbspb20bit(void); +extern void InitMcbspb24bit(void); +extern void InitMcbspb32bit(void); +extern void InitMcbspbGpio(void); + +// +//Temp Sensor Functions +// +extern void InitTempSensor(float32 vrefhi_voltage); +extern int16 GetTemperatureC(int16 sensorSample); +extern int16 GetTemperatureK(int16 sensorSample); + +// +// External symbols created by the linker cmd file +// DSP28 examples will use these to relocate code from one LOAD location +// in Flash to a different RUN location in internal +// RAM +// +extern Uint16 RamfuncsLoadStart; +extern Uint16 RamfuncsLoadEnd; +extern Uint16 RamfuncsLoadSize; +extern Uint16 RamfuncsRunStart; +extern Uint16 RamfuncsRunEnd; +extern Uint16 RamfuncsRunSize; + +// +// External Boot ROM variable definitions +// +extern Uint16 EmuBMode; +extern Uint16 EmuBootPins; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_GLOBALPROTOTYPES_H + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Gpio_defines.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Gpio_defines.h new file mode 100644 index 0000000000..ecbff65618 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Gpio_defines.h @@ -0,0 +1,116 @@ +//########################################################################### +// +// FILE: F2837xD_Gpio_defines.h +// +// TITLE: F2837xD GPIO support definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_GPIO_DEFINES_H +#define F2837xD_GPIO_DEFINES_H + +// +// Defines +// + +// +//CPU pin masters for GPIO_SelectPinMux() +// +#define GPIO_MUX_CPU1 0x0 +#define GPIO_MUX_CPU1CLA 0x1 +#define GPIO_MUX_CPU2 0x2 +#define GPIO_MUX_CPU2CLA 0x3 + +// +//Flags for GPIO_SetupPinOptions(). The qualification flags (SYNC, QUAL3, +//QUAL6, and ASYNC) take up two bits and must be in the order specified. +// +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 +#define GPIO_PUSHPULL 0 +#define GPIO_PULLUP (1 << 0) +#define GPIO_INVERT (1 << 1) +#define GPIO_OPENDRAIN (1 << 2) +#define GPIO_SYNC (0x0 << 4) +#define GPIO_QUAL3 (0x1 << 4) +#define GPIO_QUAL6 (0x2 << 4) +#define GPIO_ASYNC (0x3 << 4) + +// +//Flags for GPIO_SetupLock(). +// +#define GPIO_UNLOCK 0 +#define GPIO_LOCK 1 + +// +//Commands for the CPU2->CPU1 GPIO configuration interrupt handler +// +#define GPIO_CMD_INIT 1L +#define GPIO_CMD_PINMUX 2L +#define GPIO_CMD_PINOPTS 3L +#define GPIO_CMD_WRITE32 4L +#define GPIO_CMD_WRITE16 5L +#define GPIO_CMD_READ32 6L +#define GPIO_CMD_READ16 7L + +// +//Helpful constants for array-based access to GPIO registers +// +#define GPY_CTRL_OFFSET (0x40/2) +#define GPY_DATA_OFFSET (0x8/2) + +#define GPYQSEL (0x2/2) +#define GPYMUX (0x6/2) +#define GPYDIR (0xA/2) +#define GPYPUD (0xC/2) +#define GPYINV (0x10/2) +#define GPYODR (0x12/2) +#define GPYGMUX (0x20/2) +#define GPYCSEL (0x28/2) +#define GPYLOCK (0x3C/2) +#define GPYCR (0x3E/2) + +#define GPYDAT (0x0/2) +#define GPYSET (0x2/2) +#define GPYCLEAR (0x4/2) +#define GPYTOGGLE (0x6/2) + +#endif // end of F2837xD_GPIO_DEFINES_H definition + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_I2c_defines.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_I2c_defines.h new file mode 100644 index 0000000000..95ed970e7f --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_I2c_defines.h @@ -0,0 +1,184 @@ +//########################################################################### +// +// FILE: F2837xD_I2c_defines.h +// +// TITLE: F2837xD I2C Common Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_I2C_DEFINES_H +#define F2837xD_I2C_DEFINES_H + +// +// Defines +// + +// +// Error Messages +// +#define I2C_ERROR 0xFFFF +#define I2C_ARB_LOST_ERROR 0x0001 +#define I2C_NACK_ERROR 0x0002 +#define I2C_BUS_BUSY_ERROR 0x1000 +#define I2C_STP_NOT_READY_ERROR 0x5555 +#define I2C_NO_FLAGS 0xAAAA +#define I2C_SUCCESS 0x0000 + +// +// Clear Status Flags +// +#define I2C_CLR_AL_BIT 0x0001 +#define I2C_CLR_NACK_BIT 0x0002 +#define I2C_CLR_ARDY_BIT 0x0004 +#define I2C_CLR_RRDY_BIT 0x0008 +#define I2C_CLR_SCD_BIT 0x0020 + +// +// Interrupt Source Messages +// +#define I2C_NO_ISRC 0x0000 +#define I2C_ARB_ISRC 0x0001 +#define I2C_NACK_ISRC 0x0002 +#define I2C_ARDY_ISRC 0x0003 +#define I2C_RX_ISRC 0x0004 +#define I2C_TX_ISRC 0x0005 +#define I2C_SCD_ISRC 0x0006 +#define I2C_AAS_ISRC 0x0007 + +// +// I2CMSG structure defines +// +#define I2C_NO_STOP 0 +#define I2C_YES_STOP 1 +#define I2C_RECEIVE 0 +#define I2C_TRANSMIT 1 +#define I2C_MAX_BUFFER_SIZE 16 + +// +// I2C Slave State defines +// +#define I2C_NOTSLAVE 0 +#define I2C_ADDR_AS_SLAVE 1 +#define I2C_ST_MSG_READY 2 + +// +// I2C Slave Receiver messages defines +// +#define I2C_SND_MSG1 1 +#define I2C_SND_MSG2 2 + +// +// I2C State defines +// +#define I2C_IDLE 0 +#define I2C_SLAVE_RECEIVER 1 +#define I2C_SLAVE_TRANSMITTER 2 +#define I2C_MASTER_RECEIVER 3 +#define I2C_MASTER_TRANSMITTER 4 + +// +// I2C Message Commands for I2CMSG struct +// +#define I2C_MSGSTAT_INACTIVE 0x0000 +#define I2C_MSGSTAT_SEND_WITHSTOP 0x0010 +#define I2C_MSGSTAT_WRITE_BUSY 0x0011 +#define I2C_MSGSTAT_SEND_NOSTOP 0x0020 +#define I2C_MSGSTAT_SEND_NOSTOP_BUSY 0x0021 +#define I2C_MSGSTAT_RESTART 0x0022 +#define I2C_MSGSTAT_READ_BUSY 0x0023 + +// +// Generic defines +// +#define I2C_TRUE 1 +#define I2C_FALSE 0 +#define I2C_YES 1 +#define I2C_NO 0 +#define I2C_DUMMY_BYTE 0 + + +// +// These are the Defines to select I2C pin muxing when calling the functions +// I2cAGpioConfig() & I2cBGpioConfig() in F2837xD_I2C.c +// +#define I2C_A_GPIO0_GPIO1 1 //switch case 1 +#define I2C_A_GPIO32_GPIO33 2 //switch case 2 +#define I2C_A_GPIO42_GPIO43 3 //switch case 3 +#define I2C_A_GPIO91_GPIO92 4 //switch case 4 +#define I2C_A_GPIO63104_GPIO105 5 //switch case 5 + +#define I2C_B_GPIO2_GPIO3 1 //switch case 1 +#define I2C_B_GPIO134_GPIO35 2 //switch case 2 +#define I2C_B_GPIO40_GPIO41 3 //switch case 3 +#define I2C_B_GPIO66_GPIO69 4 //switch case 4 + +// +// Globals +// + +// +// I2C Message Structure +// +struct I2CMSG { + Uint16 MsgStatus; // Word stating what state msg is in: + // I2C_MSGCMD_INACTIVE = do not send msg + // I2C_MSGCMD_BUSY = msg start has been sent, + // awaiting stop + // I2C_MSGCMD_SEND_WITHSTOP = command to send + // master trans msg complete with a stop bit + // I2C_MSGCMD_SEND_NOSTOP = command to send + // master trans msg without the stop bit + // I2C_MSGCMD_RESTART = command to send a + // restart as a master receiver with a + // stop bit + Uint16 SlaveAddress; // I2C address of slave msg is intended for + Uint16 NumOfBytes; // Num of valid bytes in (or to be put + // in MsgBuffer) + Uint16 MemoryHighAddr; // EEPROM address of data associated with + // msg (high byte) + Uint16 MemoryLowAddr; // EEPROM address of data associated with + // msg (low byte) + Uint16 MsgBuffer[I2C_MAX_BUFFER_SIZE]; // Array holding msg data - max that + // MAX_BUFFER_SIZE can be is 16 due + // to the FIFO's +}; + +#endif // end of F2837xD_I2C_DEFINES_H definition + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_defines.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_defines.h new file mode 100644 index 0000000000..404caee0b1 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_defines.h @@ -0,0 +1,70 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc_defines.h +// +// TITLE: F2837xD IPC support definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_IPC_DEFINES_H +#define F2837xD_IPC_DEFINES_H + +// +// Defines +// +#define C1TOC2_MSG_RAM ((void *)0x3FC00) +#define C2TOC1_MSG_RAM ((void *)0x3F800) + +#if defined(CPU1) + #define SEND_MSG_RAM C1TOC2_MSG_RAM + #define RECV_MSG_RAM C2TOC1_MSG_RAM +#elif defined(CPU2) + #define SEND_MSG_RAM C2TOC1_MSG_RAM + #define RECV_MSG_RAM C1TOC2_MSG_RAM +#endif +#define MSG_RAM_SIZE 0x400 + +// +//Used with SendIpcData() and SendIpcCommand() to avoid setting a flag +// +#define NO_IPC_FLAG 32 + +#endif // end of F2837xD_IPC_DEFINES_H definition + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_drivers.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_drivers.h new file mode 100644 index 0000000000..648ad6a83a --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Ipc_drivers.h @@ -0,0 +1,511 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc_drivers.h +// +// TITLE: Defines and Macros for the IPC Controller +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +//! \addtogroup ipc_driver_api +//! @{ +// + +#ifndef F2837xD_IPC_DRIVERS_H +#define F2837xD_IPC_DRIVERS_H + +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +#ifdef __cplusplus +extern "C" { +#endif + +// +// Included Files +// +#include "F2837xD_device.h" + +// +// Defines +// + +// +// The following are values that are used to define the maximum size of the +// global circular buffer variables g_asIPCCPU1toCPU2Buffers and +// g_asIPCCPU2toCPU1Buffers. They are also used in the IpcPut() and IpcGet() +// functions. IPC_BUFFER_SIZE and NUM_IPC_INTERRUPTS are user-configurable. +// +#define IPC_BUFFER_SIZE 4 // # of tIpcMessage messages in + // circular buffer + // (must be interval of 2) +#define NUM_IPC_INTERRUPTS 4 // # of IPC interrupts using circular + // buffer + // (must be same number on both CPUs +#define MAX_BUFFER_INDEX IPC_BUFFER_SIZE - 1 + +// +// The following are values that can be passed to IPCInitialize() +// as the usCPU1IpcInterrupt and usCPU2IpcInterrupt parameters +// +#define IPC_INT0 0x0001 +#define IPC_INT1 0x0002 +#define IPC_INT2 0x0003 +#define IPC_INT3 0x0004 + +// +// The following are values that are returned from all of the IPCCtoM command +// functions to determine whether the command was successfully sent or not. +// +#define STATUS_FAIL 0x0001 +#define STATUS_PASS 0x0000 + +// +// The following are values that can be passed to IPCReqMemAccess() as +// usMaster parameter to determine which processor to give master access to +// GSx blocks. +// +#define IPC_GSX_CPU1_MASTER 0x0001 +#define IPC_GSX_CPU2_MASTER 0x0000 + +// +// The following are values that can be passed to all IPC CPU1 to CPU2 or +// CPU2 to CPU1 command functions as bBlock parameter to determine whether to +// wait/block until a slot in PutBuffer is available if it is full, or to exit +// with a failure status. +// +#define ENABLE_BLOCKING 0x0001 +#define DISABLE_BLOCKING 0x0000 + +// +// The following are values that can be passed to IPCCtoMDataRead(), +// IPCCCtoMSetBits(),IPCCCtoMSetBits_Protected(), IPCCCtoMClearBits(), +// IPCCCtoMClearBits_Protected(), IPCCCtoMDataWrite(), +// IPCCtoMDataWrite_Protected() +// as usLength parameter to determine whether command applies to 16- or 32-bit +// data word. +// +#define IPC_LENGTH_16_BITS 0x00000001 +#define IPC_LENGTH_32_BITS 0x00000002 + +// +// The following are values that can be passed to IPCReqMemAccess() as +// ulMask parameter to configure GSxMSEL_REG register for master access to Sx +// RAM block. +// +#define GS0_ACCESS 0x00000001 // Master Access to GS0 +#define GS1_ACCESS 0x00000002 // Master Access to GS1 +#define GS2_ACCESS 0x00000004 // Master Access to GS2 +#define GS3_ACCESS 0x00000008 // Master Access to GS3 +#define GS4_ACCESS 0x00000010 // Master Access to GS4 +#define GS5_ACCESS 0x00000020 // Master Access to GS5 +#define GS6_ACCESS 0x00000040 // Master Access to GS6 +#define GS7_ACCESS 0x00000080 // Master Access to GS7 +#define GS8_ACCESS 0x00000100 // Master Access to GS8 +#define GS9_ACCESS 0x00000200 // Master Access to GS9 +#define GS10_ACCESS 0x00000400 // Master Access to GS10 +#define GS11_ACCESS 0x00000800 // Master Access to GS11 +#define GS12_ACCESS 0x00001000 // Master Access to GS12 +#define GS13_ACCESS 0x00002000 // Master Access to GS13 +#define GS14_ACCESS 0x00004000 // Master Access to GS14 +#define GS15_ACCESS 0x00008000 // Master Access to GS15 + +// +// The following are values that can be passed to IPCCtoMTaskBusy() as the +// ulFlags parameter. +// IPC_FLAG17 - IPC_FLAG32 can also be passed to IPCtoMDataRead() and +// IPCCtoMReadBlock() as the ulResponseFlag parameter. +// +#define NO_FLAG 0x00000000 // NO FLAG +#define IPC_FLAG0 0x00000001 // IPC FLAG 0 +#define IPC_FLAG1 0x00000002 // IPC FLAG 1 +#define IPC_FLAG2 0x00000004 // IPC FLAG 2 +#define IPC_FLAG3 0x00000008 // IPC FLAG 3 +#define IPC_FLAG4 0x00000010 // IPC FLAG 4 +#define IPC_FLAG5 0x00000020 // IPC FLAG 5 +#define IPC_FLAG6 0x00000040 // IPC FLAG 6 +#define IPC_FLAG7 0x00000080 // IPC FLAG 7 +#define IPC_FLAG8 0x00000100 // IPC FLAG 8 +#define IPC_FLAG9 0x00000200 // IPC FLAG 9 +#define IPC_FLAG10 0x00000400 // IPC FLAG 10 +#define IPC_FLAG11 0x00000800 // IPC FLAG 11 +#define IPC_FLAG12 0x00001000 // IPC FLAG 12 +#define IPC_FLAG13 0x00002000 // IPC FLAG 13 +#define IPC_FLAG14 0x00004000 // IPC FLAG 14 +#define IPC_FLAG15 0x00008000 // IPC FLAG 15 +#define IPC_FLAG16 0x00010000 // IPC FLAG 16 +#define IPC_FLAG17 0x00020000 // IPC FLAG 17 +#define IPC_FLAG18 0x00040000 // IPC FLAG 18 +#define IPC_FLAG19 0x00080000 // IPC FLAG 19 +#define IPC_FLAG20 0x00100000 // IPC FLAG 20 +#define IPC_FLAG21 0x00200000 // IPC FLAG 21 +#define IPC_FLAG22 0x00400000 // IPC FLAG 22 +#define IPC_FLAG23 0x00800000 // IPC FLAG 23 +#define IPC_FLAG24 0x01000000 // IPC FLAG 24 +#define IPC_FLAG25 0x02000000 // IPC FLAG 25 +#define IPC_FLAG26 0x04000000 // IPC FLAG 26 +#define IPC_FLAG27 0x08000000 // IPC FLAG 27 +#define IPC_FLAG28 0x10000000 // IPC FLAG 28 +#define IPC_FLAG29 0x20000000 // IPC FLAG 29 +#define IPC_FLAG30 0x40000000 // IPC FLAG 30 +#define IPC_FLAG31 0x80000000 // IPC FLAG 31 + +// +// The following are values that are used by all command functions and passed +// between processors in tIpcMessage.ulmessage or in the xTOyIPCCOM register +// to determine what command is requested by the sending processor. +// +#define IPC_SET_BITS_16 0x00000001 // Used for IPC-Lite +#define IPC_SET_BITS_32 0x00000002 // Used for IPC-Lite +#define IPC_CLEAR_BITS_16 0x00000003 // Used for IPC-Lite +#define IPC_CLEAR_BITS_32 0x00000004 // Used for IPC-Lite +#define IPC_DATA_WRITE_16 0x00000005 // Used for IPC-Lite +#define IPC_DATA_WRITE_32 0x00000006 // Used for IPC-Lite +#define IPC_DATA_READ_16 0x00000007 // Used for Boot ROM +#define IPC_DATA_READ_32 0x00000008 // Used for Boot ROM +#define IPC_DATA_READ 0x00000008 +#define IPC_SET_BITS_16_PROTECTED 0x00000009 // Used for IPC-Lite +#define IPC_SET_BITS_32_PROTECTED 0x0000000A // Used for IPC-Lite +#define IPC_CLEAR_BITS_16_PROTECTED 0x0000000B // Used for IPC-Lite +#define IPC_CLEAR_BITS_32_PROTECTED 0x0000000C // Used for IPC-Lite +#define IPC_DATA_WRITE_16_PROTECTED 0x0000000D // Used for IPC-Lite +#define IPC_DATA_WRITE_32_PROTECTED 0x0000000E // Used for IPC-Lite + +// +// 0x0000000F and 0x0000010 are reserved by boot ROM +// + +#define IPC_BRANCH 0x00000011 +#define IPC_FUNC_CALL 0x00000012 +#define IPC_MTOC_EXECUTE_BOOTMODE_CMD 0x00000013 + +#define IPC_SET_BITS 0x00010001 +#define IPC_CLEAR_BITS 0x00010002 +#define IPC_DATA_WRITE 0x00010003 +#define IPC_BLOCK_READ 0x00010004 +#define IPC_BLOCK_WRITE 0x00010005 +#define IPC_DATA_READ_PROTECTED 0x00010007 +#define IPC_SET_BITS_PROTECTED 0x00010008 +#define IPC_CLEAR_BITS_PROTECTED 0x00010009 +#define IPC_DATA_WRITE_PROTECTED 0x0001000A +#define IPC_BLOCK_WRITE_PROTECTED 0x0001000B + +// +// The following are values that can be passed into the +// IPCBootControlSystem() function in the ulBootMode parameter. +// +#define BROM_IPC_EXECUTE_BOOTMODE_CMD 0x00000013 + +// +// Below are the values programmed into IPCBOOTMODE register +// +#define C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL 0x00000000 +#define C1C2_BROM_BOOTMODE_BOOT_FROM_SCI 0x00000001 +#define C1C2_BROM_BOOTMODE_BOOT_FROM_SPI 0x00000004 +#define C1C2_BROM_BOOTMODE_BOOT_FROM_I2C 0x00000005 +#define C1C2_BROM_BOOTMODE_BOOT_FROM_CAN 0x00000007 +#define C1C2_BROM_BOOTMODE_BOOT_FROM_RAM 0x0000000A +#define C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH 0x0000000B + +// +// The following value is used by the +// IPCBootControlSystem() function to limit the allowed boot mode values. +// +#define C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE 0x0000000C + +// +// The following values report on the CPU02 boot ROM status at all times while +// the CPU02 is booting, and will reside in IPCBOOTSTS[11:0]. +// + +// +// CPU02 has not filled in a valid value yet +// +#define C2_BOOTROM_BOOTSTS_C2TOC1_IGNORE 0x00000000 + +// +// CPU02 has started to boot, but not completed +// the boot process yet +// +#define C2_BOOTROM_BOOTSTS_SYSTEM_START_BOOT 0x00000001 + +// +// CPU02 has completed the boot and is ready for +// CPU01 TO CPU02 IPC commands +// +#define C2_BOOTROM_BOOTSTS_SYSTEM_READY 0x00000002 + +// +// CPU02 ACKs the command in CPU01 TO CPU01 +// BOOTMODE register +// +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK 0x00000003 + +// +// CPU02 un-supported command in CPU01 TO CPU01 +// BOOTMODE register +// +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_NOT_SUPPORTED 0x00000004 + +// +// CPU2 NAKs the current boot command in +// CPU01 TO CPU01 BOOTMODE register +// +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_BUSY_WITH_BOOT 0x00000005 + +// +//! A structure that defines an IPC message. These fields are used by the +//! IPC drivers to determine handling of data passed between processors. +//! Although they have a defined naming scheme, they can also be used +//! generically +//! to pass 32-bit data words between processors. +// +typedef struct +{ + //! The command passed between processor systems. + uint32_t ulcommand; + + //! The receiving processor address the command is requesting action on. + uint32_t uladdress; + + //! A 32-bit variable, the usage of which is determined by ulcommand. + //! The most common usage is to pass length requirements + //! with the upper 16-bits storing a Response Flag for read commands. + uint32_t uldataw1; + + //! A 32-bit variable, the usage of which is determined by ulcommand. + //! For block transfers, this variable is generally the address in + //! shared memory used to pass data between processors. + uint32_t uldataw2; + +} tIpcMessage; + +// +//! A structure that defines an IPC control instance. These +//! fields are used by the IPC drivers, and normally it is not necessary for +//! user software to directly read or write fields in the table. +// +typedef struct +{ + //! The address of the PutBuffer IPC message (in MSGRAM) + tIpcMessage *psPutBuffer; + + //! The IPC INT flag to set when sending messages + //! for this IPC controller instance. + uint32_t ulPutFlag; + + //! The address of the PutBuffer Write index (in MSGRAM) + uint16_t *pusPutWriteIndex; + + //! The address of the PutBuffer Read index (in MSGRAM) + uint16_t *pusPutReadIndex; + + //! The address of the GetBuffer IPC message(in MSGRAM) + tIpcMessage *psGetBuffer; + + //! The address of the GetBuffer Write Index (in MSGRAM) + uint16_t *pusGetWriteIndex; + + //! The address of the GetBuffer Read Index (in MSGRAM) + uint16_t *pusGetReadIndex; + +} tIpcController; + +// +// A type definition for the IPC function call command. +// +typedef uint32_t (*tfIpcFuncCall)(uint32_t ulParam); + +// +// Prototypes for Circular Buffers +// +extern tIpcMessage g_asIPCCPU1toCPU2Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE]; +extern tIpcMessage g_asIPCCPU2toCPU1Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE]; + +// +// Function Prototypes +// +extern void IPCInitialize (volatile tIpcController *psController, + uint16_t usCPU2IpcInterrupt, + uint16_t usCPU1IpcInterrupt); +extern uint16_t IpcPut (volatile tIpcController *psController, + tIpcMessage *psMessage, + uint16_t bBlock); +extern uint16_t IpcGet (volatile tIpcController *psController, + tIpcMessage *psMessage, + uint16_t bBlock); +extern uint16_t IPCLtoRDataRead (volatile tIpcController *psController, + uint32_t ulAddress, void *pvData, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag); +extern uint16_t IPCLtoRDataRead_Protected (volatile tIpcController *psController, + uint32_t ulAddress, void *pvData, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag); +extern uint16_t IPCLtoRSetBits(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength,uint16_t bBlock); +extern uint16_t IPCLtoRSetBits_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength, uint16_t bBlock); +extern uint16_t IPCLtoRClearBits(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength,uint16_t bBlock); +extern uint16_t IPCLtoRClearBits_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength, uint16_t bBlock); +extern uint16_t IPCLtoRDataWrite(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulData, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag); +extern uint16_t IPCLtoRDataWrite_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulData, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag); +extern uint16_t IPCLtoRBlockRead(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulShareAddress, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag); +extern uint16_t IPCLtoRBlockWrite(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulShareAddress, + uint16_t usLength, uint16_t usWordLength, + uint16_t bBlock); +extern uint16_t IPCLtoRBlockWrite_Protected(volatile tIpcController *psController, + uint32_t ulAddress, + uint32_t ulShareAddress, + uint16_t usLength, + uint16_t usWordLength, + uint16_t bBlock); +extern uint16_t IPCLtoRFunctionCall(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulParam, + uint16_t bBlock); +extern uint16_t IPCLtoRSendMessage(volatile tIpcController *psController, + uint32_t ulCommand, uint32_t ulAddress, + uint32_t ulDataW1, uint32_t ulDataW2, + uint16_t bBlock); +#if defined (CPU2) +uint16_t +IPCReqMemAccess (volatile tIpcController *psController, uint32_t ulMask, + uint16_t usMaster, uint16_t bBlock); +#endif + +extern void IPCRtoLDataWrite(tIpcMessage *psMessage); +extern void IPCRtoLDataWrite_Protected(tIpcMessage *psMessage); +extern void IPCRtoLDataRead(volatile tIpcController *psController, + tIpcMessage *psMessage, uint16_t bBlock); +extern void IPCRtoLDataRead_Protected(volatile tIpcController *psController, + tIpcMessage *psMessage,uint16_t bBlock); +extern void IPCRtoLSetBits(tIpcMessage *psMessage); +extern void IPCRtoLSetBits_Protected(tIpcMessage *psMessage); +extern void IPCRtoLClearBits(tIpcMessage *psMessage); +extern void IPCRtoLClearBits_Protected(tIpcMessage *psMessage); +extern void IPCRtoLBlockRead(tIpcMessage *psMessage); +extern void IPCRtoLBlockWrite(tIpcMessage *psMessage); +extern void IPCRtoLBlockWrite_Protected(tIpcMessage *psMessage); +extern void IPCRtoLFunctionCall(tIpcMessage *psMessage); + +// +// IPC Lite Driver Prototype Definitions +// +extern uint16_t IPCLiteLtoRGetResult (void *pvData, uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRDataRead(uint32_t ulFlag, uint32_t ulAddress, + uint16_t usLength, uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRSetBits(uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRSetBits_Protected (uint32_t ulFlag, + uint32_t ulAddress, + uint32_t ulMask, + uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRClearBits(uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRClearBits_Protected (uint32_t ulFlag, + uint32_t ulAddress, + uint32_t ulMask, + uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRDataWrite(uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulData, uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRDataWrite_Protected(uint32_t ulFlag, + uint32_t ulAddress, + uint32_t ulData, + uint16_t usLength, + uint32_t ulStatusFlag); +extern uint16_t IPCLiteLtoRFunctionCall(uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulParam, uint32_t ulStatusFlag); +extern uint16_t IPCLiteReqMemAccess (uint32_t ulFlag, uint32_t ulMask, + uint16_t ulMaster, uint32_t ulStatusFlag); +extern void IPCLiteRtoLDataRead(uint32_t ulFlag, uint32_t ulStatusFlag); +extern void IPCLiteRtoLSetBits(uint32_t ulFlag, uint32_t ulStatusFlag); +extern void IPCLiteRtoLSetBits_Protected (uint32_t ulFlag, uint32_t ulStatusFlag); +extern void IPCLiteRtoLClearBits(uint32_t ulFlag, uint32_t ulStatusFlag); +extern void IPCLiteRtoLClearBits_Protected (uint32_t ulFlag, + uint32_t ulStatusFlag); +extern void IPCLiteRtoLDataWrite(uint32_t ulFlag, uint32_t ulStatusFlag); +extern void IPCLiteRtoLDataWrite_Protected(uint32_t ulFlag, + uint32_t ulStatusFlag); +extern void IPCLiteRtoLFunctionCall(uint32_t ulFlag, uint32_t ulStatusFlag); + +// +// IPC Utility Driver Prototype Definitions +// +extern void IPCRtoLFlagAcknowledge (uint32_t ulFlags); +extern Uint16 IPCRtoLFlagBusy (uint32_t ulFlags); +extern Uint16 IPCLtoRFlagBusy (uint32_t ulFlags); +extern void IPCLtoRFlagSet (uint32_t ulFlags); +extern void IPCLtoRFlagClear (uint32_t ulFlags); +extern uint32_t IPCGetBootStatus (void); +extern uint16_t IPCBootCPU2(uint32_t ulBootMode); +#ifdef __cplusplus +} +#endif /* extern "C" */ + +// +// Close the Doxygen group. +//! @} +// + +#endif // end of F2837xD_IPC_DRIVERS_H definition + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Pie_defines.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Pie_defines.h new file mode 100644 index 0000000000..1905d88ca8 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Pie_defines.h @@ -0,0 +1,74 @@ +//########################################################################### +// +// FILE: F2837xD_Pie_defines.h +// +// TITLE: #defines used in PIE examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_PIE_DEFINES_H +#define F2837xD_PIE_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define PIEACK_GROUP1 0x0001 +#define PIEACK_GROUP2 0x0002 +#define PIEACK_GROUP3 0x0004 +#define PIEACK_GROUP4 0x0008 +#define PIEACK_GROUP5 0x0010 +#define PIEACK_GROUP6 0x0020 +#define PIEACK_GROUP7 0x0040 +#define PIEACK_GROUP8 0x0080 +#define PIEACK_GROUP9 0x0100 +#define PIEACK_GROUP10 0x0200 +#define PIEACK_GROUP11 0x0400 +#define PIEACK_GROUP12 0x0800 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_PIE_DEFINES_H + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_SWPrioritizedIsrLevels.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_SWPrioritizedIsrLevels.h new file mode 100644 index 0000000000..6fd2700965 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_SWPrioritizedIsrLevels.h @@ -0,0 +1,20681 @@ +//########################################################################### +// +// FILE: F2837xD_SWPrioritizedIsrLevels.h +// +// TITLE: F28 Devices Software Prioritized Interrupt Service Routine +// Level definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_SW_PRIORITZIED_ISR_H +#define F2837xD_SW_PRIORITZIED_ISR_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Interrupt Enable Register Allocation For F2837xD Devices: +// +// Interrupts can be enabled/disabled using the CPU interrupt enable register +// (IER) and the PIE interrupt enable registers (PIEIER1 to PIEIER12). +// +// +// Set "Global" Interrupt Priority Level (IER register): +// +// The user must set the appropriate priority level for each of the CPU +// interrupts. This is termed as the "global" priority. The priority level +// must be a number between 1 (highest) to 16 (lowest). A value of 0 must +// be entered for reserved interrupts or interrupts that are not used. This +// will also reduce code size by not including ISR's that are not used. +// +// Note: The priority levels below are used to calculate the IER register +// interrupt masks MINT1 to MINT16. +// +// +// Note: The priority levels shown here may not make sense in a +// real application. This is for demonstration purposes only!!! +// +// The user should change these to values that make sense for +// their application. +// +// 0 = not used +// 1 = highest priority +// ... +// 16 = lowest priority +// +#define INT1PL 2 // Group1 Interrupts (PIEIER1) +#define INT2PL 1 // Group2 Interrupts (PIEIER2) +#define INT3PL 4 // Group3 Interrupts (PIEIER3) +#define INT4PL 2 // Group4 Interrupts (PIEIER4) +#define INT5PL 2 // Group5 Interrupts (PIEIER5) +#define INT6PL 3 // Group6 Interrupts (PIEIER6) +#define INT7PL 5 // Group7 Interrupts (PIEIER6) +#define INT8PL 5 // Group8 Interrupts (PIEIER6) +#define INT9PL 3 // Group9 Interrupts (PIEIER9) +#define INT10PL 6 // Group10 Interrupts (PIEIER6) +#define INT11PL 6 // Group11 Interrupts (PIEIER6) +#define INT12PL 8 // Group12 Interrupts (PIEIER6) +#define INT13PL 4 // XINT13 +#define INT14PL 4 // INT14 (TINT2) +#define INT15PL 4 // DATALOG +#define INT16PL 4 // RTOSINT + +// +// Set "Group" Interrupt Priority Level (PIEIER1 to PIEIER12 registers): +// +// The user must set the appropriate priority level for each of the PIE +// interrupts. This is termed as the "group" priority. The priority level +// must be a number between 1 (highest) to 16 (lowest). A value of 0 must +// be entered for reserved interrupts or interrupts that are not used. This +// will also reduce code size by not including ISR's that are not used: +// +// Note: The priority levels below are used to calculate the following +// PIEIER register interrupt masks: +// MG1_1 to MG1_16 +// MG2_1 to MG2_16 +// MG3_1 to MG3_16 +// MG4_1 to MG4_16 +// MG5_1 to MG5_16 +// MG6_1 to MG6_16 +// MG7_1 to MG7_16 +// MG8_1 to MG8_16 +// MG9_1 to MG9_16 +// MG10_1 to MG10_16 +// MG11_1 to MG11_16 +// MG12_1 to MG12_16 +// +// Note: The priority levels shown here may not make sense in a +// real application. This is for demonstration purposes only!!! +// +// The user should change these to values that make sense for +// their application. +// +// 0 = not used +// 1 = highest priority +// ... +// 16 = lowest priority +// +#define G1_1PL 5 // ADCA1_INT +#define G1_2PL 3 // ADCB1_INT +#define G1_3PL 1 // ADCC1_INT +#define G1_4PL 4 // XINT1_INT +#define G1_5PL 4 // XINT2_INT +#define G1_6PL 1 // ADCD1_INT +#define G1_7PL 12 // TIMER0_INT +#define G1_8PL 5 // WAKE_INT +#define G1_9PL 0 // Reserved +#define G1_10PL 0 // Reserved +#define G1_11PL 0 // Reserved +#define G1_12PL 0 // Reserved +#define G1_13PL 8 // IPC1_INT +#define G1_14PL 13 // IPC2_INT +#define G1_15PL 15 // IPC3_INT +#define G1_16PL 9 // IPC4_INT + +#define G2_1PL 13 // EPWM1_TZ_INT +#define G2_2PL 1 // EPWM2_TZ_INT +#define G2_3PL 1 // EPWM3_TZ_INT +#define G2_4PL 9 // EPWM4_TZ_INT +#define G2_5PL 3 // EPWM5_TZ_INT +#define G2_6PL 13 // EPWM6_TZ_INT +#define G2_7PL 9 // EPWM7_TZ_INT +#define G2_8PL 13 // EPWM8_TZ_INT +#define G2_9PL 15 // EPWM9_TZ_INT +#define G2_10PL 11 // EPWM10_TZ_INT +#define G2_11PL 7 // EPWM11_TZ_INT +#define G2_12PL 10 // EPWM12_TZ_INT +#define G2_13PL 0 // Reserved +#define G2_14PL 0 // Reserved +#define G2_15PL 0 // Reserved +#define G2_16PL 0 // Reserved + +#define G3_1PL 5 // EPWM1_INT +#define G3_2PL 9 // EPWM2_INT +#define G3_3PL 5 // EPWM3_INT +#define G3_4PL 2 // EPWM4_INT +#define G3_5PL 12 // EPWM5_INT +#define G3_6PL 4 // EPWM6_INT +#define G3_7PL 2 // EPWM7_INT +#define G3_8PL 13 // EPWM8_INT +#define G3_9PL 4 // EPWM9_INT +#define G3_10PL 12 // EPWM10_INT +#define G3_11PL 4 // EPWM11_INT +#define G3_12PL 14 // EPWM12_INT +#define G3_13PL 0 // Reserved +#define G3_14PL 0 // Reserved +#define G3_15PL 0 // Reserved +#define G3_16PL 0 // Reserved + +#define G4_1PL 3 // ECAP1_INT +#define G4_2PL 3 // ECAP2_INT +#define G4_3PL 3 // ECAP3_INT +#define G4_4PL 6 // ECAP4_INT +#define G4_5PL 7 // ECAP5_INT +#define G4_6PL 7 // ECAP6_INT +#define G4_7PL 0 // Reserved +#define G4_8PL 0 // Reserved +#define G4_9PL 0 // Reserved +#define G4_10PL 0 // Reserved +#define G4_11PL 0 // Reserved +#define G4_12PL 0 // Reserved +#define G4_13PL 0 // Reserved +#define G4_14PL 0 // Reserved +#define G4_15PL 0 // Reserved +#define G4_16PL 0 // Reserved + +#define G5_1PL 6 // EQEP1_INT +#define G5_2PL 5 // EQEP2_INT +#define G5_3PL 5 // EQEP3_INT +#define G5_4PL 1 // Reserved +#define G5_5PL 9 // CLB1_INT +#define G5_6PL 10 // CLB2_INT +#define G5_7PL 15 // CLB3_INT +#define G5_8PL 13 // CLB4_INT +#define G5_9PL 12 // SD1_INT +#define G5_10PL 9 // SD2_INT +#define G5_11PL 0 // Reserved +#define G5_12PL 0 // Reserved +#define G5_13PL 0 // Reserved +#define G5_14PL 0 // Reserved +#define G5_15PL 0 // Reserved +#define G5_16PL 0 // Reserved + +#define G6_1PL 1 // SPIA_RX_INT +#define G6_2PL 7 // SPIA_TX_INT +#define G6_3PL 3 // SPIB_RX_INT +#define G6_4PL 3 // SPIB_TX_INT +#define G6_5PL 10 // MCBSPA_RX_INT +#define G6_6PL 7 // MCBSPA_TX_INT +#define G6_7PL 6 // MCBSPB_RX_INT +#define G6_8PL 13 // MCBSPB_TX_INT +#define G6_9PL 14 // SPIC_RX_INT +#define G6_10PL 3 // SPIC_TX_INT +#define G6_11PL 0 // Reserved +#define G6_12PL 0 // Reserved +#define G6_13PL 0 // Reserved +#define G6_14PL 0 // Reserved +#define G6_15PL 0 // Reserved +#define G6_16PL 0 // Reserved + +#define G7_1PL 1 // DMA_CH1_INT +#define G7_2PL 11 // DMA_CH2_INT +#define G7_3PL 14 // DMA_CH3_INT +#define G7_4PL 3 // DMA_CH4_INT +#define G7_5PL 13 // DMA_CH5_INT +#define G7_6PL 14 // DMA_CH6_INT +#define G7_7PL 0 // Reserved +#define G7_8PL 0 // Reserved +#define G7_9PL 0 // Reserved +#define G7_10PL 0 // Reserved +#define G7_11PL 0 // Reserved +#define G7_12PL 0 // Reserved +#define G7_13PL 0 // Reserved +#define G7_14PL 0 // Reserved +#define G7_15PL 0 // Reserved +#define G7_16PL 0 // Reserved + +#define G8_1PL 14 // I2CA_INT +#define G8_2PL 10 // I2CA_FIFO_INT +#define G8_3PL 11 // I2CB_INT +#define G8_4PL 9 // I2CB_FIFO_INT +#define G8_5PL 12 // SCIC_RX_INT +#define G8_6PL 2 // SCIC_TX_INT +#define G8_7PL 8 // SCID_RX_INT +#define G8_8PL 7 // SCID_TX_INT +#define G8_9PL 0 // Reserved +#define G8_10PL 0 // Reserved +#define G8_11PL 0 // Reserved +#define G8_12PL 0 // Reserved +#define G8_13PL 0 // Reserved +#define G8_14PL 0 // Reserved +#define G8_15PL 1 // UPPA_INT +#define G8_16PL 0 // Reserved + +#define G9_1PL 12 // SCIA_RX_INT +#define G9_2PL 14 // SCIA_TX_INT +#define G9_3PL 11 // SCIB_RX_INT +#define G9_4PL 6 // SCIB_TX_INT +#define G9_5PL 14 // CANA0_INT +#define G9_6PL 10 // CANA1_INT +#define G9_7PL 10 // CANB0_INT +#define G9_8PL 5 // CANB1_INT +#define G9_9PL 0 // Reserved +#define G9_10PL 0 // Reserved +#define G9_11PL 0 // Reserved +#define G9_12PL 0 // Reserved +#define G9_13PL 0 // Reserved +#define G9_14PL 0 // Reserved +#define G9_15PL 12 // USBA_INT +#define G9_16PL 0 // Reserved + +#define G10_1PL 14 // ADCA_EVT_INT +#define G10_2PL 3 // ADCA2_INT +#define G10_3PL 1 // ADCA3_INT +#define G10_4PL 12 // ADCA4_INT +#define G10_5PL 5 // ADCB_EVT_INT +#define G10_6PL 11 // ADCB2_INT +#define G10_7PL 12 // ADCB3_INT +#define G10_8PL 13 // ADCB4_INT +#define G10_9PL 7 // ADCC_EVT_INT +#define G10_10PL 8 // ADCC2_INT +#define G10_11PL 4 // ADCC3_INT +#define G10_12PL 9 // ADCC4_INT +#define G10_13PL 2 // ADCD_EVT_INT +#define G10_14PL 10 // ADCD2_INT +#define G10_15PL 11 // ADCD3_INT +#define G10_16PL 5 // ADCD4_INT + +#define G11_1PL 9 // CLA1_1_INT +#define G11_2PL 6 // CLA1_2_INT +#define G11_3PL 9 // CLA1_3_INT +#define G11_4PL 9 // CLA1_4_INT +#define G11_5PL 6 // CLA1_5_INT +#define G11_6PL 13 // CLA1_6_INT +#define G11_7PL 10 // CLA1_7_INT +#define G11_8PL 15 // CLA1_8_INT +#define G11_9PL 0 // Reserved +#define G11_10PL 0 // Reserved +#define G11_11PL 0 // Reserved +#define G11_12PL 0 // Reserved +#define G11_13PL 0 // Reserved +#define G11_14PL 0 // Reserved +#define G11_15PL 0 // Reserved +#define G11_16PL 0 // Reserved + +#define G12_1PL 3 // XINT3_INT +#define G12_2PL 6 // XINT4_INT +#define G12_3PL 10 // XINT5_INT +#define G12_4PL 5 // Reserved +#define G12_5PL 2 // FMC_INT +#define G12_6PL 11 // VCU_INT +#define G12_7PL 14 // FPU_OVERFLOW_ISR +#define G12_8PL 14 // FPU_UNDERFLOW_ISR +#define G12_9PL 6 // EMIF_ERROR_ISR +#define G12_10PL 5 // RAM_CORRECTABLE_ERROR_ISR +#define G12_11PL 4 // FLASH_CORRECTABLE_ERROR_ISR +#define G12_12PL 12 // RAM_ACCESS_VIOLATION_INT +#define G12_13PL 8 // SYS_PLL_SLIP_INT +#define G12_14PL 2 // AUX_PLL_SLIP_INT +#define G12_15PL 12 // CLA_UNDERFLOW_INT +#define G12_16PL 2 // CLA_OVERFLOW_INT + +// +// There should be no need to modify code below this line +// +// Automatically generate IER interrupt masks MINT1 to MINT16: +// +// Beginning of MINT1: +#if (INT1PL == 0) +#define MINT1_1PL ~(1 << 0) +#else +#define MINT1_1PL 0xFFFF +#endif + +#if (INT2PL >= INT1PL) || (INT2PL == 0) +#define MINT1_2PL ~(1 << 1) +#else +#define MINT1_2PL 0xFFFF +#endif + +#if (INT3PL >= INT1PL) || (INT3PL == 0) +#define MINT1_3PL ~(1 << 2) +#else +#define MINT1_3PL 0xFFFF +#endif + +#if (INT4PL >= INT1PL) || (INT4PL == 0) +#define MINT1_4PL ~(1 << 3) +#else +#define MINT1_4PL 0xFFFF +#endif + +#if (INT5PL >= INT1PL) || (INT5PL == 0) +#define MINT1_5PL ~(1 << 4) +#else +#define MINT1_5PL 0xFFFF +#endif + +#if (INT6PL >= INT1PL) || (INT6PL == 0) +#define MINT1_6PL ~(1 << 5) +#else +#define MINT1_6PL 0xFFFF +#endif + +#if (INT7PL >= INT1PL) || (INT7PL == 0) +#define MINT1_7PL ~(1 << 6) +#else +#define MINT1_7PL 0xFFFF +#endif + +#if (INT8PL >= INT1PL) || (INT8PL == 0) +#define MINT1_8PL ~(1 << 7) +#else +#define MINT1_8PL 0xFFFF +#endif + +#if (INT9PL >= INT1PL) || (INT9PL == 0) +#define MINT1_9PL ~(1 << 8) +#else +#define MINT1_9PL 0xFFFF +#endif + +#if (INT10PL >= INT1PL) || (INT10PL == 0) +#define MINT1_10PL ~(1 << 9) +#else +#define MINT1_10PL 0xFFFF +#endif + +#if (INT11PL >= INT1PL) || (INT11PL == 0) +#define MINT1_11PL ~(1 << 10) +#else +#define MINT1_11PL 0xFFFF +#endif + +#if (INT12PL >= INT1PL) || (INT12PL == 0) +#define MINT1_12PL ~(1 << 11) +#else +#define MINT1_12PL 0xFFFF +#endif + +#if (INT13PL >= INT1PL) || (INT13PL == 0) +#define MINT1_13PL ~(1 << 12) +#else +#define MINT1_13PL 0xFFFF +#endif + +#if (INT14PL >= INT1PL) || (INT14PL == 0) +#define MINT1_14PL ~(1 << 13) +#else +#define MINT1_14PL 0xFFFF +#endif + +#if (INT15PL >= INT1PL) || (INT15PL == 0) +#define MINT1_15PL ~(1 << 14) +#else +#define MINT1_15PL 0xFFFF +#endif + +#if (INT16PL >= INT1PL) || (INT16PL == 0) +#define MINT1_16PL ~(1 << 15) +#else +#define MINT1_16PL 0xFFFF +#endif + +#define MINT1 (MINT1_1PL & MINT1_2PL & MINT1_3PL & MINT1_4PL & \ + MINT1_5PL & MINT1_6PL & MINT1_7PL & MINT1_8PL & \ + MINT1_9PL & MINT1_10PL & MINT1_11PL & MINT1_12PL & \ + MINT1_13PL & MINT1_14PL & MINT1_15PL & MINT1_16PL) +// End Of MINT1. + +// Beginning of MINT2: +#if (INT1PL >= INT2PL) || (INT1PL == 0) +#define MINT2_1PL ~(1 << 0) +#else +#define MINT2_1PL 0xFFFF +#endif + +#if (INT2PL == 0) +#define MINT2_2PL ~(1 << 1) +#else +#define MINT2_2PL 0xFFFF +#endif + +#if (INT3PL >= INT2PL) || (INT3PL == 0) +#define MINT2_3PL ~(1 << 2) +#else +#define MINT2_3PL 0xFFFF +#endif + +#if (INT4PL >= INT2PL) || (INT4PL == 0) +#define MINT2_4PL ~(1 << 3) +#else +#define MINT2_4PL 0xFFFF +#endif + +#if (INT5PL >= INT2PL) || (INT5PL == 0) +#define MINT2_5PL ~(1 << 4) +#else +#define MINT2_5PL 0xFFFF +#endif + +#if (INT6PL >= INT2PL) || (INT6PL == 0) +#define MINT2_6PL ~(1 << 5) +#else +#define MINT2_6PL 0xFFFF +#endif + +#if (INT7PL >= INT2PL) || (INT7PL == 0) +#define MINT2_7PL ~(1 << 6) +#else +#define MINT2_7PL 0xFFFF +#endif + +#if (INT8PL >= INT2PL) || (INT8PL == 0) +#define MINT2_8PL ~(1 << 7) +#else +#define MINT2_8PL 0xFFFF +#endif + +#if (INT9PL >= INT2PL) || (INT9PL == 0) +#define MINT2_9PL ~(1 << 8) +#else +#define MINT2_9PL 0xFFFF +#endif + +#if (INT10PL >= INT2PL) || (INT10PL == 0) +#define MINT2_10PL ~(1 << 9) +#else +#define MINT2_10PL 0xFFFF +#endif + +#if (INT11PL >= INT2PL) || (INT11PL == 0) +#define MINT2_11PL ~(1 << 10) +#else +#define MINT2_11PL 0xFFFF +#endif + +#if (INT12PL >= INT2PL) || (INT12PL == 0) +#define MINT2_12PL ~(1 << 11) +#else +#define MINT2_12PL 0xFFFF +#endif + +#if (INT13PL >= INT2PL) || (INT13PL == 0) +#define MINT2_13PL ~(1 << 12) +#else +#define MINT2_13PL 0xFFFF +#endif + +#if (INT14PL >= INT2PL) || (INT14PL == 0) +#define MINT2_14PL ~(1 << 13) +#else +#define MINT2_14PL 0xFFFF +#endif + +#if (INT15PL >= INT2PL) || (INT15PL == 0) +#define MINT2_15PL ~(1 << 14) +#else +#define MINT2_15PL 0xFFFF +#endif + +#if (INT16PL >= INT2PL) || (INT16PL == 0) +#define MINT2_16PL ~(1 << 15) +#else +#define MINT2_16PL 0xFFFF +#endif + +#define MINT2 (MINT2_1PL & MINT2_2PL & MINT2_3PL & MINT2_4PL & \ + MINT2_5PL & MINT2_6PL & MINT2_7PL & MINT2_8PL & \ + MINT2_9PL & MINT2_10PL & MINT2_11PL & MINT2_12PL & \ + MINT2_13PL & MINT2_14PL & MINT2_15PL & MINT2_16PL) +// End Of MINT2. + +// Beginning of MINT3: +#if (INT1PL >= INT3PL) || (INT1PL == 0) +#define MINT3_1PL ~(1 << 0) +#else +#define MINT3_1PL 0xFFFF +#endif + +#if (INT2PL >= INT3PL) || (INT2PL == 0) +#define MINT3_2PL ~(1 << 1) +#else +#define MINT3_2PL 0xFFFF +#endif + +#if (INT3PL == 0) +#define MINT3_3PL ~(1 << 2) +#else +#define MINT3_3PL 0xFFFF +#endif + +#if (INT4PL >= INT3PL) || (INT4PL == 0) +#define MINT3_4PL ~(1 << 3) +#else +#define MINT3_4PL 0xFFFF +#endif + +#if (INT5PL >= INT3PL) || (INT5PL == 0) +#define MINT3_5PL ~(1 << 4) +#else +#define MINT3_5PL 0xFFFF +#endif + +#if (INT6PL >= INT3PL) || (INT6PL == 0) +#define MINT3_6PL ~(1 << 5) +#else +#define MINT3_6PL 0xFFFF +#endif + +#if (INT7PL >= INT3PL) || (INT7PL == 0) +#define MINT3_7PL ~(1 << 6) +#else +#define MINT3_7PL 0xFFFF +#endif + +#if (INT8PL >= INT3PL) || (INT8PL == 0) +#define MINT3_8PL ~(1 << 7) +#else +#define MINT3_8PL 0xFFFF +#endif + +#if (INT9PL >= INT3PL) || (INT9PL == 0) +#define MINT3_9PL ~(1 << 8) +#else +#define MINT3_9PL 0xFFFF +#endif + +#if (INT10PL >= INT3PL) || (INT10PL == 0) +#define MINT3_10PL ~(1 << 9) +#else +#define MINT3_10PL 0xFFFF +#endif + +#if (INT11PL >= INT3PL) || (INT11PL == 0) +#define MINT3_11PL ~(1 << 10) +#else +#define MINT3_11PL 0xFFFF +#endif + +#if (INT12PL >= INT3PL) || (INT12PL == 0) +#define MINT3_12PL ~(1 << 11) +#else +#define MINT3_12PL 0xFFFF +#endif + +#if (INT13PL >= INT3PL) || (INT13PL == 0) +#define MINT3_13PL ~(1 << 12) +#else +#define MINT3_13PL 0xFFFF +#endif + +#if (INT14PL >= INT3PL) || (INT14PL == 0) +#define MINT3_14PL ~(1 << 13) +#else +#define MINT3_14PL 0xFFFF +#endif + +#if (INT15PL >= INT3PL) || (INT15PL == 0) +#define MINT3_15PL ~(1 << 14) +#else +#define MINT3_15PL 0xFFFF +#endif + +#if (INT16PL >= INT3PL) || (INT16PL == 0) +#define MINT3_16PL ~(1 << 15) +#else +#define MINT3_16PL 0xFFFF +#endif + +#define MINT3 (MINT3_1PL & MINT3_2PL & MINT3_3PL & MINT3_4PL & \ + MINT3_5PL & MINT3_6PL & MINT3_7PL & MINT3_8PL & \ + MINT3_9PL & MINT3_10PL & MINT3_11PL & MINT3_12PL & \ + MINT3_13PL & MINT3_14PL & MINT3_15PL & MINT3_16PL) +// End Of MINT3. + +// Beginning of MINT4: +#if (INT1PL >= INT4PL) || (INT1PL == 0) +#define MINT4_1PL ~(1 << 0) +#else +#define MINT4_1PL 0xFFFF +#endif + +#if (INT2PL >= INT4PL) || (INT2PL == 0) +#define MINT4_2PL ~(1 << 1) +#else +#define MINT4_2PL 0xFFFF +#endif + +#if (INT3PL >= INT4PL) || (INT3PL == 0) +#define MINT4_3PL ~(1 << 2) +#else +#define MINT4_3PL 0xFFFF +#endif + +#if (INT4PL == 0) +#define MINT4_4PL ~(1 << 3) +#else +#define MINT4_4PL 0xFFFF +#endif + +#if (INT5PL >= INT4PL) || (INT5PL == 0) +#define MINT4_5PL ~(1 << 4) +#else +#define MINT4_5PL 0xFFFF +#endif + +#if (INT6PL >= INT4PL) || (INT6PL == 0) +#define MINT4_6PL ~(1 << 5) +#else +#define MINT4_6PL 0xFFFF +#endif + +#if (INT7PL >= INT4PL) || (INT7PL == 0) +#define MINT4_7PL ~(1 << 6) +#else +#define MINT4_7PL 0xFFFF +#endif + +#if (INT8PL >= INT4PL) || (INT8PL == 0) +#define MINT4_8PL ~(1 << 7) +#else +#define MINT4_8PL 0xFFFF +#endif + +#if (INT9PL >= INT4PL) || (INT9PL == 0) +#define MINT4_9PL ~(1 << 8) +#else +#define MINT4_9PL 0xFFFF +#endif + +#if (INT10PL >= INT4PL) || (INT10PL == 0) +#define MINT4_10PL ~(1 << 9) +#else +#define MINT4_10PL 0xFFFF +#endif + +#if (INT11PL >= INT4PL) || (INT11PL == 0) +#define MINT4_11PL ~(1 << 10) +#else +#define MINT4_11PL 0xFFFF +#endif + +#if (INT12PL >= INT4PL) || (INT12PL == 0) +#define MINT4_12PL ~(1 << 11) +#else +#define MINT4_12PL 0xFFFF +#endif + +#if (INT13PL >= INT4PL) || (INT13PL == 0) +#define MINT4_13PL ~(1 << 12) +#else +#define MINT4_13PL 0xFFFF +#endif + +#if (INT14PL >= INT4PL) || (INT14PL == 0) +#define MINT4_14PL ~(1 << 13) +#else +#define MINT4_14PL 0xFFFF +#endif + +#if (INT15PL >= INT4PL) || (INT15PL == 0) +#define MINT4_15PL ~(1 << 14) +#else +#define MINT4_15PL 0xFFFF +#endif + +#if (INT16PL >= INT4PL) || (INT16PL == 0) +#define MINT4_16PL ~(1 << 15) +#else +#define MINT4_16PL 0xFFFF +#endif + +#define MINT4 (MINT4_1PL & MINT4_2PL & MINT4_3PL & MINT4_4PL & \ + MINT4_5PL & MINT4_6PL & MINT4_7PL & MINT4_8PL & \ + MINT4_9PL & MINT4_10PL & MINT4_11PL & MINT4_12PL & \ + MINT4_13PL & MINT4_14PL & MINT4_15PL & MINT4_16PL) +// End Of MINT4. + +// Beginning of MINT5: +#if (INT1PL >= INT5PL) || (INT1PL == 0) +#define MINT5_1PL ~(1 << 0) +#else +#define MINT5_1PL 0xFFFF +#endif + +#if (INT2PL >= INT5PL) || (INT2PL == 0) +#define MINT5_2PL ~(1 << 1) +#else +#define MINT5_2PL 0xFFFF +#endif + +#if (INT3PL >= INT5PL) || (INT3PL == 0) +#define MINT5_3PL ~(1 << 2) +#else +#define MINT5_3PL 0xFFFF +#endif + +#if (INT4PL >= INT5PL) || (INT4PL == 0) +#define MINT5_4PL ~(1 << 3) +#else +#define MINT5_4PL 0xFFFF +#endif + +#if (INT5PL == 0) +#define MINT5_5PL ~(1 << 4) +#else +#define MINT5_5PL 0xFFFF +#endif + +#if (INT6PL >= INT5PL) || (INT6PL == 0) +#define MINT5_6PL ~(1 << 5) +#else +#define MINT5_6PL 0xFFFF +#endif + +#if (INT7PL >= INT5PL) || (INT7PL == 0) +#define MINT5_7PL ~(1 << 6) +#else +#define MINT5_7PL 0xFFFF +#endif + +#if (INT8PL >= INT5PL) || (INT8PL == 0) +#define MINT5_8PL ~(1 << 7) +#else +#define MINT5_8PL 0xFFFF +#endif + +#if (INT9PL >= INT5PL) || (INT9PL == 0) +#define MINT5_9PL ~(1 << 8) +#else +#define MINT5_9PL 0xFFFF +#endif + +#if (INT10PL >= INT5PL) || (INT10PL == 0) +#define MINT5_10PL ~(1 << 9) +#else +#define MINT5_10PL 0xFFFF +#endif + +#if (INT11PL >= INT5PL) || (INT11PL == 0) +#define MINT5_11PL ~(1 << 10) +#else +#define MINT5_11PL 0xFFFF +#endif + +#if (INT12PL >= INT5PL) || (INT12PL == 0) +#define MINT5_12PL ~(1 << 11) +#else +#define MINT5_12PL 0xFFFF +#endif + +#if (INT13PL >= INT5PL) || (INT13PL == 0) +#define MINT5_13PL ~(1 << 12) +#else +#define MINT5_13PL 0xFFFF +#endif + +#if (INT14PL >= INT5PL) || (INT14PL == 0) +#define MINT5_14PL ~(1 << 13) +#else +#define MINT5_14PL 0xFFFF +#endif + +#if (INT15PL >= INT5PL) || (INT15PL == 0) +#define MINT5_15PL ~(1 << 14) +#else +#define MINT5_15PL 0xFFFF +#endif + +#if (INT16PL >= INT5PL) || (INT16PL == 0) +#define MINT5_16PL ~(1 << 15) +#else +#define MINT5_16PL 0xFFFF +#endif + +#define MINT5 (MINT5_1PL & MINT5_2PL & MINT5_3PL & MINT5_4PL & \ + MINT5_5PL & MINT5_6PL & MINT5_7PL & MINT5_8PL & \ + MINT5_9PL & MINT5_10PL & MINT5_11PL & MINT5_12PL & \ + MINT5_13PL & MINT5_14PL & MINT5_15PL & MINT5_16PL) +// End Of MINT5. + +// Beginning of MINT6: +#if (INT1PL >= INT6PL) || (INT1PL == 0) +#define MINT6_1PL ~(1 << 0) +#else +#define MINT6_1PL 0xFFFF +#endif + +#if (INT2PL >= INT6PL) || (INT2PL == 0) +#define MINT6_2PL ~(1 << 1) +#else +#define MINT6_2PL 0xFFFF +#endif + +#if (INT3PL >= INT6PL) || (INT3PL == 0) +#define MINT6_3PL ~(1 << 2) +#else +#define MINT6_3PL 0xFFFF +#endif + +#if (INT4PL >= INT6PL) || (INT4PL == 0) +#define MINT6_4PL ~(1 << 3) +#else +#define MINT6_4PL 0xFFFF +#endif + +#if (INT5PL >= INT6PL) || (INT5PL == 0) +#define MINT6_5PL ~(1 << 4) +#else +#define MINT6_5PL 0xFFFF +#endif + +#if (INT6PL == 0) +#define MINT6_6PL ~(1 << 5) +#else +#define MINT6_6PL 0xFFFF +#endif + +#if (INT7PL >= INT6PL) || (INT7PL == 0) +#define MINT6_7PL ~(1 << 6) +#else +#define MINT6_7PL 0xFFFF +#endif + +#if (INT8PL >= INT6PL) || (INT8PL == 0) +#define MINT6_8PL ~(1 << 7) +#else +#define MINT6_8PL 0xFFFF +#endif + +#if (INT9PL >= INT6PL) || (INT9PL == 0) +#define MINT6_9PL ~(1 << 8) +#else +#define MINT6_9PL 0xFFFF +#endif + +#if (INT10PL >= INT6PL) || (INT10PL == 0) +#define MINT6_10PL ~(1 << 9) +#else +#define MINT6_10PL 0xFFFF +#endif + +#if (INT11PL >= INT6PL) || (INT11PL == 0) +#define MINT6_11PL ~(1 << 10) +#else +#define MINT6_11PL 0xFFFF +#endif + +#if (INT12PL >= INT6PL) || (INT12PL == 0) +#define MINT6_12PL ~(1 << 11) +#else +#define MINT6_12PL 0xFFFF +#endif + +#if (INT13PL >= INT6PL) || (INT13PL == 0) +#define MINT6_13PL ~(1 << 12) +#else +#define MINT6_13PL 0xFFFF +#endif + +#if (INT14PL >= INT6PL) || (INT14PL == 0) +#define MINT6_14PL ~(1 << 13) +#else +#define MINT6_14PL 0xFFFF +#endif + +#if (INT15PL >= INT6PL) || (INT15PL == 0) +#define MINT6_15PL ~(1 << 14) +#else +#define MINT6_15PL 0xFFFF +#endif + +#if (INT16PL >= INT6PL) || (INT16PL == 0) +#define MINT6_16PL ~(1 << 15) +#else +#define MINT6_16PL 0xFFFF +#endif + +#define MINT6 (MINT6_1PL & MINT6_2PL & MINT6_3PL & MINT6_4PL & \ + MINT6_5PL & MINT6_6PL & MINT6_7PL & MINT6_8PL & \ + MINT6_9PL & MINT6_10PL & MINT6_11PL & MINT6_12PL & \ + MINT6_13PL & MINT6_14PL & MINT6_15PL & MINT6_16PL) +// End Of MINT6. + +// Beginning of MINT7: +#if (INT1PL >= INT7PL) || (INT1PL == 0) +#define MINT7_1PL ~(1 << 0) +#else +#define MINT7_1PL 0xFFFF +#endif + +#if (INT2PL >= INT7PL) || (INT2PL == 0) +#define MINT7_2PL ~(1 << 1) +#else +#define MINT7_2PL 0xFFFF +#endif + +#if (INT3PL >= INT7PL) || (INT3PL == 0) +#define MINT7_3PL ~(1 << 2) +#else +#define MINT7_3PL 0xFFFF +#endif + +#if (INT4PL >= INT7PL) || (INT4PL == 0) +#define MINT7_4PL ~(1 << 3) +#else +#define MINT7_4PL 0xFFFF +#endif + +#if (INT5PL >= INT7PL) || (INT5PL == 0) +#define MINT7_5PL ~(1 << 4) +#else +#define MINT7_5PL 0xFFFF +#endif + +#if (INT6PL >= INT7PL) || (INT6PL == 0) +#define MINT7_6PL ~(1 << 5) +#else +#define MINT7_6PL 0xFFFF +#endif + +#if (INT7PL == 0) +#define MINT7_7PL ~(1 << 6) +#else +#define MINT7_7PL 0xFFFF +#endif + +#if (INT8PL >= INT7PL) || (INT8PL == 0) +#define MINT7_8PL ~(1 << 7) +#else +#define MINT7_8PL 0xFFFF +#endif + +#if (INT9PL >= INT7PL) || (INT9PL == 0) +#define MINT7_9PL ~(1 << 8) +#else +#define MINT7_9PL 0xFFFF +#endif + +#if (INT10PL >= INT7PL) || (INT10PL == 0) +#define MINT7_10PL ~(1 << 9) +#else +#define MINT7_10PL 0xFFFF +#endif + +#if (INT11PL >= INT7PL) || (INT11PL == 0) +#define MINT7_11PL ~(1 << 10) +#else +#define MINT7_11PL 0xFFFF +#endif + +#if (INT12PL >= INT7PL) || (INT12PL == 0) +#define MINT7_12PL ~(1 << 11) +#else +#define MINT7_12PL 0xFFFF +#endif + +#if (INT13PL >= INT7PL) || (INT13PL == 0) +#define MINT7_13PL ~(1 << 12) +#else +#define MINT7_13PL 0xFFFF +#endif + +#if (INT14PL >= INT7PL) || (INT14PL == 0) +#define MINT7_14PL ~(1 << 13) +#else +#define MINT7_14PL 0xFFFF +#endif + +#if (INT15PL >= INT7PL) || (INT15PL == 0) +#define MINT7_15PL ~(1 << 14) +#else +#define MINT7_15PL 0xFFFF +#endif + +#if (INT16PL >= INT7PL) || (INT16PL == 0) +#define MINT7_16PL ~(1 << 15) +#else +#define MINT7_16PL 0xFFFF +#endif + +#define MINT7 (MINT7_1PL & MINT7_2PL & MINT7_3PL & MINT7_4PL & \ + MINT7_5PL & MINT7_6PL & MINT7_7PL & MINT7_8PL & \ + MINT7_9PL & MINT7_10PL & MINT7_11PL & MINT7_12PL & \ + MINT7_13PL & MINT7_14PL & MINT7_15PL & MINT7_16PL) +// End Of MINT7. + +// Beginning of MINT8: +#if (INT1PL >= INT8PL) || (INT1PL == 0) +#define MINT8_1PL ~(1 << 0) +#else +#define MINT8_1PL 0xFFFF +#endif + +#if (INT2PL >= INT8PL) || (INT2PL == 0) +#define MINT8_2PL ~(1 << 1) +#else +#define MINT8_2PL 0xFFFF +#endif + +#if (INT3PL >= INT8PL) || (INT3PL == 0) +#define MINT8_3PL ~(1 << 2) +#else +#define MINT8_3PL 0xFFFF +#endif + +#if (INT4PL >= INT8PL) || (INT4PL == 0) +#define MINT8_4PL ~(1 << 3) +#else +#define MINT8_4PL 0xFFFF +#endif + +#if (INT5PL >= INT8PL) || (INT5PL == 0) +#define MINT8_5PL ~(1 << 4) +#else +#define MINT8_5PL 0xFFFF +#endif + +#if (INT6PL >= INT8PL) || (INT6PL == 0) +#define MINT8_6PL ~(1 << 5) +#else +#define MINT8_6PL 0xFFFF +#endif + +#if (INT7PL >= INT8PL) || (INT7PL == 0) +#define MINT8_7PL ~(1 << 6) +#else +#define MINT8_7PL 0xFFFF +#endif + +#if (INT8PL == 0) +#define MINT8_8PL ~(1 << 7) +#else +#define MINT8_8PL 0xFFFF +#endif + +#if (INT9PL >= INT8PL) || (INT9PL == 0) +#define MINT8_9PL ~(1 << 8) +#else +#define MINT8_9PL 0xFFFF +#endif + +#if (INT10PL >= INT8PL) || (INT10PL == 0) +#define MINT8_10PL ~(1 << 9) +#else +#define MINT8_10PL 0xFFFF +#endif + +#if (INT11PL >= INT8PL) || (INT11PL == 0) +#define MINT8_11PL ~(1 << 10) +#else +#define MINT8_11PL 0xFFFF +#endif + +#if (INT12PL >= INT8PL) || (INT12PL == 0) +#define MINT8_12PL ~(1 << 11) +#else +#define MINT8_12PL 0xFFFF +#endif + +#if (INT13PL >= INT8PL) || (INT13PL == 0) +#define MINT8_13PL ~(1 << 12) +#else +#define MINT8_13PL 0xFFFF +#endif + +#if (INT14PL >= INT8PL) || (INT14PL == 0) +#define MINT8_14PL ~(1 << 13) +#else +#define MINT8_14PL 0xFFFF +#endif + +#if (INT15PL >= INT8PL) || (INT15PL == 0) +#define MINT8_15PL ~(1 << 14) +#else +#define MINT8_15PL 0xFFFF +#endif + +#if (INT16PL >= INT8PL) || (INT16PL == 0) +#define MINT8_16PL ~(1 << 15) +#else +#define MINT8_16PL 0xFFFF +#endif + +#define MINT8 (MINT8_1PL & MINT8_2PL & MINT8_3PL & MINT8_4PL & \ + MINT8_5PL & MINT8_6PL & MINT8_7PL & MINT8_8PL & \ + MINT8_9PL & MINT8_10PL & MINT8_11PL & MINT8_12PL & \ + MINT8_13PL & MINT8_14PL & MINT8_15PL & MINT8_16PL) +// End Of MINT8. + +// Beginning of MINT9: +#if (INT1PL >= INT9PL) || (INT1PL == 0) +#define MINT9_1PL ~(1 << 0) +#else +#define MINT9_1PL 0xFFFF +#endif + +#if (INT2PL >= INT9PL) || (INT2PL == 0) +#define MINT9_2PL ~(1 << 1) +#else +#define MINT9_2PL 0xFFFF +#endif + +#if (INT3PL >= INT9PL) || (INT3PL == 0) +#define MINT9_3PL ~(1 << 2) +#else +#define MINT9_3PL 0xFFFF +#endif + +#if (INT4PL >= INT9PL) || (INT4PL == 0) +#define MINT9_4PL ~(1 << 3) +#else +#define MINT9_4PL 0xFFFF +#endif + +#if (INT5PL >= INT9PL) || (INT5PL == 0) +#define MINT9_5PL ~(1 << 4) +#else +#define MINT9_5PL 0xFFFF +#endif + +#if (INT6PL >= INT9PL) || (INT6PL == 0) +#define MINT9_6PL ~(1 << 5) +#else +#define MINT9_6PL 0xFFFF +#endif + +#if (INT7PL >= INT9PL) || (INT7PL == 0) +#define MINT9_7PL ~(1 << 6) +#else +#define MINT9_7PL 0xFFFF +#endif + +#if (INT8PL >= INT9PL) || (INT8PL == 0) +#define MINT9_8PL ~(1 << 7) +#else +#define MINT9_8PL 0xFFFF +#endif + +#if (INT9PL == 0) +#define MINT9_9PL ~(1 << 8) +#else +#define MINT9_9PL 0xFFFF +#endif + +#if (INT10PL >= INT9PL) || (INT10PL == 0) +#define MINT9_10PL ~(1 << 9) +#else +#define MINT9_10PL 0xFFFF +#endif + +#if (INT11PL >= INT9PL) || (INT11PL == 0) +#define MINT9_11PL ~(1 << 10) +#else +#define MINT9_11PL 0xFFFF +#endif + +#if (INT12PL >= INT9PL) || (INT12PL == 0) +#define MINT9_12PL ~(1 << 11) +#else +#define MINT9_12PL 0xFFFF +#endif + +#if (INT13PL >= INT9PL) || (INT13PL == 0) +#define MINT9_13PL ~(1 << 12) +#else +#define MINT9_13PL 0xFFFF +#endif + +#if (INT14PL >= INT9PL) || (INT14PL == 0) +#define MINT9_14PL ~(1 << 13) +#else +#define MINT9_14PL 0xFFFF +#endif + +#if (INT15PL >= INT9PL) || (INT15PL == 0) +#define MINT9_15PL ~(1 << 14) +#else +#define MINT9_15PL 0xFFFF +#endif + +#if (INT16PL >= INT9PL) || (INT16PL == 0) +#define MINT9_16PL ~(1 << 15) +#else +#define MINT9_16PL 0xFFFF +#endif + +#define MINT9 (MINT9_1PL & MINT9_2PL & MINT9_3PL & MINT9_4PL & \ + MINT9_5PL & MINT9_6PL & MINT9_7PL & MINT9_8PL & \ + MINT9_9PL & MINT9_10PL & MINT9_11PL & MINT9_12PL & \ + MINT9_13PL & MINT9_14PL & MINT9_15PL & MINT9_16PL) +// End Of MINT9. + +// Beginning of MINT10: +#if (INT1PL >= INT10PL) || (INT1PL == 0) +#define MINT10_1PL ~(1 << 0) +#else +#define MINT10_1PL 0xFFFF +#endif + +#if (INT2PL >= INT10PL) || (INT2PL == 0) +#define MINT10_2PL ~(1 << 1) +#else +#define MINT10_2PL 0xFFFF +#endif + +#if (INT3PL >= INT10PL) || (INT3PL == 0) +#define MINT10_3PL ~(1 << 2) +#else +#define MINT10_3PL 0xFFFF +#endif + +#if (INT4PL >= INT10PL) || (INT4PL == 0) +#define MINT10_4PL ~(1 << 3) +#else +#define MINT10_4PL 0xFFFF +#endif + +#if (INT5PL >= INT10PL) || (INT5PL == 0) +#define MINT10_5PL ~(1 << 4) +#else +#define MINT10_5PL 0xFFFF +#endif + +#if (INT6PL >= INT10PL) || (INT6PL == 0) +#define MINT10_6PL ~(1 << 5) +#else +#define MINT10_6PL 0xFFFF +#endif + +#if (INT7PL >= INT10PL) || (INT7PL == 0) +#define MINT10_7PL ~(1 << 6) +#else +#define MINT10_7PL 0xFFFF +#endif + +#if (INT8PL >= INT10PL) || (INT8PL == 0) +#define MINT10_8PL ~(1 << 7) +#else +#define MINT10_8PL 0xFFFF +#endif + +#if (INT9PL >= INT10PL) || (INT9PL == 0) +#define MINT10_9PL ~(1 << 8) +#else +#define MINT10_9PL 0xFFFF +#endif + +#if (INT10PL == 0) +#define MINT10_10PL ~(1 << 9) +#else +#define MINT10_10PL 0xFFFF +#endif + +#if (INT11PL >= INT10PL) || (INT11PL == 0) +#define MINT10_11PL ~(1 << 10) +#else +#define MINT10_11PL 0xFFFF +#endif + +#if (INT12PL >= INT10PL) || (INT12PL == 0) +#define MINT10_12PL ~(1 << 11) +#else +#define MINT10_12PL 0xFFFF +#endif + +#if (INT13PL >= INT10PL) || (INT13PL == 0) +#define MINT10_13PL ~(1 << 12) +#else +#define MINT10_13PL 0xFFFF +#endif + +#if (INT14PL >= INT10PL) || (INT14PL == 0) +#define MINT10_14PL ~(1 << 13) +#else +#define MINT10_14PL 0xFFFF +#endif + +#if (INT15PL >= INT10PL) || (INT15PL == 0) +#define MINT10_15PL ~(1 << 14) +#else +#define MINT10_15PL 0xFFFF +#endif + +#if (INT16PL >= INT10PL) || (INT16PL == 0) +#define MINT10_16PL ~(1 << 15) +#else +#define MINT10_16PL 0xFFFF +#endif + +#define MINT10 (MINT10_1PL & MINT10_2PL & MINT10_3PL & MINT10_4PL & \ + MINT10_5PL & MINT10_6PL & MINT10_7PL & MINT10_8PL & \ + MINT10_9PL & MINT10_10PL & MINT10_11PL & MINT10_12PL & \ + MINT10_13PL & MINT10_14PL & MINT10_15PL & MINT10_16PL) +// End Of MINT10. + +// Beginning of MINT11: +#if (INT1PL >= INT11PL) || (INT1PL == 0) +#define MINT11_1PL ~(1 << 0) +#else +#define MINT11_1PL 0xFFFF +#endif + +#if (INT2PL >= INT11PL) || (INT2PL == 0) +#define MINT11_2PL ~(1 << 1) +#else +#define MINT11_2PL 0xFFFF +#endif + +#if (INT3PL >= INT11PL) || (INT3PL == 0) +#define MINT11_3PL ~(1 << 2) +#else +#define MINT11_3PL 0xFFFF +#endif + +#if (INT4PL >= INT11PL) || (INT4PL == 0) +#define MINT11_4PL ~(1 << 3) +#else +#define MINT11_4PL 0xFFFF +#endif + +#if (INT5PL >= INT11PL) || (INT5PL == 0) +#define MINT11_5PL ~(1 << 4) +#else +#define MINT11_5PL 0xFFFF +#endif + +#if (INT6PL >= INT11PL) || (INT6PL == 0) +#define MINT11_6PL ~(1 << 5) +#else +#define MINT11_6PL 0xFFFF +#endif + +#if (INT7PL >= INT11PL) || (INT7PL == 0) +#define MINT11_7PL ~(1 << 6) +#else +#define MINT11_7PL 0xFFFF +#endif + +#if (INT8PL >= INT11PL) || (INT8PL == 0) +#define MINT11_8PL ~(1 << 7) +#else +#define MINT11_8PL 0xFFFF +#endif + +#if (INT9PL >= INT11PL) || (INT9PL == 0) +#define MINT11_9PL ~(1 << 8) +#else +#define MINT11_9PL 0xFFFF +#endif + +#if (INT10PL >= INT11PL) || (INT10PL == 0) +#define MINT11_10PL ~(1 << 9) +#else +#define MINT11_10PL 0xFFFF +#endif + +#if (INT11PL == 0) +#define MINT11_11PL ~(1 << 10) +#else +#define MINT11_11PL 0xFFFF +#endif + +#if (INT12PL >= INT11PL) || (INT12PL == 0) +#define MINT11_12PL ~(1 << 11) +#else +#define MINT11_12PL 0xFFFF +#endif + +#if (INT13PL >= INT11PL) || (INT13PL == 0) +#define MINT11_13PL ~(1 << 12) +#else +#define MINT11_13PL 0xFFFF +#endif + +#if (INT14PL >= INT11PL) || (INT14PL == 0) +#define MINT11_14PL ~(1 << 13) +#else +#define MINT11_14PL 0xFFFF +#endif + +#if (INT15PL >= INT11PL) || (INT15PL == 0) +#define MINT11_15PL ~(1 << 14) +#else +#define MINT11_15PL 0xFFFF +#endif + +#if (INT16PL >= INT11PL) || (INT16PL == 0) +#define MINT11_16PL ~(1 << 15) +#else +#define MINT11_16PL 0xFFFF +#endif + +#define MINT11 (MINT11_1PL & MINT11_2PL & MINT11_3PL & MINT11_4PL & \ + MINT11_5PL & MINT11_6PL & MINT11_7PL & MINT11_8PL & \ + MINT11_9PL & MINT11_10PL & MINT11_11PL & MINT11_12PL & \ + MINT11_13PL & MINT11_14PL & MINT11_15PL & MINT11_16PL) +// End Of MINT11. + +// Beginning of MINT12: +#if (INT1PL >= INT12PL) || (INT1PL == 0) +#define MINT12_1PL ~(1 << 0) +#else +#define MINT12_1PL 0xFFFF +#endif + +#if (INT2PL >= INT12PL) || (INT2PL == 0) +#define MINT12_2PL ~(1 << 1) +#else +#define MINT12_2PL 0xFFFF +#endif + +#if (INT3PL >= INT12PL) || (INT3PL == 0) +#define MINT12_3PL ~(1 << 2) +#else +#define MINT12_3PL 0xFFFF +#endif + +#if (INT4PL >= INT12PL) || (INT4PL == 0) +#define MINT12_4PL ~(1 << 3) +#else +#define MINT12_4PL 0xFFFF +#endif + +#if (INT5PL >= INT12PL) || (INT5PL == 0) +#define MINT12_5PL ~(1 << 4) +#else +#define MINT12_5PL 0xFFFF +#endif + +#if (INT6PL >= INT12PL) || (INT6PL == 0) +#define MINT12_6PL ~(1 << 5) +#else +#define MINT12_6PL 0xFFFF +#endif + +#if (INT7PL >= INT12PL) || (INT7PL == 0) +#define MINT12_7PL ~(1 << 6) +#else +#define MINT12_7PL 0xFFFF +#endif + +#if (INT8PL >= INT12PL) || (INT8PL == 0) +#define MINT12_8PL ~(1 << 7) +#else +#define MINT12_8PL 0xFFFF +#endif + +#if (INT9PL >= INT12PL) || (INT9PL == 0) +#define MINT12_9PL ~(1 << 8) +#else +#define MINT12_9PL 0xFFFF +#endif + +#if (INT10PL >= INT12PL) || (INT10PL == 0) +#define MINT12_10PL ~(1 << 9) +#else +#define MINT12_10PL 0xFFFF +#endif + +#if (INT11PL >= INT12PL) || (INT11PL == 0) +#define MINT12_11PL ~(1 << 10) +#else +#define MINT12_11PL 0xFFFF +#endif + +#if (INT12PL == 0) +#define MINT12_12PL ~(1 << 11) +#else +#define MINT12_12PL 0xFFFF +#endif + +#if (INT13PL >= INT12PL) || (INT13PL == 0) +#define MINT12_13PL ~(1 << 12) +#else +#define MINT12_13PL 0xFFFF +#endif + +#if (INT14PL >= INT12PL) || (INT14PL == 0) +#define MINT12_14PL ~(1 << 13) +#else +#define MINT12_14PL 0xFFFF +#endif + +#if (INT15PL >= INT12PL) || (INT15PL == 0) +#define MINT12_15PL ~(1 << 14) +#else +#define MINT12_15PL 0xFFFF +#endif + +#if (INT16PL >= INT12PL) || (INT16PL == 0) +#define MINT12_16PL ~(1 << 15) +#else +#define MINT12_16PL 0xFFFF +#endif + +#define MINT12 (MINT12_1PL & MINT12_2PL & MINT12_3PL & MINT12_4PL & \ + MINT12_5PL & MINT12_6PL & MINT12_7PL & MINT12_8PL & \ + MINT12_9PL & MINT12_10PL & MINT12_11PL & MINT12_12PL & \ + MINT12_13PL & MINT12_14PL & MINT12_15PL & MINT12_16PL) +// End Of MINT12. + +// Beginning of MINT13: +#if (INT1PL >= INT13PL) || (INT1PL == 0) +#define MINT13_1PL ~(1 << 0) +#else +#define MINT13_1PL 0xFFFF +#endif + +#if (INT2PL >= INT13PL) || (INT2PL == 0) +#define MINT13_2PL ~(1 << 1) +#else +#define MINT13_2PL 0xFFFF +#endif + +#if (INT3PL >= INT13PL) || (INT3PL == 0) +#define MINT13_3PL ~(1 << 2) +#else +#define MINT13_3PL 0xFFFF +#endif + +#if (INT4PL >= INT13PL) || (INT4PL == 0) +#define MINT13_4PL ~(1 << 3) +#else +#define MINT13_4PL 0xFFFF +#endif + +#if (INT5PL >= INT13PL) || (INT5PL == 0) +#define MINT13_5PL ~(1 << 4) +#else +#define MINT13_5PL 0xFFFF +#endif + +#if (INT6PL >= INT13PL) || (INT6PL == 0) +#define MINT13_6PL ~(1 << 5) +#else +#define MINT13_6PL 0xFFFF +#endif + +#if (INT7PL >= INT13PL) || (INT7PL == 0) +#define MINT13_7PL ~(1 << 6) +#else +#define MINT13_7PL 0xFFFF +#endif + +#if (INT8PL >= INT13PL) || (INT8PL == 0) +#define MINT13_8PL ~(1 << 7) +#else +#define MINT13_8PL 0xFFFF +#endif + +#if (INT9PL >= INT13PL) || (INT9PL == 0) +#define MINT13_9PL ~(1 << 8) +#else +#define MINT13_9PL 0xFFFF +#endif + +#if (INT10PL >= INT13PL) || (INT10PL == 0) +#define MINT13_10PL ~(1 << 9) +#else +#define MINT13_10PL 0xFFFF +#endif + +#if (INT11PL >= INT13PL) || (INT11PL == 0) +#define MINT13_11PL ~(1 << 10) +#else +#define MINT13_11PL 0xFFFF +#endif + +#if (INT12PL >= INT13PL) || (INT12PL == 0) +#define MINT13_12PL ~(1 << 11) +#else +#define MINT13_12PL 0xFFFF +#endif + +#if (INT13PL == 0) +#define MINT13_13PL ~(1 << 12) +#else +#define MINT13_13PL 0xFFFF +#endif + +#if (INT14PL >= INT13PL) || (INT14PL == 0) +#define MINT13_14PL ~(1 << 13) +#else +#define MINT13_14PL 0xFFFF +#endif + +#if (INT15PL >= INT13PL) || (INT15PL == 0) +#define MINT13_15PL ~(1 << 14) +#else +#define MINT13_15PL 0xFFFF +#endif + +#if (INT16PL >= INT13PL) || (INT16PL == 0) +#define MINT13_16PL ~(1 << 15) +#else +#define MINT13_16PL 0xFFFF +#endif + +#define MINT13 (MINT13_1PL & MINT13_2PL & MINT13_3PL & MINT13_4PL & \ + MINT13_5PL & MINT13_6PL & MINT13_7PL & MINT13_8PL & \ + MINT13_9PL & MINT13_10PL & MINT13_11PL & MINT13_12PL & \ + MINT13_13PL & MINT13_14PL & MINT13_15PL & MINT13_16PL) +// End Of MINT13. + +// Beginning of MINT14: +#if (INT1PL >= INT14PL) || (INT1PL == 0) +#define MINT14_1PL ~(1 << 0) +#else +#define MINT14_1PL 0xFFFF +#endif + +#if (INT2PL >= INT14PL) || (INT2PL == 0) +#define MINT14_2PL ~(1 << 1) +#else +#define MINT14_2PL 0xFFFF +#endif + +#if (INT3PL >= INT14PL) || (INT3PL == 0) +#define MINT14_3PL ~(1 << 2) +#else +#define MINT14_3PL 0xFFFF +#endif + +#if (INT4PL >= INT14PL) || (INT4PL == 0) +#define MINT14_4PL ~(1 << 3) +#else +#define MINT14_4PL 0xFFFF +#endif + +#if (INT5PL >= INT14PL) || (INT5PL == 0) +#define MINT14_5PL ~(1 << 4) +#else +#define MINT14_5PL 0xFFFF +#endif + +#if (INT6PL >= INT14PL) || (INT6PL == 0) +#define MINT14_6PL ~(1 << 5) +#else +#define MINT14_6PL 0xFFFF +#endif + +#if (INT7PL >= INT14PL) || (INT7PL == 0) +#define MINT14_7PL ~(1 << 6) +#else +#define MINT14_7PL 0xFFFF +#endif + +#if (INT8PL >= INT14PL) || (INT8PL == 0) +#define MINT14_8PL ~(1 << 7) +#else +#define MINT14_8PL 0xFFFF +#endif + +#if (INT9PL >= INT14PL) || (INT9PL == 0) +#define MINT14_9PL ~(1 << 8) +#else +#define MINT14_9PL 0xFFFF +#endif + +#if (INT10PL >= INT14PL) || (INT10PL == 0) +#define MINT14_10PL ~(1 << 9) +#else +#define MINT14_10PL 0xFFFF +#endif + +#if (INT11PL >= INT14PL) || (INT11PL == 0) +#define MINT14_11PL ~(1 << 10) +#else +#define MINT14_11PL 0xFFFF +#endif + +#if (INT12PL >= INT14PL) || (INT12PL == 0) +#define MINT14_12PL ~(1 << 11) +#else +#define MINT14_12PL 0xFFFF +#endif + +#if (INT13PL >= INT14PL) || (INT13PL == 0) +#define MINT14_13PL ~(1 << 12) +#else +#define MINT14_13PL 0xFFFF +#endif + +#define MINT14_14PL ~(1 << 13) + +#if (INT15PL >= INT14PL) || (INT15PL == 0) +#define MINT14_15PL ~(1 << 14) +#else +#define MINT14_15PL 0xFFFF +#endif + +#if (INT16PL >= INT14PL) || (INT16PL == 0) +#define MINT14_16PL ~(1 << 15) +#else +#define MINT14_16PL 0xFFFF +#endif + +#define MINT14 (MINT14_1PL & MINT14_2PL & MINT14_3PL & MINT14_4PL & \ + MINT14_5PL & MINT14_6PL & MINT14_7PL & MINT14_8PL & \ + MINT14_9PL & MINT14_10PL & MINT14_11PL & MINT14_12PL & \ + MINT14_13PL & MINT14_14PL & MINT14_15PL & MINT14_16PL) +// End Of MINT14. + +// Beginning of MINT15: +#if (INT1PL >= INT15PL) || (INT1PL == 0) +#define MINT15_1PL ~(1 << 0) +#else +#define MINT15_1PL 0xFFFF +#endif + +#if (INT2PL >= INT15PL) || (INT2PL == 0) +#define MINT15_2PL ~(1 << 1) +#else +#define MINT15_2PL 0xFFFF +#endif + +#if (INT3PL >= INT15PL) || (INT3PL == 0) +#define MINT15_3PL ~(1 << 2) +#else +#define MINT15_3PL 0xFFFF +#endif + +#if (INT4PL >= INT15PL) || (INT4PL == 0) +#define MINT15_4PL ~(1 << 3) +#else +#define MINT15_4PL 0xFFFF +#endif + +#if (INT5PL >= INT15PL) || (INT5PL == 0) +#define MINT15_5PL ~(1 << 4) +#else +#define MINT15_5PL 0xFFFF +#endif + +#if (INT6PL >= INT15PL) || (INT6PL == 0) +#define MINT15_6PL ~(1 << 5) +#else +#define MINT15_6PL 0xFFFF +#endif + +#if (INT7PL >= INT15PL) || (INT7PL == 0) +#define MINT15_7PL ~(1 << 6) +#else +#define MINT15_7PL 0xFFFF +#endif + +#if (INT8PL >= INT15PL) || (INT8PL == 0) +#define MINT15_8PL ~(1 << 7) +#else +#define MINT15_8PL 0xFFFF +#endif + +#if (INT9PL >= INT15PL) || (INT9PL == 0) +#define MINT15_9PL ~(1 << 8) +#else +#define MINT15_9PL 0xFFFF +#endif + +#if (INT10PL >= INT15PL) || (INT10PL == 0) +#define MINT15_10PL ~(1 << 9) +#else +#define MINT15_10PL 0xFFFF +#endif + +#if (INT11PL >= INT15PL) || (INT11PL == 0) +#define MINT15_11PL ~(1 << 10) +#else +#define MINT15_11PL 0xFFFF +#endif + +#if (INT12PL >= INT15PL) || (INT12PL == 0) +#define MINT15_12PL ~(1 << 11) +#else +#define MINT15_12PL 0xFFFF +#endif + +#if (INT13PL >= INT15PL) || (INT13PL == 0) +#define MINT15_13PL ~(1 << 12) +#else +#define MINT15_13PL 0xFFFF +#endif + +#if (INT14PL >= INT15PL) || (INT14PL == 0) +#define MINT15_14PL ~(1 << 13) +#else +#define MINT15_14PL 0xFFFF +#endif + +#define MINT15_15PL ~(1 << 14) + +#if (INT16PL >= INT15PL) || (INT16PL == 0) +#define MINT15_16PL ~(1 << 15) +#else +#define MINT15_16PL 0xFFFF +#endif + +#define MINT15 (MINT15_1PL & MINT15_2PL & MINT15_3PL & MINT15_4PL & \ + MINT15_5PL & MINT15_6PL & MINT15_7PL & MINT15_8PL & \ + MINT15_9PL & MINT15_10PL & MINT15_11PL & MINT15_12PL & \ + MINT15_13PL & MINT15_14PL & MINT15_15PL & MINT15_16PL) +// End Of MINT15. + +// Beginning of MINT16: +#if (INT1PL >= INT16PL) || (INT1PL == 0) +#define MINT16_1PL ~(1 << 0) +#else +#define MINT16_1PL 0xFFFF +#endif + +#if (INT2PL >= INT16PL) || (INT2PL == 0) +#define MINT16_2PL ~(1 << 1) +#else +#define MINT16_2PL 0xFFFF +#endif + +#if (INT3PL >= INT16PL) || (INT3PL == 0) +#define MINT16_3PL ~(1 << 2) +#else +#define MINT16_3PL 0xFFFF +#endif + +#if (INT4PL >= INT16PL) || (INT4PL == 0) +#define MINT16_4PL ~(1 << 3) +#else +#define MINT16_4PL 0xFFFF +#endif + +#if (INT5PL >= INT16PL) || (INT5PL == 0) +#define MINT16_5PL ~(1 << 4) +#else +#define MINT16_5PL 0xFFFF +#endif + +#if (INT6PL >= INT16PL) || (INT6PL == 0) +#define MINT16_6PL ~(1 << 5) +#else +#define MINT16_6PL 0xFFFF +#endif + +#if (INT7PL >= INT16PL) || (INT7PL == 0) +#define MINT16_7PL ~(1 << 6) +#else +#define MINT16_7PL 0xFFFF +#endif + +#if (INT8PL >= INT16PL) || (INT8PL == 0) +#define MINT16_8PL ~(1 << 7) +#else +#define MINT16_8PL 0xFFFF +#endif + +#if (INT9PL >= INT16PL) || (INT9PL == 0) +#define MINT16_9PL ~(1 << 8) +#else +#define MINT16_9PL 0xFFFF +#endif + +#if (INT10PL >= INT16PL) || (INT10PL == 0) +#define MINT16_10PL ~(1 << 9) +#else +#define MINT16_10PL 0xFFFF +#endif + +#if (INT11PL >= INT16PL) || (INT11PL == 0) +#define MINT16_11PL ~(1 << 10) +#else +#define MINT16_11PL 0xFFFF +#endif + +#if (INT12PL >= INT16PL) || (INT12PL == 0) +#define MINT16_12PL ~(1 << 11) +#else +#define MINT16_12PL 0xFFFF +#endif + +#if (INT13PL >= INT16PL) || (INT13PL == 0) +#define MINT16_13PL ~(1 << 12) +#else +#define MINT16_13PL 0xFFFF +#endif + +#if (INT14PL >= INT16PL) || (INT14PL == 0) +#define MINT16_14PL ~(1 << 13) +#else +#define MINT16_14PL 0xFFFF +#endif + +#if (INT15PL >= INT16PL) || (INT15PL == 0) +#define MINT16_15PL ~(1 << 14) +#else +#define MINT16_15PL 0xFFFF +#endif + +#define MINT16_16PL ~(1 << 15) + +#define MINT16 (MINT16_1PL & MINT16_2PL & MINT16_3PL & MINT16_4PL & \ + MINT16_5PL & MINT16_6PL & MINT16_7PL & MINT16_8PL & \ + MINT16_9PL & MINT16_10PL & MINT16_11PL & MINT16_12PL & \ + MINT16_13PL & MINT16_14PL & MINT16_15PL & MINT16_16PL) +// End Of MINT16. + +// +// Automatically generate PIEIER1 interrupt masks MG11 to MG116: +// + +// Beginning of MG11: +#if (G1_2PL >= G1_1PL) || (G1_2PL == 0) +#define MG1_1_12PL ~(1 << 1) +#else +#define MG1_1_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_1PL) || (G1_3PL == 0) +#define MG1_1_13PL ~(1 << 2) +#else +#define MG1_1_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_1PL) || (G1_4PL == 0) +#define MG1_1_14PL ~(1 << 3) +#else +#define MG1_1_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_1PL) || (G1_5PL == 0) +#define MG1_1_15PL ~(1 << 4) +#else +#define MG1_1_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_1PL) || (G1_6PL == 0) +#define MG1_1_16PL ~(1 << 5) +#else +#define MG1_1_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_1PL) || (G1_7PL == 0) +#define MG1_1_17PL ~(1 << 6) +#else +#define MG1_1_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_1PL) || (G1_8PL == 0) +#define MG1_1_18PL ~(1 << 7) +#else +#define MG1_1_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_1PL) || (G1_9PL == 0) +#define MG1_1_19PL ~(1 << 8) +#else +#define MG1_1_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_1PL) || (G1_10PL == 0) +#define MG1_1_110PL ~(1 << 9) +#else +#define MG1_1_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_1PL) || (G1_11PL == 0) +#define MG1_1_111PL ~(1 << 10) +#else +#define MG1_1_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_1PL) || (G1_12PL == 0) +#define MG1_1_112PL ~(1 << 11) +#else +#define MG1_1_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_1PL) || (G1_13PL == 0) +#define MG1_1_113PL ~(1 << 12) +#else +#define MG1_1_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_1PL) || (G1_14PL == 0) +#define MG1_1_114PL ~(1 << 13) +#else +#define MG1_1_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_1PL) || (G1_15PL == 0) +#define MG1_1_115PL ~(1 << 14) +#else +#define MG1_1_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_1PL) || (G1_16PL == 0) +#define MG1_1_116PL ~(1 << 15) +#else +#define MG1_1_116PL 0xFFFF +#endif + +#define MG1_1_11PL 0xFFFE +#define MG1_1 (MG1_1_11PL & MG1_1_12PL & MG1_1_13PL & MG1_1_14PL & \ + MG1_1_15PL & MG1_1_16PL & MG1_1_17PL & MG1_1_18PL & \ + MG1_1_19PL & MG1_1_110PL & MG1_1_111PL & MG1_1_112PL & \ + MG1_1_113PL & MG1_1_114PL & MG1_1_115PL & MG1_1_116PL) +// End of MG1_1: +// Beginning of MG12: +#if (G1_1PL >= G1_2PL) || (G1_1PL == 0) +#define MG1_2_11PL ~(1 << 0) +#else +#define MG1_2_11PL 0xFFFF +#endif + +#if (G1_3PL >= G1_2PL) || (G1_3PL == 0) +#define MG1_2_13PL ~(1 << 2) +#else +#define MG1_2_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_2PL) || (G1_4PL == 0) +#define MG1_2_14PL ~(1 << 3) +#else +#define MG1_2_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_2PL) || (G1_5PL == 0) +#define MG1_2_15PL ~(1 << 4) +#else +#define MG1_2_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_2PL) || (G1_6PL == 0) +#define MG1_2_16PL ~(1 << 5) +#else +#define MG1_2_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_2PL) || (G1_7PL == 0) +#define MG1_2_17PL ~(1 << 6) +#else +#define MG1_2_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_2PL) || (G1_8PL == 0) +#define MG1_2_18PL ~(1 << 7) +#else +#define MG1_2_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_2PL) || (G1_9PL == 0) +#define MG1_2_19PL ~(1 << 8) +#else +#define MG1_2_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_2PL) || (G1_10PL == 0) +#define MG1_2_110PL ~(1 << 9) +#else +#define MG1_2_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_2PL) || (G1_11PL == 0) +#define MG1_2_111PL ~(1 << 10) +#else +#define MG1_2_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_2PL) || (G1_12PL == 0) +#define MG1_2_112PL ~(1 << 11) +#else +#define MG1_2_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_2PL) || (G1_13PL == 0) +#define MG1_2_113PL ~(1 << 12) +#else +#define MG1_2_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_2PL) || (G1_14PL == 0) +#define MG1_2_114PL ~(1 << 13) +#else +#define MG1_2_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_2PL) || (G1_15PL == 0) +#define MG1_2_115PL ~(1 << 14) +#else +#define MG1_2_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_2PL) || (G1_16PL == 0) +#define MG1_2_116PL ~(1 << 15) +#else +#define MG1_2_116PL 0xFFFF +#endif + +#define MG1_2_12PL 0xFFFD +#define MG1_2 (MG1_2_11PL & MG1_2_12PL & MG1_2_13PL & MG1_2_14PL & \ + MG1_2_15PL & MG1_2_16PL & MG1_2_17PL & MG1_2_18PL & \ + MG1_2_19PL & MG1_2_110PL & MG1_2_111PL & MG1_2_112PL & \ + MG1_2_113PL & MG1_2_114PL & MG1_2_115PL & MG1_2_116PL) +// End of MG1_2: +// Beginning of MG13: +#if (G1_1PL >= G1_3PL) || (G1_1PL == 0) +#define MG1_3_11PL ~(1 << 0) +#else +#define MG1_3_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_3PL) || (G1_2PL == 0) +#define MG1_3_12PL ~(1 << 1) +#else +#define MG1_3_12PL 0xFFFF +#endif + +#if (G1_4PL >= G1_3PL) || (G1_4PL == 0) +#define MG1_3_14PL ~(1 << 3) +#else +#define MG1_3_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_3PL) || (G1_5PL == 0) +#define MG1_3_15PL ~(1 << 4) +#else +#define MG1_3_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_3PL) || (G1_6PL == 0) +#define MG1_3_16PL ~(1 << 5) +#else +#define MG1_3_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_3PL) || (G1_7PL == 0) +#define MG1_3_17PL ~(1 << 6) +#else +#define MG1_3_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_3PL) || (G1_8PL == 0) +#define MG1_3_18PL ~(1 << 7) +#else +#define MG1_3_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_3PL) || (G1_9PL == 0) +#define MG1_3_19PL ~(1 << 8) +#else +#define MG1_3_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_3PL) || (G1_10PL == 0) +#define MG1_3_110PL ~(1 << 9) +#else +#define MG1_3_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_3PL) || (G1_11PL == 0) +#define MG1_3_111PL ~(1 << 10) +#else +#define MG1_3_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_3PL) || (G1_12PL == 0) +#define MG1_3_112PL ~(1 << 11) +#else +#define MG1_3_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_3PL) || (G1_13PL == 0) +#define MG1_3_113PL ~(1 << 12) +#else +#define MG1_3_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_3PL) || (G1_14PL == 0) +#define MG1_3_114PL ~(1 << 13) +#else +#define MG1_3_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_3PL) || (G1_15PL == 0) +#define MG1_3_115PL ~(1 << 14) +#else +#define MG1_3_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_3PL) || (G1_16PL == 0) +#define MG1_3_116PL ~(1 << 15) +#else +#define MG1_3_116PL 0xFFFF +#endif + +#define MG1_3_13PL 0xFFFB +#define MG1_3 (MG1_3_11PL & MG1_3_12PL & MG1_3_13PL & MG1_3_14PL & \ + MG1_3_15PL & MG1_3_16PL & MG1_3_17PL & MG1_3_18PL & \ + MG1_3_19PL & MG1_3_110PL & MG1_3_111PL & MG1_3_112PL & \ + MG1_3_113PL & MG1_3_114PL & MG1_3_115PL & MG1_3_116PL) +// End of MG1_3: +// Beginning of MG14: +#if (G1_1PL >= G1_4PL) || (G1_1PL == 0) +#define MG1_4_11PL ~(1 << 0) +#else +#define MG1_4_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_4PL) || (G1_2PL == 0) +#define MG1_4_12PL ~(1 << 1) +#else +#define MG1_4_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_4PL) || (G1_3PL == 0) +#define MG1_4_13PL ~(1 << 2) +#else +#define MG1_4_13PL 0xFFFF +#endif + +#if (G1_5PL >= G1_4PL) || (G1_5PL == 0) +#define MG1_4_15PL ~(1 << 4) +#else +#define MG1_4_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_4PL) || (G1_6PL == 0) +#define MG1_4_16PL ~(1 << 5) +#else +#define MG1_4_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_4PL) || (G1_7PL == 0) +#define MG1_4_17PL ~(1 << 6) +#else +#define MG1_4_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_4PL) || (G1_8PL == 0) +#define MG1_4_18PL ~(1 << 7) +#else +#define MG1_4_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_4PL) || (G1_9PL == 0) +#define MG1_4_19PL ~(1 << 8) +#else +#define MG1_4_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_4PL) || (G1_10PL == 0) +#define MG1_4_110PL ~(1 << 9) +#else +#define MG1_4_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_4PL) || (G1_11PL == 0) +#define MG1_4_111PL ~(1 << 10) +#else +#define MG1_4_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_4PL) || (G1_12PL == 0) +#define MG1_4_112PL ~(1 << 11) +#else +#define MG1_4_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_4PL) || (G1_13PL == 0) +#define MG1_4_113PL ~(1 << 12) +#else +#define MG1_4_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_4PL) || (G1_14PL == 0) +#define MG1_4_114PL ~(1 << 13) +#else +#define MG1_4_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_4PL) || (G1_15PL == 0) +#define MG1_4_115PL ~(1 << 14) +#else +#define MG1_4_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_4PL) || (G1_16PL == 0) +#define MG1_4_116PL ~(1 << 15) +#else +#define MG1_4_116PL 0xFFFF +#endif + +#define MG1_4_14PL 0xFFF7 +#define MG1_4 (MG1_4_11PL & MG1_4_12PL & MG1_4_13PL & MG1_4_14PL & \ + MG1_4_15PL & MG1_4_16PL & MG1_4_17PL & MG1_4_18PL & \ + MG1_4_19PL & MG1_4_110PL & MG1_4_111PL & MG1_4_112PL & \ + MG1_4_113PL & MG1_4_114PL & MG1_4_115PL & MG1_4_116PL) +// End of MG1_4: +// Beginning of MG15: +#if (G1_1PL >= G1_5PL) || (G1_1PL == 0) +#define MG1_5_11PL ~(1 << 0) +#else +#define MG1_5_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_5PL) || (G1_2PL == 0) +#define MG1_5_12PL ~(1 << 1) +#else +#define MG1_5_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_5PL) || (G1_3PL == 0) +#define MG1_5_13PL ~(1 << 2) +#else +#define MG1_5_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_5PL) || (G1_4PL == 0) +#define MG1_5_14PL ~(1 << 3) +#else +#define MG1_5_14PL 0xFFFF +#endif + +#if (G1_6PL >= G1_5PL) || (G1_6PL == 0) +#define MG1_5_16PL ~(1 << 5) +#else +#define MG1_5_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_5PL) || (G1_7PL == 0) +#define MG1_5_17PL ~(1 << 6) +#else +#define MG1_5_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_5PL) || (G1_8PL == 0) +#define MG1_5_18PL ~(1 << 7) +#else +#define MG1_5_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_5PL) || (G1_9PL == 0) +#define MG1_5_19PL ~(1 << 8) +#else +#define MG1_5_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_5PL) || (G1_10PL == 0) +#define MG1_5_110PL ~(1 << 9) +#else +#define MG1_5_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_5PL) || (G1_11PL == 0) +#define MG1_5_111PL ~(1 << 10) +#else +#define MG1_5_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_5PL) || (G1_12PL == 0) +#define MG1_5_112PL ~(1 << 11) +#else +#define MG1_5_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_5PL) || (G1_13PL == 0) +#define MG1_5_113PL ~(1 << 12) +#else +#define MG1_5_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_5PL) || (G1_14PL == 0) +#define MG1_5_114PL ~(1 << 13) +#else +#define MG1_5_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_5PL) || (G1_15PL == 0) +#define MG1_5_115PL ~(1 << 14) +#else +#define MG1_5_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_5PL) || (G1_16PL == 0) +#define MG1_5_116PL ~(1 << 15) +#else +#define MG1_5_116PL 0xFFFF +#endif + +#define MG1_5_15PL 0xFFEF +#define MG1_5 (MG1_5_11PL & MG1_5_12PL & MG1_5_13PL & MG1_5_14PL & \ + MG1_5_15PL & MG1_5_16PL & MG1_5_17PL & MG1_5_18PL & \ + MG1_5_19PL & MG1_5_110PL & MG1_5_111PL & MG1_5_112PL & \ + MG1_5_113PL & MG1_5_114PL & MG1_5_115PL & MG1_5_116PL) +// End of MG1_5: +// Beginning of MG16: +#if (G1_1PL >= G1_6PL) || (G1_1PL == 0) +#define MG1_6_11PL ~(1 << 0) +#else +#define MG1_6_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_6PL) || (G1_2PL == 0) +#define MG1_6_12PL ~(1 << 1) +#else +#define MG1_6_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_6PL) || (G1_3PL == 0) +#define MG1_6_13PL ~(1 << 2) +#else +#define MG1_6_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_6PL) || (G1_4PL == 0) +#define MG1_6_14PL ~(1 << 3) +#else +#define MG1_6_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_6PL) || (G1_5PL == 0) +#define MG1_6_15PL ~(1 << 4) +#else +#define MG1_6_15PL 0xFFFF +#endif + +#if (G1_7PL >= G1_6PL) || (G1_7PL == 0) +#define MG1_6_17PL ~(1 << 6) +#else +#define MG1_6_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_6PL) || (G1_8PL == 0) +#define MG1_6_18PL ~(1 << 7) +#else +#define MG1_6_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_6PL) || (G1_9PL == 0) +#define MG1_6_19PL ~(1 << 8) +#else +#define MG1_6_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_6PL) || (G1_10PL == 0) +#define MG1_6_110PL ~(1 << 9) +#else +#define MG1_6_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_6PL) || (G1_11PL == 0) +#define MG1_6_111PL ~(1 << 10) +#else +#define MG1_6_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_6PL) || (G1_12PL == 0) +#define MG1_6_112PL ~(1 << 11) +#else +#define MG1_6_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_6PL) || (G1_13PL == 0) +#define MG1_6_113PL ~(1 << 12) +#else +#define MG1_6_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_6PL) || (G1_14PL == 0) +#define MG1_6_114PL ~(1 << 13) +#else +#define MG1_6_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_6PL) || (G1_15PL == 0) +#define MG1_6_115PL ~(1 << 14) +#else +#define MG1_6_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_6PL) || (G1_16PL == 0) +#define MG1_6_116PL ~(1 << 15) +#else +#define MG1_6_116PL 0xFFFF +#endif + +#define MG1_6_16PL 0xFFDF +#define MG1_6 (MG1_6_11PL & MG1_6_12PL & MG1_6_13PL & MG1_6_14PL & \ + MG1_6_15PL & MG1_6_16PL & MG1_6_17PL & MG1_6_18PL & \ + MG1_6_19PL & MG1_6_110PL & MG1_6_111PL & MG1_6_112PL & \ + MG1_6_113PL & MG1_6_114PL & MG1_6_115PL & MG1_6_116PL) +// End of MG1_6: +// Beginning of MG17: +#if (G1_1PL >= G1_7PL) || (G1_1PL == 0) +#define MG1_7_11PL ~(1 << 0) +#else +#define MG1_7_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_7PL) || (G1_2PL == 0) +#define MG1_7_12PL ~(1 << 1) +#else +#define MG1_7_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_7PL) || (G1_3PL == 0) +#define MG1_7_13PL ~(1 << 2) +#else +#define MG1_7_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_7PL) || (G1_4PL == 0) +#define MG1_7_14PL ~(1 << 3) +#else +#define MG1_7_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_7PL) || (G1_5PL == 0) +#define MG1_7_15PL ~(1 << 4) +#else +#define MG1_7_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_7PL) || (G1_6PL == 0) +#define MG1_7_16PL ~(1 << 5) +#else +#define MG1_7_16PL 0xFFFF +#endif + +#if (G1_8PL >= G1_7PL) || (G1_8PL == 0) +#define MG1_7_18PL ~(1 << 7) +#else +#define MG1_7_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_7PL) || (G1_9PL == 0) +#define MG1_7_19PL ~(1 << 8) +#else +#define MG1_7_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_7PL) || (G1_10PL == 0) +#define MG1_7_110PL ~(1 << 9) +#else +#define MG1_7_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_7PL) || (G1_11PL == 0) +#define MG1_7_111PL ~(1 << 10) +#else +#define MG1_7_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_7PL) || (G1_12PL == 0) +#define MG1_7_112PL ~(1 << 11) +#else +#define MG1_7_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_7PL) || (G1_13PL == 0) +#define MG1_7_113PL ~(1 << 12) +#else +#define MG1_7_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_7PL) || (G1_14PL == 0) +#define MG1_7_114PL ~(1 << 13) +#else +#define MG1_7_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_7PL) || (G1_15PL == 0) +#define MG1_7_115PL ~(1 << 14) +#else +#define MG1_7_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_7PL) || (G1_16PL == 0) +#define MG1_7_116PL ~(1 << 15) +#else +#define MG1_7_116PL 0xFFFF +#endif + +#define MG1_7_17PL 0xFFBF +#define MG1_7 (MG1_7_11PL & MG1_7_12PL & MG1_7_13PL & MG1_7_14PL & \ + MG1_7_15PL & MG1_7_16PL & MG1_7_17PL & MG1_7_18PL & \ + MG1_7_19PL & MG1_7_110PL & MG1_7_111PL & MG1_7_112PL & \ + MG1_7_113PL & MG1_7_114PL & MG1_7_115PL & MG1_7_116PL) +// End of MG1_7: +// Beginning of MG18: +#if (G1_1PL >= G1_8PL) || (G1_1PL == 0) +#define MG1_8_11PL ~(1 << 0) +#else +#define MG1_8_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_8PL) || (G1_2PL == 0) +#define MG1_8_12PL ~(1 << 1) +#else +#define MG1_8_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_8PL) || (G1_3PL == 0) +#define MG1_8_13PL ~(1 << 2) +#else +#define MG1_8_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_8PL) || (G1_4PL == 0) +#define MG1_8_14PL ~(1 << 3) +#else +#define MG1_8_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_8PL) || (G1_5PL == 0) +#define MG1_8_15PL ~(1 << 4) +#else +#define MG1_8_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_8PL) || (G1_6PL == 0) +#define MG1_8_16PL ~(1 << 5) +#else +#define MG1_8_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_8PL) || (G1_7PL == 0) +#define MG1_8_17PL ~(1 << 6) +#else +#define MG1_8_17PL 0xFFFF +#endif + +#if (G1_9PL >= G1_8PL) || (G1_9PL == 0) +#define MG1_8_19PL ~(1 << 8) +#else +#define MG1_8_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_8PL) || (G1_10PL == 0) +#define MG1_8_110PL ~(1 << 9) +#else +#define MG1_8_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_8PL) || (G1_11PL == 0) +#define MG1_8_111PL ~(1 << 10) +#else +#define MG1_8_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_8PL) || (G1_12PL == 0) +#define MG1_8_112PL ~(1 << 11) +#else +#define MG1_8_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_8PL) || (G1_13PL == 0) +#define MG1_8_113PL ~(1 << 12) +#else +#define MG1_8_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_8PL) || (G1_14PL == 0) +#define MG1_8_114PL ~(1 << 13) +#else +#define MG1_8_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_8PL) || (G1_15PL == 0) +#define MG1_8_115PL ~(1 << 14) +#else +#define MG1_8_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_8PL) || (G1_16PL == 0) +#define MG1_8_116PL ~(1 << 15) +#else +#define MG1_8_116PL 0xFFFF +#endif + +#define MG1_8_18PL 0xFF7F +#define MG1_8 (MG1_8_11PL & MG1_8_12PL & MG1_8_13PL & MG1_8_14PL & \ + MG1_8_15PL & MG1_8_16PL & MG1_8_17PL & MG1_8_18PL & \ + MG1_8_19PL & MG1_8_110PL & MG1_8_111PL & MG1_8_112PL & \ + MG1_8_113PL & MG1_8_114PL & MG1_8_115PL & MG1_8_116PL) +// End of MG1_8: +// Beginning of MG19: +#if (G1_1PL >= G1_9PL) || (G1_1PL == 0) +#define MG1_9_11PL ~(1 << 0) +#else +#define MG1_9_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_9PL) || (G1_2PL == 0) +#define MG1_9_12PL ~(1 << 1) +#else +#define MG1_9_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_9PL) || (G1_3PL == 0) +#define MG1_9_13PL ~(1 << 2) +#else +#define MG1_9_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_9PL) || (G1_4PL == 0) +#define MG1_9_14PL ~(1 << 3) +#else +#define MG1_9_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_9PL) || (G1_5PL == 0) +#define MG1_9_15PL ~(1 << 4) +#else +#define MG1_9_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_9PL) || (G1_6PL == 0) +#define MG1_9_16PL ~(1 << 5) +#else +#define MG1_9_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_9PL) || (G1_7PL == 0) +#define MG1_9_17PL ~(1 << 6) +#else +#define MG1_9_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_9PL) || (G1_8PL == 0) +#define MG1_9_18PL ~(1 << 7) +#else +#define MG1_9_18PL 0xFFFF +#endif + +#if (G1_10PL >= G1_9PL) || (G1_10PL == 0) +#define MG1_9_110PL ~(1 << 9) +#else +#define MG1_9_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_9PL) || (G1_11PL == 0) +#define MG1_9_111PL ~(1 << 10) +#else +#define MG1_9_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_9PL) || (G1_12PL == 0) +#define MG1_9_112PL ~(1 << 11) +#else +#define MG1_9_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_9PL) || (G1_13PL == 0) +#define MG1_9_113PL ~(1 << 12) +#else +#define MG1_9_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_9PL) || (G1_14PL == 0) +#define MG1_9_114PL ~(1 << 13) +#else +#define MG1_9_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_9PL) || (G1_15PL == 0) +#define MG1_9_115PL ~(1 << 14) +#else +#define MG1_9_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_9PL) || (G1_16PL == 0) +#define MG1_9_116PL ~(1 << 15) +#else +#define MG1_9_116PL 0xFFFF +#endif + +#define MG1_9_19PL 0xFEFF +#define MG1_9 (MG1_9_11PL & MG1_9_12PL & MG1_9_13PL & MG1_9_14PL & \ + MG1_9_15PL & MG1_9_16PL & MG1_9_17PL & MG1_9_18PL & \ + MG1_9_19PL & MG1_9_110PL & MG1_9_111PL & MG1_9_112PL & \ + MG1_9_113PL & MG1_9_114PL & MG1_9_115PL & MG1_9_116PL) +// End of MG1_9: +// Beginning of MG110: +#if (G1_1PL >= G1_10PL) || (G1_1PL == 0) +#define MG1_10_11PL ~(1 << 0) +#else +#define MG1_10_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_10PL) || (G1_2PL == 0) +#define MG1_10_12PL ~(1 << 1) +#else +#define MG1_10_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_10PL) || (G1_3PL == 0) +#define MG1_10_13PL ~(1 << 2) +#else +#define MG1_10_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_10PL) || (G1_4PL == 0) +#define MG1_10_14PL ~(1 << 3) +#else +#define MG1_10_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_10PL) || (G1_5PL == 0) +#define MG1_10_15PL ~(1 << 4) +#else +#define MG1_10_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_10PL) || (G1_6PL == 0) +#define MG1_10_16PL ~(1 << 5) +#else +#define MG1_10_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_10PL) || (G1_7PL == 0) +#define MG1_10_17PL ~(1 << 6) +#else +#define MG1_10_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_10PL) || (G1_8PL == 0) +#define MG1_10_18PL ~(1 << 7) +#else +#define MG1_10_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_10PL) || (G1_9PL == 0) +#define MG1_10_19PL ~(1 << 8) +#else +#define MG1_10_19PL 0xFFFF +#endif + +#if (G1_11PL >= G1_10PL) || (G1_11PL == 0) +#define MG1_10_111PL ~(1 << 10) +#else +#define MG1_10_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_10PL) || (G1_12PL == 0) +#define MG1_10_112PL ~(1 << 11) +#else +#define MG1_10_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_10PL) || (G1_13PL == 0) +#define MG1_10_113PL ~(1 << 12) +#else +#define MG1_10_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_10PL) || (G1_14PL == 0) +#define MG1_10_114PL ~(1 << 13) +#else +#define MG1_10_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_10PL) || (G1_15PL == 0) +#define MG1_10_115PL ~(1 << 14) +#else +#define MG1_10_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_10PL) || (G1_16PL == 0) +#define MG1_10_116PL ~(1 << 15) +#else +#define MG1_10_116PL 0xFFFF +#endif + +#define MG1_10_110PL 0xFDFF +#define MG1_10 (MG1_10_11PL & MG1_10_12PL & MG1_10_13PL & MG1_10_14PL & \ + MG1_10_15PL & MG1_10_16PL & MG1_10_17PL & MG1_10_18PL & \ + MG1_10_19PL & MG1_10_110PL & MG1_10_111PL & MG1_10_112PL & \ + MG1_10_113PL & MG1_10_114PL & MG1_10_115PL & MG1_10_116PL) +// End of MG1_10: +// Beginning of MG111: +#if (G1_1PL >= G1_11PL) || (G1_1PL == 0) +#define MG1_11_11PL ~(1 << 0) +#else +#define MG1_11_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_11PL) || (G1_2PL == 0) +#define MG1_11_12PL ~(1 << 1) +#else +#define MG1_11_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_11PL) || (G1_3PL == 0) +#define MG1_11_13PL ~(1 << 2) +#else +#define MG1_11_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_11PL) || (G1_4PL == 0) +#define MG1_11_14PL ~(1 << 3) +#else +#define MG1_11_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_11PL) || (G1_5PL == 0) +#define MG1_11_15PL ~(1 << 4) +#else +#define MG1_11_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_11PL) || (G1_6PL == 0) +#define MG1_11_16PL ~(1 << 5) +#else +#define MG1_11_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_11PL) || (G1_7PL == 0) +#define MG1_11_17PL ~(1 << 6) +#else +#define MG1_11_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_11PL) || (G1_8PL == 0) +#define MG1_11_18PL ~(1 << 7) +#else +#define MG1_11_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_11PL) || (G1_9PL == 0) +#define MG1_11_19PL ~(1 << 8) +#else +#define MG1_11_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_11PL) || (G1_10PL == 0) +#define MG1_11_110PL ~(1 << 9) +#else +#define MG1_11_110PL 0xFFFF +#endif + +#if (G1_12PL >= G1_11PL) || (G1_12PL == 0) +#define MG1_11_112PL ~(1 << 11) +#else +#define MG1_11_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_11PL) || (G1_13PL == 0) +#define MG1_11_113PL ~(1 << 12) +#else +#define MG1_11_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_11PL) || (G1_14PL == 0) +#define MG1_11_114PL ~(1 << 13) +#else +#define MG1_11_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_11PL) || (G1_15PL == 0) +#define MG1_11_115PL ~(1 << 14) +#else +#define MG1_11_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_11PL) || (G1_16PL == 0) +#define MG1_11_116PL ~(1 << 15) +#else +#define MG1_11_116PL 0xFFFF +#endif + +#define MG1_11_111PL 0xFBFF +#define MG1_11 (MG1_11_11PL & MG1_11_12PL & MG1_11_13PL & MG1_11_14PL & \ + MG1_11_15PL & MG1_11_16PL & MG1_11_17PL & MG1_11_18PL & \ + MG1_11_19PL & MG1_11_110PL & MG1_11_111PL & MG1_11_112PL & \ + MG1_11_113PL & MG1_11_114PL & MG1_11_115PL & MG1_11_116PL) +// End of MG1_11: +// Beginning of MG112: +#if (G1_1PL >= G1_12PL) || (G1_1PL == 0) +#define MG1_12_11PL ~(1 << 0) +#else +#define MG1_12_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_12PL) || (G1_2PL == 0) +#define MG1_12_12PL ~(1 << 1) +#else +#define MG1_12_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_12PL) || (G1_3PL == 0) +#define MG1_12_13PL ~(1 << 2) +#else +#define MG1_12_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_12PL) || (G1_4PL == 0) +#define MG1_12_14PL ~(1 << 3) +#else +#define MG1_12_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_12PL) || (G1_5PL == 0) +#define MG1_12_15PL ~(1 << 4) +#else +#define MG1_12_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_12PL) || (G1_6PL == 0) +#define MG1_12_16PL ~(1 << 5) +#else +#define MG1_12_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_12PL) || (G1_7PL == 0) +#define MG1_12_17PL ~(1 << 6) +#else +#define MG1_12_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_12PL) || (G1_8PL == 0) +#define MG1_12_18PL ~(1 << 7) +#else +#define MG1_12_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_12PL) || (G1_9PL == 0) +#define MG1_12_19PL ~(1 << 8) +#else +#define MG1_12_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_12PL) || (G1_10PL == 0) +#define MG1_12_110PL ~(1 << 9) +#else +#define MG1_12_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_12PL) || (G1_11PL == 0) +#define MG1_12_111PL ~(1 << 10) +#else +#define MG1_12_111PL 0xFFFF +#endif + +#if (G1_13PL >= G1_12PL) || (G1_13PL == 0) +#define MG1_12_113PL ~(1 << 12) +#else +#define MG1_12_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_12PL) || (G1_14PL == 0) +#define MG1_12_114PL ~(1 << 13) +#else +#define MG1_12_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_12PL) || (G1_15PL == 0) +#define MG1_12_115PL ~(1 << 14) +#else +#define MG1_12_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_12PL) || (G1_16PL == 0) +#define MG1_12_116PL ~(1 << 15) +#else +#define MG1_12_116PL 0xFFFF +#endif + +#define MG1_12_112PL 0xF7FF +#define MG1_12 (MG1_12_11PL & MG1_12_12PL & MG1_12_13PL & MG1_12_14PL & \ + MG1_12_15PL & MG1_12_16PL & MG1_12_17PL & MG1_12_18PL & \ + MG1_12_19PL & MG1_12_110PL & MG1_12_111PL & MG1_12_112PL & \ + MG1_12_113PL & MG1_12_114PL & MG1_12_115PL & MG1_12_116PL) +// End of MG1_12: +// Beginning of MG113: +#if (G1_1PL >= G1_13PL) || (G1_1PL == 0) +#define MG1_13_11PL ~(1 << 0) +#else +#define MG1_13_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_13PL) || (G1_2PL == 0) +#define MG1_13_12PL ~(1 << 1) +#else +#define MG1_13_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_13PL) || (G1_3PL == 0) +#define MG1_13_13PL ~(1 << 2) +#else +#define MG1_13_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_13PL) || (G1_4PL == 0) +#define MG1_13_14PL ~(1 << 3) +#else +#define MG1_13_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_13PL) || (G1_5PL == 0) +#define MG1_13_15PL ~(1 << 4) +#else +#define MG1_13_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_13PL) || (G1_6PL == 0) +#define MG1_13_16PL ~(1 << 5) +#else +#define MG1_13_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_13PL) || (G1_7PL == 0) +#define MG1_13_17PL ~(1 << 6) +#else +#define MG1_13_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_13PL) || (G1_8PL == 0) +#define MG1_13_18PL ~(1 << 7) +#else +#define MG1_13_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_13PL) || (G1_9PL == 0) +#define MG1_13_19PL ~(1 << 8) +#else +#define MG1_13_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_13PL) || (G1_10PL == 0) +#define MG1_13_110PL ~(1 << 9) +#else +#define MG1_13_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_13PL) || (G1_11PL == 0) +#define MG1_13_111PL ~(1 << 10) +#else +#define MG1_13_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_13PL) || (G1_12PL == 0) +#define MG1_13_112PL ~(1 << 11) +#else +#define MG1_13_112PL 0xFFFF +#endif + +#if (G1_14PL >= G1_13PL) || (G1_14PL == 0) +#define MG1_13_114PL ~(1 << 13) +#else +#define MG1_13_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_13PL) || (G1_15PL == 0) +#define MG1_13_115PL ~(1 << 14) +#else +#define MG1_13_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_13PL) || (G1_16PL == 0) +#define MG1_13_116PL ~(1 << 15) +#else +#define MG1_13_116PL 0xFFFF +#endif + +#define MG1_13_113PL 0xEFFF +#define MG1_13 (MG1_13_11PL & MG1_13_12PL & MG1_13_13PL & MG1_13_14PL & \ + MG1_13_15PL & MG1_13_16PL & MG1_13_17PL & MG1_13_18PL & \ + MG1_13_19PL & MG1_13_110PL & MG1_13_111PL & MG1_13_112PL & \ + MG1_13_113PL & MG1_13_114PL & MG1_13_115PL & MG1_13_116PL) +// End of MG1_13: +// Beginning of MG114: +#if (G1_1PL >= G1_14PL) || (G1_1PL == 0) +#define MG1_14_11PL ~(1 << 0) +#else +#define MG1_14_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_14PL) || (G1_2PL == 0) +#define MG1_14_12PL ~(1 << 1) +#else +#define MG1_14_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_14PL) || (G1_3PL == 0) +#define MG1_14_13PL ~(1 << 2) +#else +#define MG1_14_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_14PL) || (G1_4PL == 0) +#define MG1_14_14PL ~(1 << 3) +#else +#define MG1_14_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_14PL) || (G1_5PL == 0) +#define MG1_14_15PL ~(1 << 4) +#else +#define MG1_14_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_14PL) || (G1_6PL == 0) +#define MG1_14_16PL ~(1 << 5) +#else +#define MG1_14_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_14PL) || (G1_7PL == 0) +#define MG1_14_17PL ~(1 << 6) +#else +#define MG1_14_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_14PL) || (G1_8PL == 0) +#define MG1_14_18PL ~(1 << 7) +#else +#define MG1_14_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_14PL) || (G1_9PL == 0) +#define MG1_14_19PL ~(1 << 8) +#else +#define MG1_14_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_14PL) || (G1_10PL == 0) +#define MG1_14_110PL ~(1 << 9) +#else +#define MG1_14_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_14PL) || (G1_11PL == 0) +#define MG1_14_111PL ~(1 << 10) +#else +#define MG1_14_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_14PL) || (G1_12PL == 0) +#define MG1_14_112PL ~(1 << 11) +#else +#define MG1_14_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_14PL) || (G1_13PL == 0) +#define MG1_14_113PL ~(1 << 12) +#else +#define MG1_14_113PL 0xFFFF +#endif + +#if (G1_15PL >= G1_14PL) || (G1_15PL == 0) +#define MG1_14_115PL ~(1 << 14) +#else +#define MG1_14_115PL 0xFFFF +#endif + +#if (G1_16PL >= G1_14PL) || (G1_16PL == 0) +#define MG1_14_116PL ~(1 << 15) +#else +#define MG1_14_116PL 0xFFFF +#endif + +#define MG1_14_114PL 0xDFFF +#define MG1_14 (MG1_14_11PL & MG1_14_12PL & MG1_14_13PL & MG1_14_14PL & \ + MG1_14_15PL & MG1_14_16PL & MG1_14_17PL & MG1_14_18PL & \ + MG1_14_19PL & MG1_14_110PL & MG1_14_111PL & MG1_14_112PL & \ + MG1_14_113PL & MG1_14_114PL & MG1_14_115PL & MG1_14_116PL) +// End of MG1_14: +// Beginning of MG115: +#if (G1_1PL >= G1_15PL) || (G1_1PL == 0) +#define MG1_15_11PL ~(1 << 0) +#else +#define MG1_15_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_15PL) || (G1_2PL == 0) +#define MG1_15_12PL ~(1 << 1) +#else +#define MG1_15_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_15PL) || (G1_3PL == 0) +#define MG1_15_13PL ~(1 << 2) +#else +#define MG1_15_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_15PL) || (G1_4PL == 0) +#define MG1_15_14PL ~(1 << 3) +#else +#define MG1_15_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_15PL) || (G1_5PL == 0) +#define MG1_15_15PL ~(1 << 4) +#else +#define MG1_15_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_15PL) || (G1_6PL == 0) +#define MG1_15_16PL ~(1 << 5) +#else +#define MG1_15_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_15PL) || (G1_7PL == 0) +#define MG1_15_17PL ~(1 << 6) +#else +#define MG1_15_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_15PL) || (G1_8PL == 0) +#define MG1_15_18PL ~(1 << 7) +#else +#define MG1_15_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_15PL) || (G1_9PL == 0) +#define MG1_15_19PL ~(1 << 8) +#else +#define MG1_15_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_15PL) || (G1_10PL == 0) +#define MG1_15_110PL ~(1 << 9) +#else +#define MG1_15_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_15PL) || (G1_11PL == 0) +#define MG1_15_111PL ~(1 << 10) +#else +#define MG1_15_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_15PL) || (G1_12PL == 0) +#define MG1_15_112PL ~(1 << 11) +#else +#define MG1_15_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_15PL) || (G1_13PL == 0) +#define MG1_15_113PL ~(1 << 12) +#else +#define MG1_15_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_15PL) || (G1_14PL == 0) +#define MG1_15_114PL ~(1 << 13) +#else +#define MG1_15_114PL 0xFFFF +#endif + +#if (G1_16PL >= G1_15PL) || (G1_16PL == 0) +#define MG1_15_116PL ~(1 << 15) +#else +#define MG1_15_116PL 0xFFFF +#endif + +#define MG1_15_115PL 0xBFFF +#define MG1_15 (MG1_15_11PL & MG1_15_12PL & MG1_15_13PL & MG1_15_14PL & \ + MG1_15_15PL & MG1_15_16PL & MG1_15_17PL & MG1_15_18PL & \ + MG1_15_19PL & MG1_15_110PL & MG1_15_111PL & MG1_15_112PL & \ + MG1_15_113PL & MG1_15_114PL & MG1_15_115PL & MG1_15_116PL) +// End of MG1_15: +// Beginning of MG116: +#if (G1_1PL >= G1_16PL) || (G1_1PL == 0) +#define MG1_16_11PL ~(1 << 0) +#else +#define MG1_16_11PL 0xFFFF +#endif + +#if (G1_2PL >= G1_16PL) || (G1_2PL == 0) +#define MG1_16_12PL ~(1 << 1) +#else +#define MG1_16_12PL 0xFFFF +#endif + +#if (G1_3PL >= G1_16PL) || (G1_3PL == 0) +#define MG1_16_13PL ~(1 << 2) +#else +#define MG1_16_13PL 0xFFFF +#endif + +#if (G1_4PL >= G1_16PL) || (G1_4PL == 0) +#define MG1_16_14PL ~(1 << 3) +#else +#define MG1_16_14PL 0xFFFF +#endif + +#if (G1_5PL >= G1_16PL) || (G1_5PL == 0) +#define MG1_16_15PL ~(1 << 4) +#else +#define MG1_16_15PL 0xFFFF +#endif + +#if (G1_6PL >= G1_16PL) || (G1_6PL == 0) +#define MG1_16_16PL ~(1 << 5) +#else +#define MG1_16_16PL 0xFFFF +#endif + +#if (G1_7PL >= G1_16PL) || (G1_7PL == 0) +#define MG1_16_17PL ~(1 << 6) +#else +#define MG1_16_17PL 0xFFFF +#endif + +#if (G1_8PL >= G1_16PL) || (G1_8PL == 0) +#define MG1_16_18PL ~(1 << 7) +#else +#define MG1_16_18PL 0xFFFF +#endif + +#if (G1_9PL >= G1_16PL) || (G1_9PL == 0) +#define MG1_16_19PL ~(1 << 8) +#else +#define MG1_16_19PL 0xFFFF +#endif + +#if (G1_10PL >= G1_16PL) || (G1_10PL == 0) +#define MG1_16_110PL ~(1 << 9) +#else +#define MG1_16_110PL 0xFFFF +#endif + +#if (G1_11PL >= G1_16PL) || (G1_11PL == 0) +#define MG1_16_111PL ~(1 << 10) +#else +#define MG1_16_111PL 0xFFFF +#endif + +#if (G1_12PL >= G1_16PL) || (G1_12PL == 0) +#define MG1_16_112PL ~(1 << 11) +#else +#define MG1_16_112PL 0xFFFF +#endif + +#if (G1_13PL >= G1_16PL) || (G1_13PL == 0) +#define MG1_16_113PL ~(1 << 12) +#else +#define MG1_16_113PL 0xFFFF +#endif + +#if (G1_14PL >= G1_16PL) || (G1_14PL == 0) +#define MG1_16_114PL ~(1 << 13) +#else +#define MG1_16_114PL 0xFFFF +#endif + +#if (G1_15PL >= G1_16PL) || (G1_15PL == 0) +#define MG1_16_115PL ~(1 << 14) +#else +#define MG1_16_115PL 0xFFFF +#endif + +#define MG1_16_116PL 0x7FFF +#define MG1_16 (MG1_16_11PL & MG1_16_12PL & MG1_16_13PL & MG1_16_14PL & \ + MG1_16_15PL & MG1_16_16PL & MG1_16_17PL & MG1_16_18PL & \ + MG1_16_19PL & MG1_16_110PL & MG1_16_111PL & MG1_16_112PL & \ + MG1_16_113PL & MG1_16_114PL & MG1_16_115PL & MG1_16_116PL) +// End of MG1_16: + + +// +// Automatically generate PIEIER2 interrupt masks MG21 to MG216: +// + +// Beginning of MG21: +#if (G2_2PL >= G2_1PL) || (G2_2PL == 0) +#define MG2_1_12PL ~(1 << 1) +#else +#define MG2_1_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_1PL) || (G2_3PL == 0) +#define MG2_1_13PL ~(1 << 2) +#else +#define MG2_1_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_1PL) || (G2_4PL == 0) +#define MG2_1_14PL ~(1 << 3) +#else +#define MG2_1_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_1PL) || (G2_5PL == 0) +#define MG2_1_15PL ~(1 << 4) +#else +#define MG2_1_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_1PL) || (G2_6PL == 0) +#define MG2_1_16PL ~(1 << 5) +#else +#define MG2_1_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_1PL) || (G2_7PL == 0) +#define MG2_1_17PL ~(1 << 6) +#else +#define MG2_1_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_1PL) || (G2_8PL == 0) +#define MG2_1_18PL ~(1 << 7) +#else +#define MG2_1_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_1PL) || (G2_9PL == 0) +#define MG2_1_19PL ~(1 << 8) +#else +#define MG2_1_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_1PL) || (G2_10PL == 0) +#define MG2_1_110PL ~(1 << 9) +#else +#define MG2_1_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_1PL) || (G2_11PL == 0) +#define MG2_1_111PL ~(1 << 10) +#else +#define MG2_1_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_1PL) || (G2_12PL == 0) +#define MG2_1_112PL ~(1 << 11) +#else +#define MG2_1_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_1PL) || (G2_13PL == 0) +#define MG2_1_113PL ~(1 << 12) +#else +#define MG2_1_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_1PL) || (G2_14PL == 0) +#define MG2_1_114PL ~(1 << 13) +#else +#define MG2_1_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_1PL) || (G2_15PL == 0) +#define MG2_1_115PL ~(1 << 14) +#else +#define MG2_1_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_1PL) || (G2_16PL == 0) +#define MG2_1_116PL ~(1 << 15) +#else +#define MG2_1_116PL 0xFFFF +#endif + +#define MG2_1_11PL 0xFFFE +#define MG2_1 (MG2_1_11PL & MG2_1_12PL & MG2_1_13PL & MG2_1_14PL & \ + MG2_1_15PL & MG2_1_16PL & MG2_1_17PL & MG2_1_18PL & \ + MG2_1_19PL & MG2_1_110PL & MG2_1_111PL & MG2_1_112PL & \ + MG2_1_113PL & MG2_1_114PL & MG2_1_115PL & MG2_1_116PL) +// End of MG2_1: +// Beginning of MG22: +#if (G2_1PL >= G2_2PL) || (G2_1PL == 0) +#define MG2_2_11PL ~(1 << 0) +#else +#define MG2_2_11PL 0xFFFF +#endif + +#if (G2_3PL >= G2_2PL) || (G2_3PL == 0) +#define MG2_2_13PL ~(1 << 2) +#else +#define MG2_2_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_2PL) || (G2_4PL == 0) +#define MG2_2_14PL ~(1 << 3) +#else +#define MG2_2_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_2PL) || (G2_5PL == 0) +#define MG2_2_15PL ~(1 << 4) +#else +#define MG2_2_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_2PL) || (G2_6PL == 0) +#define MG2_2_16PL ~(1 << 5) +#else +#define MG2_2_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_2PL) || (G2_7PL == 0) +#define MG2_2_17PL ~(1 << 6) +#else +#define MG2_2_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_2PL) || (G2_8PL == 0) +#define MG2_2_18PL ~(1 << 7) +#else +#define MG2_2_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_2PL) || (G2_9PL == 0) +#define MG2_2_19PL ~(1 << 8) +#else +#define MG2_2_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_2PL) || (G2_10PL == 0) +#define MG2_2_110PL ~(1 << 9) +#else +#define MG2_2_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_2PL) || (G2_11PL == 0) +#define MG2_2_111PL ~(1 << 10) +#else +#define MG2_2_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_2PL) || (G2_12PL == 0) +#define MG2_2_112PL ~(1 << 11) +#else +#define MG2_2_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_2PL) || (G2_13PL == 0) +#define MG2_2_113PL ~(1 << 12) +#else +#define MG2_2_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_2PL) || (G2_14PL == 0) +#define MG2_2_114PL ~(1 << 13) +#else +#define MG2_2_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_2PL) || (G2_15PL == 0) +#define MG2_2_115PL ~(1 << 14) +#else +#define MG2_2_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_2PL) || (G2_16PL == 0) +#define MG2_2_116PL ~(1 << 15) +#else +#define MG2_2_116PL 0xFFFF +#endif + +#define MG2_2_12PL 0xFFFD +#define MG2_2 (MG2_2_11PL & MG2_2_12PL & MG2_2_13PL & MG2_2_14PL & \ + MG2_2_15PL & MG2_2_16PL & MG2_2_17PL & MG2_2_18PL & \ + MG2_2_19PL & MG2_2_110PL & MG2_2_111PL & MG2_2_112PL & \ + MG2_2_113PL & MG2_2_114PL & MG2_2_115PL & MG2_2_116PL) +// End of MG2_2: +// Beginning of MG23: +#if (G2_1PL >= G2_3PL) || (G2_1PL == 0) +#define MG2_3_11PL ~(1 << 0) +#else +#define MG2_3_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_3PL) || (G2_2PL == 0) +#define MG2_3_12PL ~(1 << 1) +#else +#define MG2_3_12PL 0xFFFF +#endif + +#if (G2_4PL >= G2_3PL) || (G2_4PL == 0) +#define MG2_3_14PL ~(1 << 3) +#else +#define MG2_3_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_3PL) || (G2_5PL == 0) +#define MG2_3_15PL ~(1 << 4) +#else +#define MG2_3_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_3PL) || (G2_6PL == 0) +#define MG2_3_16PL ~(1 << 5) +#else +#define MG2_3_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_3PL) || (G2_7PL == 0) +#define MG2_3_17PL ~(1 << 6) +#else +#define MG2_3_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_3PL) || (G2_8PL == 0) +#define MG2_3_18PL ~(1 << 7) +#else +#define MG2_3_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_3PL) || (G2_9PL == 0) +#define MG2_3_19PL ~(1 << 8) +#else +#define MG2_3_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_3PL) || (G2_10PL == 0) +#define MG2_3_110PL ~(1 << 9) +#else +#define MG2_3_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_3PL) || (G2_11PL == 0) +#define MG2_3_111PL ~(1 << 10) +#else +#define MG2_3_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_3PL) || (G2_12PL == 0) +#define MG2_3_112PL ~(1 << 11) +#else +#define MG2_3_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_3PL) || (G2_13PL == 0) +#define MG2_3_113PL ~(1 << 12) +#else +#define MG2_3_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_3PL) || (G2_14PL == 0) +#define MG2_3_114PL ~(1 << 13) +#else +#define MG2_3_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_3PL) || (G2_15PL == 0) +#define MG2_3_115PL ~(1 << 14) +#else +#define MG2_3_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_3PL) || (G2_16PL == 0) +#define MG2_3_116PL ~(1 << 15) +#else +#define MG2_3_116PL 0xFFFF +#endif + +#define MG2_3_13PL 0xFFFB +#define MG2_3 (MG2_3_11PL & MG2_3_12PL & MG2_3_13PL & MG2_3_14PL & \ + MG2_3_15PL & MG2_3_16PL & MG2_3_17PL & MG2_3_18PL & \ + MG2_3_19PL & MG2_3_110PL & MG2_3_111PL & MG2_3_112PL & \ + MG2_3_113PL & MG2_3_114PL & MG2_3_115PL & MG2_3_116PL) +// End of MG2_3: +// Beginning of MG24: +#if (G2_1PL >= G2_4PL) || (G2_1PL == 0) +#define MG2_4_11PL ~(1 << 0) +#else +#define MG2_4_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_4PL) || (G2_2PL == 0) +#define MG2_4_12PL ~(1 << 1) +#else +#define MG2_4_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_4PL) || (G2_3PL == 0) +#define MG2_4_13PL ~(1 << 2) +#else +#define MG2_4_13PL 0xFFFF +#endif + +#if (G2_5PL >= G2_4PL) || (G2_5PL == 0) +#define MG2_4_15PL ~(1 << 4) +#else +#define MG2_4_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_4PL) || (G2_6PL == 0) +#define MG2_4_16PL ~(1 << 5) +#else +#define MG2_4_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_4PL) || (G2_7PL == 0) +#define MG2_4_17PL ~(1 << 6) +#else +#define MG2_4_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_4PL) || (G2_8PL == 0) +#define MG2_4_18PL ~(1 << 7) +#else +#define MG2_4_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_4PL) || (G2_9PL == 0) +#define MG2_4_19PL ~(1 << 8) +#else +#define MG2_4_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_4PL) || (G2_10PL == 0) +#define MG2_4_110PL ~(1 << 9) +#else +#define MG2_4_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_4PL) || (G2_11PL == 0) +#define MG2_4_111PL ~(1 << 10) +#else +#define MG2_4_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_4PL) || (G2_12PL == 0) +#define MG2_4_112PL ~(1 << 11) +#else +#define MG2_4_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_4PL) || (G2_13PL == 0) +#define MG2_4_113PL ~(1 << 12) +#else +#define MG2_4_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_4PL) || (G2_14PL == 0) +#define MG2_4_114PL ~(1 << 13) +#else +#define MG2_4_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_4PL) || (G2_15PL == 0) +#define MG2_4_115PL ~(1 << 14) +#else +#define MG2_4_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_4PL) || (G2_16PL == 0) +#define MG2_4_116PL ~(1 << 15) +#else +#define MG2_4_116PL 0xFFFF +#endif + +#define MG2_4_14PL 0xFFF7 +#define MG2_4 (MG2_4_11PL & MG2_4_12PL & MG2_4_13PL & MG2_4_14PL & \ + MG2_4_15PL & MG2_4_16PL & MG2_4_17PL & MG2_4_18PL & \ + MG2_4_19PL & MG2_4_110PL & MG2_4_111PL & MG2_4_112PL & \ + MG2_4_113PL & MG2_4_114PL & MG2_4_115PL & MG2_4_116PL) +// End of MG2_4: +// Beginning of MG25: +#if (G2_1PL >= G2_5PL) || (G2_1PL == 0) +#define MG2_5_11PL ~(1 << 0) +#else +#define MG2_5_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_5PL) || (G2_2PL == 0) +#define MG2_5_12PL ~(1 << 1) +#else +#define MG2_5_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_5PL) || (G2_3PL == 0) +#define MG2_5_13PL ~(1 << 2) +#else +#define MG2_5_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_5PL) || (G2_4PL == 0) +#define MG2_5_14PL ~(1 << 3) +#else +#define MG2_5_14PL 0xFFFF +#endif + +#if (G2_6PL >= G2_5PL) || (G2_6PL == 0) +#define MG2_5_16PL ~(1 << 5) +#else +#define MG2_5_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_5PL) || (G2_7PL == 0) +#define MG2_5_17PL ~(1 << 6) +#else +#define MG2_5_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_5PL) || (G2_8PL == 0) +#define MG2_5_18PL ~(1 << 7) +#else +#define MG2_5_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_5PL) || (G2_9PL == 0) +#define MG2_5_19PL ~(1 << 8) +#else +#define MG2_5_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_5PL) || (G2_10PL == 0) +#define MG2_5_110PL ~(1 << 9) +#else +#define MG2_5_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_5PL) || (G2_11PL == 0) +#define MG2_5_111PL ~(1 << 10) +#else +#define MG2_5_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_5PL) || (G2_12PL == 0) +#define MG2_5_112PL ~(1 << 11) +#else +#define MG2_5_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_5PL) || (G2_13PL == 0) +#define MG2_5_113PL ~(1 << 12) +#else +#define MG2_5_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_5PL) || (G2_14PL == 0) +#define MG2_5_114PL ~(1 << 13) +#else +#define MG2_5_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_5PL) || (G2_15PL == 0) +#define MG2_5_115PL ~(1 << 14) +#else +#define MG2_5_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_5PL) || (G2_16PL == 0) +#define MG2_5_116PL ~(1 << 15) +#else +#define MG2_5_116PL 0xFFFF +#endif + +#define MG2_5_15PL 0xFFEF +#define MG2_5 (MG2_5_11PL & MG2_5_12PL & MG2_5_13PL & MG2_5_14PL & \ + MG2_5_15PL & MG2_5_16PL & MG2_5_17PL & MG2_5_18PL & \ + MG2_5_19PL & MG2_5_110PL & MG2_5_111PL & MG2_5_112PL & \ + MG2_5_113PL & MG2_5_114PL & MG2_5_115PL & MG2_5_116PL) +// End of MG2_5: +// Beginning of MG26: +#if (G2_1PL >= G2_6PL) || (G2_1PL == 0) +#define MG2_6_11PL ~(1 << 0) +#else +#define MG2_6_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_6PL) || (G2_2PL == 0) +#define MG2_6_12PL ~(1 << 1) +#else +#define MG2_6_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_6PL) || (G2_3PL == 0) +#define MG2_6_13PL ~(1 << 2) +#else +#define MG2_6_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_6PL) || (G2_4PL == 0) +#define MG2_6_14PL ~(1 << 3) +#else +#define MG2_6_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_6PL) || (G2_5PL == 0) +#define MG2_6_15PL ~(1 << 4) +#else +#define MG2_6_15PL 0xFFFF +#endif + +#if (G2_7PL >= G2_6PL) || (G2_7PL == 0) +#define MG2_6_17PL ~(1 << 6) +#else +#define MG2_6_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_6PL) || (G2_8PL == 0) +#define MG2_6_18PL ~(1 << 7) +#else +#define MG2_6_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_6PL) || (G2_9PL == 0) +#define MG2_6_19PL ~(1 << 8) +#else +#define MG2_6_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_6PL) || (G2_10PL == 0) +#define MG2_6_110PL ~(1 << 9) +#else +#define MG2_6_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_6PL) || (G2_11PL == 0) +#define MG2_6_111PL ~(1 << 10) +#else +#define MG2_6_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_6PL) || (G2_12PL == 0) +#define MG2_6_112PL ~(1 << 11) +#else +#define MG2_6_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_6PL) || (G2_13PL == 0) +#define MG2_6_113PL ~(1 << 12) +#else +#define MG2_6_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_6PL) || (G2_14PL == 0) +#define MG2_6_114PL ~(1 << 13) +#else +#define MG2_6_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_6PL) || (G2_15PL == 0) +#define MG2_6_115PL ~(1 << 14) +#else +#define MG2_6_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_6PL) || (G2_16PL == 0) +#define MG2_6_116PL ~(1 << 15) +#else +#define MG2_6_116PL 0xFFFF +#endif + +#define MG2_6_16PL 0xFFDF +#define MG2_6 (MG2_6_11PL & MG2_6_12PL & MG2_6_13PL & MG2_6_14PL & \ + MG2_6_15PL & MG2_6_16PL & MG2_6_17PL & MG2_6_18PL & \ + MG2_6_19PL & MG2_6_110PL & MG2_6_111PL & MG2_6_112PL & \ + MG2_6_113PL & MG2_6_114PL & MG2_6_115PL & MG2_6_116PL) +// End of MG2_6: +// Beginning of MG27: +#if (G2_1PL >= G2_7PL) || (G2_1PL == 0) +#define MG2_7_11PL ~(1 << 0) +#else +#define MG2_7_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_7PL) || (G2_2PL == 0) +#define MG2_7_12PL ~(1 << 1) +#else +#define MG2_7_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_7PL) || (G2_3PL == 0) +#define MG2_7_13PL ~(1 << 2) +#else +#define MG2_7_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_7PL) || (G2_4PL == 0) +#define MG2_7_14PL ~(1 << 3) +#else +#define MG2_7_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_7PL) || (G2_5PL == 0) +#define MG2_7_15PL ~(1 << 4) +#else +#define MG2_7_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_7PL) || (G2_6PL == 0) +#define MG2_7_16PL ~(1 << 5) +#else +#define MG2_7_16PL 0xFFFF +#endif + +#if (G2_8PL >= G2_7PL) || (G2_8PL == 0) +#define MG2_7_18PL ~(1 << 7) +#else +#define MG2_7_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_7PL) || (G2_9PL == 0) +#define MG2_7_19PL ~(1 << 8) +#else +#define MG2_7_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_7PL) || (G2_10PL == 0) +#define MG2_7_110PL ~(1 << 9) +#else +#define MG2_7_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_7PL) || (G2_11PL == 0) +#define MG2_7_111PL ~(1 << 10) +#else +#define MG2_7_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_7PL) || (G2_12PL == 0) +#define MG2_7_112PL ~(1 << 11) +#else +#define MG2_7_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_7PL) || (G2_13PL == 0) +#define MG2_7_113PL ~(1 << 12) +#else +#define MG2_7_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_7PL) || (G2_14PL == 0) +#define MG2_7_114PL ~(1 << 13) +#else +#define MG2_7_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_7PL) || (G2_15PL == 0) +#define MG2_7_115PL ~(1 << 14) +#else +#define MG2_7_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_7PL) || (G2_16PL == 0) +#define MG2_7_116PL ~(1 << 15) +#else +#define MG2_7_116PL 0xFFFF +#endif + +#define MG2_7_17PL 0xFFBF +#define MG2_7 (MG2_7_11PL & MG2_7_12PL & MG2_7_13PL & MG2_7_14PL & \ + MG2_7_15PL & MG2_7_16PL & MG2_7_17PL & MG2_7_18PL & \ + MG2_7_19PL & MG2_7_110PL & MG2_7_111PL & MG2_7_112PL & \ + MG2_7_113PL & MG2_7_114PL & MG2_7_115PL & MG2_7_116PL) +// End of MG2_7: +// Beginning of MG28: +#if (G2_1PL >= G2_8PL) || (G2_1PL == 0) +#define MG2_8_11PL ~(1 << 0) +#else +#define MG2_8_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_8PL) || (G2_2PL == 0) +#define MG2_8_12PL ~(1 << 1) +#else +#define MG2_8_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_8PL) || (G2_3PL == 0) +#define MG2_8_13PL ~(1 << 2) +#else +#define MG2_8_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_8PL) || (G2_4PL == 0) +#define MG2_8_14PL ~(1 << 3) +#else +#define MG2_8_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_8PL) || (G2_5PL == 0) +#define MG2_8_15PL ~(1 << 4) +#else +#define MG2_8_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_8PL) || (G2_6PL == 0) +#define MG2_8_16PL ~(1 << 5) +#else +#define MG2_8_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_8PL) || (G2_7PL == 0) +#define MG2_8_17PL ~(1 << 6) +#else +#define MG2_8_17PL 0xFFFF +#endif + +#if (G2_9PL >= G2_8PL) || (G2_9PL == 0) +#define MG2_8_19PL ~(1 << 8) +#else +#define MG2_8_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_8PL) || (G2_10PL == 0) +#define MG2_8_110PL ~(1 << 9) +#else +#define MG2_8_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_8PL) || (G2_11PL == 0) +#define MG2_8_111PL ~(1 << 10) +#else +#define MG2_8_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_8PL) || (G2_12PL == 0) +#define MG2_8_112PL ~(1 << 11) +#else +#define MG2_8_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_8PL) || (G2_13PL == 0) +#define MG2_8_113PL ~(1 << 12) +#else +#define MG2_8_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_8PL) || (G2_14PL == 0) +#define MG2_8_114PL ~(1 << 13) +#else +#define MG2_8_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_8PL) || (G2_15PL == 0) +#define MG2_8_115PL ~(1 << 14) +#else +#define MG2_8_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_8PL) || (G2_16PL == 0) +#define MG2_8_116PL ~(1 << 15) +#else +#define MG2_8_116PL 0xFFFF +#endif + +#define MG2_8_18PL 0xFF7F +#define MG2_8 (MG2_8_11PL & MG2_8_12PL & MG2_8_13PL & MG2_8_14PL & \ + MG2_8_15PL & MG2_8_16PL & MG2_8_17PL & MG2_8_18PL & \ + MG2_8_19PL & MG2_8_110PL & MG2_8_111PL & MG2_8_112PL & \ + MG2_8_113PL & MG2_8_114PL & MG2_8_115PL & MG2_8_116PL) +// End of MG2_8: +// Beginning of MG29: +#if (G2_1PL >= G2_9PL) || (G2_1PL == 0) +#define MG2_9_11PL ~(1 << 0) +#else +#define MG2_9_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_9PL) || (G2_2PL == 0) +#define MG2_9_12PL ~(1 << 1) +#else +#define MG2_9_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_9PL) || (G2_3PL == 0) +#define MG2_9_13PL ~(1 << 2) +#else +#define MG2_9_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_9PL) || (G2_4PL == 0) +#define MG2_9_14PL ~(1 << 3) +#else +#define MG2_9_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_9PL) || (G2_5PL == 0) +#define MG2_9_15PL ~(1 << 4) +#else +#define MG2_9_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_9PL) || (G2_6PL == 0) +#define MG2_9_16PL ~(1 << 5) +#else +#define MG2_9_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_9PL) || (G2_7PL == 0) +#define MG2_9_17PL ~(1 << 6) +#else +#define MG2_9_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_9PL) || (G2_8PL == 0) +#define MG2_9_18PL ~(1 << 7) +#else +#define MG2_9_18PL 0xFFFF +#endif + +#if (G2_10PL >= G2_9PL) || (G2_10PL == 0) +#define MG2_9_110PL ~(1 << 9) +#else +#define MG2_9_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_9PL) || (G2_11PL == 0) +#define MG2_9_111PL ~(1 << 10) +#else +#define MG2_9_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_9PL) || (G2_12PL == 0) +#define MG2_9_112PL ~(1 << 11) +#else +#define MG2_9_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_9PL) || (G2_13PL == 0) +#define MG2_9_113PL ~(1 << 12) +#else +#define MG2_9_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_9PL) || (G2_14PL == 0) +#define MG2_9_114PL ~(1 << 13) +#else +#define MG2_9_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_9PL) || (G2_15PL == 0) +#define MG2_9_115PL ~(1 << 14) +#else +#define MG2_9_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_9PL) || (G2_16PL == 0) +#define MG2_9_116PL ~(1 << 15) +#else +#define MG2_9_116PL 0xFFFF +#endif + +#define MG2_9_19PL 0xFEFF +#define MG2_9 (MG2_9_11PL & MG2_9_12PL & MG2_9_13PL & MG2_9_14PL & \ + MG2_9_15PL & MG2_9_16PL & MG2_9_17PL & MG2_9_18PL & \ + MG2_9_19PL & MG2_9_110PL & MG2_9_111PL & MG2_9_112PL & \ + MG2_9_113PL & MG2_9_114PL & MG2_9_115PL & MG2_9_116PL) +// End of MG2_9: +// Beginning of MG210: +#if (G2_1PL >= G2_10PL) || (G2_1PL == 0) +#define MG2_10_11PL ~(1 << 0) +#else +#define MG2_10_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_10PL) || (G2_2PL == 0) +#define MG2_10_12PL ~(1 << 1) +#else +#define MG2_10_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_10PL) || (G2_3PL == 0) +#define MG2_10_13PL ~(1 << 2) +#else +#define MG2_10_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_10PL) || (G2_4PL == 0) +#define MG2_10_14PL ~(1 << 3) +#else +#define MG2_10_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_10PL) || (G2_5PL == 0) +#define MG2_10_15PL ~(1 << 4) +#else +#define MG2_10_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_10PL) || (G2_6PL == 0) +#define MG2_10_16PL ~(1 << 5) +#else +#define MG2_10_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_10PL) || (G2_7PL == 0) +#define MG2_10_17PL ~(1 << 6) +#else +#define MG2_10_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_10PL) || (G2_8PL == 0) +#define MG2_10_18PL ~(1 << 7) +#else +#define MG2_10_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_10PL) || (G2_9PL == 0) +#define MG2_10_19PL ~(1 << 8) +#else +#define MG2_10_19PL 0xFFFF +#endif + +#if (G2_11PL >= G2_10PL) || (G2_11PL == 0) +#define MG2_10_111PL ~(1 << 10) +#else +#define MG2_10_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_10PL) || (G2_12PL == 0) +#define MG2_10_112PL ~(1 << 11) +#else +#define MG2_10_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_10PL) || (G2_13PL == 0) +#define MG2_10_113PL ~(1 << 12) +#else +#define MG2_10_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_10PL) || (G2_14PL == 0) +#define MG2_10_114PL ~(1 << 13) +#else +#define MG2_10_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_10PL) || (G2_15PL == 0) +#define MG2_10_115PL ~(1 << 14) +#else +#define MG2_10_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_10PL) || (G2_16PL == 0) +#define MG2_10_116PL ~(1 << 15) +#else +#define MG2_10_116PL 0xFFFF +#endif + +#define MG2_10_110PL 0xFDFF +#define MG2_10 (MG2_10_11PL & MG2_10_12PL & MG2_10_13PL & MG2_10_14PL & \ + MG2_10_15PL & MG2_10_16PL & MG2_10_17PL & MG2_10_18PL & \ + MG2_10_19PL & MG2_10_110PL & MG2_10_111PL & MG2_10_112PL & \ + MG2_10_113PL & MG2_10_114PL & MG2_10_115PL & MG2_10_116PL) +// End of MG2_10: +// Beginning of MG211: +#if (G2_1PL >= G2_11PL) || (G2_1PL == 0) +#define MG2_11_11PL ~(1 << 0) +#else +#define MG2_11_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_11PL) || (G2_2PL == 0) +#define MG2_11_12PL ~(1 << 1) +#else +#define MG2_11_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_11PL) || (G2_3PL == 0) +#define MG2_11_13PL ~(1 << 2) +#else +#define MG2_11_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_11PL) || (G2_4PL == 0) +#define MG2_11_14PL ~(1 << 3) +#else +#define MG2_11_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_11PL) || (G2_5PL == 0) +#define MG2_11_15PL ~(1 << 4) +#else +#define MG2_11_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_11PL) || (G2_6PL == 0) +#define MG2_11_16PL ~(1 << 5) +#else +#define MG2_11_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_11PL) || (G2_7PL == 0) +#define MG2_11_17PL ~(1 << 6) +#else +#define MG2_11_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_11PL) || (G2_8PL == 0) +#define MG2_11_18PL ~(1 << 7) +#else +#define MG2_11_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_11PL) || (G2_9PL == 0) +#define MG2_11_19PL ~(1 << 8) +#else +#define MG2_11_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_11PL) || (G2_10PL == 0) +#define MG2_11_110PL ~(1 << 9) +#else +#define MG2_11_110PL 0xFFFF +#endif + +#if (G2_12PL >= G2_11PL) || (G2_12PL == 0) +#define MG2_11_112PL ~(1 << 11) +#else +#define MG2_11_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_11PL) || (G2_13PL == 0) +#define MG2_11_113PL ~(1 << 12) +#else +#define MG2_11_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_11PL) || (G2_14PL == 0) +#define MG2_11_114PL ~(1 << 13) +#else +#define MG2_11_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_11PL) || (G2_15PL == 0) +#define MG2_11_115PL ~(1 << 14) +#else +#define MG2_11_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_11PL) || (G2_16PL == 0) +#define MG2_11_116PL ~(1 << 15) +#else +#define MG2_11_116PL 0xFFFF +#endif + +#define MG2_11_111PL 0xFBFF +#define MG2_11 (MG2_11_11PL & MG2_11_12PL & MG2_11_13PL & MG2_11_14PL & \ + MG2_11_15PL & MG2_11_16PL & MG2_11_17PL & MG2_11_18PL & \ + MG2_11_19PL & MG2_11_110PL & MG2_11_111PL & MG2_11_112PL & \ + MG2_11_113PL & MG2_11_114PL & MG2_11_115PL & MG2_11_116PL) +// End of MG2_11: +// Beginning of MG212: +#if (G2_1PL >= G2_12PL) || (G2_1PL == 0) +#define MG2_12_11PL ~(1 << 0) +#else +#define MG2_12_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_12PL) || (G2_2PL == 0) +#define MG2_12_12PL ~(1 << 1) +#else +#define MG2_12_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_12PL) || (G2_3PL == 0) +#define MG2_12_13PL ~(1 << 2) +#else +#define MG2_12_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_12PL) || (G2_4PL == 0) +#define MG2_12_14PL ~(1 << 3) +#else +#define MG2_12_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_12PL) || (G2_5PL == 0) +#define MG2_12_15PL ~(1 << 4) +#else +#define MG2_12_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_12PL) || (G2_6PL == 0) +#define MG2_12_16PL ~(1 << 5) +#else +#define MG2_12_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_12PL) || (G2_7PL == 0) +#define MG2_12_17PL ~(1 << 6) +#else +#define MG2_12_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_12PL) || (G2_8PL == 0) +#define MG2_12_18PL ~(1 << 7) +#else +#define MG2_12_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_12PL) || (G2_9PL == 0) +#define MG2_12_19PL ~(1 << 8) +#else +#define MG2_12_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_12PL) || (G2_10PL == 0) +#define MG2_12_110PL ~(1 << 9) +#else +#define MG2_12_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_12PL) || (G2_11PL == 0) +#define MG2_12_111PL ~(1 << 10) +#else +#define MG2_12_111PL 0xFFFF +#endif + +#if (G2_13PL >= G2_12PL) || (G2_13PL == 0) +#define MG2_12_113PL ~(1 << 12) +#else +#define MG2_12_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_12PL) || (G2_14PL == 0) +#define MG2_12_114PL ~(1 << 13) +#else +#define MG2_12_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_12PL) || (G2_15PL == 0) +#define MG2_12_115PL ~(1 << 14) +#else +#define MG2_12_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_12PL) || (G2_16PL == 0) +#define MG2_12_116PL ~(1 << 15) +#else +#define MG2_12_116PL 0xFFFF +#endif + +#define MG2_12_112PL 0xF7FF +#define MG2_12 (MG2_12_11PL & MG2_12_12PL & MG2_12_13PL & MG2_12_14PL & \ + MG2_12_15PL & MG2_12_16PL & MG2_12_17PL & MG2_12_18PL & \ + MG2_12_19PL & MG2_12_110PL & MG2_12_111PL & MG2_12_112PL & \ + MG2_12_113PL & MG2_12_114PL & MG2_12_115PL & MG2_12_116PL) +// End of MG2_12: +// Beginning of MG213: +#if (G2_1PL >= G2_13PL) || (G2_1PL == 0) +#define MG2_13_11PL ~(1 << 0) +#else +#define MG2_13_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_13PL) || (G2_2PL == 0) +#define MG2_13_12PL ~(1 << 1) +#else +#define MG2_13_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_13PL) || (G2_3PL == 0) +#define MG2_13_13PL ~(1 << 2) +#else +#define MG2_13_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_13PL) || (G2_4PL == 0) +#define MG2_13_14PL ~(1 << 3) +#else +#define MG2_13_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_13PL) || (G2_5PL == 0) +#define MG2_13_15PL ~(1 << 4) +#else +#define MG2_13_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_13PL) || (G2_6PL == 0) +#define MG2_13_16PL ~(1 << 5) +#else +#define MG2_13_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_13PL) || (G2_7PL == 0) +#define MG2_13_17PL ~(1 << 6) +#else +#define MG2_13_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_13PL) || (G2_8PL == 0) +#define MG2_13_18PL ~(1 << 7) +#else +#define MG2_13_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_13PL) || (G2_9PL == 0) +#define MG2_13_19PL ~(1 << 8) +#else +#define MG2_13_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_13PL) || (G2_10PL == 0) +#define MG2_13_110PL ~(1 << 9) +#else +#define MG2_13_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_13PL) || (G2_11PL == 0) +#define MG2_13_111PL ~(1 << 10) +#else +#define MG2_13_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_13PL) || (G2_12PL == 0) +#define MG2_13_112PL ~(1 << 11) +#else +#define MG2_13_112PL 0xFFFF +#endif + +#if (G2_14PL >= G2_13PL) || (G2_14PL == 0) +#define MG2_13_114PL ~(1 << 13) +#else +#define MG2_13_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_13PL) || (G2_15PL == 0) +#define MG2_13_115PL ~(1 << 14) +#else +#define MG2_13_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_13PL) || (G2_16PL == 0) +#define MG2_13_116PL ~(1 << 15) +#else +#define MG2_13_116PL 0xFFFF +#endif + +#define MG2_13_113PL 0xEFFF +#define MG2_13 (MG2_13_11PL & MG2_13_12PL & MG2_13_13PL & MG2_13_14PL & \ + MG2_13_15PL & MG2_13_16PL & MG2_13_17PL & MG2_13_18PL & \ + MG2_13_19PL & MG2_13_110PL & MG2_13_111PL & MG2_13_112PL & \ + MG2_13_113PL & MG2_13_114PL & MG2_13_115PL & MG2_13_116PL) +// End of MG2_13: +// Beginning of MG214: +#if (G2_1PL >= G2_14PL) || (G2_1PL == 0) +#define MG2_14_11PL ~(1 << 0) +#else +#define MG2_14_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_14PL) || (G2_2PL == 0) +#define MG2_14_12PL ~(1 << 1) +#else +#define MG2_14_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_14PL) || (G2_3PL == 0) +#define MG2_14_13PL ~(1 << 2) +#else +#define MG2_14_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_14PL) || (G2_4PL == 0) +#define MG2_14_14PL ~(1 << 3) +#else +#define MG2_14_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_14PL) || (G2_5PL == 0) +#define MG2_14_15PL ~(1 << 4) +#else +#define MG2_14_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_14PL) || (G2_6PL == 0) +#define MG2_14_16PL ~(1 << 5) +#else +#define MG2_14_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_14PL) || (G2_7PL == 0) +#define MG2_14_17PL ~(1 << 6) +#else +#define MG2_14_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_14PL) || (G2_8PL == 0) +#define MG2_14_18PL ~(1 << 7) +#else +#define MG2_14_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_14PL) || (G2_9PL == 0) +#define MG2_14_19PL ~(1 << 8) +#else +#define MG2_14_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_14PL) || (G2_10PL == 0) +#define MG2_14_110PL ~(1 << 9) +#else +#define MG2_14_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_14PL) || (G2_11PL == 0) +#define MG2_14_111PL ~(1 << 10) +#else +#define MG2_14_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_14PL) || (G2_12PL == 0) +#define MG2_14_112PL ~(1 << 11) +#else +#define MG2_14_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_14PL) || (G2_13PL == 0) +#define MG2_14_113PL ~(1 << 12) +#else +#define MG2_14_113PL 0xFFFF +#endif + +#if (G2_15PL >= G2_14PL) || (G2_15PL == 0) +#define MG2_14_115PL ~(1 << 14) +#else +#define MG2_14_115PL 0xFFFF +#endif + +#if (G2_16PL >= G2_14PL) || (G2_16PL == 0) +#define MG2_14_116PL ~(1 << 15) +#else +#define MG2_14_116PL 0xFFFF +#endif + +#define MG2_14_114PL 0xDFFF +#define MG2_14 (MG2_14_11PL & MG2_14_12PL & MG2_14_13PL & MG2_14_14PL & \ + MG2_14_15PL & MG2_14_16PL & MG2_14_17PL & MG2_14_18PL & \ + MG2_14_19PL & MG2_14_110PL & MG2_14_111PL & MG2_14_112PL & \ + MG2_14_113PL & MG2_14_114PL & MG2_14_115PL & MG2_14_116PL) +// End of MG2_14: +// Beginning of MG215: +#if (G2_1PL >= G2_15PL) || (G2_1PL == 0) +#define MG2_15_11PL ~(1 << 0) +#else +#define MG2_15_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_15PL) || (G2_2PL == 0) +#define MG2_15_12PL ~(1 << 1) +#else +#define MG2_15_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_15PL) || (G2_3PL == 0) +#define MG2_15_13PL ~(1 << 2) +#else +#define MG2_15_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_15PL) || (G2_4PL == 0) +#define MG2_15_14PL ~(1 << 3) +#else +#define MG2_15_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_15PL) || (G2_5PL == 0) +#define MG2_15_15PL ~(1 << 4) +#else +#define MG2_15_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_15PL) || (G2_6PL == 0) +#define MG2_15_16PL ~(1 << 5) +#else +#define MG2_15_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_15PL) || (G2_7PL == 0) +#define MG2_15_17PL ~(1 << 6) +#else +#define MG2_15_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_15PL) || (G2_8PL == 0) +#define MG2_15_18PL ~(1 << 7) +#else +#define MG2_15_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_15PL) || (G2_9PL == 0) +#define MG2_15_19PL ~(1 << 8) +#else +#define MG2_15_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_15PL) || (G2_10PL == 0) +#define MG2_15_110PL ~(1 << 9) +#else +#define MG2_15_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_15PL) || (G2_11PL == 0) +#define MG2_15_111PL ~(1 << 10) +#else +#define MG2_15_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_15PL) || (G2_12PL == 0) +#define MG2_15_112PL ~(1 << 11) +#else +#define MG2_15_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_15PL) || (G2_13PL == 0) +#define MG2_15_113PL ~(1 << 12) +#else +#define MG2_15_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_15PL) || (G2_14PL == 0) +#define MG2_15_114PL ~(1 << 13) +#else +#define MG2_15_114PL 0xFFFF +#endif + +#if (G2_16PL >= G2_15PL) || (G2_16PL == 0) +#define MG2_15_116PL ~(1 << 15) +#else +#define MG2_15_116PL 0xFFFF +#endif + +#define MG2_15_115PL 0xBFFF +#define MG2_15 (MG2_15_11PL & MG2_15_12PL & MG2_15_13PL & MG2_15_14PL & \ + MG2_15_15PL & MG2_15_16PL & MG2_15_17PL & MG2_15_18PL & \ + MG2_15_19PL & MG2_15_110PL & MG2_15_111PL & MG2_15_112PL & \ + MG2_15_113PL & MG2_15_114PL & MG2_15_115PL & MG2_15_116PL) +// End of MG2_15: +// Beginning of MG216: +#if (G2_1PL >= G2_16PL) || (G2_1PL == 0) +#define MG2_16_11PL ~(1 << 0) +#else +#define MG2_16_11PL 0xFFFF +#endif + +#if (G2_2PL >= G2_16PL) || (G2_2PL == 0) +#define MG2_16_12PL ~(1 << 1) +#else +#define MG2_16_12PL 0xFFFF +#endif + +#if (G2_3PL >= G2_16PL) || (G2_3PL == 0) +#define MG2_16_13PL ~(1 << 2) +#else +#define MG2_16_13PL 0xFFFF +#endif + +#if (G2_4PL >= G2_16PL) || (G2_4PL == 0) +#define MG2_16_14PL ~(1 << 3) +#else +#define MG2_16_14PL 0xFFFF +#endif + +#if (G2_5PL >= G2_16PL) || (G2_5PL == 0) +#define MG2_16_15PL ~(1 << 4) +#else +#define MG2_16_15PL 0xFFFF +#endif + +#if (G2_6PL >= G2_16PL) || (G2_6PL == 0) +#define MG2_16_16PL ~(1 << 5) +#else +#define MG2_16_16PL 0xFFFF +#endif + +#if (G2_7PL >= G2_16PL) || (G2_7PL == 0) +#define MG2_16_17PL ~(1 << 6) +#else +#define MG2_16_17PL 0xFFFF +#endif + +#if (G2_8PL >= G2_16PL) || (G2_8PL == 0) +#define MG2_16_18PL ~(1 << 7) +#else +#define MG2_16_18PL 0xFFFF +#endif + +#if (G2_9PL >= G2_16PL) || (G2_9PL == 0) +#define MG2_16_19PL ~(1 << 8) +#else +#define MG2_16_19PL 0xFFFF +#endif + +#if (G2_10PL >= G2_16PL) || (G2_10PL == 0) +#define MG2_16_110PL ~(1 << 9) +#else +#define MG2_16_110PL 0xFFFF +#endif + +#if (G2_11PL >= G2_16PL) || (G2_11PL == 0) +#define MG2_16_111PL ~(1 << 10) +#else +#define MG2_16_111PL 0xFFFF +#endif + +#if (G2_12PL >= G2_16PL) || (G2_12PL == 0) +#define MG2_16_112PL ~(1 << 11) +#else +#define MG2_16_112PL 0xFFFF +#endif + +#if (G2_13PL >= G2_16PL) || (G2_13PL == 0) +#define MG2_16_113PL ~(1 << 12) +#else +#define MG2_16_113PL 0xFFFF +#endif + +#if (G2_14PL >= G2_16PL) || (G2_14PL == 0) +#define MG2_16_114PL ~(1 << 13) +#else +#define MG2_16_114PL 0xFFFF +#endif + +#if (G2_15PL >= G2_16PL) || (G2_15PL == 0) +#define MG2_16_115PL ~(1 << 14) +#else +#define MG2_16_115PL 0xFFFF +#endif + +#define MG2_16_116PL 0x7FFF +#define MG2_16 (MG2_16_11PL & MG2_16_12PL & MG2_16_13PL & MG2_16_14PL & \ + MG2_16_15PL & MG2_16_16PL & MG2_16_17PL & MG2_16_18PL & \ + MG2_16_19PL & MG2_16_110PL & MG2_16_111PL & MG2_16_112PL & \ + MG2_16_113PL & MG2_16_114PL & MG2_16_115PL & MG2_16_116PL) +// End of MG2_16: + + +// +// Automatically generate PIEIER3 interrupt masks MG31 to MG316: +// + +// Beginning of MG31: +#if (G3_2PL >= G3_1PL) || (G3_2PL == 0) +#define MG3_1_12PL ~(1 << 1) +#else +#define MG3_1_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_1PL) || (G3_3PL == 0) +#define MG3_1_13PL ~(1 << 2) +#else +#define MG3_1_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_1PL) || (G3_4PL == 0) +#define MG3_1_14PL ~(1 << 3) +#else +#define MG3_1_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_1PL) || (G3_5PL == 0) +#define MG3_1_15PL ~(1 << 4) +#else +#define MG3_1_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_1PL) || (G3_6PL == 0) +#define MG3_1_16PL ~(1 << 5) +#else +#define MG3_1_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_1PL) || (G3_7PL == 0) +#define MG3_1_17PL ~(1 << 6) +#else +#define MG3_1_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_1PL) || (G3_8PL == 0) +#define MG3_1_18PL ~(1 << 7) +#else +#define MG3_1_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_1PL) || (G3_9PL == 0) +#define MG3_1_19PL ~(1 << 8) +#else +#define MG3_1_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_1PL) || (G3_10PL == 0) +#define MG3_1_110PL ~(1 << 9) +#else +#define MG3_1_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_1PL) || (G3_11PL == 0) +#define MG3_1_111PL ~(1 << 10) +#else +#define MG3_1_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_1PL) || (G3_12PL == 0) +#define MG3_1_112PL ~(1 << 11) +#else +#define MG3_1_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_1PL) || (G3_13PL == 0) +#define MG3_1_113PL ~(1 << 12) +#else +#define MG3_1_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_1PL) || (G3_14PL == 0) +#define MG3_1_114PL ~(1 << 13) +#else +#define MG3_1_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_1PL) || (G3_15PL == 0) +#define MG3_1_115PL ~(1 << 14) +#else +#define MG3_1_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_1PL) || (G3_16PL == 0) +#define MG3_1_116PL ~(1 << 15) +#else +#define MG3_1_116PL 0xFFFF +#endif + +#define MG3_1_11PL 0xFFFE +#define MG3_1 (MG3_1_11PL & MG3_1_12PL & MG3_1_13PL & MG3_1_14PL & \ + MG3_1_15PL & MG3_1_16PL & MG3_1_17PL & MG3_1_18PL & \ + MG3_1_19PL & MG3_1_110PL & MG3_1_111PL & MG3_1_112PL & \ + MG3_1_113PL & MG3_1_114PL & MG3_1_115PL & MG3_1_116PL) +// End of MG3_1: +// Beginning of MG32: +#if (G3_1PL >= G3_2PL) || (G3_1PL == 0) +#define MG3_2_11PL ~(1 << 0) +#else +#define MG3_2_11PL 0xFFFF +#endif + +#if (G3_3PL >= G3_2PL) || (G3_3PL == 0) +#define MG3_2_13PL ~(1 << 2) +#else +#define MG3_2_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_2PL) || (G3_4PL == 0) +#define MG3_2_14PL ~(1 << 3) +#else +#define MG3_2_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_2PL) || (G3_5PL == 0) +#define MG3_2_15PL ~(1 << 4) +#else +#define MG3_2_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_2PL) || (G3_6PL == 0) +#define MG3_2_16PL ~(1 << 5) +#else +#define MG3_2_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_2PL) || (G3_7PL == 0) +#define MG3_2_17PL ~(1 << 6) +#else +#define MG3_2_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_2PL) || (G3_8PL == 0) +#define MG3_2_18PL ~(1 << 7) +#else +#define MG3_2_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_2PL) || (G3_9PL == 0) +#define MG3_2_19PL ~(1 << 8) +#else +#define MG3_2_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_2PL) || (G3_10PL == 0) +#define MG3_2_110PL ~(1 << 9) +#else +#define MG3_2_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_2PL) || (G3_11PL == 0) +#define MG3_2_111PL ~(1 << 10) +#else +#define MG3_2_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_2PL) || (G3_12PL == 0) +#define MG3_2_112PL ~(1 << 11) +#else +#define MG3_2_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_2PL) || (G3_13PL == 0) +#define MG3_2_113PL ~(1 << 12) +#else +#define MG3_2_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_2PL) || (G3_14PL == 0) +#define MG3_2_114PL ~(1 << 13) +#else +#define MG3_2_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_2PL) || (G3_15PL == 0) +#define MG3_2_115PL ~(1 << 14) +#else +#define MG3_2_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_2PL) || (G3_16PL == 0) +#define MG3_2_116PL ~(1 << 15) +#else +#define MG3_2_116PL 0xFFFF +#endif + +#define MG3_2_12PL 0xFFFD +#define MG3_2 (MG3_2_11PL & MG3_2_12PL & MG3_2_13PL & MG3_2_14PL & \ + MG3_2_15PL & MG3_2_16PL & MG3_2_17PL & MG3_2_18PL & \ + MG3_2_19PL & MG3_2_110PL & MG3_2_111PL & MG3_2_112PL & \ + MG3_2_113PL & MG3_2_114PL & MG3_2_115PL & MG3_2_116PL) +// End of MG3_2: +// Beginning of MG33: +#if (G3_1PL >= G3_3PL) || (G3_1PL == 0) +#define MG3_3_11PL ~(1 << 0) +#else +#define MG3_3_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_3PL) || (G3_2PL == 0) +#define MG3_3_12PL ~(1 << 1) +#else +#define MG3_3_12PL 0xFFFF +#endif + +#if (G3_4PL >= G3_3PL) || (G3_4PL == 0) +#define MG3_3_14PL ~(1 << 3) +#else +#define MG3_3_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_3PL) || (G3_5PL == 0) +#define MG3_3_15PL ~(1 << 4) +#else +#define MG3_3_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_3PL) || (G3_6PL == 0) +#define MG3_3_16PL ~(1 << 5) +#else +#define MG3_3_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_3PL) || (G3_7PL == 0) +#define MG3_3_17PL ~(1 << 6) +#else +#define MG3_3_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_3PL) || (G3_8PL == 0) +#define MG3_3_18PL ~(1 << 7) +#else +#define MG3_3_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_3PL) || (G3_9PL == 0) +#define MG3_3_19PL ~(1 << 8) +#else +#define MG3_3_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_3PL) || (G3_10PL == 0) +#define MG3_3_110PL ~(1 << 9) +#else +#define MG3_3_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_3PL) || (G3_11PL == 0) +#define MG3_3_111PL ~(1 << 10) +#else +#define MG3_3_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_3PL) || (G3_12PL == 0) +#define MG3_3_112PL ~(1 << 11) +#else +#define MG3_3_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_3PL) || (G3_13PL == 0) +#define MG3_3_113PL ~(1 << 12) +#else +#define MG3_3_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_3PL) || (G3_14PL == 0) +#define MG3_3_114PL ~(1 << 13) +#else +#define MG3_3_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_3PL) || (G3_15PL == 0) +#define MG3_3_115PL ~(1 << 14) +#else +#define MG3_3_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_3PL) || (G3_16PL == 0) +#define MG3_3_116PL ~(1 << 15) +#else +#define MG3_3_116PL 0xFFFF +#endif + +#define MG3_3_13PL 0xFFFB +#define MG3_3 (MG3_3_11PL & MG3_3_12PL & MG3_3_13PL & MG3_3_14PL & \ + MG3_3_15PL & MG3_3_16PL & MG3_3_17PL & MG3_3_18PL & \ + MG3_3_19PL & MG3_3_110PL & MG3_3_111PL & MG3_3_112PL & \ + MG3_3_113PL & MG3_3_114PL & MG3_3_115PL & MG3_3_116PL) +// End of MG3_3: +// Beginning of MG34: +#if (G3_1PL >= G3_4PL) || (G3_1PL == 0) +#define MG3_4_11PL ~(1 << 0) +#else +#define MG3_4_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_4PL) || (G3_2PL == 0) +#define MG3_4_12PL ~(1 << 1) +#else +#define MG3_4_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_4PL) || (G3_3PL == 0) +#define MG3_4_13PL ~(1 << 2) +#else +#define MG3_4_13PL 0xFFFF +#endif + +#if (G3_5PL >= G3_4PL) || (G3_5PL == 0) +#define MG3_4_15PL ~(1 << 4) +#else +#define MG3_4_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_4PL) || (G3_6PL == 0) +#define MG3_4_16PL ~(1 << 5) +#else +#define MG3_4_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_4PL) || (G3_7PL == 0) +#define MG3_4_17PL ~(1 << 6) +#else +#define MG3_4_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_4PL) || (G3_8PL == 0) +#define MG3_4_18PL ~(1 << 7) +#else +#define MG3_4_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_4PL) || (G3_9PL == 0) +#define MG3_4_19PL ~(1 << 8) +#else +#define MG3_4_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_4PL) || (G3_10PL == 0) +#define MG3_4_110PL ~(1 << 9) +#else +#define MG3_4_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_4PL) || (G3_11PL == 0) +#define MG3_4_111PL ~(1 << 10) +#else +#define MG3_4_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_4PL) || (G3_12PL == 0) +#define MG3_4_112PL ~(1 << 11) +#else +#define MG3_4_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_4PL) || (G3_13PL == 0) +#define MG3_4_113PL ~(1 << 12) +#else +#define MG3_4_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_4PL) || (G3_14PL == 0) +#define MG3_4_114PL ~(1 << 13) +#else +#define MG3_4_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_4PL) || (G3_15PL == 0) +#define MG3_4_115PL ~(1 << 14) +#else +#define MG3_4_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_4PL) || (G3_16PL == 0) +#define MG3_4_116PL ~(1 << 15) +#else +#define MG3_4_116PL 0xFFFF +#endif + +#define MG3_4_14PL 0xFFF7 +#define MG3_4 (MG3_4_11PL & MG3_4_12PL & MG3_4_13PL & MG3_4_14PL & \ + MG3_4_15PL & MG3_4_16PL & MG3_4_17PL & MG3_4_18PL & \ + MG3_4_19PL & MG3_4_110PL & MG3_4_111PL & MG3_4_112PL & \ + MG3_4_113PL & MG3_4_114PL & MG3_4_115PL & MG3_4_116PL) +// End of MG3_4: +// Beginning of MG35: +#if (G3_1PL >= G3_5PL) || (G3_1PL == 0) +#define MG3_5_11PL ~(1 << 0) +#else +#define MG3_5_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_5PL) || (G3_2PL == 0) +#define MG3_5_12PL ~(1 << 1) +#else +#define MG3_5_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_5PL) || (G3_3PL == 0) +#define MG3_5_13PL ~(1 << 2) +#else +#define MG3_5_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_5PL) || (G3_4PL == 0) +#define MG3_5_14PL ~(1 << 3) +#else +#define MG3_5_14PL 0xFFFF +#endif + +#if (G3_6PL >= G3_5PL) || (G3_6PL == 0) +#define MG3_5_16PL ~(1 << 5) +#else +#define MG3_5_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_5PL) || (G3_7PL == 0) +#define MG3_5_17PL ~(1 << 6) +#else +#define MG3_5_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_5PL) || (G3_8PL == 0) +#define MG3_5_18PL ~(1 << 7) +#else +#define MG3_5_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_5PL) || (G3_9PL == 0) +#define MG3_5_19PL ~(1 << 8) +#else +#define MG3_5_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_5PL) || (G3_10PL == 0) +#define MG3_5_110PL ~(1 << 9) +#else +#define MG3_5_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_5PL) || (G3_11PL == 0) +#define MG3_5_111PL ~(1 << 10) +#else +#define MG3_5_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_5PL) || (G3_12PL == 0) +#define MG3_5_112PL ~(1 << 11) +#else +#define MG3_5_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_5PL) || (G3_13PL == 0) +#define MG3_5_113PL ~(1 << 12) +#else +#define MG3_5_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_5PL) || (G3_14PL == 0) +#define MG3_5_114PL ~(1 << 13) +#else +#define MG3_5_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_5PL) || (G3_15PL == 0) +#define MG3_5_115PL ~(1 << 14) +#else +#define MG3_5_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_5PL) || (G3_16PL == 0) +#define MG3_5_116PL ~(1 << 15) +#else +#define MG3_5_116PL 0xFFFF +#endif + +#define MG3_5_15PL 0xFFEF +#define MG3_5 (MG3_5_11PL & MG3_5_12PL & MG3_5_13PL & MG3_5_14PL & \ + MG3_5_15PL & MG3_5_16PL & MG3_5_17PL & MG3_5_18PL & \ + MG3_5_19PL & MG3_5_110PL & MG3_5_111PL & MG3_5_112PL & \ + MG3_5_113PL & MG3_5_114PL & MG3_5_115PL & MG3_5_116PL) +// End of MG3_5: +// Beginning of MG36: +#if (G3_1PL >= G3_6PL) || (G3_1PL == 0) +#define MG3_6_11PL ~(1 << 0) +#else +#define MG3_6_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_6PL) || (G3_2PL == 0) +#define MG3_6_12PL ~(1 << 1) +#else +#define MG3_6_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_6PL) || (G3_3PL == 0) +#define MG3_6_13PL ~(1 << 2) +#else +#define MG3_6_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_6PL) || (G3_4PL == 0) +#define MG3_6_14PL ~(1 << 3) +#else +#define MG3_6_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_6PL) || (G3_5PL == 0) +#define MG3_6_15PL ~(1 << 4) +#else +#define MG3_6_15PL 0xFFFF +#endif + +#if (G3_7PL >= G3_6PL) || (G3_7PL == 0) +#define MG3_6_17PL ~(1 << 6) +#else +#define MG3_6_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_6PL) || (G3_8PL == 0) +#define MG3_6_18PL ~(1 << 7) +#else +#define MG3_6_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_6PL) || (G3_9PL == 0) +#define MG3_6_19PL ~(1 << 8) +#else +#define MG3_6_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_6PL) || (G3_10PL == 0) +#define MG3_6_110PL ~(1 << 9) +#else +#define MG3_6_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_6PL) || (G3_11PL == 0) +#define MG3_6_111PL ~(1 << 10) +#else +#define MG3_6_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_6PL) || (G3_12PL == 0) +#define MG3_6_112PL ~(1 << 11) +#else +#define MG3_6_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_6PL) || (G3_13PL == 0) +#define MG3_6_113PL ~(1 << 12) +#else +#define MG3_6_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_6PL) || (G3_14PL == 0) +#define MG3_6_114PL ~(1 << 13) +#else +#define MG3_6_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_6PL) || (G3_15PL == 0) +#define MG3_6_115PL ~(1 << 14) +#else +#define MG3_6_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_6PL) || (G3_16PL == 0) +#define MG3_6_116PL ~(1 << 15) +#else +#define MG3_6_116PL 0xFFFF +#endif + +#define MG3_6_16PL 0xFFDF +#define MG3_6 (MG3_6_11PL & MG3_6_12PL & MG3_6_13PL & MG3_6_14PL & \ + MG3_6_15PL & MG3_6_16PL & MG3_6_17PL & MG3_6_18PL & \ + MG3_6_19PL & MG3_6_110PL & MG3_6_111PL & MG3_6_112PL & \ + MG3_6_113PL & MG3_6_114PL & MG3_6_115PL & MG3_6_116PL) +// End of MG3_6: +// Beginning of MG37: +#if (G3_1PL >= G3_7PL) || (G3_1PL == 0) +#define MG3_7_11PL ~(1 << 0) +#else +#define MG3_7_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_7PL) || (G3_2PL == 0) +#define MG3_7_12PL ~(1 << 1) +#else +#define MG3_7_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_7PL) || (G3_3PL == 0) +#define MG3_7_13PL ~(1 << 2) +#else +#define MG3_7_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_7PL) || (G3_4PL == 0) +#define MG3_7_14PL ~(1 << 3) +#else +#define MG3_7_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_7PL) || (G3_5PL == 0) +#define MG3_7_15PL ~(1 << 4) +#else +#define MG3_7_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_7PL) || (G3_6PL == 0) +#define MG3_7_16PL ~(1 << 5) +#else +#define MG3_7_16PL 0xFFFF +#endif + +#if (G3_8PL >= G3_7PL) || (G3_8PL == 0) +#define MG3_7_18PL ~(1 << 7) +#else +#define MG3_7_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_7PL) || (G3_9PL == 0) +#define MG3_7_19PL ~(1 << 8) +#else +#define MG3_7_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_7PL) || (G3_10PL == 0) +#define MG3_7_110PL ~(1 << 9) +#else +#define MG3_7_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_7PL) || (G3_11PL == 0) +#define MG3_7_111PL ~(1 << 10) +#else +#define MG3_7_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_7PL) || (G3_12PL == 0) +#define MG3_7_112PL ~(1 << 11) +#else +#define MG3_7_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_7PL) || (G3_13PL == 0) +#define MG3_7_113PL ~(1 << 12) +#else +#define MG3_7_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_7PL) || (G3_14PL == 0) +#define MG3_7_114PL ~(1 << 13) +#else +#define MG3_7_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_7PL) || (G3_15PL == 0) +#define MG3_7_115PL ~(1 << 14) +#else +#define MG3_7_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_7PL) || (G3_16PL == 0) +#define MG3_7_116PL ~(1 << 15) +#else +#define MG3_7_116PL 0xFFFF +#endif + +#define MG3_7_17PL 0xFFBF +#define MG3_7 (MG3_7_11PL & MG3_7_12PL & MG3_7_13PL & MG3_7_14PL & \ + MG3_7_15PL & MG3_7_16PL & MG3_7_17PL & MG3_7_18PL & \ + MG3_7_19PL & MG3_7_110PL & MG3_7_111PL & MG3_7_112PL & \ + MG3_7_113PL & MG3_7_114PL & MG3_7_115PL & MG3_7_116PL) +// End of MG3_7: +// Beginning of MG38: +#if (G3_1PL >= G3_8PL) || (G3_1PL == 0) +#define MG3_8_11PL ~(1 << 0) +#else +#define MG3_8_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_8PL) || (G3_2PL == 0) +#define MG3_8_12PL ~(1 << 1) +#else +#define MG3_8_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_8PL) || (G3_3PL == 0) +#define MG3_8_13PL ~(1 << 2) +#else +#define MG3_8_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_8PL) || (G3_4PL == 0) +#define MG3_8_14PL ~(1 << 3) +#else +#define MG3_8_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_8PL) || (G3_5PL == 0) +#define MG3_8_15PL ~(1 << 4) +#else +#define MG3_8_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_8PL) || (G3_6PL == 0) +#define MG3_8_16PL ~(1 << 5) +#else +#define MG3_8_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_8PL) || (G3_7PL == 0) +#define MG3_8_17PL ~(1 << 6) +#else +#define MG3_8_17PL 0xFFFF +#endif + +#if (G3_9PL >= G3_8PL) || (G3_9PL == 0) +#define MG3_8_19PL ~(1 << 8) +#else +#define MG3_8_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_8PL) || (G3_10PL == 0) +#define MG3_8_110PL ~(1 << 9) +#else +#define MG3_8_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_8PL) || (G3_11PL == 0) +#define MG3_8_111PL ~(1 << 10) +#else +#define MG3_8_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_8PL) || (G3_12PL == 0) +#define MG3_8_112PL ~(1 << 11) +#else +#define MG3_8_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_8PL) || (G3_13PL == 0) +#define MG3_8_113PL ~(1 << 12) +#else +#define MG3_8_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_8PL) || (G3_14PL == 0) +#define MG3_8_114PL ~(1 << 13) +#else +#define MG3_8_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_8PL) || (G3_15PL == 0) +#define MG3_8_115PL ~(1 << 14) +#else +#define MG3_8_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_8PL) || (G3_16PL == 0) +#define MG3_8_116PL ~(1 << 15) +#else +#define MG3_8_116PL 0xFFFF +#endif + +#define MG3_8_18PL 0xFF7F +#define MG3_8 (MG3_8_11PL & MG3_8_12PL & MG3_8_13PL & MG3_8_14PL & \ + MG3_8_15PL & MG3_8_16PL & MG3_8_17PL & MG3_8_18PL & \ + MG3_8_19PL & MG3_8_110PL & MG3_8_111PL & MG3_8_112PL & \ + MG3_8_113PL & MG3_8_114PL & MG3_8_115PL & MG3_8_116PL) +// End of MG3_8: +// Beginning of MG39: +#if (G3_1PL >= G3_9PL) || (G3_1PL == 0) +#define MG3_9_11PL ~(1 << 0) +#else +#define MG3_9_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_9PL) || (G3_2PL == 0) +#define MG3_9_12PL ~(1 << 1) +#else +#define MG3_9_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_9PL) || (G3_3PL == 0) +#define MG3_9_13PL ~(1 << 2) +#else +#define MG3_9_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_9PL) || (G3_4PL == 0) +#define MG3_9_14PL ~(1 << 3) +#else +#define MG3_9_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_9PL) || (G3_5PL == 0) +#define MG3_9_15PL ~(1 << 4) +#else +#define MG3_9_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_9PL) || (G3_6PL == 0) +#define MG3_9_16PL ~(1 << 5) +#else +#define MG3_9_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_9PL) || (G3_7PL == 0) +#define MG3_9_17PL ~(1 << 6) +#else +#define MG3_9_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_9PL) || (G3_8PL == 0) +#define MG3_9_18PL ~(1 << 7) +#else +#define MG3_9_18PL 0xFFFF +#endif + +#if (G3_10PL >= G3_9PL) || (G3_10PL == 0) +#define MG3_9_110PL ~(1 << 9) +#else +#define MG3_9_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_9PL) || (G3_11PL == 0) +#define MG3_9_111PL ~(1 << 10) +#else +#define MG3_9_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_9PL) || (G3_12PL == 0) +#define MG3_9_112PL ~(1 << 11) +#else +#define MG3_9_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_9PL) || (G3_13PL == 0) +#define MG3_9_113PL ~(1 << 12) +#else +#define MG3_9_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_9PL) || (G3_14PL == 0) +#define MG3_9_114PL ~(1 << 13) +#else +#define MG3_9_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_9PL) || (G3_15PL == 0) +#define MG3_9_115PL ~(1 << 14) +#else +#define MG3_9_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_9PL) || (G3_16PL == 0) +#define MG3_9_116PL ~(1 << 15) +#else +#define MG3_9_116PL 0xFFFF +#endif + +#define MG3_9_19PL 0xFEFF +#define MG3_9 (MG3_9_11PL & MG3_9_12PL & MG3_9_13PL & MG3_9_14PL & \ + MG3_9_15PL & MG3_9_16PL & MG3_9_17PL & MG3_9_18PL & \ + MG3_9_19PL & MG3_9_110PL & MG3_9_111PL & MG3_9_112PL & \ + MG3_9_113PL & MG3_9_114PL & MG3_9_115PL & MG3_9_116PL) +// End of MG3_9: +// Beginning of MG310: +#if (G3_1PL >= G3_10PL) || (G3_1PL == 0) +#define MG3_10_11PL ~(1 << 0) +#else +#define MG3_10_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_10PL) || (G3_2PL == 0) +#define MG3_10_12PL ~(1 << 1) +#else +#define MG3_10_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_10PL) || (G3_3PL == 0) +#define MG3_10_13PL ~(1 << 2) +#else +#define MG3_10_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_10PL) || (G3_4PL == 0) +#define MG3_10_14PL ~(1 << 3) +#else +#define MG3_10_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_10PL) || (G3_5PL == 0) +#define MG3_10_15PL ~(1 << 4) +#else +#define MG3_10_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_10PL) || (G3_6PL == 0) +#define MG3_10_16PL ~(1 << 5) +#else +#define MG3_10_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_10PL) || (G3_7PL == 0) +#define MG3_10_17PL ~(1 << 6) +#else +#define MG3_10_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_10PL) || (G3_8PL == 0) +#define MG3_10_18PL ~(1 << 7) +#else +#define MG3_10_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_10PL) || (G3_9PL == 0) +#define MG3_10_19PL ~(1 << 8) +#else +#define MG3_10_19PL 0xFFFF +#endif + +#if (G3_11PL >= G3_10PL) || (G3_11PL == 0) +#define MG3_10_111PL ~(1 << 10) +#else +#define MG3_10_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_10PL) || (G3_12PL == 0) +#define MG3_10_112PL ~(1 << 11) +#else +#define MG3_10_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_10PL) || (G3_13PL == 0) +#define MG3_10_113PL ~(1 << 12) +#else +#define MG3_10_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_10PL) || (G3_14PL == 0) +#define MG3_10_114PL ~(1 << 13) +#else +#define MG3_10_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_10PL) || (G3_15PL == 0) +#define MG3_10_115PL ~(1 << 14) +#else +#define MG3_10_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_10PL) || (G3_16PL == 0) +#define MG3_10_116PL ~(1 << 15) +#else +#define MG3_10_116PL 0xFFFF +#endif + +#define MG3_10_110PL 0xFDFF +#define MG3_10 (MG3_10_11PL & MG3_10_12PL & MG3_10_13PL & MG3_10_14PL & \ + MG3_10_15PL & MG3_10_16PL & MG3_10_17PL & MG3_10_18PL & \ + MG3_10_19PL & MG3_10_110PL & MG3_10_111PL & MG3_10_112PL & \ + MG3_10_113PL & MG3_10_114PL & MG3_10_115PL & MG3_10_116PL) +// End of MG3_10: +// Beginning of MG311: +#if (G3_1PL >= G3_11PL) || (G3_1PL == 0) +#define MG3_11_11PL ~(1 << 0) +#else +#define MG3_11_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_11PL) || (G3_2PL == 0) +#define MG3_11_12PL ~(1 << 1) +#else +#define MG3_11_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_11PL) || (G3_3PL == 0) +#define MG3_11_13PL ~(1 << 2) +#else +#define MG3_11_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_11PL) || (G3_4PL == 0) +#define MG3_11_14PL ~(1 << 3) +#else +#define MG3_11_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_11PL) || (G3_5PL == 0) +#define MG3_11_15PL ~(1 << 4) +#else +#define MG3_11_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_11PL) || (G3_6PL == 0) +#define MG3_11_16PL ~(1 << 5) +#else +#define MG3_11_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_11PL) || (G3_7PL == 0) +#define MG3_11_17PL ~(1 << 6) +#else +#define MG3_11_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_11PL) || (G3_8PL == 0) +#define MG3_11_18PL ~(1 << 7) +#else +#define MG3_11_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_11PL) || (G3_9PL == 0) +#define MG3_11_19PL ~(1 << 8) +#else +#define MG3_11_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_11PL) || (G3_10PL == 0) +#define MG3_11_110PL ~(1 << 9) +#else +#define MG3_11_110PL 0xFFFF +#endif + +#if (G3_12PL >= G3_11PL) || (G3_12PL == 0) +#define MG3_11_112PL ~(1 << 11) +#else +#define MG3_11_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_11PL) || (G3_13PL == 0) +#define MG3_11_113PL ~(1 << 12) +#else +#define MG3_11_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_11PL) || (G3_14PL == 0) +#define MG3_11_114PL ~(1 << 13) +#else +#define MG3_11_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_11PL) || (G3_15PL == 0) +#define MG3_11_115PL ~(1 << 14) +#else +#define MG3_11_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_11PL) || (G3_16PL == 0) +#define MG3_11_116PL ~(1 << 15) +#else +#define MG3_11_116PL 0xFFFF +#endif + +#define MG3_11_111PL 0xFBFF +#define MG3_11 (MG3_11_11PL & MG3_11_12PL & MG3_11_13PL & MG3_11_14PL & \ + MG3_11_15PL & MG3_11_16PL & MG3_11_17PL & MG3_11_18PL & \ + MG3_11_19PL & MG3_11_110PL & MG3_11_111PL & MG3_11_112PL & \ + MG3_11_113PL & MG3_11_114PL & MG3_11_115PL & MG3_11_116PL) +// End of MG3_11: +// Beginning of MG312: +#if (G3_1PL >= G3_12PL) || (G3_1PL == 0) +#define MG3_12_11PL ~(1 << 0) +#else +#define MG3_12_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_12PL) || (G3_2PL == 0) +#define MG3_12_12PL ~(1 << 1) +#else +#define MG3_12_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_12PL) || (G3_3PL == 0) +#define MG3_12_13PL ~(1 << 2) +#else +#define MG3_12_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_12PL) || (G3_4PL == 0) +#define MG3_12_14PL ~(1 << 3) +#else +#define MG3_12_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_12PL) || (G3_5PL == 0) +#define MG3_12_15PL ~(1 << 4) +#else +#define MG3_12_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_12PL) || (G3_6PL == 0) +#define MG3_12_16PL ~(1 << 5) +#else +#define MG3_12_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_12PL) || (G3_7PL == 0) +#define MG3_12_17PL ~(1 << 6) +#else +#define MG3_12_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_12PL) || (G3_8PL == 0) +#define MG3_12_18PL ~(1 << 7) +#else +#define MG3_12_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_12PL) || (G3_9PL == 0) +#define MG3_12_19PL ~(1 << 8) +#else +#define MG3_12_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_12PL) || (G3_10PL == 0) +#define MG3_12_110PL ~(1 << 9) +#else +#define MG3_12_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_12PL) || (G3_11PL == 0) +#define MG3_12_111PL ~(1 << 10) +#else +#define MG3_12_111PL 0xFFFF +#endif + +#if (G3_13PL >= G3_12PL) || (G3_13PL == 0) +#define MG3_12_113PL ~(1 << 12) +#else +#define MG3_12_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_12PL) || (G3_14PL == 0) +#define MG3_12_114PL ~(1 << 13) +#else +#define MG3_12_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_12PL) || (G3_15PL == 0) +#define MG3_12_115PL ~(1 << 14) +#else +#define MG3_12_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_12PL) || (G3_16PL == 0) +#define MG3_12_116PL ~(1 << 15) +#else +#define MG3_12_116PL 0xFFFF +#endif + +#define MG3_12_112PL 0xF7FF +#define MG3_12 (MG3_12_11PL & MG3_12_12PL & MG3_12_13PL & MG3_12_14PL & \ + MG3_12_15PL & MG3_12_16PL & MG3_12_17PL & MG3_12_18PL & \ + MG3_12_19PL & MG3_12_110PL & MG3_12_111PL & MG3_12_112PL & \ + MG3_12_113PL & MG3_12_114PL & MG3_12_115PL & MG3_12_116PL) +// End of MG3_12: +// Beginning of MG313: +#if (G3_1PL >= G3_13PL) || (G3_1PL == 0) +#define MG3_13_11PL ~(1 << 0) +#else +#define MG3_13_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_13PL) || (G3_2PL == 0) +#define MG3_13_12PL ~(1 << 1) +#else +#define MG3_13_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_13PL) || (G3_3PL == 0) +#define MG3_13_13PL ~(1 << 2) +#else +#define MG3_13_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_13PL) || (G3_4PL == 0) +#define MG3_13_14PL ~(1 << 3) +#else +#define MG3_13_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_13PL) || (G3_5PL == 0) +#define MG3_13_15PL ~(1 << 4) +#else +#define MG3_13_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_13PL) || (G3_6PL == 0) +#define MG3_13_16PL ~(1 << 5) +#else +#define MG3_13_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_13PL) || (G3_7PL == 0) +#define MG3_13_17PL ~(1 << 6) +#else +#define MG3_13_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_13PL) || (G3_8PL == 0) +#define MG3_13_18PL ~(1 << 7) +#else +#define MG3_13_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_13PL) || (G3_9PL == 0) +#define MG3_13_19PL ~(1 << 8) +#else +#define MG3_13_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_13PL) || (G3_10PL == 0) +#define MG3_13_110PL ~(1 << 9) +#else +#define MG3_13_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_13PL) || (G3_11PL == 0) +#define MG3_13_111PL ~(1 << 10) +#else +#define MG3_13_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_13PL) || (G3_12PL == 0) +#define MG3_13_112PL ~(1 << 11) +#else +#define MG3_13_112PL 0xFFFF +#endif + +#if (G3_14PL >= G3_13PL) || (G3_14PL == 0) +#define MG3_13_114PL ~(1 << 13) +#else +#define MG3_13_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_13PL) || (G3_15PL == 0) +#define MG3_13_115PL ~(1 << 14) +#else +#define MG3_13_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_13PL) || (G3_16PL == 0) +#define MG3_13_116PL ~(1 << 15) +#else +#define MG3_13_116PL 0xFFFF +#endif + +#define MG3_13_113PL 0xEFFF +#define MG3_13 (MG3_13_11PL & MG3_13_12PL & MG3_13_13PL & MG3_13_14PL & \ + MG3_13_15PL & MG3_13_16PL & MG3_13_17PL & MG3_13_18PL & \ + MG3_13_19PL & MG3_13_110PL & MG3_13_111PL & MG3_13_112PL & \ + MG3_13_113PL & MG3_13_114PL & MG3_13_115PL & MG3_13_116PL) +// End of MG3_13: +// Beginning of MG314: +#if (G3_1PL >= G3_14PL) || (G3_1PL == 0) +#define MG3_14_11PL ~(1 << 0) +#else +#define MG3_14_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_14PL) || (G3_2PL == 0) +#define MG3_14_12PL ~(1 << 1) +#else +#define MG3_14_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_14PL) || (G3_3PL == 0) +#define MG3_14_13PL ~(1 << 2) +#else +#define MG3_14_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_14PL) || (G3_4PL == 0) +#define MG3_14_14PL ~(1 << 3) +#else +#define MG3_14_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_14PL) || (G3_5PL == 0) +#define MG3_14_15PL ~(1 << 4) +#else +#define MG3_14_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_14PL) || (G3_6PL == 0) +#define MG3_14_16PL ~(1 << 5) +#else +#define MG3_14_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_14PL) || (G3_7PL == 0) +#define MG3_14_17PL ~(1 << 6) +#else +#define MG3_14_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_14PL) || (G3_8PL == 0) +#define MG3_14_18PL ~(1 << 7) +#else +#define MG3_14_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_14PL) || (G3_9PL == 0) +#define MG3_14_19PL ~(1 << 8) +#else +#define MG3_14_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_14PL) || (G3_10PL == 0) +#define MG3_14_110PL ~(1 << 9) +#else +#define MG3_14_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_14PL) || (G3_11PL == 0) +#define MG3_14_111PL ~(1 << 10) +#else +#define MG3_14_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_14PL) || (G3_12PL == 0) +#define MG3_14_112PL ~(1 << 11) +#else +#define MG3_14_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_14PL) || (G3_13PL == 0) +#define MG3_14_113PL ~(1 << 12) +#else +#define MG3_14_113PL 0xFFFF +#endif + +#if (G3_15PL >= G3_14PL) || (G3_15PL == 0) +#define MG3_14_115PL ~(1 << 14) +#else +#define MG3_14_115PL 0xFFFF +#endif + +#if (G3_16PL >= G3_14PL) || (G3_16PL == 0) +#define MG3_14_116PL ~(1 << 15) +#else +#define MG3_14_116PL 0xFFFF +#endif + +#define MG3_14_114PL 0xDFFF +#define MG3_14 (MG3_14_11PL & MG3_14_12PL & MG3_14_13PL & MG3_14_14PL & \ + MG3_14_15PL & MG3_14_16PL & MG3_14_17PL & MG3_14_18PL & \ + MG3_14_19PL & MG3_14_110PL & MG3_14_111PL & MG3_14_112PL & \ + MG3_14_113PL & MG3_14_114PL & MG3_14_115PL & MG3_14_116PL) +// End of MG3_14: +// Beginning of MG315: +#if (G3_1PL >= G3_15PL) || (G3_1PL == 0) +#define MG3_15_11PL ~(1 << 0) +#else +#define MG3_15_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_15PL) || (G3_2PL == 0) +#define MG3_15_12PL ~(1 << 1) +#else +#define MG3_15_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_15PL) || (G3_3PL == 0) +#define MG3_15_13PL ~(1 << 2) +#else +#define MG3_15_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_15PL) || (G3_4PL == 0) +#define MG3_15_14PL ~(1 << 3) +#else +#define MG3_15_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_15PL) || (G3_5PL == 0) +#define MG3_15_15PL ~(1 << 4) +#else +#define MG3_15_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_15PL) || (G3_6PL == 0) +#define MG3_15_16PL ~(1 << 5) +#else +#define MG3_15_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_15PL) || (G3_7PL == 0) +#define MG3_15_17PL ~(1 << 6) +#else +#define MG3_15_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_15PL) || (G3_8PL == 0) +#define MG3_15_18PL ~(1 << 7) +#else +#define MG3_15_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_15PL) || (G3_9PL == 0) +#define MG3_15_19PL ~(1 << 8) +#else +#define MG3_15_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_15PL) || (G3_10PL == 0) +#define MG3_15_110PL ~(1 << 9) +#else +#define MG3_15_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_15PL) || (G3_11PL == 0) +#define MG3_15_111PL ~(1 << 10) +#else +#define MG3_15_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_15PL) || (G3_12PL == 0) +#define MG3_15_112PL ~(1 << 11) +#else +#define MG3_15_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_15PL) || (G3_13PL == 0) +#define MG3_15_113PL ~(1 << 12) +#else +#define MG3_15_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_15PL) || (G3_14PL == 0) +#define MG3_15_114PL ~(1 << 13) +#else +#define MG3_15_114PL 0xFFFF +#endif + +#if (G3_16PL >= G3_15PL) || (G3_16PL == 0) +#define MG3_15_116PL ~(1 << 15) +#else +#define MG3_15_116PL 0xFFFF +#endif + +#define MG3_15_115PL 0xBFFF +#define MG3_15 (MG3_15_11PL & MG3_15_12PL & MG3_15_13PL & MG3_15_14PL & \ + MG3_15_15PL & MG3_15_16PL & MG3_15_17PL & MG3_15_18PL & \ + MG3_15_19PL & MG3_15_110PL & MG3_15_111PL & MG3_15_112PL & \ + MG3_15_113PL & MG3_15_114PL & MG3_15_115PL & MG3_15_116PL) +// End of MG3_15: +// Beginning of MG316: +#if (G3_1PL >= G3_16PL) || (G3_1PL == 0) +#define MG3_16_11PL ~(1 << 0) +#else +#define MG3_16_11PL 0xFFFF +#endif + +#if (G3_2PL >= G3_16PL) || (G3_2PL == 0) +#define MG3_16_12PL ~(1 << 1) +#else +#define MG3_16_12PL 0xFFFF +#endif + +#if (G3_3PL >= G3_16PL) || (G3_3PL == 0) +#define MG3_16_13PL ~(1 << 2) +#else +#define MG3_16_13PL 0xFFFF +#endif + +#if (G3_4PL >= G3_16PL) || (G3_4PL == 0) +#define MG3_16_14PL ~(1 << 3) +#else +#define MG3_16_14PL 0xFFFF +#endif + +#if (G3_5PL >= G3_16PL) || (G3_5PL == 0) +#define MG3_16_15PL ~(1 << 4) +#else +#define MG3_16_15PL 0xFFFF +#endif + +#if (G3_6PL >= G3_16PL) || (G3_6PL == 0) +#define MG3_16_16PL ~(1 << 5) +#else +#define MG3_16_16PL 0xFFFF +#endif + +#if (G3_7PL >= G3_16PL) || (G3_7PL == 0) +#define MG3_16_17PL ~(1 << 6) +#else +#define MG3_16_17PL 0xFFFF +#endif + +#if (G3_8PL >= G3_16PL) || (G3_8PL == 0) +#define MG3_16_18PL ~(1 << 7) +#else +#define MG3_16_18PL 0xFFFF +#endif + +#if (G3_9PL >= G3_16PL) || (G3_9PL == 0) +#define MG3_16_19PL ~(1 << 8) +#else +#define MG3_16_19PL 0xFFFF +#endif + +#if (G3_10PL >= G3_16PL) || (G3_10PL == 0) +#define MG3_16_110PL ~(1 << 9) +#else +#define MG3_16_110PL 0xFFFF +#endif + +#if (G3_11PL >= G3_16PL) || (G3_11PL == 0) +#define MG3_16_111PL ~(1 << 10) +#else +#define MG3_16_111PL 0xFFFF +#endif + +#if (G3_12PL >= G3_16PL) || (G3_12PL == 0) +#define MG3_16_112PL ~(1 << 11) +#else +#define MG3_16_112PL 0xFFFF +#endif + +#if (G3_13PL >= G3_16PL) || (G3_13PL == 0) +#define MG3_16_113PL ~(1 << 12) +#else +#define MG3_16_113PL 0xFFFF +#endif + +#if (G3_14PL >= G3_16PL) || (G3_14PL == 0) +#define MG3_16_114PL ~(1 << 13) +#else +#define MG3_16_114PL 0xFFFF +#endif + +#if (G3_15PL >= G3_16PL) || (G3_15PL == 0) +#define MG3_16_115PL ~(1 << 14) +#else +#define MG3_16_115PL 0xFFFF +#endif + +#define MG3_16_116PL 0x7FFF +#define MG3_16 (MG3_16_11PL & MG3_16_12PL & MG3_16_13PL & MG3_16_14PL & \ + MG3_16_15PL & MG3_16_16PL & MG3_16_17PL & MG3_16_18PL & \ + MG3_16_19PL & MG3_16_110PL & MG3_16_111PL & MG3_16_112PL & \ + MG3_16_113PL & MG3_16_114PL & MG3_16_115PL & MG3_16_116PL) +// End of MG3_16: + + +// +// Automatically generate PIEIER4 interrupt masks MG41 to MG416: +// + +// Beginning of MG41: +#if (G4_2PL >= G4_1PL) || (G4_2PL == 0) +#define MG4_1_12PL ~(1 << 1) +#else +#define MG4_1_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_1PL) || (G4_3PL == 0) +#define MG4_1_13PL ~(1 << 2) +#else +#define MG4_1_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_1PL) || (G4_4PL == 0) +#define MG4_1_14PL ~(1 << 3) +#else +#define MG4_1_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_1PL) || (G4_5PL == 0) +#define MG4_1_15PL ~(1 << 4) +#else +#define MG4_1_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_1PL) || (G4_6PL == 0) +#define MG4_1_16PL ~(1 << 5) +#else +#define MG4_1_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_1PL) || (G4_7PL == 0) +#define MG4_1_17PL ~(1 << 6) +#else +#define MG4_1_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_1PL) || (G4_8PL == 0) +#define MG4_1_18PL ~(1 << 7) +#else +#define MG4_1_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_1PL) || (G4_9PL == 0) +#define MG4_1_19PL ~(1 << 8) +#else +#define MG4_1_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_1PL) || (G4_10PL == 0) +#define MG4_1_110PL ~(1 << 9) +#else +#define MG4_1_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_1PL) || (G4_11PL == 0) +#define MG4_1_111PL ~(1 << 10) +#else +#define MG4_1_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_1PL) || (G4_12PL == 0) +#define MG4_1_112PL ~(1 << 11) +#else +#define MG4_1_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_1PL) || (G4_13PL == 0) +#define MG4_1_113PL ~(1 << 12) +#else +#define MG4_1_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_1PL) || (G4_14PL == 0) +#define MG4_1_114PL ~(1 << 13) +#else +#define MG4_1_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_1PL) || (G4_15PL == 0) +#define MG4_1_115PL ~(1 << 14) +#else +#define MG4_1_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_1PL) || (G4_16PL == 0) +#define MG4_1_116PL ~(1 << 15) +#else +#define MG4_1_116PL 0xFFFF +#endif + +#define MG4_1_11PL 0xFFFE +#define MG4_1 (MG4_1_11PL & MG4_1_12PL & MG4_1_13PL & MG4_1_14PL & \ + MG4_1_15PL & MG4_1_16PL & MG4_1_17PL & MG4_1_18PL & \ + MG4_1_19PL & MG4_1_110PL & MG4_1_111PL & MG4_1_112PL & \ + MG4_1_113PL & MG4_1_114PL & MG4_1_115PL & MG4_1_116PL) +// End of MG4_1: +// Beginning of MG42: +#if (G4_1PL >= G4_2PL) || (G4_1PL == 0) +#define MG4_2_11PL ~(1 << 0) +#else +#define MG4_2_11PL 0xFFFF +#endif + +#if (G4_3PL >= G4_2PL) || (G4_3PL == 0) +#define MG4_2_13PL ~(1 << 2) +#else +#define MG4_2_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_2PL) || (G4_4PL == 0) +#define MG4_2_14PL ~(1 << 3) +#else +#define MG4_2_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_2PL) || (G4_5PL == 0) +#define MG4_2_15PL ~(1 << 4) +#else +#define MG4_2_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_2PL) || (G4_6PL == 0) +#define MG4_2_16PL ~(1 << 5) +#else +#define MG4_2_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_2PL) || (G4_7PL == 0) +#define MG4_2_17PL ~(1 << 6) +#else +#define MG4_2_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_2PL) || (G4_8PL == 0) +#define MG4_2_18PL ~(1 << 7) +#else +#define MG4_2_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_2PL) || (G4_9PL == 0) +#define MG4_2_19PL ~(1 << 8) +#else +#define MG4_2_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_2PL) || (G4_10PL == 0) +#define MG4_2_110PL ~(1 << 9) +#else +#define MG4_2_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_2PL) || (G4_11PL == 0) +#define MG4_2_111PL ~(1 << 10) +#else +#define MG4_2_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_2PL) || (G4_12PL == 0) +#define MG4_2_112PL ~(1 << 11) +#else +#define MG4_2_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_2PL) || (G4_13PL == 0) +#define MG4_2_113PL ~(1 << 12) +#else +#define MG4_2_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_2PL) || (G4_14PL == 0) +#define MG4_2_114PL ~(1 << 13) +#else +#define MG4_2_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_2PL) || (G4_15PL == 0) +#define MG4_2_115PL ~(1 << 14) +#else +#define MG4_2_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_2PL) || (G4_16PL == 0) +#define MG4_2_116PL ~(1 << 15) +#else +#define MG4_2_116PL 0xFFFF +#endif + +#define MG4_2_12PL 0xFFFD +#define MG4_2 (MG4_2_11PL & MG4_2_12PL & MG4_2_13PL & MG4_2_14PL & \ + MG4_2_15PL & MG4_2_16PL & MG4_2_17PL & MG4_2_18PL & \ + MG4_2_19PL & MG4_2_110PL & MG4_2_111PL & MG4_2_112PL & \ + MG4_2_113PL & MG4_2_114PL & MG4_2_115PL & MG4_2_116PL) +// End of MG4_2: +// Beginning of MG43: +#if (G4_1PL >= G4_3PL) || (G4_1PL == 0) +#define MG4_3_11PL ~(1 << 0) +#else +#define MG4_3_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_3PL) || (G4_2PL == 0) +#define MG4_3_12PL ~(1 << 1) +#else +#define MG4_3_12PL 0xFFFF +#endif + +#if (G4_4PL >= G4_3PL) || (G4_4PL == 0) +#define MG4_3_14PL ~(1 << 3) +#else +#define MG4_3_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_3PL) || (G4_5PL == 0) +#define MG4_3_15PL ~(1 << 4) +#else +#define MG4_3_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_3PL) || (G4_6PL == 0) +#define MG4_3_16PL ~(1 << 5) +#else +#define MG4_3_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_3PL) || (G4_7PL == 0) +#define MG4_3_17PL ~(1 << 6) +#else +#define MG4_3_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_3PL) || (G4_8PL == 0) +#define MG4_3_18PL ~(1 << 7) +#else +#define MG4_3_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_3PL) || (G4_9PL == 0) +#define MG4_3_19PL ~(1 << 8) +#else +#define MG4_3_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_3PL) || (G4_10PL == 0) +#define MG4_3_110PL ~(1 << 9) +#else +#define MG4_3_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_3PL) || (G4_11PL == 0) +#define MG4_3_111PL ~(1 << 10) +#else +#define MG4_3_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_3PL) || (G4_12PL == 0) +#define MG4_3_112PL ~(1 << 11) +#else +#define MG4_3_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_3PL) || (G4_13PL == 0) +#define MG4_3_113PL ~(1 << 12) +#else +#define MG4_3_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_3PL) || (G4_14PL == 0) +#define MG4_3_114PL ~(1 << 13) +#else +#define MG4_3_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_3PL) || (G4_15PL == 0) +#define MG4_3_115PL ~(1 << 14) +#else +#define MG4_3_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_3PL) || (G4_16PL == 0) +#define MG4_3_116PL ~(1 << 15) +#else +#define MG4_3_116PL 0xFFFF +#endif + +#define MG4_3_13PL 0xFFFB +#define MG4_3 (MG4_3_11PL & MG4_3_12PL & MG4_3_13PL & MG4_3_14PL & \ + MG4_3_15PL & MG4_3_16PL & MG4_3_17PL & MG4_3_18PL & \ + MG4_3_19PL & MG4_3_110PL & MG4_3_111PL & MG4_3_112PL & \ + MG4_3_113PL & MG4_3_114PL & MG4_3_115PL & MG4_3_116PL) +// End of MG4_3: +// Beginning of MG44: +#if (G4_1PL >= G4_4PL) || (G4_1PL == 0) +#define MG4_4_11PL ~(1 << 0) +#else +#define MG4_4_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_4PL) || (G4_2PL == 0) +#define MG4_4_12PL ~(1 << 1) +#else +#define MG4_4_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_4PL) || (G4_3PL == 0) +#define MG4_4_13PL ~(1 << 2) +#else +#define MG4_4_13PL 0xFFFF +#endif + +#if (G4_5PL >= G4_4PL) || (G4_5PL == 0) +#define MG4_4_15PL ~(1 << 4) +#else +#define MG4_4_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_4PL) || (G4_6PL == 0) +#define MG4_4_16PL ~(1 << 5) +#else +#define MG4_4_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_4PL) || (G4_7PL == 0) +#define MG4_4_17PL ~(1 << 6) +#else +#define MG4_4_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_4PL) || (G4_8PL == 0) +#define MG4_4_18PL ~(1 << 7) +#else +#define MG4_4_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_4PL) || (G4_9PL == 0) +#define MG4_4_19PL ~(1 << 8) +#else +#define MG4_4_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_4PL) || (G4_10PL == 0) +#define MG4_4_110PL ~(1 << 9) +#else +#define MG4_4_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_4PL) || (G4_11PL == 0) +#define MG4_4_111PL ~(1 << 10) +#else +#define MG4_4_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_4PL) || (G4_12PL == 0) +#define MG4_4_112PL ~(1 << 11) +#else +#define MG4_4_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_4PL) || (G4_13PL == 0) +#define MG4_4_113PL ~(1 << 12) +#else +#define MG4_4_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_4PL) || (G4_14PL == 0) +#define MG4_4_114PL ~(1 << 13) +#else +#define MG4_4_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_4PL) || (G4_15PL == 0) +#define MG4_4_115PL ~(1 << 14) +#else +#define MG4_4_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_4PL) || (G4_16PL == 0) +#define MG4_4_116PL ~(1 << 15) +#else +#define MG4_4_116PL 0xFFFF +#endif + +#define MG4_4_14PL 0xFFF7 +#define MG4_4 (MG4_4_11PL & MG4_4_12PL & MG4_4_13PL & MG4_4_14PL & \ + MG4_4_15PL & MG4_4_16PL & MG4_4_17PL & MG4_4_18PL & \ + MG4_4_19PL & MG4_4_110PL & MG4_4_111PL & MG4_4_112PL & \ + MG4_4_113PL & MG4_4_114PL & MG4_4_115PL & MG4_4_116PL) +// End of MG4_4: +// Beginning of MG45: +#if (G4_1PL >= G4_5PL) || (G4_1PL == 0) +#define MG4_5_11PL ~(1 << 0) +#else +#define MG4_5_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_5PL) || (G4_2PL == 0) +#define MG4_5_12PL ~(1 << 1) +#else +#define MG4_5_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_5PL) || (G4_3PL == 0) +#define MG4_5_13PL ~(1 << 2) +#else +#define MG4_5_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_5PL) || (G4_4PL == 0) +#define MG4_5_14PL ~(1 << 3) +#else +#define MG4_5_14PL 0xFFFF +#endif + +#if (G4_6PL >= G4_5PL) || (G4_6PL == 0) +#define MG4_5_16PL ~(1 << 5) +#else +#define MG4_5_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_5PL) || (G4_7PL == 0) +#define MG4_5_17PL ~(1 << 6) +#else +#define MG4_5_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_5PL) || (G4_8PL == 0) +#define MG4_5_18PL ~(1 << 7) +#else +#define MG4_5_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_5PL) || (G4_9PL == 0) +#define MG4_5_19PL ~(1 << 8) +#else +#define MG4_5_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_5PL) || (G4_10PL == 0) +#define MG4_5_110PL ~(1 << 9) +#else +#define MG4_5_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_5PL) || (G4_11PL == 0) +#define MG4_5_111PL ~(1 << 10) +#else +#define MG4_5_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_5PL) || (G4_12PL == 0) +#define MG4_5_112PL ~(1 << 11) +#else +#define MG4_5_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_5PL) || (G4_13PL == 0) +#define MG4_5_113PL ~(1 << 12) +#else +#define MG4_5_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_5PL) || (G4_14PL == 0) +#define MG4_5_114PL ~(1 << 13) +#else +#define MG4_5_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_5PL) || (G4_15PL == 0) +#define MG4_5_115PL ~(1 << 14) +#else +#define MG4_5_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_5PL) || (G4_16PL == 0) +#define MG4_5_116PL ~(1 << 15) +#else +#define MG4_5_116PL 0xFFFF +#endif + +#define MG4_5_15PL 0xFFEF +#define MG4_5 (MG4_5_11PL & MG4_5_12PL & MG4_5_13PL & MG4_5_14PL & \ + MG4_5_15PL & MG4_5_16PL & MG4_5_17PL & MG4_5_18PL & \ + MG4_5_19PL & MG4_5_110PL & MG4_5_111PL & MG4_5_112PL & \ + MG4_5_113PL & MG4_5_114PL & MG4_5_115PL & MG4_5_116PL) +// End of MG4_5: +// Beginning of MG46: +#if (G4_1PL >= G4_6PL) || (G4_1PL == 0) +#define MG4_6_11PL ~(1 << 0) +#else +#define MG4_6_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_6PL) || (G4_2PL == 0) +#define MG4_6_12PL ~(1 << 1) +#else +#define MG4_6_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_6PL) || (G4_3PL == 0) +#define MG4_6_13PL ~(1 << 2) +#else +#define MG4_6_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_6PL) || (G4_4PL == 0) +#define MG4_6_14PL ~(1 << 3) +#else +#define MG4_6_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_6PL) || (G4_5PL == 0) +#define MG4_6_15PL ~(1 << 4) +#else +#define MG4_6_15PL 0xFFFF +#endif + +#if (G4_7PL >= G4_6PL) || (G4_7PL == 0) +#define MG4_6_17PL ~(1 << 6) +#else +#define MG4_6_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_6PL) || (G4_8PL == 0) +#define MG4_6_18PL ~(1 << 7) +#else +#define MG4_6_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_6PL) || (G4_9PL == 0) +#define MG4_6_19PL ~(1 << 8) +#else +#define MG4_6_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_6PL) || (G4_10PL == 0) +#define MG4_6_110PL ~(1 << 9) +#else +#define MG4_6_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_6PL) || (G4_11PL == 0) +#define MG4_6_111PL ~(1 << 10) +#else +#define MG4_6_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_6PL) || (G4_12PL == 0) +#define MG4_6_112PL ~(1 << 11) +#else +#define MG4_6_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_6PL) || (G4_13PL == 0) +#define MG4_6_113PL ~(1 << 12) +#else +#define MG4_6_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_6PL) || (G4_14PL == 0) +#define MG4_6_114PL ~(1 << 13) +#else +#define MG4_6_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_6PL) || (G4_15PL == 0) +#define MG4_6_115PL ~(1 << 14) +#else +#define MG4_6_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_6PL) || (G4_16PL == 0) +#define MG4_6_116PL ~(1 << 15) +#else +#define MG4_6_116PL 0xFFFF +#endif + +#define MG4_6_16PL 0xFFDF +#define MG4_6 (MG4_6_11PL & MG4_6_12PL & MG4_6_13PL & MG4_6_14PL & \ + MG4_6_15PL & MG4_6_16PL & MG4_6_17PL & MG4_6_18PL & \ + MG4_6_19PL & MG4_6_110PL & MG4_6_111PL & MG4_6_112PL & \ + MG4_6_113PL & MG4_6_114PL & MG4_6_115PL & MG4_6_116PL) +// End of MG4_6: +// Beginning of MG47: +#if (G4_1PL >= G4_7PL) || (G4_1PL == 0) +#define MG4_7_11PL ~(1 << 0) +#else +#define MG4_7_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_7PL) || (G4_2PL == 0) +#define MG4_7_12PL ~(1 << 1) +#else +#define MG4_7_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_7PL) || (G4_3PL == 0) +#define MG4_7_13PL ~(1 << 2) +#else +#define MG4_7_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_7PL) || (G4_4PL == 0) +#define MG4_7_14PL ~(1 << 3) +#else +#define MG4_7_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_7PL) || (G4_5PL == 0) +#define MG4_7_15PL ~(1 << 4) +#else +#define MG4_7_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_7PL) || (G4_6PL == 0) +#define MG4_7_16PL ~(1 << 5) +#else +#define MG4_7_16PL 0xFFFF +#endif + +#if (G4_8PL >= G4_7PL) || (G4_8PL == 0) +#define MG4_7_18PL ~(1 << 7) +#else +#define MG4_7_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_7PL) || (G4_9PL == 0) +#define MG4_7_19PL ~(1 << 8) +#else +#define MG4_7_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_7PL) || (G4_10PL == 0) +#define MG4_7_110PL ~(1 << 9) +#else +#define MG4_7_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_7PL) || (G4_11PL == 0) +#define MG4_7_111PL ~(1 << 10) +#else +#define MG4_7_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_7PL) || (G4_12PL == 0) +#define MG4_7_112PL ~(1 << 11) +#else +#define MG4_7_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_7PL) || (G4_13PL == 0) +#define MG4_7_113PL ~(1 << 12) +#else +#define MG4_7_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_7PL) || (G4_14PL == 0) +#define MG4_7_114PL ~(1 << 13) +#else +#define MG4_7_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_7PL) || (G4_15PL == 0) +#define MG4_7_115PL ~(1 << 14) +#else +#define MG4_7_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_7PL) || (G4_16PL == 0) +#define MG4_7_116PL ~(1 << 15) +#else +#define MG4_7_116PL 0xFFFF +#endif + +#define MG4_7_17PL 0xFFBF +#define MG4_7 (MG4_7_11PL & MG4_7_12PL & MG4_7_13PL & MG4_7_14PL & \ + MG4_7_15PL & MG4_7_16PL & MG4_7_17PL & MG4_7_18PL & \ + MG4_7_19PL & MG4_7_110PL & MG4_7_111PL & MG4_7_112PL & \ + MG4_7_113PL & MG4_7_114PL & MG4_7_115PL & MG4_7_116PL) +// End of MG4_7: +// Beginning of MG48: +#if (G4_1PL >= G4_8PL) || (G4_1PL == 0) +#define MG4_8_11PL ~(1 << 0) +#else +#define MG4_8_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_8PL) || (G4_2PL == 0) +#define MG4_8_12PL ~(1 << 1) +#else +#define MG4_8_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_8PL) || (G4_3PL == 0) +#define MG4_8_13PL ~(1 << 2) +#else +#define MG4_8_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_8PL) || (G4_4PL == 0) +#define MG4_8_14PL ~(1 << 3) +#else +#define MG4_8_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_8PL) || (G4_5PL == 0) +#define MG4_8_15PL ~(1 << 4) +#else +#define MG4_8_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_8PL) || (G4_6PL == 0) +#define MG4_8_16PL ~(1 << 5) +#else +#define MG4_8_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_8PL) || (G4_7PL == 0) +#define MG4_8_17PL ~(1 << 6) +#else +#define MG4_8_17PL 0xFFFF +#endif + +#if (G4_9PL >= G4_8PL) || (G4_9PL == 0) +#define MG4_8_19PL ~(1 << 8) +#else +#define MG4_8_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_8PL) || (G4_10PL == 0) +#define MG4_8_110PL ~(1 << 9) +#else +#define MG4_8_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_8PL) || (G4_11PL == 0) +#define MG4_8_111PL ~(1 << 10) +#else +#define MG4_8_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_8PL) || (G4_12PL == 0) +#define MG4_8_112PL ~(1 << 11) +#else +#define MG4_8_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_8PL) || (G4_13PL == 0) +#define MG4_8_113PL ~(1 << 12) +#else +#define MG4_8_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_8PL) || (G4_14PL == 0) +#define MG4_8_114PL ~(1 << 13) +#else +#define MG4_8_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_8PL) || (G4_15PL == 0) +#define MG4_8_115PL ~(1 << 14) +#else +#define MG4_8_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_8PL) || (G4_16PL == 0) +#define MG4_8_116PL ~(1 << 15) +#else +#define MG4_8_116PL 0xFFFF +#endif + +#define MG4_8_18PL 0xFF7F +#define MG4_8 (MG4_8_11PL & MG4_8_12PL & MG4_8_13PL & MG4_8_14PL & \ + MG4_8_15PL & MG4_8_16PL & MG4_8_17PL & MG4_8_18PL & \ + MG4_8_19PL & MG4_8_110PL & MG4_8_111PL & MG4_8_112PL & \ + MG4_8_113PL & MG4_8_114PL & MG4_8_115PL & MG4_8_116PL) +// End of MG4_8: +// Beginning of MG49: +#if (G4_1PL >= G4_9PL) || (G4_1PL == 0) +#define MG4_9_11PL ~(1 << 0) +#else +#define MG4_9_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_9PL) || (G4_2PL == 0) +#define MG4_9_12PL ~(1 << 1) +#else +#define MG4_9_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_9PL) || (G4_3PL == 0) +#define MG4_9_13PL ~(1 << 2) +#else +#define MG4_9_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_9PL) || (G4_4PL == 0) +#define MG4_9_14PL ~(1 << 3) +#else +#define MG4_9_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_9PL) || (G4_5PL == 0) +#define MG4_9_15PL ~(1 << 4) +#else +#define MG4_9_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_9PL) || (G4_6PL == 0) +#define MG4_9_16PL ~(1 << 5) +#else +#define MG4_9_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_9PL) || (G4_7PL == 0) +#define MG4_9_17PL ~(1 << 6) +#else +#define MG4_9_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_9PL) || (G4_8PL == 0) +#define MG4_9_18PL ~(1 << 7) +#else +#define MG4_9_18PL 0xFFFF +#endif + +#if (G4_10PL >= G4_9PL) || (G4_10PL == 0) +#define MG4_9_110PL ~(1 << 9) +#else +#define MG4_9_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_9PL) || (G4_11PL == 0) +#define MG4_9_111PL ~(1 << 10) +#else +#define MG4_9_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_9PL) || (G4_12PL == 0) +#define MG4_9_112PL ~(1 << 11) +#else +#define MG4_9_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_9PL) || (G4_13PL == 0) +#define MG4_9_113PL ~(1 << 12) +#else +#define MG4_9_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_9PL) || (G4_14PL == 0) +#define MG4_9_114PL ~(1 << 13) +#else +#define MG4_9_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_9PL) || (G4_15PL == 0) +#define MG4_9_115PL ~(1 << 14) +#else +#define MG4_9_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_9PL) || (G4_16PL == 0) +#define MG4_9_116PL ~(1 << 15) +#else +#define MG4_9_116PL 0xFFFF +#endif + +#define MG4_9_19PL 0xFEFF +#define MG4_9 (MG4_9_11PL & MG4_9_12PL & MG4_9_13PL & MG4_9_14PL & \ + MG4_9_15PL & MG4_9_16PL & MG4_9_17PL & MG4_9_18PL & \ + MG4_9_19PL & MG4_9_110PL & MG4_9_111PL & MG4_9_112PL & \ + MG4_9_113PL & MG4_9_114PL & MG4_9_115PL & MG4_9_116PL) +// End of MG4_9: +// Beginning of MG410: +#if (G4_1PL >= G4_10PL) || (G4_1PL == 0) +#define MG4_10_11PL ~(1 << 0) +#else +#define MG4_10_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_10PL) || (G4_2PL == 0) +#define MG4_10_12PL ~(1 << 1) +#else +#define MG4_10_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_10PL) || (G4_3PL == 0) +#define MG4_10_13PL ~(1 << 2) +#else +#define MG4_10_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_10PL) || (G4_4PL == 0) +#define MG4_10_14PL ~(1 << 3) +#else +#define MG4_10_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_10PL) || (G4_5PL == 0) +#define MG4_10_15PL ~(1 << 4) +#else +#define MG4_10_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_10PL) || (G4_6PL == 0) +#define MG4_10_16PL ~(1 << 5) +#else +#define MG4_10_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_10PL) || (G4_7PL == 0) +#define MG4_10_17PL ~(1 << 6) +#else +#define MG4_10_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_10PL) || (G4_8PL == 0) +#define MG4_10_18PL ~(1 << 7) +#else +#define MG4_10_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_10PL) || (G4_9PL == 0) +#define MG4_10_19PL ~(1 << 8) +#else +#define MG4_10_19PL 0xFFFF +#endif + +#if (G4_11PL >= G4_10PL) || (G4_11PL == 0) +#define MG4_10_111PL ~(1 << 10) +#else +#define MG4_10_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_10PL) || (G4_12PL == 0) +#define MG4_10_112PL ~(1 << 11) +#else +#define MG4_10_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_10PL) || (G4_13PL == 0) +#define MG4_10_113PL ~(1 << 12) +#else +#define MG4_10_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_10PL) || (G4_14PL == 0) +#define MG4_10_114PL ~(1 << 13) +#else +#define MG4_10_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_10PL) || (G4_15PL == 0) +#define MG4_10_115PL ~(1 << 14) +#else +#define MG4_10_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_10PL) || (G4_16PL == 0) +#define MG4_10_116PL ~(1 << 15) +#else +#define MG4_10_116PL 0xFFFF +#endif + +#define MG4_10_110PL 0xFDFF +#define MG4_10 (MG4_10_11PL & MG4_10_12PL & MG4_10_13PL & MG4_10_14PL & \ + MG4_10_15PL & MG4_10_16PL & MG4_10_17PL & MG4_10_18PL & \ + MG4_10_19PL & MG4_10_110PL & MG4_10_111PL & MG4_10_112PL & \ + MG4_10_113PL & MG4_10_114PL & MG4_10_115PL & MG4_10_116PL) +// End of MG4_10: +// Beginning of MG411: +#if (G4_1PL >= G4_11PL) || (G4_1PL == 0) +#define MG4_11_11PL ~(1 << 0) +#else +#define MG4_11_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_11PL) || (G4_2PL == 0) +#define MG4_11_12PL ~(1 << 1) +#else +#define MG4_11_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_11PL) || (G4_3PL == 0) +#define MG4_11_13PL ~(1 << 2) +#else +#define MG4_11_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_11PL) || (G4_4PL == 0) +#define MG4_11_14PL ~(1 << 3) +#else +#define MG4_11_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_11PL) || (G4_5PL == 0) +#define MG4_11_15PL ~(1 << 4) +#else +#define MG4_11_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_11PL) || (G4_6PL == 0) +#define MG4_11_16PL ~(1 << 5) +#else +#define MG4_11_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_11PL) || (G4_7PL == 0) +#define MG4_11_17PL ~(1 << 6) +#else +#define MG4_11_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_11PL) || (G4_8PL == 0) +#define MG4_11_18PL ~(1 << 7) +#else +#define MG4_11_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_11PL) || (G4_9PL == 0) +#define MG4_11_19PL ~(1 << 8) +#else +#define MG4_11_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_11PL) || (G4_10PL == 0) +#define MG4_11_110PL ~(1 << 9) +#else +#define MG4_11_110PL 0xFFFF +#endif + +#if (G4_12PL >= G4_11PL) || (G4_12PL == 0) +#define MG4_11_112PL ~(1 << 11) +#else +#define MG4_11_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_11PL) || (G4_13PL == 0) +#define MG4_11_113PL ~(1 << 12) +#else +#define MG4_11_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_11PL) || (G4_14PL == 0) +#define MG4_11_114PL ~(1 << 13) +#else +#define MG4_11_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_11PL) || (G4_15PL == 0) +#define MG4_11_115PL ~(1 << 14) +#else +#define MG4_11_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_11PL) || (G4_16PL == 0) +#define MG4_11_116PL ~(1 << 15) +#else +#define MG4_11_116PL 0xFFFF +#endif + +#define MG4_11_111PL 0xFBFF +#define MG4_11 (MG4_11_11PL & MG4_11_12PL & MG4_11_13PL & MG4_11_14PL & \ + MG4_11_15PL & MG4_11_16PL & MG4_11_17PL & MG4_11_18PL & \ + MG4_11_19PL & MG4_11_110PL & MG4_11_111PL & MG4_11_112PL & \ + MG4_11_113PL & MG4_11_114PL & MG4_11_115PL & MG4_11_116PL) +// End of MG4_11: +// Beginning of MG412: +#if (G4_1PL >= G4_12PL) || (G4_1PL == 0) +#define MG4_12_11PL ~(1 << 0) +#else +#define MG4_12_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_12PL) || (G4_2PL == 0) +#define MG4_12_12PL ~(1 << 1) +#else +#define MG4_12_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_12PL) || (G4_3PL == 0) +#define MG4_12_13PL ~(1 << 2) +#else +#define MG4_12_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_12PL) || (G4_4PL == 0) +#define MG4_12_14PL ~(1 << 3) +#else +#define MG4_12_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_12PL) || (G4_5PL == 0) +#define MG4_12_15PL ~(1 << 4) +#else +#define MG4_12_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_12PL) || (G4_6PL == 0) +#define MG4_12_16PL ~(1 << 5) +#else +#define MG4_12_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_12PL) || (G4_7PL == 0) +#define MG4_12_17PL ~(1 << 6) +#else +#define MG4_12_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_12PL) || (G4_8PL == 0) +#define MG4_12_18PL ~(1 << 7) +#else +#define MG4_12_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_12PL) || (G4_9PL == 0) +#define MG4_12_19PL ~(1 << 8) +#else +#define MG4_12_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_12PL) || (G4_10PL == 0) +#define MG4_12_110PL ~(1 << 9) +#else +#define MG4_12_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_12PL) || (G4_11PL == 0) +#define MG4_12_111PL ~(1 << 10) +#else +#define MG4_12_111PL 0xFFFF +#endif + +#if (G4_13PL >= G4_12PL) || (G4_13PL == 0) +#define MG4_12_113PL ~(1 << 12) +#else +#define MG4_12_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_12PL) || (G4_14PL == 0) +#define MG4_12_114PL ~(1 << 13) +#else +#define MG4_12_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_12PL) || (G4_15PL == 0) +#define MG4_12_115PL ~(1 << 14) +#else +#define MG4_12_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_12PL) || (G4_16PL == 0) +#define MG4_12_116PL ~(1 << 15) +#else +#define MG4_12_116PL 0xFFFF +#endif + +#define MG4_12_112PL 0xF7FF +#define MG4_12 (MG4_12_11PL & MG4_12_12PL & MG4_12_13PL & MG4_12_14PL & \ + MG4_12_15PL & MG4_12_16PL & MG4_12_17PL & MG4_12_18PL & \ + MG4_12_19PL & MG4_12_110PL & MG4_12_111PL & MG4_12_112PL & \ + MG4_12_113PL & MG4_12_114PL & MG4_12_115PL & MG4_12_116PL) +// End of MG4_12: +// Beginning of MG413: +#if (G4_1PL >= G4_13PL) || (G4_1PL == 0) +#define MG4_13_11PL ~(1 << 0) +#else +#define MG4_13_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_13PL) || (G4_2PL == 0) +#define MG4_13_12PL ~(1 << 1) +#else +#define MG4_13_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_13PL) || (G4_3PL == 0) +#define MG4_13_13PL ~(1 << 2) +#else +#define MG4_13_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_13PL) || (G4_4PL == 0) +#define MG4_13_14PL ~(1 << 3) +#else +#define MG4_13_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_13PL) || (G4_5PL == 0) +#define MG4_13_15PL ~(1 << 4) +#else +#define MG4_13_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_13PL) || (G4_6PL == 0) +#define MG4_13_16PL ~(1 << 5) +#else +#define MG4_13_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_13PL) || (G4_7PL == 0) +#define MG4_13_17PL ~(1 << 6) +#else +#define MG4_13_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_13PL) || (G4_8PL == 0) +#define MG4_13_18PL ~(1 << 7) +#else +#define MG4_13_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_13PL) || (G4_9PL == 0) +#define MG4_13_19PL ~(1 << 8) +#else +#define MG4_13_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_13PL) || (G4_10PL == 0) +#define MG4_13_110PL ~(1 << 9) +#else +#define MG4_13_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_13PL) || (G4_11PL == 0) +#define MG4_13_111PL ~(1 << 10) +#else +#define MG4_13_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_13PL) || (G4_12PL == 0) +#define MG4_13_112PL ~(1 << 11) +#else +#define MG4_13_112PL 0xFFFF +#endif + +#if (G4_14PL >= G4_13PL) || (G4_14PL == 0) +#define MG4_13_114PL ~(1 << 13) +#else +#define MG4_13_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_13PL) || (G4_15PL == 0) +#define MG4_13_115PL ~(1 << 14) +#else +#define MG4_13_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_13PL) || (G4_16PL == 0) +#define MG4_13_116PL ~(1 << 15) +#else +#define MG4_13_116PL 0xFFFF +#endif + +#define MG4_13_113PL 0xEFFF +#define MG4_13 (MG4_13_11PL & MG4_13_12PL & MG4_13_13PL & MG4_13_14PL & \ + MG4_13_15PL & MG4_13_16PL & MG4_13_17PL & MG4_13_18PL & \ + MG4_13_19PL & MG4_13_110PL & MG4_13_111PL & MG4_13_112PL & \ + MG4_13_113PL & MG4_13_114PL & MG4_13_115PL & MG4_13_116PL) +// End of MG4_13: +// Beginning of MG414: +#if (G4_1PL >= G4_14PL) || (G4_1PL == 0) +#define MG4_14_11PL ~(1 << 0) +#else +#define MG4_14_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_14PL) || (G4_2PL == 0) +#define MG4_14_12PL ~(1 << 1) +#else +#define MG4_14_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_14PL) || (G4_3PL == 0) +#define MG4_14_13PL ~(1 << 2) +#else +#define MG4_14_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_14PL) || (G4_4PL == 0) +#define MG4_14_14PL ~(1 << 3) +#else +#define MG4_14_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_14PL) || (G4_5PL == 0) +#define MG4_14_15PL ~(1 << 4) +#else +#define MG4_14_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_14PL) || (G4_6PL == 0) +#define MG4_14_16PL ~(1 << 5) +#else +#define MG4_14_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_14PL) || (G4_7PL == 0) +#define MG4_14_17PL ~(1 << 6) +#else +#define MG4_14_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_14PL) || (G4_8PL == 0) +#define MG4_14_18PL ~(1 << 7) +#else +#define MG4_14_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_14PL) || (G4_9PL == 0) +#define MG4_14_19PL ~(1 << 8) +#else +#define MG4_14_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_14PL) || (G4_10PL == 0) +#define MG4_14_110PL ~(1 << 9) +#else +#define MG4_14_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_14PL) || (G4_11PL == 0) +#define MG4_14_111PL ~(1 << 10) +#else +#define MG4_14_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_14PL) || (G4_12PL == 0) +#define MG4_14_112PL ~(1 << 11) +#else +#define MG4_14_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_14PL) || (G4_13PL == 0) +#define MG4_14_113PL ~(1 << 12) +#else +#define MG4_14_113PL 0xFFFF +#endif + +#if (G4_15PL >= G4_14PL) || (G4_15PL == 0) +#define MG4_14_115PL ~(1 << 14) +#else +#define MG4_14_115PL 0xFFFF +#endif + +#if (G4_16PL >= G4_14PL) || (G4_16PL == 0) +#define MG4_14_116PL ~(1 << 15) +#else +#define MG4_14_116PL 0xFFFF +#endif + +#define MG4_14_114PL 0xDFFF +#define MG4_14 (MG4_14_11PL & MG4_14_12PL & MG4_14_13PL & MG4_14_14PL & \ + MG4_14_15PL & MG4_14_16PL & MG4_14_17PL & MG4_14_18PL & \ + MG4_14_19PL & MG4_14_110PL & MG4_14_111PL & MG4_14_112PL & \ + MG4_14_113PL & MG4_14_114PL & MG4_14_115PL & MG4_14_116PL) +// End of MG4_14: +// Beginning of MG415: +#if (G4_1PL >= G4_15PL) || (G4_1PL == 0) +#define MG4_15_11PL ~(1 << 0) +#else +#define MG4_15_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_15PL) || (G4_2PL == 0) +#define MG4_15_12PL ~(1 << 1) +#else +#define MG4_15_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_15PL) || (G4_3PL == 0) +#define MG4_15_13PL ~(1 << 2) +#else +#define MG4_15_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_15PL) || (G4_4PL == 0) +#define MG4_15_14PL ~(1 << 3) +#else +#define MG4_15_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_15PL) || (G4_5PL == 0) +#define MG4_15_15PL ~(1 << 4) +#else +#define MG4_15_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_15PL) || (G4_6PL == 0) +#define MG4_15_16PL ~(1 << 5) +#else +#define MG4_15_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_15PL) || (G4_7PL == 0) +#define MG4_15_17PL ~(1 << 6) +#else +#define MG4_15_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_15PL) || (G4_8PL == 0) +#define MG4_15_18PL ~(1 << 7) +#else +#define MG4_15_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_15PL) || (G4_9PL == 0) +#define MG4_15_19PL ~(1 << 8) +#else +#define MG4_15_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_15PL) || (G4_10PL == 0) +#define MG4_15_110PL ~(1 << 9) +#else +#define MG4_15_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_15PL) || (G4_11PL == 0) +#define MG4_15_111PL ~(1 << 10) +#else +#define MG4_15_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_15PL) || (G4_12PL == 0) +#define MG4_15_112PL ~(1 << 11) +#else +#define MG4_15_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_15PL) || (G4_13PL == 0) +#define MG4_15_113PL ~(1 << 12) +#else +#define MG4_15_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_15PL) || (G4_14PL == 0) +#define MG4_15_114PL ~(1 << 13) +#else +#define MG4_15_114PL 0xFFFF +#endif + +#if (G4_16PL >= G4_15PL) || (G4_16PL == 0) +#define MG4_15_116PL ~(1 << 15) +#else +#define MG4_15_116PL 0xFFFF +#endif + +#define MG4_15_115PL 0xBFFF +#define MG4_15 (MG4_15_11PL & MG4_15_12PL & MG4_15_13PL & MG4_15_14PL & \ + MG4_15_15PL & MG4_15_16PL & MG4_15_17PL & MG4_15_18PL & \ + MG4_15_19PL & MG4_15_110PL & MG4_15_111PL & MG4_15_112PL & \ + MG4_15_113PL & MG4_15_114PL & MG4_15_115PL & MG4_15_116PL) +// End of MG4_15: +// Beginning of MG416: +#if (G4_1PL >= G4_16PL) || (G4_1PL == 0) +#define MG4_16_11PL ~(1 << 0) +#else +#define MG4_16_11PL 0xFFFF +#endif + +#if (G4_2PL >= G4_16PL) || (G4_2PL == 0) +#define MG4_16_12PL ~(1 << 1) +#else +#define MG4_16_12PL 0xFFFF +#endif + +#if (G4_3PL >= G4_16PL) || (G4_3PL == 0) +#define MG4_16_13PL ~(1 << 2) +#else +#define MG4_16_13PL 0xFFFF +#endif + +#if (G4_4PL >= G4_16PL) || (G4_4PL == 0) +#define MG4_16_14PL ~(1 << 3) +#else +#define MG4_16_14PL 0xFFFF +#endif + +#if (G4_5PL >= G4_16PL) || (G4_5PL == 0) +#define MG4_16_15PL ~(1 << 4) +#else +#define MG4_16_15PL 0xFFFF +#endif + +#if (G4_6PL >= G4_16PL) || (G4_6PL == 0) +#define MG4_16_16PL ~(1 << 5) +#else +#define MG4_16_16PL 0xFFFF +#endif + +#if (G4_7PL >= G4_16PL) || (G4_7PL == 0) +#define MG4_16_17PL ~(1 << 6) +#else +#define MG4_16_17PL 0xFFFF +#endif + +#if (G4_8PL >= G4_16PL) || (G4_8PL == 0) +#define MG4_16_18PL ~(1 << 7) +#else +#define MG4_16_18PL 0xFFFF +#endif + +#if (G4_9PL >= G4_16PL) || (G4_9PL == 0) +#define MG4_16_19PL ~(1 << 8) +#else +#define MG4_16_19PL 0xFFFF +#endif + +#if (G4_10PL >= G4_16PL) || (G4_10PL == 0) +#define MG4_16_110PL ~(1 << 9) +#else +#define MG4_16_110PL 0xFFFF +#endif + +#if (G4_11PL >= G4_16PL) || (G4_11PL == 0) +#define MG4_16_111PL ~(1 << 10) +#else +#define MG4_16_111PL 0xFFFF +#endif + +#if (G4_12PL >= G4_16PL) || (G4_12PL == 0) +#define MG4_16_112PL ~(1 << 11) +#else +#define MG4_16_112PL 0xFFFF +#endif + +#if (G4_13PL >= G4_16PL) || (G4_13PL == 0) +#define MG4_16_113PL ~(1 << 12) +#else +#define MG4_16_113PL 0xFFFF +#endif + +#if (G4_14PL >= G4_16PL) || (G4_14PL == 0) +#define MG4_16_114PL ~(1 << 13) +#else +#define MG4_16_114PL 0xFFFF +#endif + +#if (G4_15PL >= G4_16PL) || (G4_15PL == 0) +#define MG4_16_115PL ~(1 << 14) +#else +#define MG4_16_115PL 0xFFFF +#endif + +#define MG4_16_116PL 0x7FFF +#define MG4_16 (MG4_16_11PL & MG4_16_12PL & MG4_16_13PL & MG4_16_14PL & \ + MG4_16_15PL & MG4_16_16PL & MG4_16_17PL & MG4_16_18PL & \ + MG4_16_19PL & MG4_16_110PL & MG4_16_111PL & MG4_16_112PL & \ + MG4_16_113PL & MG4_16_114PL & MG4_16_115PL & MG4_16_116PL) +// End of MG4_16: + + +// +// Automatically generate PIEIER5 interrupt masks MG51 to MG516: +// + +// Beginning of MG51: +#if (G5_2PL >= G5_1PL) || (G5_2PL == 0) +#define MG5_1_12PL ~(1 << 1) +#else +#define MG5_1_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_1PL) || (G5_3PL == 0) +#define MG5_1_13PL ~(1 << 2) +#else +#define MG5_1_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_1PL) || (G5_4PL == 0) +#define MG5_1_14PL ~(1 << 3) +#else +#define MG5_1_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_1PL) || (G5_5PL == 0) +#define MG5_1_15PL ~(1 << 4) +#else +#define MG5_1_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_1PL) || (G5_6PL == 0) +#define MG5_1_16PL ~(1 << 5) +#else +#define MG5_1_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_1PL) || (G5_7PL == 0) +#define MG5_1_17PL ~(1 << 6) +#else +#define MG5_1_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_1PL) || (G5_8PL == 0) +#define MG5_1_18PL ~(1 << 7) +#else +#define MG5_1_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_1PL) || (G5_9PL == 0) +#define MG5_1_19PL ~(1 << 8) +#else +#define MG5_1_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_1PL) || (G5_10PL == 0) +#define MG5_1_110PL ~(1 << 9) +#else +#define MG5_1_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_1PL) || (G5_11PL == 0) +#define MG5_1_111PL ~(1 << 10) +#else +#define MG5_1_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_1PL) || (G5_12PL == 0) +#define MG5_1_112PL ~(1 << 11) +#else +#define MG5_1_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_1PL) || (G5_13PL == 0) +#define MG5_1_113PL ~(1 << 12) +#else +#define MG5_1_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_1PL) || (G5_14PL == 0) +#define MG5_1_114PL ~(1 << 13) +#else +#define MG5_1_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_1PL) || (G5_15PL == 0) +#define MG5_1_115PL ~(1 << 14) +#else +#define MG5_1_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_1PL) || (G5_16PL == 0) +#define MG5_1_116PL ~(1 << 15) +#else +#define MG5_1_116PL 0xFFFF +#endif + +#define MG5_1_11PL 0xFFFE +#define MG5_1 (MG5_1_11PL & MG5_1_12PL & MG5_1_13PL & MG5_1_14PL & \ + MG5_1_15PL & MG5_1_16PL & MG5_1_17PL & MG5_1_18PL & \ + MG5_1_19PL & MG5_1_110PL & MG5_1_111PL & MG5_1_112PL & \ + MG5_1_113PL & MG5_1_114PL & MG5_1_115PL & MG5_1_116PL) +// End of MG5_1: +// Beginning of MG52: +#if (G5_1PL >= G5_2PL) || (G5_1PL == 0) +#define MG5_2_11PL ~(1 << 0) +#else +#define MG5_2_11PL 0xFFFF +#endif + +#if (G5_3PL >= G5_2PL) || (G5_3PL == 0) +#define MG5_2_13PL ~(1 << 2) +#else +#define MG5_2_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_2PL) || (G5_4PL == 0) +#define MG5_2_14PL ~(1 << 3) +#else +#define MG5_2_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_2PL) || (G5_5PL == 0) +#define MG5_2_15PL ~(1 << 4) +#else +#define MG5_2_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_2PL) || (G5_6PL == 0) +#define MG5_2_16PL ~(1 << 5) +#else +#define MG5_2_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_2PL) || (G5_7PL == 0) +#define MG5_2_17PL ~(1 << 6) +#else +#define MG5_2_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_2PL) || (G5_8PL == 0) +#define MG5_2_18PL ~(1 << 7) +#else +#define MG5_2_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_2PL) || (G5_9PL == 0) +#define MG5_2_19PL ~(1 << 8) +#else +#define MG5_2_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_2PL) || (G5_10PL == 0) +#define MG5_2_110PL ~(1 << 9) +#else +#define MG5_2_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_2PL) || (G5_11PL == 0) +#define MG5_2_111PL ~(1 << 10) +#else +#define MG5_2_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_2PL) || (G5_12PL == 0) +#define MG5_2_112PL ~(1 << 11) +#else +#define MG5_2_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_2PL) || (G5_13PL == 0) +#define MG5_2_113PL ~(1 << 12) +#else +#define MG5_2_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_2PL) || (G5_14PL == 0) +#define MG5_2_114PL ~(1 << 13) +#else +#define MG5_2_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_2PL) || (G5_15PL == 0) +#define MG5_2_115PL ~(1 << 14) +#else +#define MG5_2_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_2PL) || (G5_16PL == 0) +#define MG5_2_116PL ~(1 << 15) +#else +#define MG5_2_116PL 0xFFFF +#endif + +#define MG5_2_12PL 0xFFFD +#define MG5_2 (MG5_2_11PL & MG5_2_12PL & MG5_2_13PL & MG5_2_14PL & \ + MG5_2_15PL & MG5_2_16PL & MG5_2_17PL & MG5_2_18PL & \ + MG5_2_19PL & MG5_2_110PL & MG5_2_111PL & MG5_2_112PL & \ + MG5_2_113PL & MG5_2_114PL & MG5_2_115PL & MG5_2_116PL) +// End of MG5_2: +// Beginning of MG53: +#if (G5_1PL >= G5_3PL) || (G5_1PL == 0) +#define MG5_3_11PL ~(1 << 0) +#else +#define MG5_3_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_3PL) || (G5_2PL == 0) +#define MG5_3_12PL ~(1 << 1) +#else +#define MG5_3_12PL 0xFFFF +#endif + +#if (G5_4PL >= G5_3PL) || (G5_4PL == 0) +#define MG5_3_14PL ~(1 << 3) +#else +#define MG5_3_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_3PL) || (G5_5PL == 0) +#define MG5_3_15PL ~(1 << 4) +#else +#define MG5_3_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_3PL) || (G5_6PL == 0) +#define MG5_3_16PL ~(1 << 5) +#else +#define MG5_3_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_3PL) || (G5_7PL == 0) +#define MG5_3_17PL ~(1 << 6) +#else +#define MG5_3_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_3PL) || (G5_8PL == 0) +#define MG5_3_18PL ~(1 << 7) +#else +#define MG5_3_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_3PL) || (G5_9PL == 0) +#define MG5_3_19PL ~(1 << 8) +#else +#define MG5_3_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_3PL) || (G5_10PL == 0) +#define MG5_3_110PL ~(1 << 9) +#else +#define MG5_3_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_3PL) || (G5_11PL == 0) +#define MG5_3_111PL ~(1 << 10) +#else +#define MG5_3_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_3PL) || (G5_12PL == 0) +#define MG5_3_112PL ~(1 << 11) +#else +#define MG5_3_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_3PL) || (G5_13PL == 0) +#define MG5_3_113PL ~(1 << 12) +#else +#define MG5_3_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_3PL) || (G5_14PL == 0) +#define MG5_3_114PL ~(1 << 13) +#else +#define MG5_3_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_3PL) || (G5_15PL == 0) +#define MG5_3_115PL ~(1 << 14) +#else +#define MG5_3_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_3PL) || (G5_16PL == 0) +#define MG5_3_116PL ~(1 << 15) +#else +#define MG5_3_116PL 0xFFFF +#endif + +#define MG5_3_13PL 0xFFFB +#define MG5_3 (MG5_3_11PL & MG5_3_12PL & MG5_3_13PL & MG5_3_14PL & \ + MG5_3_15PL & MG5_3_16PL & MG5_3_17PL & MG5_3_18PL & \ + MG5_3_19PL & MG5_3_110PL & MG5_3_111PL & MG5_3_112PL & \ + MG5_3_113PL & MG5_3_114PL & MG5_3_115PL & MG5_3_116PL) +// End of MG5_3: +// Beginning of MG54: +#if (G5_1PL >= G5_4PL) || (G5_1PL == 0) +#define MG5_4_11PL ~(1 << 0) +#else +#define MG5_4_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_4PL) || (G5_2PL == 0) +#define MG5_4_12PL ~(1 << 1) +#else +#define MG5_4_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_4PL) || (G5_3PL == 0) +#define MG5_4_13PL ~(1 << 2) +#else +#define MG5_4_13PL 0xFFFF +#endif + +#if (G5_5PL >= G5_4PL) || (G5_5PL == 0) +#define MG5_4_15PL ~(1 << 4) +#else +#define MG5_4_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_4PL) || (G5_6PL == 0) +#define MG5_4_16PL ~(1 << 5) +#else +#define MG5_4_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_4PL) || (G5_7PL == 0) +#define MG5_4_17PL ~(1 << 6) +#else +#define MG5_4_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_4PL) || (G5_8PL == 0) +#define MG5_4_18PL ~(1 << 7) +#else +#define MG5_4_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_4PL) || (G5_9PL == 0) +#define MG5_4_19PL ~(1 << 8) +#else +#define MG5_4_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_4PL) || (G5_10PL == 0) +#define MG5_4_110PL ~(1 << 9) +#else +#define MG5_4_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_4PL) || (G5_11PL == 0) +#define MG5_4_111PL ~(1 << 10) +#else +#define MG5_4_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_4PL) || (G5_12PL == 0) +#define MG5_4_112PL ~(1 << 11) +#else +#define MG5_4_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_4PL) || (G5_13PL == 0) +#define MG5_4_113PL ~(1 << 12) +#else +#define MG5_4_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_4PL) || (G5_14PL == 0) +#define MG5_4_114PL ~(1 << 13) +#else +#define MG5_4_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_4PL) || (G5_15PL == 0) +#define MG5_4_115PL ~(1 << 14) +#else +#define MG5_4_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_4PL) || (G5_16PL == 0) +#define MG5_4_116PL ~(1 << 15) +#else +#define MG5_4_116PL 0xFFFF +#endif + +#define MG5_4_14PL 0xFFF7 +#define MG5_4 (MG5_4_11PL & MG5_4_12PL & MG5_4_13PL & MG5_4_14PL & \ + MG5_4_15PL & MG5_4_16PL & MG5_4_17PL & MG5_4_18PL & \ + MG5_4_19PL & MG5_4_110PL & MG5_4_111PL & MG5_4_112PL & \ + MG5_4_113PL & MG5_4_114PL & MG5_4_115PL & MG5_4_116PL) +// End of MG5_4: +// Beginning of MG55: +#if (G5_1PL >= G5_5PL) || (G5_1PL == 0) +#define MG5_5_11PL ~(1 << 0) +#else +#define MG5_5_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_5PL) || (G5_2PL == 0) +#define MG5_5_12PL ~(1 << 1) +#else +#define MG5_5_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_5PL) || (G5_3PL == 0) +#define MG5_5_13PL ~(1 << 2) +#else +#define MG5_5_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_5PL) || (G5_4PL == 0) +#define MG5_5_14PL ~(1 << 3) +#else +#define MG5_5_14PL 0xFFFF +#endif + +#if (G5_6PL >= G5_5PL) || (G5_6PL == 0) +#define MG5_5_16PL ~(1 << 5) +#else +#define MG5_5_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_5PL) || (G5_7PL == 0) +#define MG5_5_17PL ~(1 << 6) +#else +#define MG5_5_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_5PL) || (G5_8PL == 0) +#define MG5_5_18PL ~(1 << 7) +#else +#define MG5_5_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_5PL) || (G5_9PL == 0) +#define MG5_5_19PL ~(1 << 8) +#else +#define MG5_5_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_5PL) || (G5_10PL == 0) +#define MG5_5_110PL ~(1 << 9) +#else +#define MG5_5_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_5PL) || (G5_11PL == 0) +#define MG5_5_111PL ~(1 << 10) +#else +#define MG5_5_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_5PL) || (G5_12PL == 0) +#define MG5_5_112PL ~(1 << 11) +#else +#define MG5_5_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_5PL) || (G5_13PL == 0) +#define MG5_5_113PL ~(1 << 12) +#else +#define MG5_5_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_5PL) || (G5_14PL == 0) +#define MG5_5_114PL ~(1 << 13) +#else +#define MG5_5_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_5PL) || (G5_15PL == 0) +#define MG5_5_115PL ~(1 << 14) +#else +#define MG5_5_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_5PL) || (G5_16PL == 0) +#define MG5_5_116PL ~(1 << 15) +#else +#define MG5_5_116PL 0xFFFF +#endif + +#define MG5_5_15PL 0xFFEF +#define MG5_5 (MG5_5_11PL & MG5_5_12PL & MG5_5_13PL & MG5_5_14PL & \ + MG5_5_15PL & MG5_5_16PL & MG5_5_17PL & MG5_5_18PL & \ + MG5_5_19PL & MG5_5_110PL & MG5_5_111PL & MG5_5_112PL & \ + MG5_5_113PL & MG5_5_114PL & MG5_5_115PL & MG5_5_116PL) +// End of MG5_5: +// Beginning of MG56: +#if (G5_1PL >= G5_6PL) || (G5_1PL == 0) +#define MG5_6_11PL ~(1 << 0) +#else +#define MG5_6_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_6PL) || (G5_2PL == 0) +#define MG5_6_12PL ~(1 << 1) +#else +#define MG5_6_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_6PL) || (G5_3PL == 0) +#define MG5_6_13PL ~(1 << 2) +#else +#define MG5_6_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_6PL) || (G5_4PL == 0) +#define MG5_6_14PL ~(1 << 3) +#else +#define MG5_6_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_6PL) || (G5_5PL == 0) +#define MG5_6_15PL ~(1 << 4) +#else +#define MG5_6_15PL 0xFFFF +#endif + +#if (G5_7PL >= G5_6PL) || (G5_7PL == 0) +#define MG5_6_17PL ~(1 << 6) +#else +#define MG5_6_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_6PL) || (G5_8PL == 0) +#define MG5_6_18PL ~(1 << 7) +#else +#define MG5_6_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_6PL) || (G5_9PL == 0) +#define MG5_6_19PL ~(1 << 8) +#else +#define MG5_6_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_6PL) || (G5_10PL == 0) +#define MG5_6_110PL ~(1 << 9) +#else +#define MG5_6_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_6PL) || (G5_11PL == 0) +#define MG5_6_111PL ~(1 << 10) +#else +#define MG5_6_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_6PL) || (G5_12PL == 0) +#define MG5_6_112PL ~(1 << 11) +#else +#define MG5_6_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_6PL) || (G5_13PL == 0) +#define MG5_6_113PL ~(1 << 12) +#else +#define MG5_6_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_6PL) || (G5_14PL == 0) +#define MG5_6_114PL ~(1 << 13) +#else +#define MG5_6_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_6PL) || (G5_15PL == 0) +#define MG5_6_115PL ~(1 << 14) +#else +#define MG5_6_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_6PL) || (G5_16PL == 0) +#define MG5_6_116PL ~(1 << 15) +#else +#define MG5_6_116PL 0xFFFF +#endif + +#define MG5_6_16PL 0xFFDF +#define MG5_6 (MG5_6_11PL & MG5_6_12PL & MG5_6_13PL & MG5_6_14PL & \ + MG5_6_15PL & MG5_6_16PL & MG5_6_17PL & MG5_6_18PL & \ + MG5_6_19PL & MG5_6_110PL & MG5_6_111PL & MG5_6_112PL & \ + MG5_6_113PL & MG5_6_114PL & MG5_6_115PL & MG5_6_116PL) +// End of MG5_6: +// Beginning of MG57: +#if (G5_1PL >= G5_7PL) || (G5_1PL == 0) +#define MG5_7_11PL ~(1 << 0) +#else +#define MG5_7_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_7PL) || (G5_2PL == 0) +#define MG5_7_12PL ~(1 << 1) +#else +#define MG5_7_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_7PL) || (G5_3PL == 0) +#define MG5_7_13PL ~(1 << 2) +#else +#define MG5_7_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_7PL) || (G5_4PL == 0) +#define MG5_7_14PL ~(1 << 3) +#else +#define MG5_7_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_7PL) || (G5_5PL == 0) +#define MG5_7_15PL ~(1 << 4) +#else +#define MG5_7_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_7PL) || (G5_6PL == 0) +#define MG5_7_16PL ~(1 << 5) +#else +#define MG5_7_16PL 0xFFFF +#endif + +#if (G5_8PL >= G5_7PL) || (G5_8PL == 0) +#define MG5_7_18PL ~(1 << 7) +#else +#define MG5_7_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_7PL) || (G5_9PL == 0) +#define MG5_7_19PL ~(1 << 8) +#else +#define MG5_7_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_7PL) || (G5_10PL == 0) +#define MG5_7_110PL ~(1 << 9) +#else +#define MG5_7_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_7PL) || (G5_11PL == 0) +#define MG5_7_111PL ~(1 << 10) +#else +#define MG5_7_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_7PL) || (G5_12PL == 0) +#define MG5_7_112PL ~(1 << 11) +#else +#define MG5_7_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_7PL) || (G5_13PL == 0) +#define MG5_7_113PL ~(1 << 12) +#else +#define MG5_7_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_7PL) || (G5_14PL == 0) +#define MG5_7_114PL ~(1 << 13) +#else +#define MG5_7_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_7PL) || (G5_15PL == 0) +#define MG5_7_115PL ~(1 << 14) +#else +#define MG5_7_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_7PL) || (G5_16PL == 0) +#define MG5_7_116PL ~(1 << 15) +#else +#define MG5_7_116PL 0xFFFF +#endif + +#define MG5_7_17PL 0xFFBF +#define MG5_7 (MG5_7_11PL & MG5_7_12PL & MG5_7_13PL & MG5_7_14PL & \ + MG5_7_15PL & MG5_7_16PL & MG5_7_17PL & MG5_7_18PL & \ + MG5_7_19PL & MG5_7_110PL & MG5_7_111PL & MG5_7_112PL & \ + MG5_7_113PL & MG5_7_114PL & MG5_7_115PL & MG5_7_116PL) +// End of MG5_7: +// Beginning of MG58: +#if (G5_1PL >= G5_8PL) || (G5_1PL == 0) +#define MG5_8_11PL ~(1 << 0) +#else +#define MG5_8_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_8PL) || (G5_2PL == 0) +#define MG5_8_12PL ~(1 << 1) +#else +#define MG5_8_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_8PL) || (G5_3PL == 0) +#define MG5_8_13PL ~(1 << 2) +#else +#define MG5_8_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_8PL) || (G5_4PL == 0) +#define MG5_8_14PL ~(1 << 3) +#else +#define MG5_8_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_8PL) || (G5_5PL == 0) +#define MG5_8_15PL ~(1 << 4) +#else +#define MG5_8_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_8PL) || (G5_6PL == 0) +#define MG5_8_16PL ~(1 << 5) +#else +#define MG5_8_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_8PL) || (G5_7PL == 0) +#define MG5_8_17PL ~(1 << 6) +#else +#define MG5_8_17PL 0xFFFF +#endif + +#if (G5_9PL >= G5_8PL) || (G5_9PL == 0) +#define MG5_8_19PL ~(1 << 8) +#else +#define MG5_8_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_8PL) || (G5_10PL == 0) +#define MG5_8_110PL ~(1 << 9) +#else +#define MG5_8_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_8PL) || (G5_11PL == 0) +#define MG5_8_111PL ~(1 << 10) +#else +#define MG5_8_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_8PL) || (G5_12PL == 0) +#define MG5_8_112PL ~(1 << 11) +#else +#define MG5_8_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_8PL) || (G5_13PL == 0) +#define MG5_8_113PL ~(1 << 12) +#else +#define MG5_8_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_8PL) || (G5_14PL == 0) +#define MG5_8_114PL ~(1 << 13) +#else +#define MG5_8_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_8PL) || (G5_15PL == 0) +#define MG5_8_115PL ~(1 << 14) +#else +#define MG5_8_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_8PL) || (G5_16PL == 0) +#define MG5_8_116PL ~(1 << 15) +#else +#define MG5_8_116PL 0xFFFF +#endif + +#define MG5_8_18PL 0xFF7F +#define MG5_8 (MG5_8_11PL & MG5_8_12PL & MG5_8_13PL & MG5_8_14PL & \ + MG5_8_15PL & MG5_8_16PL & MG5_8_17PL & MG5_8_18PL & \ + MG5_8_19PL & MG5_8_110PL & MG5_8_111PL & MG5_8_112PL & \ + MG5_8_113PL & MG5_8_114PL & MG5_8_115PL & MG5_8_116PL) +// End of MG5_8: +// Beginning of MG59: +#if (G5_1PL >= G5_9PL) || (G5_1PL == 0) +#define MG5_9_11PL ~(1 << 0) +#else +#define MG5_9_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_9PL) || (G5_2PL == 0) +#define MG5_9_12PL ~(1 << 1) +#else +#define MG5_9_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_9PL) || (G5_3PL == 0) +#define MG5_9_13PL ~(1 << 2) +#else +#define MG5_9_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_9PL) || (G5_4PL == 0) +#define MG5_9_14PL ~(1 << 3) +#else +#define MG5_9_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_9PL) || (G5_5PL == 0) +#define MG5_9_15PL ~(1 << 4) +#else +#define MG5_9_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_9PL) || (G5_6PL == 0) +#define MG5_9_16PL ~(1 << 5) +#else +#define MG5_9_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_9PL) || (G5_7PL == 0) +#define MG5_9_17PL ~(1 << 6) +#else +#define MG5_9_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_9PL) || (G5_8PL == 0) +#define MG5_9_18PL ~(1 << 7) +#else +#define MG5_9_18PL 0xFFFF +#endif + +#if (G5_10PL >= G5_9PL) || (G5_10PL == 0) +#define MG5_9_110PL ~(1 << 9) +#else +#define MG5_9_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_9PL) || (G5_11PL == 0) +#define MG5_9_111PL ~(1 << 10) +#else +#define MG5_9_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_9PL) || (G5_12PL == 0) +#define MG5_9_112PL ~(1 << 11) +#else +#define MG5_9_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_9PL) || (G5_13PL == 0) +#define MG5_9_113PL ~(1 << 12) +#else +#define MG5_9_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_9PL) || (G5_14PL == 0) +#define MG5_9_114PL ~(1 << 13) +#else +#define MG5_9_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_9PL) || (G5_15PL == 0) +#define MG5_9_115PL ~(1 << 14) +#else +#define MG5_9_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_9PL) || (G5_16PL == 0) +#define MG5_9_116PL ~(1 << 15) +#else +#define MG5_9_116PL 0xFFFF +#endif + +#define MG5_9_19PL 0xFEFF +#define MG5_9 (MG5_9_11PL & MG5_9_12PL & MG5_9_13PL & MG5_9_14PL & \ + MG5_9_15PL & MG5_9_16PL & MG5_9_17PL & MG5_9_18PL & \ + MG5_9_19PL & MG5_9_110PL & MG5_9_111PL & MG5_9_112PL & \ + MG5_9_113PL & MG5_9_114PL & MG5_9_115PL & MG5_9_116PL) +// End of MG5_9: +// Beginning of MG510: +#if (G5_1PL >= G5_10PL) || (G5_1PL == 0) +#define MG5_10_11PL ~(1 << 0) +#else +#define MG5_10_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_10PL) || (G5_2PL == 0) +#define MG5_10_12PL ~(1 << 1) +#else +#define MG5_10_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_10PL) || (G5_3PL == 0) +#define MG5_10_13PL ~(1 << 2) +#else +#define MG5_10_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_10PL) || (G5_4PL == 0) +#define MG5_10_14PL ~(1 << 3) +#else +#define MG5_10_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_10PL) || (G5_5PL == 0) +#define MG5_10_15PL ~(1 << 4) +#else +#define MG5_10_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_10PL) || (G5_6PL == 0) +#define MG5_10_16PL ~(1 << 5) +#else +#define MG5_10_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_10PL) || (G5_7PL == 0) +#define MG5_10_17PL ~(1 << 6) +#else +#define MG5_10_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_10PL) || (G5_8PL == 0) +#define MG5_10_18PL ~(1 << 7) +#else +#define MG5_10_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_10PL) || (G5_9PL == 0) +#define MG5_10_19PL ~(1 << 8) +#else +#define MG5_10_19PL 0xFFFF +#endif + +#if (G5_11PL >= G5_10PL) || (G5_11PL == 0) +#define MG5_10_111PL ~(1 << 10) +#else +#define MG5_10_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_10PL) || (G5_12PL == 0) +#define MG5_10_112PL ~(1 << 11) +#else +#define MG5_10_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_10PL) || (G5_13PL == 0) +#define MG5_10_113PL ~(1 << 12) +#else +#define MG5_10_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_10PL) || (G5_14PL == 0) +#define MG5_10_114PL ~(1 << 13) +#else +#define MG5_10_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_10PL) || (G5_15PL == 0) +#define MG5_10_115PL ~(1 << 14) +#else +#define MG5_10_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_10PL) || (G5_16PL == 0) +#define MG5_10_116PL ~(1 << 15) +#else +#define MG5_10_116PL 0xFFFF +#endif + +#define MG5_10_110PL 0xFDFF +#define MG5_10 (MG5_10_11PL & MG5_10_12PL & MG5_10_13PL & MG5_10_14PL & \ + MG5_10_15PL & MG5_10_16PL & MG5_10_17PL & MG5_10_18PL & \ + MG5_10_19PL & MG5_10_110PL & MG5_10_111PL & MG5_10_112PL & \ + MG5_10_113PL & MG5_10_114PL & MG5_10_115PL & MG5_10_116PL) +// End of MG5_10: +// Beginning of MG511: +#if (G5_1PL >= G5_11PL) || (G5_1PL == 0) +#define MG5_11_11PL ~(1 << 0) +#else +#define MG5_11_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_11PL) || (G5_2PL == 0) +#define MG5_11_12PL ~(1 << 1) +#else +#define MG5_11_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_11PL) || (G5_3PL == 0) +#define MG5_11_13PL ~(1 << 2) +#else +#define MG5_11_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_11PL) || (G5_4PL == 0) +#define MG5_11_14PL ~(1 << 3) +#else +#define MG5_11_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_11PL) || (G5_5PL == 0) +#define MG5_11_15PL ~(1 << 4) +#else +#define MG5_11_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_11PL) || (G5_6PL == 0) +#define MG5_11_16PL ~(1 << 5) +#else +#define MG5_11_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_11PL) || (G5_7PL == 0) +#define MG5_11_17PL ~(1 << 6) +#else +#define MG5_11_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_11PL) || (G5_8PL == 0) +#define MG5_11_18PL ~(1 << 7) +#else +#define MG5_11_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_11PL) || (G5_9PL == 0) +#define MG5_11_19PL ~(1 << 8) +#else +#define MG5_11_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_11PL) || (G5_10PL == 0) +#define MG5_11_110PL ~(1 << 9) +#else +#define MG5_11_110PL 0xFFFF +#endif + +#if (G5_12PL >= G5_11PL) || (G5_12PL == 0) +#define MG5_11_112PL ~(1 << 11) +#else +#define MG5_11_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_11PL) || (G5_13PL == 0) +#define MG5_11_113PL ~(1 << 12) +#else +#define MG5_11_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_11PL) || (G5_14PL == 0) +#define MG5_11_114PL ~(1 << 13) +#else +#define MG5_11_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_11PL) || (G5_15PL == 0) +#define MG5_11_115PL ~(1 << 14) +#else +#define MG5_11_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_11PL) || (G5_16PL == 0) +#define MG5_11_116PL ~(1 << 15) +#else +#define MG5_11_116PL 0xFFFF +#endif + +#define MG5_11_111PL 0xFBFF +#define MG5_11 (MG5_11_11PL & MG5_11_12PL & MG5_11_13PL & MG5_11_14PL & \ + MG5_11_15PL & MG5_11_16PL & MG5_11_17PL & MG5_11_18PL & \ + MG5_11_19PL & MG5_11_110PL & MG5_11_111PL & MG5_11_112PL & \ + MG5_11_113PL & MG5_11_114PL & MG5_11_115PL & MG5_11_116PL) +// End of MG5_11: +// Beginning of MG512: +#if (G5_1PL >= G5_12PL) || (G5_1PL == 0) +#define MG5_12_11PL ~(1 << 0) +#else +#define MG5_12_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_12PL) || (G5_2PL == 0) +#define MG5_12_12PL ~(1 << 1) +#else +#define MG5_12_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_12PL) || (G5_3PL == 0) +#define MG5_12_13PL ~(1 << 2) +#else +#define MG5_12_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_12PL) || (G5_4PL == 0) +#define MG5_12_14PL ~(1 << 3) +#else +#define MG5_12_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_12PL) || (G5_5PL == 0) +#define MG5_12_15PL ~(1 << 4) +#else +#define MG5_12_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_12PL) || (G5_6PL == 0) +#define MG5_12_16PL ~(1 << 5) +#else +#define MG5_12_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_12PL) || (G5_7PL == 0) +#define MG5_12_17PL ~(1 << 6) +#else +#define MG5_12_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_12PL) || (G5_8PL == 0) +#define MG5_12_18PL ~(1 << 7) +#else +#define MG5_12_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_12PL) || (G5_9PL == 0) +#define MG5_12_19PL ~(1 << 8) +#else +#define MG5_12_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_12PL) || (G5_10PL == 0) +#define MG5_12_110PL ~(1 << 9) +#else +#define MG5_12_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_12PL) || (G5_11PL == 0) +#define MG5_12_111PL ~(1 << 10) +#else +#define MG5_12_111PL 0xFFFF +#endif + +#if (G5_13PL >= G5_12PL) || (G5_13PL == 0) +#define MG5_12_113PL ~(1 << 12) +#else +#define MG5_12_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_12PL) || (G5_14PL == 0) +#define MG5_12_114PL ~(1 << 13) +#else +#define MG5_12_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_12PL) || (G5_15PL == 0) +#define MG5_12_115PL ~(1 << 14) +#else +#define MG5_12_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_12PL) || (G5_16PL == 0) +#define MG5_12_116PL ~(1 << 15) +#else +#define MG5_12_116PL 0xFFFF +#endif + +#define MG5_12_112PL 0xF7FF +#define MG5_12 (MG5_12_11PL & MG5_12_12PL & MG5_12_13PL & MG5_12_14PL & \ + MG5_12_15PL & MG5_12_16PL & MG5_12_17PL & MG5_12_18PL & \ + MG5_12_19PL & MG5_12_110PL & MG5_12_111PL & MG5_12_112PL & \ + MG5_12_113PL & MG5_12_114PL & MG5_12_115PL & MG5_12_116PL) +// End of MG5_12: +// Beginning of MG513: +#if (G5_1PL >= G5_13PL) || (G5_1PL == 0) +#define MG5_13_11PL ~(1 << 0) +#else +#define MG5_13_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_13PL) || (G5_2PL == 0) +#define MG5_13_12PL ~(1 << 1) +#else +#define MG5_13_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_13PL) || (G5_3PL == 0) +#define MG5_13_13PL ~(1 << 2) +#else +#define MG5_13_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_13PL) || (G5_4PL == 0) +#define MG5_13_14PL ~(1 << 3) +#else +#define MG5_13_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_13PL) || (G5_5PL == 0) +#define MG5_13_15PL ~(1 << 4) +#else +#define MG5_13_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_13PL) || (G5_6PL == 0) +#define MG5_13_16PL ~(1 << 5) +#else +#define MG5_13_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_13PL) || (G5_7PL == 0) +#define MG5_13_17PL ~(1 << 6) +#else +#define MG5_13_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_13PL) || (G5_8PL == 0) +#define MG5_13_18PL ~(1 << 7) +#else +#define MG5_13_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_13PL) || (G5_9PL == 0) +#define MG5_13_19PL ~(1 << 8) +#else +#define MG5_13_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_13PL) || (G5_10PL == 0) +#define MG5_13_110PL ~(1 << 9) +#else +#define MG5_13_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_13PL) || (G5_11PL == 0) +#define MG5_13_111PL ~(1 << 10) +#else +#define MG5_13_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_13PL) || (G5_12PL == 0) +#define MG5_13_112PL ~(1 << 11) +#else +#define MG5_13_112PL 0xFFFF +#endif + +#if (G5_14PL >= G5_13PL) || (G5_14PL == 0) +#define MG5_13_114PL ~(1 << 13) +#else +#define MG5_13_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_13PL) || (G5_15PL == 0) +#define MG5_13_115PL ~(1 << 14) +#else +#define MG5_13_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_13PL) || (G5_16PL == 0) +#define MG5_13_116PL ~(1 << 15) +#else +#define MG5_13_116PL 0xFFFF +#endif + +#define MG5_13_113PL 0xEFFF +#define MG5_13 (MG5_13_11PL & MG5_13_12PL & MG5_13_13PL & MG5_13_14PL & \ + MG5_13_15PL & MG5_13_16PL & MG5_13_17PL & MG5_13_18PL & \ + MG5_13_19PL & MG5_13_110PL & MG5_13_111PL & MG5_13_112PL & \ + MG5_13_113PL & MG5_13_114PL & MG5_13_115PL & MG5_13_116PL) +// End of MG5_13: +// Beginning of MG514: +#if (G5_1PL >= G5_14PL) || (G5_1PL == 0) +#define MG5_14_11PL ~(1 << 0) +#else +#define MG5_14_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_14PL) || (G5_2PL == 0) +#define MG5_14_12PL ~(1 << 1) +#else +#define MG5_14_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_14PL) || (G5_3PL == 0) +#define MG5_14_13PL ~(1 << 2) +#else +#define MG5_14_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_14PL) || (G5_4PL == 0) +#define MG5_14_14PL ~(1 << 3) +#else +#define MG5_14_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_14PL) || (G5_5PL == 0) +#define MG5_14_15PL ~(1 << 4) +#else +#define MG5_14_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_14PL) || (G5_6PL == 0) +#define MG5_14_16PL ~(1 << 5) +#else +#define MG5_14_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_14PL) || (G5_7PL == 0) +#define MG5_14_17PL ~(1 << 6) +#else +#define MG5_14_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_14PL) || (G5_8PL == 0) +#define MG5_14_18PL ~(1 << 7) +#else +#define MG5_14_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_14PL) || (G5_9PL == 0) +#define MG5_14_19PL ~(1 << 8) +#else +#define MG5_14_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_14PL) || (G5_10PL == 0) +#define MG5_14_110PL ~(1 << 9) +#else +#define MG5_14_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_14PL) || (G5_11PL == 0) +#define MG5_14_111PL ~(1 << 10) +#else +#define MG5_14_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_14PL) || (G5_12PL == 0) +#define MG5_14_112PL ~(1 << 11) +#else +#define MG5_14_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_14PL) || (G5_13PL == 0) +#define MG5_14_113PL ~(1 << 12) +#else +#define MG5_14_113PL 0xFFFF +#endif + +#if (G5_15PL >= G5_14PL) || (G5_15PL == 0) +#define MG5_14_115PL ~(1 << 14) +#else +#define MG5_14_115PL 0xFFFF +#endif + +#if (G5_16PL >= G5_14PL) || (G5_16PL == 0) +#define MG5_14_116PL ~(1 << 15) +#else +#define MG5_14_116PL 0xFFFF +#endif + +#define MG5_14_114PL 0xDFFF +#define MG5_14 (MG5_14_11PL & MG5_14_12PL & MG5_14_13PL & MG5_14_14PL & \ + MG5_14_15PL & MG5_14_16PL & MG5_14_17PL & MG5_14_18PL & \ + MG5_14_19PL & MG5_14_110PL & MG5_14_111PL & MG5_14_112PL & \ + MG5_14_113PL & MG5_14_114PL & MG5_14_115PL & MG5_14_116PL) +// End of MG5_14: +// Beginning of MG515: +#if (G5_1PL >= G5_15PL) || (G5_1PL == 0) +#define MG5_15_11PL ~(1 << 0) +#else +#define MG5_15_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_15PL) || (G5_2PL == 0) +#define MG5_15_12PL ~(1 << 1) +#else +#define MG5_15_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_15PL) || (G5_3PL == 0) +#define MG5_15_13PL ~(1 << 2) +#else +#define MG5_15_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_15PL) || (G5_4PL == 0) +#define MG5_15_14PL ~(1 << 3) +#else +#define MG5_15_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_15PL) || (G5_5PL == 0) +#define MG5_15_15PL ~(1 << 4) +#else +#define MG5_15_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_15PL) || (G5_6PL == 0) +#define MG5_15_16PL ~(1 << 5) +#else +#define MG5_15_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_15PL) || (G5_7PL == 0) +#define MG5_15_17PL ~(1 << 6) +#else +#define MG5_15_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_15PL) || (G5_8PL == 0) +#define MG5_15_18PL ~(1 << 7) +#else +#define MG5_15_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_15PL) || (G5_9PL == 0) +#define MG5_15_19PL ~(1 << 8) +#else +#define MG5_15_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_15PL) || (G5_10PL == 0) +#define MG5_15_110PL ~(1 << 9) +#else +#define MG5_15_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_15PL) || (G5_11PL == 0) +#define MG5_15_111PL ~(1 << 10) +#else +#define MG5_15_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_15PL) || (G5_12PL == 0) +#define MG5_15_112PL ~(1 << 11) +#else +#define MG5_15_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_15PL) || (G5_13PL == 0) +#define MG5_15_113PL ~(1 << 12) +#else +#define MG5_15_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_15PL) || (G5_14PL == 0) +#define MG5_15_114PL ~(1 << 13) +#else +#define MG5_15_114PL 0xFFFF +#endif + +#if (G5_16PL >= G5_15PL) || (G5_16PL == 0) +#define MG5_15_116PL ~(1 << 15) +#else +#define MG5_15_116PL 0xFFFF +#endif + +#define MG5_15_115PL 0xBFFF +#define MG5_15 (MG5_15_11PL & MG5_15_12PL & MG5_15_13PL & MG5_15_14PL & \ + MG5_15_15PL & MG5_15_16PL & MG5_15_17PL & MG5_15_18PL & \ + MG5_15_19PL & MG5_15_110PL & MG5_15_111PL & MG5_15_112PL & \ + MG5_15_113PL & MG5_15_114PL & MG5_15_115PL & MG5_15_116PL) +// End of MG5_15: +// Beginning of MG516: +#if (G5_1PL >= G5_16PL) || (G5_1PL == 0) +#define MG5_16_11PL ~(1 << 0) +#else +#define MG5_16_11PL 0xFFFF +#endif + +#if (G5_2PL >= G5_16PL) || (G5_2PL == 0) +#define MG5_16_12PL ~(1 << 1) +#else +#define MG5_16_12PL 0xFFFF +#endif + +#if (G5_3PL >= G5_16PL) || (G5_3PL == 0) +#define MG5_16_13PL ~(1 << 2) +#else +#define MG5_16_13PL 0xFFFF +#endif + +#if (G5_4PL >= G5_16PL) || (G5_4PL == 0) +#define MG5_16_14PL ~(1 << 3) +#else +#define MG5_16_14PL 0xFFFF +#endif + +#if (G5_5PL >= G5_16PL) || (G5_5PL == 0) +#define MG5_16_15PL ~(1 << 4) +#else +#define MG5_16_15PL 0xFFFF +#endif + +#if (G5_6PL >= G5_16PL) || (G5_6PL == 0) +#define MG5_16_16PL ~(1 << 5) +#else +#define MG5_16_16PL 0xFFFF +#endif + +#if (G5_7PL >= G5_16PL) || (G5_7PL == 0) +#define MG5_16_17PL ~(1 << 6) +#else +#define MG5_16_17PL 0xFFFF +#endif + +#if (G5_8PL >= G5_16PL) || (G5_8PL == 0) +#define MG5_16_18PL ~(1 << 7) +#else +#define MG5_16_18PL 0xFFFF +#endif + +#if (G5_9PL >= G5_16PL) || (G5_9PL == 0) +#define MG5_16_19PL ~(1 << 8) +#else +#define MG5_16_19PL 0xFFFF +#endif + +#if (G5_10PL >= G5_16PL) || (G5_10PL == 0) +#define MG5_16_110PL ~(1 << 9) +#else +#define MG5_16_110PL 0xFFFF +#endif + +#if (G5_11PL >= G5_16PL) || (G5_11PL == 0) +#define MG5_16_111PL ~(1 << 10) +#else +#define MG5_16_111PL 0xFFFF +#endif + +#if (G5_12PL >= G5_16PL) || (G5_12PL == 0) +#define MG5_16_112PL ~(1 << 11) +#else +#define MG5_16_112PL 0xFFFF +#endif + +#if (G5_13PL >= G5_16PL) || (G5_13PL == 0) +#define MG5_16_113PL ~(1 << 12) +#else +#define MG5_16_113PL 0xFFFF +#endif + +#if (G5_14PL >= G5_16PL) || (G5_14PL == 0) +#define MG5_16_114PL ~(1 << 13) +#else +#define MG5_16_114PL 0xFFFF +#endif + +#if (G5_15PL >= G5_16PL) || (G5_15PL == 0) +#define MG5_16_115PL ~(1 << 14) +#else +#define MG5_16_115PL 0xFFFF +#endif + +#define MG5_16_116PL 0x7FFF +#define MG5_16 (MG5_16_11PL & MG5_16_12PL & MG5_16_13PL & MG5_16_14PL & \ + MG5_16_15PL & MG5_16_16PL & MG5_16_17PL & MG5_16_18PL & \ + MG5_16_19PL & MG5_16_110PL & MG5_16_111PL & MG5_16_112PL & \ + MG5_16_113PL & MG5_16_114PL & MG5_16_115PL & MG5_16_116PL) +// End of MG5_16: + + +// +// Automatically generate PIEIER6 interrupt masks MG61 to MG616: +// + +// Beginning of MG61: +#if (G6_2PL >= G6_1PL) || (G6_2PL == 0) +#define MG6_1_12PL ~(1 << 1) +#else +#define MG6_1_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_1PL) || (G6_3PL == 0) +#define MG6_1_13PL ~(1 << 2) +#else +#define MG6_1_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_1PL) || (G6_4PL == 0) +#define MG6_1_14PL ~(1 << 3) +#else +#define MG6_1_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_1PL) || (G6_5PL == 0) +#define MG6_1_15PL ~(1 << 4) +#else +#define MG6_1_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_1PL) || (G6_6PL == 0) +#define MG6_1_16PL ~(1 << 5) +#else +#define MG6_1_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_1PL) || (G6_7PL == 0) +#define MG6_1_17PL ~(1 << 6) +#else +#define MG6_1_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_1PL) || (G6_8PL == 0) +#define MG6_1_18PL ~(1 << 7) +#else +#define MG6_1_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_1PL) || (G6_9PL == 0) +#define MG6_1_19PL ~(1 << 8) +#else +#define MG6_1_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_1PL) || (G6_10PL == 0) +#define MG6_1_110PL ~(1 << 9) +#else +#define MG6_1_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_1PL) || (G6_11PL == 0) +#define MG6_1_111PL ~(1 << 10) +#else +#define MG6_1_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_1PL) || (G6_12PL == 0) +#define MG6_1_112PL ~(1 << 11) +#else +#define MG6_1_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_1PL) || (G6_13PL == 0) +#define MG6_1_113PL ~(1 << 12) +#else +#define MG6_1_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_1PL) || (G6_14PL == 0) +#define MG6_1_114PL ~(1 << 13) +#else +#define MG6_1_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_1PL) || (G6_15PL == 0) +#define MG6_1_115PL ~(1 << 14) +#else +#define MG6_1_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_1PL) || (G6_16PL == 0) +#define MG6_1_116PL ~(1 << 15) +#else +#define MG6_1_116PL 0xFFFF +#endif + +#define MG6_1_11PL 0xFFFE +#define MG6_1 (MG6_1_11PL & MG6_1_12PL & MG6_1_13PL & MG6_1_14PL & \ + MG6_1_15PL & MG6_1_16PL & MG6_1_17PL & MG6_1_18PL & \ + MG6_1_19PL & MG6_1_110PL & MG6_1_111PL & MG6_1_112PL & \ + MG6_1_113PL & MG6_1_114PL & MG6_1_115PL & MG6_1_116PL) +// End of MG6_1: +// Beginning of MG62: +#if (G6_1PL >= G6_2PL) || (G6_1PL == 0) +#define MG6_2_11PL ~(1 << 0) +#else +#define MG6_2_11PL 0xFFFF +#endif + +#if (G6_3PL >= G6_2PL) || (G6_3PL == 0) +#define MG6_2_13PL ~(1 << 2) +#else +#define MG6_2_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_2PL) || (G6_4PL == 0) +#define MG6_2_14PL ~(1 << 3) +#else +#define MG6_2_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_2PL) || (G6_5PL == 0) +#define MG6_2_15PL ~(1 << 4) +#else +#define MG6_2_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_2PL) || (G6_6PL == 0) +#define MG6_2_16PL ~(1 << 5) +#else +#define MG6_2_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_2PL) || (G6_7PL == 0) +#define MG6_2_17PL ~(1 << 6) +#else +#define MG6_2_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_2PL) || (G6_8PL == 0) +#define MG6_2_18PL ~(1 << 7) +#else +#define MG6_2_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_2PL) || (G6_9PL == 0) +#define MG6_2_19PL ~(1 << 8) +#else +#define MG6_2_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_2PL) || (G6_10PL == 0) +#define MG6_2_110PL ~(1 << 9) +#else +#define MG6_2_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_2PL) || (G6_11PL == 0) +#define MG6_2_111PL ~(1 << 10) +#else +#define MG6_2_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_2PL) || (G6_12PL == 0) +#define MG6_2_112PL ~(1 << 11) +#else +#define MG6_2_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_2PL) || (G6_13PL == 0) +#define MG6_2_113PL ~(1 << 12) +#else +#define MG6_2_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_2PL) || (G6_14PL == 0) +#define MG6_2_114PL ~(1 << 13) +#else +#define MG6_2_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_2PL) || (G6_15PL == 0) +#define MG6_2_115PL ~(1 << 14) +#else +#define MG6_2_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_2PL) || (G6_16PL == 0) +#define MG6_2_116PL ~(1 << 15) +#else +#define MG6_2_116PL 0xFFFF +#endif + +#define MG6_2_12PL 0xFFFD +#define MG6_2 (MG6_2_11PL & MG6_2_12PL & MG6_2_13PL & MG6_2_14PL & \ + MG6_2_15PL & MG6_2_16PL & MG6_2_17PL & MG6_2_18PL & \ + MG6_2_19PL & MG6_2_110PL & MG6_2_111PL & MG6_2_112PL & \ + MG6_2_113PL & MG6_2_114PL & MG6_2_115PL & MG6_2_116PL) +// End of MG6_2: +// Beginning of MG63: +#if (G6_1PL >= G6_3PL) || (G6_1PL == 0) +#define MG6_3_11PL ~(1 << 0) +#else +#define MG6_3_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_3PL) || (G6_2PL == 0) +#define MG6_3_12PL ~(1 << 1) +#else +#define MG6_3_12PL 0xFFFF +#endif + +#if (G6_4PL >= G6_3PL) || (G6_4PL == 0) +#define MG6_3_14PL ~(1 << 3) +#else +#define MG6_3_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_3PL) || (G6_5PL == 0) +#define MG6_3_15PL ~(1 << 4) +#else +#define MG6_3_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_3PL) || (G6_6PL == 0) +#define MG6_3_16PL ~(1 << 5) +#else +#define MG6_3_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_3PL) || (G6_7PL == 0) +#define MG6_3_17PL ~(1 << 6) +#else +#define MG6_3_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_3PL) || (G6_8PL == 0) +#define MG6_3_18PL ~(1 << 7) +#else +#define MG6_3_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_3PL) || (G6_9PL == 0) +#define MG6_3_19PL ~(1 << 8) +#else +#define MG6_3_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_3PL) || (G6_10PL == 0) +#define MG6_3_110PL ~(1 << 9) +#else +#define MG6_3_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_3PL) || (G6_11PL == 0) +#define MG6_3_111PL ~(1 << 10) +#else +#define MG6_3_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_3PL) || (G6_12PL == 0) +#define MG6_3_112PL ~(1 << 11) +#else +#define MG6_3_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_3PL) || (G6_13PL == 0) +#define MG6_3_113PL ~(1 << 12) +#else +#define MG6_3_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_3PL) || (G6_14PL == 0) +#define MG6_3_114PL ~(1 << 13) +#else +#define MG6_3_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_3PL) || (G6_15PL == 0) +#define MG6_3_115PL ~(1 << 14) +#else +#define MG6_3_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_3PL) || (G6_16PL == 0) +#define MG6_3_116PL ~(1 << 15) +#else +#define MG6_3_116PL 0xFFFF +#endif + +#define MG6_3_13PL 0xFFFB +#define MG6_3 (MG6_3_11PL & MG6_3_12PL & MG6_3_13PL & MG6_3_14PL & \ + MG6_3_15PL & MG6_3_16PL & MG6_3_17PL & MG6_3_18PL & \ + MG6_3_19PL & MG6_3_110PL & MG6_3_111PL & MG6_3_112PL & \ + MG6_3_113PL & MG6_3_114PL & MG6_3_115PL & MG6_3_116PL) +// End of MG6_3: +// Beginning of MG64: +#if (G6_1PL >= G6_4PL) || (G6_1PL == 0) +#define MG6_4_11PL ~(1 << 0) +#else +#define MG6_4_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_4PL) || (G6_2PL == 0) +#define MG6_4_12PL ~(1 << 1) +#else +#define MG6_4_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_4PL) || (G6_3PL == 0) +#define MG6_4_13PL ~(1 << 2) +#else +#define MG6_4_13PL 0xFFFF +#endif + +#if (G6_5PL >= G6_4PL) || (G6_5PL == 0) +#define MG6_4_15PL ~(1 << 4) +#else +#define MG6_4_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_4PL) || (G6_6PL == 0) +#define MG6_4_16PL ~(1 << 5) +#else +#define MG6_4_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_4PL) || (G6_7PL == 0) +#define MG6_4_17PL ~(1 << 6) +#else +#define MG6_4_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_4PL) || (G6_8PL == 0) +#define MG6_4_18PL ~(1 << 7) +#else +#define MG6_4_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_4PL) || (G6_9PL == 0) +#define MG6_4_19PL ~(1 << 8) +#else +#define MG6_4_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_4PL) || (G6_10PL == 0) +#define MG6_4_110PL ~(1 << 9) +#else +#define MG6_4_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_4PL) || (G6_11PL == 0) +#define MG6_4_111PL ~(1 << 10) +#else +#define MG6_4_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_4PL) || (G6_12PL == 0) +#define MG6_4_112PL ~(1 << 11) +#else +#define MG6_4_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_4PL) || (G6_13PL == 0) +#define MG6_4_113PL ~(1 << 12) +#else +#define MG6_4_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_4PL) || (G6_14PL == 0) +#define MG6_4_114PL ~(1 << 13) +#else +#define MG6_4_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_4PL) || (G6_15PL == 0) +#define MG6_4_115PL ~(1 << 14) +#else +#define MG6_4_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_4PL) || (G6_16PL == 0) +#define MG6_4_116PL ~(1 << 15) +#else +#define MG6_4_116PL 0xFFFF +#endif + +#define MG6_4_14PL 0xFFF7 +#define MG6_4 (MG6_4_11PL & MG6_4_12PL & MG6_4_13PL & MG6_4_14PL & \ + MG6_4_15PL & MG6_4_16PL & MG6_4_17PL & MG6_4_18PL & \ + MG6_4_19PL & MG6_4_110PL & MG6_4_111PL & MG6_4_112PL & \ + MG6_4_113PL & MG6_4_114PL & MG6_4_115PL & MG6_4_116PL) +// End of MG6_4: +// Beginning of MG65: +#if (G6_1PL >= G6_5PL) || (G6_1PL == 0) +#define MG6_5_11PL ~(1 << 0) +#else +#define MG6_5_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_5PL) || (G6_2PL == 0) +#define MG6_5_12PL ~(1 << 1) +#else +#define MG6_5_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_5PL) || (G6_3PL == 0) +#define MG6_5_13PL ~(1 << 2) +#else +#define MG6_5_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_5PL) || (G6_4PL == 0) +#define MG6_5_14PL ~(1 << 3) +#else +#define MG6_5_14PL 0xFFFF +#endif + +#if (G6_6PL >= G6_5PL) || (G6_6PL == 0) +#define MG6_5_16PL ~(1 << 5) +#else +#define MG6_5_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_5PL) || (G6_7PL == 0) +#define MG6_5_17PL ~(1 << 6) +#else +#define MG6_5_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_5PL) || (G6_8PL == 0) +#define MG6_5_18PL ~(1 << 7) +#else +#define MG6_5_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_5PL) || (G6_9PL == 0) +#define MG6_5_19PL ~(1 << 8) +#else +#define MG6_5_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_5PL) || (G6_10PL == 0) +#define MG6_5_110PL ~(1 << 9) +#else +#define MG6_5_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_5PL) || (G6_11PL == 0) +#define MG6_5_111PL ~(1 << 10) +#else +#define MG6_5_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_5PL) || (G6_12PL == 0) +#define MG6_5_112PL ~(1 << 11) +#else +#define MG6_5_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_5PL) || (G6_13PL == 0) +#define MG6_5_113PL ~(1 << 12) +#else +#define MG6_5_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_5PL) || (G6_14PL == 0) +#define MG6_5_114PL ~(1 << 13) +#else +#define MG6_5_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_5PL) || (G6_15PL == 0) +#define MG6_5_115PL ~(1 << 14) +#else +#define MG6_5_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_5PL) || (G6_16PL == 0) +#define MG6_5_116PL ~(1 << 15) +#else +#define MG6_5_116PL 0xFFFF +#endif + +#define MG6_5_15PL 0xFFEF +#define MG6_5 (MG6_5_11PL & MG6_5_12PL & MG6_5_13PL & MG6_5_14PL & \ + MG6_5_15PL & MG6_5_16PL & MG6_5_17PL & MG6_5_18PL & \ + MG6_5_19PL & MG6_5_110PL & MG6_5_111PL & MG6_5_112PL & \ + MG6_5_113PL & MG6_5_114PL & MG6_5_115PL & MG6_5_116PL) +// End of MG6_5: +// Beginning of MG66: +#if (G6_1PL >= G6_6PL) || (G6_1PL == 0) +#define MG6_6_11PL ~(1 << 0) +#else +#define MG6_6_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_6PL) || (G6_2PL == 0) +#define MG6_6_12PL ~(1 << 1) +#else +#define MG6_6_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_6PL) || (G6_3PL == 0) +#define MG6_6_13PL ~(1 << 2) +#else +#define MG6_6_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_6PL) || (G6_4PL == 0) +#define MG6_6_14PL ~(1 << 3) +#else +#define MG6_6_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_6PL) || (G6_5PL == 0) +#define MG6_6_15PL ~(1 << 4) +#else +#define MG6_6_15PL 0xFFFF +#endif + +#if (G6_7PL >= G6_6PL) || (G6_7PL == 0) +#define MG6_6_17PL ~(1 << 6) +#else +#define MG6_6_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_6PL) || (G6_8PL == 0) +#define MG6_6_18PL ~(1 << 7) +#else +#define MG6_6_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_6PL) || (G6_9PL == 0) +#define MG6_6_19PL ~(1 << 8) +#else +#define MG6_6_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_6PL) || (G6_10PL == 0) +#define MG6_6_110PL ~(1 << 9) +#else +#define MG6_6_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_6PL) || (G6_11PL == 0) +#define MG6_6_111PL ~(1 << 10) +#else +#define MG6_6_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_6PL) || (G6_12PL == 0) +#define MG6_6_112PL ~(1 << 11) +#else +#define MG6_6_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_6PL) || (G6_13PL == 0) +#define MG6_6_113PL ~(1 << 12) +#else +#define MG6_6_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_6PL) || (G6_14PL == 0) +#define MG6_6_114PL ~(1 << 13) +#else +#define MG6_6_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_6PL) || (G6_15PL == 0) +#define MG6_6_115PL ~(1 << 14) +#else +#define MG6_6_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_6PL) || (G6_16PL == 0) +#define MG6_6_116PL ~(1 << 15) +#else +#define MG6_6_116PL 0xFFFF +#endif + +#define MG6_6_16PL 0xFFDF +#define MG6_6 (MG6_6_11PL & MG6_6_12PL & MG6_6_13PL & MG6_6_14PL & \ + MG6_6_15PL & MG6_6_16PL & MG6_6_17PL & MG6_6_18PL & \ + MG6_6_19PL & MG6_6_110PL & MG6_6_111PL & MG6_6_112PL & \ + MG6_6_113PL & MG6_6_114PL & MG6_6_115PL & MG6_6_116PL) +// End of MG6_6: +// Beginning of MG67: +#if (G6_1PL >= G6_7PL) || (G6_1PL == 0) +#define MG6_7_11PL ~(1 << 0) +#else +#define MG6_7_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_7PL) || (G6_2PL == 0) +#define MG6_7_12PL ~(1 << 1) +#else +#define MG6_7_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_7PL) || (G6_3PL == 0) +#define MG6_7_13PL ~(1 << 2) +#else +#define MG6_7_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_7PL) || (G6_4PL == 0) +#define MG6_7_14PL ~(1 << 3) +#else +#define MG6_7_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_7PL) || (G6_5PL == 0) +#define MG6_7_15PL ~(1 << 4) +#else +#define MG6_7_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_7PL) || (G6_6PL == 0) +#define MG6_7_16PL ~(1 << 5) +#else +#define MG6_7_16PL 0xFFFF +#endif + +#if (G6_8PL >= G6_7PL) || (G6_8PL == 0) +#define MG6_7_18PL ~(1 << 7) +#else +#define MG6_7_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_7PL) || (G6_9PL == 0) +#define MG6_7_19PL ~(1 << 8) +#else +#define MG6_7_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_7PL) || (G6_10PL == 0) +#define MG6_7_110PL ~(1 << 9) +#else +#define MG6_7_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_7PL) || (G6_11PL == 0) +#define MG6_7_111PL ~(1 << 10) +#else +#define MG6_7_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_7PL) || (G6_12PL == 0) +#define MG6_7_112PL ~(1 << 11) +#else +#define MG6_7_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_7PL) || (G6_13PL == 0) +#define MG6_7_113PL ~(1 << 12) +#else +#define MG6_7_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_7PL) || (G6_14PL == 0) +#define MG6_7_114PL ~(1 << 13) +#else +#define MG6_7_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_7PL) || (G6_15PL == 0) +#define MG6_7_115PL ~(1 << 14) +#else +#define MG6_7_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_7PL) || (G6_16PL == 0) +#define MG6_7_116PL ~(1 << 15) +#else +#define MG6_7_116PL 0xFFFF +#endif + +#define MG6_7_17PL 0xFFBF +#define MG6_7 (MG6_7_11PL & MG6_7_12PL & MG6_7_13PL & MG6_7_14PL & \ + MG6_7_15PL & MG6_7_16PL & MG6_7_17PL & MG6_7_18PL & \ + MG6_7_19PL & MG6_7_110PL & MG6_7_111PL & MG6_7_112PL & \ + MG6_7_113PL & MG6_7_114PL & MG6_7_115PL & MG6_7_116PL) +// End of MG6_7: +// Beginning of MG68: +#if (G6_1PL >= G6_8PL) || (G6_1PL == 0) +#define MG6_8_11PL ~(1 << 0) +#else +#define MG6_8_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_8PL) || (G6_2PL == 0) +#define MG6_8_12PL ~(1 << 1) +#else +#define MG6_8_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_8PL) || (G6_3PL == 0) +#define MG6_8_13PL ~(1 << 2) +#else +#define MG6_8_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_8PL) || (G6_4PL == 0) +#define MG6_8_14PL ~(1 << 3) +#else +#define MG6_8_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_8PL) || (G6_5PL == 0) +#define MG6_8_15PL ~(1 << 4) +#else +#define MG6_8_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_8PL) || (G6_6PL == 0) +#define MG6_8_16PL ~(1 << 5) +#else +#define MG6_8_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_8PL) || (G6_7PL == 0) +#define MG6_8_17PL ~(1 << 6) +#else +#define MG6_8_17PL 0xFFFF +#endif + +#if (G6_9PL >= G6_8PL) || (G6_9PL == 0) +#define MG6_8_19PL ~(1 << 8) +#else +#define MG6_8_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_8PL) || (G6_10PL == 0) +#define MG6_8_110PL ~(1 << 9) +#else +#define MG6_8_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_8PL) || (G6_11PL == 0) +#define MG6_8_111PL ~(1 << 10) +#else +#define MG6_8_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_8PL) || (G6_12PL == 0) +#define MG6_8_112PL ~(1 << 11) +#else +#define MG6_8_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_8PL) || (G6_13PL == 0) +#define MG6_8_113PL ~(1 << 12) +#else +#define MG6_8_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_8PL) || (G6_14PL == 0) +#define MG6_8_114PL ~(1 << 13) +#else +#define MG6_8_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_8PL) || (G6_15PL == 0) +#define MG6_8_115PL ~(1 << 14) +#else +#define MG6_8_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_8PL) || (G6_16PL == 0) +#define MG6_8_116PL ~(1 << 15) +#else +#define MG6_8_116PL 0xFFFF +#endif + +#define MG6_8_18PL 0xFF7F +#define MG6_8 (MG6_8_11PL & MG6_8_12PL & MG6_8_13PL & MG6_8_14PL & \ + MG6_8_15PL & MG6_8_16PL & MG6_8_17PL & MG6_8_18PL & \ + MG6_8_19PL & MG6_8_110PL & MG6_8_111PL & MG6_8_112PL & \ + MG6_8_113PL & MG6_8_114PL & MG6_8_115PL & MG6_8_116PL) +// End of MG6_8: +// Beginning of MG69: +#if (G6_1PL >= G6_9PL) || (G6_1PL == 0) +#define MG6_9_11PL ~(1 << 0) +#else +#define MG6_9_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_9PL) || (G6_2PL == 0) +#define MG6_9_12PL ~(1 << 1) +#else +#define MG6_9_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_9PL) || (G6_3PL == 0) +#define MG6_9_13PL ~(1 << 2) +#else +#define MG6_9_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_9PL) || (G6_4PL == 0) +#define MG6_9_14PL ~(1 << 3) +#else +#define MG6_9_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_9PL) || (G6_5PL == 0) +#define MG6_9_15PL ~(1 << 4) +#else +#define MG6_9_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_9PL) || (G6_6PL == 0) +#define MG6_9_16PL ~(1 << 5) +#else +#define MG6_9_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_9PL) || (G6_7PL == 0) +#define MG6_9_17PL ~(1 << 6) +#else +#define MG6_9_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_9PL) || (G6_8PL == 0) +#define MG6_9_18PL ~(1 << 7) +#else +#define MG6_9_18PL 0xFFFF +#endif + +#if (G6_10PL >= G6_9PL) || (G6_10PL == 0) +#define MG6_9_110PL ~(1 << 9) +#else +#define MG6_9_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_9PL) || (G6_11PL == 0) +#define MG6_9_111PL ~(1 << 10) +#else +#define MG6_9_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_9PL) || (G6_12PL == 0) +#define MG6_9_112PL ~(1 << 11) +#else +#define MG6_9_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_9PL) || (G6_13PL == 0) +#define MG6_9_113PL ~(1 << 12) +#else +#define MG6_9_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_9PL) || (G6_14PL == 0) +#define MG6_9_114PL ~(1 << 13) +#else +#define MG6_9_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_9PL) || (G6_15PL == 0) +#define MG6_9_115PL ~(1 << 14) +#else +#define MG6_9_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_9PL) || (G6_16PL == 0) +#define MG6_9_116PL ~(1 << 15) +#else +#define MG6_9_116PL 0xFFFF +#endif + +#define MG6_9_19PL 0xFEFF +#define MG6_9 (MG6_9_11PL & MG6_9_12PL & MG6_9_13PL & MG6_9_14PL & \ + MG6_9_15PL & MG6_9_16PL & MG6_9_17PL & MG6_9_18PL & \ + MG6_9_19PL & MG6_9_110PL & MG6_9_111PL & MG6_9_112PL & \ + MG6_9_113PL & MG6_9_114PL & MG6_9_115PL & MG6_9_116PL) +// End of MG6_9: +// Beginning of MG610: +#if (G6_1PL >= G6_10PL) || (G6_1PL == 0) +#define MG6_10_11PL ~(1 << 0) +#else +#define MG6_10_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_10PL) || (G6_2PL == 0) +#define MG6_10_12PL ~(1 << 1) +#else +#define MG6_10_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_10PL) || (G6_3PL == 0) +#define MG6_10_13PL ~(1 << 2) +#else +#define MG6_10_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_10PL) || (G6_4PL == 0) +#define MG6_10_14PL ~(1 << 3) +#else +#define MG6_10_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_10PL) || (G6_5PL == 0) +#define MG6_10_15PL ~(1 << 4) +#else +#define MG6_10_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_10PL) || (G6_6PL == 0) +#define MG6_10_16PL ~(1 << 5) +#else +#define MG6_10_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_10PL) || (G6_7PL == 0) +#define MG6_10_17PL ~(1 << 6) +#else +#define MG6_10_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_10PL) || (G6_8PL == 0) +#define MG6_10_18PL ~(1 << 7) +#else +#define MG6_10_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_10PL) || (G6_9PL == 0) +#define MG6_10_19PL ~(1 << 8) +#else +#define MG6_10_19PL 0xFFFF +#endif + +#if (G6_11PL >= G6_10PL) || (G6_11PL == 0) +#define MG6_10_111PL ~(1 << 10) +#else +#define MG6_10_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_10PL) || (G6_12PL == 0) +#define MG6_10_112PL ~(1 << 11) +#else +#define MG6_10_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_10PL) || (G6_13PL == 0) +#define MG6_10_113PL ~(1 << 12) +#else +#define MG6_10_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_10PL) || (G6_14PL == 0) +#define MG6_10_114PL ~(1 << 13) +#else +#define MG6_10_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_10PL) || (G6_15PL == 0) +#define MG6_10_115PL ~(1 << 14) +#else +#define MG6_10_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_10PL) || (G6_16PL == 0) +#define MG6_10_116PL ~(1 << 15) +#else +#define MG6_10_116PL 0xFFFF +#endif + +#define MG6_10_110PL 0xFDFF +#define MG6_10 (MG6_10_11PL & MG6_10_12PL & MG6_10_13PL & MG6_10_14PL & \ + MG6_10_15PL & MG6_10_16PL & MG6_10_17PL & MG6_10_18PL & \ + MG6_10_19PL & MG6_10_110PL & MG6_10_111PL & MG6_10_112PL & \ + MG6_10_113PL & MG6_10_114PL & MG6_10_115PL & MG6_10_116PL) +// End of MG6_10: +// Beginning of MG611: +#if (G6_1PL >= G6_11PL) || (G6_1PL == 0) +#define MG6_11_11PL ~(1 << 0) +#else +#define MG6_11_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_11PL) || (G6_2PL == 0) +#define MG6_11_12PL ~(1 << 1) +#else +#define MG6_11_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_11PL) || (G6_3PL == 0) +#define MG6_11_13PL ~(1 << 2) +#else +#define MG6_11_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_11PL) || (G6_4PL == 0) +#define MG6_11_14PL ~(1 << 3) +#else +#define MG6_11_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_11PL) || (G6_5PL == 0) +#define MG6_11_15PL ~(1 << 4) +#else +#define MG6_11_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_11PL) || (G6_6PL == 0) +#define MG6_11_16PL ~(1 << 5) +#else +#define MG6_11_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_11PL) || (G6_7PL == 0) +#define MG6_11_17PL ~(1 << 6) +#else +#define MG6_11_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_11PL) || (G6_8PL == 0) +#define MG6_11_18PL ~(1 << 7) +#else +#define MG6_11_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_11PL) || (G6_9PL == 0) +#define MG6_11_19PL ~(1 << 8) +#else +#define MG6_11_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_11PL) || (G6_10PL == 0) +#define MG6_11_110PL ~(1 << 9) +#else +#define MG6_11_110PL 0xFFFF +#endif + +#if (G6_12PL >= G6_11PL) || (G6_12PL == 0) +#define MG6_11_112PL ~(1 << 11) +#else +#define MG6_11_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_11PL) || (G6_13PL == 0) +#define MG6_11_113PL ~(1 << 12) +#else +#define MG6_11_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_11PL) || (G6_14PL == 0) +#define MG6_11_114PL ~(1 << 13) +#else +#define MG6_11_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_11PL) || (G6_15PL == 0) +#define MG6_11_115PL ~(1 << 14) +#else +#define MG6_11_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_11PL) || (G6_16PL == 0) +#define MG6_11_116PL ~(1 << 15) +#else +#define MG6_11_116PL 0xFFFF +#endif + +#define MG6_11_111PL 0xFBFF +#define MG6_11 (MG6_11_11PL & MG6_11_12PL & MG6_11_13PL & MG6_11_14PL & \ + MG6_11_15PL & MG6_11_16PL & MG6_11_17PL & MG6_11_18PL & \ + MG6_11_19PL & MG6_11_110PL & MG6_11_111PL & MG6_11_112PL & \ + MG6_11_113PL & MG6_11_114PL & MG6_11_115PL & MG6_11_116PL) +// End of MG6_11: +// Beginning of MG612: +#if (G6_1PL >= G6_12PL) || (G6_1PL == 0) +#define MG6_12_11PL ~(1 << 0) +#else +#define MG6_12_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_12PL) || (G6_2PL == 0) +#define MG6_12_12PL ~(1 << 1) +#else +#define MG6_12_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_12PL) || (G6_3PL == 0) +#define MG6_12_13PL ~(1 << 2) +#else +#define MG6_12_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_12PL) || (G6_4PL == 0) +#define MG6_12_14PL ~(1 << 3) +#else +#define MG6_12_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_12PL) || (G6_5PL == 0) +#define MG6_12_15PL ~(1 << 4) +#else +#define MG6_12_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_12PL) || (G6_6PL == 0) +#define MG6_12_16PL ~(1 << 5) +#else +#define MG6_12_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_12PL) || (G6_7PL == 0) +#define MG6_12_17PL ~(1 << 6) +#else +#define MG6_12_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_12PL) || (G6_8PL == 0) +#define MG6_12_18PL ~(1 << 7) +#else +#define MG6_12_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_12PL) || (G6_9PL == 0) +#define MG6_12_19PL ~(1 << 8) +#else +#define MG6_12_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_12PL) || (G6_10PL == 0) +#define MG6_12_110PL ~(1 << 9) +#else +#define MG6_12_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_12PL) || (G6_11PL == 0) +#define MG6_12_111PL ~(1 << 10) +#else +#define MG6_12_111PL 0xFFFF +#endif + +#if (G6_13PL >= G6_12PL) || (G6_13PL == 0) +#define MG6_12_113PL ~(1 << 12) +#else +#define MG6_12_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_12PL) || (G6_14PL == 0) +#define MG6_12_114PL ~(1 << 13) +#else +#define MG6_12_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_12PL) || (G6_15PL == 0) +#define MG6_12_115PL ~(1 << 14) +#else +#define MG6_12_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_12PL) || (G6_16PL == 0) +#define MG6_12_116PL ~(1 << 15) +#else +#define MG6_12_116PL 0xFFFF +#endif + +#define MG6_12_112PL 0xF7FF +#define MG6_12 (MG6_12_11PL & MG6_12_12PL & MG6_12_13PL & MG6_12_14PL & \ + MG6_12_15PL & MG6_12_16PL & MG6_12_17PL & MG6_12_18PL & \ + MG6_12_19PL & MG6_12_110PL & MG6_12_111PL & MG6_12_112PL & \ + MG6_12_113PL & MG6_12_114PL & MG6_12_115PL & MG6_12_116PL) +// End of MG6_12: +// Beginning of MG613: +#if (G6_1PL >= G6_13PL) || (G6_1PL == 0) +#define MG6_13_11PL ~(1 << 0) +#else +#define MG6_13_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_13PL) || (G6_2PL == 0) +#define MG6_13_12PL ~(1 << 1) +#else +#define MG6_13_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_13PL) || (G6_3PL == 0) +#define MG6_13_13PL ~(1 << 2) +#else +#define MG6_13_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_13PL) || (G6_4PL == 0) +#define MG6_13_14PL ~(1 << 3) +#else +#define MG6_13_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_13PL) || (G6_5PL == 0) +#define MG6_13_15PL ~(1 << 4) +#else +#define MG6_13_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_13PL) || (G6_6PL == 0) +#define MG6_13_16PL ~(1 << 5) +#else +#define MG6_13_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_13PL) || (G6_7PL == 0) +#define MG6_13_17PL ~(1 << 6) +#else +#define MG6_13_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_13PL) || (G6_8PL == 0) +#define MG6_13_18PL ~(1 << 7) +#else +#define MG6_13_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_13PL) || (G6_9PL == 0) +#define MG6_13_19PL ~(1 << 8) +#else +#define MG6_13_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_13PL) || (G6_10PL == 0) +#define MG6_13_110PL ~(1 << 9) +#else +#define MG6_13_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_13PL) || (G6_11PL == 0) +#define MG6_13_111PL ~(1 << 10) +#else +#define MG6_13_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_13PL) || (G6_12PL == 0) +#define MG6_13_112PL ~(1 << 11) +#else +#define MG6_13_112PL 0xFFFF +#endif + +#if (G6_14PL >= G6_13PL) || (G6_14PL == 0) +#define MG6_13_114PL ~(1 << 13) +#else +#define MG6_13_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_13PL) || (G6_15PL == 0) +#define MG6_13_115PL ~(1 << 14) +#else +#define MG6_13_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_13PL) || (G6_16PL == 0) +#define MG6_13_116PL ~(1 << 15) +#else +#define MG6_13_116PL 0xFFFF +#endif + +#define MG6_13_113PL 0xEFFF +#define MG6_13 (MG6_13_11PL & MG6_13_12PL & MG6_13_13PL & MG6_13_14PL & \ + MG6_13_15PL & MG6_13_16PL & MG6_13_17PL & MG6_13_18PL & \ + MG6_13_19PL & MG6_13_110PL & MG6_13_111PL & MG6_13_112PL & \ + MG6_13_113PL & MG6_13_114PL & MG6_13_115PL & MG6_13_116PL) +// End of MG6_13: +// Beginning of MG614: +#if (G6_1PL >= G6_14PL) || (G6_1PL == 0) +#define MG6_14_11PL ~(1 << 0) +#else +#define MG6_14_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_14PL) || (G6_2PL == 0) +#define MG6_14_12PL ~(1 << 1) +#else +#define MG6_14_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_14PL) || (G6_3PL == 0) +#define MG6_14_13PL ~(1 << 2) +#else +#define MG6_14_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_14PL) || (G6_4PL == 0) +#define MG6_14_14PL ~(1 << 3) +#else +#define MG6_14_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_14PL) || (G6_5PL == 0) +#define MG6_14_15PL ~(1 << 4) +#else +#define MG6_14_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_14PL) || (G6_6PL == 0) +#define MG6_14_16PL ~(1 << 5) +#else +#define MG6_14_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_14PL) || (G6_7PL == 0) +#define MG6_14_17PL ~(1 << 6) +#else +#define MG6_14_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_14PL) || (G6_8PL == 0) +#define MG6_14_18PL ~(1 << 7) +#else +#define MG6_14_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_14PL) || (G6_9PL == 0) +#define MG6_14_19PL ~(1 << 8) +#else +#define MG6_14_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_14PL) || (G6_10PL == 0) +#define MG6_14_110PL ~(1 << 9) +#else +#define MG6_14_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_14PL) || (G6_11PL == 0) +#define MG6_14_111PL ~(1 << 10) +#else +#define MG6_14_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_14PL) || (G6_12PL == 0) +#define MG6_14_112PL ~(1 << 11) +#else +#define MG6_14_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_14PL) || (G6_13PL == 0) +#define MG6_14_113PL ~(1 << 12) +#else +#define MG6_14_113PL 0xFFFF +#endif + +#if (G6_15PL >= G6_14PL) || (G6_15PL == 0) +#define MG6_14_115PL ~(1 << 14) +#else +#define MG6_14_115PL 0xFFFF +#endif + +#if (G6_16PL >= G6_14PL) || (G6_16PL == 0) +#define MG6_14_116PL ~(1 << 15) +#else +#define MG6_14_116PL 0xFFFF +#endif + +#define MG6_14_114PL 0xDFFF +#define MG6_14 (MG6_14_11PL & MG6_14_12PL & MG6_14_13PL & MG6_14_14PL & \ + MG6_14_15PL & MG6_14_16PL & MG6_14_17PL & MG6_14_18PL & \ + MG6_14_19PL & MG6_14_110PL & MG6_14_111PL & MG6_14_112PL & \ + MG6_14_113PL & MG6_14_114PL & MG6_14_115PL & MG6_14_116PL) +// End of MG6_14: +// Beginning of MG615: +#if (G6_1PL >= G6_15PL) || (G6_1PL == 0) +#define MG6_15_11PL ~(1 << 0) +#else +#define MG6_15_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_15PL) || (G6_2PL == 0) +#define MG6_15_12PL ~(1 << 1) +#else +#define MG6_15_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_15PL) || (G6_3PL == 0) +#define MG6_15_13PL ~(1 << 2) +#else +#define MG6_15_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_15PL) || (G6_4PL == 0) +#define MG6_15_14PL ~(1 << 3) +#else +#define MG6_15_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_15PL) || (G6_5PL == 0) +#define MG6_15_15PL ~(1 << 4) +#else +#define MG6_15_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_15PL) || (G6_6PL == 0) +#define MG6_15_16PL ~(1 << 5) +#else +#define MG6_15_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_15PL) || (G6_7PL == 0) +#define MG6_15_17PL ~(1 << 6) +#else +#define MG6_15_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_15PL) || (G6_8PL == 0) +#define MG6_15_18PL ~(1 << 7) +#else +#define MG6_15_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_15PL) || (G6_9PL == 0) +#define MG6_15_19PL ~(1 << 8) +#else +#define MG6_15_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_15PL) || (G6_10PL == 0) +#define MG6_15_110PL ~(1 << 9) +#else +#define MG6_15_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_15PL) || (G6_11PL == 0) +#define MG6_15_111PL ~(1 << 10) +#else +#define MG6_15_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_15PL) || (G6_12PL == 0) +#define MG6_15_112PL ~(1 << 11) +#else +#define MG6_15_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_15PL) || (G6_13PL == 0) +#define MG6_15_113PL ~(1 << 12) +#else +#define MG6_15_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_15PL) || (G6_14PL == 0) +#define MG6_15_114PL ~(1 << 13) +#else +#define MG6_15_114PL 0xFFFF +#endif + +#if (G6_16PL >= G6_15PL) || (G6_16PL == 0) +#define MG6_15_116PL ~(1 << 15) +#else +#define MG6_15_116PL 0xFFFF +#endif + +#define MG6_15_115PL 0xBFFF +#define MG6_15 (MG6_15_11PL & MG6_15_12PL & MG6_15_13PL & MG6_15_14PL & \ + MG6_15_15PL & MG6_15_16PL & MG6_15_17PL & MG6_15_18PL & \ + MG6_15_19PL & MG6_15_110PL & MG6_15_111PL & MG6_15_112PL & \ + MG6_15_113PL & MG6_15_114PL & MG6_15_115PL & MG6_15_116PL) +// End of MG6_15: +// Beginning of MG616: +#if (G6_1PL >= G6_16PL) || (G6_1PL == 0) +#define MG6_16_11PL ~(1 << 0) +#else +#define MG6_16_11PL 0xFFFF +#endif + +#if (G6_2PL >= G6_16PL) || (G6_2PL == 0) +#define MG6_16_12PL ~(1 << 1) +#else +#define MG6_16_12PL 0xFFFF +#endif + +#if (G6_3PL >= G6_16PL) || (G6_3PL == 0) +#define MG6_16_13PL ~(1 << 2) +#else +#define MG6_16_13PL 0xFFFF +#endif + +#if (G6_4PL >= G6_16PL) || (G6_4PL == 0) +#define MG6_16_14PL ~(1 << 3) +#else +#define MG6_16_14PL 0xFFFF +#endif + +#if (G6_5PL >= G6_16PL) || (G6_5PL == 0) +#define MG6_16_15PL ~(1 << 4) +#else +#define MG6_16_15PL 0xFFFF +#endif + +#if (G6_6PL >= G6_16PL) || (G6_6PL == 0) +#define MG6_16_16PL ~(1 << 5) +#else +#define MG6_16_16PL 0xFFFF +#endif + +#if (G6_7PL >= G6_16PL) || (G6_7PL == 0) +#define MG6_16_17PL ~(1 << 6) +#else +#define MG6_16_17PL 0xFFFF +#endif + +#if (G6_8PL >= G6_16PL) || (G6_8PL == 0) +#define MG6_16_18PL ~(1 << 7) +#else +#define MG6_16_18PL 0xFFFF +#endif + +#if (G6_9PL >= G6_16PL) || (G6_9PL == 0) +#define MG6_16_19PL ~(1 << 8) +#else +#define MG6_16_19PL 0xFFFF +#endif + +#if (G6_10PL >= G6_16PL) || (G6_10PL == 0) +#define MG6_16_110PL ~(1 << 9) +#else +#define MG6_16_110PL 0xFFFF +#endif + +#if (G6_11PL >= G6_16PL) || (G6_11PL == 0) +#define MG6_16_111PL ~(1 << 10) +#else +#define MG6_16_111PL 0xFFFF +#endif + +#if (G6_12PL >= G6_16PL) || (G6_12PL == 0) +#define MG6_16_112PL ~(1 << 11) +#else +#define MG6_16_112PL 0xFFFF +#endif + +#if (G6_13PL >= G6_16PL) || (G6_13PL == 0) +#define MG6_16_113PL ~(1 << 12) +#else +#define MG6_16_113PL 0xFFFF +#endif + +#if (G6_14PL >= G6_16PL) || (G6_14PL == 0) +#define MG6_16_114PL ~(1 << 13) +#else +#define MG6_16_114PL 0xFFFF +#endif + +#if (G6_15PL >= G6_16PL) || (G6_15PL == 0) +#define MG6_16_115PL ~(1 << 14) +#else +#define MG6_16_115PL 0xFFFF +#endif + +#define MG6_16_116PL 0x7FFF +#define MG6_16 (MG6_16_11PL & MG6_16_12PL & MG6_16_13PL & MG6_16_14PL & \ + MG6_16_15PL & MG6_16_16PL & MG6_16_17PL & MG6_16_18PL & \ + MG6_16_19PL & MG6_16_110PL & MG6_16_111PL & MG6_16_112PL & \ + MG6_16_113PL & MG6_16_114PL & MG6_16_115PL & MG6_16_116PL) +// End of MG6_16: + + +// +// Automatically generate PIEIER7 interrupt masks MG71 to MG716: +// + +// Beginning of MG71: +#if (G7_2PL >= G7_1PL) || (G7_2PL == 0) +#define MG7_1_12PL ~(1 << 1) +#else +#define MG7_1_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_1PL) || (G7_3PL == 0) +#define MG7_1_13PL ~(1 << 2) +#else +#define MG7_1_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_1PL) || (G7_4PL == 0) +#define MG7_1_14PL ~(1 << 3) +#else +#define MG7_1_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_1PL) || (G7_5PL == 0) +#define MG7_1_15PL ~(1 << 4) +#else +#define MG7_1_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_1PL) || (G7_6PL == 0) +#define MG7_1_16PL ~(1 << 5) +#else +#define MG7_1_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_1PL) || (G7_7PL == 0) +#define MG7_1_17PL ~(1 << 6) +#else +#define MG7_1_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_1PL) || (G7_8PL == 0) +#define MG7_1_18PL ~(1 << 7) +#else +#define MG7_1_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_1PL) || (G7_9PL == 0) +#define MG7_1_19PL ~(1 << 8) +#else +#define MG7_1_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_1PL) || (G7_10PL == 0) +#define MG7_1_110PL ~(1 << 9) +#else +#define MG7_1_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_1PL) || (G7_11PL == 0) +#define MG7_1_111PL ~(1 << 10) +#else +#define MG7_1_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_1PL) || (G7_12PL == 0) +#define MG7_1_112PL ~(1 << 11) +#else +#define MG7_1_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_1PL) || (G7_13PL == 0) +#define MG7_1_113PL ~(1 << 12) +#else +#define MG7_1_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_1PL) || (G7_14PL == 0) +#define MG7_1_114PL ~(1 << 13) +#else +#define MG7_1_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_1PL) || (G7_15PL == 0) +#define MG7_1_115PL ~(1 << 14) +#else +#define MG7_1_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_1PL) || (G7_16PL == 0) +#define MG7_1_116PL ~(1 << 15) +#else +#define MG7_1_116PL 0xFFFF +#endif + +#define MG7_1_11PL 0xFFFE +#define MG7_1 (MG7_1_11PL & MG7_1_12PL & MG7_1_13PL & MG7_1_14PL & \ + MG7_1_15PL & MG7_1_16PL & MG7_1_17PL & MG7_1_18PL & \ + MG7_1_19PL & MG7_1_110PL & MG7_1_111PL & MG7_1_112PL & \ + MG7_1_113PL & MG7_1_114PL & MG7_1_115PL & MG7_1_116PL) +// End of MG7_1: +// Beginning of MG72: +#if (G7_1PL >= G7_2PL) || (G7_1PL == 0) +#define MG7_2_11PL ~(1 << 0) +#else +#define MG7_2_11PL 0xFFFF +#endif + +#if (G7_3PL >= G7_2PL) || (G7_3PL == 0) +#define MG7_2_13PL ~(1 << 2) +#else +#define MG7_2_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_2PL) || (G7_4PL == 0) +#define MG7_2_14PL ~(1 << 3) +#else +#define MG7_2_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_2PL) || (G7_5PL == 0) +#define MG7_2_15PL ~(1 << 4) +#else +#define MG7_2_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_2PL) || (G7_6PL == 0) +#define MG7_2_16PL ~(1 << 5) +#else +#define MG7_2_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_2PL) || (G7_7PL == 0) +#define MG7_2_17PL ~(1 << 6) +#else +#define MG7_2_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_2PL) || (G7_8PL == 0) +#define MG7_2_18PL ~(1 << 7) +#else +#define MG7_2_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_2PL) || (G7_9PL == 0) +#define MG7_2_19PL ~(1 << 8) +#else +#define MG7_2_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_2PL) || (G7_10PL == 0) +#define MG7_2_110PL ~(1 << 9) +#else +#define MG7_2_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_2PL) || (G7_11PL == 0) +#define MG7_2_111PL ~(1 << 10) +#else +#define MG7_2_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_2PL) || (G7_12PL == 0) +#define MG7_2_112PL ~(1 << 11) +#else +#define MG7_2_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_2PL) || (G7_13PL == 0) +#define MG7_2_113PL ~(1 << 12) +#else +#define MG7_2_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_2PL) || (G7_14PL == 0) +#define MG7_2_114PL ~(1 << 13) +#else +#define MG7_2_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_2PL) || (G7_15PL == 0) +#define MG7_2_115PL ~(1 << 14) +#else +#define MG7_2_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_2PL) || (G7_16PL == 0) +#define MG7_2_116PL ~(1 << 15) +#else +#define MG7_2_116PL 0xFFFF +#endif + +#define MG7_2_12PL 0xFFFD +#define MG7_2 (MG7_2_11PL & MG7_2_12PL & MG7_2_13PL & MG7_2_14PL & \ + MG7_2_15PL & MG7_2_16PL & MG7_2_17PL & MG7_2_18PL & \ + MG7_2_19PL & MG7_2_110PL & MG7_2_111PL & MG7_2_112PL & \ + MG7_2_113PL & MG7_2_114PL & MG7_2_115PL & MG7_2_116PL) +// End of MG7_2: +// Beginning of MG73: +#if (G7_1PL >= G7_3PL) || (G7_1PL == 0) +#define MG7_3_11PL ~(1 << 0) +#else +#define MG7_3_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_3PL) || (G7_2PL == 0) +#define MG7_3_12PL ~(1 << 1) +#else +#define MG7_3_12PL 0xFFFF +#endif + +#if (G7_4PL >= G7_3PL) || (G7_4PL == 0) +#define MG7_3_14PL ~(1 << 3) +#else +#define MG7_3_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_3PL) || (G7_5PL == 0) +#define MG7_3_15PL ~(1 << 4) +#else +#define MG7_3_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_3PL) || (G7_6PL == 0) +#define MG7_3_16PL ~(1 << 5) +#else +#define MG7_3_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_3PL) || (G7_7PL == 0) +#define MG7_3_17PL ~(1 << 6) +#else +#define MG7_3_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_3PL) || (G7_8PL == 0) +#define MG7_3_18PL ~(1 << 7) +#else +#define MG7_3_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_3PL) || (G7_9PL == 0) +#define MG7_3_19PL ~(1 << 8) +#else +#define MG7_3_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_3PL) || (G7_10PL == 0) +#define MG7_3_110PL ~(1 << 9) +#else +#define MG7_3_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_3PL) || (G7_11PL == 0) +#define MG7_3_111PL ~(1 << 10) +#else +#define MG7_3_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_3PL) || (G7_12PL == 0) +#define MG7_3_112PL ~(1 << 11) +#else +#define MG7_3_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_3PL) || (G7_13PL == 0) +#define MG7_3_113PL ~(1 << 12) +#else +#define MG7_3_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_3PL) || (G7_14PL == 0) +#define MG7_3_114PL ~(1 << 13) +#else +#define MG7_3_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_3PL) || (G7_15PL == 0) +#define MG7_3_115PL ~(1 << 14) +#else +#define MG7_3_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_3PL) || (G7_16PL == 0) +#define MG7_3_116PL ~(1 << 15) +#else +#define MG7_3_116PL 0xFFFF +#endif + +#define MG7_3_13PL 0xFFFB +#define MG7_3 (MG7_3_11PL & MG7_3_12PL & MG7_3_13PL & MG7_3_14PL & \ + MG7_3_15PL & MG7_3_16PL & MG7_3_17PL & MG7_3_18PL & \ + MG7_3_19PL & MG7_3_110PL & MG7_3_111PL & MG7_3_112PL & \ + MG7_3_113PL & MG7_3_114PL & MG7_3_115PL & MG7_3_116PL) +// End of MG7_3: +// Beginning of MG74: +#if (G7_1PL >= G7_4PL) || (G7_1PL == 0) +#define MG7_4_11PL ~(1 << 0) +#else +#define MG7_4_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_4PL) || (G7_2PL == 0) +#define MG7_4_12PL ~(1 << 1) +#else +#define MG7_4_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_4PL) || (G7_3PL == 0) +#define MG7_4_13PL ~(1 << 2) +#else +#define MG7_4_13PL 0xFFFF +#endif + +#if (G7_5PL >= G7_4PL) || (G7_5PL == 0) +#define MG7_4_15PL ~(1 << 4) +#else +#define MG7_4_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_4PL) || (G7_6PL == 0) +#define MG7_4_16PL ~(1 << 5) +#else +#define MG7_4_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_4PL) || (G7_7PL == 0) +#define MG7_4_17PL ~(1 << 6) +#else +#define MG7_4_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_4PL) || (G7_8PL == 0) +#define MG7_4_18PL ~(1 << 7) +#else +#define MG7_4_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_4PL) || (G7_9PL == 0) +#define MG7_4_19PL ~(1 << 8) +#else +#define MG7_4_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_4PL) || (G7_10PL == 0) +#define MG7_4_110PL ~(1 << 9) +#else +#define MG7_4_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_4PL) || (G7_11PL == 0) +#define MG7_4_111PL ~(1 << 10) +#else +#define MG7_4_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_4PL) || (G7_12PL == 0) +#define MG7_4_112PL ~(1 << 11) +#else +#define MG7_4_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_4PL) || (G7_13PL == 0) +#define MG7_4_113PL ~(1 << 12) +#else +#define MG7_4_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_4PL) || (G7_14PL == 0) +#define MG7_4_114PL ~(1 << 13) +#else +#define MG7_4_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_4PL) || (G7_15PL == 0) +#define MG7_4_115PL ~(1 << 14) +#else +#define MG7_4_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_4PL) || (G7_16PL == 0) +#define MG7_4_116PL ~(1 << 15) +#else +#define MG7_4_116PL 0xFFFF +#endif + +#define MG7_4_14PL 0xFFF7 +#define MG7_4 (MG7_4_11PL & MG7_4_12PL & MG7_4_13PL & MG7_4_14PL & \ + MG7_4_15PL & MG7_4_16PL & MG7_4_17PL & MG7_4_18PL & \ + MG7_4_19PL & MG7_4_110PL & MG7_4_111PL & MG7_4_112PL & \ + MG7_4_113PL & MG7_4_114PL & MG7_4_115PL & MG7_4_116PL) +// End of MG7_4: +// Beginning of MG75: +#if (G7_1PL >= G7_5PL) || (G7_1PL == 0) +#define MG7_5_11PL ~(1 << 0) +#else +#define MG7_5_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_5PL) || (G7_2PL == 0) +#define MG7_5_12PL ~(1 << 1) +#else +#define MG7_5_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_5PL) || (G7_3PL == 0) +#define MG7_5_13PL ~(1 << 2) +#else +#define MG7_5_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_5PL) || (G7_4PL == 0) +#define MG7_5_14PL ~(1 << 3) +#else +#define MG7_5_14PL 0xFFFF +#endif + +#if (G7_6PL >= G7_5PL) || (G7_6PL == 0) +#define MG7_5_16PL ~(1 << 5) +#else +#define MG7_5_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_5PL) || (G7_7PL == 0) +#define MG7_5_17PL ~(1 << 6) +#else +#define MG7_5_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_5PL) || (G7_8PL == 0) +#define MG7_5_18PL ~(1 << 7) +#else +#define MG7_5_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_5PL) || (G7_9PL == 0) +#define MG7_5_19PL ~(1 << 8) +#else +#define MG7_5_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_5PL) || (G7_10PL == 0) +#define MG7_5_110PL ~(1 << 9) +#else +#define MG7_5_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_5PL) || (G7_11PL == 0) +#define MG7_5_111PL ~(1 << 10) +#else +#define MG7_5_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_5PL) || (G7_12PL == 0) +#define MG7_5_112PL ~(1 << 11) +#else +#define MG7_5_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_5PL) || (G7_13PL == 0) +#define MG7_5_113PL ~(1 << 12) +#else +#define MG7_5_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_5PL) || (G7_14PL == 0) +#define MG7_5_114PL ~(1 << 13) +#else +#define MG7_5_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_5PL) || (G7_15PL == 0) +#define MG7_5_115PL ~(1 << 14) +#else +#define MG7_5_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_5PL) || (G7_16PL == 0) +#define MG7_5_116PL ~(1 << 15) +#else +#define MG7_5_116PL 0xFFFF +#endif + +#define MG7_5_15PL 0xFFEF +#define MG7_5 (MG7_5_11PL & MG7_5_12PL & MG7_5_13PL & MG7_5_14PL & \ + MG7_5_15PL & MG7_5_16PL & MG7_5_17PL & MG7_5_18PL & \ + MG7_5_19PL & MG7_5_110PL & MG7_5_111PL & MG7_5_112PL & \ + MG7_5_113PL & MG7_5_114PL & MG7_5_115PL & MG7_5_116PL) +// End of MG7_5: +// Beginning of MG76: +#if (G7_1PL >= G7_6PL) || (G7_1PL == 0) +#define MG7_6_11PL ~(1 << 0) +#else +#define MG7_6_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_6PL) || (G7_2PL == 0) +#define MG7_6_12PL ~(1 << 1) +#else +#define MG7_6_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_6PL) || (G7_3PL == 0) +#define MG7_6_13PL ~(1 << 2) +#else +#define MG7_6_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_6PL) || (G7_4PL == 0) +#define MG7_6_14PL ~(1 << 3) +#else +#define MG7_6_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_6PL) || (G7_5PL == 0) +#define MG7_6_15PL ~(1 << 4) +#else +#define MG7_6_15PL 0xFFFF +#endif + +#if (G7_7PL >= G7_6PL) || (G7_7PL == 0) +#define MG7_6_17PL ~(1 << 6) +#else +#define MG7_6_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_6PL) || (G7_8PL == 0) +#define MG7_6_18PL ~(1 << 7) +#else +#define MG7_6_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_6PL) || (G7_9PL == 0) +#define MG7_6_19PL ~(1 << 8) +#else +#define MG7_6_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_6PL) || (G7_10PL == 0) +#define MG7_6_110PL ~(1 << 9) +#else +#define MG7_6_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_6PL) || (G7_11PL == 0) +#define MG7_6_111PL ~(1 << 10) +#else +#define MG7_6_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_6PL) || (G7_12PL == 0) +#define MG7_6_112PL ~(1 << 11) +#else +#define MG7_6_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_6PL) || (G7_13PL == 0) +#define MG7_6_113PL ~(1 << 12) +#else +#define MG7_6_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_6PL) || (G7_14PL == 0) +#define MG7_6_114PL ~(1 << 13) +#else +#define MG7_6_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_6PL) || (G7_15PL == 0) +#define MG7_6_115PL ~(1 << 14) +#else +#define MG7_6_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_6PL) || (G7_16PL == 0) +#define MG7_6_116PL ~(1 << 15) +#else +#define MG7_6_116PL 0xFFFF +#endif + +#define MG7_6_16PL 0xFFDF +#define MG7_6 (MG7_6_11PL & MG7_6_12PL & MG7_6_13PL & MG7_6_14PL & \ + MG7_6_15PL & MG7_6_16PL & MG7_6_17PL & MG7_6_18PL & \ + MG7_6_19PL & MG7_6_110PL & MG7_6_111PL & MG7_6_112PL & \ + MG7_6_113PL & MG7_6_114PL & MG7_6_115PL & MG7_6_116PL) +// End of MG7_6: +// Beginning of MG77: +#if (G7_1PL >= G7_7PL) || (G7_1PL == 0) +#define MG7_7_11PL ~(1 << 0) +#else +#define MG7_7_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_7PL) || (G7_2PL == 0) +#define MG7_7_12PL ~(1 << 1) +#else +#define MG7_7_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_7PL) || (G7_3PL == 0) +#define MG7_7_13PL ~(1 << 2) +#else +#define MG7_7_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_7PL) || (G7_4PL == 0) +#define MG7_7_14PL ~(1 << 3) +#else +#define MG7_7_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_7PL) || (G7_5PL == 0) +#define MG7_7_15PL ~(1 << 4) +#else +#define MG7_7_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_7PL) || (G7_6PL == 0) +#define MG7_7_16PL ~(1 << 5) +#else +#define MG7_7_16PL 0xFFFF +#endif + +#if (G7_8PL >= G7_7PL) || (G7_8PL == 0) +#define MG7_7_18PL ~(1 << 7) +#else +#define MG7_7_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_7PL) || (G7_9PL == 0) +#define MG7_7_19PL ~(1 << 8) +#else +#define MG7_7_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_7PL) || (G7_10PL == 0) +#define MG7_7_110PL ~(1 << 9) +#else +#define MG7_7_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_7PL) || (G7_11PL == 0) +#define MG7_7_111PL ~(1 << 10) +#else +#define MG7_7_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_7PL) || (G7_12PL == 0) +#define MG7_7_112PL ~(1 << 11) +#else +#define MG7_7_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_7PL) || (G7_13PL == 0) +#define MG7_7_113PL ~(1 << 12) +#else +#define MG7_7_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_7PL) || (G7_14PL == 0) +#define MG7_7_114PL ~(1 << 13) +#else +#define MG7_7_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_7PL) || (G7_15PL == 0) +#define MG7_7_115PL ~(1 << 14) +#else +#define MG7_7_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_7PL) || (G7_16PL == 0) +#define MG7_7_116PL ~(1 << 15) +#else +#define MG7_7_116PL 0xFFFF +#endif + +#define MG7_7_17PL 0xFFBF +#define MG7_7 (MG7_7_11PL & MG7_7_12PL & MG7_7_13PL & MG7_7_14PL & \ + MG7_7_15PL & MG7_7_16PL & MG7_7_17PL & MG7_7_18PL & \ + MG7_7_19PL & MG7_7_110PL & MG7_7_111PL & MG7_7_112PL & \ + MG7_7_113PL & MG7_7_114PL & MG7_7_115PL & MG7_7_116PL) +// End of MG7_7: +// Beginning of MG78: +#if (G7_1PL >= G7_8PL) || (G7_1PL == 0) +#define MG7_8_11PL ~(1 << 0) +#else +#define MG7_8_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_8PL) || (G7_2PL == 0) +#define MG7_8_12PL ~(1 << 1) +#else +#define MG7_8_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_8PL) || (G7_3PL == 0) +#define MG7_8_13PL ~(1 << 2) +#else +#define MG7_8_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_8PL) || (G7_4PL == 0) +#define MG7_8_14PL ~(1 << 3) +#else +#define MG7_8_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_8PL) || (G7_5PL == 0) +#define MG7_8_15PL ~(1 << 4) +#else +#define MG7_8_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_8PL) || (G7_6PL == 0) +#define MG7_8_16PL ~(1 << 5) +#else +#define MG7_8_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_8PL) || (G7_7PL == 0) +#define MG7_8_17PL ~(1 << 6) +#else +#define MG7_8_17PL 0xFFFF +#endif + +#if (G7_9PL >= G7_8PL) || (G7_9PL == 0) +#define MG7_8_19PL ~(1 << 8) +#else +#define MG7_8_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_8PL) || (G7_10PL == 0) +#define MG7_8_110PL ~(1 << 9) +#else +#define MG7_8_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_8PL) || (G7_11PL == 0) +#define MG7_8_111PL ~(1 << 10) +#else +#define MG7_8_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_8PL) || (G7_12PL == 0) +#define MG7_8_112PL ~(1 << 11) +#else +#define MG7_8_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_8PL) || (G7_13PL == 0) +#define MG7_8_113PL ~(1 << 12) +#else +#define MG7_8_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_8PL) || (G7_14PL == 0) +#define MG7_8_114PL ~(1 << 13) +#else +#define MG7_8_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_8PL) || (G7_15PL == 0) +#define MG7_8_115PL ~(1 << 14) +#else +#define MG7_8_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_8PL) || (G7_16PL == 0) +#define MG7_8_116PL ~(1 << 15) +#else +#define MG7_8_116PL 0xFFFF +#endif + +#define MG7_8_18PL 0xFF7F +#define MG7_8 (MG7_8_11PL & MG7_8_12PL & MG7_8_13PL & MG7_8_14PL & \ + MG7_8_15PL & MG7_8_16PL & MG7_8_17PL & MG7_8_18PL & \ + MG7_8_19PL & MG7_8_110PL & MG7_8_111PL & MG7_8_112PL & \ + MG7_8_113PL & MG7_8_114PL & MG7_8_115PL & MG7_8_116PL) +// End of MG7_8: +// Beginning of MG79: +#if (G7_1PL >= G7_9PL) || (G7_1PL == 0) +#define MG7_9_11PL ~(1 << 0) +#else +#define MG7_9_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_9PL) || (G7_2PL == 0) +#define MG7_9_12PL ~(1 << 1) +#else +#define MG7_9_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_9PL) || (G7_3PL == 0) +#define MG7_9_13PL ~(1 << 2) +#else +#define MG7_9_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_9PL) || (G7_4PL == 0) +#define MG7_9_14PL ~(1 << 3) +#else +#define MG7_9_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_9PL) || (G7_5PL == 0) +#define MG7_9_15PL ~(1 << 4) +#else +#define MG7_9_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_9PL) || (G7_6PL == 0) +#define MG7_9_16PL ~(1 << 5) +#else +#define MG7_9_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_9PL) || (G7_7PL == 0) +#define MG7_9_17PL ~(1 << 6) +#else +#define MG7_9_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_9PL) || (G7_8PL == 0) +#define MG7_9_18PL ~(1 << 7) +#else +#define MG7_9_18PL 0xFFFF +#endif + +#if (G7_10PL >= G7_9PL) || (G7_10PL == 0) +#define MG7_9_110PL ~(1 << 9) +#else +#define MG7_9_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_9PL) || (G7_11PL == 0) +#define MG7_9_111PL ~(1 << 10) +#else +#define MG7_9_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_9PL) || (G7_12PL == 0) +#define MG7_9_112PL ~(1 << 11) +#else +#define MG7_9_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_9PL) || (G7_13PL == 0) +#define MG7_9_113PL ~(1 << 12) +#else +#define MG7_9_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_9PL) || (G7_14PL == 0) +#define MG7_9_114PL ~(1 << 13) +#else +#define MG7_9_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_9PL) || (G7_15PL == 0) +#define MG7_9_115PL ~(1 << 14) +#else +#define MG7_9_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_9PL) || (G7_16PL == 0) +#define MG7_9_116PL ~(1 << 15) +#else +#define MG7_9_116PL 0xFFFF +#endif + +#define MG7_9_19PL 0xFEFF +#define MG7_9 (MG7_9_11PL & MG7_9_12PL & MG7_9_13PL & MG7_9_14PL & \ + MG7_9_15PL & MG7_9_16PL & MG7_9_17PL & MG7_9_18PL & \ + MG7_9_19PL & MG7_9_110PL & MG7_9_111PL & MG7_9_112PL & \ + MG7_9_113PL & MG7_9_114PL & MG7_9_115PL & MG7_9_116PL) +// End of MG7_9: +// Beginning of MG710: +#if (G7_1PL >= G7_10PL) || (G7_1PL == 0) +#define MG7_10_11PL ~(1 << 0) +#else +#define MG7_10_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_10PL) || (G7_2PL == 0) +#define MG7_10_12PL ~(1 << 1) +#else +#define MG7_10_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_10PL) || (G7_3PL == 0) +#define MG7_10_13PL ~(1 << 2) +#else +#define MG7_10_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_10PL) || (G7_4PL == 0) +#define MG7_10_14PL ~(1 << 3) +#else +#define MG7_10_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_10PL) || (G7_5PL == 0) +#define MG7_10_15PL ~(1 << 4) +#else +#define MG7_10_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_10PL) || (G7_6PL == 0) +#define MG7_10_16PL ~(1 << 5) +#else +#define MG7_10_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_10PL) || (G7_7PL == 0) +#define MG7_10_17PL ~(1 << 6) +#else +#define MG7_10_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_10PL) || (G7_8PL == 0) +#define MG7_10_18PL ~(1 << 7) +#else +#define MG7_10_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_10PL) || (G7_9PL == 0) +#define MG7_10_19PL ~(1 << 8) +#else +#define MG7_10_19PL 0xFFFF +#endif + +#if (G7_11PL >= G7_10PL) || (G7_11PL == 0) +#define MG7_10_111PL ~(1 << 10) +#else +#define MG7_10_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_10PL) || (G7_12PL == 0) +#define MG7_10_112PL ~(1 << 11) +#else +#define MG7_10_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_10PL) || (G7_13PL == 0) +#define MG7_10_113PL ~(1 << 12) +#else +#define MG7_10_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_10PL) || (G7_14PL == 0) +#define MG7_10_114PL ~(1 << 13) +#else +#define MG7_10_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_10PL) || (G7_15PL == 0) +#define MG7_10_115PL ~(1 << 14) +#else +#define MG7_10_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_10PL) || (G7_16PL == 0) +#define MG7_10_116PL ~(1 << 15) +#else +#define MG7_10_116PL 0xFFFF +#endif + +#define MG7_10_110PL 0xFDFF +#define MG7_10 (MG7_10_11PL & MG7_10_12PL & MG7_10_13PL & MG7_10_14PL & \ + MG7_10_15PL & MG7_10_16PL & MG7_10_17PL & MG7_10_18PL & \ + MG7_10_19PL & MG7_10_110PL & MG7_10_111PL & MG7_10_112PL & \ + MG7_10_113PL & MG7_10_114PL & MG7_10_115PL & MG7_10_116PL) +// End of MG7_10: +// Beginning of MG711: +#if (G7_1PL >= G7_11PL) || (G7_1PL == 0) +#define MG7_11_11PL ~(1 << 0) +#else +#define MG7_11_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_11PL) || (G7_2PL == 0) +#define MG7_11_12PL ~(1 << 1) +#else +#define MG7_11_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_11PL) || (G7_3PL == 0) +#define MG7_11_13PL ~(1 << 2) +#else +#define MG7_11_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_11PL) || (G7_4PL == 0) +#define MG7_11_14PL ~(1 << 3) +#else +#define MG7_11_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_11PL) || (G7_5PL == 0) +#define MG7_11_15PL ~(1 << 4) +#else +#define MG7_11_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_11PL) || (G7_6PL == 0) +#define MG7_11_16PL ~(1 << 5) +#else +#define MG7_11_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_11PL) || (G7_7PL == 0) +#define MG7_11_17PL ~(1 << 6) +#else +#define MG7_11_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_11PL) || (G7_8PL == 0) +#define MG7_11_18PL ~(1 << 7) +#else +#define MG7_11_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_11PL) || (G7_9PL == 0) +#define MG7_11_19PL ~(1 << 8) +#else +#define MG7_11_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_11PL) || (G7_10PL == 0) +#define MG7_11_110PL ~(1 << 9) +#else +#define MG7_11_110PL 0xFFFF +#endif + +#if (G7_12PL >= G7_11PL) || (G7_12PL == 0) +#define MG7_11_112PL ~(1 << 11) +#else +#define MG7_11_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_11PL) || (G7_13PL == 0) +#define MG7_11_113PL ~(1 << 12) +#else +#define MG7_11_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_11PL) || (G7_14PL == 0) +#define MG7_11_114PL ~(1 << 13) +#else +#define MG7_11_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_11PL) || (G7_15PL == 0) +#define MG7_11_115PL ~(1 << 14) +#else +#define MG7_11_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_11PL) || (G7_16PL == 0) +#define MG7_11_116PL ~(1 << 15) +#else +#define MG7_11_116PL 0xFFFF +#endif + +#define MG7_11_111PL 0xFBFF +#define MG7_11 (MG7_11_11PL & MG7_11_12PL & MG7_11_13PL & MG7_11_14PL & \ + MG7_11_15PL & MG7_11_16PL & MG7_11_17PL & MG7_11_18PL & \ + MG7_11_19PL & MG7_11_110PL & MG7_11_111PL & MG7_11_112PL & \ + MG7_11_113PL & MG7_11_114PL & MG7_11_115PL & MG7_11_116PL) +// End of MG7_11: +// Beginning of MG712: +#if (G7_1PL >= G7_12PL) || (G7_1PL == 0) +#define MG7_12_11PL ~(1 << 0) +#else +#define MG7_12_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_12PL) || (G7_2PL == 0) +#define MG7_12_12PL ~(1 << 1) +#else +#define MG7_12_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_12PL) || (G7_3PL == 0) +#define MG7_12_13PL ~(1 << 2) +#else +#define MG7_12_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_12PL) || (G7_4PL == 0) +#define MG7_12_14PL ~(1 << 3) +#else +#define MG7_12_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_12PL) || (G7_5PL == 0) +#define MG7_12_15PL ~(1 << 4) +#else +#define MG7_12_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_12PL) || (G7_6PL == 0) +#define MG7_12_16PL ~(1 << 5) +#else +#define MG7_12_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_12PL) || (G7_7PL == 0) +#define MG7_12_17PL ~(1 << 6) +#else +#define MG7_12_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_12PL) || (G7_8PL == 0) +#define MG7_12_18PL ~(1 << 7) +#else +#define MG7_12_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_12PL) || (G7_9PL == 0) +#define MG7_12_19PL ~(1 << 8) +#else +#define MG7_12_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_12PL) || (G7_10PL == 0) +#define MG7_12_110PL ~(1 << 9) +#else +#define MG7_12_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_12PL) || (G7_11PL == 0) +#define MG7_12_111PL ~(1 << 10) +#else +#define MG7_12_111PL 0xFFFF +#endif + +#if (G7_13PL >= G7_12PL) || (G7_13PL == 0) +#define MG7_12_113PL ~(1 << 12) +#else +#define MG7_12_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_12PL) || (G7_14PL == 0) +#define MG7_12_114PL ~(1 << 13) +#else +#define MG7_12_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_12PL) || (G7_15PL == 0) +#define MG7_12_115PL ~(1 << 14) +#else +#define MG7_12_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_12PL) || (G7_16PL == 0) +#define MG7_12_116PL ~(1 << 15) +#else +#define MG7_12_116PL 0xFFFF +#endif + +#define MG7_12_112PL 0xF7FF +#define MG7_12 (MG7_12_11PL & MG7_12_12PL & MG7_12_13PL & MG7_12_14PL & \ + MG7_12_15PL & MG7_12_16PL & MG7_12_17PL & MG7_12_18PL & \ + MG7_12_19PL & MG7_12_110PL & MG7_12_111PL & MG7_12_112PL & \ + MG7_12_113PL & MG7_12_114PL & MG7_12_115PL & MG7_12_116PL) +// End of MG7_12: +// Beginning of MG713: +#if (G7_1PL >= G7_13PL) || (G7_1PL == 0) +#define MG7_13_11PL ~(1 << 0) +#else +#define MG7_13_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_13PL) || (G7_2PL == 0) +#define MG7_13_12PL ~(1 << 1) +#else +#define MG7_13_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_13PL) || (G7_3PL == 0) +#define MG7_13_13PL ~(1 << 2) +#else +#define MG7_13_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_13PL) || (G7_4PL == 0) +#define MG7_13_14PL ~(1 << 3) +#else +#define MG7_13_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_13PL) || (G7_5PL == 0) +#define MG7_13_15PL ~(1 << 4) +#else +#define MG7_13_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_13PL) || (G7_6PL == 0) +#define MG7_13_16PL ~(1 << 5) +#else +#define MG7_13_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_13PL) || (G7_7PL == 0) +#define MG7_13_17PL ~(1 << 6) +#else +#define MG7_13_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_13PL) || (G7_8PL == 0) +#define MG7_13_18PL ~(1 << 7) +#else +#define MG7_13_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_13PL) || (G7_9PL == 0) +#define MG7_13_19PL ~(1 << 8) +#else +#define MG7_13_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_13PL) || (G7_10PL == 0) +#define MG7_13_110PL ~(1 << 9) +#else +#define MG7_13_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_13PL) || (G7_11PL == 0) +#define MG7_13_111PL ~(1 << 10) +#else +#define MG7_13_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_13PL) || (G7_12PL == 0) +#define MG7_13_112PL ~(1 << 11) +#else +#define MG7_13_112PL 0xFFFF +#endif + +#if (G7_14PL >= G7_13PL) || (G7_14PL == 0) +#define MG7_13_114PL ~(1 << 13) +#else +#define MG7_13_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_13PL) || (G7_15PL == 0) +#define MG7_13_115PL ~(1 << 14) +#else +#define MG7_13_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_13PL) || (G7_16PL == 0) +#define MG7_13_116PL ~(1 << 15) +#else +#define MG7_13_116PL 0xFFFF +#endif + +#define MG7_13_113PL 0xEFFF +#define MG7_13 (MG7_13_11PL & MG7_13_12PL & MG7_13_13PL & MG7_13_14PL & \ + MG7_13_15PL & MG7_13_16PL & MG7_13_17PL & MG7_13_18PL & \ + MG7_13_19PL & MG7_13_110PL & MG7_13_111PL & MG7_13_112PL & \ + MG7_13_113PL & MG7_13_114PL & MG7_13_115PL & MG7_13_116PL) +// End of MG7_13: +// Beginning of MG714: +#if (G7_1PL >= G7_14PL) || (G7_1PL == 0) +#define MG7_14_11PL ~(1 << 0) +#else +#define MG7_14_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_14PL) || (G7_2PL == 0) +#define MG7_14_12PL ~(1 << 1) +#else +#define MG7_14_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_14PL) || (G7_3PL == 0) +#define MG7_14_13PL ~(1 << 2) +#else +#define MG7_14_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_14PL) || (G7_4PL == 0) +#define MG7_14_14PL ~(1 << 3) +#else +#define MG7_14_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_14PL) || (G7_5PL == 0) +#define MG7_14_15PL ~(1 << 4) +#else +#define MG7_14_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_14PL) || (G7_6PL == 0) +#define MG7_14_16PL ~(1 << 5) +#else +#define MG7_14_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_14PL) || (G7_7PL == 0) +#define MG7_14_17PL ~(1 << 6) +#else +#define MG7_14_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_14PL) || (G7_8PL == 0) +#define MG7_14_18PL ~(1 << 7) +#else +#define MG7_14_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_14PL) || (G7_9PL == 0) +#define MG7_14_19PL ~(1 << 8) +#else +#define MG7_14_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_14PL) || (G7_10PL == 0) +#define MG7_14_110PL ~(1 << 9) +#else +#define MG7_14_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_14PL) || (G7_11PL == 0) +#define MG7_14_111PL ~(1 << 10) +#else +#define MG7_14_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_14PL) || (G7_12PL == 0) +#define MG7_14_112PL ~(1 << 11) +#else +#define MG7_14_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_14PL) || (G7_13PL == 0) +#define MG7_14_113PL ~(1 << 12) +#else +#define MG7_14_113PL 0xFFFF +#endif + +#if (G7_15PL >= G7_14PL) || (G7_15PL == 0) +#define MG7_14_115PL ~(1 << 14) +#else +#define MG7_14_115PL 0xFFFF +#endif + +#if (G7_16PL >= G7_14PL) || (G7_16PL == 0) +#define MG7_14_116PL ~(1 << 15) +#else +#define MG7_14_116PL 0xFFFF +#endif + +#define MG7_14_114PL 0xDFFF +#define MG7_14 (MG7_14_11PL & MG7_14_12PL & MG7_14_13PL & MG7_14_14PL & \ + MG7_14_15PL & MG7_14_16PL & MG7_14_17PL & MG7_14_18PL & \ + MG7_14_19PL & MG7_14_110PL & MG7_14_111PL & MG7_14_112PL & \ + MG7_14_113PL & MG7_14_114PL & MG7_14_115PL & MG7_14_116PL) +// End of MG7_14: +// Beginning of MG715: +#if (G7_1PL >= G7_15PL) || (G7_1PL == 0) +#define MG7_15_11PL ~(1 << 0) +#else +#define MG7_15_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_15PL) || (G7_2PL == 0) +#define MG7_15_12PL ~(1 << 1) +#else +#define MG7_15_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_15PL) || (G7_3PL == 0) +#define MG7_15_13PL ~(1 << 2) +#else +#define MG7_15_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_15PL) || (G7_4PL == 0) +#define MG7_15_14PL ~(1 << 3) +#else +#define MG7_15_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_15PL) || (G7_5PL == 0) +#define MG7_15_15PL ~(1 << 4) +#else +#define MG7_15_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_15PL) || (G7_6PL == 0) +#define MG7_15_16PL ~(1 << 5) +#else +#define MG7_15_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_15PL) || (G7_7PL == 0) +#define MG7_15_17PL ~(1 << 6) +#else +#define MG7_15_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_15PL) || (G7_8PL == 0) +#define MG7_15_18PL ~(1 << 7) +#else +#define MG7_15_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_15PL) || (G7_9PL == 0) +#define MG7_15_19PL ~(1 << 8) +#else +#define MG7_15_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_15PL) || (G7_10PL == 0) +#define MG7_15_110PL ~(1 << 9) +#else +#define MG7_15_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_15PL) || (G7_11PL == 0) +#define MG7_15_111PL ~(1 << 10) +#else +#define MG7_15_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_15PL) || (G7_12PL == 0) +#define MG7_15_112PL ~(1 << 11) +#else +#define MG7_15_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_15PL) || (G7_13PL == 0) +#define MG7_15_113PL ~(1 << 12) +#else +#define MG7_15_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_15PL) || (G7_14PL == 0) +#define MG7_15_114PL ~(1 << 13) +#else +#define MG7_15_114PL 0xFFFF +#endif + +#if (G7_16PL >= G7_15PL) || (G7_16PL == 0) +#define MG7_15_116PL ~(1 << 15) +#else +#define MG7_15_116PL 0xFFFF +#endif + +#define MG7_15_115PL 0xBFFF +#define MG7_15 (MG7_15_11PL & MG7_15_12PL & MG7_15_13PL & MG7_15_14PL & \ + MG7_15_15PL & MG7_15_16PL & MG7_15_17PL & MG7_15_18PL & \ + MG7_15_19PL & MG7_15_110PL & MG7_15_111PL & MG7_15_112PL & \ + MG7_15_113PL & MG7_15_114PL & MG7_15_115PL & MG7_15_116PL) +// End of MG7_15: +// Beginning of MG716: +#if (G7_1PL >= G7_16PL) || (G7_1PL == 0) +#define MG7_16_11PL ~(1 << 0) +#else +#define MG7_16_11PL 0xFFFF +#endif + +#if (G7_2PL >= G7_16PL) || (G7_2PL == 0) +#define MG7_16_12PL ~(1 << 1) +#else +#define MG7_16_12PL 0xFFFF +#endif + +#if (G7_3PL >= G7_16PL) || (G7_3PL == 0) +#define MG7_16_13PL ~(1 << 2) +#else +#define MG7_16_13PL 0xFFFF +#endif + +#if (G7_4PL >= G7_16PL) || (G7_4PL == 0) +#define MG7_16_14PL ~(1 << 3) +#else +#define MG7_16_14PL 0xFFFF +#endif + +#if (G7_5PL >= G7_16PL) || (G7_5PL == 0) +#define MG7_16_15PL ~(1 << 4) +#else +#define MG7_16_15PL 0xFFFF +#endif + +#if (G7_6PL >= G7_16PL) || (G7_6PL == 0) +#define MG7_16_16PL ~(1 << 5) +#else +#define MG7_16_16PL 0xFFFF +#endif + +#if (G7_7PL >= G7_16PL) || (G7_7PL == 0) +#define MG7_16_17PL ~(1 << 6) +#else +#define MG7_16_17PL 0xFFFF +#endif + +#if (G7_8PL >= G7_16PL) || (G7_8PL == 0) +#define MG7_16_18PL ~(1 << 7) +#else +#define MG7_16_18PL 0xFFFF +#endif + +#if (G7_9PL >= G7_16PL) || (G7_9PL == 0) +#define MG7_16_19PL ~(1 << 8) +#else +#define MG7_16_19PL 0xFFFF +#endif + +#if (G7_10PL >= G7_16PL) || (G7_10PL == 0) +#define MG7_16_110PL ~(1 << 9) +#else +#define MG7_16_110PL 0xFFFF +#endif + +#if (G7_11PL >= G7_16PL) || (G7_11PL == 0) +#define MG7_16_111PL ~(1 << 10) +#else +#define MG7_16_111PL 0xFFFF +#endif + +#if (G7_12PL >= G7_16PL) || (G7_12PL == 0) +#define MG7_16_112PL ~(1 << 11) +#else +#define MG7_16_112PL 0xFFFF +#endif + +#if (G7_13PL >= G7_16PL) || (G7_13PL == 0) +#define MG7_16_113PL ~(1 << 12) +#else +#define MG7_16_113PL 0xFFFF +#endif + +#if (G7_14PL >= G7_16PL) || (G7_14PL == 0) +#define MG7_16_114PL ~(1 << 13) +#else +#define MG7_16_114PL 0xFFFF +#endif + +#if (G7_15PL >= G7_16PL) || (G7_15PL == 0) +#define MG7_16_115PL ~(1 << 14) +#else +#define MG7_16_115PL 0xFFFF +#endif + +#define MG7_16_116PL 0x7FFF +#define MG7_16 (MG7_16_11PL & MG7_16_12PL & MG7_16_13PL & MG7_16_14PL & \ + MG7_16_15PL & MG7_16_16PL & MG7_16_17PL & MG7_16_18PL & \ + MG7_16_19PL & MG7_16_110PL & MG7_16_111PL & MG7_16_112PL & \ + MG7_16_113PL & MG7_16_114PL & MG7_16_115PL & MG7_16_116PL) +// End of MG7_16: + + +// +// Automatically generate PIEIER8 interrupt masks MG81 to MG816: +// + +// Beginning of MG81: +#if (G8_2PL >= G8_1PL) || (G8_2PL == 0) +#define MG8_1_12PL ~(1 << 1) +#else +#define MG8_1_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_1PL) || (G8_3PL == 0) +#define MG8_1_13PL ~(1 << 2) +#else +#define MG8_1_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_1PL) || (G8_4PL == 0) +#define MG8_1_14PL ~(1 << 3) +#else +#define MG8_1_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_1PL) || (G8_5PL == 0) +#define MG8_1_15PL ~(1 << 4) +#else +#define MG8_1_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_1PL) || (G8_6PL == 0) +#define MG8_1_16PL ~(1 << 5) +#else +#define MG8_1_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_1PL) || (G8_7PL == 0) +#define MG8_1_17PL ~(1 << 6) +#else +#define MG8_1_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_1PL) || (G8_8PL == 0) +#define MG8_1_18PL ~(1 << 7) +#else +#define MG8_1_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_1PL) || (G8_9PL == 0) +#define MG8_1_19PL ~(1 << 8) +#else +#define MG8_1_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_1PL) || (G8_10PL == 0) +#define MG8_1_110PL ~(1 << 9) +#else +#define MG8_1_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_1PL) || (G8_11PL == 0) +#define MG8_1_111PL ~(1 << 10) +#else +#define MG8_1_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_1PL) || (G8_12PL == 0) +#define MG8_1_112PL ~(1 << 11) +#else +#define MG8_1_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_1PL) || (G8_13PL == 0) +#define MG8_1_113PL ~(1 << 12) +#else +#define MG8_1_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_1PL) || (G8_14PL == 0) +#define MG8_1_114PL ~(1 << 13) +#else +#define MG8_1_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_1PL) || (G8_15PL == 0) +#define MG8_1_115PL ~(1 << 14) +#else +#define MG8_1_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_1PL) || (G8_16PL == 0) +#define MG8_1_116PL ~(1 << 15) +#else +#define MG8_1_116PL 0xFFFF +#endif + +#define MG8_1_11PL 0xFFFE +#define MG8_1 (MG8_1_11PL & MG8_1_12PL & MG8_1_13PL & MG8_1_14PL & \ + MG8_1_15PL & MG8_1_16PL & MG8_1_17PL & MG8_1_18PL & \ + MG8_1_19PL & MG8_1_110PL & MG8_1_111PL & MG8_1_112PL & \ + MG8_1_113PL & MG8_1_114PL & MG8_1_115PL & MG8_1_116PL) +// End of MG8_1: +// Beginning of MG82: +#if (G8_1PL >= G8_2PL) || (G8_1PL == 0) +#define MG8_2_11PL ~(1 << 0) +#else +#define MG8_2_11PL 0xFFFF +#endif + +#if (G8_3PL >= G8_2PL) || (G8_3PL == 0) +#define MG8_2_13PL ~(1 << 2) +#else +#define MG8_2_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_2PL) || (G8_4PL == 0) +#define MG8_2_14PL ~(1 << 3) +#else +#define MG8_2_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_2PL) || (G8_5PL == 0) +#define MG8_2_15PL ~(1 << 4) +#else +#define MG8_2_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_2PL) || (G8_6PL == 0) +#define MG8_2_16PL ~(1 << 5) +#else +#define MG8_2_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_2PL) || (G8_7PL == 0) +#define MG8_2_17PL ~(1 << 6) +#else +#define MG8_2_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_2PL) || (G8_8PL == 0) +#define MG8_2_18PL ~(1 << 7) +#else +#define MG8_2_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_2PL) || (G8_9PL == 0) +#define MG8_2_19PL ~(1 << 8) +#else +#define MG8_2_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_2PL) || (G8_10PL == 0) +#define MG8_2_110PL ~(1 << 9) +#else +#define MG8_2_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_2PL) || (G8_11PL == 0) +#define MG8_2_111PL ~(1 << 10) +#else +#define MG8_2_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_2PL) || (G8_12PL == 0) +#define MG8_2_112PL ~(1 << 11) +#else +#define MG8_2_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_2PL) || (G8_13PL == 0) +#define MG8_2_113PL ~(1 << 12) +#else +#define MG8_2_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_2PL) || (G8_14PL == 0) +#define MG8_2_114PL ~(1 << 13) +#else +#define MG8_2_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_2PL) || (G8_15PL == 0) +#define MG8_2_115PL ~(1 << 14) +#else +#define MG8_2_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_2PL) || (G8_16PL == 0) +#define MG8_2_116PL ~(1 << 15) +#else +#define MG8_2_116PL 0xFFFF +#endif + +#define MG8_2_12PL 0xFFFD +#define MG8_2 (MG8_2_11PL & MG8_2_12PL & MG8_2_13PL & MG8_2_14PL & \ + MG8_2_15PL & MG8_2_16PL & MG8_2_17PL & MG8_2_18PL & \ + MG8_2_19PL & MG8_2_110PL & MG8_2_111PL & MG8_2_112PL & \ + MG8_2_113PL & MG8_2_114PL & MG8_2_115PL & MG8_2_116PL) +// End of MG8_2: +// Beginning of MG83: +#if (G8_1PL >= G8_3PL) || (G8_1PL == 0) +#define MG8_3_11PL ~(1 << 0) +#else +#define MG8_3_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_3PL) || (G8_2PL == 0) +#define MG8_3_12PL ~(1 << 1) +#else +#define MG8_3_12PL 0xFFFF +#endif + +#if (G8_4PL >= G8_3PL) || (G8_4PL == 0) +#define MG8_3_14PL ~(1 << 3) +#else +#define MG8_3_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_3PL) || (G8_5PL == 0) +#define MG8_3_15PL ~(1 << 4) +#else +#define MG8_3_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_3PL) || (G8_6PL == 0) +#define MG8_3_16PL ~(1 << 5) +#else +#define MG8_3_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_3PL) || (G8_7PL == 0) +#define MG8_3_17PL ~(1 << 6) +#else +#define MG8_3_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_3PL) || (G8_8PL == 0) +#define MG8_3_18PL ~(1 << 7) +#else +#define MG8_3_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_3PL) || (G8_9PL == 0) +#define MG8_3_19PL ~(1 << 8) +#else +#define MG8_3_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_3PL) || (G8_10PL == 0) +#define MG8_3_110PL ~(1 << 9) +#else +#define MG8_3_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_3PL) || (G8_11PL == 0) +#define MG8_3_111PL ~(1 << 10) +#else +#define MG8_3_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_3PL) || (G8_12PL == 0) +#define MG8_3_112PL ~(1 << 11) +#else +#define MG8_3_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_3PL) || (G8_13PL == 0) +#define MG8_3_113PL ~(1 << 12) +#else +#define MG8_3_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_3PL) || (G8_14PL == 0) +#define MG8_3_114PL ~(1 << 13) +#else +#define MG8_3_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_3PL) || (G8_15PL == 0) +#define MG8_3_115PL ~(1 << 14) +#else +#define MG8_3_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_3PL) || (G8_16PL == 0) +#define MG8_3_116PL ~(1 << 15) +#else +#define MG8_3_116PL 0xFFFF +#endif + +#define MG8_3_13PL 0xFFFB +#define MG8_3 (MG8_3_11PL & MG8_3_12PL & MG8_3_13PL & MG8_3_14PL & \ + MG8_3_15PL & MG8_3_16PL & MG8_3_17PL & MG8_3_18PL & \ + MG8_3_19PL & MG8_3_110PL & MG8_3_111PL & MG8_3_112PL & \ + MG8_3_113PL & MG8_3_114PL & MG8_3_115PL & MG8_3_116PL) +// End of MG8_3: +// Beginning of MG84: +#if (G8_1PL >= G8_4PL) || (G8_1PL == 0) +#define MG8_4_11PL ~(1 << 0) +#else +#define MG8_4_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_4PL) || (G8_2PL == 0) +#define MG8_4_12PL ~(1 << 1) +#else +#define MG8_4_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_4PL) || (G8_3PL == 0) +#define MG8_4_13PL ~(1 << 2) +#else +#define MG8_4_13PL 0xFFFF +#endif + +#if (G8_5PL >= G8_4PL) || (G8_5PL == 0) +#define MG8_4_15PL ~(1 << 4) +#else +#define MG8_4_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_4PL) || (G8_6PL == 0) +#define MG8_4_16PL ~(1 << 5) +#else +#define MG8_4_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_4PL) || (G8_7PL == 0) +#define MG8_4_17PL ~(1 << 6) +#else +#define MG8_4_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_4PL) || (G8_8PL == 0) +#define MG8_4_18PL ~(1 << 7) +#else +#define MG8_4_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_4PL) || (G8_9PL == 0) +#define MG8_4_19PL ~(1 << 8) +#else +#define MG8_4_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_4PL) || (G8_10PL == 0) +#define MG8_4_110PL ~(1 << 9) +#else +#define MG8_4_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_4PL) || (G8_11PL == 0) +#define MG8_4_111PL ~(1 << 10) +#else +#define MG8_4_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_4PL) || (G8_12PL == 0) +#define MG8_4_112PL ~(1 << 11) +#else +#define MG8_4_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_4PL) || (G8_13PL == 0) +#define MG8_4_113PL ~(1 << 12) +#else +#define MG8_4_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_4PL) || (G8_14PL == 0) +#define MG8_4_114PL ~(1 << 13) +#else +#define MG8_4_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_4PL) || (G8_15PL == 0) +#define MG8_4_115PL ~(1 << 14) +#else +#define MG8_4_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_4PL) || (G8_16PL == 0) +#define MG8_4_116PL ~(1 << 15) +#else +#define MG8_4_116PL 0xFFFF +#endif + +#define MG8_4_14PL 0xFFF7 +#define MG8_4 (MG8_4_11PL & MG8_4_12PL & MG8_4_13PL & MG8_4_14PL & \ + MG8_4_15PL & MG8_4_16PL & MG8_4_17PL & MG8_4_18PL & \ + MG8_4_19PL & MG8_4_110PL & MG8_4_111PL & MG8_4_112PL & \ + MG8_4_113PL & MG8_4_114PL & MG8_4_115PL & MG8_4_116PL) +// End of MG8_4: +// Beginning of MG85: +#if (G8_1PL >= G8_5PL) || (G8_1PL == 0) +#define MG8_5_11PL ~(1 << 0) +#else +#define MG8_5_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_5PL) || (G8_2PL == 0) +#define MG8_5_12PL ~(1 << 1) +#else +#define MG8_5_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_5PL) || (G8_3PL == 0) +#define MG8_5_13PL ~(1 << 2) +#else +#define MG8_5_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_5PL) || (G8_4PL == 0) +#define MG8_5_14PL ~(1 << 3) +#else +#define MG8_5_14PL 0xFFFF +#endif + +#if (G8_6PL >= G8_5PL) || (G8_6PL == 0) +#define MG8_5_16PL ~(1 << 5) +#else +#define MG8_5_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_5PL) || (G8_7PL == 0) +#define MG8_5_17PL ~(1 << 6) +#else +#define MG8_5_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_5PL) || (G8_8PL == 0) +#define MG8_5_18PL ~(1 << 7) +#else +#define MG8_5_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_5PL) || (G8_9PL == 0) +#define MG8_5_19PL ~(1 << 8) +#else +#define MG8_5_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_5PL) || (G8_10PL == 0) +#define MG8_5_110PL ~(1 << 9) +#else +#define MG8_5_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_5PL) || (G8_11PL == 0) +#define MG8_5_111PL ~(1 << 10) +#else +#define MG8_5_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_5PL) || (G8_12PL == 0) +#define MG8_5_112PL ~(1 << 11) +#else +#define MG8_5_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_5PL) || (G8_13PL == 0) +#define MG8_5_113PL ~(1 << 12) +#else +#define MG8_5_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_5PL) || (G8_14PL == 0) +#define MG8_5_114PL ~(1 << 13) +#else +#define MG8_5_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_5PL) || (G8_15PL == 0) +#define MG8_5_115PL ~(1 << 14) +#else +#define MG8_5_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_5PL) || (G8_16PL == 0) +#define MG8_5_116PL ~(1 << 15) +#else +#define MG8_5_116PL 0xFFFF +#endif + +#define MG8_5_15PL 0xFFEF +#define MG8_5 (MG8_5_11PL & MG8_5_12PL & MG8_5_13PL & MG8_5_14PL & \ + MG8_5_15PL & MG8_5_16PL & MG8_5_17PL & MG8_5_18PL & \ + MG8_5_19PL & MG8_5_110PL & MG8_5_111PL & MG8_5_112PL & \ + MG8_5_113PL & MG8_5_114PL & MG8_5_115PL & MG8_5_116PL) +// End of MG8_5: +// Beginning of MG86: +#if (G8_1PL >= G8_6PL) || (G8_1PL == 0) +#define MG8_6_11PL ~(1 << 0) +#else +#define MG8_6_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_6PL) || (G8_2PL == 0) +#define MG8_6_12PL ~(1 << 1) +#else +#define MG8_6_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_6PL) || (G8_3PL == 0) +#define MG8_6_13PL ~(1 << 2) +#else +#define MG8_6_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_6PL) || (G8_4PL == 0) +#define MG8_6_14PL ~(1 << 3) +#else +#define MG8_6_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_6PL) || (G8_5PL == 0) +#define MG8_6_15PL ~(1 << 4) +#else +#define MG8_6_15PL 0xFFFF +#endif + +#if (G8_7PL >= G8_6PL) || (G8_7PL == 0) +#define MG8_6_17PL ~(1 << 6) +#else +#define MG8_6_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_6PL) || (G8_8PL == 0) +#define MG8_6_18PL ~(1 << 7) +#else +#define MG8_6_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_6PL) || (G8_9PL == 0) +#define MG8_6_19PL ~(1 << 8) +#else +#define MG8_6_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_6PL) || (G8_10PL == 0) +#define MG8_6_110PL ~(1 << 9) +#else +#define MG8_6_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_6PL) || (G8_11PL == 0) +#define MG8_6_111PL ~(1 << 10) +#else +#define MG8_6_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_6PL) || (G8_12PL == 0) +#define MG8_6_112PL ~(1 << 11) +#else +#define MG8_6_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_6PL) || (G8_13PL == 0) +#define MG8_6_113PL ~(1 << 12) +#else +#define MG8_6_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_6PL) || (G8_14PL == 0) +#define MG8_6_114PL ~(1 << 13) +#else +#define MG8_6_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_6PL) || (G8_15PL == 0) +#define MG8_6_115PL ~(1 << 14) +#else +#define MG8_6_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_6PL) || (G8_16PL == 0) +#define MG8_6_116PL ~(1 << 15) +#else +#define MG8_6_116PL 0xFFFF +#endif + +#define MG8_6_16PL 0xFFDF +#define MG8_6 (MG8_6_11PL & MG8_6_12PL & MG8_6_13PL & MG8_6_14PL & \ + MG8_6_15PL & MG8_6_16PL & MG8_6_17PL & MG8_6_18PL & \ + MG8_6_19PL & MG8_6_110PL & MG8_6_111PL & MG8_6_112PL & \ + MG8_6_113PL & MG8_6_114PL & MG8_6_115PL & MG8_6_116PL) +// End of MG8_6: +// Beginning of MG87: +#if (G8_1PL >= G8_7PL) || (G8_1PL == 0) +#define MG8_7_11PL ~(1 << 0) +#else +#define MG8_7_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_7PL) || (G8_2PL == 0) +#define MG8_7_12PL ~(1 << 1) +#else +#define MG8_7_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_7PL) || (G8_3PL == 0) +#define MG8_7_13PL ~(1 << 2) +#else +#define MG8_7_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_7PL) || (G8_4PL == 0) +#define MG8_7_14PL ~(1 << 3) +#else +#define MG8_7_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_7PL) || (G8_5PL == 0) +#define MG8_7_15PL ~(1 << 4) +#else +#define MG8_7_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_7PL) || (G8_6PL == 0) +#define MG8_7_16PL ~(1 << 5) +#else +#define MG8_7_16PL 0xFFFF +#endif + +#if (G8_8PL >= G8_7PL) || (G8_8PL == 0) +#define MG8_7_18PL ~(1 << 7) +#else +#define MG8_7_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_7PL) || (G8_9PL == 0) +#define MG8_7_19PL ~(1 << 8) +#else +#define MG8_7_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_7PL) || (G8_10PL == 0) +#define MG8_7_110PL ~(1 << 9) +#else +#define MG8_7_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_7PL) || (G8_11PL == 0) +#define MG8_7_111PL ~(1 << 10) +#else +#define MG8_7_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_7PL) || (G8_12PL == 0) +#define MG8_7_112PL ~(1 << 11) +#else +#define MG8_7_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_7PL) || (G8_13PL == 0) +#define MG8_7_113PL ~(1 << 12) +#else +#define MG8_7_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_7PL) || (G8_14PL == 0) +#define MG8_7_114PL ~(1 << 13) +#else +#define MG8_7_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_7PL) || (G8_15PL == 0) +#define MG8_7_115PL ~(1 << 14) +#else +#define MG8_7_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_7PL) || (G8_16PL == 0) +#define MG8_7_116PL ~(1 << 15) +#else +#define MG8_7_116PL 0xFFFF +#endif + +#define MG8_7_17PL 0xFFBF +#define MG8_7 (MG8_7_11PL & MG8_7_12PL & MG8_7_13PL & MG8_7_14PL & \ + MG8_7_15PL & MG8_7_16PL & MG8_7_17PL & MG8_7_18PL & \ + MG8_7_19PL & MG8_7_110PL & MG8_7_111PL & MG8_7_112PL & \ + MG8_7_113PL & MG8_7_114PL & MG8_7_115PL & MG8_7_116PL) +// End of MG8_7: +// Beginning of MG88: +#if (G8_1PL >= G8_8PL) || (G8_1PL == 0) +#define MG8_8_11PL ~(1 << 0) +#else +#define MG8_8_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_8PL) || (G8_2PL == 0) +#define MG8_8_12PL ~(1 << 1) +#else +#define MG8_8_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_8PL) || (G8_3PL == 0) +#define MG8_8_13PL ~(1 << 2) +#else +#define MG8_8_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_8PL) || (G8_4PL == 0) +#define MG8_8_14PL ~(1 << 3) +#else +#define MG8_8_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_8PL) || (G8_5PL == 0) +#define MG8_8_15PL ~(1 << 4) +#else +#define MG8_8_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_8PL) || (G8_6PL == 0) +#define MG8_8_16PL ~(1 << 5) +#else +#define MG8_8_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_8PL) || (G8_7PL == 0) +#define MG8_8_17PL ~(1 << 6) +#else +#define MG8_8_17PL 0xFFFF +#endif + +#if (G8_9PL >= G8_8PL) || (G8_9PL == 0) +#define MG8_8_19PL ~(1 << 8) +#else +#define MG8_8_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_8PL) || (G8_10PL == 0) +#define MG8_8_110PL ~(1 << 9) +#else +#define MG8_8_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_8PL) || (G8_11PL == 0) +#define MG8_8_111PL ~(1 << 10) +#else +#define MG8_8_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_8PL) || (G8_12PL == 0) +#define MG8_8_112PL ~(1 << 11) +#else +#define MG8_8_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_8PL) || (G8_13PL == 0) +#define MG8_8_113PL ~(1 << 12) +#else +#define MG8_8_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_8PL) || (G8_14PL == 0) +#define MG8_8_114PL ~(1 << 13) +#else +#define MG8_8_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_8PL) || (G8_15PL == 0) +#define MG8_8_115PL ~(1 << 14) +#else +#define MG8_8_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_8PL) || (G8_16PL == 0) +#define MG8_8_116PL ~(1 << 15) +#else +#define MG8_8_116PL 0xFFFF +#endif + +#define MG8_8_18PL 0xFF7F +#define MG8_8 (MG8_8_11PL & MG8_8_12PL & MG8_8_13PL & MG8_8_14PL & \ + MG8_8_15PL & MG8_8_16PL & MG8_8_17PL & MG8_8_18PL & \ + MG8_8_19PL & MG8_8_110PL & MG8_8_111PL & MG8_8_112PL & \ + MG8_8_113PL & MG8_8_114PL & MG8_8_115PL & MG8_8_116PL) +// End of MG8_8: +// Beginning of MG89: +#if (G8_1PL >= G8_9PL) || (G8_1PL == 0) +#define MG8_9_11PL ~(1 << 0) +#else +#define MG8_9_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_9PL) || (G8_2PL == 0) +#define MG8_9_12PL ~(1 << 1) +#else +#define MG8_9_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_9PL) || (G8_3PL == 0) +#define MG8_9_13PL ~(1 << 2) +#else +#define MG8_9_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_9PL) || (G8_4PL == 0) +#define MG8_9_14PL ~(1 << 3) +#else +#define MG8_9_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_9PL) || (G8_5PL == 0) +#define MG8_9_15PL ~(1 << 4) +#else +#define MG8_9_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_9PL) || (G8_6PL == 0) +#define MG8_9_16PL ~(1 << 5) +#else +#define MG8_9_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_9PL) || (G8_7PL == 0) +#define MG8_9_17PL ~(1 << 6) +#else +#define MG8_9_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_9PL) || (G8_8PL == 0) +#define MG8_9_18PL ~(1 << 7) +#else +#define MG8_9_18PL 0xFFFF +#endif + +#if (G8_10PL >= G8_9PL) || (G8_10PL == 0) +#define MG8_9_110PL ~(1 << 9) +#else +#define MG8_9_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_9PL) || (G8_11PL == 0) +#define MG8_9_111PL ~(1 << 10) +#else +#define MG8_9_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_9PL) || (G8_12PL == 0) +#define MG8_9_112PL ~(1 << 11) +#else +#define MG8_9_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_9PL) || (G8_13PL == 0) +#define MG8_9_113PL ~(1 << 12) +#else +#define MG8_9_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_9PL) || (G8_14PL == 0) +#define MG8_9_114PL ~(1 << 13) +#else +#define MG8_9_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_9PL) || (G8_15PL == 0) +#define MG8_9_115PL ~(1 << 14) +#else +#define MG8_9_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_9PL) || (G8_16PL == 0) +#define MG8_9_116PL ~(1 << 15) +#else +#define MG8_9_116PL 0xFFFF +#endif + +#define MG8_9_19PL 0xFEFF +#define MG8_9 (MG8_9_11PL & MG8_9_12PL & MG8_9_13PL & MG8_9_14PL & \ + MG8_9_15PL & MG8_9_16PL & MG8_9_17PL & MG8_9_18PL & \ + MG8_9_19PL & MG8_9_110PL & MG8_9_111PL & MG8_9_112PL & \ + MG8_9_113PL & MG8_9_114PL & MG8_9_115PL & MG8_9_116PL) +// End of MG8_9: +// Beginning of MG810: +#if (G8_1PL >= G8_10PL) || (G8_1PL == 0) +#define MG8_10_11PL ~(1 << 0) +#else +#define MG8_10_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_10PL) || (G8_2PL == 0) +#define MG8_10_12PL ~(1 << 1) +#else +#define MG8_10_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_10PL) || (G8_3PL == 0) +#define MG8_10_13PL ~(1 << 2) +#else +#define MG8_10_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_10PL) || (G8_4PL == 0) +#define MG8_10_14PL ~(1 << 3) +#else +#define MG8_10_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_10PL) || (G8_5PL == 0) +#define MG8_10_15PL ~(1 << 4) +#else +#define MG8_10_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_10PL) || (G8_6PL == 0) +#define MG8_10_16PL ~(1 << 5) +#else +#define MG8_10_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_10PL) || (G8_7PL == 0) +#define MG8_10_17PL ~(1 << 6) +#else +#define MG8_10_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_10PL) || (G8_8PL == 0) +#define MG8_10_18PL ~(1 << 7) +#else +#define MG8_10_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_10PL) || (G8_9PL == 0) +#define MG8_10_19PL ~(1 << 8) +#else +#define MG8_10_19PL 0xFFFF +#endif + +#if (G8_11PL >= G8_10PL) || (G8_11PL == 0) +#define MG8_10_111PL ~(1 << 10) +#else +#define MG8_10_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_10PL) || (G8_12PL == 0) +#define MG8_10_112PL ~(1 << 11) +#else +#define MG8_10_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_10PL) || (G8_13PL == 0) +#define MG8_10_113PL ~(1 << 12) +#else +#define MG8_10_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_10PL) || (G8_14PL == 0) +#define MG8_10_114PL ~(1 << 13) +#else +#define MG8_10_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_10PL) || (G8_15PL == 0) +#define MG8_10_115PL ~(1 << 14) +#else +#define MG8_10_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_10PL) || (G8_16PL == 0) +#define MG8_10_116PL ~(1 << 15) +#else +#define MG8_10_116PL 0xFFFF +#endif + +#define MG8_10_110PL 0xFDFF +#define MG8_10 (MG8_10_11PL & MG8_10_12PL & MG8_10_13PL & MG8_10_14PL & \ + MG8_10_15PL & MG8_10_16PL & MG8_10_17PL & MG8_10_18PL & \ + MG8_10_19PL & MG8_10_110PL & MG8_10_111PL & MG8_10_112PL & \ + MG8_10_113PL & MG8_10_114PL & MG8_10_115PL & MG8_10_116PL) +// End of MG8_10: +// Beginning of MG811: +#if (G8_1PL >= G8_11PL) || (G8_1PL == 0) +#define MG8_11_11PL ~(1 << 0) +#else +#define MG8_11_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_11PL) || (G8_2PL == 0) +#define MG8_11_12PL ~(1 << 1) +#else +#define MG8_11_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_11PL) || (G8_3PL == 0) +#define MG8_11_13PL ~(1 << 2) +#else +#define MG8_11_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_11PL) || (G8_4PL == 0) +#define MG8_11_14PL ~(1 << 3) +#else +#define MG8_11_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_11PL) || (G8_5PL == 0) +#define MG8_11_15PL ~(1 << 4) +#else +#define MG8_11_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_11PL) || (G8_6PL == 0) +#define MG8_11_16PL ~(1 << 5) +#else +#define MG8_11_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_11PL) || (G8_7PL == 0) +#define MG8_11_17PL ~(1 << 6) +#else +#define MG8_11_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_11PL) || (G8_8PL == 0) +#define MG8_11_18PL ~(1 << 7) +#else +#define MG8_11_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_11PL) || (G8_9PL == 0) +#define MG8_11_19PL ~(1 << 8) +#else +#define MG8_11_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_11PL) || (G8_10PL == 0) +#define MG8_11_110PL ~(1 << 9) +#else +#define MG8_11_110PL 0xFFFF +#endif + +#if (G8_12PL >= G8_11PL) || (G8_12PL == 0) +#define MG8_11_112PL ~(1 << 11) +#else +#define MG8_11_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_11PL) || (G8_13PL == 0) +#define MG8_11_113PL ~(1 << 12) +#else +#define MG8_11_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_11PL) || (G8_14PL == 0) +#define MG8_11_114PL ~(1 << 13) +#else +#define MG8_11_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_11PL) || (G8_15PL == 0) +#define MG8_11_115PL ~(1 << 14) +#else +#define MG8_11_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_11PL) || (G8_16PL == 0) +#define MG8_11_116PL ~(1 << 15) +#else +#define MG8_11_116PL 0xFFFF +#endif + +#define MG8_11_111PL 0xFBFF +#define MG8_11 (MG8_11_11PL & MG8_11_12PL & MG8_11_13PL & MG8_11_14PL & \ + MG8_11_15PL & MG8_11_16PL & MG8_11_17PL & MG8_11_18PL & \ + MG8_11_19PL & MG8_11_110PL & MG8_11_111PL & MG8_11_112PL & \ + MG8_11_113PL & MG8_11_114PL & MG8_11_115PL & MG8_11_116PL) +// End of MG8_11: +// Beginning of MG812: +#if (G8_1PL >= G8_12PL) || (G8_1PL == 0) +#define MG8_12_11PL ~(1 << 0) +#else +#define MG8_12_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_12PL) || (G8_2PL == 0) +#define MG8_12_12PL ~(1 << 1) +#else +#define MG8_12_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_12PL) || (G8_3PL == 0) +#define MG8_12_13PL ~(1 << 2) +#else +#define MG8_12_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_12PL) || (G8_4PL == 0) +#define MG8_12_14PL ~(1 << 3) +#else +#define MG8_12_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_12PL) || (G8_5PL == 0) +#define MG8_12_15PL ~(1 << 4) +#else +#define MG8_12_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_12PL) || (G8_6PL == 0) +#define MG8_12_16PL ~(1 << 5) +#else +#define MG8_12_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_12PL) || (G8_7PL == 0) +#define MG8_12_17PL ~(1 << 6) +#else +#define MG8_12_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_12PL) || (G8_8PL == 0) +#define MG8_12_18PL ~(1 << 7) +#else +#define MG8_12_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_12PL) || (G8_9PL == 0) +#define MG8_12_19PL ~(1 << 8) +#else +#define MG8_12_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_12PL) || (G8_10PL == 0) +#define MG8_12_110PL ~(1 << 9) +#else +#define MG8_12_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_12PL) || (G8_11PL == 0) +#define MG8_12_111PL ~(1 << 10) +#else +#define MG8_12_111PL 0xFFFF +#endif + +#if (G8_13PL >= G8_12PL) || (G8_13PL == 0) +#define MG8_12_113PL ~(1 << 12) +#else +#define MG8_12_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_12PL) || (G8_14PL == 0) +#define MG8_12_114PL ~(1 << 13) +#else +#define MG8_12_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_12PL) || (G8_15PL == 0) +#define MG8_12_115PL ~(1 << 14) +#else +#define MG8_12_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_12PL) || (G8_16PL == 0) +#define MG8_12_116PL ~(1 << 15) +#else +#define MG8_12_116PL 0xFFFF +#endif + +#define MG8_12_112PL 0xF7FF +#define MG8_12 (MG8_12_11PL & MG8_12_12PL & MG8_12_13PL & MG8_12_14PL & \ + MG8_12_15PL & MG8_12_16PL & MG8_12_17PL & MG8_12_18PL & \ + MG8_12_19PL & MG8_12_110PL & MG8_12_111PL & MG8_12_112PL & \ + MG8_12_113PL & MG8_12_114PL & MG8_12_115PL & MG8_12_116PL) +// End of MG8_12: +// Beginning of MG813: +#if (G8_1PL >= G8_13PL) || (G8_1PL == 0) +#define MG8_13_11PL ~(1 << 0) +#else +#define MG8_13_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_13PL) || (G8_2PL == 0) +#define MG8_13_12PL ~(1 << 1) +#else +#define MG8_13_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_13PL) || (G8_3PL == 0) +#define MG8_13_13PL ~(1 << 2) +#else +#define MG8_13_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_13PL) || (G8_4PL == 0) +#define MG8_13_14PL ~(1 << 3) +#else +#define MG8_13_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_13PL) || (G8_5PL == 0) +#define MG8_13_15PL ~(1 << 4) +#else +#define MG8_13_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_13PL) || (G8_6PL == 0) +#define MG8_13_16PL ~(1 << 5) +#else +#define MG8_13_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_13PL) || (G8_7PL == 0) +#define MG8_13_17PL ~(1 << 6) +#else +#define MG8_13_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_13PL) || (G8_8PL == 0) +#define MG8_13_18PL ~(1 << 7) +#else +#define MG8_13_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_13PL) || (G8_9PL == 0) +#define MG8_13_19PL ~(1 << 8) +#else +#define MG8_13_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_13PL) || (G8_10PL == 0) +#define MG8_13_110PL ~(1 << 9) +#else +#define MG8_13_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_13PL) || (G8_11PL == 0) +#define MG8_13_111PL ~(1 << 10) +#else +#define MG8_13_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_13PL) || (G8_12PL == 0) +#define MG8_13_112PL ~(1 << 11) +#else +#define MG8_13_112PL 0xFFFF +#endif + +#if (G8_14PL >= G8_13PL) || (G8_14PL == 0) +#define MG8_13_114PL ~(1 << 13) +#else +#define MG8_13_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_13PL) || (G8_15PL == 0) +#define MG8_13_115PL ~(1 << 14) +#else +#define MG8_13_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_13PL) || (G8_16PL == 0) +#define MG8_13_116PL ~(1 << 15) +#else +#define MG8_13_116PL 0xFFFF +#endif + +#define MG8_13_113PL 0xEFFF +#define MG8_13 (MG8_13_11PL & MG8_13_12PL & MG8_13_13PL & MG8_13_14PL & \ + MG8_13_15PL & MG8_13_16PL & MG8_13_17PL & MG8_13_18PL & \ + MG8_13_19PL & MG8_13_110PL & MG8_13_111PL & MG8_13_112PL & \ + MG8_13_113PL & MG8_13_114PL & MG8_13_115PL & MG8_13_116PL) +// End of MG8_13: +// Beginning of MG814: +#if (G8_1PL >= G8_14PL) || (G8_1PL == 0) +#define MG8_14_11PL ~(1 << 0) +#else +#define MG8_14_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_14PL) || (G8_2PL == 0) +#define MG8_14_12PL ~(1 << 1) +#else +#define MG8_14_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_14PL) || (G8_3PL == 0) +#define MG8_14_13PL ~(1 << 2) +#else +#define MG8_14_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_14PL) || (G8_4PL == 0) +#define MG8_14_14PL ~(1 << 3) +#else +#define MG8_14_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_14PL) || (G8_5PL == 0) +#define MG8_14_15PL ~(1 << 4) +#else +#define MG8_14_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_14PL) || (G8_6PL == 0) +#define MG8_14_16PL ~(1 << 5) +#else +#define MG8_14_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_14PL) || (G8_7PL == 0) +#define MG8_14_17PL ~(1 << 6) +#else +#define MG8_14_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_14PL) || (G8_8PL == 0) +#define MG8_14_18PL ~(1 << 7) +#else +#define MG8_14_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_14PL) || (G8_9PL == 0) +#define MG8_14_19PL ~(1 << 8) +#else +#define MG8_14_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_14PL) || (G8_10PL == 0) +#define MG8_14_110PL ~(1 << 9) +#else +#define MG8_14_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_14PL) || (G8_11PL == 0) +#define MG8_14_111PL ~(1 << 10) +#else +#define MG8_14_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_14PL) || (G8_12PL == 0) +#define MG8_14_112PL ~(1 << 11) +#else +#define MG8_14_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_14PL) || (G8_13PL == 0) +#define MG8_14_113PL ~(1 << 12) +#else +#define MG8_14_113PL 0xFFFF +#endif + +#if (G8_15PL >= G8_14PL) || (G8_15PL == 0) +#define MG8_14_115PL ~(1 << 14) +#else +#define MG8_14_115PL 0xFFFF +#endif + +#if (G8_16PL >= G8_14PL) || (G8_16PL == 0) +#define MG8_14_116PL ~(1 << 15) +#else +#define MG8_14_116PL 0xFFFF +#endif + +#define MG8_14_114PL 0xDFFF +#define MG8_14 (MG8_14_11PL & MG8_14_12PL & MG8_14_13PL & MG8_14_14PL & \ + MG8_14_15PL & MG8_14_16PL & MG8_14_17PL & MG8_14_18PL & \ + MG8_14_19PL & MG8_14_110PL & MG8_14_111PL & MG8_14_112PL & \ + MG8_14_113PL & MG8_14_114PL & MG8_14_115PL & MG8_14_116PL) +// End of MG8_14: +// Beginning of MG815: +#if (G8_1PL >= G8_15PL) || (G8_1PL == 0) +#define MG8_15_11PL ~(1 << 0) +#else +#define MG8_15_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_15PL) || (G8_2PL == 0) +#define MG8_15_12PL ~(1 << 1) +#else +#define MG8_15_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_15PL) || (G8_3PL == 0) +#define MG8_15_13PL ~(1 << 2) +#else +#define MG8_15_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_15PL) || (G8_4PL == 0) +#define MG8_15_14PL ~(1 << 3) +#else +#define MG8_15_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_15PL) || (G8_5PL == 0) +#define MG8_15_15PL ~(1 << 4) +#else +#define MG8_15_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_15PL) || (G8_6PL == 0) +#define MG8_15_16PL ~(1 << 5) +#else +#define MG8_15_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_15PL) || (G8_7PL == 0) +#define MG8_15_17PL ~(1 << 6) +#else +#define MG8_15_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_15PL) || (G8_8PL == 0) +#define MG8_15_18PL ~(1 << 7) +#else +#define MG8_15_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_15PL) || (G8_9PL == 0) +#define MG8_15_19PL ~(1 << 8) +#else +#define MG8_15_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_15PL) || (G8_10PL == 0) +#define MG8_15_110PL ~(1 << 9) +#else +#define MG8_15_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_15PL) || (G8_11PL == 0) +#define MG8_15_111PL ~(1 << 10) +#else +#define MG8_15_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_15PL) || (G8_12PL == 0) +#define MG8_15_112PL ~(1 << 11) +#else +#define MG8_15_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_15PL) || (G8_13PL == 0) +#define MG8_15_113PL ~(1 << 12) +#else +#define MG8_15_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_15PL) || (G8_14PL == 0) +#define MG8_15_114PL ~(1 << 13) +#else +#define MG8_15_114PL 0xFFFF +#endif + +#if (G8_16PL >= G8_15PL) || (G8_16PL == 0) +#define MG8_15_116PL ~(1 << 15) +#else +#define MG8_15_116PL 0xFFFF +#endif + +#define MG8_15_115PL 0xBFFF +#define MG8_15 (MG8_15_11PL & MG8_15_12PL & MG8_15_13PL & MG8_15_14PL & \ + MG8_15_15PL & MG8_15_16PL & MG8_15_17PL & MG8_15_18PL & \ + MG8_15_19PL & MG8_15_110PL & MG8_15_111PL & MG8_15_112PL & \ + MG8_15_113PL & MG8_15_114PL & MG8_15_115PL & MG8_15_116PL) +// End of MG8_15: +// Beginning of MG816: +#if (G8_1PL >= G8_16PL) || (G8_1PL == 0) +#define MG8_16_11PL ~(1 << 0) +#else +#define MG8_16_11PL 0xFFFF +#endif + +#if (G8_2PL >= G8_16PL) || (G8_2PL == 0) +#define MG8_16_12PL ~(1 << 1) +#else +#define MG8_16_12PL 0xFFFF +#endif + +#if (G8_3PL >= G8_16PL) || (G8_3PL == 0) +#define MG8_16_13PL ~(1 << 2) +#else +#define MG8_16_13PL 0xFFFF +#endif + +#if (G8_4PL >= G8_16PL) || (G8_4PL == 0) +#define MG8_16_14PL ~(1 << 3) +#else +#define MG8_16_14PL 0xFFFF +#endif + +#if (G8_5PL >= G8_16PL) || (G8_5PL == 0) +#define MG8_16_15PL ~(1 << 4) +#else +#define MG8_16_15PL 0xFFFF +#endif + +#if (G8_6PL >= G8_16PL) || (G8_6PL == 0) +#define MG8_16_16PL ~(1 << 5) +#else +#define MG8_16_16PL 0xFFFF +#endif + +#if (G8_7PL >= G8_16PL) || (G8_7PL == 0) +#define MG8_16_17PL ~(1 << 6) +#else +#define MG8_16_17PL 0xFFFF +#endif + +#if (G8_8PL >= G8_16PL) || (G8_8PL == 0) +#define MG8_16_18PL ~(1 << 7) +#else +#define MG8_16_18PL 0xFFFF +#endif + +#if (G8_9PL >= G8_16PL) || (G8_9PL == 0) +#define MG8_16_19PL ~(1 << 8) +#else +#define MG8_16_19PL 0xFFFF +#endif + +#if (G8_10PL >= G8_16PL) || (G8_10PL == 0) +#define MG8_16_110PL ~(1 << 9) +#else +#define MG8_16_110PL 0xFFFF +#endif + +#if (G8_11PL >= G8_16PL) || (G8_11PL == 0) +#define MG8_16_111PL ~(1 << 10) +#else +#define MG8_16_111PL 0xFFFF +#endif + +#if (G8_12PL >= G8_16PL) || (G8_12PL == 0) +#define MG8_16_112PL ~(1 << 11) +#else +#define MG8_16_112PL 0xFFFF +#endif + +#if (G8_13PL >= G8_16PL) || (G8_13PL == 0) +#define MG8_16_113PL ~(1 << 12) +#else +#define MG8_16_113PL 0xFFFF +#endif + +#if (G8_14PL >= G8_16PL) || (G8_14PL == 0) +#define MG8_16_114PL ~(1 << 13) +#else +#define MG8_16_114PL 0xFFFF +#endif + +#if (G8_15PL >= G8_16PL) || (G8_15PL == 0) +#define MG8_16_115PL ~(1 << 14) +#else +#define MG8_16_115PL 0xFFFF +#endif + +#define MG8_16_116PL 0x7FFF +#define MG8_16 (MG8_16_11PL & MG8_16_12PL & MG8_16_13PL & MG8_16_14PL & \ + MG8_16_15PL & MG8_16_16PL & MG8_16_17PL & MG8_16_18PL & \ + MG8_16_19PL & MG8_16_110PL & MG8_16_111PL & MG8_16_112PL & \ + MG8_16_113PL & MG8_16_114PL & MG8_16_115PL & MG8_16_116PL) +// End of MG8_16: + + +// +// Automatically generate PIEIER9 interrupt masks MG91 to MG916: +// + +// Beginning of MG91: +#if (G9_2PL >= G9_1PL) || (G9_2PL == 0) +#define MG9_1_12PL ~(1 << 1) +#else +#define MG9_1_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_1PL) || (G9_3PL == 0) +#define MG9_1_13PL ~(1 << 2) +#else +#define MG9_1_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_1PL) || (G9_4PL == 0) +#define MG9_1_14PL ~(1 << 3) +#else +#define MG9_1_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_1PL) || (G9_5PL == 0) +#define MG9_1_15PL ~(1 << 4) +#else +#define MG9_1_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_1PL) || (G9_6PL == 0) +#define MG9_1_16PL ~(1 << 5) +#else +#define MG9_1_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_1PL) || (G9_7PL == 0) +#define MG9_1_17PL ~(1 << 6) +#else +#define MG9_1_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_1PL) || (G9_8PL == 0) +#define MG9_1_18PL ~(1 << 7) +#else +#define MG9_1_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_1PL) || (G9_9PL == 0) +#define MG9_1_19PL ~(1 << 8) +#else +#define MG9_1_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_1PL) || (G9_10PL == 0) +#define MG9_1_110PL ~(1 << 9) +#else +#define MG9_1_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_1PL) || (G9_11PL == 0) +#define MG9_1_111PL ~(1 << 10) +#else +#define MG9_1_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_1PL) || (G9_12PL == 0) +#define MG9_1_112PL ~(1 << 11) +#else +#define MG9_1_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_1PL) || (G9_13PL == 0) +#define MG9_1_113PL ~(1 << 12) +#else +#define MG9_1_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_1PL) || (G9_14PL == 0) +#define MG9_1_114PL ~(1 << 13) +#else +#define MG9_1_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_1PL) || (G9_15PL == 0) +#define MG9_1_115PL ~(1 << 14) +#else +#define MG9_1_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_1PL) || (G9_16PL == 0) +#define MG9_1_116PL ~(1 << 15) +#else +#define MG9_1_116PL 0xFFFF +#endif + +#define MG9_1_11PL 0xFFFE +#define MG9_1 (MG9_1_11PL & MG9_1_12PL & MG9_1_13PL & MG9_1_14PL & \ + MG9_1_15PL & MG9_1_16PL & MG9_1_17PL & MG9_1_18PL & \ + MG9_1_19PL & MG9_1_110PL & MG9_1_111PL & MG9_1_112PL & \ + MG9_1_113PL & MG9_1_114PL & MG9_1_115PL & MG9_1_116PL) +// End of MG9_1: +// Beginning of MG92: +#if (G9_1PL >= G9_2PL) || (G9_1PL == 0) +#define MG9_2_11PL ~(1 << 0) +#else +#define MG9_2_11PL 0xFFFF +#endif + +#if (G9_3PL >= G9_2PL) || (G9_3PL == 0) +#define MG9_2_13PL ~(1 << 2) +#else +#define MG9_2_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_2PL) || (G9_4PL == 0) +#define MG9_2_14PL ~(1 << 3) +#else +#define MG9_2_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_2PL) || (G9_5PL == 0) +#define MG9_2_15PL ~(1 << 4) +#else +#define MG9_2_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_2PL) || (G9_6PL == 0) +#define MG9_2_16PL ~(1 << 5) +#else +#define MG9_2_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_2PL) || (G9_7PL == 0) +#define MG9_2_17PL ~(1 << 6) +#else +#define MG9_2_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_2PL) || (G9_8PL == 0) +#define MG9_2_18PL ~(1 << 7) +#else +#define MG9_2_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_2PL) || (G9_9PL == 0) +#define MG9_2_19PL ~(1 << 8) +#else +#define MG9_2_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_2PL) || (G9_10PL == 0) +#define MG9_2_110PL ~(1 << 9) +#else +#define MG9_2_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_2PL) || (G9_11PL == 0) +#define MG9_2_111PL ~(1 << 10) +#else +#define MG9_2_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_2PL) || (G9_12PL == 0) +#define MG9_2_112PL ~(1 << 11) +#else +#define MG9_2_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_2PL) || (G9_13PL == 0) +#define MG9_2_113PL ~(1 << 12) +#else +#define MG9_2_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_2PL) || (G9_14PL == 0) +#define MG9_2_114PL ~(1 << 13) +#else +#define MG9_2_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_2PL) || (G9_15PL == 0) +#define MG9_2_115PL ~(1 << 14) +#else +#define MG9_2_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_2PL) || (G9_16PL == 0) +#define MG9_2_116PL ~(1 << 15) +#else +#define MG9_2_116PL 0xFFFF +#endif + +#define MG9_2_12PL 0xFFFD +#define MG9_2 (MG9_2_11PL & MG9_2_12PL & MG9_2_13PL & MG9_2_14PL & \ + MG9_2_15PL & MG9_2_16PL & MG9_2_17PL & MG9_2_18PL & \ + MG9_2_19PL & MG9_2_110PL & MG9_2_111PL & MG9_2_112PL & \ + MG9_2_113PL & MG9_2_114PL & MG9_2_115PL & MG9_2_116PL) +// End of MG9_2: +// Beginning of MG93: +#if (G9_1PL >= G9_3PL) || (G9_1PL == 0) +#define MG9_3_11PL ~(1 << 0) +#else +#define MG9_3_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_3PL) || (G9_2PL == 0) +#define MG9_3_12PL ~(1 << 1) +#else +#define MG9_3_12PL 0xFFFF +#endif + +#if (G9_4PL >= G9_3PL) || (G9_4PL == 0) +#define MG9_3_14PL ~(1 << 3) +#else +#define MG9_3_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_3PL) || (G9_5PL == 0) +#define MG9_3_15PL ~(1 << 4) +#else +#define MG9_3_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_3PL) || (G9_6PL == 0) +#define MG9_3_16PL ~(1 << 5) +#else +#define MG9_3_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_3PL) || (G9_7PL == 0) +#define MG9_3_17PL ~(1 << 6) +#else +#define MG9_3_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_3PL) || (G9_8PL == 0) +#define MG9_3_18PL ~(1 << 7) +#else +#define MG9_3_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_3PL) || (G9_9PL == 0) +#define MG9_3_19PL ~(1 << 8) +#else +#define MG9_3_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_3PL) || (G9_10PL == 0) +#define MG9_3_110PL ~(1 << 9) +#else +#define MG9_3_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_3PL) || (G9_11PL == 0) +#define MG9_3_111PL ~(1 << 10) +#else +#define MG9_3_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_3PL) || (G9_12PL == 0) +#define MG9_3_112PL ~(1 << 11) +#else +#define MG9_3_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_3PL) || (G9_13PL == 0) +#define MG9_3_113PL ~(1 << 12) +#else +#define MG9_3_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_3PL) || (G9_14PL == 0) +#define MG9_3_114PL ~(1 << 13) +#else +#define MG9_3_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_3PL) || (G9_15PL == 0) +#define MG9_3_115PL ~(1 << 14) +#else +#define MG9_3_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_3PL) || (G9_16PL == 0) +#define MG9_3_116PL ~(1 << 15) +#else +#define MG9_3_116PL 0xFFFF +#endif + +#define MG9_3_13PL 0xFFFB +#define MG9_3 (MG9_3_11PL & MG9_3_12PL & MG9_3_13PL & MG9_3_14PL & \ + MG9_3_15PL & MG9_3_16PL & MG9_3_17PL & MG9_3_18PL & \ + MG9_3_19PL & MG9_3_110PL & MG9_3_111PL & MG9_3_112PL & \ + MG9_3_113PL & MG9_3_114PL & MG9_3_115PL & MG9_3_116PL) +// End of MG9_3: +// Beginning of MG94: +#if (G9_1PL >= G9_4PL) || (G9_1PL == 0) +#define MG9_4_11PL ~(1 << 0) +#else +#define MG9_4_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_4PL) || (G9_2PL == 0) +#define MG9_4_12PL ~(1 << 1) +#else +#define MG9_4_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_4PL) || (G9_3PL == 0) +#define MG9_4_13PL ~(1 << 2) +#else +#define MG9_4_13PL 0xFFFF +#endif + +#if (G9_5PL >= G9_4PL) || (G9_5PL == 0) +#define MG9_4_15PL ~(1 << 4) +#else +#define MG9_4_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_4PL) || (G9_6PL == 0) +#define MG9_4_16PL ~(1 << 5) +#else +#define MG9_4_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_4PL) || (G9_7PL == 0) +#define MG9_4_17PL ~(1 << 6) +#else +#define MG9_4_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_4PL) || (G9_8PL == 0) +#define MG9_4_18PL ~(1 << 7) +#else +#define MG9_4_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_4PL) || (G9_9PL == 0) +#define MG9_4_19PL ~(1 << 8) +#else +#define MG9_4_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_4PL) || (G9_10PL == 0) +#define MG9_4_110PL ~(1 << 9) +#else +#define MG9_4_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_4PL) || (G9_11PL == 0) +#define MG9_4_111PL ~(1 << 10) +#else +#define MG9_4_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_4PL) || (G9_12PL == 0) +#define MG9_4_112PL ~(1 << 11) +#else +#define MG9_4_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_4PL) || (G9_13PL == 0) +#define MG9_4_113PL ~(1 << 12) +#else +#define MG9_4_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_4PL) || (G9_14PL == 0) +#define MG9_4_114PL ~(1 << 13) +#else +#define MG9_4_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_4PL) || (G9_15PL == 0) +#define MG9_4_115PL ~(1 << 14) +#else +#define MG9_4_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_4PL) || (G9_16PL == 0) +#define MG9_4_116PL ~(1 << 15) +#else +#define MG9_4_116PL 0xFFFF +#endif + +#define MG9_4_14PL 0xFFF7 +#define MG9_4 (MG9_4_11PL & MG9_4_12PL & MG9_4_13PL & MG9_4_14PL & \ + MG9_4_15PL & MG9_4_16PL & MG9_4_17PL & MG9_4_18PL & \ + MG9_4_19PL & MG9_4_110PL & MG9_4_111PL & MG9_4_112PL & \ + MG9_4_113PL & MG9_4_114PL & MG9_4_115PL & MG9_4_116PL) +// End of MG9_4: +// Beginning of MG95: +#if (G9_1PL >= G9_5PL) || (G9_1PL == 0) +#define MG9_5_11PL ~(1 << 0) +#else +#define MG9_5_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_5PL) || (G9_2PL == 0) +#define MG9_5_12PL ~(1 << 1) +#else +#define MG9_5_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_5PL) || (G9_3PL == 0) +#define MG9_5_13PL ~(1 << 2) +#else +#define MG9_5_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_5PL) || (G9_4PL == 0) +#define MG9_5_14PL ~(1 << 3) +#else +#define MG9_5_14PL 0xFFFF +#endif + +#if (G9_6PL >= G9_5PL) || (G9_6PL == 0) +#define MG9_5_16PL ~(1 << 5) +#else +#define MG9_5_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_5PL) || (G9_7PL == 0) +#define MG9_5_17PL ~(1 << 6) +#else +#define MG9_5_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_5PL) || (G9_8PL == 0) +#define MG9_5_18PL ~(1 << 7) +#else +#define MG9_5_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_5PL) || (G9_9PL == 0) +#define MG9_5_19PL ~(1 << 8) +#else +#define MG9_5_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_5PL) || (G9_10PL == 0) +#define MG9_5_110PL ~(1 << 9) +#else +#define MG9_5_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_5PL) || (G9_11PL == 0) +#define MG9_5_111PL ~(1 << 10) +#else +#define MG9_5_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_5PL) || (G9_12PL == 0) +#define MG9_5_112PL ~(1 << 11) +#else +#define MG9_5_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_5PL) || (G9_13PL == 0) +#define MG9_5_113PL ~(1 << 12) +#else +#define MG9_5_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_5PL) || (G9_14PL == 0) +#define MG9_5_114PL ~(1 << 13) +#else +#define MG9_5_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_5PL) || (G9_15PL == 0) +#define MG9_5_115PL ~(1 << 14) +#else +#define MG9_5_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_5PL) || (G9_16PL == 0) +#define MG9_5_116PL ~(1 << 15) +#else +#define MG9_5_116PL 0xFFFF +#endif + +#define MG9_5_15PL 0xFFEF +#define MG9_5 (MG9_5_11PL & MG9_5_12PL & MG9_5_13PL & MG9_5_14PL & \ + MG9_5_15PL & MG9_5_16PL & MG9_5_17PL & MG9_5_18PL & \ + MG9_5_19PL & MG9_5_110PL & MG9_5_111PL & MG9_5_112PL & \ + MG9_5_113PL & MG9_5_114PL & MG9_5_115PL & MG9_5_116PL) +// End of MG9_5: +// Beginning of MG96: +#if (G9_1PL >= G9_6PL) || (G9_1PL == 0) +#define MG9_6_11PL ~(1 << 0) +#else +#define MG9_6_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_6PL) || (G9_2PL == 0) +#define MG9_6_12PL ~(1 << 1) +#else +#define MG9_6_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_6PL) || (G9_3PL == 0) +#define MG9_6_13PL ~(1 << 2) +#else +#define MG9_6_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_6PL) || (G9_4PL == 0) +#define MG9_6_14PL ~(1 << 3) +#else +#define MG9_6_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_6PL) || (G9_5PL == 0) +#define MG9_6_15PL ~(1 << 4) +#else +#define MG9_6_15PL 0xFFFF +#endif + +#if (G9_7PL >= G9_6PL) || (G9_7PL == 0) +#define MG9_6_17PL ~(1 << 6) +#else +#define MG9_6_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_6PL) || (G9_8PL == 0) +#define MG9_6_18PL ~(1 << 7) +#else +#define MG9_6_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_6PL) || (G9_9PL == 0) +#define MG9_6_19PL ~(1 << 8) +#else +#define MG9_6_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_6PL) || (G9_10PL == 0) +#define MG9_6_110PL ~(1 << 9) +#else +#define MG9_6_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_6PL) || (G9_11PL == 0) +#define MG9_6_111PL ~(1 << 10) +#else +#define MG9_6_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_6PL) || (G9_12PL == 0) +#define MG9_6_112PL ~(1 << 11) +#else +#define MG9_6_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_6PL) || (G9_13PL == 0) +#define MG9_6_113PL ~(1 << 12) +#else +#define MG9_6_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_6PL) || (G9_14PL == 0) +#define MG9_6_114PL ~(1 << 13) +#else +#define MG9_6_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_6PL) || (G9_15PL == 0) +#define MG9_6_115PL ~(1 << 14) +#else +#define MG9_6_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_6PL) || (G9_16PL == 0) +#define MG9_6_116PL ~(1 << 15) +#else +#define MG9_6_116PL 0xFFFF +#endif + +#define MG9_6_16PL 0xFFDF +#define MG9_6 (MG9_6_11PL & MG9_6_12PL & MG9_6_13PL & MG9_6_14PL & \ + MG9_6_15PL & MG9_6_16PL & MG9_6_17PL & MG9_6_18PL & \ + MG9_6_19PL & MG9_6_110PL & MG9_6_111PL & MG9_6_112PL & \ + MG9_6_113PL & MG9_6_114PL & MG9_6_115PL & MG9_6_116PL) +// End of MG9_6: +// Beginning of MG97: +#if (G9_1PL >= G9_7PL) || (G9_1PL == 0) +#define MG9_7_11PL ~(1 << 0) +#else +#define MG9_7_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_7PL) || (G9_2PL == 0) +#define MG9_7_12PL ~(1 << 1) +#else +#define MG9_7_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_7PL) || (G9_3PL == 0) +#define MG9_7_13PL ~(1 << 2) +#else +#define MG9_7_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_7PL) || (G9_4PL == 0) +#define MG9_7_14PL ~(1 << 3) +#else +#define MG9_7_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_7PL) || (G9_5PL == 0) +#define MG9_7_15PL ~(1 << 4) +#else +#define MG9_7_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_7PL) || (G9_6PL == 0) +#define MG9_7_16PL ~(1 << 5) +#else +#define MG9_7_16PL 0xFFFF +#endif + +#if (G9_8PL >= G9_7PL) || (G9_8PL == 0) +#define MG9_7_18PL ~(1 << 7) +#else +#define MG9_7_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_7PL) || (G9_9PL == 0) +#define MG9_7_19PL ~(1 << 8) +#else +#define MG9_7_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_7PL) || (G9_10PL == 0) +#define MG9_7_110PL ~(1 << 9) +#else +#define MG9_7_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_7PL) || (G9_11PL == 0) +#define MG9_7_111PL ~(1 << 10) +#else +#define MG9_7_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_7PL) || (G9_12PL == 0) +#define MG9_7_112PL ~(1 << 11) +#else +#define MG9_7_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_7PL) || (G9_13PL == 0) +#define MG9_7_113PL ~(1 << 12) +#else +#define MG9_7_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_7PL) || (G9_14PL == 0) +#define MG9_7_114PL ~(1 << 13) +#else +#define MG9_7_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_7PL) || (G9_15PL == 0) +#define MG9_7_115PL ~(1 << 14) +#else +#define MG9_7_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_7PL) || (G9_16PL == 0) +#define MG9_7_116PL ~(1 << 15) +#else +#define MG9_7_116PL 0xFFFF +#endif + +#define MG9_7_17PL 0xFFBF +#define MG9_7 (MG9_7_11PL & MG9_7_12PL & MG9_7_13PL & MG9_7_14PL & \ + MG9_7_15PL & MG9_7_16PL & MG9_7_17PL & MG9_7_18PL & \ + MG9_7_19PL & MG9_7_110PL & MG9_7_111PL & MG9_7_112PL & \ + MG9_7_113PL & MG9_7_114PL & MG9_7_115PL & MG9_7_116PL) +// End of MG9_7: +// Beginning of MG98: +#if (G9_1PL >= G9_8PL) || (G9_1PL == 0) +#define MG9_8_11PL ~(1 << 0) +#else +#define MG9_8_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_8PL) || (G9_2PL == 0) +#define MG9_8_12PL ~(1 << 1) +#else +#define MG9_8_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_8PL) || (G9_3PL == 0) +#define MG9_8_13PL ~(1 << 2) +#else +#define MG9_8_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_8PL) || (G9_4PL == 0) +#define MG9_8_14PL ~(1 << 3) +#else +#define MG9_8_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_8PL) || (G9_5PL == 0) +#define MG9_8_15PL ~(1 << 4) +#else +#define MG9_8_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_8PL) || (G9_6PL == 0) +#define MG9_8_16PL ~(1 << 5) +#else +#define MG9_8_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_8PL) || (G9_7PL == 0) +#define MG9_8_17PL ~(1 << 6) +#else +#define MG9_8_17PL 0xFFFF +#endif + +#if (G9_9PL >= G9_8PL) || (G9_9PL == 0) +#define MG9_8_19PL ~(1 << 8) +#else +#define MG9_8_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_8PL) || (G9_10PL == 0) +#define MG9_8_110PL ~(1 << 9) +#else +#define MG9_8_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_8PL) || (G9_11PL == 0) +#define MG9_8_111PL ~(1 << 10) +#else +#define MG9_8_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_8PL) || (G9_12PL == 0) +#define MG9_8_112PL ~(1 << 11) +#else +#define MG9_8_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_8PL) || (G9_13PL == 0) +#define MG9_8_113PL ~(1 << 12) +#else +#define MG9_8_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_8PL) || (G9_14PL == 0) +#define MG9_8_114PL ~(1 << 13) +#else +#define MG9_8_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_8PL) || (G9_15PL == 0) +#define MG9_8_115PL ~(1 << 14) +#else +#define MG9_8_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_8PL) || (G9_16PL == 0) +#define MG9_8_116PL ~(1 << 15) +#else +#define MG9_8_116PL 0xFFFF +#endif + +#define MG9_8_18PL 0xFF7F +#define MG9_8 (MG9_8_11PL & MG9_8_12PL & MG9_8_13PL & MG9_8_14PL & \ + MG9_8_15PL & MG9_8_16PL & MG9_8_17PL & MG9_8_18PL & \ + MG9_8_19PL & MG9_8_110PL & MG9_8_111PL & MG9_8_112PL & \ + MG9_8_113PL & MG9_8_114PL & MG9_8_115PL & MG9_8_116PL) +// End of MG9_8: +// Beginning of MG99: +#if (G9_1PL >= G9_9PL) || (G9_1PL == 0) +#define MG9_9_11PL ~(1 << 0) +#else +#define MG9_9_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_9PL) || (G9_2PL == 0) +#define MG9_9_12PL ~(1 << 1) +#else +#define MG9_9_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_9PL) || (G9_3PL == 0) +#define MG9_9_13PL ~(1 << 2) +#else +#define MG9_9_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_9PL) || (G9_4PL == 0) +#define MG9_9_14PL ~(1 << 3) +#else +#define MG9_9_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_9PL) || (G9_5PL == 0) +#define MG9_9_15PL ~(1 << 4) +#else +#define MG9_9_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_9PL) || (G9_6PL == 0) +#define MG9_9_16PL ~(1 << 5) +#else +#define MG9_9_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_9PL) || (G9_7PL == 0) +#define MG9_9_17PL ~(1 << 6) +#else +#define MG9_9_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_9PL) || (G9_8PL == 0) +#define MG9_9_18PL ~(1 << 7) +#else +#define MG9_9_18PL 0xFFFF +#endif + +#if (G9_10PL >= G9_9PL) || (G9_10PL == 0) +#define MG9_9_110PL ~(1 << 9) +#else +#define MG9_9_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_9PL) || (G9_11PL == 0) +#define MG9_9_111PL ~(1 << 10) +#else +#define MG9_9_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_9PL) || (G9_12PL == 0) +#define MG9_9_112PL ~(1 << 11) +#else +#define MG9_9_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_9PL) || (G9_13PL == 0) +#define MG9_9_113PL ~(1 << 12) +#else +#define MG9_9_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_9PL) || (G9_14PL == 0) +#define MG9_9_114PL ~(1 << 13) +#else +#define MG9_9_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_9PL) || (G9_15PL == 0) +#define MG9_9_115PL ~(1 << 14) +#else +#define MG9_9_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_9PL) || (G9_16PL == 0) +#define MG9_9_116PL ~(1 << 15) +#else +#define MG9_9_116PL 0xFFFF +#endif + +#define MG9_9_19PL 0xFEFF +#define MG9_9 (MG9_9_11PL & MG9_9_12PL & MG9_9_13PL & MG9_9_14PL & \ + MG9_9_15PL & MG9_9_16PL & MG9_9_17PL & MG9_9_18PL & \ + MG9_9_19PL & MG9_9_110PL & MG9_9_111PL & MG9_9_112PL & \ + MG9_9_113PL & MG9_9_114PL & MG9_9_115PL & MG9_9_116PL) +// End of MG9_9: +// Beginning of MG910: +#if (G9_1PL >= G9_10PL) || (G9_1PL == 0) +#define MG9_10_11PL ~(1 << 0) +#else +#define MG9_10_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_10PL) || (G9_2PL == 0) +#define MG9_10_12PL ~(1 << 1) +#else +#define MG9_10_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_10PL) || (G9_3PL == 0) +#define MG9_10_13PL ~(1 << 2) +#else +#define MG9_10_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_10PL) || (G9_4PL == 0) +#define MG9_10_14PL ~(1 << 3) +#else +#define MG9_10_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_10PL) || (G9_5PL == 0) +#define MG9_10_15PL ~(1 << 4) +#else +#define MG9_10_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_10PL) || (G9_6PL == 0) +#define MG9_10_16PL ~(1 << 5) +#else +#define MG9_10_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_10PL) || (G9_7PL == 0) +#define MG9_10_17PL ~(1 << 6) +#else +#define MG9_10_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_10PL) || (G9_8PL == 0) +#define MG9_10_18PL ~(1 << 7) +#else +#define MG9_10_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_10PL) || (G9_9PL == 0) +#define MG9_10_19PL ~(1 << 8) +#else +#define MG9_10_19PL 0xFFFF +#endif + +#if (G9_11PL >= G9_10PL) || (G9_11PL == 0) +#define MG9_10_111PL ~(1 << 10) +#else +#define MG9_10_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_10PL) || (G9_12PL == 0) +#define MG9_10_112PL ~(1 << 11) +#else +#define MG9_10_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_10PL) || (G9_13PL == 0) +#define MG9_10_113PL ~(1 << 12) +#else +#define MG9_10_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_10PL) || (G9_14PL == 0) +#define MG9_10_114PL ~(1 << 13) +#else +#define MG9_10_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_10PL) || (G9_15PL == 0) +#define MG9_10_115PL ~(1 << 14) +#else +#define MG9_10_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_10PL) || (G9_16PL == 0) +#define MG9_10_116PL ~(1 << 15) +#else +#define MG9_10_116PL 0xFFFF +#endif + +#define MG9_10_110PL 0xFDFF +#define MG9_10 (MG9_10_11PL & MG9_10_12PL & MG9_10_13PL & MG9_10_14PL & \ + MG9_10_15PL & MG9_10_16PL & MG9_10_17PL & MG9_10_18PL & \ + MG9_10_19PL & MG9_10_110PL & MG9_10_111PL & MG9_10_112PL & \ + MG9_10_113PL & MG9_10_114PL & MG9_10_115PL & MG9_10_116PL) +// End of MG9_10: +// Beginning of MG911: +#if (G9_1PL >= G9_11PL) || (G9_1PL == 0) +#define MG9_11_11PL ~(1 << 0) +#else +#define MG9_11_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_11PL) || (G9_2PL == 0) +#define MG9_11_12PL ~(1 << 1) +#else +#define MG9_11_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_11PL) || (G9_3PL == 0) +#define MG9_11_13PL ~(1 << 2) +#else +#define MG9_11_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_11PL) || (G9_4PL == 0) +#define MG9_11_14PL ~(1 << 3) +#else +#define MG9_11_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_11PL) || (G9_5PL == 0) +#define MG9_11_15PL ~(1 << 4) +#else +#define MG9_11_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_11PL) || (G9_6PL == 0) +#define MG9_11_16PL ~(1 << 5) +#else +#define MG9_11_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_11PL) || (G9_7PL == 0) +#define MG9_11_17PL ~(1 << 6) +#else +#define MG9_11_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_11PL) || (G9_8PL == 0) +#define MG9_11_18PL ~(1 << 7) +#else +#define MG9_11_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_11PL) || (G9_9PL == 0) +#define MG9_11_19PL ~(1 << 8) +#else +#define MG9_11_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_11PL) || (G9_10PL == 0) +#define MG9_11_110PL ~(1 << 9) +#else +#define MG9_11_110PL 0xFFFF +#endif + +#if (G9_12PL >= G9_11PL) || (G9_12PL == 0) +#define MG9_11_112PL ~(1 << 11) +#else +#define MG9_11_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_11PL) || (G9_13PL == 0) +#define MG9_11_113PL ~(1 << 12) +#else +#define MG9_11_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_11PL) || (G9_14PL == 0) +#define MG9_11_114PL ~(1 << 13) +#else +#define MG9_11_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_11PL) || (G9_15PL == 0) +#define MG9_11_115PL ~(1 << 14) +#else +#define MG9_11_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_11PL) || (G9_16PL == 0) +#define MG9_11_116PL ~(1 << 15) +#else +#define MG9_11_116PL 0xFFFF +#endif + +#define MG9_11_111PL 0xFBFF +#define MG9_11 (MG9_11_11PL & MG9_11_12PL & MG9_11_13PL & MG9_11_14PL & \ + MG9_11_15PL & MG9_11_16PL & MG9_11_17PL & MG9_11_18PL & \ + MG9_11_19PL & MG9_11_110PL & MG9_11_111PL & MG9_11_112PL & \ + MG9_11_113PL & MG9_11_114PL & MG9_11_115PL & MG9_11_116PL) +// End of MG9_11: +// Beginning of MG912: +#if (G9_1PL >= G9_12PL) || (G9_1PL == 0) +#define MG9_12_11PL ~(1 << 0) +#else +#define MG9_12_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_12PL) || (G9_2PL == 0) +#define MG9_12_12PL ~(1 << 1) +#else +#define MG9_12_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_12PL) || (G9_3PL == 0) +#define MG9_12_13PL ~(1 << 2) +#else +#define MG9_12_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_12PL) || (G9_4PL == 0) +#define MG9_12_14PL ~(1 << 3) +#else +#define MG9_12_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_12PL) || (G9_5PL == 0) +#define MG9_12_15PL ~(1 << 4) +#else +#define MG9_12_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_12PL) || (G9_6PL == 0) +#define MG9_12_16PL ~(1 << 5) +#else +#define MG9_12_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_12PL) || (G9_7PL == 0) +#define MG9_12_17PL ~(1 << 6) +#else +#define MG9_12_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_12PL) || (G9_8PL == 0) +#define MG9_12_18PL ~(1 << 7) +#else +#define MG9_12_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_12PL) || (G9_9PL == 0) +#define MG9_12_19PL ~(1 << 8) +#else +#define MG9_12_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_12PL) || (G9_10PL == 0) +#define MG9_12_110PL ~(1 << 9) +#else +#define MG9_12_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_12PL) || (G9_11PL == 0) +#define MG9_12_111PL ~(1 << 10) +#else +#define MG9_12_111PL 0xFFFF +#endif + +#if (G9_13PL >= G9_12PL) || (G9_13PL == 0) +#define MG9_12_113PL ~(1 << 12) +#else +#define MG9_12_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_12PL) || (G9_14PL == 0) +#define MG9_12_114PL ~(1 << 13) +#else +#define MG9_12_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_12PL) || (G9_15PL == 0) +#define MG9_12_115PL ~(1 << 14) +#else +#define MG9_12_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_12PL) || (G9_16PL == 0) +#define MG9_12_116PL ~(1 << 15) +#else +#define MG9_12_116PL 0xFFFF +#endif + +#define MG9_12_112PL 0xF7FF +#define MG9_12 (MG9_12_11PL & MG9_12_12PL & MG9_12_13PL & MG9_12_14PL & \ + MG9_12_15PL & MG9_12_16PL & MG9_12_17PL & MG9_12_18PL & \ + MG9_12_19PL & MG9_12_110PL & MG9_12_111PL & MG9_12_112PL & \ + MG9_12_113PL & MG9_12_114PL & MG9_12_115PL & MG9_12_116PL) +// End of MG9_12: +// Beginning of MG913: +#if (G9_1PL >= G9_13PL) || (G9_1PL == 0) +#define MG9_13_11PL ~(1 << 0) +#else +#define MG9_13_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_13PL) || (G9_2PL == 0) +#define MG9_13_12PL ~(1 << 1) +#else +#define MG9_13_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_13PL) || (G9_3PL == 0) +#define MG9_13_13PL ~(1 << 2) +#else +#define MG9_13_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_13PL) || (G9_4PL == 0) +#define MG9_13_14PL ~(1 << 3) +#else +#define MG9_13_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_13PL) || (G9_5PL == 0) +#define MG9_13_15PL ~(1 << 4) +#else +#define MG9_13_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_13PL) || (G9_6PL == 0) +#define MG9_13_16PL ~(1 << 5) +#else +#define MG9_13_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_13PL) || (G9_7PL == 0) +#define MG9_13_17PL ~(1 << 6) +#else +#define MG9_13_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_13PL) || (G9_8PL == 0) +#define MG9_13_18PL ~(1 << 7) +#else +#define MG9_13_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_13PL) || (G9_9PL == 0) +#define MG9_13_19PL ~(1 << 8) +#else +#define MG9_13_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_13PL) || (G9_10PL == 0) +#define MG9_13_110PL ~(1 << 9) +#else +#define MG9_13_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_13PL) || (G9_11PL == 0) +#define MG9_13_111PL ~(1 << 10) +#else +#define MG9_13_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_13PL) || (G9_12PL == 0) +#define MG9_13_112PL ~(1 << 11) +#else +#define MG9_13_112PL 0xFFFF +#endif + +#if (G9_14PL >= G9_13PL) || (G9_14PL == 0) +#define MG9_13_114PL ~(1 << 13) +#else +#define MG9_13_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_13PL) || (G9_15PL == 0) +#define MG9_13_115PL ~(1 << 14) +#else +#define MG9_13_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_13PL) || (G9_16PL == 0) +#define MG9_13_116PL ~(1 << 15) +#else +#define MG9_13_116PL 0xFFFF +#endif + +#define MG9_13_113PL 0xEFFF +#define MG9_13 (MG9_13_11PL & MG9_13_12PL & MG9_13_13PL & MG9_13_14PL & \ + MG9_13_15PL & MG9_13_16PL & MG9_13_17PL & MG9_13_18PL & \ + MG9_13_19PL & MG9_13_110PL & MG9_13_111PL & MG9_13_112PL & \ + MG9_13_113PL & MG9_13_114PL & MG9_13_115PL & MG9_13_116PL) +// End of MG9_13: +// Beginning of MG914: +#if (G9_1PL >= G9_14PL) || (G9_1PL == 0) +#define MG9_14_11PL ~(1 << 0) +#else +#define MG9_14_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_14PL) || (G9_2PL == 0) +#define MG9_14_12PL ~(1 << 1) +#else +#define MG9_14_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_14PL) || (G9_3PL == 0) +#define MG9_14_13PL ~(1 << 2) +#else +#define MG9_14_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_14PL) || (G9_4PL == 0) +#define MG9_14_14PL ~(1 << 3) +#else +#define MG9_14_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_14PL) || (G9_5PL == 0) +#define MG9_14_15PL ~(1 << 4) +#else +#define MG9_14_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_14PL) || (G9_6PL == 0) +#define MG9_14_16PL ~(1 << 5) +#else +#define MG9_14_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_14PL) || (G9_7PL == 0) +#define MG9_14_17PL ~(1 << 6) +#else +#define MG9_14_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_14PL) || (G9_8PL == 0) +#define MG9_14_18PL ~(1 << 7) +#else +#define MG9_14_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_14PL) || (G9_9PL == 0) +#define MG9_14_19PL ~(1 << 8) +#else +#define MG9_14_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_14PL) || (G9_10PL == 0) +#define MG9_14_110PL ~(1 << 9) +#else +#define MG9_14_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_14PL) || (G9_11PL == 0) +#define MG9_14_111PL ~(1 << 10) +#else +#define MG9_14_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_14PL) || (G9_12PL == 0) +#define MG9_14_112PL ~(1 << 11) +#else +#define MG9_14_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_14PL) || (G9_13PL == 0) +#define MG9_14_113PL ~(1 << 12) +#else +#define MG9_14_113PL 0xFFFF +#endif + +#if (G9_15PL >= G9_14PL) || (G9_15PL == 0) +#define MG9_14_115PL ~(1 << 14) +#else +#define MG9_14_115PL 0xFFFF +#endif + +#if (G9_16PL >= G9_14PL) || (G9_16PL == 0) +#define MG9_14_116PL ~(1 << 15) +#else +#define MG9_14_116PL 0xFFFF +#endif + +#define MG9_14_114PL 0xDFFF +#define MG9_14 (MG9_14_11PL & MG9_14_12PL & MG9_14_13PL & MG9_14_14PL & \ + MG9_14_15PL & MG9_14_16PL & MG9_14_17PL & MG9_14_18PL & \ + MG9_14_19PL & MG9_14_110PL & MG9_14_111PL & MG9_14_112PL & \ + MG9_14_113PL & MG9_14_114PL & MG9_14_115PL & MG9_14_116PL) +// End of MG9_14: +// Beginning of MG915: +#if (G9_1PL >= G9_15PL) || (G9_1PL == 0) +#define MG9_15_11PL ~(1 << 0) +#else +#define MG9_15_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_15PL) || (G9_2PL == 0) +#define MG9_15_12PL ~(1 << 1) +#else +#define MG9_15_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_15PL) || (G9_3PL == 0) +#define MG9_15_13PL ~(1 << 2) +#else +#define MG9_15_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_15PL) || (G9_4PL == 0) +#define MG9_15_14PL ~(1 << 3) +#else +#define MG9_15_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_15PL) || (G9_5PL == 0) +#define MG9_15_15PL ~(1 << 4) +#else +#define MG9_15_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_15PL) || (G9_6PL == 0) +#define MG9_15_16PL ~(1 << 5) +#else +#define MG9_15_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_15PL) || (G9_7PL == 0) +#define MG9_15_17PL ~(1 << 6) +#else +#define MG9_15_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_15PL) || (G9_8PL == 0) +#define MG9_15_18PL ~(1 << 7) +#else +#define MG9_15_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_15PL) || (G9_9PL == 0) +#define MG9_15_19PL ~(1 << 8) +#else +#define MG9_15_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_15PL) || (G9_10PL == 0) +#define MG9_15_110PL ~(1 << 9) +#else +#define MG9_15_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_15PL) || (G9_11PL == 0) +#define MG9_15_111PL ~(1 << 10) +#else +#define MG9_15_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_15PL) || (G9_12PL == 0) +#define MG9_15_112PL ~(1 << 11) +#else +#define MG9_15_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_15PL) || (G9_13PL == 0) +#define MG9_15_113PL ~(1 << 12) +#else +#define MG9_15_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_15PL) || (G9_14PL == 0) +#define MG9_15_114PL ~(1 << 13) +#else +#define MG9_15_114PL 0xFFFF +#endif + +#if (G9_16PL >= G9_15PL) || (G9_16PL == 0) +#define MG9_15_116PL ~(1 << 15) +#else +#define MG9_15_116PL 0xFFFF +#endif + +#define MG9_15_115PL 0xBFFF +#define MG9_15 (MG9_15_11PL & MG9_15_12PL & MG9_15_13PL & MG9_15_14PL & \ + MG9_15_15PL & MG9_15_16PL & MG9_15_17PL & MG9_15_18PL & \ + MG9_15_19PL & MG9_15_110PL & MG9_15_111PL & MG9_15_112PL & \ + MG9_15_113PL & MG9_15_114PL & MG9_15_115PL & MG9_15_116PL) +// End of MG9_15: +// Beginning of MG916: +#if (G9_1PL >= G9_16PL) || (G9_1PL == 0) +#define MG9_16_11PL ~(1 << 0) +#else +#define MG9_16_11PL 0xFFFF +#endif + +#if (G9_2PL >= G9_16PL) || (G9_2PL == 0) +#define MG9_16_12PL ~(1 << 1) +#else +#define MG9_16_12PL 0xFFFF +#endif + +#if (G9_3PL >= G9_16PL) || (G9_3PL == 0) +#define MG9_16_13PL ~(1 << 2) +#else +#define MG9_16_13PL 0xFFFF +#endif + +#if (G9_4PL >= G9_16PL) || (G9_4PL == 0) +#define MG9_16_14PL ~(1 << 3) +#else +#define MG9_16_14PL 0xFFFF +#endif + +#if (G9_5PL >= G9_16PL) || (G9_5PL == 0) +#define MG9_16_15PL ~(1 << 4) +#else +#define MG9_16_15PL 0xFFFF +#endif + +#if (G9_6PL >= G9_16PL) || (G9_6PL == 0) +#define MG9_16_16PL ~(1 << 5) +#else +#define MG9_16_16PL 0xFFFF +#endif + +#if (G9_7PL >= G9_16PL) || (G9_7PL == 0) +#define MG9_16_17PL ~(1 << 6) +#else +#define MG9_16_17PL 0xFFFF +#endif + +#if (G9_8PL >= G9_16PL) || (G9_8PL == 0) +#define MG9_16_18PL ~(1 << 7) +#else +#define MG9_16_18PL 0xFFFF +#endif + +#if (G9_9PL >= G9_16PL) || (G9_9PL == 0) +#define MG9_16_19PL ~(1 << 8) +#else +#define MG9_16_19PL 0xFFFF +#endif + +#if (G9_10PL >= G9_16PL) || (G9_10PL == 0) +#define MG9_16_110PL ~(1 << 9) +#else +#define MG9_16_110PL 0xFFFF +#endif + +#if (G9_11PL >= G9_16PL) || (G9_11PL == 0) +#define MG9_16_111PL ~(1 << 10) +#else +#define MG9_16_111PL 0xFFFF +#endif + +#if (G9_12PL >= G9_16PL) || (G9_12PL == 0) +#define MG9_16_112PL ~(1 << 11) +#else +#define MG9_16_112PL 0xFFFF +#endif + +#if (G9_13PL >= G9_16PL) || (G9_13PL == 0) +#define MG9_16_113PL ~(1 << 12) +#else +#define MG9_16_113PL 0xFFFF +#endif + +#if (G9_14PL >= G9_16PL) || (G9_14PL == 0) +#define MG9_16_114PL ~(1 << 13) +#else +#define MG9_16_114PL 0xFFFF +#endif + +#if (G9_15PL >= G9_16PL) || (G9_15PL == 0) +#define MG9_16_115PL ~(1 << 14) +#else +#define MG9_16_115PL 0xFFFF +#endif + +#define MG9_16_116PL 0x7FFF +#define MG9_16 (MG9_16_11PL & MG9_16_12PL & MG9_16_13PL & MG9_16_14PL & \ + MG9_16_15PL & MG9_16_16PL & MG9_16_17PL & MG9_16_18PL & \ + MG9_16_19PL & MG9_16_110PL & MG9_16_111PL & MG9_16_112PL & \ + MG9_16_113PL & MG9_16_114PL & MG9_16_115PL & MG9_16_116PL) +// End of MG9_16: + + +// +// Automatically generate PIEIER10 interrupt masks MG101 to MG1016: +// + +// Beginning of MG101: +#if (G10_2PL >= G10_1PL) || (G10_2PL == 0) +#define MG10_1_12PL ~(1 << 1) +#else +#define MG10_1_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_1PL) || (G10_3PL == 0) +#define MG10_1_13PL ~(1 << 2) +#else +#define MG10_1_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_1PL) || (G10_4PL == 0) +#define MG10_1_14PL ~(1 << 3) +#else +#define MG10_1_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_1PL) || (G10_5PL == 0) +#define MG10_1_15PL ~(1 << 4) +#else +#define MG10_1_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_1PL) || (G10_6PL == 0) +#define MG10_1_16PL ~(1 << 5) +#else +#define MG10_1_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_1PL) || (G10_7PL == 0) +#define MG10_1_17PL ~(1 << 6) +#else +#define MG10_1_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_1PL) || (G10_8PL == 0) +#define MG10_1_18PL ~(1 << 7) +#else +#define MG10_1_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_1PL) || (G10_9PL == 0) +#define MG10_1_19PL ~(1 << 8) +#else +#define MG10_1_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_1PL) || (G10_10PL == 0) +#define MG10_1_110PL ~(1 << 9) +#else +#define MG10_1_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_1PL) || (G10_11PL == 0) +#define MG10_1_111PL ~(1 << 10) +#else +#define MG10_1_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_1PL) || (G10_12PL == 0) +#define MG10_1_112PL ~(1 << 11) +#else +#define MG10_1_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_1PL) || (G10_13PL == 0) +#define MG10_1_113PL ~(1 << 12) +#else +#define MG10_1_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_1PL) || (G10_14PL == 0) +#define MG10_1_114PL ~(1 << 13) +#else +#define MG10_1_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_1PL) || (G10_15PL == 0) +#define MG10_1_115PL ~(1 << 14) +#else +#define MG10_1_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_1PL) || (G10_16PL == 0) +#define MG10_1_116PL ~(1 << 15) +#else +#define MG10_1_116PL 0xFFFF +#endif + +#define MG10_1_11PL 0xFFFE +#define MG10_1 (MG10_1_11PL & MG10_1_12PL & MG10_1_13PL & MG10_1_14PL & \ + MG10_1_15PL & MG10_1_16PL & MG10_1_17PL & MG10_1_18PL & \ + MG10_1_19PL & MG10_1_110PL & MG10_1_111PL & MG10_1_112PL & \ + MG10_1_113PL & MG10_1_114PL & MG10_1_115PL & MG10_1_116PL) +// End of MG10_1: +// Beginning of MG102: +#if (G10_1PL >= G10_2PL) || (G10_1PL == 0) +#define MG10_2_11PL ~(1 << 0) +#else +#define MG10_2_11PL 0xFFFF +#endif + +#if (G10_3PL >= G10_2PL) || (G10_3PL == 0) +#define MG10_2_13PL ~(1 << 2) +#else +#define MG10_2_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_2PL) || (G10_4PL == 0) +#define MG10_2_14PL ~(1 << 3) +#else +#define MG10_2_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_2PL) || (G10_5PL == 0) +#define MG10_2_15PL ~(1 << 4) +#else +#define MG10_2_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_2PL) || (G10_6PL == 0) +#define MG10_2_16PL ~(1 << 5) +#else +#define MG10_2_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_2PL) || (G10_7PL == 0) +#define MG10_2_17PL ~(1 << 6) +#else +#define MG10_2_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_2PL) || (G10_8PL == 0) +#define MG10_2_18PL ~(1 << 7) +#else +#define MG10_2_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_2PL) || (G10_9PL == 0) +#define MG10_2_19PL ~(1 << 8) +#else +#define MG10_2_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_2PL) || (G10_10PL == 0) +#define MG10_2_110PL ~(1 << 9) +#else +#define MG10_2_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_2PL) || (G10_11PL == 0) +#define MG10_2_111PL ~(1 << 10) +#else +#define MG10_2_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_2PL) || (G10_12PL == 0) +#define MG10_2_112PL ~(1 << 11) +#else +#define MG10_2_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_2PL) || (G10_13PL == 0) +#define MG10_2_113PL ~(1 << 12) +#else +#define MG10_2_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_2PL) || (G10_14PL == 0) +#define MG10_2_114PL ~(1 << 13) +#else +#define MG10_2_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_2PL) || (G10_15PL == 0) +#define MG10_2_115PL ~(1 << 14) +#else +#define MG10_2_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_2PL) || (G10_16PL == 0) +#define MG10_2_116PL ~(1 << 15) +#else +#define MG10_2_116PL 0xFFFF +#endif + +#define MG10_2_12PL 0xFFFD +#define MG10_2 (MG10_2_11PL & MG10_2_12PL & MG10_2_13PL & MG10_2_14PL & \ + MG10_2_15PL & MG10_2_16PL & MG10_2_17PL & MG10_2_18PL & \ + MG10_2_19PL & MG10_2_110PL & MG10_2_111PL & MG10_2_112PL & \ + MG10_2_113PL & MG10_2_114PL & MG10_2_115PL & MG10_2_116PL) +// End of MG10_2: +// Beginning of MG103: +#if (G10_1PL >= G10_3PL) || (G10_1PL == 0) +#define MG10_3_11PL ~(1 << 0) +#else +#define MG10_3_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_3PL) || (G10_2PL == 0) +#define MG10_3_12PL ~(1 << 1) +#else +#define MG10_3_12PL 0xFFFF +#endif + +#if (G10_4PL >= G10_3PL) || (G10_4PL == 0) +#define MG10_3_14PL ~(1 << 3) +#else +#define MG10_3_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_3PL) || (G10_5PL == 0) +#define MG10_3_15PL ~(1 << 4) +#else +#define MG10_3_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_3PL) || (G10_6PL == 0) +#define MG10_3_16PL ~(1 << 5) +#else +#define MG10_3_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_3PL) || (G10_7PL == 0) +#define MG10_3_17PL ~(1 << 6) +#else +#define MG10_3_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_3PL) || (G10_8PL == 0) +#define MG10_3_18PL ~(1 << 7) +#else +#define MG10_3_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_3PL) || (G10_9PL == 0) +#define MG10_3_19PL ~(1 << 8) +#else +#define MG10_3_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_3PL) || (G10_10PL == 0) +#define MG10_3_110PL ~(1 << 9) +#else +#define MG10_3_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_3PL) || (G10_11PL == 0) +#define MG10_3_111PL ~(1 << 10) +#else +#define MG10_3_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_3PL) || (G10_12PL == 0) +#define MG10_3_112PL ~(1 << 11) +#else +#define MG10_3_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_3PL) || (G10_13PL == 0) +#define MG10_3_113PL ~(1 << 12) +#else +#define MG10_3_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_3PL) || (G10_14PL == 0) +#define MG10_3_114PL ~(1 << 13) +#else +#define MG10_3_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_3PL) || (G10_15PL == 0) +#define MG10_3_115PL ~(1 << 14) +#else +#define MG10_3_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_3PL) || (G10_16PL == 0) +#define MG10_3_116PL ~(1 << 15) +#else +#define MG10_3_116PL 0xFFFF +#endif + +#define MG10_3_13PL 0xFFFB +#define MG10_3 (MG10_3_11PL & MG10_3_12PL & MG10_3_13PL & MG10_3_14PL & \ + MG10_3_15PL & MG10_3_16PL & MG10_3_17PL & MG10_3_18PL & \ + MG10_3_19PL & MG10_3_110PL & MG10_3_111PL & MG10_3_112PL & \ + MG10_3_113PL & MG10_3_114PL & MG10_3_115PL & MG10_3_116PL) +// End of MG10_3: +// Beginning of MG104: +#if (G10_1PL >= G10_4PL) || (G10_1PL == 0) +#define MG10_4_11PL ~(1 << 0) +#else +#define MG10_4_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_4PL) || (G10_2PL == 0) +#define MG10_4_12PL ~(1 << 1) +#else +#define MG10_4_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_4PL) || (G10_3PL == 0) +#define MG10_4_13PL ~(1 << 2) +#else +#define MG10_4_13PL 0xFFFF +#endif + +#if (G10_5PL >= G10_4PL) || (G10_5PL == 0) +#define MG10_4_15PL ~(1 << 4) +#else +#define MG10_4_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_4PL) || (G10_6PL == 0) +#define MG10_4_16PL ~(1 << 5) +#else +#define MG10_4_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_4PL) || (G10_7PL == 0) +#define MG10_4_17PL ~(1 << 6) +#else +#define MG10_4_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_4PL) || (G10_8PL == 0) +#define MG10_4_18PL ~(1 << 7) +#else +#define MG10_4_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_4PL) || (G10_9PL == 0) +#define MG10_4_19PL ~(1 << 8) +#else +#define MG10_4_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_4PL) || (G10_10PL == 0) +#define MG10_4_110PL ~(1 << 9) +#else +#define MG10_4_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_4PL) || (G10_11PL == 0) +#define MG10_4_111PL ~(1 << 10) +#else +#define MG10_4_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_4PL) || (G10_12PL == 0) +#define MG10_4_112PL ~(1 << 11) +#else +#define MG10_4_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_4PL) || (G10_13PL == 0) +#define MG10_4_113PL ~(1 << 12) +#else +#define MG10_4_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_4PL) || (G10_14PL == 0) +#define MG10_4_114PL ~(1 << 13) +#else +#define MG10_4_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_4PL) || (G10_15PL == 0) +#define MG10_4_115PL ~(1 << 14) +#else +#define MG10_4_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_4PL) || (G10_16PL == 0) +#define MG10_4_116PL ~(1 << 15) +#else +#define MG10_4_116PL 0xFFFF +#endif + +#define MG10_4_14PL 0xFFF7 +#define MG10_4 (MG10_4_11PL & MG10_4_12PL & MG10_4_13PL & MG10_4_14PL & \ + MG10_4_15PL & MG10_4_16PL & MG10_4_17PL & MG10_4_18PL & \ + MG10_4_19PL & MG10_4_110PL & MG10_4_111PL & MG10_4_112PL & \ + MG10_4_113PL & MG10_4_114PL & MG10_4_115PL & MG10_4_116PL) +// End of MG10_4: +// Beginning of MG105: +#if (G10_1PL >= G10_5PL) || (G10_1PL == 0) +#define MG10_5_11PL ~(1 << 0) +#else +#define MG10_5_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_5PL) || (G10_2PL == 0) +#define MG10_5_12PL ~(1 << 1) +#else +#define MG10_5_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_5PL) || (G10_3PL == 0) +#define MG10_5_13PL ~(1 << 2) +#else +#define MG10_5_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_5PL) || (G10_4PL == 0) +#define MG10_5_14PL ~(1 << 3) +#else +#define MG10_5_14PL 0xFFFF +#endif + +#if (G10_6PL >= G10_5PL) || (G10_6PL == 0) +#define MG10_5_16PL ~(1 << 5) +#else +#define MG10_5_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_5PL) || (G10_7PL == 0) +#define MG10_5_17PL ~(1 << 6) +#else +#define MG10_5_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_5PL) || (G10_8PL == 0) +#define MG10_5_18PL ~(1 << 7) +#else +#define MG10_5_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_5PL) || (G10_9PL == 0) +#define MG10_5_19PL ~(1 << 8) +#else +#define MG10_5_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_5PL) || (G10_10PL == 0) +#define MG10_5_110PL ~(1 << 9) +#else +#define MG10_5_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_5PL) || (G10_11PL == 0) +#define MG10_5_111PL ~(1 << 10) +#else +#define MG10_5_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_5PL) || (G10_12PL == 0) +#define MG10_5_112PL ~(1 << 11) +#else +#define MG10_5_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_5PL) || (G10_13PL == 0) +#define MG10_5_113PL ~(1 << 12) +#else +#define MG10_5_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_5PL) || (G10_14PL == 0) +#define MG10_5_114PL ~(1 << 13) +#else +#define MG10_5_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_5PL) || (G10_15PL == 0) +#define MG10_5_115PL ~(1 << 14) +#else +#define MG10_5_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_5PL) || (G10_16PL == 0) +#define MG10_5_116PL ~(1 << 15) +#else +#define MG10_5_116PL 0xFFFF +#endif + +#define MG10_5_15PL 0xFFEF +#define MG10_5 (MG10_5_11PL & MG10_5_12PL & MG10_5_13PL & MG10_5_14PL & \ + MG10_5_15PL & MG10_5_16PL & MG10_5_17PL & MG10_5_18PL & \ + MG10_5_19PL & MG10_5_110PL & MG10_5_111PL & MG10_5_112PL & \ + MG10_5_113PL & MG10_5_114PL & MG10_5_115PL & MG10_5_116PL) +// End of MG10_5: +// Beginning of MG106: +#if (G10_1PL >= G10_6PL) || (G10_1PL == 0) +#define MG10_6_11PL ~(1 << 0) +#else +#define MG10_6_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_6PL) || (G10_2PL == 0) +#define MG10_6_12PL ~(1 << 1) +#else +#define MG10_6_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_6PL) || (G10_3PL == 0) +#define MG10_6_13PL ~(1 << 2) +#else +#define MG10_6_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_6PL) || (G10_4PL == 0) +#define MG10_6_14PL ~(1 << 3) +#else +#define MG10_6_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_6PL) || (G10_5PL == 0) +#define MG10_6_15PL ~(1 << 4) +#else +#define MG10_6_15PL 0xFFFF +#endif + +#if (G10_7PL >= G10_6PL) || (G10_7PL == 0) +#define MG10_6_17PL ~(1 << 6) +#else +#define MG10_6_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_6PL) || (G10_8PL == 0) +#define MG10_6_18PL ~(1 << 7) +#else +#define MG10_6_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_6PL) || (G10_9PL == 0) +#define MG10_6_19PL ~(1 << 8) +#else +#define MG10_6_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_6PL) || (G10_10PL == 0) +#define MG10_6_110PL ~(1 << 9) +#else +#define MG10_6_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_6PL) || (G10_11PL == 0) +#define MG10_6_111PL ~(1 << 10) +#else +#define MG10_6_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_6PL) || (G10_12PL == 0) +#define MG10_6_112PL ~(1 << 11) +#else +#define MG10_6_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_6PL) || (G10_13PL == 0) +#define MG10_6_113PL ~(1 << 12) +#else +#define MG10_6_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_6PL) || (G10_14PL == 0) +#define MG10_6_114PL ~(1 << 13) +#else +#define MG10_6_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_6PL) || (G10_15PL == 0) +#define MG10_6_115PL ~(1 << 14) +#else +#define MG10_6_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_6PL) || (G10_16PL == 0) +#define MG10_6_116PL ~(1 << 15) +#else +#define MG10_6_116PL 0xFFFF +#endif + +#define MG10_6_16PL 0xFFDF +#define MG10_6 (MG10_6_11PL & MG10_6_12PL & MG10_6_13PL & MG10_6_14PL & \ + MG10_6_15PL & MG10_6_16PL & MG10_6_17PL & MG10_6_18PL & \ + MG10_6_19PL & MG10_6_110PL & MG10_6_111PL & MG10_6_112PL & \ + MG10_6_113PL & MG10_6_114PL & MG10_6_115PL & MG10_6_116PL) +// End of MG10_6: +// Beginning of MG107: +#if (G10_1PL >= G10_7PL) || (G10_1PL == 0) +#define MG10_7_11PL ~(1 << 0) +#else +#define MG10_7_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_7PL) || (G10_2PL == 0) +#define MG10_7_12PL ~(1 << 1) +#else +#define MG10_7_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_7PL) || (G10_3PL == 0) +#define MG10_7_13PL ~(1 << 2) +#else +#define MG10_7_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_7PL) || (G10_4PL == 0) +#define MG10_7_14PL ~(1 << 3) +#else +#define MG10_7_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_7PL) || (G10_5PL == 0) +#define MG10_7_15PL ~(1 << 4) +#else +#define MG10_7_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_7PL) || (G10_6PL == 0) +#define MG10_7_16PL ~(1 << 5) +#else +#define MG10_7_16PL 0xFFFF +#endif + +#if (G10_8PL >= G10_7PL) || (G10_8PL == 0) +#define MG10_7_18PL ~(1 << 7) +#else +#define MG10_7_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_7PL) || (G10_9PL == 0) +#define MG10_7_19PL ~(1 << 8) +#else +#define MG10_7_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_7PL) || (G10_10PL == 0) +#define MG10_7_110PL ~(1 << 9) +#else +#define MG10_7_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_7PL) || (G10_11PL == 0) +#define MG10_7_111PL ~(1 << 10) +#else +#define MG10_7_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_7PL) || (G10_12PL == 0) +#define MG10_7_112PL ~(1 << 11) +#else +#define MG10_7_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_7PL) || (G10_13PL == 0) +#define MG10_7_113PL ~(1 << 12) +#else +#define MG10_7_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_7PL) || (G10_14PL == 0) +#define MG10_7_114PL ~(1 << 13) +#else +#define MG10_7_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_7PL) || (G10_15PL == 0) +#define MG10_7_115PL ~(1 << 14) +#else +#define MG10_7_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_7PL) || (G10_16PL == 0) +#define MG10_7_116PL ~(1 << 15) +#else +#define MG10_7_116PL 0xFFFF +#endif + +#define MG10_7_17PL 0xFFBF +#define MG10_7 (MG10_7_11PL & MG10_7_12PL & MG10_7_13PL & MG10_7_14PL & \ + MG10_7_15PL & MG10_7_16PL & MG10_7_17PL & MG10_7_18PL & \ + MG10_7_19PL & MG10_7_110PL & MG10_7_111PL & MG10_7_112PL & \ + MG10_7_113PL & MG10_7_114PL & MG10_7_115PL & MG10_7_116PL) +// End of MG10_7: +// Beginning of MG108: +#if (G10_1PL >= G10_8PL) || (G10_1PL == 0) +#define MG10_8_11PL ~(1 << 0) +#else +#define MG10_8_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_8PL) || (G10_2PL == 0) +#define MG10_8_12PL ~(1 << 1) +#else +#define MG10_8_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_8PL) || (G10_3PL == 0) +#define MG10_8_13PL ~(1 << 2) +#else +#define MG10_8_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_8PL) || (G10_4PL == 0) +#define MG10_8_14PL ~(1 << 3) +#else +#define MG10_8_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_8PL) || (G10_5PL == 0) +#define MG10_8_15PL ~(1 << 4) +#else +#define MG10_8_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_8PL) || (G10_6PL == 0) +#define MG10_8_16PL ~(1 << 5) +#else +#define MG10_8_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_8PL) || (G10_7PL == 0) +#define MG10_8_17PL ~(1 << 6) +#else +#define MG10_8_17PL 0xFFFF +#endif + +#if (G10_9PL >= G10_8PL) || (G10_9PL == 0) +#define MG10_8_19PL ~(1 << 8) +#else +#define MG10_8_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_8PL) || (G10_10PL == 0) +#define MG10_8_110PL ~(1 << 9) +#else +#define MG10_8_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_8PL) || (G10_11PL == 0) +#define MG10_8_111PL ~(1 << 10) +#else +#define MG10_8_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_8PL) || (G10_12PL == 0) +#define MG10_8_112PL ~(1 << 11) +#else +#define MG10_8_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_8PL) || (G10_13PL == 0) +#define MG10_8_113PL ~(1 << 12) +#else +#define MG10_8_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_8PL) || (G10_14PL == 0) +#define MG10_8_114PL ~(1 << 13) +#else +#define MG10_8_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_8PL) || (G10_15PL == 0) +#define MG10_8_115PL ~(1 << 14) +#else +#define MG10_8_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_8PL) || (G10_16PL == 0) +#define MG10_8_116PL ~(1 << 15) +#else +#define MG10_8_116PL 0xFFFF +#endif + +#define MG10_8_18PL 0xFF7F +#define MG10_8 (MG10_8_11PL & MG10_8_12PL & MG10_8_13PL & MG10_8_14PL & \ + MG10_8_15PL & MG10_8_16PL & MG10_8_17PL & MG10_8_18PL & \ + MG10_8_19PL & MG10_8_110PL & MG10_8_111PL & MG10_8_112PL & \ + MG10_8_113PL & MG10_8_114PL & MG10_8_115PL & MG10_8_116PL) +// End of MG10_8: +// Beginning of MG109: +#if (G10_1PL >= G10_9PL) || (G10_1PL == 0) +#define MG10_9_11PL ~(1 << 0) +#else +#define MG10_9_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_9PL) || (G10_2PL == 0) +#define MG10_9_12PL ~(1 << 1) +#else +#define MG10_9_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_9PL) || (G10_3PL == 0) +#define MG10_9_13PL ~(1 << 2) +#else +#define MG10_9_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_9PL) || (G10_4PL == 0) +#define MG10_9_14PL ~(1 << 3) +#else +#define MG10_9_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_9PL) || (G10_5PL == 0) +#define MG10_9_15PL ~(1 << 4) +#else +#define MG10_9_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_9PL) || (G10_6PL == 0) +#define MG10_9_16PL ~(1 << 5) +#else +#define MG10_9_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_9PL) || (G10_7PL == 0) +#define MG10_9_17PL ~(1 << 6) +#else +#define MG10_9_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_9PL) || (G10_8PL == 0) +#define MG10_9_18PL ~(1 << 7) +#else +#define MG10_9_18PL 0xFFFF +#endif + +#if (G10_10PL >= G10_9PL) || (G10_10PL == 0) +#define MG10_9_110PL ~(1 << 9) +#else +#define MG10_9_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_9PL) || (G10_11PL == 0) +#define MG10_9_111PL ~(1 << 10) +#else +#define MG10_9_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_9PL) || (G10_12PL == 0) +#define MG10_9_112PL ~(1 << 11) +#else +#define MG10_9_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_9PL) || (G10_13PL == 0) +#define MG10_9_113PL ~(1 << 12) +#else +#define MG10_9_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_9PL) || (G10_14PL == 0) +#define MG10_9_114PL ~(1 << 13) +#else +#define MG10_9_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_9PL) || (G10_15PL == 0) +#define MG10_9_115PL ~(1 << 14) +#else +#define MG10_9_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_9PL) || (G10_16PL == 0) +#define MG10_9_116PL ~(1 << 15) +#else +#define MG10_9_116PL 0xFFFF +#endif + +#define MG10_9_19PL 0xFEFF +#define MG10_9 (MG10_9_11PL & MG10_9_12PL & MG10_9_13PL & MG10_9_14PL & \ + MG10_9_15PL & MG10_9_16PL & MG10_9_17PL & MG10_9_18PL & \ + MG10_9_19PL & MG10_9_110PL & MG10_9_111PL & MG10_9_112PL & \ + MG10_9_113PL & MG10_9_114PL & MG10_9_115PL & MG10_9_116PL) +// End of MG10_9: +// Beginning of MG1010: +#if (G10_1PL >= G10_10PL) || (G10_1PL == 0) +#define MG10_10_11PL ~(1 << 0) +#else +#define MG10_10_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_10PL) || (G10_2PL == 0) +#define MG10_10_12PL ~(1 << 1) +#else +#define MG10_10_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_10PL) || (G10_3PL == 0) +#define MG10_10_13PL ~(1 << 2) +#else +#define MG10_10_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_10PL) || (G10_4PL == 0) +#define MG10_10_14PL ~(1 << 3) +#else +#define MG10_10_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_10PL) || (G10_5PL == 0) +#define MG10_10_15PL ~(1 << 4) +#else +#define MG10_10_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_10PL) || (G10_6PL == 0) +#define MG10_10_16PL ~(1 << 5) +#else +#define MG10_10_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_10PL) || (G10_7PL == 0) +#define MG10_10_17PL ~(1 << 6) +#else +#define MG10_10_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_10PL) || (G10_8PL == 0) +#define MG10_10_18PL ~(1 << 7) +#else +#define MG10_10_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_10PL) || (G10_9PL == 0) +#define MG10_10_19PL ~(1 << 8) +#else +#define MG10_10_19PL 0xFFFF +#endif + +#if (G10_11PL >= G10_10PL) || (G10_11PL == 0) +#define MG10_10_111PL ~(1 << 10) +#else +#define MG10_10_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_10PL) || (G10_12PL == 0) +#define MG10_10_112PL ~(1 << 11) +#else +#define MG10_10_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_10PL) || (G10_13PL == 0) +#define MG10_10_113PL ~(1 << 12) +#else +#define MG10_10_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_10PL) || (G10_14PL == 0) +#define MG10_10_114PL ~(1 << 13) +#else +#define MG10_10_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_10PL) || (G10_15PL == 0) +#define MG10_10_115PL ~(1 << 14) +#else +#define MG10_10_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_10PL) || (G10_16PL == 0) +#define MG10_10_116PL ~(1 << 15) +#else +#define MG10_10_116PL 0xFFFF +#endif + +#define MG10_10_110PL 0xFDFF +#define MG10_10 (MG10_10_11PL & MG10_10_12PL & MG10_10_13PL & MG10_10_14PL & \ + MG10_10_15PL & MG10_10_16PL & MG10_10_17PL & MG10_10_18PL & \ + MG10_10_19PL & MG10_10_110PL & MG10_10_111PL & MG10_10_112PL & \ + MG10_10_113PL & MG10_10_114PL & MG10_10_115PL & MG10_10_116PL) +// End of MG10_10: +// Beginning of MG1011: +#if (G10_1PL >= G10_11PL) || (G10_1PL == 0) +#define MG10_11_11PL ~(1 << 0) +#else +#define MG10_11_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_11PL) || (G10_2PL == 0) +#define MG10_11_12PL ~(1 << 1) +#else +#define MG10_11_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_11PL) || (G10_3PL == 0) +#define MG10_11_13PL ~(1 << 2) +#else +#define MG10_11_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_11PL) || (G10_4PL == 0) +#define MG10_11_14PL ~(1 << 3) +#else +#define MG10_11_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_11PL) || (G10_5PL == 0) +#define MG10_11_15PL ~(1 << 4) +#else +#define MG10_11_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_11PL) || (G10_6PL == 0) +#define MG10_11_16PL ~(1 << 5) +#else +#define MG10_11_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_11PL) || (G10_7PL == 0) +#define MG10_11_17PL ~(1 << 6) +#else +#define MG10_11_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_11PL) || (G10_8PL == 0) +#define MG10_11_18PL ~(1 << 7) +#else +#define MG10_11_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_11PL) || (G10_9PL == 0) +#define MG10_11_19PL ~(1 << 8) +#else +#define MG10_11_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_11PL) || (G10_10PL == 0) +#define MG10_11_110PL ~(1 << 9) +#else +#define MG10_11_110PL 0xFFFF +#endif + +#if (G10_12PL >= G10_11PL) || (G10_12PL == 0) +#define MG10_11_112PL ~(1 << 11) +#else +#define MG10_11_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_11PL) || (G10_13PL == 0) +#define MG10_11_113PL ~(1 << 12) +#else +#define MG10_11_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_11PL) || (G10_14PL == 0) +#define MG10_11_114PL ~(1 << 13) +#else +#define MG10_11_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_11PL) || (G10_15PL == 0) +#define MG10_11_115PL ~(1 << 14) +#else +#define MG10_11_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_11PL) || (G10_16PL == 0) +#define MG10_11_116PL ~(1 << 15) +#else +#define MG10_11_116PL 0xFFFF +#endif + +#define MG10_11_111PL 0xFBFF +#define MG10_11 (MG10_11_11PL & MG10_11_12PL & MG10_11_13PL & MG10_11_14PL & \ + MG10_11_15PL & MG10_11_16PL & MG10_11_17PL & MG10_11_18PL & \ + MG10_11_19PL & MG10_11_110PL & MG10_11_111PL & MG10_11_112PL & \ + MG10_11_113PL & MG10_11_114PL & MG10_11_115PL & MG10_11_116PL) +// End of MG10_11: +// Beginning of MG1012: +#if (G10_1PL >= G10_12PL) || (G10_1PL == 0) +#define MG10_12_11PL ~(1 << 0) +#else +#define MG10_12_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_12PL) || (G10_2PL == 0) +#define MG10_12_12PL ~(1 << 1) +#else +#define MG10_12_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_12PL) || (G10_3PL == 0) +#define MG10_12_13PL ~(1 << 2) +#else +#define MG10_12_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_12PL) || (G10_4PL == 0) +#define MG10_12_14PL ~(1 << 3) +#else +#define MG10_12_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_12PL) || (G10_5PL == 0) +#define MG10_12_15PL ~(1 << 4) +#else +#define MG10_12_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_12PL) || (G10_6PL == 0) +#define MG10_12_16PL ~(1 << 5) +#else +#define MG10_12_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_12PL) || (G10_7PL == 0) +#define MG10_12_17PL ~(1 << 6) +#else +#define MG10_12_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_12PL) || (G10_8PL == 0) +#define MG10_12_18PL ~(1 << 7) +#else +#define MG10_12_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_12PL) || (G10_9PL == 0) +#define MG10_12_19PL ~(1 << 8) +#else +#define MG10_12_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_12PL) || (G10_10PL == 0) +#define MG10_12_110PL ~(1 << 9) +#else +#define MG10_12_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_12PL) || (G10_11PL == 0) +#define MG10_12_111PL ~(1 << 10) +#else +#define MG10_12_111PL 0xFFFF +#endif + +#if (G10_13PL >= G10_12PL) || (G10_13PL == 0) +#define MG10_12_113PL ~(1 << 12) +#else +#define MG10_12_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_12PL) || (G10_14PL == 0) +#define MG10_12_114PL ~(1 << 13) +#else +#define MG10_12_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_12PL) || (G10_15PL == 0) +#define MG10_12_115PL ~(1 << 14) +#else +#define MG10_12_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_12PL) || (G10_16PL == 0) +#define MG10_12_116PL ~(1 << 15) +#else +#define MG10_12_116PL 0xFFFF +#endif + +#define MG10_12_112PL 0xF7FF +#define MG10_12 (MG10_12_11PL & MG10_12_12PL & MG10_12_13PL & MG10_12_14PL & \ + MG10_12_15PL & MG10_12_16PL & MG10_12_17PL & MG10_12_18PL & \ + MG10_12_19PL & MG10_12_110PL & MG10_12_111PL & MG10_12_112PL & \ + MG10_12_113PL & MG10_12_114PL & MG10_12_115PL & MG10_12_116PL) +// End of MG10_12: +// Beginning of MG1013: +#if (G10_1PL >= G10_13PL) || (G10_1PL == 0) +#define MG10_13_11PL ~(1 << 0) +#else +#define MG10_13_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_13PL) || (G10_2PL == 0) +#define MG10_13_12PL ~(1 << 1) +#else +#define MG10_13_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_13PL) || (G10_3PL == 0) +#define MG10_13_13PL ~(1 << 2) +#else +#define MG10_13_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_13PL) || (G10_4PL == 0) +#define MG10_13_14PL ~(1 << 3) +#else +#define MG10_13_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_13PL) || (G10_5PL == 0) +#define MG10_13_15PL ~(1 << 4) +#else +#define MG10_13_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_13PL) || (G10_6PL == 0) +#define MG10_13_16PL ~(1 << 5) +#else +#define MG10_13_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_13PL) || (G10_7PL == 0) +#define MG10_13_17PL ~(1 << 6) +#else +#define MG10_13_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_13PL) || (G10_8PL == 0) +#define MG10_13_18PL ~(1 << 7) +#else +#define MG10_13_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_13PL) || (G10_9PL == 0) +#define MG10_13_19PL ~(1 << 8) +#else +#define MG10_13_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_13PL) || (G10_10PL == 0) +#define MG10_13_110PL ~(1 << 9) +#else +#define MG10_13_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_13PL) || (G10_11PL == 0) +#define MG10_13_111PL ~(1 << 10) +#else +#define MG10_13_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_13PL) || (G10_12PL == 0) +#define MG10_13_112PL ~(1 << 11) +#else +#define MG10_13_112PL 0xFFFF +#endif + +#if (G10_14PL >= G10_13PL) || (G10_14PL == 0) +#define MG10_13_114PL ~(1 << 13) +#else +#define MG10_13_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_13PL) || (G10_15PL == 0) +#define MG10_13_115PL ~(1 << 14) +#else +#define MG10_13_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_13PL) || (G10_16PL == 0) +#define MG10_13_116PL ~(1 << 15) +#else +#define MG10_13_116PL 0xFFFF +#endif + +#define MG10_13_113PL 0xEFFF +#define MG10_13 (MG10_13_11PL & MG10_13_12PL & MG10_13_13PL & MG10_13_14PL & \ + MG10_13_15PL & MG10_13_16PL & MG10_13_17PL & MG10_13_18PL & \ + MG10_13_19PL & MG10_13_110PL & MG10_13_111PL & MG10_13_112PL & \ + MG10_13_113PL & MG10_13_114PL & MG10_13_115PL & MG10_13_116PL) +// End of MG10_13: +// Beginning of MG1014: +#if (G10_1PL >= G10_14PL) || (G10_1PL == 0) +#define MG10_14_11PL ~(1 << 0) +#else +#define MG10_14_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_14PL) || (G10_2PL == 0) +#define MG10_14_12PL ~(1 << 1) +#else +#define MG10_14_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_14PL) || (G10_3PL == 0) +#define MG10_14_13PL ~(1 << 2) +#else +#define MG10_14_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_14PL) || (G10_4PL == 0) +#define MG10_14_14PL ~(1 << 3) +#else +#define MG10_14_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_14PL) || (G10_5PL == 0) +#define MG10_14_15PL ~(1 << 4) +#else +#define MG10_14_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_14PL) || (G10_6PL == 0) +#define MG10_14_16PL ~(1 << 5) +#else +#define MG10_14_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_14PL) || (G10_7PL == 0) +#define MG10_14_17PL ~(1 << 6) +#else +#define MG10_14_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_14PL) || (G10_8PL == 0) +#define MG10_14_18PL ~(1 << 7) +#else +#define MG10_14_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_14PL) || (G10_9PL == 0) +#define MG10_14_19PL ~(1 << 8) +#else +#define MG10_14_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_14PL) || (G10_10PL == 0) +#define MG10_14_110PL ~(1 << 9) +#else +#define MG10_14_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_14PL) || (G10_11PL == 0) +#define MG10_14_111PL ~(1 << 10) +#else +#define MG10_14_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_14PL) || (G10_12PL == 0) +#define MG10_14_112PL ~(1 << 11) +#else +#define MG10_14_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_14PL) || (G10_13PL == 0) +#define MG10_14_113PL ~(1 << 12) +#else +#define MG10_14_113PL 0xFFFF +#endif + +#if (G10_15PL >= G10_14PL) || (G10_15PL == 0) +#define MG10_14_115PL ~(1 << 14) +#else +#define MG10_14_115PL 0xFFFF +#endif + +#if (G10_16PL >= G10_14PL) || (G10_16PL == 0) +#define MG10_14_116PL ~(1 << 15) +#else +#define MG10_14_116PL 0xFFFF +#endif + +#define MG10_14_114PL 0xDFFF +#define MG10_14 (MG10_14_11PL & MG10_14_12PL & MG10_14_13PL & MG10_14_14PL & \ + MG10_14_15PL & MG10_14_16PL & MG10_14_17PL & MG10_14_18PL & \ + MG10_14_19PL & MG10_14_110PL & MG10_14_111PL & MG10_14_112PL & \ + MG10_14_113PL & MG10_14_114PL & MG10_14_115PL & MG10_14_116PL) +// End of MG10_14: +// Beginning of MG1015: +#if (G10_1PL >= G10_15PL) || (G10_1PL == 0) +#define MG10_15_11PL ~(1 << 0) +#else +#define MG10_15_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_15PL) || (G10_2PL == 0) +#define MG10_15_12PL ~(1 << 1) +#else +#define MG10_15_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_15PL) || (G10_3PL == 0) +#define MG10_15_13PL ~(1 << 2) +#else +#define MG10_15_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_15PL) || (G10_4PL == 0) +#define MG10_15_14PL ~(1 << 3) +#else +#define MG10_15_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_15PL) || (G10_5PL == 0) +#define MG10_15_15PL ~(1 << 4) +#else +#define MG10_15_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_15PL) || (G10_6PL == 0) +#define MG10_15_16PL ~(1 << 5) +#else +#define MG10_15_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_15PL) || (G10_7PL == 0) +#define MG10_15_17PL ~(1 << 6) +#else +#define MG10_15_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_15PL) || (G10_8PL == 0) +#define MG10_15_18PL ~(1 << 7) +#else +#define MG10_15_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_15PL) || (G10_9PL == 0) +#define MG10_15_19PL ~(1 << 8) +#else +#define MG10_15_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_15PL) || (G10_10PL == 0) +#define MG10_15_110PL ~(1 << 9) +#else +#define MG10_15_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_15PL) || (G10_11PL == 0) +#define MG10_15_111PL ~(1 << 10) +#else +#define MG10_15_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_15PL) || (G10_12PL == 0) +#define MG10_15_112PL ~(1 << 11) +#else +#define MG10_15_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_15PL) || (G10_13PL == 0) +#define MG10_15_113PL ~(1 << 12) +#else +#define MG10_15_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_15PL) || (G10_14PL == 0) +#define MG10_15_114PL ~(1 << 13) +#else +#define MG10_15_114PL 0xFFFF +#endif + +#if (G10_16PL >= G10_15PL) || (G10_16PL == 0) +#define MG10_15_116PL ~(1 << 15) +#else +#define MG10_15_116PL 0xFFFF +#endif + +#define MG10_15_115PL 0xBFFF +#define MG10_15 (MG10_15_11PL & MG10_15_12PL & MG10_15_13PL & MG10_15_14PL & \ + MG10_15_15PL & MG10_15_16PL & MG10_15_17PL & MG10_15_18PL & \ + MG10_15_19PL & MG10_15_110PL & MG10_15_111PL & MG10_15_112PL & \ + MG10_15_113PL & MG10_15_114PL & MG10_15_115PL & MG10_15_116PL) +// End of MG10_15: +// Beginning of MG1016: +#if (G10_1PL >= G10_16PL) || (G10_1PL == 0) +#define MG10_16_11PL ~(1 << 0) +#else +#define MG10_16_11PL 0xFFFF +#endif + +#if (G10_2PL >= G10_16PL) || (G10_2PL == 0) +#define MG10_16_12PL ~(1 << 1) +#else +#define MG10_16_12PL 0xFFFF +#endif + +#if (G10_3PL >= G10_16PL) || (G10_3PL == 0) +#define MG10_16_13PL ~(1 << 2) +#else +#define MG10_16_13PL 0xFFFF +#endif + +#if (G10_4PL >= G10_16PL) || (G10_4PL == 0) +#define MG10_16_14PL ~(1 << 3) +#else +#define MG10_16_14PL 0xFFFF +#endif + +#if (G10_5PL >= G10_16PL) || (G10_5PL == 0) +#define MG10_16_15PL ~(1 << 4) +#else +#define MG10_16_15PL 0xFFFF +#endif + +#if (G10_6PL >= G10_16PL) || (G10_6PL == 0) +#define MG10_16_16PL ~(1 << 5) +#else +#define MG10_16_16PL 0xFFFF +#endif + +#if (G10_7PL >= G10_16PL) || (G10_7PL == 0) +#define MG10_16_17PL ~(1 << 6) +#else +#define MG10_16_17PL 0xFFFF +#endif + +#if (G10_8PL >= G10_16PL) || (G10_8PL == 0) +#define MG10_16_18PL ~(1 << 7) +#else +#define MG10_16_18PL 0xFFFF +#endif + +#if (G10_9PL >= G10_16PL) || (G10_9PL == 0) +#define MG10_16_19PL ~(1 << 8) +#else +#define MG10_16_19PL 0xFFFF +#endif + +#if (G10_10PL >= G10_16PL) || (G10_10PL == 0) +#define MG10_16_110PL ~(1 << 9) +#else +#define MG10_16_110PL 0xFFFF +#endif + +#if (G10_11PL >= G10_16PL) || (G10_11PL == 0) +#define MG10_16_111PL ~(1 << 10) +#else +#define MG10_16_111PL 0xFFFF +#endif + +#if (G10_12PL >= G10_16PL) || (G10_12PL == 0) +#define MG10_16_112PL ~(1 << 11) +#else +#define MG10_16_112PL 0xFFFF +#endif + +#if (G10_13PL >= G10_16PL) || (G10_13PL == 0) +#define MG10_16_113PL ~(1 << 12) +#else +#define MG10_16_113PL 0xFFFF +#endif + +#if (G10_14PL >= G10_16PL) || (G10_14PL == 0) +#define MG10_16_114PL ~(1 << 13) +#else +#define MG10_16_114PL 0xFFFF +#endif + +#if (G10_15PL >= G10_16PL) || (G10_15PL == 0) +#define MG10_16_115PL ~(1 << 14) +#else +#define MG10_16_115PL 0xFFFF +#endif + +#define MG10_16_116PL 0x7FFF +#define MG10_16 (MG10_16_11PL & MG10_16_12PL & MG10_16_13PL & MG10_16_14PL & \ + MG10_16_15PL & MG10_16_16PL & MG10_16_17PL & MG10_16_18PL & \ + MG10_16_19PL & MG10_16_110PL & MG10_16_111PL & MG10_16_112PL & \ + MG10_16_113PL & MG10_16_114PL & MG10_16_115PL & MG10_16_116PL) +// End of MG10_16: + + +// +// Automatically generate PIEIER11 interrupt masks MG111 to MG1116: +// + +// Beginning of MG111: +#if (G11_2PL >= G11_1PL) || (G11_2PL == 0) +#define MG11_1_12PL ~(1 << 1) +#else +#define MG11_1_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_1PL) || (G11_3PL == 0) +#define MG11_1_13PL ~(1 << 2) +#else +#define MG11_1_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_1PL) || (G11_4PL == 0) +#define MG11_1_14PL ~(1 << 3) +#else +#define MG11_1_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_1PL) || (G11_5PL == 0) +#define MG11_1_15PL ~(1 << 4) +#else +#define MG11_1_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_1PL) || (G11_6PL == 0) +#define MG11_1_16PL ~(1 << 5) +#else +#define MG11_1_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_1PL) || (G11_7PL == 0) +#define MG11_1_17PL ~(1 << 6) +#else +#define MG11_1_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_1PL) || (G11_8PL == 0) +#define MG11_1_18PL ~(1 << 7) +#else +#define MG11_1_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_1PL) || (G11_9PL == 0) +#define MG11_1_19PL ~(1 << 8) +#else +#define MG11_1_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_1PL) || (G11_10PL == 0) +#define MG11_1_110PL ~(1 << 9) +#else +#define MG11_1_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_1PL) || (G11_11PL == 0) +#define MG11_1_111PL ~(1 << 10) +#else +#define MG11_1_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_1PL) || (G11_12PL == 0) +#define MG11_1_112PL ~(1 << 11) +#else +#define MG11_1_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_1PL) || (G11_13PL == 0) +#define MG11_1_113PL ~(1 << 12) +#else +#define MG11_1_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_1PL) || (G11_14PL == 0) +#define MG11_1_114PL ~(1 << 13) +#else +#define MG11_1_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_1PL) || (G11_15PL == 0) +#define MG11_1_115PL ~(1 << 14) +#else +#define MG11_1_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_1PL) || (G11_16PL == 0) +#define MG11_1_116PL ~(1 << 15) +#else +#define MG11_1_116PL 0xFFFF +#endif + +#define MG11_1_11PL 0xFFFE +#define MG11_1 (MG11_1_11PL & MG11_1_12PL & MG11_1_13PL & MG11_1_14PL & \ + MG11_1_15PL & MG11_1_16PL & MG11_1_17PL & MG11_1_18PL & \ + MG11_1_19PL & MG11_1_110PL & MG11_1_111PL & MG11_1_112PL & \ + MG11_1_113PL & MG11_1_114PL & MG11_1_115PL & MG11_1_116PL) +// End of MG11_1: +// Beginning of MG112: +#if (G11_1PL >= G11_2PL) || (G11_1PL == 0) +#define MG11_2_11PL ~(1 << 0) +#else +#define MG11_2_11PL 0xFFFF +#endif + +#if (G11_3PL >= G11_2PL) || (G11_3PL == 0) +#define MG11_2_13PL ~(1 << 2) +#else +#define MG11_2_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_2PL) || (G11_4PL == 0) +#define MG11_2_14PL ~(1 << 3) +#else +#define MG11_2_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_2PL) || (G11_5PL == 0) +#define MG11_2_15PL ~(1 << 4) +#else +#define MG11_2_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_2PL) || (G11_6PL == 0) +#define MG11_2_16PL ~(1 << 5) +#else +#define MG11_2_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_2PL) || (G11_7PL == 0) +#define MG11_2_17PL ~(1 << 6) +#else +#define MG11_2_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_2PL) || (G11_8PL == 0) +#define MG11_2_18PL ~(1 << 7) +#else +#define MG11_2_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_2PL) || (G11_9PL == 0) +#define MG11_2_19PL ~(1 << 8) +#else +#define MG11_2_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_2PL) || (G11_10PL == 0) +#define MG11_2_110PL ~(1 << 9) +#else +#define MG11_2_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_2PL) || (G11_11PL == 0) +#define MG11_2_111PL ~(1 << 10) +#else +#define MG11_2_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_2PL) || (G11_12PL == 0) +#define MG11_2_112PL ~(1 << 11) +#else +#define MG11_2_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_2PL) || (G11_13PL == 0) +#define MG11_2_113PL ~(1 << 12) +#else +#define MG11_2_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_2PL) || (G11_14PL == 0) +#define MG11_2_114PL ~(1 << 13) +#else +#define MG11_2_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_2PL) || (G11_15PL == 0) +#define MG11_2_115PL ~(1 << 14) +#else +#define MG11_2_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_2PL) || (G11_16PL == 0) +#define MG11_2_116PL ~(1 << 15) +#else +#define MG11_2_116PL 0xFFFF +#endif + +#define MG11_2_12PL 0xFFFD +#define MG11_2 (MG11_2_11PL & MG11_2_12PL & MG11_2_13PL & MG11_2_14PL & \ + MG11_2_15PL & MG11_2_16PL & MG11_2_17PL & MG11_2_18PL & \ + MG11_2_19PL & MG11_2_110PL & MG11_2_111PL & MG11_2_112PL & \ + MG11_2_113PL & MG11_2_114PL & MG11_2_115PL & MG11_2_116PL) +// End of MG11_2: +// Beginning of MG113: +#if (G11_1PL >= G11_3PL) || (G11_1PL == 0) +#define MG11_3_11PL ~(1 << 0) +#else +#define MG11_3_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_3PL) || (G11_2PL == 0) +#define MG11_3_12PL ~(1 << 1) +#else +#define MG11_3_12PL 0xFFFF +#endif + +#if (G11_4PL >= G11_3PL) || (G11_4PL == 0) +#define MG11_3_14PL ~(1 << 3) +#else +#define MG11_3_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_3PL) || (G11_5PL == 0) +#define MG11_3_15PL ~(1 << 4) +#else +#define MG11_3_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_3PL) || (G11_6PL == 0) +#define MG11_3_16PL ~(1 << 5) +#else +#define MG11_3_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_3PL) || (G11_7PL == 0) +#define MG11_3_17PL ~(1 << 6) +#else +#define MG11_3_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_3PL) || (G11_8PL == 0) +#define MG11_3_18PL ~(1 << 7) +#else +#define MG11_3_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_3PL) || (G11_9PL == 0) +#define MG11_3_19PL ~(1 << 8) +#else +#define MG11_3_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_3PL) || (G11_10PL == 0) +#define MG11_3_110PL ~(1 << 9) +#else +#define MG11_3_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_3PL) || (G11_11PL == 0) +#define MG11_3_111PL ~(1 << 10) +#else +#define MG11_3_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_3PL) || (G11_12PL == 0) +#define MG11_3_112PL ~(1 << 11) +#else +#define MG11_3_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_3PL) || (G11_13PL == 0) +#define MG11_3_113PL ~(1 << 12) +#else +#define MG11_3_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_3PL) || (G11_14PL == 0) +#define MG11_3_114PL ~(1 << 13) +#else +#define MG11_3_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_3PL) || (G11_15PL == 0) +#define MG11_3_115PL ~(1 << 14) +#else +#define MG11_3_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_3PL) || (G11_16PL == 0) +#define MG11_3_116PL ~(1 << 15) +#else +#define MG11_3_116PL 0xFFFF +#endif + +#define MG11_3_13PL 0xFFFB +#define MG11_3 (MG11_3_11PL & MG11_3_12PL & MG11_3_13PL & MG11_3_14PL & \ + MG11_3_15PL & MG11_3_16PL & MG11_3_17PL & MG11_3_18PL & \ + MG11_3_19PL & MG11_3_110PL & MG11_3_111PL & MG11_3_112PL & \ + MG11_3_113PL & MG11_3_114PL & MG11_3_115PL & MG11_3_116PL) +// End of MG11_3: +// Beginning of MG114: +#if (G11_1PL >= G11_4PL) || (G11_1PL == 0) +#define MG11_4_11PL ~(1 << 0) +#else +#define MG11_4_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_4PL) || (G11_2PL == 0) +#define MG11_4_12PL ~(1 << 1) +#else +#define MG11_4_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_4PL) || (G11_3PL == 0) +#define MG11_4_13PL ~(1 << 2) +#else +#define MG11_4_13PL 0xFFFF +#endif + +#if (G11_5PL >= G11_4PL) || (G11_5PL == 0) +#define MG11_4_15PL ~(1 << 4) +#else +#define MG11_4_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_4PL) || (G11_6PL == 0) +#define MG11_4_16PL ~(1 << 5) +#else +#define MG11_4_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_4PL) || (G11_7PL == 0) +#define MG11_4_17PL ~(1 << 6) +#else +#define MG11_4_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_4PL) || (G11_8PL == 0) +#define MG11_4_18PL ~(1 << 7) +#else +#define MG11_4_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_4PL) || (G11_9PL == 0) +#define MG11_4_19PL ~(1 << 8) +#else +#define MG11_4_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_4PL) || (G11_10PL == 0) +#define MG11_4_110PL ~(1 << 9) +#else +#define MG11_4_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_4PL) || (G11_11PL == 0) +#define MG11_4_111PL ~(1 << 10) +#else +#define MG11_4_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_4PL) || (G11_12PL == 0) +#define MG11_4_112PL ~(1 << 11) +#else +#define MG11_4_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_4PL) || (G11_13PL == 0) +#define MG11_4_113PL ~(1 << 12) +#else +#define MG11_4_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_4PL) || (G11_14PL == 0) +#define MG11_4_114PL ~(1 << 13) +#else +#define MG11_4_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_4PL) || (G11_15PL == 0) +#define MG11_4_115PL ~(1 << 14) +#else +#define MG11_4_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_4PL) || (G11_16PL == 0) +#define MG11_4_116PL ~(1 << 15) +#else +#define MG11_4_116PL 0xFFFF +#endif + +#define MG11_4_14PL 0xFFF7 +#define MG11_4 (MG11_4_11PL & MG11_4_12PL & MG11_4_13PL & MG11_4_14PL & \ + MG11_4_15PL & MG11_4_16PL & MG11_4_17PL & MG11_4_18PL & \ + MG11_4_19PL & MG11_4_110PL & MG11_4_111PL & MG11_4_112PL & \ + MG11_4_113PL & MG11_4_114PL & MG11_4_115PL & MG11_4_116PL) +// End of MG11_4: +// Beginning of MG115: +#if (G11_1PL >= G11_5PL) || (G11_1PL == 0) +#define MG11_5_11PL ~(1 << 0) +#else +#define MG11_5_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_5PL) || (G11_2PL == 0) +#define MG11_5_12PL ~(1 << 1) +#else +#define MG11_5_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_5PL) || (G11_3PL == 0) +#define MG11_5_13PL ~(1 << 2) +#else +#define MG11_5_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_5PL) || (G11_4PL == 0) +#define MG11_5_14PL ~(1 << 3) +#else +#define MG11_5_14PL 0xFFFF +#endif + +#if (G11_6PL >= G11_5PL) || (G11_6PL == 0) +#define MG11_5_16PL ~(1 << 5) +#else +#define MG11_5_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_5PL) || (G11_7PL == 0) +#define MG11_5_17PL ~(1 << 6) +#else +#define MG11_5_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_5PL) || (G11_8PL == 0) +#define MG11_5_18PL ~(1 << 7) +#else +#define MG11_5_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_5PL) || (G11_9PL == 0) +#define MG11_5_19PL ~(1 << 8) +#else +#define MG11_5_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_5PL) || (G11_10PL == 0) +#define MG11_5_110PL ~(1 << 9) +#else +#define MG11_5_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_5PL) || (G11_11PL == 0) +#define MG11_5_111PL ~(1 << 10) +#else +#define MG11_5_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_5PL) || (G11_12PL == 0) +#define MG11_5_112PL ~(1 << 11) +#else +#define MG11_5_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_5PL) || (G11_13PL == 0) +#define MG11_5_113PL ~(1 << 12) +#else +#define MG11_5_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_5PL) || (G11_14PL == 0) +#define MG11_5_114PL ~(1 << 13) +#else +#define MG11_5_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_5PL) || (G11_15PL == 0) +#define MG11_5_115PL ~(1 << 14) +#else +#define MG11_5_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_5PL) || (G11_16PL == 0) +#define MG11_5_116PL ~(1 << 15) +#else +#define MG11_5_116PL 0xFFFF +#endif + +#define MG11_5_15PL 0xFFEF +#define MG11_5 (MG11_5_11PL & MG11_5_12PL & MG11_5_13PL & MG11_5_14PL & \ + MG11_5_15PL & MG11_5_16PL & MG11_5_17PL & MG11_5_18PL & \ + MG11_5_19PL & MG11_5_110PL & MG11_5_111PL & MG11_5_112PL & \ + MG11_5_113PL & MG11_5_114PL & MG11_5_115PL & MG11_5_116PL) +// End of MG11_5: +// Beginning of MG116: +#if (G11_1PL >= G11_6PL) || (G11_1PL == 0) +#define MG11_6_11PL ~(1 << 0) +#else +#define MG11_6_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_6PL) || (G11_2PL == 0) +#define MG11_6_12PL ~(1 << 1) +#else +#define MG11_6_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_6PL) || (G11_3PL == 0) +#define MG11_6_13PL ~(1 << 2) +#else +#define MG11_6_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_6PL) || (G11_4PL == 0) +#define MG11_6_14PL ~(1 << 3) +#else +#define MG11_6_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_6PL) || (G11_5PL == 0) +#define MG11_6_15PL ~(1 << 4) +#else +#define MG11_6_15PL 0xFFFF +#endif + +#if (G11_7PL >= G11_6PL) || (G11_7PL == 0) +#define MG11_6_17PL ~(1 << 6) +#else +#define MG11_6_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_6PL) || (G11_8PL == 0) +#define MG11_6_18PL ~(1 << 7) +#else +#define MG11_6_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_6PL) || (G11_9PL == 0) +#define MG11_6_19PL ~(1 << 8) +#else +#define MG11_6_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_6PL) || (G11_10PL == 0) +#define MG11_6_110PL ~(1 << 9) +#else +#define MG11_6_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_6PL) || (G11_11PL == 0) +#define MG11_6_111PL ~(1 << 10) +#else +#define MG11_6_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_6PL) || (G11_12PL == 0) +#define MG11_6_112PL ~(1 << 11) +#else +#define MG11_6_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_6PL) || (G11_13PL == 0) +#define MG11_6_113PL ~(1 << 12) +#else +#define MG11_6_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_6PL) || (G11_14PL == 0) +#define MG11_6_114PL ~(1 << 13) +#else +#define MG11_6_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_6PL) || (G11_15PL == 0) +#define MG11_6_115PL ~(1 << 14) +#else +#define MG11_6_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_6PL) || (G11_16PL == 0) +#define MG11_6_116PL ~(1 << 15) +#else +#define MG11_6_116PL 0xFFFF +#endif + +#define MG11_6_16PL 0xFFDF +#define MG11_6 (MG11_6_11PL & MG11_6_12PL & MG11_6_13PL & MG11_6_14PL & \ + MG11_6_15PL & MG11_6_16PL & MG11_6_17PL & MG11_6_18PL & \ + MG11_6_19PL & MG11_6_110PL & MG11_6_111PL & MG11_6_112PL & \ + MG11_6_113PL & MG11_6_114PL & MG11_6_115PL & MG11_6_116PL) +// End of MG11_6: +// Beginning of MG117: +#if (G11_1PL >= G11_7PL) || (G11_1PL == 0) +#define MG11_7_11PL ~(1 << 0) +#else +#define MG11_7_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_7PL) || (G11_2PL == 0) +#define MG11_7_12PL ~(1 << 1) +#else +#define MG11_7_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_7PL) || (G11_3PL == 0) +#define MG11_7_13PL ~(1 << 2) +#else +#define MG11_7_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_7PL) || (G11_4PL == 0) +#define MG11_7_14PL ~(1 << 3) +#else +#define MG11_7_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_7PL) || (G11_5PL == 0) +#define MG11_7_15PL ~(1 << 4) +#else +#define MG11_7_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_7PL) || (G11_6PL == 0) +#define MG11_7_16PL ~(1 << 5) +#else +#define MG11_7_16PL 0xFFFF +#endif + +#if (G11_8PL >= G11_7PL) || (G11_8PL == 0) +#define MG11_7_18PL ~(1 << 7) +#else +#define MG11_7_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_7PL) || (G11_9PL == 0) +#define MG11_7_19PL ~(1 << 8) +#else +#define MG11_7_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_7PL) || (G11_10PL == 0) +#define MG11_7_110PL ~(1 << 9) +#else +#define MG11_7_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_7PL) || (G11_11PL == 0) +#define MG11_7_111PL ~(1 << 10) +#else +#define MG11_7_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_7PL) || (G11_12PL == 0) +#define MG11_7_112PL ~(1 << 11) +#else +#define MG11_7_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_7PL) || (G11_13PL == 0) +#define MG11_7_113PL ~(1 << 12) +#else +#define MG11_7_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_7PL) || (G11_14PL == 0) +#define MG11_7_114PL ~(1 << 13) +#else +#define MG11_7_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_7PL) || (G11_15PL == 0) +#define MG11_7_115PL ~(1 << 14) +#else +#define MG11_7_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_7PL) || (G11_16PL == 0) +#define MG11_7_116PL ~(1 << 15) +#else +#define MG11_7_116PL 0xFFFF +#endif + +#define MG11_7_17PL 0xFFBF +#define MG11_7 (MG11_7_11PL & MG11_7_12PL & MG11_7_13PL & MG11_7_14PL & \ + MG11_7_15PL & MG11_7_16PL & MG11_7_17PL & MG11_7_18PL & \ + MG11_7_19PL & MG11_7_110PL & MG11_7_111PL & MG11_7_112PL & \ + MG11_7_113PL & MG11_7_114PL & MG11_7_115PL & MG11_7_116PL) +// End of MG11_7: +// Beginning of MG118: +#if (G11_1PL >= G11_8PL) || (G11_1PL == 0) +#define MG11_8_11PL ~(1 << 0) +#else +#define MG11_8_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_8PL) || (G11_2PL == 0) +#define MG11_8_12PL ~(1 << 1) +#else +#define MG11_8_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_8PL) || (G11_3PL == 0) +#define MG11_8_13PL ~(1 << 2) +#else +#define MG11_8_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_8PL) || (G11_4PL == 0) +#define MG11_8_14PL ~(1 << 3) +#else +#define MG11_8_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_8PL) || (G11_5PL == 0) +#define MG11_8_15PL ~(1 << 4) +#else +#define MG11_8_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_8PL) || (G11_6PL == 0) +#define MG11_8_16PL ~(1 << 5) +#else +#define MG11_8_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_8PL) || (G11_7PL == 0) +#define MG11_8_17PL ~(1 << 6) +#else +#define MG11_8_17PL 0xFFFF +#endif + +#if (G11_9PL >= G11_8PL) || (G11_9PL == 0) +#define MG11_8_19PL ~(1 << 8) +#else +#define MG11_8_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_8PL) || (G11_10PL == 0) +#define MG11_8_110PL ~(1 << 9) +#else +#define MG11_8_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_8PL) || (G11_11PL == 0) +#define MG11_8_111PL ~(1 << 10) +#else +#define MG11_8_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_8PL) || (G11_12PL == 0) +#define MG11_8_112PL ~(1 << 11) +#else +#define MG11_8_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_8PL) || (G11_13PL == 0) +#define MG11_8_113PL ~(1 << 12) +#else +#define MG11_8_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_8PL) || (G11_14PL == 0) +#define MG11_8_114PL ~(1 << 13) +#else +#define MG11_8_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_8PL) || (G11_15PL == 0) +#define MG11_8_115PL ~(1 << 14) +#else +#define MG11_8_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_8PL) || (G11_16PL == 0) +#define MG11_8_116PL ~(1 << 15) +#else +#define MG11_8_116PL 0xFFFF +#endif + +#define MG11_8_18PL 0xFF7F +#define MG11_8 (MG11_8_11PL & MG11_8_12PL & MG11_8_13PL & MG11_8_14PL & \ + MG11_8_15PL & MG11_8_16PL & MG11_8_17PL & MG11_8_18PL & \ + MG11_8_19PL & MG11_8_110PL & MG11_8_111PL & MG11_8_112PL & \ + MG11_8_113PL & MG11_8_114PL & MG11_8_115PL & MG11_8_116PL) +// End of MG11_8: +// Beginning of MG119: +#if (G11_1PL >= G11_9PL) || (G11_1PL == 0) +#define MG11_9_11PL ~(1 << 0) +#else +#define MG11_9_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_9PL) || (G11_2PL == 0) +#define MG11_9_12PL ~(1 << 1) +#else +#define MG11_9_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_9PL) || (G11_3PL == 0) +#define MG11_9_13PL ~(1 << 2) +#else +#define MG11_9_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_9PL) || (G11_4PL == 0) +#define MG11_9_14PL ~(1 << 3) +#else +#define MG11_9_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_9PL) || (G11_5PL == 0) +#define MG11_9_15PL ~(1 << 4) +#else +#define MG11_9_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_9PL) || (G11_6PL == 0) +#define MG11_9_16PL ~(1 << 5) +#else +#define MG11_9_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_9PL) || (G11_7PL == 0) +#define MG11_9_17PL ~(1 << 6) +#else +#define MG11_9_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_9PL) || (G11_8PL == 0) +#define MG11_9_18PL ~(1 << 7) +#else +#define MG11_9_18PL 0xFFFF +#endif + +#if (G11_10PL >= G11_9PL) || (G11_10PL == 0) +#define MG11_9_110PL ~(1 << 9) +#else +#define MG11_9_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_9PL) || (G11_11PL == 0) +#define MG11_9_111PL ~(1 << 10) +#else +#define MG11_9_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_9PL) || (G11_12PL == 0) +#define MG11_9_112PL ~(1 << 11) +#else +#define MG11_9_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_9PL) || (G11_13PL == 0) +#define MG11_9_113PL ~(1 << 12) +#else +#define MG11_9_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_9PL) || (G11_14PL == 0) +#define MG11_9_114PL ~(1 << 13) +#else +#define MG11_9_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_9PL) || (G11_15PL == 0) +#define MG11_9_115PL ~(1 << 14) +#else +#define MG11_9_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_9PL) || (G11_16PL == 0) +#define MG11_9_116PL ~(1 << 15) +#else +#define MG11_9_116PL 0xFFFF +#endif + +#define MG11_9_19PL 0xFEFF +#define MG11_9 (MG11_9_11PL & MG11_9_12PL & MG11_9_13PL & MG11_9_14PL & \ + MG11_9_15PL & MG11_9_16PL & MG11_9_17PL & MG11_9_18PL & \ + MG11_9_19PL & MG11_9_110PL & MG11_9_111PL & MG11_9_112PL & \ + MG11_9_113PL & MG11_9_114PL & MG11_9_115PL & MG11_9_116PL) +// End of MG11_9: +// Beginning of MG1110: +#if (G11_1PL >= G11_10PL) || (G11_1PL == 0) +#define MG11_10_11PL ~(1 << 0) +#else +#define MG11_10_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_10PL) || (G11_2PL == 0) +#define MG11_10_12PL ~(1 << 1) +#else +#define MG11_10_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_10PL) || (G11_3PL == 0) +#define MG11_10_13PL ~(1 << 2) +#else +#define MG11_10_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_10PL) || (G11_4PL == 0) +#define MG11_10_14PL ~(1 << 3) +#else +#define MG11_10_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_10PL) || (G11_5PL == 0) +#define MG11_10_15PL ~(1 << 4) +#else +#define MG11_10_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_10PL) || (G11_6PL == 0) +#define MG11_10_16PL ~(1 << 5) +#else +#define MG11_10_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_10PL) || (G11_7PL == 0) +#define MG11_10_17PL ~(1 << 6) +#else +#define MG11_10_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_10PL) || (G11_8PL == 0) +#define MG11_10_18PL ~(1 << 7) +#else +#define MG11_10_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_10PL) || (G11_9PL == 0) +#define MG11_10_19PL ~(1 << 8) +#else +#define MG11_10_19PL 0xFFFF +#endif + +#if (G11_11PL >= G11_10PL) || (G11_11PL == 0) +#define MG11_10_111PL ~(1 << 10) +#else +#define MG11_10_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_10PL) || (G11_12PL == 0) +#define MG11_10_112PL ~(1 << 11) +#else +#define MG11_10_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_10PL) || (G11_13PL == 0) +#define MG11_10_113PL ~(1 << 12) +#else +#define MG11_10_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_10PL) || (G11_14PL == 0) +#define MG11_10_114PL ~(1 << 13) +#else +#define MG11_10_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_10PL) || (G11_15PL == 0) +#define MG11_10_115PL ~(1 << 14) +#else +#define MG11_10_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_10PL) || (G11_16PL == 0) +#define MG11_10_116PL ~(1 << 15) +#else +#define MG11_10_116PL 0xFFFF +#endif + +#define MG11_10_110PL 0xFDFF +#define MG11_10 (MG11_10_11PL & MG11_10_12PL & MG11_10_13PL & MG11_10_14PL & \ + MG11_10_15PL & MG11_10_16PL & MG11_10_17PL & MG11_10_18PL & \ + MG11_10_19PL & MG11_10_110PL & MG11_10_111PL & MG11_10_112PL & \ + MG11_10_113PL & MG11_10_114PL & MG11_10_115PL & MG11_10_116PL) +// End of MG11_10: +// Beginning of MG1111: +#if (G11_1PL >= G11_11PL) || (G11_1PL == 0) +#define MG11_11_11PL ~(1 << 0) +#else +#define MG11_11_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_11PL) || (G11_2PL == 0) +#define MG11_11_12PL ~(1 << 1) +#else +#define MG11_11_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_11PL) || (G11_3PL == 0) +#define MG11_11_13PL ~(1 << 2) +#else +#define MG11_11_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_11PL) || (G11_4PL == 0) +#define MG11_11_14PL ~(1 << 3) +#else +#define MG11_11_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_11PL) || (G11_5PL == 0) +#define MG11_11_15PL ~(1 << 4) +#else +#define MG11_11_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_11PL) || (G11_6PL == 0) +#define MG11_11_16PL ~(1 << 5) +#else +#define MG11_11_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_11PL) || (G11_7PL == 0) +#define MG11_11_17PL ~(1 << 6) +#else +#define MG11_11_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_11PL) || (G11_8PL == 0) +#define MG11_11_18PL ~(1 << 7) +#else +#define MG11_11_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_11PL) || (G11_9PL == 0) +#define MG11_11_19PL ~(1 << 8) +#else +#define MG11_11_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_11PL) || (G11_10PL == 0) +#define MG11_11_110PL ~(1 << 9) +#else +#define MG11_11_110PL 0xFFFF +#endif + +#if (G11_12PL >= G11_11PL) || (G11_12PL == 0) +#define MG11_11_112PL ~(1 << 11) +#else +#define MG11_11_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_11PL) || (G11_13PL == 0) +#define MG11_11_113PL ~(1 << 12) +#else +#define MG11_11_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_11PL) || (G11_14PL == 0) +#define MG11_11_114PL ~(1 << 13) +#else +#define MG11_11_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_11PL) || (G11_15PL == 0) +#define MG11_11_115PL ~(1 << 14) +#else +#define MG11_11_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_11PL) || (G11_16PL == 0) +#define MG11_11_116PL ~(1 << 15) +#else +#define MG11_11_116PL 0xFFFF +#endif + +#define MG11_11_111PL 0xFBFF +#define MG11_11 (MG11_11_11PL & MG11_11_12PL & MG11_11_13PL & MG11_11_14PL & \ + MG11_11_15PL & MG11_11_16PL & MG11_11_17PL & MG11_11_18PL & \ + MG11_11_19PL & MG11_11_110PL & MG11_11_111PL & MG11_11_112PL & \ + MG11_11_113PL & MG11_11_114PL & MG11_11_115PL & MG11_11_116PL) +// End of MG11_11: +// Beginning of MG1112: +#if (G11_1PL >= G11_12PL) || (G11_1PL == 0) +#define MG11_12_11PL ~(1 << 0) +#else +#define MG11_12_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_12PL) || (G11_2PL == 0) +#define MG11_12_12PL ~(1 << 1) +#else +#define MG11_12_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_12PL) || (G11_3PL == 0) +#define MG11_12_13PL ~(1 << 2) +#else +#define MG11_12_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_12PL) || (G11_4PL == 0) +#define MG11_12_14PL ~(1 << 3) +#else +#define MG11_12_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_12PL) || (G11_5PL == 0) +#define MG11_12_15PL ~(1 << 4) +#else +#define MG11_12_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_12PL) || (G11_6PL == 0) +#define MG11_12_16PL ~(1 << 5) +#else +#define MG11_12_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_12PL) || (G11_7PL == 0) +#define MG11_12_17PL ~(1 << 6) +#else +#define MG11_12_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_12PL) || (G11_8PL == 0) +#define MG11_12_18PL ~(1 << 7) +#else +#define MG11_12_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_12PL) || (G11_9PL == 0) +#define MG11_12_19PL ~(1 << 8) +#else +#define MG11_12_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_12PL) || (G11_10PL == 0) +#define MG11_12_110PL ~(1 << 9) +#else +#define MG11_12_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_12PL) || (G11_11PL == 0) +#define MG11_12_111PL ~(1 << 10) +#else +#define MG11_12_111PL 0xFFFF +#endif + +#if (G11_13PL >= G11_12PL) || (G11_13PL == 0) +#define MG11_12_113PL ~(1 << 12) +#else +#define MG11_12_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_12PL) || (G11_14PL == 0) +#define MG11_12_114PL ~(1 << 13) +#else +#define MG11_12_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_12PL) || (G11_15PL == 0) +#define MG11_12_115PL ~(1 << 14) +#else +#define MG11_12_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_12PL) || (G11_16PL == 0) +#define MG11_12_116PL ~(1 << 15) +#else +#define MG11_12_116PL 0xFFFF +#endif + +#define MG11_12_112PL 0xF7FF +#define MG11_12 (MG11_12_11PL & MG11_12_12PL & MG11_12_13PL & MG11_12_14PL & \ + MG11_12_15PL & MG11_12_16PL & MG11_12_17PL & MG11_12_18PL & \ + MG11_12_19PL & MG11_12_110PL & MG11_12_111PL & MG11_12_112PL & \ + MG11_12_113PL & MG11_12_114PL & MG11_12_115PL & MG11_12_116PL) +// End of MG11_12: +// Beginning of MG1113: +#if (G11_1PL >= G11_13PL) || (G11_1PL == 0) +#define MG11_13_11PL ~(1 << 0) +#else +#define MG11_13_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_13PL) || (G11_2PL == 0) +#define MG11_13_12PL ~(1 << 1) +#else +#define MG11_13_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_13PL) || (G11_3PL == 0) +#define MG11_13_13PL ~(1 << 2) +#else +#define MG11_13_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_13PL) || (G11_4PL == 0) +#define MG11_13_14PL ~(1 << 3) +#else +#define MG11_13_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_13PL) || (G11_5PL == 0) +#define MG11_13_15PL ~(1 << 4) +#else +#define MG11_13_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_13PL) || (G11_6PL == 0) +#define MG11_13_16PL ~(1 << 5) +#else +#define MG11_13_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_13PL) || (G11_7PL == 0) +#define MG11_13_17PL ~(1 << 6) +#else +#define MG11_13_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_13PL) || (G11_8PL == 0) +#define MG11_13_18PL ~(1 << 7) +#else +#define MG11_13_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_13PL) || (G11_9PL == 0) +#define MG11_13_19PL ~(1 << 8) +#else +#define MG11_13_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_13PL) || (G11_10PL == 0) +#define MG11_13_110PL ~(1 << 9) +#else +#define MG11_13_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_13PL) || (G11_11PL == 0) +#define MG11_13_111PL ~(1 << 10) +#else +#define MG11_13_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_13PL) || (G11_12PL == 0) +#define MG11_13_112PL ~(1 << 11) +#else +#define MG11_13_112PL 0xFFFF +#endif + +#if (G11_14PL >= G11_13PL) || (G11_14PL == 0) +#define MG11_13_114PL ~(1 << 13) +#else +#define MG11_13_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_13PL) || (G11_15PL == 0) +#define MG11_13_115PL ~(1 << 14) +#else +#define MG11_13_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_13PL) || (G11_16PL == 0) +#define MG11_13_116PL ~(1 << 15) +#else +#define MG11_13_116PL 0xFFFF +#endif + +#define MG11_13_113PL 0xEFFF +#define MG11_13 (MG11_13_11PL & MG11_13_12PL & MG11_13_13PL & MG11_13_14PL & \ + MG11_13_15PL & MG11_13_16PL & MG11_13_17PL & MG11_13_18PL & \ + MG11_13_19PL & MG11_13_110PL & MG11_13_111PL & MG11_13_112PL & \ + MG11_13_113PL & MG11_13_114PL & MG11_13_115PL & MG11_13_116PL) +// End of MG11_13: +// Beginning of MG1114: +#if (G11_1PL >= G11_14PL) || (G11_1PL == 0) +#define MG11_14_11PL ~(1 << 0) +#else +#define MG11_14_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_14PL) || (G11_2PL == 0) +#define MG11_14_12PL ~(1 << 1) +#else +#define MG11_14_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_14PL) || (G11_3PL == 0) +#define MG11_14_13PL ~(1 << 2) +#else +#define MG11_14_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_14PL) || (G11_4PL == 0) +#define MG11_14_14PL ~(1 << 3) +#else +#define MG11_14_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_14PL) || (G11_5PL == 0) +#define MG11_14_15PL ~(1 << 4) +#else +#define MG11_14_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_14PL) || (G11_6PL == 0) +#define MG11_14_16PL ~(1 << 5) +#else +#define MG11_14_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_14PL) || (G11_7PL == 0) +#define MG11_14_17PL ~(1 << 6) +#else +#define MG11_14_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_14PL) || (G11_8PL == 0) +#define MG11_14_18PL ~(1 << 7) +#else +#define MG11_14_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_14PL) || (G11_9PL == 0) +#define MG11_14_19PL ~(1 << 8) +#else +#define MG11_14_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_14PL) || (G11_10PL == 0) +#define MG11_14_110PL ~(1 << 9) +#else +#define MG11_14_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_14PL) || (G11_11PL == 0) +#define MG11_14_111PL ~(1 << 10) +#else +#define MG11_14_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_14PL) || (G11_12PL == 0) +#define MG11_14_112PL ~(1 << 11) +#else +#define MG11_14_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_14PL) || (G11_13PL == 0) +#define MG11_14_113PL ~(1 << 12) +#else +#define MG11_14_113PL 0xFFFF +#endif + +#if (G11_15PL >= G11_14PL) || (G11_15PL == 0) +#define MG11_14_115PL ~(1 << 14) +#else +#define MG11_14_115PL 0xFFFF +#endif + +#if (G11_16PL >= G11_14PL) || (G11_16PL == 0) +#define MG11_14_116PL ~(1 << 15) +#else +#define MG11_14_116PL 0xFFFF +#endif + +#define MG11_14_114PL 0xDFFF +#define MG11_14 (MG11_14_11PL & MG11_14_12PL & MG11_14_13PL & MG11_14_14PL & \ + MG11_14_15PL & MG11_14_16PL & MG11_14_17PL & MG11_14_18PL & \ + MG11_14_19PL & MG11_14_110PL & MG11_14_111PL & MG11_14_112PL & \ + MG11_14_113PL & MG11_14_114PL & MG11_14_115PL & MG11_14_116PL) +// End of MG11_14: +// Beginning of MG1115: +#if (G11_1PL >= G11_15PL) || (G11_1PL == 0) +#define MG11_15_11PL ~(1 << 0) +#else +#define MG11_15_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_15PL) || (G11_2PL == 0) +#define MG11_15_12PL ~(1 << 1) +#else +#define MG11_15_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_15PL) || (G11_3PL == 0) +#define MG11_15_13PL ~(1 << 2) +#else +#define MG11_15_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_15PL) || (G11_4PL == 0) +#define MG11_15_14PL ~(1 << 3) +#else +#define MG11_15_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_15PL) || (G11_5PL == 0) +#define MG11_15_15PL ~(1 << 4) +#else +#define MG11_15_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_15PL) || (G11_6PL == 0) +#define MG11_15_16PL ~(1 << 5) +#else +#define MG11_15_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_15PL) || (G11_7PL == 0) +#define MG11_15_17PL ~(1 << 6) +#else +#define MG11_15_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_15PL) || (G11_8PL == 0) +#define MG11_15_18PL ~(1 << 7) +#else +#define MG11_15_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_15PL) || (G11_9PL == 0) +#define MG11_15_19PL ~(1 << 8) +#else +#define MG11_15_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_15PL) || (G11_10PL == 0) +#define MG11_15_110PL ~(1 << 9) +#else +#define MG11_15_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_15PL) || (G11_11PL == 0) +#define MG11_15_111PL ~(1 << 10) +#else +#define MG11_15_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_15PL) || (G11_12PL == 0) +#define MG11_15_112PL ~(1 << 11) +#else +#define MG11_15_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_15PL) || (G11_13PL == 0) +#define MG11_15_113PL ~(1 << 12) +#else +#define MG11_15_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_15PL) || (G11_14PL == 0) +#define MG11_15_114PL ~(1 << 13) +#else +#define MG11_15_114PL 0xFFFF +#endif + +#if (G11_16PL >= G11_15PL) || (G11_16PL == 0) +#define MG11_15_116PL ~(1 << 15) +#else +#define MG11_15_116PL 0xFFFF +#endif + +#define MG11_15_115PL 0xBFFF +#define MG11_15 (MG11_15_11PL & MG11_15_12PL & MG11_15_13PL & MG11_15_14PL & \ + MG11_15_15PL & MG11_15_16PL & MG11_15_17PL & MG11_15_18PL & \ + MG11_15_19PL & MG11_15_110PL & MG11_15_111PL & MG11_15_112PL & \ + MG11_15_113PL & MG11_15_114PL & MG11_15_115PL & MG11_15_116PL) +// End of MG11_15: +// Beginning of MG1116: +#if (G11_1PL >= G11_16PL) || (G11_1PL == 0) +#define MG11_16_11PL ~(1 << 0) +#else +#define MG11_16_11PL 0xFFFF +#endif + +#if (G11_2PL >= G11_16PL) || (G11_2PL == 0) +#define MG11_16_12PL ~(1 << 1) +#else +#define MG11_16_12PL 0xFFFF +#endif + +#if (G11_3PL >= G11_16PL) || (G11_3PL == 0) +#define MG11_16_13PL ~(1 << 2) +#else +#define MG11_16_13PL 0xFFFF +#endif + +#if (G11_4PL >= G11_16PL) || (G11_4PL == 0) +#define MG11_16_14PL ~(1 << 3) +#else +#define MG11_16_14PL 0xFFFF +#endif + +#if (G11_5PL >= G11_16PL) || (G11_5PL == 0) +#define MG11_16_15PL ~(1 << 4) +#else +#define MG11_16_15PL 0xFFFF +#endif + +#if (G11_6PL >= G11_16PL) || (G11_6PL == 0) +#define MG11_16_16PL ~(1 << 5) +#else +#define MG11_16_16PL 0xFFFF +#endif + +#if (G11_7PL >= G11_16PL) || (G11_7PL == 0) +#define MG11_16_17PL ~(1 << 6) +#else +#define MG11_16_17PL 0xFFFF +#endif + +#if (G11_8PL >= G11_16PL) || (G11_8PL == 0) +#define MG11_16_18PL ~(1 << 7) +#else +#define MG11_16_18PL 0xFFFF +#endif + +#if (G11_9PL >= G11_16PL) || (G11_9PL == 0) +#define MG11_16_19PL ~(1 << 8) +#else +#define MG11_16_19PL 0xFFFF +#endif + +#if (G11_10PL >= G11_16PL) || (G11_10PL == 0) +#define MG11_16_110PL ~(1 << 9) +#else +#define MG11_16_110PL 0xFFFF +#endif + +#if (G11_11PL >= G11_16PL) || (G11_11PL == 0) +#define MG11_16_111PL ~(1 << 10) +#else +#define MG11_16_111PL 0xFFFF +#endif + +#if (G11_12PL >= G11_16PL) || (G11_12PL == 0) +#define MG11_16_112PL ~(1 << 11) +#else +#define MG11_16_112PL 0xFFFF +#endif + +#if (G11_13PL >= G11_16PL) || (G11_13PL == 0) +#define MG11_16_113PL ~(1 << 12) +#else +#define MG11_16_113PL 0xFFFF +#endif + +#if (G11_14PL >= G11_16PL) || (G11_14PL == 0) +#define MG11_16_114PL ~(1 << 13) +#else +#define MG11_16_114PL 0xFFFF +#endif + +#if (G11_15PL >= G11_16PL) || (G11_15PL == 0) +#define MG11_16_115PL ~(1 << 14) +#else +#define MG11_16_115PL 0xFFFF +#endif + +#define MG11_16_116PL 0x7FFF +#define MG11_16 (MG11_16_11PL & MG11_16_12PL & MG11_16_13PL & MG11_16_14PL & \ + MG11_16_15PL & MG11_16_16PL & MG11_16_17PL & MG11_16_18PL & \ + MG11_16_19PL & MG11_16_110PL & MG11_16_111PL & MG11_16_112PL & \ + MG11_16_113PL & MG11_16_114PL & MG11_16_115PL & MG11_16_116PL) +// End of MG11_16: + + +// +// Automatically generate PIEIER12 interrupt masks MG121 to MG1216: +// + +// Beginning of MG121: +#if (G12_2PL >= G12_1PL) || (G12_2PL == 0) +#define MG12_1_12PL ~(1 << 1) +#else +#define MG12_1_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_1PL) || (G12_3PL == 0) +#define MG12_1_13PL ~(1 << 2) +#else +#define MG12_1_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_1PL) || (G12_4PL == 0) +#define MG12_1_14PL ~(1 << 3) +#else +#define MG12_1_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_1PL) || (G12_5PL == 0) +#define MG12_1_15PL ~(1 << 4) +#else +#define MG12_1_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_1PL) || (G12_6PL == 0) +#define MG12_1_16PL ~(1 << 5) +#else +#define MG12_1_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_1PL) || (G12_7PL == 0) +#define MG12_1_17PL ~(1 << 6) +#else +#define MG12_1_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_1PL) || (G12_8PL == 0) +#define MG12_1_18PL ~(1 << 7) +#else +#define MG12_1_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_1PL) || (G12_9PL == 0) +#define MG12_1_19PL ~(1 << 8) +#else +#define MG12_1_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_1PL) || (G12_10PL == 0) +#define MG12_1_110PL ~(1 << 9) +#else +#define MG12_1_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_1PL) || (G12_11PL == 0) +#define MG12_1_111PL ~(1 << 10) +#else +#define MG12_1_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_1PL) || (G12_12PL == 0) +#define MG12_1_112PL ~(1 << 11) +#else +#define MG12_1_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_1PL) || (G12_13PL == 0) +#define MG12_1_113PL ~(1 << 12) +#else +#define MG12_1_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_1PL) || (G12_14PL == 0) +#define MG12_1_114PL ~(1 << 13) +#else +#define MG12_1_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_1PL) || (G12_15PL == 0) +#define MG12_1_115PL ~(1 << 14) +#else +#define MG12_1_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_1PL) || (G12_16PL == 0) +#define MG12_1_116PL ~(1 << 15) +#else +#define MG12_1_116PL 0xFFFF +#endif + +#define MG12_1_11PL 0xFFFE +#define MG12_1 (MG12_1_11PL & MG12_1_12PL & MG12_1_13PL & MG12_1_14PL & \ + MG12_1_15PL & MG12_1_16PL & MG12_1_17PL & MG12_1_18PL & \ + MG12_1_19PL & MG12_1_110PL & MG12_1_111PL & MG12_1_112PL & \ + MG12_1_113PL & MG12_1_114PL & MG12_1_115PL & MG12_1_116PL) +// End of MG12_1: +// Beginning of MG122: +#if (G12_1PL >= G12_2PL) || (G12_1PL == 0) +#define MG12_2_11PL ~(1 << 0) +#else +#define MG12_2_11PL 0xFFFF +#endif + +#if (G12_3PL >= G12_2PL) || (G12_3PL == 0) +#define MG12_2_13PL ~(1 << 2) +#else +#define MG12_2_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_2PL) || (G12_4PL == 0) +#define MG12_2_14PL ~(1 << 3) +#else +#define MG12_2_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_2PL) || (G12_5PL == 0) +#define MG12_2_15PL ~(1 << 4) +#else +#define MG12_2_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_2PL) || (G12_6PL == 0) +#define MG12_2_16PL ~(1 << 5) +#else +#define MG12_2_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_2PL) || (G12_7PL == 0) +#define MG12_2_17PL ~(1 << 6) +#else +#define MG12_2_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_2PL) || (G12_8PL == 0) +#define MG12_2_18PL ~(1 << 7) +#else +#define MG12_2_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_2PL) || (G12_9PL == 0) +#define MG12_2_19PL ~(1 << 8) +#else +#define MG12_2_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_2PL) || (G12_10PL == 0) +#define MG12_2_110PL ~(1 << 9) +#else +#define MG12_2_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_2PL) || (G12_11PL == 0) +#define MG12_2_111PL ~(1 << 10) +#else +#define MG12_2_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_2PL) || (G12_12PL == 0) +#define MG12_2_112PL ~(1 << 11) +#else +#define MG12_2_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_2PL) || (G12_13PL == 0) +#define MG12_2_113PL ~(1 << 12) +#else +#define MG12_2_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_2PL) || (G12_14PL == 0) +#define MG12_2_114PL ~(1 << 13) +#else +#define MG12_2_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_2PL) || (G12_15PL == 0) +#define MG12_2_115PL ~(1 << 14) +#else +#define MG12_2_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_2PL) || (G12_16PL == 0) +#define MG12_2_116PL ~(1 << 15) +#else +#define MG12_2_116PL 0xFFFF +#endif + +#define MG12_2_12PL 0xFFFD +#define MG12_2 (MG12_2_11PL & MG12_2_12PL & MG12_2_13PL & MG12_2_14PL & \ + MG12_2_15PL & MG12_2_16PL & MG12_2_17PL & MG12_2_18PL & \ + MG12_2_19PL & MG12_2_110PL & MG12_2_111PL & MG12_2_112PL & \ + MG12_2_113PL & MG12_2_114PL & MG12_2_115PL & MG12_2_116PL) +// End of MG12_2: +// Beginning of MG123: +#if (G12_1PL >= G12_3PL) || (G12_1PL == 0) +#define MG12_3_11PL ~(1 << 0) +#else +#define MG12_3_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_3PL) || (G12_2PL == 0) +#define MG12_3_12PL ~(1 << 1) +#else +#define MG12_3_12PL 0xFFFF +#endif + +#if (G12_4PL >= G12_3PL) || (G12_4PL == 0) +#define MG12_3_14PL ~(1 << 3) +#else +#define MG12_3_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_3PL) || (G12_5PL == 0) +#define MG12_3_15PL ~(1 << 4) +#else +#define MG12_3_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_3PL) || (G12_6PL == 0) +#define MG12_3_16PL ~(1 << 5) +#else +#define MG12_3_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_3PL) || (G12_7PL == 0) +#define MG12_3_17PL ~(1 << 6) +#else +#define MG12_3_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_3PL) || (G12_8PL == 0) +#define MG12_3_18PL ~(1 << 7) +#else +#define MG12_3_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_3PL) || (G12_9PL == 0) +#define MG12_3_19PL ~(1 << 8) +#else +#define MG12_3_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_3PL) || (G12_10PL == 0) +#define MG12_3_110PL ~(1 << 9) +#else +#define MG12_3_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_3PL) || (G12_11PL == 0) +#define MG12_3_111PL ~(1 << 10) +#else +#define MG12_3_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_3PL) || (G12_12PL == 0) +#define MG12_3_112PL ~(1 << 11) +#else +#define MG12_3_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_3PL) || (G12_13PL == 0) +#define MG12_3_113PL ~(1 << 12) +#else +#define MG12_3_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_3PL) || (G12_14PL == 0) +#define MG12_3_114PL ~(1 << 13) +#else +#define MG12_3_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_3PL) || (G12_15PL == 0) +#define MG12_3_115PL ~(1 << 14) +#else +#define MG12_3_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_3PL) || (G12_16PL == 0) +#define MG12_3_116PL ~(1 << 15) +#else +#define MG12_3_116PL 0xFFFF +#endif + +#define MG12_3_13PL 0xFFFB +#define MG12_3 (MG12_3_11PL & MG12_3_12PL & MG12_3_13PL & MG12_3_14PL & \ + MG12_3_15PL & MG12_3_16PL & MG12_3_17PL & MG12_3_18PL & \ + MG12_3_19PL & MG12_3_110PL & MG12_3_111PL & MG12_3_112PL & \ + MG12_3_113PL & MG12_3_114PL & MG12_3_115PL & MG12_3_116PL) +// End of MG12_3: +// Beginning of MG124: +#if (G12_1PL >= G12_4PL) || (G12_1PL == 0) +#define MG12_4_11PL ~(1 << 0) +#else +#define MG12_4_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_4PL) || (G12_2PL == 0) +#define MG12_4_12PL ~(1 << 1) +#else +#define MG12_4_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_4PL) || (G12_3PL == 0) +#define MG12_4_13PL ~(1 << 2) +#else +#define MG12_4_13PL 0xFFFF +#endif + +#if (G12_5PL >= G12_4PL) || (G12_5PL == 0) +#define MG12_4_15PL ~(1 << 4) +#else +#define MG12_4_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_4PL) || (G12_6PL == 0) +#define MG12_4_16PL ~(1 << 5) +#else +#define MG12_4_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_4PL) || (G12_7PL == 0) +#define MG12_4_17PL ~(1 << 6) +#else +#define MG12_4_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_4PL) || (G12_8PL == 0) +#define MG12_4_18PL ~(1 << 7) +#else +#define MG12_4_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_4PL) || (G12_9PL == 0) +#define MG12_4_19PL ~(1 << 8) +#else +#define MG12_4_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_4PL) || (G12_10PL == 0) +#define MG12_4_110PL ~(1 << 9) +#else +#define MG12_4_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_4PL) || (G12_11PL == 0) +#define MG12_4_111PL ~(1 << 10) +#else +#define MG12_4_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_4PL) || (G12_12PL == 0) +#define MG12_4_112PL ~(1 << 11) +#else +#define MG12_4_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_4PL) || (G12_13PL == 0) +#define MG12_4_113PL ~(1 << 12) +#else +#define MG12_4_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_4PL) || (G12_14PL == 0) +#define MG12_4_114PL ~(1 << 13) +#else +#define MG12_4_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_4PL) || (G12_15PL == 0) +#define MG12_4_115PL ~(1 << 14) +#else +#define MG12_4_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_4PL) || (G12_16PL == 0) +#define MG12_4_116PL ~(1 << 15) +#else +#define MG12_4_116PL 0xFFFF +#endif + +#define MG12_4_14PL 0xFFF7 +#define MG12_4 (MG12_4_11PL & MG12_4_12PL & MG12_4_13PL & MG12_4_14PL & \ + MG12_4_15PL & MG12_4_16PL & MG12_4_17PL & MG12_4_18PL & \ + MG12_4_19PL & MG12_4_110PL & MG12_4_111PL & MG12_4_112PL & \ + MG12_4_113PL & MG12_4_114PL & MG12_4_115PL & MG12_4_116PL) +// End of MG12_4: +// Beginning of MG125: +#if (G12_1PL >= G12_5PL) || (G12_1PL == 0) +#define MG12_5_11PL ~(1 << 0) +#else +#define MG12_5_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_5PL) || (G12_2PL == 0) +#define MG12_5_12PL ~(1 << 1) +#else +#define MG12_5_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_5PL) || (G12_3PL == 0) +#define MG12_5_13PL ~(1 << 2) +#else +#define MG12_5_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_5PL) || (G12_4PL == 0) +#define MG12_5_14PL ~(1 << 3) +#else +#define MG12_5_14PL 0xFFFF +#endif + +#if (G12_6PL >= G12_5PL) || (G12_6PL == 0) +#define MG12_5_16PL ~(1 << 5) +#else +#define MG12_5_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_5PL) || (G12_7PL == 0) +#define MG12_5_17PL ~(1 << 6) +#else +#define MG12_5_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_5PL) || (G12_8PL == 0) +#define MG12_5_18PL ~(1 << 7) +#else +#define MG12_5_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_5PL) || (G12_9PL == 0) +#define MG12_5_19PL ~(1 << 8) +#else +#define MG12_5_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_5PL) || (G12_10PL == 0) +#define MG12_5_110PL ~(1 << 9) +#else +#define MG12_5_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_5PL) || (G12_11PL == 0) +#define MG12_5_111PL ~(1 << 10) +#else +#define MG12_5_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_5PL) || (G12_12PL == 0) +#define MG12_5_112PL ~(1 << 11) +#else +#define MG12_5_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_5PL) || (G12_13PL == 0) +#define MG12_5_113PL ~(1 << 12) +#else +#define MG12_5_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_5PL) || (G12_14PL == 0) +#define MG12_5_114PL ~(1 << 13) +#else +#define MG12_5_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_5PL) || (G12_15PL == 0) +#define MG12_5_115PL ~(1 << 14) +#else +#define MG12_5_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_5PL) || (G12_16PL == 0) +#define MG12_5_116PL ~(1 << 15) +#else +#define MG12_5_116PL 0xFFFF +#endif + +#define MG12_5_15PL 0xFFEF +#define MG12_5 (MG12_5_11PL & MG12_5_12PL & MG12_5_13PL & MG12_5_14PL & \ + MG12_5_15PL & MG12_5_16PL & MG12_5_17PL & MG12_5_18PL & \ + MG12_5_19PL & MG12_5_110PL & MG12_5_111PL & MG12_5_112PL & \ + MG12_5_113PL & MG12_5_114PL & MG12_5_115PL & MG12_5_116PL) +// End of MG12_5: +// Beginning of MG126: +#if (G12_1PL >= G12_6PL) || (G12_1PL == 0) +#define MG12_6_11PL ~(1 << 0) +#else +#define MG12_6_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_6PL) || (G12_2PL == 0) +#define MG12_6_12PL ~(1 << 1) +#else +#define MG12_6_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_6PL) || (G12_3PL == 0) +#define MG12_6_13PL ~(1 << 2) +#else +#define MG12_6_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_6PL) || (G12_4PL == 0) +#define MG12_6_14PL ~(1 << 3) +#else +#define MG12_6_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_6PL) || (G12_5PL == 0) +#define MG12_6_15PL ~(1 << 4) +#else +#define MG12_6_15PL 0xFFFF +#endif + +#if (G12_7PL >= G12_6PL) || (G12_7PL == 0) +#define MG12_6_17PL ~(1 << 6) +#else +#define MG12_6_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_6PL) || (G12_8PL == 0) +#define MG12_6_18PL ~(1 << 7) +#else +#define MG12_6_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_6PL) || (G12_9PL == 0) +#define MG12_6_19PL ~(1 << 8) +#else +#define MG12_6_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_6PL) || (G12_10PL == 0) +#define MG12_6_110PL ~(1 << 9) +#else +#define MG12_6_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_6PL) || (G12_11PL == 0) +#define MG12_6_111PL ~(1 << 10) +#else +#define MG12_6_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_6PL) || (G12_12PL == 0) +#define MG12_6_112PL ~(1 << 11) +#else +#define MG12_6_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_6PL) || (G12_13PL == 0) +#define MG12_6_113PL ~(1 << 12) +#else +#define MG12_6_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_6PL) || (G12_14PL == 0) +#define MG12_6_114PL ~(1 << 13) +#else +#define MG12_6_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_6PL) || (G12_15PL == 0) +#define MG12_6_115PL ~(1 << 14) +#else +#define MG12_6_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_6PL) || (G12_16PL == 0) +#define MG12_6_116PL ~(1 << 15) +#else +#define MG12_6_116PL 0xFFFF +#endif + +#define MG12_6_16PL 0xFFDF +#define MG12_6 (MG12_6_11PL & MG12_6_12PL & MG12_6_13PL & MG12_6_14PL & \ + MG12_6_15PL & MG12_6_16PL & MG12_6_17PL & MG12_6_18PL & \ + MG12_6_19PL & MG12_6_110PL & MG12_6_111PL & MG12_6_112PL & \ + MG12_6_113PL & MG12_6_114PL & MG12_6_115PL & MG12_6_116PL) +// End of MG12_6: +// Beginning of MG127: +#if (G12_1PL >= G12_7PL) || (G12_1PL == 0) +#define MG12_7_11PL ~(1 << 0) +#else +#define MG12_7_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_7PL) || (G12_2PL == 0) +#define MG12_7_12PL ~(1 << 1) +#else +#define MG12_7_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_7PL) || (G12_3PL == 0) +#define MG12_7_13PL ~(1 << 2) +#else +#define MG12_7_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_7PL) || (G12_4PL == 0) +#define MG12_7_14PL ~(1 << 3) +#else +#define MG12_7_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_7PL) || (G12_5PL == 0) +#define MG12_7_15PL ~(1 << 4) +#else +#define MG12_7_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_7PL) || (G12_6PL == 0) +#define MG12_7_16PL ~(1 << 5) +#else +#define MG12_7_16PL 0xFFFF +#endif + +#if (G12_8PL >= G12_7PL) || (G12_8PL == 0) +#define MG12_7_18PL ~(1 << 7) +#else +#define MG12_7_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_7PL) || (G12_9PL == 0) +#define MG12_7_19PL ~(1 << 8) +#else +#define MG12_7_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_7PL) || (G12_10PL == 0) +#define MG12_7_110PL ~(1 << 9) +#else +#define MG12_7_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_7PL) || (G12_11PL == 0) +#define MG12_7_111PL ~(1 << 10) +#else +#define MG12_7_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_7PL) || (G12_12PL == 0) +#define MG12_7_112PL ~(1 << 11) +#else +#define MG12_7_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_7PL) || (G12_13PL == 0) +#define MG12_7_113PL ~(1 << 12) +#else +#define MG12_7_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_7PL) || (G12_14PL == 0) +#define MG12_7_114PL ~(1 << 13) +#else +#define MG12_7_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_7PL) || (G12_15PL == 0) +#define MG12_7_115PL ~(1 << 14) +#else +#define MG12_7_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_7PL) || (G12_16PL == 0) +#define MG12_7_116PL ~(1 << 15) +#else +#define MG12_7_116PL 0xFFFF +#endif + +#define MG12_7_17PL 0xFFBF +#define MG12_7 (MG12_7_11PL & MG12_7_12PL & MG12_7_13PL & MG12_7_14PL & \ + MG12_7_15PL & MG12_7_16PL & MG12_7_17PL & MG12_7_18PL & \ + MG12_7_19PL & MG12_7_110PL & MG12_7_111PL & MG12_7_112PL & \ + MG12_7_113PL & MG12_7_114PL & MG12_7_115PL & MG12_7_116PL) +// End of MG12_7: +// Beginning of MG128: +#if (G12_1PL >= G12_8PL) || (G12_1PL == 0) +#define MG12_8_11PL ~(1 << 0) +#else +#define MG12_8_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_8PL) || (G12_2PL == 0) +#define MG12_8_12PL ~(1 << 1) +#else +#define MG12_8_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_8PL) || (G12_3PL == 0) +#define MG12_8_13PL ~(1 << 2) +#else +#define MG12_8_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_8PL) || (G12_4PL == 0) +#define MG12_8_14PL ~(1 << 3) +#else +#define MG12_8_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_8PL) || (G12_5PL == 0) +#define MG12_8_15PL ~(1 << 4) +#else +#define MG12_8_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_8PL) || (G12_6PL == 0) +#define MG12_8_16PL ~(1 << 5) +#else +#define MG12_8_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_8PL) || (G12_7PL == 0) +#define MG12_8_17PL ~(1 << 6) +#else +#define MG12_8_17PL 0xFFFF +#endif + +#if (G12_9PL >= G12_8PL) || (G12_9PL == 0) +#define MG12_8_19PL ~(1 << 8) +#else +#define MG12_8_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_8PL) || (G12_10PL == 0) +#define MG12_8_110PL ~(1 << 9) +#else +#define MG12_8_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_8PL) || (G12_11PL == 0) +#define MG12_8_111PL ~(1 << 10) +#else +#define MG12_8_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_8PL) || (G12_12PL == 0) +#define MG12_8_112PL ~(1 << 11) +#else +#define MG12_8_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_8PL) || (G12_13PL == 0) +#define MG12_8_113PL ~(1 << 12) +#else +#define MG12_8_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_8PL) || (G12_14PL == 0) +#define MG12_8_114PL ~(1 << 13) +#else +#define MG12_8_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_8PL) || (G12_15PL == 0) +#define MG12_8_115PL ~(1 << 14) +#else +#define MG12_8_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_8PL) || (G12_16PL == 0) +#define MG12_8_116PL ~(1 << 15) +#else +#define MG12_8_116PL 0xFFFF +#endif + +#define MG12_8_18PL 0xFF7F +#define MG12_8 (MG12_8_11PL & MG12_8_12PL & MG12_8_13PL & MG12_8_14PL & \ + MG12_8_15PL & MG12_8_16PL & MG12_8_17PL & MG12_8_18PL & \ + MG12_8_19PL & MG12_8_110PL & MG12_8_111PL & MG12_8_112PL & \ + MG12_8_113PL & MG12_8_114PL & MG12_8_115PL & MG12_8_116PL) +// End of MG12_8: +// Beginning of MG129: +#if (G12_1PL >= G12_9PL) || (G12_1PL == 0) +#define MG12_9_11PL ~(1 << 0) +#else +#define MG12_9_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_9PL) || (G12_2PL == 0) +#define MG12_9_12PL ~(1 << 1) +#else +#define MG12_9_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_9PL) || (G12_3PL == 0) +#define MG12_9_13PL ~(1 << 2) +#else +#define MG12_9_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_9PL) || (G12_4PL == 0) +#define MG12_9_14PL ~(1 << 3) +#else +#define MG12_9_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_9PL) || (G12_5PL == 0) +#define MG12_9_15PL ~(1 << 4) +#else +#define MG12_9_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_9PL) || (G12_6PL == 0) +#define MG12_9_16PL ~(1 << 5) +#else +#define MG12_9_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_9PL) || (G12_7PL == 0) +#define MG12_9_17PL ~(1 << 6) +#else +#define MG12_9_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_9PL) || (G12_8PL == 0) +#define MG12_9_18PL ~(1 << 7) +#else +#define MG12_9_18PL 0xFFFF +#endif + +#if (G12_10PL >= G12_9PL) || (G12_10PL == 0) +#define MG12_9_110PL ~(1 << 9) +#else +#define MG12_9_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_9PL) || (G12_11PL == 0) +#define MG12_9_111PL ~(1 << 10) +#else +#define MG12_9_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_9PL) || (G12_12PL == 0) +#define MG12_9_112PL ~(1 << 11) +#else +#define MG12_9_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_9PL) || (G12_13PL == 0) +#define MG12_9_113PL ~(1 << 12) +#else +#define MG12_9_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_9PL) || (G12_14PL == 0) +#define MG12_9_114PL ~(1 << 13) +#else +#define MG12_9_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_9PL) || (G12_15PL == 0) +#define MG12_9_115PL ~(1 << 14) +#else +#define MG12_9_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_9PL) || (G12_16PL == 0) +#define MG12_9_116PL ~(1 << 15) +#else +#define MG12_9_116PL 0xFFFF +#endif + +#define MG12_9_19PL 0xFEFF +#define MG12_9 (MG12_9_11PL & MG12_9_12PL & MG12_9_13PL & MG12_9_14PL & \ + MG12_9_15PL & MG12_9_16PL & MG12_9_17PL & MG12_9_18PL & \ + MG12_9_19PL & MG12_9_110PL & MG12_9_111PL & MG12_9_112PL & \ + MG12_9_113PL & MG12_9_114PL & MG12_9_115PL & MG12_9_116PL) +// End of MG12_9: +// Beginning of MG1210: +#if (G12_1PL >= G12_10PL) || (G12_1PL == 0) +#define MG12_10_11PL ~(1 << 0) +#else +#define MG12_10_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_10PL) || (G12_2PL == 0) +#define MG12_10_12PL ~(1 << 1) +#else +#define MG12_10_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_10PL) || (G12_3PL == 0) +#define MG12_10_13PL ~(1 << 2) +#else +#define MG12_10_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_10PL) || (G12_4PL == 0) +#define MG12_10_14PL ~(1 << 3) +#else +#define MG12_10_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_10PL) || (G12_5PL == 0) +#define MG12_10_15PL ~(1 << 4) +#else +#define MG12_10_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_10PL) || (G12_6PL == 0) +#define MG12_10_16PL ~(1 << 5) +#else +#define MG12_10_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_10PL) || (G12_7PL == 0) +#define MG12_10_17PL ~(1 << 6) +#else +#define MG12_10_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_10PL) || (G12_8PL == 0) +#define MG12_10_18PL ~(1 << 7) +#else +#define MG12_10_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_10PL) || (G12_9PL == 0) +#define MG12_10_19PL ~(1 << 8) +#else +#define MG12_10_19PL 0xFFFF +#endif + +#if (G12_11PL >= G12_10PL) || (G12_11PL == 0) +#define MG12_10_111PL ~(1 << 10) +#else +#define MG12_10_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_10PL) || (G12_12PL == 0) +#define MG12_10_112PL ~(1 << 11) +#else +#define MG12_10_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_10PL) || (G12_13PL == 0) +#define MG12_10_113PL ~(1 << 12) +#else +#define MG12_10_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_10PL) || (G12_14PL == 0) +#define MG12_10_114PL ~(1 << 13) +#else +#define MG12_10_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_10PL) || (G12_15PL == 0) +#define MG12_10_115PL ~(1 << 14) +#else +#define MG12_10_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_10PL) || (G12_16PL == 0) +#define MG12_10_116PL ~(1 << 15) +#else +#define MG12_10_116PL 0xFFFF +#endif + +#define MG12_10_110PL 0xFDFF +#define MG12_10 (MG12_10_11PL & MG12_10_12PL & MG12_10_13PL & MG12_10_14PL & \ + MG12_10_15PL & MG12_10_16PL & MG12_10_17PL & MG12_10_18PL & \ + MG12_10_19PL & MG12_10_110PL & MG12_10_111PL & MG12_10_112PL & \ + MG12_10_113PL & MG12_10_114PL & MG12_10_115PL & MG12_10_116PL) +// End of MG12_10: +// Beginning of MG1211: +#if (G12_1PL >= G12_11PL) || (G12_1PL == 0) +#define MG12_11_11PL ~(1 << 0) +#else +#define MG12_11_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_11PL) || (G12_2PL == 0) +#define MG12_11_12PL ~(1 << 1) +#else +#define MG12_11_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_11PL) || (G12_3PL == 0) +#define MG12_11_13PL ~(1 << 2) +#else +#define MG12_11_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_11PL) || (G12_4PL == 0) +#define MG12_11_14PL ~(1 << 3) +#else +#define MG12_11_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_11PL) || (G12_5PL == 0) +#define MG12_11_15PL ~(1 << 4) +#else +#define MG12_11_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_11PL) || (G12_6PL == 0) +#define MG12_11_16PL ~(1 << 5) +#else +#define MG12_11_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_11PL) || (G12_7PL == 0) +#define MG12_11_17PL ~(1 << 6) +#else +#define MG12_11_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_11PL) || (G12_8PL == 0) +#define MG12_11_18PL ~(1 << 7) +#else +#define MG12_11_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_11PL) || (G12_9PL == 0) +#define MG12_11_19PL ~(1 << 8) +#else +#define MG12_11_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_11PL) || (G12_10PL == 0) +#define MG12_11_110PL ~(1 << 9) +#else +#define MG12_11_110PL 0xFFFF +#endif + +#if (G12_12PL >= G12_11PL) || (G12_12PL == 0) +#define MG12_11_112PL ~(1 << 11) +#else +#define MG12_11_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_11PL) || (G12_13PL == 0) +#define MG12_11_113PL ~(1 << 12) +#else +#define MG12_11_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_11PL) || (G12_14PL == 0) +#define MG12_11_114PL ~(1 << 13) +#else +#define MG12_11_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_11PL) || (G12_15PL == 0) +#define MG12_11_115PL ~(1 << 14) +#else +#define MG12_11_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_11PL) || (G12_16PL == 0) +#define MG12_11_116PL ~(1 << 15) +#else +#define MG12_11_116PL 0xFFFF +#endif + +#define MG12_11_111PL 0xFBFF +#define MG12_11 (MG12_11_11PL & MG12_11_12PL & MG12_11_13PL & MG12_11_14PL & \ + MG12_11_15PL & MG12_11_16PL & MG12_11_17PL & MG12_11_18PL & \ + MG12_11_19PL & MG12_11_110PL & MG12_11_111PL & MG12_11_112PL & \ + MG12_11_113PL & MG12_11_114PL & MG12_11_115PL & MG12_11_116PL) +// End of MG12_11: +// Beginning of MG1212: +#if (G12_1PL >= G12_12PL) || (G12_1PL == 0) +#define MG12_12_11PL ~(1 << 0) +#else +#define MG12_12_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_12PL) || (G12_2PL == 0) +#define MG12_12_12PL ~(1 << 1) +#else +#define MG12_12_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_12PL) || (G12_3PL == 0) +#define MG12_12_13PL ~(1 << 2) +#else +#define MG12_12_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_12PL) || (G12_4PL == 0) +#define MG12_12_14PL ~(1 << 3) +#else +#define MG12_12_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_12PL) || (G12_5PL == 0) +#define MG12_12_15PL ~(1 << 4) +#else +#define MG12_12_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_12PL) || (G12_6PL == 0) +#define MG12_12_16PL ~(1 << 5) +#else +#define MG12_12_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_12PL) || (G12_7PL == 0) +#define MG12_12_17PL ~(1 << 6) +#else +#define MG12_12_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_12PL) || (G12_8PL == 0) +#define MG12_12_18PL ~(1 << 7) +#else +#define MG12_12_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_12PL) || (G12_9PL == 0) +#define MG12_12_19PL ~(1 << 8) +#else +#define MG12_12_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_12PL) || (G12_10PL == 0) +#define MG12_12_110PL ~(1 << 9) +#else +#define MG12_12_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_12PL) || (G12_11PL == 0) +#define MG12_12_111PL ~(1 << 10) +#else +#define MG12_12_111PL 0xFFFF +#endif + +#if (G12_13PL >= G12_12PL) || (G12_13PL == 0) +#define MG12_12_113PL ~(1 << 12) +#else +#define MG12_12_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_12PL) || (G12_14PL == 0) +#define MG12_12_114PL ~(1 << 13) +#else +#define MG12_12_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_12PL) || (G12_15PL == 0) +#define MG12_12_115PL ~(1 << 14) +#else +#define MG12_12_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_12PL) || (G12_16PL == 0) +#define MG12_12_116PL ~(1 << 15) +#else +#define MG12_12_116PL 0xFFFF +#endif + +#define MG12_12_112PL 0xF7FF +#define MG12_12 (MG12_12_11PL & MG12_12_12PL & MG12_12_13PL & MG12_12_14PL & \ + MG12_12_15PL & MG12_12_16PL & MG12_12_17PL & MG12_12_18PL & \ + MG12_12_19PL & MG12_12_110PL & MG12_12_111PL & MG12_12_112PL & \ + MG12_12_113PL & MG12_12_114PL & MG12_12_115PL & MG12_12_116PL) +// End of MG12_12: +// Beginning of MG1213: +#if (G12_1PL >= G12_13PL) || (G12_1PL == 0) +#define MG12_13_11PL ~(1 << 0) +#else +#define MG12_13_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_13PL) || (G12_2PL == 0) +#define MG12_13_12PL ~(1 << 1) +#else +#define MG12_13_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_13PL) || (G12_3PL == 0) +#define MG12_13_13PL ~(1 << 2) +#else +#define MG12_13_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_13PL) || (G12_4PL == 0) +#define MG12_13_14PL ~(1 << 3) +#else +#define MG12_13_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_13PL) || (G12_5PL == 0) +#define MG12_13_15PL ~(1 << 4) +#else +#define MG12_13_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_13PL) || (G12_6PL == 0) +#define MG12_13_16PL ~(1 << 5) +#else +#define MG12_13_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_13PL) || (G12_7PL == 0) +#define MG12_13_17PL ~(1 << 6) +#else +#define MG12_13_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_13PL) || (G12_8PL == 0) +#define MG12_13_18PL ~(1 << 7) +#else +#define MG12_13_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_13PL) || (G12_9PL == 0) +#define MG12_13_19PL ~(1 << 8) +#else +#define MG12_13_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_13PL) || (G12_10PL == 0) +#define MG12_13_110PL ~(1 << 9) +#else +#define MG12_13_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_13PL) || (G12_11PL == 0) +#define MG12_13_111PL ~(1 << 10) +#else +#define MG12_13_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_13PL) || (G12_12PL == 0) +#define MG12_13_112PL ~(1 << 11) +#else +#define MG12_13_112PL 0xFFFF +#endif + +#if (G12_14PL >= G12_13PL) || (G12_14PL == 0) +#define MG12_13_114PL ~(1 << 13) +#else +#define MG12_13_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_13PL) || (G12_15PL == 0) +#define MG12_13_115PL ~(1 << 14) +#else +#define MG12_13_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_13PL) || (G12_16PL == 0) +#define MG12_13_116PL ~(1 << 15) +#else +#define MG12_13_116PL 0xFFFF +#endif + +#define MG12_13_113PL 0xEFFF +#define MG12_13 (MG12_13_11PL & MG12_13_12PL & MG12_13_13PL & MG12_13_14PL & \ + MG12_13_15PL & MG12_13_16PL & MG12_13_17PL & MG12_13_18PL & \ + MG12_13_19PL & MG12_13_110PL & MG12_13_111PL & MG12_13_112PL & \ + MG12_13_113PL & MG12_13_114PL & MG12_13_115PL & MG12_13_116PL) +// End of MG12_13: +// Beginning of MG1214: +#if (G12_1PL >= G12_14PL) || (G12_1PL == 0) +#define MG12_14_11PL ~(1 << 0) +#else +#define MG12_14_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_14PL) || (G12_2PL == 0) +#define MG12_14_12PL ~(1 << 1) +#else +#define MG12_14_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_14PL) || (G12_3PL == 0) +#define MG12_14_13PL ~(1 << 2) +#else +#define MG12_14_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_14PL) || (G12_4PL == 0) +#define MG12_14_14PL ~(1 << 3) +#else +#define MG12_14_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_14PL) || (G12_5PL == 0) +#define MG12_14_15PL ~(1 << 4) +#else +#define MG12_14_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_14PL) || (G12_6PL == 0) +#define MG12_14_16PL ~(1 << 5) +#else +#define MG12_14_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_14PL) || (G12_7PL == 0) +#define MG12_14_17PL ~(1 << 6) +#else +#define MG12_14_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_14PL) || (G12_8PL == 0) +#define MG12_14_18PL ~(1 << 7) +#else +#define MG12_14_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_14PL) || (G12_9PL == 0) +#define MG12_14_19PL ~(1 << 8) +#else +#define MG12_14_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_14PL) || (G12_10PL == 0) +#define MG12_14_110PL ~(1 << 9) +#else +#define MG12_14_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_14PL) || (G12_11PL == 0) +#define MG12_14_111PL ~(1 << 10) +#else +#define MG12_14_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_14PL) || (G12_12PL == 0) +#define MG12_14_112PL ~(1 << 11) +#else +#define MG12_14_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_14PL) || (G12_13PL == 0) +#define MG12_14_113PL ~(1 << 12) +#else +#define MG12_14_113PL 0xFFFF +#endif + +#if (G12_15PL >= G12_14PL) || (G12_15PL == 0) +#define MG12_14_115PL ~(1 << 14) +#else +#define MG12_14_115PL 0xFFFF +#endif + +#if (G12_16PL >= G12_14PL) || (G12_16PL == 0) +#define MG12_14_116PL ~(1 << 15) +#else +#define MG12_14_116PL 0xFFFF +#endif + +#define MG12_14_114PL 0xDFFF +#define MG12_14 (MG12_14_11PL & MG12_14_12PL & MG12_14_13PL & MG12_14_14PL & \ + MG12_14_15PL & MG12_14_16PL & MG12_14_17PL & MG12_14_18PL & \ + MG12_14_19PL & MG12_14_110PL & MG12_14_111PL & MG12_14_112PL & \ + MG12_14_113PL & MG12_14_114PL & MG12_14_115PL & MG12_14_116PL) +// End of MG12_14: +// Beginning of MG1215: +#if (G12_1PL >= G12_15PL) || (G12_1PL == 0) +#define MG12_15_11PL ~(1 << 0) +#else +#define MG12_15_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_15PL) || (G12_2PL == 0) +#define MG12_15_12PL ~(1 << 1) +#else +#define MG12_15_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_15PL) || (G12_3PL == 0) +#define MG12_15_13PL ~(1 << 2) +#else +#define MG12_15_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_15PL) || (G12_4PL == 0) +#define MG12_15_14PL ~(1 << 3) +#else +#define MG12_15_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_15PL) || (G12_5PL == 0) +#define MG12_15_15PL ~(1 << 4) +#else +#define MG12_15_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_15PL) || (G12_6PL == 0) +#define MG12_15_16PL ~(1 << 5) +#else +#define MG12_15_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_15PL) || (G12_7PL == 0) +#define MG12_15_17PL ~(1 << 6) +#else +#define MG12_15_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_15PL) || (G12_8PL == 0) +#define MG12_15_18PL ~(1 << 7) +#else +#define MG12_15_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_15PL) || (G12_9PL == 0) +#define MG12_15_19PL ~(1 << 8) +#else +#define MG12_15_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_15PL) || (G12_10PL == 0) +#define MG12_15_110PL ~(1 << 9) +#else +#define MG12_15_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_15PL) || (G12_11PL == 0) +#define MG12_15_111PL ~(1 << 10) +#else +#define MG12_15_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_15PL) || (G12_12PL == 0) +#define MG12_15_112PL ~(1 << 11) +#else +#define MG12_15_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_15PL) || (G12_13PL == 0) +#define MG12_15_113PL ~(1 << 12) +#else +#define MG12_15_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_15PL) || (G12_14PL == 0) +#define MG12_15_114PL ~(1 << 13) +#else +#define MG12_15_114PL 0xFFFF +#endif + +#if (G12_16PL >= G12_15PL) || (G12_16PL == 0) +#define MG12_15_116PL ~(1 << 15) +#else +#define MG12_15_116PL 0xFFFF +#endif + +#define MG12_15_115PL 0xBFFF +#define MG12_15 (MG12_15_11PL & MG12_15_12PL & MG12_15_13PL & MG12_15_14PL & \ + MG12_15_15PL & MG12_15_16PL & MG12_15_17PL & MG12_15_18PL & \ + MG12_15_19PL & MG12_15_110PL & MG12_15_111PL & MG12_15_112PL & \ + MG12_15_113PL & MG12_15_114PL & MG12_15_115PL & MG12_15_116PL) +// End of MG12_15: +// Beginning of MG1216: +#if (G12_1PL >= G12_16PL) || (G12_1PL == 0) +#define MG12_16_11PL ~(1 << 0) +#else +#define MG12_16_11PL 0xFFFF +#endif + +#if (G12_2PL >= G12_16PL) || (G12_2PL == 0) +#define MG12_16_12PL ~(1 << 1) +#else +#define MG12_16_12PL 0xFFFF +#endif + +#if (G12_3PL >= G12_16PL) || (G12_3PL == 0) +#define MG12_16_13PL ~(1 << 2) +#else +#define MG12_16_13PL 0xFFFF +#endif + +#if (G12_4PL >= G12_16PL) || (G12_4PL == 0) +#define MG12_16_14PL ~(1 << 3) +#else +#define MG12_16_14PL 0xFFFF +#endif + +#if (G12_5PL >= G12_16PL) || (G12_5PL == 0) +#define MG12_16_15PL ~(1 << 4) +#else +#define MG12_16_15PL 0xFFFF +#endif + +#if (G12_6PL >= G12_16PL) || (G12_6PL == 0) +#define MG12_16_16PL ~(1 << 5) +#else +#define MG12_16_16PL 0xFFFF +#endif + +#if (G12_7PL >= G12_16PL) || (G12_7PL == 0) +#define MG12_16_17PL ~(1 << 6) +#else +#define MG12_16_17PL 0xFFFF +#endif + +#if (G12_8PL >= G12_16PL) || (G12_8PL == 0) +#define MG12_16_18PL ~(1 << 7) +#else +#define MG12_16_18PL 0xFFFF +#endif + +#if (G12_9PL >= G12_16PL) || (G12_9PL == 0) +#define MG12_16_19PL ~(1 << 8) +#else +#define MG12_16_19PL 0xFFFF +#endif + +#if (G12_10PL >= G12_16PL) || (G12_10PL == 0) +#define MG12_16_110PL ~(1 << 9) +#else +#define MG12_16_110PL 0xFFFF +#endif + +#if (G12_11PL >= G12_16PL) || (G12_11PL == 0) +#define MG12_16_111PL ~(1 << 10) +#else +#define MG12_16_111PL 0xFFFF +#endif + +#if (G12_12PL >= G12_16PL) || (G12_12PL == 0) +#define MG12_16_112PL ~(1 << 11) +#else +#define MG12_16_112PL 0xFFFF +#endif + +#if (G12_13PL >= G12_16PL) || (G12_13PL == 0) +#define MG12_16_113PL ~(1 << 12) +#else +#define MG12_16_113PL 0xFFFF +#endif + +#if (G12_14PL >= G12_16PL) || (G12_14PL == 0) +#define MG12_16_114PL ~(1 << 13) +#else +#define MG12_16_114PL 0xFFFF +#endif + +#if (G12_15PL >= G12_16PL) || (G12_15PL == 0) +#define MG12_16_115PL ~(1 << 14) +#else +#define MG12_16_115PL 0xFFFF +#endif + +#define MG12_16_116PL 0x7FFF +#define MG12_16 (MG12_16_11PL & MG12_16_12PL & MG12_16_13PL & MG12_16_14PL & \ + MG12_16_15PL & MG12_16_16PL & MG12_16_17PL & MG12_16_18PL & \ + MG12_16_19PL & MG12_16_110PL & MG12_16_111PL & MG12_16_112PL & \ + MG12_16_113PL & MG12_16_114PL & MG12_16_115PL & MG12_16_116PL) +// End of MG12_16: + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // eof + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_SysCtrl_defines.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_SysCtrl_defines.h new file mode 100644 index 0000000000..a0f342d14c --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_SysCtrl_defines.h @@ -0,0 +1,63 @@ +//########################################################################### +// +// FILE: F2837xD_SysCtrl_defines.h +// +// TITLE: F2837xD LPM support definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_SYSCTRL_DEFINES_H +#define F2837xD_SYSCTRL_DEFINES_H + +// +// Defines +// +#define LPM_IDLE 0x0 +#define LPM_STANDBY 0x1 +#define LPM_HALT 0x2 +#define LPM_HIB 0x3 + +// +//Key value used for write access to the flash pump semaphore register +// +#define IPC_PUMP_KEY 0x5a5a0000 + +#endif // end of F2837xD_SYSCTRL_DEFINES_H definition + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Systick_defines.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Systick_defines.h new file mode 100644 index 0000000000..dbf45cb249 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Systick_defines.h @@ -0,0 +1,80 @@ +//########################################################################### +// +// FILE: systick.h +// +// TITLE: Stellaris style wrapper driver for C28x CPU Timer 0. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __SYSTICK_H__ +#define __SYSTICK_H__ + +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +#ifdef __cplusplus +extern "C" +{ +#endif + +// +// Function Prototypes +// +extern void SysTickInit(void); +extern void SysTickEnable(void); +extern void SysTickDisable(void); +extern void SysTickIntRegister(void (*pfnHandler)(void)); +extern void SysTickIntUnregister(void); +extern void SysTickIntEnable(void); +extern void SysTickIntDisable(void); +extern void SysTickPeriodSet(unsigned long ulPeriod); +extern unsigned long SysTickPeriodGet(void); +extern unsigned long SysTickValueGet(void); + +// +// Mark the end of the C bindings section for C++ compilers. +// +#ifdef __cplusplus +} +#endif + +#endif // __SYSTICK_H__ + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Upp_defines.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Upp_defines.h new file mode 100644 index 0000000000..43d602bfb0 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_Upp_defines.h @@ -0,0 +1,86 @@ +//########################################################################### +// +// FILE: F2837xD_Upp_defines.h +// +// TITLE: #defines used in Upp examples +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_UPP_DEFINES_H +#define F2837xD_UPP_DEFINES_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// +#define uPP_TX_MSGRAM_ADDR 0x6C00 +#define uPP_TX_MSGRAM_SIZE 512 + +#define uPP_RX_MSGRAM_ADDR 0x6E00 +#define uPP_RX_MSGRAM_SIZE 512 + +#define uPP_RX_MODE 0 +#define uPP_TX_MODE 1 + +#define uPP_SDR 0 +#define uPP_DDR 1 + +#define uPP_TX_SIZE_64B 0 +#define uPP_TX_SIZE_128B 1 +#define uPP_TX_SIZE_256B 3 + +#define uPP_RX_SIZE_64B 0 +#define uPP_RX_SIZE_128B 1 +#define uPP_RX_SIZE_256B 3 + +#define uPP_INT_EOWI 0x8 +#define uPP_INT_EOLI 0x10 +#define uPP_INT_EOWQ 0x800 +#define uPP_INT_EOLQ 0x1000 + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_UPP_DEFINES_H + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_cputimervars.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_cputimervars.h new file mode 100644 index 0000000000..0f32f58aea --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_cputimervars.h @@ -0,0 +1,138 @@ +//########################################################################### +// +// FILE: F2837xD_Cputimers.h +// +// TITLE: F2837xD Device CPUTIMERS Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_CPUTIMERVARS_H +#define F2837xD_CPUTIMERVARS_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Globals +// +struct CPUTIMER_VARS { + volatile struct CPUTIMER_REGS *RegsAddr; + Uint32 InterruptCount; + float CPUFreqInMHz; + float PeriodInUSec; +}; + +extern struct CPUTIMER_VARS CpuTimer0; +extern struct CPUTIMER_VARS CpuTimer1; +extern struct CPUTIMER_VARS CpuTimer2; + +// +// Defines +// + +// +// Start Timer: +// +#define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 + +// +// Stop Timer: +// +#define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value: +// +#define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value: +// +#define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all + +// +// Read 32-Bit Period Value: +// +#define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all + +// +// Start Timer: +// +#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 +#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 + +// +// Stop Timer: +// +#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 +#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 + +// +// Reload Timer With period Value: +// +#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 +#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 + +// +// Read 32-Bit Timer Value: +// +#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all +#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all + +// +// Read 32-Bit Period Value: +// +#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all +#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all + +// +// Function Prototypes +// +void InitCpuTimers(void); +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif // end of F2837xD_CPUTIMERVARS_H definition + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_defaultisr.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_defaultisr.h new file mode 100644 index 0000000000..3f351d85b7 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_defaultisr.h @@ -0,0 +1,216 @@ +//########################################################################### +// +// FILE: F2837xD_defaultisr.h +// +// TITLE: F2837xD Device Default Interrupt Service Routines Definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_DEFAULT_ISR_H +#define F2837xD_DEFAULT_ISR_H +#ifdef __cplusplus +extern "C" { +#endif + +// +// Default Interrupt Service Routine Declarations: +// The following function prototypes are for the +// default ISR routines used with the default PIE vector table. +// This default vector table is found in the F2837xD_pievect.h +// file. +// +interrupt void TIMER1_ISR(void); // CPU Timer 1 Interrupt +interrupt void TIMER2_ISR(void); // CPU Timer 2 Interrupt +interrupt void DATALOG_ISR(void); // Datalogging Interrupt +interrupt void RTOS_ISR(void); // RTOS Interrupt +interrupt void EMU_ISR(void); // Emulation Interrupt +interrupt void NMI_ISR(void); // Non-Maskable Interrupt +interrupt void ILLEGAL_ISR(void); // Illegal Operation Trap +interrupt void USER1_ISR(void); // User Defined Trap 1 +interrupt void USER2_ISR(void); // User Defined Trap 2 +interrupt void USER3_ISR(void); // User Defined Trap 3 +interrupt void USER4_ISR(void); // User Defined Trap 4 +interrupt void USER5_ISR(void); // User Defined Trap 5 +interrupt void USER6_ISR(void); // User Defined Trap 6 +interrupt void USER7_ISR(void); // User Defined Trap 7 +interrupt void USER8_ISR(void); // User Defined Trap 8 +interrupt void USER9_ISR(void); // User Defined Trap 9 +interrupt void USER10_ISR(void); // User Defined Trap 10 +interrupt void USER11_ISR(void); // User Defined Trap 11 +interrupt void USER12_ISR(void); // User Defined Trap 12 +interrupt void ADCA1_ISR(void); // 1.1 - ADCA Interrupt 1 +interrupt void ADCB1_ISR(void); // 1.2 - ADCB Interrupt 1 +interrupt void ADCC1_ISR(void); // 1.3 - ADCC Interrupt 1 +interrupt void XINT1_ISR(void); // 1.4 - XINT1 Interrupt +interrupt void XINT2_ISR(void); // 1.5 - XINT2 Interrupt +interrupt void ADCD1_ISR(void); // 1.6 - ADCD Interrupt 1 +interrupt void TIMER0_ISR(void); // 1.7 - Timer 0 Interrupt +interrupt void WAKE_ISR(void); // 1.8 - Standby and Halt Wakeup Interrupt +interrupt void EPWM1_TZ_ISR(void); // 2.1 - ePWM1 Trip Zone Interrupt +interrupt void EPWM2_TZ_ISR(void); // 2.2 - ePWM2 Trip Zone Interrupt +interrupt void EPWM3_TZ_ISR(void); // 2.3 - ePWM3 Trip Zone Interrupt +interrupt void EPWM4_TZ_ISR(void); // 2.4 - ePWM4 Trip Zone Interrupt +interrupt void EPWM5_TZ_ISR(void); // 2.5 - ePWM5 Trip Zone Interrupt +interrupt void EPWM6_TZ_ISR(void); // 2.6 - ePWM6 Trip Zone Interrupt +interrupt void EPWM7_TZ_ISR(void); // 2.7 - ePWM7 Trip Zone Interrupt +interrupt void EPWM8_TZ_ISR(void); // 2.8 - ePWM8 Trip Zone Interrupt +interrupt void EPWM1_ISR(void); // 3.1 - ePWM1 Interrupt +interrupt void EPWM2_ISR(void); // 3.2 - ePWM2 Interrupt +interrupt void EPWM3_ISR(void); // 3.3 - ePWM3 Interrupt +interrupt void EPWM4_ISR(void); // 3.4 - ePWM4 Interrupt +interrupt void EPWM5_ISR(void); // 3.5 - ePWM5 Interrupt +interrupt void EPWM6_ISR(void); // 3.6 - ePWM6 Interrupt +interrupt void EPWM7_ISR(void); // 3.7 - ePWM7 Interrupt +interrupt void EPWM8_ISR(void); // 3.8 - ePWM8 Interrupt +interrupt void ECAP1_ISR(void); // 4.1 - eCAP1 Interrupt +interrupt void ECAP2_ISR(void); // 4.2 - eCAP2 Interrupt +interrupt void ECAP3_ISR(void); // 4.3 - eCAP3 Interrupt +interrupt void ECAP4_ISR(void); // 4.4 - eCAP4 Interrupt +interrupt void ECAP5_ISR(void); // 4.5 - eCAP5 Interrupt +interrupt void ECAP6_ISR(void); // 4.6 - eCAP6 Interrupt +interrupt void EQEP1_ISR(void); // 5.1 - eQEP1 Interrupt +interrupt void EQEP2_ISR(void); // 5.2 - eQEP2 Interrupt +interrupt void EQEP3_ISR(void); // 5.3 - eQEP3 Interrupt +interrupt void SPIA_RX_ISR(void); // 6.1 - SPIA Receive Interrupt +interrupt void SPIA_TX_ISR(void); // 6.2 - SPIA Transmit Interrupt +interrupt void SPIB_RX_ISR(void); // 6.3 - SPIB Receive Interrupt +interrupt void SPIB_TX_ISR(void); // 6.4 - SPIB Transmit Interrupt +interrupt void MCBSPA_RX_ISR(void); // 6.5 - McBSPA Receive Interrupt +interrupt void MCBSPA_TX_ISR(void); // 6.6 - McBSPA Transmit Interrupt +interrupt void MCBSPB_RX_ISR(void); // 6.7 - McBSPB Receive Interrupt +interrupt void MCBSPB_TX_ISR(void); // 6.8 - McBSPB Transmit Interrupt +interrupt void DMA_CH1_ISR(void); // 7.1 - DMA Channel 1 Interrupt +interrupt void DMA_CH2_ISR(void); // 7.2 - DMA Channel 2 Interrupt +interrupt void DMA_CH3_ISR(void); // 7.3 - DMA Channel 3 Interrupt +interrupt void DMA_CH4_ISR(void); // 7.4 - DMA Channel 4 Interrupt +interrupt void DMA_CH5_ISR(void); // 7.5 - DMA Channel 5 Interrupt +interrupt void DMA_CH6_ISR(void); // 7.6 - DMA Channel 6 Interrupt +interrupt void I2CA_ISR(void); // 8.1 - I2CA Interrupt 1 +interrupt void I2CA_FIFO_ISR(void); // 8.2 - I2CA Interrupt 2 +interrupt void I2CB_ISR(void); // 8.3 - I2CB Interrupt 1 +interrupt void I2CB_FIFO_ISR(void); // 8.4 - I2CB Interrupt 2 +interrupt void SCIC_RX_ISR(void); // 8.5 - SCIC Receive Interrupt +interrupt void SCIC_TX_ISR(void); // 8.6 - SCIC Transmit Interrupt +interrupt void SCID_RX_ISR(void); // 8.7 - SCID Receive Interrupt +interrupt void SCID_TX_ISR(void); // 8.8 - SCID Transmit Interrupt +interrupt void SCIA_RX_ISR(void); // 9.1 - SCIA Receive Interrupt +interrupt void SCIA_TX_ISR(void); // 9.2 - SCIA Transmit Interrupt +interrupt void SCIB_RX_ISR(void); // 9.3 - SCIB Receive Interrupt +interrupt void SCIB_TX_ISR(void); // 9.4 - SCIB Transmit Interrupt +interrupt void CANA0_ISR(void); // 9.5 - CANA Interrupt 0 +interrupt void CANA1_ISR(void); // 9.6 - CANA Interrupt 1 +interrupt void CANB0_ISR(void); // 9.7 - CANB Interrupt 0 +interrupt void CANB1_ISR(void); // 9.8 - CANB Interrupt 1 +interrupt void ADCA_EVT_ISR(void); // 10.1 - ADCA Event Interrupt +interrupt void ADCA2_ISR(void); // 10.2 - ADCA Interrupt 2 +interrupt void ADCA3_ISR(void); // 10.3 - ADCA Interrupt 3 +interrupt void ADCA4_ISR(void); // 10.4 - ADCA Interrupt 4 +interrupt void ADCB_EVT_ISR(void); // 10.5 - ADCB Event Interrupt +interrupt void ADCB2_ISR(void); // 10.6 - ADCB Interrupt 2 +interrupt void ADCB3_ISR(void); // 10.7 - ADCB Interrupt 3 +interrupt void ADCB4_ISR(void); // 10.8 - ADCB Interrupt 4 +interrupt void CLA1_1_ISR(void); // 11.1 - CLA1 Interrupt 1 +interrupt void CLA1_2_ISR(void); // 11.2 - CLA1 Interrupt 2 +interrupt void CLA1_3_ISR(void); // 11.3 - CLA1 Interrupt 3 +interrupt void CLA1_4_ISR(void); // 11.4 - CLA1 Interrupt 4 +interrupt void CLA1_5_ISR(void); // 11.5 - CLA1 Interrupt 5 +interrupt void CLA1_6_ISR(void); // 11.6 - CLA1 Interrupt 6 +interrupt void CLA1_7_ISR(void); // 11.7 - CLA1 Interrupt 7 +interrupt void CLA1_8_ISR(void); // 11.8 - CLA1 Interrupt 8 +interrupt void XINT3_ISR(void); // 12.1 - XINT3 Interrupt +interrupt void XINT4_ISR(void); // 12.2 - XINT4 Interrupt +interrupt void XINT5_ISR(void); // 12.3 - XINT5 Interrupt +interrupt void VCU_ISR(void); // 12.6 - VCU Interrupt +interrupt void FPU_OVERFLOW_ISR(void); // 12.7 - FPU Overflow Interrupt +interrupt void FPU_UNDERFLOW_ISR(void); // 12.8 - FPU Underflow Interrupt +interrupt void IPC0_ISR(void); // 1.13 - IPC Interrupt 0 +interrupt void IPC1_ISR(void); // 1.14 - IPC Interrupt 1 +interrupt void IPC2_ISR(void); // 1.15 - IPC Interrupt 2 +interrupt void IPC3_ISR(void); // 1.16 - IPC Interrupt 3 +interrupt void EPWM9_TZ_ISR(void); // 2.9 - ePWM9 Trip Zone Interrupt +interrupt void EPWM10_TZ_ISR(void); // 2.10 - ePWM10 Trip Zone Interrupt +interrupt void EPWM11_TZ_ISR(void); // 2.11 - ePWM11 Trip Zone Interrupt +interrupt void EPWM12_TZ_ISR(void); // 2.12 - ePWM12 Trip Zone Interrupt +interrupt void EPWM9_ISR(void); // 3.9 - ePWM9 Interrupt +interrupt void EPWM10_ISR(void); // 3.10 - ePWM10 Interrupt +interrupt void EPWM11_ISR(void); // 3.11 - ePWM11 Interrupt +interrupt void EPWM12_ISR(void); // 3.12 - ePWM12 Interrupt +interrupt void SD1_ISR(void); // 5.9 - SD1 Interrupt +interrupt void SD2_ISR(void); // 5.10 - SD2 Interrupt +interrupt void SPIC_RX_ISR(void); // 6.9 - SPIC Receive Interrupt +interrupt void SPIC_TX_ISR(void); // 6.10 - SPIC Transmit Interrupt +interrupt void UPPA_ISR(void); // 8.15 - uPPA Interrupt +interrupt void USBA_ISR(void); // 9.15 - USBA Interrupt +interrupt void ADCC_EVT_ISR(void); // 10.9 - ADCC Event Interrupt +interrupt void ADCC2_ISR(void); // 10.10 - ADCC Interrupt 2 +interrupt void ADCC3_ISR(void); // 10.11 - ADCC Interrupt 3 +interrupt void ADCC4_ISR(void); // 10.12 - ADCC Interrupt 4 +interrupt void ADCD_EVT_ISR(void); // 10.13 - ADCD Event Interrupt +interrupt void ADCD2_ISR(void); // 10.14 - ADCD Interrupt 2 +interrupt void ADCD3_ISR(void); // 10.15 - ADCD Interrupt 3 +interrupt void ADCD4_ISR(void); // 10.16 - ADCD Interrupt 4 +interrupt void EMIF_ERROR_ISR(void); // 12.9 - EMIF Error Interrupt +interrupt void RAM_CORRECTABLE_ERROR_ISR(void); // 12.10 - RAM Correctable + // Error Interrupt +interrupt void FLASH_CORRECTABLE_ERROR_ISR(void); // 12.11 - Flash Correctable + // Error Interrupt +interrupt void RAM_ACCESS_VIOLATION_ISR(void); // 12.12 - RAM Access + // Violation Interrupt +interrupt void SYS_PLL_SLIP_ISR(void); // 12.13 - System PLL Slip + // Interrupt +interrupt void AUX_PLL_SLIP_ISR(void); // 12.14 - Auxiliary PLL + // Slip Interrupt +interrupt void CLA_OVERFLOW_ISR(void); // 12.15 - CLA Overflow + // Interrupt +interrupt void CLA_UNDERFLOW_ISR(void); // 12.16 - CLA Underflow + // Interrupt + +// +// Catch-all for PIE Reserved Locations for testing purposes: +// +interrupt void PIE_RESERVED_ISR(void); // Reserved ISR +interrupt void EMPTY_ISR(void); // Only does a return +interrupt void NOTUSED_ISR(void); // Unused ISR +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // end of F2837xD_PIEVECT_H definition + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_sci_io.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_sci_io.h new file mode 100644 index 0000000000..41ecacb9be --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_sci_io.h @@ -0,0 +1,70 @@ +//########################################################################### +// +// FILE: F2837xD_sci_io.h +// +// TITLE: Prototypes for SCI redirection to STDIO +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_SCI_IO_H +#define F2837xD_SCI_IO_H + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Function Prototypes +// +extern int SCI_open(const char * path, unsigned flags, int llv_fd); +extern int SCI_close(int dev_fd); +extern int SCI_read(int dev_fd, char * buf, unsigned count); +extern int SCI_write(int dev_fd, char * buf, unsigned count); +extern off_t SCI_lseek(int dev_fd, off_t offset, int origin); +extern int SCI_unlink(const char * path); +extern int SCI_rename(const char * old_name, const char * new_name); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_sdfm_drivers.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_sdfm_drivers.h new file mode 100644 index 0000000000..0cde1ad5ae --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_sdfm_drivers.h @@ -0,0 +1,530 @@ +//########################################################################### +// +// FILE: F2837xD_sdfm_drivers.h +// +// TITLE: Defines and Macros for the SDFM driver Controller +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_SDFM_DRIVERS_H +#define F2837xD_SDFM_DRIVERS_H + + +#ifdef __cplusplus +extern "C" { +#endif + +// +// Defines +// + +// +// This is used to select either SDFM module 1 & SDFM module 2 +// +#define SDFM1 1 //Can be used to select SDFM module 1 +#define SDFM2 2 //Can be used to select SDFM module 2 + +// +// Max OSR values of different modules +// +#define COMPARATOR_MAX_OSR 32 //Max OSR for comparator +#define DATA_FILTER_MAX_OSR 256 //Max OSR for Data filter + +// +// Different Input Control modes +// These values can be passed as argument to Sdfm_configureInputCtrl() +// +#define MODE_0 0 //Used to select Mode0 : + //Modulator clock rate = Modulator data rate +#define MODE_1 1 //Used to select MODE1 : + //Modulator clock rate = (Modulator data rate / 2) +#define MODE_2 2 //Used to select MODE2 : + //Manchester encoded data + //(Modulator clock is encoded into data) +#define MODE_3 3 //Used to select MODE3 : + //Modulator clock rate = (2 x Modulator data rate) + +// +// The following are values that can be passed to following functions +// +// (1) Sdfm_configureInputCtrl() +// (2) Sdfm_configureComparator() +// (3) Sdfm_configureData_filter() +// (4) Sdfm_configureInterrupt() +// +#define FILTER1 0x01 //Used to select filter1 for comparator or Data filter +#define FILTER2 0x02 //Used to select filter2 for comparator or Data filter +#define FILTER3 0x04 //Used to select filter3 for comparator or Data filter +#define FILTER4 0x08 //Used to select filter4 for comparator or Data filter + +// +// The following are values that can be passed to Sdfm_configureData_filter() +// +#define FILTER_DISABLE 0 //Used to disable filter +#define FILTER_ENABLE 1 //Used to enable filter + +// +// The following are values that can be passed to following functions +// +// (1) Sdfm_configureComparator() +// (2) Sdfm_configureData_filter() +// +#define SINCFAST 0x00 //Used to select Sincfast filter type for comparator + //or Data filter +#define SINC1 0x01 //Used to select Sinc1 filter type for comparator + //or Data filter +#define SINC2 0x02 //Used to select Sinc2 filter type for comparator + //or Data filter +#define SINC3 0x03 //Used to select Sinc3 filter type for comparator + //or Data filter + +// +// Enable / Disable High-level threshold interrupt for Comparator filter output +// These values can be passed as argument to Sdfm_configureInterrupt() +// +#define IEH_DISABLE 0 //Used to disable over value interrupt to CPU +#define IEH_ENABLE 1 //Used to enable over value interrupt to CPU + +// +// Enable / Disable Low-level threshold interrupt for Comparator filter output +// These values can be passed as argument to Sdfm_configureInterrupt() +// +#define IEL_DISABLE 0 //Used to disable under value interrupt to CPU +#define IEL_ENABLE 1 //Used to enable under value interrupt to CPU + +// +//Enable / Disable modulator failure interrupt +// These values can be passed as argument to Sdfm_configureInterrupt() +// +#define MFIE_DISABLE 0 //Used to disable modulator failure interrupt to CPU +#define MFIE_ENABLE 1 //Used to enable modulator failure interrupt to CPU + +// +// Enable / Disable Acknowledge flag +// These values can be passed as argument to Sdfm_configureInterrupt() +// +#define AE_DISABLE 0 //Used to disable new filter data acknowledge + //interrupt to CPU +#define AE_ENABLE 1 //Used to enable new filter data acknowledge + //interrupt to CPU + +// +// Sinc Filter Reset enable / disable for External Reset from PWM Compare +// output +// This following value can be passed to Sdfm_configureExternalreset() +// +#define FILTER_1_EXT_RESET_DISABLE 0 +#define FILTER_1_EXT_RESET_ENABLE 1 +#define FILTER_2_EXT_RESET_DISABLE 0 +#define FILTER_2_EXT_RESET_ENABLE 1 +#define FILTER_3_EXT_RESET_DISABLE 0 +#define FILTER_3_EXT_RESET_ENABLE 1 +#define FILTER_4_EXT_RESET_DISABLE 0 +#define FILTER_4_EXT_RESET_ENABLE 1 + +// +// Filter output data can be represented in 16 bit (or) 32 bit format +// This value can be passed to Sdfm_configureData_filter() +// +#define DATA_16_BIT 0 //Data stored in 16b 2's complement +#define DATA_32_BIT 1 //Data stored in 32b 2's complement + +// +// Macro to read the SDFM1 filter data in 16 bit format +// +#define SDFM1_READ_FILTER1_DATA_16BIT *(volatile Uint16 *)0x5E17 +#define SDFM1_READ_FILTER2_DATA_16BIT *(volatile Uint16 *)0x5E27 +#define SDFM1_READ_FILTER3_DATA_16BIT *(volatile Uint16 *)0x5E37 +#define SDFM1_READ_FILTER4_DATA_16BIT *(volatile Uint16 *)0x5E47 + +// +// Macro to read the SDFM1 filter data in 32 bit format +// +#define SDFM1_READ_FILTER1_DATA_32BIT *(volatile Uint32 *)0x5E16 +#define SDFM1_READ_FILTER2_DATA_32BIT *(volatile Uint32 *)0x5E26 +#define SDFM1_READ_FILTER3_DATA_32BIT *(volatile Uint32 *)0x5E36 +#define SDFM1_READ_FILTER4_DATA_32BIT *(volatile Uint32 *)0x5E46 + +// +// Macro to read the SDFM2 filter data in 16 bit format +// +#define SDFM2_READ_FILTER1_DATA_16BIT *(volatile Uint16 *)0x5E97 +#define SDFM2_READ_FILTER2_DATA_16BIT *(volatile Uint16 *)0x5EA7 +#define SDFM2_READ_FILTER3_DATA_16BIT *(volatile Uint16 *)0x5EB7 +#define SDFM2_READ_FILTER4_DATA_16BIT *(volatile Uint16 *)0x5EC7 + +// +// Macro to read the SDFM2 filter data in 32 bit format +// +#define SDFM2_READ_FILTER1_DATA_32BIT *(volatile Uint16 *)0x5E96 +#define SDFM2_READ_FILTER2_DATA_32BIT *(volatile Uint16 *)0x5EA6 +#define SDFM2_READ_FILTER3_DATA_32BIT *(volatile Uint16 *)0x5EB6 +#define SDFM2_READ_FILTER4_DATA_32BIT *(volatile Uint16 *)0x5EC6 + +// +// The following are defines for different OSR values +// +#define OSR_1 0 +#define OSR_2 1 +#define OSR_3 2 +#define OSR_4 3 +#define OSR_5 4 +#define OSR_6 5 +#define OSR_7 6 +#define OSR_8 7 +#define OSR_9 8 +#define OSR_10 9 +#define OSR_11 10 +#define OSR_12 11 +#define OSR_13 12 +#define OSR_14 13 +#define OSR_15 14 +#define OSR_16 15 +#define OSR_17 16 +#define OSR_18 17 +#define OSR_19 18 +#define OSR_20 19 +#define OSR_21 20 +#define OSR_22 21 +#define OSR_23 22 +#define OSR_24 23 +#define OSR_25 24 +#define OSR_26 25 +#define OSR_27 26 +#define OSR_28 27 +#define OSR_29 28 +#define OSR_30 29 +#define OSR_31 30 +#define OSR_32 31 +#define OSR_33 32 +#define OSR_34 33 +#define OSR_35 34 +#define OSR_36 35 +#define OSR_37 36 +#define OSR_38 37 +#define OSR_39 38 +#define OSR_40 39 +#define OSR_41 40 +#define OSR_42 41 +#define OSR_43 42 +#define OSR_44 43 +#define OSR_45 44 +#define OSR_46 45 +#define OSR_47 46 +#define OSR_48 47 +#define OSR_49 48 +#define OSR_50 49 +#define OSR_51 50 +#define OSR_52 51 +#define OSR_53 52 +#define OSR_54 53 +#define OSR_55 54 +#define OSR_56 55 +#define OSR_57 56 +#define OSR_58 57 +#define OSR_59 58 +#define OSR_60 59 +#define OSR_61 60 +#define OSR_62 61 +#define OSR_63 62 +#define OSR_64 63 +#define OSR_65 64 +#define OSR_66 65 +#define OSR_67 66 +#define OSR_68 67 +#define OSR_69 68 +#define OSR_70 69 +#define OSR_71 70 +#define OSR_72 71 +#define OSR_73 72 +#define OSR_74 73 +#define OSR_75 74 +#define OSR_76 75 +#define OSR_77 76 +#define OSR_78 77 +#define OSR_79 78 +#define OSR_80 79 +#define OSR_81 80 +#define OSR_82 81 +#define OSR_83 82 +#define OSR_84 83 +#define OSR_85 84 +#define OSR_86 85 +#define OSR_87 86 +#define OSR_88 87 +#define OSR_89 88 +#define OSR_90 89 +#define OSR_91 90 +#define OSR_92 91 +#define OSR_93 92 +#define OSR_94 93 +#define OSR_95 94 +#define OSR_96 95 +#define OSR_97 96 +#define OSR_98 97 +#define OSR_99 98 +#define OSR_100 99 +#define OSR_101 100 +#define OSR_102 101 +#define OSR_103 102 +#define OSR_104 103 +#define OSR_105 104 +#define OSR_106 105 +#define OSR_107 106 +#define OSR_108 107 +#define OSR_109 108 +#define OSR_110 109 +#define OSR_111 110 +#define OSR_112 111 +#define OSR_113 112 +#define OSR_114 113 +#define OSR_115 114 +#define OSR_116 115 +#define OSR_117 116 +#define OSR_118 117 +#define OSR_119 118 +#define OSR_120 119 +#define OSR_121 120 +#define OSR_122 121 +#define OSR_123 122 +#define OSR_124 123 +#define OSR_125 124 +#define OSR_126 125 +#define OSR_127 126 +#define OSR_128 127 +#define OSR_129 128 +#define OSR_130 129 +#define OSR_131 130 +#define OSR_132 131 +#define OSR_133 132 +#define OSR_134 133 +#define OSR_135 134 +#define OSR_136 135 +#define OSR_137 136 +#define OSR_138 137 +#define OSR_139 138 +#define OSR_140 139 +#define OSR_141 140 +#define OSR_142 141 +#define OSR_143 142 +#define OSR_144 143 +#define OSR_145 144 +#define OSR_146 145 +#define OSR_147 146 +#define OSR_148 147 +#define OSR_149 148 +#define OSR_150 149 +#define OSR_151 150 +#define OSR_152 151 +#define OSR_153 152 +#define OSR_154 153 +#define OSR_155 154 +#define OSR_156 155 +#define OSR_157 156 +#define OSR_158 157 +#define OSR_159 158 +#define OSR_160 159 +#define OSR_161 160 +#define OSR_162 161 +#define OSR_163 162 +#define OSR_164 163 +#define OSR_165 164 +#define OSR_166 165 +#define OSR_167 166 +#define OSR_168 167 +#define OSR_169 168 +#define OSR_170 169 +#define OSR_171 170 +#define OSR_172 171 +#define OSR_173 172 +#define OSR_174 173 +#define OSR_175 174 +#define OSR_176 175 +#define OSR_177 176 +#define OSR_178 177 +#define OSR_179 178 +#define OSR_180 179 +#define OSR_181 180 +#define OSR_182 181 +#define OSR_183 182 +#define OSR_184 183 +#define OSR_185 184 +#define OSR_186 185 +#define OSR_187 186 +#define OSR_188 187 +#define OSR_189 188 +#define OSR_190 189 +#define OSR_191 190 +#define OSR_192 191 +#define OSR_193 192 +#define OSR_194 193 +#define OSR_195 194 +#define OSR_196 195 +#define OSR_197 196 +#define OSR_198 197 +#define OSR_199 198 +#define OSR_200 199 +#define OSR_201 200 +#define OSR_202 201 +#define OSR_203 202 +#define OSR_204 203 +#define OSR_205 204 +#define OSR_206 205 +#define OSR_207 206 +#define OSR_208 207 +#define OSR_209 208 +#define OSR_210 209 +#define OSR_211 210 +#define OSR_212 211 +#define OSR_213 212 +#define OSR_214 213 +#define OSR_215 214 +#define OSR_216 215 +#define OSR_217 216 +#define OSR_218 217 +#define OSR_219 218 +#define OSR_220 219 +#define OSR_221 220 +#define OSR_222 221 +#define OSR_223 222 +#define OSR_224 223 +#define OSR_225 224 +#define OSR_226 225 +#define OSR_227 226 +#define OSR_228 227 +#define OSR_229 228 +#define OSR_230 229 +#define OSR_231 230 +#define OSR_232 231 +#define OSR_233 232 +#define OSR_234 233 +#define OSR_235 234 +#define OSR_236 235 +#define OSR_237 236 +#define OSR_238 237 +#define OSR_239 238 +#define OSR_240 239 +#define OSR_241 240 +#define OSR_242 241 +#define OSR_243 242 +#define OSR_244 243 +#define OSR_245 244 +#define OSR_246 245 +#define OSR_247 246 +#define OSR_248 247 +#define OSR_249 248 +#define OSR_250 249 +#define OSR_251 250 +#define OSR_252 251 +#define OSR_253 252 +#define OSR_254 253 +#define OSR_255 254 +#define OSR_256 255 + +// +// The following are defines for different OSR values +// +#define SHIFT_0_BITS 0 +#define SHIFT_1_BITS 1 +#define SHIFT_2_BITS 2 +#define SHIFT_3_BITS 3 +#define SHIFT_4_BITS 4 +#define SHIFT_5_BITS 5 +#define SHIFT_6_BITS 6 +#define SHIFT_7_BITS 7 +#define SHIFT_8_BITS 8 +#define SHIFT_9_BITS 9 +#define SHIFT_10_BITS 10 +#define SHIFT_11_BITS 11 +#define SHIFT_12_BITS 12 +#define SHIFT_13_BITS 13 +#define SHIFT_14_BITS 14 +#define SHIFT_15_BITS 15 +#define SHIFT_16_BITS 16 +#define SHIFT_17_BITS 17 +#define SHIFT_18_BITS 18 +#define SHIFT_19_BITS 19 +#define SHIFT_20_BITS 20 +#define SHIFT_21_BITS 21 +#define SHIFT_22_BITS 22 +#define SHIFT_23_BITS 23 +#define SHIFT_24_BITS 24 +#define SHIFT_25_BITS 25 +#define SHIFT_26_BITS 26 +#define SHIFT_27_BITS 27 +#define SHIFT_28_BITS 28 +#define SHIFT_29_BITS 29 +#define SHIFT_30_BITS 30 +#define SHIFT_31_BITS 31 + +// +// Function prototypes +// +extern void Sdfm_configureInputCtrl(Uint16 SDFM_number, + Uint16 Filter_number, Uint16 mode); +extern void Sdfm_configureComparator(Uint16 SDFM_number, + Uint16 Filter_number, Uint16 Filter_type, + Uint16 OSR, Uint16 HLT, Uint16 LLT); +extern void Sdfm_configureData_filter(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 Filter_switch, Uint16 filterType, + Uint16 OSR, Uint16 DR_switch, + Uint16 shift_bits); +extern void Sdfm_enableMFE(Uint16 SDFM_number); +extern void Sdfm_disableMFE(Uint16 SDFM_number); +extern void Sdfm_configureInterrupt(Uint16 SDFM_number, Uint16 Filter_number, + Uint16 IEH_Switch, Uint16 IEL_Switch, + Uint16 MFIE_Switch, Uint16 AE_Switch); +extern void Sdfm_enableMIE(Uint16 SDFM_number); +extern void Sdfm_disableMIE(Uint16 SDFM_number); +extern void Sdfm_configureExternalreset(Uint16 SDFM_number, + Uint16 filter1_Config_ext_reset, + Uint16 filter2_Config_ext_reset, + Uint16 filter3_Config_ext_reset, + Uint16 filter4_Config_ext_reset); +extern Uint32 Sdfm_readFlagRegister(Uint16 SDFM_number); +extern void Sdfm_clearFlagRegister(Uint16 sdfmNumber, + Uint32 sdfmReadFlagRegister); + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_SDFM_DRIVERS_H + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_struct.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_struct.h new file mode 100644 index 0000000000..bd307dd782 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F2837xD_struct.h @@ -0,0 +1,82 @@ +//########################################################################### +// +// FILE: F2837xD_sdfm_strut.h +// +// TITLE: contains structures used for the SDFM driver. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_SDFM_STRUCT_H +#define F2837xD_SDFM_STRUCT_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define MAX_CPUTIMER 4 +#define MAX_ECAP 7 +#define MAX_EPWM 13 +#define MAX_EQEP 4 +#define MAX_I2C 2 +#define MAX_MCBSP 2 +#define MAX_SCI 2 +#define MAX_SPI 4 +#define MAX_ADC 5 +#define MAX_SDFM 3 +#define MAX_TRIPSEL 15 + +extern volatile Uint16 *TRIP_SEL[MAX_TRIPSEL]; +extern volatile struct ADC_REGS *ADC[MAX_ADC]; +extern volatile struct CPUTIMER_REGS *CPUTIMER[MAX_CPUTIMER]; +extern volatile struct ECAP_REGS *ECAP[MAX_ECAP]; +extern volatile struct EPWM_REGS *EPWM[MAX_EPWM]; +extern volatile struct EQEP_REGS *EQEP[MAX_EQEP]; +extern volatile struct I2C_REGS *I2C[MAX_I2C]; +extern volatile struct McBSP_REGS *MCBSP[MAX_MCBSP]; +extern volatile struct SCI_REGS *SCI[MAX_SCI]; +extern volatile struct SPI_REGS *SPI[MAX_SPI]; +extern volatile struct SDFM_REGS *SDFM[MAX_SDFM]; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif // - end of F2837xD_SDFM_STRUCT_H + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/F28x_Project.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F28x_Project.h new file mode 100644 index 0000000000..ffdaa6e98c --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/F28x_Project.h @@ -0,0 +1,58 @@ +//########################################################################### +// +// FILE: F28x_Project.h +// +// TITLE: F28x Project Headerfile and Examples Include File +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F28X_PROJECT_H +#define F28X_PROJECT_H + +// +// Included Files +// +#include "F2837xD_Cla_typedefs.h" // F2837xD CLA Type definitions +#include "F2837xD_device.h" // F2837xD Headerfile Include File +#include "F2837xD_Examples.h" // F2837xD Examples Include File + + +#endif // end of F28X_PROJECT_H definition + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/device.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/device.h new file mode 100644 index 0000000000..9a8e0ad33e --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/device.h @@ -0,0 +1,199 @@ +//############################################################################# +// +// FILE: device.h +// +// TITLE: Device setup for examples. +// +//############################################################################# +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include "driverlib.h" + +#if (!defined(CPU1) && !defined(CPU2)) +#error "You must define CPU1 or CPU2 in your project properties. Otherwise, \ +the offsets in your header files will be inaccurate." +#endif + +#if (defined(CPU1) && defined(CPU2)) +#error "You have defined both CPU1 and CPU2 in your project properties. Only \ +a single CPU should be defined." +#endif + +//***************************************************************************** +// +// Defines for pin numbers and other GPIO configuration +// +//***************************************************************************** +// +// LEDs +// +#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD2 +#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD3 +#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD2 +#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD3 + +// +// SCI for USB-to-UART adapter on FTDI chip +// +#define DEVICE_GPIO_PIN_SCIRXDA 28U // GPIO number for SCI RX +#define DEVICE_GPIO_PIN_SCITXDA 29U // GPIO number for SCI TX +#define DEVICE_GPIO_CFG_SCIRXDA GPIO_28_SCIRXDA // "pinConfig" for SCI RX +#define DEVICE_GPIO_CFG_SCITXDA GPIO_29_SCITXDA // "pinConfig" for SCI TX + +// +// CANA +// +#define DEVICE_GPIO_PIN_CANTXA 31U // GPIO number for CANTXA +#define DEVICE_GPIO_PIN_CANRXA 30U // GPIO number for CANRXA + +// +// CAN External Loopback +// +#define DEVICE_GPIO_CFG_CANRXA GPIO_30_CANRXA // "pinConfig" for CANA RX +#define DEVICE_GPIO_CFG_CANTXA GPIO_31_CANTXA // "pinConfig" for CANA TX +#define DEVICE_GPIO_CFG_CANRXB GPIO_10_CANRXB // "pinConfig" for CANB RX +#define DEVICE_GPIO_CFG_CANTXB GPIO_8_CANTXB // "pinConfig" for CANB TX + +//***************************************************************************** +// +// Defines related to clock configuration +// +//***************************************************************************** +// +// Launchpad Configuration +// +#ifdef _LAUNCHXL_F28379D + +// +// 10MHz XTAL on LaunchPad. For use with SysCtl_getClock(). +// +#define DEVICE_OSCSRC_FREQ 10000000U + +// +// Define to pass to SysCtl_setClock(). Will configure the clock as follows: +// PLLSYSCLK = 10MHz (XTAL_OSC) * 40 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) +// +#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(40) | \ + SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ + SYSCTL_PLL_ENABLE) + +// +// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the +// code below if a different clock configuration is used! +// +#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 40 * 1) / 2) + +// +// ControlCARD Configuration +// +#else + +// +// 20MHz XTAL on controlCARD. For use with SysCtl_getClock(). +// +#define DEVICE_OSCSRC_FREQ 20000000U + +// +// Define to pass to SysCtl_setClock(). Will configure the clock as follows: +// PLLSYSCLK = 20MHz (XTAL_OSC) * 20 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) +// +#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(20) | \ + SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ + SYSCTL_PLL_ENABLE) + +// +// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the +// code below if a different clock configuration is used! +// +#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 20 * 1) / 2) + +#endif + +// +// 50MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default +// low speed peripheral clock divider of 4. Update the code below if a +// different LSPCLK divider is used! +// +#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4) + +//***************************************************************************** +// +// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro +// will convert the desired delay in microseconds to the count value expected +// by the function. \b x is the number of microseconds to delay. +// +//***************************************************************************** +#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \ + (long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L) + +//***************************************************************************** +// +// Defines, Globals, and Header Includes related to Flash Support +// +//***************************************************************************** +#ifdef _FLASH +#include + +extern uint16_t RamfuncsLoadStart; +extern uint16_t RamfuncsLoadEnd; +extern uint16_t RamfuncsLoadSize; +extern uint16_t RamfuncsRunStart; +extern uint16_t RamfuncsRunEnd; +extern uint16_t RamfuncsRunSize; + +#define DEVICE_FLASH_WAITSTATES 3 + +#endif + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +extern void Device_init(void); +extern void Device_enableAllPeripherals(void); +extern void Device_initGPIO(void); +extern void Device_enableUnbondedGPIOPullupsFor176Pin(void); +extern void Device_enableUnbondedGPIOPullupsFor100Pin(void); +extern void Device_enableUnbondedGPIOPullups(void); +extern void __error__(char *filename, uint32_t line); + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/driverlib.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/driverlib.h new file mode 100644 index 0000000000..0dd941033f --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/driverlib.h @@ -0,0 +1,82 @@ +//############################################################################# +// +// FILE: driverlib.h +// +// TITLE: C28x Driverlib Header File +// +//############################################################################# +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# +#ifndef DRIVERLIB_H +#define DRIVERLIB_H + +#include "inc/hw_memmap.h" + +#include "adc.h" +#include "asysctl.h" +#include "can.h" +#include "cla.h" +#include "cmpss.h" +#include "cpu.h" +#include "cputimer.h" +#include "dac.h" +#include "dcsm.h" +#include "debug.h" +#include "dma.h" +#include "ecap.h" +#include "emif.h" +#include "epwm.h" +#include "eqep.h" +#include "flash.h" +#include "gpio.h" +#include "hrpwm.h" +#include "i2c.h" +#include "interrupt.h" +#include "mcbsp.h" +#include "memcfg.h" +#include "pin_map.h" +#include "sci.h" +#include "sdfm.h" +#include "spi.h" +#include "sysctl.h" +#include "upp.h" +#include "version.h" +#include "xbar.h" + +#endif // end of DRIVERLIB_H definition + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/stdint.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/stdint.h new file mode 100644 index 0000000000..479234292a --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/stdint.h @@ -0,0 +1,522 @@ +/*****************************************************************************/ +/* STDINT.H */ +/* */ +/* Copyright (c) 2002 Texas Instruments Incorporated */ +/* http://www.ti.com/ */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following conditions */ +/* are met: */ +/* */ +/* Redistributions of source code must retain the above copyright */ +/* notice, this list of conditions and the following disclaimer. */ +/* */ +/* Redistributions in binary form must reproduce the above copyright */ +/* notice, this list of conditions and the following disclaimer in */ +/* the documentation and/or other materials provided with the */ +/* distribution. */ +/* */ +/* Neither the name of Texas Instruments Incorporated nor the names */ +/* of its contributors may be used to endorse or promote products */ +/* derived from this software without specific prior written */ +/* permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS */ +/* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT */ +/* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR */ +/* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT */ +/* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, */ +/* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, */ +/* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY */ +/* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE */ +/* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* */ +/*****************************************************************************/ +#ifndef _STDINT_H_ +#define _STDINT_H_ + +#if __has_include() +#include +#else +/* 7.18.1.1 Exact-width integer types */ + +#if defined(__MSP430__) || defined(__TMS320C55X_PLUS_BYTE__) + typedef signed char int8_t; + typedef unsigned char uint8_t; + typedef int int16_t; + typedef unsigned int uint16_t; + typedef long int32_t; + typedef unsigned long uint32_t; +#elif defined(_TMS320C5XX) || defined(__TMS320C55X__) + typedef int int16_t; + typedef unsigned int uint16_t; + typedef long int32_t; + typedef unsigned long uint32_t; +#elif defined(_TMS320C6X) || defined(__ARM_ARCH) || defined(__ARP32__) || \ + defined(__PRU__) || defined(__FROZEN__) + typedef signed char int8_t; + typedef unsigned char uint8_t; + typedef short int16_t; + typedef unsigned short uint16_t; + typedef int int32_t; + typedef unsigned int uint32_t; +#elif defined (__TMS320C2000__) +#if defined(__TMS320C28XX_CLA__) + typedef short int16_t; + typedef unsigned short uint16_t; + typedef int int32_t; + typedef unsigned int uint32_t; +#else + typedef char int8_t; + typedef unsigned char uint8_t; + typedef int int16_t; + typedef unsigned int uint16_t; + typedef long int32_t; + typedef unsigned long uint32_t; +#endif +#endif + +#if defined(__TMS320C55X__) + typedef long long int40_t; + typedef unsigned long long uint40_t; +#elif defined(_TMS320C6X) && !defined(__C6X_MIGRATION__) + typedef __int40_t int40_t; + typedef unsigned __int40_t uint40_t; +#endif + +#if defined(__ARM_ARCH) || defined(_TMS320C6X) || defined(__ARP32__) || \ + defined(__MSP430__) || defined(__PRU__) || defined(__FROZEN__) + typedef long long int64_t; + typedef unsigned long long uint64_t; +#elif defined(__TMS320C2000__) +#if defined(__TMS320C28X__) || \ + (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) + typedef long long int64_t; + typedef unsigned long long uint64_t; +#endif +#endif + +/* 7.18.1.2 Minimum-width integer types */ + +#if defined(_TMS320C6X) || defined(__ARM_ARCH) || defined(__MSP430__) || \ + defined(__TMS320C55X_PLUS_BYTE__) || defined(__ARP32__) || \ + defined(__PRU__) || defined(__FROZEN__) + typedef int8_t int_least8_t; + typedef uint8_t uint_least8_t; +#elif defined(__TMS320C2000__) || defined(_TMS320C5XX) || defined(__TMS320C55X__) + typedef int16_t int_least8_t; + typedef uint16_t uint_least8_t; +#endif + + typedef int16_t int_least16_t; + typedef uint16_t uint_least16_t; + typedef int32_t int_least32_t; + typedef uint32_t uint_least32_t; + +#if defined(__TMS320C55X__) || \ + (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) + typedef int40_t int_least40_t; + typedef uint40_t uint_least40_t; +#endif + +#if defined(__ARM_ARCH) || defined(_TMS320C6X) || defined(__FROZEN__) || \ + defined(__ARP32__) || defined(__MSP430__) || defined(__PRU__) + typedef int64_t int_least64_t; + typedef uint64_t uint_least64_t; +#elif defined(__TMS320C2000__) +#if defined(__TMS320C28X__) || \ + (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) + typedef int64_t int_least64_t; + typedef uint64_t uint_least64_t; +#else +/* sorry, [u]int_least64_t not implemented for C27X, CLA */ +#endif +#elif defined(_TMS320C5XX) || defined(__TMS320C55X__) +/* sorry, [u]int_least64_t not implemented for C54x, C55x */ +#endif + +/* 7.18.1.3 Fastest minimum-width integer types */ + +#if defined(_TMS320C5XX) || defined(__TMS320C55X__) || defined(__MSP430__) + typedef int16_t int_fast8_t; + typedef uint16_t uint_fast8_t; + typedef int16_t int_fast16_t; + typedef uint16_t uint_fast16_t; +#elif defined(_TMS320C6X) || defined(__ARM_ARCH) || defined(__ARP32__) || \ + defined(__PRU__) || defined(__FROZEN__) + typedef int32_t int_fast8_t; + typedef uint32_t uint_fast8_t; + typedef int32_t int_fast16_t; + typedef uint32_t uint_fast16_t; +#elif defined (__TMS320C2000__) +#if defined(__TMS320C28XX_CLA__) + typedef int32_t int_fast8_t; + typedef uint32_t uint_fast8_t; + typedef int32_t int_fast16_t; + typedef uint32_t uint_fast16_t; +#else + typedef int16_t int_fast8_t; + typedef uint16_t uint_fast8_t; + typedef int16_t int_fast16_t; + typedef uint16_t uint_fast16_t; +#endif +#endif + + typedef int32_t int_fast32_t; + typedef uint32_t uint_fast32_t; + +#if defined(__TMS320C55X__) || \ + (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) + typedef int40_t int_fast40_t; + typedef uint40_t uint_fast40_t; +#endif + +#if defined(__ARM_ARCH) || defined(_TMS320C6X) || defined(__FROZEN__) || \ + defined(__ARP32__) || defined(__MSP430__) || defined(__PRU__) + typedef int64_t int_fast64_t; + typedef uint64_t uint_fast64_t; +#elif defined(__TMS320C2000__) +#if defined(__TMS320C28X__) || \ + (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) + typedef int64_t int_fast64_t; + typedef uint64_t uint_fast64_t; +#else +/* sorry, [u]int_fast64_t not implemented for C27X, CLA */ +#endif +#elif defined(_TMS320C5XX) || defined(__TMS320C55X__) +/* sorry, [u]int_fast64_t not implemented for C54x, C55x */ +#endif + +/* 7.18.1.4 Integer types capable of holding object pointers */ +#if defined(_TMS320C5XX) || defined(__TMS320C55X__) || \ + (defined(__MSP430__) && defined(__LARGE_CODE_MODEL__)) || \ + defined(__FROZEN__) + typedef long intptr_t; + typedef unsigned long uintptr_t; +#elif defined(_TMS320C6X) || defined(__ARM_ARCH) || defined(__MSP430__) || \ + defined(__ARP32__) || defined(__PRU__) + typedef int intptr_t; + typedef unsigned int uintptr_t; +#elif defined(__TMS320C2000__) +#if defined(__TMS320C28XX_CLA__) + typedef short intptr_t; + typedef unsigned short uintptr_t; +#else + typedef long intptr_t; + typedef unsigned long uintptr_t; +#endif +#endif + +/* 7.18.1.5 Greatest-width integer types */ +#if defined(__TMS320C55X__) || defined(__ARM_ARCH) || defined(_TMS320C6X) || \ + defined(__ARP32__) || defined(__MSP430__) || defined(__PRU__) || \ + defined(__FROZEN__) + typedef long long intmax_t; + typedef unsigned long long uintmax_t; +#elif defined(_TMS320C5XX) + typedef long intmax_t; + typedef unsigned long uintmax_t; +#elif defined(__TMS320C2000__) +#if defined(__TMS320C28X__) || \ + (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) + typedef long long intmax_t; + typedef unsigned long long uintmax_t; +#else /* C27X or CLA */ + typedef long intmax_t; + typedef unsigned long uintmax_t; +#endif +#endif + +/* + According to footnotes in the 1999 C standard, "C++ implementations + should define these macros only when __STDC_LIMIT_MACROS is defined + before is included." +*/ +#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) + +/* 7.18.2 Limits of specified width integer types */ + +#if defined(_TMS320C6X) || defined(__ARM_ARCH) || defined(__MSP430__) || \ + defined(__TMS320C55X_PLUS_BYTE__) || defined(__ARP32__) || \ + defined(__PRU__) || defined(__FROZEN__) + #define INT8_MAX 0x7f + #define INT8_MIN (-INT8_MAX-1) + #define UINT8_MAX 0xff +#endif + + #define INT16_MAX 0x7fff + #define INT16_MIN (-INT16_MAX-1) + #define UINT16_MAX 0xffff + + #define INT32_MAX 0x7fffffff + #define INT32_MIN (-INT32_MAX-1) + #define UINT32_MAX 0xffffffff + +#if defined(__TMS320C55X__) || \ + (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) + #define INT40_MAX 0x7fffffffff + #define INT40_MIN (-INT40_MAX-1) + #define UINT40_MAX 0xffffffffff +#endif + +#if defined(__ARM_ARCH) || defined(_TMS320C6X) || defined(__FROZEN__) || \ + defined(__ARP32__) || defined(__MSP430__) || defined(__PRU__) + #define INT64_MAX 0x7fffffffffffffff + #define INT64_MIN (-INT64_MAX-1) + #define UINT64_MAX 0xffffffffffffffff +#elif defined(__TMS320C2000__) +#if defined(__TMS320C28X__) || \ + (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) + #define INT64_MAX 0x7fffffffffffffff + #define INT64_MIN (-INT64_MAX-1) + #define UINT64_MAX 0xffffffffffffffff +#endif +#endif + +#if defined(_TMS320C6X) || defined(__ARM_ARCH) || defined(__MSP430__) || \ + defined(__TMS320C55X_PLUS_BYTE__) || defined(__ARP32__) || \ + defined(__PRU__) || defined(__FROZEN__) + #define INT_LEAST8_MAX (INT8_MAX) + #define INT_LEAST8_MIN (INT8_MIN) + #define UINT_LEAST8_MAX (UINT8_MAX) +#elif defined(__TMS320C2000__) || defined(_TMS320C5XX) || defined(__TMS320C55X__) + #define INT_LEAST8_MAX (INT16_MAX) + #define INT_LEAST8_MIN (INT16_MIN) + #define UINT_LEAST8_MAX (UINT16_MAX) +#endif + + #define INT_LEAST16_MAX (INT16_MAX) + #define INT_LEAST16_MIN (INT16_MIN) + #define UINT_LEAST16_MAX (UINT16_MAX) + #define INT_LEAST32_MAX (INT32_MAX) + #define INT_LEAST32_MIN (INT32_MIN) + #define UINT_LEAST32_MAX (UINT32_MAX) + +#if defined(__TMS320C55X__) || \ + (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) + #define INT_LEAST40_MAX (INT40_MAX) + #define INT_LEAST40_MIN (INT40_MIN) + #define UINT_LEAST40_MAX (UINT40_MAX) +#endif + +#if defined(__ARM_ARCH) || defined(_TMS320C6X) || defined(__FROZEN__) || \ + defined(__ARP32__) || defined(__MSP430__) || defined(__PRU__) + #define INT_LEAST64_MAX (INT64_MAX) + #define INT_LEAST64_MIN (INT64_MIN) + #define UINT_LEAST64_MAX (UINT64_MAX) +#elif defined(__TMS320C2000__) +#if defined(__TMS320C28X__) || \ + (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) + #define INT_LEAST64_MAX (INT64_MAX) + #define INT_LEAST64_MIN (INT64_MIN) + #define UINT_LEAST64_MAX (UINT64_MAX) +#endif +#endif + +#if defined(_TMS320C5XX) || defined(__TMS320C55X__) + #define INT_FAST8_MAX (INT16_MAX) + #define INT_FAST8_MIN (INT16_MIN) + #define UINT_FAST8_MAX (UINT16_MAX) + #define INT_FAST16_MAX (INT16_MAX) + #define INT_FAST16_MIN (INT16_MIN) + #define UINT_FAST16_MAX (UINT16_MAX) +#elif defined(_TMS320C6X) || defined(__ARM_ARCH) || defined(__ARP32__) || \ + defined(__PRU__) || defined(__FROZEN__) + #define INT_FAST8_MAX (INT32_MAX) + #define INT_FAST8_MIN (INT32_MIN) + #define UINT_FAST8_MAX (UINT32_MAX) + #define INT_FAST16_MAX (INT32_MAX) + #define INT_FAST16_MIN (INT32_MIN) + #define UINT_FAST16_MAX (UINT32_MAX) +#elif defined(__MSP430__) + #define INT_FAST8_MAX (INT16_MAX) + #define INT_FAST8_MIN (INT16_MIN) + #define UINT_FAST8_MAX (UINT16_MAX) + #define INT_FAST16_MAX (INT16_MAX) + #define INT_FAST16_MIN (INT16_MIN) + #define UINT_FAST16_MAX (UINT16_MAX) +#elif defined (__TMS320C2000__) +#if defined(__TMS320C28XX_CLA__) + #define INT_FAST8_MAX (INT32_MAX) + #define INT_FAST8_MIN (INT32_MIN) + #define UINT_FAST8_MAX (UINT32_MAX) + #define INT_FAST16_MAX (INT32_MAX) + #define INT_FAST16_MIN (INT32_MIN) + #define UINT_FAST16_MAX (UINT32_MAX) +#else + #define INT_FAST8_MAX (INT16_MAX) + #define INT_FAST8_MIN (INT16_MIN) + #define UINT_FAST8_MAX (UINT16_MAX) + #define INT_FAST16_MAX (INT16_MAX) + #define INT_FAST16_MIN (INT16_MIN) + #define UINT_FAST16_MAX (UINT16_MAX) +#endif +#endif + + #define INT_FAST32_MAX (INT32_MAX) + #define INT_FAST32_MIN (INT32_MIN) + #define UINT_FAST32_MAX (UINT32_MAX) + +#if defined(__TMS320C55X__) || \ + (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) + #define INT_FAST40_MAX (INT40_MAX) + #define INT_FAST40_MIN (INT40_MIN) + #define UINT_FAST40_MAX (UINT40_MAX) +#endif + +#if defined(__ARM_ARCH) || defined(_TMS320C6X) || defined(__FROZEN__) || \ + defined(__ARP32__) || defined(__MSP430__) || defined(__PRU__) + #define INT_FAST64_MAX (INT64_MAX) + #define INT_FAST64_MIN (INT64_MIN) + #define UINT_FAST64_MAX (UINT64_MAX) +#elif defined(__TMS320C2000__) +#if defined(__TMS320C28X__) || \ + (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) + #define INT_FAST64_MAX (INT64_MAX) + #define INT_FAST64_MIN (INT64_MIN) + #define UINT_FAST64_MAX (UINT64_MAX) +#endif +#endif + +#if defined(__MSP430__) && !defined(__LARGE_CODE_MODEL__) + #define INTPTR_MAX (INT16_MAX) + #define INTPTR_MIN (INT16_MIN) + #define UINTPTR_MAX (UINT16_MAX) +#elif defined(__FROZEN__) + #define INTPTR_MAX (INT64_MAX) + #define INTPTR_MIN (INT64_MIN) + #define UINTPTR_MAX (UINT64_MAX) +#else + #define INTPTR_MAX (INT32_MAX) + #define INTPTR_MIN (INT32_MIN) + #define UINTPTR_MAX (UINT32_MAX) +#endif + +#if defined(__ARM_ARCH) || defined(_TMS320C6X) || defined(__FROZEN__) || \ + defined(__ARP32__) || defined(__MSP430__) || defined(__PRU__) + #define INTMAX_MIN (INT64_MIN) + #define INTMAX_MAX (INT64_MAX) + #define UINTMAX_MAX (UINT64_MAX) +#elif defined(__TMS320C55X__) + #define INTMAX_MIN (INT40_MIN) + #define INTMAX_MAX (INT40_MAX) + #define UINTMAX_MAX (UINT40_MAX) +#elif defined(_TMS320C5XX) + #define INTMAX_MIN (INT32_MIN) + #define INTMAX_MAX (INT32_MAX) + #define UINTMAX_MAX (UINT32_MAX) +#elif defined(__TMS320C2000__) +#if defined(__TMS320C28X__) || \ + (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) + #define INTMAX_MIN (INT64_MIN) + #define INTMAX_MAX (INT64_MAX) + #define UINTMAX_MAX (UINT64_MAX) +#else + #define INTMAX_MIN (INT32_MIN) + #define INTMAX_MAX (INT32_MAX) + #define UINTMAX_MAX (UINT32_MAX) +#endif +#endif + +/* 7.18.3 Limits of other integer types */ + +#if defined(_TMS320C5XX) || defined(__TMS320C55X__) || \ + (defined(__MSP430__) && !defined(__LONG_PTRDIFF_T__)) + #define PTRDIFF_MAX (INT16_MAX) + #define PTRDIFF_MIN (INT16_MIN) +#elif defined(__TMS320C2000__) || defined(__MSP430__) || \ + (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \ + defined(__ARM_ARCH) || defined(__ARP32__) || defined(__PRU__) + #define PTRDIFF_MAX (INT32_MAX) + #define PTRDIFF_MIN (INT32_MIN) +#elif defined(__FROZEN__) + #define PTRDIFF_MAX (INT64_MAX) + #define PTRDIFF_MIN (INT64_MIN) +#endif + +#if defined(_TMS320C5XX) || defined(__TMS320C55X__) || defined(__MSP430__) + #define SIG_ATOMIC_MIN (INT16_MIN) + #define SIG_ATOMIC_MAX (INT16_MAX) +#elif defined(__TMS320C2000__) || defined(_TMS320C6X) || defined(__FROZEN__) || \ + defined(__ARM_ARCH) || defined(__ARP32__) || defined(__PRU__) + #define SIG_ATOMIC_MIN (INT32_MIN) + #define SIG_ATOMIC_MAX (INT32_MAX) +#endif + +#if defined(_TMS320C5XX) || defined(__TMS320C55X__) || \ + (defined(__MSP430__) && !defined(__LONG_PTRDIFF_T__)) + #define SIZE_MAX (UINT16_MAX) +#elif defined(__TMS320C2000__) || defined(__MSP430__) || \ + (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) || \ + defined(__ARM_ARCH) || defined(__ARP32__) || defined(__PRU__) + #define SIZE_MAX (UINT32_MAX) +#elif defined(__FROZEN__) + #define SIZE_MAX (UINT64_MAX) +#endif + +#ifndef WCHAR_MAX +#if !defined(__TI_WCHAR_T_BITS__) || __TI_WCHAR_T_BITS__ == 16 +#define WCHAR_MAX 0xffffu +#else +#define WCHAR_MAX 0xffffffffu +#endif +#endif + +#ifndef WCHAR_MIN +#define WCHAR_MIN 0 +#endif + +#if defined(_TMS320C5XX) || defined(__TMS320C55X__) || defined(__MSP430__) + #define WINT_MIN (INT16_MIN) + #define WINT_MAX (INT16_MAX) +#elif defined(__TMS320C2000__) || defined(_TMS320C6X) || defined(__FROZEN__) || \ + defined(__ARM_ARCH) || defined(__ARP32__) || defined(__PRU__) + #define WINT_MIN (INT32_MIN) + #define WINT_MAX (INT32_MAX) +#endif + +/* 7.18.4.1 Macros for minimum-width integer constants */ + +/* + There is a defect report filed against the C99 standard concerning how + the (U)INTN_C macros should be implemented. Please refer to -- + http://wwwold.dkuug.dk/JTC1/SC22/WG14/www/docs/dr_209.htm + for more information. These macros are implemented according to the + suggestion given at this web site. +*/ + + #define INT8_C(value) ((int_least8_t)(value)) + #define UINT8_C(value) ((uint_least8_t)(value)) + #define INT16_C(value) ((int_least16_t)(value)) + #define UINT16_C(value) ((uint_least16_t)(value)) + #define INT32_C(value) ((int_least32_t)(value)) + #define UINT32_C(value) ((uint_least32_t)(value)) + +#if defined(__TMS320C55X__) || \ + (defined(_TMS320C6X) && !defined(__C6X_MIGRATION__)) + #define INT40_C(value) ((int_least40_t)(value)) + #define UINT40_C(value) ((uint_least40_t)(value)) +#endif + +#if defined(__ARM_ARCH) || defined(_TMS320C6X) || defined(__FROZEN__) || \ + defined(__ARP32__) || defined(__MSP430__) || defined(__PRU__) + #define INT64_C(value) ((int_least64_t)(value)) + #define UINT64_C(value) ((uint_least64_t)(value)) +#elif defined(__TMS320C2000__) +#if defined(__TMS320C28X__) || \ + (defined(__TMS320C28XX_CLA__) && defined(__TI_EABI__)) + #define INT64_C(value) ((int_least64_t)(value)) + #define UINT64_C(value) ((uint_least64_t)(value)) +#endif +#endif + +/* 7.18.4.2 Macros for greatest-width integer constants */ + + #define INTMAX_C(value) ((intmax_t)(value)) + #define UINTMAX_C(value) ((uintmax_t)(value)) + +#endif /* !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) */ +#endif +#endif /* _STDINT_H_ */ diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/usb.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/usb.h new file mode 100644 index 0000000000..1eb1f8396e --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/usb.h @@ -0,0 +1,561 @@ +//########################################################################### +// +// FILE: usb.h +// +// TITLE: Prototypes for the USB Interface Driver. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + + +#ifndef __DRIVERLIB_USB_H__ +#define __DRIVERLIB_USB_H__ + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +// The following are defines for the g_usUSBFlags variable +// +//***************************************************************************** +#define USB_VBUS_VALID 0x0001 +#define USB_ID_HOST 0x0002 +#define USB_ID_DEVICE 0x0000 +#define USB_PFLT_ACTIVE 0x0004 + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableControl() and +// USBIntDisableControl() as the ui32Flags parameter, and are returned from +// USBIntStatusControl(). +// +//***************************************************************************** +#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources +#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts +#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error +#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected +#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected +#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected +#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected +#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected +#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled +#define USB_INTCTRL_RESET 0x00000004 // Reset signaled +#define USB_INTCTRL_RESUME 0x00000002 // Resume detected +#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected +#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid +#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableEndpoint() and +// USBIntDisableEndpoint() as the ui32Flags parameter, and are returned from +// USBIntStatusEndpoint(). +// +//***************************************************************************** +#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts +#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts +#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt +#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt +#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt +#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt +#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt +#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt +#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt +#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt +#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt +#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt +#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt +#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt +#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt +#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt +#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt + +#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts +#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt + +#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts +#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt + +#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts +#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt +#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt +#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt +#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt +#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt +#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt +#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt +#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt +#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt +#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt +#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt +#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt +#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt +#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt +#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt + +#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are values that are returned from USBSpeedGet(). +// +//***************************************************************************** +#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined +#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed +#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed + +//***************************************************************************** +// +// The following are values that are returned from USBEndpointStatus(). The +// USB_HOST_* values are used when the USB controller is in host mode and the +// USB_DEV_* values are used when the USB controller is in device mode. +// +//***************************************************************************** +#define USB_HOST_IN_STATUS 0xFFFF0000 // Mask of all host IN interrupts +#define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received +#define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond +#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received +#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error + // (ISOC Mode) +#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the + // specified timeout period +#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a + // device +#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready +#define USB_HOST_OUT_STATUS 0x0000FFFF // Mask of all host OUT interrupts +#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the + // specified timeout period +#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device + // (ISOC mode) +#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received +#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a + // device +#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty +#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted +#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the + // specified timeout period +#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet +#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a + // device +#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received +#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready +#define USB_DEV_RX_PID_ERROR 0x01000000 // PID error in isochronous + // transfer +#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint +#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data +#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to + // a full FIFO +#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready +#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data + // to come +#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint +#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready +#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty +#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted +#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before + // Data End seen +#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint +#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready + +//***************************************************************************** +// +// The following are values that can be passed to USBHostEndpointConfig() and +// USBDevEndpointConfigSet() as the ui32Flags parameter. +// +//***************************************************************************** +#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled +#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled +#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled +#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0 +#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1 +#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint +#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint +#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint +#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint +#define USB_EP_MODE_MASK 0x00000300 // Mode Mask +#define USB_EP_SPEED_LOW 0x00000000 // Low Speed +#define USB_EP_SPEED_FULL 0x00001000 // Full Speed +#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint +#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint +#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint +#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint + +//***************************************************************************** +// +// The following are values that can be passed to USBHostPwrConfig() as the +// ui32Flags parameter. +// +//***************************************************************************** +#define USB_HOST_PWRFLT_LOW 0x00000010 +#define USB_HOST_PWRFLT_HIGH 0x00000030 +#define USB_HOST_PWRFLT_EP_NONE 0x00000000 +#define USB_HOST_PWRFLT_EP_TRI 0x00000140 +#define USB_HOST_PWRFLT_EP_LOW 0x00000240 +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 +#define USB_HOST_PWREN_MAN_LOW 0x00000000 +#define USB_HOST_PWREN_MAN_HIGH 0x00000001 +#define USB_HOST_PWREN_AUTOLOW 0x00000002 +#define USB_HOST_PWREN_AUTOHIGH 0x00000003 +#define USB_HOST_PWREN_FILTER 0x00010000 + +//***************************************************************************** +// +// The following are special values that can be passed to +// USBHostEndpointConfig() as the ui32NAKPollInterval parameter. +// +//***************************************************************************** +#define MAX_NAK_LIMIT 31 // Maximum NAK interval +#define DISABLE_NAK_LIMIT 0 // No NAK timeouts + +//***************************************************************************** +// +// This value specifies the maximum size of transfers on endpoint 0 as 64 +// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. +// +//***************************************************************************** +#define MAX_PACKET_SIZE_EP0 64 + +//***************************************************************************** +// +// These values are used to indicate which endpoint to access. +// +//***************************************************************************** +#define USB_EP_0 0x00000000 // Endpoint 0 +#define USB_EP_1 0x00000010 // Endpoint 1 +#define USB_EP_2 0x00000020 // Endpoint 2 +#define USB_EP_3 0x00000030 // Endpoint 3 +#define USB_EP_4 0x00000040 // Endpoint 4 +#define USB_EP_5 0x00000050 // Endpoint 5 +#define USB_EP_6 0x00000060 // Endpoint 6 +#define USB_EP_7 0x00000070 // Endpoint 7 +#define USB_EP_8 0x00000080 // Endpoint 8 +#define USB_EP_9 0x00000090 // Endpoint 9 +#define USB_EP_10 0x000000A0 // Endpoint 10 +#define USB_EP_11 0x000000B0 // Endpoint 11 +#define USB_EP_12 0x000000C0 // Endpoint 12 +#define USB_EP_13 0x000000D0 // Endpoint 13 +#define USB_EP_14 0x000000E0 // Endpoint 14 +#define USB_EP_15 0x000000F0 // Endpoint 15 +#define NUM_USB_EP 16 // Number of supported endpoints + +//***************************************************************************** +// +// These macros allow conversion between 0-based endpoint indices and the +// USB_EP_x values required when calling various USB APIs. +// +//***************************************************************************** +#define IndexToUSBEP(x) (((uint32_t)(x) << 4) & 0xFF) +#define USBEPToIndex(x) ((x) >> 4) + +//***************************************************************************** +// +// The following are values that can be passed to USBFIFOConfigSet() as the +// ui32FIFOSize parameter. +// +//***************************************************************************** +#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO +#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO +#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO +#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO +#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO +#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO +#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO +#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO +#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO +#define USB_FIFO_SZ_4096 0x00000009 // 4096 byte FIFO +#define USB_FIFO_SZ_8_DB 0x00000010 // 8 byte double buffered FIFO + // (occupying 16 bytes) +#define USB_FIFO_SZ_16_DB 0x00000011 // 16 byte double buffered FIFO + // (occupying 32 bytes) +#define USB_FIFO_SZ_32_DB 0x00000012 // 32 byte double buffered FIFO + // (occupying 64 bytes) +#define USB_FIFO_SZ_64_DB 0x00000013 // 64 byte double buffered FIFO + // (occupying 128 bytes) +#define USB_FIFO_SZ_128_DB 0x00000014 // 128 byte double buffered FIFO + // (occupying 256 bytes) +#define USB_FIFO_SZ_256_DB 0x00000015 // 256 byte double buffered FIFO + // (occupying 512 bytes) +#define USB_FIFO_SZ_512_DB 0x00000016 // 512 byte double buffered FIFO + // (occupying 1024 bytes) +#define USB_FIFO_SZ_1024_DB 0x00000017 // 1024 byte double buffered FIFO + // (occupying 2048 bytes) +#define USB_FIFO_SZ_2048_DB 0x00000018 // 2048 byte double buffered FIFO + // (occupying 4096 bytes) + +//***************************************************************************** +// +// This macro allow conversion from a FIFO size label as defined above to +// a number of bytes +// +//***************************************************************************** +#define USB_FIFO_SIZE_DB_FLAG 0x00000010 +#define USBFIFOSizeToBytes(x) ((uint32_t)8 << (x)) + +//***************************************************************************** +// +// The following are values that can be passed to USBEndpointDataSend() as the +// ui32TransType parameter. +// +//***************************************************************************** +#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction +#define USB_TRANS_IN 0x00000102 // Normal IN transaction +#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for + // endpoint 0 in device mode) +#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint + // 0) +#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint + // 0) + +//***************************************************************************** +// +// The following are values are returned by the USBModeGet function. +// +//***************************************************************************** +#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host + // mode. +#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in + // Device mode. +#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not + // set. +#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of + // the cable Session Valid. +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of + // the cable A valid. +#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set. + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern uint32_t USBDevAddrGet(uint32_t ui32Base); +extern void USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address); +extern void USBDevConnect(uint32_t ui32Base); +extern void USBDevDisconnect(uint32_t ui32Base); +extern void USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32Flags); +extern void USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, + uint32_t *pui32Flags); +extern void USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bIsLastPacket); +extern void USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Config); +extern int32_t USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size); +extern int32_t USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t ui32Size); +extern int32_t USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32TransType); +extern void USBEndpointDataToggleClear(uint32_t ui32Base, + uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Count); +extern uint32_t USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint); +extern uint32_t USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32FIFOAddress, + uint32_t *pui32FIFOSize, uint32_t ui32Flags); +extern void USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, + uint32_t ui32Flags); +extern void USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBFrameNumberGet(uint32_t ui32Base); +extern uint32_t USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags); +extern void USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, + uint32_t ui32Flags); +extern void USBHostEndpointDataAck(uint32_t ui32Base, + uint32_t ui32Endpoint); +extern void USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bDataToggle, uint32_t ui32Flags); +extern void USBHostEndpointStatusClear(uint32_t ui32Base, + uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags); +extern void USBHostPwrDisable(uint32_t ui32Base); +extern void USBHostPwrEnable(uint32_t ui32Base); +extern void USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags); +extern void USBHostPwrFaultDisable(uint32_t ui32Base); +extern void USBHostPwrFaultEnable(uint32_t ui32Base); +extern void USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBHostRequestStatus(uint32_t ui32Base); +extern void USBHostReset(uint32_t ui32Base, bool bStart); +extern void USBHostResume(uint32_t ui32Base, bool bStart); +extern uint32_t USBHostSpeedGet(uint32_t ui32Base); +extern void USBHostSuspend(uint32_t ui32Base); +extern void USBIntDisableControl(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void USBIntEnableControl(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t USBIntStatus(uint32_t ui32Base, uint32_t *ui32IntStatusEP); +extern uint32_t USBIntStatusControl(uint32_t ui32Base); +extern void USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t USBIntStatusEndpoint(uint32_t ui32Base); +extern void USBIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)); +extern void USBIntUnregister(uint32_t ui32Base); +extern void USBOTGSessionRequest(uint32_t ui32Base, bool bStart); +extern uint32_t USBModeGet(uint32_t ui32Base); +extern void USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Channel); +extern void USBHostMode(uint32_t ui32Base); +extern void USBDevMode(uint32_t ui32Base); +extern void USBOTGMode(uint32_t ui32Base); +extern void USBPHYPowerOff(uint32_t ui32Base); +extern void USBPHYPowerOn(uint32_t ui32Base); +extern uint32_t USBNumEndpointsGet(uint32_t ui32Base); + +//***************************************************************************** +// The following are values that can be passed to USBIntEnable() and +// USBIntDisable() as the ulIntFlags parameter, and are returned from +// USBIntStatus(). +//***************************************************************************** +#define USB_INT_ALL 0xFF030E0F // All Interrupt sources +#define USB_INT_STATUS 0xFF000000 // Status Interrupts +#define USB_INT_VBUS_ERR 0x80000000 // VBUS Error +#define USB_INT_SESSION_START 0x40000000 // Session Start Detected +#define USB_INT_SESSION_END 0x20000000 // Session End Detected +#define USB_INT_DISCONNECT 0x20000000 // Disconnect Detected +#define USB_INT_CONNECT 0x10000000 // Device Connect Detected +#define USB_INT_SOF 0x08000000 // Start of Frame Detected +#define USB_INT_BABBLE 0x04000000 // Babble signaled +#define USB_INT_RESET 0x04000000 // Reset signaled +#define USB_INT_RESUME 0x02000000 // Resume detected +#define USB_INT_SUSPEND 0x01000000 // Suspend detected +#define USB_INT_MODE_DETECT 0x00020000 // Mode value valid +#define USB_INT_POWER_FAULT 0x00010000 // Power Fault detected +#define USB_INT_HOST_IN 0x00000E00 // Host IN Interrupts +#define USB_INT_DEV_OUT 0x00000E00 // Device OUT Interrupts +#define USB_INT_HOST_IN_EP3 0x00000800 // Endpoint 3 Host IN Interrupt +#define USB_INT_HOST_IN_EP2 0x00000400 // Endpoint 2 Host IN Interrupt +#define USB_INT_HOST_IN_EP1 0x00000200 // Endpoint 1 Host IN Interrupt +#define USB_INT_DEV_OUT_EP3 0x00000800 // Endpoint 3 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP2 0x00000400 // Endpoint 2 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP1 0x00000200 // Endpoint 1 Device OUT Interrupt +#define USB_INT_HOST_OUT 0x0000000E // Host OUT Interrupts +#define USB_INT_DEV_IN 0x0000000E // Device IN Interrupts +#define USB_INT_HOST_OUT_EP3 0x00000008 // Endpoint 3 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP2 0x00000004 // Endpoint 2 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP1 0x00000002 // Endpoint 1 HOST_OUT Interrupt +#define USB_INT_DEV_IN_EP3 0x00000008 // Endpoint 3 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP2 0x00000004 // Endpoint 2 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP1 0x00000002 // Endpoint 1 DEV_IN Interrupt +#define USB_INT_EP0 0x00000001 // Endpoint 0 Interrupt + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // __DRIVERLIB_USB_H__ diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/include/usb_hal.h b/bsp/ti/c28x/libraries/tms320f28379d/common/include/usb_hal.h new file mode 100644 index 0000000000..d89577ebc3 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/include/usb_hal.h @@ -0,0 +1,82 @@ +//########################################################################### +// FILE: usb_hal.h +// TITLE: Compatability layer for ported software. +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __USB_HAL_H__ +#define __USB_HAL_H__ + +//***************************************************************************** +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + + + +//***************************************************************************** +//! \addtogroup c2000_specific +//! @{ +//***************************************************************************** + +extern void USBGPIOEnable(void); +extern void USBGPIODisable(void); +extern void USBDelay(uint32_t ui32Delay); + +extern void f28x_USB0DeviceIntHandler(void); +extern void f28x_USB0HostIntHandler(void); +extern void f28x_USB0DualModeIntHandler(void); +extern void f28x_USB0OTGModeIntHandler(void); + + +//***************************************************************************** +// Mark the end of the C bindings section for C++ compilers. +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +//***************************************************************************** +// Close the Doxygen group. +//! @} +//***************************************************************************** + +#endif // __F28X_USB_HAL_H__ + diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Adc.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Adc.c new file mode 100644 index 0000000000..3959c44698 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Adc.c @@ -0,0 +1,286 @@ +//########################################################################### +// +// FILE: F2837xD_Adc.c +// +// TITLE: F2837xD Adc Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// AdcSetMode - Set the resolution and signalmode for a given ADC. This will +// ensure that the correct trim is loaded. +// +// NOTE!!! There is no EALLOW/EDIS in this function! You need to make sure you +// perform the EALLOW before calling this function or else the ADC registers +// will not be configured. +// +void AdcSetMode(Uint16 adc, Uint16 resolution, Uint16 signalmode) +{ + Uint16 adcOffsetTrimOTPIndex; //index into OTP table of ADC offset trims + Uint16 adcOffsetTrim; //temporary ADC offset trim + + // + //re-populate INL trim + // + CalAdcINL(adc); + + if(0xFFFF != *((Uint16*)GetAdcOffsetTrimOTP)) + { + // + //offset trim function is programmed into OTP, so call it + // + + // + //calculate the index into OTP table of offset trims and call + //function to return the correct offset trim + // +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + adcOffsetTrimOTPIndex = 4*adc + 1*signalmode; + } + else + { + adcOffsetTrimOTPIndex = 4*adc + 1*signalmode + 2; + } + + adcOffsetTrim = (*GetAdcOffsetTrimOTP)(adcOffsetTrimOTPIndex); + } + else + { + // + //offset trim function is not populated, so set offset trim to 0 + // + adcOffsetTrim = 0; + } + + // + // Apply the resolution and signalmode to the specified ADC. + // Also apply the offset trim and, if needed, linearity trim correction. + // + switch(adc) + { + case ADC_ADCA: + { + AdcaRegs.ADCCTL2.bit.SIGNALMODE = signalmode; + AdcaRegs.ADCOFFTRIM.all = adcOffsetTrim; +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + AdcaRegs.ADCCTL2.bit.RESOLUTION = 0; + + // + //12-bit linearity trim workaround + // + AdcaRegs.ADCINLTRIM1 &= 0xFFFF0000; + AdcaRegs.ADCINLTRIM2 &= 0xFFFF0000; + AdcaRegs.ADCINLTRIM4 &= 0xFFFF0000; + AdcaRegs.ADCINLTRIM5 &= 0xFFFF0000; + } + else + { + AdcaRegs.ADCCTL2.bit.RESOLUTION = 1; + } + break; + } + case ADC_ADCB: + { + AdcbRegs.ADCCTL2.bit.SIGNALMODE = signalmode; + AdcbRegs.ADCOFFTRIM.all = adcOffsetTrim; +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + AdcbRegs.ADCCTL2.bit.RESOLUTION = 0; + + // + //12-bit linearity trim workaround + // + AdcbRegs.ADCINLTRIM1 &= 0xFFFF0000; + AdcbRegs.ADCINLTRIM2 &= 0xFFFF0000; + AdcbRegs.ADCINLTRIM4 &= 0xFFFF0000; + AdcbRegs.ADCINLTRIM5 &= 0xFFFF0000; + } + else + { + AdcbRegs.ADCCTL2.bit.RESOLUTION = 1; + } + break; + } + case ADC_ADCC: + { + AdccRegs.ADCCTL2.bit.SIGNALMODE = signalmode; + AdccRegs.ADCOFFTRIM.all = adcOffsetTrim; +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + AdccRegs.ADCCTL2.bit.RESOLUTION = 0; + // + //12-bit linearity trim workaround + // + AdccRegs.ADCINLTRIM1 &= 0xFFFF0000; + AdccRegs.ADCINLTRIM2 &= 0xFFFF0000; + AdccRegs.ADCINLTRIM4 &= 0xFFFF0000; + AdccRegs.ADCINLTRIM5 &= 0xFFFF0000; + } + else + { + AdccRegs.ADCCTL2.bit.RESOLUTION = 1; + } + break; + } + case ADC_ADCD: + { + AdcdRegs.ADCCTL2.bit.SIGNALMODE = signalmode; + AdcdRegs.ADCOFFTRIM.all = adcOffsetTrim; +#ifndef _DUAL_HEADERS + if(ADC_RESOLUTION_12BIT == resolution) +#else + if(ADC_BITRESOLUTION_12BIT == resolution) +#endif + { + AdcdRegs.ADCCTL2.bit.RESOLUTION = 0; + + // + //12-bit linearity trim workaround + // + AdcdRegs.ADCINLTRIM1 &= 0xFFFF0000; + AdcdRegs.ADCINLTRIM2 &= 0xFFFF0000; + AdcdRegs.ADCINLTRIM4 &= 0xFFFF0000; + AdcdRegs.ADCINLTRIM5 &= 0xFFFF0000; + } + else + { + AdcdRegs.ADCCTL2.bit.RESOLUTION = 1; + } + break; + } + } +} + +// +// CalAdcINL - Loads INL trim values from OTP into the trim registers of the +// specified ADC. Use only as part of AdcSetMode function, since +// linearity trim correction is needed for some modes. +// +void CalAdcINL(Uint16 adc) +{ + switch(adc) + { + case ADC_ADCA: + if(0xFFFF != *((Uint16*)CalAdcaINL)) + { + // + //trim function is programmed into OTP, so call it + // + (*CalAdcaINL)(); + } + else + { + // + //do nothing, no INL trim function populated + // + } + break; + case ADC_ADCB: + if(0xFFFF != *((Uint16*)CalAdcbINL)) + { + // + //trim function is programmed into OTP, so call it + // + (*CalAdcbINL)(); + } + else + { + // + //do nothing, no INL trim function populated + // + } + break; + case ADC_ADCC: + if(0xFFFF != *((Uint16*)CalAdccINL)) + { + // + //trim function is programmed into OTP, so call it + // + (*CalAdccINL)(); + } + else + { + // + //do nothing, no INL trim function populated + // + } + break; + case ADC_ADCD: + if(0xFFFF != *((Uint16*)CalAdcdINL)) + { + // + //trim function is programmed into OTP, so call it + // + (*CalAdcdINL)(); + } + else + { + // + //do nothing, no INL trim function populated + // + } + break; + } +} + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_CodeStartBranch.asm b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_CodeStartBranch.asm new file mode 100644 index 0000000000..cd08bf30c0 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_CodeStartBranch.asm @@ -0,0 +1,111 @@ +;//########################################################################### +;// +;// FILE: F2837xD_CodeStartBranch.asm +;// +;// TITLE: Branch for redirecting code execution after boot. +;// +;// For these examples, code_start is the first code that is executed after +;// exiting the boot ROM code. +;// +;// The codestart section in the linker cmd file is used to physically place +;// this code at the correct memory location. This section should be placed +;// at the location the BOOT ROM will re-direct the code to. For example, +;// for boot to FLASH this code will be located at 0x3f7ff6. +;// +;// In addition, the example F2837xD projects are setup such that the codegen +;// entry point is also set to the code_start label. This is done by linker +;// option -e in the project build options. When the debugger loads the code, +;// it will automatically set the PC to the "entry point" address indicated by +;// the -e linker option. In this case the debugger is simply assigning the PC, +;// it is not the same as a full reset of the device. +;// +;// The compiler may warn that the entry point for the project is other then +;// _c_init00. _c_init00 is the C environment setup and is run before +;// main() is entered. The code_start code will re-direct the execution +;// to _c_init00 and thus there is no worry and this warning can be ignored. +;// +;//########################################################################### +;// $TI Release: F2837xD Support Library v3.05.00.00 $ +;// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +;// $Copyright: +;// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + +*********************************************************************** + +WD_DISABLE .set 0 ;set to 1 to disable WD, else set to 0 + + .ref _c_int00 + .global code_start + +*********************************************************************** +* Function: codestart section +* +* Description: Branch to code starting point +*********************************************************************** + + .sect "codestart" + +code_start: + .if WD_DISABLE == 1 + LB wd_disable ;Branch to watchdog disable code + .else + LB _c_int00 ;Branch to start of boot._asm in RTS library + .endif + +;end codestart section + +*********************************************************************** +* Function: wd_disable +* +* Description: Disables the watchdog timer +*********************************************************************** + .if WD_DISABLE == 1 + + .text +wd_disable: + SETC OBJMODE ;Set OBJMODE for 28x object code + EALLOW ;Enable EALLOW protected register access + MOVZ DP, #7029h>>6 ;Set data page for WDCR register + MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD + EDIS ;Disable EALLOW protected register access + LB _c_int00 ;Branch to start of boot._asm in RTS library + + .endif + +;end wd_disable + + .end + +;// +;// End of file. +;// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_CpuTimers.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_CpuTimers.c new file mode 100644 index 0000000000..1a0877ea6d --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_CpuTimers.c @@ -0,0 +1,181 @@ +//########################################################################### +// +// FILE: F2837xD_CpuTimers.c +// +// TITLE: CPU 32-bit Timers Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// Globals +// +struct CPUTIMER_VARS CpuTimer0; +struct CPUTIMER_VARS CpuTimer1; +struct CPUTIMER_VARS CpuTimer2; + +// +// InitCpuTimers - This function initializes all three CPU timers to a known +// state. +// +void InitCpuTimers(void) +{ + // + // CPU Timer 0 + // Initialize address pointers to respective timer registers: + // + CpuTimer0.RegsAddr = &CpuTimer0Regs; + + // + // Initialize timer period to maximum: + // + CpuTimer0Regs.PRD.all = 0xFFFFFFFF; + + // + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + // + CpuTimer0Regs.TPR.all = 0; + CpuTimer0Regs.TPRH.all = 0; + + // + // Make sure timer is stopped: + // + CpuTimer0Regs.TCR.bit.TSS = 1; + + // + // Reload all counter register with period value: + // + CpuTimer0Regs.TCR.bit.TRB = 1; + + // + // Reset interrupt counters: + // + CpuTimer0.InterruptCount = 0; + + // + // Initialize address pointers to respective timer registers: + // + CpuTimer1.RegsAddr = &CpuTimer1Regs; + CpuTimer2.RegsAddr = &CpuTimer2Regs; + + // + // Initialize timer period to maximum: + // + CpuTimer1Regs.PRD.all = 0xFFFFFFFF; + CpuTimer2Regs.PRD.all = 0xFFFFFFFF; + + // + // Initialize pre-scale counter to divide by 1 (SYSCLKOUT): + // + CpuTimer1Regs.TPR.all = 0; + CpuTimer1Regs.TPRH.all = 0; + CpuTimer2Regs.TPR.all = 0; + CpuTimer2Regs.TPRH.all = 0; + + // + // Make sure timers are stopped: + // + CpuTimer1Regs.TCR.bit.TSS = 1; + CpuTimer2Regs.TCR.bit.TSS = 1; + + // + // Reload all counter register with period value: + // + CpuTimer1Regs.TCR.bit.TRB = 1; + CpuTimer2Regs.TCR.bit.TRB = 1; + + // + // Reset interrupt counters: + // + CpuTimer1.InterruptCount = 0; + CpuTimer2.InterruptCount = 0; +} + +// +// ConfigCpuTimer - This function initializes the selected timer to the period +// specified by the "Freq" and "Period" parameters. The "Freq" +// is entered as "MHz" and the period in "uSeconds". The timer +// is held in the stopped state after configuration. +// +void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period) +{ + Uint32 temp; + + // + // Initialize timer period: + // + Timer->CPUFreqInMHz = Freq; + Timer->PeriodInUSec = Period; + temp = (long) (Freq * Period); + + // + // Counter decrements PRD+1 times each period + // + Timer->RegsAddr->PRD.all = temp - 1; + + // + // Set pre-scale counter to divide by 1 (SYSCLKOUT): + // + Timer->RegsAddr->TPR.all = 0; + Timer->RegsAddr->TPRH.all = 0; + + // + // Initialize timer control register: + // + Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart + // Timer + Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer + Timer->RegsAddr->TCR.bit.SOFT = 0; + Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled + Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer + // Interrupt + + // + // Reset interrupt counter: + // + Timer->InterruptCount = 0; +} + + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_DBGIER.asm b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_DBGIER.asm new file mode 100644 index 0000000000..951fe6a28a --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_DBGIER.asm @@ -0,0 +1,60 @@ +;//########################################################################### +;// +;// FILE: F2837xD_DBGIER.asm +;// +;// TITLE: Set the DBGIER register +;// +;// DESCRIPTION: +;// +;// Function to set the DBGIER register (for realtime emulation). +;// Function Prototype: void SetDBGIER(Uint16) +;// Usage: SetDBGIER(value); +;// Input Parameters: Uint16 value = value to put in DBGIER register. +;// Return Value: none +;// +;//########################################################################### +;// $TI Release: F2837xD Support Library v3.05.00.00 $ +;// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +;// $Copyright: +;// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + .global _SetDBGIER + .text + +_SetDBGIER: + MOV *SP++,AL + POP DBGIER + LRETR + +;// +;// End of file +;// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_DefaultISR.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_DefaultISR.c new file mode 100644 index 0000000000..bd589343b6 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_DefaultISR.c @@ -0,0 +1,3138 @@ +//########################################################################### +// +// FILE: F2837xD_DefaultISR.c +// +// TITLE: F2837xD Device Default Interrupt Service Routines +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// CPU Timer 1 Interrupt +// +interrupt void TIMER1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// CPU Timer 2 Interrupt +// +interrupt void TIMER2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Datalogging Interrupt +// +interrupt void DATALOG_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// RTOS Interrupt +// +interrupt void RTOS_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Emulation Interrupt +// +interrupt void EMU_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Non-Maskable Interrupt +// +interrupt void NMI_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Illegal Operation Trap +// +interrupt void ILLEGAL_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 1 +// +interrupt void USER1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 2 +// +interrupt void USER2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 3 +// +interrupt void USER3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 4 +// +interrupt void USER4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 5 +// +interrupt void USER5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 6 +// +interrupt void USER6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 7 +// +interrupt void USER7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 8 +// +interrupt void USER8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 9 +// +interrupt void USER9_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 10 +// +interrupt void USER10_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 11 +// +interrupt void USER11_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// User Defined Trap 12 +// +interrupt void USER12_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.1 - ADCA Interrupt 1 +// +interrupt void ADCA1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.2 - ADCB Interrupt 1 +// +interrupt void ADCB1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.3 - ADCC Interrupt 1 +// +interrupt void ADCC1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.4 - XINT1 Interrupt +// +interrupt void XINT1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.5 - XINT2 Interrupt +// +interrupt void XINT2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.6 - ADCD Interrupt 1 +// +interrupt void ADCD1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.7 - Timer 0 Interrupt +// +interrupt void TIMER0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.8 - Standby and Halt Wakeup Interrupt +// +interrupt void WAKE_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.1 - ePWM1 Trip Zone Interrupt +// +interrupt void EPWM1_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.2 - ePWM2 Trip Zone Interrupt +// +interrupt void EPWM2_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.3 - ePWM3 Trip Zone Interrupt +// +interrupt void EPWM3_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.4 - ePWM4 Trip Zone Interrupt +// +interrupt void EPWM4_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.5 - ePWM5 Trip Zone Interrupt +// +interrupt void EPWM5_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.6 - ePWM6 Trip Zone Interrupt +// +interrupt void EPWM6_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.7 - ePWM7 Trip Zone Interrupt +// +interrupt void EPWM7_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.8 - ePWM8 Trip Zone Interrupt +// +interrupt void EPWM8_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.1 - ePWM1 Interrupt +// +interrupt void EPWM1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.2 - ePWM2 Interrupt +// +interrupt void EPWM2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.3 - ePWM3 Interrupt +// +interrupt void EPWM3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.4 - ePWM4 Interrupt +// +interrupt void EPWM4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.5 - ePWM5 Interrupt +// +interrupt void EPWM5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.6 - ePWM6 Interrupt +// +interrupt void EPWM6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.7 - ePWM7 Interrupt +// +interrupt void EPWM7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.8 - ePWM8 Interrupt +// +interrupt void EPWM8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.1 - eCAP1 Interrupt +// +interrupt void ECAP1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.2 - eCAP2 Interrupt +// +interrupt void ECAP2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.3 - eCAP3 Interrupt +// +interrupt void ECAP3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.4 - eCAP4 Interrupt +// +interrupt void ECAP4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.5 - eCAP5 Interrupt +// +interrupt void ECAP5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 4.6 - eCAP6 Interrupt +// +interrupt void ECAP6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP4; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.1 - eQEP1 Interrupt +// +interrupt void EQEP1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.2 - eQEP2 Interrupt +// +interrupt void EQEP2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.3 - eQEP3 Interrupt +// +interrupt void EQEP3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.1 - SPIA Receive Interrupt +// +interrupt void SPIA_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.2 - SPIA Transmit Interrupt +// +interrupt void SPIA_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.3 - SPIB Receive Interrupt +// +interrupt void SPIB_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.4 - SPIB Transmit Interrupt +// +interrupt void SPIB_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.5 - McBSPA Receive Interrupt +// +interrupt void MCBSPA_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.6 - McBSPA Transmit Interrupt +// +interrupt void MCBSPA_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.7 - McBSPB Receive Interrupt +// +interrupt void MCBSPB_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.8 - McBSPB Transmit Interrupt +// +interrupt void MCBSPB_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.1 - DMA Channel 1 Interrupt +// +interrupt void DMA_CH1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.2 - DMA Channel 2 Interrupt +// +interrupt void DMA_CH2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.3 - DMA Channel 3 Interrupt +// +interrupt void DMA_CH3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.4 - DMA Channel 4 Interrupt +// +interrupt void DMA_CH4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.5 - DMA Channel 5 Interrupt +// +interrupt void DMA_CH5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 7.6 - DMA Channel 6 Interrupt +// +interrupt void DMA_CH6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.1 - I2CA Interrupt 1 +// +interrupt void I2CA_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.2 - I2CA Interrupt 2 +// +interrupt void I2CA_FIFO_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.3 - I2CB Interrupt 1 +// +interrupt void I2CB_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.4 - I2CB Interrupt 2 +// +interrupt void I2CB_FIFO_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.5 - SCIC Receive Interrupt +// +interrupt void SCIC_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.6 - SCIC Transmit Interrupt +// +interrupt void SCIC_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.7 - SCID Receive Interrupt +// +interrupt void SCID_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.8 - SCID Transmit Interrupt +// +interrupt void SCID_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.1 - SCIA Receive Interrupt +// +interrupt void SCIA_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.2 - SCIA Transmit Interrupt +// +interrupt void SCIA_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.3 - SCIB Receive Interrupt +// +interrupt void SCIB_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.4 - SCIB Transmit Interrupt +// +interrupt void SCIB_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.5 - CANA Interrupt 0 +// +interrupt void CANA0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.6 - CANA Interrupt 1 +// +interrupt void CANA1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.7 - CANB Interrupt 0 +// +interrupt void CANB0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.8 - CANB Interrupt 1 +// +interrupt void CANB1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.1 - ADCA Event Interrupt +// +interrupt void ADCA_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.2 - ADCA Interrupt 2 +// +interrupt void ADCA2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.3 - ADCA Interrupt 3 +// +interrupt void ADCA3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.4 - ADCA Interrupt 4 +// +interrupt void ADCA4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.5 - ADCB Event Interrupt +// +interrupt void ADCB_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.6 - ADCB Interrupt 2 +// +interrupt void ADCB2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.7 - ADCB Interrupt 3 +// +interrupt void ADCB3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.8 - ADCB Interrupt 4 +// +interrupt void ADCB4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.1 - CLA1 Interrupt 1 +// +interrupt void CLA1_1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.2 - CLA1 Interrupt 2 +// +interrupt void CLA1_2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.3 - CLA1 Interrupt 3 +// +interrupt void CLA1_3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.4 - CLA1 Interrupt 4 +// +interrupt void CLA1_4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.5 - CLA1 Interrupt 5 +// +interrupt void CLA1_5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.6 - CLA1 Interrupt 6 +// +interrupt void CLA1_6_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.7 - CLA1 Interrupt 7 +// +interrupt void CLA1_7_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 11.8 - CLA1 Interrupt 8 +// +interrupt void CLA1_8_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP11; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.1 - XINT3 Interrupt +// +interrupt void XINT3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.2 - XINT4 Interrupt +// +interrupt void XINT4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.3 - XINT5 Interrupt +// +interrupt void XINT5_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.6 - VCU Interrupt +// +interrupt void VCU_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.7 - FPU Overflow Interrupt +// +interrupt void FPU_OVERFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.8 - FPU Underflow Interrupt +// +interrupt void FPU_UNDERFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.13 - IPC Interrupt 0 +// +interrupt void IPC0_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.14 - IPC Interrupt 1 +// +interrupt void IPC1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.15 - IPC Interrupt 2 +// +interrupt void IPC2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 1.16 - IPC Interrupt 3 +// +interrupt void IPC3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.9 - ePWM9 Trip Zone Interrupt +// +interrupt void EPWM9_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.10 - ePWM10 Trip Zone Interrupt +// +interrupt void EPWM10_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.11 - ePWM11 Trip Zone Interrupt +// +interrupt void EPWM11_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 2.12 - ePWM12 Trip Zone Interrupt +// +interrupt void EPWM12_TZ_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP2; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.9 - ePWM9 Interrupt +// +interrupt void EPWM9_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.10 - ePWM10 Interrupt +// +interrupt void EPWM10_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.11 - ePWM11 Interrupt +// +interrupt void EPWM11_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 3.12 - ePWM12 Interrupt +// +interrupt void EPWM12_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP3; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.9 - SD1 Interrupt +// +interrupt void SD1_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 5.10 - SD2 Interrupt +// +interrupt void SD2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP5; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.9 - SPIC Receive Interrupt +// +interrupt void SPIC_RX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 6.10 - SPIC Transmit Interrupt +// +interrupt void SPIC_TX_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP6; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 8.15 - uPPA Interrupt +// +interrupt void UPPA_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP8; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 9.15 - USBA Interrupt +// +interrupt void USBA_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP9; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.9 - ADCC Event Interrupt +// +interrupt void ADCC_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.10 - ADCC Interrupt 2 +// +interrupt void ADCC2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.11 - ADCC Interrupt 3 +// +interrupt void ADCC3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.12 - ADCC Interrupt 4 +// +interrupt void ADCC4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.13 - ADCD Event Interrupt +// +interrupt void ADCD_EVT_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.14 - ADCD Interrupt 2 +// +interrupt void ADCD2_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.15 - ADCD Interrupt 3 +// +interrupt void ADCD3_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 10.16 - ADCD Interrupt 4 +// +interrupt void ADCD4_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP10; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.9 - EMIF Error Interrupt +// +interrupt void EMIF_ERROR_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.10 - RAM Correctable Error Interrupt +// +interrupt void RAM_CORRECTABLE_ERROR_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.11 - Flash Correctable Error Interrupt +// +interrupt void FLASH_CORRECTABLE_ERROR_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.12 - RAM Access Violation Interrupt +// +interrupt void RAM_ACCESS_VIOLATION_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.13 - System PLL Slip Interrupt +// +interrupt void SYS_PLL_SLIP_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.14 - Auxiliary PLL Slip Interrupt +// +interrupt void AUX_PLL_SLIP_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.15 - CLA Overflow Interrupt +// +interrupt void CLA_OVERFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// 12.16 - CLA Underflow Interrupt +// +interrupt void CLA_UNDERFLOW_ISR(void) +{ + // + // Insert ISR Code here + // + + // + // To receive more interrupts from this PIE group, + // acknowledge this interrupt. + // PieCtrlRegs.PIEACK.all = PIEACK_GROUP12; + // + + // + // Next two lines for debug only to halt the processor here + // Remove after inserting ISR Code + // + asm (" ESTOP0"); + for(;;); +} + +// +// Catch-all Default ISRs: +// + +// +// PIE_RESERVED_ISR - Reserved ISR +// +interrupt void PIE_RESERVED_ISR(void) +{ + asm (" ESTOP0"); + for(;;); +} + +// +// EMPTY_ISR - Only does a return +// +interrupt void EMPTY_ISR(void) +{ + +} + +// +// NOTUSED_ISR - Unused ISR +// +interrupt void NOTUSED_ISR(void) +{ + asm (" ESTOP0"); + for(;;); +} + diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Dma.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Dma.c new file mode 100644 index 0000000000..ca5593c851 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Dma.c @@ -0,0 +1,1100 @@ +//########################################################################### +// +// FILE: F2837xD_DMA.c +// +// TITLE: F2837xD Device DMA Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// DMAInitialize - This function initializes the DMA to a known state. +// +void DMAInitialize(void) +{ + EALLOW; + + // + // Perform a hard reset on DMA + // + DmaRegs.DMACTRL.bit.HARDRESET = 1; + __asm (" nop"); // one NOP required after HARDRESET + + // + // Allow DMA to run free on emulation suspend + // + DmaRegs.DEBUGCTRL.bit.FREE = 1; + + EDIS; +} + +// +// DMACH1AddrConfig - DMA Channel 1 Address Configuration +// +void DMACH1AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to + // beginning of + // source buffer + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to + // beginning of + // destination buffer + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH1BurstConfig - DMA Channel 1 Burst size configuration +// +void DMACH1BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH1.BURST_SIZE.all = bsize; // Number of words(X-1) + // x-ferred in a burst. + DmaRegs.CH1.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH1.DST_BURST_STEP = desbstep; // Increment dest addr between + // each word x-ferred. + + EDIS; +} + +// +// DMACH1TransferConfig - DMA Channel 1 Transfer size configuration +// +void DMACH1TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH1.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH1.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored + // when WRAP occurs. + DmaRegs.CH1.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored + // when WRAP occurs. + + EDIS; +} + +// +// DMACH1WrapConfig - DMA Channel 1 Wrap size configuration +// +void DMACH1WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH1.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH1.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH1.DST_WRAP_SIZE = deswsize; // Wrap destination address after + // N bursts. + DmaRegs.CH1.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH1ModeConfig - DMA Channel 1 Mode configuration +// +void DMACH1ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH1 = persel; + DmaRegs.CH1.MODE.bit.PERINTSEL = 1; + DmaRegs.CH1.MODE.bit.PERINTE = perinte; + DmaRegs.CH1.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH1.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH1.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH1.MODE.bit.DATASIZE = datasize; + DmaRegs.CH1.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH1.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: interrupt and sync error flags + // + DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH1 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx1 = 1; + + EDIS; +} + +// +// StartDMACH1 - This function starts DMA Channel 1. +// +void StartDMACH1(void) +{ + EALLOW; + DmaRegs.CH1.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH2AddrConfig - DMA Channel 2 Address Configuration +// +void DMACH2AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to + // beginning of + // source buffer. + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH2BurstConfig - DMA Channel 2 Burst size configuration +// +void DMACH2BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH2.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH2.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH2.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH2TransferConfig - DMA Channel 2 Transfer size Configuration +// +void DMACH2TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH2.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH2.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH2.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH2WrapConfig - DMA Channel 2 Wrap size configuration +// +void DMACH2WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH2.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH2.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH2.DST_WRAP_SIZE = deswsize; // Wrap destination address after + // N bursts. + DmaRegs.CH2.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH2ModeConfig - DMA Channel 2 Mode configuration +// +void DMACH2ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH2 = persel; + DmaRegs.CH2.MODE.bit.PERINTSEL = 2; + DmaRegs.CH2.MODE.bit.PERINTE = perinte; + DmaRegs.CH2.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH2.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH2.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH2.MODE.bit.DATASIZE = datasize; + DmaRegs.CH2.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH2.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: Interrupt flags and sync error flags + // + DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH2 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx2 = 1; + + EDIS; +} + +// +// StartDMACH2 - This function starts DMA Channel 2. +// +void StartDMACH2(void) +{ + EALLOW; + DmaRegs.CH2.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH3AddrConfig - DMA Channel 3 Address configuration +// +void DMACH3AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer. + DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH3BurstConfig - DMA Channel 3 burst size configuration +// +void DMACH3BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH3.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH3.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH3.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH3TransferConfig - DMA channel 3 transfer size configuration +// +void DMACH3TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH3.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH3.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH3.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH3WrapConfig - DMA Channel 3 wrap size configuration +// +void DMACH3WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH3.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH3.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH3.DST_WRAP_SIZE = deswsize; // Wrap destination address after N + // bursts. + DmaRegs.CH3.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH3ModeConfig - DMA Channel 3 mode configuration +// +void DMACH3ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH3 = persel; + DmaRegs.CH3.MODE.bit.PERINTSEL = 3; + DmaRegs.CH3.MODE.bit.PERINTE = perinte; + DmaRegs.CH3.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH3.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH3.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH3.MODE.bit.DATASIZE = datasize; + DmaRegs.CH3.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH3.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: interrupt flags and sync error flags + // + DmaRegs.CH3.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH3.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH3 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx3 = 1; + + EDIS; +} + +// +// StartDMACH3 - This function starts DMA Channel 3. +// +void StartDMACH3(void) +{ + EALLOW; + DmaRegs.CH3.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH4AddrConfig - DMA Channel 4 address configuration +// +void DMACH4AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer. + DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH4BurstConfig - DMA Channel 4 burst size configuration +// +void DMACH4BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH4.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH4.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH4.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH4TransferConfig - DMA channel 4 transfer size configuration +// +void DMACH4TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH4.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH4.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH4.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH4WrapConfig - DMA channel 4 wrap size configuration +// +void DMACH4WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH4.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH4.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH4.DST_WRAP_SIZE = deswsize; // Wrap destination address after + // N bursts. + DmaRegs.CH4.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH4ModeConfig - DMA Channel 4 mode configuration +// +void DMACH4ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL1.bit.CH4 = persel; + DmaRegs.CH4.MODE.bit.PERINTSEL = 4; + DmaRegs.CH4.MODE.bit.PERINTE = perinte; + DmaRegs.CH4.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH4.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH4.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH4.MODE.bit.DATASIZE = datasize; + DmaRegs.CH4.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH4.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: Interrupt flags and sync error flags + // + DmaRegs.CH4.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH4.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH4 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx4 = 1; + + EDIS; +} + +// +// StartDMACH4 - This function starts DMA Channel 4. +// +void StartDMACH4(void) +{ + EALLOW; + DmaRegs.CH4.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH5AddrConfig - DMA channel 5 address configuration +// +void DMACH5AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH5BurstConfig - DMA Channel 5 burst size configuration +// +void DMACH5BurstConfig(Uint16 bsize, int16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH5.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH5.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH5.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH5TransferConfig - DMA channel 5 transfer size configuration +// +void DMACH5TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH5.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH5.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH5.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH5WrapConfig - DMA Channel 5 wrap size configuration +// +void DMACH5WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH5.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH5.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH5.DST_WRAP_SIZE = deswsize; // Wrap destination address after + // N bursts. + DmaRegs.CH5.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH5ModeConfig - DMA Channel 5 mode configuration +// +void DMACH5ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH5 = persel; + DmaRegs.CH5.MODE.bit.PERINTSEL = 5; + DmaRegs.CH5.MODE.bit.PERINTE = perinte; + DmaRegs.CH5.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH5.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH5.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH5.MODE.bit.DATASIZE = datasize; + DmaRegs.CH5.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH5.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: Interrupt flags and sync error flags + // + DmaRegs.CH5.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH5.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH5 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx5 = 1; + + EDIS; +} + +// +// StartDMACH5 - This function starts DMA Channel 5. +// +void StartDMACH5(void) +{ + EALLOW; + DmaRegs.CH5.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// DMACH6AddrConfig - DMA Channel 6 address configuration +// +void DMACH6AddrConfig(volatile Uint16 *DMA_Dest,volatile Uint16 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer. + DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH6BurstConfig - DMA Channel 6 burst size configuration +// +void DMACH6BurstConfig(Uint16 bsize,Uint16 srcbstep, int16 desbstep) +{ + EALLOW; + + // + // Set up BURST registers: + // + DmaRegs.CH6.BURST_SIZE.all = bsize; // Number of words(X-1) x-ferred in + // a burst. + DmaRegs.CH6.SRC_BURST_STEP = srcbstep; // Increment source addr between + // each word x-ferred. + DmaRegs.CH6.DST_BURST_STEP = desbstep; // Increment dest addr between each + // word x-ferred. + + EDIS; +} + +// +// DMACH6TransferConfig - DMA channel 6 transfer size configuration +// +void DMACH6TransferConfig(Uint16 tsize, int16 srctstep, int16 deststep) +{ + EALLOW; + + // + // Set up TRANSFER registers: + // + DmaRegs.CH6.TRANSFER_SIZE = tsize; // Number of bursts per transfer, + // DMA interrupt will occur after + // completed transfer. + DmaRegs.CH6.SRC_TRANSFER_STEP = srctstep; // TRANSFER_STEP is ignored when + // WRAP occurs. + DmaRegs.CH6.DST_TRANSFER_STEP = deststep; // TRANSFER_STEP is ignored when + // WRAP occurs. + + EDIS; +} + +// +// DMACH6WrapConfig - DMA Channel 6 wrap size configuration +// +void DMACH6WrapConfig(Uint16 srcwsize, int16 srcwstep, Uint16 deswsize, + int16 deswstep) +{ + EALLOW; + + // + // Set up WRAP registers: + // + DmaRegs.CH6.SRC_WRAP_SIZE = srcwsize; // Wrap source address after N bursts + DmaRegs.CH6.SRC_WRAP_STEP = srcwstep; // Step for source wrap + + DmaRegs.CH6.DST_WRAP_SIZE = deswsize; // Wrap destination address after N + // bursts. + DmaRegs.CH6.DST_WRAP_STEP = deswstep; // Step for destination wrap + + EDIS; +} + +// +// DMACH6ModeConfig - DMA Channel 6 mode configuration +// +void DMACH6ModeConfig(Uint16 persel, Uint16 perinte, Uint16 oneshot, + Uint16 cont, Uint16 synce, Uint16 syncsel, + Uint16 ovrinte, Uint16 datasize, Uint16 chintmode, + Uint16 chinte) +{ + EALLOW; + + // + // Set up MODE Register: + // persel - Source select + // PERINTSEL - Should be hard coded to channel, above now selects source + // PERINTE - Peripheral interrupt enable + // ONESHOT - Oneshot enable + // CONTINUOUS - Continuous enable + // OVRINTE - Enable/disable the overflow interrupt + // DATASIZE - 16-bit/32-bit data size transfers + // CHINTMODE - Generate interrupt to CPU at beginning/end of transfer + // CHINTE - Channel Interrupt to CPU enable + // + DmaClaSrcSelRegs.DMACHSRCSEL2.bit.CH6 = persel; + DmaRegs.CH6.MODE.bit.PERINTSEL = 6; + DmaRegs.CH6.MODE.bit.PERINTE = perinte; + DmaRegs.CH6.MODE.bit.ONESHOT = oneshot; + DmaRegs.CH6.MODE.bit.CONTINUOUS = cont; + DmaRegs.CH6.MODE.bit.OVRINTE = ovrinte; + DmaRegs.CH6.MODE.bit.DATASIZE = datasize; + DmaRegs.CH6.MODE.bit.CHINTMODE = chintmode; + DmaRegs.CH6.MODE.bit.CHINTE = chinte; + + // + // Clear any spurious flags: Interrupt flags and sync error flags + // + DmaRegs.CH6.CONTROL.bit.PERINTCLR = 1; + DmaRegs.CH6.CONTROL.bit.ERRCLR = 1; + + // + // Initialize PIE vector for CPU interrupt: + // Enable DMA CH6 interrupt in PIE + // + PieCtrlRegs.PIEIER7.bit.INTx6 = 1; + + EDIS; +} + +// +// StartDMACH6 - This function starts DMA Channel 6. +// +void StartDMACH6(void) +{ + EALLOW; + DmaRegs.CH6.CONTROL.bit.RUN = 1; + EDIS; +} + +// +// NOTE: +// Following functions are required for EMIF as the address is out of +// 22bit range +// + +// +// DMACH1AddrConfig32bit - DMA Channel 1 address configuration for 32bit +// +void DMACH1AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH2AddrConfig32bit - DMA Channel 2 address configuration for 32bit +// +void DMACH2AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH2.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH3AddrConfig32bit - DMA Channel 3 address configuration for 32bit +// +void DMACH3AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH3.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH3.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH3.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer. + DmaRegs.CH3.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH4AddrConfig32bit - DMA Channel 4 address configuration for 32bit +// +void DMACH4AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH4.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH4.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH4.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH4.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH5AddrConfig32bit - DMA Channel 5 address configuration for 32bit +// +void DMACH5AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH5.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH5.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH5.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH5.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// DMACH6AddrConfig32bit - DMA Channel 6 address configuration for 32bit +// +void DMACH6AddrConfig32bit(volatile Uint32 *DMA_Dest, + volatile Uint32 *DMA_Source) +{ + EALLOW; + + // + // Set up SOURCE address: + // + DmaRegs.CH6.SRC_BEG_ADDR_SHADOW = (Uint32)DMA_Source; // Point to beginning + // of source buffer + DmaRegs.CH6.SRC_ADDR_SHADOW = (Uint32)DMA_Source; + + // + // Set up DESTINATION address: + // + DmaRegs.CH6.DST_BEG_ADDR_SHADOW = (Uint32)DMA_Dest; // Point to beginning + // of destination + // buffer + DmaRegs.CH6.DST_ADDR_SHADOW = (Uint32)DMA_Dest; + + EDIS; +} + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_ECap.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_ECap.c new file mode 100644 index 0000000000..d9dcfab62e --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_ECap.c @@ -0,0 +1,147 @@ +//########################################################################### +// +// FILE: F2837xD_ECap.c +// +// TITLE: F2837xD eCAP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// InitECap - This function initializes the eCAP(s) to a known state. +// +void InitECap(void) +{ + // Initialize eCAP1/2/3/4/5/6 + + //tbd... +} + +// +// InitECapGpio - This function initializes GPIO pins to function as ECAP pins +// Each GPIO pin can be configured as a GPIO pin or up to 3 +// different peripheral functional pins. By default all pins +// come up as GPIO inputs after reset. +// Caution: +// For each eCAP peripheral +// Only one GPIO pin should be enabled for ECAP operation. +// Comment out other unwanted lines. +// +void InitECapGpio() +{ +} + +// +// InitECap1Gpio - Initialize ECAP1 GPIOs +// +void InitECap1Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT7SELECT = pin; // Set eCAP1 source to GPIO-pin + EDIS; +} + +// +// InitECap2Gpio - Initialize ECAP2 GPIOs +// +void InitECap2Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT8SELECT = pin; // Set eCAP2 source to GPIO-pin + EDIS; +} + +// +// InitECap3Gpio - Initialize ECAP3 GPIOs +// +void InitECap3Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT9SELECT = pin; // Set eCAP3 source to GPIO-pin + EDIS; +} + +// +// InitECap4Gpio - Initialize ECAP4 GPIOs +// +void InitECap4Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT10SELECT = pin; // Set eCAP4 source to GPIO-pin + EDIS; +} + +// +// InitECap5Gpio - Initialize ECAP5 GPIOs +// +void InitECap5Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT11SELECT = pin; // Set eCAP5 source to GPIO-pin + EDIS; +} + +// +// InitECap6Gpio - Initialize ECAP6 GPIOs +// +void InitECap6Gpio(Uint16 pin) +{ + EALLOW; + InputXbarRegs.INPUT12SELECT = pin; // Set eCAP6 source to GPIO-pin + EDIS; +} + +// +// InitAPwm1Gpio - Initialize EPWM1 GPIOs +// +void InitAPwm1Gpio() +{ + EALLOW; + OutputXbarRegs.OUTPUT3MUX0TO15CFG.bit.MUX0 = 3; // Select ECAP1.OUT on Mux0 + OutputXbarRegs.OUTPUT3MUXENABLE.bit.MUX0 = 1; // Enable MUX0 for ECAP1.OUT + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 3; // Select OUTPUTXBAR3 on GPIO5 + EDIS; +} + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_EPwm.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_EPwm.c new file mode 100644 index 0000000000..2581fe46c9 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_EPwm.c @@ -0,0 +1,436 @@ +//########################################################################### +// +// FILE: F2837xD_EPwm.c +// +// TITLE: F2837xD EPwm Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// InitEPwmGpio - Initialize all EPWM modules' GPIOs +// +void InitEPwmGpio(void) +{ + InitEPwm1Gpio(); + InitEPwm2Gpio(); + InitEPwm3Gpio(); + InitEPwm4Gpio(); + InitEPwm5Gpio(); + InitEPwm6Gpio(); + InitEPwm7Gpio(); + InitEPwm8Gpio(); + InitEPwm9Gpio(); + InitEPwm10Gpio(); + InitEPwm11Gpio(); + InitEPwm12Gpio(); +} + +// +// InitEPwm1Gpio - Initialize EPWM1 GPIOs +// +void InitEPwm1Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 1; // Disable pull-up on GPIO0 (EPWM1A) + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 1; // Disable pull-up on GPIO1 (EPWM1B) + // GpioCtrlRegs.GPEPUD.bit.GPIO145 = 1; // Disable pull-up on GPIO145 (EPWM1A) + // GpioCtrlRegs.GPEPUD.bit.GPIO146 = 1; // Disable pull-up on GPIO146 (EPWM1B) + + // + // Configure EPWM-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM1 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 1; // Configure GPIO0 as EPWM1A + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 1; // Configure GPIO1 as EPWM1B + // GpioCtrlRegs.GPEMUX2.bit.GPIO145 = 1; // Configure GPIO145 as EPWM1A + // GpioCtrlRegs.GPEMUX2.bit.GPIO146 = 1; // Configure GPIO0146 as EPWM1B + + EDIS; +} + +// +// InitEPwm2Gpio - Initialize EPWM2 GPIOs +// +void InitEPwm2Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 1; // Disable pull-up on GPIO2 (EPWM2A) + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 1; // Disable pull-up on GPIO3 (EPWM2B) + // GpioCtrlRegs.GPEPUD.bit.GPIO147 = 1; // Disable pull-up on GPIO147 (EPWM2A) + // GpioCtrlRegs.GPEPUD.bit.GPIO148 = 1; // Disable pull-up on GPIO148 (EPWM2B) + + // + // Configure EPwm-2 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM2 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 1; // Configure GPIO2 as EPWM2A + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 1; // Configure GPIO3 as EPWM2B + // GpioCtrlRegs.GPEMUX2.bit.GPIO147 = 1; // Configure GPIO147 as EPWM2A + // GpioCtrlRegs.GPEMUX2.bit.GPIO148 = 1; // Configure GPIO148 as EPWM2B + + EDIS; +} + +// +// InitEPwm3Gpio - Initialize EPWM3 GPIOs +// +void InitEPwm3Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO4 = 1; // Disable pull-up on GPIO4 (EPWM3A) + GpioCtrlRegs.GPAPUD.bit.GPIO5 = 1; // Disable pull-up on GPIO5 (EPWM3B) + // GpioCtrlRegs.GPEPUD.bit.GPIO149 = 1; // Disable pull-up on GPIO149 (EPWM3A) + // GpioCtrlRegs.GPEPUD.bit.GPIO150 = 1; // Disable pull-up on GPIO150 (EPWM3B) + + // + // Configure EPwm-3 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM3 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 1; // Configure GPIO4 as EPWM3A + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 1; // Configure GPIO5 as EPWM3B + // GpioCtrlRegs.GPEMUX2.bit.GPIO149 = 1; // Configure GPIO149 as EPWM3A + // GpioCtrlRegs.GPEMUX2.bit.GPIO150 = 1; // Configure GPIO150 as EPWM3B + + EDIS; +} + +// +// InitEPwm4Gpio - Initialize EPWM4 GPIOs +// +void InitEPwm4Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up on GPIO6 (EPWM4A) + GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; // Disable pull-up on GPIO7 (EPWM4B) + // GpioCtrlRegs.GPEPUD.bit.GPIO151 = 1; // Disable pull-up on GPIO151 (EPWM4A) + // GpioCtrlRegs.GPEPUD.bit.GPIO152 = 1; // Disable pull-up on GPIO152 (EPWM4B) + + // + // Configure EPWM-4 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM4 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EPWM4A + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EPWM4B + // GpioCtrlRegs.GPEMUX2.bit.GPIO151 = 1; // Configure GPIO151 as EPWM4A + // GpioCtrlRegs.GPEMUX2.bit.GPIO152 = 1; // Configure GPIO152 as EPWM4B + + EDIS; +} + +// +// InitEPwm5Gpio - Initialize EPWM5 GPIOs +// +void InitEPwm5Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; // Disable pull-up on GPIO8 (EPWM5A) + GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; // Disable pull-up on GPIO9 (EPWM5B) + // GpioCtrlRegs.GPEPUD.bit.GPIO153 = 1; // Disable pull-up on GPIO153 (EPWM5A) + // GpioCtrlRegs.GPEPUD.bit.GPIO154 = 1; // Disable pull-up on GPIO154 (EPWM5B) + + // + // Configure EPWM-5 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM5 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EPWM5A + GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EPWM5B + // GpioCtrlRegs.GPEMUX2.bit.GPIO153 = 1; // Configure GPIO153 as EPWM5A + // GpioCtrlRegs.GPEMUX2.bit.GPIO154 = 1; // Configure GPIO0154 as EPWM5B + + EDIS; +} + +// +// InitEPwm6Gpio - Initialize EPWM6 GPIOs +// +void InitEPwm6Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (EPWM6A) + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (EPWM6B) + // GpioCtrlRegs.GPEPUD.bit.GPIO155 = 1; // Disable pull-up on GPIO155 (EPWM6A) + // GpioCtrlRegs.GPEPUD.bit.GPIO156 = 1; // Disable pull-up on GPIO156 (EPWM6B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EPWM6A + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EPWM6B + // GpioCtrlRegs.GPEMUX2.bit.GPIO155 = 1; // Configure GPIO155 as EPWM6A + // GpioCtrlRegs.GPEMUX2.bit.GPIO156 = 1; // Configure GPIO156 as EPWM6B + + EDIS; +} + +// +// InitEPwm7Gpio - Initialize EPWM7 GPIOs +// +void InitEPwm7Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (EPWM7A) + GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (EPWM7B) + // GpioCtrlRegs.GPEPUD.bit.GPIO157 = 1; // Disable pull-up on GPIO157 (EPWM7A) + // GpioCtrlRegs.GPEPUD.bit.GPIO158 = 1; // Disable pull-up on GPIO158 (EPWM7B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EPWM7A + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EPWM7B + // GpioCtrlRegs.GPEMUX2.bit.GPIO157 = 1; // Configure GPIO157 as EPWM7A + // GpioCtrlRegs.GPEMUX2.bit.GPIO158 = 1; // Configure GPIO158 as EPWM7B + + EDIS; +} + +// +// InitEPwm8Gpio - Initialize EPWM8 GPIOs +// +void InitEPwm8Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; // Disable pull-up on GPIO14 (EPWM8A) + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1; // Disable pull-up on GPIO15 (EPWM8B) +// GpioCtrlRegs.GPEPUD.bit.GPIO159 = 1; // Disable pull-up on GPIO159 (EPWM8A) +// GpioCtrlRegs.GPFPUD.bit.GPIO160 = 1; // Disable pull-up on GPIO160 (EPWM8B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1; // Configure GPIO14 as EPWM8A + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1; // Configure GPIO15 as EPWM8B + // GpioCtrlRegs.GPEMUX2.bit.GPIO159 = 1; // Configure GPIO159 as EPWM8A + // GpioCtrlRegs.GPFMUX1.bit.GPIO160 = 1; // Configure GPIO160 as EPWM8B + + EDIS; +} + +// +// InitEPwm9Gpio - Initialize EPWM9 GPIOs +// +void InitEPwm9Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO161 = 1; // Disable pull-up on GPIO161 (EPWM9A) + GpioCtrlRegs.GPFPUD.bit.GPIO162 = 1; // Disable pull-up on GPIO162 (EPWM9B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO161 = 1; // Configure GPIO161 as EPWM9A + GpioCtrlRegs.GPFMUX1.bit.GPIO162 = 1; // Configure GPIO162 as EPWM9B + + EDIS; +} + +// +// InitEPwm10Gpio - Initialize EPWM10 GPIOs +// +void InitEPwm10Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO163 = 1; // Disable pull-up on GPIO163 (EPWM10A) + GpioCtrlRegs.GPFPUD.bit.GPIO164 = 1; // Disable pull-up on GPIO164 (EPWM10B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO163 = 1; // Configure GPIO163 as EPWM10A + GpioCtrlRegs.GPFMUX1.bit.GPIO164 = 1; // Configure GPIO164 as EPWM10B + + EDIS; +} + +// +// InitEPwm11Gpio - Initialize EPWM11 GPIOs +// +void InitEPwm11Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO165 = 1; // Disable pull-up on GPIO165 (EPWM11A) + GpioCtrlRegs.GPFPUD.bit.GPIO166 = 1; // Disable pull-up on GPIO166 (EPWM11B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO165 = 1; // Configure GPIO165 as EPWM11A + GpioCtrlRegs.GPFMUX1.bit.GPIO166 = 1; // Configure GPIO166 as EPWM11B + + EDIS; +} + +// +// InitEPwm12Gpio - Initialize EPWM12 GPIOs +// +void InitEPwm12Gpio(void) +{ + EALLOW; + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFPUD.bit.GPIO167 = 1; // Disable pull-up on GPIO167 (EPWM12A) + GpioCtrlRegs.GPFPUD.bit.GPIO168 = 1; // Disable pull-up on GPIO168 (EPWM12B) + + // + // Configure EPWM-6 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM6 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPFMUX1.bit.GPIO167 = 1; // Configure GPIO167 as EPWM12A + GpioCtrlRegs.GPFMUX1.bit.GPIO168 = 1; // Configure GPIO168 as EPWM12B + + EDIS; +} diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_EQep.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_EQep.c new file mode 100644 index 0000000000..90629e6f40 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_EQep.c @@ -0,0 +1,389 @@ +//########################################################################### +// +// FILE: F2837xD_EQep.c +// +// TITLE: F2837xD eQEP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// InitEQep - This function initializes the eQEP(s) to a known state. +// +void InitEQep(void) +{ + // Initialize eQEP1 + + //tbd... +} + +// +// InitEQepGpio - This function initializes GPIO pins to function as eQEP pins +// Each GPIO pin can be configured as a GPIO pin or up to 3 +// different peripheral functional pins. By default all pins +// come up as GPIO inputs after reset. +// Caution: +// For each eQEP peripheral +// Only one GPIO pin should be enabled for EQEPxA operation. +// Only one GPIO pin should be enabled for EQEPxB operation. +// Only one GPIO pin should be enabled for EQEPxS operation. +// Only one GPIO pin should be enabled for EQEPxI operation. +// Comment out other unwanted lines. +// +void InitEQepGpio() +{ + InitEQep1Gpio(); + InitEQep2Gpio(); + InitEQep3Gpio(); +} + +// +// InitEQep1Gpio - Initialize EQEP-1 GPIOs +// Caution: +// For each eQEP peripheral +// Only one GPIO pin should be enabled for EQEPxA operation. +// Only one GPIO pin should be enabled for EQEPxB operation. +// Only one GPIO pin should be enabled for EQEPxS operation. +// Only one GPIO pin should be enabled for EQEPxI operation. +// Comment out other unwanted lines. +// +void InitEQep1Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (EQEP1A) +// GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (EQEP1B) +// GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (EQEP1S) +// GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (EQEP1I) + + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 1; // Disable pull-up on GPIO20 (EQEP1A) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 1; // Disable pull-up on GPIO21 (EQEP1B) + GpioCtrlRegs.GPAPUD.bit.GPIO22 = 1; // Disable pull-up on GPIO22 (EQEP1S) + GpioCtrlRegs.GPAPUD.bit.GPIO23 = 1; // Disable pull-up on GPIO23 (EQEP1I) + +// GpioCtrlRegs.GPBPUD.bit.GPIO50 = 1; // Disable pull-up on GPIO50 (EQEP1A) +// GpioCtrlRegs.GPBPUD.bit.GPIO51 = 1; // Disable pull-up on GPIO51 (EQEP1B) +// GpioCtrlRegs.GPBPUD.bit.GPIO52 = 1; // Disable pull-up on GPIO52 (EQEP1S) +// GpioCtrlRegs.GPBPUD.bit.GPIO53 = 1; // Disable pull-up on GPIO53 (EQEP1I) + +// GpioCtrlRegs.GPDPUD.bit.GPIO96 = 1; // Disable pull-up on GPIO96 (EQEP1A) +// GpioCtrlRegs.GPDPUD.bit.GPIO97 = 1; // Disable pull-up on GPIO97 (EQEP1B) +// GpioCtrlRegs.GPDPUD.bit.GPIO98 = 1; // Disable pull-up on GPIO98 (EQEP1S) +// GpioCtrlRegs.GPDPUD.bit.GPIO99 = 1; // Disable pull-up on GPIO99 (EQEP1I) + + // + // Synchronize inputs to SYSCLK + // Synchronization can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 0; // Sync GPIO10 to SYSCLK (EQEP1A) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 0; // Sync GPIO11 to SYSCLK (EQEP1B) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 0; // Sync GPIO12 to SYSCLK (EQEP1S) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 0; // Sync GPIO13 to SYSCLK (EQEP1I) + + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 0; // Sync GPIO20 to SYSCLK (EQEP1A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 0; // Sync GPIO21 to SYSCLK (EQEP1B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 0; // Sync GPIO22 to SYSCLK (EQEP1S) + GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 0; // Sync GPIO23 to SYSCLK (EQEP1I) + +// GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 0; // Sync GPIO50 to SYSCLK (EQEP1A) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 0; // Sync GPIO51 to SYSCLK (EQEP1B) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 0; // Sync GPIO52 to SYSCLK (EQEP1S) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 0; // Sync GPIO53 to SYSCLK (EQEP1I) + +// GpioCtrlRegs.GPDQSEL1.bit.GPIO96 = 0; // Sync GPIO96 to SYSCLK (EQEP1A) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO97 = 0; // Sync GPIO97 to SYSCLK (EQEP1B) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO98 = 0; // Sync GPIO98 to SYSCLK (EQEP1S) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO99 = 0; // Sync GPIO99 to SYSCLK (EQEP1I) + + // + // Configure EQEP-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EQEP1 functional + // pins. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EQEP1A +// GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1; // Configure GPIO10 as EQEP1A +// GpioCtrlRegs.GPAGMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EQEP1B +// GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1; // Configure GPIO11 as EQEP1B +// GpioCtrlRegs.GPAGMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EQEP1S +// GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1; // Configure GPIO12 as EQEP1S +// GpioCtrlRegs.GPAGMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EQEP1I +// GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1; // Configure GPIO13 as EQEP1I + + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 1; // Configure GPIO20 as EQEP1A + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 1; // Configure GPIO21 as EQEP1B + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 1; // Configure GPIO22 as EQEP1S + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 1; // Configure GPIO23 as EQEP1I + +// GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 1; // Configure GPIO50 as EQEP1A +// GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 1; // Configure GPIO51 as EQEP1B +// GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 1; // Configure GPIO52 as EQEP1S +// GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 1; // Configure GPIO53 as EQEP1I + +// GpioCtrlRegs.GPDGMUX1.bit.GPIO96 = 1; // Configure GPIO96 as EQEP1A +// GpioCtrlRegs.GPDMUX1.bit.GPIO96 = 1; // Configure GPIO96 as EQEP1A +// GpioCtrlRegs.GPDGMUX1.bit.GPIO97 = 1; // Configure GPIO97 as EQEP1B +// GpioCtrlRegs.GPDMUX1.bit.GPIO97 = 1; // Configure GPIO97 as EQEP1B +// GpioCtrlRegs.GPDGMUX1.bit.GPIO98 = 1; // Configure GPIO98 as EQEP1S +// GpioCtrlRegs.GPDMUX1.bit.GPIO98 = 1; // Configure GPIO98 as EQEP1S +// GpioCtrlRegs.GPDGMUX1.bit.GPIO99 = 1; // Configure GPIO99 as EQEP1I +// GpioCtrlRegs.GPDMUX1.bit.GPIO99 = 1; // Configure GPIO99 as EQEP1I + + EDIS; +} + +// +// InitEQep2Gpio - Initialize EQEP-2 GPIOs +// +void InitEQep2Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO24 = 1; // Disable pull-up on GPIO24 (EQEP2A) + GpioCtrlRegs.GPAPUD.bit.GPIO25 = 1; // Disable pull-up on GPIO25 (EQEP2B) + GpioCtrlRegs.GPAPUD.bit.GPIO26 = 1; // Disable pull-up on GPIO26 (EQEP2S) + GpioCtrlRegs.GPAPUD.bit.GPIO27 = 1; // Disable pull-up on GPIO27 (EQEP2I) + +// GpioCtrlRegs.GPBPUD.bit.GPIO54 = 1; // Disable pull-up on GPIO54 (EQEP2A) +// GpioCtrlRegs.GPBPUD.bit.GPIO55 = 1; // Disable pull-up on GPIO55 (EQEP2B) +// GpioCtrlRegs.GPBPUD.bit.GPIO56 = 1; // Disable pull-up on GPIO56 (EQEP2S) +// GpioCtrlRegs.GPBPUD.bit.GPIO57 = 1; // Disable pull-up on GPIO57 (EQEP2I) + +// GpioCtrlRegs.GPCPUD.bit.GPIO78 = 1; // Disable pull-up on GPIO78 (EQEP2A) +// GpioCtrlRegs.GPCPUD.bit.GPIO79 = 1; // Disable pull-up on GPIO79 (EQEP2B) +// GpioCtrlRegs.GPCPUD.bit.GPIO80 = 1; // Disable pull-up on GPIO80 (EQEP2S) +// GpioCtrlRegs.GPCPUD.bit.GPIO81 = 1; // Disable pull-up on GPIO81 (EQEP2I) + +// GpioCtrlRegs.GPDPUD.bit.GPIO100 = 1; // Disable pull-up on GPIO100 (EQEP2A) +// GpioCtrlRegs.GPDPUD.bit.GPIO101 = 1; // Disable pull-up on GPIO101 (EQEP2B) +// GpioCtrlRegs.GPDPUD.bit.GPIO102 = 1; // Disable pull-up on GPIO102 (EQEP2S) +// GpioCtrlRegs.GPDPUD.bit.GPIO103 = 1; // Disable pull-up on GPIO103 (EQEP2I) + + // + // Synchronize inputs to SYSCLK + // Synchronization can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO24 = 0; // Sync GPIO24 to SYSCLK (EQEP2A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 0; // Sync GPIO25 to SYSCLK (EQEP2B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 0; // Sync GPIO26 to SYSCLK (EQEP2S) + GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 0; // Sync GPIO27 to SYSCLK (EQEP2I) + +// GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 0; // Sync GPIO54 to SYSCLK (EQEP2A) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 0; // Sync GPIO55 to SYSCLK (EQEP2B) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 0; // Sync GPIO56 to SYSCLK (EQEP2S) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 0; // Sync GPIO57 to SYSCLK (EQEP2I) + +// GpioCtrlRegs.GPCQSEL1.bit.GPIO78 = 0; // Sync GPIO78 to SYSCLK (EQEP2A) +// GpioCtrlRegs.GPCQSEL1.bit.GPIO79 = 0; // Sync GPIO79 to SYSCLK (EQEP2B) +// GpioCtrlRegs.GPCQSEL2.bit.GPIO80 = 0; // Sync GPIO80 to SYSCLK (EQEP2S) +// GpioCtrlRegs.GPCQSEL2.bit.GPIO81 = 0; // Sync GPIO81 to SYSCLK (EQEP2I) + +// GpioCtrlRegs.GPDQSEL1.bit.GPIO100 = 0; // Sync GPIO100 to SYSCLK (EQEP2A) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO101 = 0; // Sync GPIO101 to SYSCLK (EQEP2B) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO102 = 0; // Sync GPIO102 to SYSCLK (EQEP2S) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO103 = 0; // Sync GPIO103 to SYSCLK (EQEP2I) + + // + // Configure EQEP-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EQEP2 functional pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 2; // Configure GPIO24 as EQEP2A + GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 2; // Configure GPIO25 as EQEP2B + GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 2; // Configure GPIO26 as EQEP2S + GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 2; // Configure GPIO27 as EQEP2I + +// GpioCtrlRegs.GPBGMUX2.bit.GPIO54 = 1; // Configure GPIO54 as EQEP2A +// GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 1; // Configure GPIO54 as EQEP2A +// GpioCtrlRegs.GPBGMUX2.bit.GPIO55 = 1; // Configure GPIO55 as EQEP2B +// GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 1; // Configure GPIO55 as EQEP2B +// GpioCtrlRegs.GPBGMUX2.bit.GPIO56 = 1; // Configure GPIO56 as EQEP2S +// GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 1; // Configure GPIO56 as EQEP2S +// GpioCtrlRegs.GPBGMUX2.bit.GPIO57 = 1; // Configure GPIO57 as EQEP2I +// GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 1; // Configure GPIO57 as EQEP2I + +// GpioCtrlRegs.GPCGMUX1.bit.GPIO78 = 1; // Configure GPIO78 as EQEP2A +// GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 2; // Configure GPIO78 as EQEP2A +// GpioCtrlRegs.GPCGMUX1.bit.GPIO79 = 1; // Configure GPIO79 as EQEP2B +// GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 2; // Configure GPIO79 as EQEP2B +// GpioCtrlRegs.GPCGMUX2.bit.GPIO80 = 1; // Configure GPIO80 as EQEP2S +// GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 2; // Configure GPIO80 as EQEP2S +// GpioCtrlRegs.GPCGMUX2.bit.GPIO81 = 1; // Configure GPIO81 as EQEP2I +// GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 2; // Configure GPIO81 as EQEP2I + +// GpioCtrlRegs.GPDGMUX1.bit.GPIO100 = 1; // Configure GPIO100 as EQEP2A +// GpioCtrlRegs.GPDMUX1.bit.GPIO100 = 1; // Configure GPIO100 as EQEP2A +// GpioCtrlRegs.GPDGMUX1.bit.GPIO101 = 1; // Configure GPIO101 as EQEP2B +// GpioCtrlRegs.GPDMUX1.bit.GPIO101 = 1; // Configure GPIO101 as EQEP2B +// GpioCtrlRegs.GPDGMUX1.bit.GPIO102 = 1; // Configure GPIO102 as EQEP2S +// GpioCtrlRegs.GPDMUX1.bit.GPIO102 = 1; // Configure GPIO102 as EQEP2S +// GpioCtrlRegs.GPDGMUX1.bit.GPIO103 = 1; // Configure GPIO103 as EQEP2I +// GpioCtrlRegs.GPDMUX1.bit.GPIO103 = 1; // Configure GPIO103 as EQEP2I + + EDIS; +} + +// +// InitEQep3Gpio - Initialize EQEP-3 GPIOs +// +void InitEQep3Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1; // Disable pull-up on GPIO6 (EQEP3A) +// GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1; // Disable pull-up on GPIO7 (EQEP3B) +// GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1; // Disable pull-up on GPIO8 (EQEP3S) +// GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1; // Disable pull-up on GPIO9 (EQEP3I) + + GpioCtrlRegs.GPAPUD.bit.GPIO28 = 1; // Disable pull-up on GPIO28 (EQEP3A) + GpioCtrlRegs.GPAPUD.bit.GPIO29 = 1; // Disable pull-up on GPIO29 (EQEP3B) + GpioCtrlRegs.GPAPUD.bit.GPIO30 = 1; // Disable pull-up on GPIO30 (EQEP3S) + GpioCtrlRegs.GPAPUD.bit.GPIO31 = 1; // Disable pull-up on GPIO31 (EQEP3I) + +// GpioCtrlRegs.GPBPUD.bit.GPIO62 = 1; // Disable pull-up on GPIO62 (EQEP3A) +// GpioCtrlRegs.GPBPUD.bit.GPIO63 = 1; // Disable pull-up on GPIO63 (EQEP3B) +// GpioCtrlRegs.GPCPUD.bit.GPIO64 = 1; // Disable pull-up on GPIO64 (EQEP3S) +// GpioCtrlRegs.GPCPUD.bit.GPIO65 = 1; // Disable pull-up on GPIO65 (EQEP3I) + +// GpioCtrlRegs.GPDPUD.bit.GPIO104 = 1; // Disable pull-up on GPIO104 (EQEP3A) +// GpioCtrlRegs.GPDPUD.bit.GPIO105 = 1; // Disable pull-up on GPIO105 (EQEP3B) +// GpioCtrlRegs.GPDPUD.bit.GPIO106 = 1; // Disable pull-up on GPIO106 (EQEP3S) +// GpioCtrlRegs.GPDPUD.bit.GPIO107 = 1; // Disable pull-up on GPIO107 (EQEP3I) + + // + // Synchronize inputs to SYSCLK + // Synchronization can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAQSEL1.bit.GPIO6 = 0; // Sync GPIO6 to SYSCLK (EQEP3A) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 0; // Sync GPIO7 to SYSCLK (EQEP3B) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO8 = 0; // Sync GPIO8 to SYSCLK (EQEP3S) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO9 = 0; // Sync GPIO9 to SYSCLK (EQEP3I) + + GpioCtrlRegs.GPAQSEL2.bit.GPIO28 = 0; // Sync GPIO28 to SYSCLK (EQEP3A) + GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 0; // Sync GPIO29 to SYSCLK (EQEP3B) + GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 0; // Sync GPIO30 to SYSCLK (EQEP3S) + GpioCtrlRegs.GPAQSEL2.bit.GPIO31 = 0; // Sync GPIO31 to SYSCLK (EQEP3I) + +// GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 0; // Sync GPIO62 to SYSCLK (EQEP3A) +// GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 0; // Sync GPIO63 to SYSCLK (EQEP3B) +// GpioCtrlRegs.GPCQSEL1.bit.GPIO64 = 0; // Sync GPIO64 to SYSCLK (EQEP3S) +// GpioCtrlRegs.GPCQSEL1.bit.GPIO65 = 0; // Sync GPIO65 to SYSCLK (EQEP3I) + +// GpioCtrlRegs.GPDQSEL1.bit.GPIO104 = 0; // Sync GPIO104 to SYSCLK (EQEP3A) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO105 = 0; // Sync GPIO105 to SYSCLK (EQEP3B) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO106 = 0; // Sync GPIO106 to SYSCLK (EQEP3S) +// GpioCtrlRegs.GPDQSEL1.bit.GPIO107 = 0; // Sync GPIO107 to SYSCLK (EQEP3I) + + // + // Configure EQEP-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EQEP3 functional pins. + // Comment out other unwanted lines. + // + +// GpioCtrlRegs.GPAGMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EQEP3A +// GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1; // Configure GPIO6 as EQEP3A +// GpioCtrlRegs.GPAGMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EQEP3B +// GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1; // Configure GPIO7 as EQEP3B +// GpioCtrlRegs.GPAGMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EQEP3S +// GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1; // Configure GPIO8 as EQEP3S +// GpioCtrlRegs.GPAGMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EQEP3I +// GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1; // Configure GPIO9 as EQEP3I + + GpioCtrlRegs.GPAGMUX2.bit.GPIO28 = 1; // Configure GPIO28 as EQEP3A + GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 2; // Configure GPIO28 as EQEP3A + GpioCtrlRegs.GPAGMUX2.bit.GPIO29 = 1; // Configure GPIO29 as EQEP3B + GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 2; // Configure GPIO29 as EQEP3B + GpioCtrlRegs.GPAGMUX2.bit.GPIO30 = 1; // Configure GPIO30 as EQEP3S + GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 2; // Configure GPIO30 as EQEP3S + GpioCtrlRegs.GPAGMUX2.bit.GPIO31 = 1; // Configure GPIO31 as EQEP3I + GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 2; // Configure GPIO31 as EQEP3I + +// GpioCtrlRegs.GPBGMUX2.bit.GPIO62 = 1; // Configure GPIO62 as EQEP3A +// GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 1; // Configure GPIO62 as EQEP3A +// GpioCtrlRegs.GPBGMUX2.bit.GPIO63 = 1; // Configure GPIO63 as EQEP3B +// GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 1; // Configure GPIO63 as EQEP3B +// GpioCtrlRegs.GPCGMUX1.bit.GPIO64 = 1; // Configure GPIO64 as EQEP3S +// GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 1; // Configure GPIO64 as EQEP3S +// GpioCtrlRegs.GPCGMUX1.bit.GPIO65 = 1; // Configure GPIO65 as EQEP3I +// GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 1; // Configure GPIO65 as EQEP3I + +// GpioCtrlRegs.GPDGMUX1.bit.GPIO104 = 1; // Configure GPIO104 as EQEP3A +// GpioCtrlRegs.GPDMUX1.bit.GPIO104 = 1; // Configure GPIO104 as EQEP3A +// GpioCtrlRegs.GPDGMUX1.bit.GPIO105 = 1; // Configure GPIO105 as EQEP3B +// GpioCtrlRegs.GPDMUX1.bit.GPIO105 = 1; // Configure GPIO105 as EQEP3B +// GpioCtrlRegs.GPDGMUX1.bit.GPIO106 = 1; // Configure GPIO106 as EQEP3S +// GpioCtrlRegs.GPDMUX1.bit.GPIO106 = 1; // Configure GPIO106 as EQEP3S +// GpioCtrlRegs.GPDGMUX1.bit.GPIO107 = 1; // Configure GPIO107 as EQEP3I +// GpioCtrlRegs.GPDMUX1.bit.GPIO107 = 1; // Configure GPIO107 as EQEP3I + + EDIS; +} + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Emif.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Emif.c new file mode 100644 index 0000000000..0f8ff9d52b --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Emif.c @@ -0,0 +1,458 @@ +//########################################################################### +// +// FILE: F2837xD_Emif.c +// +// TITLE: F2837xD EMIF Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// Emif1Initialize - This function initializes the EMIF1 to a known state. +// +void Emif1Initialize(void) +{ + EALLOW; + // + // Perform a Module soft reset on EMIF + // +#ifdef CPU1 + DevCfgRegs.SOFTPRES1.all = 0x1; + __asm (" nop"); + DevCfgRegs.SOFTPRES1.all = 0x0; +#endif + EDIS; +} + +// +// Emif2Initialize - This function initializes the EMIF2 to a known state. +// +void Emif2Initialize(void) +{ + EALLOW; + // + // Perform a Module soft reset on EMIF + // +#ifdef CPU1 + DevCfgRegs.SOFTPRES1.all = 0x2; + __asm (" nop"); + DevCfgRegs.SOFTPRES1.all = 0x0; +#endif + EDIS; +} + +// +// ASync_wait_config - Async wait configuration function +// +void ASync_wait_config(Uint16 inst, Uint16 wait_count, Uint16 wait_polarity) +{ + if (inst == 0) + { + // + // 7:0 Maximum Extended Wait cycles. + // + Emif1Regs.ASYNC_WCCR.bit.MAX_EXT_WAIT = wait_count; + + // + // 28 Wait Polarity for pad_wait_i[0]. + // + Emif1Regs.ASYNC_WCCR.bit.WP0 = wait_polarity; + } + else + { + // + // 7:0 Maximum Extended Wait cycles. + // + Emif2Regs.ASYNC_WCCR.bit.MAX_EXT_WAIT = wait_count; + + // + // 28 Wait Polarity for pad_wait_i[0]. + // + Emif2Regs.ASYNC_WCCR.bit.WP0 = wait_polarity; + } +} + +// +// ASync_cs2_config - Async CS2 Configuration +// +void ASync_cs2_config(Uint16 inst, Uint16 async_mem_data_width, + Uint16 turn_around_time, Uint16 r_hold_time, + Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold, + Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait, + Uint16 strobe_sel) +{ + if (inst == 0) + { + // + // 1:0 Asynchronous Memory Size. + // 3:2 Turn Around cycles. + // 6:4 Read Strobe Hold cycles. + // 12:7 Read Strobe Duration cycles. + // 16:13 Read Strobe Setup cycles. + // 19:17 Write Strobe Hold cycles. + // 25:20 Write Strobe Duration cycles. + // 29:26 Write Strobe Setup cycles. + // 30 Extend Wait mode. + // 31 Select Strobe mode. + // + Emif1Regs.ASYNC_CS2_CR.bit.ASIZE = async_mem_data_width; + Emif1Regs.ASYNC_CS2_CR.bit.TA= turn_around_time; + Emif1Regs.ASYNC_CS2_CR.bit.R_HOLD= r_hold_time; + Emif1Regs.ASYNC_CS2_CR.bit.R_STROBE = r_strobe_time; + Emif1Regs.ASYNC_CS2_CR.bit.R_SETUP = r_setup; + Emif1Regs.ASYNC_CS2_CR.bit.W_HOLD = w_hold; + Emif1Regs.ASYNC_CS2_CR.bit.W_STROBE = w_strobe; + Emif1Regs.ASYNC_CS2_CR.bit.W_SETUP = w_setup; + Emif1Regs.ASYNC_CS2_CR.bit.EW = extend_wait; + Emif1Regs.ASYNC_CS2_CR.bit.SS = strobe_sel; + } + else + { + // + // 1:0 Asynchronous Memory Size. + // 3:2 Turn Around cycles. + // 6:4 Read Strobe Hold cycles. + // 12:7 Read Strobe Duration cycles. + // 16:13 Read Strobe Setup cycles. + // 19:17 Write Strobe Hold cycles. + // 25:20 Write Strobe Duration cycles. + // 29:26 Write Strobe Setup cycles. + // 30 Extend Wait mode. + // 31 Select Strobe mode. + // + Emif2Regs.ASYNC_CS2_CR.bit.ASIZE = async_mem_data_width; + Emif2Regs.ASYNC_CS2_CR.bit.TA= turn_around_time; + Emif2Regs.ASYNC_CS2_CR.bit.R_HOLD= r_hold_time; + Emif2Regs.ASYNC_CS2_CR.bit.R_STROBE = r_strobe_time; + Emif2Regs.ASYNC_CS2_CR.bit.R_SETUP = r_setup; + Emif2Regs.ASYNC_CS2_CR.bit.W_HOLD = w_hold; + Emif2Regs.ASYNC_CS2_CR.bit.W_STROBE = w_strobe; + Emif2Regs.ASYNC_CS2_CR.bit.W_SETUP = w_setup; + Emif2Regs.ASYNC_CS2_CR.bit.EW = extend_wait; + Emif2Regs.ASYNC_CS2_CR.bit.SS = strobe_sel; + } +} + +// +// ASync_cs3_config - Async CS3 Configuration +// +void ASync_cs3_config(Uint16 inst, Uint16 async_mem_data_width, + Uint16 turn_around_time, Uint16 r_hold_time, + Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold, + Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait, + Uint16 strobe_sel) +{ + // + // 1:0 Asynchronous Memory Size. + // 3:2 Turn Around cycles. + // 6:4 Read Strobe Hold cycles. + // 12:7 Read Strobe Duration cycles. + // 16:13 Read Strobe Setup cycles. + // 19:17 Write Strobe Hold cycles. + // 25:20 Write Strobe Duration cycles. + // 29:26 Write Strobe Setup cycles. + // 30 Extend Wait mode. + // 31 Select Strobe mode. + // + Emif1Regs.ASYNC_CS3_CR.bit.ASIZE = async_mem_data_width; + Emif1Regs.ASYNC_CS3_CR.bit.TA= turn_around_time; + Emif1Regs.ASYNC_CS3_CR.bit.R_HOLD= r_hold_time; + Emif1Regs.ASYNC_CS3_CR.bit.R_STROBE = r_strobe_time; + Emif1Regs.ASYNC_CS3_CR.bit.R_SETUP = r_setup; + Emif1Regs.ASYNC_CS3_CR.bit.W_HOLD = w_hold; + Emif1Regs.ASYNC_CS3_CR.bit.W_STROBE = w_strobe; + Emif1Regs.ASYNC_CS3_CR.bit.W_SETUP = w_setup; + Emif1Regs.ASYNC_CS3_CR.bit.EW = extend_wait; + Emif1Regs.ASYNC_CS3_CR.bit.SS = strobe_sel; +} + +// +// ASync_cs4_config - Async CS4 Configuration +// +void ASync_cs4_config(Uint16 inst, Uint16 async_mem_data_width, + Uint16 turn_around_time, Uint16 r_hold_time, + Uint16 r_strobe_time, Uint16 r_setup, Uint16 w_hold, + Uint16 w_strobe, Uint16 w_setup, Uint16 extend_wait, + Uint16 strobe_sel) +{ + // + // 1:0 Asynchronous Memory Size. + // 3:2 Turn Around cycles. + // 6:4 Read Strobe Hold cycles. + // 12:7 Read Strobe Duration cycles. + // 16:13 Read Strobe Setup cycles. + // 19:17 Write Strobe Hold cycles. + // 25:20 Write Strobe Duration cycles. + // 29:26 Write Strobe Setup cycles. + // 30 Extend Wait mode. + // 31 Select Strobe mode. + // + Emif1Regs.ASYNC_CS4_CR.bit.ASIZE = async_mem_data_width; + Emif1Regs.ASYNC_CS4_CR.bit.TA= turn_around_time; + Emif1Regs.ASYNC_CS4_CR.bit.R_HOLD= r_hold_time; + Emif1Regs.ASYNC_CS4_CR.bit.R_STROBE = r_strobe_time; + Emif1Regs.ASYNC_CS4_CR.bit.R_SETUP = r_setup; + Emif1Regs.ASYNC_CS4_CR.bit.W_HOLD = w_hold; + Emif1Regs.ASYNC_CS4_CR.bit.W_STROBE = w_strobe; + Emif1Regs.ASYNC_CS4_CR.bit.W_SETUP = w_setup; + Emif1Regs.ASYNC_CS4_CR.bit.EW = extend_wait; + Emif1Regs.ASYNC_CS4_CR.bit.SS = strobe_sel; +} + +#ifdef CPU1 +// +// setup_emif1_pinmux_async_16bit - function for EMIF1 GPIO pin setup +// +void setup_emif1_pinmux_async_16bit(Uint16 cpu_sel) +{ + Uint16 i; + + for (i=28; i<=52; i++) + { + if ((i != 42) && (i != 43)) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + for (i=63; i<=87; i++) + { + if (i != 84) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + + GPIO_SetupPinMux(88,cpu_sel,3); + GPIO_SetupPinMux(89,cpu_sel,3); + GPIO_SetupPinMux(90,cpu_sel,3); + GPIO_SetupPinMux(91,cpu_sel,3); + GPIO_SetupPinMux(92,cpu_sel,3); + GPIO_SetupPinMux(93,cpu_sel,3); + GPIO_SetupPinMux(94,cpu_sel,2); + + // + //setup async mode and enable pull-ups for Data pins + // + for (i=69; i<=85; i++) + { + if (i != 84) + { + GPIO_SetupPinOptions(i,0,0x31); // GPIO_ASYNC||GPIO_PULLUP + } + } +} + +// +// setup_emif1_pinmux_async_32bit - Setup pinmux for 32bit async +// +void setup_emif1_pinmux_async_32bit(Uint16 cpu_sel) +{ + Uint16 i; + + for (i=28; i<=87; i++) + { + if ((i != 42) && (i != 43) && (i != 84)) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + + GPIO_SetupPinMux(88,cpu_sel,3); + GPIO_SetupPinMux(89,cpu_sel,3); + GPIO_SetupPinMux(90,cpu_sel,3); + GPIO_SetupPinMux(91,cpu_sel,3); + GPIO_SetupPinMux(92,cpu_sel,3); + GPIO_SetupPinMux(93,cpu_sel,3); + GPIO_SetupPinMux(94,cpu_sel,2); + + // + //setup async mode for Data pins + // + for (i=53; i<=85; i++) + { + if (i != 84) + { + GPIO_SetupPinOptions(i,0,0x31); + } + } +} + +// +// setup_emif2_pinmux_async_16bit - function for EMIF1 GPIO pin setup +// +void setup_emif2_pinmux_async_16bit(Uint16 cpu_sel) +{ + Uint16 i; + + for (i=96; i<=121; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + + for (i=53; i<=68; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + + // + //setup async mode for Data pins + // + for (i=53; i<=68; i++) + { + GPIO_SetupPinOptions(i,0,0x31); + } +} + +// +// setup_emif1_pinmux_sdram_16bit - Setup pinmux for 16bit SDRAM +// +void setup_emif1_pinmux_sdram_16bit(Uint16 cpu_sel) +{ + int i; + + for (i=29; i<=52; i++) + { + if ((i != 42) && (i != 43)) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + + for (i=69; i<=85; i++) + { + if (i != 84) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + + for(i=86; i<=93; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + + // + //configure Data pins for Async mode + // + for (i = 69; i <= 85; i++) + { + if (i != 84) + { + GPIO_SetupPinOptions(i,0,0x31); + } + } + + GPIO_SetupPinOptions(88,0,0x31); + GPIO_SetupPinOptions(89,0,0x31); + GPIO_SetupPinOptions(90,0,0x31); + GPIO_SetupPinOptions(91,0,0x31); +} + +// +// setup_emif2_pinmux_sdram_16bit - Setup pinmux for 16bit SDRAM +// +void setup_emif2_pinmux_sdram_16bit(Uint16 cpu_sel) +{ + int i; + + for (i=53; i<=68; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + for (i=96; i<=121; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + + // + //configure Data pins for Async mode + // + for (i = 53; i <= 68; i++) + { + GPIO_SetupPinOptions(i,0,0x31); + } +} + +// +// setup_emif1_pinmux_sdram_32bit - Setup pinmux for 32bit SDRAM +// +void setup_emif1_pinmux_sdram_32bit(Uint16 cpu_sel) +{ + int i; + + for (i=28; i<=85; i++) + { + if ((i != 42) && (i != 43) && (i != 84)) + { + GPIO_SetupPinMux(i,cpu_sel,2); + } + } + + for(i=86; i<=93; i++) + { + GPIO_SetupPinMux(i,cpu_sel,3); + } + + GPIO_SetupPinMux(94,cpu_sel,2); + + // + //configure Data pins for Async mode + // + for (i = 53; i <= 85; i++) + { + if (i != 84) + { + GPIO_SetupPinOptions(i,0,0x31); + } + } + + GPIO_SetupPinOptions(88,0,0x31); + GPIO_SetupPinOptions(89,0,0x31); + GPIO_SetupPinOptions(90,0,0x31); + GPIO_SetupPinOptions(91,0,0x31); + } + +#endif // CPU1 + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Gpio.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Gpio.c new file mode 100644 index 0000000000..0c5927b5ed --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Gpio.c @@ -0,0 +1,506 @@ +//########################################################################### +// +// FILE: F2837xD_Gpio.c +// +// TITLE: GPIO module support functions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +//Low-level functions for GPIO configuration (CPU1 only) +// + +#ifdef CPU1 + // + // InitGpio - Sets all pins to be muxed to GPIO in input mode with pull-ups + // enabled. Also resets CPU control to CPU1 and disables open + // drain and polarity inversion and sets the qualification to + // synchronous. Also unlocks all GPIOs. Only one CPU should call + // this function. + // + void InitGpio() + { + volatile Uint32 *gpioBaseAddr; + Uint16 regOffset; + + // + //Disable pin locks + // + EALLOW; + GpioCtrlRegs.GPALOCK.all = 0x00000000; + GpioCtrlRegs.GPBLOCK.all = 0x00000000; + GpioCtrlRegs.GPCLOCK.all = 0x00000000; + GpioCtrlRegs.GPDLOCK.all = 0x00000000; + GpioCtrlRegs.GPELOCK.all = 0x00000000; + GpioCtrlRegs.GPFLOCK.all = 0x00000000; + + // + // Fill all registers with zeros. Writing to each register separately + // for six GPIO modules would make this function *very* long. + // Fortunately, we'd be writing them all with zeros anyway, so this + // saves a lot of space. + // + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs; + for (regOffset = 0; regOffset < sizeof(GpioCtrlRegs)/2; regOffset++) + { + // + //Hack to avoid enabling pull-ups on all pins. GPyPUD is offset + //0x0C in each register group of 0x40 words. Since this is a + //32-bit pointer, the addresses must be divided by 2. + // + if (regOffset % (0x40/2) != (0x0C/2)) + { + gpioBaseAddr[regOffset] = 0x00000000; + } + } + + gpioBaseAddr = (Uint32 *)&GpioDataRegs; + for (regOffset = 0; regOffset < sizeof(GpioDataRegs)/2; regOffset++) + { + gpioBaseAddr[regOffset] = 0x00000000; + } + + EDIS; + } + + // + // GPIO_SetupPinMux - Set the peripheral muxing for the specified pin. The + // appropriate parameters can be found in the GPIO Muxed + // Pins table(4.4) in the datasheet. Use the GPIO index + // row (0 to 15) to select a muxing option for the GPIO. + // + void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *mux, *gmux, *csel; + Uint16 pin32, pin16, pin8; + + pin32 = gpioNumber % 32; + pin16 = gpioNumber % 16; + pin8 = gpioNumber % 8; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Sanity check for valid cpu and peripheral values + // + if (cpu > GPIO_MUX_CPU2CLA || muxPosition > 0xF) + return; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyCSEL1-4. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + mux = gpioBaseAddr + GPYMUX + pin32/16; + gmux = gpioBaseAddr + GPYGMUX + pin32/16; + csel = gpioBaseAddr + GPYCSEL + pin32/8; + + // + //Now for the actual function + // + EALLOW; + + // + //To change the muxing, set the peripheral mux to 0/GPIO first to avoid + //glitches, then change the group mux, then set the peripheral mux to + //its target value. Finally, set the CPU select. This procedure is + //described in the TRM. Unfortunately, since we don't know the pin in + //advance we can't hardcode a bitfield reference, so there's some + //tricky bit twiddling here. + // + *mux &= ~(0x3UL << (2*pin16)); + *gmux &= ~(0x3UL << (2*pin16)); + *gmux |= (Uint32)((muxPosition >> 2) & 0x3UL) << (2*pin16); + *mux |= (Uint32)(muxPosition & 0x3UL) << (2*pin16); + + *csel &= ~(0x3L << (4*pin8)); + *csel |= (Uint32)(cpu & 0x3L) << (4*pin8); + + // + //WARNING: This code does not touch the analog mode select registers, + //which are needed to give the USB module control of its IOs. + // + EDIS; + } + + // + // GPIO_SetupPinOptions - Setup up the GPIO input/output options for the + // specified pin. + // + //The flags are a 16-bit mask produced by ORing together options. + //For input pins, the valid flags are: + //GPIO_PULLUP Enable pull-up + //GPIO_INVERT Enable input polarity inversion + //GPIO_SYNC Synchronize the input latch to PLLSYSCLK + // (default -- you don't need to specify this) + //GPIO_QUAL3 Use 3-sample qualification + //GPIO_QUAL6 Use 6-sample qualification + //GPIO_ASYNC Do not use synchronization or qualification + //(Note: only one of SYNC, QUAL3, QUAL6, or ASYNC is allowed) + // + //For output pins, the valid flags are: + //GPIO_OPENDRAIN Output in open drain mode + //GPIO_PULLUP If open drain enabled, also enable the pull-up + //and the input qualification flags (SYNC/QUAL3/QUAL6/SYNC) listed above. + // + //With no flags, the default input state is synchronous with no + //pull-up or polarity inversion. The default output state is + //the standard digital output. + // + void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *dir, *pud, *inv, *odr, *qsel; + Uint32 pin32, pin16, pinMask, qual; + + pin32 = gpioNumber % 32; + pin16 = gpioNumber % 16; + pinMask = 1UL << pin32; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyQSEL1-2. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + dir = gpioBaseAddr + GPYDIR; + pud = gpioBaseAddr + GPYPUD; + inv = gpioBaseAddr + GPYINV; + odr = gpioBaseAddr + GPYODR; + qsel = gpioBaseAddr + GPYQSEL + pin32/16; + + EALLOW; + + // + //Set the data direction + // + *dir &= ~pinMask; + if (output == 1) + { + // + //Output, with optional open drain mode and pull-up + // + *dir |= pinMask; + + // + //Enable open drain if necessary + // + if (flags & GPIO_OPENDRAIN) + { + *odr |= pinMask; + } + else + { + *odr &= ~pinMask; + } + + // + //Enable pull-up if necessary. Open drain mode must be active. + // + if (flags & (GPIO_OPENDRAIN | GPIO_PULLUP)) + { + *pud &= ~pinMask; + } + else + { + *pud |= pinMask; + } + } + else + { + // + //Input, with optional pull-up, qualification, and polarity + //inversion + // + *dir &= ~pinMask; + + // + //Enable pull-up if necessary + // + if (flags & GPIO_PULLUP) + { + *pud &= ~pinMask; + } + else + { + *pud |= pinMask; + } + + // + //Invert polarity if necessary + // + if (flags & GPIO_INVERT) + { + *inv |= pinMask; + } + else + { + *inv &= ~pinMask; + } + } + + // + //Extract the qualification parameter and load it into the register. + //This is also needed for open drain outputs, so we might as well do it + //all the time. + // + qual = (flags & GPIO_ASYNC) / GPIO_QUAL3; + *qsel &= ~(0x3L << (2 * pin16)); + if (qual != 0x0) + { + *qsel |= qual << (2 * pin16); + } + + EDIS; + } + + // + // GPIO_SetupLock - Enable or disable the GPIO register bit lock for the + // specified pin. + // The valid flags are: + // GPIO_UNLOCK - Unlock the pin setup register bits for + // the specified pin + // GPIO_LOCK - Lock the pin setup register bits for the + // specified pin + // + void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags) + { + volatile Uint32 *gpioBaseAddr; + volatile Uint32 *lock; + Uint32 pin32, pinMask; + + pin32 = gpioNumber % 32; + pinMask = 1UL << pin32; + gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET; + + // + //Create pointers to the appropriate registers. This is a workaround + //for the way GPIO registers are defined. The standard definition + //in the header file makes it very easy to do named accesses of one + //register or bit, but hard to do arbitrary numerical accesses. It's + //easier to have an array of GPIO modules with identical registers, + //including arrays for multi-register groups like GPyQSEL1-2. But + //the header file doesn't define anything we can turn into an array, + //so manual pointer arithmetic is used instead. + // + lock = gpioBaseAddr + GPYLOCK; + + EALLOW; + if(flags) + { + //Lock the pin + *lock |= pinMask; + } + else + { + //Unlock the pin + *lock &= ~pinMask; + } + EDIS; + } + + // + //External interrupt setup + // + void GPIO_SetupXINT1Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT4SELECT = gpioNumber; //Set XINT1 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT2Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT5SELECT = gpioNumber; //Set XINT2 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT3Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT6SELECT = gpioNumber; //Set XINT3 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT4Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT13SELECT = gpioNumber; //Set XINT4 source to GPIO-pin + EDIS; + } + void GPIO_SetupXINT5Gpio(Uint16 gpioNumber) + { + EALLOW; + InputXbarRegs.INPUT14SELECT = gpioNumber; //Set XINT5 source to GPIO-pin + EDIS; + } + + // + //GPIO_EnableUnbondedIOPullupsFor176Pin - Enable pullups for the unbonded + // GPIOs on the 176PTP package: + // GPIOs Grp Bits + // 95-132 C 31 + // D 31:0 + // E 4:0 + // 134-168 E 31:6 + // F 8:0 + // + void GPIO_EnableUnbondedIOPullupsFor176Pin() + { + EALLOW; + GpioCtrlRegs.GPCPUD.all = ~0x80000000; //GPIO 95 + GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127 + GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFDF; //GPIOs 128-159 except for 133 + GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168 + EDIS; + } + + // + // GPIO_EnableUnbondedIOPullupsFor100Pin - Enable pullups for the unbonded + // GPIOs on the 100PZ package: + // GPIOs Grp Bits + // 0-1 A 1:0 + // 5-9 A 9:5 + // 22-40 A 31:22 + // B 8:0 + // 44-57 B 25:12 + // 67-68 C 4:3 + // 74-77 C 13:10 + // 79-83 C 19:15 + // 93-168 C 31:29 + // D 31:0 + // E 31:0 + // F 8:0 + // + void GPIO_EnableUnbondedIOPullupsFor100Pin() + { + EALLOW; + GpioCtrlRegs.GPAPUD.all = ~0xFFC003E3; //GPIOs 0-1, 5-9, 22-31 + GpioCtrlRegs.GPBPUD.all = ~0x03FFF1FF; //GPIOs 32-40, 44-57 + GpioCtrlRegs.GPCPUD.all = ~0xE10FBC18; //GPIOs 67-68, 74-77, 79-83, 93-95 + GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127 + GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFFF; //GPIOs 128-159 + GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168 + EDIS; + } + + // + // GPIO_EnableUnbondedIOPullups - InitSysCtrl would call this function + // this takes care of enabling IO pullups. + // + void GPIO_EnableUnbondedIOPullups() + { + // + //bits 8-10 have pin count + // + unsigned char pin_count = ((DevCfgRegs.PARTIDL.all & 0x00000700) >> 8) ; + + // + //5 = 100 pin + //6 = 176 pin + //7 = 337 pin + // + if(pin_count == 5) + { + GPIO_EnableUnbondedIOPullupsFor100Pin(); + } + else if (pin_count == 6) + { + GPIO_EnableUnbondedIOPullupsFor176Pin(); + } + else + { + //do nothing - this is 337 pin package + } + } + +#endif //CPU1 + +// +// GPIO_ReadPin - Read the GPyDAT register bit for the specified pin. Note that +// this returns the actual state of the pin, not the state of +// the output latch. +// +Uint16 GPIO_ReadPin(Uint16 gpioNumber) +{ + volatile Uint32 *gpioDataReg; + Uint16 pinVal; + + gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; + pinVal = (gpioDataReg[GPYDAT] >> (gpioNumber % 32)) & 0x1; + + return pinVal; +} + +// +// GPIO_WritePin - Set the GPyDAT register bit for the specified pin. +// +void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal) +{ + volatile Uint32 *gpioDataReg; + Uint32 pinMask; + + gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET; + pinMask = 1UL << (gpioNumber % 32); + + if (outVal == 0) + { + gpioDataReg[GPYCLEAR] = pinMask; + } + else + { + gpioDataReg[GPYSET] = pinMask; + } +} + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_I2C.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_I2C.c new file mode 100644 index 0000000000..d17266a9b0 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_I2C.c @@ -0,0 +1,301 @@ +//########################################################################### +// +// FILE: F2837xD_I2C.c +// +// TITLE: F2837xD I2C Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +//--------------------------------------------------------------------------- +// Example: I2cAGpioConfig(), I2cBGpioConfig() +//--------------------------------------------------------------------------- +// These functions configures GPIO pins to function as I2C pins +// +// Each GPIO pin can be configured as a GPIO pin or up to 3 different +// peripheral functional pins. By default all pins come up as GPIO +// inputs after reset. +// + +#ifdef CPU1 +// +// I2cAGpioConfig - Configure I2CA GPIOs +// 'I2caDataClkPin' should be assign with one of the +// possible I2C_A SDA - SDL GPIO pin Use defined Macros from +// "F2837xD_I2c_defines.h" for assignment +// +void I2cAGpioConfig(Uint16 I2caDataClkPin) +{ + EALLOW; + + switch(I2caDataClkPin) + { + case I2C_A_GPIO0_GPIO1: + + // + // Enable internal pull-up for the selected I2C pins + // Enable pull-up for GPIO0 (SDAA) + // Enable pull-up for GPIO1 (SDLA) + // + GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0; + GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0; + + // + // Set qualification for the selected I2C pins + // Async/no qualification (I/ps sync to SYSCLKOUT by default) + // + GpioCtrlRegs.GPAQSEL1.bit.GPIO0 = 3; + GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; + + // + // Configure which of the possible GPIO pins will be I2C_A pins + // using GPIO regs + // Configure GPIO0 for SDAA operation + // Configure GPIO0 for SDAA operation + // + GpioCtrlRegs.GPAGMUX1.bit.GPIO0 = 1; + GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 2; + + // + // Configure GPIO1 for SDLA operation + // Configure GPIO1 for SDLA operation + // + GpioCtrlRegs.GPAGMUX1.bit.GPIO1 = 1; + GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 2; + + break; + + case I2C_A_GPIO32_GPIO33: + // + // Enable internal pull-up for the selected I2C pins + // + GpioCtrlRegs.GPBPUD.bit.GPIO32 = 0; + GpioCtrlRegs.GPBPUD.bit.GPIO33 = 0; + + // + // Set qualification for the selected I2C pins + // + GpioCtrlRegs.GPBQSEL1.bit.GPIO32 = 3; + GpioCtrlRegs.GPBQSEL1.bit.GPIO33 = 3; + + // + // Configure which of the possible GPIO pins will be I2C_A pins + // using GPIO regs + // + GpioCtrlRegs.GPBMUX1.bit.GPIO32 = 1; + GpioCtrlRegs.GPBMUX1.bit.GPIO33 = 1; + + break; + + case I2C_A_GPIO42_GPIO43: + // + // Enable internal pull-up for the selected I2C pins + // + + // + // Set qualification for the selected I2C pins + // + + // + // Configure which of the possible GPIO pins will be I2C_A pins + // using GPIO regs + // + break; + + case I2C_A_GPIO91_GPIO92: + // + // Enable internal pull-up for the selected I2C pins + // + GpioCtrlRegs.GPCPUD.bit.GPIO91 = 0; + GpioCtrlRegs.GPCPUD.bit.GPIO92 = 0; + + // + // Set qualification for the selected I2C pins + // + GpioCtrlRegs.GPCQSEL2.bit.GPIO91 = 3; + GpioCtrlRegs.GPCQSEL2.bit.GPIO92 = 3; + + // + // Configure which of the possible GPIO pins will be I2C_A pins + // using GPIO regs + // + GpioCtrlRegs.GPCGMUX2.bit.GPIO91 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO91 = 2; + GpioCtrlRegs.GPCGMUX2.bit.GPIO92 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO92 = 2; + break; + + case I2C_A_GPIO63104_GPIO105: + // + // Enable internal pull-up for the selected I2C pins + // + + // + // Set qualification for the selected I2C pins + // + + // + // Configure which of the possible GPIO pins will be I2C_A pins + // using GPIO regs + // + break; + + default: + + break; + + } // End of Switch + EDIS; +} + +// +// I2cBGpioConfig - Configure I2CB GPIOs +// 'I2cbDataClkPin' should be assign with one of the possible +// I2C_B SDA - SDL GPIO pin Use defined Macros from +// "F2837xD_I2c_defines.h" for assignment +// +void I2cBGpioConfig(Uint16 I2cbDataClkPin) +{ + EALLOW; + + switch(I2cbDataClkPin) + { + case I2C_B_GPIO2_GPIO3: + // + // Enable internal pull-up for the selected I2C pins + // Enable pull-up for GPIO2 (SDAB) + // Enable pull-up for GPIO3 (SDLB) + // + GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0; + GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; + + // + // Set qualification for the selected I2C pins + // Async/no qualification (I/ps sync to SYSCLKOUT by default) + // + GpioCtrlRegs.GPAQSEL1.bit.GPIO2 = 3; + GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; + + // + // Configure which of the possible GPIO pins will be I2C_B pins + // using GPIO regs + // Configure GPIO2 for SDAB operation + // Configure GPIO3 for SDAB operation + // Configure GPIO1 for SDLB operation + // Configure GPIO1 for SDLB operation + // + GpioCtrlRegs.GPAGMUX1.bit.GPIO2 = 1; + GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 2; + + GpioCtrlRegs.GPAGMUX1.bit.GPIO3 = 1; + GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; + + break; + + case I2C_B_GPIO134_GPIO35: + // + // Enable internal pull-up for the selected I2C pins + // + + // + // Set qualification for the selected I2C pins + // + + // + // Configure which of the possible GPIO pins will be I2C_B pins + // using GPIO regs + // + break; + + case I2C_B_GPIO40_GPIO41: + // + // Enable internal pull-up for the selected I2C pins + // + + // + // Set qualification for the selected I2C pins + // + + // + // Configure which of the possible GPIO pins will be I2C_B pins + // using GPIO regs + // + break; + + case I2C_B_GPIO66_GPIO69: + // + // Enable internal pull-up for the selected I2C pins + // + GpioCtrlRegs.GPCPUD.bit.GPIO66 = 0; //SDAB + GpioCtrlRegs.GPCPUD.bit.GPIO69 = 0; //SCLB + + // + // Set qualification for the selected I2C pins + // + GpioCtrlRegs.GPCQSEL1.bit.GPIO66 = 3; + GpioCtrlRegs.GPCQSEL1.bit.GPIO69 = 3; + + // + // Configure which of the possible GPIO pins will be I2C_B pins + // using GPIO regs + // + GpioCtrlRegs.GPCGMUX1.bit.GPIO66 = 1; //0x6 + GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 2; + + GpioCtrlRegs.GPCGMUX1.bit.GPIO69 = 1; //0x6 + GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 2; + break; + + default: + break; + + } + EDIS; +} + +#endif + + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc.c new file mode 100644 index 0000000000..a58533c200 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc.c @@ -0,0 +1,216 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc.c +// +// TITLE: Inter-Processor Communication module support functions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" +#include + +// +// InitIpc - Initialize all IPC registers and clear all flags +// +void InitIpc() +{ + // + //Clear sent flags. Received flags must not be cleared locally + //to handle the case where the remote CPU starts executing first. + //In this case, a remote flag could be sent correctly and be + //incorrectly cleared by this function. Unfortunately, we're + //still left with a startup synchronization problem if the + //remote CPU has flags left over from a previous run. There's + //probably a better way of handling this. + // + IpcRegs.IPCCLR.all = 0xFFFFFFFF; + + // + //Clear commands + // + IpcRegs.IPCSENDCOM = 0; + IpcRegs.IPCSENDADDR = 0; + IpcRegs.IPCSENDDATA = 0; + IpcRegs.IPCLOCALREPLY = 0; + + // + //Clear boot status and pump semaphore + // + #if defined(CPU1) + IpcRegs.IPCBOOTMODE = 0; + #elif defined(CPU2) + IpcRegs.IPCBOOTSTS = 0; + #endif + ReleaseFlashPump(); +} + +// +// ReadIpcTimer - Read the current IPC timer value. The low register must be +// read first to latch a value in the high register. +// +unsigned long long ReadIpcTimer() +{ + Uint32 low, high; + + low = IpcRegs.IPCCOUNTERL; + high = IpcRegs.IPCCOUNTERH; + return ((unsigned long long)high << 32) | (unsigned long long)low; +} + +// +// SendIpcData - Copy data into the IPC send message RAM for this CPU and set +// a flag. If the specified 16-bit word length is greater than +// the size of the message RAM, the data is truncated. +// +void SendIpcData(void *data, Uint16 word_length, Uint16 flag) +{ + word_length = (word_length < MSG_RAM_SIZE) ? word_length : MSG_RAM_SIZE; + + memcpy(SEND_MSG_RAM, data, word_length); + + if (flag != NO_IPC_FLAG) + { + SendIpcFlag(flag); + } +} + +// +// RecvIpcData - Copy data out of the IPC receive message RAM for this CPU. If +// the specified 16-bit word length is greater than the size of +// the message RAM, the data is truncated. +// +void RecvIpcData(void *recv_buf, Uint16 word_length) +{ + word_length = (word_length < MSG_RAM_SIZE) ? word_length : MSG_RAM_SIZE; + memcpy(recv_buf, RECV_MSG_RAM, word_length); +} + +// +// FillIpcSendData - Fill the IPC send message RAM for this CPU with a constant +// value +// +void FillIpcSendData(Uint16 fill_data) +{ + memset(SEND_MSG_RAM, fill_data, MSG_RAM_SIZE); +} + +// +// SendIpcCommand - Write the send command, address, and data registers with +// the specified values, then set an IPC flag. +// +void SendIpcCommand(Uint32 command, Uint32 address, Uint32 data, Uint16 flag) +{ + IpcRegs.IPCSENDCOM = command; + IpcRegs.IPCSENDADDR = address; + IpcRegs.IPCSENDDATA = data; + + if (flag != NO_IPC_FLAG) + { + SendIpcFlag(flag); + } +} + +// +// SendIpcFlag - Set an IPC flag bit for the other CPU. Flags 0-3 will generate +// PIE interrupts. +// +void SendIpcFlag(Uint16 flag) +{ + IpcRegs.IPCSET.all = 1UL << flag; +} + +// +// AckIpcFlag - Acknowledge/clear a received IPC flag +// +void AckIpcFlag(Uint16 flag) +{ + IpcRegs.IPCACK.all = 1UL << flag; +} + +// +// CancelIpcFlag - Clear a sent IPC flag bit before the other CPU acknowledges +// it. You will normally never use this function. To clear a +// received flag, call AckIpcFlag() instead. +// +void CancelIpcFlag(Uint16 flag) +{ + IpcRegs.IPCCLR.all = 1UL << flag; +} + +// +// WaitForIpcFlag - Wait for any IPC flag in the specified mask to be set. +// WARNING: If you use this function to wait for an IPC +// interrupt, you must not clear the IPC flag in the interrupt +// handler. Otherwise, this function will never return. +// +void WaitForIpcFlag(Uint16 flag) +{ + // + //WARNING: Don't use this function to wait for an IPC interrupt! + // + while ((IpcRegs.IPCSTS.all & (1UL << flag)) == 0x00000000) {;} +} + +// +// WaitForIpcAck - Wait for any IPC flag in the specified mask to be +// acknowledged. +// +void WaitForIpcAck(Uint16 flag) +{ + while ((IpcRegs.IPCFLG.all & (1UL << flag)) != 0x00000000) {;} +} + +// +// IpcSync - Synchronize the two CPUs. Neither CPU will return from this +// function call before the other one enters it. Must be called with +// the same flag number on both CPUs. +// +void IpcSync(Uint16 flag) +{ + SendIpcFlag(flag); + WaitForIpcFlag(flag); + AckIpcFlag(flag); + WaitForIpcAck(flag); +} + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver.c new file mode 100644 index 0000000000..9b38efc7b5 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver.c @@ -0,0 +1,1702 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc_Driver.c +// +// TITLE: F2837xD Inter-Processor Communication (IPC) API Driver Functions. +// +// DESCRIPTION: +// 28x API functions for inter-processor communications between the +// two CPUs. The IPC functions require the usage of the CPU1 to CPU2 +// and CPU2 to CPU1 MSG RAM's to store the circular ring +// buffer and indexes. Commands can be queued up in order on a single +// IPC interrupt channel. For those IPC commands which are not +// interdependent, multiple IPC interrupt channels may be used. +// The driver functions in this file are available only as +// sample functions for application development. Due to the generic +// nature of these functions and the cycle overhead inherent to a +// function call, the code is not intended to be used in cases where +// maximum efficiency is required in a system. +// NOTE: This source code is used by both CPUs. That is both CPU1 and CPU2 +// Cores use this code. +// The active debug CPU will be referred to as Local CPU. +// When using this source code in CPU1, the term "local" +// will mean CPU1 and the term "remote" CPU will be mean CPU2. +// When using this source code in CPU2, the term "local" +// will mean CPU2 and the term "remote" CPU will be mean CPU1. +// +// The abbreviations LtoR and RtoL within the function names mean +// Local to Remote and Remote to Local respectively. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +//! \addtogroup ipc_driver_api +//! @{ +//***************************************************************************** +#include "F2837xD_device.h" +#include "F2837xD_Ipc_drivers.h" + +#if defined(CPU1) +#pragma DATA_SECTION(g_asIPCCPU1toCPU2Buffers, "PUTBUFFER"); +#pragma DATA_SECTION(g_usPutWriteIndexes, "PUTWRITEIDX"); +#pragma DATA_SECTION(g_usGetReadIndexes, "GETREADIDX"); + +#pragma DATA_SECTION(g_asIPCCPU2toCPU1Buffers, "GETBUFFER"); +#pragma DATA_SECTION(g_usGetWriteIndexes, "GETWRITEIDX"); +#pragma DATA_SECTION(g_usPutReadIndexes, "PUTREADIDX"); + +#elif defined(CPU2) + +#pragma DATA_SECTION(g_asIPCCPU2toCPU1Buffers, "PUTBUFFER"); +#pragma DATA_SECTION(g_usPutWriteIndexes, "PUTWRITEIDX"); +#pragma DATA_SECTION(g_usGetReadIndexes, "GETREADIDX"); + +#pragma DATA_SECTION(g_asIPCCPU1toCPU2Buffers, "GETBUFFER"); +#pragma DATA_SECTION(g_usGetWriteIndexes, "GETWRITEIDX"); +#pragma DATA_SECTION(g_usPutReadIndexes, "PUTREADIDX"); + +#endif + +// +// Global Circular Buffer Definitions +// +tIpcMessage g_asIPCCPU1toCPU2Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE]; +tIpcMessage g_asIPCCPU2toCPU1Buffers[NUM_IPC_INTERRUPTS][IPC_BUFFER_SIZE]; + +// +// Global Circular Buffer Index Definitions +// +uint16_t g_usPutWriteIndexes[NUM_IPC_INTERRUPTS]; +uint16_t g_usPutReadIndexes[NUM_IPC_INTERRUPTS]; +uint16_t g_usGetWriteIndexes[NUM_IPC_INTERRUPTS]; +uint16_t g_usGetReadIndexes[NUM_IPC_INTERRUPTS]; + +//***************************************************************************** +// +//! Initializes System IPC driver controller +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param usCPU2IpcInterrupt specifies the CPU2 IPC interrupt number used by +//! psController. +//! \param usCPU1IpcInterrupt specifies the CPU1 IPC interrupt number used by +//! psController. +//! +//! This function initializes the IPC driver controller with circular buffer +//! and index addresses for an IPC interrupt pair. The +//! \e usCPU2IpcInterrupt and \e usCPU1IpcInterrupt parameters can be one of +//! the following values: +//! \b IPC_INT0, \b IPC_INT1, \b IPC_INT2, \b IPC_INT3. +//! +//! \note If an interrupt is currently in use by an \e tIpcController instance, +//! that particular interrupt should not be tied to a second \e tIpcController +//! instance. +//! +//! \note For a particular usCPU2IpcInterrupt - usCPU1IpcInterrupt pair, there +//! must be an instance of tIpcController defined and initialized on both the +//! CPU1 and CPU2 systems. +//! +//! \return None. +// +//***************************************************************************** +void +IPCInitialize (volatile tIpcController *psController, + uint16_t usCPU2IpcInterrupt, uint16_t usCPU1IpcInterrupt) +{ +#if defined(CPU1) + // CPU1toCPU2PutBuffer and Index Initialization + psController->psPutBuffer = &g_asIPCCPU1toCPU2Buffers[usCPU2IpcInterrupt-1][0]; + psController->pusPutWriteIndex = &g_usPutWriteIndexes[usCPU2IpcInterrupt-1]; + psController->pusGetReadIndex = &g_usGetReadIndexes[usCPU1IpcInterrupt-1]; + psController->ulPutFlag = (uint32_t)(1 << (usCPU2IpcInterrupt - 1)); + + // CPU1toCPU2GetBuffer and Index Initialization + psController->psGetBuffer = &g_asIPCCPU2toCPU1Buffers[usCPU1IpcInterrupt-1][0]; + psController->pusGetWriteIndex = &g_usGetWriteIndexes[usCPU1IpcInterrupt-1]; + psController->pusPutReadIndex = &g_usPutReadIndexes[usCPU2IpcInterrupt-1]; +#elif defined(CPU2) + // CPU2toCPU1PutBuffer and Index Initialization + psController->psPutBuffer = &g_asIPCCPU2toCPU1Buffers[usCPU1IpcInterrupt-1][0]; + psController->pusPutWriteIndex = &g_usPutWriteIndexes[usCPU1IpcInterrupt-1]; + psController->pusGetReadIndex = &g_usGetReadIndexes[usCPU2IpcInterrupt-1]; + psController->ulPutFlag = (uint32_t)(1 << (usCPU1IpcInterrupt - 1)); + + // CPU1toCPU2GetBuffer and Index Initialization + psController->psGetBuffer = &g_asIPCCPU1toCPU2Buffers[usCPU2IpcInterrupt-1][0]; + psController->pusGetWriteIndex = &g_usGetWriteIndexes[usCPU2IpcInterrupt-1]; + psController->pusPutReadIndex = &g_usPutReadIndexes[usCPU1IpcInterrupt-1]; +#endif + // Initialize PutBuffer WriteIndex = 0 and GetBuffer ReadIndex = 0 + *(psController->pusPutWriteIndex) = 0; + *(psController->pusGetReadIndex) = 0; +} + +//***************************************************************************** +// +//! Writes a message into the PutBuffer. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param psMessage specifies the address of the \e tIpcMessage instance to be +//! written to PutBuffer. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a free slot (1= wait until free spot available, 0 = exit with +//! STATUS_FAIL if no free slot). +//! +//! This function checks if there is a free slot in the PutBuffer. If so, it +//! puts the message pointed to by \e psMessage into the free slot and +//! increments the WriteIndex. Then it sets the appropriate IPC interrupt flag +//! specified by \e psController->usPutFlag. The \e bBlock parameter can be +//! one of the following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return \b STATUS_FAIL if PutBuffer is full. \b STATUS_PASS if Put occurs +//! successfully. +// +//***************************************************************************** +uint16_t +IpcPut (volatile tIpcController *psController, tIpcMessage *psMessage, + uint16_t bBlock) +{ + uint16_t writeIndex; + uint16_t readIndex; + uint16_t returnStatus = STATUS_PASS; + + writeIndex = *(psController->pusPutWriteIndex); + readIndex = *(psController->pusPutReadIndex); + + // + // Wait until Put Buffer slot is free + // + while (((writeIndex + 1) & MAX_BUFFER_INDEX) == readIndex) + { + // + // If designated as a "Blocking" function, and Put buffer is full, + // return immediately with fail status. + // + if (!bBlock) + { + returnStatus = STATUS_FAIL; + break; + } + + readIndex = *(psController->pusPutReadIndex); + } + + if (returnStatus != STATUS_FAIL) + { + // + // When slot is free, Write Message to PutBuffer, update PutWriteIndex, + // and set the CPU IPC INT Flag + // + psController->psPutBuffer[writeIndex] = *psMessage; + + writeIndex = (writeIndex + 1) & MAX_BUFFER_INDEX; + *(psController->pusPutWriteIndex) = writeIndex; + + IpcRegs.IPCSET.all |= psController->ulPutFlag; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Reads a message from the GetBuffer. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param psMessage specifies the address of the \e tIpcMessage instance where +//! the message from GetBuffer should be written to. +//! \param bBlock specifies whether to allow function to block until GetBuffer +//! has a message (1= wait until message available, 0 = exit with STATUS_FAIL +//! if no message). +//! +//! This function checks if there is a message in the GetBuffer. If so, it gets +//! the message in the GetBuffer pointed to by the ReadIndex and writes it to +//! the address pointed to by \e psMessage. The \e bBlock parameter can be one +//! of the following +//! values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return \b STATUS_PASS if GetBuffer is empty. \b STATUS_FAIL if Get occurs +//! successfully. +// +//***************************************************************************** +uint16_t +IpcGet (volatile tIpcController *psController, tIpcMessage *psMessage, + uint16_t bBlock) +{ + uint16_t writeIndex; + uint16_t readIndex; + uint16_t returnStatus = STATUS_PASS; + + writeIndex = *(psController->pusGetWriteIndex); + readIndex = *(psController->pusGetReadIndex); + + // + // Loop while GetBuffer is empty + // + while (writeIndex == readIndex) + { + // + // If designated as a "Blocking" function, and Get buffer is empty, + // return immediately with fail status. + // + if (!bBlock) + { + returnStatus = STATUS_FAIL; + break; + } + + writeIndex = *(psController->pusGetWriteIndex); + } + + if (returnStatus != STATUS_FAIL) + { + // + // If there is a message in GetBuffer, Read Message and update + // the ReadIndex + // + *psMessage = psController->psGetBuffer[readIndex]; + + readIndex = (readIndex + 1) & MAX_BUFFER_INDEX; + *(psController->pusGetReadIndex) = readIndex; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Sends a command to read either a 16- or 32-bit data word from the remote +//! CPU +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU address to read from +//! \param pvData is a pointer to the 16/32-bit variable where read data will +//! be stored. +//! \param usLength designates 16- or 32-bit read (1 = 16-bit, 2 = 32-bit) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! \param ulResponseFlag indicates the remote CPU to the local CPU Flag +//! number mask used to report when the read data is available at pvData. +//! (\e ulResponseFlag MUST use IPC flags 17-32, and not 1-16) +//! +//! This function will allow the local CPU system to send a 16/32-bit data +//! read command to the remote CPU system and set a ResponseFlag to track the +//! status of the read. +//! The remote CPU will respond with a DataWrite command which will place +//! the data in the local CPU address pointed to by \e pvData. When the local +//! CPU receives the DataWrite command and writes the read data into \e *pvData location, +//! it will clear the ResponseFlag, indicating to the rest of the system that +//! the data is ready. The \e usLength parameter can be one of the +//! following values: \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e +//! bBlock parameter can be one of the following values: \b ENABLE_BLOCKING or +//! \b DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRDataRead (volatile tIpcController *psController, uint32_t ulAddress, + void *pvData, uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag) +{ + + uint16_t status; + tIpcMessage sMessage; + + // + // Set up read command, address, dataw1 = ResponseFlag | word length, + // dataw2 = address where word + // should be written to when returned. + // + sMessage.ulcommand = IPC_DATA_READ; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (ulResponseFlag & 0xFFFF0000)|(uint32_t)usLength; + sMessage.uldataw2 = (uint32_t)pvData; + + // + // Set ResponseFlag (cleared once data is read into address at pvData) + // Put Message into PutBuffer and set IPC INT flag + // + IpcRegs.IPCSET.all |= (ulResponseFlag & 0xFFFF0000); + status = IpcPut (psController, &sMessage, bBlock); + + return status; + + // + //Note: Read Response will have sMessage.ulcommand = IPC_DATA_WRITE + // sMessage.uladdress = (uint32_t) pvData + // sMessage.uldataw1 = ulStatusFlag | + // (uint32_t) usLength; + // sMessage.uldataw2 = word to be read into + // pvData address. + // +} + +//***************************************************************************** +// +//! Sends the command to read either a 16- or 32-bit data word from remote +//! CPU system address to a write-protected local CPU address. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU address to read from +//! \param pvData is a pointer to the 16/32-bit variable where read data will +//! be stored. +//! \param usLength designates 16- or 32-bit read (1 = 16-bit, 2 = 32-bit) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! \param ulResponseFlag indicates the local CPU to remote CPU Flag number +//! mask used to report when the read data is available at pvData. +//! (\e ulResponseFlag MUST use IPC flags 17-32, and not 1-16) +//! +//! This function will allow the local CPU system to send a 16/32-bit data +//! read command to the remote CPU system and set a ResponseFlag to track the +//! status of the read. +//! The remote CPU system will respond with a DataWrite command which will +//! place the data in the local CPU address pointed to by \e pvData. +//! When the local CPU receives the DataWrite command and writes the read data +//! into \e *pvData location, it will clear the ResponseFlag, indicating to +//! the rest of the system that the data is ready. The \e usLength parameter +//! can be one of the following values: \b IPC_LENGTH_16_BITS or +//! \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be one of the following +//! values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRDataRead_Protected (volatile tIpcController *psController, + uint32_t ulAddress, void *pvData, uint16_t usLength, + uint16_t bBlock, + uint32_t ulResponseFlag) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up read command, address, dataw1 = ResponseFlag | word length, dataw2 + // = address where word should be written to when returned. + // + sMessage.ulcommand = IPC_DATA_READ_PROTECTED; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (ulResponseFlag & 0xFFFF0000)|(uint32_t)usLength; + sMessage.uldataw2 = (uint32_t)pvData; + + // + // Set ResponseFlag (cleared once data is read into address at pvData) + // Put Message into PutBuffer and set IPC INT flag + // + IpcRegs.IPCSET.all |= (ulResponseFlag & 0xFFFF0000); + status = IpcPut (psController, &sMessage, bBlock); + + return status; + // + // Note: Read Response will have sMessage.ulcommand = IPC_DATA_WRITE + // sMessage.uladdress = (uint32_t) pvData + // sMessage.uldataw1 = ulStatusFlag | + // (uint32_t) usLength; + // sMessage.uldataw2 = word to be read into + // pvData address. + // +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16-bit data word at the remote CPU system +//! address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU address to write to +//! \param ulMask specifies the 16/32-bit mask for bits which should be set at +//! \e ulAddress. +//! 16-bit masks should fill the lower 16-bits (upper 16-bits will be all +//! 0x0000). +//! \param usLength specifies the length of the bit mask (1=16-bits, 2=32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to set bits specified by the +//! \e ulMask variable in a 16/32-bit word on the remote CPU system. The \e +//! usLength parameter can be one of the following values: \b IPC_LENGTH_16_BITS +//! or \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be one of the +//! following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRSetBits(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up set bits command, address, dataw1 = word length, dataw2 = + // 16/32-bit mask + // + sMessage.ulcommand = IPC_SET_BITS; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (uint32_t)usLength; + sMessage.uldataw2 = ulMask; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} +//***************************************************************************** +// +//! Sets the designated bits in a 16-bit write-protected data word at the +//! remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU address to write to +//! \param ulMask specifies the 16/32-bit mask for bits which should be set at +//! \e ulAddress. 16-bit masks should fill the lower 16-bits (upper 16-bits +//! will be all 0x0000). +//! \param usLength specifies the length of the bit mask (1=16-bits, 2=32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to set bits specified by the +//! \e ulMask variable in a write-protected 16/32-bit word on the remote CPU +//! system. The \e usLength parameter can be one of the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be +//! one of the following values: +//! \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRSetBits_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, uint16_t usLength, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up set bits command, address, dataw1 = word length, dataw2 = + // 16/32-bit mask + // + sMessage.ulcommand = IPC_SET_BITS_PROTECTED; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (uint32_t)usLength; + sMessage.uldataw2 = ulMask; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Clears the designated bits in a 16-bit data word at the remote CPU system +//! address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU address to write to +//! \param ulMask specifies the 16/32-bit mask for bits which should be cleared +//! at \e ulAddress. 16-bit masks should fill the lower 16-bits (upper 16-bits +//! will be all 0x0000). +//! \param usLength specifies the length of the bit mask (1=16-bits, 2=32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to clear bits specified by +//! the \e ulMask variable in a 16/32-bit word on the remote CPU system. The \e +//! usLength parameter can be one of the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be +//! one of the following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRClearBits(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up clear bits command, address, dataw1 = word length, dataw2 = + // 16/32-bit mask + // + sMessage.ulcommand = IPC_CLEAR_BITS; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (uint32_t)usLength; + sMessage.uldataw2 = ulMask; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Clears the designated bits in a 16-bit write-protected data word at +//! remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the secondary CPU address to write to +//! \param ulMask specifies the 16/32-bit mask for bits which should be cleared +//! at \e ulAddress. 16-bit masks should fill the lower 16-bits (upper 16-bits +//! will be all 0x0000). +//! \param usLength specifies the length of the bit mask (1=16-bits, 2=32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to set bits specified by the +//! \e ulMask variable in a write-protected 16/32-bit word on the remote CPU +//! system. The \e usLength parameter can be one of the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter can be +//! one of the following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRClearBits_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength, uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up clear bits command, address, dataw1 = word length, dataw2 = + // 16/32-bit mask + // + sMessage.ulcommand = IPC_CLEAR_BITS_PROTECTED; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (uint32_t)usLength; + sMessage.uldataw2 = ulMask; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to the remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote cpu address to write to +//! \param ulData specifies the 16/32-bit word which will be written. +//! For 16-bit words, only the lower 16-bits of ulData will be considered by +//! the master system. +//! \param usLength is the length of the word to write (1 = 16-bits, 2 = +//! 32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! \param ulResponseFlag is used to pass the \e ulResponseFlag back to the +//! remote cpu only when this function is called in response to \e +//! IPCMtoCDataRead(). Otherwise, set to 0. +//! +//! This function will allow the local CPU system to write a 16/32-bit word +//! via the \e ulData variable to an address on the remote CPU system. +//! The \e usLength parameter can be one of the following values: +//! \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter +//! can be one of the following values: \b ENABLE_BLOCKING or \b +//! DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRDataWrite(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulData, uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up write command, address, dataw1 = ResponseFlag | word length, + // dataw2 = data to write + // + sMessage.ulcommand = IPC_DATA_WRITE; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ulResponseFlag |(uint32_t)usLength; + sMessage.uldataw2 = ulData; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to a write-protected remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the write-protected remote CPU address to +//! write to +//! \param ulData specifies the 16/32-bit word which will be written. For +//! 16-bit words, only the lower 16-bits of ulData will be considered by the +//! master system. +//! \param usLength is the length of the word to write (1 = 16-bits, 2 = +//! 32-bits) +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! \param ulResponseFlag is used to pass the \e ulResponseFlag back to the +//! remote CPU only when this function is called in response to \e +//! IPCMtoCDataRead(). Otherwise, set to 0. +//! +//! This function will allow the local CPU system to write a 16/32-bit word +//! via the \e ulData variable to a write-protected address on the remote CPU +//! system. The \e usLength parameter can be one of the following values: +//! \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter +//! can be one of the following values: \b ENABLE_BLOCKING or \b +//! DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - +//! \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRDataWrite_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulData, + uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up write command, address, dataw1 = ResponseFlag | word length, + // dataw2 = data to write + // + sMessage.ulcommand = IPC_DATA_WRITE_PROTECTED; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ulResponseFlag |(uint32_t)usLength; + sMessage.uldataw2 = ulData; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Sends the command to read a block of data from remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU memory block starting address +//! to read from. +//! \param ulShareAddress specifies the local CPU shared memory address the +//! read block will read to. +//! \param usLength designates the block size in 16-bit words. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! \param ulResponseFlag indicates the local CPU to remote CPU Flag number +//! mask used to report when the read block data is available starting at +//! /e ulShareAddress. (\e ulResponseFlag MUST use IPC flags 17-32, and not +//! 1-16) +//! +//! This function will allow the local CPU system to send a read block +//! command to the remote CPU system and set a ResponseFlag to track the status +//! of the read. The remote CPU system will process the read and place the data +//! in shared memory at the location specified in the \e ulShareAddress +//! parameter and then clear the ResponseFlag, indicating that the block is +//! ready. The \e bBlock parameter can be one of the following values: \b +//! ENABLE_BLOCKING or \b DISABLE_BLOCKING. The \e ulResponseFlag parameter can +//! be any single one of the flags \b IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRBlockRead(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulShareAddress, uint16_t usLength, uint16_t bBlock, + uint32_t ulResponseFlag) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up block read command, address, dataw1 = ResponseFlag | block length, + // dataw2 = remote CPU address in shared memory + // where block data should be read to + // (corresponding to local CPU ulShareAddress). + // + sMessage.ulcommand = IPC_BLOCK_READ; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = (ulResponseFlag & 0xFFFF0000) |(uint32_t)usLength; + sMessage.uldataw2 = ulShareAddress; + + // + // Set ResponseFlag (cleared once data is read into Share Address location) + // Put Message into PutBuffer and set IPC INT flag + // + IpcRegs.IPCSET.all |= (ulResponseFlag & 0xFFFF0000); + status = IpcPut (psController, &sMessage, bBlock); + + return status; + // + // Note: Read Block Response will occur in processing of ReadBlock (since + // remote CPU has access to shared memory) + // +} + +//***************************************************************************** +// +//! Writes a block of data to remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU memory block starting address +//! to write to. +//! \param ulShareAddress specifies the local CPU shared memory address where +//! data to write from resides. +//! \param usLength designates the block size in 16- or 32-bit words (depends +//! on \e usWordLength). +//! \param usWordLength designates the word size (16-bits = 1 or 32-bits = 2). +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to write a block of data to +//! the remote CPU system starting from the location specified by the +//! \e ulAdress parameter. Prior to calling this function, the local CPU +//! system code should place the data to write in shared memory starting at /e +//! ulShareAddress. +//! The \e usWordLength parameter can be one of the following values: +//! \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter +//! can be one of the following values: \b ENABLE_BLOCKING or \b +//! DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \note If the shared SARAM blocks are used to pass the RAM block between the +//! processors, the IPCReqMemAccess() function must be called first in order to +//! give the slave CPU write access to the shared memory block(s). +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRBlockWrite(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulShareAddress, uint16_t usLength, + uint16_t usWordLength, uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up block write command, address, dataw1 = block length, + // dataw2 = remote CPU shared mem address + // where write data resides + // + sMessage.ulcommand = IPC_BLOCK_WRITE; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ((uint32_t)(usWordLength)<<16) + (uint32_t)usLength; + sMessage.uldataw2 = ulShareAddress; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Writes a block of data to a write-protected remote CPU system address +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the write-protected remote CPU block starting +//! address to write to. +//! \param ulShareAddress specifies the local CPU shared memory address where +//! data to write from resides. +//! \param usLength designates the block size in 16- or 32-bit words (depends +//! on \e usWordLength). +//! \param usWordLength designates the word size (16-bits = 1 or 32-bits = 2). +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to write a block of data to +//! a write-protected region on the remote CPU system starting from the +//! location specified by the \e ulAdress parameter. Prior to calling this +//! function, the local CPU system code should place the data to write in +//! shared memory starting at /e ulShareAddress. +//! The \e usWordLength parameter can be one of the following values: +//! \b IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e bBlock parameter +//! can be one of the following values: \b ENABLE_BLOCKING or \b +//! DISABLE_BLOCKING. +//! The \e ulResponseFlag parameter can be any single one of the flags \b +//! IPC_FLAG16 - \b IPC_FLAG31 or \b NO_FLAG. +//! +//! \note If the shared SARAM blocks are used to pass the RAM block between the +//! processors, the IPCReqMemAccess() function must be called first in order to +//! give the the slave CPU write access to the shared memory block(s). +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRBlockWrite_Protected(volatile tIpcController *psController, + uint32_t ulAddress, uint32_t ulShareAddress, + uint16_t usLength, uint16_t usWordLength, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up block write command, address, dataw1 = block length, + // dataw2 = remote CPU shared mem address + // where write data resides + // + sMessage.ulcommand = IPC_BLOCK_WRITE_PROTECTED; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ((uint32_t)(usWordLength)<<16) + (uint32_t)usLength; + sMessage.uldataw2 = ulShareAddress; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Calls remote CPU function with 1 optional parameter . +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulAddress specifies the remote CPU function address +//! \param ulParam specifies the 32-bit optional parameter value. If not used, +//! this can be a dummy value. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to call a function on the +//! remote CPU. The \e ulParam variable is a single optional 32-bit parameter +//! to pass to the function. The \e bBlock parameter can be one of the +//! following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRFunctionCall(volatile tIpcController *psController, uint32_t ulAddress, + uint32_t ulParam, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Set up function call command, address, dataw1 = 32-bit parameter + // + sMessage.ulcommand = IPC_FUNC_CALL; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ulParam; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +//***************************************************************************** +// +//! Sends generic message to remote CPU system +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulCommand specifies 32-bit command word to insert into message. +//! \param ulAddress specifies 32-bit address word to insert into message. +//! \param ulDataW1 specifies 1st 32-bit data word to insert into message. +//! \param ulDataW2 specifies 2nd 32-bit data word to insert into message. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the local CPU system to send a generic message to +//! the remote CPU system. Note that the user should create a corresponding +//! function on the remote CPU side to interpret/use the message or fill +//! parameters in such a way that the existing IPC drivers can recognize the +//! command and properly process the message. +//! The \e bBlock parameter can be one of the following values: \b +//! ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCLtoRSendMessage(volatile tIpcController *psController, uint32_t ulCommand, + uint32_t ulAddress, uint32_t ulDataW1, uint32_t ulDataW2, + uint16_t bBlock) +{ + uint16_t status; + tIpcMessage sMessage; + + // + // Package message to send + // + sMessage.ulcommand = ulCommand; + sMessage.uladdress = ulAddress; + sMessage.uldataw1 = ulDataW1; + sMessage.uldataw2 = ulDataW2; + + // + // Put Message into PutBuffer and set IPC INT flag + // + status = IpcPut (psController, &sMessage, bBlock); + return status; +} + +#if defined (CPU2) +//***************************************************************************** +// +//! Slave CPU Configures master R/W/Exe Access to Shared SARAM. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param ulMask specifies the 32-bit mask for the GSxMSEL RAM control +//! register to indicate which GSx SARAM blocks the slave CPU is requesting +//! master access to. +//! \param usMaster specifies whether the CPU1 or CPU2 are given +//! master access to the GSx blocks. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the slave CPU system to configure master R/W/Exe +//! access to the GSx SARAM blocks specified by the /e ulMask parameter. The +//! function calls the \e IPCSetBits_Protected() or \e +//! IPCClearBits_Protected() functions, and therefore in the master CPU +//! application code, the corresponding functions should be called. +//! The \e bBlock parameter can be one of the following values: \b +//! ENABLE_BLOCKING or \b DISABLE_BLOCKING. The \e usMaster parameter can be +//! either: \b IPC_GSX_CPU2_MASTER or \b IPC_GSX_CPU1_MASTER. The \e ulMask +//! parameter can be any of the options: \b S0_ACCESS - \b S7_ACCESS. +//! +//! \return status of command (\b STATUS_PASS =success, \b STATUS_FAIL = error +//! because PutBuffer was full, command was not sent) +// +//***************************************************************************** +uint16_t +IPCReqMemAccess (volatile tIpcController *psController, uint32_t ulMask, + uint16_t usMaster, uint16_t bBlock) +{ + uint16_t status = STATUS_PASS; + uint32_t GSxMSEL_REGaddress = (uint32_t)(&MemCfgRegs.GSxMSEL.all); + + if (usMaster == IPC_GSX_CPU2_MASTER) + { + if ((MemCfgRegs.GSxMSEL.all & ulMask) != ulMask) + { + status = + IPCLtoRSetBits_Protected (psController, GSxMSEL_REGaddress, + ulMask, IPC_LENGTH_32_BITS, + bBlock); + } + } + else if (usMaster == IPC_GSX_CPU1_MASTER) + { + if ((MemCfgRegs.GSxMSEL.all & ulMask) != 0) + { + status = + IPCLtoRClearBits_Protected (psController, GSxMSEL_REGaddress, + ulMask, IPC_LENGTH_32_BITS, + bBlock); + } + } + + return status; +} +#endif + +//***************************************************************************** +// +//! Responds to 16/32-bit data word write command the remote CPU system +//! +//! \param psMessage specifies the pointer to the message received from remote +//! CPU system which includes the 16/32-bit data word to write to the local CPU +//! address. +//! +//! This function will allow the local CPU system to write a 16/32-bit word +//! received from the remote CPU system to the address indicated in \e +//! *psMessage. In the event that the IPC_DATA_WRITE command was received as a +//! result of an IPC_DATA_READ command, this function will also clear the IPC +//! response flag tracking the read so other threads in the local CPU system +//! will be aware that the data is ready. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLDataWrite(tIpcMessage *psMessage) +{ + // + // Data word length = dataw1 (15:0), responseFlag = valid only for IPC + // flags 17-32 + // + uint16_t length = (uint16_t) psMessage->uldataw1; + uint32_t responseFlag = (psMessage->uldataw1) & 0xFFFF0000; + + // + // Write 16/32-bit word to address + // + if (length == IPC_LENGTH_16_BITS) + { + *(uint16_t *)(psMessage->uladdress) = (uint16_t)psMessage->uldataw2; + } + else if (length == IPC_LENGTH_32_BITS) + { + *(uint32_t *)(psMessage->uladdress) = psMessage->uldataw2; + } + + // + // If data write command is in response to a data read command from remote + // CPU to local CPU clear ResponseFlag, indicating read data from remote + // CPU is ready. + // + IpcRegs.IPCCLR.all |= responseFlag; +} + +//***************************************************************************** +// +//! Responds to 16/32-bit write-protected data word write command from +//! secondary CPU system +//! +//! \param psMessage specifies the pointer to the message received from the +//! secondary CPU system which includes the 16/32-bit data word to write to the +//! local CPU address. +//! +//! This function will allow the local CPU system to write a 16/32-bit word +//! received from the secondary CPU system to the write-protected address +//! indicated in \e *psMessage. +//! In the event that the IPC_DATA_WRITE_PROTECTED command was received as a +//! result of an IPC_DATA_READ_PROTECTED command, this function will also clear +//! the IPC response flag tracking the read so other threads in the local CPU +//! will be aware that the data is ready. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLDataWrite_Protected(tIpcMessage *psMessage) +{ + // + // Data word length = dataw1 (15:0), responseFlag = valid only for IPC + // flags 17-32 + // + uint16_t length = (uint16_t) psMessage->uldataw1; + uint32_t responseFlag = (psMessage->uldataw1) & 0xFFFF0000; + + // + // Allow access to EALLOW-protected registers. + // + EALLOW; + + // + // Write 16/32-bit word to EALLOW-protected address + // + if (length == IPC_LENGTH_16_BITS) + { + *(uint16_t *)(psMessage->uladdress) = (uint16_t)psMessage->uldataw2; + } + else if (length == IPC_LENGTH_32_BITS) + { + *(uint32_t *)(psMessage->uladdress) = psMessage->uldataw2; + } + + // + // Disable access to EALLOW-protected registers. + // + EDIS; + + // + // If data write command is in response to a data read command from local + // CPU to remote CPU, clear ResponseFlag, indicating read data from + // secondary CPU is ready + // + IpcRegs.IPCCLR.all |= responseFlag; +} + +//***************************************************************************** +// +//! Responds to 16/32-bit data word read command from remote CPU system. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the remote CPU system to read a 16/32-bit data +//! word at the local CPU address specified in /e psMessage, and send a Write +//! command with the read data back to the local CPU system. It will also send +//! the Response Flag used to track the read back to the remote CPU. +//! The \e bBlock parameter can be one of the following values: \b +//! ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLDataRead(volatile tIpcController *psController, tIpcMessage *psMessage, + uint16_t bBlock) +{ + unsigned long ulReaddata; + uint16_t usLength; + + // + // If data word length = 16-bits, read the 16-bit value at the given + // address and cast as 32-bit word to send back to remote CPU. + // If data word length = 32-bits, read the 32-bit value at the given + // address. + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + ulReaddata = (unsigned long)(*(volatile uint16_t *)psMessage->uladdress); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + ulReaddata = *(unsigned long *)psMessage->uladdress; + } + + // + // Send a Write command to write the requested data to the remote CPU read + // into address. + // psMessage->uldataw2 contains remote CPU address where readdata will be + // written. + // psMessage->uldataw1 contains the read response flag in IPC flag 17-32. + // + IPCLtoRDataWrite(psController, psMessage->uldataw2, ulReaddata, usLength, + bBlock,(psMessage->uldataw1 & 0xFFFF0000)); +} + +//***************************************************************************** +// +//! Responds to 16/32-bit data word read command from remote CPU system. +//! to read into a write-protected word on the remote CPU system. +//! +//! \param psController specifies the address of a \e tIpcController instance +//! used to store information about the "Put" and "Get" circular buffers and +//! their respective indexes. +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! \param bBlock specifies whether to allow function to block until PutBuffer +//! has a slot (1= wait until slot free, 0 = exit with STATUS_FAIL if no slot). +//! +//! This function will allow the remote CPU system to read a 16/32-bit data +//! word at the local CPU address specified in /e psMessage, and send a Write +//! Protected command with the read data back to the remote CPU system at a +//! write protected address. It will also send the Response Flag used to track +//! the read back to the remote CPU. The \e bBlock parameter can be one of the +//! following values: \b ENABLE_BLOCKING or \b DISABLE_BLOCKING. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLDataRead_Protected(volatile tIpcController *psController, + tIpcMessage *psMessage, uint16_t bBlock) +{ + unsigned long ulReaddata; + uint16_t usLength; + + // + // If data word length = 16-bits, read the 16-bit value at the given + // address and cast as 32-bit word to send back to remote CPU. + // If data word length = 32-bits, read the 32-bit value at the given + // address. + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + ulReaddata = (unsigned long)(*(volatile uint16_t *)psMessage->uladdress); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + ulReaddata = *(unsigned long *)psMessage->uladdress; + } + + // + // Send a Write command to write the requested data to the remote CPU read + // into address. + // psMessage->uldataw2 contains remote CPU address where readdata will be + // written. + // psMessage->uldataw1 contains the read response flag in IPC flag 17-32. + // + IPCLtoRDataWrite_Protected(psController, psMessage->uldataw2, ulReaddata, + usLength, bBlock, + (psMessage->uldataw1 & 0xFFFF0000)); +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit data word at a local CPU system +//! address +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will allow the remote CPU system to set the bits in a +//! 16/32-bit word on the local CPU system via a local CPU address and mask +//! passed in via the \e psMessage. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLSetBits(tIpcMessage *psMessage) +{ + uint16_t usLength; + + // + // Determine length of word at psMessage->uladdress and then set bits based + // on either the 16-bit or 32-bit bit-mask in psMessage->uldataw2. + // (16-bit length ignores upper 16-bits of psMessage->uldataw2) + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + *(volatile uint16_t*)psMessage->uladdress |= + (uint16_t) psMessage->uldataw2; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + *(volatile unsigned long *)psMessage->uladdress |= psMessage->uldataw2; + } +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit write-protected data word at a +//! local CPU system address +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will allow the remote CPU system to set the bits in a write- +//! protected 16/32-bit word on the local CPU system via a local CPU address +//! and mask passed in via the \e psMessage. +//! +//! \return None +// +//***************************************************************************** +void +IPCRtoLSetBits_Protected(tIpcMessage *psMessage) +{ + uint16_t usLength; + + // + // Allow access to EALLOW-protected registers. + // + EALLOW; + + // + // Determine length of word at psMessage->uladdress and then set bits based + // on either the 16-bit or 32-bit bit-mask in psMessage->uldataw2. + // (16-bit length ignores upper 16-bits of psMessage->uldataw2) + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + *(volatile uint16_t*)psMessage->uladdress |= + (uint16_t) psMessage->uldataw2; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + *(volatile unsigned long *)psMessage->uladdress |= psMessage->uldataw2; + } + + // + // Disable access to EALLOW-protected registers. + // + EDIS; +} + +//***************************************************************************** +// +//! Clears the designated bits in a 32-bit data word at a local CPU system +//! address +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will allow the remote CPU system to clear the bits in a +//! 16/32-bit word on the local CPU system via a local CPU address and mask +//! passed in via the \e psMessage. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLClearBits(tIpcMessage *psMessage) +{ + uint16_t usLength; + + // + // Determine length of word at psMessage->uladdress and then clear bits + // based on + // either the 16-bit or 32-bit bit-mask in psMessage->uldataw2. + // (16-bit length ignores upper 16-bits of psMessage->uldataw2) + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + *(volatile uint16_t*)psMessage->uladdress &= + ~((uint16_t) psMessage->uldataw2); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + *(volatile unsigned long *)psMessage->uladdress &= + ~(psMessage->uldataw2); + } +} + +//***************************************************************************** +// +//! Clears the designated bits in a write-protected 16/32-bit data word at a +//! local CPU system address +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will allow the secondary CPU system to clear the bits in a +//! 16/32-bit write-protected word on the local CPU system via a local +//! CPU address and mask passed in via the \e psMessage. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLClearBits_Protected(tIpcMessage *psMessage) +{ + uint16_t usLength; + + // + // Allow access to EALLOW-protected registers. + // + EALLOW; + + // + // Determine length of word at psMessage->uladdress and then clear bits + // based on + // either the 16-bit or 32-bit bit-mask in psMessage->uldataw2. + // (16-bit length ignores upper 16-bits of psMessage->uldataw2) + // + usLength = (uint16_t)psMessage->uldataw1; + + if (usLength == IPC_LENGTH_16_BITS) + { + *(volatile uint16_t*)psMessage->uladdress &= + ~((uint16_t) psMessage->uldataw2); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + *(volatile unsigned long *)psMessage->uladdress &= + ~(psMessage->uldataw2); + } + + // + // Disable access to EALLOW-protected registers. + // + EDIS; +} + +//***************************************************************************** +// +//! Reads a block of data from a remote CPU system address and stores into +//! shared RAM +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will respond to the remote CPU system request to read a block +//! of data from the local control system, by reading the data and placing that +//! data into the shared RAM location specified in \e psMessage. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLBlockRead(tIpcMessage *psMessage) +{ + + uint16_t usLength; + volatile uint16_t* pusRAddress; + volatile uint16_t* pusWAddress; + uint16_t usIndex; + + pusRAddress = (volatile uint16_t *)psMessage->uladdress; + pusWAddress = (volatile uint16_t *)psMessage->uldataw2; + usLength = (uint16_t)psMessage->uldataw1; + + for (usIndex=0; usIndexuldataw1 & 0xFFFF0000); +} + +//***************************************************************************** +// +//! Writes a block of data to a local CPU system address from shared RAM +//! +//! \param psMessage specifies the pointer to the message received from the +//! remote CPU system. +//! +//! This function will write a block of data to an address on the local CPU +//! system. +//! The data is first written by the remote CPU to shared RAM. This function +//! reads the shared RAM location, word size (16- or 32-bit), and block size +//! from \e psMessage and writes the block to the local address specified +//! in \e psMessage. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLBlockWrite(tIpcMessage *psMessage) +{ + uint16_t usLength; + uint16_t usWLength; + uint16_t usIndex; + + usLength = (uint16_t)psMessage->uldataw1; + usWLength = (uint16_t)((psMessage->uldataw1)>>16); + + // + // Determine data word access size to write to data block. + // + if (usWLength == IPC_LENGTH_16_BITS) + { + volatile uint16_t *pusWAddress = (volatile uint16_t *)psMessage->uladdress; + volatile uint16_t *pusRAddress = (volatile uint16_t *)psMessage->uldataw2; + for (usIndex=0; usIndexuladdress; + volatile unsigned long *pulRAddress = + (volatile unsigned long *)psMessage->uldataw2; + + for (usIndex=0; usIndexuldataw1; + usWLength = (uint16_t)((psMessage->uldataw1)>>16); + + // + // Determine data word access size to write to data block. + // (Writes registers accessible via APB bus must be 32-bits wide) + // + if (usWLength == IPC_LENGTH_16_BITS) + { + volatile uint16_t *pusWAddress = (volatile uint16_t *)psMessage->uladdress; + volatile uint16_t *pusRAddress = (volatile uint16_t *)psMessage->uldataw2; + for (usIndex=0; usIndexuladdress; + volatile unsigned long *pulRAddress = + (volatile unsigned long *)psMessage->uldataw2; + + for (usIndex=0; usIndexuladdress; + func_call(psMessage->uldataw1); +} + +//***************************************************************************** +// Close the Doxygen group. +//! @} +//***************************************************************************** + + diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Lite.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Lite.c new file mode 100644 index 0000000000..9f8dc61c9c --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Lite.c @@ -0,0 +1,1302 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc_Driver_Lite.c +// +// TITLE: F2837xD Inter-Processor Communication (IPC) Lite API Driver +// Functions. +// +// DESCRIPTION: +// API functions for inter-processor communications between +// CPU1 control system and CPU2 control system (Lite version). The IPC +// Lite functions only allow for basic functions such as data writes, +// reads, bit setting, and bit clearing. The Lite functions do not +// require the usage of the MSG RAM's or shared memories and can only +// be used with a single IPC interrupt channel. Commands can only +// be processed one at a time without queuing. +// The driver functions in this file are available only as +// sample functions for application development. Due to the generic +// nature of these functions and the cycle overhead inherent to a +// function call, the code is not intended to be used in cases where +// maximum efficiency is required in a system. +// +// NOTE: This source code is used by both CPUs. That is both CPU1 and CPU2 +// cores use this code. +// The active debug CPU will be referred to as Local CPU and the other +// CPU will be referred to as Remote CPU. +// When using this source code in CPU1, the term "local" +// will mean CPU1 and the term "remote" CPU will be mean CPU2. +// When using this source code in CPU2, the term "local" +// will mean CPU2 and the term "remote" CPU will be mean CPU1. +// +// The abbreviations LtoR and RtoL within the function names mean +// Local to Remote and Remote to Local respectively. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +//! \addtogroup ipc_lite_api IPC-Lite API Drivers +//! @{ +//***************************************************************************** +#include "F2837xD_device.h" +#include "F2837xD_Ipc_drivers.h" + +// +// Function Prototypes +// +void DelayLoop (void); + +//***************************************************************************** +// +//! Reads single word data result of Local to Remote IPC command +//! +//! \param pvData is a pointer to the 16/32-bit variable where the result data +//! will be stored. +//! \param usLength designates 16- or 32-bit read. +//! \param ulStatusFlag indicates the Local to Remote CPU Flag number mask used +//! to report the status of the command sent back from the Remote CPU. If +//! a status flag was not used with the command call, set this parameter to 0. +//! +//! Allows the caller to read the 16/32-bit data result of non-blocking IPC +//! functions from the IPCREMOTEREPLY register if the status flag is cleared +//! indicating the IPC command was successfully interpreted. If the status flag +//! is not cleared, the command was not recognized, and the function will +//! return STATUS_FAIL. To determine what data is read from a call to this +//! function, see the descriptions of the non-blocking IPC functions. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +//! The function returns \b STATUS_PASS or \b STATUS_FAIL. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRGetResult (void *pvData, uint16_t usLength, uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // If Remote System never acknowledged Status Task, indicates command + // failure. + // + if (IpcRegs.IPCFLG.all & ulStatusFlag) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Read data. + // + if (usLength == IPC_LENGTH_16_BITS) + { + *(uint16_t *)pvData = IpcRegs.IPCREMOTEREPLY; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + *(uint32_t *)pvData = IpcRegs.IPCREMOTEREPLY; + } + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Reads either a 16- or 32-bit data word from the remote CPU System address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the remote address to read from +//! \param usLength designates 16- or 32-bit read (1 = 16-bit, 2 = 32-bit) +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the remote system. +//! +//! This function will allow the Local CPU System to read 16/32-bit data from +//! the Remote CPU System into the IPCREMOTEREPLY register. After calling this +//! function, a call to \e IPCLiteLtoRGetResult() will read the data value in +//! the IPCREMOTEREPLY register into a 16- or 32-bit variable in the local CPU +//! application. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRDataRead(uint32_t ulFlag, uint32_t ulAddress, uint16_t usLength, + uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Set up read command, address, and word length. + // + if (usLength == IPC_LENGTH_16_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_READ_16; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_READ_32; + } + IpcRegs.IPCSENDADDR = ulAddress; + + // + // Force IPC event on selected request task and enable status-checking. + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit data word at the remote CPU system +//! address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote address to write to. +//! \param ulMask specifies the 16/32-bit mask for bits which should be set at +//! remote ulAddress. For 16-bit mask, only the lower 16-bits of ulMask are +//! considered. +//! \param usLength specifies the length of the \e ulMask (1 = 16-bit, 2 = +//! 32-bit). +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Remote system. +//! +//! This function will allow the Local CPU system to set bits specified by the +//! \e usMask variable in a 16/32-bit word on the Remote CPU system. The data +//! word at /e ulAddress after the set bits command is then read into the +//! IPCREMOTEREPLY register. After calling this function, a call to \e +//! IPCLiteLtoRGetResult() will read the data value in the IPCREMOTEREPLY +//! register into a 16/32-bit variable in the Local CPU application. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRSetBits(uint32_t ulFlag, uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength, uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + if (usLength == IPC_LENGTH_16_BITS) + { + // + // Set up 16-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_SET_BITS_16; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask & (0x0000FFFF); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + // + // Set up 32-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_SET_BITS_32; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask; + } + + // + // Force IPC event on selected request task and enable status-checking. + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit write-protected data word at +//! the Remote CPU system address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU write-protected address to write +//! to. +//! \param ulMask specifies the 16/32-bit mask for bits which should be set at +//! Remote CPU ulAddress.For 16-bit mask, only the lower 16-bits of ulMask are +//! considered. +//! \param usLength specifies the length of the \e ulMask (1 = 16-bit, 2 = +//! 32-bit). +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Master system. +//! +//! This function will allow the Local CPU system to set bits specified by the +//! \e usMask variable in a write-protected 16/32-bit word on the REmote CPU +//! system. +//! The data word at /e ulAddress after the set bits command is then read into +//! the IPCREMOTEREPLY register. After calling this function, a call to +//! \e IPCLiteLtoRGetResult() will read the data value in the IPCREMOTEREPLY +//! register into a 16/32-bit variable in the Local application. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRSetBits_Protected (uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + if (usLength == IPC_LENGTH_16_BITS) + { + // + // Set up 16-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_SET_BITS_16_PROTECTED; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask & (0x0000FFFF); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + // + // Set up 32-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_SET_BITS_32_PROTECTED; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask; + } + + // + // Force IPC event on selected request task and enable status-checking. + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit data word at the remote CPU system +//! address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU address to write to. +//! \param ulMask specifies the 16/32-bit mask for bits which should be set at +//! the remote CPU ulAddress. (For 16-bit mask, only the lower 16-bits of +//! ulMask are considered. +//! \param usLength specifies the length of the \e ulMask (1 = 16-bit, 2 = +//! 32-bit). +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Master system. +//! +//! This function will allow the Local CPU system to set bits specified by the +//! \e usMask variable in a 16/32-bit word on the Remote CPU system. The data +//! word at /e ulAddress after the set bits command is then read into the +//! IPCREMOTEREPLY register. After calling this function, a call to \e +//! IPCLiteLtoRGetResult() will read the data value in the IPCREMOTEREPLY +//! register into a 16/32-bit variable in the Local CPU application. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRClearBits(uint32_t ulFlag, uint32_t ulAddress, uint32_t ulMask, + uint16_t usLength, uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + if (usLength == IPC_LENGTH_16_BITS) + { + // + // Set up 16-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_CLEAR_BITS_16; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask & (0x0000FFFF); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + // + // Set up 32-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_CLEAR_BITS_32; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask; + } + + // + // Force IPC event on selected request task and enable status-checking. + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Clears the designated bits in a 16/32-bit write-protected data word at +//! Remote CPU system address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU write-protected address to write +//! to. +//! \param ulMask specifies the 16/32-bit mask for bits which should be cleared +//! at Remote CPU ulAddress.For 16-bit mask, only the lower 16-bits of ulMask +//! are considered. +//! \param usLength specifies the length of the \e ulMask (1 = 16-bit, 2 = +//! 32-bit). +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Master system. +//! +//! This function will allow the Local CPU system to clear bits specified by +//! the \e usMask variable in a write-protected 16/32-bit word on the Remote +//! CPU system. +//! The data word at /e ulAddress after the clear bits command is then read +//! into the IPCREMOTEREPLY register. After calling this function, a call to +//! \e IPCLiteLtoRGetResult() will read the data value in the IPCREMOTEREPLY +//! register into a 16/32-bit variable in the Local CPU application. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRClearBits_Protected (uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulMask, uint16_t usLength, + uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + if (usLength == IPC_LENGTH_16_BITS) + { + // + // Set up 16-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_CLEAR_BITS_16_PROTECTED; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask & (0x0000FFFF); + } + else if (usLength == IPC_LENGTH_32_BITS) + { + // + // Set up 32-bit set bits command, address, and mask. + // + IpcRegs.IPCSENDCOM = IPC_CLEAR_BITS_32_PROTECTED; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulMask; + } + + // + // Force IPC event on selected request task and enable status-checking. + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to Remote CPU System address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU address to write to +//! \param ulData specifies the 16/32-bit word which will be written. +//! For 16-bit words, only the lower 16-bits of ulData will be considered by +//! the master system. +//! \param usLength is the length of the word to write (0 = 16-bits, 1 = +//! 32-bits) +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Remote CPU system. +//! +//! This function will allow the Local CPU System to write a 16/32-bit word +//! via the \e ulData variable to an address on the Remote CPU System. +//! The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRDataWrite(uint32_t ulFlag, uint32_t ulAddress, uint32_t ulData, + uint16_t usLength, uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Set up data write command, address, and data. For 16-bit write, + // Master system will look at lower 16-bits only. + // + if (usLength == IPC_LENGTH_16_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_WRITE_16; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_WRITE_32; + } + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulData; + + // + // Force IPC event on selected request task and enable status-checking + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to a protected Remote CPU System address +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU address to write to +//! \param ulData specifies the 16/32-bit word which will be written. +//! For 16-bit words, only the lower 16-bits of ulData will be considered by +//! the master system. +//! \param usLength is the length of the word to write (0 = 16-bits, 1 = +//! 32-bits) +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Master system. +//! +//! This function will allow the Local CPU System to write a 16/32-bit word +//! via the \e ulData variable to a write-protected address on the Remote CPU +//! System. The \e usLength parameter accepts the following values: \b +//! IPC_LENGTH_16_BITS or \b IPC_LENGTH_32_BITS. The \e ulStatusFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and \b +//! NO_FLAG. The function returns \b STATUS_PASS if the command is successful +//! or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRDataWrite_Protected(uint32_t ulFlag, uint32_t ulAddress, + uint32_t ulData, uint16_t usLength, + uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Local to Remote request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Set up data write command, address, and data. For 16-bit write, Master + // system will look at lower 16-bits only. + // + if (usLength == IPC_LENGTH_16_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_WRITE_16_PROTECTED; + } + else if (usLength == IPC_LENGTH_32_BITS) + { + IpcRegs.IPCSENDCOM = IPC_DATA_WRITE_32_PROTECTED; + } + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulData; + + // + // Force IPC event on selected request task and enable status-checking + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Calls a Remote CPU function with 1 optional parameter and an optional +//! return value. +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulAddress specifies the Remote CPU function address +//! \param ulParam specifies the 32-bit optional parameter value +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Local CPU system to call a function on the +//! Remote CPU. The \e ulParam variable is a single optional 32-bit parameter +//! to pass to the function. The \e ulFlag parameter accepts any one of the +//! flag values \b IPC_FLAG1 - \b IPC_FLAG32. The \e ulStatusFlag parameter +//! accepts any other one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 +//! and \b NO_FLAG. The function returns \b STATUS_PASS if the command is +//! successful or \b STATUS_FAIL if the request or status flags are unavailable. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteLtoRFunctionCall(uint32_t ulFlag, uint32_t ulAddress, uint32_t ulParam, + uint32_t ulStatusFlag) +{ + uint16_t returnStatus; + + // + // Return false if IPC Remote to Local request or status flags are not + // available. + // + if (IpcRegs.IPCFLG.all & (ulFlag | ulStatusFlag)) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Set up function call command, address, and parameter. + // + IpcRegs.IPCSENDCOM = IPC_FUNC_CALL; + IpcRegs.IPCSENDADDR = ulAddress; + IpcRegs.IPCSENDDATA = ulParam; + + // + // Force IPC event on selected request task and enable status-checking + // + IpcRegs.IPCSET.all |= (ulFlag | ulStatusFlag); + + returnStatus = STATUS_PASS; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Slave Requests Master R/W/Exe Access to Shared SARAM. +//! +//! \param ulFlag specifies Local to Remote IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulMask specifies the 32-bit mask for the GSxMEMSEL RAM control +//! register to indicate which GSx SARAM blocks the Slave is requesting master +//! access to. +//! \param ulMaster specifies whether CPU1 or CPU2 should be the master of the +//! GSx RAM. +//! \param ulStatusFlag indicates the Local to Remote Flag number mask used to +//! report the status of the command sent back from the Master system. +//! +//! This function will allow the slave CPU System to request slave or master +//! mastership of any of the GSx Shared SARAM blocks. +//! The \e ulMaster parameter accepts the following values: +//! \b IPC_GSX_CPU2_MASTER or \b IPC_GSX_CPU1_MASTER. The \e ulStatusFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 +//! and \b NO_FLAG. The function returns \b STATUS_PASS if the command is +//! successful or \b STATUS_FAIL if the request or status flags are unavailable. +//! \note This function calls the \e IPCLiteLtoRSetBits_Protected() or the +//! \e IPCLiteLtoRClearBits_Protected function, and therefore in order to +//! process this function, the above 2 functions should be ready to be called +//! on the master system to process this command. +//! +//! \return status of command (0=success, 1=error) +// +//***************************************************************************** +uint16_t +IPCLiteReqMemAccess (uint32_t ulFlag, uint32_t ulMask, uint16_t ulMaster, + uint32_t ulStatusFlag) +{ + uint16_t status; + uint32_t GSxMSEL_REGaddress = (uint32_t)(&MemCfgRegs.GSxMSEL.all); + if (ulMaster == IPC_GSX_CPU2_MASTER) + { + status = + IPCLiteLtoRSetBits_Protected (ulFlag, GSxMSEL_REGaddress, ulMask, + IPC_LENGTH_32_BITS, + ulStatusFlag); + } + else if (ulMaster == IPC_GSX_CPU1_MASTER) + { + status = + IPCLiteLtoRClearBits_Protected (ulFlag, GSxMSEL_REGaddress, ulMask, + IPC_LENGTH_32_BITS, + ulStatusFlag); + } + + return status; +} + +//***************************************************************************** +// +//! Reads either a 16- or 32-bit data word from the Local CPU system address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to read 16/32-bit data from +//! the Local CPU system. The \e ulFlag parameter accepts any one of the +//! flag values \b IPC_FLAG1 - \b IPC_FLAG32, and the \e ulStatusFlag parameter +//! accepts any other one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and +//! \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLDataRead(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + + uint32_t* pulRAddress; + uint16_t* pusRAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command and data length are correct for this function: + // Then read from requested address and write 16/32-bit data + // to IPCLOCALREPLY. Acknowledge the status flag + // and the task flag. + // + if (IpcRegs.IPCRECVCOM == IPC_DATA_READ_16) + { + // + // Perform 16-bit read. + // + pusRAddress = (uint16_t *)IpcRegs.IPCRECVADDR; + IpcRegs.IPCLOCALREPLY = (uint32_t)(*pusRAddress); + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_DATA_READ_32) + { + pulRAddress = (uint32_t *)IpcRegs.IPCRECVADDR; + IpcRegs.IPCLOCALREPLY = *pulRAddress; + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + //(Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16/32-bit data word at the Local CPU system +//! address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to set bits specified by a +//! mask variable in a 16/32-bit word on the Local CPU system, and then read +//! back the word into the IPCLOCALREPLY register. The \e ulFlag parameter +//! accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, and the +//! \e ulStatusFlag parameter accepts any other one of the flag values \b +//! IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLSetBits(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + + uint16_t* pusAddress; + uint32_t* pulAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then set the mask bits at the requested address + // and write back the 16/32-bit data to IPCLOCALREPLY. + // Acknowledge the status flag and the task flag. + // + if (IpcRegs.IPCRECVCOM == IPC_SET_BITS_16) + { + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; + *pusAddress |= (uint16_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_SET_BITS_32) + { + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR;; + *pulAddress |= (uint32_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = *pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + // (Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } +} + +//***************************************************************************** +// +//! Sets the designated bits in a 16-bit data word at the Local CPU system +//! write-protected address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to set bits specified by a +//! mask variable in a write-protected 16/32-bit word on the Local CPU system, +//! and then read back the word into the IPCLOCALREPLY register. The \e ulFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, +//! and the \e ulStatusFlag parameter accepts any other one of the flag values +//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLSetBits_Protected (uint32_t ulFlag, uint32_t ulStatusFlag) +{ + + uint16_t* pusAddress; + uint32_t* pulAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then enable write access with EALLOW and + // set the mask bits at the requested address. + // Write back the 16-bit data to IPCLOCALREPLY. + // Restore write-protection with EDIS. + // Acknowledge the status flag and the task flag. + // + + EALLOW; + + if (IpcRegs.IPCRECVCOM == IPC_SET_BITS_16_PROTECTED) + { + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR; + *pusAddress |= (uint16_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_SET_BITS_32_PROTECTED) + { + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR; + *pulAddress |= (uint32_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = *pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + //(Indicates to the Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } + + EDIS; +} + +//***************************************************************************** +// +//! Clears the designated bits in a 16/32-bit data word at Local CPU system +//! address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to clear bits specified by a +//! mask variable in a 16/32-bit word on the Local CPU system, and then read +//! back the word into the IPCLOCALREPLY register. The \e ulFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, +//! and the \e ulStatusFlag parameter accepts any other one of the flag values +//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLClearBits(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + uint16_t* pusAddress; + uint32_t* pulAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then clear the mask bits at the requested address + // and write back the 16/32-bit data to IPCLOCALREPLY. + // Acknowledge the status flag and the task flag. + // + if (IpcRegs.IPCRECVCOM == IPC_CLEAR_BITS_16) + { + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; + *pusAddress &= ~((uint16_t)IpcRegs.IPCRECVDATA); + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_CLEAR_BITS_32) + { + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR; + *pulAddress &= ~((uint32_t)IpcRegs.IPCRECVDATA); + IpcRegs.IPCLOCALREPLY = *pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + // (Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } +} + +//***************************************************************************** +// +//! Clears the designated bits in a 16/32-bit data word at the Local CPU system +//! write-protected address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to clear bits specified by a +//! mask variable in a 16/32-bit word on the Local CPU system, and then read +//! back the word into the IPCLOCALREPLY register. The \e ulFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, +//! and the \e ulStatusFlag parameter accepts any other one of the flag values +//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLClearBits_Protected (uint32_t ulFlag, uint32_t ulStatusFlag) +{ + uint16_t* pusAddress; + uint32_t* pulAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then enable write access with EALLOW and + // clear the mask bits at the requested address. + // Write back the 16/32-bit data to IPCLOCALREPLY. + // Restore the status of the EALLOW register. + // Acknowledge the status flag and the task flag. + // + EALLOW; + + if (IpcRegs.IPCRECVCOM == IPC_CLEAR_BITS_16_PROTECTED) + { + + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; + *pusAddress &= ~((uint16_t)IpcRegs.IPCRECVDATA); + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_CLEAR_BITS_32_PROTECTED) + { + + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR;; + *pulAddress &= ~((uint32_t)IpcRegs.IPCRECVDATA); + IpcRegs.IPCLOCALREPLY = (uint32_t)*pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + // (Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } + + EDIS; +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to Local CPU system address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to write a 16/32-bit word +//! to an address on the Local CPU system. The \e ulFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, +//! and the \e ulStatusFlag parameter accepts any other one of the flag values +//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLDataWrite(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + uint32_t* pulAddress; + uint16_t* pusAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then write the 16/32-bit data to the requested address + // and write back the 16/32-bit data to IPCLOCALREPLY. + // Acknowledge the status flag and the task flag. + // + if (IpcRegs.IPCRECVCOM == IPC_DATA_WRITE_16) + { + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; + *pusAddress = (uint16_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_DATA_WRITE_32) + { + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR;; + *pulAddress = IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = *pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + + } + + // + // Otherwise, only acknowledge the task flag. + // (Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } +} + +//***************************************************************************** +// +//! Writes a 16/32-bit data word to a write-protected Local CPU system address +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to write a 16/32-bit word +//! to an address on the Local CPU system. The \e ulFlag +//! parameter accepts any one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32, +//! and the \e ulStatusFlag parameter accepts any other one of the flag values +//! \b IPC_FLAG1 - \b IPC_FLAG32 and \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLDataWrite_Protected(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + uint32_t* pulAddress; + uint16_t* pusAddress; + + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then enable write access with EALLOW and + // write the 16/32-bit data to the requested address + // and write back the 16/32-bit data to IPCLOCALREPLY. + // Acknowledge the status flag and the task flag. + // + EALLOW; + + if (IpcRegs.IPCRECVCOM == IPC_DATA_WRITE_16_PROTECTED) + { + pusAddress = (uint16_t *)IpcRegs.IPCRECVADDR;; + *pusAddress = (uint16_t)IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = (uint32_t)*pusAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + else if (IpcRegs.IPCRECVCOM == IPC_DATA_WRITE_32_PROTECTED) + { + pulAddress = (uint32_t *)IpcRegs.IPCRECVADDR; + *pulAddress = IpcRegs.IPCRECVDATA; + IpcRegs.IPCLOCALREPLY = *pulAddress; + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + + } + + // + // Otherwise, only acknowledge the task flag. + // (Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } + + // + // Restore write-protection status. + // + EDIS; +} + +//***************************************************************************** +// +//! Calls a Local CPU function with a single optional parameter and return +//! value. +//! +//! \param ulFlag specifies Remote to Local IPC Flag number mask used to +//! indicate a command is being sent. +//! \param ulStatusFlag indicates the Remote to Local Flag number mask used to +//! report the status of the command sent back from the control system. +//! +//! This function will allow the Remote CPU system to call a Local CPU function +//! with a single optional parameter and places an optional return value in the +//! IPCLOCALREPLY register. The \e ulFlag parameter accepts any one of the flag +//! values \b IPC_FLAG1 - \b IPC_FLAG32, and the \e ulStatusFlag parameter +//! accepts any other one of the flag values \b IPC_FLAG1 - \b IPC_FLAG32 and +//! \b NO_FLAG. +// +//***************************************************************************** +void +IPCLiteRtoLFunctionCall(uint32_t ulFlag, uint32_t ulStatusFlag) +{ + // + // Wait until IPC Remote to Local request task is flagged + // + while (!(IpcRegs.IPCSTS.all & ulFlag)) + { + } + + // + // If the command is correct for this function: + // Then call function at requested address + // and if there is a return value, insert into + // IPCLOCALREPLY register. + // Acknowledge the status flag and the task flag. + // + if (IpcRegs.IPCRECVCOM == IPC_FUNC_CALL) + { + tfIpcFuncCall func_call = (tfIpcFuncCall)IpcRegs.IPCRECVADDR; + IpcRegs.IPCLOCALREPLY = func_call(IpcRegs.IPCRECVDATA); + + IpcRegs.IPCACK.all |= (ulStatusFlag | ulFlag); + } + + // + // Otherwise, only acknowledge the task flag. + //(Indicates to Remote CPU there was an error) + // + else + { + IpcRegs.IPCACK.all |= (ulFlag); + } +} + +void DelayLoop (void) +{ + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); + __asm(" nop"); +} + +//***************************************************************************** +// Close the Doxygen group. +//! @} +//***************************************************************************** + + diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Util.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Util.c new file mode 100644 index 0000000000..7f98a29ea1 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Util.c @@ -0,0 +1,469 @@ +//########################################################################### +// +// FILE: F2837xD_Ipc_Driver_Util.c +// +// TITLE: F2837xD Inter-Processor Communication (IPC) API Driver Utility +// Functions +// +// DESCRIPTION: +// API functions for inter-processor communications between the +// Local and Remote CPU system. +// The driver functions in this file are available only as +// sample functions for application development. Due to the generic +// nature of these functions and the cycle overhead inherent to a +// function call, the code is not intended to be used in cases where +// maximum efficiency is required in a system. +// +// NOTE: This source code is used by both CPUs. That is both CPU1 and CPU2 +// cores use this code. +// The active debug CPU will be referred to as Local CPU and the other +// CPU will be referred to as Remote CPU. +// When using this source code in CPU1, the term "local" +// will mean CPU1 and the term "remote" CPU will be mean CPU2. +// When using this source code in CPU2, the term "local" +// will mean CPU2 and the term "remote" CPU will be mean CPU1. +// +// The abbreviations LtoR and RtoL within the function names mean +// Local to Remote and Remote to Local respectively. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +//***************************************************************************** +// +//! \addtogroup ipc_util_api +//! @{ +// +//***************************************************************************** +#include "F2837xD_device.h" +#include "F2837xD_GlobalPrototypes.h" +#include "F2837xD_Gpio_defines.h" +#include "F2837xD_Ipc_drivers.h" + +//***************************************************************************** +// +//! Local CPU Acknowledges Remote to Local IPC Flag. +//! +//! \param ulFlags specifies the IPC flag mask for flags being acknowledged. +//! +//! This function will allow the Local CPU system to acknowledge/clear the IPC +//! flag set by the Remote CPU system. The \e ulFlags parameter can be any of +//! the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +void +IPCRtoLFlagAcknowledge (uint32_t ulFlags) +{ + IpcRegs.IPCACK.all |= ulFlags; +} + +//***************************************************************************** +// +//! Determines whether the given Remote to Local IPC flags are busy or not. +//! +//! \param ulFlags specifies Remote to Local IPC Flag number masks to check the +//! status of. +//! +//! Allows the caller to determine whether the designated IPC flags are +//! pending. The \e ulFlags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return Returns \b 1 if the IPC flags are busy or \b 0 if designated +//! IPC flags are free. +// +//***************************************************************************** +Uint16 +IPCRtoLFlagBusy (uint32_t ulFlags) +{ + Uint16 returnStatus; + + if ((IpcRegs.IPCSTS.all & ulFlags) == 0) + { + returnStatus = 0; + } + else + { + returnStatus = 1; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Determines whether the given IPC flags are busy or not. +//! +//! \param ulFlags specifies Local to Remote IPC Flag number masks to check the +//! status of. +//! +//! Allows the caller to determine whether the designated IPC flags are +//! available for further control to master system communication. If \b 0 is +//! returned, then all designated tasks have completed and are available. +//! The \e ulFlags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return Returns \b 1 if the IPC flags are busy or \b 0 if designated +//! IPC flags are free. +// +//***************************************************************************** +Uint16 +IPCLtoRFlagBusy (uint32_t ulFlags) +{ + Uint16 returnStatus; + + if ((IpcRegs.IPCFLG.all & ulFlags) == 0) + { + returnStatus = 0; + } + else + { + returnStatus = 1; + } + + return returnStatus; +} + +//***************************************************************************** +// +//! Local CPU Sets Local to Remote IPC Flag +//! +//! \param ulFlags specifies the IPC flag mask for flags being set. +//! +//! This function will allow the Local CPU system to set the designated IPC +//! flags to send to the Remote CPU system. The \e ulFlags parameter can be any +//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +void +IPCLtoRFlagSet (uint32_t ulFlags) +{ + IpcRegs.IPCSET.all |= ulFlags; +} + +//***************************************************************************** +// +//! Local CPU Clears Local to Remote IPC Flag +//! +//! \param ulFlags specifies the IPC flag mask for flags being set. +//! +//! This function will allow the Local CPU system to set the designated IPC +//! flags to send to the Remote CPU system. The \e ulFlags parameter can be any +//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +void +IPCLtoRFlagClear (uint32_t ulFlags) +{ + IpcRegs.IPCCLR.all |= ulFlags; +} + +//***************************************************************************** +// +//! Local Return CPU02 BOOT status +//! +//! This function returns the value at IPCBOOTSTS register. +//! +//! \return Boot status. +// +//***************************************************************************** +uint32_t +IPCGetBootStatus (void) +{ + return(IpcRegs.IPCBOOTSTS); +} + +#if defined (CPU1) +//***************************************************************************** +//! Executes a CPU02 control system bootloader. +//! +//! \param ulBootMode specifies which CPU02 control system boot mode to execute. +//! +//! This function will allow the CPU01 master system to boot the CPU02 control +//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI, +//! SCI, I2C, or parallel I/O. Unlike other IPCLite driver functions, this +//! function blocks and waits until the control system boot ROM is configured +//! and ready to receive CPU01 to CPU02 IPC INT0 interrupts. It then blocks and +//! waits until IPC INT0 and IPC FLAG31 are available in the CPU02 boot ROM +//! prior to sending the command to execute the selected bootloader. The \e +//! ulBootMode parameter accepts one of the following values: \b +//! C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL, \b +//! C1C2_BROM_BOOTMODE_BOOT_FROM_SCI, \b +//! C1C2_BROM_BOOTMODE_BOOT_FROM_SPI, \b +//! C1C2_BROM_BOOTMODE_BOOT_FROM_I2C, \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN, +//! \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM, \b +//! C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH. +//! +//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is +//! invalid and command was not sent. +// +//***************************************************************************** +uint16_t +IPCBootCPU2(uint32_t ulBootMode) +{ + uint32_t bootStatus; + uint16_t pin; + uint16_t returnStatus = STATUS_PASS; + + // + // If CPU2 has already booted, return a fail to let the application + // know that something is out of the ordinary. + // + bootStatus = IPCGetBootStatus() & 0x0000000F; + + if(bootStatus == C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK) + { + // + // Check if MSB is set as well + // + bootStatus = ((uint32_t)(IPCGetBootStatus() & 0x80000000)) >> 31U; + + if(bootStatus != 0) + { + returnStatus = STATUS_FAIL; + + return returnStatus; + } + } + + // + // Wait until CPU02 control system boot ROM is ready to receive + // CPU01 to CPU02 INT1 interrupts. + // + do + { + bootStatus = IPCGetBootStatus() & C2_BOOTROM_BOOTSTS_SYSTEM_READY; + } while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY)); + + // + // Loop until CPU02 control system IPC flags 1 and 32 are available + // + while ((IPCLtoRFlagBusy(IPC_FLAG0) == 1) || + (IPCLtoRFlagBusy(IPC_FLAG31) == 1)) + { + + } + + if (ulBootMode >= C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Based on boot mode, enable pull-ups on peripheral pins and + // give GPIO pin control to CPU02 control system. + // + switch (ulBootMode) + { + case C1C2_BROM_BOOTMODE_BOOT_FROM_SCI: + + EALLOW; + + // + //SCIA connected to CPU02 + // + DevCfgRegs.CPUSEL5.bit.SCI_A = 1; + + // + //Allows CPU02 bootrom to take control of clock + //configuration registers + // + ClkCfgRegs.CLKSEM.all = 0xA5A50000; + + ClkCfgRegs.LOSPCP.all = 0x0002; + EDIS; + + GPIO_SetupPinOptions(29, GPIO_OUTPUT, GPIO_ASYNC); + GPIO_SetupPinMux(29,GPIO_MUX_CPU2,1); + + GPIO_SetupPinOptions(28, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(28,GPIO_MUX_CPU2,1); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_SPI: + EALLOW; + + // + //SPI-A connected to CPU02 + // + DevCfgRegs.CPUSEL6.bit.SPI_A = 1; + + // + //Allows CPU02 bootrom to take control of clock configuration + // registers + // + ClkCfgRegs.CLKSEM.all = 0xA5A50000; + EDIS; + + GPIO_SetupPinOptions(16, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(16,GPIO_MUX_CPU2,1); + + GPIO_SetupPinOptions(17, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(17,GPIO_MUX_CPU2,1); + + GPIO_SetupPinOptions(18, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(18,GPIO_MUX_CPU2,1); + + GPIO_SetupPinOptions(19, GPIO_OUTPUT, GPIO_ASYNC); + GPIO_SetupPinMux(19,GPIO_MUX_CPU2,0); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_I2C: + EALLOW; + + // + //I2CA connected to CPU02 + // + DevCfgRegs.CPUSEL7.bit.I2C_A = 1; + + // + //Allows CPU2 bootrom to take control of clock + //configuration registers + // + ClkCfgRegs.CLKSEM.all = 0xA5A50000; + ClkCfgRegs.LOSPCP.all = 0x0002; + EDIS; + GPIO_SetupPinOptions(32, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(32,GPIO_MUX_CPU2,1); + + GPIO_SetupPinOptions(33, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(33,GPIO_MUX_CPU2,1); + + break; + case C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL: + + for(pin=58;pin<=65;pin++) + { + GPIO_SetupPinOptions(pin, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(pin,GPIO_MUX_CPU2,0); + } + + GPIO_SetupPinOptions(69, GPIO_OUTPUT, GPIO_ASYNC); + GPIO_SetupPinMux(69,GPIO_MUX_CPU2,0); + + GPIO_SetupPinOptions(70, GPIO_INPUT, GPIO_ASYNC); + GPIO_SetupPinMux(70,GPIO_MUX_CPU2,0); + break; + + + case C1C2_BROM_BOOTMODE_BOOT_FROM_CAN: + // + //Set up the GPIO mux to bring out CANATX on GPIO71 + //and CANARX on GPIO70 + // + EALLOW; + GpioCtrlRegs.GPCLOCK.all = 0x00000000; //Unlock GPIOs 64-95 + + // + //Give CPU2 control just in case + // + GpioCtrlRegs.GPCCSEL1.bit.GPIO71 = GPIO_MUX_CPU2; + + // + //Set the extended mux to 0x5 + // + GpioCtrlRegs.GPCGMUX1.bit.GPIO71 = 0x1; + GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 0x1; + + // + //Set qualification to async just in case + // + GpioCtrlRegs.GPCQSEL1.bit.GPIO71 = 0x3; + + GpioCtrlRegs.GPCLOCK.all = 0x00000000; //Unlock GPIOs 64-95 + + // + //Give CPU2 control just in case + // + GpioCtrlRegs.GPCCSEL1.bit.GPIO70 = GPIO_MUX_CPU2; + + // + //Set the extended mux to bring out CANATX + // + GpioCtrlRegs.GPCGMUX1.bit.GPIO70 = 0x1; + GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 0x1; + + // + //Set qualification to async just in case + // + GpioCtrlRegs.GPCQSEL1.bit.GPIO70 = 0x3; + GpioCtrlRegs.GPCLOCK.all = 0xFFFFFFFF; //Lock GPIOs 64-95 + ClkCfgRegs.CLKSRCCTL2.bit.CANABCLKSEL = 0x0; + CpuSysRegs.PCLKCR10.bit.CAN_A = 1; + EDIS; + + break; + + } + + // + //CPU01 to CPU02 IPC Boot Mode Register + // + IpcRegs.IPCBOOTMODE = ulBootMode; + + // + // CPU01 To CPU02 IPC Command Register + // + IpcRegs.IPCSENDCOM = BROM_IPC_EXECUTE_BOOTMODE_CMD; + + // + // CPU01 to CPU02 IPC flag register + // + IpcRegs.IPCSET.all = 0x80000001; + + } + + + + return returnStatus; +} + + +#endif +//***************************************************************************** +// Close the Doxygen group. +//! @} +//***************************************************************************** + + diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Mcbsp.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Mcbsp.c new file mode 100644 index 0000000000..b93b01a4ff --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Mcbsp.c @@ -0,0 +1,584 @@ +//########################################################################### +// +// FILE: F2837xD_McBSP.c +// +// TITLE: F2837xD Device McBSP Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// MCBSP_INIT_DELAY determines the amount of CPU cycles in the 2 sample rate +// generator (SRG) cycles required for the Mcbsp initialization routine. +// MCBSP_CLKG_DELAY determines the amount of CPU cycles in the 2 clock +// generator (CLKG) cycles required for the Mcbsp initialization routine. +// + +// +// Defines +// +#define CPU_SPD 200E6 +#define MCBSP_SRG_FREQ CPU_SPD/4 // SRG input is LSPCLK (SYSCLKOUT/4) + // for examples +#define CLKGDV_VAL 1 + +// # of CPU cycles in 2 SRG cycles-init delay +#define MCBSP_INIT_DELAY 2*(CPU_SPD/MCBSP_SRG_FREQ) + +// # of CPU cycles in 2 CLKG cycles-init delay +#define MCBSP_CLKG_DELAY 2*(CPU_SPD/(MCBSP_SRG_FREQ/(1+CLKGDV_VAL))) + +// +// Function Prototypes +// +void delay_loop(void); // Delay function used for SRG initialization +void clkg_delay_loop(void); // Delay function used for CLKG initialization + +// +// InitMcbsp - This function initializes the McBSP to a known state. +// +void InitMcbspa(void) +{ + // + // Reset the McBSP + // Disable all interrupts + // Frame sync generator reset + // Sample rate generator reset + // Transmitter reset + // Receiver reset + // + McbspaRegs.SPCR2.bit.FRST = 0; + McbspaRegs.SPCR2.bit.GRST = 0; + McbspaRegs.SPCR2.bit.XRST = 0; + McbspaRegs.SPCR1.bit.RRST = 0; + + // + // Enable loop back mode + // This does not require external hardware + // + McbspaRegs.SPCR2.all = 0x0000; + McbspaRegs.SPCR1.all = 0x8000; + + // + // RX data delay is 1 bit + // TX data delay is 1 bit + // + McbspaRegs.RCR2.bit.RDATDLY = 1; + McbspaRegs.XCR2.bit.XDATDLY = 1; + + // + // No clock sync for CLKG + // Frame-synchronization period + // + McbspaRegs.SRGR2.bit.GSYNC = 0; + McbspaRegs.SRGR2.bit.FPER = 320; + + // + // Frame-synchronization pulses from + // the sample rate generator + // + McbspaRegs.SRGR2.bit.FSGM = 1; + + // + // Sample rate generator input clock is LSPCLK + // + McbspaRegs.SRGR2.bit.CLKSM = 1; + McbspaRegs.PCR.bit.SCLKME = 0; + + // + // Divide-down value for CLKG + // Frame-synchronization pulse width + // + McbspaRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; + clkg_delay_loop(); + McbspaRegs.SRGR1.bit.FWID = 1; + + // + // CLKX is driven by the sample rate generator + // Transmit frame synchronization generated by internal + // sample rate generator + // + McbspaRegs.PCR.bit.CLKXM = 1; + McbspaRegs.PCR.bit.FSXM = 1; + + // + // Enable Sample rate generator and + // wait at least 2 CLKG clock cycles + // + McbspaRegs.SPCR2.bit.GRST = 1; + clkg_delay_loop(); + + // + // Release from reset + // RX, TX and frame sync generator + // + McbspaRegs.SPCR2.bit.XRST = 1; + McbspaRegs.SPCR1.bit.RRST = 1; + McbspaRegs.SPCR2.bit.FRST = 1; +} + +// +// InitMcbspaInt - Enable TX and RX interrupts +// +void InitMcbspaInt(void) +{ + // Reset TX and RX + // Enable interrupts for TX and RX + // Release TX and RX + McbspaRegs.SPCR2.bit.XRST = 0; + McbspaRegs.SPCR1.bit.RRST = 0; + McbspaRegs.MFFINT.bit.XINT = 1; + McbspaRegs.MFFINT.bit.RINT = 1; + McbspaRegs.SPCR2.bit.XRST = 1; + McbspaRegs.SPCR1.bit.RRST = 1; +} + +// +// InitMcbspa8bit - McBSP uses an 8-bit word for both TX and RX +// +void InitMcbspa8bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 0; + McbspaRegs.XCR1.bit.XWDLEN1 = 0; +} + +// +// InitMcbspa12bit - McBSP uses an 12-bit word for both TX and RX +// +void InitMcbspa12bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 1; + McbspaRegs.XCR1.bit.XWDLEN1 = 1; +} + +// +// InitMcbspa16bit - McBSP uses an 16-bit word for both TX and RX +// +void InitMcbspa16bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 2; + McbspaRegs.XCR1.bit.XWDLEN1 = 2; +} + +// +// InitMcbspa20bit - McBSP uses an 20-bit word for both TX and RX +// +void InitMcbspa20bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 3; + McbspaRegs.XCR1.bit.XWDLEN1 = 3; +} + +// +// InitMcbspa24bit - McBSP uses an 24-bit word for both TX and RX +// +void InitMcbspa24bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 4; + McbspaRegs.XCR1.bit.XWDLEN1 = 4; +} + +// +// InitMcbspa32bit - McBSP uses an 32-bit word for both TX and RX +// +void InitMcbspa32bit(void) +{ + McbspaRegs.RCR1.bit.RWDLEN1 = 5; + McbspaRegs.XCR1.bit.XWDLEN1 = 5; +} + +// +// InitMcbspaGpio - Assign GPIO pins to the McBSP peripheral +// (Note: This function must be called from CPU1.) +// +void InitMcbspaGpio(void) +{ +#ifdef CPU1 + EALLOW; + + // + // This specifies which of the possible GPIO pins will be + // McBSPA functional pins. Comment out unwanted connections. + // Set qualification for selected input pins to asynchronous only + // This will select asynchronous (no qualification) for the selected pins. + // + + // + // MDXA + // GPIO20 + // GPIO84 + // + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 2; + //GpioCtrlRegs.GPCGMUX2.bit.GPIO84 = 3; + //GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; + + // + // MDRA + // GPIO21 with asynchronous qualification + // GPIO85 with asynchronous qualification + // + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 2; + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; + //GpioCtrlRegs.GPCGMUX2.bit.GPIO85 = 3; + //GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; + //GpioCtrlRegs.GPCQSEL2.bit.GPIO85 = 3; + + // + // MCLKXA + // GPIO22 with asynchronous qualification + // GPIO86 with asynchronous qualification + // + GpioCtrlRegs.GPAMUX2.bit.GPIO22 = 2; + //GpioCtrlRegs.GPAQSEL2.bit.GPIO22 = 3; + //GpioCtrlRegs.GPCGMUX2.bit.GPIO86 = 3; + //GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; + //GpioCtrlRegs.GPCQSEL2.bit.GPIO86 = 3; + + // + // MCLKRA + // Select one of the following + // GPIO7 with asynchronous qualification + // GPIO58 with asynchronous qualification + // + GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 2; + GpioCtrlRegs.GPAQSEL1.bit.GPIO7 = 3; + //GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 1; + //GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; + + // + // MFSXA + // GPIO23 with asynchronous qualification + // GPIO87 with asynchronous qualification + // + GpioCtrlRegs.GPAMUX2.bit.GPIO23 = 2; + //GpioCtrlRegs.GPAQSEL2.bit.GPIO23 = 3; + //GpioCtrlRegs.GPCGMUX2.bit.GPIO87 = 3; + //GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; + //GpioCtrlRegs.GPCQSEL2.bit.GPIO87 = 3; + + // + // MFSRA + // Select one of the following + // GPIO5 with asynchronous qualification + // GPIO59 with asynchronous qualification + // + GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; + GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; + //GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 1; + //GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; + + EDIS; +#endif +} + +// +// InitMcbspb - McBSPB initialization routine for examples +// +void InitMcbspb(void) +{ + // + // Reset the McBSP + // Disable all interrupts + // Frame sync generator reset + // Sample rate generator reset + // Transmitter reset + // Receiver reset + // + McbspbRegs.SPCR2.bit.FRST = 0; + McbspbRegs.SPCR2.bit.GRST = 0; + McbspbRegs.SPCR2.bit.XRST = 0; + McbspbRegs.SPCR1.bit.RRST = 0; + + // + // Enable loop back mode + // This does not require external hardware + // + McbspbRegs.SPCR2.all = 0x0000; + McbspbRegs.SPCR1.all = 0x8000; + + // + // RX data delay is 1 bit + // TX data delay is 1 bit + // + McbspbRegs.RCR2.bit.RDATDLY = 1; + McbspbRegs.XCR2.bit.XDATDLY = 1; + + // + // No clock sync for CLKG + // Frame-synchronization period + // + McbspbRegs.SRGR2.bit.GSYNC = 0; + McbspbRegs.SRGR2.bit.FPER = 320; + + // + // Frame-synchronization pulses from + // the sample rate generator + // + McbspbRegs.SRGR2.bit.FSGM = 1; + + // + // Sample rate generator input clock is LSPCLK + // + McbspbRegs.SRGR2.bit.CLKSM = 1; + McbspbRegs.PCR.bit.SCLKME = 0; + + // + // Divide-down value for CLKG + // Frame-synchronization pulse width + // + McbspbRegs.SRGR1.bit.CLKGDV = CLKGDV_VAL; + clkg_delay_loop(); + McbspbRegs.SRGR1.bit.FWID = 1; + + // + // CLKX is driven by the sample rate generator + // Transmit frame synchronization generated by internal + // sample rate generator + // + McbspbRegs.PCR.bit.CLKXM = 1; + McbspbRegs.PCR.bit.FSXM = 1; + + // + // Enable Sample rate generator and + // wait at least 2 CLKG clock cycles + // + McbspbRegs.SPCR2.bit.GRST = 1; + clkg_delay_loop(); + + // + // Release from reset + // RX, TX and frame sync generator + // + McbspbRegs.SPCR2.bit.XRST = 1; + McbspbRegs.SPCR1.bit.RRST = 1; + McbspbRegs.SPCR2.bit.FRST = 1; +} + +// +// InitMcbspbInt - Enable TX and RX interrupts +// +void InitMcbspbInt(void) +{ + // + // Reset TX and RX + // Enable interrupts for TX and RX + // Release TX and RX + // + McbspbRegs.SPCR2.bit.XRST = 0; + McbspbRegs.SPCR1.bit.RRST = 0; + McbspbRegs.MFFINT.bit.XINT = 1; + McbspbRegs.MFFINT.bit.RINT = 1; + McbspbRegs.SPCR2.bit.XRST = 1; + McbspbRegs.SPCR1.bit.RRST = 1; +} + +// +// InitMcbspb8bit - McBSPB uses an 8-bit word for both TX and RX +// +void InitMcbspb8bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 0; + McbspbRegs.XCR1.bit.XWDLEN1 = 0; +} + +// +// IniMcbspb12bit - McBSPB uses an 12-bit word for both TX and RX +// +void IniMcbspb12bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 1; + McbspbRegs.XCR1.bit.XWDLEN1 = 1; +} + +// +// InitMcbspb16bit - McBSPB uses an 16-bit word for both TX and RX +// +void InitMcbspb16bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 2; + McbspbRegs.XCR1.bit.XWDLEN1 = 2; +} + +// +// InitMcbspb20bit - McBSPB uses an 20-bit word for both TX and RX +// +void InitMcbspb20bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 3; + McbspbRegs.XCR1.bit.XWDLEN1 = 3; +} + +// +// InitMcbspb24bit - McBSPB uses an 24-bit word for both TX and RX +// +void InitMcbspb24bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 4; + McbspbRegs.XCR1.bit.XWDLEN1 = 4; +} + +// +// InitMcbspb32bit - McBSPB uses an 32-bit word for both TX and RX +// +void InitMcbspb32bit(void) +{ + McbspbRegs.RCR1.bit.RWDLEN1 = 5; + McbspbRegs.XCR1.bit.XWDLEN1 = 5; +} + +// +// InitMcbspbGpio - Assign GPIO pins to the McBSP peripheral +// (Note: This function must be called from CPU1.) +// +void InitMcbspbGpio(void) +{ +#ifdef CPU1 + EALLOW; + + // + // This specifies which of the possible GPIO pins will be + // McBSPB functional pins. Comment out unwanted connections. + // Set qualification for selected input pins to asynchronous only + // This will select asynchronous (no qualification) for the selected pins. + // + + // + // Select one of the following for MDXB + // GPIO24 + // GPIO84 + // + //GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 3; + GpioCtrlRegs.GPCGMUX2.bit.GPIO84 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 2; + + // + // MDRB + // GPIO13 with asynchronous qualification + // GPIO25 with asynchronous qualification + // GPIO85 with asynchronous qualification + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; + //GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; + //GpioCtrlRegs.GPAMUX2.bit.GPIO25 = 3; + //GpioCtrlRegs.GPAQSEL2.bit.GPIO25 = 3; + GpioCtrlRegs.GPCGMUX2.bit.GPIO85 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 2; + GpioCtrlRegs.GPCQSEL2.bit.GPIO85 = 3; + + // + // MCLKXB + // GPIO14 with asynchronous qualification + // GPIO26 with asynchronous qualification + // GPIO86 with asynchronous qualification + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; + //GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; + //GpioCtrlRegs.GPAMUX2.bit.GPIO26 = 3; + //GpioCtrlRegs.GPAQSEL2.bit.GPIO26 = 3; + GpioCtrlRegs.GPCGMUX2.bit.GPIO86 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 2; + GpioCtrlRegs.GPCQSEL2.bit.GPIO86= 3; + + // + // MCLKRB + // Select one of the following + // GPIO3 with asynchronous qualification + // GPIO60 with asynchronous qualification + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 3; + //GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; + GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 1; + GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; + + // + // MFSXB + // GPIO15 with asynchronous qualification + // GPIO27 with asynchronous qualification + // GPIO87 with asynchronous qualification + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; + //GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; + //GpioCtrlRegs.GPAMUX2.bit.GPIO27 = 3; + //GpioCtrlRegs.GPAQSEL2.bit.GPIO27 = 3; + GpioCtrlRegs.GPCGMUX2.bit.GPIO87 = 1; + GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 2; + GpioCtrlRegs.GPCQSEL2.bit.GPIO87= 3; + + // + // MFSRB + // Select one of the following + // GPIO1 with asynchronous qualification + // GPIO61 with asynchronous qualification + // + //GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 3; + //GpioCtrlRegs.GPAQSEL1.bit.GPIO1 = 3; + GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 1; + GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; + + EDIS; + +#endif +} + +// +// delay_loop - Delay function (at least 2 SRG cycles) +// Required in McBSP initialization +// +void delay_loop(void) +{ + long i; + for (i = 0; i < MCBSP_INIT_DELAY; i++) {} +} + +// +// clkg_delay_loop - Delay function (at least 2 CLKG cycles) +// Required in McBSP init +// +void clkg_delay_loop(void) +{ + long i; + for (i = 0; i < MCBSP_CLKG_DELAY; i++) {} +} + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_PieCtrl.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_PieCtrl.c new file mode 100644 index 0000000000..e6be2e920c --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_PieCtrl.c @@ -0,0 +1,121 @@ +//########################################################################### +// +// FILE: F2837xD_PieCtrl.c +// +// TITLE: F2837xD Device PIE Control Register Initialization Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" // F2837xD Headerfile Include File +#include "F2837xD_Examples.h" // F2837xD Examples Include File + +// +// InitPieCtrl - This function initializes the PIE control registers to a +// known state. +// +void InitPieCtrl(void) +{ + // + // Disable Interrupts at the CPU level: + // + DINT; + + // + // Disable the PIE + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 0; + + // + // Clear all PIEIER registers: + // + PieCtrlRegs.PIEIER1.all = 0; + PieCtrlRegs.PIEIER2.all = 0; + PieCtrlRegs.PIEIER3.all = 0; + PieCtrlRegs.PIEIER4.all = 0; + PieCtrlRegs.PIEIER5.all = 0; + PieCtrlRegs.PIEIER6.all = 0; + PieCtrlRegs.PIEIER7.all = 0; + PieCtrlRegs.PIEIER8.all = 0; + PieCtrlRegs.PIEIER9.all = 0; + PieCtrlRegs.PIEIER10.all = 0; + PieCtrlRegs.PIEIER11.all = 0; + PieCtrlRegs.PIEIER12.all = 0; + + // + // Clear all PIEIFR registers: + // + PieCtrlRegs.PIEIFR1.all = 0; + PieCtrlRegs.PIEIFR2.all = 0; + PieCtrlRegs.PIEIFR3.all = 0; + PieCtrlRegs.PIEIFR4.all = 0; + PieCtrlRegs.PIEIFR5.all = 0; + PieCtrlRegs.PIEIFR6.all = 0; + PieCtrlRegs.PIEIFR7.all = 0; + PieCtrlRegs.PIEIFR8.all = 0; + PieCtrlRegs.PIEIFR9.all = 0; + PieCtrlRegs.PIEIFR10.all = 0; + PieCtrlRegs.PIEIFR11.all = 0; + PieCtrlRegs.PIEIFR12.all = 0; +} + +// +// EnableInterrupts - This function enables the PIE module and CPU __interrupts +// +void EnableInterrupts() +{ + // + // Enable the PIE + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; + + // + // Enables PIE to drive a pulse into the CPU + // + PieCtrlRegs.PIEACK.all = 0xFFFF; + + // + // Enable Interrupts at the CPU level + // + EINT; +} + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_PieVect.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_PieVect.c new file mode 100644 index 0000000000..20e8fbf74b --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_PieVect.c @@ -0,0 +1,320 @@ +//########################################################################### +// +// FILE: F2837xD_PieVect.c +// +// TITLE: F2837xD Device PIE Vector Initialization Functions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// Globals +// +const struct PIE_VECT_TABLE PieVectTableInit = { + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + TIMER1_ISR, // CPU Timer 1 Interrupt + TIMER2_ISR, // CPU Timer 2 Interrupt + DATALOG_ISR, // Datalogging Interrupt + RTOS_ISR, // RTOS Interrupt + EMU_ISR, // Emulation Interrupt + NMI_ISR, // Non-Maskable Interrupt + ILLEGAL_ISR, // Illegal Operation Trap + USER1_ISR, // User Defined Trap 1 + USER2_ISR, // User Defined Trap 2 + USER3_ISR, // User Defined Trap 3 + USER4_ISR, // User Defined Trap 4 + USER5_ISR, // User Defined Trap 5 + USER6_ISR, // User Defined Trap 6 + USER7_ISR, // User Defined Trap 7 + USER8_ISR, // User Defined Trap 8 + USER9_ISR, // User Defined Trap 9 + USER10_ISR, // User Defined Trap 10 + USER11_ISR, // User Defined Trap 11 + USER12_ISR, // User Defined Trap 12 + ADCA1_ISR, // 1.1 - ADCA Interrupt 1 + ADCB1_ISR, // 1.2 - ADCB Interrupt 1 + ADCC1_ISR, // 1.3 - ADCC Interrupt 1 + XINT1_ISR, // 1.4 - XINT1 Interrupt + XINT2_ISR, // 1.5 - XINT2 Interrupt + ADCD1_ISR, // 1.6 - ADCD Interrupt 1 + TIMER0_ISR, // 1.7 - Timer 0 Interrupt + WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt + EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt + EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt + EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt + EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt + EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt + EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt + EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt + EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt + EPWM1_ISR, // 3.1 - ePWM1 Interrupt + EPWM2_ISR, // 3.2 - ePWM2 Interrupt + EPWM3_ISR, // 3.3 - ePWM3 Interrupt + EPWM4_ISR, // 3.4 - ePWM4 Interrupt + EPWM5_ISR, // 3.5 - ePWM5 Interrupt + EPWM6_ISR, // 3.6 - ePWM6 Interrupt + EPWM7_ISR, // 3.7 - ePWM7 Interrupt + EPWM8_ISR, // 3.8 - ePWM8 Interrupt + ECAP1_ISR, // 4.1 - eCAP1 Interrupt + ECAP2_ISR, // 4.2 - eCAP2 Interrupt + ECAP3_ISR, // 4.3 - eCAP3 Interrupt + ECAP4_ISR, // 4.4 - eCAP4 Interrupt + ECAP5_ISR, // 4.5 - eCAP5 Interrupt + ECAP6_ISR, // 4.6 - eCAP6 Interrupt + PIE_RESERVED_ISR, // 4.7 - Reserved + PIE_RESERVED_ISR, // 4.8 - Reserved + EQEP1_ISR, // 5.1 - eQEP1 Interrupt + EQEP2_ISR, // 5.2 - eQEP2 Interrupt + EQEP3_ISR, // 5.3 - eQEP3 Interrupt + PIE_RESERVED_ISR, // 5.4 - Reserved + PIE_RESERVED_ISR, // 5.5 - Reserved + PIE_RESERVED_ISR, // 5.6 - Reserved + PIE_RESERVED_ISR, // 5.7 - Reserved + PIE_RESERVED_ISR, // 5.8 - Reserved + SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt + SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt + SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt + SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt + MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt + MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt + MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt + MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt + DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt + DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt + DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt + DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt + DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt + DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt + PIE_RESERVED_ISR, // 7.7 - Reserved + PIE_RESERVED_ISR, // 7.8 - Reserved + I2CA_ISR, // 8.1 - I2CA Interrupt 1 + I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2 + I2CB_ISR, // 8.3 - I2CB Interrupt 1 + I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2 + SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt + SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt + SCID_RX_ISR, // 8.7 - SCID Receive Interrupt + SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt + SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt + SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt + SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt + SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt + CANA0_ISR, // 9.5 - CANA Interrupt 0 + CANA1_ISR, // 9.6 - CANA Interrupt 1 + CANB0_ISR, // 9.7 - CANB Interrupt 0 + CANB1_ISR, // 9.8 - CANB Interrupt 1 + ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt + ADCA2_ISR, // 10.2 - ADCA Interrupt 2 + ADCA3_ISR, // 10.3 - ADCA Interrupt 3 + ADCA4_ISR, // 10.4 - ADCA Interrupt 4 + ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt + ADCB2_ISR, // 10.6 - ADCB Interrupt 2 + ADCB3_ISR, // 10.7 - ADCB Interrupt 3 + ADCB4_ISR, // 10.8 - ADCB Interrupt 4 + CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1 + CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2 + CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3 + CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4 + CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5 + CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6 + CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7 + CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8 + XINT3_ISR, // 12.1 - XINT3 Interrupt + XINT4_ISR, // 12.2 - XINT4 Interrupt + XINT5_ISR, // 12.3 - XINT5 Interrupt + PIE_RESERVED_ISR, // 12.4 - Reserved + PIE_RESERVED_ISR, // 12.5 - Reserved + VCU_ISR, // 12.6 - VCU Interrupt + FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt + FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt + PIE_RESERVED_ISR, // 1.9 - Reserved + PIE_RESERVED_ISR, // 1.10 - Reserved + PIE_RESERVED_ISR, // 1.11 - Reserved + PIE_RESERVED_ISR, // 1.12 - Reserved + IPC0_ISR, // 1.13 - IPC Interrupt 0 + IPC1_ISR, // 1.14 - IPC Interrupt 1 + IPC2_ISR, // 1.15 - IPC Interrupt 2 + IPC3_ISR, // 1.16 - IPC Interrupt 3 + EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt + EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt + EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt + EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt + PIE_RESERVED_ISR, // 2.13 - Reserved + PIE_RESERVED_ISR, // 2.14 - Reserved + PIE_RESERVED_ISR, // 2.15 - Reserved + PIE_RESERVED_ISR, // 2.16 - Reserved + EPWM9_ISR, // 3.9 - ePWM9 Interrupt + EPWM10_ISR, // 3.10 - ePWM10 Interrupt + EPWM11_ISR, // 3.11 - ePWM11 Interrupt + EPWM12_ISR, // 3.12 - ePWM12 Interrupt + PIE_RESERVED_ISR, // 3.13 - Reserved + PIE_RESERVED_ISR, // 3.14 - Reserved + PIE_RESERVED_ISR, // 3.15 - Reserved + PIE_RESERVED_ISR, // 3.16 - Reserved + PIE_RESERVED_ISR, // 4.9 - Reserved + PIE_RESERVED_ISR, // 4.10 - Reserved + PIE_RESERVED_ISR, // 4.11 - Reserved + PIE_RESERVED_ISR, // 4.12 - Reserved + PIE_RESERVED_ISR, // 4.13 - Reserved + PIE_RESERVED_ISR, // 4.14 - Reserved + PIE_RESERVED_ISR, // 4.15 - Reserved + PIE_RESERVED_ISR, // 4.16 - Reserved + SD1_ISR, // 5.9 - SD1 Interrupt + SD2_ISR, // 5.10 - SD2 Interrupt + PIE_RESERVED_ISR, // 5.11 - Reserved + PIE_RESERVED_ISR, // 5.12 - Reserved + PIE_RESERVED_ISR, // 5.13 - Reserved + PIE_RESERVED_ISR, // 5.14 - Reserved + PIE_RESERVED_ISR, // 5.15 - Reserved + PIE_RESERVED_ISR, // 5.16 - Reserved + SPIC_RX_ISR, // 6.9 - SPIC Receive Interrupt + SPIC_TX_ISR, // 6.10 - SPIC Transmit Interrupt + PIE_RESERVED_ISR, // 6.11 - Reserved + PIE_RESERVED_ISR, // 6.12 - Reserved + PIE_RESERVED_ISR, // 6.13 - Reserved + PIE_RESERVED_ISR, // 6.14 - Reserved + PIE_RESERVED_ISR, // 6.15 - Reserved + PIE_RESERVED_ISR, // 6.16 - Reserved + PIE_RESERVED_ISR, // 7.9 - Reserved + PIE_RESERVED_ISR, // 7.10 - Reserved + PIE_RESERVED_ISR, // 7.11 - Reserved + PIE_RESERVED_ISR, // 7.12 - Reserved + PIE_RESERVED_ISR, // 7.13 - Reserved + PIE_RESERVED_ISR, // 7.14 - Reserved + PIE_RESERVED_ISR, // 7.15 - Reserved + PIE_RESERVED_ISR, // 7.16 - Reserved + PIE_RESERVED_ISR, // 8.9 - Reserved + PIE_RESERVED_ISR, // 8.10 - Reserved + PIE_RESERVED_ISR, // 8.11 - Reserved + PIE_RESERVED_ISR, // 8.12 - Reserved + PIE_RESERVED_ISR, // 8.13 - Reserved + PIE_RESERVED_ISR, // 8.14 - Reserved +#ifdef CPU1 + UPPA_ISR, // 8.15 - uPPA Interrupt + PIE_RESERVED_ISR, // 8.16 - Reserved +#elif defined(CPU2) + PIE_RESERVED_ISR, // 8.15 - Reserved + PIE_RESERVED_ISR, // 8.16 - Reserved +#endif + PIE_RESERVED_ISR, // 9.9 - Reserved + PIE_RESERVED_ISR, // 9.10 - Reserved + PIE_RESERVED_ISR, // 9.11 - Reserved + PIE_RESERVED_ISR, // 9.12 - Reserved + PIE_RESERVED_ISR, // 9.13 - Reserved + PIE_RESERVED_ISR, // 9.14 - Reserved +#ifdef CPU1 + USBA_ISR, // 9.15 - USBA Interrupt +#elif defined(CPU2) + PIE_RESERVED_ISR, // 9.15 - Reserved +#endif + PIE_RESERVED_ISR, // 9.16 - Reserved + ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt + ADCC2_ISR, // 10.10 - ADCC Interrupt 2 + ADCC3_ISR, // 10.11 - ADCC Interrupt 3 + ADCC4_ISR, // 10.12 - ADCC Interrupt 4 + ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt + ADCD2_ISR, // 10.14 - ADCD Interrupt 2 + ADCD3_ISR, // 10.15 - ADCD Interrupt 3 + ADCD4_ISR, // 10.16 - ADCD Interrupt 4 + PIE_RESERVED_ISR, // 11.9 - Reserved + PIE_RESERVED_ISR, // 11.10 - Reserved + PIE_RESERVED_ISR, // 11.11 - Reserved + PIE_RESERVED_ISR, // 11.12 - Reserved + PIE_RESERVED_ISR, // 11.13 - Reserved + PIE_RESERVED_ISR, // 11.14 - Reserved + PIE_RESERVED_ISR, // 11.15 - Reserved + PIE_RESERVED_ISR, // 11.16 - Reserved + EMIF_ERROR_ISR, // 12.9 - EMIF Error Interrupt + RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt + FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt + RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt + SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt + AUX_PLL_SLIP_ISR, // 12.14 - Auxiliary PLL Slip Interrupt + CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt + CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt +}; + +// +// InitPieVectTable - This function initializes the PIE vector table to a +// known state and must be executed after boot time. +// +void InitPieVectTable(void) +{ + Uint16 i; + Uint32 *Source = (void *) &PieVectTableInit; + Uint32 *Dest = (void *) &PieVectTable; + + // + // Do not write over first 3 32-bit locations (these locations are + // initialized by Boot ROM with boot variables) + // + Source = Source + 3; + Dest = Dest + 3; + + EALLOW; + for(i = 0; i < 221; i++) + { + *Dest++ = *Source++; + } + EDIS; + + // + // Enable the PIE Vector Table + // + PieCtrlRegs.PIECTRL.bit.ENPIE = 1; +} + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_SWPrioritizedPieVect.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_SWPrioritizedPieVect.c new file mode 100644 index 0000000000..7c2b5d1f56 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_SWPrioritizedPieVect.c @@ -0,0 +1,967 @@ +//########################################################################### +// +// FILE: F2837xD_SWPrioritizedPieVect.c +// +// TITLE: F2837xD Devices SW Prioritized PIE Vector Table Initialization. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" +#include "F2837xD_SWPrioritizedIsrLevels.h" + +const struct PIE_VECT_TABLE PieVectTableInit = +{ + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + PIE_RESERVED_ISR, // Reserved + + // + // Non-Peripheral Interrupts: + // + #if (INT13PL != 0) + TIMER1_ISR, // CPU Timer 1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (INT14PL != 0) + TIMER2_ISR, // CPU Timer 2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (INT15PL != 0) + DATALOG_ISR, // Datalogging interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (INT16PL != 0) + RTOS_ISR, // RTOS Interrupt + #else + INT_NOTUSED_ISR, + #endif + + EMU_ISR, // Emulation Interrupt + NMI_ISR, // Non-Maskable Interrupt + ILLEGAL_ISR, // Illegal Operation Trap + USER1_ISR, // User Defined Trap 1 + USER2_ISR, // User Defined Trap 2 + USER3_ISR, // User Defined Trap 3 + USER4_ISR, // User Defined Trap 4 + USER5_ISR, // User Defined Trap 5 + USER6_ISR, // User Defined Trap 6 + USER7_ISR, // User Defined Trap 7 + USER8_ISR, // User Defined Trap 8 + USER9_ISR, // User Defined Trap 9 + USER10_ISR, // User Defined Trap 10 + USER11_ISR, // User Defined Trap 11 + USER12_ISR, // User Defined Trap 12 + + // + // Group 1 PIE Vectors: + // + #if (G1_1PL != 0) + ADCA1_ISR, // 1.1 - ADCA Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_2PL != 0) + ADCB1_ISR, // 1.2 - ADCB Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_3PL != 0) + ADCC1_ISR, // 1.3 - ADCC Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_4PL != 0) + XINT1_ISR, // 1.4 - XINT1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_5PL != 0) + XINT2_ISR, // 1.5 - XINT2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_6PL != 0) + ADCD1_ISR, // 1.6 - ADCD Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_7PL != 0) + TIMER0_ISR, // 1.7 - Timer 0 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_8PL != 0) + WAKE_ISR, // 1.8 - Standby and Halt Wakeup Interrupt + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 2 PIE Vectors: + // + #if (G2_1PL != 0) + EPWM1_TZ_ISR, // 2.1 - ePWM1 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_2PL != 0) + EPWM2_TZ_ISR, // 2.2 - ePWM2 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_3PL != 0) + EPWM3_TZ_ISR, // 2.3 - ePWM3 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_4PL != 0) + EPWM4_TZ_ISR, // 2.4 - ePWM4 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_5PL != 0) + EPWM5_TZ_ISR, // 2.5 - ePWM5 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_6PL != 0) + EPWM6_TZ_ISR, // 2.6 - ePWM6 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_7PL != 0) + EPWM7_TZ_ISR, // 2.7 - ePWM7 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_8PL != 0) + EPWM8_TZ_ISR, // 2.8 - ePWM8 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 3 PIE Vectors: + // + #if (G3_1PL != 0) + EPWM1_ISR, // 3.1 - ePWM1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_2PL != 0) + EPWM2_ISR, // 3.2 - ePWM2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_3PL != 0) + EPWM3_ISR, // 3.3 - ePWM3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_4PL != 0) + EPWM4_ISR, // 3.4 - ePWM4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_5PL != 0) + EPWM5_ISR, // 3.5 - ePWM5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_6PL != 0) + EPWM6_ISR, // 3.6 - ePWM6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_7PL != 0) + EPWM7_ISR, // 3.7 - ePWM7 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_8PL != 0) + EPWM8_ISR, // 3.8 - ePWM8 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 4 PIE Vectors: + // + #if (G4_1PL != 0) + ECAP1_ISR, // 4.1 - eCAP1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G4_2PL != 0) + ECAP2_ISR, // 4.2 - eCAP2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G4_3PL != 0) + ECAP3_ISR, // 4.3 - eCAP3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G4_4PL != 0) + ECAP4_ISR, // 4.4 - eCAP4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G4_5PL != 0) + ECAP5_ISR, // 4.5 - eCAP5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G4_6PL != 0) + ECAP6_ISR, // 4.6 - eCAP6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + PIE_RESERVED_ISR, // 4.7 - Reserved + PIE_RESERVED_ISR, // 4.8 - Reserved + + // + // Group 5 PIE Vectors: + // + #if (G5_1PL != 0) + EQEP1_ISR, // 5.1 - eQEP1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G5_2PL != 0) + EQEP2_ISR, // 5.2 - eQEP2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G5_3PL != 0) + EQEP3_ISR, // 5.3 - eQEP3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + PIE_RESERVED_ISR, // 5.4 - Reserved + PIE_RESERVED_ISR, // 5.5 - Reserved + PIE_RESERVED_ISR, // 5.6 - Reserved + PIE_RESERVED_ISR, // 5.7 - Reserved + PIE_RESERVED_ISR, // 5.8 - Reserved + + // + // Group 6 PIE Vectors: + // + #if (G6_1PL != 0) + SPIA_RX_ISR, // 6.1 - SPIA Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_2PL != 0) + SPIA_TX_ISR, // 6.2 - SPIA Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_3PL != 0) + SPIB_RX_ISR, // 6.3 - SPIB Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_4PL != 0) + SPIB_TX_ISR, // 6.4 - SPIB Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_5PL != 0) + MCBSPA_RX_ISR, // 6.5 - McBSPA Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_6PL != 0) + MCBSPA_TX_ISR, // 6.6 - McBSPA Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_7PL != 0) + MCBSPB_RX_ISR, // 6.7 - McBSPB Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_8PL != 0) + MCBSPB_TX_ISR, // 6.8 - McBSPB Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 7 PIE Vectors: + // + #if (G7_1PL != 0) + DMA_CH1_ISR, // 7.1 - DMA Channel 1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G7_2PL != 0) + DMA_CH2_ISR, // 7.2 - DMA Channel 2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G7_3PL != 0) + DMA_CH3_ISR, // 7.3 - DMA Channel 3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G7_4PL != 0) + DMA_CH4_ISR, // 7.4 - DMA Channel 4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G7_5PL != 0) + DMA_CH5_ISR, // 7.5 - DMA Channel 5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G7_6PL != 0) + DMA_CH6_ISR, // 7.6 - DMA Channel 6 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + PIE_RESERVED_ISR, // 7.7 - Reserved + PIE_RESERVED_ISR, // 7.8 - Reserved + + // + // Group 8 PIE Vectors: + // + #if (G8_1PL != 0) + I2CA_ISR, // 8.1 - I2CA Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_2PL != 0) + I2CA_FIFO_ISR, // 8.2 - I2CA Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_3PL != 0) + I2CB_ISR, // 8.3 - I2CB Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_4PL != 0) + I2CB_FIFO_ISR, // 8.4 - I2CB Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_5PL != 0) + SCIC_RX_ISR, // 8.5 - SCIC Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_6PL != 0) + SCIC_TX_ISR, // 8.6 - SCIC Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_7PL != 0) + SCID_RX_ISR, // 8.7 - SCID Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G8_8PL != 0) + SCID_TX_ISR, // 8.8 - SCID Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 9 PIE Vectors: + // + #if (G9_1PL != 0) + SCIA_RX_ISR, // 9.1 - SCIA Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_2PL != 0) + SCIA_TX_ISR, // 9.2 - SCIA Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_3PL != 0) + SCIB_RX_ISR, // 9.3 - SCIB Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_4PL != 0) + SCIB_TX_ISR, // 9.4 - SCIB Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_5PL != 0) + CANA0_ISR, // 9.5 - CANA Interrupt 0 + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_6PL != 0) + CANA1_ISR, // 9.6 - CANA Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_7PL != 0) + CANB0_ISR, // 9.7 - CANB Interrupt 0 + #else + INT_NOTUSED_ISR, + #endif + + #if (G9_8PL != 0) + CANB1_ISR, // 9.8 - CANB Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 10 PIE Vectors + // + #if (G10_1PL != 0) + ADCA_EVT_ISR, // 10.1 - ADCA Event Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_2PL != 0) + ADCA2_ISR, // 10.2 - ADCA Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_3PL != 0) + ADCA3_ISR, // 10.3 - ADCA Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_4PL != 0) + ADCA4_ISR, // 10.4 - ADCA Interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_5PL != 0) + ADCB_EVT_ISR, // 10.5 - ADCB Event Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_6PL != 0) + ADCB2_ISR, // 10.6 - ADCB Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_7PL != 0) + ADCB3_ISR, // 10.7 - ADCB Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_8PL != 0) + ADCB4_ISR, // 10.8 - ADCB Interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 11 PIE Vectors + // + #if (G11_1PL != 0) + CLA1_1_ISR, // 11.1 - CLA1 Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_2PL != 0) + CLA1_2_ISR, // 11.2 - CLA1 Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_3PL != 0) + CLA1_3_ISR, // 11.3 - CLA1 Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_4PL != 0) + CLA1_4_ISR, // 11.4 - CLA1 Interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_5PL != 0) + CLA1_5_ISR, // 11.5 - CLA1 Interrupt 5 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_6PL != 0) + CLA1_6_ISR, // 11.6 - CLA1 Interrupt 6 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_7PL != 0) + CLA1_7_ISR, // 11.7 - CLA1 Interrupt 7 + #else + INT_NOTUSED_ISR, + #endif + + #if (G11_8PL != 0) + CLA1_8_ISR, // 11.8 - CLA1 Interrupt 8 + #else + INT_NOTUSED_ISR, + #endif + + // + // Group 12 PIE Vectors + // + #if (G12_1PL != 0) + XINT3_ISR, // 12.1 - XINT3 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_2PL != 0) + XINT4_ISR, // 12.2 - XINT4 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_3PL != 0) + XINT5_ISR, // 12.3 - XINT5 Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 12.4 - Reserved + PIE_RESERVED_ISR, // 12.5 - Reserved + + #if (G12_6PL != 0) + VCU_ISR, // 12.6 - VCU Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_7PL != 0) + FPU_OVERFLOW_ISR, // 12.7 - FPU Overflow Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_8PL != 0) + FPU_UNDERFLOW_ISR, // 12.8 - FPU Underflow Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 1.9 - Reserved + PIE_RESERVED_ISR, // 1.10 - Reserved + PIE_RESERVED_ISR, // 1.11 - Reserved + PIE_RESERVED_ISR, // 1.12 - Reserved + + #if (G1_13PL != 0) + IPC0_ISR, // 1.13 - IPC Interrupt 0 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_14PL != 0) + IPC1_ISR, // 1.14 - IPC Interrupt 1 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_15PL != 0) + IPC2_ISR, // 1.15 - IPC Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G1_16PL != 0) + IPC3_ISR, // 1.16 - IPC Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_9PL != 0) + EPWM9_TZ_ISR, // 2.9 - ePWM9 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_10PL != 0) + EPWM10_TZ_ISR, // 2.10 - ePWM10 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_11PL != 0) + EPWM11_TZ_ISR, // 2.11 - ePWM11 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G2_12PL != 0) + EPWM12_TZ_ISR, // 2.12 - ePWM12 Trip Zone Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 2.13 - Reserved + PIE_RESERVED_ISR, // 2.14 - Reserved + PIE_RESERVED_ISR, // 2.15 - Reserved + PIE_RESERVED_ISR, // 2.16 - Reserved + + #if (G3_9PL != 0) + EPWM9_ISR, // 3.9 - ePWM9 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_10PL != 0) + EPWM10_ISR, // 3.10 - ePWM10 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_11PL != 0) + EPWM11_ISR, // 3.11 - ePWM11 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G3_12PL != 0) + EPWM12_ISR, // 3.12 - ePWM12 Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 3.13 - Reserved + PIE_RESERVED_ISR, // 3.14 - Reserved + PIE_RESERVED_ISR, // 3.15 - Reserved + PIE_RESERVED_ISR, // 3.16 - Reserved + PIE_RESERVED_ISR, // 4.9 - Reserved + PIE_RESERVED_ISR, // 4.10 - Reserved + PIE_RESERVED_ISR, // 4.11 - Reserved + PIE_RESERVED_ISR, // 4.12 - Reserved + PIE_RESERVED_ISR, // 4.13 - Reserved + PIE_RESERVED_ISR, // 4.14 - Reserved + PIE_RESERVED_ISR, // 4.15 - Reserved + PIE_RESERVED_ISR, // 4.16 - Reserved + + #if (G5_9PL != 0) + SD1_ISR, // 5.9 - SD1 Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G5_10PL != 0) + SD2_ISR, // 5.10 - SD2 Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 5.11 - Reserved + PIE_RESERVED_ISR, // 5.12 - Reserved + PIE_RESERVED_ISR, // 5.13 - Reserved + PIE_RESERVED_ISR, // 5.14 - Reserved + PIE_RESERVED_ISR, // 5.15 - Reserved + PIE_RESERVED_ISR, // 5.16 - Reserved + + #if (G6_9PL != 0) + SPIC_RX_ISR, // 6.9 - SPIC Receive Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G6_10PL != 0) + SPIC_TX_ISR, // 6.10 - SPIC Transmit Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 6.11 - Reserved + PIE_RESERVED_ISR, // 6.12 - Reserved + PIE_RESERVED_ISR, // 6.13 - Reserved + PIE_RESERVED_ISR, // 6.14 - Reserved + PIE_RESERVED_ISR, // 6.15 - Reserved + PIE_RESERVED_ISR, // 6.16 - Reserved + PIE_RESERVED_ISR, // 7.9 - Reserved + PIE_RESERVED_ISR, // 7.10 - Reserved + PIE_RESERVED_ISR, // 7.11 - Reserved + PIE_RESERVED_ISR, // 7.12 - Reserved + PIE_RESERVED_ISR, // 7.13 - Reserved + PIE_RESERVED_ISR, // 7.14 - Reserved + PIE_RESERVED_ISR, // 7.15 - Reserved + PIE_RESERVED_ISR, // 7.16 - Reserved + PIE_RESERVED_ISR, // 8.9 - Reserved + PIE_RESERVED_ISR, // 8.10 - Reserved + PIE_RESERVED_ISR, // 8.11 - Reserved + PIE_RESERVED_ISR, // 8.12 - Reserved + PIE_RESERVED_ISR, // 8.13 - Reserved + PIE_RESERVED_ISR, // 8.14 - Reserved +#ifdef CPU1 + + #if (G8_15PL != 0) + UPPA_ISR, // 8.15 - uPPA Interrupt + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 8.16 - Reserved +#elif defined(CPU2) + PIE_RESERVED_ISR, // 8.15 - Reserved + PIE_RESERVED_ISR, // 8.16 - Reserved +#endif + PIE_RESERVED_ISR, // 9.9 - Reserved + PIE_RESERVED_ISR, // 9.10 - Reserved + PIE_RESERVED_ISR, // 9.11 - Reserved + PIE_RESERVED_ISR, // 9.12 - Reserved + PIE_RESERVED_ISR, // 9.13 - Reserved + PIE_RESERVED_ISR, // 9.14 - Reserved +#ifdef CPU1 + + #if (G9_15PL != 0) + USBA_ISR, // 9.15 - USBA Interrupt + #else + INT_NOTUSED_ISR, + #endif +#elif defined(CPU2) + PIE_RESERVED_ISR, // 9.15 - Reserved +#endif + PIE_RESERVED_ISR, // 9.16 - Reserved + + #if (G10_9PL != 0) + ADCC_EVT_ISR, // 10.9 - ADCC Event Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_10PL != 0) + ADCC2_ISR, // 10.10 - ADCC Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_11PL != 0) + ADCC3_ISR, // 10.11 - ADCC Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_12PL != 0) + ADCC4_ISR, // 10.12 - ADCC Interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_13PL != 0) + ADCD_EVT_ISR, // 10.13 - ADCD Event Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_14PL != 0) + ADCD2_ISR, // 10.14 - ADCD Interrupt 2 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_15PL != 0) + ADCD3_ISR, // 10.15 - ADCD Interrupt 3 + #else + INT_NOTUSED_ISR, + #endif + + #if (G10_16PL != 0) + ADCD4_ISR, // 10.16 - ADCD Interrupt 4 + #else + INT_NOTUSED_ISR, + #endif + PIE_RESERVED_ISR, // 11.9 - Reserved + PIE_RESERVED_ISR, // 11.10 - Reserved + PIE_RESERVED_ISR, // 11.11 - Reserved + PIE_RESERVED_ISR, // 11.12 - Reserved + PIE_RESERVED_ISR, // 11.13 - Reserved + PIE_RESERVED_ISR, // 11.14 - Reserved + PIE_RESERVED_ISR, // 11.15 - Reserved + PIE_RESERVED_ISR, // 11.16 - Reserved + + #if (G12_9PL != 0) + EMIF_ERROR_ISR, // 12.9 - EMIF Error Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_10PL != 0) + RAM_CORRECTABLE_ERROR_ISR, // 12.10 - RAM Correctable Error Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_11PL != 0) + FLASH_CORRECTABLE_ERROR_ISR, // 12.11 - Flash Correctable Error Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_12PL != 0) + RAM_ACCESS_VIOLATION_ISR, // 12.12 - RAM Access Violation Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_13PL != 0) + SYS_PLL_SLIP_ISR, // 12.13 - System PLL Slip Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_14PL != 0) + AUX_PLL_SLIP_ISR, // 12.14 - Auxiliary PLL Slip Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_15PL != 0) + CLA_OVERFLOW_ISR, // 12.15 - CLA Overflow Interrupt + #else + INT_NOTUSED_ISR, + #endif + + #if (G12_16PL != 0) + CLA_UNDERFLOW_ISR // 12.16 - CLA Underflow Interrupt + #else + INT_NOTUSED_ISR, + #endif + +}; + +// +// InitPieVectTable - This function initializes the PIE vector table to a known +// state. This function must be executed after boot time. +// +void +InitPieVectTable(void) +{ + int16 i; + Uint32 *Source = (void *) &PieVectTableInit; + Uint32 *Dest = (void *) &PieVectTable; + + EALLOW; + for(i=0; i < 221; i++) + { + *Dest++ = *Source++; + } + EDIS; +} + +// +// End of File +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Sci.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Sci.c new file mode 100644 index 0000000000..e21b934a5e --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Sci.c @@ -0,0 +1,48 @@ +//########################################################################### +// +// FILE: F2837xD_Sci.c +// +// TITLE: F2837xD SCI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "F2837xD_device.h" // F2837xD Headerfile Include File +#include "F2837xD_Examples.h" // F2837xD Examples Include File + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Spi.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Spi.c new file mode 100644 index 0000000000..1a82751d7e --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Spi.c @@ -0,0 +1,175 @@ +//########################################################################### +// +// FILE: F2837xD_Spi.c +// +// TITLE: F2837xD SPI Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// Calculate BRR: 7-bit baud rate register value +// SPI CLK freq = 500 kHz +// LSPCLK freq = CPU freq / 4 (by default) +// BRR = (LSPCLK freq / SPI CLK freq) - 1 +// +#if CPU_FRQ_200MHZ +#define SPI_BRR ((200E6 / 4) / 500E3) - 1 +#endif + +#if CPU_FRQ_150MHZ +#define SPI_BRR ((150E6 / 4) / 500E3) - 1 +#endif + +#if CPU_FRQ_120MHZ +#define SPI_BRR ((120E6 / 4) / 500E3) - 1 +#endif + +// +// InitSPI - This function initializes the SPI to a known state +// +void InitSpi(void) +{ + // Initialize SPI-A + + // Set reset low before configuration changes + // Clock polarity (0 == rising, 1 == falling) + // 16-bit character + // Enable loop-back + SpiaRegs.SPICCR.bit.SPISWRESET = 0; + SpiaRegs.SPICCR.bit.CLKPOLARITY = 0; + SpiaRegs.SPICCR.bit.SPICHAR = (16-1); + SpiaRegs.SPICCR.bit.SPILBK = 1; + + // Enable master (0 == slave, 1 == master) + // Enable transmission (Talk) + // Clock phase (0 == normal, 1 == delayed) + // SPI interrupts are disabled + SpiaRegs.SPICTL.bit.MASTER_SLAVE = 1; + SpiaRegs.SPICTL.bit.TALK = 1; + SpiaRegs.SPICTL.bit.CLK_PHASE = 0; + SpiaRegs.SPICTL.bit.SPIINTENA = 0; + + // Set the baud rate + SpiaRegs.SPIBRR.bit.SPI_BIT_RATE = SPI_BRR; + + // Set FREE bit + // Halting on a breakpoint will not halt the SPI + SpiaRegs.SPIPRI.bit.FREE = 1; + + // Release the SPI from reset + SpiaRegs.SPICCR.bit.SPISWRESET = 1; +} + +// +// InitSpiGpio - This function initializes GPIO pins to function as SPI pins. +// Each GPIO pin can be configured as a GPIO pin or up to 3 +// different peripheral functional pins. By default all pins come +// up as GPIO inputs after reset. +// +// Caution: +// For each SPI peripheral +// Only one GPIO pin should be enabled for SPISOMO operation. +// Only one GPIO pin should be enabled for SPISOMI operation. +// Only one GPIO pin should be enabled for SPICLK operation. +// Only one GPIO pin should be enabled for SPISTE operation. +// Comment out other unwanted lines. +// +void InitSpiGpio() +{ + InitSpiaGpio(); +} + +// +// InitSpiaGpio - Initialize SPIA GPIOs +// +void InitSpiaGpio() +{ + EALLOW; + + // + // Enable internal pull-up for the selected pins + // + // Pull-ups can be enabled or disabled by the user. + // This will enable the pullups for the specified pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 0; // Enable pull-up on GPIO16 (SPISIMOA) +// GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0; // Enable pull-up on GPIO5 (SPISIMOA) + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 0; // Enable pull-up on GPIO17 (SPISOMIA) +// GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0; // Enable pull-up on GPIO3 (SPISOMIA) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 0; // Enable pull-up on GPIO18 (SPICLKA) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 0; // Enable pull-up on GPIO19 (SPISTEA) + + // + // Set qualification for selected pins to asynch only + // + // This will select asynch (no qualification) for the selected pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Asynch input GPIO16 (SPISIMOA) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO5 = 3; // Asynch input GPIO5 (SPISIMOA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Asynch input GPIO17 (SPISOMIA) +// GpioCtrlRegs.GPAQSEL1.bit.GPIO3 = 3; // Asynch input GPIO3 (SPISOMIA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Asynch input GPIO18 (SPICLKA) + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Asynch input GPIO19 (SPISTEA) + + // + //Configure SPI-A pins using GPIO regs + // + // This specifies which of the possible GPIO pins will be SPI functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 1; // Configure GPIO16 as SPISIMOA +// GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 2; // Configure GPIO5 as SPISIMOA + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 1; // Configure GPIO17 as SPISOMIA +// GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 2; // Configure GPIO3 as SPISOMIA + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 1; // Configure GPIO18 as SPICLKA + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 1; // Configure GPIO19 as SPISTEA + + EDIS; +} + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_SysCtrl.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_SysCtrl.c new file mode 100644 index 0000000000..0971cee2d5 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_SysCtrl.c @@ -0,0 +1,1276 @@ +//########################################################################### +// +// FILE: F2837xD_SysCtrl.c +// +// TITLE: F2837xD Device System Control Initialization & Support Functions. +// +// DESCRIPTION: +// +// Example initialization of system resources. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" +#ifdef __cplusplus +using std::memcpy; +#endif + +#define STATUS_FAIL 0 +#define STATUS_SUCCESS 1 +#define TMR1SYSCLKCTR 0xF0000000 +#define TMR2INPCLKCTR 0x800 + +// +// Functions that will be run from RAM need to be assigned to a different +// section. This section will then be mapped to a load and run address using +// the linker cmd file. +// +// *IMPORTANT* +// +// IF RUNNING FROM FLASH, PLEASE COPY OVER THE SECTION ".TI.ramfunc" FROM +// FLASH TO RAM PRIOR TO CALLING InitSysCtrl(). THIS PREVENTS THE MCU FROM +// THROWING AN EXCEPTION WHEN A CALL TO DELAY_US() IS MADE. +// +#ifndef __cplusplus + #ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(InitFlash, ".TI.ramfunc"); + #pragma CODE_SECTION(FlashOff, ".TI.ramfunc"); + #else + #pragma CODE_SECTION(InitFlash, "ramfuncs"); + #pragma CODE_SECTION(FlashOff, "ramfuncs"); + #endif + #endif +#endif + +// +// InitSysCtrl - Initialization of system resources. +// +void InitSysCtrl(void) +{ + // + // Disable the watchdog + // + DisableDog(); + +#ifdef _FLASH + // + // Copy time critical code and Flash setup code to RAM. This includes the + // following functions: InitFlash() + // + // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart + // symbols are created by the linker. Refer to the device .cmd file. + // + memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); + + // + // Call Flash Initialization to setup flash waitstates. This function must + // reside in RAM. + // + InitFlash(); +#endif + + // + // *IMPORTANT* + // + // The Device_cal function, which copies the ADC & oscillator calibration + // values from TI reserved OTP into the appropriate trim registers, occurs + // automatically in the Boot ROM. If the boot ROM code is bypassed during + // the debug process, the following function MUST be called for the ADC and + // oscillators to function according to specification. The clocks to the + // ADC MUST be enabled before calling this function. + // + // See the device data manual and/or the ADC Reference Manual for more + // information. + // +#ifdef CPU1 + EALLOW; + + // + // Enable pull-ups on unbonded IOs as soon as possible to reduce power + // consumption. + // + GPIO_EnableUnbondedIOPullups(); + + CpuSysRegs.PCLKCR13.bit.ADC_A = 1; + CpuSysRegs.PCLKCR13.bit.ADC_B = 1; + CpuSysRegs.PCLKCR13.bit.ADC_C = 1; + CpuSysRegs.PCLKCR13.bit.ADC_D = 1; + + // + // Check if device is trimmed + // + if(*((Uint16 *)0x5D1B6) == 0x0000){ + // + // Device is not trimmed--apply static calibration values + // + AnalogSubsysRegs.ANAREFTRIMA.all = 31709; + AnalogSubsysRegs.ANAREFTRIMB.all = 31709; + AnalogSubsysRegs.ANAREFTRIMC.all = 31709; + AnalogSubsysRegs.ANAREFTRIMD.all = 31709; + } + + CpuSysRegs.PCLKCR13.bit.ADC_A = 0; + CpuSysRegs.PCLKCR13.bit.ADC_B = 0; + CpuSysRegs.PCLKCR13.bit.ADC_C = 0; + CpuSysRegs.PCLKCR13.bit.ADC_D = 0; + EDIS; + + // + // Initialize the PLL control: SYSPLLMULT and SYSCLKDIVSEL. + // + // Defined options to be passed as arguments to this function are defined + // in F2837xD_Examples.h. + // + // Note: The internal oscillator CANNOT be used as the PLL source if the + // PLLSYSCLK is configured to frequencies above 194 MHz. + // + // PLLSYSCLK = (XTAL_OSC) * (IMULT + FMULT) / (PLLSYSCLKDIV) + // +#ifdef _LAUNCHXL_F28379D + InitSysPll(XTAL_OSC,IMULT_40,FMULT_0,PLLCLK_BY_2); +#else + InitSysPll(XTAL_OSC, IMULT_20, FMULT_0, PLLCLK_BY_2); +#endif // _LAUNCHXL_F28379D + +#endif // CPU1 + + // + // Turn on all peripherals + // + InitPeripheralClocks(); +} + +// +// InitPeripheralClocks - Initializes the clocks for the peripherals. +// +// Note: In order to reduce power consumption, turn off the clocks to any +// peripheral that is not specified for your part-number or is not used in the +// application +// +void InitPeripheralClocks(void) +{ + EALLOW; + + CpuSysRegs.PCLKCR0.bit.CLA1 = 1; + CpuSysRegs.PCLKCR0.bit.DMA = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER0 = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER1 = 1; + CpuSysRegs.PCLKCR0.bit.CPUTIMER2 = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR0.bit.HRPWM = 1; +#endif + + CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR1.bit.EMIF1 = 1; + CpuSysRegs.PCLKCR1.bit.EMIF2 = 1; +#endif + + CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM2 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM3 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM4 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM5 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM6 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM7 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM8 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM9 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM10 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM11 = 1; + CpuSysRegs.PCLKCR2.bit.EPWM12 = 1; + + CpuSysRegs.PCLKCR3.bit.ECAP1 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP2 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP3 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP4 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP5 = 1; + CpuSysRegs.PCLKCR3.bit.ECAP6 = 1; + + CpuSysRegs.PCLKCR4.bit.EQEP1 = 1; + CpuSysRegs.PCLKCR4.bit.EQEP2 = 1; + CpuSysRegs.PCLKCR4.bit.EQEP3 = 1; + + CpuSysRegs.PCLKCR6.bit.SD1 = 1; + CpuSysRegs.PCLKCR6.bit.SD2 = 1; + + CpuSysRegs.PCLKCR7.bit.SCI_A = 1; + CpuSysRegs.PCLKCR7.bit.SCI_B = 1; + CpuSysRegs.PCLKCR7.bit.SCI_C = 1; + CpuSysRegs.PCLKCR7.bit.SCI_D = 1; + + CpuSysRegs.PCLKCR8.bit.SPI_A = 1; + CpuSysRegs.PCLKCR8.bit.SPI_B = 1; + CpuSysRegs.PCLKCR8.bit.SPI_C = 1; + + CpuSysRegs.PCLKCR9.bit.I2C_A = 1; + CpuSysRegs.PCLKCR9.bit.I2C_B = 1; + + CpuSysRegs.PCLKCR10.bit.CAN_A = 1; + CpuSysRegs.PCLKCR10.bit.CAN_B = 1; + + CpuSysRegs.PCLKCR11.bit.McBSP_A = 1; + CpuSysRegs.PCLKCR11.bit.McBSP_B = 1; + +#ifdef CPU1 + CpuSysRegs.PCLKCR11.bit.USB_A = 1; + + CpuSysRegs.PCLKCR12.bit.uPP_A = 1; +#endif + + CpuSysRegs.PCLKCR13.bit.ADC_A = 1; + CpuSysRegs.PCLKCR13.bit.ADC_B = 1; + CpuSysRegs.PCLKCR13.bit.ADC_C = 1; + CpuSysRegs.PCLKCR13.bit.ADC_D = 1; + + CpuSysRegs.PCLKCR14.bit.CMPSS1 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS2 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS3 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS4 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS5 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS6 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS7 = 1; + CpuSysRegs.PCLKCR14.bit.CMPSS8 = 1; + + CpuSysRegs.PCLKCR16.bit.DAC_A = 1; + CpuSysRegs.PCLKCR16.bit.DAC_B = 1; + CpuSysRegs.PCLKCR16.bit.DAC_C = 1; + + EDIS; +} + +// +// DisablePeripheralClocks - Gates-off all peripheral clocks. +// +void DisablePeripheralClocks(void) +{ + EALLOW; + + CpuSysRegs.PCLKCR0.all = 0; + CpuSysRegs.PCLKCR1.all = 0; + CpuSysRegs.PCLKCR2.all = 0; + CpuSysRegs.PCLKCR3.all = 0; + CpuSysRegs.PCLKCR4.all = 0; + CpuSysRegs.PCLKCR6.all = 0; + CpuSysRegs.PCLKCR7.all = 0; + CpuSysRegs.PCLKCR8.all = 0; + CpuSysRegs.PCLKCR9.all = 0; + CpuSysRegs.PCLKCR10.all = 0; + CpuSysRegs.PCLKCR11.all = 0; + CpuSysRegs.PCLKCR12.all = 0; + CpuSysRegs.PCLKCR13.all = 0; + CpuSysRegs.PCLKCR14.all = 0; + CpuSysRegs.PCLKCR16.all = 0; + + EDIS; +} + +// +// InitFlash - This function initializes the Flash Control registers. +// +// *CAUTION* +// This function MUST be executed out of RAM. Executing it out of OTP/Flash +// will yield unpredictable results. +// +#ifdef __cplusplus + #ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(".TI.ramfunc"); + #else + #pragma CODE_SECTION("ramfuncs"); + #endif + #endif +#endif +void InitFlash(void) +{ + EALLOW; + + // + // The default value of VREADST is good enough for the flash to power up + // properly at the INTOSC frequency. Below VREADST configuration covers up + // to the max frequency possible for this device. This is required for + // proper flash wake up at the higher frequencies if users put it to sleep + // for power saving reason. + // + Flash0CtrlRegs.FBAC.bit.VREADST = 0x14; + + // + // At reset bank and pump are in sleep. A Flash access will power up the + // bank and pump automatically. + // + // After a Flash access, bank and pump go to low power mode (configurable + // in FBFALLBACK/FPAC1 registers) if there is no further access to flash. + // + // Power up Flash bank and pump. This also sets the fall back mode of + // flash and pump as active. + // + Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0x1; + Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0x3; + + // + // Disable Cache and prefetch mechanism before changing wait states + // + Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 0; + Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 0; + + // + // Set waitstates according to frequency + // + // *CAUTION* + // Minimum waitstates required for the flash operating at a given CPU rate + // must be characterized by TI. Refer to the datasheet for the latest + // information. + // + #if CPU_FRQ_200MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x3; + #endif + + #if CPU_FRQ_150MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2; + #endif + + #if CPU_FRQ_120MHZ + Flash0CtrlRegs.FRDCNTL.bit.RWAIT = 0x2; + #endif + + // + // Enable Cache and prefetch mechanism to improve performance of code + // executed from Flash. + // + Flash0CtrlRegs.FRD_INTF_CTRL.bit.DATA_CACHE_EN = 1; + Flash0CtrlRegs.FRD_INTF_CTRL.bit.PREFETCH_EN = 1; + + // + // At reset, ECC is enabled. If it is disabled by application software and + // if application again wants to enable ECC. + // + Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA; + + EDIS; + + // + // Force a pipeline flush to ensure that the write to the last register + // configured occurs before returning. + // + __asm(" RPT #7 || NOP"); +} + +// +// FlashOff - This function powers down the flash +// +// *CAUTION* +// This function MUST be executed out of RAM. Executing it out of OTP/Flash +// will yield unpredictable results. Also you must seize the flash pump in +// order to power it down. +// +#ifdef __cplusplus + #ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #pragma CODE_SECTION(".TI.ramfunc"); + #else + #pragma CODE_SECTION("ramfuncs"); + #endif + #endif +#endif +void FlashOff(void) +{ + EALLOW; + + // + // Set VREADST to the proper value for the flash banks to power up properly + // + Flash0CtrlRegs.FBAC.bit.VREADST = 0x14; + + // + // Power down bank + // + Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0; + + // + // Power down pump + // + Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0; + + EDIS; +} + +// +// SeizeFlashPump - Wait until the flash pump is available. Then take control +// of it using the flash pump Semaphore. +// +void SeizeFlashPump(void) +{ + EALLOW; + #ifdef CPU1 + while (FlashPumpSemaphoreRegs.PUMPREQUEST.bit.PUMP_OWNERSHIP != 0x2) + { + FlashPumpSemaphoreRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x2; + } + #elif defined(CPU2) + while (FlashPumpSemaphoreRegs.PUMPREQUEST.bit.PUMP_OWNERSHIP != 0x1) + { + FlashPumpSemaphoreRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x1; + } + #endif + EDIS; +} + +// +// ReleaseFlashPump - Release control of the flash pump using the flash pump +// semaphore. +// +void ReleaseFlashPump(void) +{ + EALLOW; + FlashPumpSemaphoreRegs.PUMPREQUEST.all = IPC_PUMP_KEY | 0x0; + EDIS; +} + +// +// ServiceDog - This function resets the watchdog timer. +// +// Enable this function for using ServiceDog in the application. +// +void ServiceDog(void) +{ + EALLOW; + WdRegs.WDKEY.bit.WDKEY = 0x0055; + WdRegs.WDKEY.bit.WDKEY = 0x00AA; + EDIS; +} + +// +// DisableDog - This function disables the watchdog timer. +// +void DisableDog(void) +{ + volatile Uint16 temp; + + // + // Grab the clock config first so we don't clobber it + // + EALLOW; + temp = WdRegs.WDCR.all & 0x0007; + WdRegs.WDCR.all = 0x0068 | temp; + EDIS; +} + +#ifdef CPU1 +// +// InitSysPll() +// This function initializes the PLL registers. +// Note: +// - The internal oscillator CANNOT be used as the PLL source if the +// PLLSYSCLK is configured to frequencies above 194 MHz. +// +// - This function uses the Watchdog as a monitor for the PLL. The user +// watchdog settings will be modified and restored upon completion. Function +// allows for a minimum re lock attempt for 5 tries. Re lock attempt is carried +// out if either SLIP condition occurs or SYSCLK to Input Clock ratio is off by 10% +// +// - This function uses the following resources to support PLL initialization: +// o Watchdog +// o CPU Timer 1 +// o CPU Timer 2 +// +void InitSysPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel) +{ + Uint16 SCSR, WDCR, WDWCR, intStatus, t1TCR, t1TPR, t1TPRH; + Uint16 t2TCR, t2TPR, t2TPRH, t2SRC, t2Prescale; + Uint32 t1PRD, t2PRD, ctr1; + float sysclkToInClkError, mult, div; + bool sysclkInvalidFreq=true; + + if((clock_source == ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) && + (imult == ClkCfgRegs.SYSPLLMULT.bit.IMULT) && + (fmult == ClkCfgRegs.SYSPLLMULT.bit.FMULT) && + (divsel == ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV)) + { + // + // Everything is set as required, so just return + // + return; + } + + if(clock_source != ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL) + { + switch (clock_source) + { + case INT_OSC1: + SysIntOsc1Sel(); + break; + + case INT_OSC2: + SysIntOsc2Sel(); + break; + + case XTAL_OSC: + SysXtalOscSel(); + break; + } + } + + EALLOW; + if(imult != ClkCfgRegs.SYSPLLMULT.bit.IMULT || + fmult != ClkCfgRegs.SYSPLLMULT.bit.FMULT) + { + Uint16 i; + + // + // This bit is reset only by POR + // + if(DevCfgRegs.SYSDBGCTL.bit.BIT_0 == 1) + { + // + // The user can optionally insert handler code here. This will only + // be executed if a watchdog reset occurred after a failed system + // PLL initialization. See your device user's guide for more + // information. + // + // If the application has a watchdog reset handler, this bit should + // be checked to determine if the watchdog reset occurred because + // of the PLL. + // + // No action here will continue with retrying the PLL as normal. + // + // Failed PLL initialization is due to any of the following: + // - No PLL clock + // - SLIP condition + // - Wrong Frequency + // + } + + // + // Bypass PLL and set dividers to /1 + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + asm(" RPT #20 || NOP"); + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = 0; + + // + // Lock the PLL five times. This helps ensure a successful start. + // Five is the minimum recommended number. The user can increase this + // number according to allotted system initialization time. + // + for(i = 0; i < 5; i++) + { + // + // Turn off PLL + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + asm(" RPT #20 || NOP"); + + // + // Write multiplier, which automatically turns on the PLL + // + ClkCfgRegs.SYSPLLMULT.all = ((fmult << 8U) | imult); + + // + // Wait for the SYSPLL lock counter + // + while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1) + { + // + // Uncomment to service the watchdog + // + // ServiceDog(); + } + } + } + + // + // Set divider to produce slower output frequency to limit current increase + // + if(divsel != PLLCLK_BY_126) + { + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel + 1; + } + else + { + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; + } + + // + // *CAUTION* + // It is recommended to use the following watchdog code to monitor the PLL + // startup sequence. If your application has already cleared the watchdog + // SCRS[WDOVERRIDE] bit this cannot be done. It is recommended not to clear + // this bit until after the PLL has been initiated. + // + + // + // Backup User Watchdog + // + SCSR = WdRegs.SCSR.all; + WDCR = WdRegs.WDCR.all; + WDWCR = WdRegs.WDWCR.all; + + // + // Disable windowed functionality, reset counter + // + EALLOW; + WdRegs.WDWCR.all = 0x0; + WdRegs.WDKEY.bit.WDKEY = 0x55; + WdRegs.WDKEY.bit.WDKEY = 0xAA; + + // + // Disable global interrupts + // + intStatus = __disable_interrupts(); + + // + // Configure for watchdog reset and to run at max frequency + // + WdRegs.SCSR.all = 0x0; + WdRegs.WDCR.all = 0x28; + + // + // This bit is reset only by power-on-reset (POR) and will not be cleared + // by a WD reset + // + DevCfgRegs.SYSDBGCTL.bit.BIT_0 = 1; + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; + + // + // Delay to ensure system is clocking from PLL prior to clearing status bit + // + asm(" RPT #20 || NOP"); + + // + // Service watchdog + // + ServiceDog(); + + // + // Slip Bit Monitor and SYSCLK Frequency Check using timers + // Re-lock routine for SLIP condition or if SYSCLK and CLKSRC timer counts + // are off by +/- 10%. + // At a minimum, SYSCLK check is performed. Re lock attempt is carried out + // if SLIPS bit is set. This while loop is monitored by watchdog. + // In the event that the PLL does not successfully lock, the loop will be + // aborted by watchdog reset. + // + EALLOW; + while(sysclkInvalidFreq == true) + { + if(ClkCfgRegs.SYSPLLSTS.bit.SLIPS == 1) + { + // + // Bypass PLL + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + asm(" RPT #20 || NOP"); + + // + // Turn off PLL + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + asm(" RPT #20 || NOP"); + + // + // Write multipliers, which automatically turns on the PLL + // + ClkCfgRegs.SYSPLLMULT.all = ((fmult << 8U) | imult); + + // + // Wait for the SYSPLL lock counter to expire + // + while(ClkCfgRegs.SYSPLLSTS.bit.LOCKS != 1); + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 1; + + // + // Delay to ensure system is clocking from PLL + // + asm(" RPT #20 || NOP"); + } + + // + // Backup timer1 and timer2 settings + // + t1TCR = CpuTimer1Regs.TCR.all; + t1PRD = CpuTimer1Regs.PRD.all; + t1TPR = CpuTimer1Regs.TPR.all; + t1TPRH = CpuTimer1Regs.TPRH.all; + t2SRC = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL; + t2Prescale = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE; + t2TCR = CpuTimer2Regs.TCR.all; + t2PRD = CpuTimer2Regs.PRD.all; + t2TPR = CpuTimer2Regs.TPR.all; + t2TPRH = CpuTimer2Regs.TPRH.all; + + // + // Set up timers 1 and 2 + // Configure timer1 to count SYSCLK cycles + // + CpuTimer1Regs.TCR.bit.TSS = 1; // stop timer1 + CpuTimer1Regs.PRD.all = TMR1SYSCLKCTR; // seed timer1 counter + CpuTimer1Regs.TPR.bit.TDDR = 0x0; // sysclock divider + CpuTimer1Regs.TCR.bit.TRB = 1; // reload timer with value in PRD + CpuTimer1Regs.TCR.bit.TIF = 1; // clear interrupt flag + CpuTimer1Regs.TCR.bit.TIE = 1; // enable interrupt + + // + // Configure timer2 to count Input clock cycles + // + switch(clock_source) + { + case INT_OSC1: + // Clk Src = INT_OSC1 + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x1; + break; + case INT_OSC2: + // Clk Src = INT_OSC2 + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x2; + break; + case XTAL_OSC: + // Clk Src = XTAL + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x3; + break; + + } + CpuTimer2Regs.TCR.bit.TIF = 1; // clear interrupt flag + CpuTimer2Regs.TCR.bit.TIE = 1; // enable interrupt + CpuTimer2Regs.TCR.bit.TSS = 1; // stop timer2 + CpuTimer2Regs.PRD.all = TMR2INPCLKCTR; // seed timer2 counter + CpuTimer2Regs.TPR.bit.TDDR = 0x0; // sysclock divider + CpuTimer2Regs.TCR.bit.TRB = 1; // reload timer with value in PRD + + // + // Stop/Start timer counters + // + CpuTimer1Regs.TCR.bit.TSS = 1; // stop timer1 + CpuTimer2Regs.TCR.bit.TSS = 1; // stop timer2 + CpuTimer1Regs.TCR.bit.TRB = 1; // reload timer1 with value in PRD + CpuTimer2Regs.TCR.bit.TRB = 1; // reload timer2 with value in PRD + CpuTimer2Regs.TCR.bit.TIF = 1; // clear timer2 interrupt flag + CpuTimer2Regs.TCR.bit.TSS = 0; // start timer2 + CpuTimer1Regs.TCR.bit.TSS = 0; // start timer1 + + // + // Stop timers if either timer1 or timer2 counters overflow + // + while((CpuTimer2Regs.TCR.bit.TIF == 0) && (CpuTimer1Regs.TCR.bit.TIF == 0)); + + CpuTimer1Regs.TCR.bit.TSS = 1; // stop timer1 + CpuTimer2Regs.TCR.bit.TSS = 1; // stop timer2 + + // + // Calculate elapsed counts on timer1 + // + ctr1 = TMR1SYSCLKCTR - CpuTimer1Regs.TIM.all; + + // + // Restore timer settings + // + CpuTimer1Regs.TCR.all = t1TCR; + CpuTimer1Regs.PRD.all = t1PRD; + CpuTimer1Regs.TPR.all = t1TPR; + CpuTimer1Regs.TPRH.all = t1TPRH; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = t2SRC; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE = t2Prescale; + CpuTimer2Regs.TCR.all = t2TCR; + CpuTimer2Regs.PRD.all = t2PRD; + CpuTimer2Regs.TPR.all = t2TPR; + CpuTimer2Regs.TPRH.all = t2TPRH; + + // + // Calculate Clock Error: + // Error = (mult/div) - (timer1 count/timer2 count) + // + mult = (float)(imult) + (float)(fmult)/4; + div = (float)((!ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV) ? 1 : (ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV << 1)); + + sysclkToInClkError = (mult/div) - ((float)ctr1/(float)TMR2INPCLKCTR); + + // + // sysclkInvalidFreq will be set to true if sysclkToInClkError is off by 10% + // + sysclkInvalidFreq = ((sysclkToInClkError > 0.10) || (sysclkToInClkError < -0.10)); + } + + // + // Clear bit + // + DevCfgRegs.SYSDBGCTL.bit.BIT_0 = 0; + + // + // Restore user watchdog, first resetting counter + // + WdRegs.WDKEY.bit.WDKEY = 0x55; + WdRegs.WDKEY.bit.WDKEY = 0xAA; + + WDCR |= 0x28; // Setup WD key--KEY bits always read 0 + WdRegs.WDCR.all = WDCR; + WdRegs.WDWCR.all = WDWCR; + WdRegs.SCSR.all = SCSR & 0xFFFE; // Mask write to bit 0 (W1toClr) + + // + // Restore state of ST1[INTM]. This was set by the __disable_interrupts() + // intrinsic previously. + // + if(!(intStatus & 0x1)) + { + EINT; + } + + // + // Restore state of ST1[DBGM]. This was set by the __disable_interrupts() + // intrinsic previously. + // + if(!(intStatus & 0x2)) + { + asm(" CLRC DBGM"); + } + + // + // 200 PLLSYSCLK delay to allow voltage regulator to stabilize prior + // to increasing entire system clock frequency. + // + asm(" RPT #200 || NOP"); + + // + // Set the divider to user value + // + ClkCfgRegs.SYSCLKDIVSEL.bit.PLLSYSCLKDIV = divsel; + + EDIS; +} +#endif // CPU1 + +// +// InitAuxPll - This function initializes the AUXPLL registers. +// +// Note: For this function to properly detect PLL startup, +// SYSCLK >= 2*AUXPLLCLK after the AUXPLL is selected as the clocking source. +// +// This function will use CPU Timer 2 to monitor a successful lock of the +// AUXPLL. +// +void InitAuxPll(Uint16 clock_source, Uint16 imult, Uint16 fmult, Uint16 divsel) +{ + Uint16 i; + Uint16 counter = 0; + Uint16 started = 0; + Uint16 t2TCR, t2TPR, t2TPRH, t2SRC, t2Prescale, attempts; + Uint32 t2PRD; + + if((clock_source == ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL) && + (imult == ClkCfgRegs.AUXPLLMULT.bit.IMULT) && + (fmult == ClkCfgRegs.AUXPLLMULT.bit.FMULT) && + (divsel == ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV)) + { + // + // Everything is set as required, so just return + // + return; + } + + switch (clock_source) + { + case INT_OSC2: + AuxIntOsc2Sel(); + break; + + case XTAL_OSC: + AuxXtalOscSel(); + break; + + case AUXCLKIN: + AuxAuxClkSel(); + break; + } + + // + // Backup Timer 2 settings + // + t2SRC = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL; + t2Prescale = CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE; + t2TCR = CpuTimer2Regs.TCR.all; + t2PRD = CpuTimer2Regs.PRD.all; + t2TPR = CpuTimer2Regs.TPR.all; + t2TPRH = CpuTimer2Regs.TPRH.all; + + // + // Configure Timer 2 for AUXPLL as source in known configuration + // + EALLOW; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = 0x6; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE = 0x0; // Divide by 1 + + CpuTimer2Regs.TCR.bit.TSS = 1; // Stop timer + CpuTimer2Regs.PRD.all = 10; // Small PRD value to detect overflow + CpuTimer2Regs.TPR.all = 0; + CpuTimer2Regs.TPRH.all = 0; + CpuTimer2Regs.TCR.bit.TIE = 0; // Disable timer interrupts + + // + // Set AUX Divide by 8 to ensure that AUXPLLCLK <= SYSCLK/2 while using + // Timer 2 + // + ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = 0x3; + EDIS; + + while((counter < 5) && (started == 0)) + { + EALLOW; + ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 0; // Turn off AUXPLL + asm(" RPT #20 || NOP"); // Small delay for power down + + // + // Set integer and fractional multiplier, which automatically turns on + // the PLL + // + ClkCfgRegs.AUXPLLMULT.all = ((fmult << 8U) | imult); + + // + // Enable AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 1; + EDIS; + + // + // Wait for the AUXPLL lock counter + // + while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1) + { + // + // Uncomment to service the watchdog + // + // ServiceDog(); + } + + // + // Enable AUXPLLCLK to be fed from AUX PLL + // + EALLOW; + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1; + asm(" RPT #20 || NOP"); + + // + // CPU Timer 2 will now be setup to be clocked from AUXPLLCLK. This is + // used to test that the PLL has successfully started. + // + CpuTimer2Regs.TCR.bit.TRB = 1; // Reload period value + CpuTimer2Regs.TCR.bit.TSS = 0; // Start Timer + + // + // Check to see timer is counting properly + // + for(i = 0; i < 1000; i++) + { + // + // Check overflow flag + // + if(CpuTimer2Regs.TCR.bit.TIF) + { + // + // Clear overflow flag + // + CpuTimer2Regs.TCR.bit.TIF = 1; + + // + // Set flag to indicate PLL started and break out of for-loop + // + started = 1; + break; + } + } + + // + // Stop timer + // + CpuTimer2Regs.TCR.bit.TSS = 1; + counter++; + EDIS; + } + + if(started == 0) + { + // + // AUX PLL may not have started. Reset multiplier to 0 (bypass PLL). + // + EALLOW; + ClkCfgRegs.AUXPLLMULT.all = 0; + EDIS; + + // + // The user should put some handler code here based on how this + // condition should be handled in their application. + // + asm(" ESTOP0"); + } + + // + // Slip Bit Monitor + // Re-lock routine for SLIP condition + // + attempts = 0; + while(ClkCfgRegs.AUXPLLSTS.bit.SLIPS && (attempts < 10)) + { + EALLOW; + // + // Bypass AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 0; + asm(" RPT #20 || NOP"); + + // + // Turn off AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLEN = 0; + asm(" RPT #20 || NOP"); + + // + // Set integer and fractional multiplier, which automatically turns + // on the PLL + // + ClkCfgRegs.AUXPLLMULT.all = ((fmult << 8U) | imult); + + // + // Wait for the AUXPLL lock counter + // + while(ClkCfgRegs.AUXPLLSTS.bit.LOCKS != 1); + + // + // Enable AUXPLLCLK to be fed from AUXPLL + // + ClkCfgRegs.AUXPLLCTL1.bit.PLLCLKEN = 1; + asm(" RPT #20 || NOP"); + + attempts++; + EDIS; + } + + // + // Set divider to desired value + // + EALLOW; + ClkCfgRegs.AUXCLKDIVSEL.bit.AUXPLLDIV = divsel; + + // + // Restore Timer 2 configuration + // + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKSRCSEL = t2SRC; + CpuSysRegs.TMR2CLKCTL.bit.TMR2CLKPRESCALE = t2Prescale; + CpuTimer2Regs.TCR.all = t2TCR; + CpuTimer2Regs.PRD.all = t2PRD; + CpuTimer2Regs.TPR.all = t2TPR; + CpuTimer2Regs.TPRH.all = t2TPRH; + + // + // Reload period value + // + CpuTimer2Regs.TCR.bit.TRB = 1; + EDIS; +} + +// +// CsmUnlock - This function unlocks the CSM. User must replace 0xFFFF's with +// current password for the DSP. Returns 1 if unlock is successful. +// +Uint16 CsmUnlock(void) +{ + volatile Uint16 temp; + + // + // Load the key registers with the current password. The 0xFFFF's are dummy + // passwords. User should replace them with the correct password for the + // DSP. + // + EALLOW; + DcsmZ1Regs.Z1_CSMKEY0 = 0xFFFFFFFF; + DcsmZ1Regs.Z1_CSMKEY1 = 0xFFFFFFFF; + DcsmZ1Regs.Z1_CSMKEY2 = 0xFFFFFFFF; + DcsmZ1Regs.Z1_CSMKEY3 = 0xFFFFFFFF; + + DcsmZ2Regs.Z2_CSMKEY0 = 0xFFFFFFFF; + DcsmZ2Regs.Z2_CSMKEY1 = 0xFFFFFFFF; + DcsmZ2Regs.Z2_CSMKEY2 = 0xFFFFFFFF; + DcsmZ2Regs.Z2_CSMKEY3 = 0xFFFFFFFF; + EDIS; + + return(0); +} + +// +// SysIntOsc1Sel - This function switches to Internal Oscillator 1. +// +void SysIntOsc1Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 2; // Clk Src = INTOSC1 + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC + EDIS; +} + +// +// SysIntOsc2Sel - This function switches to Internal oscillator 2. +// +void SysIntOsc2Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 0; // Clk Src = INTOSC2 + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=1; // Turn off XTALOSC + EDIS; +} + +// +// SysXtalOscSel - This function switches to External CRYSTAL oscillator. +// +void SysXtalOscSel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC + ClkCfgRegs.CLKSRCCTL1.bit.OSCCLKSRCSEL = 1; // Clk Src = XTAL + EDIS; +} + +// +// AuxIntOsc2Sel - This function switches to Internal oscillator 2. +// +void AuxIntOsc2Sel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.INTOSC2OFF=0; // Turn on INTOSC2 + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 0; // Clk Src = INTOSC2 + EDIS; +} + +// +// AuxXtalOscSel - This function switches to External CRYSTAL oscillator. +// +void AuxXtalOscSel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL1.bit.XTALOFF=0; // Turn on XTALOSC + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 1; // Clk Src = XTAL + EDIS; +} + +// +// AuxAUXCLKOscSel - This function switches to AUXCLKIN (from a GPIO). +// +void AuxAuxClkSel(void) +{ + EALLOW; + ClkCfgRegs.CLKSRCCTL2.bit.AUXOSCCLKSRCSEL = 2; // Clk Src = XTAL + EDIS; +} + +// +// IDLE - Enter IDLE mode (single CPU). +// +void IDLE(void) +{ + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_IDLE; + EDIS; + asm(" IDLE"); +} + +// +// STANDBY - Enter STANDBY mode (single CPU). +// +void STANDBY(void) +{ + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_STANDBY; + EDIS; + asm(" IDLE"); +} + +// +// HALT - Enter HALT mode (dual CPU). Puts CPU2 in IDLE mode first. +// +void HALT(void) +{ +#if defined(CPU2) + IDLE(); +#elif defined(CPU1) + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_HALT; + EDIS; + + while(DevCfgRegs.LPMSTAT.bit.CPU2LPMSTAT != 0x1); + + EALLOW; + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + EDIS; + asm(" IDLE"); +#endif +} + +// +// HIB - Enter HIB mode (dual CPU). Puts CPU2 in STANDBY first. Alternately, +// CPU2 may be in reset. +void HIB(void) +{ +#if defined(CPU2) + STANDBY(); +#elif defined(CPU1) + EALLOW; + CpuSysRegs.LPMCR.bit.LPM = LPM_HIB; + EDIS; + + while((DevCfgRegs.LPMSTAT.bit.CPU2LPMSTAT == 0x0) && + (DevCfgRegs.RSTSTAT.bit.CPU2RES == 1)); + + DisablePeripheralClocks(); + EALLOW; + ClkCfgRegs.SYSPLLCTL1.bit.PLLCLKEN = 0; + ClkCfgRegs.SYSPLLCTL1.bit.PLLEN = 0; + EDIS; + asm(" IDLE"); +#endif +} + diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_TempSensorConv.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_TempSensorConv.c new file mode 100644 index 0000000000..ffc70fec07 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_TempSensorConv.c @@ -0,0 +1,153 @@ +//########################################################################### +// +// FILE: F2837xD_TempSensorConv.c +// +// TITLE: F2837xD Temperature Sensor Conversion Functions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// Defines +// +#define FP_SCALE 32768 //Scale factor for Q15 fixed point numbers (2^15) +#define FP_ROUND FP_SCALE/2 //Added to Q15 numbers before converting to + //integer to round the number. +#define KELVIN 273 // Amount to add to Q15 fixed point numbers + // to shift from Celsius to Kelvin + // (Converting guarantees number is + // positive, which makes rounding more + // efficient) +#define KELVIN_OFF FP_SCALE*KELVIN +#define getTempSlope() (*(int (*)(void))0x7036E)() //Slope of temperature sensor + //(deg. C / ADC code). + //Stored in fixed point Q15 + //format. +#define getTempOffset() (*(int (*)(void))0x70372)() //ADC code corresponding to + //temperature sensor output + //at 0 deg. C + +// +// Globals +// +float32 tempSensor_tempSlope; +float32 tempSensor_tempOffset; +float32 tempSensor_scaleFactor; + +// +// InitTempSensor - Initialize the temperature sensor by powering up the +// sensor, loading the calibration values from OTP to RAM, +// and recording the intended VREFHI voltage. +// Note: This function doesn't support VREFLO != 0.0V, +// but this could be implemented if desired. +// +void InitTempSensor(float32 vrefhi_voltage) +{ + EALLOW; + + // + //power up the the temperature sensor + // + AnalogSubsysRegs.TSNSCTL.bit.ENABLE = 1; + + // + //delay to allow the sensor to power up + // + DELAY_US(1000); + + EDIS; + + // + //need to remember VREFHI voltage so that sensor readings can be scaled + //to match 2.5V values used for calibration data. + // + tempSensor_scaleFactor = vrefhi_voltage; + + // + //check the device revision + // + if(DevCfgRegs.REVID >= 3) + { + // + //for production devices (Rev. C), pull the slope and offset from OTP + // + tempSensor_tempSlope = (int32)getTempSlope(); + tempSensor_tempOffset = getTempOffset(); + } + else + { + // + //for pre-production devices, use these static values for slope + //and offset + // + tempSensor_tempSlope = 5196; + tempSensor_tempOffset = 1788; + } +} + +// +// GetTemperatureC - This function uses the reference data stored in OTP to +// convert the raw temperature sensor reading into degrees C +// +int16 GetTemperatureC(int16 sensorSample) +{ + sensorSample = (int16)((tempSensor_scaleFactor/2.5)*(sensorSample)); + + return (((sensorSample - tempSensor_tempOffset)*tempSensor_tempSlope + + FP_ROUND + KELVIN_OFF)/FP_SCALE - KELVIN); +} + +// +// GetTemperatureK - This function uses the reference data stored in OTP to +// convert the raw temperature sensor reading into degrees K +// +int16 GetTemperatureK(int16 sensorSample) +{ + sensorSample = (int16)((2.5/tempSensor_scaleFactor)*(sensorSample)); + + return (((sensorSample - tempSensor_tempOffset)*tempSensor_tempSlope + + FP_ROUND + KELVIN_OFF)/FP_SCALE); +} + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Upp.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Upp.c new file mode 100644 index 0000000000..f0432c9c8d --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_Upp.c @@ -0,0 +1,153 @@ +//########################################################################### +// +// FILE: F2837xD_Upp.c +// +// TITLE: F2837xD Upp Initialization & Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// InitUpp1Gpio - Initialize UPP1 GPIOs +// +void InitUpp1Gpio(void) +{ + EALLOW; + + // + // Disable internal pull-up for the selected output pins + // for reduced power consumption + // Pull-ups can be enabled or disabled by the user. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1; // Disable pull-up on GPIO10 (uPP_WAIT) + GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1; // Disable pull-up on GPIO11 (uPP_START) + GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1; // Disable pull-up on GPIO12 (uPP_ENA) + GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1; // Disable pull-up on GPIO13 (uPP_D7) + GpioCtrlRegs.GPAPUD.bit.GPIO14 = 1; // Disable pull-up on GPIO14 (uPP_D6) + GpioCtrlRegs.GPAPUD.bit.GPIO15 = 1; // Disable pull-up on GPIO15 (uPP_D5) + GpioCtrlRegs.GPAPUD.bit.GPIO16 = 1; // Disable pull-up on GPIO16 (uPP_D4) + GpioCtrlRegs.GPAPUD.bit.GPIO17 = 1; // Disable pull-up on GPIO17 (uPP_D3) + GpioCtrlRegs.GPAPUD.bit.GPIO18 = 1; // Disable pull-up on GPIO18 (uPP_D2) + GpioCtrlRegs.GPAPUD.bit.GPIO19 = 1; // Disable pull-up on GPIO19 (uPP_D1) + GpioCtrlRegs.GPAPUD.bit.GPIO20 = 1; // Disable pull-up on GPIO20 (uPP_D0) + GpioCtrlRegs.GPAPUD.bit.GPIO21 = 1; // Disable pull-up on GPIO21 (uPP_CLK) + + // + // Disable QUAL for selected pins (ASYNC Input) + // + GpioCtrlRegs.GPAQSEL1.bit.GPIO10 = 3; // Disable pull-up on GPIO10 (uPP_WAIT) + GpioCtrlRegs.GPAQSEL1.bit.GPIO11 = 3; // Disable pull-up on GPIO11 (uPP_START) + GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 3; // Disable pull-up on GPIO12 (uPP_ENA) + GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 3; // Disable pull-up on GPIO13 (uPP_D7) + GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 3; // Disable pull-up on GPIO14 (uPP_D6) + GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 3; // Disable pull-up on GPIO15 (uPP_D5) + GpioCtrlRegs.GPAQSEL2.bit.GPIO16 = 3; // Disable pull-up on GPIO16 (uPP_D4) + GpioCtrlRegs.GPAQSEL2.bit.GPIO17 = 3; // Disable pull-up on GPIO17 (uPP_D3) + GpioCtrlRegs.GPAQSEL2.bit.GPIO18 = 3; // Disable pull-up on GPIO18 (uPP_D2) + GpioCtrlRegs.GPAQSEL2.bit.GPIO19 = 3; // Disable pull-up on GPIO19 (uPP_D1) + GpioCtrlRegs.GPAQSEL2.bit.GPIO20 = 3; // Disable pull-up on GPIO20 (uPP_D0) + GpioCtrlRegs.GPAQSEL2.bit.GPIO21 = 3; // Disable pull-up on GPIO21 (uPP_CLK) + + // + // Configure uPP-1 pins using GPIO regs + // This specifies which of the possible GPIO pins will be EPWM1 functional + // pins. + // Comment out other unwanted lines. + // + GpioCtrlRegs.GPAGMUX1.bit.GPIO10 = 3; // Configure GPIO10 as uPP_WAIT + GpioCtrlRegs.GPAGMUX1.bit.GPIO11 = 3; // Configure GPIO11 as uPP_START + GpioCtrlRegs.GPAGMUX1.bit.GPIO12 = 3; // Configure GPIO12 as uPP_ENA + GpioCtrlRegs.GPAGMUX1.bit.GPIO13 = 3; // Configure GPIO13 as uPP_D7 + GpioCtrlRegs.GPAGMUX1.bit.GPIO14 = 3; // Configure GPIO14 as uPP_D6 + GpioCtrlRegs.GPAGMUX1.bit.GPIO15 = 3; // Configure GPIO15 as uPP_D5 + GpioCtrlRegs.GPAGMUX2.bit.GPIO16 = 3; // Configure GPIO16 as uPP_D4 + GpioCtrlRegs.GPAGMUX2.bit.GPIO17 = 3; // Configure GPIO17 as uPP_D3 + GpioCtrlRegs.GPAGMUX2.bit.GPIO18 = 3; // Configure GPIO18 as uPP_D2 + GpioCtrlRegs.GPAGMUX2.bit.GPIO19 = 3; // Configure GPIO19 as uPP_D1 + GpioCtrlRegs.GPAGMUX2.bit.GPIO20 = 3; // Configure GPIO20 as uPP_D0 + GpioCtrlRegs.GPAGMUX2.bit.GPIO21 = 3; // Configure GPIO21 as uPP_CLK + + GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 3; // Configure GPIO10 as uPP_WAIT + GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 3; // Configure GPIO11 as uPP_START + GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 3; // Configure GPIO12 as uPP_ENA + GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 3; // Configure GPIO13 as uPP_D7 + GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 3; // Configure GPIO14 as uPP_D6 + GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 3; // Configure GPIO15 as uPP_D5 + GpioCtrlRegs.GPAMUX2.bit.GPIO16 = 3; // Configure GPIO16 as uPP_D4 + GpioCtrlRegs.GPAMUX2.bit.GPIO17 = 3; // Configure GPIO17 as uPP_D3 + GpioCtrlRegs.GPAMUX2.bit.GPIO18 = 3; // Configure GPIO18 as uPP_D2 + GpioCtrlRegs.GPAMUX2.bit.GPIO19 = 3; // Configure GPIO19 as uPP_D1 + GpioCtrlRegs.GPAMUX2.bit.GPIO20 = 3; // Configure GPIO20 as uPP_D0 + GpioCtrlRegs.GPAMUX2.bit.GPIO21 = 3; // Configure GPIO21 as uPP_CLK + + EDIS; +} + +// +// SoftResetUpp - Trigger an internal uPP reset +// +void SoftResetUpp(void) +{ + UppRegs.PERCTL.bit.SOFTRST = 1; // Issue uPP Internal Reset. + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + asm(" NOP"); + UppRegs.PERCTL.bit.SOFTRST = 0; // Release uPP Internal Reset. +} + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_can.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_can.c new file mode 100644 index 0000000000..3b3cb24bea --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_can.c @@ -0,0 +1,131 @@ +//########################################################################### +// +// FILE: F2837xD_can.c +// +// TITLE: F2837xD CAN Support Functions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" + +// +// InitCAN - Initializes the CAN-A controller after reset. +// +void InitCAN(void) +{ + int16_t iMsg; + + // + // Place CAN controller in init state, regardless of previous state. This + // will put controller in idle, and allow the message object RAM to be + // programmed. + // + CanaRegs.CAN_CTL.bit.Init = 1; + CanaRegs.CAN_CTL.bit.SWR = 1; + + // + // Wait for busy bit to clear + // + while(CanaRegs.CAN_IF1CMD.bit.Busy) + { + } + + // + // Clear the message value bit in the arbitration register. This indicates + // the message is not valid and is a "safe" condition to leave the message + // object. The same arb reg is used to program all the message objects. + // + CanaRegs.CAN_IF1CMD.bit.DIR = 1; + CanaRegs.CAN_IF1CMD.bit.Arb = 1; + CanaRegs.CAN_IF1CMD.bit.Control = 1; + + CanaRegs.CAN_IF1ARB.all = 0; + + CanaRegs.CAN_IF1MCTL.all = 0; + + CanaRegs.CAN_IF2CMD.bit.DIR = 1; + CanaRegs.CAN_IF2CMD.bit.Arb = 1; + CanaRegs.CAN_IF2CMD.bit.Control = 1; + + CanaRegs.CAN_IF2ARB.all = 0; + + CanaRegs.CAN_IF2MCTL.all = 0; + + // + // Loop through to program all 32 message objects + // + for(iMsg = 1; iMsg <= 32; iMsg+=2) + { + // + // Wait for busy bit to clear + // + while(CanaRegs.CAN_IF1CMD.bit.Busy) + { + } + + // + // Initiate programming the message object + // + CanaRegs.CAN_IF1CMD.bit.MSG_NUM = iMsg; + + // + // Wait for busy bit to clear + // + while(CanaRegs.CAN_IF2CMD.bit.Busy) + { + } + + // + // Initiate programming the message object + // + CanaRegs.CAN_IF2CMD.bit.MSG_NUM = iMsg + 1; + } + + // + // Acknowledge any pending status interrupts. + // + volatile uint32_t discardRead = CanaRegs.CAN_ES.all; + +} + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_sci_io.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_sci_io.c new file mode 100644 index 0000000000..28c676c18d --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_sci_io.c @@ -0,0 +1,185 @@ +//############################################################################# +// +// File: F2837xD_sci_io.c +// +// Description: Contains the various functions related to the serial +// communications interface (SCI) object +// +//############################################################################# +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include +#include +#include "F28x_Project.h" +#include "F2837xD_sci_io.h" + +// +// Globals +// +uint16_t deviceOpen = 0; + +// +// SCI_open - Initialize and setup SCI +// +int SCI_open(const char * path, unsigned flags, int llv_fd) +{ + if(deviceOpen) + { + return (-1); + } + else + { + EALLOW; + CpuSysRegs.PCLKCR7.bit.SCI_A = 1; + SciaRegs.SCIFFTX.all=0xE040; + SciaRegs.SCIFFRX.all=0x2044; + SciaRegs.SCIFFCT.all=0x0; + SciaRegs.SCICCR.all =0x0007; // 1 stop bit, No loopback + // No parity,8 char bits, + // async mode, idle-line protocol + SciaRegs.SCICTL1.all =0x0003; // enable TX, RX, internal SCICLK, + // Disable RX ERR, SLEEP, TXWAKE + SciaRegs.SCICTL2.all =0x0003; + SciaRegs.SCICTL2.bit.TXINTENA =1; + SciaRegs.SCICTL2.bit.RXBKINTENA =1; + + SciaRegs.SCIHBAUD.bit.BAUD =0x0000; // 9600 baud @LSPCLK = 10MHz + //(40 MHz SYSCLK). + SciaRegs.SCILBAUD.bit.BAUD =0x0081; + + SciaRegs.SCICTL1.all =0x0023; // Relinquish SCI from Reset + EDIS; + + deviceOpen = 1; + return (1); + } +} + +// +// SCI_close - Set SCI to closed +// +int SCI_close(int dev_fd) +{ + if((dev_fd != 1) || (!deviceOpen)) + { + return (-1); + } + else + { + deviceOpen = 0; + return (0); + } +} + +// +// SCI_read - Read from the SCI RX buffer +// +int SCI_read(int dev_fd, char * buf, unsigned count) +{ + uint16_t readCount = 0; + uint16_t * bufPtr = (uint16_t *) buf; + + if(count == 0) + { + return (0); + } + + while((readCount < count) && SciaRegs.SCIRXST.bit.RXRDY) + { + *bufPtr = SciaRegs.SCIRXBUF.bit.SAR; + readCount++; + bufPtr++; + } + + return (readCount); +} + +// +// SCI_write - Write to the SCI TX buffer +// +int SCI_write(int dev_fd, char * buf, unsigned count) +{ + uint16_t writeCount = 0; + uint16_t * bufPtr = (uint16_t *) buf; + + if(count == 0) + { + return (0); + } + + while(writeCount < count) + { + while(SciaRegs.SCICTL2.bit.TXRDY != 1) + { + } + SciaRegs.SCITXBUF.bit.TXDT = *bufPtr; + writeCount++; + bufPtr++; + } + + return (writeCount); +} + +// +// SCI_lseek - Do nothing +// +off_t SCI_lseek(int dev_fd, off_t offset, int origin) +{ + return (0); +} + +// +// SCI_unlink - Do nothing +// +int SCI_unlink(const char * path) +{ + return (0); +} + +// +// SCI_rename - Do nothing +// +int SCI_rename(const char * old_name, const char * new_name) +{ + return (0); +} + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_sdfm_drivers.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_sdfm_drivers.c new file mode 100644 index 0000000000..4bbfdf5890 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_sdfm_drivers.c @@ -0,0 +1,554 @@ +//########################################################################### +// +// FILE: F2837xD_sdfm_drivers.c +// +// TITLE: SDFM Driver functions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F28x_Project.h" +#include "F2837xD_struct.h" +#include "F2837xD_sdfm_drivers.h" + +// +// Sdfm_configureInputCtrl - This function configures SDFM Input control unit. +// sdfmNumber - This parameter should be used to +// select SDFM1 (or) SDFM2 +// filterNumber - This parameter is used to select +// which filter (FILTER1,FILTER2, +// FILTER3,FILTER4) needs to be +// configured. +// mode - This parameter is used to select +// one of the modes mentioned above +// +// Input control unit can be configured in four different modes: +// MODE_0 : Modulator clock rate = Modulator data rate +// MODE_1 : Modulator clock rate = (Modulator data rate / 2) +// MODE_2 : Manchester encoded data (Modulator clock is encoded into data) +// MODE_3 : Modulator clock rate = (2 x Modulator data rate) +// +void Sdfm_configureInputCtrl(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 mode) +{ + EALLOW; + + switch (filterNumber) + { + case FILTER1: + (*SDFM[sdfmNumber]).SDCTLPARM1.bit.MOD = mode; + break; + + case FILTER2: + (*SDFM[sdfmNumber]).SDCTLPARM2.bit.MOD = mode; + break; + + case FILTER3: + (*SDFM[sdfmNumber]).SDCTLPARM3.bit.MOD = mode; + break; + + case FILTER4: + (*SDFM[sdfmNumber]).SDCTLPARM4.bit.MOD = mode; + break; + } + + EDIS; +} + +// +// Sdfm_configureComparator - This function configures SDFM Comparator unit. +// Comparator unit can be configured to monitor +// input conditions with a fast settling time. +// This module can be programmed to detect over and +// under value conditions. +// +// sdfmNumber - This parameter should be used to +// select SDFM1 (or) SDFM2 +// filterNumber - This parameter is used to select +// which filter (FILTER1,FILTER2, +// FILTER3,FILTER3) +// filterType - This parameter is used to select +// one of the filter type mentioned +// above (SINC1,SINC2,SINC3,SINCFAST) +// OSR - This parameter is used to +// configure oversampling ratio for +// comparator +// HLT - This parameter is used to +// configure to detect over value +// condition +// LLT - This parameter is used to +// configure to detect under value +// condition +// +void Sdfm_configureComparator(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 filterType, Uint16 OSR, Uint16 HLT, + Uint16 LLT) +{ + EALLOW; + + switch (filterNumber) + { + case FILTER1: //Filter 1 + + // + //Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 + // + (*SDFM[sdfmNumber]).SDCPARM1.bit.CS1_CS0 = filterType; + + // + //Configure OSR value + // + if(OSR<=COMPARATOR_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDCPARM1.bit.COSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDCPARM1.bit.COSR = COMPARATOR_MAX_OSR; + } + + (*SDFM[sdfmNumber]).SDCMPH1.bit.HLT = HLT; + (*SDFM[sdfmNumber]).SDCMPL1.bit.LLT = LLT; + break; + + case FILTER2: //Filter 2 + // + //Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 + // + (*SDFM[sdfmNumber]).SDCPARM2.bit.CS1_CS0 = filterType; + + // + //Configure OSR value + // + if(OSR<=COMPARATOR_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDCPARM2.bit.COSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDCPARM2.bit.COSR = COMPARATOR_MAX_OSR; + } + + (*SDFM[sdfmNumber]).SDCMPH2.bit.HLT = HLT; + (*SDFM[sdfmNumber]).SDCMPL2.bit.LLT = LLT; + break; + + case FILTER3: //Filter 3 + // + //Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 + // + (*SDFM[sdfmNumber]).SDCPARM3.bit.CS1_CS0 = filterType; + + // + //Configure OSR value + // + if(OSR<=COMPARATOR_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDCPARM3.bit.COSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDCPARM3.bit.COSR = COMPARATOR_MAX_OSR; + } + + (*SDFM[sdfmNumber]).SDCMPH3.bit.HLT = HLT; + (*SDFM[sdfmNumber]).SDCMPL3.bit.LLT = LLT; + break; + + case FILTER4: //Filter 4 + // + //Configure filter type : Sincfast / Sinc1 / Sinc2 / Sinc3 + // + (*SDFM[sdfmNumber]).SDCPARM4.bit.CS1_CS0 = filterType; + + // + //Configure Comparator OSR value + // + if(OSR<=COMPARATOR_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDCPARM4.bit.COSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDCPARM4.bit.COSR = COMPARATOR_MAX_OSR; + } + + (*SDFM[sdfmNumber]).SDCMPH4.bit.HLT = HLT; + (*SDFM[sdfmNumber]).SDCMPL4.bit.LLT = LLT; + break; + } + + EDIS; +} + + +// +// SDFM_configureData_filter - This function configures SDFM Data filter unit +// +// SDFM Data filter unit can be configured in any +// of four different Sinc filter types: +// sdfmNumber - This parameter should be used to +// select SDFM1 (or) SDFM2 +// filterNumber - This parameter is used to select +// which filter(FILTER1,FILTER2, +// FILTER3,FILTER3) needs to be +// configured +// Filter_switch - This parameter is used to +// enable/disable a filter +// filterType - This parameter is used to select +// one of the filter type mentioned +// above (SINC1 / SINC2 / SINC3 / +// SINCFAST) +// OSR - This parameter is used to +// configure oversampling ratio +// for Data filter (Upto OSR_256) +// DR_switch - This parameter selects whether +// data is represented in 16 (or) +// 32 bits +// shift_bits - When user chooses 16 bit +// representation, this variable +// allows to right shift by +// specific number of bits +// +void Sdfm_configureData_filter(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 Filter_switch, Uint16 filterType, + Uint16 OSR, Uint16 DR_switch, Uint16 shift_bits) +{ + EALLOW; + + switch(filterNumber) + { + + case FILTER1: //Filter 1 + (*SDFM[sdfmNumber]).SDDFPARM1.bit.FEN = Filter_switch; + (*SDFM[sdfmNumber]).SDDFPARM1.bit.SST = filterType; + + // + //Configure Sinc filter OSR value + // + if(OSR<=DATA_FILTER_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDDFPARM1.bit.DOSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDDFPARM1.bit.DOSR = DATA_FILTER_MAX_OSR; + } + + // + //Configure Data filter data representation + //DR_switch - Data Representation (0/1 = 16/32b 2's complement) + // + (*SDFM[sdfmNumber]).SDDPARM1.bit.DR = DR_switch; + if(DR_switch == 0) + { + (*SDFM[sdfmNumber]).SDDPARM1.bit.SH = shift_bits; + } + + break; + + case FILTER2: //Filter 2 + (*SDFM[sdfmNumber]).SDDFPARM2.bit.FEN = Filter_switch; + (*SDFM[sdfmNumber]).SDDFPARM2.bit.SST = filterType; + + // + //Configure Sinc filter OSR value + // + if(OSR<=DATA_FILTER_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDDFPARM2.bit.DOSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDDFPARM2.bit.DOSR = DATA_FILTER_MAX_OSR; + } + + // + //Configure Data filter data representation + // DR_switch - Data Representation (0/1 = 16/32b 2's complement) + // + (*SDFM[sdfmNumber]).SDDPARM2.bit.DR = DR_switch; + if(DR_switch == 0) + { + (*SDFM[sdfmNumber]).SDDPARM2.bit.SH = shift_bits; + } + + break; + + case FILTER3: //Filter 3 + (*SDFM[sdfmNumber]).SDDFPARM3.bit.FEN = Filter_switch; + (*SDFM[sdfmNumber]).SDDFPARM3.bit.SST = filterType; + + // + //Configure Sinc filter OSR value + // + if(OSR<=DATA_FILTER_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDDFPARM3.bit.DOSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDDFPARM3.bit.DOSR = DATA_FILTER_MAX_OSR; + } + + // + //Configure Data filter data representation + // DR_switch - Data Representation (0/1 = 16/32b 2's complement) + // + (*SDFM[sdfmNumber]).SDDPARM3.bit.DR = DR_switch; + if(DR_switch == 0) + { + (*SDFM[sdfmNumber]).SDDPARM3.bit.SH = shift_bits; + } + + break; + + case FILTER4: //Filter 4 + (*SDFM[sdfmNumber]).SDDFPARM4.bit.FEN = Filter_switch; + (*SDFM[sdfmNumber]).SDDFPARM4.bit.SST = filterType; + + // + //Configure Sinc filter OSR value + // + if(OSR<=DATA_FILTER_MAX_OSR) + { + (*SDFM[sdfmNumber]).SDDFPARM4.bit.DOSR = OSR; + } + else + { + (*SDFM[sdfmNumber]).SDDFPARM4.bit.DOSR = DATA_FILTER_MAX_OSR; + } + + // + //Configure Data filter data representation + // DR_switch - Data Representation (0/1 = 16/32b 2's complement) + // + (*SDFM[sdfmNumber]).SDDPARM4.bit.DR = DR_switch; + if(DR_switch == 0) + { + (*SDFM[sdfmNumber]).SDDPARM4.bit.SH = shift_bits; + } + + break; + } + + EDIS; +} + +// +// Sdfm_configureInterrupt - This function configures SDFM Interrupt unit. +// SDFM Interrupt unit can be configured to +// enable/disable different sources of SDFM +// interrupts which should trigger CPU interrupt. +// +// sdfmNumber - This parameter should be used to +// select SDFM1 (or) SDFM2 +// filterNumber - This parameter is used to select +// which filter(FILTER1,FILTER2, +// FILTER3,FILTER3) needs to be +// configured +// IEH_Switch - This parameter allows over value +// condition to trigger CPU interrupt +// IEL_Switch - This parameter allows under value +// condition to trigger CPU interrupt +// MFIE_Switch - This parameter allows modulator +// failure to trigger CPU interrupt +// AE_Switch - This parameter allows new filter +// data acknowledge interrupt signal +// to trigger CPU interrupt +// +void Sdfm_configureInterrupt(Uint16 sdfmNumber, Uint16 filterNumber, + Uint16 IEH_Switch, Uint16 IEL_Switch, + Uint16 MFIE_Switch, Uint16 AE_Switch) +{ + EALLOW; + + switch(filterNumber) + { + case FILTER1: //Filter 1 + (*SDFM[sdfmNumber]).SDCPARM1.bit.IEH = IEH_Switch; + (*SDFM[sdfmNumber]).SDCPARM1.bit.IEL = IEL_Switch; + (*SDFM[sdfmNumber]).SDCPARM1.bit.MFIE = MFIE_Switch; + (*SDFM[sdfmNumber]).SDDFPARM1.bit.AE = AE_Switch; + break; + + case FILTER2: //Filter 2 + (*SDFM[sdfmNumber]).SDCPARM2.bit.IEH = IEH_Switch; + (*SDFM[sdfmNumber]).SDCPARM2.bit.IEL = IEL_Switch; + (*SDFM[sdfmNumber]).SDCPARM2.bit.MFIE = MFIE_Switch; + (*SDFM[sdfmNumber]).SDDFPARM2.bit.AE = AE_Switch; + break; + + case FILTER3: //Filter 3 + (*SDFM[sdfmNumber]).SDCPARM3.bit.IEH = IEH_Switch; + (*SDFM[sdfmNumber]).SDCPARM3.bit.IEL = IEL_Switch; + (*SDFM[sdfmNumber]).SDCPARM3.bit.MFIE = MFIE_Switch; + (*SDFM[sdfmNumber]).SDDFPARM3.bit.AE = AE_Switch; + break; + + case FILTER4: //Filter 4 + (*SDFM[sdfmNumber]).SDCPARM4.bit.IEH = IEH_Switch; + (*SDFM[sdfmNumber]).SDCPARM4.bit.IEL = IEL_Switch; + (*SDFM[sdfmNumber]).SDCPARM4.bit.MFIE = MFIE_Switch; + (*SDFM[sdfmNumber]).SDDFPARM4.bit.AE = AE_Switch; + break; + } + + EDIS; +} + + +// +// SDFM_configExternalreset - This function configures SDFM module to +// enable/disable external filter reset from PWM +// +// sdfmNumber - This parameter should +// be used to select +// SDFM1 (or) SDFM2 +// filter1_Config_ext_reset - This parameter is used +// to enable/disable +// external PWM reset for +// filter1 +// filter2_Config_ext_reset - This parameter is used +// to enable/disable +// external PWM reset for +// filter2 +// filter3_Config_ext_reset - This parameter is used +// to enable / disable +// external PWM reset for +// filter3 +// filter4_Config_ext_reset - This parameter is used +// to enable / disable +// external PWM reset for +// filter4 +// +void Sdfm_configureExternalreset(Uint16 sdfmNumber, + Uint16 filter1_Config_ext_reset, + Uint16 filter2_Config_ext_reset, + Uint16 filter3_Config_ext_reset, + Uint16 filter4_Config_ext_reset) +{ + EALLOW; + (*SDFM[sdfmNumber]).SDDFPARM1.bit.SDSYNCEN = filter1_Config_ext_reset; + (*SDFM[sdfmNumber]).SDDFPARM2.bit.SDSYNCEN = filter2_Config_ext_reset; + (*SDFM[sdfmNumber]).SDDFPARM3.bit.SDSYNCEN = filter3_Config_ext_reset; + (*SDFM[sdfmNumber]).SDDFPARM4.bit.SDSYNCEN = filter4_Config_ext_reset; + EDIS; +} + +// +// SDFM_enableMFE - This function enables Master filter bit of SDFM module +// +// sdfmNumber - This parameter should be used to select +// SDFM1 (or) SDFM2 +// +void Sdfm_enableMFE(Uint16 sdfmNumber) +{ + EALLOW; + (*SDFM[sdfmNumber]).SDMFILEN.bit.MFE = 1; //Master Filter bit is enabled + EDIS; +} + +// +// SDFM_disableMFE - This function disable Master filter bit of SDFM module +// +// sdfmNumber - This parameter should be used to select +// SDFM1 (or) SDFM2 +// +void SDFM_disableMFE(Uint16 sdfmNumber) +{ + EALLOW; + (*SDFM[sdfmNumber]).SDMFILEN.bit.MFE = 0; //Master Filter bit is disabled + EDIS; +} + +// +// SDFM_enableMIE - This function enable Master Interrupt bit of SDFM module +// +// sdfmNumber - This parameter should be used to select +// SDFM1 (or) SDFM2 +// +void Sdfm_enableMIE(Uint16 sdfmNumber) +{ + EALLOW; + // + //Enable MIE (Master Interrupt Enable) bit + // + (*SDFM[sdfmNumber]).SDCTL.bit.MIE = 1; + EDIS; +} + +// +// Sdfm_disableMIE - This function disable Master Interrupt bit of SDFM module +// +// sdfmNumber - This parameter should be used to select +// SDFM1 (or) SDFM2 +// +void Sdfm_disableMIE(Uint16 sdfmNumber) +{ + + EALLOW; + // + //Disable MIE (Master Interrupt Enable) bit + // + (*SDFM[sdfmNumber]).SDCTL.bit.MIE = 0; + EDIS; +} + +// +// Sdfm_readFlagRegister - This function helps user read SDFM flag +// register (SDIFLG) +// +Uint32 Sdfm_readFlagRegister(Uint16 sdfmNumber) +{ + return ((*SDFM[sdfmNumber]).SDIFLG.all); +} + +// +// Sdfm_clearFlagRegister - This function helps is used to clear +// SDIFLG register +// +void Sdfm_clearFlagRegister(Uint16 sdfmNumber,Uint32 sdfmReadFlagRegister) +{ + (*SDFM[sdfmNumber]).SDIFLGCLR.all = sdfmReadFlagRegister; +} + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_struct.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_struct.c new file mode 100644 index 0000000000..1a306bd1d4 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_struct.c @@ -0,0 +1,100 @@ +//########################################################################### +// +// FILE: F2837xD_struct.c +// +// TITLE: F2837xD SDFM structure +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +// +// Included Files +// +#include "F2837xD_device.h" +#include "F2837xD_struct.h" + +// +// Globals +// +#if defined(CPU1) +volatile struct ADC_REGS *ADC[MAX_ADC] = +{ 0, &AdcaRegs, &AdcbRegs, + &AdccRegs, &AdcdRegs }; +#endif + +volatile struct ECAP_REGS *ECAP[MAX_ECAP] = +{ 0, &ECap1Regs, &ECap2Regs, &ECap3Regs, + &ECap4Regs, &ECap5Regs, &ECap6Regs }; + +volatile struct EPWM_REGS *EPWM[MAX_EPWM] = +{ 0, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, + &EPwm4Regs, &EPwm5Regs, &EPwm6Regs, + &EPwm7Regs, &EPwm8Regs, &EPwm9Regs, + &EPwm10Regs, &EPwm11Regs, &EPwm12Regs }; + +volatile struct EQEP_REGS *EQEP[MAX_EQEP] = +{ 0, &EQep1Regs, &EQep2Regs, &EQep3Regs }; + +volatile struct I2C_REGS *I2C[MAX_I2C] = +{ 0, &I2caRegs }; + +volatile struct McBSP_REGS *MCBSP[MAX_MCBSP] = +{ 0, &McbspaRegs }; + +volatile struct SCI_REGS *SCI[MAX_SCI] = +{ 0, &SciaRegs }; + +volatile struct SPI_REGS *SPI[MAX_SPI] = +{ 0, &SpiaRegs, &SpibRegs, &SpicRegs }; + +volatile struct SDFM_REGS *SDFM[MAX_SDFM] = +{ 0, &Sdfm1Regs, &Sdfm2Regs}; + +#if defined(CPU1) +volatile Uint16 *TRIP_SEL[MAX_TRIPSEL] = +{ 0, &InputXbarRegs.INPUT1SELECT, &InputXbarRegs.INPUT2SELECT, + &InputXbarRegs.INPUT3SELECT, &InputXbarRegs.INPUT4SELECT, + &InputXbarRegs.INPUT5SELECT, &InputXbarRegs.INPUT6SELECT, + &InputXbarRegs.INPUT7SELECT, &InputXbarRegs.INPUT8SELECT, + &InputXbarRegs.INPUT9SELECT, &InputXbarRegs.INPUT10SELECT, + &InputXbarRegs.INPUT11SELECT, &InputXbarRegs.INPUT12SELECT, + &InputXbarRegs.INPUT13SELECT, &InputXbarRegs.INPUT14SELECT +}; +#endif + +// +// End of file +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_usDelay.asm b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_usDelay.asm new file mode 100644 index 0000000000..71d3606fd0 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/F2837xD_usDelay.asm @@ -0,0 +1,105 @@ +;//########################################################################### +;// +;// FILE: F2837xD_usDelay.asm +;// +;// TITLE: Simple delay function +;// +;// DESCRIPTION: +;// This is a simple delay function that can be used to insert a specified +;// delay into code. +;// This function is only accurate if executed from internal zero-waitstate +;// SARAM. If it is executed from waitstate memory then the delay will be +;// longer then specified. +;// To use this function: +;// 1 - update the CPU clock speed in the F2837xD_Examples.h +;// file. For example: +;// #define CPU_RATE 6.667L // for a 150MHz CPU clock speed +;// 2 - Call this function by using the DELAY_US(A) macro +;// that is defined in the F2837xD_Device.h file. This macro +;// will convert the number of microseconds specified +;// into a loop count for use with this function. +;// This count will be based on the CPU frequency you specify. +;// 3 - For the most accurate delay +;// - Execute this function in 0 waitstate RAM. +;// - Disable interrupts before calling the function +;// If you do not disable interrupts, then think of +;// this as an "at least" delay function as the actual +;// delay may be longer. +;// The C assembly call from the DELAY_US(time) macro will +;// look as follows: +;// extern void Delay(long LoopCount); +;// MOV AL,#LowLoopCount +;// MOV AH,#HighLoopCount +;// LCR _Delay +;// Or as follows (if count is less then 16-bits): +;// MOV ACC,#LoopCount +;// LCR _Delay +;// +;//########################################################################### +;// $TI Release: F2837xD Support Library v3.05.00.00 $ +;// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +;// $Copyright: +;// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + + .def _F28x_usDelay + + .cdecls LIST ;;Used to populate __TI_COMPILER_VERSION__ macro + %{ + %} + + .if __TI_COMPILER_VERSION__ + .if __TI_COMPILER_VERSION__ >= 15009000 + .sect ".TI.ramfunc" ;;Used with compiler v15.9.0 and newer + .else + .sect "ramfuncs" ;;Used with compilers older than v15.9.0 + .endif + .endif + + .global __F28x_usDelay +_F28x_usDelay: + SUB ACC,#1 + BF _F28x_usDelay,GEQ ;; Loop if ACC >= 0 + LRETR + +;There is a 9/10 cycle overhead and each loop +;takes five cycles. The LoopCount is given by +;the following formula: +; DELAY_CPU_CYCLES = 9 + 5*LoopCount +; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 +; The macro DELAY_US(A) performs this calculation for you +; +; + +;// +;// End of file +;// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/device.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/device.c new file mode 100644 index 0000000000..171d3ac8f1 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/device.c @@ -0,0 +1,328 @@ +//############################################################################# +// +// FILE: device.c +// +// TITLE: Device setup for examples. +// +//############################################################################# +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include "device.h" +#include "driverlib.h" +#ifdef __cplusplus +using std::memcpy; +#endif + +//***************************************************************************** +// +// Function to initialize the device. Primarily initializes system control to a +// known state by disabling the watchdog, setting up the SYSCLKOUT frequency, +// and enabling the clocks to the peripherals. +// +//***************************************************************************** +void Device_init(void) +{ + // + // Disable the watchdog + // + SysCtl_disableWatchdog(); + +#ifdef _FLASH + // + // Copy time critical code and flash setup code to RAM. This includes the + // following functions: InitFlash(); + // + // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols + // are created by the linker. Refer to the device .cmd file. + // + memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); + + // + // Call Flash Initialization to setup flash waitstates. This function must + // reside in RAM. + // + Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES); +#endif +#ifdef CPU1 + // + // Set up PLL control and clock dividers + // + SysCtl_setClock(DEVICE_SETCLOCK_CFG); + + // + // Make sure the LSPCLK divider is set to the default (divide by 4) + // + SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_4); + + // + // These asserts will check that the #defines for the clock rates in + // device.h match the actual rates that have been configured. If they do + // not match, check that the calculations of DEVICE_SYSCLK_FREQ and + // DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as + // expected if these are not correct. + // + ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ); + ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ); +#endif + // + // Turn on all peripherals + // + Device_enableAllPeripherals(); +} + +//***************************************************************************** +// +// Function to turn on all peripherals, enabling reads and writes to the +// peripherals' registers. +// +// Note that to reduce power, unused peripherals should be disabled. +// +//***************************************************************************** +void Device_enableAllPeripherals(void) +{ + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DMA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER0); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER2); +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRPWM); +#endif + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_GTBCLKSYNC); + +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF2); +#endif + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM6); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM8); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM9); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM10); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM11); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM12); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP6); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP3); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD2); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCID); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIC); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CB); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANB); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPB); + +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_USBA); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_UPPA); +#endif + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS6); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS7); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS8); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACC); +} + +//***************************************************************************** +// +// Function to disable pin locks on GPIOs. +// +//***************************************************************************** +void Device_initGPIO(void) +{ + // + // Disable pin locks. + // + GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_D, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_E, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_F, 0xFFFFFFFF); + + // + // Enable GPIO Pullups + // + Device_enableUnbondedGPIOPullups(); +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 176PTP package: +// GPIOs Grp Bits +// 95-132 C 31 +// D 31:0 +// E 4:0 +// 134-168 E 31:6 +// F 8:0 +// +//***************************************************************************** + +void Device_enableUnbondedGPIOPullupsFor176Pin(void) +{ + EALLOW; + HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0x80000000U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFDFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; + EDIS; +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 100PZ package: +// GPIOs Grp Bits +// 0-1 A 1:0 +// 5-9 A 9:5 +// 22-40 A 31:22 +// B 8:0 +// 44-57 B 25:12 +// 67-68 C 4:3 +// 74-77 C 13:10 +// 79-83 C 19:15 +// 93-168 C 31:29 +// D 31:0 +// E 31:0 +// F 8:0 +// +//***************************************************************************** +void Device_enableUnbondedGPIOPullupsFor100Pin(void) +{ + EALLOW; + HWREG(GPIOCTRL_BASE + GPIO_O_GPAPUD) = ~0xFFC003E3U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPBPUD) = ~0x03FFF1FFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0xE10FBC18U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFFFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; + EDIS; +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 100PZ or +// 176PTP package. +// +//***************************************************************************** +void Device_enableUnbondedGPIOPullups(void) +{ + // + // bits 8-10 have pin count + // + uint16_t pinCount = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + (uint32_t)SYSCTL_PARTIDL_PIN_COUNT_M) >> + SYSCTL_PARTIDL_PIN_COUNT_S); + + /* + * 5 = 100 pin + * 6 = 176 pin + * 7 = 337 pin + */ + if(pinCount == 5) + { + Device_enableUnbondedGPIOPullupsFor100Pin(); + } + else if(pinCount == 6) + { + Device_enableUnbondedGPIOPullupsFor176Pin(); + } + else + { + // + // Do nothing - this is 337 pin package + // + } +} + +//***************************************************************************** +// +// Error handling function to be called when an ASSERT is violated +// +//***************************************************************************** +void __error__(char *filename, uint32_t line) +{ + // + // An ASSERT condition was evaluated as false. You can use the filename and + // line parameters to determine what went wrong. + // + ESTOP0; +} diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/usb.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/usb.c new file mode 100644 index 0000000000..db82fb7a39 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/usb.c @@ -0,0 +1,3972 @@ +//########################################################################### +// +// FILE: usb.c +// +// TITLE: Driver for the USB Interface. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + + +//***************************************************************************** +// +//! \addtogroup usb_api +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_usb.h" +#include "driverlib/debug.h" +#include "driverlib/interrupt.h" +#include "driverlib/sysctl.h" +#include "usb.h" + +//***************************************************************************** +// +// Amount to shift the RX interrupt sources by in the flags used in the +// interrupt calls. +// +//***************************************************************************** +#define USB_INTEP_RX_SHIFT 16 + +//***************************************************************************** +// +// Amount to shift the RX endpoint status sources by in the flags used in the +// calls. +// +//***************************************************************************** +#define USB_RX_EPSTATUS_SHIFT 16 + +//***************************************************************************** +// +// Converts from an endpoint specifier to the offset of the endpoint's +// control/status registers. +// +//***************************************************************************** +#define EP_OFFSET(Endpoint) (Endpoint - 0x10) + +//***************************************************************************** +// +// Sets one of the indexed registers. +// +// \param ui32Base specifies the USB module base address. +// \param ui32Endpoint is the endpoint index to target for this write. +// \param ui32IndexedReg is the indexed register to write to. +// \param ui8Value is the value to write to the register. +// +// This function is used to access the indexed registers for each endpoint. +// The only registers that are indexed are the FIFO configuration registers, +// which are not used after configuration. +// +// \return None. +// +//***************************************************************************** +static void +_USBIndexWrite(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32IndexedReg, uint32_t ui32Value, uint32_t ui32Size) +{ + uint32_t ui32Index; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) || + (ui32Endpoint == 3)); + ASSERT((ui32Size == 1) || (ui32Size == 2)); + + // + // Save the old index in case it was in use. + // + ui32Index = HWREGB(ui32Base + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; + + // + // Determine the size of the register value. + // + if(ui32Size == 1) + { + // + // Set the value. + // + HWREGB(ui32Base + ui32IndexedReg) = ui32Value; + } + else + { + // + // Set the value. + // + HWREGH(ui32Base + ui32IndexedReg) = ui32Value; + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Index; +} + +//***************************************************************************** +// +// Reads one of the indexed registers. +// +// \param ui32Base specifies the USB module base address. +// \param ui32Endpoint is the endpoint index to target for this write. +// \param ui32IndexedReg is the indexed register to write to. +// +// This function is used internally to access the indexed registers for each +// endpoint. The only registers that are indexed are the FIFO configuration +// registers, which are not used after configuration. +// +// \return The value in the register requested. +// +//***************************************************************************** +static uint32_t +_USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32IndexedReg, uint32_t ui32Size) +{ + uint8_t ui8Index; + uint8_t ui8Value; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) || + (ui32Endpoint == 3)); + ASSERT((ui32Size == 1) || (ui32Size == 2)); + + // + // Save the old index in case it was in use. + // + ui8Index = HWREGB(ui32Base + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; + + // + // Determine the size of the register value. + // + if(ui32Size == 1) + { + // + // Get the value. + // + ui8Value = HWREGB(ui32Base + ui32IndexedReg); + } + else + { + // + // Get the value. + // + ui8Value = HWREGH(ui32Base + ui32IndexedReg); + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui8Index; + + // + // Return the register's value. + // + return(ui8Value); +} + +//***************************************************************************** +// +//! Puts the USB bus in a suspended state. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! When used in host mode, this function puts the USB bus in the suspended +//! state. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostSuspend(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Send the suspend signaling to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SUSPEND; +} + +//***************************************************************************** +// +//! Handles the USB bus reset condition. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies whether to start or stop signaling reset on the USB +//! bus. +//! +//! When this function is called with the \e bStart parameter set to \b true, +//! this function causes the start of a reset condition on the USB bus. +//! The caller must then delay at least 20ms before calling this function +//! again with the \e bStart parameter set to \b false. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostReset(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Send a reset signal to the bus. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESET; + } + else + { + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESET; + } +} + +//***************************************************************************** +// +//! Handles the USB bus resume condition. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies if the USB controller is entering or leaving the +//! resume signaling state. +//! +//! When in device mode, this function brings the USB controller out of the +//! suspend state. This call must first be made with the \e bStart parameter +//! set to \b true to start resume signaling. The device application must +//! then delay at least 10ms but not more than 15ms before calling this +//! function with the \e bStart parameter set to \b false. +//! +//! When in host mode, this function signals devices to leave the suspend +//! state. This call must first be made with the \e bStart parameter set to +//! \b true to start resume signaling. The host application must then delay +//! at least 20ms before calling this function with the \e bStart parameter set +//! to \b false. This action causes the controller to complete the resume +//! signaling on the USB bus. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostResume(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Send a resume signal to the bus. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESUME; + } + else + { + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESUME; + } +} + +//***************************************************************************** +// +//! Returns the current speed of the USB device connected. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current speed of the USB bus in host mode. +//! +//! \b Example: Get the USB connection speed. +//! +//! \verbatim +//! // +//! // Get the connection speed of the device connected to the USB controller. +//! // +//! USBHostSpeedGet(USB0_BASE); +//! \endverbatim +//! +//! \note This function must only be called in host mode. +//! +//! \return Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, +//! or \b USB_UNDEF_SPEED. +// +//***************************************************************************** +uint32_t +USBHostSpeedGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // If the Full Speed device bit is set, then this is a full speed device. + // + if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_FSDEV) + { + return(USB_FULL_SPEED); + } + + // + // If the Low Speed device bit is set, then this is a low speed device. + // + if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_LSDEV) + { + return(USB_LOW_SPEED); + } + + // + // The device speed is not known. + // + return(USB_UNDEF_SPEED); +} + +//***************************************************************************** +// +//! Disables control interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which control interrupts to disable. +//! +//! This function disables the control interrupts for the USB controller +//! specified by the \e ui32Base parameter. The \e ui32Flags parameter +//! specifies which control interrupts to disable. The flags passed in the +//! \e ui32Flags parameters must be the definitions that start with +//! \b USB_INTCTRL_* and not any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisableControl(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Flags & ~(USB_INTCTRL_ALL)) == 0); + + // + // If any general interrupts were disabled then write the general interrupt + // settings out to the hardware. + // + if(ui32Flags & USB_INTCTRL_STATUS) + { + HWREGB(ui32Base + USB_O_IE) &= ~(ui32Flags & USB_INTCTRL_STATUS); + } + + // + // Disable the power fault interrupt. + // + if(ui32Flags & USB_INTCTRL_POWER_FAULT) + { + HWREG(ui32Base + USB_O_EPCIM) = 0; + } + + // + // Disable the ID pin detect interrupt. + // + if(ui32Flags & USB_INTCTRL_MODE_DETECT) + { + HWREG(USB0_BASE + USB_O_IDVIM) = 0; + } +} + +//***************************************************************************** +// +//! Enables control interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which control interrupts to enable. +//! +//! This function enables the control interrupts for the USB controller +//! specified by the \e ui32Base parameter. The \e ui32Flags parameter +//! specifies which control interrupts to enable. The flags passed in the +//! \e ui32Flags parameters must be the definitions that start with +//! \b USB_INTCTRL_* and not any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnableControl(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Flags & (~USB_INTCTRL_ALL)) == 0); + + // + // If any general interrupts were enabled, then write the general + // interrupt settings out to the hardware. + // + if(ui32Flags & USB_INTCTRL_STATUS) + { + HWREGB(ui32Base + USB_O_IE) |= ui32Flags; + } + + // + // Enable the power fault interrupt. + // + if(ui32Flags & USB_INTCTRL_POWER_FAULT) + { + HWREG(ui32Base + USB_O_EPCIM) = USB_EPCIM_PF; + } + + // + // Enable the ID pin detect interrupt. + // + if(ui32Flags & USB_INTCTRL_MODE_DETECT) + { + HWREG(USB0_BASE + USB_O_IDVIM) = USB_IDVIM_ID; + } +} + +//***************************************************************************** +// +//! Returns the control interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32IntStatusEP is a pointer to the variable which holds the +//! endpoint interrupt status from RXIS And TXIS. +//! +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned are compared against the \b USB_INTCTRL_* values. +//! +//! The following are the meanings of all \b USB_INCTRL_ flags and the modes +//! for which they are valid. These values apply to any calls to +//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). +//! Some of these flags are only valid in the following modes as indicated in +//! the parentheses: Host, Device, and OTG. +//! +//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. +//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). +//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable +//! (OTG Only). +//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) +//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) +//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) +//! - \b USB_INTCTRL_SOF - Start of Frame Detected. +//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past +//! the end of a frame (Host Only) +//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) +//! - \b USB_INTCTRL_RESUME - Resume signaling detected. +//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device +//! Only) +//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed +//! (OTG Only) +//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) +//! +//! \note This call clears the source of all of the control status interrupts. +//! +//! \return Returns the status of the control interrupts for a USB controller. +//! This is the value of USBIS. +// +//***************************************************************************** +uint32_t +USBIntStatus(uint32_t ui32Base, uint32_t *pui32IntStatusEP) +{ + uint32_t ui32Status = 0; + *pui32IntStatusEP = 0; + uint32_t usbis = 0; + uint32_t rxis = 0; + uint32_t txis = 0; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + // + // Do-While to make sure that all status registers are cleared before continuing. + // This eliminates the race condition which can cause the USB interrupt to stay high + // and never get triggered again. + // + do + { + // Get the general interrupt status. + usbis = (uint32_t)HWREGB(ui32Base + USB_O_IS); + // Get the transmit interrupt status. + txis = (uint32_t)HWREGH(ui32Base + USB_O_TXIS); + // Get the receive interrupt status. + rxis = (uint32_t)HWREGH(ui32Base + USB_O_RXIS); + + // Get the general interrupt status, these bits go into the upper 8 bits + // of the returned value. + ui32Status |= usbis; + // Get the transmit interrupt status. + *pui32IntStatusEP |= txis; + // Get the receive interrupt status, these bits go into the second byte of + // the returned value. + *pui32IntStatusEP |= ((uint32_t)rxis << USB_INTEP_RX_SHIFT); + + } while(usbis != 0x0000 || txis != 0x0000 || rxis != 0x0000); + + // + // Add the power fault status. + // + if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ui32Status |= USB_INTCTRL_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate an id detection. + // + ui32Status |= USB_INTCTRL_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Returns the control interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned are compared against the \b USB_INTCTRL_* values. +//! +//! The following are the meanings of all \b USB_INCTRL_ flags and the modes +//! for which they are valid. These values apply to any calls to +//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). +//! Some of these flags are only valid in the following modes as indicated in +//! the parentheses: Host, Device, and OTG. +//! +//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. +//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). +//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable +//! (OTG Only). +//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) +//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) +//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) +//! - \b USB_INTCTRL_SOF - Start of Frame Detected. +//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past +//! the end of a frame (Host Only) +//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) +//! - \b USB_INTCTRL_RESUME - Resume signaling detected. +//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device +//! Only) +//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed +//! (OTG Only) +//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) +//! +//! \note This call clears the source of all of the control status interrupts. +//! +//! \return Returns the status of the control interrupts for a USB controller. +// +//***************************************************************************** +uint32_t +USBIntStatusControl(uint32_t ui32Base) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Get the general interrupt status, these bits go into the upper 8 bits + // of the returned value. + // + ui32Status = HWREGB(ui32Base + USB_O_IS); + + //*ui32EPStatus = USBIntStatusEndpoint(ui32Base); + + // + // Add the power fault status. + // + if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ui32Status |= USB_INTCTRL_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(USB0_BASE + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate an id detection. + // + ui32Status |= USB_INTCTRL_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(USB0_BASE + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Disables endpoint interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which endpoint interrupts to disable. +//! +//! This function disables endpoint interrupts for the USB controller specified +//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which +//! endpoint interrupts to disable. The flags passed in the \e ui32Flags +//! parameters must be the definitions that start with \b USB_INTEP_* and not +//! any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // If any transmit interrupts were disabled, then write the transmit + // interrupt settings out to the hardware. + // + HWREGH(ui32Base + USB_O_TXIE) &= + ~(ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); + + // + // If any receive interrupts were disabled, then write the receive + // interrupt settings out to the hardware. + // + HWREGH(ui32Base + USB_O_RXIE) &= + ~((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> + USB_INTEP_RX_SHIFT); +} + +//***************************************************************************** +// +//! Enables endpoint interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which endpoint interrupts to enable. +//! +//! This function enables endpoint interrupts for the USB controller specified +//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which +//! endpoint interrupts to enable. The flags passed in the \e ui32Flags +//! parameters must be the definitions that start with \b USB_INTEP_* and not +//! any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Enable any transmit endpoint interrupts. + // + HWREGH(ui32Base + USB_O_TXIE) |= + ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0); + + // + // Enable any receive endpoint interrupts. + // + HWREGH(ui32Base + USB_O_RXIE) |= + ((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> + USB_INTEP_RX_SHIFT); +} + +//***************************************************************************** +// +//! Returns the endpoint interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function reads endpoint interrupt status for a USB controller. This +//! call returns the current status for endpoint interrupts only, the control +//! interrupt status is retrieved by calling USBIntStatusControl(). The bit +//! values returned are compared against the \b USB_INTEP_* values. +//! These values are grouped into classes for \b USB_INTEP_HOST_* and +//! \b USB_INTEP_DEV_* values to handle both host and device modes with all +//! endpoints. +//! +//! \note This call clears the source of all of the endpoint interrupts. +//! +//! \return Returns the status of the endpoint interrupts for a USB controller. +// +//***************************************************************************** +uint32_t +USBIntStatusEndpoint(uint32_t ui32Base) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Get the transmit interrupt status. + // + ui32Status = HWREGH(ui32Base + USB_O_TXIS); + ui32Status |= ((uint32_t)HWREGH(ui32Base + USB_O_RXIS) << USB_INTEP_RX_SHIFT); + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Returns the interrupt number for a given USB module. +//! +//! \param ui32Base is the base address of the USB module. +//! +//! This function returns the interrupt number for the USB module with the base +//! address passed in the \e ui32Base parameter. +//! +//! \return Returns the USB interrupt number or 0 if the interrupt does not +//! exist. +// +//***************************************************************************** +static uint32_t +_USBIntNumberGet(uint32_t ui32Base) +{ + return(INT_USB0); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for the USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param pfnHandler is a pointer to the function to be called when a USB +//! interrupt occurs. +//! +//! This function registers the handler to be called when a USB interrupt +//! occurs and enables the global USB interrupt in the interrupt controller. +//! The specific desired USB interrupts must be enabled via a separate call to +//! USBIntEnable(). It is the interrupt handler's responsibility to clear the +//! interrupt sources via calls to USBIntStatusControl() and +//! USBIntStatusEndpoint(). +//! +//! \sa IntRegister() for important information about registering interrupt +//! handlers. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntRegister(uint32_t ui32Base, void (*pfnHandler)(void)) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + ui32Int = _USBIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Register the interrupt handler. + // + IntRegister(ui32Int, pfnHandler); + + // + // Enable the USB interrupt. + // + IntEnable(ui32Int); +} + +//***************************************************************************** +// +//! Unregisters an interrupt handler for the USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function unregisters the interrupt handler. This function also +//! disables the USB interrupt in the interrupt controller. +//! +//! \sa IntRegister() for important information about registering or +//! unregistering interrupt handlers. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntUnregister(uint32_t ui32Base) +{ + uint32_t ui32Int; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + ui32Int = _USBIntNumberGet(ui32Base); + + ASSERT(ui32Int != 0); + + // + // Disable the USB interrupt. + // + IntDisable(ui32Int); + + // + // Unregister the interrupt handler. + // + IntUnregister(ui32Int); +} + +//***************************************************************************** +// +//! Returns the current status of an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function returns the status of a given endpoint. If any of these +//! status bits must be cleared, then the USBDevEndpointStatusClear() or the +//! USBHostEndpointStatusClear() functions must be called. +//! +//! The following are the status flags for host mode: +//! +//! - \b USB_HOST_IN_PID_ERROR - PID error on the given endpoint. +//! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request. +//! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint. +//! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN +//! endpoint in Isochronous mode. +//! - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN +//! endpoint. +//! - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full. +//! - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint. +//! - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT +//! request. +//! - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint. +//! - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this +//! OUT endpoint. +//! - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty. +//! - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not +//! completed. +//! - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the +//! specified timeout period. +//! - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on +//! endpoint zero. +//! - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an +//! IN transaction. +//! - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN +//! transaction. +//! +//! The following are the status flags for device mode: +//! +//! - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint. +//! - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT +//! endpoint. +//! - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO. +//! - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full. +//! - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT +//! endpoint's FIFO. +//! - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come. +//! - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint. +//! - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no +//! data was ready. +//! - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty. +//! - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not +//! completed. +//! - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End +//! condition was sent. +//! - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero. +//! - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not +//! completed. +//! - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint +//! zero's OUT FIFO. +//! +//! \return The current status flags for the endpoint depending on mode. +// +//***************************************************************************** +uint32_t +USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Get the TX portion of the endpoint status. + // + ui32Status = HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1); + + // + // Get the RX portion of the endpoint status. + // + ui32Status |= + (((uint32_t)HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1)) << + USB_RX_EPSTATUS_SHIFT); + + // + // Return the endpoint status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags are the status bits that are cleared. +//! +//! This function clears the status of any bits that are passed in the +//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value +//! returned from the USBEndpointStatus() call. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Clear the specified flags for the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~ui32Flags; + } + else + { + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~ui32Flags; + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(ui32Flags >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags are the status bits that are cleared. +//! +//! This function clears the status of any bits that are passed in the +//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value +//! returned from the USBEndpointStatus() call. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // If this is endpoint 0, then the bits have different meaning and map + // into the TX memory location. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the Serviced RxPktRdy bit to clear the RxPktRdy. + // + if(ui32Flags & USB_DEV_EP0_OUT_PKTRDY) + { + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_RXRDYC; + } + + // + // Set the serviced Setup End bit to clear the SetupEnd status. + // + if(ui32Flags & USB_DEV_EP0_SETUP_END) + { + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_SETENDC; + } + + // + // Clear the Sent Stall status flag. + // + if(ui32Flags & USB_DEV_EP0_SENT_STALL) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL); + } + } + else + { + // + // Clear out any TX flags that were passed in. Only + // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN must be cleared. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(ui32Flags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN)); + + // + // Clear out valid RX flags that were passed in. Only + // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN + // must be cleared. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~((ui32Flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR | + USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Sets the value data toggle on an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to reset the data toggle. +//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1. +//! \param ui32Flags specifies whether to set the IN or OUT endpoint. +//! +//! This function is used to force the state of the data toggle in host mode. +//! If the value passed in the \e bDataToggle parameter is \b false, then the +//! data toggle is set to the DATA0 state, and if it is \b true it is set to +//! the DATA1 state. The \e ui32Flags parameter can be \b USB_EP_HOST_IN or +//! \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The +//! \e ui32Flags parameter is ignored for endpoint zero. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bDataToggle, uint32_t ui32Flags) +{ + uint32_t ui32DataToggle; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // The data toggle defaults to DATA0. + // + ui32DataToggle = 0; + + // + // See if the data toggle must be set to DATA1. + // + if(bDataToggle) + { + // + // Select the data toggle bit based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32DataToggle = USB_CSRH0_DT; + } + else if(ui32Flags == USB_EP_HOST_IN) + { + ui32DataToggle = USB_RXCSRH1_DT; + } + else + { + ui32DataToggle = USB_TXCSRH1_DT; + } + } + + // + // Set the data toggle based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the write enable and the bit value for endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRH0) = + ((HWREGB(ui32Base + USB_O_CSRH0) & + ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) | + (ui32DataToggle | USB_CSRH0_DTWE)); + } + else if(ui32Flags == USB_EP_HOST_IN) + { + // + // Set the Write enable and the bit value for an IN endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) = + ((HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) & + ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) | + (ui32DataToggle | USB_RXCSRH1_DTWE)); + } + else + { + // + // Set the Write enable and the bit value for an OUT endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) = + ((HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) & + ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) | + (ui32DataToggle | USB_TXCSRH1_DTWE)); + } +} + +//***************************************************************************** +// +//! Sets the data toggle on an endpoint to zero. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to reset the data toggle. +//! \param ui32Flags specifies whether to access the IN or OUT endpoint. +//! +//! This function causes the USB controller to clear the data toggle for an +//! endpoint. This call is not valid for endpoint zero and can be made with +//! host or device controllers. +//! +//! The \e ui32Flags parameter must be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDataToggleClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); + + // + // See if the transmit or receive data toggle must be cleared. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Stalls the specified endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to stall. +//! \param ui32Flags specifies whether to stall the IN or OUT endpoint. +//! +//! This function causes the endpoint number passed in to go into a stall +//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the +//! stall is issued on the IN portion of this endpoint. If the \e ui32Flags +//! parameter is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion +//! of this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Determine how to stall this endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Perform a stall on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_STALL | USB_CSRL0_RXRDYC; + } + else if(ui32Flags == USB_EP_DEV_IN) + { + // + // Perform a stall on an IN endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_STALL; + } + else + { + // + // Perform a stall on an OUT endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_STALL; + } +} + +//***************************************************************************** +// +//! Clears the stall condition on the specified endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint to remove the stall condition. +//! \param ui32Flags specifies whether to remove the stall condition from the +//! IN or the OUT portion of this endpoint. +//! +//! This function causes the endpoint number passed in to exit the stall +//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the +//! stall is cleared on the IN portion of this endpoint. If the \e ui32Flags +//! parameter is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT +//! portion of this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0); + + // + // Determine how to clear the stall on this endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Clear the stall on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_STALLED; + } + else if(ui32Flags == USB_EP_DEV_IN) + { + // + // Clear the stall on an IN endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + // + // Clear the stall on an OUT endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Connects the USB controller to the bus in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function causes the soft connect feature of the USB controller to +//! be enabled. Call USBDevDisconnect() to remove the USB device from the bus. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevConnect(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Enable connection to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SOFTCONN; +} + +//***************************************************************************** +// +//! Removes the USB controller from the bus in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function causes the soft connect feature of the USB controller to +//! remove the device from the USB bus. A call to USBDevConnect() is needed to +//! reconnect to the bus. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevDisconnect(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Disable connection to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) &= (~USB_POWER_SOFTCONN); +} + +//***************************************************************************** +// +//! Sets the address in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Address is the address to use for a device. +//! +//! This function configures the device address on the USB bus. This address +//! was likely received via a SET ADDRESS command from the host controller. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Set the function address in the correct location. + // + HWREGB(ui32Base + USB_O_FADDR) = (uint8_t)ui32Address; +} + +//***************************************************************************** +// +//! Returns the current device address in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current device address. This address was set +//! by a call to USBDevAddrSet(). +//! +//! \note This function must only be called in device mode. +//! +//! \return The current device address. +// +//***************************************************************************** +uint32_t +USBDevAddrGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Return the function address. + // + return(HWREGB(ui32Base + USB_O_FADDR)); +} + +//***************************************************************************** +// +//! Sets the base configuration for a host endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32MaxPayload is the maximum payload for this endpoint. +//! \param ui32NAKPollInterval is the either the NAK timeout limit or the +//! polling interval, depending on the type of endpoint. +//! \param ui32TargetEndpoint is the endpoint that the host endpoint is +//! targeting. +//! \param ui32Flags are used to configure other endpoint settings. +//! +//! This function sets the basic configuration for the transmit or receive +//! portion of an endpoint in host mode. The \e ui32Flags parameter determines +//! some of the configuration while the other parameters provide the rest. The +//! \e ui32Flags parameter determines whether this is an IN endpoint +//! (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint +//! (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed +//! endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint +//! (\b USB_EP_SPEED_LOW). +//! +//! The \b USB_EP_MODE_ flags control the type of the endpoint. +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \e ui32NAKPollInterval parameter has different meanings based on the +//! \b USB_EP_MODE value and whether or not this call is being made for +//! endpoint zero or another endpoint. For endpoint zero or any Bulk +//! endpoints, this value always indicates the number of frames to allow a +//! device to NAK before considering it a timeout. If this endpoint is an +//! isochronous or interrupt endpoint, this value is the polling interval for +//! this endpoint. +//! +//! For interrupt endpoints, the polling interval is the number of frames +//! between interrupt IN requests to an endpoint and has a range of 1 to 255. +//! For isochronous endpoints this value represents a polling interval of +//! 2 ^ (\e ui32NAKPollInterval - 1) frames. When used as a NAK timeout, the +//! \e ui32NAKPollInterval value specifies 2 ^ (\e ui32NAKPollInterval - 1) +//! frames before issuing a time out. +//! +//! There are two special time out values that can be specified when setting +//! the \e ui32NAKPollInterval value. The first is \b MAX_NAK_LIMIT, which is +//! the maximum value that can be passed in this variable. The other is +//! \b DISABLE_NAK_LIMIT, which indicates that there is no limit on the +//! number of NAKs. +//! +//! The \b USB_EP_DMA_MODE_ flags enable the type of DMA used to access the +//! endpoint's data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' section for more information on DMA +//! configuration. +//! +//! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit +//! is specified to cause the transmission of data on the USB bus to start +//! as soon as the number of bytes specified by \e ui32MaxPayload has been +//! written into the OUT FIFO for this endpoint. +//! +//! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST +//! bit can be specified to trigger the request for more data once the FIFO has +//! been drained enough to fit \e ui32MaxPayload bytes. The +//! \b USB_EP_AUTO_CLEAR bit can be used to clear the data packet ready flag +//! automatically once the data has been read from the FIFO. If this option is +//! not used, this flag must be manually cleared via a call to +//! USBDevEndpointStatusClear() or USBHostEndpointStatusClear(). +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPayload, uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + ASSERT(ui32NAKPollInterval <= MAX_NAK_LIMIT); + + // + // Endpoint zero is configured differently than the other endpoints, so see + // if this is endpoint zero. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the NAK timeout. + // + HWREGB(ui32Base + USB_O_NAKLMT) = ui32NAKPollInterval; + + // + // Set the transfer type information. + // + HWREGB(ui32Base + USB_O_TYPE0) = + ((ui32Flags & USB_EP_SPEED_FULL) ? USB_TYPE0_SPEED_FULL : + USB_TYPE0_SPEED_LOW); + } + else + { + // + // Start with the target endpoint. + // + ui32Register = ui32TargetEndpoint; + + // + // Set the speed for the device using this endpoint. + // + if(ui32Flags & USB_EP_SPEED_FULL) + { + ui32Register |= USB_TXTYPE1_SPEED_FULL; + } + else + { + ui32Register |= USB_TXTYPE1_SPEED_LOW; + } + + // + // Set the protocol for the device using this endpoint. + // + switch(ui32Flags & USB_EP_MODE_MASK) + { + // + // The bulk protocol is being used. + // + case USB_EP_MODE_BULK: + { + ui32Register |= USB_TXTYPE1_PROTO_BULK; + break; + } + + // + // The isochronous protocol is being used. + // + case USB_EP_MODE_ISOC: + { + ui32Register |= USB_TXTYPE1_PROTO_ISOC; + break; + } + + // + // The interrupt protocol is being used. + // + case USB_EP_MODE_INT: + { + ui32Register |= USB_TXTYPE1_PROTO_INT; + break; + } + + // + // The control protocol is being used. + // + case USB_EP_MODE_CTRL: + { + ui32Register |= USB_TXTYPE1_PROTO_CTRL; + break; + } + } + + // + // See if the transmit or receive endpoint is being configured. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transfer type information. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) = + ui32Register; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXINTERVAL1) = + ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = + ui32MaxPayload; + + // + // Set the transmit control value to zero. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been + // loaded into the FIFO. + // + if(ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA Mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_TXCSRH1_DMAEN; + } + + // + // Write out the transmit control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + (uint8_t)ui32Register; + } + else + { + // + // Set the transfer type information. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) = + ui32Register; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXINTERVAL1) = + ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = + ui32MaxPayload; + + // + // Set the receive control value to zero. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register |= USB_RXCSRH1_AUTOCL; + } + + // + // Allow auto generation of DMA requests. + // + if(ui32Flags & USB_EP_AUTO_REQUEST) + { + ui32Register |= USB_RXCSRH1_AUTORQ; + } + + // + // Configure the DMA Mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_RXCSRH1_DMAEN; + } + + // + // Write out the receive control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + (uint8_t)ui32Register; + } + } +} + +//***************************************************************************** +// +//! Sets the configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32MaxPacketSize is the maximum packet size for this endpoint. +//! \param ui32Flags are used to configure other endpoint settings. +//! +//! This function sets the basic configuration for an endpoint in device mode. +//! Endpoint zero does not have a dynamic configuration, so this function +//! must not be called for endpoint zero. The \e ui32Flags parameter +//! determines some of the configuration while the other parameters provide the +//! rest. +//! +//! The \b USB_EP_MODE_ flags define what the type is for the given endpoint. +//! +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the +//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' section for more information on DMA +//! configuration. +//! +//! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be +//! specified to cause the automatic transmission of data on the USB bus as +//! soon as \e ui32MaxPacketSize bytes of data are written into the FIFO for +//! this endpoint. This option is commonly used with DMA as no interaction is +//! required to start the transmission of data. +//! +//! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is +//! specified to trigger the request for more data once the FIFO has been +//! drained enough to receive \e ui32MaxPacketSize more bytes of data. Also +//! for OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the +//! data packet ready flag automatically once the data has been read from the +//! FIFO. If this option is not used, this flag must be manually cleared via a +//! call to USBDevEndpointStatusClear(). Both of these settings can be used to +//! remove the need for extra calls when using the controller in DMA mode. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); + + // + // Determine if a transmit or receive endpoint is being configured. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Set the maximum packet size. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = + ui32MaxPacketSize; + + // + // The transmit control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been loaded + // into the FIFO. + // + if(ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_TXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_TXCSRH1_ISO; + } + + // + // Write the transmit control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + (uint8_t)ui32Register; + + // + // Reset the Data toggle to zero. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1) = + USB_TXCSRL1_CLRDT; + } + else + { + // + // Set the MaxPacketSize. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = + ui32MaxPacketSize; + + // + // The receive control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register = USB_RXCSRH1_AUTOCL; + } + + // + // Configure the DMA mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_RXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_RXCSRH1_ISO; + } + + // + // Write the receive control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + (uint8_t)ui32Register; + + // + // Reset the Data toggle to zero. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1) = + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Gets the current configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui32MaxPacketSize is a pointer which is written with the maximum +//! packet size for this endpoint. +//! \param pui32Flags is a pointer which is written with the current endpoint +//! settings. On entry to the function, this pointer must contain either +//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT +//! endpoint is to be queried. +//! +//! This function returns the basic configuration for an endpoint in device +//! mode. The values returned in \e *pui32MaxPacketSize and \e *pui32Flags are +//! equivalent to the \e ui32MaxPacketSize and \e ui32Flags previously passed +//! to USBDevEndpointConfigSet() for this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, uint32_t *pui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT(pui32MaxPacketSize && pui32Flags); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); + + // + // Determine if a transmit or receive endpoint is being queried. + // + if(*pui32Flags & USB_EP_DEV_IN) + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_IN; + + // + // Get the maximum packet size. + // + *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + + EP_OFFSET(ui32Endpoint) + + USB_O_TXMAXP1); + + // + // Get the current transmit control register value. + // + ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + + USB_O_TXCSRH1); + + // + // Are we allowing auto setting of TxPktRdy when max packet size has + // been loaded into the FIFO? + // + if(ui32Register & USB_TXCSRH1_AUTOSET) + { + *pui32Flags |= USB_EP_AUTO_SET; + } + + // + // Get the DMA mode. + // + if(ui32Register & USB_TXCSRH1_DMAEN) + { + if(ui32Register & USB_TXCSRH1_DMAMOD) + { + *pui32Flags |= USB_EP_DMA_MODE_1; + } + else + { + *pui32Flags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ui32Register & USB_TXCSRH1_ISO) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode change. + // If they decode the returned mode, however, they may be in for + // a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } + else + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_OUT; + + // + // Get the MaxPacketSize. + // + *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + + EP_OFFSET(ui32Endpoint) + + USB_O_RXMAXP1); + + // + // Get the current receive control register value. + // + ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + + USB_O_RXCSRH1); + + // + // Are we allowing auto clearing of RxPktRdy when packet of size max + // packet has been unloaded from the FIFO? + // + if(ui32Register & USB_RXCSRH1_AUTOCL) + { + *pui32Flags |= USB_EP_AUTO_CLEAR; + } + + // + // Get the DMA mode. + // + if(ui32Register & USB_RXCSRH1_DMAEN) + { + if(ui32Register & USB_RXCSRH1_DMAMOD) + { + *pui32Flags |= USB_EP_DMA_MODE_1; + } + else + { + *pui32Flags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ui32Register & USB_RXCSRH1_ISO) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode change. + // If they decode the returned mode, however, they may be in for + // a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } +} + +//***************************************************************************** +// +//! Sets the FIFO configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32FIFOAddress is the starting address for the FIFO. +//! \param ui32FIFOSize is the size of the FIFO specified by one of the +//! USB_FIFO_SZ_ values. +//! \param ui32Flags specifies what information to set in the FIFO +//! configuration. +//! +//! This function configures the starting FIFO RAM address and size of the FIFO +//! for a given endpoint. Endpoint zero does not have a dynamically +//! configurable FIFO, so this function must not be called for endpoint zero. +//! The \e ui32FIFOSize parameter must be one of the values in the +//! \b USB_FIFO_SZ_ values. +//! +//! The \e ui32FIFOAddress value must be a multiple of 8 bytes and directly +//! indicates the starting address in the USB controller's FIFO RAM. For +//! example, a value of 64 indicates that the FIFO starts 64 bytes into +//! the USB controller's FIFO memory. The \e ui32Flags value specifies whether +//! the endpoint's OUT or IN FIFO must be configured. If in host mode, use +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use +//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Set the transmit FIFO location and size for this endpoint. + // + _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_TXFIFOSZ, + ui32FIFOSize, 1); + _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_TXFIFOADD, + ui32FIFOAddress >> 3, 2); + } + else + { + // + // Set the receive FIFO location and size for this endpoint. + // + _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_RXFIFOSZ, + ui32FIFOSize, 1); + _USBIndexWrite(ui32Base, ui32Endpoint >> 4, USB_O_RXFIFOADD, + ui32FIFOAddress >> 3, 2); + } +} + +//***************************************************************************** +// +//! Returns the FIFO configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui32FIFOAddress is the starting address for the FIFO. +//! \param pui32FIFOSize is the size of the FIFO as specified by one of the +//! USB_FIFO_SZ_ values. +//! \param ui32Flags specifies what information to retrieve from the FIFO +//! configuration. +//! +//! This function returns the starting address and size of the FIFO for a +//! given endpoint. Endpoint zero does not have a dynamically configurable +//! FIFO, so this function must not be called for endpoint zero. The +//! \e ui32Flags parameter specifies whether the endpoint's OUT or IN FIFO must +//! be read. If in host mode, the \e ui32Flags parameter must be +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the +//! \e ui32Flags parameter must be either \b USB_EP_DEV_OUT or +//! \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32FIFOAddress, uint32_t *pui32FIFOSize, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Get the transmit FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4, + (uint32_t)USB_O_TXFIFOADD, + 2)) << 3; + *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4, + (uint32_t)USB_O_TXFIFOSZ, 1); + } + else + { + // + // Get the receive FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4, + (uint32_t)USB_O_RXFIFOADD, + 2)) << 3; + *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4, + (uint32_t)USB_O_RXFIFOSZ, 1); + } +} + +//***************************************************************************** +// +//! Configure the DMA settings for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Config specifies the configuration options for an endpoint. +//! +//! This function configures the DMA settings for a given endpoint without +//! changing other options that may already be configured. In order for the +//! DMA transfer to be enabled, the USBEndpointDMAEnable() function must be +//! called before starting the DMA transfer. The configuration +//! options are passed in the \e ui32Config parameter and can have the values +//! described below. +//! +//! One of the following values to specify direction: +//! - \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN - This setting is used with +//! DMA transfers from memory to the USB controller. +//! - \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT - This setting is used with +//! DMA transfers from the USB controller to memory. +//! +//! One of the following values: +//! - \b USB_EP_DMA_MODE_0(default) - This setting is typically used for +//! transfers that do not span multiple packets or when interrupts are +//! required for each packet. +//! - \b USB_EP_DMA_MODE_1 - This setting is typically used for +//! transfers that span multiple packets and do not require interrupts +//! between packets. +//! +//! Values only used with \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN: +//! - \b USB_EP_AUTO_SET - This setting is used to allow transmit DMA transfers +//! to automatically be sent when a full packet is loaded into a FIFO. +//! This is needed with \b USB_EP_DMA_MODE_1 to ensure that packets go +//! out when the FIFO becomes full and the DMA has more data to send. +//! +//! Values only used with \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT: +//! - \b USB_EP_AUTO_CLEAR - This setting is used to allow receive DMA +//! transfers to automatically be acknowledged as they are received. This is +//! needed with \b USB_EP_DMA_MODE_1 to ensure that packets continue to +//! be received and acknowledged when the FIFO is emptied by the DMA +//! transfer. +//! +//! Values only used with \b USB_EP_HOST_IN: +//! - \b USB_EP_AUTO_REQUEST - This setting is used to allow receive DMA +//! transfers to automatically request a new IN transaction when the +//! previous transfer has emptied the FIFO. This is typically used in +//! conjunction with \b USB_EP_AUTO_CLEAR so that receive DMA transfers +//! can continue without interrupting the main processor. +//! +//! \b Example: Set endpoint 1 receive endpoint to automatically acknowledge +//! request and automatically generate a new IN request in host mode. +//! +//! \verbatim +//! // +//! // Configure endpoint 1 for receiving multiple packets using DMA. +//! // +//! USBEndpointDMAConfigSet(USB0_BASE, USB_EP_1, USB_EP_HOST_IN | +//! USB_EP_DMA_MODE_1 | +//! USB_EP_AUTO_CLEAR | +//! USB_EP_AUTO_REQUEST); +//! \endverbatim +//! +//! \b Example: Set endpoint 2 transmit endpoint to automatically send each +//! packet in host mode when spanning multiple packets. +//! +//! \verbatim +//! // +//! // Configure endpoint 1 for transmitting multiple packets using DMA. +//! // +//! USBEndpointDMAConfigSet(USB0_BASE, USB_EP_2, USB_EP_HOST_OUT | +//! USB_EP_DMA_MODE_1 | +//! USB_EP_AUTO_SET); +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Config) +{ + uint32_t ui32NewConfig; + + if(ui32Config & USB_EP_HOST_OUT) + { + // + // Clear mode and DMA enable. + // + ui32NewConfig = + (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) & + ~(USB_TXCSRH1_DMAMOD | USB_TXCSRH1_AUTOSET)); + + if(ui32Config & USB_EP_DMA_MODE_1) + { + ui32NewConfig |= USB_TXCSRH1_DMAMOD; + } + + if(ui32Config & USB_EP_AUTO_SET) + { + ui32NewConfig |= USB_TXCSRH1_AUTOSET; + } + + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + ui32NewConfig; + } + else + { + ui32NewConfig = + (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) & + ~(USB_RXCSRH1_AUTORQ | USB_RXCSRH1_AUTOCL | USB_RXCSRH1_DMAMOD)); + + if(ui32Config & USB_EP_DMA_MODE_1) + { + ui32NewConfig |= USB_RXCSRH1_DMAMOD; + } + + if(ui32Config & USB_EP_AUTO_CLEAR) + { + ui32NewConfig |= USB_RXCSRH1_AUTOCL; + } + if(ui32Config & USB_EP_AUTO_REQUEST) + { + ui32NewConfig |= USB_RXCSRH1_AUTORQ; + } + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + ui32NewConfig; + } +} + +//***************************************************************************** +// +//! Enable DMA on a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies which direction and what mode to use when +//! enabling DMA. +//! +//! This function enables DMA on a given endpoint and configures the mode +//! according to the values in the \e ui32Flags parameter. The \e ui32Flags +//! parameter must have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. Once this +//! function is called the only DMA or error interrupts are generated by the +//! USB controller. +//! +//! \note If this function is called when an endpoint is configured in DMA +//! mode 0 the USB controller does not generate an interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // See if the transmit DMA is being enabled. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Enable DMA on the transmit endpoint. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) |= + USB_TXCSRH1_DMAEN; + } + else + { + // + // Enable DMA on the receive endpoint. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) |= + USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Disable DMA on a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies which direction to disable. +//! +//! This function disables DMA on a given endpoint to allow non-DMA USB +//! transactions to generate interrupts normally. The \e ui32Flags parameter +//! must be \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // If this was a request to disable DMA on the IN portion of the endpoint + // then handle it. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) &= + ~USB_TXCSRH1_DMAEN; + } + else + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) &= + ~USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Determine the number of bytes of data available in a given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function returns the number of bytes of data currently available in +//! the FIFO for the given receive (OUT) endpoint. It may be used prior to +//! calling USBEndpointDataGet() to determine the size of buffer required to +//! hold the newly-received packet. +//! +//! \return This call returns the number of bytes available in a given endpoint +//! FIFO. +// +//***************************************************************************** +uint32_t +USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Is there a packet ready in the FIFO? + // + if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) + { + return(0); + } + + // + // Return the byte count in the FIFO. + // + return(HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint)); +} + +//***************************************************************************** +// +//! Retrieves data from the given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui8Data is a pointer to the data area used to return the data from +//! the FIFO. +//! \param pui32Size is initially the size of the buffer passed into this call +//! via the \e pui8Data parameter. It is set to the amount of data returned in +//! the buffer. +//! +//! This function returns the data from the FIFO for the given endpoint. +//! The \e pui32Size parameter indicates the size of the buffer passed in +//! the \e pui32Data parameter. The data in the \e pui32Size parameter is +//! changed to match the amount of data returned in the \e pui8Data parameter. +//! If a zero-byte packet is received, this call does not return an error but +//! instead just returns a zero in the \e pui32Size parameter. The only error +//! case occurs when there is no data packet available. +//! +//! \return This call returns 0, or -1 if no packet was received. +// +//***************************************************************************** +int32_t +USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size) +{ + uint32_t ui32Register, ui32ByteCount, ui32FIFO; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Don't allow reading of data if the RxPktRdy bit is not set. + // + if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) + { + // + // Can't read the data because none is available. + // + *pui32Size = 0; + + // + // Return a failure since there is no data to read. + // + return(-1); + } + + // + // Get the byte count in the FIFO. + // + ui32ByteCount = HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint); + + // + // Determine how many bytes are copied. + // + ui32ByteCount = (ui32ByteCount < *pui32Size) ? ui32ByteCount : *pui32Size; + + // + // Return the number of bytes we are going to read. + // + *pui32Size = ui32ByteCount; + + // + // Calculate the FIFO address. + // + ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); + + // + // Read the data out of the FIFO. + // + for(; ui32ByteCount > 0; ui32ByteCount--) + { + // + // Read a byte at a time from the FIFO. + // + *pui8Data++ = HWREGB(ui32FIFO); + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the given endpoint's FIFO in device +//! mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param bIsLastPacket indicates if this packet is the last one. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! The \e bIsLastPacket parameter is set to a \b true value if this is the +//! last in a series of data packets on endpoint zero. The \e bIsLastPacket +//! parameter is not used for endpoints other than endpoint zero. This call +//! can be used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bIsLastPacket) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Determine which endpoint is being acked. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Clear RxPktRdy, and optionally DataEnd, on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) = + USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0); + } + else + { + // + // Clear RxPktRdy on all other endpoints. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the given endpoint's FIFO in host +//! mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! This call is used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Clear RxPktRdy. + // + if(ui32Endpoint == USB_EP_0) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY; + } + else + { + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Puts data into the given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui8Data is a pointer to the data area used as the source for the +//! data to put into the FIFO. +//! \param ui32Size is the amount of data to put into the FIFO. +//! +//! This function puts the data from the \e pui8Data parameter into the FIFO +//! for this endpoint. If a packet is already pending for transmission, then +//! this call does not put any of the data into the FIFO and returns -1. Care +//! must be taken to not write more data than can fit into the FIFO +//! allocated by the call to USBFIFOConfigSet(). +//! +//! \return This call returns 0 on success, or -1 to indicate that the FIFO +//! is in use and cannot be written. +// +//***************************************************************************** +int32_t +USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t ui32Size) +{ + uint32_t ui32FIFO; + uint8_t ui8TxPktRdy; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui8TxPktRdy = USB_CSRL0_TXRDY; + } + else + { + ui8TxPktRdy = USB_TXCSRL1_TXRDY; + } + + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & ui8TxPktRdy) + { + return(-1); + } + + // + // Calculate the FIFO address. + // + ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); + + // + // Write the data to the FIFO. + // + for(; ui32Size > 0; ui32Size--) + { + HWREGB(ui32FIFO) = *pui8Data++; + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Starts the transfer of data from an endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32TransType is set to indicate what type of data is being sent. +//! +//! This function starts the transfer of data from the FIFO for a given +//! endpoint. This function is called if the \b USB_EP_AUTO_SET bit was +//! not enabled for the endpoint. Setting the \e ui32TransType parameter +//! allows the appropriate signaling on the USB bus for the type of transaction +//! being requested. The \e ui32TransType parameter must be one of the +//! following: +//! +//! - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode. +//! - \b USB_TRANS_IN for IN transaction on any endpoint in device mode. +//! - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a +//! sequence of IN transactions. +//! - \b USB_TRANS_SETUP for setup transactions on endpoint zero. +//! - \b USB_TRANS_STATUS for status results on endpoint zero. +//! +//! \return This call returns 0 on success, or -1 if a transmission is already +//! in progress. +// +//***************************************************************************** +int32_t +USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32TransType) +{ + uint32_t ui32TxPktRdy; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0) & USB_CSRL0_TXRDY) + { + return(-1); + } + + ui32TxPktRdy = ui32TransType & 0xff; + } + else + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & USB_TXCSRL1_TXRDY) + { + return(-1); + } + + ui32TxPktRdy = (ui32TransType >> 8) & 0xff; + } + + // + // Set TxPktRdy in order to send the data. + // + HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) = ui32TxPktRdy; + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Forces a flush of an endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies if the IN or OUT endpoint is accessed. +//! +//! This function forces the USB controller to flush out the data in the FIFO. +//! The function can be called with either host or device controllers and +//! requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Endpoint zero has a different register set for FIFO flushing. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Nothing in the FIFO if neither of these bits are set. + // + if((HWREGB(ui32Base + USB_O_CSRL0) & + (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_CSRH0) = USB_CSRH0_FLUSH; + } + } + else + { + // + // Only reset the IN or OUT FIFO. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Make sure the FIFO is not empty. + // + if(HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) & + USB_TXCSRL1_TXRDY) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_FLUSH; + } + } + else + { + // + // Make sure that the FIFO is not empty. + // + if(HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) & + USB_RXCSRL1_RXRDY) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_FLUSH; + } + } + } +} + +//***************************************************************************** +// +//! Schedules a request for an IN transaction on an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function schedules a request for an IN transaction. When the USB +//! device being communicated with responds with the data, the data can be +//! retrieved by calling USBEndpointDataGet() or via a DMA transfer. +//! +//! \note This function must only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Set the request for an IN transaction. + // + HWREGB(ui32Base + ui32Register) = USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Clears a scheduled IN transaction for an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function clears a previously scheduled IN transaction if it is still +//! pending. This function is used to safely disable any scheduled IN +//! transactions if the endpoint specified by \e ui32Endpoint is reconfigured +//! for communications with other devices. +//! +//! \note This function must only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Clear the request for an IN transaction. + // + HWREGB(ui32Base + ui32Register) &= ~USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Issues a request for a status IN transaction on endpoint zero. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function is used to cause a request for a status IN transaction from +//! a device on endpoint zero. This function can only be used with endpoint +//! zero as that is the only control endpoint that supports this ability. This +//! function is used to complete the last phase of a control transaction to a +//! device and an interrupt is signaled when the status packet has been +//! received. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestStatus(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Set the request for a status IN transaction. + // + HWREGB(ui32Base + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS; +} + +//***************************************************************************** +// +//! Sets the functional address for the device that is connected to an +//! endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Addr is the functional address for the controller to use for +//! this endpoint. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function configures the functional address for a device that is using +//! this endpoint for communication. This \e ui32Addr parameter is the address +//! of the target device that this endpoint is communicating with. The +//! \e ui32Flags parameter indicates if the IN or OUT endpoint is set. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // See if the transmit or receive address is set. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transmit address. + // + HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1)) = ui32Addr; + } + else + { + // + // Set the receive address. + // + HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4 + (ui32Endpoint >> 1)) = + ui32Addr; + } +} + +//***************************************************************************** +// +//! Gets the current functional device address for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current functional address that an endpoint is +//! using to communicate with a device. The \e ui32Flags parameter determines +//! if the IN or OUT endpoint's device address is returned. +//! +//! \note This function must only be called in host mode. +//! +//! \return Returns the current function address being used by an endpoint. +// +//***************************************************************************** +uint32_t +USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // See if the transmit or receive address is returned. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Return this endpoint's transmit address. + // + return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1))); + } + else + { + // + // Return this endpoint's receive address. + // + return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4 + (ui32Endpoint >> 1))); + } +} + +//***************************************************************************** +// +//! Sets the hub address for the device that is connected to an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Addr is the hub address and port for the device using this +//! endpoint. The hub address must be defined in bits 0 through 6 with the +//! port number in bits 8 through 14. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function configures the hub address for a device that is using this +//! endpoint for communication. The \e ui32Flags parameter determines if the +//! device address for the IN or the OUT endpoint is configured by this call +//! and sets the speed of the downstream device. Valid values are one of +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with +//! \b USB_EP_SPEED_LOW. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // See if the hub transmit or receive address is being set. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the hub transmit address and port number for this endpoint. + // + HWREGH(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1)) = ui32Addr; + } + else + { + // + // Set the hub receive address and port number for this endpoint. + // + HWREGH(ui32Base + USB_O_TXHUBADDR0 + 4 + (ui32Endpoint >> 1)) = + ui32Addr; + } + + // + // Set the speed of communication for endpoint 0. This configuration is + // done here because it changes on a transaction-by-transaction basis for + // EP0. For other endpoints, this is set in USBHostEndpointConfig(). + // + if(ui32Endpoint == USB_EP_0) + { + if(ui32Flags & USB_EP_SPEED_FULL) + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL; + } + else + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW; + } + } +} + +//***************************************************************************** +// +//! Gets the current device hub address for this endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current hub address that an endpoint is using +//! to communicate with a device. The \e ui32Flags parameter determines if the +//! device address for the IN or OUT endpoint is returned. +//! +//! \note This function must only be called in host mode. +//! +//! \return This function returns the current hub address being used by an +//! endpoint. +// +//***************************************************************************** +uint32_t +USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7)); + + // + // See if the hub transmit or receive address is returned. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Return the hub transmit address for this endpoint. + // + return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1))); + } + else + { + // + // Return the hub receive address for this endpoint. + // + return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + 4 + (ui32Endpoint >> 1))); + } +} + +//***************************************************************************** +// +//! Sets the configuration for USB power fault. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies the configuration of the power fault. +//! +//! This function controls how the USB controller uses its external power +//! control pins (USBnPFLT and USBnEPEN). The flags specify the power +//! fault level sensitivity, the power fault action, and the power enable level +//! and source. +//! +//! One of the following can be selected as the power fault level sensitivity: +//! +//! - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin +//! being driven low. +//! - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin +//! being driven high. +//! +//! One of the following can be selected as the power fault action: +//! +//! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault +//! detected. +//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a +//! power fault. +//! +//! One of the following can be selected as the power enable level and source: +//! +//! - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller +//! when USBHostPwrEnable() is called. +//! - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB +//! controller when USBHostPwrEnable() is +//! called. +//! - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller +//! automatically if USBOTGSessionRequest() has +//! enabled a session. +//! - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB +//! controller automatically if +//! USBOTGSessionRequest() has enabled a +//! session. +//! +//! On devices that support the VBUS glitch filter, the +//! \b USB_HOST_PWREN_FILTER can be added to ignore small, short drops in VBUS +//! level caused by high power consumption. This feature is mainly used to +//! avoid causing VBUS errors caused by devices with high in-rush current. +//! +//! \note This function must only be called on microcontrollers that support +//! host mode or OTG operation. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Flags & ~(USB_HOST_PWREN_FILTER | USB_EPC_PFLTACT_M | + USB_EPC_PFLTAEN | USB_EPC_PFLTSEN_HIGH | + USB_EPC_EPEN_M)) == 0); + + // + // If requested, enable VBUS droop detection on parts that support this + // feature. + // + HWREG(ui32Base + USB_O_VDC) = ui32Flags >> 16; + + // + // Set the power fault configuration as specified. This configuration + // does not change whether fault detection is enabled or not. + // + HWREGH(ui32Base + USB_O_EPC) = + (ui32Flags | (HWREGH(ui32Base + USB_O_EPC) & + ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN | + USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M))); +} + +//***************************************************************************** +// +//! Enables power fault detection. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function enables power fault detection in the USB controller. If the +//! USBnPFLT pin is not in use, this function must not be used. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Enable power fault input. + // + HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Disables power fault detection. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables power fault detection in the USB controller. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Enable power fault input. + // + HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Enables the external power pin. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function enables the USBnEPEN signal, which enables an external power +//! supply in host mode operation. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Enable the external power supply enable signal. + // + HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Disables the external power pin. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables the USBnEPEN signal, which disables an external +//! power supply in host mode operation. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Disable the external power supply enable signal. + // + HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Get the current frame number. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the last frame number received. +//! +//! \return The last frame number received. +// +//***************************************************************************** +uint32_t +USBFrameNumberGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Return the most recent frame number. + // + return(HWREGH(ui32Base + USB_O_FRAME)); +} + +//***************************************************************************** +// +//! Starts or ends a session. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies if this call starts or ends a session. +//! +//! This function is used in OTG mode to start a session request or end a +//! session. If the \e bStart parameter is set to \b true, then this function +//! starts a session and if it is \b false it ends a session. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGSessionRequest(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Start or end the session as directed. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_DEVCTL) |= USB_DEVCTL_SESSION; + } + else + { + HWREGB(ui32Base + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION; + } +} + +//***************************************************************************** +// +//! Returns the absolute FIFO address for a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint's FIFO address to return. +//! +//! This function returns the actual physical address of the FIFO. This +//! address is needed when the USB is going to be used with the uDMA +//! controller and the source or destination address must be set to the +//! physical FIFO address for a given endpoint. +//! +//! \return None. +// +//***************************************************************************** +uint32_t +USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + // + // Return the FIFO address for this endpoint. + // + return(ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2)); +} + +//***************************************************************************** +// +//! Returns the current operating mode of the controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current operating mode on USB controllers with +//! OTG or Dual mode functionality. +//! +//! For OTG controllers: +//! +//! The function returns one of the following values on OTG controllers: +//! \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE. +//! +//! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode +//! on the B-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode +//! on the B-side of the cable. If an OTG session request is started with no +//! cable in place, this mode is the default. +//! +//! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to +//! determine its role in the system. +//! +//! For Dual Mode controllers: +//! +//! The function returns one of the following values: +//! \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +//! +//! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host. +//! +//! \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device. +//! +//! \b USB_DUAL_MODE_NONE indicates that the controller is not active as +//! either a host or device. +//! +//! \return Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +// +//***************************************************************************** +uint32_t +USBModeGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Checks the current mode in the USB_O_DEVCTL and returns the current + // mode. + // + // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION + // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION + // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION | + // USB_DEVCTL_HOST + // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION + // USB_OTG_MODE_NONE: USB_DEVCTL_DEV + // + return(HWREGB(ui32Base + USB_O_DEVCTL) & + (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION | + USB_DEVCTL_VBUS_M)); +} + +//***************************************************************************** +// +//! Sets the DMA channel to use for a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint's FIFO address to return. +//! \param ui32Channel specifies which DMA channel to use for which endpoint. +//! +//! This function is used to configure which DMA channel to use with a given +//! endpoint. Receive DMA channels can only be used with receive endpoints +//! and transmit DMA channels can only be used with transmit endpoints. As a +//! result, the 3 receive and 3 transmit DMA channels can be mapped to any +//! endpoint other than 0. The values that are passed into the +//! \e ui32Channel value are the UDMA_CHANNEL_USBEP* values defined in udma.h. +//! +//! \note This function only has an effect on microcontrollers that have the +//! ability to change the DMA channel for an endpoint. Calling this function +//! on other devices has no effect. +//! +//! \return None. +//! +//***************************************************************************** +void +USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Channel) +{ + uint32_t ui32Mask; + + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7)); +// ASSERT(ui32Channel <= UDMA_CHANNEL_USBEP3TX); + + // + // The input select mask must be shifted into the correct position + // based on the channel. + // + ui32Mask = (uint32_t)0xf << (ui32Channel * 4); + + // + // Clear out the current selection for the channel. + // + ui32Mask = HWREG(ui32Base + USB_O_DMASEL) & (~ui32Mask); + + // + // The input select is now shifted into the correct position based on the + // channel. + // + ui32Mask |= ((uint32_t)USBEPToIndex(ui32Endpoint)) << (ui32Channel * 4); + + // + // Write the value out to the register. + // + HWREG(ui32Base + USB_O_DMASEL) = ui32Mask; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to host. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to host mode. +//! +//! \note This function must only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Force mode in OTG parts that support forcing USB controller mode. + // This bit is not writable in USB controllers that do not support + // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a + // force of host mode. + // + HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to device. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to device mode. +//! +//! \note This function must only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Set the USB controller mode to device. + // + HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to OTG. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to OTG mode. This +//! function is only valid on microcontrollers that have the OTG capabilities. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USB0_BASE); + + // + // Disable the override of the USB controller mode when running on an OTG + // device. + // + HWREGB(ui32Base + USB_O_GPCS) = 0; +} + +//***************************************************************************** +// +//! Powers off the USB PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function powers off the USB PHY, reducing the current consuption +//! of the device. While in the powered-off state, the USB controller is +//! unable to operate. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOff(uint32_t ui32Base) +{ + // + // Set the PWRDNPHY bit in the PHY, putting it into its low power mode. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Powers on the USB PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function powers on the USB PHY, enabling it return to normal +//! operation. By default, the PHY is powered on, so this function must +//! only be called if USBPHYPowerOff() has previously been called. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOn(uint32_t ui32Base) +{ + // + // Clear the PWRDNPHY bit in the PHY, putting it into normal operating + // mode. + // + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Sets the number of packets to request when transferring multiple bulk +//! packets. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint index to target for this write. +//! \param ui32Count is the number of packets to request. +//! +//! This function sets the number of consecutive bulk packets to request +//! when transferring multiple bulk packets with DMA. +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Count) +{ + HWREG(ui32Base + USB_O_RQPKTCOUNT1 + + (0x4 * (USBEPToIndex(ui32Endpoint) - 1))) = ui32Count; +} + +//***************************************************************************** +// +//! Returns the number of USB endpoint pairs on the device. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the number of endpoint pairs supported by the USB +//! controller corresponding to the passed base address. The value returned is +//! the number of IN or OUT endpoints available and does not include endpoint 0 +//! (the control endpoint). For example, if 15 is returned, there are 15 IN +//! and 15 OUT endpoints available in addition to endpoint 0. +//! +//! \return Returns the number of IN or OUT endpoints available. +// +//***************************************************************************** +uint32_t +USBNumEndpointsGet(uint32_t ui32Base) +{ + // + // Read the number of endpoints from the hardware. The number of TX and + // RX endpoints are always the same. + // + return(15); +} + diff --git a/bsp/ti/c28x/libraries/tms320f28379d/common/source/usb_hal.c b/bsp/ti/c28x/libraries/tms320f28379d/common/source/usb_hal.c new file mode 100644 index 0000000000..f73ff48a86 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/common/source/usb_hal.c @@ -0,0 +1,163 @@ +//########################################################################### +// +// FILE: usb_hal.c +// +// TITLE: Wrapper for interrupt functions and USB support pins. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "F2837xD_device.h" +#include "F2837xD_Examples.h" +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_usb.h" +#include "usb_hal.h" +#include "usb.h" +#include "include/usblib.h" +#include "include/usblibpriv.h" +#include "include/device/usbdevice.h" +#include "include/host/usbhost.h" +#include "include/host/usbhostpriv.h" +#include "include/usblibpriv.h" + +//***************************************************************************** +// +//! \addtogroup c2000_specific +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +//! Enables USB related GPIOs to perform their USB function. +// +//***************************************************************************** +void USBGPIOEnable(void) +{ + EALLOW; + GpioCtrlRegs.GPBLOCK.all = 0x00000000; + GpioCtrlRegs.GPBAMSEL.bit.GPIO42 = 1; + GpioCtrlRegs.GPBAMSEL.bit.GPIO43 = 1; + + //VBUS + GpioCtrlRegs.GPBDIR.bit.GPIO46 = 0; + //ID + GpioCtrlRegs.GPBDIR.bit.GPIO47 = 0; + + GpioCtrlRegs.GPDGMUX2.bit.GPIO120 = 3; + GpioCtrlRegs.GPDMUX2.bit.GPIO120 = 3; + GpioCtrlRegs.GPDGMUX2.bit.GPIO121 = 3; + GpioCtrlRegs.GPDMUX2.bit.GPIO121 = 3; + EDIS; +} + +//***************************************************************************** +// +//! Disables USB related GPIOs from performing their USB function. +// +//***************************************************************************** +void USBGPIODisable(void) +{ + EALLOW; + GpioCtrlRegs.GPBLOCK.all = 0x00000000; + GpioCtrlRegs.GPBAMSEL.bit.GPIO42 = 0; + GpioCtrlRegs.GPBAMSEL.bit.GPIO43 = 0; + + GpioCtrlRegs.GPDGMUX2.bit.GPIO120 = 0; + GpioCtrlRegs.GPDMUX2.bit.GPIO120 = 0; + GpioCtrlRegs.GPDGMUX2.bit.GPIO121 = 0; + GpioCtrlRegs.GPDMUX2.bit.GPIO121 = 0; + EDIS; +} + + +//***************************************************************************** +// +//! Wrapper function to implement mS based delay for USB functions +// +//***************************************************************************** +void USBDelay(uint32_t ui32Delay) +{ + DELAY_US(ui32Delay*1000); +} + +//***************************************************************************** +// +//! Device interrupt service routine wrapper to make ISR compatible with +//! C2000 PIE controller. +// +//***************************************************************************** + +__interrupt void +f28x_USB0DeviceIntHandler(void) +{ + USB0DeviceIntHandler(); + PieCtrlRegs.PIEACK.all |= 0x0100; +} +//***************************************************************************** +// +//! Host interrupt service routine wrapper to make ISR compatible with +//! C2000 PIE controller. +// +//***************************************************************************** +__interrupt void +f28x_USB0HostIntHandler(void) +{ + USB0HostIntHandler(); + PieCtrlRegs.PIEACK.all |= 0x0100; +} + +//***************************************************************************** +// +//! Dual mode interrupt service routine wrapper to make ISR compatible with +//! C2000 PIE controller. +// +//***************************************************************************** +__interrupt void +f28x_USB0DualModeIntHandler(void) +{ + USB0DualModeIntHandler(); + PieCtrlRegs.PIEACK.all |= 0x0100; +} + +//***************************************************************************** +// +// Close the c2000_specific Doxygen group. +//! @} +// +//***************************************************************************** + diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd b/bsp/ti/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd new file mode 100644 index 0000000000..2f91325867 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd @@ -0,0 +1,287 @@ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + ADCA_RESULT : origin = 0x000B00, length = 0x000020 + ADCB_RESULT : origin = 0x000B20, length = 0x000020 + ADCC_RESULT : origin = 0x000B40, length = 0x000020 + ADCD_RESULT : origin = 0x000B60, length = 0x000020 + + ADCA : origin = 0x007400, length = 0x000080 + ADCB : origin = 0x007480, length = 0x000080 + ADCC : origin = 0x007500, length = 0x000080 + ADCD : origin = 0x007580, length = 0x000080 + + ANALOG_SUBSYS : origin = 0x05D180, length = 0x000080 + + CANA : origin = 0x048000, length = 0x000800 + CANB : origin = 0x04A000, length = 0x000800 + + CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */ + + CLB_XBAR : origin = 0x007A40, length = 0x000040 + + CMPSS1 : origin = 0x005C80, length = 0x000020 + CMPSS2 : origin = 0x005CA0, length = 0x000020 + CMPSS3 : origin = 0x005CC0, length = 0x000020 + CMPSS4 : origin = 0x005CE0, length = 0x000020 + CMPSS5 : origin = 0x005D00, length = 0x000020 + CMPSS6 : origin = 0x005D20, length = 0x000020 + CMPSS7 : origin = 0x005D40, length = 0x000020 + CMPSS8 : origin = 0x005D60, length = 0x000020 + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ + + DACA : origin = 0x005C00, length = 0x000010 + DACB : origin = 0x005C10, length = 0x000010 + DACC : origin = 0x005C20, length = 0x000010 + + DMA : origin = 0x001000, length = 0x000200 + DMACLASRCSEL : origin = 0x007980, length = 0x000040 + + ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EMIF1 : origin = 0x047000, length = 0x000800 + EMIF2 : origin = 0x047800, length = 0x000800 + + EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ + EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */ + + EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ + EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ + EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ + EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */ + EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */ + EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */ + EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */ + + EPWM_XBAR : origin = 0x007A00, length = 0x000040 + + FLASH0_CTRL : origin = 0x05F800, length = 0x000300 + FLASH0_ECC : origin = 0x05FB00, length = 0x000040 + + GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */ + GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */ + + OUTPUT_XBAR : origin = 0x007A80, length = 0x000040 + I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ + I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */ + + IPC : origin = 0x050000, length = 0x000024 + + FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002 + + ROMPREFETCH : origin = 0x05E608, length = 0x000002 + + MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ + EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */ + EMIF2CONFIG : origin = 0x05F4A0, length = 0x000020 /* Emif-2 Config registers */ + ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ + MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ + ROMWAITSTATE : origin = 0x05F540, length = 0x000002 /* ROM Config registers */ + + + MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */ + + NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ + SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ + SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ + SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */ + SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */ + + SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ + SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */ + + SPIA : origin = 0x006100, length = 0x000010 + SPIB : origin = 0x006110, length = 0x000010 + SPIC : origin = 0x006120, length = 0x000010 + SPID : origin = 0x006130, length = 0x000010 + + UPP : origin = 0x006200, length = 0x000100 /* uPP registers */ + + DEV_CFG : origin = 0x05D000, length = 0x000180 + CLK_CFG : origin = 0x05D200, length = 0x000100 + CPU_SYS : origin = 0x05D300, length = 0x000100 + + INPUT_XBAR : origin = 0x007900, length = 0x000020 + XBAR : origin = 0x007920, length = 0x000020 + SYNC_SOC : origin = 0x007940, length = 0x000010 + WD : origin = 0x007000, length = 0x000040 + + XINT : origin = 0x007070, length = 0x000010 + + DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */ + DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */ + DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ + +} + + +SECTIONS +{ +/*** PIE Vect Table and Boot ROM Variables Structures ***/ + UNION run = PIE_VECT, PAGE = 1 + { + PieVectTableFile : TYPE=DSECT + GROUP + { + EmuBModeVar : TYPE=DSECT + EmuBootPinsVar : TYPE=DSECT + } + } + + AdcaResultFile : > ADCA_RESULT, PAGE = 1 + AdcbResultFile : > ADCB_RESULT, PAGE = 1 + AdccResultFile : > ADCC_RESULT, PAGE = 1 + AdcdResultFile : > ADCD_RESULT, PAGE = 1 + + AdcaRegsFile : > ADCA, PAGE = 1 + AdcbRegsFile : > ADCB, PAGE = 1 + AdccRegsFile : > ADCC, PAGE = 1 + AdcdRegsFile : > ADCD, PAGE = 1 + + AnalogSubsysRegsFile : > ANALOG_SUBSYS, PAGE = 1 + + CanaRegsFile : > CANA, PAGE = 1 + CanbRegsFile : > CANB, PAGE = 1 + + Cla1RegsFile : > CLA1, PAGE = 1 + Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT + + ClbXbarRegsFile : > CLB_XBAR PAGE = 1 + + Cmpss1RegsFile : > CMPSS1, PAGE = 1 + Cmpss2RegsFile : > CMPSS2, PAGE = 1 + Cmpss3RegsFile : > CMPSS3, PAGE = 1 + Cmpss4RegsFile : > CMPSS4, PAGE = 1 + Cmpss5RegsFile : > CMPSS5, PAGE = 1 + Cmpss6RegsFile : > CMPSS6, PAGE = 1 + Cmpss7RegsFile : > CMPSS7, PAGE = 1 + Cmpss8RegsFile : > CMPSS8, PAGE = 1 + + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + + DacaRegsFile : > DACA PAGE = 1 + DacbRegsFile : > DACB PAGE = 1 + DaccRegsFile : > DACC PAGE = 1 + + DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1 + DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1 + DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 + + DmaRegsFile : > DMA PAGE = 1 + DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 + + ECap1RegsFile : > ECAP1, PAGE = 1 + ECap2RegsFile : > ECAP2, PAGE = 1 + ECap3RegsFile : > ECAP3, PAGE = 1 + ECap4RegsFile : > ECAP4, PAGE = 1 + ECap5RegsFile : > ECAP5, PAGE = 1 + ECap6RegsFile : > ECAP6, PAGE = 1 + + Emif1RegsFile : > EMIF1 PAGE = 1 + Emif2RegsFile : > EMIF2 PAGE = 1 + + EPwm1RegsFile : > EPWM1, PAGE = 1 + EPwm2RegsFile : > EPWM2, PAGE = 1 + EPwm3RegsFile : > EPWM3, PAGE = 1 + EPwm4RegsFile : > EPWM4, PAGE = 1 + EPwm5RegsFile : > EPWM5, PAGE = 1 + EPwm6RegsFile : > EPWM6, PAGE = 1 + EPwm7RegsFile : > EPWM7, PAGE = 1 + EPwm8RegsFile : > EPWM8, PAGE = 1 + EPwm9RegsFile : > EPWM9, PAGE = 1 + EPwm10RegsFile : > EPWM10, PAGE = 1 + EPwm11RegsFile : > EPWM11, PAGE = 1 + EPwm12RegsFile : > EPWM12, PAGE = 1 + + EPwmXbarRegsFile : > EPWM_XBAR PAGE = 1 + + EQep1RegsFile : > EQEP1, PAGE = 1 + EQep2RegsFile : > EQEP2, PAGE = 1 + EQep3RegsFile : > EQEP3, PAGE = 1 + + Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 + Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 + GpioDataRegsFile : > GPIODAT, PAGE = 1 + + OutputXbarRegsFile : > OUTPUT_XBAR PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + I2cbRegsFile : > I2CB, PAGE = 1 + InputXbarRegsFile : > INPUT_XBAR PAGE = 1 + XbarRegsFile : > XBAR PAGE = 1 + IpcRegsFile : > IPC, PAGE = 1 + + FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1 + + RomPrefetchRegsFile : > ROMPREFETCH, PAGE = 1 + MemCfgRegsFile : > MEMCFG, PAGE = 1 + Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1 + Emif2ConfigRegsFile : > EMIF2CONFIG, PAGE = 1 + AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 + MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 + RomWaitStateRegsFile : > ROMWAITSTATE, PAGE = 1 + + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + + UppRegsFile : > UPP, PAGE = 1 + + NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + + SciaRegsFile : > SCIA, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + ScidRegsFile : > SCID, PAGE = 1 + + Sdfm1RegsFile : > SDFM1, PAGE = 1 + Sdfm2RegsFile : > SDFM2, PAGE = 1 + + SpiaRegsFile : > SPIA, PAGE = 1 + SpibRegsFile : > SPIB, PAGE = 1 + SpicRegsFile : > SPIC, PAGE = 1 + SpidRegsFile : > SPID, PAGE = 1 + + DevCfgRegsFile : > DEV_CFG, PAGE = 1 + ClkCfgRegsFile : > CLK_CFG, PAGE = 1 + CpuSysRegsFile : > CPU_SYS, PAGE = 1 + + SyncSocRegsFile : > SYNC_SOC, PAGE = 1 + + WdRegsFile : > WD, PAGE = 1 + + XintRegsFile : > XINT PAGE = 1 + MemCfgRegs : > MEMCFG PAGE = 1 + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd b/bsp/ti/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd new file mode 100644 index 0000000000..189250ad3b --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd @@ -0,0 +1,255 @@ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + ADCA_RESULT : origin = 0x000B00, length = 0x000020 + ADCB_RESULT : origin = 0x000B20, length = 0x000020 + ADCC_RESULT : origin = 0x000B40, length = 0x000020 + ADCD_RESULT : origin = 0x000B60, length = 0x000020 + + ADCA : origin = 0x007400, length = 0x000080 + ADCB : origin = 0x007480, length = 0x000080 + ADCC : origin = 0x007500, length = 0x000080 + ADCD : origin = 0x007580, length = 0x000080 + + CANA : origin = 0x048000, length = 0x000800 + CANB : origin = 0x04A000, length = 0x000800 + + CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */ + + CMPSS1 : origin = 0x005C80, length = 0x000020 + CMPSS2 : origin = 0x005CA0, length = 0x000020 + CMPSS3 : origin = 0x005CC0, length = 0x000020 + CMPSS4 : origin = 0x005CE0, length = 0x000020 + CMPSS5 : origin = 0x005D00, length = 0x000020 + CMPSS6 : origin = 0x005D20, length = 0x000020 + CMPSS7 : origin = 0x005D40, length = 0x000020 + CMPSS8 : origin = 0x005D60, length = 0x000020 + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ + + DACA : origin = 0x005C00, length = 0x000010 + DACB : origin = 0x005C10, length = 0x000010 + DACC : origin = 0x005C20, length = 0x000010 + + DMA : origin = 0x001000, length = 0x000200 + DMACLASRCSEL : origin = 0x007980, length = 0x000040 + + ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EMIF1 : origin = 0x047000, length = 0x000800 + EMIF2 : origin = 0x047800, length = 0x000800 + + EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ + EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */ + + EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ + EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ + EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ + EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */ + EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */ + EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */ + EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */ + + FLASH0_CTRL : origin = 0x05F800, length = 0x000300 + FLASH0_ECC : origin = 0x05FB00, length = 0x000040 + + GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */ + GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */ + I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ + I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */ + + IPC : origin = 0x050000, length = 0x000024 + + FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002 + + MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ + EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */ + ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ + MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ + + + MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */ + + NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ + + SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ + SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ + SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */ + SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */ + + SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ + SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */ + + SPIA : origin = 0x006100, length = 0x000010 + SPIB : origin = 0x006110, length = 0x000010 + SPIC : origin = 0x006120, length = 0x000010 + SPID : origin = 0x006130, length = 0x000010 + + DEV_CFG : origin = 0x05D000, length = 0x000200 + CLK_CFG : origin = 0x05D200, length = 0x000100 + CPU_SYS : origin = 0x05D300, length = 0x000100 + + WD : origin = 0x007000, length = 0x000040 + + XINT : origin = 0x007070, length = 0x000010 + + DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */ + DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */ + DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ + +} + + +SECTIONS +{ +/*** PIE Vect Table and Boot ROM Variables Structures ***/ + UNION run = PIE_VECT, PAGE = 1 + { + PieVectTableFile : TYPE=DSECT + GROUP + { + EmuBModeVar : TYPE=DSECT + } + } + + AdcaResultFile : > ADCA_RESULT, PAGE = 1 + AdcbResultFile : > ADCB_RESULT, PAGE = 1 + AdccResultFile : > ADCC_RESULT, PAGE = 1 + AdcdResultFile : > ADCD_RESULT, PAGE = 1 + + AdcaRegsFile : > ADCA, PAGE = 1 + AdcbRegsFile : > ADCB, PAGE = 1 + AdccRegsFile : > ADCC, PAGE = 1 + AdcdRegsFile : > ADCD, PAGE = 1 + + CanaRegsFile : > CANA, PAGE = 1 + CanbRegsFile : > CANB, PAGE = 1 + + Cla1RegsFile : > CLA1, PAGE = 1 + Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT + + Cmpss1RegsFile : > CMPSS1, PAGE = 1 + Cmpss2RegsFile : > CMPSS2, PAGE = 1 + Cmpss3RegsFile : > CMPSS3, PAGE = 1 + Cmpss4RegsFile : > CMPSS4, PAGE = 1 + Cmpss5RegsFile : > CMPSS5, PAGE = 1 + Cmpss6RegsFile : > CMPSS6, PAGE = 1 + Cmpss7RegsFile : > CMPSS7, PAGE = 1 + Cmpss8RegsFile : > CMPSS8, PAGE = 1 + + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + + DacaRegsFile : > DACA PAGE = 1 + DacbRegsFile : > DACB PAGE = 1 + DaccRegsFile : > DACC PAGE = 1 + + DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1 + DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1 + DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 + + DmaRegsFile : > DMA PAGE = 1 + DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 + + ECap1RegsFile : > ECAP1, PAGE = 1 + ECap2RegsFile : > ECAP2, PAGE = 1 + ECap3RegsFile : > ECAP3, PAGE = 1 + ECap4RegsFile : > ECAP4, PAGE = 1 + ECap5RegsFile : > ECAP5, PAGE = 1 + ECap6RegsFile : > ECAP6, PAGE = 1 + + Emif1RegsFile : > EMIF1 PAGE = 1 + Emif2RegsFile : > EMIF2 PAGE = 1 + + EPwm1RegsFile : > EPWM1, PAGE = 1 + EPwm2RegsFile : > EPWM2, PAGE = 1 + EPwm3RegsFile : > EPWM3, PAGE = 1 + EPwm4RegsFile : > EPWM4, PAGE = 1 + EPwm5RegsFile : > EPWM5, PAGE = 1 + EPwm6RegsFile : > EPWM6, PAGE = 1 + EPwm7RegsFile : > EPWM7, PAGE = 1 + EPwm8RegsFile : > EPWM8, PAGE = 1 + EPwm9RegsFile : > EPWM9, PAGE = 1 + EPwm10RegsFile : > EPWM10, PAGE = 1 + EPwm11RegsFile : > EPWM11, PAGE = 1 + EPwm12RegsFile : > EPWM12, PAGE = 1 + + EQep1RegsFile : > EQEP1, PAGE = 1 + EQep2RegsFile : > EQEP2, PAGE = 1 + EQep3RegsFile : > EQEP3, PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 + GpioDataRegsFile : > GPIODAT, PAGE = 1 + + Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 + Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 + + I2caRegsFile : > I2CA, PAGE = 1 + I2cbRegsFile : > I2CB, PAGE = 1 + IpcRegsFile : > IPC, PAGE = 1 + + FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1 + + MemCfgRegsFile : > MEMCFG, PAGE = 1 + Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1 + AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 + MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 + + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + + NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 + + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + + SciaRegsFile : > SCIA, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + ScidRegsFile : > SCID, PAGE = 1 + + Sdfm1RegsFile : > SDFM1, PAGE = 1 + Sdfm2RegsFile : > SDFM2, PAGE = 1 + + SpiaRegsFile : > SPIA, PAGE = 1 + SpibRegsFile : > SPIB, PAGE = 1 + SpicRegsFile : > SPIC, PAGE = 1 + SpidRegsFile : > SPID, PAGE = 1 + + DevCfgRegsFile : > DEV_CFG, PAGE = 1 + ClkCfgRegsFile : > CLK_CFG, PAGE = 1 + CpuSysRegsFile : > CPU_SYS, PAGE = 1 + + WdRegsFile : > WD, PAGE = 1 + + XintRegsFile : > XINT PAGE = 1 + MemCfgRegs : > MEMCFG PAGE = 1 + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd b/bsp/ti/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd new file mode 100644 index 0000000000..c125c94918 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd @@ -0,0 +1,287 @@ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + ADCA_RESULT : origin = 0x000B00, length = 0x000020 + ADCB_RESULT : origin = 0x000B20, length = 0x000020 + ADCC_RESULT : origin = 0x000B40, length = 0x000020 + ADCD_RESULT : origin = 0x000B60, length = 0x000020 + + ADCA : origin = 0x007400, length = 0x000080 + ADCB : origin = 0x007480, length = 0x000080 + ADCC : origin = 0x007500, length = 0x000080 + ADCD : origin = 0x007580, length = 0x000080 + + ANALOG_SUBSYS : origin = 0x05D180, length = 0x000080 + + CANA : origin = 0x048000, length = 0x000800 + CANB : origin = 0x04A000, length = 0x000800 + + CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */ + + CLB_XBAR : origin = 0x007A40, length = 0x000040 + + CMPSS1 : origin = 0x005C80, length = 0x000020 + CMPSS2 : origin = 0x005CA0, length = 0x000020 + CMPSS3 : origin = 0x005CC0, length = 0x000020 + CMPSS4 : origin = 0x005CE0, length = 0x000020 + CMPSS5 : origin = 0x005D00, length = 0x000020 + CMPSS6 : origin = 0x005D20, length = 0x000020 + CMPSS7 : origin = 0x005D40, length = 0x000020 + CMPSS8 : origin = 0x005D60, length = 0x000020 + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ + + DACA : origin = 0x005C00, length = 0x000010 + DACB : origin = 0x005C10, length = 0x000010 + DACC : origin = 0x005C20, length = 0x000010 + + DMA : origin = 0x001000, length = 0x000200 + DMACLASRCSEL : origin = 0x007980, length = 0x000040 + + ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EMIF1 : origin = 0x047000, length = 0x000800 + EMIF2 : origin = 0x047800, length = 0x000800 + + EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ + EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */ + + EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ + EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ + EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ + EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */ + EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */ + EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */ + EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */ + + EPWM_XBAR : origin = 0x007A00, length = 0x000040 + + FLASH0_CTRL : origin = 0x05F800, length = 0x000300 + FLASH0_ECC : origin = 0x05FB00, length = 0x000040 + + GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */ + GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */ + + OUTPUT_XBAR : origin = 0x007A80, length = 0x000040 + I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ + I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */ + + IPC : origin = 0x050000, length = 0x000024 + + FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002 + + ROMPREFETCH : origin = 0x05E608, length = 0x000002 + + MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ + EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */ + EMIF2CONFIG : origin = 0x05F4A0, length = 0x000020 /* Emif-2 Config registers */ + ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ + MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ + ROMWAITSTATE : origin = 0x05F540, length = 0x000002 /* ROM Config registers */ + + + MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */ + + NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ + SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ + SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ + SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */ + SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */ + + SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ + SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */ + + SPIA : origin = 0x006100, length = 0x000010 + SPIB : origin = 0x006110, length = 0x000010 + SPIC : origin = 0x006120, length = 0x000010 + SPID : origin = 0x006130, length = 0x000010 + + UPP : origin = 0x006200, length = 0x000100 /* uPP registers */ + + DEV_CFG : origin = 0x05D000, length = 0x000180 + CLK_CFG : origin = 0x05D200, length = 0x000100 + CPU_SYS : origin = 0x05D300, length = 0x000100 + + INPUT_XBAR : origin = 0x007900, length = 0x000020 + XBAR : origin = 0x007920, length = 0x000020 + SYNC_SOC : origin = 0x007940, length = 0x000010 + WD : origin = 0x007000, length = 0x000040 + + XINT : origin = 0x007070, length = 0x000010 + + DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */ + DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */ + DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ + +} + + +SECTIONS +{ +/*** PIE Vect Table and Boot ROM Variables Structures ***/ + UNION run = PIE_VECT, PAGE = 1 + { + PieVectTableFile + GROUP + { + EmuBModeVar + EmuBootPinsVar + } + } + + AdcaResultFile : > ADCA_RESULT, PAGE = 1 + AdcbResultFile : > ADCB_RESULT, PAGE = 1 + AdccResultFile : > ADCC_RESULT, PAGE = 1 + AdcdResultFile : > ADCD_RESULT, PAGE = 1 + + AdcaRegsFile : > ADCA, PAGE = 1 + AdcbRegsFile : > ADCB, PAGE = 1 + AdccRegsFile : > ADCC, PAGE = 1 + AdcdRegsFile : > ADCD, PAGE = 1 + + AnalogSubsysRegsFile : > ANALOG_SUBSYS, PAGE = 1 + + CanaRegsFile : > CANA, PAGE = 1 + CanbRegsFile : > CANB, PAGE = 1 + + Cla1RegsFile : > CLA1, PAGE = 1 + Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT + + ClbXbarRegsFile : > CLB_XBAR PAGE = 1 + + Cmpss1RegsFile : > CMPSS1, PAGE = 1 + Cmpss2RegsFile : > CMPSS2, PAGE = 1 + Cmpss3RegsFile : > CMPSS3, PAGE = 1 + Cmpss4RegsFile : > CMPSS4, PAGE = 1 + Cmpss5RegsFile : > CMPSS5, PAGE = 1 + Cmpss6RegsFile : > CMPSS6, PAGE = 1 + Cmpss7RegsFile : > CMPSS7, PAGE = 1 + Cmpss8RegsFile : > CMPSS8, PAGE = 1 + + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + + DacaRegsFile : > DACA PAGE = 1 + DacbRegsFile : > DACB PAGE = 1 + DaccRegsFile : > DACC PAGE = 1 + + DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1 + DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1 + DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 + + DmaRegsFile : > DMA PAGE = 1 + DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 + + ECap1RegsFile : > ECAP1, PAGE = 1 + ECap2RegsFile : > ECAP2, PAGE = 1 + ECap3RegsFile : > ECAP3, PAGE = 1 + ECap4RegsFile : > ECAP4, PAGE = 1 + ECap5RegsFile : > ECAP5, PAGE = 1 + ECap6RegsFile : > ECAP6, PAGE = 1 + + Emif1RegsFile : > EMIF1 PAGE = 1 + Emif2RegsFile : > EMIF2 PAGE = 1 + + EPwm1RegsFile : > EPWM1, PAGE = 1 + EPwm2RegsFile : > EPWM2, PAGE = 1 + EPwm3RegsFile : > EPWM3, PAGE = 1 + EPwm4RegsFile : > EPWM4, PAGE = 1 + EPwm5RegsFile : > EPWM5, PAGE = 1 + EPwm6RegsFile : > EPWM6, PAGE = 1 + EPwm7RegsFile : > EPWM7, PAGE = 1 + EPwm8RegsFile : > EPWM8, PAGE = 1 + EPwm9RegsFile : > EPWM9, PAGE = 1 + EPwm10RegsFile : > EPWM10, PAGE = 1 + EPwm11RegsFile : > EPWM11, PAGE = 1 + EPwm12RegsFile : > EPWM12, PAGE = 1 + + EPwmXbarRegsFile : > EPWM_XBAR PAGE = 1 + + EQep1RegsFile : > EQEP1, PAGE = 1 + EQep2RegsFile : > EQEP2, PAGE = 1 + EQep3RegsFile : > EQEP3, PAGE = 1 + + Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 + Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 + GpioDataRegsFile : > GPIODAT, PAGE = 1 + + OutputXbarRegsFile : > OUTPUT_XBAR PAGE = 1 + I2caRegsFile : > I2CA, PAGE = 1 + I2cbRegsFile : > I2CB, PAGE = 1 + InputXbarRegsFile : > INPUT_XBAR PAGE = 1 + XbarRegsFile : > XBAR PAGE = 1 + IpcRegsFile : > IPC, PAGE = 1 + + FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1 + + RomPrefetchRegsFile : > ROMPREFETCH, PAGE = 1 + MemCfgRegsFile : > MEMCFG, PAGE = 1 + Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1 + Emif2ConfigRegsFile : > EMIF2CONFIG, PAGE = 1 + AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 + MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 + RomWaitStateRegsFile : > ROMWAITSTATE, PAGE = 1 + + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + + UppRegsFile : > UPP, PAGE = 1 + + NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + + SciaRegsFile : > SCIA, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + ScidRegsFile : > SCID, PAGE = 1 + + Sdfm1RegsFile : > SDFM1, PAGE = 1 + Sdfm2RegsFile : > SDFM2, PAGE = 1 + + SpiaRegsFile : > SPIA, PAGE = 1 + SpibRegsFile : > SPIB, PAGE = 1 + SpicRegsFile : > SPIC, PAGE = 1 + SpidRegsFile : > SPID, PAGE = 1 + + DevCfgRegsFile : > DEV_CFG, PAGE = 1 + ClkCfgRegsFile : > CLK_CFG, PAGE = 1 + CpuSysRegsFile : > CPU_SYS, PAGE = 1 + + SyncSocRegsFile : > SYNC_SOC, PAGE = 1 + + WdRegsFile : > WD, PAGE = 1 + + XintRegsFile : > XINT PAGE = 1 + MemCfgRegs : > MEMCFG PAGE = 1 + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd b/bsp/ti/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd new file mode 100644 index 0000000000..af9414a90d --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd @@ -0,0 +1,251 @@ + +MEMORY +{ + PAGE 0: /* Program Memory */ + + PAGE 1: /* Data Memory */ + + ADCA_RESULT : origin = 0x000B00, length = 0x000020 + ADCB_RESULT : origin = 0x000B20, length = 0x000020 + ADCC_RESULT : origin = 0x000B40, length = 0x000020 + ADCD_RESULT : origin = 0x000B60, length = 0x000020 + + ADCA : origin = 0x007400, length = 0x000080 + ADCB : origin = 0x007480, length = 0x000080 + ADCC : origin = 0x007500, length = 0x000080 + ADCD : origin = 0x007580, length = 0x000080 + + CANA : origin = 0x048000, length = 0x000800 + CANB : origin = 0x04A000, length = 0x000800 + + CLA1 : origin = 0x001400, length = 0x000040 /* CLA registers */ + + CMPSS1 : origin = 0x005C80, length = 0x000020 + CMPSS2 : origin = 0x005CA0, length = 0x000020 + CMPSS3 : origin = 0x005CC0, length = 0x000020 + CMPSS4 : origin = 0x005CE0, length = 0x000020 + CMPSS5 : origin = 0x005D00, length = 0x000020 + CMPSS6 : origin = 0x005D20, length = 0x000020 + CMPSS7 : origin = 0x005D40, length = 0x000020 + CMPSS8 : origin = 0x005D60, length = 0x000020 + + CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers */ + CPU_TIMER1 : origin = 0x000C08, length = 0x000008 /* CPU Timer1 registers */ + CPU_TIMER2 : origin = 0x000C10, length = 0x000008 /* CPU Timer2 registers */ + + DACA : origin = 0x005C00, length = 0x000010 + DACB : origin = 0x005C10, length = 0x000010 + DACC : origin = 0x005C20, length = 0x000010 + + DMA : origin = 0x001000, length = 0x000200 + DMACLASRCSEL : origin = 0x007980, length = 0x000040 + + ECAP1 : origin = 0x005000, length = 0x000020 /* Enhanced Capture 1 registers */ + ECAP2 : origin = 0x005020, length = 0x000020 /* Enhanced Capture 2 registers */ + ECAP3 : origin = 0x005040, length = 0x000020 /* Enhanced Capture 3 registers */ + ECAP4 : origin = 0x005060, length = 0x000020 /* Enhanced Capture 4 registers */ + ECAP5 : origin = 0x005080, length = 0x000020 /* Enhanced Capture 5 registers */ + ECAP6 : origin = 0x0050A0, length = 0x000020 /* Enhanced Capture 6 registers */ + + EMIF1 : origin = 0x047000, length = 0x000800 + EMIF2 : origin = 0x047800, length = 0x000800 + + EQEP1 : origin = 0x005100, length = 0x000040 /* Enhanced QEP 1 registers */ + EQEP2 : origin = 0x005140, length = 0x000040 /* Enhanced QEP 2 registers */ + EQEP3 : origin = 0x005180, length = 0x000040 /* Enhanced QEP 3 registers */ + + EPWM1 : origin = 0x004000, length = 0x000100 /* Enhanced PWM 1 registers */ + EPWM2 : origin = 0x004100, length = 0x000100 /* Enhanced PWM 2 registers */ + EPWM3 : origin = 0x004200, length = 0x000100 /* Enhanced PWM 3 registers */ + EPWM4 : origin = 0x004300, length = 0x000100 /* Enhanced PWM 4 registers */ + EPWM5 : origin = 0x004400, length = 0x000100 /* Enhanced PWM 5 registers */ + EPWM6 : origin = 0x004500, length = 0x000100 /* Enhanced PWM 6 registers */ + EPWM7 : origin = 0x004600, length = 0x000100 /* Enhanced PWM 7 registers */ + EPWM8 : origin = 0x004700, length = 0x000100 /* Enhanced PWM 8 registers */ + EPWM9 : origin = 0x004800, length = 0x000100 /* Enhanced PWM 9 registers */ + EPWM10 : origin = 0x004900, length = 0x000100 /* Enhanced PWM 10 registers */ + EPWM11 : origin = 0x004A00, length = 0x000100 /* Enhanced PWM 11 registers */ + EPWM12 : origin = 0x004B00, length = 0x000100 /* Enhanced PWM 12 registers */ + + FLASH0_CTRL : origin = 0x05F800, length = 0x000300 + FLASH0_ECC : origin = 0x05FB00, length = 0x000040 + + GPIOCTRL : origin = 0x007C00, length = 0x000180 /* GPIO control registers */ + GPIODAT : origin = 0x007F00, length = 0x000030 /* GPIO data registers */ + I2CA : origin = 0x007300, length = 0x000040 /* I2C-A registers */ + I2CB : origin = 0x007340, length = 0x000040 /* I2C-B registers */ + + IPC : origin = 0x050000, length = 0x000024 + + FLASHPUMPSEMAPHORE : origin = 0x050024, length = 0x000002 + + MEMCFG : origin = 0x05F400, length = 0x000080 /* Mem Config registers */ + EMIF1CONFIG : origin = 0x05F480, length = 0x000020 /* Emif-1 Config registers */ + ACCESSPROTECTION : origin = 0x05F4C0, length = 0x000040 /* Access Protection registers */ + MEMORYERROR : origin = 0x05F500, length = 0x000040 /* Access Protection registers */ + + + MCBSPA : origin = 0x006000, length = 0x000040 /* McBSP-A registers */ + MCBSPB : origin = 0x006040, length = 0x000040 /* McBSP-A registers */ + + NMIINTRUPT : origin = 0x007060, length = 0x000010 /* NMI Watchdog Interrupt Registers */ + + PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ + PIE_VECT : origin = 0x000D00, length = 0x000200 /* PIE Vector Table */ + SCIA : origin = 0x007200, length = 0x000010 /* SCI-A registers */ + SCIB : origin = 0x007210, length = 0x000010 /* SCI-B registers */ + SCIC : origin = 0x007220, length = 0x000010 /* SCI-C registers */ + SCID : origin = 0x007230, length = 0x000010 /* SCI-D registers */ + + SDFM1 : origin = 0x005E00, length = 0x000080 /* Sigma delta 1 registers */ + SDFM2 : origin = 0x005E80, length = 0x000080 /* Sigma delta 2 registers */ + + SPIA : origin = 0x006100, length = 0x000010 + SPIB : origin = 0x006110, length = 0x000010 + SPIC : origin = 0x006120, length = 0x000010 + SPID : origin = 0x006130, length = 0x000010 + CLK_CFG : origin = 0x05D200, length = 0x000100 + CPU_SYS : origin = 0x05D300, length = 0x000100 + + WD : origin = 0x007000, length = 0x000040 + + XINT : origin = 0x007070, length = 0x000010 + + DCSM_Z1 : origin = 0x05F000, length = 0x000030 /* Zone 1 Dual code security module registers */ + DCSM_Z2 : origin = 0x05F040, length = 0x000030 /* Zone 2 Dual code security module registers */ + DCSM_COMMON : origin = 0x05F070, length = 0x000010 /* Common Dual code security module registers */ + +} + + +SECTIONS +{ +/*** PIE Vect Table and Boot ROM Variables Structures ***/ + UNION run = PIE_VECT, PAGE = 1 + { + PieVectTableFile + GROUP + { + EmuBModeVar + } + } + + AdcaResultFile : > ADCA_RESULT, PAGE = 1 + AdcbResultFile : > ADCB_RESULT, PAGE = 1 + AdccResultFile : > ADCC_RESULT, PAGE = 1 + AdcdResultFile : > ADCD_RESULT, PAGE = 1 + + AdcaRegsFile : > ADCA, PAGE = 1 + AdcbRegsFile : > ADCB, PAGE = 1 + AdccRegsFile : > ADCC, PAGE = 1 + AdcdRegsFile : > ADCD, PAGE = 1 + + CanaRegsFile : > CANA, PAGE = 1 + CanbRegsFile : > CANB, PAGE = 1 + + Cla1RegsFile : > CLA1, PAGE = 1 + Cla1SoftIntRegsFile : > PIE_CTRL, PAGE = 1, type=DSECT + + Cmpss1RegsFile : > CMPSS1, PAGE = 1 + Cmpss2RegsFile : > CMPSS2, PAGE = 1 + Cmpss3RegsFile : > CMPSS3, PAGE = 1 + Cmpss4RegsFile : > CMPSS4, PAGE = 1 + Cmpss5RegsFile : > CMPSS5, PAGE = 1 + Cmpss6RegsFile : > CMPSS6, PAGE = 1 + Cmpss7RegsFile : > CMPSS7, PAGE = 1 + Cmpss8RegsFile : > CMPSS8, PAGE = 1 + + CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 + CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1 + CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1 + + DacaRegsFile : > DACA PAGE = 1 + DacbRegsFile : > DACB PAGE = 1 + DaccRegsFile : > DACC PAGE = 1 + + DcsmZ1RegsFile : > DCSM_Z1, PAGE = 1 + DcsmZ2RegsFile : > DCSM_Z2, PAGE = 1 + DcsmCommonRegsFile : > DCSM_COMMON, PAGE = 1 + + DmaRegsFile : > DMA PAGE = 1 + DmaClaSrcSelRegsFile : > DMACLASRCSEL PAGE = 1 + + ECap1RegsFile : > ECAP1, PAGE = 1 + ECap2RegsFile : > ECAP2, PAGE = 1 + ECap3RegsFile : > ECAP3, PAGE = 1 + ECap4RegsFile : > ECAP4, PAGE = 1 + ECap5RegsFile : > ECAP5, PAGE = 1 + ECap6RegsFile : > ECAP6, PAGE = 1 + + Emif1RegsFile : > EMIF1 PAGE = 1 + Emif2RegsFile : > EMIF2 PAGE = 1 + + EPwm1RegsFile : > EPWM1, PAGE = 1 + EPwm2RegsFile : > EPWM2, PAGE = 1 + EPwm3RegsFile : > EPWM3, PAGE = 1 + EPwm4RegsFile : > EPWM4, PAGE = 1 + EPwm5RegsFile : > EPWM5, PAGE = 1 + EPwm6RegsFile : > EPWM6, PAGE = 1 + EPwm7RegsFile : > EPWM7, PAGE = 1 + EPwm8RegsFile : > EPWM8, PAGE = 1 + EPwm9RegsFile : > EPWM9, PAGE = 1 + EPwm10RegsFile : > EPWM10, PAGE = 1 + EPwm11RegsFile : > EPWM11, PAGE = 1 + EPwm12RegsFile : > EPWM12, PAGE = 1 + + EQep1RegsFile : > EQEP1, PAGE = 1 + EQep2RegsFile : > EQEP2, PAGE = 1 + EQep3RegsFile : > EQEP3, PAGE = 1 + + Flash0CtrlRegsFile : > FLASH0_CTRL PAGE = 1 + Flash0EccRegsFile : > FLASH0_ECC PAGE = 1 + + GpioCtrlRegsFile : > GPIOCTRL, PAGE = 1 + GpioDataRegsFile : > GPIODAT, PAGE = 1 + + I2caRegsFile : > I2CA, PAGE = 1 + I2cbRegsFile : > I2CB, PAGE = 1 + + IpcRegsFile : > IPC, PAGE = 1 + + FlashPumpSemaphoreRegsFile : > FLASHPUMPSEMAPHORE, PAGE = 1 + + MemCfgRegsFile : > MEMCFG, PAGE = 1 + Emif1ConfigRegsFile : > EMIF1CONFIG, PAGE = 1 + AccessProtectionRegsFile : > ACCESSPROTECTION, PAGE = 1 + MemoryErrorRegsFile : > MEMORYERROR, PAGE = 1 + + McbspaRegsFile : > MCBSPA, PAGE = 1 + McbspbRegsFile : > MCBSPB, PAGE = 1 + + NmiIntruptRegsFile : > NMIINTRUPT, PAGE = 1 + PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 + + SciaRegsFile : > SCIA, PAGE = 1 + ScibRegsFile : > SCIB, PAGE = 1 + ScicRegsFile : > SCIC, PAGE = 1 + ScidRegsFile : > SCID, PAGE = 1 + + Sdfm1RegsFile : > SDFM1, PAGE = 1 + Sdfm2RegsFile : > SDFM2, PAGE = 1 + + SpiaRegsFile : > SPIA, PAGE = 1 + SpibRegsFile : > SPIB, PAGE = 1 + SpicRegsFile : > SPIC, PAGE = 1 + SpidRegsFile : > SPID, PAGE = 1 + + ClkCfgRegsFile : > CLK_CFG, PAGE = 1 + CpuSysRegsFile : > CPU_SYS, PAGE = 1 + + WdRegsFile : > WD, PAGE = 1 + + XintRegsFile : > XINT PAGE = 1 + MemCfgRegs : > MEMCFG PAGE = 1 + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_adc.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_adc.h new file mode 100644 index 0000000000..cdcee353fb --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_adc.h @@ -0,0 +1,1067 @@ +//########################################################################### +// +// FILE: F2837xD_adc.h +// +// TITLE: ADC Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_ADC_H__ +#define __F2837xD_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// ADC Individual Register Bit Definitions: + +struct ADCCTL1_BITS { // bits description + Uint16 rsvd1:2; // 1:0 Reserved + Uint16 INTPULSEPOS:1; // 2 ADC Interrupt Pulse Position + Uint16 rsvd2:4; // 6:3 Reserved + Uint16 ADCPWDNZ:1; // 7 ADC Power Down + Uint16 ADCBSYCHN:4; // 11:8 ADC Busy Channel + Uint16 rsvd3:1; // 12 Reserved + Uint16 ADCBSY:1; // 13 ADC Busy + Uint16 rsvd4:2; // 15:14 Reserved +}; + +union ADCCTL1_REG { + Uint16 all; + struct ADCCTL1_BITS bit; +}; + +struct ADCCTL2_BITS { // bits description + Uint16 PRESCALE:4; // 3:0 ADC Clock Prescaler + Uint16 rsvd1:2; // 5:4 Reserved + Uint16 RESOLUTION:1; // 6 SOC Conversion Resolution + Uint16 SIGNALMODE:1; // 7 SOC Signaling Mode + Uint16 rsvd2:5; // 12:8 Reserved + Uint16 rsvd3:3; // 15:13 Reserved +}; + +union ADCCTL2_REG { + Uint16 all; + struct ADCCTL2_BITS bit; +}; + +struct ADCBURSTCTL_BITS { // bits description + Uint16 BURSTTRIGSEL:6; // 5:0 SOC Burst Trigger Source Select + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 BURSTSIZE:4; // 11:8 SOC Burst Size Select + Uint16 rsvd2:3; // 14:12 Reserved + Uint16 BURSTEN:1; // 15 SOC Burst Mode Enable +}; + +union ADCBURSTCTL_REG { + Uint16 all; + struct ADCBURSTCTL_BITS bit; +}; + +struct ADCINTFLG_BITS { // bits description + Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag + Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag + Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag + Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union ADCINTFLG_REG { + Uint16 all; + struct ADCINTFLG_BITS bit; +}; + +struct ADCINTFLGCLR_BITS { // bits description + Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Flag Clear + Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Flag Clear + Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Flag Clear + Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Flag Clear + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union ADCINTFLGCLR_REG { + Uint16 all; + struct ADCINTFLGCLR_BITS bit; +}; + +struct ADCINTOVF_BITS { // bits description + Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Flags + Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Flags + Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Flags + Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Flags + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union ADCINTOVF_REG { + Uint16 all; + struct ADCINTOVF_BITS bit; +}; + +struct ADCINTOVFCLR_BITS { // bits description + Uint16 ADCINT1:1; // 0 ADC Interrupt 1 Overflow Clear Bits + Uint16 ADCINT2:1; // 1 ADC Interrupt 2 Overflow Clear Bits + Uint16 ADCINT3:1; // 2 ADC Interrupt 3 Overflow Clear Bits + Uint16 ADCINT4:1; // 3 ADC Interrupt 4 Overflow Clear Bits + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union ADCINTOVFCLR_REG { + Uint16 all; + struct ADCINTOVFCLR_BITS bit; +}; + +struct ADCINTSEL1N2_BITS { // bits description + Uint16 INT1SEL:4; // 3:0 ADCINT1 EOC Source Select + Uint16 rsvd1:1; // 4 Reserved + Uint16 INT1E:1; // 5 ADCINT1 Interrupt Enable + Uint16 INT1CONT:1; // 6 ADCINT1 Continuous Mode Enable + Uint16 rsvd2:1; // 7 Reserved + Uint16 INT2SEL:4; // 11:8 ADCINT2 EOC Source Select + Uint16 rsvd3:1; // 12 Reserved + Uint16 INT2E:1; // 13 ADCINT2 Interrupt Enable + Uint16 INT2CONT:1; // 14 ADCINT2 Continuous Mode Enable + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCINTSEL1N2_REG { + Uint16 all; + struct ADCINTSEL1N2_BITS bit; +}; + +struct ADCINTSEL3N4_BITS { // bits description + Uint16 INT3SEL:4; // 3:0 ADCINT3 EOC Source Select + Uint16 rsvd1:1; // 4 Reserved + Uint16 INT3E:1; // 5 ADCINT3 Interrupt Enable + Uint16 INT3CONT:1; // 6 ADCINT3 Continuous Mode Enable + Uint16 rsvd2:1; // 7 Reserved + Uint16 INT4SEL:4; // 11:8 ADCINT4 EOC Source Select + Uint16 rsvd3:1; // 12 Reserved + Uint16 INT4E:1; // 13 ADCINT4 Interrupt Enable + Uint16 INT4CONT:1; // 14 ADCINT4 Continuous Mode Enable + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCINTSEL3N4_REG { + Uint16 all; + struct ADCINTSEL3N4_BITS bit; +}; + +struct ADCSOCPRICTL_BITS { // bits description + Uint16 SOCPRIORITY:5; // 4:0 SOC Priority + Uint16 RRPOINTER:5; // 9:5 Round Robin Pointer + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union ADCSOCPRICTL_REG { + Uint16 all; + struct ADCSOCPRICTL_BITS bit; +}; + +struct ADCINTSOCSEL1_BITS { // bits description + Uint16 SOC0:2; // 1:0 SOC0 ADC Interrupt Trigger Select + Uint16 SOC1:2; // 3:2 SOC1 ADC Interrupt Trigger Select + Uint16 SOC2:2; // 5:4 SOC2 ADC Interrupt Trigger Select + Uint16 SOC3:2; // 7:6 SOC3 ADC Interrupt Trigger Select + Uint16 SOC4:2; // 9:8 SOC4 ADC Interrupt Trigger Select + Uint16 SOC5:2; // 11:10 SOC5 ADC Interrupt Trigger Select + Uint16 SOC6:2; // 13:12 SOC6 ADC Interrupt Trigger Select + Uint16 SOC7:2; // 15:14 SOC7 ADC Interrupt Trigger Select +}; + +union ADCINTSOCSEL1_REG { + Uint16 all; + struct ADCINTSOCSEL1_BITS bit; +}; + +struct ADCINTSOCSEL2_BITS { // bits description + Uint16 SOC8:2; // 1:0 SOC8 ADC Interrupt Trigger Select + Uint16 SOC9:2; // 3:2 SOC9 ADC Interrupt Trigger Select + Uint16 SOC10:2; // 5:4 SOC10 ADC Interrupt Trigger Select + Uint16 SOC11:2; // 7:6 SOC11 ADC Interrupt Trigger Select + Uint16 SOC12:2; // 9:8 SOC12 ADC Interrupt Trigger Select + Uint16 SOC13:2; // 11:10 SOC13 ADC Interrupt Trigger Select + Uint16 SOC14:2; // 13:12 SOC14 ADC Interrupt Trigger Select + Uint16 SOC15:2; // 15:14 SOC15 ADC Interrupt Trigger Select +}; + +union ADCINTSOCSEL2_REG { + Uint16 all; + struct ADCINTSOCSEL2_BITS bit; +}; + +struct ADCSOCFLG1_BITS { // bits description + Uint16 SOC0:1; // 0 SOC0 Start of Conversion Flag + Uint16 SOC1:1; // 1 SOC1 Start of Conversion Flag + Uint16 SOC2:1; // 2 SOC2 Start of Conversion Flag + Uint16 SOC3:1; // 3 SOC3 Start of Conversion Flag + Uint16 SOC4:1; // 4 SOC4 Start of Conversion Flag + Uint16 SOC5:1; // 5 SOC5 Start of Conversion Flag + Uint16 SOC6:1; // 6 SOC6 Start of Conversion Flag + Uint16 SOC7:1; // 7 SOC7 Start of Conversion Flag + Uint16 SOC8:1; // 8 SOC8 Start of Conversion Flag + Uint16 SOC9:1; // 9 SOC9 Start of Conversion Flag + Uint16 SOC10:1; // 10 SOC10 Start of Conversion Flag + Uint16 SOC11:1; // 11 SOC11 Start of Conversion Flag + Uint16 SOC12:1; // 12 SOC12 Start of Conversion Flag + Uint16 SOC13:1; // 13 SOC13 Start of Conversion Flag + Uint16 SOC14:1; // 14 SOC14 Start of Conversion Flag + Uint16 SOC15:1; // 15 SOC15 Start of Conversion Flag +}; + +union ADCSOCFLG1_REG { + Uint16 all; + struct ADCSOCFLG1_BITS bit; +}; + +struct ADCSOCFRC1_BITS { // bits description + Uint16 SOC0:1; // 0 SOC0 Force Start of Conversion Bit + Uint16 SOC1:1; // 1 SOC1 Force Start of Conversion Bit + Uint16 SOC2:1; // 2 SOC2 Force Start of Conversion Bit + Uint16 SOC3:1; // 3 SOC3 Force Start of Conversion Bit + Uint16 SOC4:1; // 4 SOC4 Force Start of Conversion Bit + Uint16 SOC5:1; // 5 SOC5 Force Start of Conversion Bit + Uint16 SOC6:1; // 6 SOC6 Force Start of Conversion Bit + Uint16 SOC7:1; // 7 SOC7 Force Start of Conversion Bit + Uint16 SOC8:1; // 8 SOC8 Force Start of Conversion Bit + Uint16 SOC9:1; // 9 SOC9 Force Start of Conversion Bit + Uint16 SOC10:1; // 10 SOC10 Force Start of Conversion Bit + Uint16 SOC11:1; // 11 SOC11 Force Start of Conversion Bit + Uint16 SOC12:1; // 12 SOC12 Force Start of Conversion Bit + Uint16 SOC13:1; // 13 SOC13 Force Start of Conversion Bit + Uint16 SOC14:1; // 14 SOC14 Force Start of Conversion Bit + Uint16 SOC15:1; // 15 SOC15 Force Start of Conversion Bit +}; + +union ADCSOCFRC1_REG { + Uint16 all; + struct ADCSOCFRC1_BITS bit; +}; + +struct ADCSOCOVF1_BITS { // bits description + Uint16 SOC0:1; // 0 SOC0 Start of Conversion Overflow Flag + Uint16 SOC1:1; // 1 SOC1 Start of Conversion Overflow Flag + Uint16 SOC2:1; // 2 SOC2 Start of Conversion Overflow Flag + Uint16 SOC3:1; // 3 SOC3 Start of Conversion Overflow Flag + Uint16 SOC4:1; // 4 SOC4 Start of Conversion Overflow Flag + Uint16 SOC5:1; // 5 SOC5 Start of Conversion Overflow Flag + Uint16 SOC6:1; // 6 SOC6 Start of Conversion Overflow Flag + Uint16 SOC7:1; // 7 SOC7 Start of Conversion Overflow Flag + Uint16 SOC8:1; // 8 SOC8 Start of Conversion Overflow Flag + Uint16 SOC9:1; // 9 SOC9 Start of Conversion Overflow Flag + Uint16 SOC10:1; // 10 SOC10 Start of Conversion Overflow Flag + Uint16 SOC11:1; // 11 SOC11 Start of Conversion Overflow Flag + Uint16 SOC12:1; // 12 SOC12 Start of Conversion Overflow Flag + Uint16 SOC13:1; // 13 SOC13 Start of Conversion Overflow Flag + Uint16 SOC14:1; // 14 SOC14 Start of Conversion Overflow Flag + Uint16 SOC15:1; // 15 SOC15 Start of Conversion Overflow Flag +}; + +union ADCSOCOVF1_REG { + Uint16 all; + struct ADCSOCOVF1_BITS bit; +}; + +struct ADCSOCOVFCLR1_BITS { // bits description + Uint16 SOC0:1; // 0 SOC0 Clear Start of Conversion Overflow Bit + Uint16 SOC1:1; // 1 SOC1 Clear Start of Conversion Overflow Bit + Uint16 SOC2:1; // 2 SOC2 Clear Start of Conversion Overflow Bit + Uint16 SOC3:1; // 3 SOC3 Clear Start of Conversion Overflow Bit + Uint16 SOC4:1; // 4 SOC4 Clear Start of Conversion Overflow Bit + Uint16 SOC5:1; // 5 SOC5 Clear Start of Conversion Overflow Bit + Uint16 SOC6:1; // 6 SOC6 Clear Start of Conversion Overflow Bit + Uint16 SOC7:1; // 7 SOC7 Clear Start of Conversion Overflow Bit + Uint16 SOC8:1; // 8 SOC8 Clear Start of Conversion Overflow Bit + Uint16 SOC9:1; // 9 SOC9 Clear Start of Conversion Overflow Bit + Uint16 SOC10:1; // 10 SOC10 Clear Start of Conversion Overflow Bit + Uint16 SOC11:1; // 11 SOC11 Clear Start of Conversion Overflow Bit + Uint16 SOC12:1; // 12 SOC12 Clear Start of Conversion Overflow Bit + Uint16 SOC13:1; // 13 SOC13 Clear Start of Conversion Overflow Bit + Uint16 SOC14:1; // 14 SOC14 Clear Start of Conversion Overflow Bit + Uint16 SOC15:1; // 15 SOC15 Clear Start of Conversion Overflow Bit +}; + +union ADCSOCOVFCLR1_REG { + Uint16 all; + struct ADCSOCOVFCLR1_BITS bit; +}; + +struct ADCSOC0CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC0 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC0 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC0 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC0CTL_REG { + Uint32 all; + struct ADCSOC0CTL_BITS bit; +}; + +struct ADCSOC1CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC1 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC1 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC1 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC1CTL_REG { + Uint32 all; + struct ADCSOC1CTL_BITS bit; +}; + +struct ADCSOC2CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC2 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC2 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC2 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC2CTL_REG { + Uint32 all; + struct ADCSOC2CTL_BITS bit; +}; + +struct ADCSOC3CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC3 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC3 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC3 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC3CTL_REG { + Uint32 all; + struct ADCSOC3CTL_BITS bit; +}; + +struct ADCSOC4CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC4 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC4 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC4 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC4CTL_REG { + Uint32 all; + struct ADCSOC4CTL_BITS bit; +}; + +struct ADCSOC5CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC5 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC5 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC5 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC5CTL_REG { + Uint32 all; + struct ADCSOC5CTL_BITS bit; +}; + +struct ADCSOC6CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC6 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC6 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC6 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC6CTL_REG { + Uint32 all; + struct ADCSOC6CTL_BITS bit; +}; + +struct ADCSOC7CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC7 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC7 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC7 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC7CTL_REG { + Uint32 all; + struct ADCSOC7CTL_BITS bit; +}; + +struct ADCSOC8CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC8 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC8 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC8 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC8CTL_REG { + Uint32 all; + struct ADCSOC8CTL_BITS bit; +}; + +struct ADCSOC9CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC9 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC9 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC9 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC9CTL_REG { + Uint32 all; + struct ADCSOC9CTL_BITS bit; +}; + +struct ADCSOC10CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC10 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC10 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC10 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC10CTL_REG { + Uint32 all; + struct ADCSOC10CTL_BITS bit; +}; + +struct ADCSOC11CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC11 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC11 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC11 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC11CTL_REG { + Uint32 all; + struct ADCSOC11CTL_BITS bit; +}; + +struct ADCSOC12CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC12 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC12 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC12 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC12CTL_REG { + Uint32 all; + struct ADCSOC12CTL_BITS bit; +}; + +struct ADCSOC13CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC13 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC13 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC13 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC13CTL_REG { + Uint32 all; + struct ADCSOC13CTL_BITS bit; +}; + +struct ADCSOC14CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC14 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC14 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC14 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC14CTL_REG { + Uint32 all; + struct ADCSOC14CTL_BITS bit; +}; + +struct ADCSOC15CTL_BITS { // bits description + Uint16 ACQPS:9; // 8:0 SOC15 Acquisition Prescale + Uint16 rsvd1:6; // 14:9 Reserved + Uint32 CHSEL:4; // 18:15 SOC15 Channel Select + Uint16 rsvd2:1; // 19 Reserved + Uint16 TRIGSEL:5; // 24:20 SOC15 Trigger Source Select + Uint16 rsvd3:7; // 31:25 Reserved +}; + +union ADCSOC15CTL_REG { + Uint32 all; + struct ADCSOC15CTL_BITS bit; +}; + +struct ADCEVTSTAT_BITS { // bits description + Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Flag + Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Flag + Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Flag + Uint16 rsvd1:1; // 3 Reserved + Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Flag + Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Flag + Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Flag + Uint16 rsvd2:1; // 7 Reserved + Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Flag + Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Flag + Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Flag + Uint16 rsvd3:1; // 11 Reserved + Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Flag + Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Flag + Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Flag + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCEVTSTAT_REG { + Uint16 all; + struct ADCEVTSTAT_BITS bit; +}; + +struct ADCEVTCLR_BITS { // bits description + Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Clear + Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Clear + Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Clear + Uint16 rsvd1:1; // 3 Reserved + Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Clear + Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Clear + Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Clear + Uint16 rsvd2:1; // 7 Reserved + Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Clear + Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Clear + Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Clear + Uint16 rsvd3:1; // 11 Reserved + Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Clear + Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Clear + Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Clear + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCEVTCLR_REG { + Uint16 all; + struct ADCEVTCLR_BITS bit; +}; + +struct ADCEVTSEL_BITS { // bits description + Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Event Enable + Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Event Enable + Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Event Enable + Uint16 rsvd1:1; // 3 Reserved + Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Event Enable + Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Event Enable + Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Event Enable + Uint16 rsvd2:1; // 7 Reserved + Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Event Enable + Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Event Enable + Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Event Enable + Uint16 rsvd3:1; // 11 Reserved + Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Event Enable + Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Event Enable + Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Event Enable + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCEVTSEL_REG { + Uint16 all; + struct ADCEVTSEL_BITS bit; +}; + +struct ADCEVTINTSEL_BITS { // bits description + Uint16 PPB1TRIPHI:1; // 0 Post Processing Block 1 Trip High Interrupt Enable + Uint16 PPB1TRIPLO:1; // 1 Post Processing Block 1 Trip Low Interrupt Enable + Uint16 PPB1ZERO:1; // 2 Post Processing Block 1 Zero Crossing Interrupt Enable + Uint16 rsvd1:1; // 3 Reserved + Uint16 PPB2TRIPHI:1; // 4 Post Processing Block 2 Trip High Interrupt Enable + Uint16 PPB2TRIPLO:1; // 5 Post Processing Block 2 Trip Low Interrupt Enable + Uint16 PPB2ZERO:1; // 6 Post Processing Block 2 Zero Crossing Interrupt Enable + Uint16 rsvd2:1; // 7 Reserved + Uint16 PPB3TRIPHI:1; // 8 Post Processing Block 3 Trip High Interrupt Enable + Uint16 PPB3TRIPLO:1; // 9 Post Processing Block 3 Trip Low Interrupt Enable + Uint16 PPB3ZERO:1; // 10 Post Processing Block 3 Zero Crossing Interrupt Enable + Uint16 rsvd3:1; // 11 Reserved + Uint16 PPB4TRIPHI:1; // 12 Post Processing Block 4 Trip High Interrupt Enable + Uint16 PPB4TRIPLO:1; // 13 Post Processing Block 4 Trip Low Interrupt Enable + Uint16 PPB4ZERO:1; // 14 Post Processing Block 4 Zero Crossing Interrupt Enable + Uint16 rsvd4:1; // 15 Reserved +}; + +union ADCEVTINTSEL_REG { + Uint16 all; + struct ADCEVTINTSEL_BITS bit; +}; + +struct ADCCOUNTER_BITS { // bits description + Uint16 FREECOUNT:12; // 11:0 ADC Free Running Counter Value + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ADCCOUNTER_REG { + Uint16 all; + struct ADCCOUNTER_BITS bit; +}; + +struct ADCREV_BITS { // bits description + Uint16 TYPE:8; // 7:0 ADC Type + Uint16 REV:8; // 15:8 ADC Revision +}; + +union ADCREV_REG { + Uint16 all; + struct ADCREV_BITS bit; +}; + +struct ADCOFFTRIM_BITS { // bits description + Uint16 OFFTRIM:8; // 7:0 ADC Offset Trim + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union ADCOFFTRIM_REG { + Uint16 all; + struct ADCOFFTRIM_BITS bit; +}; + +struct ADCPPB1CONFIG_BITS { // bits description + Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 1 Configuration + Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 1 Two's Complement Enable + Uint16 rsvd1:1; // 5 Reserved + Uint16 rsvd2:10; // 15:6 Reserved +}; + +union ADCPPB1CONFIG_REG { + Uint16 all; + struct ADCPPB1CONFIG_BITS bit; +}; + +struct ADCPPB1STAMP_BITS { // bits description + Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 1 Delay Time Stamp + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ADCPPB1STAMP_REG { + Uint16 all; + struct ADCPPB1STAMP_BITS bit; +}; + +struct ADCPPB1OFFCAL_BITS { // bits description + Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union ADCPPB1OFFCAL_REG { + Uint16 all; + struct ADCPPB1OFFCAL_BITS bit; +}; + +struct ADCPPB1TRIPHI_BITS { // bits description + Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 1 Trip High Limit + Uint16 HSIGN:1; // 16 High Limit Sign Bit + Uint16 rsvd1:15; // 31:17 Reserved +}; + +union ADCPPB1TRIPHI_REG { + Uint32 all; + struct ADCPPB1TRIPHI_BITS bit; +}; + +struct ADCPPB1TRIPLO_BITS { // bits description + Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 1 Trip Low Limit + Uint16 LSIGN:1; // 16 Low Limit Sign Bit + Uint16 rsvd1:3; // 19:17 Reserved + Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 1 Request Time Stamp +}; + +union ADCPPB1TRIPLO_REG { + Uint32 all; + struct ADCPPB1TRIPLO_BITS bit; +}; + +struct ADCPPB2CONFIG_BITS { // bits description + Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 2 Configuration + Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 2 Two's Complement Enable + Uint16 rsvd1:1; // 5 Reserved + Uint16 rsvd2:10; // 15:6 Reserved +}; + +union ADCPPB2CONFIG_REG { + Uint16 all; + struct ADCPPB2CONFIG_BITS bit; +}; + +struct ADCPPB2STAMP_BITS { // bits description + Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 2 Delay Time Stamp + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ADCPPB2STAMP_REG { + Uint16 all; + struct ADCPPB2STAMP_BITS bit; +}; + +struct ADCPPB2OFFCAL_BITS { // bits description + Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union ADCPPB2OFFCAL_REG { + Uint16 all; + struct ADCPPB2OFFCAL_BITS bit; +}; + +struct ADCPPB2TRIPHI_BITS { // bits description + Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 2 Trip High Limit + Uint16 HSIGN:1; // 16 High Limit Sign Bit + Uint16 rsvd1:15; // 31:17 Reserved +}; + +union ADCPPB2TRIPHI_REG { + Uint32 all; + struct ADCPPB2TRIPHI_BITS bit; +}; + +struct ADCPPB2TRIPLO_BITS { // bits description + Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 2 Trip Low Limit + Uint16 LSIGN:1; // 16 Low Limit Sign Bit + Uint16 rsvd1:3; // 19:17 Reserved + Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 2 Request Time Stamp +}; + +union ADCPPB2TRIPLO_REG { + Uint32 all; + struct ADCPPB2TRIPLO_BITS bit; +}; + +struct ADCPPB3CONFIG_BITS { // bits description + Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 3 Configuration + Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 3 Two's Complement Enable + Uint16 rsvd1:1; // 5 Reserved + Uint16 rsvd2:10; // 15:6 Reserved +}; + +union ADCPPB3CONFIG_REG { + Uint16 all; + struct ADCPPB3CONFIG_BITS bit; +}; + +struct ADCPPB3STAMP_BITS { // bits description + Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 3 Delay Time Stamp + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ADCPPB3STAMP_REG { + Uint16 all; + struct ADCPPB3STAMP_BITS bit; +}; + +struct ADCPPB3OFFCAL_BITS { // bits description + Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union ADCPPB3OFFCAL_REG { + Uint16 all; + struct ADCPPB3OFFCAL_BITS bit; +}; + +struct ADCPPB3TRIPHI_BITS { // bits description + Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 3 Trip High Limit + Uint16 HSIGN:1; // 16 High Limit Sign Bit + Uint16 rsvd1:15; // 31:17 Reserved +}; + +union ADCPPB3TRIPHI_REG { + Uint32 all; + struct ADCPPB3TRIPHI_BITS bit; +}; + +struct ADCPPB3TRIPLO_BITS { // bits description + Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 3 Trip Low Limit + Uint16 LSIGN:1; // 16 Low Limit Sign Bit + Uint16 rsvd1:3; // 19:17 Reserved + Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 3 Request Time Stamp +}; + +union ADCPPB3TRIPLO_REG { + Uint32 all; + struct ADCPPB3TRIPLO_BITS bit; +}; + +struct ADCPPB4CONFIG_BITS { // bits description + Uint16 CONFIG:4; // 3:0 ADC Post Processing Block 4 Configuration + Uint16 TWOSCOMPEN:1; // 4 ADC Post Processing Block 4 Two's Complement Enable + Uint16 rsvd1:1; // 5 Reserved + Uint16 rsvd2:10; // 15:6 Reserved +}; + +union ADCPPB4CONFIG_REG { + Uint16 all; + struct ADCPPB4CONFIG_BITS bit; +}; + +struct ADCPPB4STAMP_BITS { // bits description + Uint16 DLYSTAMP:12; // 11:0 ADC Post Processing Block 4 Delay Time Stamp + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ADCPPB4STAMP_REG { + Uint16 all; + struct ADCPPB4STAMP_BITS bit; +}; + +struct ADCPPB4OFFCAL_BITS { // bits description + Uint16 OFFCAL:10; // 9:0 ADC Post Processing Block Offset Correction + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union ADCPPB4OFFCAL_REG { + Uint16 all; + struct ADCPPB4OFFCAL_BITS bit; +}; + +struct ADCPPB4TRIPHI_BITS { // bits description + Uint16 LIMITHI:16; // 15:0 ADC Post Processing Block 4 Trip High Limit + Uint16 HSIGN:1; // 16 High Limit Sign Bit + Uint16 rsvd1:15; // 31:17 Reserved +}; + +union ADCPPB4TRIPHI_REG { + Uint32 all; + struct ADCPPB4TRIPHI_BITS bit; +}; + +struct ADCPPB4TRIPLO_BITS { // bits description + Uint16 LIMITLO:16; // 15:0 ADC Post Processing Block 4 Trip Low Limit + Uint16 LSIGN:1; // 16 Low Limit Sign Bit + Uint16 rsvd1:3; // 19:17 Reserved + Uint16 REQSTAMP:12; // 31:20 ADC Post Processing Block 4 Request Time Stamp +}; + +union ADCPPB4TRIPLO_REG { + Uint32 all; + struct ADCPPB4TRIPLO_BITS bit; +}; + +struct ADC_REGS { + union ADCCTL1_REG ADCCTL1; // ADC Control 1 Register + union ADCCTL2_REG ADCCTL2; // ADC Control 2 Register + union ADCBURSTCTL_REG ADCBURSTCTL; // ADC Burst Control Register + union ADCINTFLG_REG ADCINTFLG; // ADC Interrupt Flag Register + union ADCINTFLGCLR_REG ADCINTFLGCLR; // ADC Interrupt Flag Clear Register + union ADCINTOVF_REG ADCINTOVF; // ADC Interrupt Overflow Register + union ADCINTOVFCLR_REG ADCINTOVFCLR; // ADC Interrupt Overflow Clear Register + union ADCINTSEL1N2_REG ADCINTSEL1N2; // ADC Interrupt 1 and 2 Selection Register + union ADCINTSEL3N4_REG ADCINTSEL3N4; // ADC Interrupt 3 and 4 Selection Register + union ADCSOCPRICTL_REG ADCSOCPRICTL; // ADC SOC Priority Control Register + union ADCINTSOCSEL1_REG ADCINTSOCSEL1; // ADC Interrupt SOC Selection 1 Register + union ADCINTSOCSEL2_REG ADCINTSOCSEL2; // ADC Interrupt SOC Selection 2 Register + union ADCSOCFLG1_REG ADCSOCFLG1; // ADC SOC Flag 1 Register + union ADCSOCFRC1_REG ADCSOCFRC1; // ADC SOC Force 1 Register + union ADCSOCOVF1_REG ADCSOCOVF1; // ADC SOC Overflow 1 Register + union ADCSOCOVFCLR1_REG ADCSOCOVFCLR1; // ADC SOC Overflow Clear 1 Register + union ADCSOC0CTL_REG ADCSOC0CTL; // ADC SOC0 Control Register + union ADCSOC1CTL_REG ADCSOC1CTL; // ADC SOC1 Control Register + union ADCSOC2CTL_REG ADCSOC2CTL; // ADC SOC2 Control Register + union ADCSOC3CTL_REG ADCSOC3CTL; // ADC SOC3 Control Register + union ADCSOC4CTL_REG ADCSOC4CTL; // ADC SOC4 Control Register + union ADCSOC5CTL_REG ADCSOC5CTL; // ADC SOC5 Control Register + union ADCSOC6CTL_REG ADCSOC6CTL; // ADC SOC6 Control Register + union ADCSOC7CTL_REG ADCSOC7CTL; // ADC SOC7 Control Register + union ADCSOC8CTL_REG ADCSOC8CTL; // ADC SOC8 Control Register + union ADCSOC9CTL_REG ADCSOC9CTL; // ADC SOC9 Control Register + union ADCSOC10CTL_REG ADCSOC10CTL; // ADC SOC10 Control Register + union ADCSOC11CTL_REG ADCSOC11CTL; // ADC SOC11 Control Register + union ADCSOC12CTL_REG ADCSOC12CTL; // ADC SOC12 Control Register + union ADCSOC13CTL_REG ADCSOC13CTL; // ADC SOC13 Control Register + union ADCSOC14CTL_REG ADCSOC14CTL; // ADC SOC14 Control Register + union ADCSOC15CTL_REG ADCSOC15CTL; // ADC SOC15 Control Register + union ADCEVTSTAT_REG ADCEVTSTAT; // ADC Event Status Register + Uint16 rsvd1; // Reserved + union ADCEVTCLR_REG ADCEVTCLR; // ADC Event Clear Register + Uint16 rsvd2; // Reserved + union ADCEVTSEL_REG ADCEVTSEL; // ADC Event Selection Register + Uint16 rsvd3; // Reserved + union ADCEVTINTSEL_REG ADCEVTINTSEL; // ADC Event Interrupt Selection Register + Uint16 rsvd4[2]; // Reserved + union ADCCOUNTER_REG ADCCOUNTER; // ADC Counter Register + union ADCREV_REG ADCREV; // ADC Revision Register + union ADCOFFTRIM_REG ADCOFFTRIM; // ADC Offset Trim Register + Uint16 rsvd5[4]; // Reserved + union ADCPPB1CONFIG_REG ADCPPB1CONFIG; // ADC PPB1 Config Register + union ADCPPB1STAMP_REG ADCPPB1STAMP; // ADC PPB1 Sample Delay Time Stamp Register + union ADCPPB1OFFCAL_REG ADCPPB1OFFCAL; // ADC PPB1 Offset Calibration Register + Uint16 ADCPPB1OFFREF; // ADC PPB1 Offset Reference Register + union ADCPPB1TRIPHI_REG ADCPPB1TRIPHI; // ADC PPB1 Trip High Register + union ADCPPB1TRIPLO_REG ADCPPB1TRIPLO; // ADC PPB1 Trip Low/Trigger Time Stamp Register + union ADCPPB2CONFIG_REG ADCPPB2CONFIG; // ADC PPB2 Config Register + union ADCPPB2STAMP_REG ADCPPB2STAMP; // ADC PPB2 Sample Delay Time Stamp Register + union ADCPPB2OFFCAL_REG ADCPPB2OFFCAL; // ADC PPB2 Offset Calibration Register + Uint16 ADCPPB2OFFREF; // ADC PPB2 Offset Reference Register + union ADCPPB2TRIPHI_REG ADCPPB2TRIPHI; // ADC PPB2 Trip High Register + union ADCPPB2TRIPLO_REG ADCPPB2TRIPLO; // ADC PPB2 Trip Low/Trigger Time Stamp Register + union ADCPPB3CONFIG_REG ADCPPB3CONFIG; // ADC PPB3 Config Register + union ADCPPB3STAMP_REG ADCPPB3STAMP; // ADC PPB3 Sample Delay Time Stamp Register + union ADCPPB3OFFCAL_REG ADCPPB3OFFCAL; // ADC PPB3 Offset Calibration Register + Uint16 ADCPPB3OFFREF; // ADC PPB3 Offset Reference Register + union ADCPPB3TRIPHI_REG ADCPPB3TRIPHI; // ADC PPB3 Trip High Register + union ADCPPB3TRIPLO_REG ADCPPB3TRIPLO; // ADC PPB3 Trip Low/Trigger Time Stamp Register + union ADCPPB4CONFIG_REG ADCPPB4CONFIG; // ADC PPB4 Config Register + union ADCPPB4STAMP_REG ADCPPB4STAMP; // ADC PPB4 Sample Delay Time Stamp Register + union ADCPPB4OFFCAL_REG ADCPPB4OFFCAL; // ADC PPB4 Offset Calibration Register + Uint16 ADCPPB4OFFREF; // ADC PPB4 Offset Reference Register + union ADCPPB4TRIPHI_REG ADCPPB4TRIPHI; // ADC PPB4 Trip High Register + union ADCPPB4TRIPLO_REG ADCPPB4TRIPLO; // ADC PPB4 Trip Low/Trigger Time Stamp Register + Uint16 rsvd6[16]; // Reserved + Uint32 ADCINLTRIM1; // ADC Linearity Trim 1 Register + Uint32 ADCINLTRIM2; // ADC Linearity Trim 2 Register + Uint32 ADCINLTRIM3; // ADC Linearity Trim 3 Register + Uint32 ADCINLTRIM4; // ADC Linearity Trim 4 Register + Uint32 ADCINLTRIM5; // ADC Linearity Trim 5 Register + Uint32 ADCINLTRIM6; // ADC Linearity Trim 6 Register + Uint16 rsvd7[4]; // Reserved +}; + +struct ADCPPB1RESULT_BITS { // bits description + Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result + Uint16 SIGN:16; // 31:16 Sign Extended Bits +}; + +union ADCPPB1RESULT_REG { + Uint32 all; + struct ADCPPB1RESULT_BITS bit; +}; + +struct ADCPPB2RESULT_BITS { // bits description + Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result + Uint16 SIGN:16; // 31:16 Sign Extended Bits +}; + +union ADCPPB2RESULT_REG { + Uint32 all; + struct ADCPPB2RESULT_BITS bit; +}; + +struct ADCPPB3RESULT_BITS { // bits description + Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result + Uint16 SIGN:16; // 31:16 Sign Extended Bits +}; + +union ADCPPB3RESULT_REG { + Uint32 all; + struct ADCPPB3RESULT_BITS bit; +}; + +struct ADCPPB4RESULT_BITS { // bits description + Uint16 PPBRESULT:16; // 15:0 ADC Post Processing Block Result + Uint16 SIGN:16; // 31:16 Sign Extended Bits +}; + +union ADCPPB4RESULT_REG { + Uint32 all; + struct ADCPPB4RESULT_BITS bit; +}; + +struct ADC_RESULT_REGS { + Uint16 ADCRESULT0; // ADC Result 0 Register + Uint16 ADCRESULT1; // ADC Result 1 Register + Uint16 ADCRESULT2; // ADC Result 2 Register + Uint16 ADCRESULT3; // ADC Result 3 Register + Uint16 ADCRESULT4; // ADC Result 4 Register + Uint16 ADCRESULT5; // ADC Result 5 Register + Uint16 ADCRESULT6; // ADC Result 6 Register + Uint16 ADCRESULT7; // ADC Result 7 Register + Uint16 ADCRESULT8; // ADC Result 8 Register + Uint16 ADCRESULT9; // ADC Result 9 Register + Uint16 ADCRESULT10; // ADC Result 10 Register + Uint16 ADCRESULT11; // ADC Result 11 Register + Uint16 ADCRESULT12; // ADC Result 12 Register + Uint16 ADCRESULT13; // ADC Result 13 Register + Uint16 ADCRESULT14; // ADC Result 14 Register + Uint16 ADCRESULT15; // ADC Result 15 Register + union ADCPPB1RESULT_REG ADCPPB1RESULT; // ADC Post Processing Block 1 Result Register + union ADCPPB2RESULT_REG ADCPPB2RESULT; // ADC Post Processing Block 2 Result Register + union ADCPPB3RESULT_REG ADCPPB3RESULT; // ADC Post Processing Block 3 Result Register + union ADCPPB4RESULT_REG ADCPPB4RESULT; // ADC Post Processing Block 4 Result Register +}; + +//--------------------------------------------------------------------------- +// ADC External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct ADC_RESULT_REGS AdcaResultRegs; +extern volatile struct ADC_RESULT_REGS AdcbResultRegs; +extern volatile struct ADC_RESULT_REGS AdccResultRegs; +extern volatile struct ADC_RESULT_REGS AdcdResultRegs; +extern volatile struct ADC_REGS AdcaRegs; +extern volatile struct ADC_REGS AdcbRegs; +extern volatile struct ADC_REGS AdccRegs; +extern volatile struct ADC_REGS AdcdRegs; +#endif +#ifdef CPU2 +extern volatile struct ADC_RESULT_REGS AdcaResultRegs; +extern volatile struct ADC_RESULT_REGS AdcbResultRegs; +extern volatile struct ADC_RESULT_REGS AdccResultRegs; +extern volatile struct ADC_RESULT_REGS AdcdResultRegs; +extern volatile struct ADC_REGS AdcaRegs; +extern volatile struct ADC_REGS AdcbRegs; +extern volatile struct ADC_REGS AdccRegs; +extern volatile struct ADC_REGS AdcdRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_analogsubsys.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_analogsubsys.h new file mode 100644 index 0000000000..b116e47d77 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_analogsubsys.h @@ -0,0 +1,199 @@ +//########################################################################### +// +// FILE: F2837xD_analogsubsys.h +// +// TITLE: ANALOGSUBSYS Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_ANALOGSUBSYS_H__ +#define __F2837xD_ANALOGSUBSYS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// ANALOGSUBSYS Individual Register Bit Definitions: + +struct INTOSC1TRIM_BITS { // bits description + Uint16 VALFINETRIM:12; // 11:0 Oscillator Value Fine Trim Bits + Uint16 rsvd1:4; // 15:12 Reserved + Uint16 rsvd2:8; // 23:16 Reserved + Uint16 rsvd3:8; // 31:24 Reserved +}; + +union INTOSC1TRIM_REG { + Uint32 all; + struct INTOSC1TRIM_BITS bit; +}; + +struct INTOSC2TRIM_BITS { // bits description + Uint16 VALFINETRIM:12; // 11:0 Oscillator Value Fine Trim Bits + Uint16 rsvd1:4; // 15:12 Reserved + Uint16 rsvd2:8; // 23:16 Reserved + Uint16 rsvd3:8; // 31:24 Reserved +}; + +union INTOSC2TRIM_REG { + Uint32 all; + struct INTOSC2TRIM_BITS bit; +}; + +struct TSNSCTL_BITS { // bits description + Uint16 ENABLE:1; // 0 Temperature Sensor Enable + Uint16 rsvd1:15; // 15:1 Reserved +}; + +union TSNSCTL_REG { + Uint16 all; + struct TSNSCTL_BITS bit; +}; + +struct LOCK_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 TSNSCTL:1; // 3 Temperature Sensor Control Register Lock + Uint16 rsvd4:1; // 4 Reserved + Uint16 rsvd5:1; // 5 Reserved + Uint16 rsvd6:1; // 6 Reserved + Uint32 rsvd7:12; // 18:7 Reserved + Uint16 rsvd8:1; // 19 Reserved + Uint16 rsvd9:1; // 20 Reserved + Uint16 rsvd10:1; // 21 Reserved + Uint16 rsvd11:1; // 22 Reserved + Uint16 rsvd12:1; // 23 Reserved + Uint16 rsvd13:1; // 24 Reserved + Uint16 rsvd14:1; // 25 Reserved + Uint16 rsvd15:1; // 26 Reserved + Uint16 rsvd16:1; // 27 Reserved + Uint16 rsvd17:1; // 28 Reserved + Uint16 rsvd18:1; // 29 Reserved + Uint16 rsvd19:1; // 30 Reserved + Uint16 rsvd20:1; // 31 Reserved +}; + +union LOCK_REG { + Uint32 all; + struct LOCK_BITS bit; +}; + +struct ANAREFTRIMA_BITS { // bits description + Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim + Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim + Uint16 IREFTRIM:5; // 15:11 Reference Current Trim + Uint16 rsvd1:8; // 23:16 Reserved + Uint16 rsvd2:8; // 31:24 Reserved +}; + +union ANAREFTRIMA_REG { + Uint32 all; + struct ANAREFTRIMA_BITS bit; +}; + +struct ANAREFTRIMB_BITS { // bits description + Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim + Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim + Uint16 IREFTRIM:5; // 15:11 Reference Current Trim + Uint16 rsvd1:8; // 23:16 Reserved + Uint16 rsvd2:8; // 31:24 Reserved +}; + +union ANAREFTRIMB_REG { + Uint32 all; + struct ANAREFTRIMB_BITS bit; +}; + +struct ANAREFTRIMC_BITS { // bits description + Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim + Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim + Uint16 IREFTRIM:5; // 15:11 Reference Current Trim + Uint16 rsvd1:8; // 23:16 Reserved + Uint16 rsvd2:8; // 31:24 Reserved +}; + +union ANAREFTRIMC_REG { + Uint32 all; + struct ANAREFTRIMC_BITS bit; +}; + +struct ANAREFTRIMD_BITS { // bits description + Uint16 BGVALTRIM:6; // 5:0 Bandgap Value Trim + Uint16 BGSLOPETRIM:5; // 10:6 Bandgap Slope Trim + Uint16 IREFTRIM:5; // 15:11 Reference Current Trim + Uint16 rsvd1:8; // 23:16 Reserved + Uint16 rsvd2:8; // 31:24 Reserved +}; + +union ANAREFTRIMD_REG { + Uint32 all; + struct ANAREFTRIMD_BITS bit; +}; + +struct ANALOG_SUBSYS_REGS { + Uint16 rsvd1[32]; // Reserved + union INTOSC1TRIM_REG INTOSC1TRIM; // Internal Oscillator 1 Trim Register + union INTOSC2TRIM_REG INTOSC2TRIM; // Internal Oscillator 2 Trim Register + Uint16 rsvd2[2]; // Reserved + union TSNSCTL_REG TSNSCTL; // Temperature Sensor Control Register + Uint16 rsvd3[7]; // Reserved + union LOCK_REG LOCK; // Lock Register + Uint16 rsvd4[6]; // Reserved + union ANAREFTRIMA_REG ANAREFTRIMA; // Analog Reference Trim A Register + union ANAREFTRIMB_REG ANAREFTRIMB; // Analog Reference Trim B Register + union ANAREFTRIMC_REG ANAREFTRIMC; // Analog Reference Trim C Register + union ANAREFTRIMD_REG ANAREFTRIMD; // Analog Reference Trim D Register + Uint16 rsvd5[10]; // Reserved +}; + +//--------------------------------------------------------------------------- +// ANALOGSUBSYS External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_can.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_can.h new file mode 100644 index 0000000000..ad625e4554 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_can.h @@ -0,0 +1,612 @@ +//########################################################################### +// +// FILE: F2837xD_can.h +// +// TITLE: CAN Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_CAN_H__ +#define __F2837xD_CAN_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// CAN Individual Register Bit Definitions: + +struct CAN_CTL_BITS { // bits description + bp_16 Init:1; // 0 Initialization + bp_16 IE0:1; // 1 Interrupt line 0 Enable + bp_16 SIE:1; // 2 Status Change Interrupt Enable + bp_16 EIE:1; // 3 Error Interrupt Enable + bp_16 rsvd1:1; // 4 Reserved + bp_16 DAR:1; // 5 Disable Automatic Retransmission + bp_16 CCE:1; // 6 Configuration Change Enable + bp_16 Test:1; // 7 Test Mode Enable + bp_16 IDS:1; // 8 Interruption Debug Support Enable + bp_16 ABO:1; // 9 Auto-Bus-On Enable + bp_16 PMD:4; // 13:10 Parity on/off + bp_16 rsvd2:1; // 14 Reserved + bp_16 SWR:1; // 15 SW Reset Enable + bp_32 INITDBG:1; // 16 Debug Mode Status + bp_32 IE1:1; // 17 Interrupt line 1 Enable Disabled + bp_32 rsvd3:1; // 18 Reserved + bp_32 rsvd4:1; // 19 Reserved + bp_32 rsvd5:1; // 20 Reserved + bp_32 rsvd6:3; // 23:21 Reserved + bp_32 rsvd7:1; // 24 Reserved + bp_32 rsvd8:1; // 25 Reserved + bp_32 rsvd9:6; // 31:26 Reserved +}; + +union CAN_CTL_REG { + bp_32 all; + struct CAN_CTL_BITS bit; +}; + +struct CAN_ES_BITS { // bits description + bp_16 LEC:3; // 2:0 Last Error Code + bp_16 TxOk:1; // 3 Transmission status + bp_16 RxOk:1; // 4 Reception status + bp_16 EPass:1; // 5 Error Passive State + bp_16 EWarn:1; // 6 Warning State + bp_16 BOff:1; // 7 Bus-Off State + bp_16 PER:1; // 8 Parity Error Detected + bp_16 rsvd1:1; // 9 Reserved + bp_16 rsvd2:1; // 10 Reserved + bp_16 rsvd3:5; // 15:11 Reserved + bp_32 rsvd4:16; // 31:16 Reserved +}; + +union CAN_ES_REG { + bp_32 all; + struct CAN_ES_BITS bit; +}; + +struct CAN_ERRC_BITS { // bits description + bp_16 TEC:8; // 7:0 Transmit Error Counter + bp_16 REC:7; // 14:8 Receive Error Counter + bp_16 RP:1; // 15 Receive Error Passive + bp_32 rsvd1:16; // 31:16 Reserved +}; + +union CAN_ERRC_REG { + bp_32 all; + struct CAN_ERRC_BITS bit; +}; + +struct CAN_BTR_BITS { // bits description + bp_16 BRP:6; // 5:0 Baud Rate Prescaler + bp_16 SJW:2; // 7:6 Synchronization Jump Width + bp_16 TSEG1:4; // 11:8 Time segment + bp_16 TSEG2:3; // 14:12 Time segment + bp_16 rsvd1:1; // 15 Reserved + bp_32 BRPE:4; // 19:16 Baud Rate Prescaler Extension + bp_32 rsvd2:12; // 31:20 Reserved +}; + +union CAN_BTR_REG { + bp_32 all; + struct CAN_BTR_BITS bit; +}; + +struct CAN_INT_BITS { // bits description + bp_16 INT0ID:16; // 15:0 Interrupt Identifier + bp_32 INT1ID:8; // 23:16 Interrupt 1 Identifier + bp_32 rsvd1:8; // 31:24 Reserved +}; + +union CAN_INT_REG { + bp_32 all; + struct CAN_INT_BITS bit; +}; + +struct CAN_TEST_BITS { // bits description + bp_16 rsvd1:3; // 2:0 Reserved + bp_16 SILENT:1; // 3 Silent Mode + bp_16 LBACK:1; // 4 Loopback Mode + bp_16 TX:2; // 6:5 CANTX Pin Control + bp_16 RX:1; // 7 CANRX Pin Status + bp_16 EXL:1; // 8 External Loopback Mode + bp_16 RDA:1; // 9 RAM Direct Access Enable: + bp_16 rsvd2:6; // 15:10 Reserved + bp_32 rsvd3:16; // 31:16 Reserved +}; + +union CAN_TEST_REG { + bp_32 all; + struct CAN_TEST_BITS bit; +}; + +struct CAN_PERR_BITS { // bits description + bp_16 MSG_NUM:8; // 7:0 Message Number + bp_16 WORD_NUM:3; // 10:8 Word Number + bp_16 rsvd1:5; // 15:11 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_PERR_REG { + bp_32 all; + struct CAN_PERR_BITS bit; +}; + +struct CAN_RAM_INIT_BITS { // bits description + bp_16 KEY0:1; // 0 KEY0 + bp_16 KEY1:1; // 1 KEY1 + bp_16 KEY2:1; // 2 KEY2 + bp_16 KEY3:1; // 3 KEY3 + bp_16 CAN_RAM_INIT:1; // 4 Initialize CAN Mailbox RAM + bp_16 RAM_INIT_DONE:1; // 5 CAN RAM initialization complete + bp_16 rsvd1:10; // 15:6 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_RAM_INIT_REG { + bp_32 all; + struct CAN_RAM_INIT_BITS bit; +}; + +struct CAN_GLB_INT_EN_BITS { // bits description + bp_16 GLBINT0_EN:1; // 0 Global Interrupt Enable for CAN INT0 + bp_16 GLBINT1_EN:1; // 1 Global Interrupt Enable for CAN INT1 + bp_16 rsvd1:14; // 15:2 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_GLB_INT_EN_REG { + bp_32 all; + struct CAN_GLB_INT_EN_BITS bit; +}; + +struct CAN_GLB_INT_FLG_BITS { // bits description + bp_16 INT0_FLG:1; // 0 Global Interrupt Flag for CAN INT0 + bp_16 INT1_FLG:1; // 1 Global Interrupt Flag for CAN INT1 + bp_16 rsvd1:14; // 15:2 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_GLB_INT_FLG_REG { + bp_32 all; + struct CAN_GLB_INT_FLG_BITS bit; +}; + +struct CAN_GLB_INT_CLR_BITS { // bits description + bp_16 INT0_FLG_CLR:1; // 0 Global Interrupt flag clear for CAN INT0 + bp_16 INT1_FLG_CLR:1; // 1 Global Interrupt flag clear for CAN INT1 + bp_16 rsvd1:14; // 15:2 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_GLB_INT_CLR_REG { + bp_32 all; + struct CAN_GLB_INT_CLR_BITS bit; +}; + +struct CAN_TXRQ_X_BITS { // bits description + bp_16 TxRqstReg1:2; // 1:0 Transmit Request Register 1 + bp_16 TxRqstReg2:2; // 3:2 Transmit Request Register 2 + bp_16 rsvd1:12; // 15:4 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_TXRQ_X_REG { + bp_32 all; + struct CAN_TXRQ_X_BITS bit; +}; + +struct CAN_NDAT_X_BITS { // bits description + bp_16 NewDatReg1:2; // 1:0 New Data Register 1 + bp_16 NewDatReg2:2; // 3:2 New Data Register 2 + bp_16 rsvd1:12; // 15:4 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_NDAT_X_REG { + bp_32 all; + struct CAN_NDAT_X_BITS bit; +}; + +struct CAN_IPEN_X_BITS { // bits description + bp_16 IntPndReg1:2; // 1:0 Interrupt Pending Register 1 + bp_16 IntPndReg2:2; // 3:2 Interrupt Pending Register 2 + bp_16 rsvd1:12; // 15:4 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_IPEN_X_REG { + bp_32 all; + struct CAN_IPEN_X_BITS bit; +}; + +struct CAN_MVAL_X_BITS { // bits description + bp_16 MsgValReg1:2; // 1:0 Message Valid Register 1 + bp_16 MsgValReg2:2; // 3:2 Message Valid Register 2 + bp_16 rsvd1:12; // 15:4 Reserved + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_MVAL_X_REG { + bp_32 all; + struct CAN_MVAL_X_BITS bit; +}; + +struct CAN_IF1CMD_BITS { // bits description + bp_16 MSG_NUM:8; // 7:0 Message Number + bp_16 rsvd1:6; // 13:8 Reserved + bp_16 rsvd2:1; // 14 Reserved + bp_16 Busy:1; // 15 Busy Flag + bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 + bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 + bp_32 TXRQST:1; // 18 Access Transmission Request Bit + bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit + bp_32 Control:1; // 20 Access Control Bits + bp_32 Arb:1; // 21 Access Arbitration Bits + bp_32 Mask:1; // 22 Access Mask Bits + bp_32 DIR:1; // 23 Write/Read Direction + bp_32 rsvd3:8; // 31:24 Reserved +}; + +union CAN_IF1CMD_REG { + bp_32 all; + struct CAN_IF1CMD_BITS bit; +}; + +struct CAN_IF1MSK_BITS { // bits description + bp_32 Msk:29; // 28:0 Identifier Mask + bp_32 rsvd1:1; // 29 Reserved + bp_32 MDir:1; // 30 Mask Message Direction + bp_32 MXtd:1; // 31 Mask Extended Identifier +}; + +union CAN_IF1MSK_REG { + bp_32 all; + struct CAN_IF1MSK_BITS bit; +}; + +struct CAN_IF1ARB_BITS { // bits description + bp_32 ID:29; // 28:0 ` + bp_32 Dir:1; // 29 Message Direction + bp_32 Xtd:1; // 30 Extended Identifier + bp_32 MsgVal:1; // 31 Message Valid +}; + +union CAN_IF1ARB_REG { + bp_32 all; + struct CAN_IF1ARB_BITS bit; +}; + +struct CAN_IF1MCTL_BITS { // bits description + bp_16 DLC:4; // 3:0 Data length code + bp_16 rsvd1:3; // 6:4 Reserved + bp_16 EoB:1; // 7 End of Block + bp_16 TxRqst:1; // 8 Transmit Request + bp_16 RmtEn:1; // 9 Remote Enable + bp_16 RxIE:1; // 10 Receive Interrupt Enable + bp_16 TxIE:1; // 11 Transmit Interrupt Enable + bp_16 UMask:1; // 12 Use Acceptance Mask + bp_16 IntPnd:1; // 13 Interrupt Pending + bp_16 MsgLst:1; // 14 Message Lost + bp_16 NewDat:1; // 15 New Data + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_IF1MCTL_REG { + bp_32 all; + struct CAN_IF1MCTL_BITS bit; +}; + +struct CAN_IF1DATA_BITS { // bits description + bp_16 Data_0:8; // 7:0 Data Byte 0 + bp_16 Data_1:8; // 15:8 Data Byte 1 + bp_32 Data_2:8; // 23:16 Data Byte 2 + bp_32 Data_3:8; // 31:24 Data Byte 3 +}; + +union CAN_IF1DATA_REG { + bp_32 all; + struct CAN_IF1DATA_BITS bit; +}; + +struct CAN_IF1DATB_BITS { // bits description + bp_16 Data_4:8; // 7:0 Data Byte 4 + bp_16 Data_5:8; // 15:8 Data Byte 5 + bp_32 Data_6:8; // 23:16 Data Byte 6 + bp_32 Data_7:8; // 31:24 Data Byte 7 +}; + +union CAN_IF1DATB_REG { + bp_32 all; + struct CAN_IF1DATB_BITS bit; +}; + +struct CAN_IF2CMD_BITS { // bits description + bp_16 MSG_NUM:8; // 7:0 Message Number + bp_16 rsvd1:6; // 13:8 Reserved + bp_16 rsvd2:1; // 14 Reserved + bp_16 Busy:1; // 15 Busy Flag + bp_32 DATA_B:1; // 16 Access Data Bytes 4-7 + bp_32 DATA_A:1; // 17 Access Data Bytes 0-3 + bp_32 TxRqst:1; // 18 Access Transmission Request Bit + bp_32 ClrIntPnd:1; // 19 Clear Interrupt Pending Bit + bp_32 Control:1; // 20 Access Control Bits + bp_32 Arb:1; // 21 Access Arbitration Bits + bp_32 Mask:1; // 22 Access Mask Bits + bp_32 DIR:1; // 23 Write/Read Direction + bp_32 rsvd3:8; // 31:24 Reserved +}; + +union CAN_IF2CMD_REG { + bp_32 all; + struct CAN_IF2CMD_BITS bit; +}; + +struct CAN_IF2MSK_BITS { // bits description + bp_32 Msk:29; // 28:0 Identifier Mask + bp_32 rsvd1:1; // 29 Reserved + bp_32 MDir:1; // 30 Mask Message Direction + bp_32 MXtd:1; // 31 Mask Extended Identifier +}; + +union CAN_IF2MSK_REG { + bp_32 all; + struct CAN_IF2MSK_BITS bit; +}; + +struct CAN_IF2ARB_BITS { // bits description + bp_32 ID:29; // 28:0 Message Identifier + bp_32 Dir:1; // 29 Message Direction + bp_32 Xtd:1; // 30 Extended Identifier + bp_32 MsgVal:1; // 31 Message Valid +}; + +union CAN_IF2ARB_REG { + bp_32 all; + struct CAN_IF2ARB_BITS bit; +}; + +struct CAN_IF2MCTL_BITS { // bits description + bp_16 DLC:4; // 3:0 Data length code + bp_16 rsvd1:3; // 6:4 Reserved + bp_16 EoB:1; // 7 End of Block + bp_16 TxRqst:1; // 8 Transmit Request + bp_16 RmtEn:1; // 9 Remote Enable + bp_16 RxIE:1; // 10 Receive Interrupt Enable + bp_16 TxIE:1; // 11 Transmit Interrupt Enable + bp_16 UMask:1; // 12 Use Acceptance Mask + bp_16 IntPnd:1; // 13 Interrupt Pending + bp_16 MsgLst:1; // 14 Message Lost + bp_16 NewDat:1; // 15 New Data + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_IF2MCTL_REG { + bp_32 all; + struct CAN_IF2MCTL_BITS bit; +}; + +struct CAN_IF2DATA_BITS { // bits description + bp_16 Data_0:8; // 7:0 Data Byte 0 + bp_16 Data_1:8; // 15:8 Data Byte 1 + bp_32 Data_2:8; // 23:16 Data Byte 2 + bp_32 Data_3:8; // 31:24 Data Byte 3 +}; + +union CAN_IF2DATA_REG { + bp_32 all; + struct CAN_IF2DATA_BITS bit; +}; + +struct CAN_IF2DATB_BITS { // bits description + bp_16 Data_4:8; // 7:0 Data Byte 4 + bp_16 Data_5:8; // 15:8 Data Byte 5 + bp_32 Data_6:8; // 23:16 Data Byte 6 + bp_32 Data_7:8; // 31:24 Data Byte 7 +}; + +union CAN_IF2DATB_REG { + bp_32 all; + struct CAN_IF2DATB_BITS bit; +}; + +struct CAN_IF3OBS_BITS { // bits description + bp_16 Mask:1; // 0 Mask data read observation + bp_16 Arb:1; // 1 Arbitration data read observation + bp_16 Ctrl:1; // 2 Ctrl read observation + bp_16 Data_A:1; // 3 Data A read observation + bp_16 Data_B:1; // 4 Data B read observation + bp_16 rsvd1:3; // 7:5 Reserved + bp_16 IF3SM:1; // 8 IF3 Status of Mask data read access + bp_16 IF3SA:1; // 9 IF3 Status of Arbitration data read access + bp_16 IF3SC:1; // 10 IF3 Status of Control bits read access + bp_16 IF3SDA:1; // 11 IF3 Status of Data A read access + bp_16 IF3SDB:1; // 12 IF3 Status of Data B read access + bp_16 rsvd2:2; // 14:13 Reserved + bp_16 IF3Upd:1; // 15 IF3 Update Data + bp_32 rsvd3:16; // 31:16 Reserved +}; + +union CAN_IF3OBS_REG { + bp_32 all; + struct CAN_IF3OBS_BITS bit; +}; + +struct CAN_IF3MSK_BITS { // bits description + bp_32 Msk:29; // 28:0 Mask + bp_32 rsvd1:1; // 29 Reserved + bp_32 MDir:1; // 30 Mask Message Direction + bp_32 MXtd:1; // 31 Mask Extended Identifier +}; + +union CAN_IF3MSK_REG { + bp_32 all; + struct CAN_IF3MSK_BITS bit; +}; + +struct CAN_IF3ARB_BITS { // bits description + bp_32 ID:29; // 28:0 Message Identifier + bp_32 Dir:1; // 29 Message Direction + bp_32 Xtd:1; // 30 Extended Identifier + bp_32 MsgVal:1; // 31 Message Valid +}; + +union CAN_IF3ARB_REG { + bp_32 all; + struct CAN_IF3ARB_BITS bit; +}; + +struct CAN_IF3MCTL_BITS { // bits description + bp_16 DLC:4; // 3:0 Data length code + bp_16 rsvd1:3; // 6:4 Reserved + bp_16 EoB:1; // 7 End of Block + bp_16 TxRqst:1; // 8 Transmit Request + bp_16 RmtEn:1; // 9 Remote Enable + bp_16 RxIE:1; // 10 Receive Interrupt Enable + bp_16 TxIE:1; // 11 Transmit Interrupt Enable + bp_16 UMask:1; // 12 Use Acceptance Mask + bp_16 IntPnd:1; // 13 Interrupt Pending + bp_16 MsgLst:1; // 14 Message Lost + bp_16 NewDat:1; // 15 New Data + bp_32 rsvd2:16; // 31:16 Reserved +}; + +union CAN_IF3MCTL_REG { + bp_32 all; + struct CAN_IF3MCTL_BITS bit; +}; + +struct CAN_IF3DATA_BITS { // bits description + bp_16 Data_0:8; // 7:0 Data Byte 0 + bp_16 Data_1:8; // 15:8 Data Byte 1 + bp_32 Data_2:8; // 23:16 Data Byte 2 + bp_32 Data_3:8; // 31:24 Data Byte 3 +}; + +union CAN_IF3DATA_REG { + bp_32 all; + struct CAN_IF3DATA_BITS bit; +}; + +struct CAN_IF3DATB_BITS { // bits description + bp_16 Data_4:8; // 7:0 Data Byte 4 + bp_16 Data_5:8; // 15:8 Data Byte 5 + bp_32 Data_6:8; // 23:16 Data Byte 6 + bp_32 Data_7:8; // 31:24 Data Byte 7 +}; + +union CAN_IF3DATB_REG { + bp_32 all; + struct CAN_IF3DATB_BITS bit; +}; + +struct CAN_REGS { + union CAN_CTL_REG CAN_CTL; // CAN Control Register + union CAN_ES_REG CAN_ES; // Error and Status Register + union CAN_ERRC_REG CAN_ERRC; // Error Counter Register + union CAN_BTR_REG CAN_BTR; // Bit Timing Register + union CAN_INT_REG CAN_INT; // Interrupt Register + union CAN_TEST_REG CAN_TEST; // Test Register + uint32_t rsvd1[2]; // Reserved + union CAN_PERR_REG CAN_PERR; // CAN Parity Error Code Register + uint32_t rsvd2[16]; // Reserved + union CAN_RAM_INIT_REG CAN_RAM_INIT; // CAN RAM Initialization Register + uint32_t rsvd3[6]; // Reserved + union CAN_GLB_INT_EN_REG CAN_GLB_INT_EN; // CAN Global Interrupt Enable Register + union CAN_GLB_INT_FLG_REG CAN_GLB_INT_FLG; // CAN Global Interrupt Flag Register + union CAN_GLB_INT_CLR_REG CAN_GLB_INT_CLR; // CAN Global Interrupt Clear Register + uint32_t rsvd4[18]; // Reserved + bp_32 CAN_ABOTR; // Auto-Bus-On Time Register + union CAN_TXRQ_X_REG CAN_TXRQ_X; // CAN Transmission Request Register + bp_32 CAN_TXRQ_21; // CAN Transmission Request 2_1 Register + uint32_t rsvd5[6]; // Reserved + union CAN_NDAT_X_REG CAN_NDAT_X; // CAN New Data Register + bp_32 CAN_NDAT_21; // CAN New Data 2_1 Register + uint32_t rsvd6[6]; // Reserved + union CAN_IPEN_X_REG CAN_IPEN_X; // CAN Interrupt Pending Register + bp_32 CAN_IPEN_21; // CAN Interrupt Pending 2_1 Register + uint32_t rsvd7[6]; // Reserved + union CAN_MVAL_X_REG CAN_MVAL_X; // CAN Message Valid Register + bp_32 CAN_MVAL_21; // CAN Message Valid 2_1 Register + uint32_t rsvd8[8]; // Reserved + bp_32 CAN_IP_MUX21; // CAN Interrupt Multiplexer 2_1 Register + uint32_t rsvd9[18]; // Reserved + union CAN_IF1CMD_REG CAN_IF1CMD; // IF1 Command Register + union CAN_IF1MSK_REG CAN_IF1MSK; // IF1 Mask Register + union CAN_IF1ARB_REG CAN_IF1ARB; // IF1 Arbitration Register + union CAN_IF1MCTL_REG CAN_IF1MCTL; // IF1 Message Control Register + union CAN_IF1DATA_REG CAN_IF1DATA; // IF1 Data A Register + union CAN_IF1DATB_REG CAN_IF1DATB; // IF1 Data B Register + uint32_t rsvd10[4]; // Reserved + union CAN_IF2CMD_REG CAN_IF2CMD; // IF2 Command Register + union CAN_IF2MSK_REG CAN_IF2MSK; // IF2 Mask Register + union CAN_IF2ARB_REG CAN_IF2ARB; // IF2 Arbitration Register + union CAN_IF2MCTL_REG CAN_IF2MCTL; // IF2 Message Control Register + union CAN_IF2DATA_REG CAN_IF2DATA; // IF2 Data A Register + union CAN_IF2DATB_REG CAN_IF2DATB; // IF2 Data B Register + uint32_t rsvd11[4]; // Reserved + union CAN_IF3OBS_REG CAN_IF3OBS; // IF3 Observation Register + union CAN_IF3MSK_REG CAN_IF3MSK; // IF3 Mask Register + union CAN_IF3ARB_REG CAN_IF3ARB; // IF3 Arbitration Register + union CAN_IF3MCTL_REG CAN_IF3MCTL; // IF3 Message Control Register + union CAN_IF3DATA_REG CAN_IF3DATA; // IF3 Data A Register + union CAN_IF3DATB_REG CAN_IF3DATB; // IF3 Data B Register + uint32_t rsvd12[4]; // Reserved + bp_32 CAN_IF3UPD; // IF3 Update Enable Register +}; + +//--------------------------------------------------------------------------- +// CAN External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct CAN_REGS CanaRegs; +extern volatile struct CAN_REGS CanbRegs; +#endif +#ifdef CPU2 +extern volatile struct CAN_REGS CanaRegs; +extern volatile struct CAN_REGS CanbRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_cla.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_cla.h new file mode 100644 index 0000000000..683333074c --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_cla.h @@ -0,0 +1,305 @@ +//########################################################################### +// +// FILE: F2837xD_cla.h +// +// TITLE: CLA Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_CLA_H__ +#define __F2837xD_CLA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// CLA Individual Register Bit Definitions: + +struct MCTL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset + Uint16 SOFTRESET:1; // 1 Soft Reset + Uint16 IACKE:1; // 2 IACK enable + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union MCTL_REG { + Uint16 all; + struct MCTL_BITS bit; +}; + +struct MIFR_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Flag + Uint16 INT2:1; // 1 Task 2 Interrupt Flag + Uint16 INT3:1; // 2 Task 3 Interrupt Flag + Uint16 INT4:1; // 3 Task 4 Interrupt Flag + Uint16 INT5:1; // 4 Task 5 Interrupt Flag + Uint16 INT6:1; // 5 Task 6 Interrupt Flag + Uint16 INT7:1; // 6 Task 7 Interrupt Flag + Uint16 INT8:1; // 7 Task 8 Interrupt Flag + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MIFR_REG { + Uint16 all; + struct MIFR_BITS bit; +}; + +struct MIOVF_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag + Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag + Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag + Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag + Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag + Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag + Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag + Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MIOVF_REG { + Uint16 all; + struct MIOVF_BITS bit; +}; + +struct MIFRC_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Force + Uint16 INT2:1; // 1 Task 2 Interrupt Force + Uint16 INT3:1; // 2 Task 3 Interrupt Force + Uint16 INT4:1; // 3 Task 4 Interrupt Force + Uint16 INT5:1; // 4 Task 5 Interrupt Force + Uint16 INT6:1; // 5 Task 6 Interrupt Force + Uint16 INT7:1; // 6 Task 7 Interrupt Force + Uint16 INT8:1; // 7 Task 8 Interrupt Force + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MIFRC_REG { + Uint16 all; + struct MIFRC_BITS bit; +}; + +struct MICLR_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Flag Clear + Uint16 INT2:1; // 1 Task 2 Interrupt Flag Clear + Uint16 INT3:1; // 2 Task 3 Interrupt Flag Clear + Uint16 INT4:1; // 3 Task 4 Interrupt Flag Clear + Uint16 INT5:1; // 4 Task 5 Interrupt Flag Clear + Uint16 INT6:1; // 5 Task 6 Interrupt Flag Clear + Uint16 INT7:1; // 6 Task 7 Interrupt Flag Clear + Uint16 INT8:1; // 7 Task 8 Interrupt Flag Clear + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MICLR_REG { + Uint16 all; + struct MICLR_BITS bit; +}; + +struct MICLROVF_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Overflow Flag Clear + Uint16 INT2:1; // 1 Task 2 Interrupt Overflow Flag Clear + Uint16 INT3:1; // 2 Task 3 Interrupt Overflow Flag Clear + Uint16 INT4:1; // 3 Task 4 Interrupt Overflow Flag Clear + Uint16 INT5:1; // 4 Task 5 Interrupt Overflow Flag Clear + Uint16 INT6:1; // 5 Task 6 Interrupt Overflow Flag Clear + Uint16 INT7:1; // 6 Task 7 Interrupt Overflow Flag Clear + Uint16 INT8:1; // 7 Task 8 Interrupt Overflow Flag Clear + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MICLROVF_REG { + Uint16 all; + struct MICLROVF_BITS bit; +}; + +struct MIER_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Interrupt Enable + Uint16 INT2:1; // 1 Task 2 Interrupt Enable + Uint16 INT3:1; // 2 Task 3 Interrupt Enable + Uint16 INT4:1; // 3 Task 4 Interrupt Enable + Uint16 INT5:1; // 4 Task 5 Interrupt Enable + Uint16 INT6:1; // 5 Task 6 Interrupt Enable + Uint16 INT7:1; // 6 Task 7 Interrupt Enable + Uint16 INT8:1; // 7 Task 8 Interrupt Enable + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MIER_REG { + Uint16 all; + struct MIER_BITS bit; +}; + +struct MIRUN_BITS { // bits description + Uint16 INT1:1; // 0 Task 1 Run Status + Uint16 INT2:1; // 1 Task 2 Run Status + Uint16 INT3:1; // 2 Task 3 Run Status + Uint16 INT4:1; // 3 Task 4 Run Status + Uint16 INT5:1; // 4 Task 5 Run Status + Uint16 INT6:1; // 5 Task 6 Run Status + Uint16 INT7:1; // 6 Task 7 Run Status + Uint16 INT8:1; // 7 Task 8 Run Status + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union MIRUN_REG { + Uint16 all; + struct MIRUN_BITS bit; +}; + +struct _MSTF_BITS { // bits description + Uint16 LVF:1; // 0 Latched Overflow Flag + Uint16 LUF:1; // 1 Latched Underflow Flag + Uint16 NF:1; // 2 Negative Float Flag + Uint16 ZF:1; // 3 Zero Float Flag + Uint16 rsvd1:2; // 5:4 Reserved + Uint16 TF:1; // 6 Test Flag + Uint16 rsvd2:2; // 8:7 Reserved + Uint16 RNDF32:1; // 9 Round 32-bit Floating-Point Mode + Uint16 rsvd3:1; // 10 Reserved + Uint16 MEALLOW:1; // 11 MEALLOW Status + Uint32 _RPC:16; // 27:12 Return PC + Uint16 rsvd4:4; // 31:28 Reserved +}; + +union _MSTF_REG { + Uint32 all; + struct _MSTF_BITS bit; +}; + +union MR_REG { + Uint32 i32; + float f32; +}; + +struct CLA_REGS { + Uint16 MVECT1; // Task Interrupt Vector + Uint16 MVECT2; // Task Interrupt Vector + Uint16 MVECT3; // Task Interrupt Vector + Uint16 MVECT4; // Task Interrupt Vector + Uint16 MVECT5; // Task Interrupt Vector + Uint16 MVECT6; // Task Interrupt Vector + Uint16 MVECT7; // Task Interrupt Vector + Uint16 MVECT8; // Task Interrupt Vector + Uint16 rsvd1[8]; // Reserved + union MCTL_REG MCTL; // Control Register + Uint16 rsvd2[15]; // Reserved + union MIFR_REG MIFR; // Interrupt Flag Register + union MIOVF_REG MIOVF; // Interrupt Overflow Flag Register + union MIFRC_REG MIFRC; // Interrupt Force Register + union MICLR_REG MICLR; // Interrupt Flag Clear Register + union MICLROVF_REG MICLROVF; // Interrupt Overflow Flag Clear Register + union MIER_REG MIER; // Interrupt Enable Register + union MIRUN_REG MIRUN; // Interrupt Run Status Register + Uint16 rsvd3; // Reserved + Uint16 _MPC; // CLA Program Counter + Uint16 rsvd4; // Reserved + Uint16 _MAR0; // CLA Auxiliary Register 0 + Uint16 _MAR1; // CLA Auxiliary Register 1 + Uint16 rsvd5[2]; // Reserved + union _MSTF_REG _MSTF; // CLA Floating-Point Status Register + union MR_REG _MR0; // CLA Floating-Point Result Register 0 + Uint16 rsvd6[2]; // Reserved + union MR_REG _MR1; // CLA Floating-Point Result Register 1 + Uint16 rsvd7[2]; // Reserved + union MR_REG _MR2; // CLA Floating-Point Result Register 2 + Uint16 rsvd8[2]; // Reserved + union MR_REG _MR3; // CLA Floating-Point Result Register 3 +}; + +struct SOFTINTEN_BITS { // bits description + Uint16 TASK1:1; // 0 Task 1 Software Interrupt Enable + Uint16 TASK2:1; // 1 Task 2 Software Interrupt Enable + Uint16 TASK3:1; // 2 Task 3 Software Interrupt Enable + Uint16 TASK4:1; // 3 Task 4 Software Interrupt Enable + Uint16 TASK5:1; // 4 Task 5 Software Interrupt Enable + Uint16 TASK6:1; // 5 Task 6 Software Interrupt Enable + Uint16 TASK7:1; // 6 Task 7 Software Interrupt Enable + Uint16 TASK8:1; // 7 Task 8 Software Interrupt Enable + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTINTEN_REG { + Uint32 all; + struct SOFTINTEN_BITS bit; +}; + +struct SOFTINTFRC_BITS { // bits description + Uint16 TASK1:1; // 0 Task 1 Software Interrupt Force + Uint16 TASK2:1; // 1 Task 2 Software Interrupt Force + Uint16 TASK3:1; // 2 Task 3 Software Interrupt Force + Uint16 TASK4:1; // 3 Task 4 Software Interrupt Force + Uint16 TASK5:1; // 4 Task 5 Software Interrupt Force + Uint16 TASK6:1; // 5 Task 6 Software Interrupt Force + Uint16 TASK7:1; // 6 Task 7 Software Interrupt Force + Uint16 TASK8:1; // 7 Task 8 Software Interrupt Force + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTINTFRC_REG { + Uint32 all; + struct SOFTINTFRC_BITS bit; +}; + +struct CLA_SOFTINT_REGS { + union SOFTINTEN_REG SOFTINTEN; // CLA Software Interrupt Enable Register + union SOFTINTFRC_REG SOFTINTFRC; // CLA Software Interrupt Force Register +}; + +//--------------------------------------------------------------------------- +// CLA External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; +extern volatile struct CLA_REGS Cla1Regs; +#endif +#ifdef CPU2 +extern volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; +extern volatile struct CLA_REGS Cla1Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_cmpss.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_cmpss.h new file mode 100644 index 0000000000..51b595b01c --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_cmpss.h @@ -0,0 +1,310 @@ +//########################################################################### +// +// FILE: F2837xD_cmpss.h +// +// TITLE: CMPSS Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_CMPSS_H__ +#define __F2837xD_CMPSS_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// CMPSS Individual Register Bit Definitions: + +struct COMPCTL_BITS { // bits description + Uint16 COMPHSOURCE:1; // 0 High Comparator Source Select + Uint16 COMPHINV:1; // 1 High Comparator Invert Select + Uint16 CTRIPHSEL:2; // 3:2 High Comparator Trip Select + Uint16 CTRIPOUTHSEL:2; // 5:4 High Comparator Trip Output Select + Uint16 ASYNCHEN:1; // 6 High Comparator Asynchronous Path Enable + Uint16 rsvd1:1; // 7 Reserved + Uint16 COMPLSOURCE:1; // 8 Low Comparator Source Select + Uint16 COMPLINV:1; // 9 Low Comparator Invert Select + Uint16 CTRIPLSEL:2; // 11:10 Low Comparator Trip Select + Uint16 CTRIPOUTLSEL:2; // 13:12 Low Comparator Trip Output Select + Uint16 ASYNCLEN:1; // 14 Low Comparator Asynchronous Path Enable + Uint16 COMPDACE:1; // 15 Comparator/DAC Enable +}; + +union COMPCTL_REG { + Uint16 all; + struct COMPCTL_BITS bit; +}; + +struct COMPHYSCTL_BITS { // bits description + Uint16 COMPHYS:3; // 2:0 Comparator Hysteresis Trim + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union COMPHYSCTL_REG { + Uint16 all; + struct COMPHYSCTL_BITS bit; +}; + +struct COMPSTS_BITS { // bits description + Uint16 COMPHSTS:1; // 0 High Comparator Status + Uint16 COMPHLATCH:1; // 1 High Comparator Latched Status + Uint16 rsvd1:6; // 7:2 Reserved + Uint16 COMPLSTS:1; // 8 Low Comparator Status + Uint16 COMPLLATCH:1; // 9 Low Comparator Latched Status + Uint16 rsvd2:6; // 15:10 Reserved +}; + +union COMPSTS_REG { + Uint16 all; + struct COMPSTS_BITS bit; +}; + +struct COMPSTSCLR_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 HLATCHCLR:1; // 1 High Comparator Latched Status Clear + Uint16 HSYNCCLREN:1; // 2 High Comparator PWMSYNC Clear Enable + Uint16 rsvd2:6; // 8:3 Reserved + Uint16 LLATCHCLR:1; // 9 Low Comparator Latched Status Clear + Uint16 LSYNCCLREN:1; // 10 Low Comparator PWMSYNC Clear Enable + Uint16 rsvd3:5; // 15:11 Reserved +}; + +union COMPSTSCLR_REG { + Uint16 all; + struct COMPSTSCLR_BITS bit; +}; + +struct COMPDACCTL_BITS { // bits description + Uint16 DACSOURCE:1; // 0 DAC Source Control + Uint16 RAMPSOURCE:4; // 4:1 Ramp Generator Source Control + Uint16 SELREF:1; // 5 DAC Reference Select + Uint16 RAMPLOADSEL:1; // 6 Ramp Load Select + Uint16 SWLOADSEL:1; // 7 Software Load Select + Uint16 rsvd1:6; // 13:8 Reserved + Uint16 FREESOFT:2; // 15:14 Free/Soft Emulation Bits +}; + +union COMPDACCTL_REG { + Uint16 all; + struct COMPDACCTL_BITS bit; +}; + +struct DACHVALS_BITS { // bits description + Uint16 DACVAL:12; // 11:0 DAC Value Control + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACHVALS_REG { + Uint16 all; + struct DACHVALS_BITS bit; +}; + +struct DACHVALA_BITS { // bits description + Uint16 DACVAL:12; // 11:0 DAC Value Control + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACHVALA_REG { + Uint16 all; + struct DACHVALA_BITS bit; +}; + +struct DACLVALS_BITS { // bits description + Uint16 DACVAL:12; // 11:0 DAC Value Control + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACLVALS_REG { + Uint16 all; + struct DACLVALS_BITS bit; +}; + +struct DACLVALA_BITS { // bits description + Uint16 DACVAL:12; // 11:0 DAC Value Control + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACLVALA_REG { + Uint16 all; + struct DACLVALA_BITS bit; +}; + +struct RAMPDLYA_BITS { // bits description + Uint16 DELAY:13; // 12:0 Ramp Delay Value + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union RAMPDLYA_REG { + Uint16 all; + struct RAMPDLYA_BITS bit; +}; + +struct RAMPDLYS_BITS { // bits description + Uint16 DELAY:13; // 12:0 Ramp Delay Value + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union RAMPDLYS_REG { + Uint16 all; + struct RAMPDLYS_BITS bit; +}; + +struct CTRIPLFILCTL_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 SAMPWIN:5; // 8:4 Sample Window + Uint16 THRESH:5; // 13:9 Majority Voting Threshold + Uint16 rsvd2:1; // 14 Reserved + Uint16 FILINIT:1; // 15 Filter Initialization Bit +}; + +union CTRIPLFILCTL_REG { + Uint16 all; + struct CTRIPLFILCTL_BITS bit; +}; + +struct CTRIPLFILCLKCTL_BITS { // bits description + Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union CTRIPLFILCLKCTL_REG { + Uint16 all; + struct CTRIPLFILCLKCTL_BITS bit; +}; + +struct CTRIPHFILCTL_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 SAMPWIN:5; // 8:4 Sample Window + Uint16 THRESH:5; // 13:9 Majority Voting Threshold + Uint16 rsvd2:1; // 14 Reserved + Uint16 FILINIT:1; // 15 Filter Initialization Bit +}; + +union CTRIPHFILCTL_REG { + Uint16 all; + struct CTRIPHFILCTL_BITS bit; +}; + +struct CTRIPHFILCLKCTL_BITS { // bits description + Uint16 CLKPRESCALE:10; // 9:0 Sample Clock Prescale + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union CTRIPHFILCLKCTL_REG { + Uint16 all; + struct CTRIPHFILCLKCTL_BITS bit; +}; + +struct COMPLOCK_BITS { // bits description + Uint16 COMPCTL:1; // 0 COMPCTL Lock + Uint16 COMPHYSCTL:1; // 1 COMPHYSCTL Lock + Uint16 DACCTL:1; // 2 DACCTL Lock + Uint16 CTRIP:1; // 3 CTRIP Lock + Uint16 rsvd1:1; // 4 Reserved + Uint16 rsvd2:11; // 15:5 Reserved +}; + +union COMPLOCK_REG { + Uint16 all; + struct COMPLOCK_BITS bit; +}; + +struct CMPSS_REGS { + union COMPCTL_REG COMPCTL; // CMPSS Comparator Control Register + union COMPHYSCTL_REG COMPHYSCTL; // CMPSS Comparator Hysteresis Control Register + union COMPSTS_REG COMPSTS; // CMPSS Comparator Status Register + union COMPSTSCLR_REG COMPSTSCLR; // CMPSS Comparator Status Clear Register + union COMPDACCTL_REG COMPDACCTL; // CMPSS DAC Control Register + Uint16 rsvd1; // Reserved + union DACHVALS_REG DACHVALS; // CMPSS High DAC Value Shadow Register + union DACHVALA_REG DACHVALA; // CMPSS High DAC Value Active Register + Uint16 RAMPMAXREFA; // CMPSS Ramp Max Reference Active Register + Uint16 rsvd2; // Reserved + Uint16 RAMPMAXREFS; // CMPSS Ramp Max Reference Shadow Register + Uint16 rsvd3; // Reserved + Uint16 RAMPDECVALA; // CMPSS Ramp Decrement Value Active Register + Uint16 rsvd4; // Reserved + Uint16 RAMPDECVALS; // CMPSS Ramp Decrement Value Shadow Register + Uint16 rsvd5; // Reserved + Uint16 RAMPSTS; // CMPSS Ramp Status Register + Uint16 rsvd6; // Reserved + union DACLVALS_REG DACLVALS; // CMPSS Low DAC Value Shadow Register + union DACLVALA_REG DACLVALA; // CMPSS Low DAC Value Active Register + union RAMPDLYA_REG RAMPDLYA; // CMPSS Ramp Delay Active Register + union RAMPDLYS_REG RAMPDLYS; // CMPSS Ramp Delay Shadow Register + union CTRIPLFILCTL_REG CTRIPLFILCTL; // CTRIPL Filter Control Register + union CTRIPLFILCLKCTL_REG CTRIPLFILCLKCTL; // CTRIPL Filter Clock Control Register + union CTRIPHFILCTL_REG CTRIPHFILCTL; // CTRIPH Filter Control Register + union CTRIPHFILCLKCTL_REG CTRIPHFILCLKCTL; // CTRIPH Filter Clock Control Register + union COMPLOCK_REG COMPLOCK; // CMPSS Lock Register + Uint16 rsvd7[5]; // Reserved +}; + +//--------------------------------------------------------------------------- +// CMPSS External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct CMPSS_REGS Cmpss1Regs; +extern volatile struct CMPSS_REGS Cmpss2Regs; +extern volatile struct CMPSS_REGS Cmpss3Regs; +extern volatile struct CMPSS_REGS Cmpss4Regs; +extern volatile struct CMPSS_REGS Cmpss5Regs; +extern volatile struct CMPSS_REGS Cmpss6Regs; +extern volatile struct CMPSS_REGS Cmpss7Regs; +extern volatile struct CMPSS_REGS Cmpss8Regs; +#endif +#ifdef CPU2 +extern volatile struct CMPSS_REGS Cmpss1Regs; +extern volatile struct CMPSS_REGS Cmpss2Regs; +extern volatile struct CMPSS_REGS Cmpss3Regs; +extern volatile struct CMPSS_REGS Cmpss4Regs; +extern volatile struct CMPSS_REGS Cmpss5Regs; +extern volatile struct CMPSS_REGS Cmpss6Regs; +extern volatile struct CMPSS_REGS Cmpss7Regs; +extern volatile struct CMPSS_REGS Cmpss8Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_cputimer.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_cputimer.h new file mode 100644 index 0000000000..f822f516e5 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_cputimer.h @@ -0,0 +1,141 @@ +//########################################################################### +// +// FILE: F2837xD_cputimer.h +// +// TITLE: CPUTIMER Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_CPUTIMER_H__ +#define __F2837xD_CPUTIMER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// CPUTIMER Individual Register Bit Definitions: + +struct TIM_BITS { // bits description + Uint16 LSW:16; // 15:0 CPU-Timer Counter Registers + Uint16 MSW:16; // 31:16 CPU-Timer Counter Registers High +}; + +union TIM_REG { + Uint32 all; + struct TIM_BITS bit; +}; + +struct PRD_BITS { // bits description + Uint16 LSW:16; // 15:0 CPU-Timer Period Registers + Uint16 MSW:16; // 31:16 CPU-Timer Period Registers High +}; + +union PRD_REG { + Uint32 all; + struct PRD_BITS bit; +}; + +struct TCR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 TSS:1; // 4 CPU-Timer stop status bit. + Uint16 TRB:1; // 5 Timer reload + Uint16 rsvd2:4; // 9:6 Reserved + Uint16 SOFT:1; // 10 Emulation modes + Uint16 FREE:1; // 11 Emulation modes + Uint16 rsvd3:2; // 13:12 Reserved + Uint16 TIE:1; // 14 CPU-Timer Interrupt Enable. + Uint16 TIF:1; // 15 CPU-Timer Interrupt Flag. +}; + +union TCR_REG { + Uint16 all; + struct TCR_BITS bit; +}; + +struct TPR_BITS { // bits description + Uint16 TDDR:8; // 7:0 CPU-Timer Divide-Down. + Uint16 PSC:8; // 15:8 CPU-Timer Prescale Counter. +}; + +union TPR_REG { + Uint16 all; + struct TPR_BITS bit; +}; + +struct TPRH_BITS { // bits description + Uint16 TDDRH:8; // 7:0 CPU-Timer Divide-Down. + Uint16 PSCH:8; // 15:8 CPU-Timer Prescale Counter. +}; + +union TPRH_REG { + Uint16 all; + struct TPRH_BITS bit; +}; + +struct CPUTIMER_REGS { + union TIM_REG TIM; // CPU-Timer, Counter Register + union PRD_REG PRD; // CPU-Timer, Period Register + union TCR_REG TCR; // CPU-Timer, Control Register + Uint16 rsvd1; // Reserved + union TPR_REG TPR; // CPU-Timer, Prescale Register + union TPRH_REG TPRH; // CPU-Timer, Prescale Register High +}; + +//--------------------------------------------------------------------------- +// CPUTIMER External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; +#endif +#ifdef CPU2 +extern volatile struct CPUTIMER_REGS CpuTimer0Regs; +extern volatile struct CPUTIMER_REGS CpuTimer1Regs; +extern volatile struct CPUTIMER_REGS CpuTimer2Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_dac.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_dac.h new file mode 100644 index 0000000000..6594bf2334 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_dac.h @@ -0,0 +1,163 @@ +//########################################################################### +// +// FILE: F2837xD_dac.h +// +// TITLE: DAC Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_DAC_H__ +#define __F2837xD_DAC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// DAC Individual Register Bit Definitions: + +struct DACREV_BITS { // bits description + Uint16 REV:8; // 7:0 DAC Revision Register + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union DACREV_REG { + Uint16 all; + struct DACREV_BITS bit; +}; + +struct DACCTL_BITS { // bits description + Uint16 DACREFSEL:1; // 0 DAC Reference Select + Uint16 rsvd1:1; // 1 Reserved + Uint16 LOADMODE:1; // 2 DACVALA Load Mode + Uint16 rsvd2:1; // 3 Reserved + Uint16 SYNCSEL:4; // 7:4 DAC PWMSYNC Select + Uint16 rsvd3:8; // 15:8 Reserved +}; + +union DACCTL_REG { + Uint16 all; + struct DACCTL_BITS bit; +}; + +struct DACVALA_BITS { // bits description + Uint16 DACVALA:12; // 11:0 DAC Active Output Code + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACVALA_REG { + Uint16 all; + struct DACVALA_BITS bit; +}; + +struct DACVALS_BITS { // bits description + Uint16 DACVALS:12; // 11:0 DAC Shadow Output Code + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union DACVALS_REG { + Uint16 all; + struct DACVALS_BITS bit; +}; + +struct DACOUTEN_BITS { // bits description + Uint16 DACOUTEN:1; // 0 DAC Output Code + Uint16 rsvd1:15; // 15:1 Reserved +}; + +union DACOUTEN_REG { + Uint16 all; + struct DACOUTEN_BITS bit; +}; + +struct DACLOCK_BITS { // bits description + Uint16 DACCTL:1; // 0 DAC Control Register Lock + Uint16 DACVAL:1; // 1 DAC Value Register Lock + Uint16 DACOUTEN:1; // 2 DAC Output Enable Register Lock + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union DACLOCK_REG { + Uint16 all; + struct DACLOCK_BITS bit; +}; + +struct DACTRIM_BITS { // bits description + Uint16 OFFSET_TRIM:8; // 7:0 DAC Offset Trim + Uint16 rsvd1:4; // 11:8 Reserved + Uint16 rsvd2:4; // 15:12 Reserved +}; + +union DACTRIM_REG { + Uint16 all; + struct DACTRIM_BITS bit; +}; + +struct DAC_REGS { + union DACREV_REG DACREV; // DAC Revision Register + union DACCTL_REG DACCTL; // DAC Control Register + union DACVALA_REG DACVALA; // DAC Value Register - Active + union DACVALS_REG DACVALS; // DAC Value Register - Shadow + union DACOUTEN_REG DACOUTEN; // DAC Output Enable Register + union DACLOCK_REG DACLOCK; // DAC Lock Register + union DACTRIM_REG DACTRIM; // DAC Trim Register + Uint16 rsvd1; // Reserved +}; + +//--------------------------------------------------------------------------- +// DAC External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct DAC_REGS DacaRegs; +extern volatile struct DAC_REGS DacbRegs; +extern volatile struct DAC_REGS DaccRegs; +#endif +#ifdef CPU2 +extern volatile struct DAC_REGS DacaRegs; +extern volatile struct DAC_REGS DacbRegs; +extern volatile struct DAC_REGS DaccRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_dcsm.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_dcsm.h new file mode 100644 index 0000000000..4ea33d6843 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_dcsm.h @@ -0,0 +1,449 @@ +//########################################################################### +// +// FILE: F2837xD_dcsm.h +// +// TITLE: DCSM Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_DCSM_H__ +#define __F2837xD_DCSM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// DCSM Individual Register Bit Definitions: + +struct Z1_LINKPOINTER_BITS { // bits description + Uint32 LINKPOINTER:29; // 28:0 Zone1 LINK Pointer. + Uint16 rsvd1:3; // 31:29 Reserved +}; + +union Z1_LINKPOINTER_REG { + Uint32 all; + struct Z1_LINKPOINTER_BITS bit; +}; + +struct Z1_OTPSECLOCK_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 PSWDLOCK:4; // 7:4 Zone1 Password Lock. + Uint16 CRCLOCK:4; // 11:8 Zone1 CRC Lock. + Uint16 rsvd2:4; // 15:12 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union Z1_OTPSECLOCK_REG { + Uint32 all; + struct Z1_OTPSECLOCK_BITS bit; +}; + +struct Z1_BOOTCTRL_BITS { // bits description + Uint16 KEY:8; // 7:0 OTP Boot Key + Uint16 BMODE:8; // 15:8 OTP Boot Mode + Uint16 BOOTPIN0:8; // 23:16 OTP Boot Pin 0 Mapping + Uint16 BOOTPIN1:8; // 31:24 OTP Boot Pin 1 Mapping +}; + +union Z1_BOOTCTRL_REG { + Uint32 all; + struct Z1_BOOTCTRL_BITS bit; +}; + +struct Z1_CR_BITS { // bits description + Uint16 rsvd1:3; // 2:0 Reserved + Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros + Uint16 ALLONE:1; // 4 CSMPSWD All Ones + Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY + Uint16 ARMED:1; // 6 CSM Armed + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:7; // 14:8 Reserved + Uint16 FORCESEC:1; // 15 Force Secure +}; + +union Z1_CR_REG { + Uint16 all; + struct Z1_CR_BITS bit; +}; + +struct Z1_GRABSECTR_BITS { // bits description + Uint16 GRAB_SECTA:2; // 1:0 Grab Flash Sector A + Uint16 GRAB_SECTB:2; // 3:2 Grab Flash Sector B + Uint16 GRAB_SECTC:2; // 5:4 Grab Flash Sector C + Uint16 GRAB_SECTD:2; // 7:6 Grab Flash Sector D + Uint16 GRAB_SECTE:2; // 9:8 Grab Flash Sector E + Uint16 GRAB_SECTF:2; // 11:10 Grab Flash Sector F + Uint16 GRAB_SECTG:2; // 13:12 Grab Flash Sector G + Uint16 GRAB_SECTH:2; // 15:14 Grab Flash Sector H + Uint16 GRAB_SECTI:2; // 17:16 Grab Flash Sector I + Uint16 GRAB_SECTJ:2; // 19:18 Grab Flash Sector J + Uint16 GRAB_SECTK:2; // 21:20 Grab Flash Sector K + Uint16 GRAB_SECTL:2; // 23:22 Grab Flash Sector L + Uint16 GRAB_SECTM:2; // 25:24 Grab Flash Sector M + Uint16 GRAB_SECTN:2; // 27:26 Grab Flash Sector N + Uint16 rsvd1:2; // 29:28 Reserved + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union Z1_GRABSECTR_REG { + Uint32 all; + struct Z1_GRABSECTR_BITS bit; +}; + +struct Z1_GRABRAMR_BITS { // bits description + Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 + Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 + Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 + Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 + Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 + Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 + Uint16 GRAB_RAM6:2; // 13:12 Grab RAM D0 + Uint16 GRAB_RAM7:2; // 15:14 Grab RAM D1 + Uint16 rsvd1:12; // 27:16 Reserved + Uint16 GRAB_CLA1:2; // 29:28 Grab CLA1 + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union Z1_GRABRAMR_REG { + Uint32 all; + struct Z1_GRABRAMR_BITS bit; +}; + +struct Z1_EXEONLYSECTR_BITS { // bits description + Uint16 EXEONLY_SECTA:1; // 0 Execute-Only Flash Sector A + Uint16 EXEONLY_SECTB:1; // 1 Execute-Only Flash Sector B + Uint16 EXEONLY_SECTC:1; // 2 Execute-Only Flash Sector C + Uint16 EXEONLY_SECTD:1; // 3 Execute-Only Flash Sector D + Uint16 EXEONLY_SECTE:1; // 4 Execute-Only Flash Sector E + Uint16 EXEONLY_SECTF:1; // 5 Execute-Only Flash Sector F + Uint16 EXEONLY_SECTG:1; // 6 Execute-Only Flash Sector G + Uint16 EXEONLY_SECTH:1; // 7 Execute-Only Flash Sector H + Uint16 EXEONLY_SECTI:1; // 8 Execute-Only Flash Sector I + Uint16 EXEONLY_SECTJ:1; // 9 Execute-Only Flash Sector J + Uint16 EXEONLY_SECTK:1; // 10 Execute-Only Flash Sector K + Uint16 EXEONLY_SECTL:1; // 11 Execute-Only Flash Sector L + Uint16 EXEONLY_SECTM:1; // 12 Execute-Only Flash Sector M + Uint16 EXEONLY_SECTN:1; // 13 Execute-Only Flash Sector N + Uint16 rsvd1:1; // 14 Reserved + Uint16 rsvd2:1; // 15 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union Z1_EXEONLYSECTR_REG { + Uint32 all; + struct Z1_EXEONLYSECTR_BITS bit; +}; + +struct Z1_EXEONLYRAMR_BITS { // bits description + Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 + Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 + Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 + Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 + Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 + Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 + Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM D0 + Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM D1 + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union Z1_EXEONLYRAMR_REG { + Uint32 all; + struct Z1_EXEONLYRAMR_BITS bit; +}; + +struct DCSM_Z1_REGS { + union Z1_LINKPOINTER_REG Z1_LINKPOINTER; // Zone 1 Link Pointer + union Z1_OTPSECLOCK_REG Z1_OTPSECLOCK; // Zone 1 OTP Secure JTAG lock + union Z1_BOOTCTRL_REG Z1_BOOTCTRL; // Boot Mode + Uint32 Z1_LINKPOINTERERR; // Link Pointer Error + Uint16 rsvd1[8]; // Reserved + Uint32 Z1_CSMKEY0; // Zone 1 CSM Key 0 + Uint32 Z1_CSMKEY1; // Zone 1 CSM Key 1 + Uint32 Z1_CSMKEY2; // Zone 1 CSM Key 2 + Uint32 Z1_CSMKEY3; // Zone 1 CSM Key 3 + Uint16 rsvd2; // Reserved + union Z1_CR_REG Z1_CR; // Zone 1 CSM Control Register + union Z1_GRABSECTR_REG Z1_GRABSECTR; // Zone 1 Grab Flash Sectors Register + union Z1_GRABRAMR_REG Z1_GRABRAMR; // Zone 1 Grab RAM Blocks Register + union Z1_EXEONLYSECTR_REG Z1_EXEONLYSECTR; // Zone 1 Flash Execute_Only Sector Register + union Z1_EXEONLYRAMR_REG Z1_EXEONLYRAMR; // Zone 1 RAM Execute_Only Block Register + Uint16 rsvd3; // Reserved +}; + +struct Z2_LINKPOINTER_BITS { // bits description + Uint32 LINKPOINTER:29; // 28:0 Zone2 LINK Pointer. + Uint16 rsvd1:3; // 31:29 Reserved +}; + +union Z2_LINKPOINTER_REG { + Uint32 all; + struct Z2_LINKPOINTER_BITS bit; +}; + +struct Z2_OTPSECLOCK_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 PSWDLOCK:4; // 7:4 Zone2 Password Lock. + Uint16 CRCLOCK:4; // 11:8 Zone2 CRC Lock. + Uint16 rsvd2:4; // 15:12 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union Z2_OTPSECLOCK_REG { + Uint32 all; + struct Z2_OTPSECLOCK_BITS bit; +}; + +struct Z2_BOOTCTRL_BITS { // bits description + Uint16 KEY:8; // 7:0 OTP Boot Key + Uint16 BMODE:8; // 15:8 OTP Boot Mode + Uint16 BOOTPIN0:8; // 23:16 OTP Boot Pin 0 Mapping + Uint16 BOOTPIN1:8; // 31:24 OTP Boot Pin 1 Mapping +}; + +union Z2_BOOTCTRL_REG { + Uint32 all; + struct Z2_BOOTCTRL_BITS bit; +}; + +struct Z2_CR_BITS { // bits description + Uint16 rsvd1:3; // 2:0 Reserved + Uint16 ALLZERO:1; // 3 CSMPSWD All Zeros + Uint16 ALLONE:1; // 4 CSMPSWD All Ones + Uint16 UNSECURE:1; // 5 CSMPSWD Match CSMKEY + Uint16 ARMED:1; // 6 CSM Armed + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:7; // 14:8 Reserved + Uint16 FORCESEC:1; // 15 Force Secure +}; + +union Z2_CR_REG { + Uint16 all; + struct Z2_CR_BITS bit; +}; + +struct Z2_GRABSECTR_BITS { // bits description + Uint16 GRAB_SECTA:2; // 1:0 Grab Flash Sector A + Uint16 GRAB_SECTB:2; // 3:2 Grab Flash Sector B + Uint16 GRAB_SECTC:2; // 5:4 Grab Flash Sector C + Uint16 GRAB_SECTD:2; // 7:6 Grab Flash Sector D + Uint16 GRAB_SECTE:2; // 9:8 Grab Flash Sector E + Uint16 GRAB_SECTF:2; // 11:10 Grab Flash Sector F + Uint16 GRAB_SECTG:2; // 13:12 Grab Flash Sector G + Uint16 GRAB_SECTH:2; // 15:14 Grab Flash Sector H + Uint16 GRAB_SECTI:2; // 17:16 Grab Flash Sector I + Uint16 GRAB_SECTJ:2; // 19:18 Grab Flash Sector J + Uint16 GRAB_SECTK:2; // 21:20 Grab Flash Sector K + Uint16 GRAB_SECTL:2; // 23:22 Grab Flash Sector L + Uint16 GRAB_SECTM:2; // 25:24 Grab Flash Sector M + Uint16 GRAB_SECTN:2; // 27:26 Grab Flash Sector N + Uint16 rsvd1:2; // 29:28 Reserved + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union Z2_GRABSECTR_REG { + Uint32 all; + struct Z2_GRABSECTR_BITS bit; +}; + +struct Z2_GRABRAMR_BITS { // bits description + Uint16 GRAB_RAM0:2; // 1:0 Grab RAM LS0 + Uint16 GRAB_RAM1:2; // 3:2 Grab RAM LS1 + Uint16 GRAB_RAM2:2; // 5:4 Grab RAM LS2 + Uint16 GRAB_RAM3:2; // 7:6 Grab RAM LS3 + Uint16 GRAB_RAM4:2; // 9:8 Grab RAM LS4 + Uint16 GRAB_RAM5:2; // 11:10 Grab RAM LS5 + Uint16 GRAB_RAM6:2; // 13:12 Grab RAM D0 + Uint16 GRAB_RAM7:2; // 15:14 Grab RAM D1 + Uint16 rsvd1:12; // 27:16 Reserved + Uint16 GRAB_CLA1:2; // 29:28 Grab CLA1 + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union Z2_GRABRAMR_REG { + Uint32 all; + struct Z2_GRABRAMR_BITS bit; +}; + +struct Z2_EXEONLYSECTR_BITS { // bits description + Uint16 EXEONLY_SECTA:1; // 0 Execute-Only Flash Sector A + Uint16 EXEONLY_SECTB:1; // 1 Execute-Only Flash Sector B + Uint16 EXEONLY_SECTC:1; // 2 Execute-Only Flash Sector C + Uint16 EXEONLY_SECTD:1; // 3 Execute-Only Flash Sector D + Uint16 EXEONLY_SECTE:1; // 4 Execute-Only Flash Sector E + Uint16 EXEONLY_SECTF:1; // 5 Execute-Only Flash Sector F + Uint16 EXEONLY_SECTG:1; // 6 Execute-Only Flash Sector G + Uint16 EXEONLY_SECTH:1; // 7 Execute-Only Flash Sector H + Uint16 EXEONLY_SECTI:1; // 8 Execute-Only Flash Sector I + Uint16 EXEONLY_SECTJ:1; // 9 Execute-Only Flash Sector J + Uint16 EXEONLY_SECTK:1; // 10 Execute-Only Flash Sector K + Uint16 EXEONLY_SECTL:1; // 11 Execute-Only Flash Sector L + Uint16 EXEONLY_SECTM:1; // 12 Execute-Only Flash Sector M + Uint16 EXEONLY_SECTN:1; // 13 Execute-Only Flash Sector N + Uint16 rsvd1:1; // 14 Reserved + Uint16 rsvd2:1; // 15 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union Z2_EXEONLYSECTR_REG { + Uint32 all; + struct Z2_EXEONLYSECTR_BITS bit; +}; + +struct Z2_EXEONLYRAMR_BITS { // bits description + Uint16 EXEONLY_RAM0:1; // 0 Execute-Only RAM LS0 + Uint16 EXEONLY_RAM1:1; // 1 Execute-Only RAM LS1 + Uint16 EXEONLY_RAM2:1; // 2 Execute-Only RAM LS2 + Uint16 EXEONLY_RAM3:1; // 3 Execute-Only RAM LS3 + Uint16 EXEONLY_RAM4:1; // 4 Execute-Only RAM LS4 + Uint16 EXEONLY_RAM5:1; // 5 Execute-Only RAM LS5 + Uint16 EXEONLY_RAM6:1; // 6 Execute-Only RAM D0 + Uint16 EXEONLY_RAM7:1; // 7 Execute-Only RAM D1 + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union Z2_EXEONLYRAMR_REG { + Uint32 all; + struct Z2_EXEONLYRAMR_BITS bit; +}; + +struct DCSM_Z2_REGS { + union Z2_LINKPOINTER_REG Z2_LINKPOINTER; // Zone 2 Link Pointer + union Z2_OTPSECLOCK_REG Z2_OTPSECLOCK; // Zone 2 OTP Secure JTAG lock + union Z2_BOOTCTRL_REG Z2_BOOTCTRL; // Boot Mode + Uint32 Z2_LINKPOINTERERR; // Link Pointer Error + Uint16 rsvd1[8]; // Reserved + Uint32 Z2_CSMKEY0; // Zone 2 CSM Key 0 + Uint32 Z2_CSMKEY1; // Zone 2 CSM Key 1 + Uint32 Z2_CSMKEY2; // Zone 2 CSM Key 2 + Uint32 Z2_CSMKEY3; // Zone 2 CSM Key 3 + Uint16 rsvd2; // Reserved + union Z2_CR_REG Z2_CR; // Zone 2 CSM Control Register + union Z2_GRABSECTR_REG Z2_GRABSECTR; // Zone 2 Grab Flash Sectors Register + union Z2_GRABRAMR_REG Z2_GRABRAMR; // Zone 2 Grab RAM Blocks Register + union Z2_EXEONLYSECTR_REG Z2_EXEONLYSECTR; // Zone 2 Flash Execute_Only Sector Register + union Z2_EXEONLYRAMR_REG Z2_EXEONLYRAMR; // Zone 2 RAM Execute_Only Block Register + Uint16 rsvd3; // Reserved +}; + +struct FLSEM_BITS { // bits description + Uint16 SEM:2; // 1:0 Flash Semaphore Bit + Uint16 rsvd1:6; // 7:2 Reserved + Uint16 KEY:8; // 15:8 Semaphore Key + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FLSEM_REG { + Uint32 all; + struct FLSEM_BITS bit; +}; + +struct SECTSTAT_BITS { // bits description + Uint16 STATUS_SECTA:2; // 1:0 Zone Status Flash Sector A + Uint16 STATUS_SECTB:2; // 3:2 Zone Status Flash Sector B + Uint16 STATUS_SECTC:2; // 5:4 Zone Status Flash Sector C + Uint16 STATUS_SECTD:2; // 7:6 Zone Status Flash Sector D + Uint16 STATUS_SECTE:2; // 9:8 Zone Status Flash Sector E + Uint16 STATUS_SECTF:2; // 11:10 Zone Status Flash Sector F + Uint16 STATUS_SECTG:2; // 13:12 Zone Status Flash Sector G + Uint16 STATUS_SECTH:2; // 15:14 Zone Status Flash Sector H + Uint16 STATUS_SECTI:2; // 17:16 Zone Status Flash Sector I + Uint16 STATUS_SECTJ:2; // 19:18 Zone Status Flash Sector J + Uint16 STATUS_SECTK:2; // 21:20 Zone Status Flash Sector K + Uint16 STATUS_SECTL:2; // 23:22 Zone Status Flash Sector L + Uint16 STATUS_SECTM:2; // 25:24 Zone Status Flash Sector M + Uint16 STATUS_SECTN:2; // 27:26 Zone Status Flash Sector N + Uint16 rsvd1:2; // 29:28 Reserved + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union SECTSTAT_REG { + Uint32 all; + struct SECTSTAT_BITS bit; +}; + +struct RAMSTAT_BITS { // bits description + Uint16 STATUS_RAM0:2; // 1:0 Zone Status RAM LS0 + Uint16 STATUS_RAM1:2; // 3:2 Zone Status RAM LS1 + Uint16 STATUS_RAM2:2; // 5:4 Zone Status RAM LS2 + Uint16 STATUS_RAM3:2; // 7:6 Zone Status RAM LS3 + Uint16 STATUS_RAM4:2; // 9:8 Zone Status RAM LS4 + Uint16 STATUS_RAM5:2; // 11:10 Zone Status RAM LS5 + Uint16 STATUS_RAM6:2; // 13:12 Zone Status RAM D0 + Uint16 STATUS_RAM7:2; // 15:14 Zone Status RAM D1 + Uint16 rsvd1:12; // 27:16 Reserved + Uint16 STATUS_CLA1:2; // 29:28 Zone Status CLA1 + Uint16 rsvd2:2; // 31:30 Reserved +}; + +union RAMSTAT_REG { + Uint32 all; + struct RAMSTAT_BITS bit; +}; + +struct DCSM_COMMON_REGS { + union FLSEM_REG FLSEM; // Flash Wrapper Semaphore Register + union SECTSTAT_REG SECTSTAT; // Sectors Status Register + union RAMSTAT_REG RAMSTAT; // RAM Status Register + Uint16 rsvd1[2]; // Reserved +}; + +//--------------------------------------------------------------------------- +// DCSM External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct DCSM_Z1_REGS DcsmZ1Regs; +extern volatile struct DCSM_Z2_REGS DcsmZ2Regs; +extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs; +#endif +#ifdef CPU2 +extern volatile struct DCSM_Z1_REGS DcsmZ1Regs; +extern volatile struct DCSM_Z2_REGS DcsmZ2Regs; +extern volatile struct DCSM_COMMON_REGS DcsmCommonRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_device.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_device.h new file mode 100644 index 0000000000..58aee28ebb --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_device.h @@ -0,0 +1,345 @@ +//########################################################################### +// +// FILE: F2837xD_device.h +// +// TITLE: F2837xD Device Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_DEVICE_H +#define F2837xD_DEVICE_H + +#if (!defined(CPU1) && !defined(CPU2)) +#error "You must define CPU1 or CPU2 in your project properties. Otherwise, the offsets in your header files will be inaccurate." +#endif + +#if (defined(CPU1) && defined(CPU2)) +#error "You have defined both CPU1 and CPU2 in your project properties. Only a single CPU should be defined." +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define TARGET 1 + +// +// User To Select Target Device: +// +#define F28_2837xD TARGET + +// +// Common CPU Definitions: +// +extern __cregister volatile unsigned int IFR; +extern __cregister volatile unsigned int IER; + +#define EINT __asm(" clrc INTM") +#define DINT __asm(" setc INTM") +#define ERTM __asm(" clrc DBGM") +#define DRTM __asm(" setc DBGM") +#ifndef EALLOW +#define EALLOW __asm(" EALLOW") +#endif +#ifndef EDIS +#define EDIS __asm(" EDIS") +#endif +#define ESTOP0 __asm(" ESTOP0") + +#define M_INT1 0x0001 +#define M_INT2 0x0002 +#define M_INT3 0x0004 +#define M_INT4 0x0008 +#define M_INT5 0x0010 +#define M_INT6 0x0020 +#define M_INT7 0x0040 +#define M_INT8 0x0080 +#define M_INT9 0x0100 +#define M_INT10 0x0200 +#define M_INT11 0x0400 +#define M_INT12 0x0800 +#define M_INT13 0x1000 +#define M_INT14 0x2000 +#define M_DLOG 0x4000 +#define M_RTOS 0x8000 + +#ifndef C28X_BIT0 +#define C28X_BIT0 0x00000001 +#endif + +#ifndef C28X_BIT1 +#define C28X_BIT1 0x00000002 +#endif + +#ifndef C28X_BIT2 +#define C28X_BIT2 0x00000004 +#endif + +#ifndef C28X_BIT3 +#define C28X_BIT3 0x00000008 +#endif + +#ifndef C28X_BIT4 +#define C28X_BIT4 0x00000010 +#endif + +#ifndef C28X_BIT5 +#define C28X_BIT5 0x00000020 +#endif + +#ifndef C28X_BIT6 +#define C28X_BIT6 0x00000040 +#endif + +#ifndef C28X_BIT7 +#define C28X_BIT7 0x00000080 +#endif + +#ifndef C28X_BIT8 +#define C28X_BIT8 0x00000100 +#endif + +#ifndef C28X_BIT9 +#define C28X_BIT9 0x00000200 +#endif + +#ifndef C28X_BIT10 +#define C28X_BIT10 0x00000400 +#endif + +#ifndef C28X_BIT11 +#define C28X_BIT11 0x00000800 +#endif + +#ifndef C28X_BIT12 +#define C28X_BIT12 0x00001000 +#endif + +#ifndef C28X_BIT13 +#define C28X_BIT13 0x00002000 +#endif + +#ifndef C28X_BIT14 +#define C28X_BIT14 0x00004000 +#endif + +#ifndef C28X_BIT15 +#define C28X_BIT15 0x00008000 +#endif + +#ifndef C28X_BIT16 +#define C28X_BIT16 0x00010000 +#endif + +#ifndef C28X_BIT17 +#define C28X_BIT17 0x00020000 +#endif + +#ifndef C28X_BIT18 +#define C28X_BIT18 0x00040000 +#endif + +#ifndef C28X_BIT19 +#define C28X_BIT19 0x00080000 +#endif + +#ifndef C28X_BIT20 +#define C28X_BIT20 0x00100000 +#endif + +#ifndef C28X_BIT21 +#define C28X_BIT21 0x00200000 +#endif + +#ifndef C28X_BIT22 +#define C28X_BIT22 0x00400000 +#endif + +#ifndef C28X_BIT23 +#define C28X_BIT23 0x00800000 +#endif + +#ifndef C28X_BIT24 +#define C28X_BIT24 0x01000000 +#endif + +#ifndef C28X_BIT25 +#define C28X_BIT25 0x02000000 +#endif + +#ifndef C28X_BIT26 +#define C28X_BIT26 0x04000000 +#endif + +#ifndef C28X_BIT27 +#define C28X_BIT27 0x08000000 +#endif + +#ifndef C28X_BIT28 +#define C28X_BIT28 0x10000000 +#endif + +#ifndef C28X_BIT29 +#define C28X_BIT29 0x20000000 +#endif + +#ifndef C28X_BIT30 +#define C28X_BIT30 0x40000000 +#endif + +#ifndef C28X_BIT31 +#define C28X_BIT31 0x80000000 +#endif + +// +// For Portability, User Is Recommended To Use the C99 Standard integer types +// +#if !defined(__TMS320C28XX_CLA__) +#include +#include +#endif //__TMS320C28XX_CLA__ +#include +#include +#include + +// +// C++ Bool Compatibility +// +#if defined(__cplusplus) +typedef bool _Bool; +#endif + +// +// C99 defines boolean type to be _Bool, but this doesn't match the format of +// the other standard integer types. bool_t has been defined to fill this gap. +// +typedef _Bool bool_t; + +// +//used for a bool function return status +// +typedef _Bool status_t; + +#ifndef SUCCESS +#define SUCCESS true +#endif + +#ifndef FAIL +#define FAIL false +#endif + +// +// The following data types are included for compatibility with legacy code, +// they are not recommended for use in new software. Please use the C99 +// types included above +// +#ifndef DSP28_DATA_TYPES +#define DSP28_DATA_TYPES +typedef int int16; +typedef long int32; +typedef long long int64; +typedef unsigned int Uint16; +typedef unsigned long Uint32; +typedef unsigned long long Uint64; +typedef float float32; +typedef long double float64; +#endif + +// +// The following data types are for use with byte addressable peripherals. +// See compiler documentation on the byte_peripheral type attribute. +// +#ifndef __TMS320C28XX_CLA__ +#if __TI_COMPILER_VERSION__ >= 16006000 +typedef unsigned int bp_16 __attribute__((byte_peripheral)); +typedef unsigned long bp_32 __attribute__((byte_peripheral)); +#endif +#endif + +// +// Include All Peripheral Header Files: +// +#include "F2837xD_adc.h" +#include "F2837xD_analogsubsys.h" +#include "F2837xD_cla.h" +#include "F2837xD_cmpss.h" +#include "F2837xD_cputimer.h" +#include "F2837xD_dac.h" +#include "F2837xD_dcsm.h" +#include "F2837xD_dma.h" +#include "F2837xD_ecap.h" +#include "F2837xD_emif.h" +#include "F2837xD_epwm.h" // Enhanced PWM +#include "F2837xD_epwm_xbar.h" +#include "F2837xD_eqep.h" +#include "F2837xD_flash.h" +#include "F2837xD_gpio.h" // General Purpose I/O Registers +#include "F2837xD_i2c.h" +#include "F2837xD_input_xbar.h" +#include "F2837xD_ipc.h" +#include "F2837xD_mcbsp.h" +#include "F2837xD_memconfig.h" +#include "F2837xD_nmiintrupt.h" // NMI Interrupt Registers +#include "F2837xD_output_xbar.h" +#include "F2837xD_piectrl.h" // PIE Control Registers +#include "F2837xD_pievect.h" +#include "F2837xD_sci.h" +#include "F2837xD_sdfm.h" +#include "F2837xD_spi.h" +#include "F2837xD_sysctrl.h" // System Control/Power Modes +#include "F2837xD_upp.h" +#include "F2837xD_xbar.h" +#include "F2837xD_xint.h" // External Interrupts + +// +// byte_peripheral attribute is only supported on the C28 +// +#ifndef __TMS320C28XX_CLA__ +#if __TI_COMPILER_VERSION__ >= 16006000 +#include "F2837xD_can.h" +#endif +#endif + +#ifdef __cplusplus +} +#endif // extern "C" + +#endif // end of F2837xD_DEVICE_H definition + +// +// End of file. +// diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_dma.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_dma.h new file mode 100644 index 0000000000..3de5b3ca0f --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_dma.h @@ -0,0 +1,214 @@ +//########################################################################### +// +// FILE: F2837xD_dma.h +// +// TITLE: DMA Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_DMA_H__ +#define __F2837xD_DMA_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// DMA Individual Register Bit Definitions: + +struct MODE_BITS { // bits description + Uint16 PERINTSEL:5; // 4:0 Peripheral Interrupt and Sync Select + Uint16 rsvd1:2; // 6:5 Reserved + Uint16 OVRINTE:1; // 7 Overflow Interrupt Enable + Uint16 PERINTE:1; // 8 Peripheral Interrupt Enable + Uint16 CHINTMODE:1; // 9 Channel Interrupt Mode + Uint16 ONESHOT:1; // 10 One Shot Mode Bit + Uint16 CONTINUOUS:1; // 11 Continuous Mode Bit + Uint16 rsvd2:2; // 13:12 Reserved + Uint16 DATASIZE:1; // 14 Data Size Mode Bit + Uint16 CHINTE:1; // 15 Channel Interrupt Enable Bit +}; + +union MODE_REG { + Uint16 all; + struct MODE_BITS bit; +}; + +struct CONTROL_BITS { // bits description + Uint16 RUN:1; // 0 Run Bit + Uint16 HALT:1; // 1 Halt Bit + Uint16 SOFTRESET:1; // 2 Soft Reset Bit + Uint16 PERINTFRC:1; // 3 Interrupt Force Bit + Uint16 PERINTCLR:1; // 4 Interrupt Clear Bit + Uint16 rsvd2:2; // 6:5 Reserved + Uint16 ERRCLR:1; // 7 Error Clear Bit + Uint16 PERINTFLG:1; // 8 Interrupt Flag Bit + Uint16 SYNCFLG:1; // 9 Sync Flag Bit + Uint16 SYNCERR:1; // 10 Sync Error Flag Bit + Uint16 TRANSFERSTS:1; // 11 Transfer Status Bit + Uint16 BURSTSTS:1; // 12 Burst Status Bit + Uint16 RUNSTS:1; // 13 Run Status Bit + Uint16 OVRFLG:1; // 14 Overflow Flag Bit + Uint16 rsvd1:1; // 15 Reserved +}; + +union CONTROL_REG { + Uint16 all; + struct CONTROL_BITS bit; +}; + +struct DMACTRL_BITS { // bits description + Uint16 HARDRESET:1; // 0 Hard Reset Bit + Uint16 PRIORITYRESET:1; // 1 Priority Reset Bit + Uint16 rsvd1:14; // 15:2 Reserved +}; + +union DMACTRL_REG { + Uint16 all; + struct DMACTRL_BITS bit; +}; + +struct DEBUGCTRL_BITS { // bits description + Uint16 rsvd1:15; // 14:0 Reserved + Uint16 FREE:1; // 15 Debug Mode Bit +}; + +union DEBUGCTRL_REG { + Uint16 all; + struct DEBUGCTRL_BITS bit; +}; + +struct PRIORITYCTRL1_BITS { // bits description + Uint16 CH1PRIORITY:1; // 0 Ch1 Priority Bit + Uint16 rsvd1:15; // 15:1 Reserved +}; + +union PRIORITYCTRL1_REG { + Uint16 all; + struct PRIORITYCTRL1_BITS bit; +}; + +struct PRIORITYSTAT_BITS { // bits description + Uint16 ACTIVESTS:3; // 2:0 Active Channel Status Bits + Uint16 rsvd1:1; // 3 Reserved + Uint16 ACTIVESTS_SHADOW:3; // 6:4 Active Channel Status Shadow Bits + Uint16 rsvd2:9; // 15:7 Reserved +}; + +union PRIORITYSTAT_REG { + Uint16 all; + struct PRIORITYSTAT_BITS bit; +}; + +struct BURST_SIZE_BITS { // bits description + Uint16 BURSTSIZE:5; // 4:0 Burst Transfer Size + Uint16 rsvd1:11; // 15:5 Reserved +}; + +union BURST_SIZE_REG { + Uint16 all; + struct BURST_SIZE_BITS bit; +}; + +struct BURST_COUNT_BITS { // bits description + Uint16 BURSTCOUNT:5; // 4:0 Burst Transfer Count + Uint16 rsvd1:11; // 15:5 Reserved +}; + +union BURST_COUNT_REG { + Uint16 all; + struct BURST_COUNT_BITS bit; +}; + +struct CH_REGS { + union MODE_REG MODE; // Mode Register + union CONTROL_REG CONTROL; // Control Register + union BURST_SIZE_REG BURST_SIZE; // Burst Size Register + union BURST_COUNT_REG BURST_COUNT; // Burst Count Register + int16 SRC_BURST_STEP; // Source Burst Step Register + int16 DST_BURST_STEP; // Destination Burst Step Register + Uint16 TRANSFER_SIZE; // Transfer Size Register + Uint16 TRANSFER_COUNT; // Transfer Count Register + int16 SRC_TRANSFER_STEP; // Source Transfer Step Register + int16 DST_TRANSFER_STEP; // Destination Transfer Step Register + Uint16 SRC_WRAP_SIZE; // Source Wrap Size Register + Uint16 SRC_WRAP_COUNT; // Source Wrap Count Register + int16 SRC_WRAP_STEP; // Source Wrap Step Register + Uint16 DST_WRAP_SIZE; // Destination Wrap Size Register + Uint16 DST_WRAP_COUNT; // Destination Wrap Count Register + int16 DST_WRAP_STEP; // Destination Wrap Step Register + Uint32 SRC_BEG_ADDR_SHADOW; // Source Begin Address Shadow Register + Uint32 SRC_ADDR_SHADOW; // Source Address Shadow Register + Uint32 SRC_BEG_ADDR_ACTIVE; // Source Begin Address Active Register + Uint32 SRC_ADDR_ACTIVE; // Source Address Active Register + Uint32 DST_BEG_ADDR_SHADOW; // Destination Begin Address Shadow Register + Uint32 DST_ADDR_SHADOW; // Destination Address Shadow Register + Uint32 DST_BEG_ADDR_ACTIVE; // Destination Begin Address Active Register + Uint32 DST_ADDR_ACTIVE; // Destination Address Active Register +}; + +struct DMA_REGS { + union DMACTRL_REG DMACTRL; // DMA Control Register + union DEBUGCTRL_REG DEBUGCTRL; // Debug Control Register + Uint16 rsvd0; // Reserved + Uint16 rsvd1; // Reserved + union PRIORITYCTRL1_REG PRIORITYCTRL1; // Priority Control 1 Register + Uint16 rsvd2; // Reserved + union PRIORITYSTAT_REG PRIORITYSTAT; // Priority Status Register + Uint16 rsvd3[25]; // Reserved + struct CH_REGS CH1; // DMA Channel 1 Registers + struct CH_REGS CH2; // DMA Channel 2 Registers + struct CH_REGS CH3; // DMA Channel 3 Registers + struct CH_REGS CH4; // DMA Channel 4 Registers + struct CH_REGS CH5; // DMA Channel 5 Registers + struct CH_REGS CH6; // DMA Channel 6 Registers +}; + +//--------------------------------------------------------------------------- +// DMA External References & Function Declarations: +// +extern volatile struct DMA_REGS DmaRegs; +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_ecap.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_ecap.h new file mode 100644 index 0000000000..1fdeb15ec3 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_ecap.h @@ -0,0 +1,203 @@ +//########################################################################### +// +// FILE: F2837xD_ecap.h +// +// TITLE: ECAP Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_ECAP_H__ +#define __F2837xD_ECAP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// ECAP Individual Register Bit Definitions: + +struct ECCTL1_BITS { // bits description + Uint16 CAP1POL:1; // 0 Capture Event 1 Polarity select + Uint16 CTRRST1:1; // 1 Counter Reset on Capture Event 1 + Uint16 CAP2POL:1; // 2 Capture Event 2 Polarity select + Uint16 CTRRST2:1; // 3 Counter Reset on Capture Event 2 + Uint16 CAP3POL:1; // 4 Capture Event 3 Polarity select + Uint16 CTRRST3:1; // 5 Counter Reset on Capture Event 3 + Uint16 CAP4POL:1; // 6 Capture Event 4 Polarity select + Uint16 CTRRST4:1; // 7 Counter Reset on Capture Event 4 + Uint16 CAPLDEN:1; // 8 Enable Loading CAP1-4 regs on a Cap Event + Uint16 PRESCALE:5; // 13:9 Event Filter prescale select + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union ECCTL1_REG { + Uint16 all; + struct ECCTL1_BITS bit; +}; + +struct ECCTL2_BITS { // bits description + Uint16 CONT_ONESHT:1; // 0 Continuous or one-shot + Uint16 STOP_WRAP:2; // 2:1 Stop value for one-shot, Wrap for continuous + Uint16 REARM:1; // 3 One-shot re-arm + Uint16 TSCTRSTOP:1; // 4 TSCNT counter stop + Uint16 SYNCI_EN:1; // 5 Counter sync-in select + Uint16 SYNCO_SEL:2; // 7:6 Sync-out mode + Uint16 SWSYNC:1; // 8 SW forced counter sync + Uint16 CAP_APWM:1; // 9 CAP/APWM operating mode select + Uint16 APWMPOL:1; // 10 APWM output polarity select + Uint16 rsvd1:5; // 15:11 Reserved +}; + +union ECCTL2_REG { + Uint16 all; + struct ECCTL2_BITS bit; +}; + +struct ECEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Enable + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Enable + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Enable + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Enable + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Enable + Uint16 CTR_EQ_PRD:1; // 6 Period Equal Interrupt Enable + Uint16 CTR_EQ_CMP:1; // 7 Compare Equal Interrupt Enable + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union ECEINT_REG { + Uint16 all; + struct ECEINT_BITS bit; +}; + +struct ECFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Flag + Uint16 CEVT1:1; // 1 Capture Event 1 Interrupt Flag + Uint16 CEVT2:1; // 2 Capture Event 2 Interrupt Flag + Uint16 CEVT3:1; // 3 Capture Event 3 Interrupt Flag + Uint16 CEVT4:1; // 4 Capture Event 4 Interrupt Flag + Uint16 CTROVF:1; // 5 Counter Overflow Interrupt Flag + Uint16 CTR_PRD:1; // 6 Period Equal Interrupt Flag + Uint16 CTR_CMP:1; // 7 Compare Equal Interrupt Flag + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union ECFLG_REG { + Uint16 all; + struct ECFLG_BITS bit; +}; + +struct ECCLR_BITS { // bits description + Uint16 INT:1; // 0 ECAP Global Interrupt Status Clear + Uint16 CEVT1:1; // 1 Capture Event 1 Status Clear + Uint16 CEVT2:1; // 2 Capture Event 2 Status Clear + Uint16 CEVT3:1; // 3 Capture Event 3 Status Clear + Uint16 CEVT4:1; // 4 Capture Event 4 Status Clear + Uint16 CTROVF:1; // 5 Counter Overflow Status Clear + Uint16 CTR_PRD:1; // 6 Period Equal Status Clear + Uint16 CTR_CMP:1; // 7 Compare Equal Status Clear + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union ECCLR_REG { + Uint16 all; + struct ECCLR_BITS bit; +}; + +struct ECFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CEVT1:1; // 1 Capture Event 1 Force Interrupt + Uint16 CEVT2:1; // 2 Capture Event 2 Force Interrupt + Uint16 CEVT3:1; // 3 Capture Event 3 Force Interrupt + Uint16 CEVT4:1; // 4 Capture Event 4 Force Interrupt + Uint16 CTROVF:1; // 5 Counter Overflow Force Interrupt + Uint16 CTR_PRD:1; // 6 Period Equal Force Interrupt + Uint16 CTR_CMP:1; // 7 Compare Equal Force Interrupt + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union ECFRC_REG { + Uint16 all; + struct ECFRC_BITS bit; +}; + +struct ECAP_REGS { + Uint32 TSCTR; // Time-Stamp Counter + Uint32 CTRPHS; // Counter Phase Offset Value Register + Uint32 CAP1; // Capture 1 Register + Uint32 CAP2; // Capture 2 Register + Uint32 CAP3; // Capture 3 Register + Uint32 CAP4; // Capture 4 Register + Uint16 rsvd1[8]; // Reserved + union ECCTL1_REG ECCTL1; // Capture Control Register 1 + union ECCTL2_REG ECCTL2; // Capture Control Register 2 + union ECEINT_REG ECEINT; // Capture Interrupt Enable Register + union ECFLG_REG ECFLG; // Capture Interrupt Flag Register + union ECCLR_REG ECCLR; // Capture Interrupt Clear Register + union ECFRC_REG ECFRC; // Capture Interrupt Force Register + Uint16 rsvd2[6]; // Reserved +}; + +//--------------------------------------------------------------------------- +// ECAP External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; +#endif +#ifdef CPU2 +extern volatile struct ECAP_REGS ECap1Regs; +extern volatile struct ECAP_REGS ECap2Regs; +extern volatile struct ECAP_REGS ECap3Regs; +extern volatile struct ECAP_REGS ECap4Regs; +extern volatile struct ECAP_REGS ECap5Regs; +extern volatile struct ECAP_REGS ECap6Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_emif.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_emif.h new file mode 100644 index 0000000000..c3246b567c --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_emif.h @@ -0,0 +1,302 @@ +//########################################################################### +// +// FILE: F2837xD_emif.h +// +// TITLE: EMIF Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_EMIF_H__ +#define __F2837xD_EMIF_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// EMIF Individual Register Bit Definitions: + +struct RCSR_BITS { // bits description + Uint16 MINOR_REVISION:8; // 7:0 Minor Revision. + Uint16 MAJOR_REVISION:8; // 15:8 Major Revision. + Uint16 MODULE_ID:14; // 29:16 EMIF module ID. + Uint16 FR:1; // 30 EMIF is running in full rate or half rate. + Uint16 BE:1; // 31 EMIF endian mode. +}; + +union RCSR_REG { + Uint32 all; + struct RCSR_BITS bit; +}; + +struct ASYNC_WCCR_BITS { // bits description + Uint16 MAX_EXT_WAIT:8; // 7:0 Maximum Extended Wait cycles. + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:2; // 17:16 Reserved + Uint16 rsvd3:2; // 19:18 Reserved + Uint16 rsvd4:2; // 21:20 Reserved + Uint16 rsvd5:2; // 23:22 Reserved + Uint16 rsvd6:4; // 27:24 Reserved + Uint16 WP0:1; // 28 Polarity for EMxWAIT. + Uint16 rsvd7:1; // 29 Reserved + Uint16 rsvd8:1; // 30 Reserved + Uint16 rsvd9:1; // 31 Reserved +}; + +union ASYNC_WCCR_REG { + Uint32 all; + struct ASYNC_WCCR_BITS bit; +}; + +struct SDRAM_CR_BITS { // bits description + Uint16 PAGESIGE:3; // 2:0 Page Size. + Uint16 rsvd1:1; // 3 Reserved + Uint16 IBANK:3; // 6:4 Internal Bank setup of SDRAM devices. + Uint16 rsvd2:1; // 7 Reserved + Uint16 BIT_11_9_LOCK:1; // 8 Bits 11 to 9 are writable only if this bit is set. + Uint16 CL:3; // 11:9 CAS Latency. + Uint16 rsvd3:1; // 12 Reserved + Uint16 rsvd4:1; // 13 Reserved + Uint16 NM:1; // 14 Narrow Mode. + Uint16 rsvd5:1; // 15 Reserved + Uint16 rsvd6:1; // 16 Reserved + Uint16 rsvd7:2; // 18:17 Reserved + Uint16 rsvd8:1; // 19 Reserved + Uint16 rsvd9:3; // 22:20 Reserved + Uint16 rsvd10:3; // 25:23 Reserved + Uint16 rsvd11:3; // 28:26 Reserved + Uint16 PDWR:1; // 29 Perform refreshes during Power Down. + Uint16 PD:1; // 30 Power Down. + Uint16 SR:1; // 31 Self Refresh. +}; + +union SDRAM_CR_REG { + Uint32 all; + struct SDRAM_CR_BITS bit; +}; + +struct SDRAM_RCR_BITS { // bits description + Uint16 REFRESH_RATE:13; // 12:0 Refresh Rate. + Uint16 rsvd1:3; // 15:13 Reserved + Uint16 rsvd2:3; // 18:16 Reserved + Uint16 rsvd3:13; // 31:19 Reserved +}; + +union SDRAM_RCR_REG { + Uint32 all; + struct SDRAM_RCR_BITS bit; +}; + +struct ASYNC_CS2_CR_BITS { // bits description + Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. + Uint16 TA:2; // 3:2 Turn Around cycles. + Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. + Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. + Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. + Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. + Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. + Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. + Uint16 EW:1; // 30 Extend Wait mode. + Uint16 SS:1; // 31 Select Strobe mode. +}; + +union ASYNC_CS2_CR_REG { + Uint32 all; + struct ASYNC_CS2_CR_BITS bit; +}; + +struct ASYNC_CS3_CR_BITS { // bits description + Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. + Uint16 TA:2; // 3:2 Turn Around cycles. + Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. + Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. + Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. + Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. + Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. + Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. + Uint16 EW:1; // 30 Extend Wait mode. + Uint16 SS:1; // 31 Select Strobe mode. +}; + +union ASYNC_CS3_CR_REG { + Uint32 all; + struct ASYNC_CS3_CR_BITS bit; +}; + +struct ASYNC_CS4_CR_BITS { // bits description + Uint16 ASIZE:2; // 1:0 Asynchronous Memory Size. + Uint16 TA:2; // 3:2 Turn Around cycles. + Uint16 R_HOLD:3; // 6:4 Read Strobe Hold cycles. + Uint16 R_STROBE:6; // 12:7 Read Strobe Duration cycles. + Uint32 R_SETUP:4; // 16:13 Read Strobe Setup cycles. + Uint16 W_HOLD:3; // 19:17 Write Strobe Hold cycles. + Uint16 W_STROBE:6; // 25:20 Write Strobe Duration cycles. + Uint16 W_SETUP:4; // 29:26 Write Strobe Setup cycles. + Uint16 EW:1; // 30 Extend Wait mode. + Uint16 SS:1; // 31 Select Strobe mode. +}; + +union ASYNC_CS4_CR_REG { + Uint32 all; + struct ASYNC_CS4_CR_BITS bit; +}; + +struct SDRAM_TR_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 T_RRD:3; // 6:4 Activate to Activate timing for different bank. + Uint16 rsvd2:1; // 7 Reserved + Uint16 T_RC:4; // 11:8 Activate to Activate timing . + Uint16 T_RAS:4; // 15:12 Activate to Precharge timing. + Uint16 T_WR:3; // 18:16 Last Write to Precharge timing. + Uint16 rsvd3:1; // 19 Reserved + Uint16 T_RCD:3; // 22:20 Activate to Read/Write timing. + Uint16 rsvd4:1; // 23 Reserved + Uint16 T_RP:3; // 26:24 Precharge to Activate/Refresh timing. + Uint16 T_RFC:5; // 31:27 Refresh/Load Mode to Refresh/Activate timing +}; + +union SDRAM_TR_REG { + Uint32 all; + struct SDRAM_TR_BITS bit; +}; + +struct SDR_EXT_TMNG_BITS { // bits description + Uint16 T_XS:5; // 4:0 Self Refresh exit to new command timing. + Uint16 rsvd1:11; // 15:5 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SDR_EXT_TMNG_REG { + Uint32 all; + struct SDR_EXT_TMNG_BITS bit; +}; + +struct INT_RAW_BITS { // bits description + Uint16 AT:1; // 0 Asynchronous Timeout. + Uint16 LT:1; // 1 Line Trap. + Uint16 WR:4; // 5:2 Wait Rise. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union INT_RAW_REG { + Uint32 all; + struct INT_RAW_BITS bit; +}; + +struct INT_MSK_BITS { // bits description + Uint16 AT_MASKED:1; // 0 Asynchronous Timeout. + Uint16 LT_MASKED:1; // 1 Line Trap. + Uint16 WR_MASKED:4; // 5:2 Wait Rise. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union INT_MSK_REG { + Uint32 all; + struct INT_MSK_BITS bit; +}; + +struct INT_MSK_SET_BITS { // bits description + Uint16 AT_MASK_SET:1; // 0 Asynchronous Timeout. + Uint16 LT_MASK_SET:1; // 1 Line Trap. + Uint16 WR_MASK_SET:4; // 5:2 Wait Rise. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union INT_MSK_SET_REG { + Uint32 all; + struct INT_MSK_SET_BITS bit; +}; + +struct INT_MSK_CLR_BITS { // bits description + Uint16 AT_MASK_CLR:1; // 0 Asynchronous Timeout. + Uint16 LT_MASK_CLR:1; // 1 Line Trap. + Uint16 WR_MASK_CLR:4; // 5:2 Wait Rise. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union INT_MSK_CLR_REG { + Uint32 all; + struct INT_MSK_CLR_BITS bit; +}; + +struct EMIF_REGS { + union RCSR_REG RCSR; // Revision Code and Status Register + union ASYNC_WCCR_REG ASYNC_WCCR; // Async Wait Cycle Config Register + union SDRAM_CR_REG SDRAM_CR; // SDRAM (EMxCS0n) Config Register + union SDRAM_RCR_REG SDRAM_RCR; // SDRAM Refresh Control Register + union ASYNC_CS2_CR_REG ASYNC_CS2_CR; // Async 1 (EMxCS2n) Config Register + union ASYNC_CS3_CR_REG ASYNC_CS3_CR; // Async 2 (EMxCS3n) Config Register + union ASYNC_CS4_CR_REG ASYNC_CS4_CR; // Async 3 (EMxCS4n) Config Register + Uint16 rsvd1[2]; // Reserved + union SDRAM_TR_REG SDRAM_TR; // SDRAM Timing Register + Uint16 rsvd2[6]; // Reserved + Uint32 TOTAL_SDRAM_AR; // Total SDRAM Accesses Register + Uint32 TOTAL_SDRAM_ACTR; // Total SDRAM Activate Register + Uint16 rsvd3[2]; // Reserved + union SDR_EXT_TMNG_REG SDR_EXT_TMNG; // SDRAM SR/PD Exit Timing Register + union INT_RAW_REG INT_RAW; // Interrupt Raw Register + union INT_MSK_REG INT_MSK; // Interrupt Masked Register + union INT_MSK_SET_REG INT_MSK_SET; // Interrupt Mask Set Register + union INT_MSK_CLR_REG INT_MSK_CLR; // Interrupt Mask Clear Register + Uint16 rsvd4[72]; // Reserved +}; + +//--------------------------------------------------------------------------- +// EMIF External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct EMIF_REGS Emif1Regs; +extern volatile struct EMIF_REGS Emif2Regs; +#endif +#ifdef CPU2 +extern volatile struct EMIF_REGS Emif1Regs; +extern volatile struct EMIF_REGS Emif2Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm.h new file mode 100644 index 0000000000..bd784afd49 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm.h @@ -0,0 +1,1240 @@ +//########################################################################### +// +// FILE: F2837xD_epwm.h +// +// TITLE: EPWM Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_EPWM_H__ +#define __F2837xD_EPWM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// EPWM Individual Register Bit Definitions: + +struct TBCTL_BITS { // bits description + Uint16 CTRMODE:2; // 1:0 Counter Mode + Uint16 PHSEN:1; // 2 Phase Load Enable + Uint16 PRDLD:1; // 3 Active Period Load + Uint16 SYNCOSEL:2; // 5:4 Sync Output Select + Uint16 SWFSYNC:1; // 6 Software Force Sync Pulse + Uint16 HSPCLKDIV:3; // 9:7 High Speed TBCLK Pre-scaler + Uint16 CLKDIV:3; // 12:10 Time Base Clock Pre-scaler + Uint16 PHSDIR:1; // 13 Phase Direction Bit + Uint16 FREE_SOFT:2; // 15:14 Emulation Mode Bits +}; + +union TBCTL_REG { + Uint16 all; + struct TBCTL_BITS bit; +}; + +struct TBCTL2_BITS { // bits description + Uint16 rsvd1:5; // 4:0 Reserved + Uint16 rsvd2:1; // 5 Reserved + Uint16 OSHTSYNCMODE:1; // 6 One shot sync mode + Uint16 OSHTSYNC:1; // 7 One shot sync + Uint16 rsvd3:4; // 11:8 Reserved + Uint16 SYNCOSELX:2; // 13:12 Syncout selection + Uint16 PRDLDSYNC:2; // 15:14 PRD Shadow to Active Load on SYNC Event +}; + +union TBCTL2_REG { + Uint16 all; + struct TBCTL2_BITS bit; +}; + +struct TBSTS_BITS { // bits description + Uint16 CTRDIR:1; // 0 Counter Direction Status + Uint16 SYNCI:1; // 1 External Input Sync Status + Uint16 CTRMAX:1; // 2 Counter Max Latched Status + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union TBSTS_REG { + Uint16 all; + struct TBSTS_BITS bit; +}; + +struct CMPCTL_BITS { // bits description + Uint16 LOADAMODE:2; // 1:0 Active Compare A Load + Uint16 LOADBMODE:2; // 3:2 Active Compare B Load + Uint16 SHDWAMODE:1; // 4 Compare A Register Block Operating Mode + Uint16 rsvd1:1; // 5 Reserved + Uint16 SHDWBMODE:1; // 6 Compare B Register Block Operating Mode + Uint16 rsvd2:1; // 7 Reserved + Uint16 SHDWAFULL:1; // 8 Compare A Shadow Register Full Status + Uint16 SHDWBFULL:1; // 9 Compare B Shadow Register Full Status + Uint16 LOADASYNC:2; // 11:10 Active Compare A Load on SYNC + Uint16 LOADBSYNC:2; // 13:12 Active Compare B Load on SYNC + Uint16 rsvd3:2; // 15:14 Reserved +}; + +union CMPCTL_REG { + Uint16 all; + struct CMPCTL_BITS bit; +}; + +struct CMPCTL2_BITS { // bits description + Uint16 LOADCMODE:2; // 1:0 Active Compare C Load + Uint16 LOADDMODE:2; // 3:2 Active Compare D load + Uint16 SHDWCMODE:1; // 4 Compare C Block Operating Mode + Uint16 rsvd1:1; // 5 Reserved + Uint16 SHDWDMODE:1; // 6 Compare D Block Operating Mode + Uint16 rsvd2:3; // 9:7 Reserved + Uint16 LOADCSYNC:2; // 11:10 Active Compare C Load on SYNC + Uint16 LOADDSYNC:2; // 13:12 Active Compare D Load on SYNC + Uint16 rsvd3:2; // 15:14 Reserved +}; + +union CMPCTL2_REG { + Uint16 all; + struct CMPCTL2_BITS bit; +}; + +struct DBCTL_BITS { // bits description + Uint16 OUT_MODE:2; // 1:0 Dead Band Output Mode Control + Uint16 POLSEL:2; // 3:2 Polarity Select Control + Uint16 IN_MODE:2; // 5:4 Dead Band Input Select Mode Control + Uint16 LOADREDMODE:2; // 7:6 Active DBRED Load Mode + Uint16 LOADFEDMODE:2; // 9:8 Active DBFED Load Mode + Uint16 SHDWDBREDMODE:1; // 10 DBRED Block Operating Mode + Uint16 SHDWDBFEDMODE:1; // 11 DBFED Block Operating Mode + Uint16 OUTSWAP:2; // 13:12 Dead Band Output Swap Control + Uint16 DEDB_MODE:1; // 14 Dead Band Dual-Edge B Mode Control + Uint16 HALFCYCLE:1; // 15 Half Cycle Clocking Enable +}; + +union DBCTL_REG { + Uint16 all; + struct DBCTL_BITS bit; +}; + +struct DBCTL2_BITS { // bits description + Uint16 LOADDBCTLMODE:2; // 1:0 DBCTL Load from Shadow Mode Select + Uint16 SHDWDBCTLMODE:1; // 2 DBCTL Load mode Select + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union DBCTL2_REG { + Uint16 all; + struct DBCTL2_BITS bit; +}; + +struct AQCTL_BITS { // bits description + Uint16 LDAQAMODE:2; // 1:0 Action Qualifier A Load Select + Uint16 LDAQBMODE:2; // 3:2 Action Qualifier B Load Select + Uint16 SHDWAQAMODE:1; // 4 Action Qualifer A Operating Mode + Uint16 rsvd1:1; // 5 Reserved + Uint16 SHDWAQBMODE:1; // 6 Action Qualifier B Operating Mode + Uint16 rsvd2:1; // 7 Reserved + Uint16 LDAQASYNC:2; // 9:8 AQCTLA Register Load on SYNC + Uint16 LDAQBSYNC:2; // 11:10 AQCTLB Register Load on SYNC + Uint16 rsvd3:4; // 15:12 Reserved +}; + +union AQCTL_REG { + Uint16 all; + struct AQCTL_BITS bit; +}; + +struct AQTSRCSEL_BITS { // bits description + Uint16 T1SEL:4; // 3:0 T1 Event Source Select Bits + Uint16 T2SEL:4; // 7:4 T2 Event Source Select Bits + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union AQTSRCSEL_REG { + Uint16 all; + struct AQTSRCSEL_BITS bit; +}; + +struct PCCTL_BITS { // bits description + Uint16 CHPEN:1; // 0 PWM chopping enable + Uint16 OSHTWTH:4; // 4:1 One-shot pulse width + Uint16 CHPFREQ:3; // 7:5 Chopping clock frequency + Uint16 CHPDUTY:3; // 10:8 Chopping clock Duty cycle + Uint16 rsvd1:5; // 15:11 Reserved +}; + +union PCCTL_REG { + Uint16 all; + struct PCCTL_BITS bit; +}; + +struct VCAPCTL_BITS { // bits description + Uint16 VCAPE:1; // 0 Valley Capture mode + Uint16 VCAPSTART:1; // 1 Valley Capture Start + Uint16 TRIGSEL:3; // 4:2 Capture Trigger Select + Uint16 rsvd1:2; // 6:5 Reserved + Uint16 VDELAYDIV:3; // 9:7 Valley Delay Mode Divide Enable + Uint16 EDGEFILTDLYSEL:1; // 10 Valley Switching Mode Delay Select + Uint16 rsvd2:5; // 15:11 Reserved +}; + +union VCAPCTL_REG { + Uint16 all; + struct VCAPCTL_BITS bit; +}; + +struct VCNTCFG_BITS { // bits description + Uint16 STARTEDGE:4; // 3:0 Counter Start Edge Selection + Uint16 rsvd1:3; // 6:4 Reserved + Uint16 STARTEDGESTS:1; // 7 Start Edge Status Bit + Uint16 STOPEDGE:4; // 11:8 Counter Start Edge Selection + Uint16 rsvd2:3; // 14:12 Reserved + Uint16 STOPEDGESTS:1; // 15 Stop Edge Status Bit +}; + +union VCNTCFG_REG { + Uint16 all; + struct VCNTCFG_BITS bit; +}; + +struct HRCNFG_BITS { // bits description + Uint16 EDGMODE:2; // 1:0 ePWMxA Edge Mode Select Bits + Uint16 CTLMODE:1; // 2 ePWMxA Control Mode Select Bits + Uint16 HRLOAD:2; // 4:3 ePWMxA Shadow Mode Select Bits + Uint16 SELOUTB:1; // 5 EPWMB Output Selection Bit + Uint16 AUTOCONV:1; // 6 Autoconversion Bit + Uint16 SWAPAB:1; // 7 Swap EPWMA and EPWMB Outputs Bit + Uint16 EDGMODEB:2; // 9:8 ePWMxB Edge Mode Select Bits + Uint16 CTLMODEB:1; // 10 ePWMxB Control Mode Select Bits + Uint16 HRLOADB:2; // 12:11 ePWMxB Shadow Mode Select Bits + Uint16 rsvd1:1; // 13 Reserved + Uint16 rsvd2:2; // 15:14 Reserved +}; + +union HRCNFG_REG { + Uint16 all; + struct HRCNFG_BITS bit; +}; + +struct HRPWR_BITS { // bits description + Uint16 rsvd1:2; // 1:0 Reserved + Uint16 rsvd2:1; // 2 Reserved + Uint16 rsvd3:1; // 3 Reserved + Uint16 rsvd4:1; // 4 Reserved + Uint16 rsvd5:1; // 5 Reserved + Uint16 rsvd6:4; // 9:6 Reserved + Uint16 rsvd7:5; // 14:10 Reserved + Uint16 CALPWRON:1; // 15 Calibration Power On +}; + +union HRPWR_REG { + Uint16 all; + struct HRPWR_BITS bit; +}; + +struct HRMSTEP_BITS { // bits description + Uint16 HRMSTEP:8; // 7:0 High Resolution Micro Step Value + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union HRMSTEP_REG { + Uint16 all; + struct HRMSTEP_BITS bit; +}; + +struct HRCNFG2_BITS { // bits description + Uint16 EDGMODEDB:2; // 1:0 Dead-Band Edge-Mode Select Bits + Uint16 CTLMODEDBRED:2; // 3:2 DBRED Control Mode Select Bits + Uint16 CTLMODEDBFED:2; // 5:4 DBFED Control Mode Select Bits + Uint16 rsvd1:8; // 13:6 Reserved + Uint16 rsvd2:1; // 14 Reserved + Uint16 rsvd3:1; // 15 Reserved +}; + +union HRCNFG2_REG { + Uint16 all; + struct HRCNFG2_BITS bit; +}; + +struct HRPCTL_BITS { // bits description + Uint16 HRPE:1; // 0 High Resolution Period Enable + Uint16 PWMSYNCSEL:1; // 1 PWMSYNC Source Select + Uint16 TBPHSHRLOADE:1; // 2 TBPHSHR Load Enable + Uint16 rsvd1:1; // 3 Reserved + Uint16 PWMSYNCSELX:3; // 6:4 PWMSYNCX Source Select Bit: + Uint16 rsvd2:9; // 15:7 Reserved +}; + +union HRPCTL_REG { + Uint16 all; + struct HRPCTL_BITS bit; +}; + +struct TRREM_BITS { // bits description + Uint16 TRREM:11; // 10:0 Translator Remainder Bits + Uint16 rsvd1:5; // 15:11 Reserved +}; + +union TRREM_REG { + Uint16 all; + struct TRREM_BITS bit; +}; + +struct GLDCTL_BITS { // bits description + Uint16 GLD:1; // 0 Global Shadow to Active load event control + Uint16 GLDMODE:4; // 4:1 Shadow to Active Global Load Pulse Selection + Uint16 OSHTMODE:1; // 5 One Shot Load mode control bit + Uint16 rsvd1:1; // 6 Reserved + Uint16 GLDPRD:3; // 9:7 Global Reload Strobe Period Select Register + Uint16 GLDCNT:3; // 12:10 Global Reload Strobe Counter Register + Uint16 rsvd2:3; // 15:13 Reserved +}; + +union GLDCTL_REG { + Uint16 all; + struct GLDCTL_BITS bit; +}; + +struct GLDCFG_BITS { // bits description + Uint16 TBPRD_TBPRDHR:1; // 0 Global load event configuration for TBPRD:TBPRDHR + Uint16 CMPA_CMPAHR:1; // 1 Global load event configuration for CMPA:CMPAHR + Uint16 CMPB_CMPBHR:1; // 2 Global load event configuration for CMPB:CMPBHR + Uint16 CMPC:1; // 3 Global load event configuration for CMPC + Uint16 CMPD:1; // 4 Global load event configuration for CMPD + Uint16 DBRED_DBREDHR:1; // 5 Global load event configuration for DBRED:DBREDHR + Uint16 DBFED_DBFEDHR:1; // 6 Global load event configuration for DBFED:DBFEDHR + Uint16 DBCTL:1; // 7 Global load event configuration for DBCTL + Uint16 AQCTLA_AQCTLA2:1; // 8 Global load event configuration for AQCTLA/A2 + Uint16 AQCTLB_AQCTLB2:1; // 9 Global load event configuration for AQCTLB/B2 + Uint16 AQCSFRC:1; // 10 Global load event configuration for AQCSFRC + Uint16 rsvd1:5; // 15:11 Reserved +}; + +union GLDCFG_REG { + Uint16 all; + struct GLDCFG_BITS bit; +}; + +struct EPWMXLINK_BITS { // bits description + Uint16 TBPRDLINK:4; // 3:0 TBPRD:TBPRDHR Link + Uint16 CMPALINK:4; // 7:4 CMPA:CMPAHR Link + Uint16 CMPBLINK:4; // 11:8 CMPB:CMPBHR Link + Uint16 CMPCLINK:4; // 15:12 CMPC Link + Uint16 CMPDLINK:4; // 19:16 CMPD Link + Uint16 rsvd1:8; // 27:20 Reserved + Uint16 GLDCTL2LINK:4; // 31:28 GLDCTL2 Link +}; + +union EPWMXLINK_REG { + Uint32 all; + struct EPWMXLINK_BITS bit; +}; + +struct EPWMREV_BITS { // bits description + Uint16 REV:8; // 7:0 EPWM Silicon Revision bits + Uint16 TYPE:8; // 15:8 EPWM Type Bits +}; + +union EPWMREV_REG { + Uint16 all; + struct EPWMREV_BITS bit; +}; + +struct AQCTLA_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A Up + Uint16 CAD:2; // 7:6 Action Counter = Compare A Down + Uint16 CBU:2; // 9:8 Action Counter = Compare B Up + Uint16 CBD:2; // 11:10 Action Counter = Compare B Down + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union AQCTLA_REG { + Uint16 all; + struct AQCTLA_BITS bit; +}; + +struct AQCTLA2_BITS { // bits description + Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count + Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count + Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count + Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union AQCTLA2_REG { + Uint16 all; + struct AQCTLA2_BITS bit; +}; + +struct AQCTLB_BITS { // bits description + Uint16 ZRO:2; // 1:0 Action Counter = Zero + Uint16 PRD:2; // 3:2 Action Counter = Period + Uint16 CAU:2; // 5:4 Action Counter = Compare A Up + Uint16 CAD:2; // 7:6 Action Counter = Compare A Down + Uint16 CBU:2; // 9:8 Action Counter = Compare B Up + Uint16 CBD:2; // 11:10 Action Counter = Compare B Down + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union AQCTLB_REG { + Uint16 all; + struct AQCTLB_BITS bit; +}; + +struct AQCTLB2_BITS { // bits description + Uint16 T1U:2; // 1:0 Action when event occurs on T1 in UP-Count + Uint16 T1D:2; // 3:2 Action when event occurs on T1 in DOWN-Count + Uint16 T2U:2; // 5:4 Action when event occurs on T2 in UP-Count + Uint16 T2D:2; // 7:6 Action when event occurs on T2 in DOWN-Count + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union AQCTLB2_REG { + Uint16 all; + struct AQCTLB2_BITS bit; +}; + +struct AQSFRC_BITS { // bits description + Uint16 ACTSFA:2; // 1:0 Action when One-time SW Force A Invoked + Uint16 OTSFA:1; // 2 One-time SW Force A Output + Uint16 ACTSFB:2; // 4:3 Action when One-time SW Force B Invoked + Uint16 OTSFB:1; // 5 One-time SW Force A Output + Uint16 RLDCSF:2; // 7:6 Reload from Shadow Options + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union AQSFRC_REG { + Uint16 all; + struct AQSFRC_BITS bit; +}; + +struct AQCSFRC_BITS { // bits description + Uint16 CSFA:2; // 1:0 Continuous Software Force on output A + Uint16 CSFB:2; // 3:2 Continuous Software Force on output B + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union AQCSFRC_REG { + Uint16 all; + struct AQCSFRC_BITS bit; +}; + +struct DBREDHR_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:7; // 7:1 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 DBREDHR:7; // 15:9 DBREDHR High Resolution Bits +}; + +union DBREDHR_REG { + Uint16 all; + struct DBREDHR_BITS bit; +}; + +struct DBRED_BITS { // bits description + Uint16 DBRED:14; // 13:0 Rising edge delay value + Uint16 rsvd1:2; // 15:14 Reserved +}; + +union DBRED_REG { + Uint16 all; + struct DBRED_BITS bit; +}; + +struct DBFEDHR_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:7; // 7:1 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 DBFEDHR:7; // 15:9 DBFEDHR High Resolution Bits +}; + +union DBFEDHR_REG { + Uint16 all; + struct DBFEDHR_BITS bit; +}; + +struct DBFED_BITS { // bits description + Uint16 DBFED:14; // 13:0 Falling edge delay value + Uint16 rsvd1:2; // 15:14 Reserved +}; + +union DBFED_REG { + Uint16 all; + struct DBFED_BITS bit; +}; + +struct TBPHS_BITS { // bits description + Uint16 TBPHSHR:16; // 15:0 Extension Register for HRPWM Phase (8-bits) + Uint16 TBPHS:16; // 31:16 Phase Offset Register +}; + +union TBPHS_REG { + Uint32 all; + struct TBPHS_BITS bit; +}; + +struct CMPA_BITS { // bits description + Uint16 CMPAHR:16; // 15:0 Compare A HRPWM Extension Register + Uint16 CMPA:16; // 31:16 Compare A Register +}; + +union CMPA_REG { + Uint32 all; + struct CMPA_BITS bit; +}; + +struct CMPB_BITS { // bits description + Uint16 CMPBHR:16; // 15:0 Compare B High Resolution Bits + Uint16 CMPB:16; // 31:16 Compare B Register +}; + +union CMPB_REG { + Uint32 all; + struct CMPB_BITS bit; +}; + +struct GLDCTL2_BITS { // bits description + Uint16 OSHTLD:1; // 0 Enable reload event in one shot mode + Uint16 GFRCLD:1; // 1 Force reload event in one shot mode + Uint16 rsvd1:14; // 15:2 Reserved +}; + +union GLDCTL2_REG { + Uint16 all; + struct GLDCTL2_BITS bit; +}; + +struct TZSEL_BITS { // bits description + Uint16 CBC1:1; // 0 TZ1 CBC select + Uint16 CBC2:1; // 1 TZ2 CBC select + Uint16 CBC3:1; // 2 TZ3 CBC select + Uint16 CBC4:1; // 3 TZ4 CBC select + Uint16 CBC5:1; // 4 TZ5 CBC select + Uint16 CBC6:1; // 5 TZ6 CBC select + Uint16 DCAEVT2:1; // 6 DCAEVT2 CBC select + Uint16 DCBEVT2:1; // 7 DCBEVT2 CBC select + Uint16 OSHT1:1; // 8 One-shot TZ1 select + Uint16 OSHT2:1; // 9 One-shot TZ2 select + Uint16 OSHT3:1; // 10 One-shot TZ3 select + Uint16 OSHT4:1; // 11 One-shot TZ4 select + Uint16 OSHT5:1; // 12 One-shot TZ5 select + Uint16 OSHT6:1; // 13 One-shot TZ6 select + Uint16 DCAEVT1:1; // 14 One-shot DCAEVT1 select + Uint16 DCBEVT1:1; // 15 One-shot DCBEVT1 select +}; + +union TZSEL_REG { + Uint16 all; + struct TZSEL_BITS bit; +}; + +struct TZDCSEL_BITS { // bits description + Uint16 DCAEVT1:3; // 2:0 Digital Compare Output A Event 1 + Uint16 DCAEVT2:3; // 5:3 Digital Compare Output A Event 2 + Uint16 DCBEVT1:3; // 8:6 Digital Compare Output B Event 1 + Uint16 DCBEVT2:3; // 11:9 Digital Compare Output B Event 2 + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union TZDCSEL_REG { + Uint16 all; + struct TZDCSEL_BITS bit; +}; + +struct TZCTL_BITS { // bits description + Uint16 TZA:2; // 1:0 TZ1 to TZ6 Trip Action On EPWMxA + Uint16 TZB:2; // 3:2 TZ1 to TZ6 Trip Action On EPWMxB + Uint16 DCAEVT1:2; // 5:4 EPWMxA action on DCAEVT1 + Uint16 DCAEVT2:2; // 7:6 EPWMxA action on DCAEVT2 + Uint16 DCBEVT1:2; // 9:8 EPWMxB action on DCBEVT1 + Uint16 DCBEVT2:2; // 11:10 EPWMxB action on DCBEVT2 + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union TZCTL_REG { + Uint16 all; + struct TZCTL_BITS bit; +}; + +struct TZCTL2_BITS { // bits description + Uint16 TZAU:3; // 2:0 Trip Action On EPWMxA while Count direction is UP + Uint16 TZAD:3; // 5:3 Trip Action On EPWMxA while Count direction is DOWN + Uint16 TZBU:3; // 8:6 Trip Action On EPWMxB while Count direction is UP + Uint16 TZBD:3; // 11:9 Trip Action On EPWMxB while Count direction is DOWN + Uint16 rsvd1:3; // 14:12 Reserved + Uint16 ETZE:1; // 15 TZCTL2 Enable +}; + +union TZCTL2_REG { + Uint16 all; + struct TZCTL2_BITS bit; +}; + +struct TZCTLDCA_BITS { // bits description + Uint16 DCAEVT1U:3; // 2:0 DCAEVT1 Action On EPWMxA while Count direction is UP + Uint16 DCAEVT1D:3; // 5:3 DCAEVT1 Action On EPWMxA while Count direction is DOWN + Uint16 DCAEVT2U:3; // 8:6 DCAEVT2 Action On EPWMxA while Count direction is UP + Uint16 DCAEVT2D:3; // 11:9 DCAEVT2 Action On EPWMxA while Count direction is DOWN + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union TZCTLDCA_REG { + Uint16 all; + struct TZCTLDCA_BITS bit; +}; + +struct TZCTLDCB_BITS { // bits description + Uint16 DCBEVT1U:3; // 2:0 DCBEVT1 Action On EPWMxA while Count direction is UP + Uint16 DCBEVT1D:3; // 5:3 DCBEVT1 Action On EPWMxA while Count direction is DOWN + Uint16 DCBEVT2U:3; // 8:6 DCBEVT2 Action On EPWMxA while Count direction is UP + Uint16 DCBEVT2D:3; // 11:9 DCBEVT2 Action On EPWMxA while Count direction is DOWN + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union TZCTLDCB_REG { + Uint16 all; + struct TZCTLDCB_BITS bit; +}; + +struct TZEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Int Enable + Uint16 OST:1; // 2 Trip Zones One Shot Int Enable + Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Int Enable + Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Int Enable + Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Int Enable + Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Int Enable + Uint16 rsvd2:9; // 15:7 Reserved +}; + +union TZEINT_REG { + Uint16 all; + struct TZEINT_BITS bit; +}; + +struct TZFLG_BITS { // bits description + Uint16 INT:1; // 0 Global Int Status Flag + Uint16 CBC:1; // 1 Trip Zones Cycle By Cycle Flag + Uint16 OST:1; // 2 Trip Zones One Shot Flag + Uint16 DCAEVT1:1; // 3 Digital Compare A Event 1 Flag + Uint16 DCAEVT2:1; // 4 Digital Compare A Event 2 Flag + Uint16 DCBEVT1:1; // 5 Digital Compare B Event 1 Flag + Uint16 DCBEVT2:1; // 6 Digital Compare B Event 2 Flag + Uint16 rsvd1:9; // 15:7 Reserved +}; + +union TZFLG_REG { + Uint16 all; + struct TZFLG_BITS bit; +}; + +struct TZCBCFLG_BITS { // bits description + Uint16 CBC1:1; // 0 Latched Status Flag for CBC1 Trip Latch + Uint16 CBC2:1; // 1 Latched Status Flag for CBC2 Trip Latch + Uint16 CBC3:1; // 2 Latched Status Flag for CBC3 Trip Latch + Uint16 CBC4:1; // 3 Latched Status Flag for CBC4 Trip Latch + Uint16 CBC5:1; // 4 Latched Status Flag for CBC5 Trip Latch + Uint16 CBC6:1; // 5 Latched Status Flag for CBC6 Trip Latch + Uint16 DCAEVT2:1; // 6 Latched Status Flag for Digital Compare Output A Event 2 + Uint16 DCBEVT2:1; // 7 Latched Status Flag for Digital Compare Output B Event 2 + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union TZCBCFLG_REG { + Uint16 all; + struct TZCBCFLG_BITS bit; +}; + +struct TZOSTFLG_BITS { // bits description + Uint16 OST1:1; // 0 Latched Status Flag for OST1 Trip Latch + Uint16 OST2:1; // 1 Latched Status Flag for OST2 Trip Latch + Uint16 OST3:1; // 2 Latched Status Flag for OST3 Trip Latch + Uint16 OST4:1; // 3 Latched Status Flag for OST4 Trip Latch + Uint16 OST5:1; // 4 Latched Status Flag for OST5 Trip Latch + Uint16 OST6:1; // 5 Latched Status Flag for OST6 Trip Latch + Uint16 DCAEVT1:1; // 6 Latched Status Flag for Digital Compare Output A Event 1 + Uint16 DCBEVT1:1; // 7 Latched Status Flag for Digital Compare Output B Event 1 + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union TZOSTFLG_REG { + Uint16 all; + struct TZOSTFLG_BITS bit; +}; + +struct TZCLR_BITS { // bits description + Uint16 INT:1; // 0 Global Interrupt Clear Flag + Uint16 CBC:1; // 1 Cycle-By-Cycle Flag Clear + Uint16 OST:1; // 2 One-Shot Flag Clear + Uint16 DCAEVT1:1; // 3 DCAVET1 Flag Clear + Uint16 DCAEVT2:1; // 4 DCAEVT2 Flag Clear + Uint16 DCBEVT1:1; // 5 DCBEVT1 Flag Clear + Uint16 DCBEVT2:1; // 6 DCBEVT2 Flag Clear + Uint16 rsvd1:7; // 13:7 Reserved + Uint16 CBCPULSE:2; // 15:14 Clear Pulse for CBC Trip Latch +}; + +union TZCLR_REG { + Uint16 all; + struct TZCLR_BITS bit; +}; + +struct TZCBCCLR_BITS { // bits description + Uint16 CBC1:1; // 0 Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch + Uint16 CBC2:1; // 1 Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch + Uint16 CBC3:1; // 2 Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch + Uint16 CBC4:1; // 3 Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch + Uint16 CBC5:1; // 4 Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch + Uint16 CBC6:1; // 5 Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch + Uint16 DCAEVT2:1; // 6 Clear Flag forDCAEVT2 selected for CBC + Uint16 DCBEVT2:1; // 7 Clear Flag for DCBEVT2 selected for CBC + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union TZCBCCLR_REG { + Uint16 all; + struct TZCBCCLR_BITS bit; +}; + +struct TZOSTCLR_BITS { // bits description + Uint16 OST1:1; // 0 Clear Flag for Oneshot (OST1) Trip Latch + Uint16 OST2:1; // 1 Clear Flag for Oneshot (OST2) Trip Latch + Uint16 OST3:1; // 2 Clear Flag for Oneshot (OST3) Trip Latch + Uint16 OST4:1; // 3 Clear Flag for Oneshot (OST4) Trip Latch + Uint16 OST5:1; // 4 Clear Flag for Oneshot (OST5) Trip Latch + Uint16 OST6:1; // 5 Clear Flag for Oneshot (OST6) Trip Latch + Uint16 DCAEVT1:1; // 6 Clear Flag for DCAEVT1 selected for OST + Uint16 DCBEVT1:1; // 7 Clear Flag for DCBEVT1 selected for OST + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union TZOSTCLR_REG { + Uint16 all; + struct TZOSTCLR_BITS bit; +}; + +struct TZFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CBC:1; // 1 Force Trip Zones Cycle By Cycle Event + Uint16 OST:1; // 2 Force Trip Zones One Shot Event + Uint16 DCAEVT1:1; // 3 Force Digital Compare A Event 1 + Uint16 DCAEVT2:1; // 4 Force Digital Compare A Event 2 + Uint16 DCBEVT1:1; // 5 Force Digital Compare B Event 1 + Uint16 DCBEVT2:1; // 6 Force Digital Compare B Event 2 + Uint16 rsvd2:9; // 15:7 Reserved +}; + +union TZFRC_REG { + Uint16 all; + struct TZFRC_BITS bit; +}; + +struct ETSEL_BITS { // bits description + Uint16 INTSEL:3; // 2:0 EPWMxINTn Select + Uint16 INTEN:1; // 3 EPWMxINTn Enable + Uint16 SOCASELCMP:1; // 4 EPWMxSOCA Compare Select + Uint16 SOCBSELCMP:1; // 5 EPWMxSOCB Compare Select + Uint16 INTSELCMP:1; // 6 EPWMxINT Compare Select + Uint16 rsvd1:1; // 7 Reserved + Uint16 SOCASEL:3; // 10:8 Start of Conversion A Select + Uint16 SOCAEN:1; // 11 Start of Conversion A Enable + Uint16 SOCBSEL:3; // 14:12 Start of Conversion B Select + Uint16 SOCBEN:1; // 15 Start of Conversion B Enable +}; + +union ETSEL_REG { + Uint16 all; + struct ETSEL_BITS bit; +}; + +struct ETPS_BITS { // bits description + Uint16 INTPRD:2; // 1:0 EPWMxINTn Period Select + Uint16 INTCNT:2; // 3:2 EPWMxINTn Counter Register + Uint16 INTPSSEL:1; // 4 EPWMxINTn Pre-Scale Selection Bits + Uint16 SOCPSSEL:1; // 5 EPWMxSOC A/B Pre-Scale Selection Bits + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 SOCAPRD:2; // 9:8 EPWMxSOCA Period Select + Uint16 SOCACNT:2; // 11:10 EPWMxSOCA Counter Register + Uint16 SOCBPRD:2; // 13:12 EPWMxSOCB Period Select + Uint16 SOCBCNT:2; // 15:14 EPWMxSOCB Counter +}; + +union ETPS_REG { + Uint16 all; + struct ETPS_BITS bit; +}; + +struct ETFLG_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Flag + Uint16 rsvd1:1; // 1 Reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Flag + Uint16 SOCB:1; // 3 EPWMxSOCB Flag + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union ETFLG_REG { + Uint16 all; + struct ETFLG_BITS bit; +}; + +struct ETCLR_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Clear + Uint16 rsvd1:1; // 1 Reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Clear + Uint16 SOCB:1; // 3 EPWMxSOCB Clear + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union ETCLR_REG { + Uint16 all; + struct ETCLR_BITS bit; +}; + +struct ETFRC_BITS { // bits description + Uint16 INT:1; // 0 EPWMxINTn Force + Uint16 rsvd1:1; // 1 Reserved + Uint16 SOCA:1; // 2 EPWMxSOCA Force + Uint16 SOCB:1; // 3 EPWMxSOCB Force + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union ETFRC_REG { + Uint16 all; + struct ETFRC_BITS bit; +}; + +struct ETINTPS_BITS { // bits description + Uint16 INTPRD2:4; // 3:0 EPWMxINTn Period Select + Uint16 INTCNT2:4; // 7:4 EPWMxINTn Counter Register + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union ETINTPS_REG { + Uint16 all; + struct ETINTPS_BITS bit; +}; + +struct ETSOCPS_BITS { // bits description + Uint16 SOCAPRD2:4; // 3:0 EPWMxSOCA Period Select + Uint16 SOCACNT2:4; // 7:4 EPWMxSOCA Counter Register + Uint16 SOCBPRD2:4; // 11:8 EPWMxSOCB Period Select + Uint16 SOCBCNT2:4; // 15:12 EPWMxSOCB Counter Register +}; + +union ETSOCPS_REG { + Uint16 all; + struct ETSOCPS_BITS bit; +}; + +struct ETCNTINITCTL_BITS { // bits description + Uint16 rsvd1:10; // 9:0 Reserved + Uint16 INTINITFRC:1; // 10 EPWMxINT Counter Initialization Force + Uint16 SOCAINITFRC:1; // 11 EPWMxSOCA Counter Initialization Force + Uint16 SOCBINITFRC:1; // 12 EPWMxSOCB Counter Initialization Force + Uint16 INTINITEN:1; // 13 EPWMxINT Counter Initialization Enable + Uint16 SOCAINITEN:1; // 14 EPWMxSOCA Counter Initialization Enable + Uint16 SOCBINITEN:1; // 15 EPWMxSOCB Counter Initialization Enable +}; + +union ETCNTINITCTL_REG { + Uint16 all; + struct ETCNTINITCTL_BITS bit; +}; + +struct ETCNTINIT_BITS { // bits description + Uint16 INTINIT:4; // 3:0 EPWMxINT Counter Initialization Bits + Uint16 SOCAINIT:4; // 7:4 EPWMxSOCA Counter Initialization Bits + Uint16 SOCBINIT:4; // 11:8 EPWMxSOCB Counter Initialization Bits + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union ETCNTINIT_REG { + Uint16 all; + struct ETCNTINIT_BITS bit; +}; + +struct DCTRIPSEL_BITS { // bits description + Uint16 DCAHCOMPSEL:4; // 3:0 Digital Compare A High COMP Input Select + Uint16 DCALCOMPSEL:4; // 7:4 Digital Compare A Low COMP Input Select + Uint16 DCBHCOMPSEL:4; // 11:8 Digital Compare B High COMP Input Select + Uint16 DCBLCOMPSEL:4; // 15:12 Digital Compare B Low COMP Input Select +}; + +union DCTRIPSEL_REG { + Uint16 all; + struct DCTRIPSEL_BITS bit; +}; + +struct DCACTL_BITS { // bits description + Uint16 EVT1SRCSEL:1; // 0 DCAEVT1 Source Signal + Uint16 EVT1FRCSYNCSEL:1; // 1 DCAEVT1 Force Sync Signal + Uint16 EVT1SOCE:1; // 2 DCAEVT1 SOC Enable + Uint16 EVT1SYNCE:1; // 3 DCAEVT1 SYNC Enable + Uint16 rsvd1:1; // 4 Reserved + Uint16 rsvd2:2; // 6:5 Reserved + Uint16 rsvd3:1; // 7 Reserved + Uint16 EVT2SRCSEL:1; // 8 DCAEVT2 Source Signal + Uint16 EVT2FRCSYNCSEL:1; // 9 DCAEVT2 Force Sync Signal + Uint16 rsvd4:2; // 11:10 Reserved + Uint16 rsvd5:1; // 12 Reserved + Uint16 rsvd6:2; // 14:13 Reserved + Uint16 rsvd7:1; // 15 Reserved +}; + +union DCACTL_REG { + Uint16 all; + struct DCACTL_BITS bit; +}; + +struct DCBCTL_BITS { // bits description + Uint16 EVT1SRCSEL:1; // 0 DCBEVT1 Source Signal + Uint16 EVT1FRCSYNCSEL:1; // 1 DCBEVT1 Force Sync Signal + Uint16 EVT1SOCE:1; // 2 DCBEVT1 SOC Enable + Uint16 EVT1SYNCE:1; // 3 DCBEVT1 SYNC Enable + Uint16 rsvd1:1; // 4 Reserved + Uint16 rsvd2:2; // 6:5 Reserved + Uint16 rsvd3:1; // 7 Reserved + Uint16 EVT2SRCSEL:1; // 8 DCBEVT2 Source Signal + Uint16 EVT2FRCSYNCSEL:1; // 9 DCBEVT2 Force Sync Signal + Uint16 rsvd4:2; // 11:10 Reserved + Uint16 rsvd5:1; // 12 Reserved + Uint16 rsvd6:2; // 14:13 Reserved + Uint16 rsvd7:1; // 15 Reserved +}; + +union DCBCTL_REG { + Uint16 all; + struct DCBCTL_BITS bit; +}; + +struct DCFCTL_BITS { // bits description + Uint16 SRCSEL:2; // 1:0 Filter Block Signal Source Select + Uint16 BLANKE:1; // 2 Blanking Enable/Disable + Uint16 BLANKINV:1; // 3 Blanking Window Inversion + Uint16 PULSESEL:2; // 5:4 Pulse Select for Blanking & Capture Alignment + Uint16 EDGEFILTSEL:1; // 6 Edge Filter Select + Uint16 rsvd1:1; // 7 Reserved + Uint16 EDGEMODE:2; // 9:8 Edge Mode + Uint16 EDGECOUNT:3; // 12:10 Edge Count + Uint16 EDGESTATUS:3; // 15:13 Edge Status +}; + +union DCFCTL_REG { + Uint16 all; + struct DCFCTL_BITS bit; +}; + +struct DCCAPCTL_BITS { // bits description + Uint16 CAPE:1; // 0 Counter Capture Enable + Uint16 SHDWMODE:1; // 1 Counter Capture Mode + Uint16 rsvd1:11; // 12:2 Reserved + Uint16 CAPSTS:1; // 13 Latched Status Flag for Capture Event + Uint16 CAPCLR:1; // 14 DC Capture Latched Status Clear Flag + Uint16 CAPMODE:1; // 15 Counter Capture Mode +}; + +union DCCAPCTL_REG { + Uint16 all; + struct DCCAPCTL_BITS bit; +}; + +struct DCAHTRIPSEL_BITS { // bits description + Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAH Mux + Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAH Mux + Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAH Mux + Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAH Mux + Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAH Mux + Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAH Mux + Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAH Mux + Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAH Mux + Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAH Mux + Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAH Mux + Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAH Mux + Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAH Mux + Uint16 rsvd1:1; // 12 Reserved + Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAH Mux + Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAH Mux + Uint16 rsvd2:1; // 15 Reserved +}; + +union DCAHTRIPSEL_REG { + Uint16 all; + struct DCAHTRIPSEL_BITS bit; +}; + +struct DCALTRIPSEL_BITS { // bits description + Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCAL Mux + Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCAL Mux + Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCAL Mux + Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCAL Mux + Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCAL Mux + Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCAL Mux + Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCAL Mux + Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCAL Mux + Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCAL Mux + Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCAL Mux + Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCAL Mux + Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCAL Mux + Uint16 rsvd1:1; // 12 Reserved + Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCAL Mux + Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCAL Mux + Uint16 rsvd2:1; // 15 Reserved +}; + +union DCALTRIPSEL_REG { + Uint16 all; + struct DCALTRIPSEL_BITS bit; +}; + +struct DCBHTRIPSEL_BITS { // bits description + Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBH Mux + Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBH Mux + Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBH Mux + Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBH Mux + Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBH Mux + Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBH Mux + Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBH Mux + Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBH Mux + Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBH Mux + Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBH Mux + Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBH Mux + Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBH Mux + Uint16 rsvd1:1; // 12 Reserved + Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBH Mux + Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBH Mux + Uint16 rsvd2:1; // 15 Reserved +}; + +union DCBHTRIPSEL_REG { + Uint16 all; + struct DCBHTRIPSEL_BITS bit; +}; + +struct DCBLTRIPSEL_BITS { // bits description + Uint16 TRIPINPUT1:1; // 0 Trip Input 1 Select to DCBL Mux + Uint16 TRIPINPUT2:1; // 1 Trip Input 2 Select to DCBL Mux + Uint16 TRIPINPUT3:1; // 2 Trip Input 3 Select to DCBL Mux + Uint16 TRIPINPUT4:1; // 3 Trip Input 4 Select to DCBL Mux + Uint16 TRIPINPUT5:1; // 4 Trip Input 5 Select to DCBL Mux + Uint16 TRIPINPUT6:1; // 5 Trip Input 6 Select to DCBL Mux + Uint16 TRIPINPUT7:1; // 6 Trip Input 7 Select to DCBL Mux + Uint16 TRIPINPUT8:1; // 7 Trip Input 8 Select to DCBL Mux + Uint16 TRIPINPUT9:1; // 8 Trip Input 9 Select to DCBL Mux + Uint16 TRIPINPUT10:1; // 9 Trip Input 10 Select to DCBL Mux + Uint16 TRIPINPUT11:1; // 10 Trip Input 11 Select to DCBL Mux + Uint16 TRIPINPUT12:1; // 11 Trip Input 12 Select to DCBL Mux + Uint16 rsvd1:1; // 12 Reserved + Uint16 TRIPINPUT14:1; // 13 Trip Input 14 Select to DCBL Mux + Uint16 TRIPINPUT15:1; // 14 Trip Input 15 Select to DCBL Mux + Uint16 rsvd2:1; // 15 Reserved +}; + +union DCBLTRIPSEL_REG { + Uint16 all; + struct DCBLTRIPSEL_BITS bit; +}; + +struct EPWM_REGS { + union TBCTL_REG TBCTL; // Time Base Control Register + union TBCTL2_REG TBCTL2; // Time Base Control Register 2 + Uint16 rsvd1[2]; // Reserved + Uint16 TBCTR; // Time Base Counter Register + union TBSTS_REG TBSTS; // Time Base Status Register + Uint16 rsvd2[2]; // Reserved + union CMPCTL_REG CMPCTL; // Counter Compare Control Register + union CMPCTL2_REG CMPCTL2; // Counter Compare Control Register 2 + Uint16 rsvd3[2]; // Reserved + union DBCTL_REG DBCTL; // Dead-Band Generator Control Register + union DBCTL2_REG DBCTL2; // Dead-Band Generator Control Register 2 + Uint16 rsvd4[2]; // Reserved + union AQCTL_REG AQCTL; // Action Qualifier Control Register + union AQTSRCSEL_REG AQTSRCSEL; // Action Qualifier Trigger Event Source Select Register + Uint16 rsvd5[2]; // Reserved + union PCCTL_REG PCCTL; // PWM Chopper Control Register + Uint16 rsvd6[3]; // Reserved + union VCAPCTL_REG VCAPCTL; // Valley Capture Control Register + union VCNTCFG_REG VCNTCFG; // Valley Counter Config Register + Uint16 rsvd7[6]; // Reserved + union HRCNFG_REG HRCNFG; // HRPWM Configuration Register + union HRPWR_REG HRPWR; // HRPWM Power Register + Uint16 rsvd8[4]; // Reserved + union HRMSTEP_REG HRMSTEP; // HRPWM MEP Step Register + union HRCNFG2_REG HRCNFG2; // HRPWM Configuration 2 Register + Uint16 rsvd9[5]; // Reserved + union HRPCTL_REG HRPCTL; // High Resolution Period Control Register + union TRREM_REG TRREM; // Translator High Resolution Remainder Register + Uint16 rsvd10[5]; // Reserved + union GLDCTL_REG GLDCTL; // Global PWM Load Control Register + union GLDCFG_REG GLDCFG; // Global PWM Load Config Register + Uint16 rsvd11[2]; // Reserved + union EPWMXLINK_REG EPWMXLINK; // EPWMx Link Register + Uint16 rsvd12[4]; // Reserved + union EPWMREV_REG EPWMREV; // EPWM Revision Register + Uint16 rsvd13; // Reserved + union AQCTLA_REG AQCTLA; // Action Qualifier Control Register For Output A + union AQCTLA2_REG AQCTLA2; // Additional Action Qualifier Control Register For Output A + union AQCTLB_REG AQCTLB; // Action Qualifier Control Register For Output B + union AQCTLB2_REG AQCTLB2; // Additional Action Qualifier Control Register For Output B + Uint16 rsvd14[3]; // Reserved + union AQSFRC_REG AQSFRC; // Action Qualifier Software Force Register + Uint16 rsvd15; // Reserved + union AQCSFRC_REG AQCSFRC; // Action Qualifier Continuous S/W Force Register + Uint16 rsvd16[6]; // Reserved + union DBREDHR_REG DBREDHR; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register + union DBRED_REG DBRED; // Dead-Band Generator Rising Edge Delay High Resolution Mirror Register + union DBFEDHR_REG DBFEDHR; // Dead-Band Generator Falling Edge Delay High Resolution Register + union DBFED_REG DBFED; // Dead-Band Generator Falling Edge Delay Count Register + Uint16 rsvd17[12]; // Reserved + union TBPHS_REG TBPHS; // Time Base Phase High + Uint16 TBPRDHR; // Time Base Period High Resolution Register + Uint16 TBPRD; // Time Base Period Register + Uint16 rsvd18[6]; // Reserved + union CMPA_REG CMPA; // Counter Compare A Register + union CMPB_REG CMPB; // Compare B Register + Uint16 rsvd19; // Reserved + Uint16 CMPC; // Counter Compare C Register + Uint16 rsvd20; // Reserved + Uint16 CMPD; // Counter Compare D Register + Uint16 rsvd21[2]; // Reserved + union GLDCTL2_REG GLDCTL2; // Global PWM Load Control Register 2 + Uint16 rsvd22[2]; // Reserved + Uint16 SWVDELVAL; // Software Valley Mode Delay Register + Uint16 rsvd23[8]; // Reserved + union TZSEL_REG TZSEL; // Trip Zone Select Register + Uint16 rsvd24; // Reserved + union TZDCSEL_REG TZDCSEL; // Trip Zone Digital Comparator Select Register + Uint16 rsvd25; // Reserved + union TZCTL_REG TZCTL; // Trip Zone Control Register + union TZCTL2_REG TZCTL2; // Additional Trip Zone Control Register + union TZCTLDCA_REG TZCTLDCA; // Trip Zone Control Register Digital Compare A + union TZCTLDCB_REG TZCTLDCB; // Trip Zone Control Register Digital Compare B + Uint16 rsvd26[5]; // Reserved + union TZEINT_REG TZEINT; // Trip Zone Enable Interrupt Register + Uint16 rsvd27[5]; // Reserved + union TZFLG_REG TZFLG; // Trip Zone Flag Register + union TZCBCFLG_REG TZCBCFLG; // Trip Zone CBC Flag Register + union TZOSTFLG_REG TZOSTFLG; // Trip Zone OST Flag Register + Uint16 rsvd28; // Reserved + union TZCLR_REG TZCLR; // Trip Zone Clear Register + union TZCBCCLR_REG TZCBCCLR; // Trip Zone CBC Clear Register + union TZOSTCLR_REG TZOSTCLR; // Trip Zone OST Clear Register + Uint16 rsvd29; // Reserved + union TZFRC_REG TZFRC; // Trip Zone Force Register + Uint16 rsvd30[8]; // Reserved + union ETSEL_REG ETSEL; // Event Trigger Selection Register + Uint16 rsvd31; // Reserved + union ETPS_REG ETPS; // Event Trigger Pre-Scale Register + Uint16 rsvd32; // Reserved + union ETFLG_REG ETFLG; // Event Trigger Flag Register + Uint16 rsvd33; // Reserved + union ETCLR_REG ETCLR; // Event Trigger Clear Register + Uint16 rsvd34; // Reserved + union ETFRC_REG ETFRC; // Event Trigger Force Register + Uint16 rsvd35; // Reserved + union ETINTPS_REG ETINTPS; // Event-Trigger Interrupt Pre-Scale Register + Uint16 rsvd36; // Reserved + union ETSOCPS_REG ETSOCPS; // Event-Trigger SOC Pre-Scale Register + Uint16 rsvd37; // Reserved + union ETCNTINITCTL_REG ETCNTINITCTL; // Event-Trigger Counter Initialization Control Register + Uint16 rsvd38; // Reserved + union ETCNTINIT_REG ETCNTINIT; // Event-Trigger Counter Initialization Register + Uint16 rsvd39[11]; // Reserved + union DCTRIPSEL_REG DCTRIPSEL; // Digital Compare Trip Select Register + Uint16 rsvd40[2]; // Reserved + union DCACTL_REG DCACTL; // Digital Compare A Control Register + union DCBCTL_REG DCBCTL; // Digital Compare B Control Register + Uint16 rsvd41[2]; // Reserved + union DCFCTL_REG DCFCTL; // Digital Compare Filter Control Register + union DCCAPCTL_REG DCCAPCTL; // Digital Compare Capture Control Register + Uint16 DCFOFFSET; // Digital Compare Filter Offset Register + Uint16 DCFOFFSETCNT; // Digital Compare Filter Offset Counter Register + Uint16 DCFWINDOW; // Digital Compare Filter Window Register + Uint16 DCFWINDOWCNT; // Digital Compare Filter Window Counter Register + Uint16 rsvd42[2]; // Reserved + Uint16 DCCAP; // Digital Compare Counter Capture Register + Uint16 rsvd43[2]; // Reserved + union DCAHTRIPSEL_REG DCAHTRIPSEL; // Digital Compare AH Trip Select + union DCALTRIPSEL_REG DCALTRIPSEL; // Digital Compare AL Trip Select + union DCBHTRIPSEL_REG DCBHTRIPSEL; // Digital Compare BH Trip Select + union DCBLTRIPSEL_REG DCBLTRIPSEL; // Digital Compare BL Trip Select + Uint16 rsvd44[39]; // Reserved + Uint16 HWVDELVAL; // Hardware Valley Mode Delay Register + Uint16 VCNTVAL; // Hardware Valley Counter Register + Uint16 rsvd45; // Reserved +}; + +//--------------------------------------------------------------------------- +// EPWM External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; +extern volatile struct EPWM_REGS EPwm7Regs; +extern volatile struct EPWM_REGS EPwm8Regs; +extern volatile struct EPWM_REGS EPwm9Regs; +extern volatile struct EPWM_REGS EPwm10Regs; +extern volatile struct EPWM_REGS EPwm11Regs; +extern volatile struct EPWM_REGS EPwm12Regs; +#endif +#ifdef CPU2 +extern volatile struct EPWM_REGS EPwm1Regs; +extern volatile struct EPWM_REGS EPwm2Regs; +extern volatile struct EPWM_REGS EPwm3Regs; +extern volatile struct EPWM_REGS EPwm4Regs; +extern volatile struct EPWM_REGS EPwm5Regs; +extern volatile struct EPWM_REGS EPwm6Regs; +extern volatile struct EPWM_REGS EPwm7Regs; +extern volatile struct EPWM_REGS EPwm8Regs; +extern volatile struct EPWM_REGS EPwm9Regs; +extern volatile struct EPWM_REGS EPwm10Regs; +extern volatile struct EPWM_REGS EPwm11Regs; +extern volatile struct EPWM_REGS EPwm12Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm_xbar.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm_xbar.h new file mode 100644 index 0000000000..47f85e18fe --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_epwm_xbar.h @@ -0,0 +1,832 @@ +//########################################################################### +// +// FILE: F2837xD_epwm_xbar.h +// +// TITLE: EPWM_XBAR Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_EPWM_XBAR_H__ +#define __F2837xD_EPWM_XBAR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// EPWM_XBAR Individual Register Bit Definitions: + +struct TRIP4MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP4 of EPWM-XBAR +}; + +union TRIP4MUX0TO15CFG_REG { + Uint32 all; + struct TRIP4MUX0TO15CFG_BITS bit; +}; + +struct TRIP4MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP4 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP4 of EPWM-XBAR +}; + +union TRIP4MUX16TO31CFG_REG { + Uint32 all; + struct TRIP4MUX16TO31CFG_BITS bit; +}; + +struct TRIP5MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP5 of EPWM-XBAR +}; + +union TRIP5MUX0TO15CFG_REG { + Uint32 all; + struct TRIP5MUX0TO15CFG_BITS bit; +}; + +struct TRIP5MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP5 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP5 of EPWM-XBAR +}; + +union TRIP5MUX16TO31CFG_REG { + Uint32 all; + struct TRIP5MUX16TO31CFG_BITS bit; +}; + +struct TRIP7MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP7 of EPWM-XBAR +}; + +union TRIP7MUX0TO15CFG_REG { + Uint32 all; + struct TRIP7MUX0TO15CFG_BITS bit; +}; + +struct TRIP7MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP7 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP7 of EPWM-XBAR +}; + +union TRIP7MUX16TO31CFG_REG { + Uint32 all; + struct TRIP7MUX16TO31CFG_BITS bit; +}; + +struct TRIP8MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP8 of EPWM-XBAR +}; + +union TRIP8MUX0TO15CFG_REG { + Uint32 all; + struct TRIP8MUX0TO15CFG_BITS bit; +}; + +struct TRIP8MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP8 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP8 of EPWM-XBAR +}; + +union TRIP8MUX16TO31CFG_REG { + Uint32 all; + struct TRIP8MUX16TO31CFG_BITS bit; +}; + +struct TRIP9MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP9 of EPWM-XBAR +}; + +union TRIP9MUX0TO15CFG_REG { + Uint32 all; + struct TRIP9MUX0TO15CFG_BITS bit; +}; + +struct TRIP9MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP9 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP9 of EPWM-XBAR +}; + +union TRIP9MUX16TO31CFG_REG { + Uint32 all; + struct TRIP9MUX16TO31CFG_BITS bit; +}; + +struct TRIP10MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP10 of EPWM-XBAR +}; + +union TRIP10MUX0TO15CFG_REG { + Uint32 all; + struct TRIP10MUX0TO15CFG_BITS bit; +}; + +struct TRIP10MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP10 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP10 of EPWM-XBAR +}; + +union TRIP10MUX16TO31CFG_REG { + Uint32 all; + struct TRIP10MUX16TO31CFG_BITS bit; +}; + +struct TRIP11MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP11 of EPWM-XBAR +}; + +union TRIP11MUX0TO15CFG_REG { + Uint32 all; + struct TRIP11MUX0TO15CFG_BITS bit; +}; + +struct TRIP11MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP11 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP11 of EPWM-XBAR +}; + +union TRIP11MUX16TO31CFG_REG { + Uint32 all; + struct TRIP11MUX16TO31CFG_BITS bit; +}; + +struct TRIP12MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for TRIP12 of EPWM-XBAR +}; + +union TRIP12MUX0TO15CFG_REG { + Uint32 all; + struct TRIP12MUX0TO15CFG_BITS bit; +}; + +struct TRIP12MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for TRIP12 of EPWM-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for TRIP12 of EPWM-XBAR +}; + +union TRIP12MUX16TO31CFG_REG { + Uint32 all; + struct TRIP12MUX16TO31CFG_BITS bit; +}; + +struct TRIP4MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP4 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP4 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP4 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP4 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP4 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP4 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP4 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP4 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP4 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP4 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP4 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP4 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP4 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP4 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP4 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP4 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP4 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP4 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP4 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP4 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP4 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP4 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP4 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP4 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP4 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP4 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP4 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP4 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP4 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP4 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP4 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP4 of EPWM-XBAR +}; + +union TRIP4MUXENABLE_REG { + Uint32 all; + struct TRIP4MUXENABLE_BITS bit; +}; + +struct TRIP5MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP5 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP5 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP5 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP5 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP5 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP5 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP5 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP5 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP5 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP5 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP5 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP5 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP5 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP5 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP5 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP5 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP5 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP5 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP5 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP5 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP5 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP5 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP5 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP5 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP5 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP5 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP5 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP5 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP5 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP5 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP5 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP5 of EPWM-XBAR +}; + +union TRIP5MUXENABLE_REG { + Uint32 all; + struct TRIP5MUXENABLE_BITS bit; +}; + +struct TRIP7MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP7 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP7 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP7 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP7 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP7 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP7 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP7 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP7 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP7 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP7 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP7 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP7 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP7 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP7 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP7 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP7 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP7 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP7 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP7 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP7 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP7 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP7 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP7 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP7 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP7 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP7 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP7 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP7 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP7 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP7 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP7 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP7 of EPWM-XBAR +}; + +union TRIP7MUXENABLE_REG { + Uint32 all; + struct TRIP7MUXENABLE_BITS bit; +}; + +struct TRIP8MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP8 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP8 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP8 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP8 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP8 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP8 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP8 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP8 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP8 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP8 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP8 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP8 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP8 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP8 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP8 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP8 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP8 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP8 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP8 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP8 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP8 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP8 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP8 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP8 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP8 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP8 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP8 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP8 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP8 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP8 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP8 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP8 of EPWM-XBAR +}; + +union TRIP8MUXENABLE_REG { + Uint32 all; + struct TRIP8MUXENABLE_BITS bit; +}; + +struct TRIP9MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP9 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP9 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP9 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP9 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP9 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP9 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP9 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP9 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP9 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP9 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP9 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP9 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP9 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP9 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP9 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP9 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP9 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP9 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP9 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP9 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP9 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP9 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP9 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP9 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP9 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP9 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP9 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP9 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP9 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP9 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP9 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP9 of EPWM-XBAR +}; + +union TRIP9MUXENABLE_REG { + Uint32 all; + struct TRIP9MUXENABLE_BITS bit; +}; + +struct TRIP10MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP10 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP10 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP10 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP10 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP10 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP10 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP10 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP10 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP10 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP10 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP10 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP10 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP10 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP10 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP10 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP10 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP10 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP10 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP10 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP10 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP10 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP10 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP10 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP10 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP10 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP10 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP10 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP10 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP10 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP10 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP10 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP10 of EPWM-XBAR +}; + +union TRIP10MUXENABLE_REG { + Uint32 all; + struct TRIP10MUXENABLE_BITS bit; +}; + +struct TRIP11MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP11 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP11 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP11 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP11 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP11 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP11 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP11 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP11 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP11 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP11 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP11 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP11 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP11 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP11 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP11 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP11 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP11 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP11 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP11 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP11 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP11 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP11 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP11 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP11 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP11 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP11 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP11 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP11 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP11 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP11 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP11 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP11 of EPWM-XBAR +}; + +union TRIP11MUXENABLE_REG { + Uint32 all; + struct TRIP11MUXENABLE_BITS bit; +}; + +struct TRIP12MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive TRIP12 of EPWM-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive TRIP12 of EPWM-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive TRIP12 of EPWM-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive TRIP12 of EPWM-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive TRIP12 of EPWM-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive TRIP12 of EPWM-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive TRIP12 of EPWM-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive TRIP12 of EPWM-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive TRIP12 of EPWM-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive TRIP12 of EPWM-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive TRIP12 of EPWM-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive TRIP12 of EPWM-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive TRIP12 of EPWM-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive TRIP12 of EPWM-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive TRIP12 of EPWM-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive TRIP12 of EPWM-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive TRIP12 of EPWM-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive TRIP12 of EPWM-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive TRIP12 of EPWM-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive TRIP12 of EPWM-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive TRIP12 of EPWM-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive TRIP12 of EPWM-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive TRIP12 of EPWM-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive TRIP12 of EPWM-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive TRIP12 of EPWM-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive TRIP12 of EPWM-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive TRIP12 of EPWM-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive TRIP12 of EPWM-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive TRIP12 of EPWM-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive TRIP12 of EPWM-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive TRIP12 of EPWM-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive TRIP12 of EPWM-XBAR +}; + +union TRIP12MUXENABLE_REG { + Uint32 all; + struct TRIP12MUXENABLE_BITS bit; +}; + +struct TRIPOUTINV_BITS { // bits description + Uint16 TRIP4:1; // 0 Selects polarity for TRIP4 of EPWM-XBAR + Uint16 TRIP5:1; // 1 Selects polarity for TRIP5 of EPWM-XBAR + Uint16 TRIP7:1; // 2 Selects polarity for TRIP7 of EPWM-XBAR + Uint16 TRIP8:1; // 3 Selects polarity for TRIP8 of EPWM-XBAR + Uint16 TRIP9:1; // 4 Selects polarity for TRIP9 of EPWM-XBAR + Uint16 TRIP10:1; // 5 Selects polarity for TRIP10 of EPWM-XBAR + Uint16 TRIP11:1; // 6 Selects polarity for TRIP11 of EPWM-XBAR + Uint16 TRIP12:1; // 7 Selects polarity for TRIP12 of EPWM-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union TRIPOUTINV_REG { + Uint32 all; + struct TRIPOUTINV_BITS bit; +}; + +struct TRIPLOCK_BITS { // bits description + Uint16 LOCK:1; // 0 Locks the configuration for EPWM-XBAR + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 KEY:16; // 31:16 Write protection KEY +}; + +union TRIPLOCK_REG { + Uint32 all; + struct TRIPLOCK_BITS bit; +}; + +struct EPWM_XBAR_REGS { + union TRIP4MUX0TO15CFG_REG TRIP4MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP4 + union TRIP4MUX16TO31CFG_REG TRIP4MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP4 + union TRIP5MUX0TO15CFG_REG TRIP5MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP5 + union TRIP5MUX16TO31CFG_REG TRIP5MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP5 + union TRIP7MUX0TO15CFG_REG TRIP7MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP7 + union TRIP7MUX16TO31CFG_REG TRIP7MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP7 + union TRIP8MUX0TO15CFG_REG TRIP8MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP8 + union TRIP8MUX16TO31CFG_REG TRIP8MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP8 + union TRIP9MUX0TO15CFG_REG TRIP9MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP9 + union TRIP9MUX16TO31CFG_REG TRIP9MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP9 + union TRIP10MUX0TO15CFG_REG TRIP10MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP10 + union TRIP10MUX16TO31CFG_REG TRIP10MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP10 + union TRIP11MUX0TO15CFG_REG TRIP11MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP11 + union TRIP11MUX16TO31CFG_REG TRIP11MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP11 + union TRIP12MUX0TO15CFG_REG TRIP12MUX0TO15CFG; // ePWM XBAR Mux Configuration for TRIP12 + union TRIP12MUX16TO31CFG_REG TRIP12MUX16TO31CFG; // ePWM XBAR Mux Configuration for TRIP12 + union TRIP4MUXENABLE_REG TRIP4MUXENABLE; // ePWM XBAR Mux Enable for TRIP4 + union TRIP5MUXENABLE_REG TRIP5MUXENABLE; // ePWM XBAR Mux Enable for TRIP5 + union TRIP7MUXENABLE_REG TRIP7MUXENABLE; // ePWM XBAR Mux Enable for TRIP7 + union TRIP8MUXENABLE_REG TRIP8MUXENABLE; // ePWM XBAR Mux Enable for TRIP8 + union TRIP9MUXENABLE_REG TRIP9MUXENABLE; // ePWM XBAR Mux Enable for TRIP9 + union TRIP10MUXENABLE_REG TRIP10MUXENABLE; // ePWM XBAR Mux Enable for TRIP10 + union TRIP11MUXENABLE_REG TRIP11MUXENABLE; // ePWM XBAR Mux Enable for TRIP11 + union TRIP12MUXENABLE_REG TRIP12MUXENABLE; // ePWM XBAR Mux Enable for TRIP12 + Uint16 rsvd1[8]; // Reserved + union TRIPOUTINV_REG TRIPOUTINV; // ePWM XBAR Output Inversion Register + Uint16 rsvd2[4]; // Reserved + union TRIPLOCK_REG TRIPLOCK; // ePWM XBAR Configuration Lock register +}; + +//--------------------------------------------------------------------------- +// EPWM_XBAR External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct EPWM_XBAR_REGS EPwmXbarRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_eqep.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_eqep.h new file mode 100644 index 0000000000..f37da095a9 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_eqep.h @@ -0,0 +1,267 @@ +//########################################################################### +// +// FILE: F2837xD_eqep.h +// +// TITLE: EQEP Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_EQEP_H__ +#define __F2837xD_EQEP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// EQEP Individual Register Bit Definitions: + +struct QDECCTL_BITS { // bits description + Uint16 rsvd1:5; // 4:0 Reserved + Uint16 QSP:1; // 5 QEPS input polarity + Uint16 QIP:1; // 6 QEPI input polarity + Uint16 QBP:1; // 7 QEPB input polarity + Uint16 QAP:1; // 8 QEPA input polarity + Uint16 IGATE:1; // 9 Index pulse gating option + Uint16 SWAP:1; // 10 CLK/DIR Signal Source for Position Counter + Uint16 XCR:1; // 11 External Clock Rate + Uint16 SPSEL:1; // 12 Sync output pin selection + Uint16 SOEN:1; // 13 Sync output-enable + Uint16 QSRC:2; // 15:14 Position-counter source selection +}; + +union QDECCTL_REG { + Uint16 all; + struct QDECCTL_BITS bit; +}; + +struct QEPCTL_BITS { // bits description + Uint16 WDE:1; // 0 QEP watchdog enable + Uint16 UTE:1; // 1 QEP unit timer enable + Uint16 QCLM:1; // 2 QEP capture latch mode + Uint16 QPEN:1; // 3 Quadrature postotion counter enable + Uint16 IEL:2; // 5:4 Index event latch + Uint16 SEL:1; // 6 Strobe event latch + Uint16 SWI:1; // 7 Software init position counter + Uint16 IEI:2; // 9:8 Index event init of position count + Uint16 SEI:2; // 11:10 Strobe event init + Uint16 PCRM:2; // 13:12 Postion counter reset + Uint16 FREE_SOFT:2; // 15:14 Emulation mode +}; + +union QEPCTL_REG { + Uint16 all; + struct QEPCTL_BITS bit; +}; + +struct QCAPCTL_BITS { // bits description + Uint16 UPPS:4; // 3:0 Unit position event prescaler + Uint16 CCPS:3; // 6:4 eQEP capture timer clock prescaler + Uint16 rsvd1:8; // 14:7 Reserved + Uint16 CEN:1; // 15 Enable eQEP capture +}; + +union QCAPCTL_REG { + Uint16 all; + struct QCAPCTL_BITS bit; +}; + +struct QPOSCTL_BITS { // bits description + Uint16 PCSPW:12; // 11:0 Position compare sync pulse width + Uint16 PCE:1; // 12 Position compare enable/disable + Uint16 PCPOL:1; // 13 Polarity of sync output + Uint16 PCLOAD:1; // 14 Position compare of shadow load + Uint16 PCSHDW:1; // 15 Position compare of shadow enable +}; + +union QPOSCTL_REG { + Uint16 all; + struct QPOSCTL_BITS bit; +}; + +struct QEINT_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 PCE:1; // 1 Position counter error interrupt enable + Uint16 QPE:1; // 2 Quadrature phase error interrupt enable + Uint16 QDC:1; // 3 Quadrature direction change interrupt enable + Uint16 WTO:1; // 4 Watchdog time out interrupt enable + Uint16 PCU:1; // 5 Position counter underflow interrupt enable + Uint16 PCO:1; // 6 Position counter overflow interrupt enable + Uint16 PCR:1; // 7 Position-compare ready interrupt enable + Uint16 PCM:1; // 8 Position-compare match interrupt enable + Uint16 SEL:1; // 9 Strobe event latch interrupt enable + Uint16 IEL:1; // 10 Index event latch interrupt enable + Uint16 UTO:1; // 11 Unit time out interrupt enable + Uint16 rsvd2:4; // 15:12 Reserved +}; + +union QEINT_REG { + Uint16 all; + struct QEINT_BITS bit; +}; + +struct QFLG_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt status flag + Uint16 PCE:1; // 1 Position counter error interrupt flag + Uint16 PHE:1; // 2 Quadrature phase error interrupt flag + Uint16 QDC:1; // 3 Quadrature direction change interrupt flag + Uint16 WTO:1; // 4 Watchdog timeout interrupt flag + Uint16 PCU:1; // 5 Position counter underflow interrupt flag + Uint16 PCO:1; // 6 Position counter overflow interrupt flag + Uint16 PCR:1; // 7 Position-compare ready interrupt flag + Uint16 PCM:1; // 8 eQEP compare match event interrupt flag + Uint16 SEL:1; // 9 Strobe event latch interrupt flag + Uint16 IEL:1; // 10 Index event latch interrupt flag + Uint16 UTO:1; // 11 Unit time out interrupt flag + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union QFLG_REG { + Uint16 all; + struct QFLG_BITS bit; +}; + +struct QCLR_BITS { // bits description + Uint16 INT:1; // 0 Global interrupt clear flag + Uint16 PCE:1; // 1 Clear position counter error interrupt flag + Uint16 PHE:1; // 2 Clear quadrature phase error interrupt flag + Uint16 QDC:1; // 3 Clear quadrature direction change interrupt flag + Uint16 WTO:1; // 4 Clear watchdog timeout interrupt flag + Uint16 PCU:1; // 5 Clear position counter underflow interrupt flag + Uint16 PCO:1; // 6 Clear position counter overflow interrupt flag + Uint16 PCR:1; // 7 Clear position-compare ready interrupt flag + Uint16 PCM:1; // 8 Clear eQEP compare match event interrupt flag + Uint16 SEL:1; // 9 Clear strobe event latch interrupt flag + Uint16 IEL:1; // 10 Clear index event latch interrupt flag + Uint16 UTO:1; // 11 Clear unit time out interrupt flag + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union QCLR_REG { + Uint16 all; + struct QCLR_BITS bit; +}; + +struct QFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 PCE:1; // 1 Force position counter error interrupt + Uint16 PHE:1; // 2 Force quadrature phase error interrupt + Uint16 QDC:1; // 3 Force quadrature direction change interrupt + Uint16 WTO:1; // 4 Force watchdog time out interrupt + Uint16 PCU:1; // 5 Force position counter underflow interrupt + Uint16 PCO:1; // 6 Force position counter overflow interrupt + Uint16 PCR:1; // 7 Force position-compare ready interrupt + Uint16 PCM:1; // 8 Force position-compare match interrupt + Uint16 SEL:1; // 9 Force strobe event latch interrupt + Uint16 IEL:1; // 10 Force index event latch interrupt + Uint16 UTO:1; // 11 Force unit time out interrupt + Uint16 rsvd2:4; // 15:12 Reserved +}; + +union QFRC_REG { + Uint16 all; + struct QFRC_BITS bit; +}; + +struct QEPSTS_BITS { // bits description + Uint16 PCEF:1; // 0 Position counter error flag. + Uint16 FIMF:1; // 1 First index marker flag + Uint16 CDEF:1; // 2 Capture direction error flag + Uint16 COEF:1; // 3 Capture overflow error flag + Uint16 QDLF:1; // 4 eQEP direction latch flag + Uint16 QDF:1; // 5 Quadrature direction flag + Uint16 FIDF:1; // 6 The first index marker + Uint16 UPEVNT:1; // 7 Unit position event flag + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union QEPSTS_REG { + Uint16 all; + struct QEPSTS_BITS bit; +}; + +struct EQEP_REGS { + Uint32 QPOSCNT; // Position Counter + Uint32 QPOSINIT; // Position Counter Init + Uint32 QPOSMAX; // Maximum Position Count + Uint32 QPOSCMP; // Position Compare + Uint32 QPOSILAT; // Index Position Latch + Uint32 QPOSSLAT; // Strobe Position Latch + Uint32 QPOSLAT; // Position Latch + Uint32 QUTMR; // QEP Unit Timer + Uint32 QUPRD; // QEP Unit Period + Uint16 QWDTMR; // QEP Watchdog Timer + Uint16 QWDPRD; // QEP Watchdog Period + union QDECCTL_REG QDECCTL; // Quadrature Decoder Control + union QEPCTL_REG QEPCTL; // QEP Control + union QCAPCTL_REG QCAPCTL; // Qaudrature Capture Control + union QPOSCTL_REG QPOSCTL; // Position Compare Control + union QEINT_REG QEINT; // QEP Interrupt Control + union QFLG_REG QFLG; // QEP Interrupt Flag + union QCLR_REG QCLR; // QEP Interrupt Clear + union QFRC_REG QFRC; // QEP Interrupt Force + union QEPSTS_REG QEPSTS; // QEP Status + Uint16 QCTMR; // QEP Capture Timer + Uint16 QCPRD; // QEP Capture Period + Uint16 QCTMRLAT; // QEP Capture Latch + Uint16 QCPRDLAT; // QEP Capture Period Latch + Uint16 rsvd1; // Reserved +}; + +//--------------------------------------------------------------------------- +// EQEP External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; +extern volatile struct EQEP_REGS EQep3Regs; +#endif +#ifdef CPU2 +extern volatile struct EQEP_REGS EQep1Regs; +extern volatile struct EQEP_REGS EQep2Regs; +extern volatile struct EQEP_REGS EQep3Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_flash.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_flash.h new file mode 100644 index 0000000000..2882c6a96d --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_flash.h @@ -0,0 +1,376 @@ +//########################################################################### +// +// FILE: F2837xD_flash.h +// +// TITLE: FLASH Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_FLASH_H__ +#define __F2837xD_FLASH_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// FLASH Individual Register Bit Definitions: + +struct FRDCNTL_BITS { // bits description + Uint16 rsvd1:8; // 7:0 Reserved + Uint16 RWAIT:4; // 11:8 Random Read Waitstate + Uint16 rsvd2:4; // 15:12 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union FRDCNTL_REG { + Uint32 all; + struct FRDCNTL_BITS bit; +}; + +struct FBAC_BITS { // bits description + Uint16 VREADST:8; // 7:0 VREAD Setup Time Count + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FBAC_REG { + Uint32 all; + struct FBAC_BITS bit; +}; + +struct FBFALLBACK_BITS { // bits description + Uint16 BNKPWR0:2; // 1:0 Bank Power Mode + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FBFALLBACK_REG { + Uint32 all; + struct FBFALLBACK_BITS bit; +}; + +struct FBPRDY_BITS { // bits description + Uint16 BANKRDY:1; // 0 Flash Bank Active Power State + Uint16 rsvd1:14; // 14:1 Reserved + Uint16 PUMPRDY:1; // 15 Flash Pump Active Power Mode + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FBPRDY_REG { + Uint32 all; + struct FBPRDY_BITS bit; +}; + +struct FPAC1_BITS { // bits description + Uint16 PMPPWR:1; // 0 Charge Pump Fallback Power Mode + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 PSLEEP:12; // 27:16 Pump Sleep Down Count + Uint16 rsvd2:4; // 31:28 Reserved +}; + +union FPAC1_REG { + Uint32 all; + struct FPAC1_BITS bit; +}; + +struct FMSTAT_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 VOLTSTAT:1; // 3 Flash Pump Power Status + Uint16 CSTAT:1; // 4 Command Fail Status + Uint16 INVDAT:1; // 5 Invalid Data + Uint16 PGM:1; // 6 Program Operation Status + Uint16 ERS:1; // 7 Erase Operation Status + Uint16 BUSY:1; // 8 Busy Bit + Uint16 rsvd4:1; // 9 Reserved + Uint16 EV:1; // 10 Erase Verify Status + Uint16 rsvd5:1; // 11 Reserved + Uint16 PGV:1; // 12 Programming Verify Status + Uint16 rsvd6:1; // 13 Reserved + Uint16 rsvd7:1; // 14 Reserved + Uint16 rsvd8:1; // 15 Reserved + Uint16 rsvd9:1; // 16 Reserved + Uint16 rsvd10:1; // 17 Reserved + Uint16 rsvd11:14; // 31:18 Reserved +}; + +union FMSTAT_REG { + Uint32 all; + struct FMSTAT_BITS bit; +}; + +struct FRD_INTF_CTRL_BITS { // bits description + Uint16 PREFETCH_EN:1; // 0 Prefetch Enable + Uint16 DATA_CACHE_EN:1; // 1 Data Cache Enable + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FRD_INTF_CTRL_REG { + Uint32 all; + struct FRD_INTF_CTRL_BITS bit; +}; + +struct FLASH_CTRL_REGS { + union FRDCNTL_REG FRDCNTL; // Flash Read Control Register + Uint16 rsvd1[28]; // Reserved + union FBAC_REG FBAC; // Flash Bank Access Control Register + union FBFALLBACK_REG FBFALLBACK; // Flash Bank Fallback Power Register + union FBPRDY_REG FBPRDY; // Flash Bank Pump Ready Register + union FPAC1_REG FPAC1; // Flash Pump Access Control Register 1 + Uint16 rsvd2[4]; // Reserved + union FMSTAT_REG FMSTAT; // Flash Module Status Register + Uint16 rsvd3[340]; // Reserved + union FRD_INTF_CTRL_REG FRD_INTF_CTRL; // Flash Read Interface Control Register +}; + +struct ECC_ENABLE_BITS { // bits description + Uint16 ENABLE:4; // 3:0 Enable ECC + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union ECC_ENABLE_REG { + Uint32 all; + struct ECC_ENABLE_BITS bit; +}; + +struct ERR_STATUS_BITS { // bits description + Uint16 FAIL_0_L:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 + Uint16 FAIL_1_L:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 + Uint16 UNC_ERR_L:1; // 2 Lower 64 bits Uncorrectable error occurred + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 FAIL_0_H:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 + Uint16 FAIL_1_H:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 + Uint16 UNC_ERR_H:1; // 18 Upper 64 bits Uncorrectable error occurred + Uint16 rsvd2:13; // 31:19 Reserved +}; + +union ERR_STATUS_REG { + Uint32 all; + struct ERR_STATUS_BITS bit; +}; + +struct ERR_POS_BITS { // bits description + Uint16 ERR_POS_L:6; // 5:0 Bit Position of Single bit Error in lower 64 bits + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 ERR_TYPE_L:1; // 8 Error Type in lower 64 bits + Uint16 rsvd2:7; // 15:9 Reserved + Uint16 ERR_POS_H:6; // 21:16 Bit Position of Single bit Error in upper 64 bits + Uint16 rsvd3:2; // 23:22 Reserved + Uint16 ERR_TYPE_H:1; // 24 Error Type in upper 64 bits + Uint16 rsvd4:7; // 31:25 Reserved +}; + +union ERR_POS_REG { + Uint32 all; + struct ERR_POS_BITS bit; +}; + +struct ERR_STATUS_CLR_BITS { // bits description + Uint16 FAIL_0_L_CLR:1; // 0 Lower 64bits Single Bit Error Corrected Value 0 Clear + Uint16 FAIL_1_L_CLR:1; // 1 Lower 64bits Single Bit Error Corrected Value 1 Clear + Uint16 UNC_ERR_L_CLR:1; // 2 Lower 64 bits Uncorrectable error occurred Clear + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 FAIL_0_H_CLR:1; // 16 Upper 64bits Single Bit Error Corrected Value 0 Clear + Uint16 FAIL_1_H_CLR:1; // 17 Upper 64bits Single Bit Error Corrected Value 1 Clear + Uint16 UNC_ERR_H_CLR:1; // 18 Upper 64 bits Uncorrectable error occurred Clear + Uint16 rsvd2:13; // 31:19 Reserved +}; + +union ERR_STATUS_CLR_REG { + Uint32 all; + struct ERR_STATUS_CLR_BITS bit; +}; + +struct ERR_CNT_BITS { // bits description + Uint16 ERR_CNT:16; // 15:0 Error counter + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union ERR_CNT_REG { + Uint32 all; + struct ERR_CNT_BITS bit; +}; + +struct ERR_THRESHOLD_BITS { // bits description + Uint16 ERR_THRESHOLD:16; // 15:0 Error Threshold + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union ERR_THRESHOLD_REG { + Uint32 all; + struct ERR_THRESHOLD_BITS bit; +}; + +struct ERR_INTFLG_BITS { // bits description + Uint16 SINGLE_ERR_INTFLG:1; // 0 Single Error Interrupt Flag + Uint16 UNC_ERR_INTFLG:1; // 1 Uncorrectable Interrupt Flag + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union ERR_INTFLG_REG { + Uint32 all; + struct ERR_INTFLG_BITS bit; +}; + +struct ERR_INTCLR_BITS { // bits description + Uint16 SINGLE_ERR_INTCLR:1; // 0 Single Error Interrupt Flag Clear + Uint16 UNC_ERR_INTCLR:1; // 1 Uncorrectable Interrupt Flag Clear + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union ERR_INTCLR_REG { + Uint32 all; + struct ERR_INTCLR_BITS bit; +}; + +struct FADDR_TEST_BITS { // bits description + Uint16 rsvd1:3; // 2:0 Reserved + Uint16 ADDRL:13; // 15:3 ECC Address Low + Uint16 ADDRH:6; // 21:16 ECC Address High + Uint16 rsvd2:10; // 31:22 Reserved +}; + +union FADDR_TEST_REG { + Uint32 all; + struct FADDR_TEST_BITS bit; +}; + +struct FECC_TEST_BITS { // bits description + Uint16 ECC:8; // 7:0 ECC Control Bits + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FECC_TEST_REG { + Uint32 all; + struct FECC_TEST_BITS bit; +}; + +struct FECC_CTRL_BITS { // bits description + Uint16 ECC_TEST_EN:1; // 0 Enable ECC Test Logic + Uint16 ECC_SELECT:1; // 1 ECC Bit Select + Uint16 DO_ECC_CALC:1; // 2 Enable ECC Calculation + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FECC_CTRL_REG { + Uint32 all; + struct FECC_CTRL_BITS bit; +}; + +struct FECC_STATUS_BITS { // bits description + Uint16 SINGLE_ERR:1; // 0 Test Result is Single Bit Error + Uint16 UNC_ERR:1; // 1 Test Result is Uncorrectable Error + Uint16 DATA_ERR_POS:6; // 7:2 Holds Bit Position of Error + Uint16 ERR_TYPE:1; // 8 Holds Bit Position of 8 Check Bits of Error + Uint16 rsvd1:7; // 15:9 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FECC_STATUS_REG { + Uint32 all; + struct FECC_STATUS_BITS bit; +}; + +struct FLASH_ECC_REGS { + union ECC_ENABLE_REG ECC_ENABLE; // ECC Enable + Uint32 SINGLE_ERR_ADDR_LOW; // Single Error Address Low + Uint32 SINGLE_ERR_ADDR_HIGH; // Single Error Address High + Uint32 UNC_ERR_ADDR_LOW; // Uncorrectable Error Address Low + Uint32 UNC_ERR_ADDR_HIGH; // Uncorrectable Error Address High + union ERR_STATUS_REG ERR_STATUS; // Error Status + union ERR_POS_REG ERR_POS; // Error Position + union ERR_STATUS_CLR_REG ERR_STATUS_CLR; // Error Status Clear + union ERR_CNT_REG ERR_CNT; // Error Control + union ERR_THRESHOLD_REG ERR_THRESHOLD; // Error Threshold + union ERR_INTFLG_REG ERR_INTFLG; // Error Interrupt Flag + union ERR_INTCLR_REG ERR_INTCLR; // Error Interrupt Flag Clear + Uint32 FDATAH_TEST; // Data High Test + Uint32 FDATAL_TEST; // Data Low Test + union FADDR_TEST_REG FADDR_TEST; // ECC Test Address + union FECC_TEST_REG FECC_TEST; // ECC Test Address + union FECC_CTRL_REG FECC_CTRL; // ECC Control + Uint32 FOUTH_TEST; // Test Data Out High + Uint32 FOUTL_TEST; // Test Data Out Low + union FECC_STATUS_REG FECC_STATUS; // ECC Status +}; + +struct PUMPREQUEST_BITS { // bits description + Uint16 PUMP_OWNERSHIP:2; // 1:0 Flash Pump Request Semaphore between CPU1 and CPU2 + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register +}; + +union PUMPREQUEST_REG { + Uint32 all; + struct PUMPREQUEST_BITS bit; +}; + +struct FLASH_PUMP_SEMAPHORE_REGS { + union PUMPREQUEST_REG PUMPREQUEST; // Flash programming semaphore PUMP request register +}; + +//--------------------------------------------------------------------------- +// FLASH External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; +extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; +extern volatile struct FLASH_ECC_REGS Flash0EccRegs; +#endif +#ifdef CPU2 +extern volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; +extern volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; +extern volatile struct FLASH_ECC_REGS Flash0EccRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_gpio.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_gpio.h new file mode 100644 index 0000000000..7aeb219836 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_gpio.h @@ -0,0 +1,3882 @@ +//########################################################################### +// +// FILE: F2837xD_gpio.h +// +// TITLE: GPIO Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_GPIO_H__ +#define __F2837xD_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// GPIO Individual Register Bit Definitions: + +struct GPACTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO0 to GPIO7 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO8 to GPIO15 + Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO16 to GPIO23 + Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO24 to GPIO31 +}; + +union GPACTRL_REG { + Uint32 all; + struct GPACTRL_BITS bit; +}; + +struct GPAQSEL1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 Select input qualification type for GPIO0 + Uint16 GPIO1:2; // 3:2 Select input qualification type for GPIO1 + Uint16 GPIO2:2; // 5:4 Select input qualification type for GPIO2 + Uint16 GPIO3:2; // 7:6 Select input qualification type for GPIO3 + Uint16 GPIO4:2; // 9:8 Select input qualification type for GPIO4 + Uint16 GPIO5:2; // 11:10 Select input qualification type for GPIO5 + Uint16 GPIO6:2; // 13:12 Select input qualification type for GPIO6 + Uint16 GPIO7:2; // 15:14 Select input qualification type for GPIO7 + Uint16 GPIO8:2; // 17:16 Select input qualification type for GPIO8 + Uint16 GPIO9:2; // 19:18 Select input qualification type for GPIO9 + Uint16 GPIO10:2; // 21:20 Select input qualification type for GPIO10 + Uint16 GPIO11:2; // 23:22 Select input qualification type for GPIO11 + Uint16 GPIO12:2; // 25:24 Select input qualification type for GPIO12 + Uint16 GPIO13:2; // 27:26 Select input qualification type for GPIO13 + Uint16 GPIO14:2; // 29:28 Select input qualification type for GPIO14 + Uint16 GPIO15:2; // 31:30 Select input qualification type for GPIO15 +}; + +union GPAQSEL1_REG { + Uint32 all; + struct GPAQSEL1_BITS bit; +}; + +struct GPAQSEL2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 Select input qualification type for GPIO16 + Uint16 GPIO17:2; // 3:2 Select input qualification type for GPIO17 + Uint16 GPIO18:2; // 5:4 Select input qualification type for GPIO18 + Uint16 GPIO19:2; // 7:6 Select input qualification type for GPIO19 + Uint16 GPIO20:2; // 9:8 Select input qualification type for GPIO20 + Uint16 GPIO21:2; // 11:10 Select input qualification type for GPIO21 + Uint16 GPIO22:2; // 13:12 Select input qualification type for GPIO22 + Uint16 GPIO23:2; // 15:14 Select input qualification type for GPIO23 + Uint16 GPIO24:2; // 17:16 Select input qualification type for GPIO24 + Uint16 GPIO25:2; // 19:18 Select input qualification type for GPIO25 + Uint16 GPIO26:2; // 21:20 Select input qualification type for GPIO26 + Uint16 GPIO27:2; // 23:22 Select input qualification type for GPIO27 + Uint16 GPIO28:2; // 25:24 Select input qualification type for GPIO28 + Uint16 GPIO29:2; // 27:26 Select input qualification type for GPIO29 + Uint16 GPIO30:2; // 29:28 Select input qualification type for GPIO30 + Uint16 GPIO31:2; // 31:30 Select input qualification type for GPIO31 +}; + +union GPAQSEL2_REG { + Uint32 all; + struct GPAQSEL2_BITS bit; +}; + +struct GPAMUX1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 + Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 + Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 + Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 + Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 + Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 + Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 + Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 + Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 + Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 + Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 + Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 + Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 + Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 + Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 + Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 +}; + +union GPAMUX1_REG { + Uint32 all; + struct GPAMUX1_BITS bit; +}; + +struct GPAMUX2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 + Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 + Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 + Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 + Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 + Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 + Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 + Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 + Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 + Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 + Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 + Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 + Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 + Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 + Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 + Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 +}; + +union GPAMUX2_REG { + Uint32 all; + struct GPAMUX2_BITS bit; +}; + +struct GPADIR_BITS { // bits description + Uint16 GPIO0:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO1:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO2:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO3:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO4:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO5:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO6:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO7:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO8:1; // 8 Defines direction for this pin in GPIO mode + Uint16 GPIO9:1; // 9 Defines direction for this pin in GPIO mode + Uint16 GPIO10:1; // 10 Defines direction for this pin in GPIO mode + Uint16 GPIO11:1; // 11 Defines direction for this pin in GPIO mode + Uint16 GPIO12:1; // 12 Defines direction for this pin in GPIO mode + Uint16 GPIO13:1; // 13 Defines direction for this pin in GPIO mode + Uint16 GPIO14:1; // 14 Defines direction for this pin in GPIO mode + Uint16 GPIO15:1; // 15 Defines direction for this pin in GPIO mode + Uint16 GPIO16:1; // 16 Defines direction for this pin in GPIO mode + Uint16 GPIO17:1; // 17 Defines direction for this pin in GPIO mode + Uint16 GPIO18:1; // 18 Defines direction for this pin in GPIO mode + Uint16 GPIO19:1; // 19 Defines direction for this pin in GPIO mode + Uint16 GPIO20:1; // 20 Defines direction for this pin in GPIO mode + Uint16 GPIO21:1; // 21 Defines direction for this pin in GPIO mode + Uint16 GPIO22:1; // 22 Defines direction for this pin in GPIO mode + Uint16 GPIO23:1; // 23 Defines direction for this pin in GPIO mode + Uint16 GPIO24:1; // 24 Defines direction for this pin in GPIO mode + Uint16 GPIO25:1; // 25 Defines direction for this pin in GPIO mode + Uint16 GPIO26:1; // 26 Defines direction for this pin in GPIO mode + Uint16 GPIO27:1; // 27 Defines direction for this pin in GPIO mode + Uint16 GPIO28:1; // 28 Defines direction for this pin in GPIO mode + Uint16 GPIO29:1; // 29 Defines direction for this pin in GPIO mode + Uint16 GPIO30:1; // 30 Defines direction for this pin in GPIO mode + Uint16 GPIO31:1; // 31 Defines direction for this pin in GPIO mode +}; + +union GPADIR_REG { + Uint32 all; + struct GPADIR_BITS bit; +}; + +struct GPAPUD_BITS { // bits description + Uint16 GPIO0:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO1:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO2:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO3:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO4:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO5:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO6:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO7:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO8:1; // 8 Pull-Up Disable control for this pin + Uint16 GPIO9:1; // 9 Pull-Up Disable control for this pin + Uint16 GPIO10:1; // 10 Pull-Up Disable control for this pin + Uint16 GPIO11:1; // 11 Pull-Up Disable control for this pin + Uint16 GPIO12:1; // 12 Pull-Up Disable control for this pin + Uint16 GPIO13:1; // 13 Pull-Up Disable control for this pin + Uint16 GPIO14:1; // 14 Pull-Up Disable control for this pin + Uint16 GPIO15:1; // 15 Pull-Up Disable control for this pin + Uint16 GPIO16:1; // 16 Pull-Up Disable control for this pin + Uint16 GPIO17:1; // 17 Pull-Up Disable control for this pin + Uint16 GPIO18:1; // 18 Pull-Up Disable control for this pin + Uint16 GPIO19:1; // 19 Pull-Up Disable control for this pin + Uint16 GPIO20:1; // 20 Pull-Up Disable control for this pin + Uint16 GPIO21:1; // 21 Pull-Up Disable control for this pin + Uint16 GPIO22:1; // 22 Pull-Up Disable control for this pin + Uint16 GPIO23:1; // 23 Pull-Up Disable control for this pin + Uint16 GPIO24:1; // 24 Pull-Up Disable control for this pin + Uint16 GPIO25:1; // 25 Pull-Up Disable control for this pin + Uint16 GPIO26:1; // 26 Pull-Up Disable control for this pin + Uint16 GPIO27:1; // 27 Pull-Up Disable control for this pin + Uint16 GPIO28:1; // 28 Pull-Up Disable control for this pin + Uint16 GPIO29:1; // 29 Pull-Up Disable control for this pin + Uint16 GPIO30:1; // 30 Pull-Up Disable control for this pin + Uint16 GPIO31:1; // 31 Pull-Up Disable control for this pin +}; + +union GPAPUD_REG { + Uint32 all; + struct GPAPUD_BITS bit; +}; + +struct GPAINV_BITS { // bits description + Uint16 GPIO0:1; // 0 Input inversion control for this pin + Uint16 GPIO1:1; // 1 Input inversion control for this pin + Uint16 GPIO2:1; // 2 Input inversion control for this pin + Uint16 GPIO3:1; // 3 Input inversion control for this pin + Uint16 GPIO4:1; // 4 Input inversion control for this pin + Uint16 GPIO5:1; // 5 Input inversion control for this pin + Uint16 GPIO6:1; // 6 Input inversion control for this pin + Uint16 GPIO7:1; // 7 Input inversion control for this pin + Uint16 GPIO8:1; // 8 Input inversion control for this pin + Uint16 GPIO9:1; // 9 Input inversion control for this pin + Uint16 GPIO10:1; // 10 Input inversion control for this pin + Uint16 GPIO11:1; // 11 Input inversion control for this pin + Uint16 GPIO12:1; // 12 Input inversion control for this pin + Uint16 GPIO13:1; // 13 Input inversion control for this pin + Uint16 GPIO14:1; // 14 Input inversion control for this pin + Uint16 GPIO15:1; // 15 Input inversion control for this pin + Uint16 GPIO16:1; // 16 Input inversion control for this pin + Uint16 GPIO17:1; // 17 Input inversion control for this pin + Uint16 GPIO18:1; // 18 Input inversion control for this pin + Uint16 GPIO19:1; // 19 Input inversion control for this pin + Uint16 GPIO20:1; // 20 Input inversion control for this pin + Uint16 GPIO21:1; // 21 Input inversion control for this pin + Uint16 GPIO22:1; // 22 Input inversion control for this pin + Uint16 GPIO23:1; // 23 Input inversion control for this pin + Uint16 GPIO24:1; // 24 Input inversion control for this pin + Uint16 GPIO25:1; // 25 Input inversion control for this pin + Uint16 GPIO26:1; // 26 Input inversion control for this pin + Uint16 GPIO27:1; // 27 Input inversion control for this pin + Uint16 GPIO28:1; // 28 Input inversion control for this pin + Uint16 GPIO29:1; // 29 Input inversion control for this pin + Uint16 GPIO30:1; // 30 Input inversion control for this pin + Uint16 GPIO31:1; // 31 Input inversion control for this pin +}; + +union GPAINV_REG { + Uint32 all; + struct GPAINV_BITS bit; +}; + +struct GPAODR_BITS { // bits description + Uint16 GPIO0:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO1:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO2:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO3:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO4:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO5:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO6:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO7:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO8:1; // 8 Outpout Open-Drain control for this pin + Uint16 GPIO9:1; // 9 Outpout Open-Drain control for this pin + Uint16 GPIO10:1; // 10 Outpout Open-Drain control for this pin + Uint16 GPIO11:1; // 11 Outpout Open-Drain control for this pin + Uint16 GPIO12:1; // 12 Outpout Open-Drain control for this pin + Uint16 GPIO13:1; // 13 Outpout Open-Drain control for this pin + Uint16 GPIO14:1; // 14 Outpout Open-Drain control for this pin + Uint16 GPIO15:1; // 15 Outpout Open-Drain control for this pin + Uint16 GPIO16:1; // 16 Outpout Open-Drain control for this pin + Uint16 GPIO17:1; // 17 Outpout Open-Drain control for this pin + Uint16 GPIO18:1; // 18 Outpout Open-Drain control for this pin + Uint16 GPIO19:1; // 19 Outpout Open-Drain control for this pin + Uint16 GPIO20:1; // 20 Outpout Open-Drain control for this pin + Uint16 GPIO21:1; // 21 Outpout Open-Drain control for this pin + Uint16 GPIO22:1; // 22 Outpout Open-Drain control for this pin + Uint16 GPIO23:1; // 23 Outpout Open-Drain control for this pin + Uint16 GPIO24:1; // 24 Outpout Open-Drain control for this pin + Uint16 GPIO25:1; // 25 Outpout Open-Drain control for this pin + Uint16 GPIO26:1; // 26 Outpout Open-Drain control for this pin + Uint16 GPIO27:1; // 27 Outpout Open-Drain control for this pin + Uint16 GPIO28:1; // 28 Outpout Open-Drain control for this pin + Uint16 GPIO29:1; // 29 Outpout Open-Drain control for this pin + Uint16 GPIO30:1; // 30 Outpout Open-Drain control for this pin + Uint16 GPIO31:1; // 31 Outpout Open-Drain control for this pin +}; + +union GPAODR_REG { + Uint32 all; + struct GPAODR_BITS bit; +}; + +struct GPAGMUX1_BITS { // bits description + Uint16 GPIO0:2; // 1:0 Defines pin-muxing selection for GPIO0 + Uint16 GPIO1:2; // 3:2 Defines pin-muxing selection for GPIO1 + Uint16 GPIO2:2; // 5:4 Defines pin-muxing selection for GPIO2 + Uint16 GPIO3:2; // 7:6 Defines pin-muxing selection for GPIO3 + Uint16 GPIO4:2; // 9:8 Defines pin-muxing selection for GPIO4 + Uint16 GPIO5:2; // 11:10 Defines pin-muxing selection for GPIO5 + Uint16 GPIO6:2; // 13:12 Defines pin-muxing selection for GPIO6 + Uint16 GPIO7:2; // 15:14 Defines pin-muxing selection for GPIO7 + Uint16 GPIO8:2; // 17:16 Defines pin-muxing selection for GPIO8 + Uint16 GPIO9:2; // 19:18 Defines pin-muxing selection for GPIO9 + Uint16 GPIO10:2; // 21:20 Defines pin-muxing selection for GPIO10 + Uint16 GPIO11:2; // 23:22 Defines pin-muxing selection for GPIO11 + Uint16 GPIO12:2; // 25:24 Defines pin-muxing selection for GPIO12 + Uint16 GPIO13:2; // 27:26 Defines pin-muxing selection for GPIO13 + Uint16 GPIO14:2; // 29:28 Defines pin-muxing selection for GPIO14 + Uint16 GPIO15:2; // 31:30 Defines pin-muxing selection for GPIO15 +}; + +union GPAGMUX1_REG { + Uint32 all; + struct GPAGMUX1_BITS bit; +}; + +struct GPAGMUX2_BITS { // bits description + Uint16 GPIO16:2; // 1:0 Defines pin-muxing selection for GPIO16 + Uint16 GPIO17:2; // 3:2 Defines pin-muxing selection for GPIO17 + Uint16 GPIO18:2; // 5:4 Defines pin-muxing selection for GPIO18 + Uint16 GPIO19:2; // 7:6 Defines pin-muxing selection for GPIO19 + Uint16 GPIO20:2; // 9:8 Defines pin-muxing selection for GPIO20 + Uint16 GPIO21:2; // 11:10 Defines pin-muxing selection for GPIO21 + Uint16 GPIO22:2; // 13:12 Defines pin-muxing selection for GPIO22 + Uint16 GPIO23:2; // 15:14 Defines pin-muxing selection for GPIO23 + Uint16 GPIO24:2; // 17:16 Defines pin-muxing selection for GPIO24 + Uint16 GPIO25:2; // 19:18 Defines pin-muxing selection for GPIO25 + Uint16 GPIO26:2; // 21:20 Defines pin-muxing selection for GPIO26 + Uint16 GPIO27:2; // 23:22 Defines pin-muxing selection for GPIO27 + Uint16 GPIO28:2; // 25:24 Defines pin-muxing selection for GPIO28 + Uint16 GPIO29:2; // 27:26 Defines pin-muxing selection for GPIO29 + Uint16 GPIO30:2; // 29:28 Defines pin-muxing selection for GPIO30 + Uint16 GPIO31:2; // 31:30 Defines pin-muxing selection for GPIO31 +}; + +union GPAGMUX2_REG { + Uint32 all; + struct GPAGMUX2_BITS bit; +}; + +struct GPACSEL1_BITS { // bits description + Uint16 GPIO0:4; // 3:0 GPIO0 Master CPU Select + Uint16 GPIO1:4; // 7:4 GPIO1 Master CPU Select + Uint16 GPIO2:4; // 11:8 GPIO2 Master CPU Select + Uint16 GPIO3:4; // 15:12 GPIO3 Master CPU Select + Uint16 GPIO4:4; // 19:16 GPIO4 Master CPU Select + Uint16 GPIO5:4; // 23:20 GPIO5 Master CPU Select + Uint16 GPIO6:4; // 27:24 GPIO6 Master CPU Select + Uint16 GPIO7:4; // 31:28 GPIO7 Master CPU Select +}; + +union GPACSEL1_REG { + Uint32 all; + struct GPACSEL1_BITS bit; +}; + +struct GPACSEL2_BITS { // bits description + Uint16 GPIO8:4; // 3:0 GPIO8 Master CPU Select + Uint16 GPIO9:4; // 7:4 GPIO9 Master CPU Select + Uint16 GPIO10:4; // 11:8 GPIO10 Master CPU Select + Uint16 GPIO11:4; // 15:12 GPIO11 Master CPU Select + Uint16 GPIO12:4; // 19:16 GPIO12 Master CPU Select + Uint16 GPIO13:4; // 23:20 GPIO13 Master CPU Select + Uint16 GPIO14:4; // 27:24 GPIO14 Master CPU Select + Uint16 GPIO15:4; // 31:28 GPIO15 Master CPU Select +}; + +union GPACSEL2_REG { + Uint32 all; + struct GPACSEL2_BITS bit; +}; + +struct GPACSEL3_BITS { // bits description + Uint16 GPIO16:4; // 3:0 GPIO16 Master CPU Select + Uint16 GPIO17:4; // 7:4 GPIO17 Master CPU Select + Uint16 GPIO18:4; // 11:8 GPIO18 Master CPU Select + Uint16 GPIO19:4; // 15:12 GPIO19 Master CPU Select + Uint16 GPIO20:4; // 19:16 GPIO20 Master CPU Select + Uint16 GPIO21:4; // 23:20 GPIO21 Master CPU Select + Uint16 GPIO22:4; // 27:24 GPIO22 Master CPU Select + Uint16 GPIO23:4; // 31:28 GPIO23 Master CPU Select +}; + +union GPACSEL3_REG { + Uint32 all; + struct GPACSEL3_BITS bit; +}; + +struct GPACSEL4_BITS { // bits description + Uint16 GPIO24:4; // 3:0 GPIO24 Master CPU Select + Uint16 GPIO25:4; // 7:4 GPIO25 Master CPU Select + Uint16 GPIO26:4; // 11:8 GPIO26 Master CPU Select + Uint16 GPIO27:4; // 15:12 GPIO27 Master CPU Select + Uint16 GPIO28:4; // 19:16 GPIO28 Master CPU Select + Uint16 GPIO29:4; // 23:20 GPIO29 Master CPU Select + Uint16 GPIO30:4; // 27:24 GPIO30 Master CPU Select + Uint16 GPIO31:4; // 31:28 GPIO31 Master CPU Select +}; + +union GPACSEL4_REG { + Uint32 all; + struct GPACSEL4_BITS bit; +}; + +struct GPALOCK_BITS { // bits description + Uint16 GPIO0:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO1:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO2:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO3:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO4:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO5:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO6:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO7:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO8:1; // 8 Configuration Lock bit for this pin + Uint16 GPIO9:1; // 9 Configuration Lock bit for this pin + Uint16 GPIO10:1; // 10 Configuration Lock bit for this pin + Uint16 GPIO11:1; // 11 Configuration Lock bit for this pin + Uint16 GPIO12:1; // 12 Configuration Lock bit for this pin + Uint16 GPIO13:1; // 13 Configuration Lock bit for this pin + Uint16 GPIO14:1; // 14 Configuration Lock bit for this pin + Uint16 GPIO15:1; // 15 Configuration Lock bit for this pin + Uint16 GPIO16:1; // 16 Configuration Lock bit for this pin + Uint16 GPIO17:1; // 17 Configuration Lock bit for this pin + Uint16 GPIO18:1; // 18 Configuration Lock bit for this pin + Uint16 GPIO19:1; // 19 Configuration Lock bit for this pin + Uint16 GPIO20:1; // 20 Configuration Lock bit for this pin + Uint16 GPIO21:1; // 21 Configuration Lock bit for this pin + Uint16 GPIO22:1; // 22 Configuration Lock bit for this pin + Uint16 GPIO23:1; // 23 Configuration Lock bit for this pin + Uint16 GPIO24:1; // 24 Configuration Lock bit for this pin + Uint16 GPIO25:1; // 25 Configuration Lock bit for this pin + Uint16 GPIO26:1; // 26 Configuration Lock bit for this pin + Uint16 GPIO27:1; // 27 Configuration Lock bit for this pin + Uint16 GPIO28:1; // 28 Configuration Lock bit for this pin + Uint16 GPIO29:1; // 29 Configuration Lock bit for this pin + Uint16 GPIO30:1; // 30 Configuration Lock bit for this pin + Uint16 GPIO31:1; // 31 Configuration Lock bit for this pin +}; + +union GPALOCK_REG { + Uint32 all; + struct GPALOCK_BITS bit; +}; + +struct GPACR_BITS { // bits description + Uint16 GPIO0:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO1:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO2:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO3:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO4:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO5:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO6:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO7:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO8:1; // 8 Configuration lock commit bit for this pin + Uint16 GPIO9:1; // 9 Configuration lock commit bit for this pin + Uint16 GPIO10:1; // 10 Configuration lock commit bit for this pin + Uint16 GPIO11:1; // 11 Configuration lock commit bit for this pin + Uint16 GPIO12:1; // 12 Configuration lock commit bit for this pin + Uint16 GPIO13:1; // 13 Configuration lock commit bit for this pin + Uint16 GPIO14:1; // 14 Configuration lock commit bit for this pin + Uint16 GPIO15:1; // 15 Configuration lock commit bit for this pin + Uint16 GPIO16:1; // 16 Configuration lock commit bit for this pin + Uint16 GPIO17:1; // 17 Configuration lock commit bit for this pin + Uint16 GPIO18:1; // 18 Configuration lock commit bit for this pin + Uint16 GPIO19:1; // 19 Configuration lock commit bit for this pin + Uint16 GPIO20:1; // 20 Configuration lock commit bit for this pin + Uint16 GPIO21:1; // 21 Configuration lock commit bit for this pin + Uint16 GPIO22:1; // 22 Configuration lock commit bit for this pin + Uint16 GPIO23:1; // 23 Configuration lock commit bit for this pin + Uint16 GPIO24:1; // 24 Configuration lock commit bit for this pin + Uint16 GPIO25:1; // 25 Configuration lock commit bit for this pin + Uint16 GPIO26:1; // 26 Configuration lock commit bit for this pin + Uint16 GPIO27:1; // 27 Configuration lock commit bit for this pin + Uint16 GPIO28:1; // 28 Configuration lock commit bit for this pin + Uint16 GPIO29:1; // 29 Configuration lock commit bit for this pin + Uint16 GPIO30:1; // 30 Configuration lock commit bit for this pin + Uint16 GPIO31:1; // 31 Configuration lock commit bit for this pin +}; + +union GPACR_REG { + Uint32 all; + struct GPACR_BITS bit; +}; + +struct GPBCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO32 to GPIO39 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO40 to GPIO47 + Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO48 to GPIO55 + Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO56 to GPIO63 +}; + +union GPBCTRL_REG { + Uint32 all; + struct GPBCTRL_BITS bit; +}; + +struct GPBQSEL1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 Select input qualification type for GPIO32 + Uint16 GPIO33:2; // 3:2 Select input qualification type for GPIO33 + Uint16 GPIO34:2; // 5:4 Select input qualification type for GPIO34 + Uint16 GPIO35:2; // 7:6 Select input qualification type for GPIO35 + Uint16 GPIO36:2; // 9:8 Select input qualification type for GPIO36 + Uint16 GPIO37:2; // 11:10 Select input qualification type for GPIO37 + Uint16 GPIO38:2; // 13:12 Select input qualification type for GPIO38 + Uint16 GPIO39:2; // 15:14 Select input qualification type for GPIO39 + Uint16 GPIO40:2; // 17:16 Select input qualification type for GPIO40 + Uint16 GPIO41:2; // 19:18 Select input qualification type for GPIO41 + Uint16 GPIO42:2; // 21:20 Select input qualification type for GPIO42 + Uint16 GPIO43:2; // 23:22 Select input qualification type for GPIO43 + Uint16 GPIO44:2; // 25:24 Select input qualification type for GPIO44 + Uint16 GPIO45:2; // 27:26 Select input qualification type for GPIO45 + Uint16 GPIO46:2; // 29:28 Select input qualification type for GPIO46 + Uint16 GPIO47:2; // 31:30 Select input qualification type for GPIO47 +}; + +union GPBQSEL1_REG { + Uint32 all; + struct GPBQSEL1_BITS bit; +}; + +struct GPBQSEL2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 Select input qualification type for GPIO48 + Uint16 GPIO49:2; // 3:2 Select input qualification type for GPIO49 + Uint16 GPIO50:2; // 5:4 Select input qualification type for GPIO50 + Uint16 GPIO51:2; // 7:6 Select input qualification type for GPIO51 + Uint16 GPIO52:2; // 9:8 Select input qualification type for GPIO52 + Uint16 GPIO53:2; // 11:10 Select input qualification type for GPIO53 + Uint16 GPIO54:2; // 13:12 Select input qualification type for GPIO54 + Uint16 GPIO55:2; // 15:14 Select input qualification type for GPIO55 + Uint16 GPIO56:2; // 17:16 Select input qualification type for GPIO56 + Uint16 GPIO57:2; // 19:18 Select input qualification type for GPIO57 + Uint16 GPIO58:2; // 21:20 Select input qualification type for GPIO58 + Uint16 GPIO59:2; // 23:22 Select input qualification type for GPIO59 + Uint16 GPIO60:2; // 25:24 Select input qualification type for GPIO60 + Uint16 GPIO61:2; // 27:26 Select input qualification type for GPIO61 + Uint16 GPIO62:2; // 29:28 Select input qualification type for GPIO62 + Uint16 GPIO63:2; // 31:30 Select input qualification type for GPIO63 +}; + +union GPBQSEL2_REG { + Uint32 all; + struct GPBQSEL2_BITS bit; +}; + +struct GPBMUX1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 + Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 + Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 + Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 + Uint16 GPIO36:2; // 9:8 Defines pin-muxing selection for GPIO36 + Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 + Uint16 GPIO38:2; // 13:12 Defines pin-muxing selection for GPIO38 + Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 + Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 + Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 + Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 + Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 + Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 + Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 + Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 + Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 +}; + +union GPBMUX1_REG { + Uint32 all; + struct GPBMUX1_BITS bit; +}; + +struct GPBMUX2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 + Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 + Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 + Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 + Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 + Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 + Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 + Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 + Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 + Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 + Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 + Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 + Uint16 GPIO60:2; // 25:24 Defines pin-muxing selection for GPIO60 + Uint16 GPIO61:2; // 27:26 Defines pin-muxing selection for GPIO61 + Uint16 GPIO62:2; // 29:28 Defines pin-muxing selection for GPIO62 + Uint16 GPIO63:2; // 31:30 Defines pin-muxing selection for GPIO63 +}; + +union GPBMUX2_REG { + Uint32 all; + struct GPBMUX2_BITS bit; +}; + +struct GPBDIR_BITS { // bits description + Uint16 GPIO32:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO33:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO34:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO35:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO36:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO37:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO38:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO39:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO40:1; // 8 Defines direction for this pin in GPIO mode + Uint16 GPIO41:1; // 9 Defines direction for this pin in GPIO mode + Uint16 GPIO42:1; // 10 Defines direction for this pin in GPIO mode + Uint16 GPIO43:1; // 11 Defines direction for this pin in GPIO mode + Uint16 GPIO44:1; // 12 Defines direction for this pin in GPIO mode + Uint16 GPIO45:1; // 13 Defines direction for this pin in GPIO mode + Uint16 GPIO46:1; // 14 Defines direction for this pin in GPIO mode + Uint16 GPIO47:1; // 15 Defines direction for this pin in GPIO mode + Uint16 GPIO48:1; // 16 Defines direction for this pin in GPIO mode + Uint16 GPIO49:1; // 17 Defines direction for this pin in GPIO mode + Uint16 GPIO50:1; // 18 Defines direction for this pin in GPIO mode + Uint16 GPIO51:1; // 19 Defines direction for this pin in GPIO mode + Uint16 GPIO52:1; // 20 Defines direction for this pin in GPIO mode + Uint16 GPIO53:1; // 21 Defines direction for this pin in GPIO mode + Uint16 GPIO54:1; // 22 Defines direction for this pin in GPIO mode + Uint16 GPIO55:1; // 23 Defines direction for this pin in GPIO mode + Uint16 GPIO56:1; // 24 Defines direction for this pin in GPIO mode + Uint16 GPIO57:1; // 25 Defines direction for this pin in GPIO mode + Uint16 GPIO58:1; // 26 Defines direction for this pin in GPIO mode + Uint16 GPIO59:1; // 27 Defines direction for this pin in GPIO mode + Uint16 GPIO60:1; // 28 Defines direction for this pin in GPIO mode + Uint16 GPIO61:1; // 29 Defines direction for this pin in GPIO mode + Uint16 GPIO62:1; // 30 Defines direction for this pin in GPIO mode + Uint16 GPIO63:1; // 31 Defines direction for this pin in GPIO mode +}; + +union GPBDIR_REG { + Uint32 all; + struct GPBDIR_BITS bit; +}; + +struct GPBPUD_BITS { // bits description + Uint16 GPIO32:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO33:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO34:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO35:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO36:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO37:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO38:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO39:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO40:1; // 8 Pull-Up Disable control for this pin + Uint16 GPIO41:1; // 9 Pull-Up Disable control for this pin + Uint16 GPIO42:1; // 10 Pull-Up Disable control for this pin + Uint16 GPIO43:1; // 11 Pull-Up Disable control for this pin + Uint16 GPIO44:1; // 12 Pull-Up Disable control for this pin + Uint16 GPIO45:1; // 13 Pull-Up Disable control for this pin + Uint16 GPIO46:1; // 14 Pull-Up Disable control for this pin + Uint16 GPIO47:1; // 15 Pull-Up Disable control for this pin + Uint16 GPIO48:1; // 16 Pull-Up Disable control for this pin + Uint16 GPIO49:1; // 17 Pull-Up Disable control for this pin + Uint16 GPIO50:1; // 18 Pull-Up Disable control for this pin + Uint16 GPIO51:1; // 19 Pull-Up Disable control for this pin + Uint16 GPIO52:1; // 20 Pull-Up Disable control for this pin + Uint16 GPIO53:1; // 21 Pull-Up Disable control for this pin + Uint16 GPIO54:1; // 22 Pull-Up Disable control for this pin + Uint16 GPIO55:1; // 23 Pull-Up Disable control for this pin + Uint16 GPIO56:1; // 24 Pull-Up Disable control for this pin + Uint16 GPIO57:1; // 25 Pull-Up Disable control for this pin + Uint16 GPIO58:1; // 26 Pull-Up Disable control for this pin + Uint16 GPIO59:1; // 27 Pull-Up Disable control for this pin + Uint16 GPIO60:1; // 28 Pull-Up Disable control for this pin + Uint16 GPIO61:1; // 29 Pull-Up Disable control for this pin + Uint16 GPIO62:1; // 30 Pull-Up Disable control for this pin + Uint16 GPIO63:1; // 31 Pull-Up Disable control for this pin +}; + +union GPBPUD_REG { + Uint32 all; + struct GPBPUD_BITS bit; +}; + +struct GPBINV_BITS { // bits description + Uint16 GPIO32:1; // 0 Input inversion control for this pin + Uint16 GPIO33:1; // 1 Input inversion control for this pin + Uint16 GPIO34:1; // 2 Input inversion control for this pin + Uint16 GPIO35:1; // 3 Input inversion control for this pin + Uint16 GPIO36:1; // 4 Input inversion control for this pin + Uint16 GPIO37:1; // 5 Input inversion control for this pin + Uint16 GPIO38:1; // 6 Input inversion control for this pin + Uint16 GPIO39:1; // 7 Input inversion control for this pin + Uint16 GPIO40:1; // 8 Input inversion control for this pin + Uint16 GPIO41:1; // 9 Input inversion control for this pin + Uint16 GPIO42:1; // 10 Input inversion control for this pin + Uint16 GPIO43:1; // 11 Input inversion control for this pin + Uint16 GPIO44:1; // 12 Input inversion control for this pin + Uint16 GPIO45:1; // 13 Input inversion control for this pin + Uint16 GPIO46:1; // 14 Input inversion control for this pin + Uint16 GPIO47:1; // 15 Input inversion control for this pin + Uint16 GPIO48:1; // 16 Input inversion control for this pin + Uint16 GPIO49:1; // 17 Input inversion control for this pin + Uint16 GPIO50:1; // 18 Input inversion control for this pin + Uint16 GPIO51:1; // 19 Input inversion control for this pin + Uint16 GPIO52:1; // 20 Input inversion control for this pin + Uint16 GPIO53:1; // 21 Input inversion control for this pin + Uint16 GPIO54:1; // 22 Input inversion control for this pin + Uint16 GPIO55:1; // 23 Input inversion control for this pin + Uint16 GPIO56:1; // 24 Input inversion control for this pin + Uint16 GPIO57:1; // 25 Input inversion control for this pin + Uint16 GPIO58:1; // 26 Input inversion control for this pin + Uint16 GPIO59:1; // 27 Input inversion control for this pin + Uint16 GPIO60:1; // 28 Input inversion control for this pin + Uint16 GPIO61:1; // 29 Input inversion control for this pin + Uint16 GPIO62:1; // 30 Input inversion control for this pin + Uint16 GPIO63:1; // 31 Input inversion control for this pin +}; + +union GPBINV_REG { + Uint32 all; + struct GPBINV_BITS bit; +}; + +struct GPBODR_BITS { // bits description + Uint16 GPIO32:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO33:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO34:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO35:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO36:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO37:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO38:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO39:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO40:1; // 8 Outpout Open-Drain control for this pin + Uint16 GPIO41:1; // 9 Outpout Open-Drain control for this pin + Uint16 GPIO42:1; // 10 Outpout Open-Drain control for this pin + Uint16 GPIO43:1; // 11 Outpout Open-Drain control for this pin + Uint16 GPIO44:1; // 12 Outpout Open-Drain control for this pin + Uint16 GPIO45:1; // 13 Outpout Open-Drain control for this pin + Uint16 GPIO46:1; // 14 Outpout Open-Drain control for this pin + Uint16 GPIO47:1; // 15 Outpout Open-Drain control for this pin + Uint16 GPIO48:1; // 16 Outpout Open-Drain control for this pin + Uint16 GPIO49:1; // 17 Outpout Open-Drain control for this pin + Uint16 GPIO50:1; // 18 Outpout Open-Drain control for this pin + Uint16 GPIO51:1; // 19 Outpout Open-Drain control for this pin + Uint16 GPIO52:1; // 20 Outpout Open-Drain control for this pin + Uint16 GPIO53:1; // 21 Outpout Open-Drain control for this pin + Uint16 GPIO54:1; // 22 Outpout Open-Drain control for this pin + Uint16 GPIO55:1; // 23 Outpout Open-Drain control for this pin + Uint16 GPIO56:1; // 24 Outpout Open-Drain control for this pin + Uint16 GPIO57:1; // 25 Outpout Open-Drain control for this pin + Uint16 GPIO58:1; // 26 Outpout Open-Drain control for this pin + Uint16 GPIO59:1; // 27 Outpout Open-Drain control for this pin + Uint16 GPIO60:1; // 28 Outpout Open-Drain control for this pin + Uint16 GPIO61:1; // 29 Outpout Open-Drain control for this pin + Uint16 GPIO62:1; // 30 Outpout Open-Drain control for this pin + Uint16 GPIO63:1; // 31 Outpout Open-Drain control for this pin +}; + +union GPBODR_REG { + Uint32 all; + struct GPBODR_BITS bit; +}; + +struct GPBAMSEL_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 rsvd4:1; // 3 Reserved + Uint16 rsvd5:1; // 4 Reserved + Uint16 rsvd6:1; // 5 Reserved + Uint16 rsvd7:1; // 6 Reserved + Uint16 rsvd8:1; // 7 Reserved + Uint16 rsvd9:1; // 8 Reserved + Uint16 rsvd10:1; // 9 Reserved + Uint16 GPIO42:1; // 10 Analog Mode select for this pin + Uint16 GPIO43:1; // 11 Analog Mode select for this pin + Uint16 rsvd11:1; // 12 Reserved + Uint16 rsvd12:1; // 13 Reserved + Uint16 rsvd13:1; // 14 Reserved + Uint16 rsvd14:1; // 15 Reserved + Uint16 rsvd15:1; // 16 Reserved + Uint16 rsvd16:1; // 17 Reserved + Uint16 rsvd17:1; // 18 Reserved + Uint16 rsvd18:1; // 19 Reserved + Uint16 rsvd19:1; // 20 Reserved + Uint16 rsvd20:1; // 21 Reserved + Uint16 rsvd21:1; // 22 Reserved + Uint16 rsvd22:1; // 23 Reserved + Uint16 rsvd23:1; // 24 Reserved + Uint16 rsvd24:1; // 25 Reserved + Uint16 rsvd25:1; // 26 Reserved + Uint16 rsvd26:1; // 27 Reserved + Uint16 rsvd27:1; // 28 Reserved + Uint16 rsvd28:1; // 29 Reserved + Uint16 rsvd29:1; // 30 Reserved + Uint16 rsvd30:1; // 31 Reserved +}; + +union GPBAMSEL_REG { + Uint32 all; + struct GPBAMSEL_BITS bit; +}; + +struct GPBGMUX1_BITS { // bits description + Uint16 GPIO32:2; // 1:0 Defines pin-muxing selection for GPIO32 + Uint16 GPIO33:2; // 3:2 Defines pin-muxing selection for GPIO33 + Uint16 GPIO34:2; // 5:4 Defines pin-muxing selection for GPIO34 + Uint16 GPIO35:2; // 7:6 Defines pin-muxing selection for GPIO35 + Uint16 GPIO36:2; // 9:8 Defines pin-muxing selection for GPIO36 + Uint16 GPIO37:2; // 11:10 Defines pin-muxing selection for GPIO37 + Uint16 GPIO38:2; // 13:12 Defines pin-muxing selection for GPIO38 + Uint16 GPIO39:2; // 15:14 Defines pin-muxing selection for GPIO39 + Uint16 GPIO40:2; // 17:16 Defines pin-muxing selection for GPIO40 + Uint16 GPIO41:2; // 19:18 Defines pin-muxing selection for GPIO41 + Uint16 GPIO42:2; // 21:20 Defines pin-muxing selection for GPIO42 + Uint16 GPIO43:2; // 23:22 Defines pin-muxing selection for GPIO43 + Uint16 GPIO44:2; // 25:24 Defines pin-muxing selection for GPIO44 + Uint16 GPIO45:2; // 27:26 Defines pin-muxing selection for GPIO45 + Uint16 GPIO46:2; // 29:28 Defines pin-muxing selection for GPIO46 + Uint16 GPIO47:2; // 31:30 Defines pin-muxing selection for GPIO47 +}; + +union GPBGMUX1_REG { + Uint32 all; + struct GPBGMUX1_BITS bit; +}; + +struct GPBGMUX2_BITS { // bits description + Uint16 GPIO48:2; // 1:0 Defines pin-muxing selection for GPIO48 + Uint16 GPIO49:2; // 3:2 Defines pin-muxing selection for GPIO49 + Uint16 GPIO50:2; // 5:4 Defines pin-muxing selection for GPIO50 + Uint16 GPIO51:2; // 7:6 Defines pin-muxing selection for GPIO51 + Uint16 GPIO52:2; // 9:8 Defines pin-muxing selection for GPIO52 + Uint16 GPIO53:2; // 11:10 Defines pin-muxing selection for GPIO53 + Uint16 GPIO54:2; // 13:12 Defines pin-muxing selection for GPIO54 + Uint16 GPIO55:2; // 15:14 Defines pin-muxing selection for GPIO55 + Uint16 GPIO56:2; // 17:16 Defines pin-muxing selection for GPIO56 + Uint16 GPIO57:2; // 19:18 Defines pin-muxing selection for GPIO57 + Uint16 GPIO58:2; // 21:20 Defines pin-muxing selection for GPIO58 + Uint16 GPIO59:2; // 23:22 Defines pin-muxing selection for GPIO59 + Uint16 GPIO60:2; // 25:24 Defines pin-muxing selection for GPIO60 + Uint16 GPIO61:2; // 27:26 Defines pin-muxing selection for GPIO61 + Uint16 GPIO62:2; // 29:28 Defines pin-muxing selection for GPIO62 + Uint16 GPIO63:2; // 31:30 Defines pin-muxing selection for GPIO63 +}; + +union GPBGMUX2_REG { + Uint32 all; + struct GPBGMUX2_BITS bit; +}; + +struct GPBCSEL1_BITS { // bits description + Uint16 GPIO32:4; // 3:0 GPIO32 Master CPU Select + Uint16 GPIO33:4; // 7:4 GPIO33 Master CPU Select + Uint16 GPIO34:4; // 11:8 GPIO34 Master CPU Select + Uint16 GPIO35:4; // 15:12 GPIO35 Master CPU Select + Uint16 GPIO36:4; // 19:16 GPIO36 Master CPU Select + Uint16 GPIO37:4; // 23:20 GPIO37 Master CPU Select + Uint16 GPIO38:4; // 27:24 GPIO38 Master CPU Select + Uint16 GPIO39:4; // 31:28 GPIO39 Master CPU Select +}; + +union GPBCSEL1_REG { + Uint32 all; + struct GPBCSEL1_BITS bit; +}; + +struct GPBCSEL2_BITS { // bits description + Uint16 GPIO40:4; // 3:0 GPIO40 Master CPU Select + Uint16 GPIO41:4; // 7:4 GPIO41 Master CPU Select + Uint16 GPIO42:4; // 11:8 GPIO42 Master CPU Select + Uint16 GPIO43:4; // 15:12 GPIO43 Master CPU Select + Uint16 GPIO44:4; // 19:16 GPIO44 Master CPU Select + Uint16 GPIO45:4; // 23:20 GPIO45 Master CPU Select + Uint16 GPIO46:4; // 27:24 GPIO46 Master CPU Select + Uint16 GPIO47:4; // 31:28 GPIO47 Master CPU Select +}; + +union GPBCSEL2_REG { + Uint32 all; + struct GPBCSEL2_BITS bit; +}; + +struct GPBCSEL3_BITS { // bits description + Uint16 GPIO48:4; // 3:0 GPIO48 Master CPU Select + Uint16 GPIO49:4; // 7:4 GPIO49 Master CPU Select + Uint16 GPIO50:4; // 11:8 GPIO50 Master CPU Select + Uint16 GPIO51:4; // 15:12 GPIO51 Master CPU Select + Uint16 GPIO52:4; // 19:16 GPIO52 Master CPU Select + Uint16 GPIO53:4; // 23:20 GPIO53 Master CPU Select + Uint16 GPIO54:4; // 27:24 GPIO54 Master CPU Select + Uint16 GPIO55:4; // 31:28 GPIO55 Master CPU Select +}; + +union GPBCSEL3_REG { + Uint32 all; + struct GPBCSEL3_BITS bit; +}; + +struct GPBCSEL4_BITS { // bits description + Uint16 GPIO56:4; // 3:0 GPIO56 Master CPU Select + Uint16 GPIO57:4; // 7:4 GPIO57 Master CPU Select + Uint16 GPIO58:4; // 11:8 GPIO58 Master CPU Select + Uint16 GPIO59:4; // 15:12 GPIO59 Master CPU Select + Uint16 GPIO60:4; // 19:16 GPIO60 Master CPU Select + Uint16 GPIO61:4; // 23:20 GPIO61 Master CPU Select + Uint16 GPIO62:4; // 27:24 GPIO62 Master CPU Select + Uint16 GPIO63:4; // 31:28 GPIO63 Master CPU Select +}; + +union GPBCSEL4_REG { + Uint32 all; + struct GPBCSEL4_BITS bit; +}; + +struct GPBLOCK_BITS { // bits description + Uint16 GPIO32:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO33:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO34:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO35:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO36:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO37:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO38:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO39:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO40:1; // 8 Configuration Lock bit for this pin + Uint16 GPIO41:1; // 9 Configuration Lock bit for this pin + Uint16 GPIO42:1; // 10 Configuration Lock bit for this pin + Uint16 GPIO43:1; // 11 Configuration Lock bit for this pin + Uint16 GPIO44:1; // 12 Configuration Lock bit for this pin + Uint16 GPIO45:1; // 13 Configuration Lock bit for this pin + Uint16 GPIO46:1; // 14 Configuration Lock bit for this pin + Uint16 GPIO47:1; // 15 Configuration Lock bit for this pin + Uint16 GPIO48:1; // 16 Configuration Lock bit for this pin + Uint16 GPIO49:1; // 17 Configuration Lock bit for this pin + Uint16 GPIO50:1; // 18 Configuration Lock bit for this pin + Uint16 GPIO51:1; // 19 Configuration Lock bit for this pin + Uint16 GPIO52:1; // 20 Configuration Lock bit for this pin + Uint16 GPIO53:1; // 21 Configuration Lock bit for this pin + Uint16 GPIO54:1; // 22 Configuration Lock bit for this pin + Uint16 GPIO55:1; // 23 Configuration Lock bit for this pin + Uint16 GPIO56:1; // 24 Configuration Lock bit for this pin + Uint16 GPIO57:1; // 25 Configuration Lock bit for this pin + Uint16 GPIO58:1; // 26 Configuration Lock bit for this pin + Uint16 GPIO59:1; // 27 Configuration Lock bit for this pin + Uint16 GPIO60:1; // 28 Configuration Lock bit for this pin + Uint16 GPIO61:1; // 29 Configuration Lock bit for this pin + Uint16 GPIO62:1; // 30 Configuration Lock bit for this pin + Uint16 GPIO63:1; // 31 Configuration Lock bit for this pin +}; + +union GPBLOCK_REG { + Uint32 all; + struct GPBLOCK_BITS bit; +}; + +struct GPBCR_BITS { // bits description + Uint16 GPIO32:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO33:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO34:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO35:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO36:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO37:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO38:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO39:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO40:1; // 8 Configuration lock commit bit for this pin + Uint16 GPIO41:1; // 9 Configuration lock commit bit for this pin + Uint16 GPIO42:1; // 10 Configuration lock commit bit for this pin + Uint16 GPIO43:1; // 11 Configuration lock commit bit for this pin + Uint16 GPIO44:1; // 12 Configuration lock commit bit for this pin + Uint16 GPIO45:1; // 13 Configuration lock commit bit for this pin + Uint16 GPIO46:1; // 14 Configuration lock commit bit for this pin + Uint16 GPIO47:1; // 15 Configuration lock commit bit for this pin + Uint16 GPIO48:1; // 16 Configuration lock commit bit for this pin + Uint16 GPIO49:1; // 17 Configuration lock commit bit for this pin + Uint16 GPIO50:1; // 18 Configuration lock commit bit for this pin + Uint16 GPIO51:1; // 19 Configuration lock commit bit for this pin + Uint16 GPIO52:1; // 20 Configuration lock commit bit for this pin + Uint16 GPIO53:1; // 21 Configuration lock commit bit for this pin + Uint16 GPIO54:1; // 22 Configuration lock commit bit for this pin + Uint16 GPIO55:1; // 23 Configuration lock commit bit for this pin + Uint16 GPIO56:1; // 24 Configuration lock commit bit for this pin + Uint16 GPIO57:1; // 25 Configuration lock commit bit for this pin + Uint16 GPIO58:1; // 26 Configuration lock commit bit for this pin + Uint16 GPIO59:1; // 27 Configuration lock commit bit for this pin + Uint16 GPIO60:1; // 28 Configuration lock commit bit for this pin + Uint16 GPIO61:1; // 29 Configuration lock commit bit for this pin + Uint16 GPIO62:1; // 30 Configuration lock commit bit for this pin + Uint16 GPIO63:1; // 31 Configuration lock commit bit for this pin +}; + +union GPBCR_REG { + Uint32 all; + struct GPBCR_BITS bit; +}; + +struct GPCCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO64 to GPIO71 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO72 to GPIO79 + Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO80 to GPIO87 + Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO88 to GPIO95 +}; + +union GPCCTRL_REG { + Uint32 all; + struct GPCCTRL_BITS bit; +}; + +struct GPCQSEL1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 Select input qualification type for GPIO64 + Uint16 GPIO65:2; // 3:2 Select input qualification type for GPIO65 + Uint16 GPIO66:2; // 5:4 Select input qualification type for GPIO66 + Uint16 GPIO67:2; // 7:6 Select input qualification type for GPIO67 + Uint16 GPIO68:2; // 9:8 Select input qualification type for GPIO68 + Uint16 GPIO69:2; // 11:10 Select input qualification type for GPIO69 + Uint16 GPIO70:2; // 13:12 Select input qualification type for GPIO70 + Uint16 GPIO71:2; // 15:14 Select input qualification type for GPIO71 + Uint16 GPIO72:2; // 17:16 Select input qualification type for GPIO72 + Uint16 GPIO73:2; // 19:18 Select input qualification type for GPIO73 + Uint16 GPIO74:2; // 21:20 Select input qualification type for GPIO74 + Uint16 GPIO75:2; // 23:22 Select input qualification type for GPIO75 + Uint16 GPIO76:2; // 25:24 Select input qualification type for GPIO76 + Uint16 GPIO77:2; // 27:26 Select input qualification type for GPIO77 + Uint16 GPIO78:2; // 29:28 Select input qualification type for GPIO78 + Uint16 GPIO79:2; // 31:30 Select input qualification type for GPIO79 +}; + +union GPCQSEL1_REG { + Uint32 all; + struct GPCQSEL1_BITS bit; +}; + +struct GPCQSEL2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 Select input qualification type for GPIO80 + Uint16 GPIO81:2; // 3:2 Select input qualification type for GPIO81 + Uint16 GPIO82:2; // 5:4 Select input qualification type for GPIO82 + Uint16 GPIO83:2; // 7:6 Select input qualification type for GPIO83 + Uint16 GPIO84:2; // 9:8 Select input qualification type for GPIO84 + Uint16 GPIO85:2; // 11:10 Select input qualification type for GPIO85 + Uint16 GPIO86:2; // 13:12 Select input qualification type for GPIO86 + Uint16 GPIO87:2; // 15:14 Select input qualification type for GPIO87 + Uint16 GPIO88:2; // 17:16 Select input qualification type for GPIO88 + Uint16 GPIO89:2; // 19:18 Select input qualification type for GPIO89 + Uint16 GPIO90:2; // 21:20 Select input qualification type for GPIO90 + Uint16 GPIO91:2; // 23:22 Select input qualification type for GPIO91 + Uint16 GPIO92:2; // 25:24 Select input qualification type for GPIO92 + Uint16 GPIO93:2; // 27:26 Select input qualification type for GPIO93 + Uint16 GPIO94:2; // 29:28 Select input qualification type for GPIO94 + Uint16 GPIO95:2; // 31:30 Select input qualification type for GPIO95 +}; + +union GPCQSEL2_REG { + Uint32 all; + struct GPCQSEL2_BITS bit; +}; + +struct GPCMUX1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 Defines pin-muxing selection for GPIO64 + Uint16 GPIO65:2; // 3:2 Defines pin-muxing selection for GPIO65 + Uint16 GPIO66:2; // 5:4 Defines pin-muxing selection for GPIO66 + Uint16 GPIO67:2; // 7:6 Defines pin-muxing selection for GPIO67 + Uint16 GPIO68:2; // 9:8 Defines pin-muxing selection for GPIO68 + Uint16 GPIO69:2; // 11:10 Defines pin-muxing selection for GPIO69 + Uint16 GPIO70:2; // 13:12 Defines pin-muxing selection for GPIO70 + Uint16 GPIO71:2; // 15:14 Defines pin-muxing selection for GPIO71 + Uint16 GPIO72:2; // 17:16 Defines pin-muxing selection for GPIO72 + Uint16 GPIO73:2; // 19:18 Defines pin-muxing selection for GPIO73 + Uint16 GPIO74:2; // 21:20 Defines pin-muxing selection for GPIO74 + Uint16 GPIO75:2; // 23:22 Defines pin-muxing selection for GPIO75 + Uint16 GPIO76:2; // 25:24 Defines pin-muxing selection for GPIO76 + Uint16 GPIO77:2; // 27:26 Defines pin-muxing selection for GPIO77 + Uint16 GPIO78:2; // 29:28 Defines pin-muxing selection for GPIO78 + Uint16 GPIO79:2; // 31:30 Defines pin-muxing selection for GPIO79 +}; + +union GPCMUX1_REG { + Uint32 all; + struct GPCMUX1_BITS bit; +}; + +struct GPCMUX2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 Defines pin-muxing selection for GPIO80 + Uint16 GPIO81:2; // 3:2 Defines pin-muxing selection for GPIO81 + Uint16 GPIO82:2; // 5:4 Defines pin-muxing selection for GPIO82 + Uint16 GPIO83:2; // 7:6 Defines pin-muxing selection for GPIO83 + Uint16 GPIO84:2; // 9:8 Defines pin-muxing selection for GPIO84 + Uint16 GPIO85:2; // 11:10 Defines pin-muxing selection for GPIO85 + Uint16 GPIO86:2; // 13:12 Defines pin-muxing selection for GPIO86 + Uint16 GPIO87:2; // 15:14 Defines pin-muxing selection for GPIO87 + Uint16 GPIO88:2; // 17:16 Defines pin-muxing selection for GPIO88 + Uint16 GPIO89:2; // 19:18 Defines pin-muxing selection for GPIO89 + Uint16 GPIO90:2; // 21:20 Defines pin-muxing selection for GPIO90 + Uint16 GPIO91:2; // 23:22 Defines pin-muxing selection for GPIO91 + Uint16 GPIO92:2; // 25:24 Defines pin-muxing selection for GPIO92 + Uint16 GPIO93:2; // 27:26 Defines pin-muxing selection for GPIO93 + Uint16 GPIO94:2; // 29:28 Defines pin-muxing selection for GPIO94 + Uint16 GPIO95:2; // 31:30 Defines pin-muxing selection for GPIO95 +}; + +union GPCMUX2_REG { + Uint32 all; + struct GPCMUX2_BITS bit; +}; + +struct GPCDIR_BITS { // bits description + Uint16 GPIO64:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO65:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO66:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO67:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO68:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO69:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO70:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO71:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO72:1; // 8 Defines direction for this pin in GPIO mode + Uint16 GPIO73:1; // 9 Defines direction for this pin in GPIO mode + Uint16 GPIO74:1; // 10 Defines direction for this pin in GPIO mode + Uint16 GPIO75:1; // 11 Defines direction for this pin in GPIO mode + Uint16 GPIO76:1; // 12 Defines direction for this pin in GPIO mode + Uint16 GPIO77:1; // 13 Defines direction for this pin in GPIO mode + Uint16 GPIO78:1; // 14 Defines direction for this pin in GPIO mode + Uint16 GPIO79:1; // 15 Defines direction for this pin in GPIO mode + Uint16 GPIO80:1; // 16 Defines direction for this pin in GPIO mode + Uint16 GPIO81:1; // 17 Defines direction for this pin in GPIO mode + Uint16 GPIO82:1; // 18 Defines direction for this pin in GPIO mode + Uint16 GPIO83:1; // 19 Defines direction for this pin in GPIO mode + Uint16 GPIO84:1; // 20 Defines direction for this pin in GPIO mode + Uint16 GPIO85:1; // 21 Defines direction for this pin in GPIO mode + Uint16 GPIO86:1; // 22 Defines direction for this pin in GPIO mode + Uint16 GPIO87:1; // 23 Defines direction for this pin in GPIO mode + Uint16 GPIO88:1; // 24 Defines direction for this pin in GPIO mode + Uint16 GPIO89:1; // 25 Defines direction for this pin in GPIO mode + Uint16 GPIO90:1; // 26 Defines direction for this pin in GPIO mode + Uint16 GPIO91:1; // 27 Defines direction for this pin in GPIO mode + Uint16 GPIO92:1; // 28 Defines direction for this pin in GPIO mode + Uint16 GPIO93:1; // 29 Defines direction for this pin in GPIO mode + Uint16 GPIO94:1; // 30 Defines direction for this pin in GPIO mode + Uint16 GPIO95:1; // 31 Defines direction for this pin in GPIO mode +}; + +union GPCDIR_REG { + Uint32 all; + struct GPCDIR_BITS bit; +}; + +struct GPCPUD_BITS { // bits description + Uint16 GPIO64:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO65:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO66:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO67:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO68:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO69:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO70:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO71:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO72:1; // 8 Pull-Up Disable control for this pin + Uint16 GPIO73:1; // 9 Pull-Up Disable control for this pin + Uint16 GPIO74:1; // 10 Pull-Up Disable control for this pin + Uint16 GPIO75:1; // 11 Pull-Up Disable control for this pin + Uint16 GPIO76:1; // 12 Pull-Up Disable control for this pin + Uint16 GPIO77:1; // 13 Pull-Up Disable control for this pin + Uint16 GPIO78:1; // 14 Pull-Up Disable control for this pin + Uint16 GPIO79:1; // 15 Pull-Up Disable control for this pin + Uint16 GPIO80:1; // 16 Pull-Up Disable control for this pin + Uint16 GPIO81:1; // 17 Pull-Up Disable control for this pin + Uint16 GPIO82:1; // 18 Pull-Up Disable control for this pin + Uint16 GPIO83:1; // 19 Pull-Up Disable control for this pin + Uint16 GPIO84:1; // 20 Pull-Up Disable control for this pin + Uint16 GPIO85:1; // 21 Pull-Up Disable control for this pin + Uint16 GPIO86:1; // 22 Pull-Up Disable control for this pin + Uint16 GPIO87:1; // 23 Pull-Up Disable control for this pin + Uint16 GPIO88:1; // 24 Pull-Up Disable control for this pin + Uint16 GPIO89:1; // 25 Pull-Up Disable control for this pin + Uint16 GPIO90:1; // 26 Pull-Up Disable control for this pin + Uint16 GPIO91:1; // 27 Pull-Up Disable control for this pin + Uint16 GPIO92:1; // 28 Pull-Up Disable control for this pin + Uint16 GPIO93:1; // 29 Pull-Up Disable control for this pin + Uint16 GPIO94:1; // 30 Pull-Up Disable control for this pin + Uint16 GPIO95:1; // 31 Pull-Up Disable control for this pin +}; + +union GPCPUD_REG { + Uint32 all; + struct GPCPUD_BITS bit; +}; + +struct GPCINV_BITS { // bits description + Uint16 GPIO64:1; // 0 Input inversion control for this pin + Uint16 GPIO65:1; // 1 Input inversion control for this pin + Uint16 GPIO66:1; // 2 Input inversion control for this pin + Uint16 GPIO67:1; // 3 Input inversion control for this pin + Uint16 GPIO68:1; // 4 Input inversion control for this pin + Uint16 GPIO69:1; // 5 Input inversion control for this pin + Uint16 GPIO70:1; // 6 Input inversion control for this pin + Uint16 GPIO71:1; // 7 Input inversion control for this pin + Uint16 GPIO72:1; // 8 Input inversion control for this pin + Uint16 GPIO73:1; // 9 Input inversion control for this pin + Uint16 GPIO74:1; // 10 Input inversion control for this pin + Uint16 GPIO75:1; // 11 Input inversion control for this pin + Uint16 GPIO76:1; // 12 Input inversion control for this pin + Uint16 GPIO77:1; // 13 Input inversion control for this pin + Uint16 GPIO78:1; // 14 Input inversion control for this pin + Uint16 GPIO79:1; // 15 Input inversion control for this pin + Uint16 GPIO80:1; // 16 Input inversion control for this pin + Uint16 GPIO81:1; // 17 Input inversion control for this pin + Uint16 GPIO82:1; // 18 Input inversion control for this pin + Uint16 GPIO83:1; // 19 Input inversion control for this pin + Uint16 GPIO84:1; // 20 Input inversion control for this pin + Uint16 GPIO85:1; // 21 Input inversion control for this pin + Uint16 GPIO86:1; // 22 Input inversion control for this pin + Uint16 GPIO87:1; // 23 Input inversion control for this pin + Uint16 GPIO88:1; // 24 Input inversion control for this pin + Uint16 GPIO89:1; // 25 Input inversion control for this pin + Uint16 GPIO90:1; // 26 Input inversion control for this pin + Uint16 GPIO91:1; // 27 Input inversion control for this pin + Uint16 GPIO92:1; // 28 Input inversion control for this pin + Uint16 GPIO93:1; // 29 Input inversion control for this pin + Uint16 GPIO94:1; // 30 Input inversion control for this pin + Uint16 GPIO95:1; // 31 Input inversion control for this pin +}; + +union GPCINV_REG { + Uint32 all; + struct GPCINV_BITS bit; +}; + +struct GPCODR_BITS { // bits description + Uint16 GPIO64:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO65:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO66:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO67:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO68:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO69:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO70:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO71:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO72:1; // 8 Outpout Open-Drain control for this pin + Uint16 GPIO73:1; // 9 Outpout Open-Drain control for this pin + Uint16 GPIO74:1; // 10 Outpout Open-Drain control for this pin + Uint16 GPIO75:1; // 11 Outpout Open-Drain control for this pin + Uint16 GPIO76:1; // 12 Outpout Open-Drain control for this pin + Uint16 GPIO77:1; // 13 Outpout Open-Drain control for this pin + Uint16 GPIO78:1; // 14 Outpout Open-Drain control for this pin + Uint16 GPIO79:1; // 15 Outpout Open-Drain control for this pin + Uint16 GPIO80:1; // 16 Outpout Open-Drain control for this pin + Uint16 GPIO81:1; // 17 Outpout Open-Drain control for this pin + Uint16 GPIO82:1; // 18 Outpout Open-Drain control for this pin + Uint16 GPIO83:1; // 19 Outpout Open-Drain control for this pin + Uint16 GPIO84:1; // 20 Outpout Open-Drain control for this pin + Uint16 GPIO85:1; // 21 Outpout Open-Drain control for this pin + Uint16 GPIO86:1; // 22 Outpout Open-Drain control for this pin + Uint16 GPIO87:1; // 23 Outpout Open-Drain control for this pin + Uint16 GPIO88:1; // 24 Outpout Open-Drain control for this pin + Uint16 GPIO89:1; // 25 Outpout Open-Drain control for this pin + Uint16 GPIO90:1; // 26 Outpout Open-Drain control for this pin + Uint16 GPIO91:1; // 27 Outpout Open-Drain control for this pin + Uint16 GPIO92:1; // 28 Outpout Open-Drain control for this pin + Uint16 GPIO93:1; // 29 Outpout Open-Drain control for this pin + Uint16 GPIO94:1; // 30 Outpout Open-Drain control for this pin + Uint16 GPIO95:1; // 31 Outpout Open-Drain control for this pin +}; + +union GPCODR_REG { + Uint32 all; + struct GPCODR_BITS bit; +}; + +struct GPCGMUX1_BITS { // bits description + Uint16 GPIO64:2; // 1:0 Defines pin-muxing selection for GPIO64 + Uint16 GPIO65:2; // 3:2 Defines pin-muxing selection for GPIO65 + Uint16 GPIO66:2; // 5:4 Defines pin-muxing selection for GPIO66 + Uint16 GPIO67:2; // 7:6 Defines pin-muxing selection for GPIO67 + Uint16 GPIO68:2; // 9:8 Defines pin-muxing selection for GPIO68 + Uint16 GPIO69:2; // 11:10 Defines pin-muxing selection for GPIO69 + Uint16 GPIO70:2; // 13:12 Defines pin-muxing selection for GPIO70 + Uint16 GPIO71:2; // 15:14 Defines pin-muxing selection for GPIO71 + Uint16 GPIO72:2; // 17:16 Defines pin-muxing selection for GPIO72 + Uint16 GPIO73:2; // 19:18 Defines pin-muxing selection for GPIO73 + Uint16 GPIO74:2; // 21:20 Defines pin-muxing selection for GPIO74 + Uint16 GPIO75:2; // 23:22 Defines pin-muxing selection for GPIO75 + Uint16 GPIO76:2; // 25:24 Defines pin-muxing selection for GPIO76 + Uint16 GPIO77:2; // 27:26 Defines pin-muxing selection for GPIO77 + Uint16 GPIO78:2; // 29:28 Defines pin-muxing selection for GPIO78 + Uint16 GPIO79:2; // 31:30 Defines pin-muxing selection for GPIO79 +}; + +union GPCGMUX1_REG { + Uint32 all; + struct GPCGMUX1_BITS bit; +}; + +struct GPCGMUX2_BITS { // bits description + Uint16 GPIO80:2; // 1:0 Defines pin-muxing selection for GPIO80 + Uint16 GPIO81:2; // 3:2 Defines pin-muxing selection for GPIO81 + Uint16 GPIO82:2; // 5:4 Defines pin-muxing selection for GPIO82 + Uint16 GPIO83:2; // 7:6 Defines pin-muxing selection for GPIO83 + Uint16 GPIO84:2; // 9:8 Defines pin-muxing selection for GPIO84 + Uint16 GPIO85:2; // 11:10 Defines pin-muxing selection for GPIO85 + Uint16 GPIO86:2; // 13:12 Defines pin-muxing selection for GPIO86 + Uint16 GPIO87:2; // 15:14 Defines pin-muxing selection for GPIO87 + Uint16 GPIO88:2; // 17:16 Defines pin-muxing selection for GPIO88 + Uint16 GPIO89:2; // 19:18 Defines pin-muxing selection for GPIO89 + Uint16 GPIO90:2; // 21:20 Defines pin-muxing selection for GPIO90 + Uint16 GPIO91:2; // 23:22 Defines pin-muxing selection for GPIO91 + Uint16 GPIO92:2; // 25:24 Defines pin-muxing selection for GPIO92 + Uint16 GPIO93:2; // 27:26 Defines pin-muxing selection for GPIO93 + Uint16 GPIO94:2; // 29:28 Defines pin-muxing selection for GPIO94 + Uint16 GPIO95:2; // 31:30 Defines pin-muxing selection for GPIO95 +}; + +union GPCGMUX2_REG { + Uint32 all; + struct GPCGMUX2_BITS bit; +}; + +struct GPCCSEL1_BITS { // bits description + Uint16 GPIO64:4; // 3:0 GPIO64 Master CPU Select + Uint16 GPIO65:4; // 7:4 GPIO65 Master CPU Select + Uint16 GPIO66:4; // 11:8 GPIO66 Master CPU Select + Uint16 GPIO67:4; // 15:12 GPIO67 Master CPU Select + Uint16 GPIO68:4; // 19:16 GPIO68 Master CPU Select + Uint16 GPIO69:4; // 23:20 GPIO69 Master CPU Select + Uint16 GPIO70:4; // 27:24 GPIO70 Master CPU Select + Uint16 GPIO71:4; // 31:28 GPIO71 Master CPU Select +}; + +union GPCCSEL1_REG { + Uint32 all; + struct GPCCSEL1_BITS bit; +}; + +struct GPCCSEL2_BITS { // bits description + Uint16 GPIO72:4; // 3:0 GPIO72 Master CPU Select + Uint16 GPIO73:4; // 7:4 GPIO73 Master CPU Select + Uint16 GPIO74:4; // 11:8 GPIO74 Master CPU Select + Uint16 GPIO75:4; // 15:12 GPIO75 Master CPU Select + Uint16 GPIO76:4; // 19:16 GPIO76 Master CPU Select + Uint16 GPIO77:4; // 23:20 GPIO77 Master CPU Select + Uint16 GPIO78:4; // 27:24 GPIO78 Master CPU Select + Uint16 GPIO79:4; // 31:28 GPIO79 Master CPU Select +}; + +union GPCCSEL2_REG { + Uint32 all; + struct GPCCSEL2_BITS bit; +}; + +struct GPCCSEL3_BITS { // bits description + Uint16 GPIO80:4; // 3:0 GPIO80 Master CPU Select + Uint16 GPIO81:4; // 7:4 GPIO81 Master CPU Select + Uint16 GPIO82:4; // 11:8 GPIO82 Master CPU Select + Uint16 GPIO83:4; // 15:12 GPIO83 Master CPU Select + Uint16 GPIO84:4; // 19:16 GPIO84 Master CPU Select + Uint16 GPIO85:4; // 23:20 GPIO85 Master CPU Select + Uint16 GPIO86:4; // 27:24 GPIO86 Master CPU Select + Uint16 GPIO87:4; // 31:28 GPIO87 Master CPU Select +}; + +union GPCCSEL3_REG { + Uint32 all; + struct GPCCSEL3_BITS bit; +}; + +struct GPCCSEL4_BITS { // bits description + Uint16 GPIO88:4; // 3:0 GPIO88 Master CPU Select + Uint16 GPIO89:4; // 7:4 GPIO89 Master CPU Select + Uint16 GPIO90:4; // 11:8 GPIO90 Master CPU Select + Uint16 GPIO91:4; // 15:12 GPIO91 Master CPU Select + Uint16 GPIO92:4; // 19:16 GPIO92 Master CPU Select + Uint16 GPIO93:4; // 23:20 GPIO93 Master CPU Select + Uint16 GPIO94:4; // 27:24 GPIO94 Master CPU Select + Uint16 GPIO95:4; // 31:28 GPIO95 Master CPU Select +}; + +union GPCCSEL4_REG { + Uint32 all; + struct GPCCSEL4_BITS bit; +}; + +struct GPCLOCK_BITS { // bits description + Uint16 GPIO64:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO65:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO66:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO67:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO68:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO69:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO70:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO71:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO72:1; // 8 Configuration Lock bit for this pin + Uint16 GPIO73:1; // 9 Configuration Lock bit for this pin + Uint16 GPIO74:1; // 10 Configuration Lock bit for this pin + Uint16 GPIO75:1; // 11 Configuration Lock bit for this pin + Uint16 GPIO76:1; // 12 Configuration Lock bit for this pin + Uint16 GPIO77:1; // 13 Configuration Lock bit for this pin + Uint16 GPIO78:1; // 14 Configuration Lock bit for this pin + Uint16 GPIO79:1; // 15 Configuration Lock bit for this pin + Uint16 GPIO80:1; // 16 Configuration Lock bit for this pin + Uint16 GPIO81:1; // 17 Configuration Lock bit for this pin + Uint16 GPIO82:1; // 18 Configuration Lock bit for this pin + Uint16 GPIO83:1; // 19 Configuration Lock bit for this pin + Uint16 GPIO84:1; // 20 Configuration Lock bit for this pin + Uint16 GPIO85:1; // 21 Configuration Lock bit for this pin + Uint16 GPIO86:1; // 22 Configuration Lock bit for this pin + Uint16 GPIO87:1; // 23 Configuration Lock bit for this pin + Uint16 GPIO88:1; // 24 Configuration Lock bit for this pin + Uint16 GPIO89:1; // 25 Configuration Lock bit for this pin + Uint16 GPIO90:1; // 26 Configuration Lock bit for this pin + Uint16 GPIO91:1; // 27 Configuration Lock bit for this pin + Uint16 GPIO92:1; // 28 Configuration Lock bit for this pin + Uint16 GPIO93:1; // 29 Configuration Lock bit for this pin + Uint16 GPIO94:1; // 30 Configuration Lock bit for this pin + Uint16 GPIO95:1; // 31 Configuration Lock bit for this pin +}; + +union GPCLOCK_REG { + Uint32 all; + struct GPCLOCK_BITS bit; +}; + +struct GPCCR_BITS { // bits description + Uint16 GPIO64:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO65:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO66:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO67:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO68:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO69:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO70:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO71:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO72:1; // 8 Configuration lock commit bit for this pin + Uint16 GPIO73:1; // 9 Configuration lock commit bit for this pin + Uint16 GPIO74:1; // 10 Configuration lock commit bit for this pin + Uint16 GPIO75:1; // 11 Configuration lock commit bit for this pin + Uint16 GPIO76:1; // 12 Configuration lock commit bit for this pin + Uint16 GPIO77:1; // 13 Configuration lock commit bit for this pin + Uint16 GPIO78:1; // 14 Configuration lock commit bit for this pin + Uint16 GPIO79:1; // 15 Configuration lock commit bit for this pin + Uint16 GPIO80:1; // 16 Configuration lock commit bit for this pin + Uint16 GPIO81:1; // 17 Configuration lock commit bit for this pin + Uint16 GPIO82:1; // 18 Configuration lock commit bit for this pin + Uint16 GPIO83:1; // 19 Configuration lock commit bit for this pin + Uint16 GPIO84:1; // 20 Configuration lock commit bit for this pin + Uint16 GPIO85:1; // 21 Configuration lock commit bit for this pin + Uint16 GPIO86:1; // 22 Configuration lock commit bit for this pin + Uint16 GPIO87:1; // 23 Configuration lock commit bit for this pin + Uint16 GPIO88:1; // 24 Configuration lock commit bit for this pin + Uint16 GPIO89:1; // 25 Configuration lock commit bit for this pin + Uint16 GPIO90:1; // 26 Configuration lock commit bit for this pin + Uint16 GPIO91:1; // 27 Configuration lock commit bit for this pin + Uint16 GPIO92:1; // 28 Configuration lock commit bit for this pin + Uint16 GPIO93:1; // 29 Configuration lock commit bit for this pin + Uint16 GPIO94:1; // 30 Configuration lock commit bit for this pin + Uint16 GPIO95:1; // 31 Configuration lock commit bit for this pin +}; + +union GPCCR_REG { + Uint32 all; + struct GPCCR_BITS bit; +}; + +struct GPDCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO96 to GPIO103 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO104 to GPIO111 + Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO112 to GPIO119 + Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO120 to GPIO127 +}; + +union GPDCTRL_REG { + Uint32 all; + struct GPDCTRL_BITS bit; +}; + +struct GPDQSEL1_BITS { // bits description + Uint16 GPIO96:2; // 1:0 Select input qualification type for GPIO96 + Uint16 GPIO97:2; // 3:2 Select input qualification type for GPIO97 + Uint16 GPIO98:2; // 5:4 Select input qualification type for GPIO98 + Uint16 GPIO99:2; // 7:6 Select input qualification type for GPIO99 + Uint16 GPIO100:2; // 9:8 Select input qualification type for GPIO100 + Uint16 GPIO101:2; // 11:10 Select input qualification type for GPIO101 + Uint16 GPIO102:2; // 13:12 Select input qualification type for GPIO102 + Uint16 GPIO103:2; // 15:14 Select input qualification type for GPIO103 + Uint16 GPIO104:2; // 17:16 Select input qualification type for GPIO104 + Uint16 GPIO105:2; // 19:18 Select input qualification type for GPIO105 + Uint16 GPIO106:2; // 21:20 Select input qualification type for GPIO106 + Uint16 GPIO107:2; // 23:22 Select input qualification type for GPIO107 + Uint16 GPIO108:2; // 25:24 Select input qualification type for GPIO108 + Uint16 GPIO109:2; // 27:26 Select input qualification type for GPIO109 + Uint16 GPIO110:2; // 29:28 Select input qualification type for GPIO110 + Uint16 GPIO111:2; // 31:30 Select input qualification type for GPIO111 +}; + +union GPDQSEL1_REG { + Uint32 all; + struct GPDQSEL1_BITS bit; +}; + +struct GPDQSEL2_BITS { // bits description + Uint16 GPIO112:2; // 1:0 Select input qualification type for GPIO112 + Uint16 GPIO113:2; // 3:2 Select input qualification type for GPIO113 + Uint16 GPIO114:2; // 5:4 Select input qualification type for GPIO114 + Uint16 GPIO115:2; // 7:6 Select input qualification type for GPIO115 + Uint16 GPIO116:2; // 9:8 Select input qualification type for GPIO116 + Uint16 GPIO117:2; // 11:10 Select input qualification type for GPIO117 + Uint16 GPIO118:2; // 13:12 Select input qualification type for GPIO118 + Uint16 GPIO119:2; // 15:14 Select input qualification type for GPIO119 + Uint16 GPIO120:2; // 17:16 Select input qualification type for GPIO120 + Uint16 GPIO121:2; // 19:18 Select input qualification type for GPIO121 + Uint16 GPIO122:2; // 21:20 Select input qualification type for GPIO122 + Uint16 GPIO123:2; // 23:22 Select input qualification type for GPIO123 + Uint16 GPIO124:2; // 25:24 Select input qualification type for GPIO124 + Uint16 GPIO125:2; // 27:26 Select input qualification type for GPIO125 + Uint16 GPIO126:2; // 29:28 Select input qualification type for GPIO126 + Uint16 GPIO127:2; // 31:30 Select input qualification type for GPIO127 +}; + +union GPDQSEL2_REG { + Uint32 all; + struct GPDQSEL2_BITS bit; +}; + +struct GPDMUX1_BITS { // bits description + Uint16 GPIO96:2; // 1:0 Defines pin-muxing selection for GPIO96 + Uint16 GPIO97:2; // 3:2 Defines pin-muxing selection for GPIO97 + Uint16 GPIO98:2; // 5:4 Defines pin-muxing selection for GPIO98 + Uint16 GPIO99:2; // 7:6 Defines pin-muxing selection for GPIO99 + Uint16 GPIO100:2; // 9:8 Defines pin-muxing selection for GPIO100 + Uint16 GPIO101:2; // 11:10 Defines pin-muxing selection for GPIO101 + Uint16 GPIO102:2; // 13:12 Defines pin-muxing selection for GPIO102 + Uint16 GPIO103:2; // 15:14 Defines pin-muxing selection for GPIO103 + Uint16 GPIO104:2; // 17:16 Defines pin-muxing selection for GPIO104 + Uint16 GPIO105:2; // 19:18 Defines pin-muxing selection for GPIO105 + Uint16 GPIO106:2; // 21:20 Defines pin-muxing selection for GPIO106 + Uint16 GPIO107:2; // 23:22 Defines pin-muxing selection for GPIO107 + Uint16 GPIO108:2; // 25:24 Defines pin-muxing selection for GPIO108 + Uint16 GPIO109:2; // 27:26 Defines pin-muxing selection for GPIO109 + Uint16 GPIO110:2; // 29:28 Defines pin-muxing selection for GPIO110 + Uint16 GPIO111:2; // 31:30 Defines pin-muxing selection for GPIO111 +}; + +union GPDMUX1_REG { + Uint32 all; + struct GPDMUX1_BITS bit; +}; + +struct GPDMUX2_BITS { // bits description + Uint16 GPIO112:2; // 1:0 Defines pin-muxing selection for GPIO112 + Uint16 GPIO113:2; // 3:2 Defines pin-muxing selection for GPIO113 + Uint16 GPIO114:2; // 5:4 Defines pin-muxing selection for GPIO114 + Uint16 GPIO115:2; // 7:6 Defines pin-muxing selection for GPIO115 + Uint16 GPIO116:2; // 9:8 Defines pin-muxing selection for GPIO116 + Uint16 GPIO117:2; // 11:10 Defines pin-muxing selection for GPIO117 + Uint16 GPIO118:2; // 13:12 Defines pin-muxing selection for GPIO118 + Uint16 GPIO119:2; // 15:14 Defines pin-muxing selection for GPIO119 + Uint16 GPIO120:2; // 17:16 Defines pin-muxing selection for GPIO120 + Uint16 GPIO121:2; // 19:18 Defines pin-muxing selection for GPIO121 + Uint16 GPIO122:2; // 21:20 Defines pin-muxing selection for GPIO122 + Uint16 GPIO123:2; // 23:22 Defines pin-muxing selection for GPIO123 + Uint16 GPIO124:2; // 25:24 Defines pin-muxing selection for GPIO124 + Uint16 GPIO125:2; // 27:26 Defines pin-muxing selection for GPIO125 + Uint16 GPIO126:2; // 29:28 Defines pin-muxing selection for GPIO126 + Uint16 GPIO127:2; // 31:30 Defines pin-muxing selection for GPIO127 +}; + +union GPDMUX2_REG { + Uint32 all; + struct GPDMUX2_BITS bit; +}; + +struct GPDDIR_BITS { // bits description + Uint16 GPIO96:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO97:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO98:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO99:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO100:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO101:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO102:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO103:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO104:1; // 8 Defines direction for this pin in GPIO mode + Uint16 GPIO105:1; // 9 Defines direction for this pin in GPIO mode + Uint16 GPIO106:1; // 10 Defines direction for this pin in GPIO mode + Uint16 GPIO107:1; // 11 Defines direction for this pin in GPIO mode + Uint16 GPIO108:1; // 12 Defines direction for this pin in GPIO mode + Uint16 GPIO109:1; // 13 Defines direction for this pin in GPIO mode + Uint16 GPIO110:1; // 14 Defines direction for this pin in GPIO mode + Uint16 GPIO111:1; // 15 Defines direction for this pin in GPIO mode + Uint16 GPIO112:1; // 16 Defines direction for this pin in GPIO mode + Uint16 GPIO113:1; // 17 Defines direction for this pin in GPIO mode + Uint16 GPIO114:1; // 18 Defines direction for this pin in GPIO mode + Uint16 GPIO115:1; // 19 Defines direction for this pin in GPIO mode + Uint16 GPIO116:1; // 20 Defines direction for this pin in GPIO mode + Uint16 GPIO117:1; // 21 Defines direction for this pin in GPIO mode + Uint16 GPIO118:1; // 22 Defines direction for this pin in GPIO mode + Uint16 GPIO119:1; // 23 Defines direction for this pin in GPIO mode + Uint16 GPIO120:1; // 24 Defines direction for this pin in GPIO mode + Uint16 GPIO121:1; // 25 Defines direction for this pin in GPIO mode + Uint16 GPIO122:1; // 26 Defines direction for this pin in GPIO mode + Uint16 GPIO123:1; // 27 Defines direction for this pin in GPIO mode + Uint16 GPIO124:1; // 28 Defines direction for this pin in GPIO mode + Uint16 GPIO125:1; // 29 Defines direction for this pin in GPIO mode + Uint16 GPIO126:1; // 30 Defines direction for this pin in GPIO mode + Uint16 GPIO127:1; // 31 Defines direction for this pin in GPIO mode +}; + +union GPDDIR_REG { + Uint32 all; + struct GPDDIR_BITS bit; +}; + +struct GPDPUD_BITS { // bits description + Uint16 GPIO96:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO97:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO98:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO99:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO100:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO101:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO102:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO103:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO104:1; // 8 Pull-Up Disable control for this pin + Uint16 GPIO105:1; // 9 Pull-Up Disable control for this pin + Uint16 GPIO106:1; // 10 Pull-Up Disable control for this pin + Uint16 GPIO107:1; // 11 Pull-Up Disable control for this pin + Uint16 GPIO108:1; // 12 Pull-Up Disable control for this pin + Uint16 GPIO109:1; // 13 Pull-Up Disable control for this pin + Uint16 GPIO110:1; // 14 Pull-Up Disable control for this pin + Uint16 GPIO111:1; // 15 Pull-Up Disable control for this pin + Uint16 GPIO112:1; // 16 Pull-Up Disable control for this pin + Uint16 GPIO113:1; // 17 Pull-Up Disable control for this pin + Uint16 GPIO114:1; // 18 Pull-Up Disable control for this pin + Uint16 GPIO115:1; // 19 Pull-Up Disable control for this pin + Uint16 GPIO116:1; // 20 Pull-Up Disable control for this pin + Uint16 GPIO117:1; // 21 Pull-Up Disable control for this pin + Uint16 GPIO118:1; // 22 Pull-Up Disable control for this pin + Uint16 GPIO119:1; // 23 Pull-Up Disable control for this pin + Uint16 GPIO120:1; // 24 Pull-Up Disable control for this pin + Uint16 GPIO121:1; // 25 Pull-Up Disable control for this pin + Uint16 GPIO122:1; // 26 Pull-Up Disable control for this pin + Uint16 GPIO123:1; // 27 Pull-Up Disable control for this pin + Uint16 GPIO124:1; // 28 Pull-Up Disable control for this pin + Uint16 GPIO125:1; // 29 Pull-Up Disable control for this pin + Uint16 GPIO126:1; // 30 Pull-Up Disable control for this pin + Uint16 GPIO127:1; // 31 Pull-Up Disable control for this pin +}; + +union GPDPUD_REG { + Uint32 all; + struct GPDPUD_BITS bit; +}; + +struct GPDINV_BITS { // bits description + Uint16 GPIO96:1; // 0 Input inversion control for this pin + Uint16 GPIO97:1; // 1 Input inversion control for this pin + Uint16 GPIO98:1; // 2 Input inversion control for this pin + Uint16 GPIO99:1; // 3 Input inversion control for this pin + Uint16 GPIO100:1; // 4 Input inversion control for this pin + Uint16 GPIO101:1; // 5 Input inversion control for this pin + Uint16 GPIO102:1; // 6 Input inversion control for this pin + Uint16 GPIO103:1; // 7 Input inversion control for this pin + Uint16 GPIO104:1; // 8 Input inversion control for this pin + Uint16 GPIO105:1; // 9 Input inversion control for this pin + Uint16 GPIO106:1; // 10 Input inversion control for this pin + Uint16 GPIO107:1; // 11 Input inversion control for this pin + Uint16 GPIO108:1; // 12 Input inversion control for this pin + Uint16 GPIO109:1; // 13 Input inversion control for this pin + Uint16 GPIO110:1; // 14 Input inversion control for this pin + Uint16 GPIO111:1; // 15 Input inversion control for this pin + Uint16 GPIO112:1; // 16 Input inversion control for this pin + Uint16 GPIO113:1; // 17 Input inversion control for this pin + Uint16 GPIO114:1; // 18 Input inversion control for this pin + Uint16 GPIO115:1; // 19 Input inversion control for this pin + Uint16 GPIO116:1; // 20 Input inversion control for this pin + Uint16 GPIO117:1; // 21 Input inversion control for this pin + Uint16 GPIO118:1; // 22 Input inversion control for this pin + Uint16 GPIO119:1; // 23 Input inversion control for this pin + Uint16 GPIO120:1; // 24 Input inversion control for this pin + Uint16 GPIO121:1; // 25 Input inversion control for this pin + Uint16 GPIO122:1; // 26 Input inversion control for this pin + Uint16 GPIO123:1; // 27 Input inversion control for this pin + Uint16 GPIO124:1; // 28 Input inversion control for this pin + Uint16 GPIO125:1; // 29 Input inversion control for this pin + Uint16 GPIO126:1; // 30 Input inversion control for this pin + Uint16 GPIO127:1; // 31 Input inversion control for this pin +}; + +union GPDINV_REG { + Uint32 all; + struct GPDINV_BITS bit; +}; + +struct GPDODR_BITS { // bits description + Uint16 GPIO96:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO97:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO98:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO99:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO100:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO101:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO102:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO103:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO104:1; // 8 Outpout Open-Drain control for this pin + Uint16 GPIO105:1; // 9 Outpout Open-Drain control for this pin + Uint16 GPIO106:1; // 10 Outpout Open-Drain control for this pin + Uint16 GPIO107:1; // 11 Outpout Open-Drain control for this pin + Uint16 GPIO108:1; // 12 Outpout Open-Drain control for this pin + Uint16 GPIO109:1; // 13 Outpout Open-Drain control for this pin + Uint16 GPIO110:1; // 14 Outpout Open-Drain control for this pin + Uint16 GPIO111:1; // 15 Outpout Open-Drain control for this pin + Uint16 GPIO112:1; // 16 Outpout Open-Drain control for this pin + Uint16 GPIO113:1; // 17 Outpout Open-Drain control for this pin + Uint16 GPIO114:1; // 18 Outpout Open-Drain control for this pin + Uint16 GPIO115:1; // 19 Outpout Open-Drain control for this pin + Uint16 GPIO116:1; // 20 Outpout Open-Drain control for this pin + Uint16 GPIO117:1; // 21 Outpout Open-Drain control for this pin + Uint16 GPIO118:1; // 22 Outpout Open-Drain control for this pin + Uint16 GPIO119:1; // 23 Outpout Open-Drain control for this pin + Uint16 GPIO120:1; // 24 Outpout Open-Drain control for this pin + Uint16 GPIO121:1; // 25 Outpout Open-Drain control for this pin + Uint16 GPIO122:1; // 26 Outpout Open-Drain control for this pin + Uint16 GPIO123:1; // 27 Outpout Open-Drain control for this pin + Uint16 GPIO124:1; // 28 Outpout Open-Drain control for this pin + Uint16 GPIO125:1; // 29 Outpout Open-Drain control for this pin + Uint16 GPIO126:1; // 30 Outpout Open-Drain control for this pin + Uint16 GPIO127:1; // 31 Outpout Open-Drain control for this pin +}; + +union GPDODR_REG { + Uint32 all; + struct GPDODR_BITS bit; +}; + +struct GPDGMUX1_BITS { // bits description + Uint16 GPIO96:2; // 1:0 Defines pin-muxing selection for GPIO96 + Uint16 GPIO97:2; // 3:2 Defines pin-muxing selection for GPIO97 + Uint16 GPIO98:2; // 5:4 Defines pin-muxing selection for GPIO98 + Uint16 GPIO99:2; // 7:6 Defines pin-muxing selection for GPIO99 + Uint16 GPIO100:2; // 9:8 Defines pin-muxing selection for GPIO100 + Uint16 GPIO101:2; // 11:10 Defines pin-muxing selection for GPIO101 + Uint16 GPIO102:2; // 13:12 Defines pin-muxing selection for GPIO102 + Uint16 GPIO103:2; // 15:14 Defines pin-muxing selection for GPIO103 + Uint16 GPIO104:2; // 17:16 Defines pin-muxing selection for GPIO104 + Uint16 GPIO105:2; // 19:18 Defines pin-muxing selection for GPIO105 + Uint16 GPIO106:2; // 21:20 Defines pin-muxing selection for GPIO106 + Uint16 GPIO107:2; // 23:22 Defines pin-muxing selection for GPIO107 + Uint16 GPIO108:2; // 25:24 Defines pin-muxing selection for GPIO108 + Uint16 GPIO109:2; // 27:26 Defines pin-muxing selection for GPIO109 + Uint16 GPIO110:2; // 29:28 Defines pin-muxing selection for GPIO110 + Uint16 GPIO111:2; // 31:30 Defines pin-muxing selection for GPIO111 +}; + +union GPDGMUX1_REG { + Uint32 all; + struct GPDGMUX1_BITS bit; +}; + +struct GPDGMUX2_BITS { // bits description + Uint16 GPIO112:2; // 1:0 Defines pin-muxing selection for GPIO112 + Uint16 GPIO113:2; // 3:2 Defines pin-muxing selection for GPIO113 + Uint16 GPIO114:2; // 5:4 Defines pin-muxing selection for GPIO114 + Uint16 GPIO115:2; // 7:6 Defines pin-muxing selection for GPIO115 + Uint16 GPIO116:2; // 9:8 Defines pin-muxing selection for GPIO116 + Uint16 GPIO117:2; // 11:10 Defines pin-muxing selection for GPIO117 + Uint16 GPIO118:2; // 13:12 Defines pin-muxing selection for GPIO118 + Uint16 GPIO119:2; // 15:14 Defines pin-muxing selection for GPIO119 + Uint16 GPIO120:2; // 17:16 Defines pin-muxing selection for GPIO120 + Uint16 GPIO121:2; // 19:18 Defines pin-muxing selection for GPIO121 + Uint16 GPIO122:2; // 21:20 Defines pin-muxing selection for GPIO122 + Uint16 GPIO123:2; // 23:22 Defines pin-muxing selection for GPIO123 + Uint16 GPIO124:2; // 25:24 Defines pin-muxing selection for GPIO124 + Uint16 GPIO125:2; // 27:26 Defines pin-muxing selection for GPIO125 + Uint16 GPIO126:2; // 29:28 Defines pin-muxing selection for GPIO126 + Uint16 GPIO127:2; // 31:30 Defines pin-muxing selection for GPIO127 +}; + +union GPDGMUX2_REG { + Uint32 all; + struct GPDGMUX2_BITS bit; +}; + +struct GPDCSEL1_BITS { // bits description + Uint16 GPIO96:4; // 3:0 GPIO96 Master CPU Select + Uint16 GPIO97:4; // 7:4 GPIO97 Master CPU Select + Uint16 GPIO98:4; // 11:8 GPIO98 Master CPU Select + Uint16 GPIO99:4; // 15:12 GPIO99 Master CPU Select + Uint16 GPIO100:4; // 19:16 GPIO100 Master CPU Select + Uint16 GPIO101:4; // 23:20 GPIO101 Master CPU Select + Uint16 GPIO102:4; // 27:24 GPIO102 Master CPU Select + Uint16 GPIO103:4; // 31:28 GPIO103 Master CPU Select +}; + +union GPDCSEL1_REG { + Uint32 all; + struct GPDCSEL1_BITS bit; +}; + +struct GPDCSEL2_BITS { // bits description + Uint16 GPIO104:4; // 3:0 GPIO104 Master CPU Select + Uint16 GPIO105:4; // 7:4 GPIO105 Master CPU Select + Uint16 GPIO106:4; // 11:8 GPIO106 Master CPU Select + Uint16 GPIO107:4; // 15:12 GPIO107 Master CPU Select + Uint16 GPIO108:4; // 19:16 GPIO108 Master CPU Select + Uint16 GPIO109:4; // 23:20 GPIO109 Master CPU Select + Uint16 GPIO110:4; // 27:24 GPIO110 Master CPU Select + Uint16 GPIO111:4; // 31:28 GPIO111 Master CPU Select +}; + +union GPDCSEL2_REG { + Uint32 all; + struct GPDCSEL2_BITS bit; +}; + +struct GPDCSEL3_BITS { // bits description + Uint16 GPIO112:4; // 3:0 GPIO112 Master CPU Select + Uint16 GPIO113:4; // 7:4 GPIO113 Master CPU Select + Uint16 GPIO114:4; // 11:8 GPIO114 Master CPU Select + Uint16 GPIO115:4; // 15:12 GPIO115 Master CPU Select + Uint16 GPIO116:4; // 19:16 GPIO116 Master CPU Select + Uint16 GPIO117:4; // 23:20 GPIO117 Master CPU Select + Uint16 GPIO118:4; // 27:24 GPIO118 Master CPU Select + Uint16 GPIO119:4; // 31:28 GPIO119 Master CPU Select +}; + +union GPDCSEL3_REG { + Uint32 all; + struct GPDCSEL3_BITS bit; +}; + +struct GPDCSEL4_BITS { // bits description + Uint16 GPIO120:4; // 3:0 GPIO120 Master CPU Select + Uint16 GPIO121:4; // 7:4 GPIO121 Master CPU Select + Uint16 GPIO122:4; // 11:8 GPIO122 Master CPU Select + Uint16 GPIO123:4; // 15:12 GPIO123 Master CPU Select + Uint16 GPIO124:4; // 19:16 GPIO124 Master CPU Select + Uint16 GPIO125:4; // 23:20 GPIO125 Master CPU Select + Uint16 GPIO126:4; // 27:24 GPIO126 Master CPU Select + Uint16 GPIO127:4; // 31:28 GPIO127 Master CPU Select +}; + +union GPDCSEL4_REG { + Uint32 all; + struct GPDCSEL4_BITS bit; +}; + +struct GPDLOCK_BITS { // bits description + Uint16 GPIO96:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO97:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO98:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO99:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO100:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO101:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO102:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO103:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO104:1; // 8 Configuration Lock bit for this pin + Uint16 GPIO105:1; // 9 Configuration Lock bit for this pin + Uint16 GPIO106:1; // 10 Configuration Lock bit for this pin + Uint16 GPIO107:1; // 11 Configuration Lock bit for this pin + Uint16 GPIO108:1; // 12 Configuration Lock bit for this pin + Uint16 GPIO109:1; // 13 Configuration Lock bit for this pin + Uint16 GPIO110:1; // 14 Configuration Lock bit for this pin + Uint16 GPIO111:1; // 15 Configuration Lock bit for this pin + Uint16 GPIO112:1; // 16 Configuration Lock bit for this pin + Uint16 GPIO113:1; // 17 Configuration Lock bit for this pin + Uint16 GPIO114:1; // 18 Configuration Lock bit for this pin + Uint16 GPIO115:1; // 19 Configuration Lock bit for this pin + Uint16 GPIO116:1; // 20 Configuration Lock bit for this pin + Uint16 GPIO117:1; // 21 Configuration Lock bit for this pin + Uint16 GPIO118:1; // 22 Configuration Lock bit for this pin + Uint16 GPIO119:1; // 23 Configuration Lock bit for this pin + Uint16 GPIO120:1; // 24 Configuration Lock bit for this pin + Uint16 GPIO121:1; // 25 Configuration Lock bit for this pin + Uint16 GPIO122:1; // 26 Configuration Lock bit for this pin + Uint16 GPIO123:1; // 27 Configuration Lock bit for this pin + Uint16 GPIO124:1; // 28 Configuration Lock bit for this pin + Uint16 GPIO125:1; // 29 Configuration Lock bit for this pin + Uint16 GPIO126:1; // 30 Configuration Lock bit for this pin + Uint16 GPIO127:1; // 31 Configuration Lock bit for this pin +}; + +union GPDLOCK_REG { + Uint32 all; + struct GPDLOCK_BITS bit; +}; + +struct GPDCR_BITS { // bits description + Uint16 GPIO96:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO97:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO98:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO99:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO100:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO101:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO102:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO103:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO104:1; // 8 Configuration lock commit bit for this pin + Uint16 GPIO105:1; // 9 Configuration lock commit bit for this pin + Uint16 GPIO106:1; // 10 Configuration lock commit bit for this pin + Uint16 GPIO107:1; // 11 Configuration lock commit bit for this pin + Uint16 GPIO108:1; // 12 Configuration lock commit bit for this pin + Uint16 GPIO109:1; // 13 Configuration lock commit bit for this pin + Uint16 GPIO110:1; // 14 Configuration lock commit bit for this pin + Uint16 GPIO111:1; // 15 Configuration lock commit bit for this pin + Uint16 GPIO112:1; // 16 Configuration lock commit bit for this pin + Uint16 GPIO113:1; // 17 Configuration lock commit bit for this pin + Uint16 GPIO114:1; // 18 Configuration lock commit bit for this pin + Uint16 GPIO115:1; // 19 Configuration lock commit bit for this pin + Uint16 GPIO116:1; // 20 Configuration lock commit bit for this pin + Uint16 GPIO117:1; // 21 Configuration lock commit bit for this pin + Uint16 GPIO118:1; // 22 Configuration lock commit bit for this pin + Uint16 GPIO119:1; // 23 Configuration lock commit bit for this pin + Uint16 GPIO120:1; // 24 Configuration lock commit bit for this pin + Uint16 GPIO121:1; // 25 Configuration lock commit bit for this pin + Uint16 GPIO122:1; // 26 Configuration lock commit bit for this pin + Uint16 GPIO123:1; // 27 Configuration lock commit bit for this pin + Uint16 GPIO124:1; // 28 Configuration lock commit bit for this pin + Uint16 GPIO125:1; // 29 Configuration lock commit bit for this pin + Uint16 GPIO126:1; // 30 Configuration lock commit bit for this pin + Uint16 GPIO127:1; // 31 Configuration lock commit bit for this pin +}; + +union GPDCR_REG { + Uint32 all; + struct GPDCR_BITS bit; +}; + +struct GPECTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO128 to GPIO135 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO136 to GPIO143 + Uint16 QUALPRD2:8; // 23:16 Qualification sampling period for GPIO144 to GPIO151 + Uint16 QUALPRD3:8; // 31:24 Qualification sampling period for GPIO152 to GPIO159 +}; + +union GPECTRL_REG { + Uint32 all; + struct GPECTRL_BITS bit; +}; + +struct GPEQSEL1_BITS { // bits description + Uint16 GPIO128:2; // 1:0 Select input qualification type for GPIO128 + Uint16 GPIO129:2; // 3:2 Select input qualification type for GPIO129 + Uint16 GPIO130:2; // 5:4 Select input qualification type for GPIO130 + Uint16 GPIO131:2; // 7:6 Select input qualification type for GPIO131 + Uint16 GPIO132:2; // 9:8 Select input qualification type for GPIO132 + Uint16 GPIO133:2; // 11:10 Select input qualification type for GPIO133 + Uint16 GPIO134:2; // 13:12 Select input qualification type for GPIO134 + Uint16 GPIO135:2; // 15:14 Select input qualification type for GPIO135 + Uint16 GPIO136:2; // 17:16 Select input qualification type for GPIO136 + Uint16 GPIO137:2; // 19:18 Select input qualification type for GPIO137 + Uint16 GPIO138:2; // 21:20 Select input qualification type for GPIO138 + Uint16 GPIO139:2; // 23:22 Select input qualification type for GPIO139 + Uint16 GPIO140:2; // 25:24 Select input qualification type for GPIO140 + Uint16 GPIO141:2; // 27:26 Select input qualification type for GPIO141 + Uint16 GPIO142:2; // 29:28 Select input qualification type for GPIO142 + Uint16 GPIO143:2; // 31:30 Select input qualification type for GPIO143 +}; + +union GPEQSEL1_REG { + Uint32 all; + struct GPEQSEL1_BITS bit; +}; + +struct GPEQSEL2_BITS { // bits description + Uint16 GPIO144:2; // 1:0 Select input qualification type for GPIO144 + Uint16 GPIO145:2; // 3:2 Select input qualification type for GPIO145 + Uint16 GPIO146:2; // 5:4 Select input qualification type for GPIO146 + Uint16 GPIO147:2; // 7:6 Select input qualification type for GPIO147 + Uint16 GPIO148:2; // 9:8 Select input qualification type for GPIO148 + Uint16 GPIO149:2; // 11:10 Select input qualification type for GPIO149 + Uint16 GPIO150:2; // 13:12 Select input qualification type for GPIO150 + Uint16 GPIO151:2; // 15:14 Select input qualification type for GPIO151 + Uint16 GPIO152:2; // 17:16 Select input qualification type for GPIO152 + Uint16 GPIO153:2; // 19:18 Select input qualification type for GPIO153 + Uint16 GPIO154:2; // 21:20 Select input qualification type for GPIO154 + Uint16 GPIO155:2; // 23:22 Select input qualification type for GPIO155 + Uint16 GPIO156:2; // 25:24 Select input qualification type for GPIO156 + Uint16 GPIO157:2; // 27:26 Select input qualification type for GPIO157 + Uint16 GPIO158:2; // 29:28 Select input qualification type for GPIO158 + Uint16 GPIO159:2; // 31:30 Select input qualification type for GPIO159 +}; + +union GPEQSEL2_REG { + Uint32 all; + struct GPEQSEL2_BITS bit; +}; + +struct GPEMUX1_BITS { // bits description + Uint16 GPIO128:2; // 1:0 Defines pin-muxing selection for GPIO128 + Uint16 GPIO129:2; // 3:2 Defines pin-muxing selection for GPIO129 + Uint16 GPIO130:2; // 5:4 Defines pin-muxing selection for GPIO130 + Uint16 GPIO131:2; // 7:6 Defines pin-muxing selection for GPIO131 + Uint16 GPIO132:2; // 9:8 Defines pin-muxing selection for GPIO132 + Uint16 GPIO133:2; // 11:10 Defines pin-muxing selection for GPIO133 + Uint16 GPIO134:2; // 13:12 Defines pin-muxing selection for GPIO134 + Uint16 GPIO135:2; // 15:14 Defines pin-muxing selection for GPIO135 + Uint16 GPIO136:2; // 17:16 Defines pin-muxing selection for GPIO136 + Uint16 GPIO137:2; // 19:18 Defines pin-muxing selection for GPIO137 + Uint16 GPIO138:2; // 21:20 Defines pin-muxing selection for GPIO138 + Uint16 GPIO139:2; // 23:22 Defines pin-muxing selection for GPIO139 + Uint16 GPIO140:2; // 25:24 Defines pin-muxing selection for GPIO140 + Uint16 GPIO141:2; // 27:26 Defines pin-muxing selection for GPIO141 + Uint16 GPIO142:2; // 29:28 Defines pin-muxing selection for GPIO142 + Uint16 GPIO143:2; // 31:30 Defines pin-muxing selection for GPIO143 +}; + +union GPEMUX1_REG { + Uint32 all; + struct GPEMUX1_BITS bit; +}; + +struct GPEMUX2_BITS { // bits description + Uint16 GPIO144:2; // 1:0 Defines pin-muxing selection for GPIO144 + Uint16 GPIO145:2; // 3:2 Defines pin-muxing selection for GPIO145 + Uint16 GPIO146:2; // 5:4 Defines pin-muxing selection for GPIO146 + Uint16 GPIO147:2; // 7:6 Defines pin-muxing selection for GPIO147 + Uint16 GPIO148:2; // 9:8 Defines pin-muxing selection for GPIO148 + Uint16 GPIO149:2; // 11:10 Defines pin-muxing selection for GPIO149 + Uint16 GPIO150:2; // 13:12 Defines pin-muxing selection for GPIO150 + Uint16 GPIO151:2; // 15:14 Defines pin-muxing selection for GPIO151 + Uint16 GPIO152:2; // 17:16 Defines pin-muxing selection for GPIO152 + Uint16 GPIO153:2; // 19:18 Defines pin-muxing selection for GPIO153 + Uint16 GPIO154:2; // 21:20 Defines pin-muxing selection for GPIO154 + Uint16 GPIO155:2; // 23:22 Defines pin-muxing selection for GPIO155 + Uint16 GPIO156:2; // 25:24 Defines pin-muxing selection for GPIO156 + Uint16 GPIO157:2; // 27:26 Defines pin-muxing selection for GPIO157 + Uint16 GPIO158:2; // 29:28 Defines pin-muxing selection for GPIO158 + Uint16 GPIO159:2; // 31:30 Defines pin-muxing selection for GPIO159 +}; + +union GPEMUX2_REG { + Uint32 all; + struct GPEMUX2_BITS bit; +}; + +struct GPEDIR_BITS { // bits description + Uint16 GPIO128:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO129:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO130:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO131:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO132:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO133:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO134:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO135:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO136:1; // 8 Defines direction for this pin in GPIO mode + Uint16 GPIO137:1; // 9 Defines direction for this pin in GPIO mode + Uint16 GPIO138:1; // 10 Defines direction for this pin in GPIO mode + Uint16 GPIO139:1; // 11 Defines direction for this pin in GPIO mode + Uint16 GPIO140:1; // 12 Defines direction for this pin in GPIO mode + Uint16 GPIO141:1; // 13 Defines direction for this pin in GPIO mode + Uint16 GPIO142:1; // 14 Defines direction for this pin in GPIO mode + Uint16 GPIO143:1; // 15 Defines direction for this pin in GPIO mode + Uint16 GPIO144:1; // 16 Defines direction for this pin in GPIO mode + Uint16 GPIO145:1; // 17 Defines direction for this pin in GPIO mode + Uint16 GPIO146:1; // 18 Defines direction for this pin in GPIO mode + Uint16 GPIO147:1; // 19 Defines direction for this pin in GPIO mode + Uint16 GPIO148:1; // 20 Defines direction for this pin in GPIO mode + Uint16 GPIO149:1; // 21 Defines direction for this pin in GPIO mode + Uint16 GPIO150:1; // 22 Defines direction for this pin in GPIO mode + Uint16 GPIO151:1; // 23 Defines direction for this pin in GPIO mode + Uint16 GPIO152:1; // 24 Defines direction for this pin in GPIO mode + Uint16 GPIO153:1; // 25 Defines direction for this pin in GPIO mode + Uint16 GPIO154:1; // 26 Defines direction for this pin in GPIO mode + Uint16 GPIO155:1; // 27 Defines direction for this pin in GPIO mode + Uint16 GPIO156:1; // 28 Defines direction for this pin in GPIO mode + Uint16 GPIO157:1; // 29 Defines direction for this pin in GPIO mode + Uint16 GPIO158:1; // 30 Defines direction for this pin in GPIO mode + Uint16 GPIO159:1; // 31 Defines direction for this pin in GPIO mode +}; + +union GPEDIR_REG { + Uint32 all; + struct GPEDIR_BITS bit; +}; + +struct GPEPUD_BITS { // bits description + Uint16 GPIO128:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO129:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO130:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO131:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO132:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO133:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO134:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO135:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO136:1; // 8 Pull-Up Disable control for this pin + Uint16 GPIO137:1; // 9 Pull-Up Disable control for this pin + Uint16 GPIO138:1; // 10 Pull-Up Disable control for this pin + Uint16 GPIO139:1; // 11 Pull-Up Disable control for this pin + Uint16 GPIO140:1; // 12 Pull-Up Disable control for this pin + Uint16 GPIO141:1; // 13 Pull-Up Disable control for this pin + Uint16 GPIO142:1; // 14 Pull-Up Disable control for this pin + Uint16 GPIO143:1; // 15 Pull-Up Disable control for this pin + Uint16 GPIO144:1; // 16 Pull-Up Disable control for this pin + Uint16 GPIO145:1; // 17 Pull-Up Disable control for this pin + Uint16 GPIO146:1; // 18 Pull-Up Disable control for this pin + Uint16 GPIO147:1; // 19 Pull-Up Disable control for this pin + Uint16 GPIO148:1; // 20 Pull-Up Disable control for this pin + Uint16 GPIO149:1; // 21 Pull-Up Disable control for this pin + Uint16 GPIO150:1; // 22 Pull-Up Disable control for this pin + Uint16 GPIO151:1; // 23 Pull-Up Disable control for this pin + Uint16 GPIO152:1; // 24 Pull-Up Disable control for this pin + Uint16 GPIO153:1; // 25 Pull-Up Disable control for this pin + Uint16 GPIO154:1; // 26 Pull-Up Disable control for this pin + Uint16 GPIO155:1; // 27 Pull-Up Disable control for this pin + Uint16 GPIO156:1; // 28 Pull-Up Disable control for this pin + Uint16 GPIO157:1; // 29 Pull-Up Disable control for this pin + Uint16 GPIO158:1; // 30 Pull-Up Disable control for this pin + Uint16 GPIO159:1; // 31 Pull-Up Disable control for this pin +}; + +union GPEPUD_REG { + Uint32 all; + struct GPEPUD_BITS bit; +}; + +struct GPEINV_BITS { // bits description + Uint16 GPIO128:1; // 0 Input inversion control for this pin + Uint16 GPIO129:1; // 1 Input inversion control for this pin + Uint16 GPIO130:1; // 2 Input inversion control for this pin + Uint16 GPIO131:1; // 3 Input inversion control for this pin + Uint16 GPIO132:1; // 4 Input inversion control for this pin + Uint16 GPIO133:1; // 5 Input inversion control for this pin + Uint16 GPIO134:1; // 6 Input inversion control for this pin + Uint16 GPIO135:1; // 7 Input inversion control for this pin + Uint16 GPIO136:1; // 8 Input inversion control for this pin + Uint16 GPIO137:1; // 9 Input inversion control for this pin + Uint16 GPIO138:1; // 10 Input inversion control for this pin + Uint16 GPIO139:1; // 11 Input inversion control for this pin + Uint16 GPIO140:1; // 12 Input inversion control for this pin + Uint16 GPIO141:1; // 13 Input inversion control for this pin + Uint16 GPIO142:1; // 14 Input inversion control for this pin + Uint16 GPIO143:1; // 15 Input inversion control for this pin + Uint16 GPIO144:1; // 16 Input inversion control for this pin + Uint16 GPIO145:1; // 17 Input inversion control for this pin + Uint16 GPIO146:1; // 18 Input inversion control for this pin + Uint16 GPIO147:1; // 19 Input inversion control for this pin + Uint16 GPIO148:1; // 20 Input inversion control for this pin + Uint16 GPIO149:1; // 21 Input inversion control for this pin + Uint16 GPIO150:1; // 22 Input inversion control for this pin + Uint16 GPIO151:1; // 23 Input inversion control for this pin + Uint16 GPIO152:1; // 24 Input inversion control for this pin + Uint16 GPIO153:1; // 25 Input inversion control for this pin + Uint16 GPIO154:1; // 26 Input inversion control for this pin + Uint16 GPIO155:1; // 27 Input inversion control for this pin + Uint16 GPIO156:1; // 28 Input inversion control for this pin + Uint16 GPIO157:1; // 29 Input inversion control for this pin + Uint16 GPIO158:1; // 30 Input inversion control for this pin + Uint16 GPIO159:1; // 31 Input inversion control for this pin +}; + +union GPEINV_REG { + Uint32 all; + struct GPEINV_BITS bit; +}; + +struct GPEODR_BITS { // bits description + Uint16 GPIO128:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO129:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO130:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO131:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO132:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO133:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO134:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO135:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO136:1; // 8 Outpout Open-Drain control for this pin + Uint16 GPIO137:1; // 9 Outpout Open-Drain control for this pin + Uint16 GPIO138:1; // 10 Outpout Open-Drain control for this pin + Uint16 GPIO139:1; // 11 Outpout Open-Drain control for this pin + Uint16 GPIO140:1; // 12 Outpout Open-Drain control for this pin + Uint16 GPIO141:1; // 13 Outpout Open-Drain control for this pin + Uint16 GPIO142:1; // 14 Outpout Open-Drain control for this pin + Uint16 GPIO143:1; // 15 Outpout Open-Drain control for this pin + Uint16 GPIO144:1; // 16 Outpout Open-Drain control for this pin + Uint16 GPIO145:1; // 17 Outpout Open-Drain control for this pin + Uint16 GPIO146:1; // 18 Outpout Open-Drain control for this pin + Uint16 GPIO147:1; // 19 Outpout Open-Drain control for this pin + Uint16 GPIO148:1; // 20 Outpout Open-Drain control for this pin + Uint16 GPIO149:1; // 21 Outpout Open-Drain control for this pin + Uint16 GPIO150:1; // 22 Outpout Open-Drain control for this pin + Uint16 GPIO151:1; // 23 Outpout Open-Drain control for this pin + Uint16 GPIO152:1; // 24 Outpout Open-Drain control for this pin + Uint16 GPIO153:1; // 25 Outpout Open-Drain control for this pin + Uint16 GPIO154:1; // 26 Outpout Open-Drain control for this pin + Uint16 GPIO155:1; // 27 Outpout Open-Drain control for this pin + Uint16 GPIO156:1; // 28 Outpout Open-Drain control for this pin + Uint16 GPIO157:1; // 29 Outpout Open-Drain control for this pin + Uint16 GPIO158:1; // 30 Outpout Open-Drain control for this pin + Uint16 GPIO159:1; // 31 Outpout Open-Drain control for this pin +}; + +union GPEODR_REG { + Uint32 all; + struct GPEODR_BITS bit; +}; + +struct GPEGMUX1_BITS { // bits description + Uint16 GPIO128:2; // 1:0 Defines pin-muxing selection for GPIO128 + Uint16 GPIO129:2; // 3:2 Defines pin-muxing selection for GPIO129 + Uint16 GPIO130:2; // 5:4 Defines pin-muxing selection for GPIO130 + Uint16 GPIO131:2; // 7:6 Defines pin-muxing selection for GPIO131 + Uint16 GPIO132:2; // 9:8 Defines pin-muxing selection for GPIO132 + Uint16 GPIO133:2; // 11:10 Defines pin-muxing selection for GPIO133 + Uint16 GPIO134:2; // 13:12 Defines pin-muxing selection for GPIO134 + Uint16 GPIO135:2; // 15:14 Defines pin-muxing selection for GPIO135 + Uint16 GPIO136:2; // 17:16 Defines pin-muxing selection for GPIO136 + Uint16 GPIO137:2; // 19:18 Defines pin-muxing selection for GPIO137 + Uint16 GPIO138:2; // 21:20 Defines pin-muxing selection for GPIO138 + Uint16 GPIO139:2; // 23:22 Defines pin-muxing selection for GPIO139 + Uint16 GPIO140:2; // 25:24 Defines pin-muxing selection for GPIO140 + Uint16 GPIO141:2; // 27:26 Defines pin-muxing selection for GPIO141 + Uint16 GPIO142:2; // 29:28 Defines pin-muxing selection for GPIO142 + Uint16 GPIO143:2; // 31:30 Defines pin-muxing selection for GPIO143 +}; + +union GPEGMUX1_REG { + Uint32 all; + struct GPEGMUX1_BITS bit; +}; + +struct GPEGMUX2_BITS { // bits description + Uint16 GPIO144:2; // 1:0 Defines pin-muxing selection for GPIO144 + Uint16 GPIO145:2; // 3:2 Defines pin-muxing selection for GPIO145 + Uint16 GPIO146:2; // 5:4 Defines pin-muxing selection for GPIO146 + Uint16 GPIO147:2; // 7:6 Defines pin-muxing selection for GPIO147 + Uint16 GPIO148:2; // 9:8 Defines pin-muxing selection for GPIO148 + Uint16 GPIO149:2; // 11:10 Defines pin-muxing selection for GPIO149 + Uint16 GPIO150:2; // 13:12 Defines pin-muxing selection for GPIO150 + Uint16 GPIO151:2; // 15:14 Defines pin-muxing selection for GPIO151 + Uint16 GPIO152:2; // 17:16 Defines pin-muxing selection for GPIO152 + Uint16 GPIO153:2; // 19:18 Defines pin-muxing selection for GPIO153 + Uint16 GPIO154:2; // 21:20 Defines pin-muxing selection for GPIO154 + Uint16 GPIO155:2; // 23:22 Defines pin-muxing selection for GPIO155 + Uint16 GPIO156:2; // 25:24 Defines pin-muxing selection for GPIO156 + Uint16 GPIO157:2; // 27:26 Defines pin-muxing selection for GPIO157 + Uint16 GPIO158:2; // 29:28 Defines pin-muxing selection for GPIO158 + Uint16 GPIO159:2; // 31:30 Defines pin-muxing selection for GPIO159 +}; + +union GPEGMUX2_REG { + Uint32 all; + struct GPEGMUX2_BITS bit; +}; + +struct GPECSEL1_BITS { // bits description + Uint16 GPIO128:4; // 3:0 GPIO128 Master CPU Select + Uint16 GPIO129:4; // 7:4 GPIO129 Master CPU Select + Uint16 GPIO130:4; // 11:8 GPIO130 Master CPU Select + Uint16 GPIO131:4; // 15:12 GPIO131 Master CPU Select + Uint16 GPIO132:4; // 19:16 GPIO132 Master CPU Select + Uint16 GPIO133:4; // 23:20 GPIO133 Master CPU Select + Uint16 GPIO134:4; // 27:24 GPIO134 Master CPU Select + Uint16 GPIO135:4; // 31:28 GPIO135 Master CPU Select +}; + +union GPECSEL1_REG { + Uint32 all; + struct GPECSEL1_BITS bit; +}; + +struct GPECSEL2_BITS { // bits description + Uint16 GPIO136:4; // 3:0 GPIO136 Master CPU Select + Uint16 GPIO137:4; // 7:4 GPIO137 Master CPU Select + Uint16 GPIO138:4; // 11:8 GPIO138 Master CPU Select + Uint16 GPIO139:4; // 15:12 GPIO139 Master CPU Select + Uint16 GPIO140:4; // 19:16 GPIO140 Master CPU Select + Uint16 GPIO141:4; // 23:20 GPIO141 Master CPU Select + Uint16 GPIO142:4; // 27:24 GPIO142 Master CPU Select + Uint16 GPIO143:4; // 31:28 GPIO143 Master CPU Select +}; + +union GPECSEL2_REG { + Uint32 all; + struct GPECSEL2_BITS bit; +}; + +struct GPECSEL3_BITS { // bits description + Uint16 GPIO144:4; // 3:0 GPIO144 Master CPU Select + Uint16 GPIO145:4; // 7:4 GPIO145 Master CPU Select + Uint16 GPIO146:4; // 11:8 GPIO146 Master CPU Select + Uint16 GPIO147:4; // 15:12 GPIO147 Master CPU Select + Uint16 GPIO148:4; // 19:16 GPIO148 Master CPU Select + Uint16 GPIO149:4; // 23:20 GPIO149 Master CPU Select + Uint16 GPIO150:4; // 27:24 GPIO150 Master CPU Select + Uint16 GPIO151:4; // 31:28 GPIO151 Master CPU Select +}; + +union GPECSEL3_REG { + Uint32 all; + struct GPECSEL3_BITS bit; +}; + +struct GPECSEL4_BITS { // bits description + Uint16 GPIO152:4; // 3:0 GPIO152 Master CPU Select + Uint16 GPIO153:4; // 7:4 GPIO153 Master CPU Select + Uint16 GPIO154:4; // 11:8 GPIO154 Master CPU Select + Uint16 GPIO155:4; // 15:12 GPIO155 Master CPU Select + Uint16 GPIO156:4; // 19:16 GPIO156 Master CPU Select + Uint16 GPIO157:4; // 23:20 GPIO157 Master CPU Select + Uint16 GPIO158:4; // 27:24 GPIO158 Master CPU Select + Uint16 GPIO159:4; // 31:28 GPIO159 Master CPU Select +}; + +union GPECSEL4_REG { + Uint32 all; + struct GPECSEL4_BITS bit; +}; + +struct GPELOCK_BITS { // bits description + Uint16 GPIO128:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO129:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO130:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO131:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO132:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO133:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO134:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO135:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO136:1; // 8 Configuration Lock bit for this pin + Uint16 GPIO137:1; // 9 Configuration Lock bit for this pin + Uint16 GPIO138:1; // 10 Configuration Lock bit for this pin + Uint16 GPIO139:1; // 11 Configuration Lock bit for this pin + Uint16 GPIO140:1; // 12 Configuration Lock bit for this pin + Uint16 GPIO141:1; // 13 Configuration Lock bit for this pin + Uint16 GPIO142:1; // 14 Configuration Lock bit for this pin + Uint16 GPIO143:1; // 15 Configuration Lock bit for this pin + Uint16 GPIO144:1; // 16 Configuration Lock bit for this pin + Uint16 GPIO145:1; // 17 Configuration Lock bit for this pin + Uint16 GPIO146:1; // 18 Configuration Lock bit for this pin + Uint16 GPIO147:1; // 19 Configuration Lock bit for this pin + Uint16 GPIO148:1; // 20 Configuration Lock bit for this pin + Uint16 GPIO149:1; // 21 Configuration Lock bit for this pin + Uint16 GPIO150:1; // 22 Configuration Lock bit for this pin + Uint16 GPIO151:1; // 23 Configuration Lock bit for this pin + Uint16 GPIO152:1; // 24 Configuration Lock bit for this pin + Uint16 GPIO153:1; // 25 Configuration Lock bit for this pin + Uint16 GPIO154:1; // 26 Configuration Lock bit for this pin + Uint16 GPIO155:1; // 27 Configuration Lock bit for this pin + Uint16 GPIO156:1; // 28 Configuration Lock bit for this pin + Uint16 GPIO157:1; // 29 Configuration Lock bit for this pin + Uint16 GPIO158:1; // 30 Configuration Lock bit for this pin + Uint16 GPIO159:1; // 31 Configuration Lock bit for this pin +}; + +union GPELOCK_REG { + Uint32 all; + struct GPELOCK_BITS bit; +}; + +struct GPECR_BITS { // bits description + Uint16 GPIO128:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO129:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO130:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO131:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO132:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO133:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO134:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO135:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO136:1; // 8 Configuration lock commit bit for this pin + Uint16 GPIO137:1; // 9 Configuration lock commit bit for this pin + Uint16 GPIO138:1; // 10 Configuration lock commit bit for this pin + Uint16 GPIO139:1; // 11 Configuration lock commit bit for this pin + Uint16 GPIO140:1; // 12 Configuration lock commit bit for this pin + Uint16 GPIO141:1; // 13 Configuration lock commit bit for this pin + Uint16 GPIO142:1; // 14 Configuration lock commit bit for this pin + Uint16 GPIO143:1; // 15 Configuration lock commit bit for this pin + Uint16 GPIO144:1; // 16 Configuration lock commit bit for this pin + Uint16 GPIO145:1; // 17 Configuration lock commit bit for this pin + Uint16 GPIO146:1; // 18 Configuration lock commit bit for this pin + Uint16 GPIO147:1; // 19 Configuration lock commit bit for this pin + Uint16 GPIO148:1; // 20 Configuration lock commit bit for this pin + Uint16 GPIO149:1; // 21 Configuration lock commit bit for this pin + Uint16 GPIO150:1; // 22 Configuration lock commit bit for this pin + Uint16 GPIO151:1; // 23 Configuration lock commit bit for this pin + Uint16 GPIO152:1; // 24 Configuration lock commit bit for this pin + Uint16 GPIO153:1; // 25 Configuration lock commit bit for this pin + Uint16 GPIO154:1; // 26 Configuration lock commit bit for this pin + Uint16 GPIO155:1; // 27 Configuration lock commit bit for this pin + Uint16 GPIO156:1; // 28 Configuration lock commit bit for this pin + Uint16 GPIO157:1; // 29 Configuration lock commit bit for this pin + Uint16 GPIO158:1; // 30 Configuration lock commit bit for this pin + Uint16 GPIO159:1; // 31 Configuration lock commit bit for this pin +}; + +union GPECR_REG { + Uint32 all; + struct GPECR_BITS bit; +}; + +struct GPFCTRL_BITS { // bits description + Uint16 QUALPRD0:8; // 7:0 Qualification sampling period for GPIO160 to GPIO167 + Uint16 QUALPRD1:8; // 15:8 Qualification sampling period for GPIO168 + Uint16 rsvd1:8; // 23:16 Reserved + Uint16 rsvd2:8; // 31:24 Reserved +}; + +union GPFCTRL_REG { + Uint32 all; + struct GPFCTRL_BITS bit; +}; + +struct GPFQSEL1_BITS { // bits description + Uint16 GPIO160:2; // 1:0 Select input qualification type for GPIO160 + Uint16 GPIO161:2; // 3:2 Select input qualification type for GPIO161 + Uint16 GPIO162:2; // 5:4 Select input qualification type for GPIO162 + Uint16 GPIO163:2; // 7:6 Select input qualification type for GPIO163 + Uint16 GPIO164:2; // 9:8 Select input qualification type for GPIO164 + Uint16 GPIO165:2; // 11:10 Select input qualification type for GPIO165 + Uint16 GPIO166:2; // 13:12 Select input qualification type for GPIO166 + Uint16 GPIO167:2; // 15:14 Select input qualification type for GPIO167 + Uint16 GPIO168:2; // 17:16 Select input qualification type for GPIO168 + Uint16 rsvd1:2; // 19:18 Reserved + Uint16 rsvd2:2; // 21:20 Reserved + Uint16 rsvd3:2; // 23:22 Reserved + Uint16 rsvd4:2; // 25:24 Reserved + Uint16 rsvd5:2; // 27:26 Reserved + Uint16 rsvd6:2; // 29:28 Reserved + Uint16 rsvd7:2; // 31:30 Reserved +}; + +union GPFQSEL1_REG { + Uint32 all; + struct GPFQSEL1_BITS bit; +}; + +struct GPFMUX1_BITS { // bits description + Uint16 GPIO160:2; // 1:0 Defines pin-muxing selection for GPIO160 + Uint16 GPIO161:2; // 3:2 Defines pin-muxing selection for GPIO161 + Uint16 GPIO162:2; // 5:4 Defines pin-muxing selection for GPIO162 + Uint16 GPIO163:2; // 7:6 Defines pin-muxing selection for GPIO163 + Uint16 GPIO164:2; // 9:8 Defines pin-muxing selection for GPIO164 + Uint16 GPIO165:2; // 11:10 Defines pin-muxing selection for GPIO165 + Uint16 GPIO166:2; // 13:12 Defines pin-muxing selection for GPIO166 + Uint16 GPIO167:2; // 15:14 Defines pin-muxing selection for GPIO167 + Uint16 GPIO168:2; // 17:16 Defines pin-muxing selection for GPIO168 + Uint16 rsvd1:2; // 19:18 Reserved + Uint16 rsvd2:2; // 21:20 Reserved + Uint16 rsvd3:2; // 23:22 Reserved + Uint16 rsvd4:2; // 25:24 Reserved + Uint16 rsvd5:2; // 27:26 Reserved + Uint16 rsvd6:2; // 29:28 Reserved + Uint16 rsvd7:2; // 31:30 Reserved +}; + +union GPFMUX1_REG { + Uint32 all; + struct GPFMUX1_BITS bit; +}; + +struct GPFDIR_BITS { // bits description + Uint16 GPIO160:1; // 0 Defines direction for this pin in GPIO mode + Uint16 GPIO161:1; // 1 Defines direction for this pin in GPIO mode + Uint16 GPIO162:1; // 2 Defines direction for this pin in GPIO mode + Uint16 GPIO163:1; // 3 Defines direction for this pin in GPIO mode + Uint16 GPIO164:1; // 4 Defines direction for this pin in GPIO mode + Uint16 GPIO165:1; // 5 Defines direction for this pin in GPIO mode + Uint16 GPIO166:1; // 6 Defines direction for this pin in GPIO mode + Uint16 GPIO167:1; // 7 Defines direction for this pin in GPIO mode + Uint16 GPIO168:1; // 8 Defines direction for this pin in GPIO mode + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFDIR_REG { + Uint32 all; + struct GPFDIR_BITS bit; +}; + +struct GPFPUD_BITS { // bits description + Uint16 GPIO160:1; // 0 Pull-Up Disable control for this pin + Uint16 GPIO161:1; // 1 Pull-Up Disable control for this pin + Uint16 GPIO162:1; // 2 Pull-Up Disable control for this pin + Uint16 GPIO163:1; // 3 Pull-Up Disable control for this pin + Uint16 GPIO164:1; // 4 Pull-Up Disable control for this pin + Uint16 GPIO165:1; // 5 Pull-Up Disable control for this pin + Uint16 GPIO166:1; // 6 Pull-Up Disable control for this pin + Uint16 GPIO167:1; // 7 Pull-Up Disable control for this pin + Uint16 GPIO168:1; // 8 Pull-Up Disable control for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFPUD_REG { + Uint32 all; + struct GPFPUD_BITS bit; +}; + +struct GPFINV_BITS { // bits description + Uint16 GPIO160:1; // 0 Input inversion control for this pin + Uint16 GPIO161:1; // 1 Input inversion control for this pin + Uint16 GPIO162:1; // 2 Input inversion control for this pin + Uint16 GPIO163:1; // 3 Input inversion control for this pin + Uint16 GPIO164:1; // 4 Input inversion control for this pin + Uint16 GPIO165:1; // 5 Input inversion control for this pin + Uint16 GPIO166:1; // 6 Input inversion control for this pin + Uint16 GPIO167:1; // 7 Input inversion control for this pin + Uint16 GPIO168:1; // 8 Input inversion control for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFINV_REG { + Uint32 all; + struct GPFINV_BITS bit; +}; + +struct GPFODR_BITS { // bits description + Uint16 GPIO160:1; // 0 Outpout Open-Drain control for this pin + Uint16 GPIO161:1; // 1 Outpout Open-Drain control for this pin + Uint16 GPIO162:1; // 2 Outpout Open-Drain control for this pin + Uint16 GPIO163:1; // 3 Outpout Open-Drain control for this pin + Uint16 GPIO164:1; // 4 Outpout Open-Drain control for this pin + Uint16 GPIO165:1; // 5 Outpout Open-Drain control for this pin + Uint16 GPIO166:1; // 6 Outpout Open-Drain control for this pin + Uint16 GPIO167:1; // 7 Outpout Open-Drain control for this pin + Uint16 GPIO168:1; // 8 Outpout Open-Drain control for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFODR_REG { + Uint32 all; + struct GPFODR_BITS bit; +}; + +struct GPFGMUX1_BITS { // bits description + Uint16 GPIO160:2; // 1:0 Defines pin-muxing selection for GPIO160 + Uint16 GPIO161:2; // 3:2 Defines pin-muxing selection for GPIO161 + Uint16 GPIO162:2; // 5:4 Defines pin-muxing selection for GPIO162 + Uint16 GPIO163:2; // 7:6 Defines pin-muxing selection for GPIO163 + Uint16 GPIO164:2; // 9:8 Defines pin-muxing selection for GPIO164 + Uint16 GPIO165:2; // 11:10 Defines pin-muxing selection for GPIO165 + Uint16 GPIO166:2; // 13:12 Defines pin-muxing selection for GPIO166 + Uint16 GPIO167:2; // 15:14 Defines pin-muxing selection for GPIO167 + Uint16 GPIO168:2; // 17:16 Defines pin-muxing selection for GPIO168 + Uint16 rsvd1:2; // 19:18 Reserved + Uint16 rsvd2:2; // 21:20 Reserved + Uint16 rsvd3:2; // 23:22 Reserved + Uint16 rsvd4:2; // 25:24 Reserved + Uint16 rsvd5:2; // 27:26 Reserved + Uint16 rsvd6:2; // 29:28 Reserved + Uint16 rsvd7:2; // 31:30 Reserved +}; + +union GPFGMUX1_REG { + Uint32 all; + struct GPFGMUX1_BITS bit; +}; + +struct GPFCSEL1_BITS { // bits description + Uint16 GPIO160:4; // 3:0 GPIO160 Master CPU Select + Uint16 GPIO161:4; // 7:4 GPIO161 Master CPU Select + Uint16 GPIO162:4; // 11:8 GPIO162 Master CPU Select + Uint16 GPIO163:4; // 15:12 GPIO163 Master CPU Select + Uint16 GPIO164:4; // 19:16 GPIO164 Master CPU Select + Uint16 GPIO165:4; // 23:20 GPIO165 Master CPU Select + Uint16 GPIO166:4; // 27:24 GPIO166 Master CPU Select + Uint16 GPIO167:4; // 31:28 GPIO167 Master CPU Select +}; + +union GPFCSEL1_REG { + Uint32 all; + struct GPFCSEL1_BITS bit; +}; + +struct GPFCSEL2_BITS { // bits description + Uint16 GPIO168:4; // 3:0 GPIO168 Master CPU Select + Uint16 rsvd1:4; // 7:4 Reserved + Uint16 rsvd2:4; // 11:8 Reserved + Uint16 rsvd3:4; // 15:12 Reserved + Uint16 rsvd4:4; // 19:16 Reserved + Uint16 rsvd5:4; // 23:20 Reserved + Uint16 rsvd6:4; // 27:24 Reserved + Uint16 rsvd7:4; // 31:28 Reserved +}; + +union GPFCSEL2_REG { + Uint32 all; + struct GPFCSEL2_BITS bit; +}; + +struct GPFLOCK_BITS { // bits description + Uint16 GPIO160:1; // 0 Configuration Lock bit for this pin + Uint16 GPIO161:1; // 1 Configuration Lock bit for this pin + Uint16 GPIO162:1; // 2 Configuration Lock bit for this pin + Uint16 GPIO163:1; // 3 Configuration Lock bit for this pin + Uint16 GPIO164:1; // 4 Configuration Lock bit for this pin + Uint16 GPIO165:1; // 5 Configuration Lock bit for this pin + Uint16 GPIO166:1; // 6 Configuration Lock bit for this pin + Uint16 GPIO167:1; // 7 Configuration Lock bit for this pin + Uint16 GPIO168:1; // 8 Configuration Lock bit for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFLOCK_REG { + Uint32 all; + struct GPFLOCK_BITS bit; +}; + +struct GPFCR_BITS { // bits description + Uint16 GPIO160:1; // 0 Configuration lock commit bit for this pin + Uint16 GPIO161:1; // 1 Configuration lock commit bit for this pin + Uint16 GPIO162:1; // 2 Configuration lock commit bit for this pin + Uint16 GPIO163:1; // 3 Configuration lock commit bit for this pin + Uint16 GPIO164:1; // 4 Configuration lock commit bit for this pin + Uint16 GPIO165:1; // 5 Configuration lock commit bit for this pin + Uint16 GPIO166:1; // 6 Configuration lock commit bit for this pin + Uint16 GPIO167:1; // 7 Configuration lock commit bit for this pin + Uint16 GPIO168:1; // 8 Configuration lock commit bit for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFCR_REG { + Uint32 all; + struct GPFCR_BITS bit; +}; + +struct GPIO_CTRL_REGS { + union GPACTRL_REG GPACTRL; // GPIO A Qualification Sampling Period Control (GPIO0 to 31) + union GPAQSEL1_REG GPAQSEL1; // GPIO A Qualifier Select 1 Register (GPIO0 to 15) + union GPAQSEL2_REG GPAQSEL2; // GPIO A Qualifier Select 2 Register (GPIO16 to 31) + union GPAMUX1_REG GPAMUX1; // GPIO A Mux 1 Register (GPIO0 to 15) + union GPAMUX2_REG GPAMUX2; // GPIO A Mux 2 Register (GPIO16 to 31) + union GPADIR_REG GPADIR; // GPIO A Direction Register (GPIO0 to 31) + union GPAPUD_REG GPAPUD; // GPIO A Pull Up Disable Register (GPIO0 to 31) + Uint16 rsvd1[2]; // Reserved + union GPAINV_REG GPAINV; // GPIO A Input Polarity Invert Registers (GPIO0 to 31) + union GPAODR_REG GPAODR; // GPIO A Open Drain Output Register (GPIO0 to GPIO31) + Uint16 rsvd2[12]; // Reserved + union GPAGMUX1_REG GPAGMUX1; // GPIO A Peripheral Group Mux (GPIO0 to 15) + union GPAGMUX2_REG GPAGMUX2; // GPIO A Peripheral Group Mux (GPIO16 to 31) + Uint16 rsvd3[4]; // Reserved + union GPACSEL1_REG GPACSEL1; // GPIO A Core Select Register (GPIO0 to 7) + union GPACSEL2_REG GPACSEL2; // GPIO A Core Select Register (GPIO8 to 15) + union GPACSEL3_REG GPACSEL3; // GPIO A Core Select Register (GPIO16 to 23) + union GPACSEL4_REG GPACSEL4; // GPIO A Core Select Register (GPIO24 to 31) + Uint16 rsvd4[12]; // Reserved + union GPALOCK_REG GPALOCK; // GPIO A Lock Configuration Register (GPIO0 to 31) + union GPACR_REG GPACR; // GPIO A Lock Commit Register (GPIO0 to 31) + union GPBCTRL_REG GPBCTRL; // GPIO B Qualification Sampling Period Control (GPIO32 to 63) + union GPBQSEL1_REG GPBQSEL1; // GPIO B Qualifier Select 1 Register (GPIO32 to 47) + union GPBQSEL2_REG GPBQSEL2; // GPIO B Qualifier Select 2 Register (GPIO48 to 63) + union GPBMUX1_REG GPBMUX1; // GPIO B Mux 1 Register (GPIO32 to 47) + union GPBMUX2_REG GPBMUX2; // GPIO B Mux 2 Register (GPIO48 to 63) + union GPBDIR_REG GPBDIR; // GPIO B Direction Register (GPIO32 to 63) + union GPBPUD_REG GPBPUD; // GPIO B Pull Up Disable Register (GPIO32 to 63) + Uint16 rsvd5[2]; // Reserved + union GPBINV_REG GPBINV; // GPIO B Input Polarity Invert Registers (GPIO32 to 63) + union GPBODR_REG GPBODR; // GPIO B Open Drain Output Register (GPIO32 to GPIO63) + union GPBAMSEL_REG GPBAMSEL; // GPIO B Analog Mode Select register (GPIO32 to GPIO63) + Uint16 rsvd6[10]; // Reserved + union GPBGMUX1_REG GPBGMUX1; // GPIO B Peripheral Group Mux (GPIO32 to 47) + union GPBGMUX2_REG GPBGMUX2; // GPIO B Peripheral Group Mux (GPIO48 to 63) + Uint16 rsvd7[4]; // Reserved + union GPBCSEL1_REG GPBCSEL1; // GPIO B Core Select Register (GPIO32 to 39) + union GPBCSEL2_REG GPBCSEL2; // GPIO B Core Select Register (GPIO40 to 47) + union GPBCSEL3_REG GPBCSEL3; // GPIO B Core Select Register (GPIO48 to 55) + union GPBCSEL4_REG GPBCSEL4; // GPIO B Core Select Register (GPIO56 to 63) + Uint16 rsvd8[12]; // Reserved + union GPBLOCK_REG GPBLOCK; // GPIO B Lock Configuration Register (GPIO32 to 63) + union GPBCR_REG GPBCR; // GPIO B Lock Commit Register (GPIO32 to 63) + union GPCCTRL_REG GPCCTRL; // GPIO C Qualification Sampling Period Control (GPIO64 to 95) + union GPCQSEL1_REG GPCQSEL1; // GPIO C Qualifier Select 1 Register (GPIO64 to 79) + union GPCQSEL2_REG GPCQSEL2; // GPIO C Qualifier Select 2 Register (GPIO80 to 95) + union GPCMUX1_REG GPCMUX1; // GPIO C Mux 1 Register (GPIO64 to 79) + union GPCMUX2_REG GPCMUX2; // GPIO C Mux 2 Register (GPIO80 to 95) + union GPCDIR_REG GPCDIR; // GPIO C Direction Register (GPIO64 to 95) + union GPCPUD_REG GPCPUD; // GPIO C Pull Up Disable Register (GPIO64 to 95) + Uint16 rsvd9[2]; // Reserved + union GPCINV_REG GPCINV; // GPIO C Input Polarity Invert Registers (GPIO64 to 95) + union GPCODR_REG GPCODR; // GPIO C Open Drain Output Register (GPIO64 to GPIO95) + Uint16 rsvd10[12]; // Reserved + union GPCGMUX1_REG GPCGMUX1; // GPIO C Peripheral Group Mux (GPIO64 to 79) + union GPCGMUX2_REG GPCGMUX2; // GPIO C Peripheral Group Mux (GPIO80 to 95) + Uint16 rsvd11[4]; // Reserved + union GPCCSEL1_REG GPCCSEL1; // GPIO C Core Select Register (GPIO64 to 71) + union GPCCSEL2_REG GPCCSEL2; // GPIO C Core Select Register (GPIO72 to 79) + union GPCCSEL3_REG GPCCSEL3; // GPIO C Core Select Register (GPIO80 to 87) + union GPCCSEL4_REG GPCCSEL4; // GPIO C Core Select Register (GPIO88 to 95) + Uint16 rsvd12[12]; // Reserved + union GPCLOCK_REG GPCLOCK; // GPIO C Lock Configuration Register (GPIO64 to 95) + union GPCCR_REG GPCCR; // GPIO C Lock Commit Register (GPIO64 to 95) + union GPDCTRL_REG GPDCTRL; // GPIO D Qualification Sampling Period Control (GPIO96 to 127) + union GPDQSEL1_REG GPDQSEL1; // GPIO D Qualifier Select 1 Register (GPIO96 to 111) + union GPDQSEL2_REG GPDQSEL2; // GPIO D Qualifier Select 2 Register (GPIO112 to 127) + union GPDMUX1_REG GPDMUX1; // GPIO D Mux 1 Register (GPIO96 to 111) + union GPDMUX2_REG GPDMUX2; // GPIO D Mux 2 Register (GPIO112 to 127) + union GPDDIR_REG GPDDIR; // GPIO D Direction Register (GPIO96 to 127) + union GPDPUD_REG GPDPUD; // GPIO D Pull Up Disable Register (GPIO96 to 127) + Uint16 rsvd13[2]; // Reserved + union GPDINV_REG GPDINV; // GPIO D Input Polarity Invert Registers (GPIO96 to 127) + union GPDODR_REG GPDODR; // GPIO D Open Drain Output Register (GPIO96 to GPIO127) + Uint16 rsvd14[12]; // Reserved + union GPDGMUX1_REG GPDGMUX1; // GPIO D Peripheral Group Mux (GPIO96 to 111) + union GPDGMUX2_REG GPDGMUX2; // GPIO D Peripheral Group Mux (GPIO112 to 127) + Uint16 rsvd15[4]; // Reserved + union GPDCSEL1_REG GPDCSEL1; // GPIO D Core Select Register (GPIO96 to 103) + union GPDCSEL2_REG GPDCSEL2; // GPIO D Core Select Register (GPIO104 to 111) + union GPDCSEL3_REG GPDCSEL3; // GPIO D Core Select Register (GPIO112 to 119) + union GPDCSEL4_REG GPDCSEL4; // GPIO D Core Select Register (GPIO120 to 127) + Uint16 rsvd16[12]; // Reserved + union GPDLOCK_REG GPDLOCK; // GPIO D Lock Configuration Register (GPIO96 to 127) + union GPDCR_REG GPDCR; // GPIO D Lock Commit Register (GPIO96 to 127) + union GPECTRL_REG GPECTRL; // GPIO E Qualification Sampling Period Control (GPIO128 to 159) + union GPEQSEL1_REG GPEQSEL1; // GPIO E Qualifier Select 1 Register (GPIO128 to 143) + union GPEQSEL2_REG GPEQSEL2; // GPIO E Qualifier Select 2 Register (GPIO144 to 159) + union GPEMUX1_REG GPEMUX1; // GPIO E Mux 1 Register (GPIO128 to 143) + union GPEMUX2_REG GPEMUX2; // GPIO E Mux 2 Register (GPIO144 to 159) + union GPEDIR_REG GPEDIR; // GPIO E Direction Register (GPIO128 to 159) + union GPEPUD_REG GPEPUD; // GPIO E Pull Up Disable Register (GPIO128 to 159) + Uint16 rsvd17[2]; // Reserved + union GPEINV_REG GPEINV; // GPIO E Input Polarity Invert Registers (GPIO128 to 159) + union GPEODR_REG GPEODR; // GPIO E Open Drain Output Register (GPIO128 to GPIO159) + Uint16 rsvd18[12]; // Reserved + union GPEGMUX1_REG GPEGMUX1; // GPIO E Peripheral Group Mux (GPIO128 to 143) + union GPEGMUX2_REG GPEGMUX2; // GPIO E Peripheral Group Mux (GPIO144 to 159) + Uint16 rsvd19[4]; // Reserved + union GPECSEL1_REG GPECSEL1; // GPIO E Core Select Register (GPIO128 to 135) + union GPECSEL2_REG GPECSEL2; // GPIO E Core Select Register (GPIO136 to 143) + union GPECSEL3_REG GPECSEL3; // GPIO E Core Select Register (GPIO144 to 151) + union GPECSEL4_REG GPECSEL4; // GPIO E Core Select Register (GPIO152 to 159) + Uint16 rsvd20[12]; // Reserved + union GPELOCK_REG GPELOCK; // GPIO E Lock Configuration Register (GPIO128 to 159) + union GPECR_REG GPECR; // GPIO E Lock Commit Register (GPIO128 to 159) + union GPFCTRL_REG GPFCTRL; // GPIO F Qualification Sampling Period Control (GPIO160 to 168) + union GPFQSEL1_REG GPFQSEL1; // GPIO F Qualifier Select 1 Register (GPIO160 to 168) + Uint16 rsvd21[2]; // Reserved + union GPFMUX1_REG GPFMUX1; // GPIO F Mux 1 Register (GPIO160 to 168) + Uint16 rsvd22[2]; // Reserved + union GPFDIR_REG GPFDIR; // GPIO F Direction Register (GPIO160 to 168) + union GPFPUD_REG GPFPUD; // GPIO F Pull Up Disable Register (GPIO160 to 168) + Uint16 rsvd23[2]; // Reserved + union GPFINV_REG GPFINV; // GPIO F Input Polarity Invert Registers (GPIO160 to 168) + union GPFODR_REG GPFODR; // GPIO F Open Drain Output Register (GPIO160 to GPIO168) + Uint16 rsvd24[12]; // Reserved + union GPFGMUX1_REG GPFGMUX1; // GPIO F Peripheral Group Mux (GPIO160 to 168) + Uint16 rsvd25[6]; // Reserved + union GPFCSEL1_REG GPFCSEL1; // GPIO F Core Select Register (GPIO160 to 167) + union GPFCSEL2_REG GPFCSEL2; // GPIO F Core Select Register (GPIO168) + Uint16 rsvd26[16]; // Reserved + union GPFLOCK_REG GPFLOCK; // GPIO F Lock Configuration Register (GPIO160 to 168) + union GPFCR_REG GPFCR; // GPIO F Lock Commit Register (GPIO160 to 168) +}; + +struct GPADAT_BITS { // bits description + Uint16 GPIO0:1; // 0 Data Register for this pin + Uint16 GPIO1:1; // 1 Data Register for this pin + Uint16 GPIO2:1; // 2 Data Register for this pin + Uint16 GPIO3:1; // 3 Data Register for this pin + Uint16 GPIO4:1; // 4 Data Register for this pin + Uint16 GPIO5:1; // 5 Data Register for this pin + Uint16 GPIO6:1; // 6 Data Register for this pin + Uint16 GPIO7:1; // 7 Data Register for this pin + Uint16 GPIO8:1; // 8 Data Register for this pin + Uint16 GPIO9:1; // 9 Data Register for this pin + Uint16 GPIO10:1; // 10 Data Register for this pin + Uint16 GPIO11:1; // 11 Data Register for this pin + Uint16 GPIO12:1; // 12 Data Register for this pin + Uint16 GPIO13:1; // 13 Data Register for this pin + Uint16 GPIO14:1; // 14 Data Register for this pin + Uint16 GPIO15:1; // 15 Data Register for this pin + Uint16 GPIO16:1; // 16 Data Register for this pin + Uint16 GPIO17:1; // 17 Data Register for this pin + Uint16 GPIO18:1; // 18 Data Register for this pin + Uint16 GPIO19:1; // 19 Data Register for this pin + Uint16 GPIO20:1; // 20 Data Register for this pin + Uint16 GPIO21:1; // 21 Data Register for this pin + Uint16 GPIO22:1; // 22 Data Register for this pin + Uint16 GPIO23:1; // 23 Data Register for this pin + Uint16 GPIO24:1; // 24 Data Register for this pin + Uint16 GPIO25:1; // 25 Data Register for this pin + Uint16 GPIO26:1; // 26 Data Register for this pin + Uint16 GPIO27:1; // 27 Data Register for this pin + Uint16 GPIO28:1; // 28 Data Register for this pin + Uint16 GPIO29:1; // 29 Data Register for this pin + Uint16 GPIO30:1; // 30 Data Register for this pin + Uint16 GPIO31:1; // 31 Data Register for this pin +}; + +union GPADAT_REG { + Uint32 all; + struct GPADAT_BITS bit; +}; + +struct GPASET_BITS { // bits description + Uint16 GPIO0:1; // 0 Output Set bit for this pin + Uint16 GPIO1:1; // 1 Output Set bit for this pin + Uint16 GPIO2:1; // 2 Output Set bit for this pin + Uint16 GPIO3:1; // 3 Output Set bit for this pin + Uint16 GPIO4:1; // 4 Output Set bit for this pin + Uint16 GPIO5:1; // 5 Output Set bit for this pin + Uint16 GPIO6:1; // 6 Output Set bit for this pin + Uint16 GPIO7:1; // 7 Output Set bit for this pin + Uint16 GPIO8:1; // 8 Output Set bit for this pin + Uint16 GPIO9:1; // 9 Output Set bit for this pin + Uint16 GPIO10:1; // 10 Output Set bit for this pin + Uint16 GPIO11:1; // 11 Output Set bit for this pin + Uint16 GPIO12:1; // 12 Output Set bit for this pin + Uint16 GPIO13:1; // 13 Output Set bit for this pin + Uint16 GPIO14:1; // 14 Output Set bit for this pin + Uint16 GPIO15:1; // 15 Output Set bit for this pin + Uint16 GPIO16:1; // 16 Output Set bit for this pin + Uint16 GPIO17:1; // 17 Output Set bit for this pin + Uint16 GPIO18:1; // 18 Output Set bit for this pin + Uint16 GPIO19:1; // 19 Output Set bit for this pin + Uint16 GPIO20:1; // 20 Output Set bit for this pin + Uint16 GPIO21:1; // 21 Output Set bit for this pin + Uint16 GPIO22:1; // 22 Output Set bit for this pin + Uint16 GPIO23:1; // 23 Output Set bit for this pin + Uint16 GPIO24:1; // 24 Output Set bit for this pin + Uint16 GPIO25:1; // 25 Output Set bit for this pin + Uint16 GPIO26:1; // 26 Output Set bit for this pin + Uint16 GPIO27:1; // 27 Output Set bit for this pin + Uint16 GPIO28:1; // 28 Output Set bit for this pin + Uint16 GPIO29:1; // 29 Output Set bit for this pin + Uint16 GPIO30:1; // 30 Output Set bit for this pin + Uint16 GPIO31:1; // 31 Output Set bit for this pin +}; + +union GPASET_REG { + Uint32 all; + struct GPASET_BITS bit; +}; + +struct GPACLEAR_BITS { // bits description + Uint16 GPIO0:1; // 0 Output Clear bit for this pin + Uint16 GPIO1:1; // 1 Output Clear bit for this pin + Uint16 GPIO2:1; // 2 Output Clear bit for this pin + Uint16 GPIO3:1; // 3 Output Clear bit for this pin + Uint16 GPIO4:1; // 4 Output Clear bit for this pin + Uint16 GPIO5:1; // 5 Output Clear bit for this pin + Uint16 GPIO6:1; // 6 Output Clear bit for this pin + Uint16 GPIO7:1; // 7 Output Clear bit for this pin + Uint16 GPIO8:1; // 8 Output Clear bit for this pin + Uint16 GPIO9:1; // 9 Output Clear bit for this pin + Uint16 GPIO10:1; // 10 Output Clear bit for this pin + Uint16 GPIO11:1; // 11 Output Clear bit for this pin + Uint16 GPIO12:1; // 12 Output Clear bit for this pin + Uint16 GPIO13:1; // 13 Output Clear bit for this pin + Uint16 GPIO14:1; // 14 Output Clear bit for this pin + Uint16 GPIO15:1; // 15 Output Clear bit for this pin + Uint16 GPIO16:1; // 16 Output Clear bit for this pin + Uint16 GPIO17:1; // 17 Output Clear bit for this pin + Uint16 GPIO18:1; // 18 Output Clear bit for this pin + Uint16 GPIO19:1; // 19 Output Clear bit for this pin + Uint16 GPIO20:1; // 20 Output Clear bit for this pin + Uint16 GPIO21:1; // 21 Output Clear bit for this pin + Uint16 GPIO22:1; // 22 Output Clear bit for this pin + Uint16 GPIO23:1; // 23 Output Clear bit for this pin + Uint16 GPIO24:1; // 24 Output Clear bit for this pin + Uint16 GPIO25:1; // 25 Output Clear bit for this pin + Uint16 GPIO26:1; // 26 Output Clear bit for this pin + Uint16 GPIO27:1; // 27 Output Clear bit for this pin + Uint16 GPIO28:1; // 28 Output Clear bit for this pin + Uint16 GPIO29:1; // 29 Output Clear bit for this pin + Uint16 GPIO30:1; // 30 Output Clear bit for this pin + Uint16 GPIO31:1; // 31 Output Clear bit for this pin +}; + +union GPACLEAR_REG { + Uint32 all; + struct GPACLEAR_BITS bit; +}; + +struct GPATOGGLE_BITS { // bits description + Uint16 GPIO0:1; // 0 Output Toggle bit for this pin + Uint16 GPIO1:1; // 1 Output Toggle bit for this pin + Uint16 GPIO2:1; // 2 Output Toggle bit for this pin + Uint16 GPIO3:1; // 3 Output Toggle bit for this pin + Uint16 GPIO4:1; // 4 Output Toggle bit for this pin + Uint16 GPIO5:1; // 5 Output Toggle bit for this pin + Uint16 GPIO6:1; // 6 Output Toggle bit for this pin + Uint16 GPIO7:1; // 7 Output Toggle bit for this pin + Uint16 GPIO8:1; // 8 Output Toggle bit for this pin + Uint16 GPIO9:1; // 9 Output Toggle bit for this pin + Uint16 GPIO10:1; // 10 Output Toggle bit for this pin + Uint16 GPIO11:1; // 11 Output Toggle bit for this pin + Uint16 GPIO12:1; // 12 Output Toggle bit for this pin + Uint16 GPIO13:1; // 13 Output Toggle bit for this pin + Uint16 GPIO14:1; // 14 Output Toggle bit for this pin + Uint16 GPIO15:1; // 15 Output Toggle bit for this pin + Uint16 GPIO16:1; // 16 Output Toggle bit for this pin + Uint16 GPIO17:1; // 17 Output Toggle bit for this pin + Uint16 GPIO18:1; // 18 Output Toggle bit for this pin + Uint16 GPIO19:1; // 19 Output Toggle bit for this pin + Uint16 GPIO20:1; // 20 Output Toggle bit for this pin + Uint16 GPIO21:1; // 21 Output Toggle bit for this pin + Uint16 GPIO22:1; // 22 Output Toggle bit for this pin + Uint16 GPIO23:1; // 23 Output Toggle bit for this pin + Uint16 GPIO24:1; // 24 Output Toggle bit for this pin + Uint16 GPIO25:1; // 25 Output Toggle bit for this pin + Uint16 GPIO26:1; // 26 Output Toggle bit for this pin + Uint16 GPIO27:1; // 27 Output Toggle bit for this pin + Uint16 GPIO28:1; // 28 Output Toggle bit for this pin + Uint16 GPIO29:1; // 29 Output Toggle bit for this pin + Uint16 GPIO30:1; // 30 Output Toggle bit for this pin + Uint16 GPIO31:1; // 31 Output Toggle bit for this pin +}; + +union GPATOGGLE_REG { + Uint32 all; + struct GPATOGGLE_BITS bit; +}; + +struct GPBDAT_BITS { // bits description + Uint16 GPIO32:1; // 0 Data Register for this pin + Uint16 GPIO33:1; // 1 Data Register for this pin + Uint16 GPIO34:1; // 2 Data Register for this pin + Uint16 GPIO35:1; // 3 Data Register for this pin + Uint16 GPIO36:1; // 4 Data Register for this pin + Uint16 GPIO37:1; // 5 Data Register for this pin + Uint16 GPIO38:1; // 6 Data Register for this pin + Uint16 GPIO39:1; // 7 Data Register for this pin + Uint16 GPIO40:1; // 8 Data Register for this pin + Uint16 GPIO41:1; // 9 Data Register for this pin + Uint16 GPIO42:1; // 10 Data Register for this pin + Uint16 GPIO43:1; // 11 Data Register for this pin + Uint16 GPIO44:1; // 12 Data Register for this pin + Uint16 GPIO45:1; // 13 Data Register for this pin + Uint16 GPIO46:1; // 14 Data Register for this pin + Uint16 GPIO47:1; // 15 Data Register for this pin + Uint16 GPIO48:1; // 16 Data Register for this pin + Uint16 GPIO49:1; // 17 Data Register for this pin + Uint16 GPIO50:1; // 18 Data Register for this pin + Uint16 GPIO51:1; // 19 Data Register for this pin + Uint16 GPIO52:1; // 20 Data Register for this pin + Uint16 GPIO53:1; // 21 Data Register for this pin + Uint16 GPIO54:1; // 22 Data Register for this pin + Uint16 GPIO55:1; // 23 Data Register for this pin + Uint16 GPIO56:1; // 24 Data Register for this pin + Uint16 GPIO57:1; // 25 Data Register for this pin + Uint16 GPIO58:1; // 26 Data Register for this pin + Uint16 GPIO59:1; // 27 Data Register for this pin + Uint16 GPIO60:1; // 28 Data Register for this pin + Uint16 GPIO61:1; // 29 Data Register for this pin + Uint16 GPIO62:1; // 30 Data Register for this pin + Uint16 GPIO63:1; // 31 Data Register for this pin +}; + +union GPBDAT_REG { + Uint32 all; + struct GPBDAT_BITS bit; +}; + +struct GPBSET_BITS { // bits description + Uint16 GPIO32:1; // 0 Output Set bit for this pin + Uint16 GPIO33:1; // 1 Output Set bit for this pin + Uint16 GPIO34:1; // 2 Output Set bit for this pin + Uint16 GPIO35:1; // 3 Output Set bit for this pin + Uint16 GPIO36:1; // 4 Output Set bit for this pin + Uint16 GPIO37:1; // 5 Output Set bit for this pin + Uint16 GPIO38:1; // 6 Output Set bit for this pin + Uint16 GPIO39:1; // 7 Output Set bit for this pin + Uint16 GPIO40:1; // 8 Output Set bit for this pin + Uint16 GPIO41:1; // 9 Output Set bit for this pin + Uint16 GPIO42:1; // 10 Output Set bit for this pin + Uint16 GPIO43:1; // 11 Output Set bit for this pin + Uint16 GPIO44:1; // 12 Output Set bit for this pin + Uint16 GPIO45:1; // 13 Output Set bit for this pin + Uint16 GPIO46:1; // 14 Output Set bit for this pin + Uint16 GPIO47:1; // 15 Output Set bit for this pin + Uint16 GPIO48:1; // 16 Output Set bit for this pin + Uint16 GPIO49:1; // 17 Output Set bit for this pin + Uint16 GPIO50:1; // 18 Output Set bit for this pin + Uint16 GPIO51:1; // 19 Output Set bit for this pin + Uint16 GPIO52:1; // 20 Output Set bit for this pin + Uint16 GPIO53:1; // 21 Output Set bit for this pin + Uint16 GPIO54:1; // 22 Output Set bit for this pin + Uint16 GPIO55:1; // 23 Output Set bit for this pin + Uint16 GPIO56:1; // 24 Output Set bit for this pin + Uint16 GPIO57:1; // 25 Output Set bit for this pin + Uint16 GPIO58:1; // 26 Output Set bit for this pin + Uint16 GPIO59:1; // 27 Output Set bit for this pin + Uint16 GPIO60:1; // 28 Output Set bit for this pin + Uint16 GPIO61:1; // 29 Output Set bit for this pin + Uint16 GPIO62:1; // 30 Output Set bit for this pin + Uint16 GPIO63:1; // 31 Output Set bit for this pin +}; + +union GPBSET_REG { + Uint32 all; + struct GPBSET_BITS bit; +}; + +struct GPBCLEAR_BITS { // bits description + Uint16 GPIO32:1; // 0 Output Clear bit for this pin + Uint16 GPIO33:1; // 1 Output Clear bit for this pin + Uint16 GPIO34:1; // 2 Output Clear bit for this pin + Uint16 GPIO35:1; // 3 Output Clear bit for this pin + Uint16 GPIO36:1; // 4 Output Clear bit for this pin + Uint16 GPIO37:1; // 5 Output Clear bit for this pin + Uint16 GPIO38:1; // 6 Output Clear bit for this pin + Uint16 GPIO39:1; // 7 Output Clear bit for this pin + Uint16 GPIO40:1; // 8 Output Clear bit for this pin + Uint16 GPIO41:1; // 9 Output Clear bit for this pin + Uint16 GPIO42:1; // 10 Output Clear bit for this pin + Uint16 GPIO43:1; // 11 Output Clear bit for this pin + Uint16 GPIO44:1; // 12 Output Clear bit for this pin + Uint16 GPIO45:1; // 13 Output Clear bit for this pin + Uint16 GPIO46:1; // 14 Output Clear bit for this pin + Uint16 GPIO47:1; // 15 Output Clear bit for this pin + Uint16 GPIO48:1; // 16 Output Clear bit for this pin + Uint16 GPIO49:1; // 17 Output Clear bit for this pin + Uint16 GPIO50:1; // 18 Output Clear bit for this pin + Uint16 GPIO51:1; // 19 Output Clear bit for this pin + Uint16 GPIO52:1; // 20 Output Clear bit for this pin + Uint16 GPIO53:1; // 21 Output Clear bit for this pin + Uint16 GPIO54:1; // 22 Output Clear bit for this pin + Uint16 GPIO55:1; // 23 Output Clear bit for this pin + Uint16 GPIO56:1; // 24 Output Clear bit for this pin + Uint16 GPIO57:1; // 25 Output Clear bit for this pin + Uint16 GPIO58:1; // 26 Output Clear bit for this pin + Uint16 GPIO59:1; // 27 Output Clear bit for this pin + Uint16 GPIO60:1; // 28 Output Clear bit for this pin + Uint16 GPIO61:1; // 29 Output Clear bit for this pin + Uint16 GPIO62:1; // 30 Output Clear bit for this pin + Uint16 GPIO63:1; // 31 Output Clear bit for this pin +}; + +union GPBCLEAR_REG { + Uint32 all; + struct GPBCLEAR_BITS bit; +}; + +struct GPBTOGGLE_BITS { // bits description + Uint16 GPIO32:1; // 0 Output Toggle bit for this pin + Uint16 GPIO33:1; // 1 Output Toggle bit for this pin + Uint16 GPIO34:1; // 2 Output Toggle bit for this pin + Uint16 GPIO35:1; // 3 Output Toggle bit for this pin + Uint16 GPIO36:1; // 4 Output Toggle bit for this pin + Uint16 GPIO37:1; // 5 Output Toggle bit for this pin + Uint16 GPIO38:1; // 6 Output Toggle bit for this pin + Uint16 GPIO39:1; // 7 Output Toggle bit for this pin + Uint16 GPIO40:1; // 8 Output Toggle bit for this pin + Uint16 GPIO41:1; // 9 Output Toggle bit for this pin + Uint16 GPIO42:1; // 10 Output Toggle bit for this pin + Uint16 GPIO43:1; // 11 Output Toggle bit for this pin + Uint16 GPIO44:1; // 12 Output Toggle bit for this pin + Uint16 GPIO45:1; // 13 Output Toggle bit for this pin + Uint16 GPIO46:1; // 14 Output Toggle bit for this pin + Uint16 GPIO47:1; // 15 Output Toggle bit for this pin + Uint16 GPIO48:1; // 16 Output Toggle bit for this pin + Uint16 GPIO49:1; // 17 Output Toggle bit for this pin + Uint16 GPIO50:1; // 18 Output Toggle bit for this pin + Uint16 GPIO51:1; // 19 Output Toggle bit for this pin + Uint16 GPIO52:1; // 20 Output Toggle bit for this pin + Uint16 GPIO53:1; // 21 Output Toggle bit for this pin + Uint16 GPIO54:1; // 22 Output Toggle bit for this pin + Uint16 GPIO55:1; // 23 Output Toggle bit for this pin + Uint16 GPIO56:1; // 24 Output Toggle bit for this pin + Uint16 GPIO57:1; // 25 Output Toggle bit for this pin + Uint16 GPIO58:1; // 26 Output Toggle bit for this pin + Uint16 GPIO59:1; // 27 Output Toggle bit for this pin + Uint16 GPIO60:1; // 28 Output Toggle bit for this pin + Uint16 GPIO61:1; // 29 Output Toggle bit for this pin + Uint16 GPIO62:1; // 30 Output Toggle bit for this pin + Uint16 GPIO63:1; // 31 Output Toggle bit for this pin +}; + +union GPBTOGGLE_REG { + Uint32 all; + struct GPBTOGGLE_BITS bit; +}; + +struct GPCDAT_BITS { // bits description + Uint16 GPIO64:1; // 0 Data Register for this pin + Uint16 GPIO65:1; // 1 Data Register for this pin + Uint16 GPIO66:1; // 2 Data Register for this pin + Uint16 GPIO67:1; // 3 Data Register for this pin + Uint16 GPIO68:1; // 4 Data Register for this pin + Uint16 GPIO69:1; // 5 Data Register for this pin + Uint16 GPIO70:1; // 6 Data Register for this pin + Uint16 GPIO71:1; // 7 Data Register for this pin + Uint16 GPIO72:1; // 8 Data Register for this pin + Uint16 GPIO73:1; // 9 Data Register for this pin + Uint16 GPIO74:1; // 10 Data Register for this pin + Uint16 GPIO75:1; // 11 Data Register for this pin + Uint16 GPIO76:1; // 12 Data Register for this pin + Uint16 GPIO77:1; // 13 Data Register for this pin + Uint16 GPIO78:1; // 14 Data Register for this pin + Uint16 GPIO79:1; // 15 Data Register for this pin + Uint16 GPIO80:1; // 16 Data Register for this pin + Uint16 GPIO81:1; // 17 Data Register for this pin + Uint16 GPIO82:1; // 18 Data Register for this pin + Uint16 GPIO83:1; // 19 Data Register for this pin + Uint16 GPIO84:1; // 20 Data Register for this pin + Uint16 GPIO85:1; // 21 Data Register for this pin + Uint16 GPIO86:1; // 22 Data Register for this pin + Uint16 GPIO87:1; // 23 Data Register for this pin + Uint16 GPIO88:1; // 24 Data Register for this pin + Uint16 GPIO89:1; // 25 Data Register for this pin + Uint16 GPIO90:1; // 26 Data Register for this pin + Uint16 GPIO91:1; // 27 Data Register for this pin + Uint16 GPIO92:1; // 28 Data Register for this pin + Uint16 GPIO93:1; // 29 Data Register for this pin + Uint16 GPIO94:1; // 30 Data Register for this pin + Uint16 GPIO95:1; // 31 Data Register for this pin +}; + +union GPCDAT_REG { + Uint32 all; + struct GPCDAT_BITS bit; +}; + +struct GPCSET_BITS { // bits description + Uint16 GPIO64:1; // 0 Output Set bit for this pin + Uint16 GPIO65:1; // 1 Output Set bit for this pin + Uint16 GPIO66:1; // 2 Output Set bit for this pin + Uint16 GPIO67:1; // 3 Output Set bit for this pin + Uint16 GPIO68:1; // 4 Output Set bit for this pin + Uint16 GPIO69:1; // 5 Output Set bit for this pin + Uint16 GPIO70:1; // 6 Output Set bit for this pin + Uint16 GPIO71:1; // 7 Output Set bit for this pin + Uint16 GPIO72:1; // 8 Output Set bit for this pin + Uint16 GPIO73:1; // 9 Output Set bit for this pin + Uint16 GPIO74:1; // 10 Output Set bit for this pin + Uint16 GPIO75:1; // 11 Output Set bit for this pin + Uint16 GPIO76:1; // 12 Output Set bit for this pin + Uint16 GPIO77:1; // 13 Output Set bit for this pin + Uint16 GPIO78:1; // 14 Output Set bit for this pin + Uint16 GPIO79:1; // 15 Output Set bit for this pin + Uint16 GPIO80:1; // 16 Output Set bit for this pin + Uint16 GPIO81:1; // 17 Output Set bit for this pin + Uint16 GPIO82:1; // 18 Output Set bit for this pin + Uint16 GPIO83:1; // 19 Output Set bit for this pin + Uint16 GPIO84:1; // 20 Output Set bit for this pin + Uint16 GPIO85:1; // 21 Output Set bit for this pin + Uint16 GPIO86:1; // 22 Output Set bit for this pin + Uint16 GPIO87:1; // 23 Output Set bit for this pin + Uint16 GPIO88:1; // 24 Output Set bit for this pin + Uint16 GPIO89:1; // 25 Output Set bit for this pin + Uint16 GPIO90:1; // 26 Output Set bit for this pin + Uint16 GPIO91:1; // 27 Output Set bit for this pin + Uint16 GPIO92:1; // 28 Output Set bit for this pin + Uint16 GPIO93:1; // 29 Output Set bit for this pin + Uint16 GPIO94:1; // 30 Output Set bit for this pin + Uint16 GPIO95:1; // 31 Output Set bit for this pin +}; + +union GPCSET_REG { + Uint32 all; + struct GPCSET_BITS bit; +}; + +struct GPCCLEAR_BITS { // bits description + Uint16 GPIO64:1; // 0 Output Clear bit for this pin + Uint16 GPIO65:1; // 1 Output Clear bit for this pin + Uint16 GPIO66:1; // 2 Output Clear bit for this pin + Uint16 GPIO67:1; // 3 Output Clear bit for this pin + Uint16 GPIO68:1; // 4 Output Clear bit for this pin + Uint16 GPIO69:1; // 5 Output Clear bit for this pin + Uint16 GPIO70:1; // 6 Output Clear bit for this pin + Uint16 GPIO71:1; // 7 Output Clear bit for this pin + Uint16 GPIO72:1; // 8 Output Clear bit for this pin + Uint16 GPIO73:1; // 9 Output Clear bit for this pin + Uint16 GPIO74:1; // 10 Output Clear bit for this pin + Uint16 GPIO75:1; // 11 Output Clear bit for this pin + Uint16 GPIO76:1; // 12 Output Clear bit for this pin + Uint16 GPIO77:1; // 13 Output Clear bit for this pin + Uint16 GPIO78:1; // 14 Output Clear bit for this pin + Uint16 GPIO79:1; // 15 Output Clear bit for this pin + Uint16 GPIO80:1; // 16 Output Clear bit for this pin + Uint16 GPIO81:1; // 17 Output Clear bit for this pin + Uint16 GPIO82:1; // 18 Output Clear bit for this pin + Uint16 GPIO83:1; // 19 Output Clear bit for this pin + Uint16 GPIO84:1; // 20 Output Clear bit for this pin + Uint16 GPIO85:1; // 21 Output Clear bit for this pin + Uint16 GPIO86:1; // 22 Output Clear bit for this pin + Uint16 GPIO87:1; // 23 Output Clear bit for this pin + Uint16 GPIO88:1; // 24 Output Clear bit for this pin + Uint16 GPIO89:1; // 25 Output Clear bit for this pin + Uint16 GPIO90:1; // 26 Output Clear bit for this pin + Uint16 GPIO91:1; // 27 Output Clear bit for this pin + Uint16 GPIO92:1; // 28 Output Clear bit for this pin + Uint16 GPIO93:1; // 29 Output Clear bit for this pin + Uint16 GPIO94:1; // 30 Output Clear bit for this pin + Uint16 GPIO95:1; // 31 Output Clear bit for this pin +}; + +union GPCCLEAR_REG { + Uint32 all; + struct GPCCLEAR_BITS bit; +}; + +struct GPCTOGGLE_BITS { // bits description + Uint16 GPIO64:1; // 0 Output Toggle bit for this pin + Uint16 GPIO65:1; // 1 Output Toggle bit for this pin + Uint16 GPIO66:1; // 2 Output Toggle bit for this pin + Uint16 GPIO67:1; // 3 Output Toggle bit for this pin + Uint16 GPIO68:1; // 4 Output Toggle bit for this pin + Uint16 GPIO69:1; // 5 Output Toggle bit for this pin + Uint16 GPIO70:1; // 6 Output Toggle bit for this pin + Uint16 GPIO71:1; // 7 Output Toggle bit for this pin + Uint16 GPIO72:1; // 8 Output Toggle bit for this pin + Uint16 GPIO73:1; // 9 Output Toggle bit for this pin + Uint16 GPIO74:1; // 10 Output Toggle bit for this pin + Uint16 GPIO75:1; // 11 Output Toggle bit for this pin + Uint16 GPIO76:1; // 12 Output Toggle bit for this pin + Uint16 GPIO77:1; // 13 Output Toggle bit for this pin + Uint16 GPIO78:1; // 14 Output Toggle bit for this pin + Uint16 GPIO79:1; // 15 Output Toggle bit for this pin + Uint16 GPIO80:1; // 16 Output Toggle bit for this pin + Uint16 GPIO81:1; // 17 Output Toggle bit for this pin + Uint16 GPIO82:1; // 18 Output Toggle bit for this pin + Uint16 GPIO83:1; // 19 Output Toggle bit for this pin + Uint16 GPIO84:1; // 20 Output Toggle bit for this pin + Uint16 GPIO85:1; // 21 Output Toggle bit for this pin + Uint16 GPIO86:1; // 22 Output Toggle bit for this pin + Uint16 GPIO87:1; // 23 Output Toggle bit for this pin + Uint16 GPIO88:1; // 24 Output Toggle bit for this pin + Uint16 GPIO89:1; // 25 Output Toggle bit for this pin + Uint16 GPIO90:1; // 26 Output Toggle bit for this pin + Uint16 GPIO91:1; // 27 Output Toggle bit for this pin + Uint16 GPIO92:1; // 28 Output Toggle bit for this pin + Uint16 GPIO93:1; // 29 Output Toggle bit for this pin + Uint16 GPIO94:1; // 30 Output Toggle bit for this pin + Uint16 GPIO95:1; // 31 Output Toggle bit for this pin +}; + +union GPCTOGGLE_REG { + Uint32 all; + struct GPCTOGGLE_BITS bit; +}; + +struct GPDDAT_BITS { // bits description + Uint16 GPIO96:1; // 0 Data Register for this pin + Uint16 GPIO97:1; // 1 Data Register for this pin + Uint16 GPIO98:1; // 2 Data Register for this pin + Uint16 GPIO99:1; // 3 Data Register for this pin + Uint16 GPIO100:1; // 4 Data Register for this pin + Uint16 GPIO101:1; // 5 Data Register for this pin + Uint16 GPIO102:1; // 6 Data Register for this pin + Uint16 GPIO103:1; // 7 Data Register for this pin + Uint16 GPIO104:1; // 8 Data Register for this pin + Uint16 GPIO105:1; // 9 Data Register for this pin + Uint16 GPIO106:1; // 10 Data Register for this pin + Uint16 GPIO107:1; // 11 Data Register for this pin + Uint16 GPIO108:1; // 12 Data Register for this pin + Uint16 GPIO109:1; // 13 Data Register for this pin + Uint16 GPIO110:1; // 14 Data Register for this pin + Uint16 GPIO111:1; // 15 Data Register for this pin + Uint16 GPIO112:1; // 16 Data Register for this pin + Uint16 GPIO113:1; // 17 Data Register for this pin + Uint16 GPIO114:1; // 18 Data Register for this pin + Uint16 GPIO115:1; // 19 Data Register for this pin + Uint16 GPIO116:1; // 20 Data Register for this pin + Uint16 GPIO117:1; // 21 Data Register for this pin + Uint16 GPIO118:1; // 22 Data Register for this pin + Uint16 GPIO119:1; // 23 Data Register for this pin + Uint16 GPIO120:1; // 24 Data Register for this pin + Uint16 GPIO121:1; // 25 Data Register for this pin + Uint16 GPIO122:1; // 26 Data Register for this pin + Uint16 GPIO123:1; // 27 Data Register for this pin + Uint16 GPIO124:1; // 28 Data Register for this pin + Uint16 GPIO125:1; // 29 Data Register for this pin + Uint16 GPIO126:1; // 30 Data Register for this pin + Uint16 GPIO127:1; // 31 Data Register for this pin +}; + +union GPDDAT_REG { + Uint32 all; + struct GPDDAT_BITS bit; +}; + +struct GPDSET_BITS { // bits description + Uint16 GPIO96:1; // 0 Output Set bit for this pin + Uint16 GPIO97:1; // 1 Output Set bit for this pin + Uint16 GPIO98:1; // 2 Output Set bit for this pin + Uint16 GPIO99:1; // 3 Output Set bit for this pin + Uint16 GPIO100:1; // 4 Output Set bit for this pin + Uint16 GPIO101:1; // 5 Output Set bit for this pin + Uint16 GPIO102:1; // 6 Output Set bit for this pin + Uint16 GPIO103:1; // 7 Output Set bit for this pin + Uint16 GPIO104:1; // 8 Output Set bit for this pin + Uint16 GPIO105:1; // 9 Output Set bit for this pin + Uint16 GPIO106:1; // 10 Output Set bit for this pin + Uint16 GPIO107:1; // 11 Output Set bit for this pin + Uint16 GPIO108:1; // 12 Output Set bit for this pin + Uint16 GPIO109:1; // 13 Output Set bit for this pin + Uint16 GPIO110:1; // 14 Output Set bit for this pin + Uint16 GPIO111:1; // 15 Output Set bit for this pin + Uint16 GPIO112:1; // 16 Output Set bit for this pin + Uint16 GPIO113:1; // 17 Output Set bit for this pin + Uint16 GPIO114:1; // 18 Output Set bit for this pin + Uint16 GPIO115:1; // 19 Output Set bit for this pin + Uint16 GPIO116:1; // 20 Output Set bit for this pin + Uint16 GPIO117:1; // 21 Output Set bit for this pin + Uint16 GPIO118:1; // 22 Output Set bit for this pin + Uint16 GPIO119:1; // 23 Output Set bit for this pin + Uint16 GPIO120:1; // 24 Output Set bit for this pin + Uint16 GPIO121:1; // 25 Output Set bit for this pin + Uint16 GPIO122:1; // 26 Output Set bit for this pin + Uint16 GPIO123:1; // 27 Output Set bit for this pin + Uint16 GPIO124:1; // 28 Output Set bit for this pin + Uint16 GPIO125:1; // 29 Output Set bit for this pin + Uint16 GPIO126:1; // 30 Output Set bit for this pin + Uint16 GPIO127:1; // 31 Output Set bit for this pin +}; + +union GPDSET_REG { + Uint32 all; + struct GPDSET_BITS bit; +}; + +struct GPDCLEAR_BITS { // bits description + Uint16 GPIO96:1; // 0 Output Clear bit for this pin + Uint16 GPIO97:1; // 1 Output Clear bit for this pin + Uint16 GPIO98:1; // 2 Output Clear bit for this pin + Uint16 GPIO99:1; // 3 Output Clear bit for this pin + Uint16 GPIO100:1; // 4 Output Clear bit for this pin + Uint16 GPIO101:1; // 5 Output Clear bit for this pin + Uint16 GPIO102:1; // 6 Output Clear bit for this pin + Uint16 GPIO103:1; // 7 Output Clear bit for this pin + Uint16 GPIO104:1; // 8 Output Clear bit for this pin + Uint16 GPIO105:1; // 9 Output Clear bit for this pin + Uint16 GPIO106:1; // 10 Output Clear bit for this pin + Uint16 GPIO107:1; // 11 Output Clear bit for this pin + Uint16 GPIO108:1; // 12 Output Clear bit for this pin + Uint16 GPIO109:1; // 13 Output Clear bit for this pin + Uint16 GPIO110:1; // 14 Output Clear bit for this pin + Uint16 GPIO111:1; // 15 Output Clear bit for this pin + Uint16 GPIO112:1; // 16 Output Clear bit for this pin + Uint16 GPIO113:1; // 17 Output Clear bit for this pin + Uint16 GPIO114:1; // 18 Output Clear bit for this pin + Uint16 GPIO115:1; // 19 Output Clear bit for this pin + Uint16 GPIO116:1; // 20 Output Clear bit for this pin + Uint16 GPIO117:1; // 21 Output Clear bit for this pin + Uint16 GPIO118:1; // 22 Output Clear bit for this pin + Uint16 GPIO119:1; // 23 Output Clear bit for this pin + Uint16 GPIO120:1; // 24 Output Clear bit for this pin + Uint16 GPIO121:1; // 25 Output Clear bit for this pin + Uint16 GPIO122:1; // 26 Output Clear bit for this pin + Uint16 GPIO123:1; // 27 Output Clear bit for this pin + Uint16 GPIO124:1; // 28 Output Clear bit for this pin + Uint16 GPIO125:1; // 29 Output Clear bit for this pin + Uint16 GPIO126:1; // 30 Output Clear bit for this pin + Uint16 GPIO127:1; // 31 Output Clear bit for this pin +}; + +union GPDCLEAR_REG { + Uint32 all; + struct GPDCLEAR_BITS bit; +}; + +struct GPDTOGGLE_BITS { // bits description + Uint16 GPIO96:1; // 0 Output Toggle bit for this pin + Uint16 GPIO97:1; // 1 Output Toggle bit for this pin + Uint16 GPIO98:1; // 2 Output Toggle bit for this pin + Uint16 GPIO99:1; // 3 Output Toggle bit for this pin + Uint16 GPIO100:1; // 4 Output Toggle bit for this pin + Uint16 GPIO101:1; // 5 Output Toggle bit for this pin + Uint16 GPIO102:1; // 6 Output Toggle bit for this pin + Uint16 GPIO103:1; // 7 Output Toggle bit for this pin + Uint16 GPIO104:1; // 8 Output Toggle bit for this pin + Uint16 GPIO105:1; // 9 Output Toggle bit for this pin + Uint16 GPIO106:1; // 10 Output Toggle bit for this pin + Uint16 GPIO107:1; // 11 Output Toggle bit for this pin + Uint16 GPIO108:1; // 12 Output Toggle bit for this pin + Uint16 GPIO109:1; // 13 Output Toggle bit for this pin + Uint16 GPIO110:1; // 14 Output Toggle bit for this pin + Uint16 GPIO111:1; // 15 Output Toggle bit for this pin + Uint16 GPIO112:1; // 16 Output Toggle bit for this pin + Uint16 GPIO113:1; // 17 Output Toggle bit for this pin + Uint16 GPIO114:1; // 18 Output Toggle bit for this pin + Uint16 GPIO115:1; // 19 Output Toggle bit for this pin + Uint16 GPIO116:1; // 20 Output Toggle bit for this pin + Uint16 GPIO117:1; // 21 Output Toggle bit for this pin + Uint16 GPIO118:1; // 22 Output Toggle bit for this pin + Uint16 GPIO119:1; // 23 Output Toggle bit for this pin + Uint16 GPIO120:1; // 24 Output Toggle bit for this pin + Uint16 GPIO121:1; // 25 Output Toggle bit for this pin + Uint16 GPIO122:1; // 26 Output Toggle bit for this pin + Uint16 GPIO123:1; // 27 Output Toggle bit for this pin + Uint16 GPIO124:1; // 28 Output Toggle bit for this pin + Uint16 GPIO125:1; // 29 Output Toggle bit for this pin + Uint16 GPIO126:1; // 30 Output Toggle bit for this pin + Uint16 GPIO127:1; // 31 Output Toggle bit for this pin +}; + +union GPDTOGGLE_REG { + Uint32 all; + struct GPDTOGGLE_BITS bit; +}; + +struct GPEDAT_BITS { // bits description + Uint16 GPIO128:1; // 0 Data Register for this pin + Uint16 GPIO129:1; // 1 Data Register for this pin + Uint16 GPIO130:1; // 2 Data Register for this pin + Uint16 GPIO131:1; // 3 Data Register for this pin + Uint16 GPIO132:1; // 4 Data Register for this pin + Uint16 GPIO133:1; // 5 Data Register for this pin + Uint16 GPIO134:1; // 6 Data Register for this pin + Uint16 GPIO135:1; // 7 Data Register for this pin + Uint16 GPIO136:1; // 8 Data Register for this pin + Uint16 GPIO137:1; // 9 Data Register for this pin + Uint16 GPIO138:1; // 10 Data Register for this pin + Uint16 GPIO139:1; // 11 Data Register for this pin + Uint16 GPIO140:1; // 12 Data Register for this pin + Uint16 GPIO141:1; // 13 Data Register for this pin + Uint16 GPIO142:1; // 14 Data Register for this pin + Uint16 GPIO143:1; // 15 Data Register for this pin + Uint16 GPIO144:1; // 16 Data Register for this pin + Uint16 GPIO145:1; // 17 Data Register for this pin + Uint16 GPIO146:1; // 18 Data Register for this pin + Uint16 GPIO147:1; // 19 Data Register for this pin + Uint16 GPIO148:1; // 20 Data Register for this pin + Uint16 GPIO149:1; // 21 Data Register for this pin + Uint16 GPIO150:1; // 22 Data Register for this pin + Uint16 GPIO151:1; // 23 Data Register for this pin + Uint16 GPIO152:1; // 24 Data Register for this pin + Uint16 GPIO153:1; // 25 Data Register for this pin + Uint16 GPIO154:1; // 26 Data Register for this pin + Uint16 GPIO155:1; // 27 Data Register for this pin + Uint16 GPIO156:1; // 28 Data Register for this pin + Uint16 GPIO157:1; // 29 Data Register for this pin + Uint16 GPIO158:1; // 30 Data Register for this pin + Uint16 GPIO159:1; // 31 Data Register for this pin +}; + +union GPEDAT_REG { + Uint32 all; + struct GPEDAT_BITS bit; +}; + +struct GPESET_BITS { // bits description + Uint16 GPIO128:1; // 0 Output Set bit for this pin + Uint16 GPIO129:1; // 1 Output Set bit for this pin + Uint16 GPIO130:1; // 2 Output Set bit for this pin + Uint16 GPIO131:1; // 3 Output Set bit for this pin + Uint16 GPIO132:1; // 4 Output Set bit for this pin + Uint16 GPIO133:1; // 5 Output Set bit for this pin + Uint16 GPIO134:1; // 6 Output Set bit for this pin + Uint16 GPIO135:1; // 7 Output Set bit for this pin + Uint16 GPIO136:1; // 8 Output Set bit for this pin + Uint16 GPIO137:1; // 9 Output Set bit for this pin + Uint16 GPIO138:1; // 10 Output Set bit for this pin + Uint16 GPIO139:1; // 11 Output Set bit for this pin + Uint16 GPIO140:1; // 12 Output Set bit for this pin + Uint16 GPIO141:1; // 13 Output Set bit for this pin + Uint16 GPIO142:1; // 14 Output Set bit for this pin + Uint16 GPIO143:1; // 15 Output Set bit for this pin + Uint16 GPIO144:1; // 16 Output Set bit for this pin + Uint16 GPIO145:1; // 17 Output Set bit for this pin + Uint16 GPIO146:1; // 18 Output Set bit for this pin + Uint16 GPIO147:1; // 19 Output Set bit for this pin + Uint16 GPIO148:1; // 20 Output Set bit for this pin + Uint16 GPIO149:1; // 21 Output Set bit for this pin + Uint16 GPIO150:1; // 22 Output Set bit for this pin + Uint16 GPIO151:1; // 23 Output Set bit for this pin + Uint16 GPIO152:1; // 24 Output Set bit for this pin + Uint16 GPIO153:1; // 25 Output Set bit for this pin + Uint16 GPIO154:1; // 26 Output Set bit for this pin + Uint16 GPIO155:1; // 27 Output Set bit for this pin + Uint16 GPIO156:1; // 28 Output Set bit for this pin + Uint16 GPIO157:1; // 29 Output Set bit for this pin + Uint16 GPIO158:1; // 30 Output Set bit for this pin + Uint16 GPIO159:1; // 31 Output Set bit for this pin +}; + +union GPESET_REG { + Uint32 all; + struct GPESET_BITS bit; +}; + +struct GPECLEAR_BITS { // bits description + Uint16 GPIO128:1; // 0 Output Clear bit for this pin + Uint16 GPIO129:1; // 1 Output Clear bit for this pin + Uint16 GPIO130:1; // 2 Output Clear bit for this pin + Uint16 GPIO131:1; // 3 Output Clear bit for this pin + Uint16 GPIO132:1; // 4 Output Clear bit for this pin + Uint16 GPIO133:1; // 5 Output Clear bit for this pin + Uint16 GPIO134:1; // 6 Output Clear bit for this pin + Uint16 GPIO135:1; // 7 Output Clear bit for this pin + Uint16 GPIO136:1; // 8 Output Clear bit for this pin + Uint16 GPIO137:1; // 9 Output Clear bit for this pin + Uint16 GPIO138:1; // 10 Output Clear bit for this pin + Uint16 GPIO139:1; // 11 Output Clear bit for this pin + Uint16 GPIO140:1; // 12 Output Clear bit for this pin + Uint16 GPIO141:1; // 13 Output Clear bit for this pin + Uint16 GPIO142:1; // 14 Output Clear bit for this pin + Uint16 GPIO143:1; // 15 Output Clear bit for this pin + Uint16 GPIO144:1; // 16 Output Clear bit for this pin + Uint16 GPIO145:1; // 17 Output Clear bit for this pin + Uint16 GPIO146:1; // 18 Output Clear bit for this pin + Uint16 GPIO147:1; // 19 Output Clear bit for this pin + Uint16 GPIO148:1; // 20 Output Clear bit for this pin + Uint16 GPIO149:1; // 21 Output Clear bit for this pin + Uint16 GPIO150:1; // 22 Output Clear bit for this pin + Uint16 GPIO151:1; // 23 Output Clear bit for this pin + Uint16 GPIO152:1; // 24 Output Clear bit for this pin + Uint16 GPIO153:1; // 25 Output Clear bit for this pin + Uint16 GPIO154:1; // 26 Output Clear bit for this pin + Uint16 GPIO155:1; // 27 Output Clear bit for this pin + Uint16 GPIO156:1; // 28 Output Clear bit for this pin + Uint16 GPIO157:1; // 29 Output Clear bit for this pin + Uint16 GPIO158:1; // 30 Output Clear bit for this pin + Uint16 GPIO159:1; // 31 Output Clear bit for this pin +}; + +union GPECLEAR_REG { + Uint32 all; + struct GPECLEAR_BITS bit; +}; + +struct GPETOGGLE_BITS { // bits description + Uint16 GPIO128:1; // 0 Output Toggle bit for this pin + Uint16 GPIO129:1; // 1 Output Toggle bit for this pin + Uint16 GPIO130:1; // 2 Output Toggle bit for this pin + Uint16 GPIO131:1; // 3 Output Toggle bit for this pin + Uint16 GPIO132:1; // 4 Output Toggle bit for this pin + Uint16 GPIO133:1; // 5 Output Toggle bit for this pin + Uint16 GPIO134:1; // 6 Output Toggle bit for this pin + Uint16 GPIO135:1; // 7 Output Toggle bit for this pin + Uint16 GPIO136:1; // 8 Output Toggle bit for this pin + Uint16 GPIO137:1; // 9 Output Toggle bit for this pin + Uint16 GPIO138:1; // 10 Output Toggle bit for this pin + Uint16 GPIO139:1; // 11 Output Toggle bit for this pin + Uint16 GPIO140:1; // 12 Output Toggle bit for this pin + Uint16 GPIO141:1; // 13 Output Toggle bit for this pin + Uint16 GPIO142:1; // 14 Output Toggle bit for this pin + Uint16 GPIO143:1; // 15 Output Toggle bit for this pin + Uint16 GPIO144:1; // 16 Output Toggle bit for this pin + Uint16 GPIO145:1; // 17 Output Toggle bit for this pin + Uint16 GPIO146:1; // 18 Output Toggle bit for this pin + Uint16 GPIO147:1; // 19 Output Toggle bit for this pin + Uint16 GPIO148:1; // 20 Output Toggle bit for this pin + Uint16 GPIO149:1; // 21 Output Toggle bit for this pin + Uint16 GPIO150:1; // 22 Output Toggle bit for this pin + Uint16 GPIO151:1; // 23 Output Toggle bit for this pin + Uint16 GPIO152:1; // 24 Output Toggle bit for this pin + Uint16 GPIO153:1; // 25 Output Toggle bit for this pin + Uint16 GPIO154:1; // 26 Output Toggle bit for this pin + Uint16 GPIO155:1; // 27 Output Toggle bit for this pin + Uint16 GPIO156:1; // 28 Output Toggle bit for this pin + Uint16 GPIO157:1; // 29 Output Toggle bit for this pin + Uint16 GPIO158:1; // 30 Output Toggle bit for this pin + Uint16 GPIO159:1; // 31 Output Toggle bit for this pin +}; + +union GPETOGGLE_REG { + Uint32 all; + struct GPETOGGLE_BITS bit; +}; + +struct GPFDAT_BITS { // bits description + Uint16 GPIO160:1; // 0 Data Register for this pin + Uint16 GPIO161:1; // 1 Data Register for this pin + Uint16 GPIO162:1; // 2 Data Register for this pin + Uint16 GPIO163:1; // 3 Data Register for this pin + Uint16 GPIO164:1; // 4 Data Register for this pin + Uint16 GPIO165:1; // 5 Data Register for this pin + Uint16 GPIO166:1; // 6 Data Register for this pin + Uint16 GPIO167:1; // 7 Data Register for this pin + Uint16 GPIO168:1; // 8 Data Register for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFDAT_REG { + Uint32 all; + struct GPFDAT_BITS bit; +}; + +struct GPFSET_BITS { // bits description + Uint16 GPIO160:1; // 0 Output Set bit for this pin + Uint16 GPIO161:1; // 1 Output Set bit for this pin + Uint16 GPIO162:1; // 2 Output Set bit for this pin + Uint16 GPIO163:1; // 3 Output Set bit for this pin + Uint16 GPIO164:1; // 4 Output Set bit for this pin + Uint16 GPIO165:1; // 5 Output Set bit for this pin + Uint16 GPIO166:1; // 6 Output Set bit for this pin + Uint16 GPIO167:1; // 7 Output Set bit for this pin + Uint16 GPIO168:1; // 8 Output Set bit for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFSET_REG { + Uint32 all; + struct GPFSET_BITS bit; +}; + +struct GPFCLEAR_BITS { // bits description + Uint16 GPIO160:1; // 0 Output Clear bit for this pin + Uint16 GPIO161:1; // 1 Output Clear bit for this pin + Uint16 GPIO162:1; // 2 Output Clear bit for this pin + Uint16 GPIO163:1; // 3 Output Clear bit for this pin + Uint16 GPIO164:1; // 4 Output Clear bit for this pin + Uint16 GPIO165:1; // 5 Output Clear bit for this pin + Uint16 GPIO166:1; // 6 Output Clear bit for this pin + Uint16 GPIO167:1; // 7 Output Clear bit for this pin + Uint16 GPIO168:1; // 8 Output Clear bit for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFCLEAR_REG { + Uint32 all; + struct GPFCLEAR_BITS bit; +}; + +struct GPFTOGGLE_BITS { // bits description + Uint16 GPIO160:1; // 0 Output Toggle bit for this pin + Uint16 GPIO161:1; // 1 Output Toggle bit for this pin + Uint16 GPIO162:1; // 2 Output Toggle bit for this pin + Uint16 GPIO163:1; // 3 Output Toggle bit for this pin + Uint16 GPIO164:1; // 4 Output Toggle bit for this pin + Uint16 GPIO165:1; // 5 Output Toggle bit for this pin + Uint16 GPIO166:1; // 6 Output Toggle bit for this pin + Uint16 GPIO167:1; // 7 Output Toggle bit for this pin + Uint16 GPIO168:1; // 8 Output Toggle bit for this pin + Uint16 rsvd1:1; // 9 Reserved + Uint16 rsvd2:1; // 10 Reserved + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:1; // 12 Reserved + Uint16 rsvd5:1; // 13 Reserved + Uint16 rsvd6:1; // 14 Reserved + Uint16 rsvd7:1; // 15 Reserved + Uint16 rsvd8:1; // 16 Reserved + Uint16 rsvd9:1; // 17 Reserved + Uint16 rsvd10:1; // 18 Reserved + Uint16 rsvd11:1; // 19 Reserved + Uint16 rsvd12:1; // 20 Reserved + Uint16 rsvd13:1; // 21 Reserved + Uint16 rsvd14:1; // 22 Reserved + Uint16 rsvd15:1; // 23 Reserved + Uint16 rsvd16:1; // 24 Reserved + Uint16 rsvd17:1; // 25 Reserved + Uint16 rsvd18:1; // 26 Reserved + Uint16 rsvd19:1; // 27 Reserved + Uint16 rsvd20:1; // 28 Reserved + Uint16 rsvd21:1; // 29 Reserved + Uint16 rsvd22:1; // 30 Reserved + Uint16 rsvd23:1; // 31 Reserved +}; + +union GPFTOGGLE_REG { + Uint32 all; + struct GPFTOGGLE_BITS bit; +}; + +struct GPIO_DATA_REGS { + union GPADAT_REG GPADAT; // GPIO A Data Register (GPIO0 to 31) + union GPASET_REG GPASET; // GPIO A Data Set Register (GPIO0 to 31) + union GPACLEAR_REG GPACLEAR; // GPIO A Data Clear Register (GPIO0 to 31) + union GPATOGGLE_REG GPATOGGLE; // GPIO A Data Toggle Register (GPIO0 to 31) + union GPBDAT_REG GPBDAT; // GPIO B Data Register (GPIO32 to 63) + union GPBSET_REG GPBSET; // GPIO B Data Set Register (GPIO32 to 63) + union GPBCLEAR_REG GPBCLEAR; // GPIO B Data Clear Register (GPIO32 to 63) + union GPBTOGGLE_REG GPBTOGGLE; // GPIO B Data Toggle Register (GPIO32 to 63) + union GPCDAT_REG GPCDAT; // GPIO C Data Register (GPIO64 to 95) + union GPCSET_REG GPCSET; // GPIO C Data Set Register (GPIO64 to 95) + union GPCCLEAR_REG GPCCLEAR; // GPIO C Data Clear Register (GPIO64 to 95) + union GPCTOGGLE_REG GPCTOGGLE; // GPIO C Data Toggle Register (GPIO64 to 95) + union GPDDAT_REG GPDDAT; // GPIO D Data Register (GPIO96 to 127) + union GPDSET_REG GPDSET; // GPIO D Data Set Register (GPIO96 to 127) + union GPDCLEAR_REG GPDCLEAR; // GPIO D Data Clear Register (GPIO96 to 127) + union GPDTOGGLE_REG GPDTOGGLE; // GPIO D Data Toggle Register (GPIO96 to 127) + union GPEDAT_REG GPEDAT; // GPIO E Data Register (GPIO128 to 159) + union GPESET_REG GPESET; // GPIO E Data Set Register (GPIO128 to 159) + union GPECLEAR_REG GPECLEAR; // GPIO E Data Clear Register (GPIO128 to 159) + union GPETOGGLE_REG GPETOGGLE; // GPIO E Data Toggle Register (GPIO128 to 159) + union GPFDAT_REG GPFDAT; // GPIO F Data Register (GPIO160 to 168) + union GPFSET_REG GPFSET; // GPIO F Data Set Register (GPIO160 to 168) + union GPFCLEAR_REG GPFCLEAR; // GPIO F Data Clear Register (GPIO160 to 168) + union GPFTOGGLE_REG GPFTOGGLE; // GPIO F Data Toggle Register (GPIO160 to 168) +}; + +//--------------------------------------------------------------------------- +// GPIO External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +#endif +#ifdef CPU2 +extern volatile struct GPIO_DATA_REGS GpioDataRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_i2c.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_i2c.h new file mode 100644 index 0000000000..470f5a398d --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_i2c.h @@ -0,0 +1,256 @@ +//########################################################################### +// +// FILE: F2837xD_i2c.h +// +// TITLE: I2C Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_I2C_H__ +#define __F2837xD_I2C_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// I2C Individual Register Bit Definitions: + +struct I2COAR_BITS { // bits description + Uint16 OAR:10; // 9:0 I2C Own address + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union I2COAR_REG { + Uint16 all; + struct I2COAR_BITS bit; +}; + +struct I2CIER_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration-lost interrupt enable + Uint16 NACK:1; // 1 No-acknowledgment interrupt enable + Uint16 ARDY:1; // 2 Register-access-ready interrupt enable + Uint16 RRDY:1; // 3 Receive-data-ready interrupt enable + Uint16 XRDY:1; // 4 Transmit-data-ready interrupt enable + Uint16 SCD:1; // 5 Stop condition detected interrupt enable + Uint16 AAS:1; // 6 Addressed as slave interrupt enable + Uint16 rsvd1:9; // 15:7 Reserved +}; + +union I2CIER_REG { + Uint16 all; + struct I2CIER_BITS bit; +}; + +struct I2CSTR_BITS { // bits description + Uint16 ARBL:1; // 0 Arbitration-lost interrupt flag bit + Uint16 NACK:1; // 1 No-acknowledgment interrupt flag bit. + Uint16 ARDY:1; // 2 Register-access-ready interrupt flag bit + Uint16 RRDY:1; // 3 Receive-data-ready interrupt flag bit. + Uint16 XRDY:1; // 4 Transmit-data-ready interrupt flag bit. + Uint16 SCD:1; // 5 Stop condition detected bit. + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 AD0:1; // 8 Address 0 bits + Uint16 AAS:1; // 9 Addressed-as-slave bit + Uint16 XSMT:1; // 10 Transmit shift register empty bit. + Uint16 RSFULL:1; // 11 Receive shift register full bit. + Uint16 BB:1; // 12 Bus busy bit. + Uint16 NACKSNT:1; // 13 NACK sent bit. + Uint16 SDIR:1; // 14 Slave direction bit + Uint16 rsvd2:1; // 15 Reserved +}; + +union I2CSTR_REG { + Uint16 all; + struct I2CSTR_BITS bit; +}; + +struct I2CDRR_BITS { // bits description + Uint16 DATA:8; // 7:0 Receive data + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union I2CDRR_REG { + Uint16 all; + struct I2CDRR_BITS bit; +}; + +struct I2CSAR_BITS { // bits description + Uint16 SAR:10; // 9:0 Slave Address + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union I2CSAR_REG { + Uint16 all; + struct I2CSAR_BITS bit; +}; + +struct I2CDXR_BITS { // bits description + Uint16 DATA:8; // 7:0 Transmit data + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union I2CDXR_REG { + Uint16 all; + struct I2CDXR_BITS bit; +}; + +struct I2CMDR_BITS { // bits description + Uint16 BC:3; // 2:0 Bit count bits. + Uint16 FDF:1; // 3 Free Data Format + Uint16 STB:1; // 4 START Byte Mode + Uint16 IRS:1; // 5 I2C Module Reset + Uint16 DLB:1; // 6 Digital Loopback Mode + Uint16 RM:1; // 7 Repeat Mode + Uint16 XA:1; // 8 Expanded Address Mode + Uint16 TRX:1; // 9 Transmitter Mode + Uint16 MST:1; // 10 Master Mode + Uint16 STP:1; // 11 STOP Condition + Uint16 rsvd1:1; // 12 Reserved + Uint16 STT:1; // 13 START condition bit + Uint16 FREE:1; // 14 Debug Action + Uint16 NACKMOD:1; // 15 NACK mode bit +}; + +union I2CMDR_REG { + Uint16 all; + struct I2CMDR_BITS bit; +}; + +struct I2CISRC_BITS { // bits description + Uint16 INTCODE:3; // 2:0 Interrupt code bits. + Uint16 rsvd1:5; // 7:3 Reserved + Uint16 WRITE_ZEROS:4; // 11:8 Reserved + Uint16 rsvd2:4; // 15:12 Reserved +}; + +union I2CISRC_REG { + Uint16 all; + struct I2CISRC_BITS bit; +}; + +struct I2CEMDR_BITS { // bits description + Uint16 BC:1; // 0 Backwards compatibility mode + Uint16 rsvd1:15; // 15:1 Reserved +}; + +union I2CEMDR_REG { + Uint16 all; + struct I2CEMDR_BITS bit; +}; + +struct I2CPSC_BITS { // bits description + Uint16 IPSC:8; // 7:0 I2C Prescaler Divide Down + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union I2CPSC_REG { + Uint16 all; + struct I2CPSC_BITS bit; +}; + +struct I2CFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 Transmit FIFO Interrupt Level + Uint16 TXFFIENA:1; // 5 Transmit FIFO Interrupt Enable + Uint16 TXFFINTCLR:1; // 6 Transmit FIFO Interrupt Flag Clear + Uint16 TXFFINT:1; // 7 Transmit FIFO Interrupt Flag + Uint16 TXFFST:5; // 12:8 Transmit FIFO Status + Uint16 TXFFRST:1; // 13 Transmit FIFO Reset + Uint16 I2CFFEN:1; // 14 Transmit FIFO Enable + Uint16 rsvd1:1; // 15 Reserved +}; + +union I2CFFTX_REG { + Uint16 all; + struct I2CFFTX_BITS bit; +}; + +struct I2CFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Receive FIFO Interrupt Level + Uint16 RXFFIENA:1; // 5 Receive FIFO Interrupt Enable + Uint16 RXFFINTCLR:1; // 6 Receive FIFO Interrupt Flag Clear + Uint16 RXFFINT:1; // 7 Receive FIFO Interrupt Flag + Uint16 RXFFST:5; // 12:8 Receive FIFO Status + Uint16 RXFFRST:1; // 13 Receive FIFO Reset + Uint16 rsvd1:2; // 15:14 Reserved +}; + +union I2CFFRX_REG { + Uint16 all; + struct I2CFFRX_BITS bit; +}; + +struct I2C_REGS { + union I2COAR_REG I2COAR; // I2C Own address + union I2CIER_REG I2CIER; // I2C Interrupt Enable + union I2CSTR_REG I2CSTR; // I2C Status + Uint16 I2CCLKL; // I2C Clock low-time divider + Uint16 I2CCLKH; // I2C Clock high-time divider + Uint16 I2CCNT; // I2C Data count + union I2CDRR_REG I2CDRR; // I2C Data receive + union I2CSAR_REG I2CSAR; // I2C Slave address + union I2CDXR_REG I2CDXR; // I2C Data Transmit + union I2CMDR_REG I2CMDR; // I2C Mode + union I2CISRC_REG I2CISRC; // I2C Interrupt Source + union I2CEMDR_REG I2CEMDR; // I2C Extended Mode + union I2CPSC_REG I2CPSC; // I2C Prescaler + Uint16 rsvd1[19]; // Reserved + union I2CFFTX_REG I2CFFTX; // I2C FIFO Transmit + union I2CFFRX_REG I2CFFRX; // I2C FIFO Receive +}; + +//--------------------------------------------------------------------------- +// I2C External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct I2C_REGS I2caRegs; +extern volatile struct I2C_REGS I2cbRegs; +#endif +#ifdef CPU2 +extern volatile struct I2C_REGS I2caRegs; +extern volatile struct I2C_REGS I2cbRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_input_xbar.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_input_xbar.h new file mode 100644 index 0000000000..ef3abbe3ab --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_input_xbar.h @@ -0,0 +1,112 @@ +//########################################################################### +// +// FILE: F2837xD_input_xbar.h +// +// TITLE: INPUT_XBAR Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_INPUT_XBAR_H__ +#define __F2837xD_INPUT_XBAR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// INPUT_XBAR Individual Register Bit Definitions: + +struct INPUTSELECTLOCK_BITS { // bits description + Uint16 INPUT1SELECT:1; // 0 Lock bit for INPUT1SEL Register + Uint16 INPUT2SELECT:1; // 1 Lock bit for INPUT2SEL Register + Uint16 INPUT3SELECT:1; // 2 Lock bit for INPUT3SEL Register + Uint16 INPUT4SELECT:1; // 3 Lock bit for INPUT4SEL Register + Uint16 INPUT5SELECT:1; // 4 Lock bit for INPUT5SEL Register + Uint16 INPUT6SELECT:1; // 5 Lock bit for INPUT7SEL Register + Uint16 INPUT7SELECT:1; // 6 Lock bit for INPUT8SEL Register + Uint16 INPUT8SELECT:1; // 7 Lock bit for INPUT9SEL Register + Uint16 INPUT9SELECT:1; // 8 Lock bit for INPUT10SEL Register + Uint16 INPUT10SELECT:1; // 9 Lock bit for INPUT11SEL Register + Uint16 INPUT11SELECT:1; // 10 Lock bit for INPUT11SEL Register + Uint16 INPUT12SELECT:1; // 11 Lock bit for INPUT12SEL Register + Uint16 INPUT13SELECT:1; // 12 Lock bit for INPUT13SEL Register + Uint16 INPUT14SELECT:1; // 13 Lock bit for INPUT14SEL Register + Uint16 INPUT15SELECT:1; // 14 Lock bit for INPUT15SEL Register + Uint16 INPUT16SELECT:1; // 15 Lock bit for INPUT16SEL Register + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union INPUTSELECTLOCK_REG { + Uint32 all; + struct INPUTSELECTLOCK_BITS bit; +}; + +struct INPUT_XBAR_REGS { + Uint16 INPUT1SELECT; // INPUT1 Input Select Register (GPIO0 to x) + Uint16 INPUT2SELECT; // INPUT2 Input Select Register (GPIO0 to x) + Uint16 INPUT3SELECT; // INPUT3 Input Select Register (GPIO0 to x) + Uint16 INPUT4SELECT; // INPUT4 Input Select Register (GPIO0 to x) + Uint16 INPUT5SELECT; // INPUT5 Input Select Register (GPIO0 to x) + Uint16 INPUT6SELECT; // INPUT6 Input Select Register (GPIO0 to x) + Uint16 INPUT7SELECT; // INPUT7 Input Select Register (GPIO0 to x) + Uint16 INPUT8SELECT; // INPUT8 Input Select Register (GPIO0 to x) + Uint16 INPUT9SELECT; // INPUT9 Input Select Register (GPIO0 to x) + Uint16 INPUT10SELECT; // INPUT10 Input Select Register (GPIO0 to x) + Uint16 INPUT11SELECT; // INPUT11 Input Select Register (GPIO0 to x) + Uint16 INPUT12SELECT; // INPUT12 Input Select Register (GPIO0 to x) + Uint16 INPUT13SELECT; // INPUT13 Input Select Register (GPIO0 to x) + Uint16 INPUT14SELECT; // INPUT14 Input Select Register (GPIO0 to x) + Uint16 rsvd1[16]; // Reserved + union INPUTSELECTLOCK_REG INPUTSELECTLOCK; // Input Select Lock Register +}; + +//--------------------------------------------------------------------------- +// INPUT_XBAR External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct INPUT_XBAR_REGS InputXbarRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_ipc.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_ipc.h new file mode 100644 index 0000000000..411ef4c80b --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_ipc.h @@ -0,0 +1,313 @@ +//########################################################################### +// +// FILE: F2837xD_ipc.h +// +// TITLE: IPC Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_IPC_H__ +#define __F2837xD_IPC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// IPC Individual Register Bit Definitions: + +struct IPCACK_BITS { // bits description + Uint16 IPC0:1; // 0 Local IPC Flag 0 Acknowledgement + Uint16 IPC1:1; // 1 Local IPC Flag 1 Acknowledgement + Uint16 IPC2:1; // 2 Local IPC Flag 2 Acknowledgement + Uint16 IPC3:1; // 3 Local IPC Flag 3 Acknowledgement + Uint16 IPC4:1; // 4 Local IPC Flag 4 Acknowledgement + Uint16 IPC5:1; // 5 Local IPC Flag 5 Acknowledgement + Uint16 IPC6:1; // 6 Local IPC Flag 6 Acknowledgement + Uint16 IPC7:1; // 7 Local IPC Flag 7 Acknowledgement + Uint16 IPC8:1; // 8 Local IPC Flag 8 Acknowledgement + Uint16 IPC9:1; // 9 Local IPC Flag 9 Acknowledgement + Uint16 IPC10:1; // 10 Local IPC Flag 10 Acknowledgement + Uint16 IPC11:1; // 11 Local IPC Flag 11 Acknowledgement + Uint16 IPC12:1; // 12 Local IPC Flag 12 Acknowledgement + Uint16 IPC13:1; // 13 Local IPC Flag 13 Acknowledgement + Uint16 IPC14:1; // 14 Local IPC Flag 14 Acknowledgement + Uint16 IPC15:1; // 15 Local IPC Flag 15 Acknowledgement + Uint16 IPC16:1; // 16 Local IPC Flag 16 Acknowledgement + Uint16 IPC17:1; // 17 Local IPC Flag 17 Acknowledgement + Uint16 IPC18:1; // 18 Local IPC Flag 18 Acknowledgement + Uint16 IPC19:1; // 19 Local IPC Flag 19 Acknowledgement + Uint16 IPC20:1; // 20 Local IPC Flag 20 Acknowledgement + Uint16 IPC21:1; // 21 Local IPC Flag 21 Acknowledgement + Uint16 IPC22:1; // 22 Local IPC Flag 22 Acknowledgement + Uint16 IPC23:1; // 23 Local IPC Flag 23 Acknowledgement + Uint16 IPC24:1; // 24 Local IPC Flag 24 Acknowledgement + Uint16 IPC25:1; // 25 Local IPC Flag 25 Acknowledgement + Uint16 IPC26:1; // 26 Local IPC Flag 26 Acknowledgement + Uint16 IPC27:1; // 27 Local IPC Flag 27 Acknowledgement + Uint16 IPC28:1; // 28 Local IPC Flag 28 Acknowledgement + Uint16 IPC29:1; // 29 Local IPC Flag 29 Acknowledgement + Uint16 IPC30:1; // 30 Local IPC Flag 30 Acknowledgement + Uint16 IPC31:1; // 31 Local IPC Flag 31 Acknowledgement +}; + +union IPCACK_REG { + Uint32 all; + struct IPCACK_BITS bit; +}; + +struct IPCSTS_BITS { // bits description + Uint16 IPC0:1; // 0 Local IPC Flag 0 Status + Uint16 IPC1:1; // 1 Local IPC Flag 1 Status + Uint16 IPC2:1; // 2 Local IPC Flag 2 Status + Uint16 IPC3:1; // 3 Local IPC Flag 3 Status + Uint16 IPC4:1; // 4 Local IPC Flag 4 Status + Uint16 IPC5:1; // 5 Local IPC Flag 5 Status + Uint16 IPC6:1; // 6 Local IPC Flag 6 Status + Uint16 IPC7:1; // 7 Local IPC Flag 7 Status + Uint16 IPC8:1; // 8 Local IPC Flag 8 Status + Uint16 IPC9:1; // 9 Local IPC Flag 9 Status + Uint16 IPC10:1; // 10 Local IPC Flag 10 Status + Uint16 IPC11:1; // 11 Local IPC Flag 11 Status + Uint16 IPC12:1; // 12 Local IPC Flag 12 Status + Uint16 IPC13:1; // 13 Local IPC Flag 13 Status + Uint16 IPC14:1; // 14 Local IPC Flag 14 Status + Uint16 IPC15:1; // 15 Local IPC Flag 15 Status + Uint16 IPC16:1; // 16 Local IPC Flag 16 Status + Uint16 IPC17:1; // 17 Local IPC Flag 17 Status + Uint16 IPC18:1; // 18 Local IPC Flag 18 Status + Uint16 IPC19:1; // 19 Local IPC Flag 19 Status + Uint16 IPC20:1; // 20 Local IPC Flag 20 Status + Uint16 IPC21:1; // 21 Local IPC Flag 21 Status + Uint16 IPC22:1; // 22 Local IPC Flag 22 Status + Uint16 IPC23:1; // 23 Local IPC Flag 23 Status + Uint16 IPC24:1; // 24 Local IPC Flag 24 Status + Uint16 IPC25:1; // 25 Local IPC Flag 25 Status + Uint16 IPC26:1; // 26 Local IPC Flag 26 Status + Uint16 IPC27:1; // 27 Local IPC Flag 27 Status + Uint16 IPC28:1; // 28 Local IPC Flag 28 Status + Uint16 IPC29:1; // 29 Local IPC Flag 29 Status + Uint16 IPC30:1; // 30 Local IPC Flag 30 Status + Uint16 IPC31:1; // 31 Local IPC Flag 31 Status +}; + +union IPCSTS_REG { + Uint32 all; + struct IPCSTS_BITS bit; +}; + +struct IPCSET_BITS { // bits description + Uint16 IPC0:1; // 0 Set Remote IPC0 Flag + Uint16 IPC1:1; // 1 Set Remote IPC1 Flag + Uint16 IPC2:1; // 2 Set Remote IPC2 Flag + Uint16 IPC3:1; // 3 Set Remote IPC3 Flag + Uint16 IPC4:1; // 4 Set Remote IPC4 Flag + Uint16 IPC5:1; // 5 Set Remote IPC5 Flag + Uint16 IPC6:1; // 6 Set Remote IPC6 Flag + Uint16 IPC7:1; // 7 Set Remote IPC7 Flag + Uint16 IPC8:1; // 8 Set Remote IPC8 Flag + Uint16 IPC9:1; // 9 Set Remote IPC9 Flag + Uint16 IPC10:1; // 10 Set Remote IPC10 Flag + Uint16 IPC11:1; // 11 Set Remote IPC11 Flag + Uint16 IPC12:1; // 12 Set Remote IPC12 Flag + Uint16 IPC13:1; // 13 Set Remote IPC13 Flag + Uint16 IPC14:1; // 14 Set Remote IPC14 Flag + Uint16 IPC15:1; // 15 Set Remote IPC15 Flag + Uint16 IPC16:1; // 16 Set Remote IPC16 Flag + Uint16 IPC17:1; // 17 Set Remote IPC17 Flag + Uint16 IPC18:1; // 18 Set Remote IPC18 Flag + Uint16 IPC19:1; // 19 Set Remote IPC19 Flag + Uint16 IPC20:1; // 20 Set Remote IPC20 Flag + Uint16 IPC21:1; // 21 Set Remote IPC21 Flag + Uint16 IPC22:1; // 22 Set Remote IPC22 Flag + Uint16 IPC23:1; // 23 Set Remote IPC23 Flag + Uint16 IPC24:1; // 24 Set Remote IPC24 Flag + Uint16 IPC25:1; // 25 Set Remote IPC25 Flag + Uint16 IPC26:1; // 26 Set Remote IPC26 Flag + Uint16 IPC27:1; // 27 Set Remote IPC27 Flag + Uint16 IPC28:1; // 28 Set Remote IPC28 Flag + Uint16 IPC29:1; // 29 Set Remote IPC29 Flag + Uint16 IPC30:1; // 30 Set Remote IPC30 Flag + Uint16 IPC31:1; // 31 Set Remote IPC31 Flag +}; + +union IPCSET_REG { + Uint32 all; + struct IPCSET_BITS bit; +}; + +struct IPCCLR_BITS { // bits description + Uint16 IPC0:1; // 0 Clear Remote IPC0 Flag + Uint16 IPC1:1; // 1 Clear Remote IPC1 Flag + Uint16 IPC2:1; // 2 Clear Remote IPC2 Flag + Uint16 IPC3:1; // 3 Clear Remote IPC3 Flag + Uint16 IPC4:1; // 4 Clear Remote IPC4 Flag + Uint16 IPC5:1; // 5 Clear Remote IPC5 Flag + Uint16 IPC6:1; // 6 Clear Remote IPC6 Flag + Uint16 IPC7:1; // 7 Clear Remote IPC7 Flag + Uint16 IPC8:1; // 8 Clear Remote IPC8 Flag + Uint16 IPC9:1; // 9 Clear Remote IPC9 Flag + Uint16 IPC10:1; // 10 Clear Remote IPC10 Flag + Uint16 IPC11:1; // 11 Clear Remote IPC11 Flag + Uint16 IPC12:1; // 12 Clear Remote IPC12 Flag + Uint16 IPC13:1; // 13 Clear Remote IPC13 Flag + Uint16 IPC14:1; // 14 Clear Remote IPC14 Flag + Uint16 IPC15:1; // 15 Clear Remote IPC15 Flag + Uint16 IPC16:1; // 16 Clear Remote IPC16 Flag + Uint16 IPC17:1; // 17 Clear Remote IPC17 Flag + Uint16 IPC18:1; // 18 Clear Remote IPC18 Flag + Uint16 IPC19:1; // 19 Clear Remote IPC19 Flag + Uint16 IPC20:1; // 20 Clear Remote IPC20 Flag + Uint16 IPC21:1; // 21 Clear Remote IPC21 Flag + Uint16 IPC22:1; // 22 Clear Remote IPC22 Flag + Uint16 IPC23:1; // 23 Clear Remote IPC23 Flag + Uint16 IPC24:1; // 24 Clear Remote IPC24 Flag + Uint16 IPC25:1; // 25 Clear Remote IPC25 Flag + Uint16 IPC26:1; // 26 Clear Remote IPC26 Flag + Uint16 IPC27:1; // 27 Clear Remote IPC27 Flag + Uint16 IPC28:1; // 28 Clear Remote IPC28 Flag + Uint16 IPC29:1; // 29 Clear Remote IPC29 Flag + Uint16 IPC30:1; // 30 Clear Remote IPC30 Flag + Uint16 IPC31:1; // 31 Clear Remote IPC31 Flag +}; + +union IPCCLR_REG { + Uint32 all; + struct IPCCLR_BITS bit; +}; + +struct IPCFLG_BITS { // bits description + Uint16 IPC0:1; // 0 Remote IPC0 Flag Status + Uint16 IPC1:1; // 1 Remote IPC1 Flag Status + Uint16 IPC2:1; // 2 Remote IPC2 Flag Status + Uint16 IPC3:1; // 3 Remote IPC3 Flag Status + Uint16 IPC4:1; // 4 Remote IPC4 Flag Status + Uint16 IPC5:1; // 5 Remote IPC5 Flag Status + Uint16 IPC6:1; // 6 Remote IPC6 Flag Status + Uint16 IPC7:1; // 7 Remote IPC7 Flag Status + Uint16 IPC8:1; // 8 Remote IPC8 Flag Status + Uint16 IPC9:1; // 9 Remote IPC9 Flag Status + Uint16 IPC10:1; // 10 Remote IPC10 Flag Status + Uint16 IPC11:1; // 11 Remote IPC11 Flag Status + Uint16 IPC12:1; // 12 Remote IPC12 Flag Status + Uint16 IPC13:1; // 13 Remote IPC13 Flag Status + Uint16 IPC14:1; // 14 Remote IPC14 Flag Status + Uint16 IPC15:1; // 15 Remote IPC15 Flag Status + Uint16 IPC16:1; // 16 Remote IPC16 Flag Status + Uint16 IPC17:1; // 17 Remote IPC17 Flag Status + Uint16 IPC18:1; // 18 Remote IPC18 Flag Status + Uint16 IPC19:1; // 19 Remote IPC19 Flag Status + Uint16 IPC20:1; // 20 Remote IPC20 Flag Status + Uint16 IPC21:1; // 21 Remote IPC21 Flag Status + Uint16 IPC22:1; // 22 Remote IPC22 Flag Status + Uint16 IPC23:1; // 23 Remote IPC23 Flag Status + Uint16 IPC24:1; // 24 Remote IPC24 Flag Status + Uint16 IPC25:1; // 25 Remote IPC25 Flag Status + Uint16 IPC26:1; // 26 Remote IPC26 Flag Status + Uint16 IPC27:1; // 27 Remote IPC27 Flag Status + Uint16 IPC28:1; // 28 Remote IPC28 Flag Status + Uint16 IPC29:1; // 29 Remote IPC29 Flag Status + Uint16 IPC30:1; // 30 Remote IPC30 Flag Status + Uint16 IPC31:1; // 31 Remote IPC31 Flag Status +}; + +union IPCFLG_REG { + Uint32 all; + struct IPCFLG_BITS bit; +}; + +struct IPC_REGS_CPU1 { + union IPCACK_REG IPCACK; // IPC incoming flag clear (acknowledge) register + union IPCSTS_REG IPCSTS; // IPC incoming flag status register + union IPCSET_REG IPCSET; // IPC remote flag set register + union IPCCLR_REG IPCCLR; // IPC remote flag clear register + union IPCFLG_REG IPCFLG; // IPC remote flag status register + Uint16 rsvd1[2]; // Reserved + Uint32 IPCCOUNTERL; // IPC Counter Low Register + Uint32 IPCCOUNTERH; // IPC Counter High Register + Uint32 IPCSENDCOM; // Local to Remote IPC Command Register + Uint32 IPCSENDADDR; // Local to Remote IPC Address Register + Uint32 IPCSENDDATA; // Local to Remote IPC Data Register + Uint32 IPCREMOTEREPLY; // Remote to Local IPC Reply Data Register + Uint32 IPCRECVCOM; // Remote to Local IPC Command Register + Uint32 IPCRECVADDR; // Remote to Local IPC Address Register + Uint32 IPCRECVDATA; // Remote to Local IPC Data Register + Uint32 IPCLOCALREPLY; // Local to Remote IPC Reply Data Register + Uint32 IPCBOOTSTS; // CPU2 to CPU1 IPC Boot Status Register + Uint32 IPCBOOTMODE; // CPU1 to CPU2 IPC Boot Mode Register +}; + +struct IPC_REGS_CPU2 { + union IPCACK_REG IPCACK; // IPC incoming flag clear (acknowledge) register + union IPCSTS_REG IPCSTS; // IPC incoming flag status register + union IPCSET_REG IPCSET; // IPC remote flag set register + union IPCCLR_REG IPCCLR; // IPC remote flag clear register + union IPCFLG_REG IPCFLG; // IPC remote flag status register + Uint16 rsvd1[2]; // Reserved + Uint32 IPCCOUNTERL; // IPC Counter Low Register + Uint32 IPCCOUNTERH; // IPC Counter High Register + Uint32 IPCRECVCOM; // Remote to Local IPC Command Register + Uint32 IPCRECVADDR; // Remote to Local IPC Address Register + Uint32 IPCRECVDATA; // Remote to Local IPC Data Register + Uint32 IPCLOCALREPLY; // Local to Remote IPC Reply Data Register + Uint32 IPCSENDCOM; // Local to Remote IPC Command Register + Uint32 IPCSENDADDR; // Local to Remote IPC Address Register + Uint32 IPCSENDDATA; // Local to Remote IPC Data Register + Uint32 IPCREMOTEREPLY; // Remote to Local IPC Reply Data Register + Uint32 IPCBOOTSTS; // CPU2 to CPU1 IPC Boot Status Register + Uint32 IPCBOOTMODE; // CPU1 to CPU2 IPC Boot Mode Register +}; + +//--------------------------------------------------------------------------- +// IPC External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct IPC_REGS_CPU1 IpcRegs; +#endif +#ifdef CPU2 +extern volatile struct IPC_REGS_CPU2 IpcRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_mcbsp.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_mcbsp.h new file mode 100644 index 0000000000..0f94e76030 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_mcbsp.h @@ -0,0 +1,323 @@ +//########################################################################### +// +// FILE: F2837xD_mcbsp.h +// +// TITLE: MCBSP Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_MCBSP_H__ +#define __F2837xD_MCBSP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// MCBSP Individual Register Bit Definitions: + +struct DRR2_BITS { // bits description + Uint16 HWLB:8; // 7:0 High word low byte + Uint16 HWHB:8; // 15:8 High word high byte +}; + +union DRR2_REG { + Uint16 all; + struct DRR2_BITS bit; +}; + +struct DRR1_BITS { // bits description + Uint16 LWLB:8; // 7:0 Low word low byte + Uint16 LWHB:8; // 15:8 Low word high byte +}; + +union DRR1_REG { + Uint16 all; + struct DRR1_BITS bit; +}; + +struct DXR2_BITS { // bits description + Uint16 HWLB:8; // 7:0 High word low byte + Uint16 HWHB:8; // 15:8 High word high byte +}; + +union DXR2_REG { + Uint16 all; + struct DXR2_BITS bit; +}; + +struct DXR1_BITS { // bits description + Uint16 LWLB:8; // 7:0 Low word low byte + Uint16 LWHB:8; // 15:8 Low word high byte +}; + +union DXR1_REG { + Uint16 all; + struct DXR1_BITS bit; +}; + +struct SPCR2_BITS { // bits description + Uint16 XRST:1; // 0 Transmitter reset + Uint16 XRDY:1; // 1 Transmitter ready + Uint16 XEMPTY:1; // 2 Transmitter empty + Uint16 XSYNCERR:1; // 3 Transmit sync error INT flag + Uint16 XINTM:2; // 5:4 Transmit Interupt mode bits + Uint16 GRST:1; // 6 Sample rate generator reset + Uint16 FRST:1; // 7 Frame sync logic reset + Uint16 SOFT:1; // 8 SOFT bit + Uint16 FREE:1; // 9 FREE bit + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union SPCR2_REG { + Uint16 all; + struct SPCR2_BITS bit; +}; + +struct SPCR1_BITS { // bits description + Uint16 RRST:1; // 0 Receiver reset + Uint16 RRDY:1; // 1 Receiver ready + Uint16 RFULL:1; // 2 Receiver full + Uint16 RSYNCERR:1; // 3 Receive sync error INT flag + Uint16 RINTM:2; // 5:4 Receive Interupt mode bits + Uint16 rsvd1:1; // 6 Reserved + Uint16 DXENA:1; // 7 DX delay enable + Uint16 rsvd2:3; // 10:8 Reserved + Uint16 CLKSTP:2; // 12:11 Clock stop mode + Uint16 RJUST:2; // 14:13 Rx sign extension and justification mode + Uint16 DLB:1; // 15 Digital loopback +}; + +union SPCR1_REG { + Uint16 all; + struct SPCR1_BITS bit; +}; + +struct RCR2_BITS { // bits description + Uint16 RDATDLY:2; // 1:0 Receive data delay + Uint16 RFIG:1; // 2 Receive frame sync ignore + Uint16 RCOMPAND:2; // 4:3 Receive Companding Mode selects + Uint16 RWDLEN2:3; // 7:5 Receive word length 2 + Uint16 RFRLEN2:7; // 14:8 Receive Frame length 2 + Uint16 RPHASE:1; // 15 Receive Phase +}; + +union RCR2_REG { + Uint16 all; + struct RCR2_BITS bit; +}; + +struct RCR1_BITS { // bits description + Uint16 rsvd1:5; // 4:0 Reserved + Uint16 RWDLEN1:3; // 7:5 Receive word length 1 + Uint16 RFRLEN1:7; // 14:8 Receive Frame length 1 + Uint16 rsvd2:1; // 15 Reserved +}; + +union RCR1_REG { + Uint16 all; + struct RCR1_BITS bit; +}; + +struct XCR2_BITS { // bits description + Uint16 XDATDLY:2; // 1:0 Transmit data delay + Uint16 XFIG:1; // 2 Transmit frame sync ignore + Uint16 XCOMPAND:2; // 4:3 Transmit Companding Mode selects + Uint16 XWDLEN2:3; // 7:5 Transmit word length 2 + Uint16 XFRLEN2:7; // 14:8 Transmit Frame length 2 + Uint16 XPHASE:1; // 15 Transmit Phase +}; + +union XCR2_REG { + Uint16 all; + struct XCR2_BITS bit; +}; + +struct XCR1_BITS { // bits description + Uint16 rsvd1:5; // 4:0 Reserved + Uint16 XWDLEN1:3; // 7:5 Transmit word length 1 + Uint16 XFRLEN1:7; // 14:8 Transmit Frame length 1 + Uint16 rsvd2:1; // 15 Reserved +}; + +union XCR1_REG { + Uint16 all; + struct XCR1_BITS bit; +}; + +struct SRGR2_BITS { // bits description + Uint16 FPER:12; // 11:0 Frame-sync period + Uint16 FSGM:1; // 12 Frame sync generator mode + Uint16 CLKSM:1; // 13 Sample rate generator mode + Uint16 rsvd1:1; // 14 Reserved + Uint16 GSYNC:1; // 15 CLKG sync +}; + +union SRGR2_REG { + Uint16 all; + struct SRGR2_BITS bit; +}; + +struct SRGR1_BITS { // bits description + Uint16 CLKGDV:8; // 7:0 CLKG divider + Uint16 FWID:8; // 15:8 Frame width +}; + +union SRGR1_REG { + Uint16 all; + struct SRGR1_BITS bit; +}; + +struct MCR2_BITS { // bits description + Uint16 XMCM:2; // 1:0 Transmit data delay + Uint16 XCBLK:3; // 4:2 Transmit frame sync ignore + Uint16 XPABLK:2; // 6:5 Transmit Companding Mode selects + Uint16 XPBBLK:2; // 8:7 Transmit word length 2 + Uint16 XMCME:1; // 9 Transmit Frame length 2 + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union MCR2_REG { + Uint16 all; + struct MCR2_BITS bit; +}; + +struct MCR1_BITS { // bits description + Uint16 RMCM:1; // 0 Receive multichannel mode + Uint16 rsvd1:1; // 1 Reserved + Uint16 RCBLK:3; // 4:2 eceive current block + Uint16 RPABLK:2; // 6:5 Receive partition A Block + Uint16 RPBBLK:2; // 8:7 Receive partition B Block + Uint16 RMCME:1; // 9 Receive multi-channel enhance mode + Uint16 rsvd2:6; // 15:10 Reserved +}; + +union MCR1_REG { + Uint16 all; + struct MCR1_BITS bit; +}; + +struct PCR_BITS { // bits description + Uint16 CLKRP:1; // 0 Receive Clock polarity + Uint16 CLKXP:1; // 1 Transmit clock polarity + Uint16 FSRP:1; // 2 Receive Frame synchronization polarity + Uint16 FSXP:1; // 3 Transmit Frame synchronization polarity + Uint16 rsvd1:1; // 4 Reserved + Uint16 rsvd2:1; // 5 Reserved + Uint16 rsvd3:1; // 6 Reserved + Uint16 SCLKME:1; // 7 Sample clock mode selection + Uint16 CLKRM:1; // 8 Receiver Clock Mode + Uint16 CLKXM:1; // 9 Transmit Clock Mode. + Uint16 FSRM:1; // 10 Receive Frame Synchronization Mode + Uint16 FSXM:1; // 11 Transmit Frame Synchronization Mode + Uint16 rsvd4:4; // 15:12 Reserved +}; + +union PCR_REG { + Uint16 all; + struct PCR_BITS bit; +}; + +struct MFFINT_BITS { // bits description + Uint16 XINT:1; // 0 Enable for Receive Interrupt + Uint16 rsvd1:1; // 1 Reserved + Uint16 RINT:1; // 2 Enable for transmit Interrupt + Uint16 rsvd2:13; // 15:3 Reserved +}; + +union MFFINT_REG { + Uint16 all; + struct MFFINT_BITS bit; +}; + +struct McBSP_REGS { + union DRR2_REG DRR2; // Data receive register bits 31-16 + union DRR1_REG DRR1; // Data receive register bits 15-0 + union DXR2_REG DXR2; // Data transmit register bits 31-16 + union DXR1_REG DXR1; // Data transmit register bits 15-0 + union SPCR2_REG SPCR2; // Control register 2 + union SPCR1_REG SPCR1; // Control register 1 + union RCR2_REG RCR2; // Receive Control register 2 + union RCR1_REG RCR1; // Receive Control register 1 + union XCR2_REG XCR2; // Transmit Control register 2 + union XCR1_REG XCR1; // Transmit Control register 1 + union SRGR2_REG SRGR2; // Sample rate generator register 2 + union SRGR1_REG SRGR1; // Sample rate generator register 1 + union MCR2_REG MCR2; // Multi-channel register 2 + union MCR1_REG MCR1; // Multi-channel register 1 + Uint16 RCERA; // Receive channel enable partition A + Uint16 RCERB; // Receive channel enable partition B + Uint16 XCERA; // Transmit channel enable partition A + Uint16 XCERB; // Transmit channel enable partition B + union PCR_REG PCR; // Pin Control register + Uint16 RCERC; // Receive channel enable partition C + Uint16 RCERD; // Receive channel enable partition D + Uint16 XCERC; // Transmit channel enable partition C + Uint16 XCERD; // Transmit channel enable partition D + Uint16 RCERE; // Receive channel enable partition E + Uint16 RCERF; // Receive channel enable partition F + Uint16 XCERE; // Transmit channel enable partition E + Uint16 XCERF; // Transmit channel enable partition F + Uint16 RCERG; // Receive channel enable partition G + Uint16 RCERH; // Receive channel enable partition H + Uint16 XCERG; // Transmit channel enable partition G + Uint16 XCERH; // Transmit channel enable partition H + Uint16 rsvd1[4]; // Reserved + union MFFINT_REG MFFINT; // Interrupt enable +}; + +//--------------------------------------------------------------------------- +// MCBSP External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct McBSP_REGS McbspaRegs; +extern volatile struct McBSP_REGS McbspbRegs; +#endif +#ifdef CPU2 +extern volatile struct McBSP_REGS McbspaRegs; +extern volatile struct McBSP_REGS McbspbRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_memconfig.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_memconfig.h new file mode 100644 index 0000000000..9dcf877d3c --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_memconfig.h @@ -0,0 +1,1071 @@ +//########################################################################### +// +// FILE: F2837xD_memconfig.h +// +// TITLE: MEMCONFIG Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_MEMCONFIG_H__ +#define __F2837xD_MEMCONFIG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// MEMCONFIG Individual Register Bit Definitions: + +struct DxLOCK_BITS { // bits description + Uint16 rsvd1:2; // 1:0 Reserved + Uint16 LOCK_D0:1; // 2 D0 RAM access protection and master select fields lock bit + Uint16 LOCK_D1:1; // 3 D1 RAM access protection and master select fields lock bit + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union DxLOCK_REG { + Uint32 all; + struct DxLOCK_BITS bit; +}; + +struct DxCOMMIT_BITS { // bits description + Uint16 rsvd1:2; // 1:0 Reserved + Uint16 COMMIT_D0:1; // 2 D0 RAM access protection and master select permanent lock + Uint16 COMMIT_D1:1; // 3 D1 RAM access protection and master select permanent lock + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union DxCOMMIT_REG { + Uint32 all; + struct DxCOMMIT_BITS bit; +}; + +struct DxACCPROT0_BITS { // bits description + Uint16 rsvd1:16; // 15:0 Reserved + Uint16 FETCHPROT_D0:1; // 16 Fetch Protection For D0 RAM + Uint16 CPUWRPROT_D0:1; // 17 CPU WR Protection For D0 RAM + Uint16 rsvd2:6; // 23:18 Reserved + Uint16 FETCHPROT_D1:1; // 24 Fetch Protection For D1 RAM + Uint16 CPUWRPROT_D1:1; // 25 CPU WR Protection For D1 RAM + Uint16 rsvd3:6; // 31:26 Reserved +}; + +union DxACCPROT0_REG { + Uint32 all; + struct DxACCPROT0_BITS bit; +}; + +struct DxTEST_BITS { // bits description + Uint16 TEST_M0:2; // 1:0 Selects the different modes for M0 RAM + Uint16 TEST_M1:2; // 3:2 Selects the different modes for M1 RAM + Uint16 TEST_D0:2; // 5:4 Selects the different modes for D0 RAM + Uint16 TEST_D1:2; // 7:6 Selects the different modes for D1 RAM + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DxTEST_REG { + Uint32 all; + struct DxTEST_BITS bit; +}; + +struct DxINIT_BITS { // bits description + Uint16 INIT_M0:1; // 0 RAM Initialization control for M0 RAM. + Uint16 INIT_M1:1; // 1 RAM Initialization control for M1 RAM. + Uint16 INIT_D0:1; // 2 RAM Initialization control for D0 RAM. + Uint16 INIT_D1:1; // 3 RAM Initialization control for D1 RAM. + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DxINIT_REG { + Uint32 all; + struct DxINIT_BITS bit; +}; + +struct DxINITDONE_BITS { // bits description + Uint16 INITDONE_M0:1; // 0 RAM Initialization status for M0 RAM. + Uint16 INITDONE_M1:1; // 1 RAM Initialization status for M1 RAM. + Uint16 INITDONE_D0:1; // 2 RAM Initialization status for D0 RAM. + Uint16 INITDONE_D1:1; // 3 RAM Initialization status for D1 RAM. + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DxINITDONE_REG { + Uint32 all; + struct DxINITDONE_BITS bit; +}; + +struct LSxLOCK_BITS { // bits description + Uint16 LOCK_LS0:1; // 0 LS0 RAM access protection and master select fields lock bit + Uint16 LOCK_LS1:1; // 1 LS1 RAM access protection and master select fields lock bit + Uint16 LOCK_LS2:1; // 2 LS2 RAM access protection and master select fields lock bit + Uint16 LOCK_LS3:1; // 3 LS3 RAM access protection and master select fields lock bit + Uint16 LOCK_LS4:1; // 4 LS4 RAM access protection and master select fields lock bit + Uint16 LOCK_LS5:1; // 5 LS5 RAM access protection and master select fields lock bit + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxLOCK_REG { + Uint32 all; + struct LSxLOCK_BITS bit; +}; + +struct LSxCOMMIT_BITS { // bits description + Uint16 COMMIT_LS0:1; // 0 LS0 RAM access protection and master select permanent lock + Uint16 COMMIT_LS1:1; // 1 LS1 RAM access protection and master select permanent lock + Uint16 COMMIT_LS2:1; // 2 LS2 RAM access protection and master select permanent lock + Uint16 COMMIT_LS3:1; // 3 LS3 RAM access protection and master select permanent lock + Uint16 COMMIT_LS4:1; // 4 LS4 RAM access protection and master select permanent lock + Uint16 COMMIT_LS5:1; // 5 LS5 RAM access protection and master select permanent lock + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxCOMMIT_REG { + Uint32 all; + struct LSxCOMMIT_BITS bit; +}; + +struct LSxMSEL_BITS { // bits description + Uint16 MSEL_LS0:2; // 1:0 Master Select for LS0 RAM + Uint16 MSEL_LS1:2; // 3:2 Master Select for LS1 RAM + Uint16 MSEL_LS2:2; // 5:4 Master Select for LS2 RAM + Uint16 MSEL_LS3:2; // 7:6 Master Select for LS3 RAM + Uint16 MSEL_LS4:2; // 9:8 Master Select for LS4 RAM + Uint16 MSEL_LS5:2; // 11:10 Master Select for LS5 RAM + Uint16 rsvd1:4; // 15:12 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxMSEL_REG { + Uint32 all; + struct LSxMSEL_BITS bit; +}; + +struct LSxCLAPGM_BITS { // bits description + Uint16 CLAPGM_LS0:1; // 0 Selects LS0 RAM as program vs data memory for CLA + Uint16 CLAPGM_LS1:1; // 1 Selects LS1 RAM as program vs data memory for CLA + Uint16 CLAPGM_LS2:1; // 2 Selects LS2 RAM as program vs data memory for CLA + Uint16 CLAPGM_LS3:1; // 3 Selects LS3 RAM as program vs data memory for CLA + Uint16 CLAPGM_LS4:1; // 4 Selects LS4 RAM as program vs data memory for CLA + Uint16 CLAPGM_LS5:1; // 5 Selects LS5 RAM as program vs data memory for CLA + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxCLAPGM_REG { + Uint32 all; + struct LSxCLAPGM_BITS bit; +}; + +struct LSxACCPROT0_BITS { // bits description + Uint16 FETCHPROT_LS0:1; // 0 Fetch Protection For LS0 RAM + Uint16 CPUWRPROT_LS0:1; // 1 CPU WR Protection For LS0 RAM + Uint16 rsvd1:6; // 7:2 Reserved + Uint16 FETCHPROT_LS1:1; // 8 Fetch Protection For LS1 RAM + Uint16 CPUWRPROT_LS1:1; // 9 CPU WR Protection For LS1 RAM + Uint16 rsvd2:6; // 15:10 Reserved + Uint16 FETCHPROT_LS2:1; // 16 Fetch Protection For LS2 RAM + Uint16 CPUWRPROT_LS2:1; // 17 CPU WR Protection For LS2 RAM + Uint16 rsvd3:6; // 23:18 Reserved + Uint16 FETCHPROT_LS3:1; // 24 Fetch Protection For LS3 RAM + Uint16 CPUWRPROT_LS3:1; // 25 CPU WR Protection For LS3 RAM + Uint16 rsvd4:6; // 31:26 Reserved +}; + +union LSxACCPROT0_REG { + Uint32 all; + struct LSxACCPROT0_BITS bit; +}; + +struct LSxACCPROT1_BITS { // bits description + Uint16 FETCHPROT_LS4:1; // 0 Fetch Protection For LS4 RAM + Uint16 CPUWRPROT_LS4:1; // 1 CPU WR Protection For LS4 RAM + Uint16 rsvd1:6; // 7:2 Reserved + Uint16 FETCHPROT_LS5:1; // 8 Fetch Protection For LS5 RAM + Uint16 CPUWRPROT_LS5:1; // 9 CPU WR Protection For LS5 RAM + Uint16 rsvd2:6; // 15:10 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union LSxACCPROT1_REG { + Uint32 all; + struct LSxACCPROT1_BITS bit; +}; + +struct LSxTEST_BITS { // bits description + Uint16 TEST_LS0:2; // 1:0 Selects the different modes for LS0 RAM + Uint16 TEST_LS1:2; // 3:2 Selects the different modes for LS1 RAM + Uint16 TEST_LS2:2; // 5:4 Selects the different modes for LS2 RAM + Uint16 TEST_LS3:2; // 7:6 Selects the different modes for LS3 RAM + Uint16 TEST_LS4:2; // 9:8 Selects the different modes for LS4 RAM + Uint16 TEST_LS5:2; // 11:10 Selects the different modes for LS5 RAM + Uint16 rsvd1:4; // 15:12 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxTEST_REG { + Uint32 all; + struct LSxTEST_BITS bit; +}; + +struct LSxINIT_BITS { // bits description + Uint16 INIT_LS0:1; // 0 RAM Initialization control for LS0 RAM. + Uint16 INIT_LS1:1; // 1 RAM Initialization control for LS1 RAM. + Uint16 INIT_LS2:1; // 2 RAM Initialization control for LS2 RAM. + Uint16 INIT_LS3:1; // 3 RAM Initialization control for LS3 RAM. + Uint16 INIT_LS4:1; // 4 RAM Initialization control for LS4 RAM. + Uint16 INIT_LS5:1; // 5 RAM Initialization control for LS5 RAM. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxINIT_REG { + Uint32 all; + struct LSxINIT_BITS bit; +}; + +struct LSxINITDONE_BITS { // bits description + Uint16 INITDONE_LS0:1; // 0 RAM Initialization status for LS0 RAM. + Uint16 INITDONE_LS1:1; // 1 RAM Initialization status for LS1 RAM. + Uint16 INITDONE_LS2:1; // 2 RAM Initialization status for LS2 RAM. + Uint16 INITDONE_LS3:1; // 3 RAM Initialization status for LS3 RAM. + Uint16 INITDONE_LS4:1; // 4 RAM Initialization status for LS4 RAM. + Uint16 INITDONE_LS5:1; // 5 RAM Initialization status for LS5 RAM. + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LSxINITDONE_REG { + Uint32 all; + struct LSxINITDONE_BITS bit; +}; + +struct GSxLOCK_BITS { // bits description + Uint16 LOCK_GS0:1; // 0 GS0 RAM access protection and master select fields lock bit + Uint16 LOCK_GS1:1; // 1 GS1 RAM access protection and master select fields lock bit + Uint16 LOCK_GS2:1; // 2 GS2 RAM access protection and master select fields lock bit + Uint16 LOCK_GS3:1; // 3 GS3 RAM access protection and master select fields lock bit + Uint16 LOCK_GS4:1; // 4 GS4 RAM access protection and master select fields lock bit + Uint16 LOCK_GS5:1; // 5 GS5 RAM access protection and master select fields lock bit + Uint16 LOCK_GS6:1; // 6 GS6 RAM access protection and master select fields lock bit + Uint16 LOCK_GS7:1; // 7 GS7 RAM access protection and master select fields lock bit + Uint16 LOCK_GS8:1; // 8 GS8 RAM access protection and master select fields lock bit + Uint16 LOCK_GS9:1; // 9 GS9 RAM access protection and master select fields lock bit + Uint16 LOCK_GS10:1; // 10 GS10 RAM access protection and master select fields lock bit + Uint16 LOCK_GS11:1; // 11 GS11 RAM access protection and master select fields lock bit + Uint16 LOCK_GS12:1; // 12 GS12 RAM access protection and master select fields lock bit + Uint16 LOCK_GS13:1; // 13 GS13 RAM access protection and master select fields lock bit + Uint16 LOCK_GS14:1; // 14 GS14 RAM access protection and master select fields lock bit + Uint16 LOCK_GS15:1; // 15 GS15 RAM access protection and master select fields lock bit + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union GSxLOCK_REG { + Uint32 all; + struct GSxLOCK_BITS bit; +}; + +struct GSxCOMMIT_BITS { // bits description + Uint16 COMMIT_GS0:1; // 0 GS0 RAM access protection and master select permanent lock + Uint16 COMMIT_GS1:1; // 1 GS1 RAM access protection and master select permanent lock + Uint16 COMMIT_GS2:1; // 2 GS2 RAM access protection and master select permanent lock + Uint16 COMMIT_GS3:1; // 3 GS3 RAM access protection and master select permanent lock + Uint16 COMMIT_GS4:1; // 4 GS4 RAM access protection and master select permanent lock + Uint16 COMMIT_GS5:1; // 5 GS5 RAM access protection and master select permanent lock + Uint16 COMMIT_GS6:1; // 6 GS6 RAM access protection and master select permanent lock + Uint16 COMMIT_GS7:1; // 7 GS7 RAM access protection and master select permanent lock + Uint16 COMMIT_GS8:1; // 8 GS8 RAM access protection and master select permanent lock + Uint16 COMMIT_GS9:1; // 9 GS9 RAM access protection and master select permanent lock + Uint16 COMMIT_GS10:1; // 10 GS10 RAM access protection and master select permanent lock + Uint16 COMMIT_GS11:1; // 11 GS11 RAM access protection and master select permanent lock + Uint16 COMMIT_GS12:1; // 12 GS12 RAM access protection and master select permanent lock + Uint16 COMMIT_GS13:1; // 13 GS13 RAM access protection and master select permanent lock + Uint16 COMMIT_GS14:1; // 14 GS14 RAM access protection and master select permanent lock + Uint16 COMMIT_GS15:1; // 15 GS15 RAM access protection and master select permanent lock + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union GSxCOMMIT_REG { + Uint32 all; + struct GSxCOMMIT_BITS bit; +}; + +struct GSxMSEL_BITS { // bits description + Uint16 MSEL_GS0:1; // 0 Master Select for GS0 RAM + Uint16 MSEL_GS1:1; // 1 Master Select for GS1 RAM + Uint16 MSEL_GS2:1; // 2 Master Select for GS2 RAM + Uint16 MSEL_GS3:1; // 3 Master Select for GS3 RAM + Uint16 MSEL_GS4:1; // 4 Master Select for GS4 RAM + Uint16 MSEL_GS5:1; // 5 Master Select for GS5 RAM + Uint16 MSEL_GS6:1; // 6 Master Select for GS6 RAM + Uint16 MSEL_GS7:1; // 7 Master Select for GS7 RAM + Uint16 MSEL_GS8:1; // 8 Master Select for GS8 RAM + Uint16 MSEL_GS9:1; // 9 Master Select for GS9 RAM + Uint16 MSEL_GS10:1; // 10 Master Select for GS10 RAM + Uint16 MSEL_GS11:1; // 11 Master Select for GS11 RAM + Uint16 MSEL_GS12:1; // 12 Master Select for GS12 RAM + Uint16 MSEL_GS13:1; // 13 Master Select for GS13 RAM + Uint16 MSEL_GS14:1; // 14 Master Select for GS14 RAM + Uint16 MSEL_GS15:1; // 15 Master Select for GS15 RAM + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union GSxMSEL_REG { + Uint32 all; + struct GSxMSEL_BITS bit; +}; + +struct GSxACCPROT0_BITS { // bits description + Uint16 FETCHPROT_GS0:1; // 0 Fetch Protection For GS0 RAM + Uint16 CPUWRPROT_GS0:1; // 1 CPU WR Protection For GS0 RAM + Uint16 DMAWRPROT_GS0:1; // 2 DMA WR Protection For GS0 RAM + Uint16 rsvd1:5; // 7:3 Reserved + Uint16 FETCHPROT_GS1:1; // 8 Fetch Protection For GS1 RAM + Uint16 CPUWRPROT_GS1:1; // 9 CPU WR Protection For GS1 RAM + Uint16 DMAWRPROT_GS1:1; // 10 DMA WR Protection For GS1 RAM + Uint16 rsvd2:5; // 15:11 Reserved + Uint16 FETCHPROT_GS2:1; // 16 Fetch Protection For GS2 RAM + Uint16 CPUWRPROT_GS2:1; // 17 CPU WR Protection For GS2 RAM + Uint16 DMAWRPROT_GS2:1; // 18 DMA WR Protection For GS2 RAM + Uint16 rsvd3:5; // 23:19 Reserved + Uint16 FETCHPROT_GS3:1; // 24 Fetch Protection For GS3 RAM + Uint16 CPUWRPROT_GS3:1; // 25 CPU WR Protection For GS3 RAM + Uint16 DMAWRPROT_GS3:1; // 26 DMA WR Protection For GS3 RAM + Uint16 rsvd4:5; // 31:27 Reserved +}; + +union GSxACCPROT0_REG { + Uint32 all; + struct GSxACCPROT0_BITS bit; +}; + +struct GSxACCPROT1_BITS { // bits description + Uint16 FETCHPROT_GS4:1; // 0 Fetch Protection For GS4 RAM + Uint16 CPUWRPROT_GS4:1; // 1 CPU WR Protection For GS4 RAM + Uint16 DMAWRPROT_GS4:1; // 2 DMA WR Protection For GS4 RAM + Uint16 rsvd1:5; // 7:3 Reserved + Uint16 FETCHPROT_GS5:1; // 8 Fetch Protection For GS5 RAM + Uint16 CPUWRPROT_GS5:1; // 9 CPU WR Protection For GS5 RAM + Uint16 DMAWRPROT_GS5:1; // 10 DMA WR Protection For GS5RAM + Uint16 rsvd2:5; // 15:11 Reserved + Uint16 FETCHPROT_GS6:1; // 16 Fetch Protection For GS6 RAM + Uint16 CPUWRPROT_GS6:1; // 17 CPU WR Protection For GS6 RAM + Uint16 DMAWRPROT_GS6:1; // 18 DMA WR Protection For GS6RAM + Uint16 rsvd3:5; // 23:19 Reserved + Uint16 FETCHPROT_GS7:1; // 24 Fetch Protection For GS7 RAM + Uint16 CPUWRPROT_GS7:1; // 25 CPU WR Protection For GS7 RAM + Uint16 DMAWRPROT_GS7:1; // 26 DMA WR Protection For GS7RAM + Uint16 rsvd4:5; // 31:27 Reserved +}; + +union GSxACCPROT1_REG { + Uint32 all; + struct GSxACCPROT1_BITS bit; +}; + +struct GSxACCPROT2_BITS { // bits description + Uint16 FETCHPROT_GS8:1; // 0 Fetch Protection For GS8 RAM + Uint16 CPUWRPROT_GS8:1; // 1 CPU WR Protection For GS8 RAM + Uint16 DMAWRPROT_GS8:1; // 2 DMA WR Protection For GS8 RAM + Uint16 rsvd1:5; // 7:3 Reserved + Uint16 FETCHPROT_GS9:1; // 8 Fetch Protection For GS9 RAM + Uint16 CPUWRPROT_GS9:1; // 9 CPU WR Protection For GS9 RAM + Uint16 DMAWRPROT_GS9:1; // 10 DMA WR Protection For GS9RAM + Uint16 rsvd2:5; // 15:11 Reserved + Uint16 FETCHPROT_GS10:1; // 16 Fetch Protection For GS10 RAM + Uint16 CPUWRPROT_GS10:1; // 17 CPU WR Protection For GS10 RAM + Uint16 DMAWRPROT_GS10:1; // 18 DMA WR Protection For GS10RAM + Uint16 rsvd3:5; // 23:19 Reserved + Uint16 FETCHPROT_GS11:1; // 24 Fetch Protection For GS11 RAM + Uint16 CPUWRPROT_GS11:1; // 25 CPU WR Protection For GS11 RAM + Uint16 DMAWRPROT_GS11:1; // 26 DMA WR Protection For GS11RAM + Uint16 rsvd4:5; // 31:27 Reserved +}; + +union GSxACCPROT2_REG { + Uint32 all; + struct GSxACCPROT2_BITS bit; +}; + +struct GSxACCPROT3_BITS { // bits description + Uint16 FETCHPROT_GS12:1; // 0 Fetch Protection For GS12 RAM + Uint16 CPUWRPROT_GS12:1; // 1 CPU WR Protection For GS12 RAM + Uint16 DMAWRPROT_GS12:1; // 2 DMA WR Protection For GS12 RAM + Uint16 rsvd1:5; // 7:3 Reserved + Uint16 FETCHPROT_GS13:1; // 8 Fetch Protection For GS13 RAM + Uint16 CPUWRPROT_GS13:1; // 9 CPU WR Protection For GS13 RAM + Uint16 DMAWRPROT_GS13:1; // 10 DMA WR Protection For GS13RAM + Uint16 rsvd2:5; // 15:11 Reserved + Uint16 FETCHPROT_GS14:1; // 16 Fetch Protection For GS14 RAM + Uint16 CPUWRPROT_GS14:1; // 17 CPU WR Protection For GS14 RAM + Uint16 DMAWRPROT_GS14:1; // 18 DMA WR Protection For GS14RAM + Uint16 rsvd3:5; // 23:19 Reserved + Uint16 FETCHPROT_GS15:1; // 24 Fetch Protection For GS15 RAM + Uint16 CPUWRPROT_GS15:1; // 25 CPU WR Protection For GS15 RAM + Uint16 DMAWRPROT_GS15:1; // 26 DMA WR Protection For GS15RAM + Uint16 rsvd4:5; // 31:27 Reserved +}; + +union GSxACCPROT3_REG { + Uint32 all; + struct GSxACCPROT3_BITS bit; +}; + +struct GSxTEST_BITS { // bits description + Uint16 TEST_GS0:2; // 1:0 Selects the different modes for GS0 RAM + Uint16 TEST_GS1:2; // 3:2 Selects the different modes for GS1 RAM + Uint16 TEST_GS2:2; // 5:4 Selects the different modes for GS2 RAM + Uint16 TEST_GS3:2; // 7:6 Selects the different modes for GS3 RAM + Uint16 TEST_GS4:2; // 9:8 Selects the different modes for GS4 RAM + Uint16 TEST_GS5:2; // 11:10 Selects the different modes for GS5 RAM + Uint16 TEST_GS6:2; // 13:12 Selects the different modes for GS6 RAM + Uint16 TEST_GS7:2; // 15:14 Selects the different modes for GS7 RAM + Uint16 TEST_GS8:2; // 17:16 Selects the different modes for GS8 RAM + Uint16 TEST_GS9:2; // 19:18 Selects the different modes for GS9 RAM + Uint16 TEST_GS10:2; // 21:20 Selects the different modes for GS10 RAM + Uint16 TEST_GS11:2; // 23:22 Selects the different modes for GS11 RAM + Uint16 TEST_GS12:2; // 25:24 Selects the different modes for GS12 RAM + Uint16 TEST_GS13:2; // 27:26 Selects the different modes for GS13 RAM + Uint16 TEST_GS14:2; // 29:28 Selects the different modes for GS14 RAM + Uint16 TEST_GS15:2; // 31:30 Selects the different modes for GS15 RAM +}; + +union GSxTEST_REG { + Uint32 all; + struct GSxTEST_BITS bit; +}; + +struct GSxINIT_BITS { // bits description + Uint16 INIT_GS0:1; // 0 RAM Initialization control for GS0 RAM. + Uint16 INIT_GS1:1; // 1 RAM Initialization control for GS1 RAM. + Uint16 INIT_GS2:1; // 2 RAM Initialization control for GS2 RAM. + Uint16 INIT_GS3:1; // 3 RAM Initialization control for GS3 RAM. + Uint16 INIT_GS4:1; // 4 RAM Initialization control for GS4 RAM. + Uint16 INIT_GS5:1; // 5 RAM Initialization control for GS5 RAM. + Uint16 INIT_GS6:1; // 6 RAM Initialization control for GS6 RAM. + Uint16 INIT_GS7:1; // 7 RAM Initialization control for GS7 RAM. + Uint16 INIT_GS8:1; // 8 RAM Initialization control for GS8 RAM. + Uint16 INIT_GS9:1; // 9 RAM Initialization control for GS9 RAM. + Uint16 INIT_GS10:1; // 10 RAM Initialization control for GS10 RAM. + Uint16 INIT_GS11:1; // 11 RAM Initialization control for GS11 RAM. + Uint16 INIT_GS12:1; // 12 RAM Initialization control for GS12 RAM. + Uint16 INIT_GS13:1; // 13 RAM Initialization control for GS13 RAM. + Uint16 INIT_GS14:1; // 14 RAM Initialization control for GS14 RAM. + Uint16 INIT_GS15:1; // 15 RAM Initialization control for GS15 RAM. + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union GSxINIT_REG { + Uint32 all; + struct GSxINIT_BITS bit; +}; + +struct GSxINITDONE_BITS { // bits description + Uint16 INITDONE_GS0:1; // 0 RAM Initialization status for GS0 RAM. + Uint16 INITDONE_GS1:1; // 1 RAM Initialization status for GS1 RAM. + Uint16 INITDONE_GS2:1; // 2 RAM Initialization status for GS2 RAM. + Uint16 INITDONE_GS3:1; // 3 RAM Initialization status for GS3 RAM. + Uint16 INITDONE_GS4:1; // 4 RAM Initialization status for GS4 RAM. + Uint16 INITDONE_GS5:1; // 5 RAM Initialization status for GS5 RAM. + Uint16 INITDONE_GS6:1; // 6 RAM Initialization status for GS6 RAM. + Uint16 INITDONE_GS7:1; // 7 RAM Initialization status for GS7 RAM. + Uint16 INITDONE_GS8:1; // 8 RAM Initialization status for GS8 RAM. + Uint16 INITDONE_GS9:1; // 9 RAM Initialization status for GS9 RAM. + Uint16 INITDONE_GS10:1; // 10 RAM Initialization status for GS10 RAM. + Uint16 INITDONE_GS11:1; // 11 RAM Initialization status for GS11 RAM. + Uint16 INITDONE_GS12:1; // 12 RAM Initialization status for GS12 RAM. + Uint16 INITDONE_GS13:1; // 13 RAM Initialization status for GS13 RAM. + Uint16 INITDONE_GS14:1; // 14 RAM Initialization status for GS14 RAM. + Uint16 INITDONE_GS15:1; // 15 RAM Initialization status for GS15 RAM. + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union GSxINITDONE_REG { + Uint32 all; + struct GSxINITDONE_BITS bit; +}; + +struct MSGxTEST_BITS { // bits description + Uint16 TEST_CPUTOCPU:2; // 1:0 CPU to CPU Mode Select + Uint16 TEST_CPUTOCLA1:2; // 3:2 CPU to CLA1 MSG RAM Mode Select + Uint16 TEST_CLA1TOCPU:2; // 5:4 CLA1 to CPU MSG RAM Mode Select + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 rsvd2:2; // 9:8 Reserved + Uint16 rsvd3:6; // 15:10 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union MSGxTEST_REG { + Uint32 all; + struct MSGxTEST_BITS bit; +}; + +struct MSGxINIT_BITS { // bits description + Uint16 INIT_CPUTOCPU:1; // 0 Initialization control for CPU to CPU MSG RAM + Uint16 INIT_CPUTOCLA1:1; // 1 Initialization control for CPUTOCLA1 MSG RAM + Uint16 INIT_CLA1TOCPU:1; // 2 Initialization control for CLA1TOCPU MSG RAM + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:1; // 4 Reserved + Uint16 rsvd3:11; // 15:5 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union MSGxINIT_REG { + Uint32 all; + struct MSGxINIT_BITS bit; +}; + +struct MSGxINITDONE_BITS { // bits description + Uint16 INITDONE_CPUTOCPU:1; // 0 Initialization status for CPU to CPU MSG RAM + Uint16 INITDONE_CPUTOCLA1:1; // 1 Initialization status for CPU to CLA1 MSG RAM + Uint16 INITDONE_CLA1TOCPU:1; // 2 Initialization status for CLA1 to CPU MSG RAM + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:1; // 4 Reserved + Uint16 rsvd3:11; // 15:5 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union MSGxINITDONE_REG { + Uint32 all; + struct MSGxINITDONE_BITS bit; +}; + +struct MEM_CFG_REGS { + union DxLOCK_REG DxLOCK; // Dedicated RAM Config Lock Register + union DxCOMMIT_REG DxCOMMIT; // Dedicated RAM Config Lock Commit Register + Uint16 rsvd1[4]; // Reserved + union DxACCPROT0_REG DxACCPROT0; // Dedicated RAM Config Register + Uint16 rsvd2[6]; // Reserved + union DxTEST_REG DxTEST; // Dedicated RAM TEST Register + union DxINIT_REG DxINIT; // Dedicated RAM Init Register + union DxINITDONE_REG DxINITDONE; // Dedicated RAM InitDone Status Register + Uint16 rsvd3[10]; // Reserved + union LSxLOCK_REG LSxLOCK; // Local Shared RAM Config Lock Register + union LSxCOMMIT_REG LSxCOMMIT; // Local Shared RAM Config Lock Commit Register + union LSxMSEL_REG LSxMSEL; // Local Shared RAM Master Sel Register + union LSxCLAPGM_REG LSxCLAPGM; // Local Shared RAM Prog/Exe control Register + union LSxACCPROT0_REG LSxACCPROT0; // Local Shared RAM Config Register 0 + union LSxACCPROT1_REG LSxACCPROT1; // Local Shared RAM Config Register 1 + Uint16 rsvd4[4]; // Reserved + union LSxTEST_REG LSxTEST; // Local Shared RAM TEST Register + union LSxINIT_REG LSxINIT; // Local Shared RAM Init Register + union LSxINITDONE_REG LSxINITDONE; // Local Shared RAM InitDone Status Register + Uint16 rsvd5[10]; // Reserved + union GSxLOCK_REG GSxLOCK; // Global Shared RAM Config Lock Register + union GSxCOMMIT_REG GSxCOMMIT; // Global Shared RAM Config Lock Commit Register + union GSxMSEL_REG GSxMSEL; // Global Shared RAM Master Sel Register + Uint16 rsvd6[2]; // Reserved + union GSxACCPROT0_REG GSxACCPROT0; // Global Shared RAM Config Register 0 + union GSxACCPROT1_REG GSxACCPROT1; // Global Shared RAM Config Register 1 + union GSxACCPROT2_REG GSxACCPROT2; // Global Shared RAM Config Register 2 + union GSxACCPROT3_REG GSxACCPROT3; // Global Shared RAM Config Register 3 + union GSxTEST_REG GSxTEST; // Global Shared RAM TEST Register + union GSxINIT_REG GSxINIT; // Global Shared RAM Init Register + union GSxINITDONE_REG GSxINITDONE; // Global Shared RAM InitDone Status Register + Uint16 rsvd7[26]; // Reserved + union MSGxTEST_REG MSGxTEST; // Message RAM TEST Register + union MSGxINIT_REG MSGxINIT; // Message RAM Init Register + union MSGxINITDONE_REG MSGxINITDONE; // Message RAM InitDone Status Register + Uint16 rsvd8[10]; // Reserved +}; + +struct EMIF1LOCK_BITS { // bits description + Uint16 LOCK_EMIF1:1; // 0 EMIF1 access protection and master select fields lock bit + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF1LOCK_REG { + Uint32 all; + struct EMIF1LOCK_BITS bit; +}; + +struct EMIF1COMMIT_BITS { // bits description + Uint16 COMMIT_EMIF1:1; // 0 EMIF1 access protection and master select permanent lock + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF1COMMIT_REG { + Uint32 all; + struct EMIF1COMMIT_BITS bit; +}; + +struct EMIF1MSEL_BITS { // bits description + Uint16 MSEL_EMIF1:2; // 1:0 Master Select for EMIF1. + Uint16 rsvd1:2; // 3:2 Reserved + Uint32 KEY:28; // 31:4 KEY to enable the write into MSEL_EMIF1 bits +}; + +union EMIF1MSEL_REG { + Uint32 all; + struct EMIF1MSEL_BITS bit; +}; + +struct EMIF1ACCPROT0_BITS { // bits description + Uint16 FETCHPROT_EMIF1:1; // 0 Fetch Protection For EMIF1 + Uint16 CPUWRPROT_EMIF1:1; // 1 CPU WR Protection For EMIF1 + Uint16 DMAWRPROT_EMIF1:1; // 2 DMA WR Protection For EMIF1 + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF1ACCPROT0_REG { + Uint32 all; + struct EMIF1ACCPROT0_BITS bit; +}; + +struct EMIF1_CONFIG_REGS { + union EMIF1LOCK_REG EMIF1LOCK; // EMIF1 Config Lock Register + union EMIF1COMMIT_REG EMIF1COMMIT; // EMIF1 Config Lock Commit Register + union EMIF1MSEL_REG EMIF1MSEL; // EMIF1 Master Sel Register + Uint16 rsvd1[2]; // Reserved + union EMIF1ACCPROT0_REG EMIF1ACCPROT0; // EMIF1 Config Register 0 + Uint16 rsvd2[22]; // Reserved +}; + +struct EMIF2LOCK_BITS { // bits description + Uint16 LOCK_EMIF2:1; // 0 EMIF2 access protection and master select permanent lock + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF2LOCK_REG { + Uint32 all; + struct EMIF2LOCK_BITS bit; +}; + +struct EMIF2COMMIT_BITS { // bits description + Uint16 COMMIT_EMIF2:1; // 0 EMIF2 access protection and master select permanent lock + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF2COMMIT_REG { + Uint32 all; + struct EMIF2COMMIT_BITS bit; +}; + +struct EMIF2ACCPROT0_BITS { // bits description + Uint16 FETCHPROT_EMIF2:1; // 0 Fetch Protection For EMIF2 + Uint16 CPUWRPROT_EMIF2:1; // 1 CPU WR Protection For EMIF2 + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union EMIF2ACCPROT0_REG { + Uint32 all; + struct EMIF2ACCPROT0_BITS bit; +}; + +struct EMIF2_CONFIG_REGS { + union EMIF2LOCK_REG EMIF2LOCK; // EMIF2 Config Lock Register + union EMIF2COMMIT_REG EMIF2COMMIT; // EMIF2 Config Lock Commit Register + Uint16 rsvd1[4]; // Reserved + union EMIF2ACCPROT0_REG EMIF2ACCPROT0; // EMIF2 Config Register 0 + Uint16 rsvd2[22]; // Reserved +}; + +struct NMAVFLG_BITS { // bits description + Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag + Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag + Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag + Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag + Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag + Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag + Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 rsvd3:1; // 9 Reserved + Uint16 rsvd4:6; // 15:10 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union NMAVFLG_REG { + Uint32 all; + struct NMAVFLG_BITS bit; +}; + +struct NMAVSET_BITS { // bits description + Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Set + Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Set + Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Set + Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Set + Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Set + Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Set + Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Set + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 rsvd3:1; // 9 Reserved + Uint16 rsvd4:6; // 15:10 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union NMAVSET_REG { + Uint32 all; + struct NMAVSET_BITS bit; +}; + +struct NMAVCLR_BITS { // bits description + Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Flag Clear + Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Flag Clear + Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Flag Clear + Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Flag Clear + Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Flag Clear + Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Flag Clear + Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Flag Clear + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 rsvd3:1; // 9 Reserved + Uint16 rsvd4:6; // 15:10 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union NMAVCLR_REG { + Uint32 all; + struct NMAVCLR_BITS bit; +}; + +struct NMAVINTEN_BITS { // bits description + Uint16 CPUREAD:1; // 0 Non Master CPU Read Access Violation Interrupt Enable + Uint16 CPUWRITE:1; // 1 Non Master CPU Write Access Violation Interrupt Enable + Uint16 CPUFETCH:1; // 2 Non Master CPU Fetch Access Violation Interrupt Enable + Uint16 DMAWRITE:1; // 3 Non Master DMA Write Access Violation Interrupt Enable + Uint16 CLA1READ:1; // 4 Non Master CLA1 Read Access Violation Interrupt Enable + Uint16 CLA1WRITE:1; // 5 Non Master CLA1 Write Access Violation Interrupt Enable + Uint16 CLA1FETCH:1; // 6 Non Master CLA1 Fetch Access Violation Interrupt Enable + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 rsvd3:1; // 9 Reserved + Uint16 rsvd4:6; // 15:10 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union NMAVINTEN_REG { + Uint32 all; + struct NMAVINTEN_BITS bit; +}; + +struct MAVFLG_BITS { // bits description + Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag + Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag + Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union MAVFLG_REG { + Uint32 all; + struct MAVFLG_BITS bit; +}; + +struct MAVSET_BITS { // bits description + Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Set + Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Set + Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Set + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union MAVSET_REG { + Uint32 all; + struct MAVSET_BITS bit; +}; + +struct MAVCLR_BITS { // bits description + Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Flag Clear + Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Flag Clear + Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Flag Clear + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union MAVCLR_REG { + Uint32 all; + struct MAVCLR_BITS bit; +}; + +struct MAVINTEN_BITS { // bits description + Uint16 CPUFETCH:1; // 0 Master CPU Fetch Access Violation Interrupt Enable + Uint16 CPUWRITE:1; // 1 Master CPU Write Access Violation Interrupt Enable + Uint16 DMAWRITE:1; // 2 Master DMA Write Access Violation Interrupt Enable + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union MAVINTEN_REG { + Uint32 all; + struct MAVINTEN_BITS bit; +}; + +struct ACCESS_PROTECTION_REGS { + union NMAVFLG_REG NMAVFLG; // Non-Master Access Violation Flag Register + union NMAVSET_REG NMAVSET; // Non-Master Access Violation Flag Set Register + union NMAVCLR_REG NMAVCLR; // Non-Master Access Violation Flag Clear Register + union NMAVINTEN_REG NMAVINTEN; // Non-Master Access Violation Interrupt Enable Register + Uint32 NMCPURDAVADDR; // Non-Master CPU Read Access Violation Address + Uint32 NMCPUWRAVADDR; // Non-Master CPU Write Access Violation Address + Uint32 NMCPUFAVADDR; // Non-Master CPU Fetch Access Violation Address + Uint32 NMDMAWRAVADDR; // Non-Master DMA Write Access Violation Address + Uint32 NMCLA1RDAVADDR; // Non-Master CLA1 Read Access Violation Address + Uint32 NMCLA1WRAVADDR; // Non-Master CLA1 Write Access Violation Address + Uint32 NMCLA1FAVADDR; // Non-Master CLA1 Fetch Access Violation Address + Uint16 rsvd1[10]; // Reserved + union MAVFLG_REG MAVFLG; // Master Access Violation Flag Register + union MAVSET_REG MAVSET; // Master Access Violation Flag Set Register + union MAVCLR_REG MAVCLR; // Master Access Violation Flag Clear Register + union MAVINTEN_REG MAVINTEN; // Master Access Violation Interrupt Enable Register + Uint32 MCPUFAVADDR; // Master CPU Fetch Access Violation Address + Uint32 MCPUWRAVADDR; // Master CPU Write Access Violation Address + Uint32 MDMAWRAVADDR; // Master DMA Write Access Violation Address + Uint16 rsvd2[18]; // Reserved +}; + +struct UCERRFLG_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag + Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag + Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union UCERRFLG_REG { + Uint32 all; + struct UCERRFLG_BITS bit; +}; + +struct UCERRSET_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Set + Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Set + Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Set + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union UCERRSET_REG { + Uint32 all; + struct UCERRSET_BITS bit; +}; + +struct UCERRCLR_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Uncorrectable Read Error Flag Clear + Uint16 DMARDERR:1; // 1 DMA Uncorrectable Read Error Flag Clear + Uint16 CLA1RDERR:1; // 2 CLA1 Uncorrectable Read Error Flag Clear + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union UCERRCLR_REG { + Uint32 all; + struct UCERRCLR_BITS bit; +}; + +struct CERRFLG_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag + Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag + Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CERRFLG_REG { + Uint32 all; + struct CERRFLG_BITS bit; +}; + +struct CERRSET_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Set + Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Set + Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Set + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CERRSET_REG { + Uint32 all; + struct CERRSET_BITS bit; +}; + +struct CERRCLR_BITS { // bits description + Uint16 CPURDERR:1; // 0 CPU Correctable Read Error Flag Clear + Uint16 DMARDERR:1; // 1 DMA Correctable Read Error Flag Clear + Uint16 CLA1RDERR:1; // 2 CLA1 Correctable Read Error Flag Clear + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CERRCLR_REG { + Uint32 all; + struct CERRCLR_BITS bit; +}; + +struct CEINTFLG_BITS { // bits description + Uint16 CEINTFLAG:1; // 0 Total corrected error count exceeded threshold flag. + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CEINTFLG_REG { + Uint32 all; + struct CEINTFLG_BITS bit; +}; + +struct CEINTCLR_BITS { // bits description + Uint16 CEINTCLR:1; // 0 CPU Corrected Error Threshold Exceeded Error Clear. + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CEINTCLR_REG { + Uint32 all; + struct CEINTCLR_BITS bit; +}; + +struct CEINTSET_BITS { // bits description + Uint16 CEINTSET:1; // 0 Total corrected error count exceeded flag set. + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CEINTSET_REG { + Uint32 all; + struct CEINTSET_BITS bit; +}; + +struct CEINTEN_BITS { // bits description + Uint16 CEINTEN:1; // 0 CPU/DMA Correctable Error Interrupt Enable. + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CEINTEN_REG { + Uint32 all; + struct CEINTEN_BITS bit; +}; + +struct MEMORY_ERROR_REGS { + union UCERRFLG_REG UCERRFLG; // Uncorrectable Error Flag Register + union UCERRSET_REG UCERRSET; // Uncorrectable Error Flag Set Register + union UCERRCLR_REG UCERRCLR; // Uncorrectable Error Flag Clear Register + Uint32 UCCPUREADDR; // Uncorrectable CPU Read Error Address + Uint32 UCDMAREADDR; // Uncorrectable DMA Read Error Address + Uint32 UCCLA1READDR; // Uncorrectable CLA1 Read Error Address + Uint16 rsvd1[20]; // Reserved + union CERRFLG_REG CERRFLG; // Correctable Error Flag Register + union CERRSET_REG CERRSET; // Correctable Error Flag Set Register + union CERRCLR_REG CERRCLR; // Correctable Error Flag Clear Register + Uint32 CCPUREADDR; // Correctable CPU Read Error Address + Uint16 rsvd2[6]; // Reserved + Uint32 CERRCNT; // Correctable Error Count Register + Uint32 CERRTHRES; // Correctable Error Threshold Value Register + union CEINTFLG_REG CEINTFLG; // Correctable Error Interrupt Flag Status Register + union CEINTCLR_REG CEINTCLR; // Correctable Error Interrupt Flag Clear Register + union CEINTSET_REG CEINTSET; // Correctable Error Interrupt Flag Set Register + union CEINTEN_REG CEINTEN; // Correctable Error Interrupt Enable Register + Uint16 rsvd3[6]; // Reserved +}; + +struct ROMWAITSTATE_BITS { // bits description + Uint16 WSDISABLE:1; // 0 ROM Wait State Enable/Disable Control + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union ROMWAITSTATE_REG { + Uint32 all; + struct ROMWAITSTATE_BITS bit; +}; + +struct ROM_WAIT_STATE_REGS { + union ROMWAITSTATE_REG ROMWAITSTATE; // ROM Wait State Configuration Register +}; + +struct ROMPREFETCH_BITS { // bits description + Uint16 PFENABLE:1; // 0 ROM Prefetch Enable/Disable Control + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union ROMPREFETCH_REG { + Uint32 all; + struct ROMPREFETCH_BITS bit; +}; + +struct ROM_PREFETCH_REGS { + union ROMPREFETCH_REG ROMPREFETCH; // ROM Prefetch Configuration Register +}; + +//--------------------------------------------------------------------------- +// MEMCONFIG External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct ROM_PREFETCH_REGS RomPrefetchRegs; +extern volatile struct MEM_CFG_REGS MemCfgRegs; +extern volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; +extern volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs; +extern volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; +extern volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; +extern volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs; +#endif +#ifdef CPU2 +extern volatile struct MEM_CFG_REGS MemCfgRegs; +extern volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; +extern volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; +extern volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_nmiintrupt.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_nmiintrupt.h new file mode 100644 index 0000000000..0bbe21fe21 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_nmiintrupt.h @@ -0,0 +1,175 @@ +//########################################################################### +// +// FILE: F2837xD_nmiintrupt.h +// +// TITLE: NMIINTRUPT Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_NMIINTRUPT_H__ +#define __F2837xD_NMIINTRUPT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// NMIINTRUPT Individual Register Bit Definitions: + +struct NMICFG_BITS { // bits description + Uint16 NMIE:1; // 0 Global NMI Enable + Uint16 rsvd1:15; // 15:1 Reserved +}; + +union NMICFG_REG { + Uint16 all; + struct NMICFG_BITS bit; +}; + +struct NMIFLG_BITS { // bits description + Uint16 NMIINT:1; // 0 NMI Interrupt Flag + Uint16 CLOCKFAIL:1; // 1 Clock Fail Interrupt Flag + Uint16 RAMUNCERR:1; // 2 RAM Uncorrectable Error NMI Flag + Uint16 FLUNCERR:1; // 3 Flash Uncorrectable Error NMI Flag + Uint16 CPU1HWBISTERR:1; // 4 HW BIST Error NMI Flag + Uint16 CPU2HWBISTERR:1; // 5 HW BIST Error NMI Flag + Uint16 PIEVECTERR:1; // 6 PIE Vector Fetch Error Flag + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 CPU2WDRSn:1; // 9 CPU2 WDRSn Reset Indication Flag + Uint16 CPU2NMIWDRSn:1; // 10 CPU2 NMIWDRSn Reset Indication Flag + Uint16 rsvd3:1; // 11 Reserved + Uint16 rsvd4:4; // 15:12 Reserved +}; + +union NMIFLG_REG { + Uint16 all; + struct NMIFLG_BITS bit; +}; + +struct NMIFLGCLR_BITS { // bits description + Uint16 NMIINT:1; // 0 NMIINT Flag Clear + Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Clear + Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Clear + Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Clear + Uint16 CPU1HWBISTERR:1; // 4 CPU1HWBISTERR Flag Clear + Uint16 CPU2HWBISTERR:1; // 5 CPU2HWBISTERR Flag Clear + Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Clear + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:1; // 8 Reserved + Uint16 CPU2WDRSn:1; // 9 CPU2WDRSn Flag Clear + Uint16 CPU2NMIWDRSn:1; // 10 CPU2NMIWDRSn Flag Clear + Uint16 OVF:1; // 11 OVF Flag Clear + Uint16 rsvd3:4; // 15:12 Reserved +}; + +union NMIFLGCLR_REG { + Uint16 all; + struct NMIFLGCLR_BITS bit; +}; + +struct NMIFLGFRC_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CLOCKFAIL:1; // 1 CLOCKFAIL Flag Force + Uint16 RAMUNCERR:1; // 2 RAMUNCERR Flag Force + Uint16 FLUNCERR:1; // 3 FLUNCERR Flag Force + Uint16 CPU1HWBISTERR:1; // 4 CPU1HWBISTERR Flag Force + Uint16 CPU2HWBISTERR:1; // 5 CPU2HWBISTERR Flag Force + Uint16 PIEVECTERR:1; // 6 PIEVECTERR Flag Force + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 CPU2WDRSn:1; // 9 CPU2WDRSn Flag Force + Uint16 CPU2NMIWDRSn:1; // 10 CPU2NMIWDRSn Flag Force + Uint16 OVF:1; // 11 OVF Flag Force + Uint16 rsvd4:4; // 15:12 Reserved +}; + +union NMIFLGFRC_REG { + Uint16 all; + struct NMIFLGFRC_BITS bit; +}; + +struct NMISHDFLG_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 CLOCKFAIL:1; // 1 Shadow CLOCKFAIL Flag + Uint16 RAMUNCERR:1; // 2 Shadow RAMUNCERR Flag + Uint16 FLUNCERR:1; // 3 Shadow FLUNCERR Flag + Uint16 CPU1HWBISTERR:1; // 4 Shadow CPU1HWBISTERR Flag + Uint16 CPU2HWBISTERR:1; // 5 Shadow CPU2HWBISTERR Flag + Uint16 PIEVECTERR:1; // 6 Shadow PIEVECTERR Flag + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 CPU2WDRSn:1; // 9 Shadow CPU2WDRSn Flag + Uint16 CPU2NMIWDRSn:1; // 10 Shadow CPU2NMIWDRSn Flag + Uint16 OVF:1; // 11 Shadow OVF Flag + Uint16 rsvd4:4; // 15:12 Reserved +}; + +union NMISHDFLG_REG { + Uint16 all; + struct NMISHDFLG_BITS bit; +}; + +struct NMI_INTRUPT_REGS { + union NMICFG_REG NMICFG; // NMI Configuration Register + union NMIFLG_REG NMIFLG; // NMI Flag Register (XRSn Clear) + union NMIFLGCLR_REG NMIFLGCLR; // NMI Flag Clear Register + union NMIFLGFRC_REG NMIFLGFRC; // NMI Flag Force Register + Uint16 NMIWDCNT; // NMI Watchdog Counter Register + Uint16 NMIWDPRD; // NMI Watchdog Period Register + union NMISHDFLG_REG NMISHDFLG; // NMI Shadow Flag Register +}; + +//--------------------------------------------------------------------------- +// NMIINTRUPT External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; +#endif +#ifdef CPU2 +extern volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_output_xbar.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_output_xbar.h new file mode 100644 index 0000000000..aad7cada65 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_output_xbar.h @@ -0,0 +1,907 @@ +//########################################################################### +// +// FILE: F2837xD_output_xbar.h +// +// TITLE: OUTPUT_XBAR Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_OUTPUT_XBAR_H__ +#define __F2837xD_OUTPUT_XBAR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// OUTPUT_XBAR Individual Register Bit Definitions: + +struct OUTPUT1MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT1 of OUTPUT-XBAR +}; + +union OUTPUT1MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT1MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT1MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT1 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT1 of OUTPUT-XBAR +}; + +union OUTPUT1MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT1MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT2MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT2 of OUTPUT-XBAR +}; + +union OUTPUT2MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT2MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT2MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT2 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT2 of OUTPUT-XBAR +}; + +union OUTPUT2MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT2MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT3MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT3 of OUTPUT-XBAR +}; + +union OUTPUT3MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT3MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT3MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT3 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT3 of OUTPUT-XBAR +}; + +union OUTPUT3MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT3MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT4MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT4 of OUTPUT-XBAR +}; + +union OUTPUT4MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT4MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT4MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT4 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT4 of OUTPUT-XBAR +}; + +union OUTPUT4MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT4MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT5MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT5 of OUTPUT-XBAR +}; + +union OUTPUT5MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT5MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT5MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT5 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT5 of OUTPUT-XBAR +}; + +union OUTPUT5MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT5MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT6MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT6 of OUTPUT-XBAR +}; + +union OUTPUT6MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT6MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT6MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT6 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT6 of OUTPUT-XBAR +}; + +union OUTPUT6MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT6MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT7MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT7 of OUTPUT-XBAR +}; + +union OUTPUT7MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT7MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT7MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT7 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT7 of OUTPUT-XBAR +}; + +union OUTPUT7MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT7MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT8MUX0TO15CFG_BITS { // bits description + Uint16 MUX0:2; // 1:0 Mux0 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX1:2; // 3:2 Mux1 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX2:2; // 5:4 Mux2 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX3:2; // 7:6 Mux3 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX4:2; // 9:8 Mux4 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX5:2; // 11:10 Mux5 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX6:2; // 13:12 Mux6 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX7:2; // 15:14 Mux7 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX8:2; // 17:16 Mux8 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX9:2; // 19:18 Mux9 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX10:2; // 21:20 Mux10 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX11:2; // 23:22 Mux11 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX12:2; // 25:24 Mux12 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX13:2; // 27:26 Mux13 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX14:2; // 29:28 Mux14 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX15:2; // 31:30 Mux15 Configuration for OUTPUT8 of OUTPUT-XBAR +}; + +union OUTPUT8MUX0TO15CFG_REG { + Uint32 all; + struct OUTPUT8MUX0TO15CFG_BITS bit; +}; + +struct OUTPUT8MUX16TO31CFG_BITS { // bits description + Uint16 MUX16:2; // 1:0 Mux16 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX17:2; // 3:2 Mux17 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX18:2; // 5:4 Mux18 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX19:2; // 7:6 Mux19 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX20:2; // 9:8 Mux20 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX21:2; // 11:10 Mux21 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX22:2; // 13:12 Mux22 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX23:2; // 15:14 Mux23 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX24:2; // 17:16 Mux24 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX25:2; // 19:18 Mux25 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX26:2; // 21:20 Mux26 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX27:2; // 23:22 Mux27 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX28:2; // 25:24 Mux28 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX29:2; // 27:26 Mux29 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX30:2; // 29:28 Mux30 Configuration for OUTPUT8 of OUTPUT-XBAR + Uint16 MUX31:2; // 31:30 Mux31 Configuration for OUTPUT8 of OUTPUT-XBAR +}; + +union OUTPUT8MUX16TO31CFG_REG { + Uint32 all; + struct OUTPUT8MUX16TO31CFG_BITS bit; +}; + +struct OUTPUT1MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 Mux0 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT1 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT1 of OUTPUT-XBAR +}; + +union OUTPUT1MUXENABLE_REG { + Uint32 all; + struct OUTPUT1MUXENABLE_BITS bit; +}; + +struct OUTPUT2MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT2 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT2 of OUTPUT-XBAR +}; + +union OUTPUT2MUXENABLE_REG { + Uint32 all; + struct OUTPUT2MUXENABLE_BITS bit; +}; + +struct OUTPUT3MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT3 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT3 of OUTPUT-XBAR +}; + +union OUTPUT3MUXENABLE_REG { + Uint32 all; + struct OUTPUT3MUXENABLE_BITS bit; +}; + +struct OUTPUT4MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT4 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT4 of OUTPUT-XBAR +}; + +union OUTPUT4MUXENABLE_REG { + Uint32 all; + struct OUTPUT4MUXENABLE_BITS bit; +}; + +struct OUTPUT5MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT5 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT5 of OUTPUT-XBAR +}; + +union OUTPUT5MUXENABLE_REG { + Uint32 all; + struct OUTPUT5MUXENABLE_BITS bit; +}; + +struct OUTPUT6MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to OUTPUT6 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT6 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT6 of OUTPUT-XBAR +}; + +union OUTPUT6MUXENABLE_REG { + Uint32 all; + struct OUTPUT6MUXENABLE_BITS bit; +}; + +struct OUTPUT7MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT7 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT7 of OUTPUT-XBAR +}; + +union OUTPUT7MUXENABLE_REG { + Uint32 all; + struct OUTPUT7MUXENABLE_BITS bit; +}; + +struct OUTPUT8MUXENABLE_BITS { // bits description + Uint16 MUX0:1; // 0 mux0 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX1:1; // 1 Mux1 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX2:1; // 2 Mux2 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX3:1; // 3 Mux3 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX4:1; // 4 Mux4 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX5:1; // 5 Mux5 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX6:1; // 6 Mux6 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX7:1; // 7 Mux7 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX8:1; // 8 Mux8 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX9:1; // 9 Mux9 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX10:1; // 10 Mux10 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX11:1; // 11 Mux11 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX12:1; // 12 Mux12 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX13:1; // 13 Mux13 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX14:1; // 14 Mux14 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX15:1; // 15 Mux15 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX16:1; // 16 Mux16 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX17:1; // 17 Mux17 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX18:1; // 18 Mux18 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX19:1; // 19 Mux19 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX20:1; // 20 Mux20 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX21:1; // 21 Mux21 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX22:1; // 22 Mux22 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX23:1; // 23 Mux23 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX24:1; // 24 Mux24 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX25:1; // 25 Mux25 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX26:1; // 26 Mux26 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX27:1; // 27 Mux27 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX28:1; // 28 Mux28 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX29:1; // 29 Mux29 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX30:1; // 30 Mux30 to drive OUTPUT8 of OUTPUT-XBAR + Uint16 MUX31:1; // 31 Mux31 to drive OUTPUT8 of OUTPUT-XBAR +}; + +union OUTPUT8MUXENABLE_REG { + Uint32 all; + struct OUTPUT8MUXENABLE_BITS bit; +}; + +struct OUTPUTLATCH_BITS { // bits description + Uint16 OUTPUT1:1; // 0 Records the OUTPUT1 of OUTPUT-XBAR + Uint16 OUTPUT2:1; // 1 Records the OUTPUT2 of OUTPUT-XBAR + Uint16 OUTPUT3:1; // 2 Records the OUTPUT3 of OUTPUT-XBAR + Uint16 OUTPUT4:1; // 3 Records the OUTPUT4 of OUTPUT-XBAR + Uint16 OUTPUT5:1; // 4 Records the OUTPUT5 of OUTPUT-XBAR + Uint16 OUTPUT6:1; // 5 Records the OUTPUT6 of OUTPUT-XBAR + Uint16 OUTPUT7:1; // 6 Records the OUTPUT7 of OUTPUT-XBAR + Uint16 OUTPUT8:1; // 7 Records the OUTPUT8 of OUTPUT-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union OUTPUTLATCH_REG { + Uint32 all; + struct OUTPUTLATCH_BITS bit; +}; + +struct OUTPUTLATCHCLR_BITS { // bits description + Uint16 OUTPUT1:1; // 0 Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR + Uint16 OUTPUT2:1; // 1 Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR + Uint16 OUTPUT3:1; // 2 Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR + Uint16 OUTPUT4:1; // 3 Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR + Uint16 OUTPUT5:1; // 4 Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR + Uint16 OUTPUT6:1; // 5 Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR + Uint16 OUTPUT7:1; // 6 Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR + Uint16 OUTPUT8:1; // 7 Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union OUTPUTLATCHCLR_REG { + Uint32 all; + struct OUTPUTLATCHCLR_BITS bit; +}; + +struct OUTPUTLATCHFRC_BITS { // bits description + Uint16 OUTPUT1:1; // 0 Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR + Uint16 OUTPUT2:1; // 1 Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR + Uint16 OUTPUT3:1; // 2 Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR + Uint16 OUTPUT4:1; // 3 Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR + Uint16 OUTPUT5:1; // 4 Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR + Uint16 OUTPUT6:1; // 5 Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR + Uint16 OUTPUT7:1; // 6 Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR + Uint16 OUTPUT8:1; // 7 Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union OUTPUTLATCHFRC_REG { + Uint32 all; + struct OUTPUTLATCHFRC_BITS bit; +}; + +struct OUTPUTLATCHENABLE_BITS { // bits description + Uint16 OUTPUT1:1; // 0 Selects the output latch to drive OUTPUT1 for OUTPUT-XBAR + Uint16 OUTPUT2:1; // 1 Selects the output latch to drive OUTPUT2 for OUTPUT-XBAR + Uint16 OUTPUT3:1; // 2 Selects the output latch to drive OUTPUT3 for OUTPUT-XBAR + Uint16 OUTPUT4:1; // 3 Selects the output latch to drive OUTPUT4 for OUTPUT-XBAR + Uint16 OUTPUT5:1; // 4 Selects the output latch to drive OUTPUT5 for OUTPUT-XBAR + Uint16 OUTPUT6:1; // 5 Selects the output latch to drive OUTPUT6 for OUTPUT-XBAR + Uint16 OUTPUT7:1; // 6 Selects the output latch to drive OUTPUT7 for OUTPUT-XBAR + Uint16 OUTPUT8:1; // 7 Selects the output latch to drive OUTPUT8 for OUTPUT-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union OUTPUTLATCHENABLE_REG { + Uint32 all; + struct OUTPUTLATCHENABLE_BITS bit; +}; + +struct OUTPUTINV_BITS { // bits description + Uint16 OUTPUT1:1; // 0 Selects polarity for OUTPUT1 of OUTPUT-XBAR + Uint16 OUTPUT2:1; // 1 Selects polarity for OUTPUT2 of OUTPUT-XBAR + Uint16 OUTPUT3:1; // 2 Selects polarity for OUTPUT3 of OUTPUT-XBAR + Uint16 OUTPUT4:1; // 3 Selects polarity for OUTPUT4 of OUTPUT-XBAR + Uint16 OUTPUT5:1; // 4 Selects polarity for OUTPUT5 of OUTPUT-XBAR + Uint16 OUTPUT6:1; // 5 Selects polarity for OUTPUT6 of OUTPUT-XBAR + Uint16 OUTPUT7:1; // 6 Selects polarity for OUTPUT7 of OUTPUT-XBAR + Uint16 OUTPUT8:1; // 7 Selects polarity for OUTPUT8 of OUTPUT-XBAR + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union OUTPUTINV_REG { + Uint32 all; + struct OUTPUTINV_BITS bit; +}; + +struct OUTPUTLOCK_BITS { // bits description + Uint16 LOCK:1; // 0 Locks the configuration for OUTPUT-XBAR + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 KEY:16; // 31:16 Write Protection KEY +}; + +union OUTPUTLOCK_REG { + Uint32 all; + struct OUTPUTLOCK_BITS bit; +}; + +struct OUTPUT_XBAR_REGS { + union OUTPUT1MUX0TO15CFG_REG OUTPUT1MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 1 + union OUTPUT1MUX16TO31CFG_REG OUTPUT1MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 1 + union OUTPUT2MUX0TO15CFG_REG OUTPUT2MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 2 + union OUTPUT2MUX16TO31CFG_REG OUTPUT2MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 2 + union OUTPUT3MUX0TO15CFG_REG OUTPUT3MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 3 + union OUTPUT3MUX16TO31CFG_REG OUTPUT3MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 3 + union OUTPUT4MUX0TO15CFG_REG OUTPUT4MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 4 + union OUTPUT4MUX16TO31CFG_REG OUTPUT4MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 4 + union OUTPUT5MUX0TO15CFG_REG OUTPUT5MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 5 + union OUTPUT5MUX16TO31CFG_REG OUTPUT5MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 5 + union OUTPUT6MUX0TO15CFG_REG OUTPUT6MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 6 + union OUTPUT6MUX16TO31CFG_REG OUTPUT6MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 6 + union OUTPUT7MUX0TO15CFG_REG OUTPUT7MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 7 + union OUTPUT7MUX16TO31CFG_REG OUTPUT7MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 7 + union OUTPUT8MUX0TO15CFG_REG OUTPUT8MUX0TO15CFG; // Output X-BAR Mux Configuration for Output 8 + union OUTPUT8MUX16TO31CFG_REG OUTPUT8MUX16TO31CFG; // Output X-BAR Mux Configuration for Output 8 + union OUTPUT1MUXENABLE_REG OUTPUT1MUXENABLE; // Output X-BAR Mux Enable for Output 1 + union OUTPUT2MUXENABLE_REG OUTPUT2MUXENABLE; // Output X-BAR Mux Enable for Output 2 + union OUTPUT3MUXENABLE_REG OUTPUT3MUXENABLE; // Output X-BAR Mux Enable for Output 3 + union OUTPUT4MUXENABLE_REG OUTPUT4MUXENABLE; // Output X-BAR Mux Enable for Output 4 + union OUTPUT5MUXENABLE_REG OUTPUT5MUXENABLE; // Output X-BAR Mux Enable for Output 5 + union OUTPUT6MUXENABLE_REG OUTPUT6MUXENABLE; // Output X-BAR Mux Enable for Output 6 + union OUTPUT7MUXENABLE_REG OUTPUT7MUXENABLE; // Output X-BAR Mux Enable for Output 7 + union OUTPUT8MUXENABLE_REG OUTPUT8MUXENABLE; // Output X-BAR Mux Enable for Output 8 + union OUTPUTLATCH_REG OUTPUTLATCH; // Output X-BAR Output Latch + union OUTPUTLATCHCLR_REG OUTPUTLATCHCLR; // Output X-BAR Output Latch Clear + union OUTPUTLATCHFRC_REG OUTPUTLATCHFRC; // Output X-BAR Output Latch Clear + union OUTPUTLATCHENABLE_REG OUTPUTLATCHENABLE; // Output X-BAR Output Latch Enable + union OUTPUTINV_REG OUTPUTINV; // Output X-BAR Output Inversion + Uint16 rsvd1[4]; // Reserved + union OUTPUTLOCK_REG OUTPUTLOCK; // Output X-BAR Configuration Lock register +}; + +//--------------------------------------------------------------------------- +// OUTPUT_XBAR External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_piectrl.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_piectrl.h new file mode 100644 index 0000000000..75f9303244 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_piectrl.h @@ -0,0 +1,707 @@ +//########################################################################### +// +// FILE: F2837xD_piectrl.h +// +// TITLE: PIECTRL Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_PIECTRL_H__ +#define __F2837xD_PIECTRL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// PIECTRL Individual Register Bit Definitions: + +struct PIECTRL_BITS { // bits description + Uint16 ENPIE:1; // 0 PIE Enable + Uint16 PIEVECT:15; // 15:1 PIE Vector Address +}; + +union PIECTRL_REG { + Uint16 all; + struct PIECTRL_BITS bit; +}; + +struct PIEACK_BITS { // bits description + Uint16 ACK1:1; // 0 Acknowledge PIE Interrupt Group 1 + Uint16 ACK2:1; // 1 Acknowledge PIE Interrupt Group 2 + Uint16 ACK3:1; // 2 Acknowledge PIE Interrupt Group 3 + Uint16 ACK4:1; // 3 Acknowledge PIE Interrupt Group 4 + Uint16 ACK5:1; // 4 Acknowledge PIE Interrupt Group 5 + Uint16 ACK6:1; // 5 Acknowledge PIE Interrupt Group 6 + Uint16 ACK7:1; // 6 Acknowledge PIE Interrupt Group 7 + Uint16 ACK8:1; // 7 Acknowledge PIE Interrupt Group 8 + Uint16 ACK9:1; // 8 Acknowledge PIE Interrupt Group 9 + Uint16 ACK10:1; // 9 Acknowledge PIE Interrupt Group 10 + Uint16 ACK11:1; // 10 Acknowledge PIE Interrupt Group 11 + Uint16 ACK12:1; // 11 Acknowledge PIE Interrupt Group 12 + Uint16 rsvd1:4; // 15:12 Reserved +}; + +union PIEACK_REG { + Uint16 all; + struct PIEACK_BITS bit; +}; + +struct PIEIER1_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 1.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 1.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 1.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 1.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 1.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 1.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 1.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 1.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 1.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 1.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 1.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 1.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 1.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 1.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 1.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 1.16 +}; + +union PIEIER1_REG { + Uint16 all; + struct PIEIER1_BITS bit; +}; + +struct PIEIFR1_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 1.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 1.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 1.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 1.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 1.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 1.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 1.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 1.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 1.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 1.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 1.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 1.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 1.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 1.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 1.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 1.16 +}; + +union PIEIFR1_REG { + Uint16 all; + struct PIEIFR1_BITS bit; +}; + +struct PIEIER2_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 2.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 2.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 2.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 2.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 2.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 2.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 2.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 2.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 2.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 2.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 2.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 2.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 2.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 2.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 2.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 2.16 +}; + +union PIEIER2_REG { + Uint16 all; + struct PIEIER2_BITS bit; +}; + +struct PIEIFR2_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 2.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 2.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 2.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 2.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 2.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 2.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 2.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 2.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 2.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 2.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 2.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 2.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 2.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 2.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 2.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 2.16 +}; + +union PIEIFR2_REG { + Uint16 all; + struct PIEIFR2_BITS bit; +}; + +struct PIEIER3_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 3.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 3.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 3.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 3.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 3.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 3.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 3.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 3.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 3.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 3.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 3.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 3.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 3.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 3.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 3.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 3.16 +}; + +union PIEIER3_REG { + Uint16 all; + struct PIEIER3_BITS bit; +}; + +struct PIEIFR3_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 3.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 3.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 3.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 3.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 3.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 3.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 3.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 3.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 3.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 3.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 3.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 3.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 3.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 3.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 3.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 3.16 +}; + +union PIEIFR3_REG { + Uint16 all; + struct PIEIFR3_BITS bit; +}; + +struct PIEIER4_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 4.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 4.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 4.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 4.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 4.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 4.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 4.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 4.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 4.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 4.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 4.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 4.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 4.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 4.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 4.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 4.16 +}; + +union PIEIER4_REG { + Uint16 all; + struct PIEIER4_BITS bit; +}; + +struct PIEIFR4_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 4.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 4.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 4.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 4.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 4.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 4.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 4.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 4.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 4.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 4.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 4.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 4.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 4.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 4.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 4.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 4.16 +}; + +union PIEIFR4_REG { + Uint16 all; + struct PIEIFR4_BITS bit; +}; + +struct PIEIER5_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 5.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 5.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 5.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 5.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 5.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 5.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 5.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 5.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 5.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 5.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 5.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 5.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 5.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 5.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 5.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 5.16 +}; + +union PIEIER5_REG { + Uint16 all; + struct PIEIER5_BITS bit; +}; + +struct PIEIFR5_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 5.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 5.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 5.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 5.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 5.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 5.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 5.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 5.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 5.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 5.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 5.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 5.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 5.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 5.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 5.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 5.16 +}; + +union PIEIFR5_REG { + Uint16 all; + struct PIEIFR5_BITS bit; +}; + +struct PIEIER6_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 6.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 6.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 6.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 6.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 6.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 6.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 6.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 6.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 6.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 6.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 6.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 6.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 6.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 6.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 6.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 6.16 +}; + +union PIEIER6_REG { + Uint16 all; + struct PIEIER6_BITS bit; +}; + +struct PIEIFR6_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 6.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 6.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 6.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 6.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 6.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 6.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 6.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 6.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 6.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 6.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 6.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 6.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 6.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 6.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 6.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 6.16 +}; + +union PIEIFR6_REG { + Uint16 all; + struct PIEIFR6_BITS bit; +}; + +struct PIEIER7_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 7.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 7.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 7.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 7.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 7.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 7.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 7.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 7.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 7.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 7.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 7.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 7.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 7.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 7.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 7.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 7.16 +}; + +union PIEIER7_REG { + Uint16 all; + struct PIEIER7_BITS bit; +}; + +struct PIEIFR7_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 7.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 7.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 7.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 7.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 7.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 7.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 7.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 7.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 7.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 7.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 7.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 7.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 7.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 7.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 7.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 7.16 +}; + +union PIEIFR7_REG { + Uint16 all; + struct PIEIFR7_BITS bit; +}; + +struct PIEIER8_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 8.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 8.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 8.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 8.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 8.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 8.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 8.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 8.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 8.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 8.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 8.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 8.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 8.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 8.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 8.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 8.16 +}; + +union PIEIER8_REG { + Uint16 all; + struct PIEIER8_BITS bit; +}; + +struct PIEIFR8_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 8.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 8.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 8.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 8.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 8.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 8.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 8.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 8.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 8.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 8.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 8.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 8.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 8.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 8.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 8.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 8.16 +}; + +union PIEIFR8_REG { + Uint16 all; + struct PIEIFR8_BITS bit; +}; + +struct PIEIER9_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 9.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 9.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 9.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 9.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 9.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 9.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 9.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 9.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 9.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 9.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 9.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 9.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 9.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 9.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 9.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 9.16 +}; + +union PIEIER9_REG { + Uint16 all; + struct PIEIER9_BITS bit; +}; + +struct PIEIFR9_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 9.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 9.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 9.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 9.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 9.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 9.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 9.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 9.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 9.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 9.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 9.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 9.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 9.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 9.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 9.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 9.16 +}; + +union PIEIFR9_REG { + Uint16 all; + struct PIEIFR9_BITS bit; +}; + +struct PIEIER10_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 10.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 10.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 10.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 10.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 10.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 10.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 10.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 10.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 10.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 10.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 10.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 10.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 10.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 10.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 10.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 10.16 +}; + +union PIEIER10_REG { + Uint16 all; + struct PIEIER10_BITS bit; +}; + +struct PIEIFR10_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 10.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 10.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 10.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 10.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 10.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 10.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 10.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 10.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 10.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 10.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 10.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 10.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 10.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 10.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 10.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 10.16 +}; + +union PIEIFR10_REG { + Uint16 all; + struct PIEIFR10_BITS bit; +}; + +struct PIEIER11_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 11.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 11.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 11.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 11.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 11.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 11.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 11.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 11.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 11.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 11.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 11.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 11.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 11.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 11.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 11.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 11.16 +}; + +union PIEIER11_REG { + Uint16 all; + struct PIEIER11_BITS bit; +}; + +struct PIEIFR11_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 11.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 11.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 11.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 11.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 11.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 11.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 11.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 11.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 11.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 11.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 11.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 11.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 11.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 11.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 11.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 11.16 +}; + +union PIEIFR11_REG { + Uint16 all; + struct PIEIFR11_BITS bit; +}; + +struct PIEIER12_BITS { // bits description + Uint16 INTx1:1; // 0 Enable for Interrupt 12.1 + Uint16 INTx2:1; // 1 Enable for Interrupt 12.2 + Uint16 INTx3:1; // 2 Enable for Interrupt 12.3 + Uint16 INTx4:1; // 3 Enable for Interrupt 12.4 + Uint16 INTx5:1; // 4 Enable for Interrupt 12.5 + Uint16 INTx6:1; // 5 Enable for Interrupt 12.6 + Uint16 INTx7:1; // 6 Enable for Interrupt 12.7 + Uint16 INTx8:1; // 7 Enable for Interrupt 12.8 + Uint16 INTx9:1; // 8 Enable for Interrupt 12.9 + Uint16 INTx10:1; // 9 Enable for Interrupt 12.10 + Uint16 INTx11:1; // 10 Enable for Interrupt 12.11 + Uint16 INTx12:1; // 11 Enable for Interrupt 12.12 + Uint16 INTx13:1; // 12 Enable for Interrupt 12.13 + Uint16 INTx14:1; // 13 Enable for Interrupt 12.14 + Uint16 INTx15:1; // 14 Enable for Interrupt 12.15 + Uint16 INTx16:1; // 15 Enable for Interrupt 12.16 +}; + +union PIEIER12_REG { + Uint16 all; + struct PIEIER12_BITS bit; +}; + +struct PIEIFR12_BITS { // bits description + Uint16 INTx1:1; // 0 Flag for Interrupt 12.1 + Uint16 INTx2:1; // 1 Flag for Interrupt 12.2 + Uint16 INTx3:1; // 2 Flag for Interrupt 12.3 + Uint16 INTx4:1; // 3 Flag for Interrupt 12.4 + Uint16 INTx5:1; // 4 Flag for Interrupt 12.5 + Uint16 INTx6:1; // 5 Flag for Interrupt 12.6 + Uint16 INTx7:1; // 6 Flag for Interrupt 12.7 + Uint16 INTx8:1; // 7 Flag for Interrupt 12.8 + Uint16 INTx9:1; // 8 Flag for Interrupt 12.9 + Uint16 INTx10:1; // 9 Flag for Interrupt 12.10 + Uint16 INTx11:1; // 10 Flag for Interrupt 12.11 + Uint16 INTx12:1; // 11 Flag for Interrupt 12.12 + Uint16 INTx13:1; // 12 Flag for Interrupt 12.13 + Uint16 INTx14:1; // 13 Flag for Interrupt 12.14 + Uint16 INTx15:1; // 14 Flag for Interrupt 12.15 + Uint16 INTx16:1; // 15 Flag for Interrupt 12.16 +}; + +union PIEIFR12_REG { + Uint16 all; + struct PIEIFR12_BITS bit; +}; + +struct PIE_CTRL_REGS { + union PIECTRL_REG PIECTRL; // ePIE Control Register + union PIEACK_REG PIEACK; // Interrupt Acknowledge Register + union PIEIER1_REG PIEIER1; // Interrupt Group 1 Enable Register + union PIEIFR1_REG PIEIFR1; // Interrupt Group 1 Flag Register + union PIEIER2_REG PIEIER2; // Interrupt Group 2 Enable Register + union PIEIFR2_REG PIEIFR2; // Interrupt Group 2 Flag Register + union PIEIER3_REG PIEIER3; // Interrupt Group 3 Enable Register + union PIEIFR3_REG PIEIFR3; // Interrupt Group 3 Flag Register + union PIEIER4_REG PIEIER4; // Interrupt Group 4 Enable Register + union PIEIFR4_REG PIEIFR4; // Interrupt Group 4 Flag Register + union PIEIER5_REG PIEIER5; // Interrupt Group 5 Enable Register + union PIEIFR5_REG PIEIFR5; // Interrupt Group 5 Flag Register + union PIEIER6_REG PIEIER6; // Interrupt Group 6 Enable Register + union PIEIFR6_REG PIEIFR6; // Interrupt Group 6 Flag Register + union PIEIER7_REG PIEIER7; // Interrupt Group 7 Enable Register + union PIEIFR7_REG PIEIFR7; // Interrupt Group 7 Flag Register + union PIEIER8_REG PIEIER8; // Interrupt Group 8 Enable Register + union PIEIFR8_REG PIEIFR8; // Interrupt Group 8 Flag Register + union PIEIER9_REG PIEIER9; // Interrupt Group 9 Enable Register + union PIEIFR9_REG PIEIFR9; // Interrupt Group 9 Flag Register + union PIEIER10_REG PIEIER10; // Interrupt Group 10 Enable Register + union PIEIFR10_REG PIEIFR10; // Interrupt Group 10 Flag Register + union PIEIER11_REG PIEIER11; // Interrupt Group 11 Enable Register + union PIEIFR11_REG PIEIFR11; // Interrupt Group 11 Flag Register + union PIEIER12_REG PIEIER12; // Interrupt Group 12 Enable Register + union PIEIFR12_REG PIEIFR12; // Interrupt Group 12 Flag Register +}; + +//--------------------------------------------------------------------------- +// PIECTRL External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; +#endif +#ifdef CPU2 +extern volatile struct PIE_CTRL_REGS PieCtrlRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_pievect.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_pievect.h new file mode 100644 index 0000000000..7772256c78 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_pievect.h @@ -0,0 +1,306 @@ +//########################################################################### +// +// FILE: F2837xD_pievect.h +// +// TITLE: F2837xD Device PIE Vector Table Definitions +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef F2837xD_PIE_VECT_H +#define F2837xD_PIE_VECT_H +#ifdef __cplusplus +extern "C" { +#endif + +//--------------------------------------------------------------------------- +// PIE Interrupt Vector Table Definition: +// Create a user type called PINT (pointer to interrupt): + +typedef __interrupt void (*PINT)(void); + +// Define Vector Table: +struct PIE_VECT_TABLE { + PINT PIE1_RESERVED_INT; // Reserved + PINT PIE2_RESERVED_INT; // Reserved + PINT PIE3_RESERVED_INT; // Reserved + PINT PIE4_RESERVED_INT; // Reserved + PINT PIE5_RESERVED_INT; // Reserved + PINT PIE6_RESERVED_INT; // Reserved + PINT PIE7_RESERVED_INT; // Reserved + PINT PIE8_RESERVED_INT; // Reserved + PINT PIE9_RESERVED_INT; // Reserved + PINT PIE10_RESERVED_INT; // Reserved + PINT PIE11_RESERVED_INT; // Reserved + PINT PIE12_RESERVED_INT; // Reserved + PINT PIE13_RESERVED_INT; // Reserved + PINT TIMER1_INT; // CPU Timer 1 Interrupt + PINT TIMER2_INT; // CPU Timer 2 Interrupt + PINT DATALOG_INT; // Datalogging Interrupt + PINT RTOS_INT; // RTOS Interrupt + PINT EMU_INT; // Emulation Interrupt + PINT NMI_INT; // Non-Maskable Interrupt + PINT ILLEGAL_INT; // Illegal Operation Trap + PINT USER1_INT; // User Defined Trap 1 + PINT USER2_INT; // User Defined Trap 2 + PINT USER3_INT; // User Defined Trap 3 + PINT USER4_INT; // User Defined Trap 4 + PINT USER5_INT; // User Defined Trap 5 + PINT USER6_INT; // User Defined Trap 6 + PINT USER7_INT; // User Defined Trap 7 + PINT USER8_INT; // User Defined Trap 8 + PINT USER9_INT; // User Defined Trap 9 + PINT USER10_INT; // User Defined Trap 10 + PINT USER11_INT; // User Defined Trap 11 + PINT USER12_INT; // User Defined Trap 12 + PINT ADCA1_INT; // 1.1 - ADCA Interrupt 1 + PINT ADCB1_INT; // 1.2 - ADCB Interrupt 1 + PINT ADCC1_INT; // 1.3 - ADCC Interrupt 1 + PINT XINT1_INT; // 1.4 - XINT1 Interrupt + PINT XINT2_INT; // 1.5 - XINT2 Interrupt + PINT ADCD1_INT; // 1.6 - ADCD Interrupt 1 + PINT TIMER0_INT; // 1.7 - Timer 0 Interrupt + PINT WAKE_INT; // 1.8 - Standby and Halt Wakeup Interrupt + PINT EPWM1_TZ_INT; // 2.1 - ePWM1 Trip Zone Interrupt + PINT EPWM2_TZ_INT; // 2.2 - ePWM2 Trip Zone Interrupt + PINT EPWM3_TZ_INT; // 2.3 - ePWM3 Trip Zone Interrupt + PINT EPWM4_TZ_INT; // 2.4 - ePWM4 Trip Zone Interrupt + PINT EPWM5_TZ_INT; // 2.5 - ePWM5 Trip Zone Interrupt + PINT EPWM6_TZ_INT; // 2.6 - ePWM6 Trip Zone Interrupt + PINT EPWM7_TZ_INT; // 2.7 - ePWM7 Trip Zone Interrupt + PINT EPWM8_TZ_INT; // 2.8 - ePWM8 Trip Zone Interrupt + PINT EPWM1_INT; // 3.1 - ePWM1 Interrupt + PINT EPWM2_INT; // 3.2 - ePWM2 Interrupt + PINT EPWM3_INT; // 3.3 - ePWM3 Interrupt + PINT EPWM4_INT; // 3.4 - ePWM4 Interrupt + PINT EPWM5_INT; // 3.5 - ePWM5 Interrupt + PINT EPWM6_INT; // 3.6 - ePWM6 Interrupt + PINT EPWM7_INT; // 3.7 - ePWM7 Interrupt + PINT EPWM8_INT; // 3.8 - ePWM8 Interrupt + PINT ECAP1_INT; // 4.1 - eCAP1 Interrupt + PINT ECAP2_INT; // 4.2 - eCAP2 Interrupt + PINT ECAP3_INT; // 4.3 - eCAP3 Interrupt + PINT ECAP4_INT; // 4.4 - eCAP4 Interrupt + PINT ECAP5_INT; // 4.5 - eCAP5 Interrupt + PINT ECAP6_INT; // 4.6 - eCAP6 Interrupt + PINT PIE14_RESERVED_INT; // 4.7 - Reserved + PINT PIE15_RESERVED_INT; // 4.8 - Reserved + PINT EQEP1_INT; // 5.1 - eQEP1 Interrupt + PINT EQEP2_INT; // 5.2 - eQEP2 Interrupt + PINT EQEP3_INT; // 5.3 - eQEP3 Interrupt + PINT PIE16_RESERVED_INT; // 5.4 - Reserved + PINT PIE17_RESERVED_INT; // 5.5 - Reserved + PINT PIE18_RESERVED_INT; // 5.6 - Reserved + PINT PIE19_RESERVED_INT; // 5.7 - Reserved + PINT PIE20_RESERVED_INT; // 5.8 - Reserved + PINT SPIA_RX_INT; // 6.1 - SPIA Receive Interrupt + PINT SPIA_TX_INT; // 6.2 - SPIA Transmit Interrupt + PINT SPIB_RX_INT; // 6.3 - SPIB Receive Interrupt + PINT SPIB_TX_INT; // 6.4 - SPIB Transmit Interrupt + PINT MCBSPA_RX_INT; // 6.5 - McBSPA Receive Interrupt + PINT MCBSPA_TX_INT; // 6.6 - McBSPA Transmit Interrupt + PINT MCBSPB_RX_INT; // 6.7 - McBSPB Receive Interrupt + PINT MCBSPB_TX_INT; // 6.8 - McBSPB Transmit Interrupt + PINT DMA_CH1_INT; // 7.1 - DMA Channel 1 Interrupt + PINT DMA_CH2_INT; // 7.2 - DMA Channel 2 Interrupt + PINT DMA_CH3_INT; // 7.3 - DMA Channel 3 Interrupt + PINT DMA_CH4_INT; // 7.4 - DMA Channel 4 Interrupt + PINT DMA_CH5_INT; // 7.5 - DMA Channel 5 Interrupt + PINT DMA_CH6_INT; // 7.6 - DMA Channel 6 Interrupt + PINT PIE21_RESERVED_INT; // 7.7 - Reserved + PINT PIE22_RESERVED_INT; // 7.8 - Reserved + PINT I2CA_INT; // 8.1 - I2CA Interrupt 1 + PINT I2CA_FIFO_INT; // 8.2 - I2CA Interrupt 2 + PINT I2CB_INT; // 8.3 - I2CB Interrupt 1 + PINT I2CB_FIFO_INT; // 8.4 - I2CB Interrupt 2 + PINT SCIC_RX_INT; // 8.5 - SCIC Receive Interrupt + PINT SCIC_TX_INT; // 8.6 - SCIC Transmit Interrupt + PINT SCID_RX_INT; // 8.7 - SCID Receive Interrupt + PINT SCID_TX_INT; // 8.8 - SCID Transmit Interrupt + PINT SCIA_RX_INT; // 9.1 - SCIA Receive Interrupt + PINT SCIA_TX_INT; // 9.2 - SCIA Transmit Interrupt + PINT SCIB_RX_INT; // 9.3 - SCIB Receive Interrupt + PINT SCIB_TX_INT; // 9.4 - SCIB Transmit Interrupt + PINT CANA0_INT; // 9.5 - CANA Interrupt 0 + PINT CANA1_INT; // 9.6 - CANA Interrupt 1 + PINT CANB0_INT; // 9.7 - CANB Interrupt 0 + PINT CANB1_INT; // 9.8 - CANB Interrupt 1 + PINT ADCA_EVT_INT; // 10.1 - ADCA Event Interrupt + PINT ADCA2_INT; // 10.2 - ADCA Interrupt 2 + PINT ADCA3_INT; // 10.3 - ADCA Interrupt 3 + PINT ADCA4_INT; // 10.4 - ADCA Interrupt 4 + PINT ADCB_EVT_INT; // 10.5 - ADCB Event Interrupt + PINT ADCB2_INT; // 10.6 - ADCB Interrupt 2 + PINT ADCB3_INT; // 10.7 - ADCB Interrupt 3 + PINT ADCB4_INT; // 10.8 - ADCB Interrupt 4 + PINT CLA1_1_INT; // 11.1 - CLA1 Interrupt 1 + PINT CLA1_2_INT; // 11.2 - CLA1 Interrupt 2 + PINT CLA1_3_INT; // 11.3 - CLA1 Interrupt 3 + PINT CLA1_4_INT; // 11.4 - CLA1 Interrupt 4 + PINT CLA1_5_INT; // 11.5 - CLA1 Interrupt 5 + PINT CLA1_6_INT; // 11.6 - CLA1 Interrupt 6 + PINT CLA1_7_INT; // 11.7 - CLA1 Interrupt 7 + PINT CLA1_8_INT; // 11.8 - CLA1 Interrupt 8 + PINT XINT3_INT; // 12.1 - XINT3 Interrupt + PINT XINT4_INT; // 12.2 - XINT4 Interrupt + PINT XINT5_INT; // 12.3 - XINT5 Interrupt + PINT PIE23_RESERVED_INT; // 12.4 - Reserved + PINT PIE24_RESERVED_INT; // 12.5 - Reserved + PINT VCU_INT; // 12.6 - VCU Interrupt + PINT FPU_OVERFLOW_INT; // 12.7 - FPU Overflow Interrupt + PINT FPU_UNDERFLOW_INT; // 12.8 - FPU Underflow Interrupt + PINT PIE25_RESERVED_INT; // 1.9 - Reserved + PINT PIE26_RESERVED_INT; // 1.10 - Reserved + PINT PIE27_RESERVED_INT; // 1.11 - Reserved + PINT PIE28_RESERVED_INT; // 1.12 - Reserved + PINT IPC0_INT; // 1.13 - IPC Interrupt 0 + PINT IPC1_INT; // 1.14 - IPC Interrupt 1 + PINT IPC2_INT; // 1.15 - IPC Interrupt 2 + PINT IPC3_INT; // 1.16 - IPC Interrupt 3 + PINT EPWM9_TZ_INT; // 2.9 - ePWM9 Trip Zone Interrupt + PINT EPWM10_TZ_INT; // 2.10 - ePWM10 Trip Zone Interrupt + PINT EPWM11_TZ_INT; // 2.11 - ePWM11 Trip Zone Interrupt + PINT EPWM12_TZ_INT; // 2.12 - ePWM12 Trip Zone Interrupt + PINT PIE29_RESERVED_INT; // 2.13 - Reserved + PINT PIE30_RESERVED_INT; // 2.14 - Reserved + PINT PIE31_RESERVED_INT; // 2.15 - Reserved + PINT PIE32_RESERVED_INT; // 2.16 - Reserved + PINT EPWM9_INT; // 3.9 - ePWM9 Interrupt + PINT EPWM10_INT; // 3.10 - ePWM10 Interrupt + PINT EPWM11_INT; // 3.11 - ePWM11 Interrupt + PINT EPWM12_INT; // 3.12 - ePWM12 Interrupt + PINT PIE33_RESERVED_INT; // 3.13 - Reserved + PINT PIE34_RESERVED_INT; // 3.14 - Reserved + PINT PIE35_RESERVED_INT; // 3.15 - Reserved + PINT PIE36_RESERVED_INT; // 3.16 - Reserved + PINT PIE37_RESERVED_INT; // 4.9 - Reserved + PINT PIE38_RESERVED_INT; // 4.10 - Reserved + PINT PIE39_RESERVED_INT; // 4.11 - Reserved + PINT PIE40_RESERVED_INT; // 4.12 - Reserved + PINT PIE41_RESERVED_INT; // 4.13 - Reserved + PINT PIE42_RESERVED_INT; // 4.14 - Reserved + PINT PIE43_RESERVED_INT; // 4.15 - Reserved + PINT PIE44_RESERVED_INT; // 4.16 - Reserved + PINT SD1_INT; // 5.9 - SD1 Interrupt + PINT SD2_INT; // 5.10 - SD2 Interrupt + PINT PIE45_RESERVED_INT; // 5.11 - Reserved + PINT PIE46_RESERVED_INT; // 5.12 - Reserved + PINT PIE47_RESERVED_INT; // 5.13 - Reserved + PINT PIE48_RESERVED_INT; // 5.14 - Reserved + PINT PIE49_RESERVED_INT; // 5.15 - Reserved + PINT PIE50_RESERVED_INT; // 5.16 - Reserved + PINT SPIC_RX_INT; // 6.9 - SPIC Receive Interrupt + PINT SPIC_TX_INT; // 6.10 - SPIC Transmit Interrupt + PINT PIE51_RESERVED_INT; // 6.11 - Reserved + PINT PIE52_RESERVED_INT; // 6.12 - Reserved + PINT PIE53_RESERVED_INT; // 6.13 - Reserved + PINT PIE54_RESERVED_INT; // 6.14 - Reserved + PINT PIE55_RESERVED_INT; // 6.15 - Reserved + PINT PIE56_RESERVED_INT; // 6.16 - Reserved + PINT PIE57_RESERVED_INT; // 7.9 - Reserved + PINT PIE58_RESERVED_INT; // 7.10 - Reserved + PINT PIE59_RESERVED_INT; // 7.11 - Reserved + PINT PIE60_RESERVED_INT; // 7.12 - Reserved + PINT PIE61_RESERVED_INT; // 7.13 - Reserved + PINT PIE62_RESERVED_INT; // 7.14 - Reserved + PINT PIE63_RESERVED_INT; // 7.15 - Reserved + PINT PIE64_RESERVED_INT; // 7.16 - Reserved + PINT PIE65_RESERVED_INT; // 8.9 - Reserved + PINT PIE66_RESERVED_INT; // 8.10 - Reserved + PINT PIE67_RESERVED_INT; // 8.11 - Reserved + PINT PIE68_RESERVED_INT; // 8.12 - Reserved + PINT PIE69_RESERVED_INT; // 8.13 - Reserved + PINT PIE70_RESERVED_INT; // 8.14 - Reserved +#ifdef CPU1 + PINT UPPA_INT; // 8.15 - uPPA Interrupt + PINT PIE72_RESERVED_INT; // 8.16 - Reserved +#elif defined(CPU2) + PINT PIE71_RESERVED_INT; // 8.15 - Reserved + PINT PIE72_RESERVED_INT; // 8.16 - Reserved +#endif + PINT PIE73_RESERVED_INT; // 9.9 - Reserved + PINT PIE74_RESERVED_INT; // 9.10 - Reserved + PINT PIE75_RESERVED_INT; // 9.11 - Reserved + PINT PIE76_RESERVED_INT; // 9.12 - Reserved + PINT PIE77_RESERVED_INT; // 9.13 - Reserved + PINT PIE78_RESERVED_INT; // 9.14 - Reserved +#ifdef CPU1 + PINT USBA_INT; // 9.15 - USBA Interrupt +#elif defined(CPU2) + PINT PIE79_RESERVED_INT; // 9.15 - Reserved +#endif + PINT PIE80_RESERVED_INT; // 9.16 - Reserved + PINT ADCC_EVT_INT; // 10.9 - ADCC Event Interrupt + PINT ADCC2_INT; // 10.10 - ADCC Interrupt 2 + PINT ADCC3_INT; // 10.11 - ADCC Interrupt 3 + PINT ADCC4_INT; // 10.12 - ADCC Interrupt 4 + PINT ADCD_EVT_INT; // 10.13 - ADCD Event Interrupt + PINT ADCD2_INT; // 10.14 - ADCD Interrupt 2 + PINT ADCD3_INT; // 10.15 - ADCD Interrupt 3 + PINT ADCD4_INT; // 10.16 - ADCD Interrupt 4 + PINT PIE81_RESERVED_INT; // 11.9 - Reserved + PINT PIE82_RESERVED_INT; // 11.10 - Reserved + PINT PIE83_RESERVED_INT; // 11.11 - Reserved + PINT PIE84_RESERVED_INT; // 11.12 - Reserved + PINT PIE85_RESERVED_INT; // 11.13 - Reserved + PINT PIE86_RESERVED_INT; // 11.14 - Reserved + PINT PIE87_RESERVED_INT; // 11.15 - Reserved + PINT PIE88_RESERVED_INT; // 11.16 - Reserved + PINT EMIF_ERROR_INT; // 12.9 - EMIF Error Interrupt + PINT RAM_CORRECTABLE_ERROR_INT; // 12.10 - RAM Correctable Error Interrupt + PINT FLASH_CORRECTABLE_ERROR_INT; // 12.11 - Flash Correctable Error Interrupt + PINT RAM_ACCESS_VIOLATION_INT; // 12.12 - RAM Access Violation Interrupt + PINT SYS_PLL_SLIP_INT; // 12.13 - System PLL Slip Interrupt + PINT AUX_PLL_SLIP_INT; // 12.14 - Auxiliary PLL Slip Interrupt + PINT CLA_OVERFLOW_INT; // 12.15 - CLA Overflow Interrupt + PINT CLA_UNDERFLOW_INT; // 12.16 - CLA Underflow Interrupt +}; + +//--------------------------------------------------------------------------- +// PieVect External References & Function Declarations: +// + +extern volatile struct PIE_VECT_TABLE PieVectTable; + +#ifdef __cplusplus +} +#endif /* extern "C" */ + + +#endif // end of F2837xD_PIEVECT_H definition +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_sci.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_sci.h new file mode 100644 index 0000000000..ae1cf3c422 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_sci.h @@ -0,0 +1,266 @@ +//########################################################################### +// +// FILE: F2837xD_sci.h +// +// TITLE: SCI Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_SCI_H__ +#define __F2837xD_SCI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// SCI Individual Register Bit Definitions: + +struct SCICCR_BITS { // bits description + Uint16 SCICHAR:3; // 2:0 Character length control + Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control + Uint16 LOOPBKENA:1; // 4 Loop Back enable + Uint16 PARITYENA:1; // 5 Parity enable + Uint16 PARITY:1; // 6 Even or Odd Parity + Uint16 STOPBITS:1; // 7 Number of Stop Bits + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SCICCR_REG { + Uint16 all; + struct SCICCR_BITS bit; +}; + +struct SCICTL1_BITS { // bits description + Uint16 RXENA:1; // 0 SCI receiver enable + Uint16 TXENA:1; // 1 SCI transmitter enable + Uint16 SLEEP:1; // 2 SCI sleep + Uint16 TXWAKE:1; // 3 Transmitter wakeup method + Uint16 rsvd1:1; // 4 Reserved + Uint16 SWRESET:1; // 5 Software reset + Uint16 RXERRINTENA:1; // 6 Recieve __interrupt enable + Uint16 rsvd2:9; // 15:7 Reserved +}; + +union SCICTL1_REG { + Uint16 all; + struct SCICTL1_BITS bit; +}; + +struct SCIHBAUD_BITS { // bits description + Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCIHBAUD + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SCIHBAUD_REG { + Uint16 all; + struct SCIHBAUD_BITS bit; +}; + +struct SCILBAUD_BITS { // bits description + Uint16 BAUD:8; // 7:0 SCI 16-bit baud selection Registers SCILBAUD + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SCILBAUD_REG { + Uint16 all; + struct SCILBAUD_BITS bit; +}; + +struct SCICTL2_BITS { // bits description + Uint16 TXINTENA:1; // 0 Transmit __interrupt enable + Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable + Uint16 rsvd1:4; // 5:2 Reserved + Uint16 TXEMPTY:1; // 6 Transmitter empty flag + Uint16 TXRDY:1; // 7 Transmitter ready flag + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union SCICTL2_REG { + Uint16 all; + struct SCICTL2_BITS bit; +}; + +struct SCIRXST_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag + Uint16 PE:1; // 2 Parity error flag + Uint16 OE:1; // 3 Overrun error flag + Uint16 FE:1; // 4 Framing error flag + Uint16 BRKDT:1; // 5 Break-detect flag + Uint16 RXRDY:1; // 6 Receiver ready flag + Uint16 RXERROR:1; // 7 Receiver error flag + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union SCIRXST_REG { + Uint16 all; + struct SCIRXST_BITS bit; +}; + +struct SCIRXEMU_BITS { // bits description + Uint16 ERXDT:8; // 7:0 Receive emulation buffer data + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SCIRXEMU_REG { + Uint16 all; + struct SCIRXEMU_BITS bit; +}; + +struct SCIRXBUF_BITS { // bits description + Uint16 SAR:8; // 7:0 Receive Character bits + Uint16 rsvd1:6; // 13:8 Reserved + Uint16 SCIFFPE:1; // 14 Receiver error flag + Uint16 SCIFFFE:1; // 15 Receiver error flag +}; + +union SCIRXBUF_REG { + Uint16 all; + struct SCIRXBUF_BITS bit; +}; + +struct SCITXBUF_BITS { // bits description + Uint16 TXDT:8; // 7:0 Transmit data buffer + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SCITXBUF_REG { + Uint16 all; + struct SCITXBUF_BITS bit; +}; + +struct SCIFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 Interrupt level + Uint16 TXFFIENA:1; // 5 Interrupt enable + Uint16 TXFFINTCLR:1; // 6 Clear INT flag + Uint16 TXFFINT:1; // 7 INT flag + Uint16 TXFFST:5; // 12:8 FIFO status + Uint16 TXFIFORESET:1; // 13 FIFO reset + Uint16 SCIFFENA:1; // 14 Enhancement enable + Uint16 SCIRST:1; // 15 SCI reset rx/tx channels +}; + +union SCIFFTX_REG { + Uint16 all; + struct SCIFFTX_BITS bit; +}; + +struct SCIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 Interrupt level + Uint16 RXFFIENA:1; // 5 Interrupt enable + Uint16 RXFFINTCLR:1; // 6 Clear INT flag + Uint16 RXFFINT:1; // 7 INT flag + Uint16 RXFFST:5; // 12:8 FIFO status + Uint16 RXFIFORESET:1; // 13 FIFO reset + Uint16 RXFFOVRCLR:1; // 14 Clear overflow + Uint16 RXFFOVF:1; // 15 FIFO overflow +}; + +union SCIFFRX_REG { + Uint16 all; + struct SCIFFRX_BITS bit; +}; + +struct SCIFFCT_BITS { // bits description + Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay + Uint16 rsvd1:5; // 12:8 Reserved + Uint16 CDC:1; // 13 Auto baud mode enable + Uint16 ABDCLR:1; // 14 Auto baud clear + Uint16 ABD:1; // 15 Auto baud detect +}; + +union SCIFFCT_REG { + Uint16 all; + struct SCIFFCT_BITS bit; +}; + +struct SCIPRI_BITS { // bits description + Uint16 rsvd1:3; // 2:0 Reserved + Uint16 FREESOFT:2; // 4:3 Emulation modes + Uint16 rsvd2:3; // 7:5 Reserved + Uint16 rsvd3:8; // 15:8 Reserved +}; + +union SCIPRI_REG { + Uint16 all; + struct SCIPRI_BITS bit; +}; + +struct SCI_REGS { + union SCICCR_REG SCICCR; // Communications control register + union SCICTL1_REG SCICTL1; // Control register 1 + union SCIHBAUD_REG SCIHBAUD; // Baud rate (high) register + union SCILBAUD_REG SCILBAUD; // Baud rate (low) register + union SCICTL2_REG SCICTL2; // Control register 2 + union SCIRXST_REG SCIRXST; // Recieve status register + union SCIRXEMU_REG SCIRXEMU; // Recieve emulation buffer register + union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer + Uint16 rsvd1; // Reserved + union SCITXBUF_REG SCITXBUF; // Transmit data buffer + union SCIFFTX_REG SCIFFTX; // FIFO transmit register + union SCIFFRX_REG SCIFFRX; // FIFO recieve register + union SCIFFCT_REG SCIFFCT; // FIFO control register + Uint16 rsvd2[2]; // Reserved + union SCIPRI_REG SCIPRI; // SCI Priority control +}; + +//--------------------------------------------------------------------------- +// SCI External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; +extern volatile struct SCI_REGS ScidRegs; +#endif +#ifdef CPU2 +extern volatile struct SCI_REGS SciaRegs; +extern volatile struct SCI_REGS ScibRegs; +extern volatile struct SCI_REGS ScicRegs; +extern volatile struct SCI_REGS ScidRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_sdfm.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_sdfm.h new file mode 100644 index 0000000000..7506115073 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_sdfm.h @@ -0,0 +1,534 @@ +//########################################################################### +// +// FILE: F2837xD_sdfm.h +// +// TITLE: SDFM Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_SDFM_H__ +#define __F2837xD_SDFM_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// SDFM Individual Register Bit Definitions: + +struct SDIFLG_BITS { // bits description + Uint16 IFH1:1; // 0 High-level Interrupt flag Filter 1 + Uint16 IFL1:1; // 1 Low-Level Interrupt flag Filter 1 + Uint16 IFH2:1; // 2 High-level Interrupt flag Filter 2 + Uint16 IFL2:1; // 3 Low-Level Interrupt flag Filter 2 + Uint16 IFH3:1; // 4 High-level Interrupt flag Filter 3 + Uint16 IFL3:1; // 5 Low-Level Interrupt flag Filter 3 + Uint16 IFH4:1; // 6 High-level Interrupt flag Filter 4 + Uint16 IFL4:1; // 7 Low-Level Interrupt flag Filter 4 + Uint16 MF1:1; // 8 Modulator Failure for Filter 1 + Uint16 MF2:1; // 9 Modulator Failure for Filter 2 + Uint16 MF3:1; // 10 Modulator Failure for Filter 3 + Uint16 MF4:1; // 11 Modulator Failure for Filter 4 + Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 + Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 + Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 + Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 + Uint16 rsvd1:15; // 30:16 Reserved + Uint16 MIF:1; // 31 Master Interrupt Flag +}; + +union SDIFLG_REG { + Uint32 all; + struct SDIFLG_BITS bit; +}; + +struct SDIFLGCLR_BITS { // bits description + Uint16 IFH1:1; // 0 High-level Interrupt flag Filter 1 + Uint16 IFL1:1; // 1 Low-Level Interrupt flag Filter 1 + Uint16 IFH2:1; // 2 High-level Interrupt flag Filter 2 + Uint16 IFL2:1; // 3 Low-Level Interrupt flag Filter 2 + Uint16 IFH3:1; // 4 High-level Interrupt flag Filter 3 + Uint16 IFL3:1; // 5 Low-Level Interrupt flag Filter 3 + Uint16 IFH4:1; // 6 High-level Interrupt flag Filter 4 + Uint16 IFL4:1; // 7 Low-Level Interrupt flag Filter 4 + Uint16 MF1:1; // 8 Modulator Failure for Filter 1 + Uint16 MF2:1; // 9 Modulator Failure for Filter 2 + Uint16 MF3:1; // 10 Modulator Failure for Filter 3 + Uint16 MF4:1; // 11 Modulator Failure for Filter 4 + Uint16 AF1:1; // 12 Acknowledge flag for Filter 1 + Uint16 AF2:1; // 13 Acknowledge flag for Filter 2 + Uint16 AF3:1; // 14 Acknowledge flag for Filter 3 + Uint16 AF4:1; // 15 Acknowledge flag for Filter 4 + Uint16 rsvd1:15; // 30:16 Reserved + Uint16 MIF:1; // 31 Master Interrupt Flag +}; + +union SDIFLGCLR_REG { + Uint32 all; + struct SDIFLGCLR_BITS bit; +}; + +struct SDCTL_BITS { // bits description + Uint16 rsvd1:13; // 12:0 Reserved + Uint16 MIE:1; // 13 Master Interrupt enable + Uint16 rsvd2:1; // 14 Reserved + Uint16 rsvd3:1; // 15 Reserved +}; + +union SDCTL_REG { + Uint16 all; + struct SDCTL_BITS bit; +}; + +struct SDMFILEN_BITS { // bits description + Uint16 rsvd1:4; // 3:0 Reserved + Uint16 rsvd2:3; // 6:4 Reserved + Uint16 rsvd3:2; // 8:7 Reserved + Uint16 rsvd4:1; // 9 Reserved + Uint16 rsvd5:1; // 10 Reserved + Uint16 MFE:1; // 11 Master Filter Enable. + Uint16 rsvd6:1; // 12 Reserved + Uint16 rsvd7:3; // 15:13 Reserved +}; + +union SDMFILEN_REG { + Uint16 all; + struct SDMFILEN_BITS bit; +}; + +struct SDCTLPARM1_BITS { // bits description + Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:11; // 15:5 Reserved +}; + +union SDCTLPARM1_REG { + Uint16 all; + struct SDCTLPARM1_BITS bit; +}; + +struct SDDFPARM1_BITS { // bits description + Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 + Uint16 FEN:1; // 8 Filter Enable + Uint16 AE:1; // 9 Ack Enable + Uint16 SST:2; // 11:10 Data Filter Structure (DataFast/1/2/3) + Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union SDDFPARM1_REG { + Uint16 all; + struct SDDFPARM1_BITS bit; +}; + +struct SDDPARM1_BITS { // bits description + Uint16 rsvd1:7; // 6:0 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 rsvd4:1; // 9 Reserved + Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) + Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) +}; + +union SDDPARM1_REG { + Uint16 all; + struct SDDPARM1_BITS bit; +}; + +struct SDCMPH1_BITS { // bits description + Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPH1_REG { + Uint16 all; + struct SDCMPH1_BITS bit; +}; + +struct SDCMPL1_BITS { // bits description + Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPL1_REG { + Uint16 all; + struct SDCMPL1_BITS bit; +}; + +struct SDCPARM1_BITS { // bits description + Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 + Uint16 IEH:1; // 5 High-level interrupt enable + Uint16 IEL:1; // 6 Low-level interrupt enable + Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 + Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union SDCPARM1_REG { + Uint16 all; + struct SDCPARM1_BITS bit; +}; + +struct SDDATA1_BITS { // bits description + Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode + Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode +}; + +union SDDATA1_REG { + Uint32 all; + struct SDDATA1_BITS bit; +}; + +struct SDCTLPARM2_BITS { // bits description + Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:11; // 15:5 Reserved +}; + +union SDCTLPARM2_REG { + Uint16 all; + struct SDCTLPARM2_BITS bit; +}; + +struct SDDFPARM2_BITS { // bits description + Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 + Uint16 FEN:1; // 8 Filter Enable + Uint16 AE:1; // 9 Ack Enable + Uint16 SST:2; // 11:10 Data Filter Structure (SincFast/1/2/3) + Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union SDDFPARM2_REG { + Uint16 all; + struct SDDFPARM2_BITS bit; +}; + +struct SDDPARM2_BITS { // bits description + Uint16 rsvd1:7; // 6:0 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 rsvd4:1; // 9 Reserved + Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) + Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) +}; + +union SDDPARM2_REG { + Uint16 all; + struct SDDPARM2_BITS bit; +}; + +struct SDCMPH2_BITS { // bits description + Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPH2_REG { + Uint16 all; + struct SDCMPH2_BITS bit; +}; + +struct SDCMPL2_BITS { // bits description + Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPL2_REG { + Uint16 all; + struct SDCMPL2_BITS bit; +}; + +struct SDCPARM2_BITS { // bits description + Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 + Uint16 IEH:1; // 5 High-level interrupt enable + Uint16 IEL:1; // 6 Low-level interrupt enable + Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 + Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union SDCPARM2_REG { + Uint16 all; + struct SDCPARM2_BITS bit; +}; + +struct SDDATA2_BITS { // bits description + Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode + Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode +}; + +union SDDATA2_REG { + Uint32 all; + struct SDDATA2_BITS bit; +}; + +struct SDCTLPARM3_BITS { // bits description + Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:11; // 15:5 Reserved +}; + +union SDCTLPARM3_REG { + Uint16 all; + struct SDCTLPARM3_BITS bit; +}; + +struct SDDFPARM3_BITS { // bits description + Uint16 DOSR:8; // 7:0 Data Filter Oversample Ratio= DOSR+1 + Uint16 FEN:1; // 8 Filter Enable + Uint16 AE:1; // 9 Ack Enable + Uint16 SST:2; // 11:10 Data filter structure (SincFast/1/2/3) + Uint16 SDSYNCEN:1; // 12 Data FILTER Reset Enable + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union SDDFPARM3_REG { + Uint16 all; + struct SDDFPARM3_BITS bit; +}; + +struct SDDPARM3_BITS { // bits description + Uint16 rsvd1:7; // 6:0 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 rsvd4:1; // 9 Reserved + Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) + Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) +}; + +union SDDPARM3_REG { + Uint16 all; + struct SDDPARM3_BITS bit; +}; + +struct SDCMPH3_BITS { // bits description + Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPH3_REG { + Uint16 all; + struct SDCMPH3_BITS bit; +}; + +struct SDCMPL3_BITS { // bits description + Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPL3_REG { + Uint16 all; + struct SDCMPL3_BITS bit; +}; + +struct SDCPARM3_BITS { // bits description + Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 + Uint16 IEH:1; // 5 High-level interrupt enable + Uint16 IEL:1; // 6 Low-level interrupt enable + Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 + Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union SDCPARM3_REG { + Uint16 all; + struct SDCPARM3_BITS bit; +}; + +struct SDDATA3_BITS { // bits description + Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode + Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode +}; + +union SDDATA3_REG { + Uint32 all; + struct SDDATA3_BITS bit; +}; + +struct SDCTLPARM4_BITS { // bits description + Uint16 MOD:2; // 1:0 Delta-Sigma Modulator mode + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:11; // 15:5 Reserved +}; + +union SDCTLPARM4_REG { + Uint16 all; + struct SDCTLPARM4_BITS bit; +}; + +struct SDDFPARM4_BITS { // bits description + Uint16 DOSR:8; // 7:0 SINC Filter Oversample Ratio= DOSR+1 + Uint16 FEN:1; // 8 Filter Enable + Uint16 AE:1; // 9 Ack Enable + Uint16 SST:2; // 11:10 Data filter structure (SincFast/1/2/3) + Uint16 SDSYNCEN:1; // 12 SINC FILTER Reset Enable + Uint16 rsvd1:3; // 15:13 Reserved +}; + +union SDDFPARM4_REG { + Uint16 all; + struct SDDFPARM4_BITS bit; +}; + +struct SDDPARM4_BITS { // bits description + Uint16 rsvd1:7; // 6:0 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:1; // 8 Reserved + Uint16 rsvd4:1; // 9 Reserved + Uint16 DR:1; // 10 Data Representation (0/1 = 16/32b 2's complement) + Uint16 SH:5; // 15:11 Shift Control (# bits to shift in 16b mode) +}; + +union SDDPARM4_REG { + Uint16 all; + struct SDDPARM4_BITS bit; +}; + +struct SDCMPH4_BITS { // bits description + Uint16 HLT:15; // 14:0 High-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPH4_REG { + Uint16 all; + struct SDCMPH4_BITS bit; +}; + +struct SDCMPL4_BITS { // bits description + Uint16 LLT:15; // 14:0 Low-level threshold for the comparator filter output. + Uint16 rsvd1:1; // 15 Reserved +}; + +union SDCMPL4_REG { + Uint16 all; + struct SDCMPL4_BITS bit; +}; + +struct SDCPARM4_BITS { // bits description + Uint16 COSR:5; // 4:0 Comparator Oversample Ratio = COSR + 1 + Uint16 IEH:1; // 5 High-level interrupt enable + Uint16 IEL:1; // 6 Low-level interrupt enable + Uint16 CS1_CS0:2; // 8:7 Comparator filter structure (Sincfast/Sinc1/Sinc2/Sinc3 + Uint16 MFIE:1; // 9 Modulator Failure Interrupt enable + Uint16 rsvd1:6; // 15:10 Reserved +}; + +union SDCPARM4_REG { + Uint16 all; + struct SDCPARM4_BITS bit; +}; + +struct SDDATA4_BITS { // bits description + Uint16 DATA16:16; // 15:0 16-bit Data in 16b mode, Lo-order 16b in 32b mode + Uint16 DATA32HI:16; // 31:16 Hi-order 16b in 32b mode +}; + +union SDDATA4_REG { + Uint32 all; + struct SDDATA4_BITS bit; +}; + +struct SDFM_REGS { + union SDIFLG_REG SDIFLG; // Interrupt Flag Register + union SDIFLGCLR_REG SDIFLGCLR; // Interrupt Flag Clear Register + union SDCTL_REG SDCTL; // SD Control Register + Uint16 rsvd1; // Reserved + union SDMFILEN_REG SDMFILEN; // SD Master Filter Enable + Uint16 rsvd2[9]; // Reserved + union SDCTLPARM1_REG SDCTLPARM1; // Control Parameter Register for Ch1 + union SDDFPARM1_REG SDDFPARM1; // Data Filter Parameter Register for Ch1 + union SDDPARM1_REG SDDPARM1; // Integer Parameter Register for Ch1 + union SDCMPH1_REG SDCMPH1; // High-level Threshold Register for Ch1 + union SDCMPL1_REG SDCMPL1; // Low-level Threshold Register for Ch1 + union SDCPARM1_REG SDCPARM1; // Comparator Parameter Register for Ch1 + union SDDATA1_REG SDDATA1; // Filter Data Register (16 or 32bit) for Ch1 + Uint16 rsvd3[8]; // Reserved + union SDCTLPARM2_REG SDCTLPARM2; // Control Parameter Register for Ch2 + union SDDFPARM2_REG SDDFPARM2; // Data Filter Parameter Register for Ch2 + union SDDPARM2_REG SDDPARM2; // Integer Parameter Register for Ch2 + union SDCMPH2_REG SDCMPH2; // High-level Threshold Register for Ch2 + union SDCMPL2_REG SDCMPL2; // Low-level Threshold Register for Ch2 + union SDCPARM2_REG SDCPARM2; // Comparator Parameter Register for Ch2 + union SDDATA2_REG SDDATA2; // Filter Data Register (16 or 32bit) for Ch2 + Uint16 rsvd4[8]; // Reserved + union SDCTLPARM3_REG SDCTLPARM3; // Control Parameter Register for Ch3 + union SDDFPARM3_REG SDDFPARM3; // Data Filter Parameter Register for Ch3 + union SDDPARM3_REG SDDPARM3; // Integer Parameter Register for Ch3 + union SDCMPH3_REG SDCMPH3; // High-level Threshold Register for Ch3 + union SDCMPL3_REG SDCMPL3; // Low-level Threshold Register for Ch3 + union SDCPARM3_REG SDCPARM3; // Comparator Parameter Register for Ch3 + union SDDATA3_REG SDDATA3; // Filter Data Register (16 or 32bit) for Ch3 + Uint16 rsvd5[8]; // Reserved + union SDCTLPARM4_REG SDCTLPARM4; // Control Parameter Register for Ch4 + union SDDFPARM4_REG SDDFPARM4; // Data Filter Parameter Register for Ch4 + union SDDPARM4_REG SDDPARM4; // Integer Parameter Register for Ch4 + union SDCMPH4_REG SDCMPH4; // High-level Threshold Register for Ch4 + union SDCMPL4_REG SDCMPL4; // Low-level Threshold Register for Ch4 + union SDCPARM4_REG SDCPARM4; // Comparator Parameter Register for Ch4 + union SDDATA4_REG SDDATA4; // Filter Data Register (16 or 32bit) for Ch4 + Uint16 rsvd6[56]; // Reserved +}; + +//--------------------------------------------------------------------------- +// SDFM External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct SDFM_REGS Sdfm1Regs; +extern volatile struct SDFM_REGS Sdfm2Regs; +#endif +#ifdef CPU2 +extern volatile struct SDFM_REGS Sdfm1Regs; +extern volatile struct SDFM_REGS Sdfm2Regs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_spi.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_spi.h new file mode 100644 index 0000000000..30e2e6babb --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_spi.h @@ -0,0 +1,201 @@ +//########################################################################### +// +// FILE: F2837xD_spi.h +// +// TITLE: SPI Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_SPI_H__ +#define __F2837xD_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// SPI Individual Register Bit Definitions: + +struct SPICCR_BITS { // bits description + Uint16 SPICHAR:4; // 3:0 Character Length Control + Uint16 SPILBK:1; // 4 SPI Loopback + Uint16 HS_MODE:1; // 5 High Speed mode control + Uint16 CLKPOLARITY:1; // 6 Shift Clock Polarity + Uint16 SPISWRESET:1; // 7 SPI Software Reset + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SPICCR_REG { + Uint16 all; + struct SPICCR_BITS bit; +}; + +struct SPICTL_BITS { // bits description + Uint16 SPIINTENA:1; // 0 SPI Interupt Enable + Uint16 TALK:1; // 1 Master/Slave Transmit Enable + Uint16 MASTER_SLAVE:1; // 2 SPI Network Mode Control + Uint16 CLK_PHASE:1; // 3 SPI Clock Phase + Uint16 OVERRUNINTENA:1; // 4 Overrun Interrupt Enable + Uint16 rsvd1:11; // 15:5 Reserved +}; + +union SPICTL_REG { + Uint16 all; + struct SPICTL_BITS bit; +}; + +struct SPISTS_BITS { // bits description + Uint16 rsvd1:5; // 4:0 Reserved + Uint16 BUFFULL_FLAG:1; // 5 SPI Transmit Buffer Full Flag + Uint16 INT_FLAG:1; // 6 SPI Interrupt Flag + Uint16 OVERRUN_FLAG:1; // 7 SPI Receiver Overrun Flag + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union SPISTS_REG { + Uint16 all; + struct SPISTS_BITS bit; +}; + +struct SPIBRR_BITS { // bits description + Uint16 SPI_BIT_RATE:7; // 6:0 SPI Bit Rate Control + Uint16 rsvd1:9; // 15:7 Reserved +}; + +union SPIBRR_REG { + Uint16 all; + struct SPIBRR_BITS bit; +}; + +struct SPIFFTX_BITS { // bits description + Uint16 TXFFIL:5; // 4:0 TXFIFO Interrupt Level + Uint16 TXFFIENA:1; // 5 TXFIFO Interrupt Enable + Uint16 TXFFINTCLR:1; // 6 TXFIFO Interrupt Clear + Uint16 TXFFINT:1; // 7 TXFIFO Interrupt Flag + Uint16 TXFFST:5; // 12:8 Transmit FIFO Status + Uint16 TXFIFO:1; // 13 TXFIFO Reset + Uint16 SPIFFENA:1; // 14 FIFO Enhancements Enable + Uint16 SPIRST:1; // 15 SPI Reset +}; + +union SPIFFTX_REG { + Uint16 all; + struct SPIFFTX_BITS bit; +}; + +struct SPIFFRX_BITS { // bits description + Uint16 RXFFIL:5; // 4:0 RXFIFO Interrupt Level + Uint16 RXFFIENA:1; // 5 RXFIFO Interrupt Enable + Uint16 RXFFINTCLR:1; // 6 RXFIFO Interupt Clear + Uint16 RXFFINT:1; // 7 RXFIFO Interrupt Flag + Uint16 RXFFST:5; // 12:8 Receive FIFO Status + Uint16 RXFIFORESET:1; // 13 RXFIFO Reset + Uint16 RXFFOVFCLR:1; // 14 Receive FIFO Overflow Clear + Uint16 RXFFOVF:1; // 15 Receive FIFO Overflow Flag +}; + +union SPIFFRX_REG { + Uint16 all; + struct SPIFFRX_BITS bit; +}; + +struct SPIFFCT_BITS { // bits description + Uint16 TXDLY:8; // 7:0 FIFO Transmit Delay Bits + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union SPIFFCT_REG { + Uint16 all; + struct SPIFFCT_BITS bit; +}; + +struct SPIPRI_BITS { // bits description + Uint16 TRIWIRE:1; // 0 3-wire mode select bit + Uint16 STEINV:1; // 1 SPISTE inversion bit + Uint16 rsvd1:2; // 3:2 Reserved + Uint16 FREE:1; // 4 Free emulation mode + Uint16 SOFT:1; // 5 Soft emulation mode + Uint16 rsvd2:1; // 6 Reserved + Uint16 rsvd3:9; // 15:7 Reserved +}; + +union SPIPRI_REG { + Uint16 all; + struct SPIPRI_BITS bit; +}; + +struct SPI_REGS { + union SPICCR_REG SPICCR; // SPI Configuration Control Register + union SPICTL_REG SPICTL; // SPI Operation Control Register + union SPISTS_REG SPISTS; // SPI Status Register + Uint16 rsvd1; // Reserved + union SPIBRR_REG SPIBRR; // SPI Baud Rate Register + Uint16 rsvd2; // Reserved + Uint16 SPIRXEMU; // SPI Emulation Buffer Register + Uint16 SPIRXBUF; // SPI Serial Input Buffer Register + Uint16 SPITXBUF; // SPI Serial Output Buffer Register + Uint16 SPIDAT; // SPI Serial Data Register + union SPIFFTX_REG SPIFFTX; // SPI FIFO Transmit Register + union SPIFFRX_REG SPIFFRX; // SPI FIFO Receive Register + union SPIFFCT_REG SPIFFCT; // SPI FIFO Control Register + Uint16 rsvd3[2]; // Reserved + union SPIPRI_REG SPIPRI; // SPI Priority Control Register +}; + +//--------------------------------------------------------------------------- +// SPI External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct SPI_REGS SpiaRegs; +extern volatile struct SPI_REGS SpibRegs; +extern volatile struct SPI_REGS SpicRegs; +#endif +#ifdef CPU2 +extern volatile struct SPI_REGS SpiaRegs; +extern volatile struct SPI_REGS SpibRegs; +extern volatile struct SPI_REGS SpicRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_sysctrl.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_sysctrl.h new file mode 100644 index 0000000000..dd438aed5f --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_sysctrl.h @@ -0,0 +1,1964 @@ +//########################################################################### +// +// FILE: F2837xD_sysctrl.h +// +// TITLE: SYSCTRL Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_SYSCTRL_H__ +#define __F2837xD_SYSCTRL_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// SYSCTRL Individual Register Bit Definitions: + +struct DEVCFGLOCK1_BITS { // bits description + Uint16 CPUSEL0:1; // 0 Lock bit for CPUSEL0 register + Uint16 CPUSEL1:1; // 1 Lock bit for CPUSEL1 register + Uint16 CPUSEL2:1; // 2 Lock bit for CPUSEL2 register + Uint16 CPUSEL3:1; // 3 Lock bit for CPUSEL3 register + Uint16 CPUSEL4:1; // 4 Lock bit for CPUSEL4 register + Uint16 CPUSEL5:1; // 5 Lock bit for CPUSEL5 register + Uint16 CPUSEL6:1; // 6 Lock bit for CPUSEL6 register + Uint16 CPUSEL7:1; // 7 Lock bit for CPUSEL7 register + Uint16 CPUSEL8:1; // 8 Lock bit for CPUSEL8 register + Uint16 CPUSEL9:1; // 9 Lock bit for CPUSEL9 register + Uint16 CPUSEL10:1; // 10 Lock bit for CPUSEL10 register + Uint16 CPUSEL11:1; // 11 Lock bit for CPUSEL11 register + Uint16 CPUSEL12:1; // 12 Lock bit for CPUSEL12 register + Uint16 CPUSEL13:1; // 13 Lock bit for CPUSEL13 register + Uint16 CPUSEL14:1; // 14 Lock bit for CPUSEL14 register + Uint16 rsvd1:1; // 15 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DEVCFGLOCK1_REG { + Uint32 all; + struct DEVCFGLOCK1_BITS bit; +}; + +struct PARTIDL_BITS { // bits description + Uint16 rsvd1:3; // 2:0 Reserved + Uint16 rsvd2:2; // 4:3 Reserved + Uint16 rsvd3:1; // 5 Reserved + Uint16 QUAL:2; // 7:6 Qualification Status + Uint16 PIN_COUNT:3; // 10:8 Device Pin Count + Uint16 rsvd4:1; // 11 Reserved + Uint16 rsvd5:1; // 12 Reserved + Uint16 INSTASPIN:2; // 14:13 Motorware feature set + Uint16 rsvd6:1; // 15 Reserved + Uint16 FLASH_SIZE:8; // 23:16 Flash size in KB + Uint16 rsvd7:4; // 27:24 Reserved + Uint16 PARTID_FORMAT_REVISION:4; // 31:28 Revision of the PARTID format +}; + +union PARTIDL_REG { + Uint32 all; + struct PARTIDL_BITS bit; +}; + +struct PARTIDH_BITS { // bits description + Uint16 rsvd1:8; // 7:0 Reserved + Uint16 FAMILY:8; // 15:8 Device family + Uint16 PARTNO:8; // 23:16 Device part number + Uint16 DEVICE_CLASS_ID:8; // 31:24 Device class ID +}; + +union PARTIDH_REG { + Uint32 all; + struct PARTIDH_BITS bit; +}; + +struct DC0_BITS { // bits description + Uint16 SINGLE_CORE:1; // 0 Single Core vs Dual Core + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC0_REG { + Uint32 all; + struct DC0_BITS bit; +}; + +struct DC1_BITS { // bits description + Uint16 CPU1_FPU_TMU:1; // 0 CPU1's FPU1+TMU1 + Uint16 CPU2_FPU_TMU:1; // 1 CPU2's FPU2+TMU2 + Uint16 CPU1_VCU:1; // 2 CPU1's VCU + Uint16 CPU2_VCU:1; // 3 CPU2's VCU + Uint16 rsvd1:2; // 5:4 Reserved + Uint16 CPU1_CLA1:1; // 6 CPU1.CLA1 + Uint16 rsvd2:1; // 7 Reserved + Uint16 CPU2_CLA1:1; // 8 CPU2.CLA1 + Uint16 rsvd3:1; // 9 Reserved + Uint16 rsvd4:6; // 15:10 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union DC1_REG { + Uint32 all; + struct DC1_BITS bit; +}; + +struct DC2_BITS { // bits description + Uint16 EMIF1:1; // 0 EMIF1 + Uint16 EMIF2:1; // 1 EMIF2 + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC2_REG { + Uint32 all; + struct DC2_BITS bit; +}; + +struct DC3_BITS { // bits description + Uint16 EPWM1:1; // 0 EPWM1 + Uint16 EPWM2:1; // 1 EPWM2 + Uint16 EPWM3:1; // 2 EPWM3 + Uint16 EPWM4:1; // 3 EPWM4 + Uint16 EPWM5:1; // 4 EPWM5 + Uint16 EPWM6:1; // 5 EPWM6 + Uint16 EPWM7:1; // 6 EPWM7 + Uint16 EPWM8:1; // 7 EPWM8 + Uint16 EPWM9:1; // 8 EPWM9 + Uint16 EPWM10:1; // 9 EPWM10 + Uint16 EPWM11:1; // 10 EPWM11 + Uint16 EPWM12:1; // 11 EPWM12 + Uint16 rsvd1:1; // 12 Reserved + Uint16 rsvd2:1; // 13 Reserved + Uint16 rsvd3:1; // 14 Reserved + Uint16 rsvd4:1; // 15 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union DC3_REG { + Uint32 all; + struct DC3_BITS bit; +}; + +struct DC4_BITS { // bits description + Uint16 ECAP1:1; // 0 ECAP1 + Uint16 ECAP2:1; // 1 ECAP2 + Uint16 ECAP3:1; // 2 ECAP3 + Uint16 ECAP4:1; // 3 ECAP4 + Uint16 ECAP5:1; // 4 ECAP5 + Uint16 ECAP6:1; // 5 ECAP6 + Uint16 rsvd1:1; // 6 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:8; // 15:8 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union DC4_REG { + Uint32 all; + struct DC4_BITS bit; +}; + +struct DC5_BITS { // bits description + Uint16 EQEP1:1; // 0 EQEP1 + Uint16 EQEP2:1; // 1 EQEP2 + Uint16 EQEP3:1; // 2 EQEP3 + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union DC5_REG { + Uint32 all; + struct DC5_BITS bit; +}; + +struct DC6_BITS { // bits description + Uint16 CLB1:1; // 0 CLB1 + Uint16 CLB2:1; // 1 CLB2 + Uint16 CLB3:1; // 2 CLB3 + Uint16 CLB4:1; // 3 CLB4 + Uint16 rsvd1:1; // 4 Reserved + Uint16 rsvd2:1; // 5 Reserved + Uint16 rsvd3:1; // 6 Reserved + Uint16 rsvd4:1; // 7 Reserved + Uint16 rsvd5:8; // 15:8 Reserved + Uint16 rsvd6:16; // 31:16 Reserved +}; + +union DC6_REG { + Uint32 all; + struct DC6_BITS bit; +}; + +struct DC7_BITS { // bits description + Uint16 SD1:1; // 0 SD1 + Uint16 SD2:1; // 1 SD2 + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:1; // 5 Reserved + Uint16 rsvd5:1; // 6 Reserved + Uint16 rsvd6:1; // 7 Reserved + Uint16 rsvd7:8; // 15:8 Reserved + Uint16 rsvd8:16; // 31:16 Reserved +}; + +union DC7_REG { + Uint32 all; + struct DC7_BITS bit; +}; + +struct DC8_BITS { // bits description + Uint16 SCI_A:1; // 0 SCI_A + Uint16 SCI_B:1; // 1 SCI_B + Uint16 SCI_C:1; // 2 SCI_C + Uint16 SCI_D:1; // 3 SCI_D + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC8_REG { + Uint32 all; + struct DC8_BITS bit; +}; + +struct DC9_BITS { // bits description + Uint16 SPI_A:1; // 0 SPI_A + Uint16 SPI_B:1; // 1 SPI_B + Uint16 SPI_C:1; // 2 SPI_C + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:1; // 16 Reserved + Uint16 rsvd4:1; // 17 Reserved + Uint16 rsvd5:14; // 31:18 Reserved +}; + +union DC9_REG { + Uint32 all; + struct DC9_BITS bit; +}; + +struct DC10_BITS { // bits description + Uint16 I2C_A:1; // 0 I2C_A + Uint16 I2C_B:1; // 1 I2C_B + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:1; // 16 Reserved + Uint16 rsvd3:1; // 17 Reserved + Uint16 rsvd4:14; // 31:18 Reserved +}; + +union DC10_REG { + Uint32 all; + struct DC10_BITS bit; +}; + +struct DC11_BITS { // bits description + Uint16 CAN_A:1; // 0 CAN_A + Uint16 CAN_B:1; // 1 CAN_B + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:12; // 15:4 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union DC11_REG { + Uint32 all; + struct DC11_BITS bit; +}; + +struct DC12_BITS { // bits description + Uint16 McBSP_A:1; // 0 McBSP_A + Uint16 McBSP_B:1; // 1 McBSP_B + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 USB_A:2; // 17:16 Decides the capability of the USB_A Module + Uint16 rsvd2:2; // 19:18 Reserved + Uint16 rsvd3:12; // 31:20 Reserved +}; + +union DC12_REG { + Uint32 all; + struct DC12_BITS bit; +}; + +struct DC13_BITS { // bits description + Uint16 uPP_A:1; // 0 uPP_A + Uint16 rsvd1:1; // 1 Reserved + Uint16 rsvd2:14; // 15:2 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union DC13_REG { + Uint32 all; + struct DC13_BITS bit; +}; + +struct DC14_BITS { // bits description + Uint16 ADC_A:1; // 0 ADC_A + Uint16 ADC_B:1; // 1 ADC_B + Uint16 ADC_C:1; // 2 ADC_C + Uint16 ADC_D:1; // 3 ADC_D + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC14_REG { + Uint32 all; + struct DC14_BITS bit; +}; + +struct DC15_BITS { // bits description + Uint16 CMPSS1:1; // 0 CMPSS1 + Uint16 CMPSS2:1; // 1 CMPSS2 + Uint16 CMPSS3:1; // 2 CMPSS3 + Uint16 CMPSS4:1; // 3 CMPSS4 + Uint16 CMPSS5:1; // 4 CMPSS5 + Uint16 CMPSS6:1; // 5 CMPSS6 + Uint16 CMPSS7:1; // 6 CMPSS7 + Uint16 CMPSS8:1; // 7 CMPSS8 + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC15_REG { + Uint32 all; + struct DC15_BITS bit; +}; + +struct DC17_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 rsvd4:1; // 3 Reserved + Uint16 rsvd5:12; // 15:4 Reserved + Uint16 DAC_A:1; // 16 Buffered-DAC_A + Uint16 DAC_B:1; // 17 Buffered-DAC_B + Uint16 DAC_C:1; // 18 Buffered-DAC_C + Uint16 rsvd6:1; // 19 Reserved + Uint16 rsvd7:12; // 31:20 Reserved +}; + +union DC17_REG { + Uint32 all; + struct DC17_BITS bit; +}; + +struct DC18_BITS { // bits description + Uint16 LS0_1:1; // 0 LS0_1 + Uint16 LS1_1:1; // 1 LS1_1 + Uint16 LS2_1:1; // 2 LS2_1 + Uint16 LS3_1:1; // 3 LS3_1 + Uint16 LS4_1:1; // 4 LS4_1 + Uint16 LS5_1:1; // 5 LS5_1 + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC18_REG { + Uint32 all; + struct DC18_BITS bit; +}; + +struct DC19_BITS { // bits description + Uint16 LS0_2:1; // 0 LS0_2 + Uint16 LS1_2:1; // 1 LS1_2 + Uint16 LS2_2:1; // 2 LS2_2 + Uint16 LS3_2:1; // 3 LS3_2 + Uint16 LS4_2:1; // 4 LS4_2 + Uint16 LS5_2:1; // 5 LS5_2 + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DC19_REG { + Uint32 all; + struct DC19_BITS bit; +}; + +struct DC20_BITS { // bits description + Uint16 GS0:1; // 0 GS0 + Uint16 GS1:1; // 1 GS1 + Uint16 GS2:1; // 2 GS2 + Uint16 GS3:1; // 3 GS3 + Uint16 GS4:1; // 4 GS4 + Uint16 GS5:1; // 5 GS5 + Uint16 GS6:1; // 6 GS6 + Uint16 GS7:1; // 7 GS7 + Uint16 GS8:1; // 8 GS8 + Uint16 GS9:1; // 9 GS9 + Uint16 GS10:1; // 10 GS10 + Uint16 GS11:1; // 11 GS11 + Uint16 GS12:1; // 12 GS12 + Uint16 GS13:1; // 13 GS13 + Uint16 GS14:1; // 14 GS14 + Uint16 GS15:1; // 15 GS15 + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union DC20_REG { + Uint32 all; + struct DC20_BITS bit; +}; + +struct PERCNF1_BITS { // bits description + Uint16 ADC_A_MODE:1; // 0 ADC_A mode setting bit + Uint16 ADC_B_MODE:1; // 1 ADC_B mode setting bit + Uint16 ADC_C_MODE:1; // 2 ADC_C mode setting bit + Uint16 ADC_D_MODE:1; // 3 ADC_D mode setting bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 USB_A_PHY:1; // 16 USB_A_PHY + Uint16 rsvd2:1; // 17 Reserved + Uint16 rsvd3:14; // 31:18 Reserved +}; + +union PERCNF1_REG { + Uint32 all; + struct PERCNF1_BITS bit; +}; + +struct FUSEERR_BITS { // bits description + Uint16 ALERR:5; // 4:0 Efuse Autoload Error Status + Uint16 ERR:1; // 5 Efuse Self Test Error Status + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union FUSEERR_REG { + Uint32 all; + struct FUSEERR_BITS bit; +}; + +struct SOFTPRES0_BITS { // bits description + Uint16 CPU1_CLA1:1; // 0 CPU1_CLA1 software reset bit + Uint16 rsvd1:1; // 1 Reserved + Uint16 CPU2_CLA1:1; // 2 CPU2_CLA1 software reset bit + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:12; // 15:4 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union SOFTPRES0_REG { + Uint32 all; + struct SOFTPRES0_BITS bit; +}; + +struct SOFTPRES1_BITS { // bits description + Uint16 EMIF1:1; // 0 EMIF1 software reset bit + Uint16 EMIF2:1; // 1 EMIF2 software reset bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTPRES1_REG { + Uint32 all; + struct SOFTPRES1_BITS bit; +}; + +struct SOFTPRES2_BITS { // bits description + Uint16 EPWM1:1; // 0 EPWM1 software reset bit + Uint16 EPWM2:1; // 1 EPWM2 software reset bit + Uint16 EPWM3:1; // 2 EPWM3 software reset bit + Uint16 EPWM4:1; // 3 EPWM4 software reset bit + Uint16 EPWM5:1; // 4 EPWM5 software reset bit + Uint16 EPWM6:1; // 5 EPWM6 software reset bit + Uint16 EPWM7:1; // 6 EPWM7 software reset bit + Uint16 EPWM8:1; // 7 EPWM8 software reset bit + Uint16 EPWM9:1; // 8 EPWM9 software reset bit + Uint16 EPWM10:1; // 9 EPWM10 software reset bit + Uint16 EPWM11:1; // 10 EPWM11 software reset bit + Uint16 EPWM12:1; // 11 EPWM12 software reset bit + Uint16 rsvd1:1; // 12 Reserved + Uint16 rsvd2:1; // 13 Reserved + Uint16 rsvd3:1; // 14 Reserved + Uint16 rsvd4:1; // 15 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union SOFTPRES2_REG { + Uint32 all; + struct SOFTPRES2_BITS bit; +}; + +struct SOFTPRES3_BITS { // bits description + Uint16 ECAP1:1; // 0 ECAP1 software reset bit + Uint16 ECAP2:1; // 1 ECAP2 software reset bit + Uint16 ECAP3:1; // 2 ECAP3 software reset bit + Uint16 ECAP4:1; // 3 ECAP4 software reset bit + Uint16 ECAP5:1; // 4 ECAP5 software reset bit + Uint16 ECAP6:1; // 5 ECAP6 software reset bit + Uint16 rsvd1:1; // 6 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:8; // 15:8 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union SOFTPRES3_REG { + Uint32 all; + struct SOFTPRES3_BITS bit; +}; + +struct SOFTPRES4_BITS { // bits description + Uint16 EQEP1:1; // 0 EQEP1 software reset bit + Uint16 EQEP2:1; // 1 EQEP2 software reset bit + Uint16 EQEP3:1; // 2 EQEP3 software reset bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union SOFTPRES4_REG { + Uint32 all; + struct SOFTPRES4_BITS bit; +}; + +struct SOFTPRES6_BITS { // bits description + Uint16 SD1:1; // 0 SD1 software reset bit + Uint16 SD2:1; // 1 SD2 software reset bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:1; // 5 Reserved + Uint16 rsvd5:1; // 6 Reserved + Uint16 rsvd6:1; // 7 Reserved + Uint16 rsvd7:8; // 15:8 Reserved + Uint16 rsvd8:16; // 31:16 Reserved +}; + +union SOFTPRES6_REG { + Uint32 all; + struct SOFTPRES6_BITS bit; +}; + +struct SOFTPRES7_BITS { // bits description + Uint16 SCI_A:1; // 0 SCI_A software reset bit + Uint16 SCI_B:1; // 1 SCI_B software reset bit + Uint16 SCI_C:1; // 2 SCI_C software reset bit + Uint16 SCI_D:1; // 3 SCI_D software reset bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTPRES7_REG { + Uint32 all; + struct SOFTPRES7_BITS bit; +}; + +struct SOFTPRES8_BITS { // bits description + Uint16 SPI_A:1; // 0 SPI_A software reset bit + Uint16 SPI_B:1; // 1 SPI_B software reset bit + Uint16 SPI_C:1; // 2 SPI_C software reset bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:1; // 16 Reserved + Uint16 rsvd4:1; // 17 Reserved + Uint16 rsvd5:14; // 31:18 Reserved +}; + +union SOFTPRES8_REG { + Uint32 all; + struct SOFTPRES8_BITS bit; +}; + +struct SOFTPRES9_BITS { // bits description + Uint16 I2C_A:1; // 0 I2C_A software reset bit + Uint16 I2C_B:1; // 1 I2C_B software reset bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:1; // 16 Reserved + Uint16 rsvd3:1; // 17 Reserved + Uint16 rsvd4:14; // 31:18 Reserved +}; + +union SOFTPRES9_REG { + Uint32 all; + struct SOFTPRES9_BITS bit; +}; + +struct SOFTPRES11_BITS { // bits description + Uint16 McBSP_A:1; // 0 McBSP_A software reset bit + Uint16 McBSP_B:1; // 1 McBSP_B software reset bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 USB_A:1; // 16 USB_A software reset bit + Uint16 rsvd2:1; // 17 Reserved + Uint16 rsvd3:14; // 31:18 Reserved +}; + +union SOFTPRES11_REG { + Uint32 all; + struct SOFTPRES11_BITS bit; +}; + +struct SOFTPRES13_BITS { // bits description + Uint16 ADC_A:1; // 0 ADC_A software reset bit + Uint16 ADC_B:1; // 1 ADC_B software reset bit + Uint16 ADC_C:1; // 2 ADC_C software reset bit + Uint16 ADC_D:1; // 3 ADC_D software reset bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTPRES13_REG { + Uint32 all; + struct SOFTPRES13_BITS bit; +}; + +struct SOFTPRES14_BITS { // bits description + Uint16 CMPSS1:1; // 0 CMPSS1 software reset bit + Uint16 CMPSS2:1; // 1 CMPSS2 software reset bit + Uint16 CMPSS3:1; // 2 CMPSS3 software reset bit + Uint16 CMPSS4:1; // 3 CMPSS4 software reset bit + Uint16 CMPSS5:1; // 4 CMPSS5 software reset bit + Uint16 CMPSS6:1; // 5 CMPSS6 software reset bit + Uint16 CMPSS7:1; // 6 CMPSS7 software reset bit + Uint16 CMPSS8:1; // 7 CMPSS8 software reset bit + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SOFTPRES14_REG { + Uint32 all; + struct SOFTPRES14_BITS bit; +}; + +struct SOFTPRES16_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 rsvd4:1; // 3 Reserved + Uint16 rsvd5:12; // 15:4 Reserved + Uint16 DAC_A:1; // 16 Buffered_DAC_A software reset bit + Uint16 DAC_B:1; // 17 Buffered_DAC_B software reset bit + Uint16 DAC_C:1; // 18 Buffered_DAC_C software reset bit + Uint16 rsvd6:1; // 19 Reserved + Uint16 rsvd7:12; // 31:20 Reserved +}; + +union SOFTPRES16_REG { + Uint32 all; + struct SOFTPRES16_BITS bit; +}; + +struct CPUSEL0_BITS { // bits description + Uint16 EPWM1:1; // 0 EPWM1 CPU select bit + Uint16 EPWM2:1; // 1 EPWM2 CPU select bit + Uint16 EPWM3:1; // 2 EPWM3 CPU select bit + Uint16 EPWM4:1; // 3 EPWM4 CPU select bit + Uint16 EPWM5:1; // 4 EPWM5 CPU select bit + Uint16 EPWM6:1; // 5 EPWM6 CPU select bit + Uint16 EPWM7:1; // 6 EPWM7 CPU select bit + Uint16 EPWM8:1; // 7 EPWM8 CPU select bit + Uint16 EPWM9:1; // 8 EPWM9 CPU select bit + Uint16 EPWM10:1; // 9 EPWM10 CPU select bit + Uint16 EPWM11:1; // 10 EPWM11 CPU select bit + Uint16 EPWM12:1; // 11 EPWM12 CPU select bit + Uint16 rsvd1:1; // 12 Reserved + Uint16 rsvd2:1; // 13 Reserved + Uint16 rsvd3:1; // 14 Reserved + Uint16 rsvd4:1; // 15 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union CPUSEL0_REG { + Uint32 all; + struct CPUSEL0_BITS bit; +}; + +struct CPUSEL1_BITS { // bits description + Uint16 ECAP1:1; // 0 ECAP1 CPU select bit + Uint16 ECAP2:1; // 1 ECAP2 CPU select bit + Uint16 ECAP3:1; // 2 ECAP3 CPU select bit + Uint16 ECAP4:1; // 3 ECAP4 CPU select bit + Uint16 ECAP5:1; // 4 ECAP5 CPU select bit + Uint16 ECAP6:1; // 5 ECAP6 CPU select bit + Uint16 rsvd1:1; // 6 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:8; // 15:8 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union CPUSEL1_REG { + Uint32 all; + struct CPUSEL1_BITS bit; +}; + +struct CPUSEL2_BITS { // bits description + Uint16 EQEP1:1; // 0 EQEP1 CPU select bit + Uint16 EQEP2:1; // 1 EQEP2 CPU select bit + Uint16 EQEP3:1; // 2 EQEP3 CPU select bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CPUSEL2_REG { + Uint32 all; + struct CPUSEL2_BITS bit; +}; + +struct CPUSEL4_BITS { // bits description + Uint16 SD1:1; // 0 SD1 CPU select bit + Uint16 SD2:1; // 1 SD2 CPU select bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:1; // 5 Reserved + Uint16 rsvd5:1; // 6 Reserved + Uint16 rsvd6:1; // 7 Reserved + Uint16 rsvd7:8; // 15:8 Reserved + Uint16 rsvd8:16; // 31:16 Reserved +}; + +union CPUSEL4_REG { + Uint32 all; + struct CPUSEL4_BITS bit; +}; + +struct CPUSEL5_BITS { // bits description + Uint16 SCI_A:1; // 0 SCI_A CPU select bit + Uint16 SCI_B:1; // 1 SCI_B CPU select bit + Uint16 SCI_C:1; // 2 SCI_C CPU select bit + Uint16 SCI_D:1; // 3 SCI_D CPU select bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CPUSEL5_REG { + Uint32 all; + struct CPUSEL5_BITS bit; +}; + +struct CPUSEL6_BITS { // bits description + Uint16 SPI_A:1; // 0 SPI_A CPU select bit + Uint16 SPI_B:1; // 1 SPI_B CPU select bit + Uint16 SPI_C:1; // 2 SPI_C CPU select bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:1; // 16 Reserved + Uint16 rsvd4:1; // 17 Reserved + Uint16 rsvd5:14; // 31:18 Reserved +}; + +union CPUSEL6_REG { + Uint32 all; + struct CPUSEL6_BITS bit; +}; + +struct CPUSEL7_BITS { // bits description + Uint16 I2C_A:1; // 0 I2C_A CPU select bit + Uint16 I2C_B:1; // 1 I2C_B CPU select bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:1; // 16 Reserved + Uint16 rsvd3:1; // 17 Reserved + Uint16 rsvd4:14; // 31:18 Reserved +}; + +union CPUSEL7_REG { + Uint32 all; + struct CPUSEL7_BITS bit; +}; + +struct CPUSEL8_BITS { // bits description + Uint16 CAN_A:1; // 0 CAN_A CPU select bit + Uint16 CAN_B:1; // 1 CAN_B CPU select bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:12; // 15:4 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union CPUSEL8_REG { + Uint32 all; + struct CPUSEL8_BITS bit; +}; + +struct CPUSEL9_BITS { // bits description + Uint16 McBSP_A:1; // 0 McBSP_A CPU select bit + Uint16 McBSP_B:1; // 1 McBSP_B CPU select bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CPUSEL9_REG { + Uint32 all; + struct CPUSEL9_BITS bit; +}; + +struct CPUSEL11_BITS { // bits description + Uint16 ADC_A:1; // 0 ADC_A CPU select bit + Uint16 ADC_B:1; // 1 ADC_B CPU select bit + Uint16 ADC_C:1; // 2 ADC_C CPU select bit + Uint16 ADC_D:1; // 3 ADC_D CPU select bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CPUSEL11_REG { + Uint32 all; + struct CPUSEL11_BITS bit; +}; + +struct CPUSEL12_BITS { // bits description + Uint16 CMPSS1:1; // 0 CMPSS1 CPU select bit + Uint16 CMPSS2:1; // 1 CMPSS2 CPU select bit + Uint16 CMPSS3:1; // 2 CMPSS3 CPU select bit + Uint16 CMPSS4:1; // 3 CMPSS4 CPU select bit + Uint16 CMPSS5:1; // 4 CMPSS5 CPU select bit + Uint16 CMPSS6:1; // 5 CMPSS6 CPU select bit + Uint16 CMPSS7:1; // 6 CMPSS7 CPU select bit + Uint16 CMPSS8:1; // 7 CMPSS8 CPU select bit + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CPUSEL12_REG { + Uint32 all; + struct CPUSEL12_BITS bit; +}; + +struct CPUSEL14_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 rsvd4:1; // 3 Reserved + Uint16 rsvd5:12; // 15:4 Reserved + Uint16 DAC_A:1; // 16 Buffered_DAC_A CPU select bit + Uint16 DAC_B:1; // 17 Buffered_DAC_B CPU select bit + Uint16 DAC_C:1; // 18 Buffered_DAC_C CPU select bit + Uint16 rsvd6:1; // 19 Reserved + Uint16 rsvd7:12; // 31:20 Reserved +}; + +union CPUSEL14_REG { + Uint32 all; + struct CPUSEL14_BITS bit; +}; + +struct CPU2RESCTL_BITS { // bits description + Uint16 RESET:1; // 0 CPU2 Reset Control bit + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register +}; + +union CPU2RESCTL_REG { + Uint32 all; + struct CPU2RESCTL_BITS bit; +}; + +struct RSTSTAT_BITS { // bits description + Uint16 CPU2RES:1; // 0 CPU2 Reset Status bit + Uint16 CPU2NMIWDRST:1; // 1 Indicates whether a CPU2.NMIWD reset was issued to CPU2 + Uint16 CPU2HWBISTRST0:1; // 2 Indicates whether a HWBIST reset was issued to CPU2 + Uint16 CPU2HWBISTRST1:1; // 3 Indicates whether a HWBIST reset was issued to CPU2 + Uint16 rsvd1:12; // 15:4 Reserved +}; + +union RSTSTAT_REG { + Uint16 all; + struct RSTSTAT_BITS bit; +}; + +struct LPMSTAT_BITS { // bits description + Uint16 CPU2LPMSTAT:2; // 1:0 CPU2 LPM Status + Uint16 rsvd1:14; // 15:2 Reserved +}; + +union LPMSTAT_REG { + Uint16 all; + struct LPMSTAT_BITS bit; +}; + +struct SYSDBGCTL_BITS { // bits description + Uint16 BIT_0:1; // 0 Used in PLL startup. Only reset by POR. + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SYSDBGCTL_REG { + Uint32 all; + struct SYSDBGCTL_BITS bit; +}; + +struct DEV_CFG_REGS { + union DEVCFGLOCK1_REG DEVCFGLOCK1; // Lock bit for CPUSELx registers + Uint16 rsvd1[6]; // Reserved + union PARTIDL_REG PARTIDL; // Lower 32-bit of Device PART Identification Number + union PARTIDH_REG PARTIDH; // Upper 32-bit of Device PART Identification Number + Uint32 REVID; // Device Revision Number + Uint16 rsvd2[2]; // Reserved + union DC0_REG DC0; // Device Capability: Device Information + union DC1_REG DC1; // Device Capability: Processing Block Customization + union DC2_REG DC2; // Device Capability: EMIF Customization + union DC3_REG DC3; // Device Capability: Peripheral Customization + union DC4_REG DC4; // Device Capability: Peripheral Customization + union DC5_REG DC5; // Device Capability: Peripheral Customization + union DC6_REG DC6; // Device Capability: Peripheral Customization + union DC7_REG DC7; // Device Capability: Peripheral Customization + union DC8_REG DC8; // Device Capability: Peripheral Customization + union DC9_REG DC9; // Device Capability: Peripheral Customization + union DC10_REG DC10; // Device Capability: Peripheral Customization + union DC11_REG DC11; // Device Capability: Peripheral Customization + union DC12_REG DC12; // Device Capability: Peripheral Customization + union DC13_REG DC13; // Device Capability: Peripheral Customization + union DC14_REG DC14; // Device Capability: Analog Modules Customization + union DC15_REG DC15; // Device Capability: Analog Modules Customization + Uint16 rsvd3[2]; // Reserved + union DC17_REG DC17; // Device Capability: Analog Modules Customization + union DC18_REG DC18; // Device Capability: CPU1 Lx SRAM Customization + union DC19_REG DC19; // Device Capability: CPU2 Lx SRAM Customization + union DC20_REG DC20; // Device Capability: GSx SRAM Customization + Uint16 rsvd4[38]; // Reserved + union PERCNF1_REG PERCNF1; // Peripheral Configuration register + Uint16 rsvd5[18]; // Reserved + union FUSEERR_REG FUSEERR; // e-Fuse error Status register + Uint16 rsvd6[12]; // Reserved + union SOFTPRES0_REG SOFTPRES0; // Processing Block Software Reset register + union SOFTPRES1_REG SOFTPRES1; // EMIF Software Reset register + union SOFTPRES2_REG SOFTPRES2; // Peripheral Software Reset register + union SOFTPRES3_REG SOFTPRES3; // Peripheral Software Reset register + union SOFTPRES4_REG SOFTPRES4; // Peripheral Software Reset register + Uint16 rsvd7[2]; // Reserved + union SOFTPRES6_REG SOFTPRES6; // Peripheral Software Reset register + union SOFTPRES7_REG SOFTPRES7; // Peripheral Software Reset register + union SOFTPRES8_REG SOFTPRES8; // Peripheral Software Reset register + union SOFTPRES9_REG SOFTPRES9; // Peripheral Software Reset register + Uint16 rsvd8[2]; // Reserved + union SOFTPRES11_REG SOFTPRES11; // Peripheral Software Reset register + Uint16 rsvd9[2]; // Reserved + union SOFTPRES13_REG SOFTPRES13; // Peripheral Software Reset register + union SOFTPRES14_REG SOFTPRES14; // Peripheral Software Reset register + Uint16 rsvd10[2]; // Reserved + union SOFTPRES16_REG SOFTPRES16; // Peripheral Software Reset register + Uint16 rsvd11[50]; // Reserved + union CPUSEL0_REG CPUSEL0; // CPU Select register for common peripherals + union CPUSEL1_REG CPUSEL1; // CPU Select register for common peripherals + union CPUSEL2_REG CPUSEL2; // CPU Select register for common peripherals + Uint16 rsvd12[2]; // Reserved + union CPUSEL4_REG CPUSEL4; // CPU Select register for common peripherals + union CPUSEL5_REG CPUSEL5; // CPU Select register for common peripherals + union CPUSEL6_REG CPUSEL6; // CPU Select register for common peripherals + union CPUSEL7_REG CPUSEL7; // CPU Select register for common peripherals + union CPUSEL8_REG CPUSEL8; // CPU Select register for common peripherals + union CPUSEL9_REG CPUSEL9; // CPU Select register for common peripherals + Uint16 rsvd13[2]; // Reserved + union CPUSEL11_REG CPUSEL11; // CPU Select register for common peripherals + union CPUSEL12_REG CPUSEL12; // CPU Select register for common peripherals + Uint16 rsvd14[2]; // Reserved + union CPUSEL14_REG CPUSEL14; // CPU Select register for common peripherals + Uint16 rsvd15[46]; // Reserved + union CPU2RESCTL_REG CPU2RESCTL; // CPU2 Reset Control Register + union RSTSTAT_REG RSTSTAT; // Reset Status register for secondary C28x CPUs + union LPMSTAT_REG LPMSTAT; // LPM Status Register for secondary C28x CPUs + Uint16 rsvd16[6]; // Reserved + union SYSDBGCTL_REG SYSDBGCTL; // System Debug Control register +}; + +struct CLKSEM_BITS { // bits description + Uint16 SEM:2; // 1:0 Semaphore for CLKCFG Ownership by CPU1 or CPU2 + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 KEY:16; // 31:16 Key Qualifier for writes to this register +}; + +union CLKSEM_REG { + Uint32 all; + struct CLKSEM_BITS bit; +}; + +struct CLKCFGLOCK1_BITS { // bits description + Uint16 CLKSRCCTL1:1; // 0 Lock bit for CLKSRCCTL1 register + Uint16 CLKSRCCTL2:1; // 1 Lock bit for CLKSRCCTL2 register + Uint16 CLKSRCCTL3:1; // 2 Lock bit for CLKSRCCTL3 register + Uint16 SYSPLLCTL1:1; // 3 Lock bit for SYSPLLCTL1 register + Uint16 SYSPLLCTL2:1; // 4 Lock bit for SYSPLLCTL2 register + Uint16 SYSPLLCTL3:1; // 5 Lock bit for SYSPLLCTL3 register + Uint16 SYSPLLMULT:1; // 6 Lock bit for SYSPLLMULT register + Uint16 AUXPLLCTL1:1; // 7 Lock bit for AUXPLLCTL1 register + Uint16 rsvd1:1; // 8 Reserved + Uint16 rsvd2:1; // 9 Reserved + Uint16 AUXPLLMULT:1; // 10 Lock bit for AUXPLLMULT register + Uint16 SYSCLKDIVSEL:1; // 11 Lock bit for SYSCLKDIVSEL register + Uint16 AUXCLKDIVSEL:1; // 12 Lock bit for AUXCLKDIVSEL register + Uint16 PERCLKDIVSEL:1; // 13 Lock bit for PERCLKDIVSEL register + Uint16 rsvd3:1; // 14 Reserved + Uint16 LOSPCP:1; // 15 Lock bit for LOSPCP register + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union CLKCFGLOCK1_REG { + Uint32 all; + struct CLKCFGLOCK1_BITS bit; +}; + +struct CLKSRCCTL1_BITS { // bits description + Uint16 OSCCLKSRCSEL:2; // 1:0 OSCCLK Source Select Bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 INTOSC2OFF:1; // 3 Internal Oscillator 2 Off Bit + Uint16 XTALOFF:1; // 4 Crystal (External) Oscillator Off Bit + Uint16 WDHALTI:1; // 5 Watchdog HALT Mode Ignore Bit + Uint16 rsvd2:10; // 15:6 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CLKSRCCTL1_REG { + Uint32 all; + struct CLKSRCCTL1_BITS bit; +}; + +struct CLKSRCCTL2_BITS { // bits description + Uint16 AUXOSCCLKSRCSEL:2; // 1:0 AUXOSCCLK Source Select Bit + Uint16 CANABCLKSEL:2; // 3:2 CANA Bit Clock Source Select Bit + Uint16 CANBBCLKSEL:2; // 5:4 CANB Bit Clock Source Select Bit + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 rsvd2:2; // 9:8 Reserved + Uint16 rsvd3:6; // 15:10 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union CLKSRCCTL2_REG { + Uint32 all; + struct CLKSRCCTL2_BITS bit; +}; + +struct CLKSRCCTL3_BITS { // bits description + Uint16 XCLKOUTSEL:3; // 2:0 XCLKOUT Source Select Bit + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CLKSRCCTL3_REG { + Uint32 all; + struct CLKSRCCTL3_BITS bit; +}; + +struct SYSPLLCTL1_BITS { // bits description + Uint16 PLLEN:1; // 0 SYSPLL enable/disable bit + Uint16 PLLCLKEN:1; // 1 SYSPLL bypassed or included in the PLLSYSCLK path + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SYSPLLCTL1_REG { + Uint32 all; + struct SYSPLLCTL1_BITS bit; +}; + +struct SYSPLLMULT_BITS { // bits description + Uint16 IMULT:7; // 6:0 SYSPLL Integer Multiplier + Uint16 rsvd1:1; // 7 Reserved + Uint16 FMULT:2; // 9:8 SYSPLL Fractional Multiplier + Uint16 rsvd2:6; // 15:10 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union SYSPLLMULT_REG { + Uint32 all; + struct SYSPLLMULT_BITS bit; +}; + +struct SYSPLLSTS_BITS { // bits description + Uint16 LOCKS:1; // 0 SYSPLL Lock Status Bit + Uint16 SLIPS:1; // 1 SYSPLL Slip Status Bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SYSPLLSTS_REG { + Uint32 all; + struct SYSPLLSTS_BITS bit; +}; + +struct AUXPLLCTL1_BITS { // bits description + Uint16 PLLEN:1; // 0 AUXPLL enable/disable bit + Uint16 PLLCLKEN:1; // 1 AUXPLL bypassed or included in the AUXPLLCLK path + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union AUXPLLCTL1_REG { + Uint32 all; + struct AUXPLLCTL1_BITS bit; +}; + +struct AUXPLLMULT_BITS { // bits description + Uint16 IMULT:7; // 6:0 AUXPLL Integer Multiplier + Uint16 rsvd1:1; // 7 Reserved + Uint16 FMULT:2; // 9:8 AUXPLL Fractional Multiplier + Uint16 rsvd2:6; // 15:10 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union AUXPLLMULT_REG { + Uint32 all; + struct AUXPLLMULT_BITS bit; +}; + +struct AUXPLLSTS_BITS { // bits description + Uint16 LOCKS:1; // 0 AUXPLL Lock Status Bit + Uint16 SLIPS:1; // 1 AUXPLL Slip Status Bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union AUXPLLSTS_REG { + Uint32 all; + struct AUXPLLSTS_BITS bit; +}; + +struct SYSCLKDIVSEL_BITS { // bits description + Uint16 PLLSYSCLKDIV:6; // 5:0 PLLSYSCLK Divide Select + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SYSCLKDIVSEL_REG { + Uint32 all; + struct SYSCLKDIVSEL_BITS bit; +}; + +struct AUXCLKDIVSEL_BITS { // bits description + Uint16 AUXPLLDIV:2; // 1:0 AUXPLLCLK Divide Select + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union AUXCLKDIVSEL_REG { + Uint32 all; + struct AUXCLKDIVSEL_BITS bit; +}; + +struct PERCLKDIVSEL_BITS { // bits description + Uint16 EPWMCLKDIV:2; // 1:0 EPWM Clock Divide Select + Uint16 rsvd1:2; // 3:2 Reserved + Uint16 EMIF1CLKDIV:1; // 4 EMIF1 Clock Divide Select + Uint16 rsvd2:1; // 5 Reserved + Uint16 EMIF2CLKDIV:1; // 6 EMIF2 Clock Divide Select + Uint16 rsvd3:9; // 15:7 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union PERCLKDIVSEL_REG { + Uint32 all; + struct PERCLKDIVSEL_BITS bit; +}; + +struct XCLKOUTDIVSEL_BITS { // bits description + Uint16 XCLKOUTDIV:2; // 1:0 XCLKOUT Divide Select + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union XCLKOUTDIVSEL_REG { + Uint32 all; + struct XCLKOUTDIVSEL_BITS bit; +}; + +struct LOSPCP_BITS { // bits description + Uint16 LSPCLKDIV:3; // 2:0 LSPCLK Divide Select + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union LOSPCP_REG { + Uint32 all; + struct LOSPCP_BITS bit; +}; + +struct MCDCR_BITS { // bits description + Uint16 MCLKSTS:1; // 0 Missing Clock Status Bit + Uint16 MCLKCLR:1; // 1 Missing Clock Clear Bit + Uint16 MCLKOFF:1; // 2 Missing Clock Detect Off Bit + Uint16 OSCOFF:1; // 3 Oscillator Clock Off Bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union MCDCR_REG { + Uint32 all; + struct MCDCR_BITS bit; +}; + +struct X1CNT_BITS { // bits description + Uint16 X1CNT:10; // 9:0 X1 Counter + Uint16 rsvd1:6; // 15:10 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union X1CNT_REG { + Uint32 all; + struct X1CNT_BITS bit; +}; + +struct CLK_CFG_REGS { + union CLKSEM_REG CLKSEM; // Clock Control Semaphore Register + union CLKCFGLOCK1_REG CLKCFGLOCK1; // Lock bit for CLKCFG registers + Uint16 rsvd1[4]; // Reserved + union CLKSRCCTL1_REG CLKSRCCTL1; // Clock Source Control register-1 + union CLKSRCCTL2_REG CLKSRCCTL2; // Clock Source Control register-2 + union CLKSRCCTL3_REG CLKSRCCTL3; // Clock Source Control register-3 + union SYSPLLCTL1_REG SYSPLLCTL1; // SYSPLL Control register-1 + Uint16 rsvd2[4]; // Reserved + union SYSPLLMULT_REG SYSPLLMULT; // SYSPLL Multiplier register + union SYSPLLSTS_REG SYSPLLSTS; // SYSPLL Status register + union AUXPLLCTL1_REG AUXPLLCTL1; // AUXPLL Control register-1 + Uint16 rsvd3[4]; // Reserved + union AUXPLLMULT_REG AUXPLLMULT; // AUXPLL Multiplier register + union AUXPLLSTS_REG AUXPLLSTS; // AUXPLL Status register + union SYSCLKDIVSEL_REG SYSCLKDIVSEL; // System Clock Divider Select register + union AUXCLKDIVSEL_REG AUXCLKDIVSEL; // Auxillary Clock Divider Select register + union PERCLKDIVSEL_REG PERCLKDIVSEL; // Peripheral Clock Divider Selet register + union XCLKOUTDIVSEL_REG XCLKOUTDIVSEL; // XCLKOUT Divider Select register + Uint16 rsvd4[2]; // Reserved + union LOSPCP_REG LOSPCP; // Low Speed Clock Source Prescalar + union MCDCR_REG MCDCR; // Missing Clock Detect Control Register + union X1CNT_REG X1CNT; // 10-bit Counter on X1 Clock +}; + +struct CPUSYSLOCK1_BITS { // bits description + Uint16 HIBBOOTMODE:1; // 0 Lock bit for HIBBOOTMODE register + Uint16 IORESTOREADDR:1; // 1 Lock bit for IORESTOREADDR Register + Uint16 PIEVERRADDR:1; // 2 Lock bit for PIEVERRADDR Register + Uint16 PCLKCR0:1; // 3 Lock bit for PCLKCR0 Register + Uint16 PCLKCR1:1; // 4 Lock bit for PCLKCR1 Register + Uint16 PCLKCR2:1; // 5 Lock bit for PCLKCR2 Register + Uint16 PCLKCR3:1; // 6 Lock bit for PCLKCR3 Register + Uint16 PCLKCR4:1; // 7 Lock bit for PCLKCR4 Register + Uint16 PCLKCR5:1; // 8 Lock bit for PCLKCR5 Register + Uint16 PCLKCR6:1; // 9 Lock bit for PCLKCR6 Register + Uint16 PCLKCR7:1; // 10 Lock bit for PCLKCR7 Register + Uint16 PCLKCR8:1; // 11 Lock bit for PCLKCR8 Register + Uint16 PCLKCR9:1; // 12 Lock bit for PCLKCR9 Register + Uint16 PCLKCR10:1; // 13 Lock bit for PCLKCR10 Register + Uint16 PCLKCR11:1; // 14 Lock bit for PCLKCR11 Register + Uint16 PCLKCR12:1; // 15 Lock bit for PCLKCR12 Register + Uint16 PCLKCR13:1; // 16 Lock bit for PCLKCR13 Register + Uint16 PCLKCR14:1; // 17 Lock bit for PCLKCR14 Register + Uint16 PCLKCR15:1; // 18 Lock bit for PCLKCR15 Register + Uint16 PCLKCR16:1; // 19 Lock bit for PCLKCR16 Register + Uint16 SECMSEL:1; // 20 Lock bit for SECMSEL Register + Uint16 LPMCR:1; // 21 Lock bit for LPMCR Register + Uint16 GPIOLPMSEL0:1; // 22 Lock bit for GPIOLPMSEL0 Register + Uint16 GPIOLPMSEL1:1; // 23 Lock bit for GPIOLPMSEL1 Register + Uint16 rsvd1:8; // 31:24 Reserved +}; + +union CPUSYSLOCK1_REG { + Uint32 all; + struct CPUSYSLOCK1_BITS bit; +}; + +struct IORESTOREADDR_BITS { // bits description + Uint32 ADDR:22; // 21:0 restoreIO() routine address + Uint16 rsvd1:10; // 31:22 Reserved +}; + +union IORESTOREADDR_REG { + Uint32 all; + struct IORESTOREADDR_BITS bit; +}; + +struct PIEVERRADDR_BITS { // bits description + Uint32 ADDR:22; // 21:0 PIE Vector Fetch Error Handler Routine Address + Uint16 rsvd1:10; // 31:22 Reserved +}; + +union PIEVERRADDR_REG { + Uint32 all; + struct PIEVERRADDR_BITS bit; +}; + +struct PCLKCR0_BITS { // bits description + Uint16 CLA1:1; // 0 CLA1 Clock Enable Bit + Uint16 rsvd1:1; // 1 Reserved + Uint16 DMA:1; // 2 DMA Clock Enable bit + Uint16 CPUTIMER0:1; // 3 CPUTIMER0 Clock Enable bit + Uint16 CPUTIMER1:1; // 4 CPUTIMER1 Clock Enable bit + Uint16 CPUTIMER2:1; // 5 CPUTIMER2 Clock Enable bit + Uint16 rsvd2:10; // 15:6 Reserved + Uint16 HRPWM:1; // 16 HRPWM Clock Enable Bit + Uint16 rsvd3:1; // 17 Reserved + Uint16 TBCLKSYNC:1; // 18 EPWM Time Base Clock sync + Uint16 GTBCLKSYNC:1; // 19 EPWM Time Base Clock Global sync + Uint16 rsvd4:12; // 31:20 Reserved +}; + +union PCLKCR0_REG { + Uint32 all; + struct PCLKCR0_BITS bit; +}; + +struct PCLKCR1_BITS { // bits description + Uint16 EMIF1:1; // 0 EMIF1 Clock Enable bit + Uint16 EMIF2:1; // 1 EMIF2 Clock Enable bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union PCLKCR1_REG { + Uint32 all; + struct PCLKCR1_BITS bit; +}; + +struct PCLKCR2_BITS { // bits description + Uint16 EPWM1:1; // 0 EPWM1 Clock Enable bit + Uint16 EPWM2:1; // 1 EPWM2 Clock Enable bit + Uint16 EPWM3:1; // 2 EPWM3 Clock Enable bit + Uint16 EPWM4:1; // 3 EPWM4 Clock Enable bit + Uint16 EPWM5:1; // 4 EPWM5 Clock Enable bit + Uint16 EPWM6:1; // 5 EPWM6 Clock Enable bit + Uint16 EPWM7:1; // 6 EPWM7 Clock Enable bit + Uint16 EPWM8:1; // 7 EPWM8 Clock Enable bit + Uint16 EPWM9:1; // 8 EPWM9 Clock Enable bit + Uint16 EPWM10:1; // 9 EPWM10 Clock Enable bit + Uint16 EPWM11:1; // 10 EPWM11 Clock Enable bit + Uint16 EPWM12:1; // 11 EPWM12 Clock Enable bit + Uint16 rsvd1:1; // 12 Reserved + Uint16 rsvd2:1; // 13 Reserved + Uint16 rsvd3:1; // 14 Reserved + Uint16 rsvd4:1; // 15 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union PCLKCR2_REG { + Uint32 all; + struct PCLKCR2_BITS bit; +}; + +struct PCLKCR3_BITS { // bits description + Uint16 ECAP1:1; // 0 ECAP1 Clock Enable bit + Uint16 ECAP2:1; // 1 ECAP2 Clock Enable bit + Uint16 ECAP3:1; // 2 ECAP3 Clock Enable bit + Uint16 ECAP4:1; // 3 ECAP4 Clock Enable bit + Uint16 ECAP5:1; // 4 ECAP5 Clock Enable bit + Uint16 ECAP6:1; // 5 ECAP6 Clock Enable bit + Uint16 rsvd1:1; // 6 Reserved + Uint16 rsvd2:1; // 7 Reserved + Uint16 rsvd3:8; // 15:8 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union PCLKCR3_REG { + Uint32 all; + struct PCLKCR3_BITS bit; +}; + +struct PCLKCR4_BITS { // bits description + Uint16 EQEP1:1; // 0 EQEP1 Clock Enable bit + Uint16 EQEP2:1; // 1 EQEP2 Clock Enable bit + Uint16 EQEP3:1; // 2 EQEP3 Clock Enable bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union PCLKCR4_REG { + Uint32 all; + struct PCLKCR4_BITS bit; +}; + +struct PCLKCR6_BITS { // bits description + Uint16 SD1:1; // 0 SD1 Clock Enable bit + Uint16 SD2:1; // 1 SD2 Clock Enable bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:1; // 4 Reserved + Uint16 rsvd4:1; // 5 Reserved + Uint16 rsvd5:1; // 6 Reserved + Uint16 rsvd6:1; // 7 Reserved + Uint16 rsvd7:8; // 15:8 Reserved + Uint16 rsvd8:16; // 31:16 Reserved +}; + +union PCLKCR6_REG { + Uint32 all; + struct PCLKCR6_BITS bit; +}; + +struct PCLKCR7_BITS { // bits description + Uint16 SCI_A:1; // 0 SCI_A Clock Enable bit + Uint16 SCI_B:1; // 1 SCI_B Clock Enable bit + Uint16 SCI_C:1; // 2 SCI_C Clock Enable bit + Uint16 SCI_D:1; // 3 SCI_D Clock Enable bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union PCLKCR7_REG { + Uint32 all; + struct PCLKCR7_BITS bit; +}; + +struct PCLKCR8_BITS { // bits description + Uint16 SPI_A:1; // 0 SPI_A Clock Enable bit + Uint16 SPI_B:1; // 1 SPI_B Clock Enable bit + Uint16 SPI_C:1; // 2 SPI_C Clock Enable bit + Uint16 rsvd1:1; // 3 Reserved + Uint16 rsvd2:12; // 15:4 Reserved + Uint16 rsvd3:1; // 16 Reserved + Uint16 rsvd4:1; // 17 Reserved + Uint16 rsvd5:14; // 31:18 Reserved +}; + +union PCLKCR8_REG { + Uint32 all; + struct PCLKCR8_BITS bit; +}; + +struct PCLKCR9_BITS { // bits description + Uint16 I2C_A:1; // 0 I2C_A Clock Enable bit + Uint16 I2C_B:1; // 1 I2C_B Clock Enable bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:1; // 16 Reserved + Uint16 rsvd3:1; // 17 Reserved + Uint16 rsvd4:14; // 31:18 Reserved +}; + +union PCLKCR9_REG { + Uint32 all; + struct PCLKCR9_BITS bit; +}; + +struct PCLKCR10_BITS { // bits description + Uint16 CAN_A:1; // 0 CAN_A Clock Enable bit + Uint16 CAN_B:1; // 1 CAN_B Clock Enable bit + Uint16 rsvd1:1; // 2 Reserved + Uint16 rsvd2:1; // 3 Reserved + Uint16 rsvd3:12; // 15:4 Reserved + Uint16 rsvd4:16; // 31:16 Reserved +}; + +union PCLKCR10_REG { + Uint32 all; + struct PCLKCR10_BITS bit; +}; + +struct PCLKCR11_BITS { // bits description + Uint16 McBSP_A:1; // 0 McBSP_A Clock Enable bit + Uint16 McBSP_B:1; // 1 McBSP_B Clock Enable bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 USB_A:1; // 16 USB_A Clock Enable bit + Uint16 rsvd2:1; // 17 Reserved + Uint16 rsvd3:14; // 31:18 Reserved +}; + +union PCLKCR11_REG { + Uint32 all; + struct PCLKCR11_BITS bit; +}; + +struct PCLKCR12_BITS { // bits description + Uint16 uPP_A:1; // 0 uPP_A Clock Enable bit + Uint16 rsvd1:1; // 1 Reserved + Uint16 rsvd2:14; // 15:2 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union PCLKCR12_REG { + Uint32 all; + struct PCLKCR12_BITS bit; +}; + +struct PCLKCR13_BITS { // bits description + Uint16 ADC_A:1; // 0 ADC_A Clock Enable bit + Uint16 ADC_B:1; // 1 ADC_B Clock Enable bit + Uint16 ADC_C:1; // 2 ADC_C Clock Enable bit + Uint16 ADC_D:1; // 3 ADC_D Clock Enable bit + Uint16 rsvd1:12; // 15:4 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union PCLKCR13_REG { + Uint32 all; + struct PCLKCR13_BITS bit; +}; + +struct PCLKCR14_BITS { // bits description + Uint16 CMPSS1:1; // 0 CMPSS1 Clock Enable bit + Uint16 CMPSS2:1; // 1 CMPSS2 Clock Enable bit + Uint16 CMPSS3:1; // 2 CMPSS3 Clock Enable bit + Uint16 CMPSS4:1; // 3 CMPSS4 Clock Enable bit + Uint16 CMPSS5:1; // 4 CMPSS5 Clock Enable bit + Uint16 CMPSS6:1; // 5 CMPSS6 Clock Enable bit + Uint16 CMPSS7:1; // 6 CMPSS7 Clock Enable bit + Uint16 CMPSS8:1; // 7 CMPSS8 Clock Enable bit + Uint16 rsvd1:8; // 15:8 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union PCLKCR14_REG { + Uint32 all; + struct PCLKCR14_BITS bit; +}; + +struct PCLKCR16_BITS { // bits description + Uint16 rsvd1:1; // 0 Reserved + Uint16 rsvd2:1; // 1 Reserved + Uint16 rsvd3:1; // 2 Reserved + Uint16 rsvd4:1; // 3 Reserved + Uint16 rsvd5:12; // 15:4 Reserved + Uint16 DAC_A:1; // 16 Buffered_DAC_A Clock Enable Bit + Uint16 DAC_B:1; // 17 Buffered_DAC_B Clock Enable Bit + Uint16 DAC_C:1; // 18 Buffered_DAC_C Clock Enable Bit + Uint16 rsvd6:1; // 19 Reserved + Uint16 rsvd7:12; // 31:20 Reserved +}; + +union PCLKCR16_REG { + Uint32 all; + struct PCLKCR16_BITS bit; +}; + +struct SECMSEL_BITS { // bits description + Uint16 PF1SEL:2; // 1:0 Secondary Master Select for VBUS32_1 Bridge + Uint16 PF2SEL:2; // 3:2 Secondary Master Select for VBUS32_2 Bridge + Uint16 rsvd1:2; // 5:4 Reserved + Uint16 rsvd2:2; // 7:6 Reserved + Uint16 rsvd3:2; // 9:8 Reserved + Uint16 rsvd4:2; // 11:10 Reserved + Uint16 rsvd5:2; // 13:12 Reserved + Uint16 rsvd6:2; // 15:14 Reserved + Uint16 rsvd7:16; // 31:16 Reserved +}; + +union SECMSEL_REG { + Uint32 all; + struct SECMSEL_BITS bit; +}; + +struct LPMCR_BITS { // bits description + Uint16 LPM:2; // 1:0 Low Power Mode setting + Uint16 QUALSTDBY:6; // 7:2 STANDBY Wakeup Pin Qualification Setting + Uint16 rsvd1:7; // 14:8 Reserved + Uint16 WDINTE:1; // 15 Enable for WDINT wakeup from STANDBY + Uint16 M0M1MODE:2; // 17:16 Configuration for M0 and M1 mode during HIB + Uint16 rsvd2:13; // 30:18 Reserved + Uint16 IOISODIS:1; // 31 IO Isolation Disable +}; + +union LPMCR_REG { + Uint32 all; + struct LPMCR_BITS bit; +}; + +struct GPIOLPMSEL0_BITS { // bits description + Uint16 GPIO0:1; // 0 GPIO0 Enable for LPM Wakeup + Uint16 GPIO1:1; // 1 GPIO1 Enable for LPM Wakeup + Uint16 GPIO2:1; // 2 GPIO2 Enable for LPM Wakeup + Uint16 GPIO3:1; // 3 GPIO3 Enable for LPM Wakeup + Uint16 GPIO4:1; // 4 GPIO4 Enable for LPM Wakeup + Uint16 GPIO5:1; // 5 GPIO5 Enable for LPM Wakeup + Uint16 GPIO6:1; // 6 GPIO6 Enable for LPM Wakeup + Uint16 GPIO7:1; // 7 GPIO7 Enable for LPM Wakeup + Uint16 GPIO8:1; // 8 GPIO8 Enable for LPM Wakeup + Uint16 GPIO9:1; // 9 GPIO9 Enable for LPM Wakeup + Uint16 GPIO10:1; // 10 GPIO10 Enable for LPM Wakeup + Uint16 GPIO11:1; // 11 GPIO11 Enable for LPM Wakeup + Uint16 GPIO12:1; // 12 GPIO12 Enable for LPM Wakeup + Uint16 GPIO13:1; // 13 GPIO13 Enable for LPM Wakeup + Uint16 GPIO14:1; // 14 GPIO14 Enable for LPM Wakeup + Uint16 GPIO15:1; // 15 GPIO15 Enable for LPM Wakeup + Uint16 GPIO16:1; // 16 GPIO16 Enable for LPM Wakeup + Uint16 GPIO17:1; // 17 GPIO17 Enable for LPM Wakeup + Uint16 GPIO18:1; // 18 GPIO18 Enable for LPM Wakeup + Uint16 GPIO19:1; // 19 GPIO19 Enable for LPM Wakeup + Uint16 GPIO20:1; // 20 GPIO20 Enable for LPM Wakeup + Uint16 GPIO21:1; // 21 GPIO21 Enable for LPM Wakeup + Uint16 GPIO22:1; // 22 GPIO22 Enable for LPM Wakeup + Uint16 GPIO23:1; // 23 GPIO23 Enable for LPM Wakeup + Uint16 GPIO24:1; // 24 GPIO24 Enable for LPM Wakeup + Uint16 GPIO25:1; // 25 GPIO25 Enable for LPM Wakeup + Uint16 GPIO26:1; // 26 GPIO26 Enable for LPM Wakeup + Uint16 GPIO27:1; // 27 GPIO27 Enable for LPM Wakeup + Uint16 GPIO28:1; // 28 GPIO28 Enable for LPM Wakeup + Uint16 GPIO29:1; // 29 GPIO29 Enable for LPM Wakeup + Uint16 GPIO30:1; // 30 GPIO30 Enable for LPM Wakeup + Uint16 GPIO31:1; // 31 GPIO31 Enable for LPM Wakeup +}; + +union GPIOLPMSEL0_REG { + Uint32 all; + struct GPIOLPMSEL0_BITS bit; +}; + +struct GPIOLPMSEL1_BITS { // bits description + Uint16 GPIO32:1; // 0 GPIO32 Enable for LPM Wakeup + Uint16 GPIO33:1; // 1 GPIO33 Enable for LPM Wakeup + Uint16 GPIO34:1; // 2 GPIO34 Enable for LPM Wakeup + Uint16 GPIO35:1; // 3 GPIO35 Enable for LPM Wakeup + Uint16 GPIO36:1; // 4 GPIO36 Enable for LPM Wakeup + Uint16 GPIO37:1; // 5 GPIO37 Enable for LPM Wakeup + Uint16 GPIO38:1; // 6 GPIO38 Enable for LPM Wakeup + Uint16 GPIO39:1; // 7 GPIO39 Enable for LPM Wakeup + Uint16 GPIO40:1; // 8 GPIO40 Enable for LPM Wakeup + Uint16 GPIO41:1; // 9 GPIO41 Enable for LPM Wakeup + Uint16 GPIO42:1; // 10 GPIO42 Enable for LPM Wakeup + Uint16 GPIO43:1; // 11 GPIO43 Enable for LPM Wakeup + Uint16 GPIO44:1; // 12 GPIO44 Enable for LPM Wakeup + Uint16 GPIO45:1; // 13 GPIO45 Enable for LPM Wakeup + Uint16 GPIO46:1; // 14 GPIO46 Enable for LPM Wakeup + Uint16 GPIO47:1; // 15 GPIO47 Enable for LPM Wakeup + Uint16 GPIO48:1; // 16 GPIO48 Enable for LPM Wakeup + Uint16 GPIO49:1; // 17 GPIO49 Enable for LPM Wakeup + Uint16 GPIO50:1; // 18 GPIO50 Enable for LPM Wakeup + Uint16 GPIO51:1; // 19 GPIO51 Enable for LPM Wakeup + Uint16 GPIO52:1; // 20 GPIO52 Enable for LPM Wakeup + Uint16 GPIO53:1; // 21 GPIO53 Enable for LPM Wakeup + Uint16 GPIO54:1; // 22 GPIO54 Enable for LPM Wakeup + Uint16 GPIO55:1; // 23 GPIO55 Enable for LPM Wakeup + Uint16 GPIO56:1; // 24 GPIO56 Enable for LPM Wakeup + Uint16 GPIO57:1; // 25 GPIO57 Enable for LPM Wakeup + Uint16 GPIO58:1; // 26 GPIO58 Enable for LPM Wakeup + Uint16 GPIO59:1; // 27 GPIO59 Enable for LPM Wakeup + Uint16 GPIO60:1; // 28 GPIO60 Enable for LPM Wakeup + Uint16 GPIO61:1; // 29 GPIO61 Enable for LPM Wakeup + Uint16 GPIO62:1; // 30 GPIO62 Enable for LPM Wakeup + Uint16 GPIO63:1; // 31 GPIO63 Enable for LPM Wakeup +}; + +union GPIOLPMSEL1_REG { + Uint32 all; + struct GPIOLPMSEL1_BITS bit; +}; + +struct TMR2CLKCTL_BITS { // bits description + Uint16 TMR2CLKSRCSEL:3; // 2:0 CPU Timer 2 Clock Source Select Bit + Uint16 TMR2CLKPRESCALE:3; // 5:3 CPU Timer 2 Clock Pre-Scale Value + Uint16 rsvd1:10; // 15:6 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union TMR2CLKCTL_REG { + Uint32 all; + struct TMR2CLKCTL_BITS bit; +}; + +struct RESC_BITS { // bits description + Uint16 POR:1; // 0 POR Reset Cause Indication Bit + Uint16 XRSn:1; // 1 XRSn Reset Cause Indication Bit + Uint16 WDRSn:1; // 2 WDRSn Reset Cause Indication Bit + Uint16 NMIWDRSn:1; // 3 NMIWDRSn Reset Cause Indication Bit + Uint16 rsvd1:1; // 4 Reserved + Uint16 HWBISTn:1; // 5 HWBISTn Reset Cause Indication Bit + Uint16 HIBRESETn:1; // 6 HIBRESETn Reset Cause Indication Bit + Uint16 rsvd2:1; // 7 Reserved + Uint16 SCCRESETn:1; // 8 SCCRESETn Reset Cause Indication Bit + Uint16 rsvd3:7; // 15:9 Reserved + Uint16 rsvd4:14; // 29:16 Reserved + Uint16 XRSn_pin_status:1; // 30 XRSN Pin Status + Uint16 TRSTn_pin_status:1; // 31 TRSTn Status +}; + +union RESC_REG { + Uint32 all; + struct RESC_BITS bit; +}; + +struct CPU_SYS_REGS { + union CPUSYSLOCK1_REG CPUSYSLOCK1; // Lock bit for CPUSYS registers + Uint16 rsvd1[4]; // Reserved + Uint32 HIBBOOTMODE; // HIB Boot Mode Register + union IORESTOREADDR_REG IORESTOREADDR; // IORestore() routine Address Register + union PIEVERRADDR_REG PIEVERRADDR; // PIE Vector Fetch Error Address register + Uint16 rsvd2[22]; // Reserved + union PCLKCR0_REG PCLKCR0; // Peripheral Clock Gating Registers + union PCLKCR1_REG PCLKCR1; // Peripheral Clock Gating Registers + union PCLKCR2_REG PCLKCR2; // Peripheral Clock Gating Registers + union PCLKCR3_REG PCLKCR3; // Peripheral Clock Gating Registers + union PCLKCR4_REG PCLKCR4; // Peripheral Clock Gating Registers + Uint16 rsvd3[2]; // Reserved + union PCLKCR6_REG PCLKCR6; // Peripheral Clock Gating Registers + union PCLKCR7_REG PCLKCR7; // Peripheral Clock Gating Registers + union PCLKCR8_REG PCLKCR8; // Peripheral Clock Gating Registers + union PCLKCR9_REG PCLKCR9; // Peripheral Clock Gating Registers + union PCLKCR10_REG PCLKCR10; // Peripheral Clock Gating Registers + union PCLKCR11_REG PCLKCR11; // Peripheral Clock Gating Registers + union PCLKCR12_REG PCLKCR12; // Peripheral Clock Gating Registers + union PCLKCR13_REG PCLKCR13; // Peripheral Clock Gating Registers + union PCLKCR14_REG PCLKCR14; // Peripheral Clock Gating Registers + Uint16 rsvd4[2]; // Reserved + union PCLKCR16_REG PCLKCR16; // Peripheral Clock Gating Registers + Uint16 rsvd5[48]; // Reserved + union SECMSEL_REG SECMSEL; // Secondary Master Select register for common peripherals: Selects between CLA & DMA + union LPMCR_REG LPMCR; // LPM Control Register + union GPIOLPMSEL0_REG GPIOLPMSEL0; // GPIO LPM Wakeup select registers + union GPIOLPMSEL1_REG GPIOLPMSEL1; // GPIO LPM Wakeup select registers + union TMR2CLKCTL_REG TMR2CLKCTL; // Timer2 Clock Measurement functionality control register + Uint16 rsvd6[2]; // Reserved + union RESC_REG RESC; // Reset Cause register +}; + +struct SCSR_BITS { // bits description + Uint16 WDOVERRIDE:1; // 0 WD Override for WDDIS bit + Uint16 WDENINT:1; // 1 WD Interrupt Enable + Uint16 WDINTS:1; // 2 WD Interrupt Status + Uint16 rsvd1:13; // 15:3 Reserved +}; + +union SCSR_REG { + Uint16 all; + struct SCSR_BITS bit; +}; + +struct WDCNTR_BITS { // bits description + Uint16 WDCNTR:8; // 7:0 WD Counter + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union WDCNTR_REG { + Uint16 all; + struct WDCNTR_BITS bit; +}; + +struct WDKEY_BITS { // bits description + Uint16 WDKEY:8; // 7:0 WD KEY + Uint16 rsvd1:8; // 15:8 Reserved +}; + +union WDKEY_REG { + Uint16 all; + struct WDKEY_BITS bit; +}; + +struct WDCR_BITS { // bits description + Uint16 WDPS:3; // 2:0 WD Clock Prescalar + Uint16 WDCHK:3; // 5:3 WD Check Bits + Uint16 WDDIS:1; // 6 WD Disable + Uint16 rsvd1:1; // 7 Reserved + Uint16 rsvd2:8; // 15:8 Reserved +}; + +union WDCR_REG { + Uint16 all; + struct WDCR_BITS bit; +}; + +struct WDWCR_BITS { // bits description + Uint16 MIN:8; // 7:0 WD Min Threshold setting for Windowed Watchdog functionality + Uint16 FIRSTKEY:1; // 8 First Key Detect Flag + Uint16 rsvd1:7; // 15:9 Reserved +}; + +union WDWCR_REG { + Uint16 all; + struct WDWCR_BITS bit; +}; + +struct WD_REGS { + Uint16 rsvd1[34]; // Reserved + union SCSR_REG SCSR; // System Control & Status Register + union WDCNTR_REG WDCNTR; // Watchdog Counter Register + Uint16 rsvd2; // Reserved + union WDKEY_REG WDKEY; // Watchdog Reset Key Register + Uint16 rsvd3[3]; // Reserved + union WDCR_REG WDCR; // Watchdog Control Register + union WDWCR_REG WDWCR; // Watchdog Windowed Control Register +}; + +struct CLA1TASKSRCSELLOCK_BITS { // bits description + Uint16 CLA1TASKSRCSEL1:1; // 0 CLA1TASKSRCSEL1 Register Lock bit + Uint16 CLA1TASKSRCSEL2:1; // 1 CLA1TASKSRCSEL2 Register Lock bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union CLA1TASKSRCSELLOCK_REG { + Uint32 all; + struct CLA1TASKSRCSELLOCK_BITS bit; +}; + +struct DMACHSRCSELLOCK_BITS { // bits description + Uint16 DMACHSRCSEL1:1; // 0 DMACHSRCSEL1 Register Lock bit + Uint16 DMACHSRCSEL2:1; // 1 DMACHSRCSEL2 Register Lock bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DMACHSRCSELLOCK_REG { + Uint32 all; + struct DMACHSRCSELLOCK_BITS bit; +}; + +struct CLA1TASKSRCSEL1_BITS { // bits description + Uint16 TASK1:8; // 7:0 Selects the Trigger Source for TASK1 of CLA1 + Uint16 TASK2:8; // 15:8 Selects the Trigger Source for TASK2 of CLA1 + Uint16 TASK3:8; // 23:16 Selects the Trigger Source for TASK3 of CLA1 + Uint16 TASK4:8; // 31:24 Selects the Trigger Source for TASK4 of CLA1 +}; + +union CLA1TASKSRCSEL1_REG { + Uint32 all; + struct CLA1TASKSRCSEL1_BITS bit; +}; + +struct CLA1TASKSRCSEL2_BITS { // bits description + Uint16 TASK5:8; // 7:0 Selects the Trigger Source for TASK5 of CLA1 + Uint16 TASK6:8; // 15:8 Selects the Trigger Source for TASK6 of CLA1 + Uint16 TASK7:8; // 23:16 Selects the Trigger Source for TASK7 of CLA1 + Uint16 TASK8:8; // 31:24 Selects the Trigger Source for TASK8 of CLA1 +}; + +union CLA1TASKSRCSEL2_REG { + Uint32 all; + struct CLA1TASKSRCSEL2_BITS bit; +}; + +struct DMACHSRCSEL1_BITS { // bits description + Uint16 CH1:8; // 7:0 Selects the Trigger and Sync Source CH1 of DMA + Uint16 CH2:8; // 15:8 Selects the Trigger and Sync Source CH2 of DMA + Uint16 CH3:8; // 23:16 Selects the Trigger and Sync Source CH3 of DMA + Uint16 CH4:8; // 31:24 Selects the Trigger and Sync Source CH4 of DMA +}; + +union DMACHSRCSEL1_REG { + Uint32 all; + struct DMACHSRCSEL1_BITS bit; +}; + +struct DMACHSRCSEL2_BITS { // bits description + Uint16 CH5:8; // 7:0 Selects the Trigger and Sync Source CH5 of DMA + Uint16 CH6:8; // 15:8 Selects the Trigger and Sync Source CH6 of DMA + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union DMACHSRCSEL2_REG { + Uint32 all; + struct DMACHSRCSEL2_BITS bit; +}; + +struct DMA_CLA_SRC_SEL_REGS { + union CLA1TASKSRCSELLOCK_REG CLA1TASKSRCSELLOCK; // CLA1 Task Trigger Source Select Lock Register + Uint16 rsvd1[2]; // Reserved + union DMACHSRCSELLOCK_REG DMACHSRCSELLOCK; // DMA Channel Triger Source Select Lock Register + union CLA1TASKSRCSEL1_REG CLA1TASKSRCSEL1; // CLA1 Task Trigger Source Select Register-1 + union CLA1TASKSRCSEL2_REG CLA1TASKSRCSEL2; // CLA1 Task Trigger Source Select Register-2 + Uint16 rsvd2[12]; // Reserved + union DMACHSRCSEL1_REG DMACHSRCSEL1; // DMA Channel Trigger Source Select Register-1 + union DMACHSRCSEL2_REG DMACHSRCSEL2; // DMA Channel Trigger Source Select Register-2 +}; + +struct SYNCSELECT_BITS { // bits description + Uint16 EPWM4SYNCIN:3; // 2:0 Selects Sync Input Source for EPWM4 + Uint16 EPWM7SYNCIN:3; // 5:3 Selects Sync Input Source for EPWM7 + Uint16 EPWM10SYNCIN:3; // 8:6 Selects Sync Input Source for EPWM10 + Uint16 ECAP1SYNCIN:3; // 11:9 Selects Sync Input Source for ECAP1 + Uint16 ECAP4SYNCIN:3; // 14:12 Selects Sync Input Source for ECAP4 + Uint16 rsvd1:1; // 15 Reserved + Uint16 rsvd2:11; // 26:16 Reserved + Uint16 SYNCOUT:2; // 28:27 Select Syncout Source + Uint16 rsvd3:3; // 31:29 Reserved +}; + +union SYNCSELECT_REG { + Uint32 all; + struct SYNCSELECT_BITS bit; +}; + +struct ADCSOCOUTSELECT_BITS { // bits description + Uint16 PWM1SOCAEN:1; // 0 PWM1SOCAEN Enable for ADCSOCAO + Uint16 PWM2SOCAEN:1; // 1 PWM2SOCAEN Enable for ADCSOCAO + Uint16 PWM3SOCAEN:1; // 2 PWM3SOCAEN Enable for ADCSOCAO + Uint16 PWM4SOCAEN:1; // 3 PWM4SOCAEN Enable for ADCSOCAO + Uint16 PWM5SOCAEN:1; // 4 PWM5SOCAEN Enable for ADCSOCAO + Uint16 PWM6SOCAEN:1; // 5 PWM6SOCAEN Enable for ADCSOCAO + Uint16 PWM7SOCAEN:1; // 6 PWM7SOCAEN Enable for ADCSOCAO + Uint16 PWM8SOCAEN:1; // 7 PWM8SOCAEN Enable for ADCSOCAO + Uint16 PWM9SOCAEN:1; // 8 PWM9SOCAEN Enable for ADCSOCAO + Uint16 PWM10SOCAEN:1; // 9 PWM10SOCAEN Enable for ADCSOCAO + Uint16 PWM11SOCAEN:1; // 10 PWM11SOCAEN Enable for ADCSOCAO + Uint16 PWM12SOCAEN:1; // 11 PWM12SOCAEN Enable for ADCSOCAO + Uint16 rsvd1:4; // 15:12 Reserved + Uint16 PWM1SOCBEN:1; // 16 PWM1SOCBEN Enable for ADCSOCBO + Uint16 PWM2SOCBEN:1; // 17 PWM2SOCBEN Enable for ADCSOCBO + Uint16 PWM3SOCBEN:1; // 18 PWM3SOCBEN Enable for ADCSOCBO + Uint16 PWM4SOCBEN:1; // 19 PWM4SOCBEN Enable for ADCSOCBO + Uint16 PWM5SOCBEN:1; // 20 PWM5SOCBEN Enable for ADCSOCBO + Uint16 PWM6SOCBEN:1; // 21 PWM6SOCBEN Enable for ADCSOCBO + Uint16 PWM7SOCBEN:1; // 22 PWM7SOCBEN Enable for ADCSOCBO + Uint16 PWM8SOCBEN:1; // 23 PWM8SOCBEN Enable for ADCSOCBO + Uint16 PWM9SOCBEN:1; // 24 PWM9SOCBEN Enable for ADCSOCBO + Uint16 PWM10SOCBEN:1; // 25 PWM10SOCBEN Enable for ADCSOCBO + Uint16 PWM11SOCBEN:1; // 26 PWM11SOCBEN Enable for ADCSOCBO + Uint16 PWM12SOCBEN:1; // 27 PWM12SOCBEN Enable for ADCSOCBO + Uint16 rsvd2:4; // 31:28 Reserved +}; + +union ADCSOCOUTSELECT_REG { + Uint32 all; + struct ADCSOCOUTSELECT_BITS bit; +}; + +struct SYNCSOCLOCK_BITS { // bits description + Uint16 SYNCSELECT:1; // 0 SYNCSEL Register Lock bit + Uint16 ADCSOCOUTSELECT:1; // 1 ADCSOCOUTSELECT Register Lock bit + Uint16 rsvd1:14; // 15:2 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union SYNCSOCLOCK_REG { + Uint32 all; + struct SYNCSOCLOCK_BITS bit; +}; + +struct SYNC_SOC_REGS { + union SYNCSELECT_REG SYNCSELECT; // Sync Input and Output Select Register + union ADCSOCOUTSELECT_REG ADCSOCOUTSELECT; // External ADC (Off Chip) SOC Select Register + union SYNCSOCLOCK_REG SYNCSOCLOCK; // SYNCSEL and EXTADCSOC Select Lock register +}; + +//--------------------------------------------------------------------------- +// SYSCTRL External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct WD_REGS WdRegs; +extern volatile struct SYNC_SOC_REGS SyncSocRegs; +extern volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; +extern volatile struct DEV_CFG_REGS DevCfgRegs; +extern volatile struct CLK_CFG_REGS ClkCfgRegs; +extern volatile struct CPU_SYS_REGS CpuSysRegs; +#endif +#ifdef CPU2 +extern volatile struct WD_REGS WdRegs; +extern volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; +extern volatile struct CLK_CFG_REGS ClkCfgRegs; +extern volatile struct CPU_SYS_REGS CpuSysRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_upp.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_upp.h new file mode 100644 index 0000000000..c33bcc90f2 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_upp.h @@ -0,0 +1,403 @@ +//########################################################################### +// +// FILE: F2837xD_upp.h +// +// TITLE: UPP Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_UPP_H__ +#define __F2837xD_UPP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// UPP Individual Register Bit Definitions: + +struct PERCTL_BITS { // bits description + Uint16 FREE:1; // 0 Emulation control. + Uint16 SOFT:1; // 1 Emulation control. + Uint16 RTEMU:1; // 2 Realtime emulation control. + Uint16 PEREN:1; // 3 Peripheral Enable + Uint16 SOFTRST:1; // 4 Software Reset + Uint16 rsvd1:2; // 6:5 Reserved + Uint16 DMAST:1; // 7 DMA Burst transaction status + Uint16 rsvd2:8; // 15:8 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union PERCTL_REG { + Uint32 all; + struct PERCTL_BITS bit; +}; + +struct CHCTL_BITS { // bits description + Uint16 MODE:2; // 1:0 Operating mode + Uint16 rsvd1:1; // 2 Reserved + Uint16 SDRTXILA:1; // 3 SDR TX Interleve mode + Uint16 DEMUXA:1; // 4 DDR de-multiplexing mode + Uint16 rsvd2:11; // 15:5 Reserved + Uint16 DRA:1; // 16 Data rate + Uint16 rsvd3:14; // 30:17 Reserved + Uint16 rsvd4:1; // 31 Reserved +}; + +union CHCTL_REG { + Uint32 all; + struct CHCTL_BITS bit; +}; + +struct IFCFG_BITS { // bits description + Uint16 STARTPOLA:1; // 0 Polarity of START(SELECT) signal + Uint16 ENAPOLA:1; // 1 Polarity of ENABLE(WRITE) signal + Uint16 WAITPOLA:1; // 2 Polarity of WAIT signal. + Uint16 STARTA:1; // 3 Enable Usage of START (SELECT) signal + Uint16 ENAA:1; // 4 Enable Usage of ENABLE (WRITE) signal + Uint16 WAITA:1; // 5 Enable Usage of WAIT signal + Uint16 rsvd1:2; // 7:6 Reserved + Uint16 CLKDIVA:4; // 11:8 Clock divider for tx mode + Uint16 CLKINVA:1; // 12 Clock inversion + Uint16 TRISENA:1; // 13 Pin Tri-state Control + Uint16 rsvd2:2; // 15:14 Reserved + Uint16 rsvd3:6; // 21:16 Reserved + Uint16 rsvd4:2; // 23:22 Reserved + Uint16 rsvd5:6; // 29:24 Reserved + Uint16 rsvd6:2; // 31:30 Reserved +}; + +union IFCFG_REG { + Uint32 all; + struct IFCFG_BITS bit; +}; + +struct IFIVAL_BITS { // bits description + Uint16 VALA:9; // 8:0 Idle Value + Uint16 rsvd1:7; // 15:9 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union IFIVAL_REG { + Uint32 all; + struct IFIVAL_BITS bit; +}; + +struct THCFG_BITS { // bits description + Uint16 RDSIZEI:2; // 1:0 DMA Read Threshold for DMA Channel I + Uint16 rsvd1:6; // 7:2 Reserved + Uint16 RDSIZEQ:2; // 9:8 DMA Read Threshold for DMA Channel Q + Uint16 rsvd2:6; // 15:10 Reserved + Uint16 TXSIZEA:2; // 17:16 I/O Transmit Threshold Value + Uint16 rsvd3:6; // 23:18 Reserved + Uint16 rsvd4:2; // 25:24 Reserved + Uint16 rsvd5:6; // 31:26 Reserved +}; + +union THCFG_REG { + Uint32 all; + struct THCFG_BITS bit; +}; + +struct RAWINTST_BITS { // bits description + Uint16 DPEI:1; // 0 Interrupt raw status for DMA programming error + Uint16 UOEI:1; // 1 Interrupt raw status for DMA under-run or over-run + Uint16 rsvd1:1; // 2 Reserved + Uint16 EOWI:1; // 3 Interrupt raw status for end-of window condition + Uint16 EOLI:1; // 4 Interrupt raw status for end-of-line condition + Uint16 rsvd2:3; // 7:5 Reserved + Uint16 DPEQ:1; // 8 Interrupt raw status for DMA programming error + Uint16 UOEQ:1; // 9 Interrupt raw status for DMA under-run or over-run + Uint16 rsvd3:1; // 10 Reserved + Uint16 EOWQ:1; // 11 Interrupt raw status for end-of window condition + Uint16 EOLQ:1; // 12 Interrupt raw status for end-of-line condition + Uint16 rsvd4:3; // 15:13 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union RAWINTST_REG { + Uint32 all; + struct RAWINTST_BITS bit; +}; + +struct ENINTST_BITS { // bits description + Uint16 DPEI:1; // 0 Interrupt enable status for DMA programming error + Uint16 UOEI:1; // 1 Interrupt enable status for DMA under-run or over-run + Uint16 rsvd1:1; // 2 Reserved + Uint16 EOWI:1; // 3 Interrupt enable status for end-of window condition + Uint16 EOLI:1; // 4 Interrupt enable status for end-of-line condition + Uint16 rsvd2:3; // 7:5 Reserved + Uint16 DPEQ:1; // 8 Interrupt enable status for DMA programming error + Uint16 UOEQ:1; // 9 Interrupt enable status for DMA under-run or over-run + Uint16 rsvd3:1; // 10 Reserved + Uint16 EOWQ:1; // 11 Interrupt enable status for end-of window condition + Uint16 EOLQ:1; // 12 Interrupt enable status for end-of-line condition + Uint16 rsvd4:3; // 15:13 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union ENINTST_REG { + Uint32 all; + struct ENINTST_BITS bit; +}; + +struct INTENSET_BITS { // bits description + Uint16 DPEI:1; // 0 Interrupt enable for DMA programming error + Uint16 UOEI:1; // 1 Interrupt enable for DMA under-run or over-run + Uint16 rsvd1:1; // 2 Reserved + Uint16 EOWI:1; // 3 Interrupt enable for end-of window condition + Uint16 EOLI:1; // 4 Interrupt enable for end-of-line condition + Uint16 rsvd2:3; // 7:5 Reserved + Uint16 DPEQ:1; // 8 Interrupt enable for DMA programming error + Uint16 UOEQ:1; // 9 Interrupt enable for DMA under-run or over-run + Uint16 rsvd3:1; // 10 Reserved + Uint16 EOWQ:1; // 11 Interrupt enable for end-of window condition + Uint16 EOLQ:1; // 12 Interrupt enable for end-of-line condition + Uint16 rsvd4:3; // 15:13 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union INTENSET_REG { + Uint32 all; + struct INTENSET_BITS bit; +}; + +struct INTENCLR_BITS { // bits description + Uint16 DPEI:1; // 0 Interrupt clear for DMA programming error + Uint16 UOEI:1; // 1 Interrupt clear for DMA under-run or over-run + Uint16 rsvd1:1; // 2 Reserved + Uint16 EOWI:1; // 3 Interrupt clear for end-of window condition + Uint16 EOLI:1; // 4 Interrupt clear for end-of-line condition + Uint16 rsvd2:3; // 7:5 Reserved + Uint16 DPEQ:1; // 8 Interrupt clear for DMA programming error + Uint16 UOEQ:1; // 9 Interrupt clear for DMA under-run or over-run + Uint16 rsvd3:1; // 10 Reserved + Uint16 EOWQ:1; // 11 Interrupt clear for end-of window condition + Uint16 EOLQ:1; // 12 Interrupt clear for end-of-line condition + Uint16 rsvd4:3; // 15:13 Reserved + Uint16 rsvd5:16; // 31:16 Reserved +}; + +union INTENCLR_REG { + Uint32 all; + struct INTENCLR_BITS bit; +}; + +struct CHIDESC1_BITS { // bits description + Uint16 BCNT:16; // 15:0 Number of bytes in a line for DMA Channel I transfer. + Uint16 LCNT:16; // 31:16 Number of lines in a window for DMA Channel I transfer. +}; + +union CHIDESC1_REG { + Uint32 all; + struct CHIDESC1_BITS bit; +}; + +struct CHIDESC2_BITS { // bits description + Uint16 LOFFSET:16; // 15:0 Current start address to next start address offset. + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union CHIDESC2_REG { + Uint32 all; + struct CHIDESC2_BITS bit; +}; + +struct CHIST1_BITS { // bits description + Uint16 BCNT:16; // 15:0 Current byte number. + Uint16 LCNT:16; // 31:16 Current line number. +}; + +union CHIST1_REG { + Uint32 all; + struct CHIST1_BITS bit; +}; + +struct CHIST2_BITS { // bits description + Uint16 ACT:1; // 0 Status of DMA descriptor. + Uint16 PEND:1; // 1 Status of DMA. + Uint16 rsvd1:2; // 3:2 Reserved + Uint16 WM:4; // 7:4 Watermark for FIFO block count for DMA Channel I tranfer. + Uint16 rsvd2:8; // 15:8 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CHIST2_REG { + Uint32 all; + struct CHIST2_BITS bit; +}; + +struct CHQDESC1_BITS { // bits description + Uint16 BCNT:16; // 15:0 Number of bytes in a line for DMA Channel Q transfer. + Uint16 LCNT:16; // 31:16 Number of lines in a window for DMA Channel Q transfer. +}; + +union CHQDESC1_REG { + Uint32 all; + struct CHQDESC1_BITS bit; +}; + +struct CHQDESC2_BITS { // bits description + Uint16 LOFFSET:16; // 15:0 Current start address to next start address offset. + Uint16 rsvd1:16; // 31:16 Reserved +}; + +union CHQDESC2_REG { + Uint32 all; + struct CHQDESC2_BITS bit; +}; + +struct CHQST1_BITS { // bits description + Uint16 BCNT:16; // 15:0 Current byte number. + Uint16 LCNT:16; // 31:16 Current line number. +}; + +union CHQST1_REG { + Uint32 all; + struct CHQST1_BITS bit; +}; + +struct CHQST2_BITS { // bits description + Uint16 ACT:1; // 0 Status of DMA descriptor. + Uint16 PEND:1; // 1 Status of DMA. + Uint16 rsvd1:2; // 3:2 Reserved + Uint16 WM:4; // 7:4 Watermark for FIFO block count for DMA Channel Q tranfer. + Uint16 rsvd2:8; // 15:8 Reserved + Uint16 rsvd3:16; // 31:16 Reserved +}; + +union CHQST2_REG { + Uint32 all; + struct CHQST2_BITS bit; +}; + +struct GINTEN_BITS { // bits description + Uint16 GINTEN:1; // 0 Global Interrupt Enable + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union GINTEN_REG { + Uint32 all; + struct GINTEN_BITS bit; +}; + +struct GINTFLG_BITS { // bits description + Uint16 GINTFLG:1; // 0 Global Interrupt Flag + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union GINTFLG_REG { + Uint32 all; + struct GINTFLG_BITS bit; +}; + +struct GINTCLR_BITS { // bits description + Uint16 GINTCLR:1; // 0 Global Interrupt Clear + Uint16 rsvd1:15; // 15:1 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union GINTCLR_REG { + Uint32 all; + struct GINTCLR_BITS bit; +}; + +struct DLYCTL_BITS { // bits description + Uint16 DLYDIS:1; // 0 IO dealy control disable. + Uint16 DLYCTL:2; // 2:1 IO delay control. + Uint16 rsvd1:13; // 15:3 Reserved + Uint16 rsvd2:16; // 31:16 Reserved +}; + +union DLYCTL_REG { + Uint32 all; + struct DLYCTL_BITS bit; +}; + +struct UPP_REGS { + Uint32 PID; // Peripheral ID Register + union PERCTL_REG PERCTL; // Peripheral Control Register + Uint16 rsvd1[4]; // Reserved + union CHCTL_REG CHCTL; // General Control Register + union IFCFG_REG IFCFG; // Interface Configuration Register + union IFIVAL_REG IFIVAL; // Interface Idle Value Register + union THCFG_REG THCFG; // Threshold Configuration Register + union RAWINTST_REG RAWINTST; // Raw Interrupt Status Register + union ENINTST_REG ENINTST; // Enable Interrupt Status Register + union INTENSET_REG INTENSET; // Interrupt Enable Set Register + union INTENCLR_REG INTENCLR; // Interrupt Enable Clear Register + Uint16 rsvd2[8]; // Reserved + Uint32 CHIDESC0; // DMA Channel I Descriptor 0 Register + union CHIDESC1_REG CHIDESC1; // DMA Channel I Descriptor 1 Register + union CHIDESC2_REG CHIDESC2; // DMA Channel I Descriptor 2 Register + Uint16 rsvd3[2]; // Reserved + Uint32 CHIST0; // DMA Channel I Status 0 Register + union CHIST1_REG CHIST1; // DMA Channel I Status 1 Register + union CHIST2_REG CHIST2; // DMA Channel I Status 2 Register + Uint16 rsvd4[2]; // Reserved + Uint32 CHQDESC0; // DMA Channel Q Descriptor 0 Register + union CHQDESC1_REG CHQDESC1; // DMA Channel Q Descriptor 1 Register + union CHQDESC2_REG CHQDESC2; // DMA Channel Q Descriptor 2 Register + Uint16 rsvd5[2]; // Reserved + Uint32 CHQST0; // DMA Channel Q Status 0 Register + union CHQST1_REG CHQST1; // DMA Channel Q Status 1 Register + union CHQST2_REG CHQST2; // DMA Channel Q Status 2 Register + Uint16 rsvd6[2]; // Reserved + union GINTEN_REG GINTEN; // Global Peripheral Interrupt Enable Register + union GINTFLG_REG GINTFLG; // Global Peripheral Interrupt Flag Register + union GINTCLR_REG GINTCLR; // Global Peripheral Interrupt Clear Register + union DLYCTL_REG DLYCTL; // IO clock data skew control Register +}; + +//--------------------------------------------------------------------------- +// UPP External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct UPP_REGS UppRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_xbar.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_xbar.h new file mode 100644 index 0000000000..d201fda67c --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_xbar.h @@ -0,0 +1,303 @@ +//########################################################################### +// +// FILE: F2837xD_xbar.h +// +// TITLE: XBAR Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_XBAR_H__ +#define __F2837xD_XBAR_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// XBAR Individual Register Bit Definitions: + +struct XBARFLG1_BITS { // bits description + Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag for CMPSS1.CTRIPL Signal + Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag for CMPSS1.CTRIPH Signal + Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag for CMPSS2.CTRIPL Signal + Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag for CMPSS2.CTRIPH Signal + Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag for CMPSS3.CTRIPL Signal + Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag for CMPSS3.CTRIPH Signal + Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag for CMPSS4.CTRIPL Signal + Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag for CMPSS4.CTRIPH Signal + Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag for CMPSS5.CTRIPL Signal + Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag for CMPSS5.CTRIPH Signal + Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag for CMPSS6.CTRIPL Signal + Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag for CMPSS6.CTRIPH Signal + Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag for CMPSS7.CTRIPL Signal + Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag for CMPSS7.CTRIPH Signal + Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag for CMPSS8.CTRIPL Signal + Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag for CMPSS8.CTRIPH Signal + Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag for CMPSS1.CTRIPOUTL Signal + Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag for CMPSS1.CTRIPOUTH Signal + Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag for CMPSS2.CTRIPOUTL Signal + Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag for CMPSS2.CTRIPOUTH Signal + Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag for CMPSS3.CTRIPOUTL Signal + Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag for CMPSS3.CTRIPOUTH Signal + Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag for CMPSS4.CTRIPOUTL Signal + Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag for CMPSS4.CTRIPOUTH Signal + Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag for CMPSS5.CTRIPOUTL Signal + Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag for CMPSS5.CTRIPOUTH Signal + Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag for CMPSS6.CTRIPOUTL Signal + Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag for CMPSS6.CTRIPOUTH Signal + Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag for CMPSS7.CTRIPOUTL Signal + Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag for CMPSS7.CTRIPOUTH Signal + Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag for CMPSS8.CTRIPOUTL Signal + Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag for CMPSS8.CTRIPOUTH Signal +}; + +union XBARFLG1_REG { + Uint32 all; + struct XBARFLG1_BITS bit; +}; + +struct XBARFLG2_BITS { // bits description + Uint16 INPUT1:1; // 0 Input Flag for INPUT1 Signal + Uint16 INPUT2:1; // 1 Input Flag for INPUT2 Signal + Uint16 INPUT3:1; // 2 Input Flag for INPUT3 Signal + Uint16 INPUT4:1; // 3 Input Flag for INPUT4 Signal + Uint16 INPUT5:1; // 4 Input Flag for INPUT5 Signal + Uint16 INPUT6:1; // 5 Input Flag for INPUT6 Signal + Uint16 ADCSOCAO:1; // 6 Input Flag for ADCSOCAO Signal + Uint16 ADCSOCBO:1; // 7 Input Flag for ADCSOCBO Signal + Uint16 rsvd1:1; // 8 Reserved + Uint16 rsvd2:1; // 9 Reserved + Uint16 rsvd3:1; // 10 Reserved + Uint16 rsvd4:1; // 11 Reserved + Uint16 rsvd5:1; // 12 Reserved + Uint16 rsvd6:1; // 13 Reserved + Uint16 rsvd7:1; // 14 Reserved + Uint16 rsvd8:1; // 15 Reserved + Uint16 ECAP1_OUT:1; // 16 Input Flag for ECAP1.OUT Signal + Uint16 ECAP2_OUT:1; // 17 Input Flag for ECAP2.OUT Signal + Uint16 ECAP3_OUT:1; // 18 Input Flag for ECAP3.OUT Signal + Uint16 ECAP4_OUT:1; // 19 Input Flag for ECAP4.OUT Signal + Uint16 ECAP5_OUT:1; // 20 Input Flag for ECAP5.OUT Signal + Uint16 ECAP6_OUT:1; // 21 Input Flag for ECAP6.OUT Signal + Uint16 EXTSYNCOUT:1; // 22 Input Flag for EXTSYNCOUT Signal + Uint16 ADCAEVT1:1; // 23 Input Flag for ADCAEVT1 Signal + Uint16 ADCAEVT2:1; // 24 Input Flag for ADCAEVT2 Signal + Uint16 ADCAEVT3:1; // 25 Input Flag for ADCAEVT3 Signal + Uint16 ADCAEVT4:1; // 26 Input Flag for ADCAEVT4 Signal + Uint16 ADCBEVT1:1; // 27 Input Flag for ADCBEVT1 Signal + Uint16 ADCBEVT2:1; // 28 Input Flag for ADCBEVT2 Signal + Uint16 ADCBEVT3:1; // 29 Input Flag for ADCBEVT3 Signal + Uint16 ADCBEVT4:1; // 30 Input Flag for ADCBEVT4 Signal + Uint16 ADCCEVT1:1; // 31 Input Flag for ADCCEVT1 Signal +}; + +union XBARFLG2_REG { + Uint32 all; + struct XBARFLG2_BITS bit; +}; + +struct XBARFLG3_BITS { // bits description + Uint16 ADCCEVT2:1; // 0 Input Flag for ADCCEVT2 Signal + Uint16 ADCCEVT3:1; // 1 Input Flag for ADCCEVT3 Signal + Uint16 ADCCEVT4:1; // 2 Input Flag for ADCCEVT4 Signal + Uint16 ADCDEVT1:1; // 3 Input Flag for ADCDEVT1 Signal + Uint16 ADCDEVT2:1; // 4 Input Flag for ADCDEVT2 Signal + Uint16 ADCDEVT3:1; // 5 Input Flag for ADCDEVT3 Signal + Uint16 ADCDEVT4:1; // 6 Input Flag for ADCDEVT4 Signal + Uint16 SD1FLT1_COMPL:1; // 7 Input Flag for SD1FLT1.COMPL Signal + Uint16 SD1FLT1_COMPH:1; // 8 Input Flag for SD1FLT1.COMPH Signal + Uint16 SD1FLT2_COMPL:1; // 9 Input Flag for SD1FLT2.COMPL Signal + Uint16 SD1FLT2_COMPH:1; // 10 Input Flag for SD1FLT2.COMPH Signal + Uint16 SD1FLT3_COMPL:1; // 11 Input Flag for SD1FLT3.COMPL Signal + Uint16 SD1FLT3_COMPH:1; // 12 Input Flag for SD1FLT3.COMPH Signal + Uint16 SD1FLT4_COMPL:1; // 13 Input Flag for SD1FLT4.COMPL Signal + Uint16 SD1FLT4_COMPH:1; // 14 Input Flag for SD1FLT4.COMPH Signal + Uint16 SD2FLT1_COMPL:1; // 15 Input Flag for SD2FLT1.COMPL Signal + Uint16 SD2FLT1_COMPH:1; // 16 Input Flag for SD2FLT1.COMPH Signal + Uint16 SD2FLT2_COMPL:1; // 17 Input Flag for SD2FLT2.COMPL Signal + Uint16 SD2FLT2_COMPH:1; // 18 Input Flag for SD2FLT2.COMPH Signal + Uint16 SD2FLT3_COMPL:1; // 19 Input Flag for SD2FLT3.COMPL Signal + Uint16 SD2FLT3_COMPH:1; // 20 Input Flag for SD2FLT3.COMPH Signal + Uint16 SD2FLT4_COMPL:1; // 21 Input Flag for SD2FLT4.COMPL Signal + Uint16 SD2FLT4_COMPH:1; // 22 Input Flag for SD2FLT4.COMPH Signal + Uint16 rsvd1:9; // 31:23 Reserved +}; + +union XBARFLG3_REG { + Uint32 all; + struct XBARFLG3_BITS bit; +}; + +struct XBARCLR1_BITS { // bits description + Uint16 CMPSS1_CTRIPL:1; // 0 Input Flag Clear for CMPSS1.CTRIPL Signal + Uint16 CMPSS1_CTRIPH:1; // 1 Input Flag Clear for CMPSS1.CTRIPH Signal + Uint16 CMPSS2_CTRIPL:1; // 2 Input Flag Clear for CMPSS2.CTRIPL Signal + Uint16 CMPSS2_CTRIPH:1; // 3 Input Flag Clear for CMPSS2.CTRIPH Signal + Uint16 CMPSS3_CTRIPL:1; // 4 Input Flag Clear for CMPSS3.CTRIPL Signal + Uint16 CMPSS3_CTRIPH:1; // 5 Input Flag Clear for CMPSS3.CTRIPH Signal + Uint16 CMPSS4_CTRIPL:1; // 6 Input Flag Clear for CMPSS4.CTRIPL Signal + Uint16 CMPSS4_CTRIPH:1; // 7 Input Flag Clear for CMPSS4.CTRIPH Signal + Uint16 CMPSS5_CTRIPL:1; // 8 Input Flag Clear for CMPSS5.CTRIPL Signal + Uint16 CMPSS5_CTRIPH:1; // 9 Input Flag Clear for CMPSS5.CTRIPH Signal + Uint16 CMPSS6_CTRIPL:1; // 10 Input Flag Clear for CMPSS6.CTRIPL Signal + Uint16 CMPSS6_CTRIPH:1; // 11 Input Flag Clear for CMPSS6.CTRIPH Signal + Uint16 CMPSS7_CTRIPL:1; // 12 Input Flag Clear for CMPSS7.CTRIPL Signal + Uint16 CMPSS7_CTRIPH:1; // 13 Input Flag Clear for CMPSS7.CTRIPH Signal + Uint16 CMPSS8_CTRIPL:1; // 14 Input Flag Clear for CMPSS8.CTRIPL Signal + Uint16 CMPSS8_CTRIPH:1; // 15 Input Flag Clear for CMPSS8.CTRIPH Signal + Uint16 CMPSS1_CTRIPOUTL:1; // 16 Input Flag Clear for CMPSS1.CTRIPOUTL Signal + Uint16 CMPSS1_CTRIPOUTH:1; // 17 Input Flag Clear for CMPSS1.CTRIPOUTH Signal + Uint16 CMPSS2_CTRIPOUTL:1; // 18 Input Flag Clear for CMPSS2.CTRIPOUTL Signal + Uint16 CMPSS2_CTRIPOUTH:1; // 19 Input Flag Clear for CMPSS2.CTRIPOUTH Signal + Uint16 CMPSS3_CTRIPOUTL:1; // 20 Input Flag Clear for CMPSS3.CTRIPOUTL Signal + Uint16 CMPSS3_CTRIPOUTH:1; // 21 Input Flag Clear for CMPSS3.CTRIPOUTH Signal + Uint16 CMPSS4_CTRIPOUTL:1; // 22 Input Flag Clear for CMPSS4.CTRIPOUTL Signal + Uint16 CMPSS4_CTRIPOUTH:1; // 23 Input Flag Clear for CMPSS4.CTRIPOUTH Signal + Uint16 CMPSS5_CTRIPOUTL:1; // 24 Input Flag Clear for CMPSS5.CTRIPOUTL Signal + Uint16 CMPSS5_CTRIPOUTH:1; // 25 Input Flag Clear for CMPSS5.CTRIPOUTH Signal + Uint16 CMPSS6_CTRIPOUTL:1; // 26 Input Flag Clear for CMPSS6.CTRIPOUTL Signal + Uint16 CMPSS6_CTRIPOUTH:1; // 27 Input Flag Clear for CMPSS6.CTRIPOUTH Signal + Uint16 CMPSS7_CTRIPOUTL:1; // 28 Input Flag Clear for CMPSS7.CTRIPOUTL Signal + Uint16 CMPSS7_CTRIPOUTH:1; // 29 Input Flag Clear for CMPSS7.CTRIPOUTH Signal + Uint16 CMPSS8_CTRIPOUTL:1; // 30 Input Flag Clear for CMPSS8.CTRIPOUTL Signal + Uint16 CMPSS8_CTRIPOUTH:1; // 31 Input Flag Clear for CMPSS8.CTRIPOUTH Signal +}; + +union XBARCLR1_REG { + Uint32 all; + struct XBARCLR1_BITS bit; +}; + +struct XBARCLR2_BITS { // bits description + Uint16 INPUT1:1; // 0 Input Flag Clear for INPUT1 Signal + Uint16 INPUT2:1; // 1 Input Flag Clear for INPUT2 Signal + Uint16 INPUT3:1; // 2 Input Flag Clear for INPUT3 Signal + Uint16 INPUT4:1; // 3 Input Flag Clear for INPUT4 Signal + Uint16 INPUT5:1; // 4 Input Flag Clear for INPUT5 Signal + Uint16 INPUT7:1; // 5 Input Flag Clear for INPUT7 Signal + Uint16 ADCSOCAO:1; // 6 Input Flag Clear for ADCSOCAO Signal + Uint16 ADCSOCBO:1; // 7 Input Flag Clear for ADCSOCBO Signal + Uint16 rsvd1:1; // 8 Reserved + Uint16 rsvd2:1; // 9 Reserved + Uint16 rsvd3:1; // 10 Reserved + Uint16 rsvd4:1; // 11 Reserved + Uint16 rsvd5:1; // 12 Reserved + Uint16 rsvd6:1; // 13 Reserved + Uint16 rsvd7:1; // 14 Reserved + Uint16 rsvd8:1; // 15 Reserved + Uint16 ECAP1_OUT:1; // 16 Input Flag Clear for ECAP1.OUT Signal + Uint16 ECAP2_OUT:1; // 17 Input Flag Clear for ECAP2.OUT Signal + Uint16 ECAP3_OUT:1; // 18 Input Flag Clear for ECAP3.OUT Signal + Uint16 ECAP4_OUT:1; // 19 Input Flag Clear for ECAP4.OUT Signal + Uint16 ECAP5_OUT:1; // 20 Input Flag Clear for ECAP5.OUT Signal + Uint16 ECAP6_OUT:1; // 21 Input Flag Clear for ECAP6.OUT Signal + Uint16 EXTSYNCOUT:1; // 22 Input Flag Clear for EXTSYNCOUT Signal + Uint16 ADCAEVT1:1; // 23 Input Flag Clear for ADCAEVT1 Signal + Uint16 ADCAEVT2:1; // 24 Input Flag Clear for ADCAEVT2 Signal + Uint16 ADCAEVT3:1; // 25 Input Flag Clear for ADCAEVT3 Signal + Uint16 ADCAEVT4:1; // 26 Input Flag Clear for ADCAEVT4 Signal + Uint16 ADCBEVT1:1; // 27 Input Flag Clear for ADCBEVT1 Signal + Uint16 ADCBEVT2:1; // 28 Input Flag Clear for ADCBEVT2 Signal + Uint16 ADCBEVT3:1; // 29 Input Flag Clear for ADCBEVT3 Signal + Uint16 ADCBEVT4:1; // 30 Input Flag Clear for ADCBEVT4 Signal + Uint16 ADCCEVT1:1; // 31 Input Flag Clear for ADCCEVT1 Signal +}; + +union XBARCLR2_REG { + Uint32 all; + struct XBARCLR2_BITS bit; +}; + +struct XBARCLR3_BITS { // bits description + Uint16 ADCCEVT2:1; // 0 Input Flag Clear for ADCCEVT2 Signal + Uint16 ADCCEVT3:1; // 1 Input Flag Clear for ADCCEVT3 Signal + Uint16 ADCCEVT4:1; // 2 Input Flag Clear for ADCCEVT4 Signal + Uint16 ADCDEVT1:1; // 3 Input Flag Clear for ADCDEVT1 Signal + Uint16 ADCDEVT2:1; // 4 Input Flag Clear for ADCDEVT2 Signal + Uint16 ADCDEVT3:1; // 5 Input Flag Clear for ADCDEVT3 Signal + Uint16 ADCDEVT4:1; // 6 Input Flag Clear for ADCDEVT4 Signal + Uint16 SD1FLT1_COMPL:1; // 7 Input Flag Clear for SD1FLT1.COMPL Signal + Uint16 SD1FLT1_COMPH:1; // 8 Input Flag Clear for SD1FLT1.COMPH Signal + Uint16 SD1FLT2_COMPL:1; // 9 Input Flag Clear for SD1FLT2.COMPL Signal + Uint16 SD1FLT2_COMPH:1; // 10 Input Flag Clear for SD1FLT2.COMPH Signal + Uint16 SD1FLT3_COMPL:1; // 11 Input Flag Clear for SD1FLT3.COMPL Signal + Uint16 SD1FLT3_COMPH:1; // 12 Input Flag Clear for SD1FLT3.COMPH Signal + Uint16 SD1FLT4_COMPL:1; // 13 Input Flag Clear for SD1FLT4.COMPL Signal + Uint16 SD1FLT4_COMPH:1; // 14 Input Flag Clear for SD1FLT4.COMPH Signal + Uint16 SD2FLT1_COMPL:1; // 15 Input Flag Clear for SD2FLT1.COMPL Signal + Uint16 SD2FLT1_COMPH:1; // 16 Input Flag Clear for SD2FLT1.COMPH Signal + Uint16 SD2FLT2_COMPL:1; // 17 Input Flag Clear for SD2FLT2.COMPL Signal + Uint16 SD2FLT2_COMPH:1; // 18 Input Flag Clear for SD2FLT2.COMPH Signal + Uint16 SD2FLT3_COMPL:1; // 19 Input Flag Clear for SD2FLT3.COMPL Signal + Uint16 SD2FLT3_COMPH:1; // 20 Input Flag Clear for SD2FLT3.COMPH Signal + Uint16 SD2FLT4_COMPL:1; // 21 Input Flag Clear for SD2FLT4.COMPL Signal + Uint16 SD2FLT4_COMPH:1; // 22 Input Flag Clear for SD2FLT4.COMPH Signal + Uint16 rsvd1:9; // 31:23 Reserved +}; + +union XBARCLR3_REG { + Uint32 all; + struct XBARCLR3_BITS bit; +}; + +struct XBAR_REGS { + union XBARFLG1_REG XBARFLG1; // X-Bar Input Flag Register 1 + union XBARFLG2_REG XBARFLG2; // X-Bar Input Flag Register 2 + union XBARFLG3_REG XBARFLG3; // X-Bar Input Flag Register 3 + Uint16 rsvd1[2]; // Reserved + union XBARCLR1_REG XBARCLR1; // X-Bar Input Flag Clear Register 1 + union XBARCLR2_REG XBARCLR2; // X-Bar Input Flag Clear Register 2 + union XBARCLR3_REG XBARCLR3; // X-Bar Input Flag Clear Register 3 + Uint16 rsvd2[18]; // Reserved +}; + +//--------------------------------------------------------------------------- +// XBAR External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct XBAR_REGS XbarRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_xint.h b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_xint.h new file mode 100644 index 0000000000..f647e68b06 --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/include/F2837xD_xint.h @@ -0,0 +1,143 @@ +//########################################################################### +// +// FILE: F2837xD_xint.h +// +// TITLE: XINT Register Definitions. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __F2837xD_XINT_H__ +#define __F2837xD_XINT_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +//--------------------------------------------------------------------------- +// XINT Individual Register Bit Definitions: + +struct XINT1CR_BITS { // bits description + Uint16 ENABLE:1; // 0 XINT1 Enable + Uint16 rsvd1:1; // 1 Reserved + Uint16 POLARITY:2; // 3:2 XINT1 Polarity + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union XINT1CR_REG { + Uint16 all; + struct XINT1CR_BITS bit; +}; + +struct XINT2CR_BITS { // bits description + Uint16 ENABLE:1; // 0 XINT2 Enable + Uint16 rsvd1:1; // 1 Reserved + Uint16 POLARITY:2; // 3:2 XINT2 Polarity + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union XINT2CR_REG { + Uint16 all; + struct XINT2CR_BITS bit; +}; + +struct XINT3CR_BITS { // bits description + Uint16 ENABLE:1; // 0 XINT3 Enable + Uint16 rsvd1:1; // 1 Reserved + Uint16 POLARITY:2; // 3:2 XINT3 Polarity + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union XINT3CR_REG { + Uint16 all; + struct XINT3CR_BITS bit; +}; + +struct XINT4CR_BITS { // bits description + Uint16 ENABLE:1; // 0 XINT4 Enable + Uint16 rsvd1:1; // 1 Reserved + Uint16 POLARITY:2; // 3:2 XINT4 Polarity + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union XINT4CR_REG { + Uint16 all; + struct XINT4CR_BITS bit; +}; + +struct XINT5CR_BITS { // bits description + Uint16 ENABLE:1; // 0 XINT5 Enable + Uint16 rsvd1:1; // 1 Reserved + Uint16 POLARITY:2; // 3:2 XINT5 Polarity + Uint16 rsvd2:12; // 15:4 Reserved +}; + +union XINT5CR_REG { + Uint16 all; + struct XINT5CR_BITS bit; +}; + +struct XINT_REGS { + union XINT1CR_REG XINT1CR; // XINT1 configuration register + union XINT2CR_REG XINT2CR; // XINT2 configuration register + union XINT3CR_REG XINT3CR; // XINT3 configuration register + union XINT4CR_REG XINT4CR; // XINT4 configuration register + union XINT5CR_REG XINT5CR; // XINT5 configuration register + Uint16 rsvd1[3]; // Reserved + Uint16 XINT1CTR; // XINT1 counter register + Uint16 XINT2CTR; // XINT2 counter register + Uint16 XINT3CTR; // XINT3 counter register +}; + +//--------------------------------------------------------------------------- +// XINT External References & Function Declarations: +// +#ifdef CPU1 +extern volatile struct XINT_REGS XintRegs; +#endif +#ifdef CPU2 +extern volatile struct XINT_REGS XintRegs; +#endif +#ifdef __cplusplus +} +#endif /* extern "C" */ + +#endif + +//=========================================================================== +// End of file. +//=========================================================================== diff --git a/bsp/ti/c28x/libraries/tms320f28379d/headers/source/F2837xD_GlobalVariableDefs.c b/bsp/ti/c28x/libraries/tms320f28379d/headers/source/F2837xD_GlobalVariableDefs.c new file mode 100644 index 0000000000..270b63815a --- /dev/null +++ b/bsp/ti/c28x/libraries/tms320f28379d/headers/source/F2837xD_GlobalVariableDefs.c @@ -0,0 +1,876 @@ +//########################################################################### +// +// FILE: F2837xD_GlobalVariableDefs.c +// +// TITLE: F2837xD Global Variables and Data Section Pragmas. +// +//########################################################################### +// $TI Release: F2837xD Support Library v3.05.00.00 $ +// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $ +// $Copyright: +// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "F2837xD_device.h" // F2837xD Headerfile Include File + +//--------------------------------------------------------------------------- +// Define Global Peripheral Variables: +// +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcaRegsFile") +#else +#pragma DATA_SECTION(AdcaRegs,"AdcaRegsFile"); +#endif +volatile struct ADC_REGS AdcaRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("AdcbRegsFile") +#else +#pragma DATA_SECTION(AdcbRegs,"AdcbRegsFile"); +#endif +volatile struct ADC_REGS AdcbRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("AdccRegsFile") +#else +#pragma DATA_SECTION(AdccRegs,"AdccRegsFile"); +#endif +volatile struct ADC_REGS AdccRegs; + +#ifdef __cplusplus +#pragma DATA_SECTION("AdcdRegsFile") +#else +#pragma DATA_SECTION(AdcdRegs,"AdcdRegsFile"); +#endif +volatile struct ADC_REGS AdcdRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcaResultFile") +#else +#pragma DATA_SECTION(AdcaResultRegs,"AdcaResultFile"); +#endif +volatile struct ADC_RESULT_REGS AdcaResultRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcbResultFile") +#else +#pragma DATA_SECTION(AdcbResultRegs,"AdcbResultFile"); +#endif +volatile struct ADC_RESULT_REGS AdcbResultRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdccResultFile") +#else +#pragma DATA_SECTION(AdccResultRegs,"AdccResultFile"); +#endif +volatile struct ADC_RESULT_REGS AdccResultRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AdcdResultFile") +#else +#pragma DATA_SECTION(AdcdResultRegs,"AdcdResultFile"); +#endif +volatile struct ADC_RESULT_REGS AdcdResultRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("AnalogSubsysRegsFile") +#else +#pragma DATA_SECTION(AnalogSubsysRegs,"AnalogSubsysRegsFile"); +#endif +volatile struct ANALOG_SUBSYS_REGS AnalogSubsysRegs; +#endif + +#if __TI_COMPILER_VERSION__ >= 16006000 +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CanaRegsFile") +#else +#pragma DATA_SECTION(CanaRegs,"CanaRegsFile"); +#endif +volatile struct CAN_REGS CanaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CanbRegsFile") +#else +#pragma DATA_SECTION(CanbRegs,"CanbRegsFile"); +#endif +volatile struct CAN_REGS CanbRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss1RegsFile") +#else +#pragma DATA_SECTION(Cmpss1Regs,"Cmpss1RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss2RegsFile") +#else +#pragma DATA_SECTION(Cmpss2Regs,"Cmpss2RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss3RegsFile") +#else +#pragma DATA_SECTION(Cmpss3Regs,"Cmpss3RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss4RegsFile") +#else +#pragma DATA_SECTION(Cmpss4Regs,"Cmpss4RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss5RegsFile") +#else +#pragma DATA_SECTION(Cmpss5Regs,"Cmpss5RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss6RegsFile") +#else +#pragma DATA_SECTION(Cmpss6Regs,"Cmpss6RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss7RegsFile") +#else +#pragma DATA_SECTION(Cmpss7Regs,"Cmpss7RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cmpss8RegsFile") +#else +#pragma DATA_SECTION(Cmpss8Regs,"Cmpss8RegsFile"); +#endif +volatile struct CMPSS_REGS Cmpss8Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DacaRegsFile") +#else +#pragma DATA_SECTION(DacaRegs,"DacaRegsFile"); +#endif +volatile struct DAC_REGS DacaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DacbRegsFile") +#else +#pragma DATA_SECTION(DacbRegs,"DacbRegsFile"); +#endif +volatile struct DAC_REGS DacbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DaccRegsFile") +#else +#pragma DATA_SECTION(DaccRegs,"DaccRegsFile"); +#endif +volatile struct DAC_REGS DaccRegs; +//---------------------------------------- + +#ifdef __cplusplus +#pragma DATA_SECTION("Cla1RegsFile") +#else +#pragma DATA_SECTION(Cla1Regs,"Cla1RegsFile"); +#endif +volatile struct CLA_REGS Cla1Regs; +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Cla1SoftIntRegsFile") +#else +#pragma DATA_SECTION(Cla1SoftIntRegs,"Cla1SoftIntRegsFile"); +#endif +volatile struct CLA_SOFTINT_REGS Cla1SoftIntRegs; +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ClkCfgRegsFile") +#else +#pragma DATA_SECTION(ClkCfgRegs,"ClkCfgRegsFile"); +#endif +volatile struct CLK_CFG_REGS ClkCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuSysRegsFile") +#else +#pragma DATA_SECTION(CpuSysRegs,"CpuSysRegsFile"); +#endif +volatile struct CPU_SYS_REGS CpuSysRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer0RegsFile") +#else +#pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer0Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer1RegsFile") +#else +#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("CpuTimer2RegsFile") +#else +#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); +#endif +volatile struct CPUTIMER_REGS CpuTimer2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmZ1RegsFile") +#else +#pragma DATA_SECTION(DcsmZ1Regs,"DcsmZ1RegsFile"); +#endif +volatile struct DCSM_Z1_REGS DcsmZ1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmZ2RegsFile") +#else +#pragma DATA_SECTION(DcsmZ2Regs,"DcsmZ2RegsFile"); +#endif +volatile struct DCSM_Z2_REGS DcsmZ2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DcsmCommonRegsFile") +#else +#pragma DATA_SECTION(DcsmCommonRegs,"DcsmCommonRegsFile"); +#endif +volatile struct DCSM_COMMON_REGS DcsmCommonRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DmaRegsFile") +#else +#pragma DATA_SECTION(DmaRegs,"DmaRegsFile"); +#endif +volatile struct DMA_REGS DmaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("DmaClaSrcSelRegsFile") +#else +#pragma DATA_SECTION(DmaClaSrcSelRegs,"DmaClaSrcSelRegsFile"); +#endif +volatile struct DMA_CLA_SRC_SEL_REGS DmaClaSrcSelRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("DevCfgRegsFile") +#else +#pragma DATA_SECTION(DevCfgRegs,"DevCfgRegsFile"); +#endif +volatile struct DEV_CFG_REGS DevCfgRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap1RegsFile") +#else +#pragma DATA_SECTION(ECap1Regs,"ECap1RegsFile"); +#endif +volatile struct ECAP_REGS ECap1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap2RegsFile") +#else +#pragma DATA_SECTION(ECap2Regs,"ECap2RegsFile"); +#endif +volatile struct ECAP_REGS ECap2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap3RegsFile") +#else +#pragma DATA_SECTION(ECap3Regs,"ECap3RegsFile"); +#endif +volatile struct ECAP_REGS ECap3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap4RegsFile") +#else +#pragma DATA_SECTION(ECap4Regs,"ECap4RegsFile"); +#endif +volatile struct ECAP_REGS ECap4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap5RegsFile") +#else +#pragma DATA_SECTION(ECap5Regs,"ECap5RegsFile"); +#endif +volatile struct ECAP_REGS ECap5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ECap6RegsFile") +#else +#pragma DATA_SECTION(ECap6Regs,"ECap6RegsFile"); +#endif +volatile struct ECAP_REGS ECap6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif1RegsFile") +#else +#pragma DATA_SECTION(Emif1Regs,"Emif1RegsFile"); +#endif +volatile struct EMIF_REGS Emif1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif2RegsFile") +#else +#pragma DATA_SECTION(Emif2Regs,"Emif2RegsFile"); +#endif +volatile struct EMIF_REGS Emif2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep1RegsFile") +#else +#pragma DATA_SECTION(EQep1Regs,"EQep1RegsFile"); +#endif +volatile struct EQEP_REGS EQep1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep2RegsFile") +#else +#pragma DATA_SECTION(EQep2Regs,"EQep2RegsFile"); +#endif +volatile struct EQEP_REGS EQep2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EQep3RegsFile") +#else +#pragma DATA_SECTION(EQep3Regs,"EQep3RegsFile"); +#endif +volatile struct EQEP_REGS EQep3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm1RegsFile") +#else +#pragma DATA_SECTION(EPwm1Regs,"EPwm1RegsFile"); +#endif +volatile struct EPWM_REGS EPwm1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm2RegsFile") +#else +#pragma DATA_SECTION(EPwm2Regs,"EPwm2RegsFile"); +#endif +volatile struct EPWM_REGS EPwm2Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm3RegsFile") +#else +#pragma DATA_SECTION(EPwm3Regs,"EPwm3RegsFile"); +#endif +volatile struct EPWM_REGS EPwm3Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm4RegsFile") +#else +#pragma DATA_SECTION(EPwm4Regs,"EPwm4RegsFile"); +#endif +volatile struct EPWM_REGS EPwm4Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm5RegsFile") +#else +#pragma DATA_SECTION(EPwm5Regs,"EPwm5RegsFile"); +#endif +volatile struct EPWM_REGS EPwm5Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm6RegsFile") +#else +#pragma DATA_SECTION(EPwm6Regs,"EPwm6RegsFile"); +#endif +volatile struct EPWM_REGS EPwm6Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm7RegsFile") +#else +#pragma DATA_SECTION(EPwm7Regs,"EPwm7RegsFile"); +#endif +volatile struct EPWM_REGS EPwm7Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm8RegsFile") +#else +#pragma DATA_SECTION(EPwm8Regs,"EPwm8RegsFile"); +#endif +volatile struct EPWM_REGS EPwm8Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm9RegsFile") +#else +#pragma DATA_SECTION(EPwm9Regs,"EPwm9RegsFile"); +#endif +volatile struct EPWM_REGS EPwm9Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm10RegsFile") +#else +#pragma DATA_SECTION(EPwm10Regs,"EPwm10RegsFile"); +#endif +volatile struct EPWM_REGS EPwm10Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm11RegsFile") +#else +#pragma DATA_SECTION(EPwm11Regs,"EPwm11RegsFile"); +#endif +volatile struct EPWM_REGS EPwm11Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EPwm12RegsFile") +#else +#pragma DATA_SECTION(EPwm12Regs,"EPwm12RegsFile"); +#endif +volatile struct EPWM_REGS EPwm12Regs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("EPwmXbarRegsFile") +#else +#pragma DATA_SECTION(EPwmXbarRegs,"EPwmXbarRegsFile"); +#endif +volatile struct EPWM_XBAR_REGS EPwmXbarRegs; +#endif + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("GpioCtrlRegsFile") +#else +#pragma DATA_SECTION(GpioCtrlRegs,"GpioCtrlRegsFile"); +#endif +volatile struct GPIO_CTRL_REGS GpioCtrlRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("GpioDataRegsFile") +#else +#pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); +#endif +volatile struct GPIO_DATA_REGS GpioDataRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("InputXbarRegsFile") +#else +#pragma DATA_SECTION(InputXbarRegs,"InputXbarRegsFile"); +#endif +volatile struct INPUT_XBAR_REGS InputXbarRegs; +#endif + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("XbarRegsFile") +#else +#pragma DATA_SECTION(XbarRegs,"XbarRegsFile"); +#endif +volatile struct XBAR_REGS XbarRegs; +#endif + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("OutputXbarRegsFile") +#else +#pragma DATA_SECTION(OutputXbarRegs,"OutputXbarRegsFile"); +#endif +volatile struct OUTPUT_XBAR_REGS OutputXbarRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("I2caRegsFile") +#else +#pragma DATA_SECTION(I2caRegs,"I2caRegsFile"); +#endif +volatile struct I2C_REGS I2caRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("I2cbRegsFile") +#else +#pragma DATA_SECTION(I2cbRegs,"I2cbRegsFile"); +#endif +volatile struct I2C_REGS I2cbRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("IpcRegsFile") +#else +#pragma DATA_SECTION(IpcRegs,"IpcRegsFile"); +#endif +volatile struct IPC_REGS_CPU1 IpcRegs; +#endif + +//---------------------------------------- +#ifdef CPU2 +#ifdef __cplusplus +#pragma DATA_SECTION("IpcRegsFile") +#else +#pragma DATA_SECTION(IpcRegs,"IpcRegsFile"); +#endif +volatile struct IPC_REGS_CPU2 IpcRegs; +#endif + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("FlashPumpSemaphoreRegsFile") +#else +#pragma DATA_SECTION(FlashPumpSemaphoreRegs,"FlashPumpSemaphoreRegsFile"); +#endif +volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; +#endif + +//---------------------------------------- +#ifdef CPU2 +#ifdef __cplusplus +#pragma DATA_SECTION("FlashPumpSemaphoreRegsFile") +#else +#pragma DATA_SECTION(FlashPumpSemaphoreRegs,"FlashPumpSemaphoreRegsFile"); +#endif +volatile struct FLASH_PUMP_SEMAPHORE_REGS FlashPumpSemaphoreRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspaRegsFile") +#else +#pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile"); +#endif +volatile struct McBSP_REGS McbspaRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("RomPrefetchRegsFile") +#else +#pragma DATA_SECTION(RomPrefetchRegs,"RomPrefetchRegsFile"); +#endif +volatile struct ROM_PREFETCH_REGS RomPrefetchRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("MemCfgRegsFile") +#else +#pragma DATA_SECTION(MemCfgRegs,"MemCfgRegsFile"); +#endif +volatile struct MEM_CFG_REGS MemCfgRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Emif1ConfigRegsFile") +#else +#pragma DATA_SECTION(Emif1ConfigRegs,"Emif1ConfigRegsFile"); +#endif +volatile struct EMIF1_CONFIG_REGS Emif1ConfigRegs; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("Emif2ConfigRegsFile") +#else +#pragma DATA_SECTION(Emif2ConfigRegs,"Emif2ConfigRegsFile"); +#endif +volatile struct EMIF2_CONFIG_REGS Emif2ConfigRegs; +#endif + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("RomWaitStateRegsFile") +#else +#pragma DATA_SECTION(RomWaitStateRegs,"RomWaitStateRegsFile"); +#endif +volatile struct ROM_WAIT_STATE_REGS RomWaitStateRegs; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("AccessProtectionRegsFile") +#else +#pragma DATA_SECTION(AccessProtectionRegs,"AccessProtectionRegsFile"); +#endif +volatile struct ACCESS_PROTECTION_REGS AccessProtectionRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("MemoryErrorRegsFile") +#else +#pragma DATA_SECTION(MemoryErrorRegs,"MemoryErrorRegsFile"); +#endif +volatile struct MEMORY_ERROR_REGS MemoryErrorRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("McbspbRegsFile") +#else +#pragma DATA_SECTION(McbspbRegs,"McbspbRegsFile"); +#endif +volatile struct McBSP_REGS McbspbRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("NmiIntruptRegsFile") +#else +#pragma DATA_SECTION(NmiIntruptRegs,"NmiIntruptRegsFile"); +#endif +volatile struct NMI_INTRUPT_REGS NmiIntruptRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieCtrlRegsFile") +#else +#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); +#endif +volatile struct PIE_CTRL_REGS PieCtrlRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("PieVectTableFile") +#else +#pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); +#endif +volatile struct PIE_VECT_TABLE PieVectTable; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SciaRegsFile") +#else +#pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); +#endif +volatile struct SCI_REGS SciaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScibRegsFile") +#else +#pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); +#endif +volatile struct SCI_REGS ScibRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScicRegsFile") +#else +#pragma DATA_SECTION(ScicRegs,"ScicRegsFile"); +#endif +volatile struct SCI_REGS ScicRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("ScidRegsFile") +#else +#pragma DATA_SECTION(ScidRegs,"ScidRegsFile"); +#endif +volatile struct SCI_REGS ScidRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpiaRegsFile") +#else +#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); +#endif +volatile struct SPI_REGS SpiaRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpibRegsFile") +#else +#pragma DATA_SECTION(SpibRegs,"SpibRegsFile"); +#endif +volatile struct SPI_REGS SpibRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("SpicRegsFile") +#else +#pragma DATA_SECTION(SpicRegs,"SpicRegsFile"); +#endif +volatile struct SPI_REGS SpicRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Sdfm1RegsFile") +#else +#pragma DATA_SECTION(Sdfm1Regs,"Sdfm1RegsFile"); +#endif +volatile struct SDFM_REGS Sdfm1Regs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Sdfm2RegsFile") +#else +#pragma DATA_SECTION(Sdfm2Regs,"Sdfm2RegsFile"); +#endif +volatile struct SDFM_REGS Sdfm2Regs; + + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("SyncSocRegsFile") +#else +#pragma DATA_SECTION(SyncSocRegs,"SyncSocRegsFile"); +#endif +volatile struct SYNC_SOC_REGS SyncSocRegs; +#endif + +//---------------------------------------- +#if defined(CPU1) +#ifdef __cplusplus +#pragma DATA_SECTION("UppRegsFile") +#else +#pragma DATA_SECTION(UppRegs,"UppRegsFile"); +#endif +volatile struct UPP_REGS UppRegs; +#endif //defined(CPU1) + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("WdRegsFile") +#else +#pragma DATA_SECTION(WdRegs,"WdRegsFile"); +#endif +volatile struct WD_REGS WdRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("XintRegsFile") +#else +#pragma DATA_SECTION(XintRegs,"XintRegsFile"); +#endif +volatile struct XINT_REGS XintRegs; + +//-------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("EmuBModeVar"); +#else +#pragma DATA_SECTION(EmuBMode,"EmuBModeVar"); +#endif +Uint16 EmuBMode; + +//---------------------------------------- +#ifdef CPU1 +#ifdef __cplusplus +#pragma DATA_SECTION("EmuBootPinsVar"); +#else +#pragma DATA_SECTION(EmuBootPins,"EmuBootPinsVar"); +#endif +Uint16 EmuBootPins; +#endif + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Flash0EccRegsFile") +#else +#pragma DATA_SECTION(Flash0EccRegs,"Flash0EccRegsFile"); +#endif +volatile struct FLASH_ECC_REGS Flash0EccRegs; + +//---------------------------------------- +#ifdef __cplusplus +#pragma DATA_SECTION("Flash0CtrlRegsFile") +#else +#pragma DATA_SECTION(Flash0CtrlRegs,"Flash0CtrlRegsFile"); +#endif +volatile struct FLASH_CTRL_REGS Flash0CtrlRegs; + + +//=========================================================================== +// End of file. +//=========================================================================== + diff --git a/bsp/ti/c28x/tms320f28379d/.ccsproject b/bsp/ti/c28x/tms320f28379d/.ccsproject new file mode 100644 index 0000000000..028ef9f5ea --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/.ccsproject @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/bsp/ti/c28x/tms320f28379d/.config b/bsp/ti/c28x/tms320f28379d/.config new file mode 100644 index 0000000000..670b11aaff --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/.config @@ -0,0 +1,689 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Configuration +# +CONFIG_SOC_TMS320F28X=y + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +CONFIG_RT_THREAD_PRIORITY_8=y +# CONFIG_RT_THREAD_PRIORITY_32 is not set +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=8 +CONFIG_RT_TICK_PER_SECOND=100 +# CONFIG_RT_USING_OVERFLOW_CHECK is not set +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +# CONFIG_RT_USING_TIMER_SOFT is not set + +# +# kservice optimization +# +# CONFIG_RT_KSERVICE_USING_STDLIB is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +CONFIG_RT_DEBUG=y +CONFIG_RT_DEBUG_COLOR=y +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="scia" +CONFIG_RT_VER_NUM=0x50000 +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_TIDSP=y +CONFIG_ARCH_TIDSP_C28X=y +CONFIG_ARCH_CPU_STACK_GROWS_UPWARD=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=4 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=4 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +# CONFIG_RT_USING_DFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +CONFIG_RT_USING_ADC=y +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_PWM=y +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set + +# +# PainterEngine: A cross-platform graphics application framework written in C language +# +# CONFIG_PKG_USING_PAINTERENGINE is not set +# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ULOG_FILE is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_RTDUINO is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_RTT_ESP_IDF is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_BL_MCU_SDK is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set + +# +# Hardware Drivers Config +# + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +# CONFIG_BSP_USING_XINT is not set +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_USING_PWM is not set +CONFIG_BSP_USING_ADC=y +CONFIG_BSP_USING_ADC1=y +CONFIG_BSP_ADC_USING_12BIT=y +# CONFIG_BSP_ADC_USING_16BIT is not set +CONFIG_BSP_USING_ADC2=y +CONFIG_BSP_USING_ADC3=y +# CONFIG_BSP_USING_ONCHIP_RTC is not set +# CONFIG_BSP_USING_WDT is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_USBD is not set + +# +# Board extended module Drivers +# diff --git a/bsp/ti/c28x/tms320f28379d/.cproject b/bsp/ti/c28x/tms320f28379d/.cproject new file mode 100644 index 0000000000..d3421753e2 --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/.cproject @@ -0,0 +1,225 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/ti/c28x/tms320f28379d/.gitignore b/bsp/ti/c28x/tms320f28379d/.gitignore new file mode 100644 index 0000000000..025af2b856 --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/.gitignore @@ -0,0 +1,3 @@ +.launches/ +FLASH +RAM diff --git a/bsp/ti/c28x/tms320f28379d/.project b/bsp/ti/c28x/tms320f28379d/.project new file mode 100644 index 0000000000..e8a85337b5 --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/.project @@ -0,0 +1,849 @@ + + + rt-thread + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + DeviceDrivers + 2 + virtual:/virtual + + + Kernel + 2 + PARENT-2-PROJECT_LOC/src + + + c28x + 2 + virtual:/virtual + + + finsh + 2 + virtual:/virtual + + + libraries + 2 + virtual:/virtual + + + DeviceDrivers/adc.c + 1 + PARENT-4-PROJECT_LOC/components/drivers/misc/adc.c + + + DeviceDrivers/ipc + 2 + PARENT-4-PROJECT_LOC/components/drivers/ipc + + + DeviceDrivers/pin.c + 1 + PARENT-4-PROJECT_LOC/components/drivers/misc/pin.c + + + DeviceDrivers/rt_drv_pwm.c + 1 + PARENT-4-PROJECT_LOC/components/drivers/misc/rt_drv_pwm.c + + + DeviceDrivers/serial.c + 1 + PARENT-4-PROJECT_LOC/components/drivers/serial/serial.c + + + Kernel/Kconfig + 1 + PARENT-4-PROJECT_LOC/src/Kconfig + + + Kernel/SConscript + 1 + PARENT-4-PROJECT_LOC/src/SConscript + + + Kernel/clock.c + 1 + PARENT-4-PROJECT_LOC/src/clock.c + + + Kernel/components.c + 1 + PARENT-4-PROJECT_LOC/src/components.c + + + Kernel/cpu.c + 1 + PARENT-4-PROJECT_LOC/src/cpu.c + + + Kernel/device.c + 1 + PARENT-4-PROJECT_LOC/src/device.c + + + Kernel/idle.c + 1 + PARENT-4-PROJECT_LOC/src/idle.c + + + Kernel/ipc.c + 1 + PARENT-4-PROJECT_LOC/src/ipc.c + + + Kernel/irq.c + 1 + PARENT-4-PROJECT_LOC/src/irq.c + + + Kernel/kservice.c + 1 + PARENT-4-PROJECT_LOC/src/kservice.c + + + Kernel/mem.c + 1 + PARENT-4-PROJECT_LOC/src/mem.c + + + Kernel/memheap.c + 1 + PARENT-4-PROJECT_LOC/src/memheap.c + + + Kernel/mempool.c + 1 + PARENT-4-PROJECT_LOC/src/mempool.c + + + Kernel/object.c + 1 + PARENT-4-PROJECT_LOC/src/object.c + + + Kernel/scheduler.c + 1 + PARENT-4-PROJECT_LOC/src/scheduler.c + + + Kernel/signal.c + 1 + PARENT-4-PROJECT_LOC/src/signal.c + + + Kernel/slab.c + 1 + PARENT-4-PROJECT_LOC/src/slab.c + + + Kernel/thread.c + 1 + PARENT-4-PROJECT_LOC/src/thread.c + + + Kernel/timer.c + 1 + PARENT-4-PROJECT_LOC/src/timer.c + + + c28x/SConscript + 1 + PARENT-4-PROJECT_LOC/libcpu/ti-dsp/c28x/SConscript + + + c28x/context.s + 1 + PARENT-4-PROJECT_LOC/libcpu/ti-dsp/c28x/context.s + + + c28x/cpuport.c + 1 + PARENT-4-PROJECT_LOC/libcpu/ti-dsp/c28x/cpuport.c + + + finsh/Kconfig + 1 + PARENT-4-PROJECT_LOC/components/finsh/Kconfig + + + finsh/SConscript + 1 + PARENT-4-PROJECT_LOC/components/finsh/SConscript + + + finsh/cmd.c + 1 + PARENT-4-PROJECT_LOC/components/finsh/cmd.c + + + finsh/finsh.h + 1 + PARENT-4-PROJECT_LOC/components/finsh/finsh.h + + + finsh/msh.c + 1 + PARENT-4-PROJECT_LOC/components/finsh/msh.c + + + finsh/msh.h + 1 + PARENT-4-PROJECT_LOC/components/finsh/msh.h + + + finsh/msh_file.c + 1 + PARENT-4-PROJECT_LOC/components/finsh/msh_file.c + + + finsh/msh_parse.c + 1 + PARENT-4-PROJECT_LOC/components/finsh/msh_parse.c + + + finsh/msh_parse.h + 1 + PARENT-4-PROJECT_LOC/components/finsh/msh_parse.h + + + finsh/shell.c + 1 + PARENT-4-PROJECT_LOC/components/finsh/shell.c + + + finsh/shell.h + 1 + PARENT-4-PROJECT_LOC/components/finsh/shell.h + + + libraries/HAL_Drivers + 2 + virtual:/virtual + + + libraries/tms320f28379d + 2 + virtual:/virtual + + + libraries/HAL_Drivers/config + 2 + virtual:/virtual + + + libraries/HAL_Drivers/drv_adc.c + 1 + PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/drv_adc.c + + + libraries/HAL_Drivers/drv_adc.h + 1 + PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/drv_adc.h + + + libraries/HAL_Drivers/drv_config.h + 1 + PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/drv_config.h + + + libraries/HAL_Drivers/drv_gpio.c + 1 + PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/drv_gpio.c + + + libraries/HAL_Drivers/drv_gpio.h + 1 + PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/drv_gpio.h + + + libraries/HAL_Drivers/drv_pwm.c + 1 + PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/drv_pwm.c + + + libraries/HAL_Drivers/drv_pwm.h + 1 + PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/drv_pwm.h + + + libraries/HAL_Drivers/drv_sci.c + 1 + PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/drv_sci.c + + + libraries/HAL_Drivers/drv_sci.h + 1 + PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/drv_sci.h + + + libraries/tms320f28379d/common + 2 + virtual:/virtual + + + libraries/tms320f28379d/headers + 2 + virtual:/virtual + + + libraries/HAL_Drivers/config/adc_config.h + 1 + PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/config/adc_config.h + + + libraries/HAL_Drivers/config/pwm_config.h + 1 + PARENT-1-PROJECT_LOC/libraries/HAL_Drivers/config/pwm_config.h + + + libraries/tms320f28379d/common/include + 2 + virtual:/virtual + + + libraries/tms320f28379d/common/source + 2 + virtual:/virtual + + + libraries/tms320f28379d/headers/cmd + 2 + virtual:/virtual + + + libraries/tms320f28379d/headers/include + 2 + virtual:/virtual + + + libraries/tms320f28379d/headers/source + 2 + virtual:/virtual + + + libraries/tms320f28379d/common/include/F2837xD_Adc_defines.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Adc_defines.h + + + libraries/tms320f28379d/common/include/F2837xD_Can_defines.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Can_defines.h + + + libraries/tms320f28379d/common/include/F2837xD_Cla_defines.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Cla_defines.h + + + libraries/tms320f28379d/common/include/F2837xD_Cla_typedefs.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Cla_typedefs.h + + + libraries/tms320f28379d/common/include/F2837xD_Dma_defines.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Dma_defines.h + + + libraries/tms320f28379d/common/include/F2837xD_EPwm_defines.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_EPwm_defines.h + + + libraries/tms320f28379d/common/include/F2837xD_Emif_defines.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Emif_defines.h + + + libraries/tms320f28379d/common/include/F2837xD_Examples.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Examples.h + + + libraries/tms320f28379d/common/include/F2837xD_GlobalPrototypes.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_GlobalPrototypes.h + + + libraries/tms320f28379d/common/include/F2837xD_Gpio_defines.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Gpio_defines.h + + + libraries/tms320f28379d/common/include/F2837xD_I2c_defines.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_I2c_defines.h + + + libraries/tms320f28379d/common/include/F2837xD_Ipc_defines.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Ipc_defines.h + + + libraries/tms320f28379d/common/include/F2837xD_Ipc_drivers.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Ipc_drivers.h + + + libraries/tms320f28379d/common/include/F2837xD_Pie_defines.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Pie_defines.h + + + libraries/tms320f28379d/common/include/F2837xD_SWPrioritizedIsrLevels.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_SWPrioritizedIsrLevels.h + + + libraries/tms320f28379d/common/include/F2837xD_SysCtrl_defines.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_SysCtrl_defines.h + + + libraries/tms320f28379d/common/include/F2837xD_Systick_defines.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Systick_defines.h + + + libraries/tms320f28379d/common/include/F2837xD_Upp_defines.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_Upp_defines.h + + + libraries/tms320f28379d/common/include/F2837xD_cputimervars.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_cputimervars.h + + + libraries/tms320f28379d/common/include/F2837xD_defaultisr.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_defaultisr.h + + + libraries/tms320f28379d/common/include/F2837xD_sci_io.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_sci_io.h + + + libraries/tms320f28379d/common/include/F2837xD_sdfm_drivers.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_sdfm_drivers.h + + + libraries/tms320f28379d/common/include/F2837xD_struct.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F2837xD_struct.h + + + libraries/tms320f28379d/common/include/F28x_Project.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/F28x_Project.h + + + libraries/tms320f28379d/common/include/device.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/device.h + + + libraries/tms320f28379d/common/include/driverlib.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/driverlib.h + + + libraries/tms320f28379d/common/include/stdint.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/stdint.h + + + libraries/tms320f28379d/common/include/usb.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/usb.h + + + libraries/tms320f28379d/common/include/usb_hal.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/include/usb_hal.h + + + libraries/tms320f28379d/common/source/F2837xD_Adc.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Adc.c + + + libraries/tms320f28379d/common/source/F2837xD_CodeStartBranch.asm + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_CodeStartBranch.asm + + + libraries/tms320f28379d/common/source/F2837xD_CpuTimers.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_CpuTimers.c + + + libraries/tms320f28379d/common/source/F2837xD_DBGIER.asm + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_DBGIER.asm + + + libraries/tms320f28379d/common/source/F2837xD_DefaultISR.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_DefaultISR.c + + + libraries/tms320f28379d/common/source/F2837xD_Dma.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Dma.c + + + libraries/tms320f28379d/common/source/F2837xD_ECap.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_ECap.c + + + libraries/tms320f28379d/common/source/F2837xD_EPwm.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_EPwm.c + + + libraries/tms320f28379d/common/source/F2837xD_EQep.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_EQep.c + + + libraries/tms320f28379d/common/source/F2837xD_Emif.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Emif.c + + + libraries/tms320f28379d/common/source/F2837xD_Gpio.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Gpio.c + + + libraries/tms320f28379d/common/source/F2837xD_I2C.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_I2C.c + + + libraries/tms320f28379d/common/source/F2837xD_Ipc.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Ipc.c + + + libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver.c + + + libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Lite.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Lite.c + + + libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Util.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Ipc_Driver_Util.c + + + libraries/tms320f28379d/common/source/F2837xD_Mcbsp.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Mcbsp.c + + + libraries/tms320f28379d/common/source/F2837xD_PieCtrl.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_PieCtrl.c + + + libraries/tms320f28379d/common/source/F2837xD_PieVect.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_PieVect.c + + + libraries/tms320f28379d/common/source/F2837xD_SWPrioritizedPieVect.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_SWPrioritizedPieVect.c + + + libraries/tms320f28379d/common/source/F2837xD_Sci.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Sci.c + + + libraries/tms320f28379d/common/source/F2837xD_Spi.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Spi.c + + + libraries/tms320f28379d/common/source/F2837xD_SysCtrl.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_SysCtrl.c + + + libraries/tms320f28379d/common/source/F2837xD_TempSensorConv.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_TempSensorConv.c + + + libraries/tms320f28379d/common/source/F2837xD_Upp.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_Upp.c + + + libraries/tms320f28379d/common/source/F2837xD_can.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_can.c + + + libraries/tms320f28379d/common/source/F2837xD_sci_io.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_sci_io.c + + + libraries/tms320f28379d/common/source/F2837xD_sdfm_drivers.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_sdfm_drivers.c + + + libraries/tms320f28379d/common/source/F2837xD_struct.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_struct.c + + + libraries/tms320f28379d/common/source/F2837xD_usDelay.asm + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/F2837xD_usDelay.asm + + + libraries/tms320f28379d/common/source/device.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/device.c + + + libraries/tms320f28379d/common/source/usb.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/usb.c + + + libraries/tms320f28379d/common/source/usb_hal.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/common/source/usb_hal.c + + + libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu1.cmd + + + libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_BIOS_cpu2.cmd + + + libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu1.cmd + + + libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/cmd/F2837xD_Headers_nonBIOS_cpu2.cmd + + + libraries/tms320f28379d/headers/include/F2837xD_adc.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_adc.h + + + libraries/tms320f28379d/headers/include/F2837xD_analogsubsys.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_analogsubsys.h + + + libraries/tms320f28379d/headers/include/F2837xD_can.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_can.h + + + libraries/tms320f28379d/headers/include/F2837xD_cla.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_cla.h + + + libraries/tms320f28379d/headers/include/F2837xD_cmpss.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_cmpss.h + + + libraries/tms320f28379d/headers/include/F2837xD_cputimer.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_cputimer.h + + + libraries/tms320f28379d/headers/include/F2837xD_dac.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_dac.h + + + libraries/tms320f28379d/headers/include/F2837xD_dcsm.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_dcsm.h + + + libraries/tms320f28379d/headers/include/F2837xD_device.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_device.h + + + libraries/tms320f28379d/headers/include/F2837xD_dma.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_dma.h + + + libraries/tms320f28379d/headers/include/F2837xD_ecap.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_ecap.h + + + libraries/tms320f28379d/headers/include/F2837xD_emif.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_emif.h + + + libraries/tms320f28379d/headers/include/F2837xD_epwm.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_epwm.h + + + libraries/tms320f28379d/headers/include/F2837xD_epwm_xbar.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_epwm_xbar.h + + + libraries/tms320f28379d/headers/include/F2837xD_eqep.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_eqep.h + + + libraries/tms320f28379d/headers/include/F2837xD_flash.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_flash.h + + + libraries/tms320f28379d/headers/include/F2837xD_gpio.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_gpio.h + + + libraries/tms320f28379d/headers/include/F2837xD_i2c.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_i2c.h + + + libraries/tms320f28379d/headers/include/F2837xD_input_xbar.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_input_xbar.h + + + libraries/tms320f28379d/headers/include/F2837xD_ipc.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_ipc.h + + + libraries/tms320f28379d/headers/include/F2837xD_mcbsp.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_mcbsp.h + + + libraries/tms320f28379d/headers/include/F2837xD_memconfig.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_memconfig.h + + + libraries/tms320f28379d/headers/include/F2837xD_nmiintrupt.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_nmiintrupt.h + + + libraries/tms320f28379d/headers/include/F2837xD_output_xbar.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_output_xbar.h + + + libraries/tms320f28379d/headers/include/F2837xD_piectrl.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_piectrl.h + + + libraries/tms320f28379d/headers/include/F2837xD_pievect.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_pievect.h + + + libraries/tms320f28379d/headers/include/F2837xD_sci.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_sci.h + + + libraries/tms320f28379d/headers/include/F2837xD_sdfm.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_sdfm.h + + + libraries/tms320f28379d/headers/include/F2837xD_spi.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_spi.h + + + libraries/tms320f28379d/headers/include/F2837xD_sysctrl.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_sysctrl.h + + + libraries/tms320f28379d/headers/include/F2837xD_upp.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_upp.h + + + libraries/tms320f28379d/headers/include/F2837xD_xbar.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_xbar.h + + + libraries/tms320f28379d/headers/include/F2837xD_xint.h + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/include/F2837xD_xint.h + + + libraries/tms320f28379d/headers/source/F2837xD_GlobalVariableDefs.c + 1 + PARENT-1-PROJECT_LOC/libraries/tms320f28379d/headers/source/F2837xD_GlobalVariableDefs.c + + + diff --git a/bsp/ti/c28x/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs b/bsp/ti/c28x/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000000..f653028c53 --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/bsp/ti/c28x/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs b/bsp/ti/c28x/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs new file mode 100644 index 0000000000..2adc7b1dde --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/.settings/org.eclipse.cdt.debug.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.debug.core.toggleBreakpointModel=com.ti.ccstudio.debug.CCSBreakpointMarker diff --git a/bsp/ti/c28x/tms320f28379d/.settings/org.eclipse.core.resources.prefs b/bsp/ti/c28x/tms320f28379d/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000000..814522b6df --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,91 @@ +eclipse.preferences.version=1 +encoding//Debug/drivers/subdir_rules.mk=UTF-8 +encoding//Debug/drivers/subdir_vars.mk=UTF-8 +encoding//Debug/libraries/common/source/subdir_rules.mk=UTF-8 +encoding//Debug/libraries/common/source/subdir_vars.mk=UTF-8 +encoding//Debug/libraries/headers/cmd/subdir_rules.mk=UTF-8 +encoding//Debug/libraries/headers/cmd/subdir_vars.mk=UTF-8 +encoding//Debug/libraries/headers/source/subdir_rules.mk=UTF-8 +encoding//Debug/libraries/headers/source/subdir_vars.mk=UTF-8 +encoding//FLASH/DeviceDrivers/ipc/subdir_rules.mk=UTF-8 +encoding//FLASH/DeviceDrivers/ipc/subdir_vars.mk=UTF-8 +encoding//FLASH/DeviceDrivers/subdir_rules.mk=UTF-8 +encoding//FLASH/DeviceDrivers/subdir_vars.mk=UTF-8 +encoding//FLASH/Kernel/subdir_rules.mk=UTF-8 +encoding//FLASH/Kernel/subdir_vars.mk=UTF-8 +encoding//FLASH/applications/subdir_rules.mk=UTF-8 +encoding//FLASH/applications/subdir_vars.mk=UTF-8 +encoding//FLASH/board/subdir_rules.mk=UTF-8 +encoding//FLASH/board/subdir_vars.mk=UTF-8 +encoding//FLASH/c28x/subdir_rules.mk=UTF-8 +encoding//FLASH/c28x/subdir_vars.mk=UTF-8 +encoding//FLASH/drivers/subdir_rules.mk=UTF-8 +encoding//FLASH/drivers/subdir_vars.mk=UTF-8 +encoding//FLASH/finsh/subdir_rules.mk=UTF-8 +encoding//FLASH/finsh/subdir_vars.mk=UTF-8 +encoding//FLASH/libraries/HAL_Drivers/subdir_rules.mk=UTF-8 +encoding//FLASH/libraries/HAL_Drivers/subdir_vars.mk=UTF-8 +encoding//FLASH/libraries/common/source/subdir_rules.mk=UTF-8 +encoding//FLASH/libraries/common/source/subdir_vars.mk=UTF-8 +encoding//FLASH/libraries/headers/cmd/subdir_rules.mk=UTF-8 +encoding//FLASH/libraries/headers/cmd/subdir_vars.mk=UTF-8 +encoding//FLASH/libraries/headers/source/subdir_rules.mk=UTF-8 +encoding//FLASH/libraries/headers/source/subdir_vars.mk=UTF-8 +encoding//FLASH/libraries/tms320f28379d/common/cmd/subdir_rules.mk=UTF-8 +encoding//FLASH/libraries/tms320f28379d/common/cmd/subdir_vars.mk=UTF-8 +encoding//FLASH/libraries/tms320f28379d/common/deprecated/driverlib/subdir_rules.mk=UTF-8 +encoding//FLASH/libraries/tms320f28379d/common/deprecated/driverlib/subdir_vars.mk=UTF-8 +encoding//FLASH/libraries/tms320f28379d/common/deprecated/utils/subdir_rules.mk=UTF-8 +encoding//FLASH/libraries/tms320f28379d/common/deprecated/utils/subdir_vars.mk=UTF-8 +encoding//FLASH/libraries/tms320f28379d/common/source/subdir_rules.mk=UTF-8 +encoding//FLASH/libraries/tms320f28379d/common/source/subdir_vars.mk=UTF-8 +encoding//FLASH/libraries/tms320f28379d/headers/cmd/subdir_rules.mk=UTF-8 +encoding//FLASH/libraries/tms320f28379d/headers/cmd/subdir_vars.mk=UTF-8 +encoding//FLASH/libraries/tms320f28379d/headers/source/subdir_rules.mk=UTF-8 +encoding//FLASH/libraries/tms320f28379d/headers/source/subdir_vars.mk=UTF-8 +encoding//FLASH/makefile=UTF-8 +encoding//FLASH/objects.mk=UTF-8 +encoding//FLASH/sources.mk=UTF-8 +encoding//FLASH/subdir_rules.mk=UTF-8 +encoding//FLASH/subdir_vars.mk=UTF-8 +encoding//RAM/DeviceDrivers/ipc/subdir_rules.mk=UTF-8 +encoding//RAM/DeviceDrivers/ipc/subdir_vars.mk=UTF-8 +encoding//RAM/DeviceDrivers/subdir_rules.mk=UTF-8 +encoding//RAM/DeviceDrivers/subdir_vars.mk=UTF-8 +encoding//RAM/Kernel/subdir_rules.mk=UTF-8 +encoding//RAM/Kernel/subdir_vars.mk=UTF-8 +encoding//RAM/applications/subdir_rules.mk=UTF-8 +encoding//RAM/applications/subdir_vars.mk=UTF-8 +encoding//RAM/board/subdir_rules.mk=UTF-8 +encoding//RAM/board/subdir_vars.mk=UTF-8 +encoding//RAM/c28x/subdir_rules.mk=UTF-8 +encoding//RAM/c28x/subdir_vars.mk=UTF-8 +encoding//RAM/drivers/subdir_rules.mk=UTF-8 +encoding//RAM/drivers/subdir_vars.mk=UTF-8 +encoding//RAM/finsh/subdir_rules.mk=UTF-8 +encoding//RAM/finsh/subdir_vars.mk=UTF-8 +encoding//RAM/libraries/HAL_Drivers/subdir_rules.mk=UTF-8 +encoding//RAM/libraries/HAL_Drivers/subdir_vars.mk=UTF-8 +encoding//RAM/libraries/common/source/subdir_rules.mk=UTF-8 +encoding//RAM/libraries/common/source/subdir_vars.mk=UTF-8 +encoding//RAM/libraries/headers/cmd/subdir_rules.mk=UTF-8 +encoding//RAM/libraries/headers/cmd/subdir_vars.mk=UTF-8 +encoding//RAM/libraries/headers/source/subdir_rules.mk=UTF-8 +encoding//RAM/libraries/headers/source/subdir_vars.mk=UTF-8 +encoding//RAM/libraries/tms320f28379d/common/cmd/subdir_rules.mk=UTF-8 +encoding//RAM/libraries/tms320f28379d/common/cmd/subdir_vars.mk=UTF-8 +encoding//RAM/libraries/tms320f28379d/common/deprecated/driverlib/subdir_rules.mk=UTF-8 +encoding//RAM/libraries/tms320f28379d/common/deprecated/driverlib/subdir_vars.mk=UTF-8 +encoding//RAM/libraries/tms320f28379d/common/deprecated/utils/subdir_rules.mk=UTF-8 +encoding//RAM/libraries/tms320f28379d/common/deprecated/utils/subdir_vars.mk=UTF-8 +encoding//RAM/libraries/tms320f28379d/common/source/subdir_rules.mk=UTF-8 +encoding//RAM/libraries/tms320f28379d/common/source/subdir_vars.mk=UTF-8 +encoding//RAM/libraries/tms320f28379d/headers/cmd/subdir_rules.mk=UTF-8 +encoding//RAM/libraries/tms320f28379d/headers/cmd/subdir_vars.mk=UTF-8 +encoding//RAM/libraries/tms320f28379d/headers/source/subdir_rules.mk=UTF-8 +encoding//RAM/libraries/tms320f28379d/headers/source/subdir_vars.mk=UTF-8 +encoding//RAM/makefile=UTF-8 +encoding//RAM/objects.mk=UTF-8 +encoding//RAM/sources.mk=UTF-8 +encoding//RAM/subdir_rules.mk=UTF-8 +encoding//RAM/subdir_vars.mk=UTF-8 diff --git a/bsp/ti/c28x/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd b/bsp/ti/c28x/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd new file mode 100644 index 0000000000..9787987d30 --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/2837x_FLASH_lnk_cpu1.cmd @@ -0,0 +1,119 @@ +___heap_end = 0x010000; +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to Flash" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RESET : origin = 0x3FFFC0, length = 0x000002 + RAMGS8_15 : origin = 0x013000, length = 0x009000 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x002000 /* on-chip Flash */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + RAMM0 : origin = 0x000122, length = 0x0002DE + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + EBSS : origin = 0x008000, length = 0x008000 /* RAMLS0-4, 5*0x0800 */ + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHF PAGE = 0, ALIGN(4) + .pinit : > FLASHF, PAGE = 0, ALIGN(4) + .text : >> FLASHE PAGE = 0, ALIGN(4) + codestart : > BEGIN PAGE = 0, ALIGN(4) + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} LOAD = FLASHF, + RUN = RAMGS8_15, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #else + ramfuncs : LOAD = FLASHF, + RUN = RAMGS8_15, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(4) + #endif +#endif + + FSymTab : > RAMM1, PAGE = 1, ALIGN(4) + LOAD_START(___fsymtab_start) + LOAD_END(___fsymtab_end) + .rti_fn.0.end : > RAMM1, PAGE = 1 + .rti_fn.0 : > RAMM1, PAGE = 1 + .rti_fn.1 : > RAMM1, PAGE = 1 + .rti_fn.2 : > RAMM1, PAGE = 1 + .rti_fn.3 : > RAMM1, PAGE = 1 + .rti_fn.4 : > RAMM1, PAGE = 1 + .rti_fn.5 : > RAMM1, PAGE = 1 + .rti_fn.1.end : > RAMM1, PAGE = 1 + .rti_fn.6.end : > RAMM1, PAGE = 1 + .rti_fn.6 : > RAMM1, PAGE = 1 + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .ebss : > EBSS, + LOAD_START(___ebss_start), + LOAD_END(___ebss_end), + PAGE = 1 + .esysmem : >> RAMM1 PAGE = 1 + + /* Initalized sections go in Flash */ + .econst : >> FLASHF PAGE = 0, ALIGN(4) + .switch : > FLASHF PAGE = 0, ALIGN(4) + + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/ti/c28x/tms320f28379d/2837x_RAM_lnk_cpu1.cmd b/bsp/ti/c28x/tms320f28379d/2837x_RAM_lnk_cpu1.cmd new file mode 100644 index 0000000000..5eae476e44 --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/2837x_RAM_lnk_cpu1.cmd @@ -0,0 +1,83 @@ +___heap_end = 0x00F000; + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000122, length = 0x0002DE + RESET : origin = 0x3FFFC0, length = 0x000002 + RAMGS8_15 : origin = 0x013000, length = 0x009000 + +PAGE 1 : + RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */ + BOOT_RSVD : origin = 0x000002, length = 0x000120 /* Part of M0, BOOT rom will use this for stack */ + EBSS : origin = 0x008000, length = 0x007000 /* RAMLS0-4, 5*0x0800 */ + ECONST : origin = 0x00F000, length = 0x004000 /* RAMGS0-2, 3*0x1000 */ + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + .text : > RAMGS8_15, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .pinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + .rti_fn.0.end : > RAMM1, PAGE = 1 + .rti_fn.0 : > RAMM1, PAGE = 1 + .rti_fn.1 : > RAMM1, PAGE = 1 + .rti_fn.2 : > RAMM1, PAGE = 1 + .rti_fn.3 : > RAMM1, PAGE = 1 + .rti_fn.4 : > RAMM1, PAGE = 1 + .rti_fn.5 : > RAMM1, PAGE = 1 + .rti_fn.1.end : > RAMM1, PAGE = 1 + .rti_fn.6.end : > RAMM1, PAGE = 1 + .rti_fn.6 : > RAMM1, PAGE = 1 + .stack : > RAMM1, PAGE = 1 + .esysmem : > RAMM1, PAGE = 1 + + .ebss : > EBSS, + LOAD_START(___ebss_start), + LOAD_END(___ebss_end), + PAGE = 1 + + .econst : > ECONST, PAGE = 1 + + /* finsh symbol table */ + FSymTab : > RAMM1, PAGE = 1, ALIGN(4) + LOAD_START(___fsymtab_start) + LOAD_END(___fsymtab_end) + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/bsp/ti/c28x/tms320f28379d/Kconfig b/bsp/ti/c28x/tms320f28379d/Kconfig new file mode 100644 index 0000000000..3e83f321c5 --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/Kconfig @@ -0,0 +1,30 @@ +mainmenu "RT-Thread Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../../../.." + +# you can change the RTT_ROOT default "../.." to your rtthread_root, +# example : default "F:/git_repositories/rt-thread" + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +config SOC_TMS320F28X + bool + select ARCH_TIDSP_C28X + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "board/Kconfig" diff --git a/bsp/ti/c28x/tms320f28379d/README.md b/bsp/ti/c28x/tms320f28379d/README.md new file mode 100644 index 0000000000..ef453d80a7 --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/README.md @@ -0,0 +1,107 @@ +# TMS320F28379D + + +## 1. 简介 + +TMS320F28379D BSP 基于 C2000 Delfino MCU F28379D LaunchPad 开发套件开发。 +TMS320F28379D 是一款功能强大的 32 位浮点微控制器单元 (MCU)，针对高级闭环控制应用而设计，例如工业驱动器和伺服电机控制、太阳能逆变器和转换器、数字电源、电力输送以及电力线通信。 + +![launch-28379d](figures/launch-28379d.png) + +包括如下硬件特性： + +| 硬件 | 描述 | +| -- | -- | +|芯片型号| TMS320F28379D | +|多核 CPU| 两个 TMS320C28x 32 位 CPU | +|| 两个可编程控制律加速器 (CLA) | +|主频| 200MHz | +|CLA 频率| 200MHz | +|总处理能力| 800MIPS | +|片内SRAM| 204kB | +|片内Flash| 1MB | + +F28379D LaunchPad 板载资源如下： +* USB 调试和下载接口通过电气隔离的高速 XDS100v2 调试器实现，同时包含虚拟串口功能 +* TMS320F28379D CPU +* 两个 LED +* 设备复位按钮 +* 易于使用的引出引脚，用于调试或用作扩展板的接口 +* 双 5V 正交编码接口 +* 带集成收发器的 CAN 接口 +* 拨码开关用于启动模式选择 +* 差分放大器向差分模式 ADC 提供 16 位模式的缓冲信号 +* 可选的 SMA 连接点 +* 四个 Sigma-Delta 解调器输入到 BP 接口 + +## 2. 编译说明 +TMS320F28379D 程序的编译和下载要使用的是 TI 官方提供的 Code Composer Studio，TMS320F28379D 至少需要 CCS6.0 以上的版本才能正常编译调试。本 BSP 在 CCS7/CCS8 版本上测试通过，其他版本未做测试。可以在 TI 的官方站点上下载最新版本的 CCS。[CCS 官方下载站点][3] +### 2.1 导入工程 +首先打开 Code Composer Studio，点击 Project -> Import CCS Projects... + +![import](figures/import.png) + +在打开的对话框中，点击 Select search -> directory 右边的 Browse... 选择 TMS320F28379D BSP 所在文件夹，如图所示。选择完成后点击 Finish 完成导入。 + +![import_dia](figures/import_dia.png) + +### 2.2 编译工程 +使用 CCS 内置的 C 编译器可以进行工程的编译。CCS 8 需要使用 TI v18.1.3.LTS 编译器。CCS 10 需要使用 TI v20.2.1.LTS 及以上版本编译器（v20.2.0.LTS及以下版本的编译器有bug编译时会出现segmentation fault）。本文使用的是 Code Composer Studio 10.1.1 和 TI v20.2.4.LTS 编译器的组合（已经配置在工程文件中）。导入工程后，在右边的 Project Explorer 列表里可以看到刚刚导入的 rt-thread 工程。本BSP提供两种编译的方式，分别用于在RAM中执行和在FLASH中执行。 +如图所示可以选择RAM和FLASH进行build。 +![](figures/build.png) +## 3. 烧写及执行 + +编译完成后，可以开始下载和调试。把开发板和电脑通过 Mini-USB 线连接，使用 CCS 中的烧写功能可直接通过板载 XDS100v2 仿真器烧写并执行。 + +![debug_as](figures/debug_as.png) + +在右边的 Project Explorer 的列表中右键点击 rt-thread 工程，在弹出的菜单中选择 Debug As -> 1 Code Composer Debug Session。 + +![launching](figures/launching.png) + +在弹出的 Launching Debug Session 对话框中可以选择要调试的 CPU 核和 CLA 核，这里我们只选择 C28xx_CPU1，点击 OK 开始下载和调试。 + +下载完成后，CCS 将进入调试模式，可以选择继续运行、单步调试、复位等操作。 + +退出 CCS 调试模式，在终端工具里打开相应的串口（115200-8-1-N），按下板子上的复位按钮执行复位操作后，可以看到 RT-Thread 的输出信息: +```bash + \ | / +- RT - Thread Operating System + / | \ 4.1.1 build Jul 4 2022 22:33:37 + 2006 - 2022 Copyright by RT-Thread team + msh > + ``` + +## 4. 注意事项 + +* 由于当前还暂未编写 Scons 编译系统对 CCS 开发环境的支持，所以在使用 env 中的 menuconfig 进行配置后，如果添加了新的组件或软件包，需要手动在 CCS 中添加相应的 C 源文件和头文件。 + +## 5. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| CPU Timer | | | +| GPIO | 支持 | | +| SCI | 支持 | SCIA/B/C | +| ePWM | 支持| | +| ADC |支持| | +| DAC | | | +| I2C | | | +| SPI | | | +| CAN | | | +| eCAP | | | + +## 6. 联系人信息 + +维护人： +1. guyunjie < yunjie.gu1@gmail.com > +2. qiyu < qiyu_sjtu@163.com > + +## 7. 参考 + +* [C2000 Delfino MCU F28379D LaunchPad 开发套件][1] +* TMS320F28379D [相关技术文档][2] + + [1]: http://www.ti.com.cn/tool/cn/launchxl-f28379d + [2]: http://www.ti.com.cn/product/cn/tms320f28379d/technicaldocuments + [3]: http://processors.wiki.ti.com/index.php/Download_CCS#Download_the_latest_CCS diff --git a/bsp/ti/c28x/tms320f28379d/applications/startup.c b/bsp/ti/c28x/tms320f28379d/applications/startup.c new file mode 100644 index 0000000000..16854cfc06 --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/applications/startup.c @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2006-08-31 Bernard first implementation + * 2018-09-02 xuzhuoyi modify for TMS320F28379D version + * 2022-08-21 qiyu modify the entry function + */ + +#include +#include +#include +#include "board.h" + +int main(void) +{ + unsigned long x=10000; + + while(x) + { + x--; + } +} + +/*@}*/ diff --git a/bsp/ti/c28x/tms320f28379d/board/Kconfig b/bsp/ti/c28x/tms320f28379d/board/Kconfig new file mode 100644 index 0000000000..1510a81dfc --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/board/Kconfig @@ -0,0 +1,1087 @@ +menu "Hardware Drivers Config" + +menu "Onboard Peripheral Drivers" +endmenu + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + menuconfig BSP_USING_XINT + bool "Enable external interrupt" + default n + if BSP_USING_XINT + menuconfig BSP_USING_XINT1 + bool "Enable XINT1" + if BSP_USING_XINT1 + config BSP_XINT1_PIN + int "Interrupt pin" + range 0 168 + default 0 + endif + if !BSP_USING_XINT1 + config BSP_XINT1_PIN + int + default -1 + endif + menuconfig BSP_USING_XINT2 + bool "Enable XINT2" + if BSP_USING_XINT2 + config BSP_XINT2_PIN + int "Interrupt pin" + range 0 168 + default 0 + endif + if !BSP_USING_XINT2 + config BSP_XINT2_PIN + int + default -1 + endif + menuconfig BSP_USING_XINT3 + bool "Enable XINT3" + if BSP_USING_XINT3 + config BSP_XINT3_PIN + int "Interrupt pin" + range 0 168 + default 0 + endif + if !BSP_USING_XINT3 + config BSP_XINT3_PIN + int + default -1 + endif + menuconfig BSP_USING_XINT4 + bool "Enable XINT4" + if BSP_USING_XINT4 + config BSP_XINT4_PIN + int "Interrupt pin" + range 0 168 + default 0 + endif + if !BSP_USING_XINT4 + config BSP_XINT4_PIN + int + default -1 + endif + if !BSP_USING_XINT5 + config BSP_XINT5_PIN + int + default -1 + endif + menuconfig BSP_USING_XINT5 + bool "Enable XINT5" + if BSP_USING_XINT5 + config BSP_XINT5_PIN + int "Interrupt pin" + range 0 168 + default 0 + endif + endif + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + endif + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + + if BSP_USING_PWM + menuconfig BSP_USING_PWM1 + bool "Enable ePWM1" + default n + if BSP_USING_PWM1 + menu "Basic settings for PWM1" + config BSP_PWM1_INIT_PERIOD + int "Initial period for PWM1(ns)" + default 10000 + config BSP_PWM1_INIT_PULSE + int "Initial pulse for PWM1(ns)" + default 1000 + endmenu + menu "Advanced Settings for PWM1" + menuconfig BSP_PWM1_PHASE_ENABLE + bool "Enable phase" + default n + if BSP_PWM1_PHASE_ENABLE + choice + prompt "Select master or slave" + default BSP_PWM1_MASTER + config BSP_PWM1_MASTER + bool "Master" + config BSP_PWM1_SLAVE + bool "Slave" + endchoice + if BSP_PWM1_MASTER + config BSP_PWM1_PHASE + int + default 0 + endif + if BSP_PWM1_SLAVE + config BSP_PWM1_PHASE + int "Phase, 0~360" + range 0 360 + default 0 + help + the phase for PWM1 module + endif + endif + + menuconfig BSP_PWM1_IT_ENABLE + bool "Enable interrupt service" + default n + if BSP_PWM1_IT_ENABLE + choice + prompt "Select interrupt time" + default BSP_PWM1_INTSEL_ET_CTR_ZERO + config BSP_PWM1_INTSEL_ET_DCAEVT1SOC + bool "DCAEVT1SOC" + config BSP_PWM1_INTSEL_ET_CTR_ZERO + bool "ctr == zero" + config BSP_PWM1_INTSEL_ET_CTR_PRD + bool "ctr == prd" + config BSP_PWM1_INTSEL_ET_CTR_PRDZERO + bool "ctr == prd or ctr == zero" + config BSP_PWM1_INTSEL_ET_CTRU_CMPA + bool "ctr == compa when counting up" + config BSP_PWM1_INTSEL_ET_CTRD_CMPA + bool "ctr == compa when counting down" + config BSP_PWM1_INTSEL_ET_CTRU_CMPB + bool "ctr == compb when counting up" + config BSP_PWM1_INTSEL_ET_CTRD_CMPB + bool "ctr == compb when counting down" + endchoice + + config BSP_PWM1_INTSEL + int + default 0 if BSP_PWM1_INTSEL_ET_DCAEVT1SOC + default 1 if BSP_PWM1_INTSEL_ET_CTR_ZERO + default 2 if BSP_PWM1_INTSEL_ET_CTR_PRD + default 3 if BSP_PWM1_INTSEL_ET_CTR_PRDZERO + default 4 if BSP_PWM1_INTSEL_ET_CTRU_CMPA + default 5 if BSP_PWM1_INTSEL_ET_CTRD_CMPA + default 6 if BSP_PWM1_INTSEL_ET_CTRU_CMPB + default 7 if BSP_PWM1_INTSEL_ET_CTRD_CMPB + choice + prompt "Interrupt generation time" + default BSP_PWM1_INT_ET_1ST + config BSP_PWM1_INT_ET_DISABLE + bool "disable PWM interrupt" + config BSP_PWM1_INT_ET_1ST + bool "generate interrupt at the first time" + config BSP_PWM1_INT_ET_2ND + bool "generate interrupt at the second time" + config BSP_PWM1_INT_ET_3RD + bool "generate interrupt at the third time" + endchoice + config BSP_PWM1_INTPRD + int + default 0 if BSP_PWM1_INT_ET_DISABLE + default 1 if BSP_PWM1_INT_ET_1ST + default 2 if BSP_PWM1_INT_ET_2ND + default 3 if BSP_PWM1_INT_ET_3RD + endif + choice + prompt "HSP Clock division" + default BSP_PWM1_HSPCLKDIV1 + config BSP_PWM1_HSPCLKDIV1 + bool "Clock Divided by 1" + config BSP_PWM1_HSPCLKDIV2 + bool "Clock Divided by 2" + config BSP_PWM1_HSPCLKDIV4 + bool "Clock Divided by 4" + endchoice + config BSP_PWM1_HSPCLKDIV + int + default 0 if BSP_PWM1_HSPCLKDIV1 + default 1 if BSP_PWM1_HSPCLKDIV2 + default 2 if BSP_PWM1_HSPCLKDIV4 + choice + prompt "Clock division" + default BSP_PWM1_CLKDIV1 + config BSP_PWM1_CLKDIV1 + bool "Clock Divided by 1" + config BSP_PWM1_CLKDIV2 + bool "Clock Divided by 2" + config BSP_PWM1_CLKDIV4 + bool "Clock Divided by 4" + endchoice + config BSP_PWM1_CLKDIV + int + default 0 if BSP_PWM1_CLKDIV1 + default 1 if BSP_PWM1_CLKDIV2 + default 2 if BSP_PWM1_CLKDIV4 + choice + default BSP_PWM1_CTR_MODE_UPDOWN + prompt "Select counter mode" + config BSP_PWM1_CTR_MODE_UPDOWN + bool "Up-down mode" + config BSP_PWM1_CTR_MODE_UP + bool "Up mode" + config BSP_PWM1_CTR_MODE_DOWN + bool "Down mode" + config BSP_PWM1_CTR_FREEZE + bool "Freezing Counter" + endchoice + config BSP_PWM1_CTRMODE + int + default 0 if BSP_PWM1_CTR_MODE_UP + default 1 if BSP_PWM1_CTR_MODE_DOWN + default 2 if BSP_PWM1_CTR_MODE_UPDOWN + default 3 if BSP_PWM1_CTR_FREEZE + choice + prompt "Register load mode" + config BSP_PWM1_CC_CTR_ZERO + bool "Load when counter == 0" + config BSP_PWM1_CC_CTR_PRD + bool "Load when counter == prd" + config BSP_PWM1_CC_CTR_ZERO_PRD + bool "load when counter ==0 or counter == prd" + config BSP_PWM1_CC_LD_DISABLE + bool "disable load" + endchoice + + config BSP_PWM1_LOADAMODE + int + default 0 if BSP_PWM1_CC_CTR_ZERO + default 1 if BSP_PWM1_CC_CTR_PRD + default 2 if BSP_PWM1_CC_CTR_ZERO_PRD + default 3 if BSP_PWM1_CC_LD_DISABLE + + config BSP_PWM1_DB + int "Dead time(ns)" + default 100 + range 0 100000 + menuconfig BSP_PWM1_ADC_TRIGGER + bool "Enable ADC trigger from PWM1" + if BSP_PWM1_ADC_TRIGGER + choice + prompt "Select soc triggering time" + default BSP_PWM1_SOCASEL_ET_CTR_ZERO + config BSP_PWM1_SOCASEL_ET_DCAEVT1SOC + bool "DCAEVT1SOC" + config BSP_PWM1_SOCASEL_ET_CTR_ZERO + bool "ctr == zero" + config BSP_PWM1_SOCASEL_ET_CTR_PRD + bool "ctr == prd" + config BSP_PWM1_SOCASEL_ET_CTR_PRDZERO + bool "ctr == prd or ctr == zero" + config BSP_PWM1_SOCASEL_ET_CTRU_CMPA + bool "ctr == compa when counting up" + config BSP_PWM1_SOCASEL_ET_CTRD_CMPA + bool "ctr == compa when counting down" + config BSP_PWM1_SOCASEL_ET_CTRU_CMPB + bool "ctr == compb when counting up" + config BSP_PWM1_SOCASEL_ET_CTRD_CMPB + bool "ctr == compb when counting down" + endchoice + + config BSP_PWM1_SOCASEL + int + default 0 if BSP_PWM1_SOCASEL_ET_DCAEVT1SOC + default 1 if BSP_PWM1_SOCASEL_ET_CTR_ZERO + default 2 if BSP_PWM1_SOCASEL_ET_CTR_PRD + default 3 if BSP_PWM1_SOCASEL_ET_CTR_PRDZERO + default 4 if BSP_PWM1_SOCASEL_ET_CTRU_CMPA + default 5 if BSP_PWM1_SOCASEL_ET_CTRD_CMPA + default 6 if BSP_PWM1_SOCASEL_ET_CTRU_CMPB + default 7 if BSP_PWM1_SOCASEL_ET_CTRD_CMPB + choice + prompt "SOCA generation time" + default BSP_PWM1_SOCA_ET_1ST + config BSP_PWM1_SOCA_ET_DISABLE + bool "disable soc generation" + config BSP_PWM1_SOCA_ET_1ST + bool "generate soc at the first time" + config BSP_PWM1_SOCA_ET_2ND + bool "generate soc at the second time" + config BSP_PWM1_SOCA_ET_3RD + bool "generate soc at the third time" + endchoice + config BSP_PWM1_SOCAPRD + int + default 0 if BSP_PWM1_SOCA_ET_DISABLE + default 1 if BSP_PWM1_SOCA_ET_1ST + default 2 if BSP_PWM1_SOCA_ET_2ND + default 3 if BSP_PWM1_SOCA_ET_3RD + endif + endmenu + endif + menuconfig BSP_USING_PWM2 + bool "Enable ePWM2" + default n + if BSP_USING_PWM2 + menu "Basic settings for PWM2" + config BSP_PWM2_INIT_PERIOD + int "Initial period for PWM2(ns)" + default 10000 + config BSP_PWM2_INIT_PULSE + int "Initial pulse for PWM2(ns)" + default 1000 + endmenu + menu "Advanced Settings for PWM2" + menuconfig BSP_PWM2_PHASE_ENABLE + bool "Enable phase" + default n + if BSP_PWM2_PHASE_ENABLE + choice + prompt "Select master or slave" + default BSP_PWM2_SLAVE + config BSP_PWM2_MASTER + bool "Master" + config BSP_PWM2_SLAVE + bool "Slave" + endchoice + if BSP_PWM2_MASTER + config BSP_PWM2_PHASE + int + default 0 + endif + if BSP_PWM2_SLAVE + config BSP_PWM2_PHASE + int "Phase, 0~360" + range 0 360 + default 0 + help + the phase for PWM2 module + endif + endif + + menuconfig BSP_PWM2_IT_ENABLE + bool "Enable interrupt service" + default n + if BSP_PWM2_IT_ENABLE + choice + prompt "Select interrupt time" + default BSP_PWM2_INTSEL_ET_CTR_ZERO + config BSP_PWM2_INTSEL_ET_DCAEVT1SOC + bool "DCAEVT1SOC" + config BSP_PWM2_INTSEL_ET_CTR_ZERO + bool "ctr == zero" + config BSP_PWM2_INTSEL_ET_CTR_PRD + bool "ctr == prd" + config BSP_PWM2_INTSEL_ET_CTR_PRDZERO + bool "ctr == prd or ctr == zero" + config BSP_PWM2_INTSEL_ET_CTRU_CMPA + bool "ctr == compa when counting up" + config BSP_PWM2_INTSEL_ET_CTRD_CMPA + bool "ctr == compa when counting down" + config BSP_PWM2_INTSEL_ET_CTRU_CMPB + bool "ctr == compb when counting up" + config BSP_PWM2_INTSEL_ET_CTRD_CMPB + bool "ctr == compb when counting down" + endchoice + + config BSP_PWM2_INTSEL + int + default 0 if BSP_PWM2_INTSEL_ET_DCAEVT1SOC + default 1 if BSP_PWM2_INTSEL_ET_CTR_ZERO + default 2 if BSP_PWM2_INTSEL_ET_CTR_PRD + default 3 if BSP_PWM2_INTSEL_ET_CTR_PRDZERO + default 4 if BSP_PWM2_INTSEL_ET_CTRU_CMPA + default 5 if BSP_PWM2_INTSEL_ET_CTRD_CMPA + default 6 if BSP_PWM2_INTSEL_ET_CTRU_CMPB + default 7 if BSP_PWM2_INTSEL_ET_CTRD_CMPB + choice + prompt "Interrupt generation time" + default BSP_PWM2_INT_ET_1ST + config BSP_PWM2_INT_ET_DISABLE + bool "disable PWM interrupt" + config BSP_PWM2_INT_ET_1ST + bool "generate interrupt at the first time" + config BSP_PWM2_INT_ET_2ND + bool "generate interrupt at the second time" + config BSP_PWM2_INT_ET_3RD + bool "generate interrupt at the third time" + endchoice + config BSP_PWM2_INTPRD + int + default 0 if BSP_PWM2_INT_ET_DISABLE + default 1 if BSP_PWM2_INT_ET_1ST + default 2 if BSP_PWM2_INT_ET_2ND + default 3 if BSP_PWM2_INT_ET_3RD + endif + choice + prompt "HSP Clock division" + default BSP_PWM2_HSPCLKDIV1 + config BSP_PWM2_HSPCLKDIV1 + bool "Clock Divided by 1" + config BSP_PWM2_HSPCLKDIV2 + bool "Clock Divided by 2" + config BSP_PWM2_HSPCLKDIV4 + bool "Clock Divided by 4" + endchoice + config BSP_PWM2_HSPCLKDIV + int + default 0 if BSP_PWM2_HSPCLKDIV1 + default 1 if BSP_PWM2_HSPCLKDIV2 + default 2 if BSP_PWM2_HSPCLKDIV4 + choice + prompt "Clock division" + default BSP_PWM2_CLKDIV1 + config BSP_PWM2_CLKDIV1 + bool "Clock Divided by 1" + config BSP_PWM2_CLKDIV2 + bool "Clock Divided by 2" + config BSP_PWM2_CLKDIV4 + bool "Clock Divided by 4" + endchoice + config BSP_PWM2_CLKDIV + int + default 0 if BSP_PWM2_CLKDIV1 + default 1 if BSP_PWM2_CLKDIV2 + default 2 if BSP_PWM2_CLKDIV4 + choice + default BSP_PWM2_CTR_MODE_UPDOWN + prompt "Select counter mode" + config BSP_PWM2_CTR_MODE_UPDOWN + bool "Up-down mode" + config BSP_PWM2_CTR_MODE_UP + bool "Up mode" + config BSP_PWM2_CTR_MODE_DOWN + bool "Down mode" + config BSP_PWM2_CTR_FREEZE + bool "Freezing Counter" + endchoice + config BSP_PWM2_CTRMODE + int + default 0 if BSP_PWM2_CTR_MODE_UP + default 1 if BSP_PWM2_CTR_MODE_DOWN + default 2 if BSP_PWM2_CTR_MODE_UPDOWN + default 3 if BSP_PWM2_CTR_FREEZE + choice + prompt "Register load mode" + config BSP_PWM2_CC_CTR_ZERO + bool "Load when counter == 0" + config BSP_PWM2_CC_CTR_PRD + bool "Load when counter == prd" + config BSP_PWM2_CC_CTR_ZERO_PRD + bool "load when counter ==0 or counter == prd" + config BSP_PWM2_CC_LD_DISABLE + bool "disable load" + endchoice + + config BSP_PWM2_LOADAMODE + int + default 0 if BSP_PWM2_CC_CTR_ZERO + default 1 if BSP_PWM2_CC_CTR_PRD + default 2 if BSP_PWM2_CC_CTR_ZERO_PRD + default 3 if BSP_PWM2_CC_LD_DISABLE + + config BSP_PWM2_DB + int "Dead time(ns)" + default 100 + range 0 100000 + menuconfig BSP_PWM2_ADC_TRIGGER + bool "Enable ADC trigger from PWM2" + if BSP_PWM2_ADC_TRIGGER + choice + prompt "Select soc triggering time" + default BSP_PWM2_SOCASEL_ET_CTR_ZERO + config BSP_PWM2_SOCASEL_ET_DCAEVT1SOC + bool "DCAEVT1SOC" + config BSP_PWM2_SOCASEL_ET_CTR_ZERO + bool "ctr == zero" + config BSP_PWM2_SOCASEL_ET_CTR_PRD + bool "ctr == prd" + config BSP_PWM2_SOCASEL_ET_CTR_PRDZERO + bool "ctr == prd or ctr == zero" + config BSP_PWM2_SOCASEL_ET_CTRU_CMPA + bool "ctr == compa when counting up" + config BSP_PWM2_SOCASEL_ET_CTRD_CMPA + bool "ctr == compa when counting down" + config BSP_PWM2_SOCASEL_ET_CTRU_CMPB + bool "ctr == compb when counting up" + config BSP_PWM2_SOCASEL_ET_CTRD_CMPB + bool "ctr == compb when counting down" + endchoice + + config BSP_PWM2_SOCASEL + int + default 0 if BSP_PWM2_SOCASEL_ET_DCAEVT1SOC + default 1 if BSP_PWM2_SOCASEL_ET_CTR_ZERO + default 2 if BSP_PWM2_SOCASEL_ET_CTR_PRD + default 3 if BSP_PWM2_SOCASEL_ET_CTR_PRDZERO + default 4 if BSP_PWM2_SOCASEL_ET_CTRU_CMPA + default 5 if BSP_PWM2_SOCASEL_ET_CTRD_CMPA + default 6 if BSP_PWM2_SOCASEL_ET_CTRU_CMPB + default 7 if BSP_PWM2_SOCASEL_ET_CTRD_CMPB + choice + prompt "SOCA generation time" + default BSP_PWM2_SOCA_ET_1ST + config BSP_PWM2_SOCA_ET_DISABLE + bool "disable soc generation" + config BSP_PWM2_SOCA_ET_1ST + bool "generate soc at the first time" + config BSP_PWM2_SOCA_ET_2ND + bool "generate soc at the second time" + config BSP_PWM2_SOCA_ET_3RD + bool "generate soc at the third time" + endchoice + config BSP_PWM2_SOCAPRD + int + default 0 if BSP_PWM2_SOCA_ET_DISABLE + default 1 if BSP_PWM2_SOCA_ET_1ST + default 2 if BSP_PWM2_SOCA_ET_2ND + default 3 if BSP_PWM2_SOCA_ET_3RD + endif + endmenu + endif + menuconfig BSP_USING_PWM3 + bool "Enable ePWM3" + default n + if BSP_USING_PWM3 + menu "Basic settings for PWM3" + config BSP_PWM3_INIT_PERIOD + int "Initial period for PWM3(ns)" + default 10000 + config BSP_PWM3_INIT_PULSE + int "Initial pulse for PWM3(ns)" + default 1000 + endmenu + menu "Advanced Settings for PWM3" + menuconfig BSP_PWM3_PHASE_ENABLE + bool "Enable phase" + default n + if BSP_PWM3_PHASE_ENABLE + choice + prompt "Select master or slave" + default BSP_PWM3_SLAVE + config BSP_PWM3_MASTER + bool "Master" + config BSP_PWM3_SLAVE + bool "Slave" + endchoice + if BSP_PWM3_MASTER + config BSP_PWM3_PHASE + int + default 0 + endif + if BSP_PWM3_SLAVE + config BSP_PWM3_PHASE + int "Phase, 0~360" + range 0 360 + default 0 + help + the phase for PWM3 module + endif + endif + + menuconfig BSP_PWM3_IT_ENABLE + bool "Enable interrupt service" + default n + if BSP_PWM3_IT_ENABLE + choice + prompt "Select interrupt time" + default BSP_PWM3_INTSEL_ET_CTR_ZERO + config BSP_PWM3_INTSEL_ET_DCAEVT1SOC + bool "DCAEVT1SOC" + config BSP_PWM3_INTSEL_ET_CTR_ZERO + bool "ctr == zero" + config BSP_PWM3_INTSEL_ET_CTR_PRD + bool "ctr == prd" + config BSP_PWM3_INTSEL_ET_CTR_PRDZERO + bool "ctr == prd or ctr == zero" + config BSP_PWM3_INTSEL_ET_CTRU_CMPA + bool "ctr == compa when counting up" + config BSP_PWM3_INTSEL_ET_CTRD_CMPA + bool "ctr == compa when counting down" + config BSP_PWM3_INTSEL_ET_CTRU_CMPB + bool "ctr == compb when counting up" + config BSP_PWM3_INTSEL_ET_CTRD_CMPB + bool "ctr == compb when counting down" + endchoice + + config BSP_PWM3_INTSEL + int + default 0 if BSP_PWM3_INTSEL_ET_DCAEVT1SOC + default 1 if BSP_PWM3_INTSEL_ET_CTR_ZERO + default 2 if BSP_PWM3_INTSEL_ET_CTR_PRD + default 3 if BSP_PWM3_INTSEL_ET_CTR_PRDZERO + default 4 if BSP_PWM3_INTSEL_ET_CTRU_CMPA + default 5 if BSP_PWM3_INTSEL_ET_CTRD_CMPA + default 6 if BSP_PWM3_INTSEL_ET_CTRU_CMPB + default 7 if BSP_PWM3_INTSEL_ET_CTRD_CMPB + choice + prompt "Interrupt generation time" + default BSP_PWM3_INT_ET_1ST + config BSP_PWM3_INT_ET_DISABLE + bool "disable PWM interrupt" + config BSP_PWM3_INT_ET_1ST + bool "generate interrupt at the first time" + config BSP_PWM3_INT_ET_2ND + bool "generate interrupt at the second time" + config BSP_PWM3_INT_ET_3RD + bool "generate interrupt at the third time" + endchoice + config BSP_PWM3_INTPRD + int + default 0 if BSP_PWM3_INT_ET_DISABLE + default 1 if BSP_PWM3_INT_ET_1ST + default 2 if BSP_PWM3_INT_ET_2ND + default 3 if BSP_PWM3_INT_ET_3RD + endif + choice + prompt "HSP Clock division" + default BSP_PWM3_HSPCLKDIV1 + config BSP_PWM3_HSPCLKDIV1 + bool "Clock Divided by 1" + config BSP_PWM3_HSPCLKDIV2 + bool "Clock Divided by 2" + config BSP_PWM3_HSPCLKDIV4 + bool "Clock Divided by 4" + endchoice + config BSP_PWM3_HSPCLKDIV + int + default 0 if BSP_PWM3_HSPCLKDIV1 + default 1 if BSP_PWM3_HSPCLKDIV2 + default 2 if BSP_PWM3_HSPCLKDIV4 + choice + prompt "Clock division" + default BSP_PWM3_CLKDIV1 + config BSP_PWM3_CLKDIV1 + bool "Clock Divided by 1" + config BSP_PWM3_CLKDIV2 + bool "Clock Divided by 2" + config BSP_PWM3_CLKDIV4 + bool "Clock Divided by 4" + endchoice + config BSP_PWM3_CLKDIV + int + default 0 if BSP_PWM3_CLKDIV1 + default 1 if BSP_PWM3_CLKDIV2 + default 2 if BSP_PWM3_CLKDIV4 + choice + default BSP_PWM3_CTR_MODE_UPDOWN + prompt "Select counter mode" + config BSP_PWM3_CTR_MODE_UPDOWN + bool "Up-down mode" + config BSP_PWM3_CTR_MODE_UP + bool "Up mode" + config BSP_PWM3_CTR_MODE_DOWN + bool "Down mode" + config BSP_PWM3_CTR_FREEZE + bool "Freezing Counter" + endchoice + config BSP_PWM3_CTRMODE + int + default 0 if BSP_PWM3_CTR_MODE_UP + default 1 if BSP_PWM3_CTR_MODE_DOWN + default 2 if BSP_PWM3_CTR_MODE_UPDOWN + default 3 if BSP_PWM3_CTR_FREEZE + choice + prompt "Register load mode" + config BSP_PWM3_CC_CTR_ZERO + bool "Load when counter == 0" + config BSP_PWM3_CC_CTR_PRD + bool "Load when counter == prd" + config BSP_PWM3_CC_CTR_ZERO_PRD + bool "load when counter ==0 or counter == prd" + config BSP_PWM3_CC_LD_DISABLE + bool "disable load" + endchoice + + config BSP_PWM3_LOADAMODE + int + default 0 if BSP_PWM3_CC_CTR_ZERO + default 1 if BSP_PWM3_CC_CTR_PRD + default 2 if BSP_PWM3_CC_CTR_ZERO_PRD + default 3 if BSP_PWM3_CC_LD_DISABLE + + config BSP_PWM3_DB + int "Dead time(ns)" + default 100 + range 0 100000 + menuconfig BSP_PWM3_ADC_TRIGGER + bool "Enable ADC trigger from PWM3" + if BSP_PWM3_ADC_TRIGGER + choice + prompt "Select soc triggering time" + default BSP_PWM3_SOCASEL_ET_CTR_ZERO + config BSP_PWM3_SOCASEL_ET_DCAEVT1SOC + bool "DCAEVT1SOC" + config BSP_PWM3_SOCASEL_ET_CTR_ZERO + bool "ctr == zero" + config BSP_PWM3_SOCASEL_ET_CTR_PRD + bool "ctr == prd" + config BSP_PWM3_SOCASEL_ET_CTR_PRDZERO + bool "ctr == prd or ctr == zero" + config BSP_PWM3_SOCASEL_ET_CTRU_CMPA + bool "ctr == compa when counting up" + config BSP_PWM3_SOCASEL_ET_CTRD_CMPA + bool "ctr == compa when counting down" + config BSP_PWM3_SOCASEL_ET_CTRU_CMPB + bool "ctr == compb when counting up" + config BSP_PWM3_SOCASEL_ET_CTRD_CMPB + bool "ctr == compb when counting down" + endchoice + + config BSP_PWM3_SOCASEL + int + default 0 if BSP_PWM3_SOCASEL_ET_DCAEVT1SOC + default 1 if BSP_PWM3_SOCASEL_ET_CTR_ZERO + default 2 if BSP_PWM3_SOCASEL_ET_CTR_PRD + default 3 if BSP_PWM3_SOCASEL_ET_CTR_PRDZERO + default 4 if BSP_PWM3_SOCASEL_ET_CTRU_CMPA + default 5 if BSP_PWM3_SOCASEL_ET_CTRD_CMPA + default 6 if BSP_PWM3_SOCASEL_ET_CTRU_CMPB + default 7 if BSP_PWM3_SOCASEL_ET_CTRD_CMPB + choice + prompt "SOCA generation time" + default BSP_PWM3_SOCA_ET_1ST + config BSP_PWM3_SOCA_ET_DISABLE + bool "disable soc generation" + config BSP_PWM3_SOCA_ET_1ST + bool "generate soc at the first time" + config BSP_PWM3_SOCA_ET_2ND + bool "generate soc at the second time" + config BSP_PWM3_SOCA_ET_3RD + bool "generate soc at the third time" + endchoice + config BSP_PWM3_SOCAPRD + int + default 0 if BSP_PWM3_SOCA_ET_DISABLE + default 1 if BSP_PWM3_SOCA_ET_1ST + default 2 if BSP_PWM3_SOCA_ET_2ND + default 3 if BSP_PWM3_SOCA_ET_3RD + endif + endmenu + endif + menuconfig BSP_USING_PWM4 + bool "Enable ePWM4" + default n + if BSP_USING_PWM4 + menu "Basic settings for PWM4" + config BSP_PWM4_INIT_PERIOD + int "Initial period for PWM4(ns)" + default 10000 + config BSP_PWM4_INIT_PULSE + int "Initial pulse for PWM4(ns)" + default 1000 + endmenu + menu "Advanced Settings for PWM4" + menuconfig BSP_PWM4_PHASE_ENABLE + bool "Enable phase" + default n + if BSP_PWM4_PHASE_ENABLE + choice + prompt "Select master or slave" + default BSP_PWM4_SLAVE + config BSP_PWM4_MASTER + bool "Master" + config BSP_PWM4_SLAVE + bool "Slave" + endchoice + if BSP_PWM4_MASTER + config BSP_PWM4_PHASE + int + default 0 + endif + if BSP_PWM4_SLAVE + config BSP_PWM4_PHASE + int "Phase, 0~360" + range 0 360 + default 0 + help + the phase for PWM4 module + endif + endif + + menuconfig BSP_PWM4_IT_ENABLE + bool "Enable interrupt service" + default n + if BSP_PWM4_IT_ENABLE + choice + prompt "Select interrupt time" + default BSP_PWM4_INTSEL_ET_CTR_ZERO + config BSP_PWM4_INTSEL_ET_DCAEVT1SOC + bool "DCAEVT1SOC" + config BSP_PWM4_INTSEL_ET_CTR_ZERO + bool "ctr == zero" + config BSP_PWM4_INTSEL_ET_CTR_PRD + bool "ctr == prd" + config BSP_PWM4_INTSEL_ET_CTR_PRDZERO + bool "ctr == prd or ctr == zero" + config BSP_PWM4_INTSEL_ET_CTRU_CMPA + bool "ctr == compa when counting up" + config BSP_PWM4_INTSEL_ET_CTRD_CMPA + bool "ctr == compa when counting down" + config BSP_PWM4_INTSEL_ET_CTRU_CMPB + bool "ctr == compb when counting up" + config BSP_PWM4_INTSEL_ET_CTRD_CMPB + bool "ctr == compb when counting down" + endchoice + + config BSP_PWM4_INTSEL + int + default 0 if BSP_PWM4_INTSEL_ET_DCAEVT1SOC + default 1 if BSP_PWM4_INTSEL_ET_CTR_ZERO + default 2 if BSP_PWM4_INTSEL_ET_CTR_PRD + default 3 if BSP_PWM4_INTSEL_ET_CTR_PRDZERO + default 4 if BSP_PWM4_INTSEL_ET_CTRU_CMPA + default 5 if BSP_PWM4_INTSEL_ET_CTRD_CMPA + default 6 if BSP_PWM4_INTSEL_ET_CTRU_CMPB + default 7 if BSP_PWM4_INTSEL_ET_CTRD_CMPB + choice + prompt "Interrupt generation time" + default BSP_PWM4_INT_ET_1ST + config BSP_PWM4_INT_ET_DISABLE + bool "disable PWM interrupt" + config BSP_PWM4_INT_ET_1ST + bool "generate interrupt at the first time" + config BSP_PWM4_INT_ET_2ND + bool "generate interrupt at the second time" + config BSP_PWM4_INT_ET_3RD + bool "generate interrupt at the third time" + endchoice + config BSP_PWM4_INTPRD + int + default 0 if BSP_PWM4_INT_ET_DISABLE + default 1 if BSP_PWM4_INT_ET_1ST + default 2 if BSP_PWM4_INT_ET_2ND + default 3 if BSP_PWM4_INT_ET_3RD + endif + choice + prompt "HSP Clock division" + default BSP_PWM4_HSPCLKDIV1 + config BSP_PWM4_HSPCLKDIV1 + bool "Clock Divided by 1" + config BSP_PWM4_HSPCLKDIV2 + bool "Clock Divided by 2" + config BSP_PWM4_HSPCLKDIV4 + bool "Clock Divided by 4" + endchoice + config BSP_PWM4_HSPCLKDIV + int + default 0 if BSP_PWM4_HSPCLKDIV1 + default 1 if BSP_PWM4_HSPCLKDIV2 + default 2 if BSP_PWM4_HSPCLKDIV4 + choice + prompt "Clock division" + default BSP_PWM4_CLKDIV1 + config BSP_PWM4_CLKDIV1 + bool "Clock Divided by 1" + config BSP_PWM4_CLKDIV2 + bool "Clock Divided by 2" + config BSP_PWM4_CLKDIV4 + bool "Clock Divided by 4" + endchoice + config BSP_PWM4_CLKDIV + int + default 0 if BSP_PWM4_CLKDIV1 + default 1 if BSP_PWM4_CLKDIV2 + default 2 if BSP_PWM4_CLKDIV4 + choice + default BSP_PWM4_CTR_MODE_UPDOWN + prompt "Select counter mode" + config BSP_PWM4_CTR_MODE_UPDOWN + bool "Up-down mode" + config BSP_PWM4_CTR_MODE_UP + bool "Up mode" + config BSP_PWM4_CTR_MODE_DOWN + bool "Down mode" + config BSP_PWM4_CTR_FREEZE + bool "Freezing Counter" + endchoice + config BSP_PWM4_CTRMODE + int + default 0 if BSP_PWM4_CTR_MODE_UP + default 1 if BSP_PWM4_CTR_MODE_DOWN + default 2 if BSP_PWM4_CTR_MODE_UPDOWN + default 3 if BSP_PWM4_CTR_FREEZE + choice + prompt "Register load mode" + config BSP_PWM4_CC_CTR_ZERO + bool "Load when counter == 0" + config BSP_PWM4_CC_CTR_PRD + bool "Load when counter == prd" + config BSP_PWM4_CC_CTR_ZERO_PRD + bool "load when counter ==0 or counter == prd" + config BSP_PWM4_CC_LD_DISABLE + bool "disable load" + endchoice + + config BSP_PWM4_LOADAMODE + int + default 0 if BSP_PWM4_CC_CTR_ZERO + default 1 if BSP_PWM4_CC_CTR_PRD + default 2 if BSP_PWM4_CC_CTR_ZERO_PRD + default 3 if BSP_PWM4_CC_LD_DISABLE + + config BSP_PWM4_DB + int "Dead time(ns)" + default 100 + range 0 100000 + menuconfig BSP_PWM4_ADC_TRIGGER + bool "Enable ADC trigger from PWM4" + if BSP_PWM4_ADC_TRIGGER + choice + prompt "Select soc triggering time" + default BSP_PWM4_SOCASEL_ET_CTR_ZERO + config BSP_PWM4_SOCASEL_ET_DCAEVT1SOC + bool "DCAEVT1SOC" + config BSP_PWM4_SOCASEL_ET_CTR_ZERO + bool "ctr == zero" + config BSP_PWM4_SOCASEL_ET_CTR_PRD + bool "ctr == prd" + config BSP_PWM4_SOCASEL_ET_CTR_PRDZERO + bool "ctr == prd or ctr == zero" + config BSP_PWM4_SOCASEL_ET_CTRU_CMPA + bool "ctr == compa when counting up" + config BSP_PWM4_SOCASEL_ET_CTRD_CMPA + bool "ctr == compa when counting down" + config BSP_PWM4_SOCASEL_ET_CTRU_CMPB + bool "ctr == compb when counting up" + config BSP_PWM4_SOCASEL_ET_CTRD_CMPB + bool "ctr == compb when counting down" + endchoice + + config BSP_PWM4_SOCASEL + int + default 0 if BSP_PWM4_SOCASEL_ET_DCAEVT1SOC + default 1 if BSP_PWM4_SOCASEL_ET_CTR_ZERO + default 2 if BSP_PWM4_SOCASEL_ET_CTR_PRD + default 3 if BSP_PWM4_SOCASEL_ET_CTR_PRDZERO + default 4 if BSP_PWM4_SOCASEL_ET_CTRU_CMPA + default 5 if BSP_PWM4_SOCASEL_ET_CTRD_CMPA + default 6 if BSP_PWM4_SOCASEL_ET_CTRU_CMPB + default 7 if BSP_PWM4_SOCASEL_ET_CTRD_CMPB + choice + prompt "SOCA generation time" + default BSP_PWM4_SOCA_ET_1ST + config BSP_PWM4_SOCA_ET_DISABLE + bool "disable soc generation" + config BSP_PWM4_SOCA_ET_1ST + bool "generate soc at the first time" + config BSP_PWM4_SOCA_ET_2ND + bool "generate soc at the second time" + config BSP_PWM4_SOCA_ET_3RD + bool "generate soc at the third time" + endchoice + config BSP_PWM4_SOCAPRD + int + default 0 if BSP_PWM4_SOCA_ET_DISABLE + default 1 if BSP_PWM4_SOCA_ET_1ST + default 2 if BSP_PWM4_SOCA_ET_2ND + default 3 if BSP_PWM4_SOCA_ET_3RD + endif + endmenu + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC1 + bool "Enable ADC1" + default n + if BSP_USING_ADC1 + choice + prompt "Select resolution" + default BSP_ADC_USING_12BIT + + config BSP_ADC_USING_12BIT + bool "ADC Using 12 bit resolution" + + config BSP_ADC_USING_16BIT + bool "ADC Using 16 bit resolution" + endchoice + endif + menuconfig BSP_USING_ADC2 + bool "Enable ADC2" + default n + if BSP_USING_ADC2 + choice + prompt "Select resolution" + default BSP_ADC_USING_12BIT + + config BSP_ADC_USING_12BIT + bool "ADC Using 12 bit resolution" + + config BSP_ADC_USING_16BIT + bool "ADC Using 16 bit resolution" + endchoice + endif + menuconfig BSP_USING_ADC3 + bool "Enable ADC3" + default n + if BSP_USING_ADC3 + choice + prompt "Select resolution" + default BSP_ADC_USING_12BIT + + config BSP_ADC_USING_12BIT + bool "ADC Using 12 bit resolution" + + config BSP_ADC_USING_16BIT + bool "ADC Using 16 bit resolution" + endchoice + endif + endif + + menuconfig BSP_USING_ONCHIP_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_ONCHIP_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LSE + + config BSP_RTC_USING_LSE + bool "RTC USING LSE" + + config BSP_RTC_USING_LSI + bool "RTC USING LSI" + endchoice + endif + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + config BSP_USING_SDIO + bool "Enable SDIO" + select RT_USING_SDIO + select RT_USING_DFS + default n + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN + if BSP_USING_CAN + config BSP_USING_CAN1 + bool "using CAN1" + default n + endif + + config BSP_USING_USBD + bool "Enable USB device" + select RT_USING_USB_DEVICE + default n + if BSP_USING_USBD + config BSP_USB_CONNECT_PIN + int "USB connect pin" + default 67 + + config BSP_USB_PULL_UP_STATUS + int "USB PULL UP STATUS" + default 0 + endif +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/ti/c28x/tms320f28379d/board/board.c b/bsp/ti/c28x/tms320f28379d/board/board.c new file mode 100644 index 0000000000..c391a2589e --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/board/board.c @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2018-09-02 xuzhuoyi modify for TMS320F28379D version + * 2022-06-21 guyunjie fix bugs in trap_rtosint and enable interrupt nesting + * 2022-08-21 yuqi adding onboard devices initialization code + */ +#include +#include "board.h" +#include "drv_sci.h" +#include "drv_gpio.h" +#include "F28x_Project.h" + +#ifndef RT_USING_SMP +extern volatile rt_uint8_t rt_interrupt_nest; +#endif + +extern rt_uint32_t rt_thread_switch_interrupt_flag; + +extern interrupt void RTOSINT_Handler(); +void trap_rtosint() +{ + if(rt_thread_switch_interrupt_flag) + { + /* only do pendsv at the end of the last level of interrupt nesting, + * so that threads do not preempt any isrs. */ + if(rt_interrupt_nest == 1) + { + /* rt_interrupt_leave_hook is called before rt_interrupt_nest -- + * in rt_interrupt_leave. We need to do this manually here to indicate + * that all isrs have been cleared before we switch to thread. */ + rt_interrupt_nest --; + asm(" trap #16"); + /* increment rt_interrupt_nest to compensate for the previous decrement. */ + rt_interrupt_nest ++; + } + } +} + +/** + * This is the timer interrupt service routine. + * + */ +interrupt void cpu_timer2_isr(void) +{ + CpuTimer2Regs.TCR.all = 0xC000; + + ALLOW_ISR_PREEMPT(); + + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + /* leave interrupt */ + rt_interrupt_leave(); +} + +extern interrupt void XINT1_Handler(void); +extern interrupt void XINT2_Handler(void); +/** + * This function will initial TMS320F28379D board. + */ +void rt_hw_board_init() +{ + /* Configure the system clock @ 84 Mhz */ + InitSysCtrl(); + + DINT; + InitPieCtrl(); + + IER = 0x0000; + IFR = 0x0000; + + InitPieVectTable(); + +#ifdef _FLASH + memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (Uint32)&RamfuncsLoadSize); + InitFlash(); +#endif + EALLOW; // This is needed to write to EALLOW protected registers + PieVectTable.TIMER2_INT = &cpu_timer2_isr; + PieVectTable.RTOS_INT = &RTOSINT_Handler; + +#ifdef BSP_USING_XINT1 + PieVectTable.XINT1_INT = &XINT1_Handler; +#endif +#ifdef BSP_USING_XINT2 + PieVectTable.XINT2_INT = &XINT2_Handler; +#endif +#ifdef BSP_USING_XINT3 + PieVectTable.XINT3_INT = &XINT3_Handler; +#endif +#ifdef BSP_USING_XINT4 + PieVectTable.XINT4_INT = &XINT4_Handler; +#endif +#ifdef BSP_USING_XINT5 + PieVectTable.XINT5_INT = &XINT5_Handler; +#endif + EDIS; + + InitCpuTimers(); + ConfigCpuTimer(&CpuTimer2, 200, 1000000 / RT_TICK_PER_SECOND); + CpuTimer2Regs.TCR.all = 0x4000; + IER |= M_INT14; + IER |= M_INT1; + +#ifdef RT_USING_HEAP + rt_system_heap_init(&__ebss_end, &(__heap_end)); +#endif + +#ifdef RT_USING_SERIAL + rt_hw_sci_init(); +#endif + +#ifdef RT_USING_PIN + rt_hw_pin_init(); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + + rt_interrupt_leave_sethook((void (*)(void))trap_rtosint); +} + +int _args_main() +{ + /* _args_main is the entry point called by _c_int00. We define it + * here to override the one defined by the compiler in args_main.c */ + + extern int rtthread_startup(); + + /* startup RT-Thread RTOS */ + rtthread_startup(); + /* never reach here*/ + return 0; +} diff --git a/bsp/ti/c28x/tms320f28379d/board/board.h b/bsp/ti/c28x/tms320f28379d/board/board.h new file mode 100644 index 0000000000..1cf7ac7134 --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/board/board.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2009-09-22 Bernard add board.h to this bsp + * 2018-09-02 xuzhuoyi modify for TMS320F28379D version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + + +extern int __ebss_end; +extern int __heap_end; + +extern void rt_hw_board_init(void); + +#endif + diff --git a/bsp/ti/c28x/tms320f28379d/figures/build.png b/bsp/ti/c28x/tms320f28379d/figures/build.png new file mode 100644 index 0000000000..4f6db2913d Binary files /dev/null and b/bsp/ti/c28x/tms320f28379d/figures/build.png differ diff --git a/bsp/ti/c28x/tms320f28379d/figures/debug_as.png b/bsp/ti/c28x/tms320f28379d/figures/debug_as.png new file mode 100644 index 0000000000..6a2abb3119 Binary files /dev/null and b/bsp/ti/c28x/tms320f28379d/figures/debug_as.png differ diff --git a/bsp/ti/c28x/tms320f28379d/figures/import.png b/bsp/ti/c28x/tms320f28379d/figures/import.png new file mode 100644 index 0000000000..db7c314b67 Binary files /dev/null and b/bsp/ti/c28x/tms320f28379d/figures/import.png differ diff --git a/bsp/ti/c28x/tms320f28379d/figures/import_dia.png b/bsp/ti/c28x/tms320f28379d/figures/import_dia.png new file mode 100644 index 0000000000..8098424824 Binary files /dev/null and b/bsp/ti/c28x/tms320f28379d/figures/import_dia.png differ diff --git a/bsp/ti/c28x/tms320f28379d/figures/launch-28379d.png b/bsp/ti/c28x/tms320f28379d/figures/launch-28379d.png new file mode 100644 index 0000000000..6db1ebdae0 Binary files /dev/null and b/bsp/ti/c28x/tms320f28379d/figures/launch-28379d.png differ diff --git a/bsp/ti/c28x/tms320f28379d/figures/launching.png b/bsp/ti/c28x/tms320f28379d/figures/launching.png new file mode 100644 index 0000000000..832c6687ce Binary files /dev/null and b/bsp/ti/c28x/tms320f28379d/figures/launching.png differ diff --git a/bsp/ti/c28x/tms320f28379d/rtconfig.h b/bsp/ti/c28x/tms320f28379d/rtconfig.h new file mode 100644 index 0000000000..12617588d5 --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/rtconfig.h @@ -0,0 +1,201 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Configuration */ + +#define SOC_TMS320F28X + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_8 +#define RT_THREAD_PRIORITY_MAX 8 +#define RT_TICK_PER_SECOND 100 +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 + +/* kservice optimization */ + +#define RT_DEBUG +#define RT_DEBUG_COLOR + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "scia" +#define RT_VER_NUM 0x50000 +#define ARCH_TIDSP +#define ARCH_TIDSP_C28X +#define ARCH_CPU_STACK_GROWS_UPWARD + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 4 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 4 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +#define RT_USING_ADC +#define RT_USING_PWM + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + + +/* Utilities */ + + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* PainterEngine: A cross-platform graphics application framework written in C language */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Hardware Drivers Config */ + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 +#define BSP_USING_ADC +#define BSP_USING_ADC1 +#define BSP_ADC_USING_12BIT +#define BSP_USING_ADC2 +#define BSP_USING_ADC3 + +/* Board extended module Drivers */ + +#include "rtconfig_project.h" + +#endif diff --git a/bsp/ti/c28x/tms320f28379d/rtconfig_project.h b/bsp/ti/c28x/tms320f28379d/rtconfig_project.h new file mode 100644 index 0000000000..fb6a3dffbb --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/rtconfig_project.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-03-27 xuzhuoyi the first version + * 2022-08-22 guyunjie remove data types other than 8bit for compatibility with libc + */ + +#ifndef __RTCONFIG_PROJECT_H__ +#define __RTCONFIG_PROJECT_H__ + +/* C28X does not support 8bit data type by hardward (char = 16bit) so + * 8bit data types are not defined in its standard libs. We define them + * here. Be careful that the 8bit is actually 16bit. */ +#define UINT8_MAX 0xff /**< Maximum number of UINT8 */ +typedef signed char int8_t; /**< 8bit integer type */ +typedef unsigned char uint8_t; /**< 8bit unsigned integer type */ + +/* C28X automatically disable interrupt in interrupt service routine. + * We need to enable manually to allow for interrupt nesting by calling + * this macro at the start of preemptible interrupt service routines*/ +#define ALLOW_ISR_PREEMPT() __asm(" CLRC INTM") + +#endif diff --git a/bsp/ti/c28x/tms320f28379d/targetConfigs/TMS320F28379D.ccxml b/bsp/ti/c28x/tms320f28379d/targetConfigs/TMS320F28379D.ccxml new file mode 100644 index 0000000000..42eb492f1f --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/targetConfigs/TMS320F28379D.ccxml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/ti/c28x/tms320f28379d/targetConfigs/readme.txt b/bsp/ti/c28x/tms320f28379d/targetConfigs/readme.txt new file mode 100644 index 0000000000..d783fef4d6 --- /dev/null +++ b/bsp/ti/c28x/tms320f28379d/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file -- cgit v1.3.1