From 8d8dc96b67eee53af2841a8819364d52fbec39cb Mon Sep 17 00:00:00 2001 From: GUI <39894654+GuEe-GUI@users.noreply.github.com> Date: Sat, 17 Oct 2026 09:44:26 +0800 Subject: [ARCH/RISC-V] Next RISC-V (#10320) * [libcpu][risc-v] Refactor the RISC-V architecture port Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration. - use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection - unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling - add PLIC, CLIC, ACLINT, APLIC and IMSIC support - map physical hart IDs to contiguous logical CPU IDs - add T-Head vendor overrides while preserving legacy ports - migrate qemu-virt64-riscv with RV32 and RV64 support - update clock_time, MM, LWP, OFW, PCI and Rust integration Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON. Signed-off-by: GuEe-GUI <2991707448@qq.com> * [libcpu][risc-v] skip disabled CPU nodes in early FDT walk Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child without checking status, so disabled cores still joined hart registration and MMU capability probing. Skip nodes that are not okay/ok via rt_fdt_device_is_available() before reading reg or mmu-type. Signed-off-by: seteiro * [libcpu][risc-v] Fix per-CPU page table mapping - reuse existing non-leaf page table entries when mapping per-CPU areas - reject leaf entry conflicts instead of overwriting mappings Signed-off-by: GuEe-GUI <2991707448@qq.com> --------- Signed-off-by: GuEe-GUI <2991707448@qq.com> Signed-off-by: seteiro Co-authored-by: seteiro --- components/drivers/clock_time/SConscript | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'components/drivers/clock_time/SConscript') diff --git a/components/drivers/clock_time/SConscript b/components/drivers/clock_time/SConscript index 111449276a..386ce7135d 100644 --- a/components/drivers/clock_time/SConscript +++ b/components/drivers/clock_time/SConscript @@ -25,7 +25,12 @@ if os.path.isdir(arch_dir): arch_list = os.listdir(arch_dir) if rtconfig.ARCH in arch_list: cpu_dir = os.path.join(arch_dir, rtconfig.ARCH, rtconfig.CPU) - if os.path.exists(cpu_dir): + if rtconfig.ARCH == 'risc-v': + if GetDepend('RT_USING_RISCV_NEW_COMMON'): + src += Glob("arch/risc-v/*.c") + elif os.path.exists(cpu_dir): + src += Glob("arch/%s/%s/*.c" % (rtconfig.ARCH, rtconfig.CPU)) + elif os.path.exists(cpu_dir): src += Glob("arch/%s/%s/*.c" % (rtconfig.ARCH, rtconfig.CPU)) else: src += Glob("arch/%s/*.c" % rtconfig.ARCH) -- cgit v1.3.1