From f51bce3fedcb5aa64514a4259068d85e8c534ab5 Mon Sep 17 00:00:00 2001 From: Grissiom Date: Fri, 24 May 2013 10:04:51 +0800 Subject: add rm48x50 bsp and libcpu We currently only support building with CCS and SCons is not using. bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file. You may need to regenerate the source file as you like, providing that: 1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The channel 5 in enabled and connected to IRQ. 2, RTI driver is enabled and compare3 source is selected to counter1 and the compare3 will generate tick in the period of 10ms. This value is coresponding with RT_TICK_PER_SECOND in rtconfig.h. In CCS, you need to create a new CCS project and create link folders pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember to add the include path to the Build Properties. --- include/rtthread.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/rtthread.h') diff --git a/include/rtthread.h b/include/rtthread.h index 4b81464f18..cc1d90fe91 100644 --- a/include/rtthread.h +++ b/include/rtthread.h @@ -19,7 +19,7 @@ #ifndef __RT_THREAD_H__ #define __RT_THREAD_H__ - + #include #include #include #include -- cgit v1.3.1