From 43d19a8b78227d042c8faeb9848b7f93e887d906 Mon Sep 17 00:00:00 2001 From: guozhanxin Date: Thu, 1 Jul 2021 01:30:54 +0800 Subject: [bsp] stm32h750-artpi-h750/stm32f412-st-nucleo support armclang. --- libcpu/arm/cortex-m7/SConscript | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'libcpu/arm') diff --git a/libcpu/arm/cortex-m7/SConscript b/libcpu/arm/cortex-m7/SConscript index 28af7ba651..717823339d 100644 --- a/libcpu/arm/cortex-m7/SConscript +++ b/libcpu/arm/cortex-m7/SConscript @@ -8,7 +8,7 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') CPPPATH = [cwd] -if rtconfig.PLATFORM == 'armcc': +if rtconfig.PLATFORM == 'armcc' or rtconfig.PLATFORM == 'armclang': src += Glob('*_rvds.S') if rtconfig.PLATFORM == 'gcc': -- cgit v1.3.1 From 7d3bac8b6ed7f7747d37c9d9e7919164e13ef305 Mon Sep 17 00:00:00 2001 From: Bernard Xiong Date: Fri, 2 Jul 2021 15:07:21 +0800 Subject: [libcpu] remove gtimer/pmu from cortex-a --- libcpu/arm/cortex-a/SConscript | 3 - libcpu/arm/cortex-a/armv7.h | 6 ++ libcpu/arm/cortex-a/gtimer.c | 179 ----------------------------------------- libcpu/arm/cortex-a/gtimer.h | 27 ------- libcpu/arm/cortex-a/pmu.c | 20 ----- libcpu/arm/cortex-a/pmu.h | 159 ------------------------------------ 6 files changed, 6 insertions(+), 388 deletions(-) delete mode 100644 libcpu/arm/cortex-a/gtimer.c delete mode 100644 libcpu/arm/cortex-a/gtimer.h delete mode 100644 libcpu/arm/cortex-a/pmu.c delete mode 100644 libcpu/arm/cortex-a/pmu.h (limited to 'libcpu/arm') diff --git a/libcpu/arm/cortex-a/SConscript b/libcpu/arm/cortex-a/SConscript index a9fe6f0bc9..10977eb3ec 100644 --- a/libcpu/arm/cortex-a/SConscript +++ b/libcpu/arm/cortex-a/SConscript @@ -8,11 +8,8 @@ cwd = GetCurrentDir() src = Split(''' cache.c cpu.c -gtimer.c mmu.c -pmu.c stack.c - ''') CPPPATH = [cwd] diff --git a/libcpu/arm/cortex-a/armv7.h b/libcpu/arm/cortex-a/armv7.h index f284bb5255..325d0ed0ae 100644 --- a/libcpu/arm/cortex-a/armv7.h +++ b/libcpu/arm/cortex-a/armv7.h @@ -69,4 +69,10 @@ struct rt_hw_stack #define E_Bit (1<<9) #define J_Bit (1<<24) +#define PABT_EXCEPTION 0x1 +#define DABT_EXCEPTION 0x2 +#define UND_EXCEPTION 0x3 +#define SWI_EXCEPTION 0x4 +#define RESV_EXCEPTION 0xF + #endif diff --git a/libcpu/arm/cortex-a/gtimer.c b/libcpu/arm/cortex-a/gtimer.c deleted file mode 100644 index b35acc6e6f..0000000000 --- a/libcpu/arm/cortex-a/gtimer.c +++ /dev/null @@ -1,179 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-03-30 huijie.feng first version - */ - -#include "cp15.h" -#include - -/** Set CNTFRQ - * This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ). - * @param value: CNTFRQ Register value to set - */ -static inline void __set_cntfrq(rt_uint32_t value) -{ - __set_cp(15, 0, value, 14, 0, 0); -} - -/** Get CNTFRQ - * This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ). - * return CNTFRQ Register value - */ -static inline rt_uint32_t __get_cntfrq(void) -{ - rt_uint32_t result; - __get_cp(15, 0, result, 14, 0 , 0); - return result; -} - -/** Set CNTP_TVAL - * This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL). - * param value: CNTP_TVAL Register value to set - */ -static inline void __set_cntp_tval(rt_uint32_t value) -{ - __set_cp(15, 0, value, 14, 2, 0); -} - -/** Get CNTP_TVAL - * This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL). - * return CNTP_TVAL Register value - */ -static inline rt_uint32_t __get_cntp_tval(void) -{ - rt_uint32_t result; - __get_cp(15, 0, result, 14, 2, 0); - return result; -} - -/** Get CNTPCT - * This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT). - * return CNTPCT Register value - */ -static inline rt_uint64_t __get_cntpct(void) -{ - rt_uint64_t result; - __get_cp64(15, 0, result, 14); - return result; -} - -/** Set CNTP_CVAL - * This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). - * param value: CNTP_CVAL Register value to set -*/ -static inline void __set_cntp_cval(rt_uint64_t value) -{ - __set_cp64(15, 2, value, 14); -} - -/** Get CNTP_CVAL - * This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL). - * return CNTP_CVAL Register value - */ -static inline rt_uint64_t __get_cntp_cval(void) -{ - rt_uint64_t result; - __get_cp64(15, 2, result, 14); - return result; -} - -/** Set CNTP_CTL - * This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL). - * param value: CNTP_CTL Register value to set - */ -static inline void __set_cntp_ctl(uint32_t value) -{ - __set_cp(15, 0, value, 14, 2, 1); -} - -/** Get CNTP_CTL register - * return CNTP_CTL Register value - */ -static inline rt_uint32_t __get_cntp_ctl(void) -{ - rt_uint32_t result; - __get_cp(15, 0, result, 14, 2, 1); - return result; -} - -/** Configures the frequency the timer shall run at. - * param value The timer frequency in Hz. - */ -void gtimer_set_counter_frequency(rt_uint32_t value) -{ - __set_cntfrq(value); - __asm__ volatile ("isb 0xF":::"memory"); -} - -/** Get the frequency the timer shall run at. - * return timer frequency in Hz. - */ -rt_uint32_t gtimer_get_counter_frequency(void) -{ - return(__get_cntfrq()); -} - -/** Sets the reset value of the timer. - * param value: The value the timer is loaded with. - */ -void gtimer_set_load_value(rt_uint32_t value) -{ - __set_cntp_tval(value); - __asm__ volatile ("isb 0xF":::"memory"); -} - -/** Get the current counter value. - * return Current counter value. - */ -rt_uint32_t gtimer_get_current_value(void) -{ - return(__get_cntp_tval()); -} - -/** Get the current physical counter value. - * return Current physical counter value. - */ -rt_uint64_t gtimer_get_current_physical_value(void) -{ - return(__get_cntpct()); -} - -/** Set the physical compare value. - * param value: New physical timer compare value. - */ -void gtimer_set_physical_compare_value(rt_uint64_t value) -{ - __set_cntp_cval(value); - __asm__ volatile ("isb 0xF":::"memory"); -} - -/** Get the physical compare value. - * return Physical compare value. - */ -rt_uint64_t gtimer_get_physical_compare_value(void) -{ - return(__get_cntp_cval()); -} - -/** Configure the timer by setting the control value. - * param value: New timer control value. - */ -void gtimer_set_control(rt_uint32_t value) -{ - __set_cntp_ctl(value); - __asm__ volatile ("isb 0xF":::"memory"); -} - -/** Get the control value. - * return Control value. - */ -rt_uint32_t gtimer_get_control(void) -{ - return(__get_cntp_ctl()); -} - diff --git a/libcpu/arm/cortex-a/gtimer.h b/libcpu/arm/cortex-a/gtimer.h deleted file mode 100644 index ec5d54127e..0000000000 --- a/libcpu/arm/cortex-a/gtimer.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2021-03-30 huijie.feng first version - */ - -#ifndef __GTIMER_H__ -#define __GTIMER_H__ - -#include - -void gtimer_set_counter_frequency(rt_uint32_t value); -rt_uint32_t gtimer_get_counter_frequency(void); -void gtimer_set_load_value(rt_uint32_t value); -rt_uint32_t gtimer_get_current_value(void); -rt_uint64_t gtimer_get_current_physical_value(void); -void gtimer_set_physical_compare_value(rt_uint64_t value); -rt_uint64_t gtimer_get_physical_compare_value(void); -void gtimer_set_control(rt_uint32_t value); -rt_uint32_t gtimer_get_control(void); - -#endif - diff --git a/libcpu/arm/cortex-a/pmu.c b/libcpu/arm/cortex-a/pmu.c deleted file mode 100644 index 2b9165cc8b..0000000000 --- a/libcpu/arm/cortex-a/pmu.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -#include -#include "pmu.h" - -void rt_hw_pmu_dump_feature(void) -{ - unsigned long reg; - - reg = rt_hw_pmu_get_control(); - rt_kprintf("ARM PMU Implementor: %c, ID code: %02x, %d counters\n", - reg >> 24, (reg >> 16) & 0xff, (reg >> 11) & 0x1f); - RT_ASSERT(ARM_PMU_CNTER_NR == ((reg >> 11) & 0x1f)); -} diff --git a/libcpu/arm/cortex-a/pmu.h b/libcpu/arm/cortex-a/pmu.h deleted file mode 100644 index 64a74b5d39..0000000000 --- a/libcpu/arm/cortex-a/pmu.h +++ /dev/null @@ -1,159 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - */ -#ifndef __PMU_H__ -#define __PMU_H__ - -#include "board.h" - -/* Number of counters */ -#define ARM_PMU_CNTER_NR 4 - -enum rt_hw_pmu_event_type { - ARM_PMU_EVENT_PMNC_SW_INCR = 0x00, - ARM_PMU_EVENT_L1_ICACHE_REFILL = 0x01, - ARM_PMU_EVENT_ITLB_REFILL = 0x02, - ARM_PMU_EVENT_L1_DCACHE_REFILL = 0x03, - ARM_PMU_EVENT_L1_DCACHE_ACCESS = 0x04, - ARM_PMU_EVENT_DTLB_REFILL = 0x05, - ARM_PMU_EVENT_MEM_READ = 0x06, - ARM_PMU_EVENT_MEM_WRITE = 0x07, - ARM_PMU_EVENT_INSTR_EXECUTED = 0x08, - ARM_PMU_EVENT_EXC_TAKEN = 0x09, - ARM_PMU_EVENT_EXC_EXECUTED = 0x0A, - ARM_PMU_EVENT_CID_WRITE = 0x0B, -}; - -/* Enable bit */ -#define ARM_PMU_PMCR_E (0x01 << 0) -/* Event counter reset */ -#define ARM_PMU_PMCR_P (0x01 << 1) -/* Cycle counter reset */ -#define ARM_PMU_PMCR_C (0x01 << 2) -/* Cycle counter divider */ -#define ARM_PMU_PMCR_D (0x01 << 3) - -#ifdef __GNUC__ -rt_inline void rt_hw_pmu_enable_cnt(int divide64) -{ - unsigned long pmcr; - unsigned long pmcntenset; - - asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); - pmcr |= ARM_PMU_PMCR_E | ARM_PMU_PMCR_P | ARM_PMU_PMCR_C; - if (divide64) - pmcr |= ARM_PMU_PMCR_D; - else - pmcr &= ~ARM_PMU_PMCR_D; - asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); - - /* enable all the counters */ - pmcntenset = ~0; - asm volatile ("mcr p15, 0, %0, c9, c12, 1" :: "r"(pmcntenset)); - /* clear overflows(just in case) */ - asm volatile ("mcr p15, 0, %0, c9, c12, 3" :: "r"(pmcntenset)); -} - -rt_inline unsigned long rt_hw_pmu_get_control(void) -{ - unsigned long pmcr; - asm ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); - return pmcr; -} - -rt_inline unsigned long rt_hw_pmu_get_ceid(void) -{ - unsigned long reg; - /* only PMCEID0 is supported, PMCEID1 is RAZ. */ - asm ("mrc p15, 0, %0, c9, c12, 6" : "=r"(reg)); - return reg; -} - -rt_inline unsigned long rt_hw_pmu_get_cnten(void) -{ - unsigned long pmcnt; - asm ("mrc p15, 0, %0, c9, c12, 1" : "=r"(pmcnt)); - return pmcnt; -} - -rt_inline void rt_hw_pmu_reset_cycle(void) -{ - unsigned long pmcr; - - asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); - pmcr |= ARM_PMU_PMCR_C; - asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); - asm volatile ("isb"); -} - -rt_inline void rt_hw_pmu_reset_event(void) -{ - unsigned long pmcr; - - asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(pmcr)); - pmcr |= ARM_PMU_PMCR_P; - asm volatile ("mcr p15, 0, %0, c9, c12, 0" :: "r"(pmcr)); - asm volatile ("isb"); -} - -rt_inline unsigned long rt_hw_pmu_get_cycle(void) -{ - unsigned long cyc; - asm volatile ("isb"); - asm volatile ("mrc p15, 0, %0, c9, c13, 0" : "=r"(cyc)); - return cyc; -} - -rt_inline void rt_hw_pmu_select_counter(int idx) -{ - RT_ASSERT(idx < ARM_PMU_CNTER_NR); - - asm volatile ("mcr p15, 0, %0, c9, c12, 5" : : "r"(idx)); - /* Linux add an isb here, don't know why here. */ - asm volatile ("isb"); -} - -rt_inline void rt_hw_pmu_select_event(int idx, - enum rt_hw_pmu_event_type eve) -{ - RT_ASSERT(idx < ARM_PMU_CNTER_NR); - - rt_hw_pmu_select_counter(idx); - asm volatile ("mcr p15, 0, %0, c9, c13, 1" : : "r"(eve)); -} - -rt_inline unsigned long rt_hw_pmu_read_counter(int idx) -{ - unsigned long reg; - - rt_hw_pmu_select_counter(idx); - asm volatile ("isb"); - asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r"(reg)); - return reg; -} - -rt_inline unsigned long rt_hw_pmu_get_ovsr(void) -{ - unsigned long reg; - asm volatile ("isb"); - asm ("mrc p15, 0, %0, c9, c12, 3" : "=r"(reg)); - return reg; -} - -rt_inline void rt_hw_pmu_clear_ovsr(unsigned long reg) -{ - asm ("mcr p15, 0, %0, c9, c12, 3" : : "r"(reg)); - asm volatile ("isb"); -} - -#endif - -void rt_hw_pmu_dump_feature(void); - -#endif /* end of include guard: __PMU_H__ */ - -- cgit v1.3.1 From a6060a41df79353a642e9a68f0af95a2c96b49bb Mon Sep 17 00:00:00 2001 From: wanghaijing Date: Sat, 3 Jul 2021 10:19:29 +0800 Subject: Adjust the stack_top to bss --- libcpu/arm/cortex-a/start_gcc.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'libcpu/arm') diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S index bd4bc84604..8fcf6abd2a 100644 --- a/libcpu/arm/cortex-a/start_gcc.S +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -42,7 +42,7 @@ #define SUB_ISR_Stack_Size (SUB_UND_Stack_Size + SUB_SVC_Stack_Size + SUB_ABT_Stack_Size + \ SUB_RT_FIQ_STACK_PGSZ + SUB_RT_IRQ_STACK_PGSZ) -.section .data.share.isr +.section .bss.share.isr /* stack */ .globl stack_start .globl stack_top -- cgit v1.3.1 From da701d6b3a7b28d7dd2aca4897a902476b1581e4 Mon Sep 17 00:00:00 2001 From: fenghuijie Date: Sat, 3 Jul 2021 17:34:45 +0800 Subject: 添加dcache invalidate/dcache clean&invalidate接口 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- libcpu/arm/cortex-a/cache.c | 48 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) (limited to 'libcpu/arm') diff --git a/libcpu/arm/cortex-a/cache.c b/libcpu/arm/cortex-a/cache.c index 0a7e702dbb..a6b59182a6 100644 --- a/libcpu/arm/cortex-a/cache.c +++ b/libcpu/arm/cortex-a/cache.c @@ -58,6 +58,37 @@ void rt_hw_cpu_dcache_invalidate(void *addr, int size) asm volatile ("dsb":::"memory"); } +void rt_hw_cpu_dcache_inv_range(void *addr, int size) +{ + rt_uint32_t line_size = rt_cpu_dcache_line_size(); + rt_uint32_t start_addr = (rt_uint32_t)addr; + rt_uint32_t end_addr = (rt_uint32_t)addr + size; + + asm volatile ("dmb":::"memory"); + + if ((start_addr & (line_size - 1)) != 0) + { + start_addr &= ~(line_size - 1); + asm volatile ("mcr p15, 0, %0, c7, c14, 1" :: "r"(start_addr)); + start_addr += line_size; + asm volatile ("dsb":::"memory"); + } + + if ((end_addr & (line_size - 1)) != 0) + { + end_addr &= ~(line_size - 1); + asm volatile ("mcr p15, 0, %0, c7, c14, 1" :: "r"(end_addr)); + asm volatile ("dsb":::"memory"); + } + + while (start_addr < end_addr) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr)); /* dcimvac */ + start_addr += line_size; + } + asm volatile ("dsb":::"memory"); +} + void rt_hw_cpu_dcache_clean(void *addr, int size) { rt_uint32_t line_size = rt_cpu_dcache_line_size(); @@ -75,6 +106,23 @@ void rt_hw_cpu_dcache_clean(void *addr, int size) asm volatile ("dsb":::"memory"); } +void rt_hw_cpu_dcache_clean_inv(void *addr, int size) +{ + rt_uint32_t line_size = rt_cpu_dcache_line_size(); + rt_uint32_t start_addr = (rt_uint32_t)addr; + rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1; + + asm volatile ("dmb":::"memory"); + start_addr &= ~(line_size-1); + end_addr &= ~(line_size-1); + while (start_addr < end_addr) + { + asm volatile ("mcr p15, 0, %0, c7, c14, 1" :: "r"(start_addr)); + start_addr += line_size; + } + asm volatile ("dsb":::"memory"); +} + void rt_hw_cpu_icache_ops(int ops, void *addr, int size) { if (ops == RT_HW_CACHE_INVALIDATE) -- cgit v1.3.1 From eb79a8a244d3d90665df0a5f3289f90bd1f9aeb1 Mon Sep 17 00:00:00 2001 From: fenghuijie Date: Mon, 5 Jul 2021 14:06:32 +0800 Subject: 修改irq handle接口rt_hw_trap_irq，支持核间IPI中断处理 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- libcpu/arm/cortex-a/trap.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'libcpu/arm') diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c index 3faa136677..f61b89871d 100644 --- a/libcpu/arm/cortex-a/trap.c +++ b/libcpu/arm/cortex-a/trap.c @@ -155,12 +155,14 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) void rt_hw_trap_irq(void) { void *param; + int int_ack; int ir; rt_isr_handler_t isr_func; extern struct rt_irq_desc isr_table[]; - ir = rt_hw_interrupt_get_irq(); + int_ack = rt_hw_interrupt_get_irq(); + ir = int_ack & GIC_ACK_INTID_MASK; if (ir == 1023) { /* Spurious interrupt */ @@ -181,7 +183,7 @@ void rt_hw_trap_irq(void) } /* end of interrupt */ - rt_hw_interrupt_ack(ir); + rt_hw_interrupt_ack(int_ack); } void rt_hw_trap_fiq(void) -- cgit v1.3.1 From e933c1f6105caf4e68bd57bc5521767b32063a5f Mon Sep 17 00:00:00 2001 From: fenghuijie Date: Mon, 5 Jul 2021 14:43:33 +0800 Subject: 调整异常处理代码结构，以支持backtrace功能 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- include/rtdef.h | 4 ++ libcpu/arm/cortex-a/start_gcc.S | 13 +++++- libcpu/arm/cortex-a/trap.c | 88 +++++++++++++++++++++++++++++++---------- 3 files changed, 84 insertions(+), 21 deletions(-) (limited to 'libcpu/arm') diff --git a/include/rtdef.h b/include/rtdef.h index d125c970c9..2eb2cc1963 100644 --- a/include/rtdef.h +++ b/include/rtdef.h @@ -567,6 +567,10 @@ typedef siginfo_t rt_siginfo_t; #define RT_SCHEDULE_IPI 0 #endif +#ifndef RT_STOP_IPI +#define RT_STOP_IPI 1 +#endif + /** * CPUs definitions * diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S index 8fcf6abd2a..6c5dd81785 100644 --- a/libcpu/arm/cortex-a/start_gcc.S +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -373,9 +373,18 @@ rt_hw_context_switch_interrupt_do: mrs r6, spsr @/* Save CPSR */ str lr, [r0, #15*4] @/* Push PC */ str r6, [r0, #16*4] @/* Push CPSR */ - cps #Mode_SVC + mrs r5, cpsr @/* Save CPSR */ + + and r4, r6, #0x1F + cmp r4, #Mode_USR + moveq r6, #Mode_SYS + + orr r6, r6, #0x80 @/* Switch to previous mode, then save SP & PC */ + msr cpsr_c, r6 str sp, [r0, #13*4] @/* Save calling SP */ str lr, [r0, #14*4] @/* Save calling PC */ + + msr cpsr_c, r5 @/* Switch back to current mode */ .endm .align 5 @@ -482,6 +491,8 @@ secondary_cpu_start: .bss .align 2 //align to 2~2=4 +.global sub_stack_top /* used for backtrace to calculate stack top of irq mode */ + sub_stack_start: .space (SUB_ISR_Stack_Size * (RT_CPUS_NR-1)) sub_stack_top: diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c index f61b89871d..b3efe31a64 100644 --- a/libcpu/arm/cortex-a/trap.c +++ b/libcpu/arm/cortex-a/trap.c @@ -35,6 +35,18 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs) rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } +void (*rt_trap_hook)(struct rt_hw_exp_stack *regs, const char *ex, unsigned int exception_type); + +/** + * This function will set a hook function to trap handler. + * + * @param hook the hook function + */ +void rt_hw_trap_set_hook(void (*hook)(struct rt_hw_exp_stack *regs, const char *ex, unsigned int exception_type)) +{ + rt_trap_hook = hook; +} + /** * When comes across an instruction which it cannot handle, * it takes the undefined instruction trap. @@ -72,12 +84,20 @@ void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) } } #endif - rt_kprintf("undefined instruction:\n"); - rt_hw_show_register(regs); + + if (rt_trap_hook == RT_NULL) + { + rt_kprintf("undefined instruction:\n"); + rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); + } + else + { + rt_trap_hook(regs, "undefined instruction", UND_EXCEPTION); + } } /** @@ -91,12 +111,19 @@ void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) */ void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) { - rt_kprintf("software interrupt:\n"); - rt_hw_show_register(regs); + if (rt_trap_hook == RT_NULL) + { + rt_kprintf("software interrupt:\n"); + rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); + } + else + { + rt_trap_hook(regs, "software instruction", SWI_EXCEPTION); + } } /** @@ -109,12 +136,19 @@ void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) */ void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) { - rt_kprintf("prefetch abort:\n"); - rt_hw_show_register(regs); + if (rt_trap_hook == RT_NULL) + { + rt_kprintf("prefetch abort:\n"); + rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); + } + else + { + rt_trap_hook(regs, "prefetch abort", PABT_EXCEPTION); + } } /** @@ -127,12 +161,19 @@ void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) */ void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) { - rt_kprintf("data abort:"); - rt_hw_show_register(regs); + if (rt_trap_hook == RT_NULL) + { + rt_kprintf("data abort:"); + rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); + } + else + { + rt_trap_hook(regs, "data abort", DABT_EXCEPTION); + } } /** @@ -144,12 +185,19 @@ void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) */ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) { - rt_kprintf("reserved trap:\n"); - rt_hw_show_register(regs); + if (rt_trap_hook == RT_NULL) + { + rt_kprintf("reserved trap:\n"); + rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); + } + else + { + rt_trap_hook(regs, "reserved trap", RESV_EXCEPTION); + } } void rt_hw_trap_irq(void) -- cgit v1.3.1 From 0015af02e4f08ab47f2d2fefcb7c1aca1682bfda Mon Sep 17 00:00:00 2001 From: fenghuijie Date: Mon, 5 Jul 2021 18:33:22 +0800 Subject: 调整代码，以支持cpu usage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- include/rtdef.h | 4 ++++ include/rtthread.h | 1 + libcpu/arm/cortex-a/interrupt.c | 14 ++++++++++++++ libcpu/arm/cortex-a/start_gcc.S | 2 ++ src/irq.c | 2 +- src/scheduler.c | 13 +++++++++++++ src/thread.c | 4 ++++ 7 files changed, 39 insertions(+), 1 deletion(-) (limited to 'libcpu/arm') diff --git a/include/rtdef.h b/include/rtdef.h index 2eb2cc1963..e1a64a433a 100644 --- a/include/rtdef.h +++ b/include/rtdef.h @@ -663,6 +663,10 @@ struct rt_thread rt_ubase_t init_tick; /**< thread's initialized tick */ rt_ubase_t remaining_tick; /**< remaining tick */ +#ifdef RT_USING_CPU_USAGE + rt_uint64_t duration_tick; /**< cpu usage tick */ +#endif + struct rt_timer thread_timer; /**< built-in thread timer */ void (*cleanup)(struct rt_thread *tid); /**< cleanup function when thread exit */ diff --git a/include/rtthread.h b/include/rtthread.h index f2f4091b8a..cf47a48efe 100644 --- a/include/rtthread.h +++ b/include/rtthread.h @@ -186,6 +186,7 @@ rt_uint16_t rt_critical_level(void); #ifdef RT_USING_HOOK void rt_scheduler_sethook(void (*hook)(rt_thread_t from, rt_thread_t to)); +void rt_scheduler_switch_sethook(void (*hook)(struct rt_thread *tid)); #endif #ifdef RT_USING_SMP diff --git a/libcpu/arm/cortex-a/interrupt.c b/libcpu/arm/cortex-a/interrupt.c index 474a23fee1..f90f1c0094 100644 --- a/libcpu/arm/cortex-a/interrupt.c +++ b/libcpu/arm/cortex-a/interrupt.c @@ -27,6 +27,20 @@ struct rt_irq_desc isr_table[MAX_HANDLERS]; rt_uint32_t rt_interrupt_from_thread = 0; rt_uint32_t rt_interrupt_to_thread = 0; rt_uint32_t rt_thread_switch_interrupt_flag = 0; + +#ifdef RT_USING_HOOK +static void (*rt_interrupt_switch_hook)(void); + +void rt_interrupt_switch_sethook(void (*hook)(void)) +{ + rt_interrupt_switch_hook = hook; +} +#endif + +void rt_interrupt_hook(void) +{ + RT_OBJECT_HOOK_CALL(rt_interrupt_switch_hook, ()); +} #endif const unsigned int VECTOR_BASE = 0x00; diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S index 6c5dd81785..908468476e 100644 --- a/libcpu/arm/cortex-a/start_gcc.S +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -341,6 +341,8 @@ rt_hw_context_switch_interrupt_do: ldr r6, [r6] ldr sp, [r6] @ get new task's stack pointer + bl rt_interrupt_hook + #ifdef RT_USING_FPU /* fpu context */ ldmfd sp!, {r6} diff --git a/src/irq.c b/src/irq.c index e89b8504dc..6ddcb3dd4a 100644 --- a/src/irq.c +++ b/src/irq.c @@ -89,8 +89,8 @@ void rt_interrupt_leave(void) rt_interrupt_nest)); level = rt_hw_interrupt_disable(); - rt_interrupt_nest --; RT_OBJECT_HOOK_CALL(rt_interrupt_leave_hook,()); + rt_interrupt_nest --; rt_hw_interrupt_enable(level); } RTM_EXPORT(rt_interrupt_leave); diff --git a/src/scheduler.c b/src/scheduler.c index 956d95d7cc..353fdad5cb 100644 --- a/src/scheduler.c +++ b/src/scheduler.c @@ -49,6 +49,7 @@ rt_uint8_t rt_current_priority; #ifdef RT_USING_HOOK static void (*rt_scheduler_hook)(struct rt_thread *from, struct rt_thread *to); +static void (*rt_scheduler_switch_hook)(struct rt_thread *tid); /** * @addtogroup Hook @@ -68,6 +69,12 @@ rt_scheduler_sethook(void (*hook)(struct rt_thread *from, struct rt_thread *to)) rt_scheduler_hook = hook; } +void +rt_scheduler_switch_sethook(void (*hook)(struct rt_thread *tid)) +{ + rt_scheduler_switch_hook = hook; +} + /**@}*/ #endif /* RT_USING_HOOK */ @@ -364,6 +371,8 @@ void rt_schedule(void) _rt_scheduler_stack_check(to_thread); #endif /* RT_USING_OVERFLOW_CHECK */ + RT_OBJECT_HOOK_CALL(rt_scheduler_switch_hook, (current_thread)); + rt_hw_context_switch((rt_ubase_t)¤t_thread->sp, (rt_ubase_t)&to_thread->sp, to_thread); } @@ -473,6 +482,8 @@ void rt_schedule(void) { extern void rt_thread_handle_sig(rt_bool_t clean_state); + RT_OBJECT_HOOK_CALL(rt_scheduler_switch_hook, (from_thread)); + rt_hw_context_switch((rt_ubase_t)&from_thread->sp, (rt_ubase_t)&to_thread->sp); @@ -609,6 +620,8 @@ void rt_scheduler_do_irq_switch(void *context) current_thread->cpus_lock_nest--; current_thread->scheduler_lock_nest--; + RT_OBJECT_HOOK_CALL(rt_scheduler_switch_hook, (current_thread)); + rt_hw_context_switch_interrupt(context, (rt_ubase_t)¤t_thread->sp, (rt_ubase_t)&to_thread->sp, to_thread); } diff --git a/src/thread.c b/src/thread.c index 88cc7b61ba..60e6ab91d1 100644 --- a/src/thread.c +++ b/src/thread.c @@ -228,6 +228,10 @@ static rt_err_t _rt_thread_init(struct rt_thread *thread, thread->lwp = RT_NULL; #endif /* RT_USING_LWP */ +#ifdef RT_USING_CPU_USAGE + thread->duration_tick = 0; +#endif + RT_OBJECT_HOOK_CALL(rt_thread_inited_hook, (thread)); return RT_EOK; -- cgit v1.3.1 From e62943abd27b4b7cadd149ed34ccb1bb332c790d Mon Sep 17 00:00:00 2001 From: iysheng Date: Mon, 5 Jul 2021 11:24:06 +0800 Subject: [libcpu][arm][s3c24x0] Fix RTC driver compile error --- libcpu/arm/s3c24x0/rtc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'libcpu/arm') diff --git a/libcpu/arm/s3c24x0/rtc.c b/libcpu/arm/s3c24x0/rtc.c index 0f9484405c..5d374dfadf 100644 --- a/libcpu/arm/s3c24x0/rtc.c +++ b/libcpu/arm/s3c24x0/rtc.c @@ -12,11 +12,12 @@ */ #include +#include #include #include // #define RTC_DEBUG - +#ifdef RT_USING_RTC #define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */ #define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */ #define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F)) @@ -183,3 +184,4 @@ void list_date() } FINSH_FUNCTION_EXPORT(list_date, list date); #endif +#endif -- cgit v1.3.1