From 7c6650186100add61ef16c13fb120ad1161f6f1d Mon Sep 17 00:00:00 2001 From: Jiaxun Yang Date: Sat, 7 Dec 2019 00:54:03 +0800 Subject: [libcpu] Refine MIPS common code MIPS common code was highly duplicated, This commit is a attempt to clean-up and refine these code. The context and exception handle flow is mostly identical with Linux, but a notable difference is that when FPU enabled, we save FP registers in stackframe unconditionally. Signed-off-by: Jiaxun Yang --- libcpu/mips/common/stackframe.h | 458 +++++++++++++++++++++------------------- 1 file changed, 240 insertions(+), 218 deletions(-) (limited to 'libcpu/mips/common/stackframe.h') diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h index 96b69ab14f..77d55f6934 100644 --- a/libcpu/mips/common/stackframe.h +++ b/libcpu/mips/common/stackframe.h @@ -1,228 +1,250 @@ /* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * Copyright (c) 2006-2019, RT-Thread Development Team * - * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle - * Copyright (C) 1994, 1995, 1996 Paul M. Antoine. - * Copyright (C) 1999 Silicon Graphics, Inc. - * Copyright (C) 2007 Maciej W. Rozycki + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2019-12-04 Jiaxun Yang Initial version */ + #ifndef __STACKFRAME_H__ #define __STACKFRAME_H__ #include "asm.h" -#include "mipsregs.h" - -/* - * Stack layout for the INT exception handler - * Derived from the stack layout described in asm-mips/stackframe.h - * - * The first PTRSIZE*6 bytes are argument save space for C subroutines. - */ - -//#define PT_R0 (PTRSIZE*6) /* 0 */ -#define PT_R0 (0) /* 0 */ -#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */ -#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */ -#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */ -#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */ -#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */ -#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */ -#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */ -#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */ -#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */ -#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */ -#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */ -#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */ -#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */ -#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */ -#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */ -#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */ -#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */ -#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */ -#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */ -#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */ -#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */ -#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */ -#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */ -#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */ -#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */ -#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */ -#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */ -#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */ -#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */ -#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */ -#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */ - -/* - * Saved special registers - */ -#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */ -#define PT_HI ((PT_STATUS) + LONGSIZE) /* 33 */ -#define PT_LO ((PT_HI) + LONGSIZE) /* 34 */ -#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */ -#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */ -#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */ - -#define PT_SIZE ((((PT_EPC) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1)) - - - .macro SAVE_AT - .set push - .set noat - LONG_S $1, PT_R1(sp) - .set pop - .endm - - .macro SAVE_TEMP - mfhi v1 - LONG_S $8, PT_R8(sp) - LONG_S $9, PT_R9(sp) - LONG_S v1, PT_HI(sp) - mflo v1 - LONG_S $10, PT_R10(sp) - LONG_S $11, PT_R11(sp) - LONG_S v1, PT_LO(sp) - LONG_S $12, PT_R12(sp) - LONG_S $13, PT_R13(sp) - LONG_S $14, PT_R14(sp) - LONG_S $15, PT_R15(sp) - LONG_S $24, PT_R24(sp) - .endm - - .macro SAVE_STATIC - LONG_S $16, PT_R16(sp) - LONG_S $17, PT_R17(sp) - LONG_S $18, PT_R18(sp) - LONG_S $19, PT_R19(sp) - LONG_S $20, PT_R20(sp) - LONG_S $21, PT_R21(sp) - LONG_S $22, PT_R22(sp) - LONG_S $23, PT_R23(sp) - LONG_S $30, PT_R30(sp) - .endm - - .macro get_saved_sp - nop - .endm - - .macro SAVE_SOME - .set push - .set noat - .set reorder - move k1, sp -8: move k0, sp - PTR_SUBU sp, k1, PT_SIZE - LONG_S k0, PT_R29(sp) - LONG_S $3, PT_R3(sp) - LONG_S $0, PT_R0(sp) - mfc0 v1, CP0_STATUS - LONG_S $2, PT_R2(sp) - LONG_S v1, PT_STATUS(sp) - LONG_S $4, PT_R4(sp) - mfc0 v1, CP0_CAUSE - LONG_S $5, PT_R5(sp) - LONG_S v1, PT_CAUSE(sp) - LONG_S $6, PT_R6(sp) - MFC0 v1, CP0_EPC - LONG_S $7, PT_R7(sp) - LONG_S v1, PT_EPC(sp) - LONG_S $25, PT_R25(sp) - LONG_S $28, PT_R28(sp) - LONG_S $31, PT_R31(sp) - .set pop - .endm - - .macro SAVE_ALL - SAVE_SOME - SAVE_AT - SAVE_TEMP - SAVE_STATIC - .endm - - .macro RESTORE_AT - .set push - .set noat - LONG_L $1, PT_R1(sp) - .set pop - .endm - - .macro RESTORE_TEMP - LONG_L $24, PT_LO(sp) - LONG_L $8, PT_R8(sp) - LONG_L $9, PT_R9(sp) - mtlo $24 - LONG_L $24, PT_HI(sp) - LONG_L $10, PT_R10(sp) - LONG_L $11, PT_R11(sp) - mthi $24 - LONG_L $12, PT_R12(sp) - LONG_L $13, PT_R13(sp) - LONG_L $14, PT_R14(sp) - LONG_L $15, PT_R15(sp) - LONG_L $24, PT_R24(sp) - .endm - - .macro RESTORE_STATIC - LONG_L $16, PT_R16(sp) - LONG_L $17, PT_R17(sp) - LONG_L $18, PT_R18(sp) - LONG_L $19, PT_R19(sp) - LONG_L $20, PT_R20(sp) - LONG_L $21, PT_R21(sp) - LONG_L $22, PT_R22(sp) - LONG_L $23, PT_R23(sp) - LONG_L $30, PT_R30(sp) - .endm - - .macro RESTORE_SOME - .set push - .set reorder - .set noat - LONG_L v0, PT_STATUS(sp) - mtc0 v0, CP0_STATUS - LONG_L v1, PT_EPC(sp) - MTC0 v1, CP0_EPC - LONG_L $31, PT_R31(sp) - LONG_L $28, PT_R28(sp) - LONG_L $25, PT_R25(sp) - LONG_L $7, PT_R7(sp) - LONG_L $6, PT_R6(sp) - LONG_L $5, PT_R5(sp) - LONG_L $4, PT_R4(sp) - LONG_L $3, PT_R3(sp) - LONG_L $2, PT_R2(sp) - .set pop - .endm - - .macro RESTORE_SP_AND_RET - LONG_L sp, PT_R29(sp) - .set mips3 - eret - .set mips0 - .endm - - - .macro RESTORE_SP - LONG_L sp, PT_R29(sp) - .endm - - .macro RESTORE_ALL - RESTORE_TEMP - RESTORE_STATIC - RESTORE_AT - RESTORE_SOME - RESTORE_SP - .endm - - .macro RESTORE_ALL_AND_RET - RESTORE_TEMP - RESTORE_STATIC - RESTORE_AT - RESTORE_SOME - RESTORE_SP_AND_RET - .endm +#include "mips_regs.h" +#include "ptrace.h" + +/* You MUST ensure FP is enabled before SAVE_FPU! */ + .macro SAVE_FPU + .set push + .set noreorder +#ifdef RT_USING_FPU + /* Ensure CU1 (FPU) is enabled */ + MFC0 v1, CP0_STATUS + ori v1, ST0_CU1 + MTC0 v1, CP0_STATUS + SSNOP + cfc1 v1, fcr31 + /* Store as delay slot */ + s.d $f0, PT_FPU_R0(sp) + s.d $f2, PT_FPU_R2(sp) + s.d $f4, PT_FPU_R4(sp) + s.d $f6, PT_FPU_R6(sp) + s.d $f8, PT_FPU_R8(sp) + s.d $f10, PT_FPU_R10(sp) + s.d $f12, PT_FPU_R12(sp) + s.d $f14, PT_FPU_R14(sp) + s.d $f16, PT_FPU_R16(sp) + s.d $f18, PT_FPU_R18(sp) + s.d $f20, PT_FPU_R20(sp) + s.d $f22, PT_FPU_R22(sp) + s.d $f24, PT_FPU_R24(sp) + s.d $f26, PT_FPU_R26(sp) + s.d $f28, PT_FPU_R28(sp) + s.d $f30, PT_FPU_R30(sp) + LONG_S v1, PT_FPU_FCSR31(sp) +#endif + .set reorder + .set pop + .endm + + .macro SAVE_AT + .set push + .set noat + LONG_S $1, PT_R1(sp) + .set pop + .endm + + .macro SAVE_TEMP + mfhi v1 + LONG_S $8, PT_R8(sp) + LONG_S $9, PT_R9(sp) + LONG_S v1, PT_HI(sp) + mflo v1 + LONG_S $10, PT_R10(sp) + LONG_S $11, PT_R11(sp) + LONG_S v1, PT_LO(sp) + LONG_S $12, PT_R12(sp) + LONG_S $13, PT_R13(sp) + LONG_S $14, PT_R14(sp) + LONG_S $15, PT_R15(sp) + LONG_S $24, PT_R24(sp) + .endm + + .macro SAVE_STATIC + LONG_S $16, PT_R16(sp) + LONG_S $17, PT_R17(sp) + LONG_S $18, PT_R18(sp) + LONG_S $19, PT_R19(sp) + LONG_S $20, PT_R20(sp) + LONG_S $21, PT_R21(sp) + LONG_S $22, PT_R22(sp) + LONG_S $23, PT_R23(sp) + LONG_S $30, PT_R30(sp) + .endm + + .macro SAVE_SOME + .set push + .set noat + .set reorder + move k1, sp + move k0, sp + PTR_SUBU sp, k1, PT_SIZE + LONG_S k0, PT_R29(sp) + LONG_S $3, PT_R3(sp) + LONG_S $0, PT_R0(sp) + MFC0 v1, CP0_STATUS + LONG_S $2, PT_R2(sp) + LONG_S v1, PT_STATUS(sp) + LONG_S $4, PT_R4(sp) + MFC0 v1, CP0_CAUSE + LONG_S $5, PT_R5(sp) + LONG_S v1, PT_CAUSE(sp) + LONG_S $6, PT_R6(sp) + MFC0 v1, CP0_EPC + LONG_S $7, PT_R7(sp) + LONG_S v1, PT_EPC(sp) + LONG_S $25, PT_R25(sp) + LONG_S $28, PT_R28(sp) + LONG_S $31, PT_R31(sp) + .set pop + .endm + + .macro SAVE_ALL + SAVE_SOME + SAVE_AT + SAVE_TEMP + SAVE_FPU + SAVE_STATIC + .endm + + .macro RESTORE_FPU + .set push + .set noreorder +#ifdef RT_USING_FPU + /* Ensure CU1 (FPU) is enabled */ + MFC0 v1, CP0_STATUS + ori v1, ST0_CU1 + MTC0 v1, CP0_STATUS + SSNOP + LONG_L v1, PT_FPU_FCSR31(sp) + ctc1 v1, fcsr31 + l.d $f0, PT_FPU_R0(sp) + l.d $f2, PT_FPU_R2(sp) + l.d $f4, PT_FPU_R4(sp) + l.d $f6, PT_FPU_R6(sp) + l.d $f8, PT_FPU_R8(sp) + l.d $f10, PT_FPU_R10(sp) + l.d $f12, PT_FPU_R12(sp) + l.d $f14, PT_FPU_R14(sp) + l.d $f16, PT_FPU_R16(sp) + l.d $f18, PT_FPU_R18(sp) + l.d $f20, PT_FPU_R20(sp) + l.d $f22, PT_FPU_R22(sp) + l.d $f24, PT_FPU_R24(sp) + l.d $f26, PT_FPU_R26(sp) + l.d $f28, PT_FPU_R28(sp) + l.d $f30, PT_FPU_R30(sp) +#endif + .set reorder + .set pop + .endm + + .macro RESTORE_AT + .set push + .set noat + LONG_L $1, PT_R1(sp) + .set pop + .endm + + .macro RESTORE_TEMP + LONG_L $24, PT_LO(sp) + LONG_L $8, PT_R8(sp) + LONG_L $9, PT_R9(sp) + mtlo $24 + LONG_L $24, PT_HI(sp) + LONG_L $10, PT_R10(sp) + LONG_L $11, PT_R11(sp) + mthi $24 + LONG_L $12, PT_R12(sp) + LONG_L $13, PT_R13(sp) + LONG_L $14, PT_R14(sp) + LONG_L $15, PT_R15(sp) + LONG_L $24, PT_R24(sp) + .endm + + .macro RESTORE_STATIC + LONG_L $16, PT_R16(sp) + LONG_L $17, PT_R17(sp) + LONG_L $18, PT_R18(sp) + LONG_L $19, PT_R19(sp) + LONG_L $20, PT_R20(sp) + LONG_L $21, PT_R21(sp) + LONG_L $22, PT_R22(sp) + LONG_L $23, PT_R23(sp) + LONG_L $30, PT_R30(sp) + .endm + +#define STATMASK 0x1f + + .macro RESTORE_SOME + .set push + .set reorder + .set noat + mfc0 a0, CP0_STATUS + ori a0, STATMASK + xori a0, STATMASK + mtc0 a0, CP0_STATUS + li v1, (ST0_CU1 | ST0_FR | ST0_IM) + and a0, v1, a0 + LONG_L v0, PT_STATUS(sp) + li v1, ~(ST0_CU1 | ST0_FR | ST0_IM) + and v0, v1 + or v0, a0 + mtc0 v0, CP0_STATUS + LONG_L v1, PT_EPC(sp) + MTC0 v1, CP0_EPC + LONG_L $31, PT_R31(sp) + LONG_L $28, PT_R28(sp) + LONG_L $25, PT_R25(sp) + LONG_L $7, PT_R7(sp) + LONG_L $6, PT_R6(sp) + LONG_L $5, PT_R5(sp) + LONG_L $4, PT_R4(sp) + LONG_L $3, PT_R3(sp) + LONG_L $2, PT_R2(sp) + .set pop + .endm + + .macro RESTORE_SP_AND_RET + LONG_L sp, PT_R29(sp) + eret + nop + .endm + + + .macro RESTORE_SP + LONG_L sp, PT_R29(sp) + .endm + + .macro RESTORE_ALL + RESTORE_TEMP + RESTORE_FPU + RESTORE_STATIC + RESTORE_AT + RESTORE_SOME + RESTORE_SP + .endm + + .macro RESTORE_ALL_AND_RET + RESTORE_TEMP + RESTORE_FPU + RESTORE_STATIC + RESTORE_AT + RESTORE_SOME + RESTORE_SP_AND_RET + .endm #endif /* end of __STACKFRAME_H__ */ -- cgit v1.3.1 From 990f731b776055390db854f9cc980799e39247e8 Mon Sep 17 00:00:00 2001 From: bigmagic Date: Mon, 6 Apr 2020 15:46:28 +0800 Subject: fix mips64 some bug --- bsp/ls2kdev/.config | 22 +----- bsp/ls2kdev/drivers/board.c | 7 +- bsp/ls2kdev/drivers/board.h | 2 +- bsp/ls2kdev/ls2k_ram.lds | 141 ++++++++++++++++++++++++++++++++++++ bsp/ls2kdev/mipssim_ram.lds | 141 ------------------------------------ bsp/ls2kdev/rtconfig.h | 11 +-- bsp/ls2kdev/rtconfig.py | 8 +- libcpu/mips/common/asm.h | 4 + libcpu/mips/common/context_gcc.S | 24 +++--- libcpu/mips/common/entry_gcc.S | 4 +- libcpu/mips/common/exception.c | 17 +++-- libcpu/mips/common/exception_gcc.S | 13 +++- libcpu/mips/common/mips_addrspace.h | 9 ++- libcpu/mips/common/mips_regs.h | 46 +++++++++++- libcpu/mips/common/ptrace.h | 25 +++++-- libcpu/mips/common/stack.c | 21 +++--- libcpu/mips/common/stackframe.h | 4 +- 17 files changed, 278 insertions(+), 221 deletions(-) create mode 100644 bsp/ls2kdev/ls2k_ram.lds delete mode 100644 bsp/ls2kdev/mipssim_ram.lds (limited to 'libcpu/mips/common/stackframe.h') diff --git a/bsp/ls2kdev/.config b/bsp/ls2kdev/.config index 00b8746e4f..20cf03b625 100644 --- a/bsp/ls2kdev/.config +++ b/bsp/ls2kdev/.config @@ -21,11 +21,12 @@ CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=2048 CONFIG_RT_USING_TIMER_SOFT=y -CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_PRIO=20 CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 CONFIG_RT_DEBUG=y # CONFIG_RT_DEBUG_COLOR is not set -# CONFIG_RT_DEBUG_INIT_CONFIG is not set +CONFIG_RT_DEBUG_INIT_CONFIG=y +CONFIG_RT_DEBUG_INIT=1 # CONFIG_RT_DEBUG_THREAD_CONFIG is not set # CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set # CONFIG_RT_DEBUG_IPC_CONFIG is not set @@ -106,18 +107,7 @@ CONFIG_FINSH_ARG_MAX=10 # # Device virtual file system # -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=2 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 -CONFIG_DFS_FD_MAX=16 -# CONFIG_RT_USING_DFS_MNTTABLE is not set -# CONFIG_RT_USING_DFS_ELMFAT is not set -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_UFFS is not set -# CONFIG_RT_USING_DFS_JFFS2 is not set +# CONFIG_RT_USING_DFS is not set # # Device Drivers @@ -161,10 +151,6 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_LIBC=y # CONFIG_RT_USING_PTHREADS is not set -CONFIG_RT_USING_POSIX=y -# CONFIG_RT_USING_POSIX_MMAP is not set -# CONFIG_RT_USING_POSIX_TERMIOS is not set -# CONFIG_RT_USING_POSIX_AIO is not set # CONFIG_RT_USING_MODULE is not set # diff --git a/bsp/ls2kdev/drivers/board.c b/bsp/ls2kdev/drivers/board.c index 3edbae9ee7..20b7a84516 100644 --- a/bsp/ls2kdev/drivers/board.c +++ b/bsp/ls2kdev/drivers/board.c @@ -70,10 +70,10 @@ void rt_hw_board_init(void) /* init hardware interrupt */ rt_hw_interrupt_init(); - #ifdef RT_USING_FPU +#ifdef RT_USING_FPU /* init hardware fpu */ rt_hw_fpu_init(); - #endif +#endif #ifdef RT_USING_SERIAL /* init hardware UART device */ @@ -88,8 +88,7 @@ void rt_hw_board_init(void) /* init operating system timer */ rt_hw_timer_init(); - - + #ifdef RT_USING_COMPONENTS_INIT rt_components_board_init(); #endif diff --git a/bsp/ls2kdev/drivers/board.h b/bsp/ls2kdev/drivers/board.h index df4b40fb78..6e2f85ec74 100644 --- a/bsp/ls2kdev/drivers/board.h +++ b/bsp/ls2kdev/drivers/board.h @@ -16,7 +16,7 @@ extern unsigned char __bss_end; #define CPU_HZ (100 * 1000 * 1000) -#define RT_HW_HEAP_BEGIN (void*)&__bss_end +#define RT_HW_HEAP_BEGIN KSEG1BASE//(void*)&__bss_end #define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024) void rt_hw_board_init(void); diff --git a/bsp/ls2kdev/ls2k_ram.lds b/bsp/ls2kdev/ls2k_ram.lds new file mode 100644 index 0000000000..8bec1e855b --- /dev/null +++ b/bsp/ls2kdev/ls2k_ram.lds @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2006-2020, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-04-05 bigmagic Initial version + */ + +OUTPUT_ARCH(mips) +GROUP(-lgcc -lc) + +ENTRY(_start) +SECTIONS +{ + . = 0xffffffff82000000 ; + .text : + { + __ebase_entry = .; + KEEP(*(.exc_vectors)) + __ebase_end = .; + start = .; + *(.start); + . = ALIGN(4); + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.rodata1) + *(.rodata1.*) + + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + . = ALIGN(4); + __rt_utest_tc_tab_start = .; + KEEP(*(UtestTcTab)) + __rt_utest_tc_tab_end = .; + . = ALIGN(4); + } + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + *(.eh_frame_entry) + } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + + . = ALIGN(4); + .data : + { + *(.data) + *(.data.*) + + *(.data1) + *(.data1.*) + + . = ALIGN(8); + _gp = ABSOLUTE(.); /* Base of small data */ + + *(.sdata) + *(.sdata.*) + } + + .stack : + { + . = ALIGN(8); + _system_stack_start = .; + . = . + 0x1000; + _system_stack = .; + } + + .sbss : + { + __bss_start = .; + *(.sbss) + *(.sbss.*) + *(.dynsbss) + *(.scommon) + } + + .bss : + { + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + __bss_end = .; + } + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/ls2kdev/mipssim_ram.lds b/bsp/ls2kdev/mipssim_ram.lds deleted file mode 100644 index 70385101c1..0000000000 --- a/bsp/ls2kdev/mipssim_ram.lds +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright (c) 2006-2020, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2020-04-05 bigmagic Initial version - */ - -OUTPUT_ARCH(mips) -GROUP(-lgcc -lc) - -ENTRY(_start) -SECTIONS -{ - . = 0x80200000 ; - .text : - { - __ebase_entry = .; - KEEP(*(.exc_vectors)) - __ebase_end = .; - start = .; - *(.start); - . = ALIGN(4); - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.rodata1) - *(.rodata1.*) - - - /* section information for finsh shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(4); - - . = ALIGN(4); - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - __rt_utest_tc_tab_end = .; - . = ALIGN(4); - } - - .eh_frame_hdr : - { - *(.eh_frame_hdr) - *(.eh_frame_entry) - } - .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } - - . = ALIGN(4); - .data : - { - *(.data) - *(.data.*) - - *(.data1) - *(.data1.*) - - . = ALIGN(8); - _gp = ABSOLUTE(.); /* Base of small data */ - - *(.sdata) - *(.sdata.*) - } - - .stack : - { - . = ALIGN(8); - _system_stack_start = .; - . = . + 0x1000; - _system_stack = .; - } - - .sbss : - { - __bss_start = .; - *(.sbss) - *(.sbss.*) - *(.dynsbss) - *(.scommon) - } - - .bss : - { - *(.bss) - *(.bss.*) - *(.dynbss) - *(COMMON) - __bss_end = .; - } - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} diff --git a/bsp/ls2kdev/rtconfig.h b/bsp/ls2kdev/rtconfig.h index f53fcc66f4..80f068c5c0 100644 --- a/bsp/ls2kdev/rtconfig.h +++ b/bsp/ls2kdev/rtconfig.h @@ -17,9 +17,11 @@ #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 2048 #define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 20 #define RT_TIMER_THREAD_STACK_SIZE 2048 #define RT_DEBUG +#define RT_DEBUG_INIT_CONFIG +#define RT_DEBUG_INIT 1 /* Inter-Thread communication */ @@ -71,12 +73,6 @@ /* Device virtual file system */ -#define RT_USING_DFS -#define DFS_USING_WORKDIR -#define DFS_FILESYSTEMS_MAX 2 -#define DFS_FILESYSTEM_TYPES_MAX 2 -#define DFS_FD_MAX 16 -#define RT_USING_DFS_DEVFS /* Device Drivers */ @@ -93,7 +89,6 @@ /* POSIX layer and C standard library */ #define RT_USING_LIBC -#define RT_USING_POSIX /* Network */ diff --git a/bsp/ls2kdev/rtconfig.py b/bsp/ls2kdev/rtconfig.py index f3e3786525..c8490a382f 100644 --- a/bsp/ls2kdev/rtconfig.py +++ b/bsp/ls2kdev/rtconfig.py @@ -40,10 +40,10 @@ OBJDUMP = PREFIX + 'objdump' OBJCPY = PREFIX + 'objcopy' READELF = PREFIX + 'readelf' -DEVICE = ' -march=mips64r2 -mabi=64 -msoft-float' -CFLAGS = DEVICE + ' -EL -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer' -AFLAGS = ' -c' + DEVICE + ' -EL -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp' -LFLAGS = DEVICE + ' -nostartfiles -EL -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T mipssim_ram.lds' +DEVICE = ' -march=mips64r2 -mabi=64 -msoft-float -EL' +CFLAGS = DEVICE + ' -G0 -mno-abicalls -fno-pic -fno-builtin -fno-exceptions -ffunction-sections -fomit-frame-pointer' +AFLAGS = ' -c' + DEVICE + ' -fno-pic -fno-builtin -mno-abicalls -x assembler-with-cpp' +LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T ls2k_ram.lds' CXXFLAGS = CFLAGS CPATH = '' diff --git a/libcpu/mips/common/asm.h b/libcpu/mips/common/asm.h index 987a1fb2b6..a16db1868e 100644 --- a/libcpu/mips/common/asm.h +++ b/libcpu/mips/common/asm.h @@ -261,7 +261,11 @@ symbol = value #define LONG_SRAV srav #define LONG .word +#ifdef ARCH_MIPS64 +#define LONGSIZE 8 +#else #define LONGSIZE 4 +#endif #define LONGMASK 3 #define LONGLOG 2 diff --git a/libcpu/mips/common/context_gcc.S b/libcpu/mips/common/context_gcc.S index 251fc81c3c..cdcdede39a 100644 --- a/libcpu/mips/common/context_gcc.S +++ b/libcpu/mips/common/context_gcc.S @@ -25,11 +25,11 @@ */ .globl rt_hw_context_switch rt_hw_context_switch: - mtc0 ra, CP0_EPC + MTC0 ra, CP0_EPC SAVE_ALL - sw sp, 0(a0) /* store sp in preempted tasks TCB */ - lw sp, 0(a1) /* get new task stack pointer */ + REG_S sp, 0(a0) /* store sp in preempted tasks TCB */ + REG_L sp, 0(a1) /* get new task stack pointer */ RESTORE_ALL_AND_RET @@ -39,7 +39,7 @@ rt_hw_context_switch: */ .globl rt_hw_context_switch_to rt_hw_context_switch_to: - lw sp, 0(a0) /* get new task stack pointer */ + REG_L sp, 0(a0) /* get new task stack pointer */ RESTORE_ALL_AND_RET /* @@ -50,17 +50,17 @@ rt_hw_context_switch_to: .globl rt_interrupt_to_thread .globl rt_hw_context_switch_interrupt rt_hw_context_switch_interrupt: - la t0, rt_thread_switch_interrupt_flag - lw t1, 0(t0) + PTR_LA t0, rt_thread_switch_interrupt_flag + REG_L t1, 0(t0) nop bnez t1, _reswitch nop li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ sw t1, 0(t0) - la t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ + PTR_LA t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ sw a0, 0(t0) _reswitch: - la t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ + PTR_LA t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ sw a1, 0(t0) jr ra nop @@ -78,7 +78,7 @@ mips_irq_handle: /* let k0 keep the current context sp */ move k0, sp /* switch to kernel stack */ - la sp, _system_stack + PTR_LA sp, _system_stack jal rt_interrupt_enter nop @@ -96,7 +96,7 @@ mips_irq_handle: * if rt_thread_switch_interrupt_flag set, jump to * rt_hw_context_switch_interrupt_do and do not return */ - la k0, rt_thread_switch_interrupt_flag + PTR_LA k0, rt_thread_switch_interrupt_flag lw k1, 0(k0) beqz k1, spurious_interrupt nop @@ -106,12 +106,12 @@ mips_irq_handle: /* * switch to the new thread */ - la k0, rt_interrupt_from_thread + PTR_LA k0, rt_interrupt_from_thread lw k1, 0(k0) nop sw sp, 0(k1) /* store sp in preempted task TCB */ - la k0, rt_interrupt_to_thread + PTR_LA k0, rt_interrupt_to_thread lw k1, 0(k0) nop lw sp, 0(k1) /* get new task stack pointer */ diff --git a/libcpu/mips/common/entry_gcc.S b/libcpu/mips/common/entry_gcc.S index 757774cfd9..d1a0704809 100644 --- a/libcpu/mips/common/entry_gcc.S +++ b/libcpu/mips/common/entry_gcc.S @@ -31,8 +31,8 @@ _start: PTR_LA ra, _rtthread_entry /* disable interrupt */ - mtc0 zero, CP0_CAUSE - mtc0 zero, CP0_STATUS # Set CPU to disable interrupt. + MTC0 zero, CP0_CAUSE + MTC0 zero, CP0_STATUS # Set CPU to disable interrupt. ehb #ifdef ARCH_MIPS64 diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c index de67e98199..11192955cf 100644 --- a/libcpu/mips/common/exception.c +++ b/libcpu/mips/common/exception.c @@ -19,10 +19,10 @@ /*@{*/ -extern rt_uint32_t __ebase_entry; -rt_uint32_t rt_interrupt_from_thread; -rt_uint32_t rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; +extern rt_ubase_t __ebase_entry; +rt_ubase_t rt_interrupt_from_thread; +rt_ubase_t rt_interrupt_to_thread; +rt_ubase_t rt_thread_switch_interrupt_flag; rt_base_t rt_hw_interrupt_disable(void) { @@ -101,7 +101,10 @@ static void install_default_exception_handler(void) int rt_hw_exception_init(void) { - rt_uint32_t ebase = (rt_uint32_t)&__ebase_entry; + rt_ubase_t ebase = (rt_ubase_t)&__ebase_entry; +#ifdef ARCH_MIPS64 + ebase |= 0xffffffff00000000; +#endif write_c0_ebase(ebase); clear_c0_status(ST0_BEV | ST0_ERL | ST0_EXL); clear_c0_status(ST0_IM | ST0_IE); @@ -114,12 +117,12 @@ int rt_hw_exception_init(void) void rt_general_exc_dispatch(struct pt_regs *regs) { - rt_uint32_t cause, exccode; + rt_ubase_t cause, exccode; exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; if (exccode == 0) { - rt_uint32_t status, pending; + rt_ubase_t status, pending; status = read_c0_status(); pending = (cause & CAUSEF_IP) & (status & ST0_IM); if (pending & CAUSEF_IP0) diff --git a/libcpu/mips/common/exception_gcc.S b/libcpu/mips/common/exception_gcc.S index 176b60e594..9664438ac1 100644 --- a/libcpu/mips/common/exception_gcc.S +++ b/libcpu/mips/common/exception_gcc.S @@ -7,6 +7,11 @@ * Date Author Notes * 2019-12-04 Jiaxun Yang Initial version */ +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ +#endif + +#include .section ".exc_vectors", "ax" .extern tlb_refill_handler @@ -45,15 +50,15 @@ irq_exception: /* general exception handler */ _general_exception_handler: .set noreorder - la $k0, mips_irq_handle - jr $k0 + PTR_LA k0, mips_irq_handle + jr k0 nop .set reorder /* interrupt handler */ _irq_handler: .set noreorder - la $k0, mips_irq_handle - jr $k0 + PTR_LA k0, mips_irq_handle + jr k0 nop .set reorder diff --git a/libcpu/mips/common/mips_addrspace.h b/libcpu/mips/common/mips_addrspace.h index b057e1e917..f3bb60662e 100644 --- a/libcpu/mips/common/mips_addrspace.h +++ b/libcpu/mips/common/mips_addrspace.h @@ -75,6 +75,12 @@ #define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) #define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) +#define KUSEGBASE 0xffffffff00000000 +#define KSEG0BASE 0xffffffff80000000 +#define KSEG1BASE 0xffffffffa0000000 +#define KSEG2BASE 0xffffffffc0000000 +#define KSEG3BASE 0xffffffffe0000000 + #else #define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) @@ -96,8 +102,6 @@ #define CKSEG2 0xc0000000 #define CKSEG3 0xe0000000 -#endif - /* * Memory segments (32bit kernel mode addresses) * These are the traditional names used in the 32-bit universe. @@ -108,6 +112,7 @@ #define KSEG2BASE 0xc0000000 #define KSEG3BASE 0xe0000000 +#endif /* diff --git a/libcpu/mips/common/mips_regs.h b/libcpu/mips/common/mips_regs.h index 7e1359fa33..a7db15d2ad 100644 --- a/libcpu/mips/common/mips_regs.h +++ b/libcpu/mips/common/mips_regs.h @@ -10,13 +10,14 @@ #ifndef _MIPS_REGS_H_ #define _MIPS_REGS_H_ - +#include #define REG_A0 4 #define REG_SP 29 #define REG_GP 28 #define REG_FP 30 #define REG_RA 31 +#ifdef ARCH_MIPS64 #define zero $0 /* wired zero */ #define AT $1 /* assembler temp - uppercase because of ".set at" */ #define v0 $2 /* return value */ @@ -56,6 +57,49 @@ #define s8 $30 /* same like fp! */ #define ra $31 /* return address */ +#else + +#define zero $0 /* wired zero */ +#define AT $at /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value - caller saved */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */ +#define ta0 $8 +#define a5 $9 +#define ta1 $9 +#define a6 $10 +#define ta2 $10 +#define a7 $11 +#define ta3 $11 +#define t0 $12 /* caller saved */ +#define t1 $13 +#define t2 $14 +#define t3 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 /* callee address for PIC/temp */ +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel temporary */ +#define k1 $27 +#define gp $28 /* global pointer - caller saved for PIC */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* callee saved */ +#define ra $31 /* return address */ + +#endif + #define fv0 $f0 /* return value */ #define fv0f $f1 #define fv1 $f2 diff --git a/libcpu/mips/common/ptrace.h b/libcpu/mips/common/ptrace.h index cae57cbf4c..c048959053 100644 --- a/libcpu/mips/common/ptrace.h +++ b/libcpu/mips/common/ptrace.h @@ -14,6 +14,8 @@ #include "asm.h" #include "mips_regs.h" +#define HI_LO_SIZE 4 + #define FP_REG_SIZE 8 #define NUM_FPU_REGS 16 @@ -27,6 +29,7 @@ struct mips_fpu_struct { }; struct pt_regs { +#ifndef ARCH_MIPS64 /* Only O32 Need This! */ /* Pad bytes for argument save space on the stack. */ rt_uint32_t pad0[8]; @@ -41,6 +44,18 @@ struct pt_regs { rt_uint32_t cp0_badvaddr; rt_uint32_t cp0_cause; rt_uint32_t cp0_epc; +#else + /* Saved main processor registers. */ + unsigned long regs[32]; + + /* Saved special registers. */ + rt_uint32_t cp0_status; + rt_uint32_t hi; + rt_uint32_t lo; + unsigned long cp0_badvaddr; + rt_uint32_t cp0_cause; + unsigned long cp0_epc; +#endif #ifdef RT_USING_FPU /* FPU Registers */ @@ -52,7 +67,7 @@ struct pt_regs { #endif /* Note: For call stack o32 ABI has 0x8 shadowsoace Here */ -#define PT_R0 (0x8 * LONGSIZE) /* 0 */ +#define PT_R0 (0x0 * LONGSIZE) /* 0 */ #define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */ #define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */ #define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */ @@ -89,8 +104,8 @@ struct pt_regs { * Saved special registers */ #define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */ -#define PT_HI ((PT_STATUS) + LONGSIZE) /* 33 */ -#define PT_LO ((PT_HI) + LONGSIZE) /* 34 */ +#define PT_HI ((PT_STATUS) + HI_LO_SIZE) /* 33 */ +#define PT_LO ((PT_HI) + HI_LO_SIZE) /* 34 */ #define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */ #define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */ #define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */ @@ -115,9 +130,9 @@ struct pt_regs { #define PT_FPU_R28 ((PT_FPU_R26) + FP_REG_SIZE) #define PT_FPU_R30 ((PT_FPU_R28) + FP_REG_SIZE) #define PT_FPU_FCSR31 ((PT_FPU_R30) + FP_REG_SIZE) -#define PT_FPU_PAD0 ((PT_FPU_FCSR31) + LONGSIZE) +#define PT_FPU_PAD0 ((PT_FPU_FCSR31) + 4) -#define PT_FPU_END ((PT_FPU_PAD0) + LONGSIZE) +#define PT_FPU_END ((PT_FPU_PAD0) + 4) #define PT_SIZE PT_FPU_END #else #define PT_SIZE PT_REG_END diff --git a/libcpu/mips/common/stack.c b/libcpu/mips/common/stack.c index b0e613c7a7..b933b184e7 100644 --- a/libcpu/mips/common/stack.c +++ b/libcpu/mips/common/stack.c @@ -16,8 +16,8 @@ register rt_uint32_t $GP __asm__ ("$28"); rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) { - static rt_uint32_t wSR=0; - static rt_uint32_t wGP; + static rt_ubase_t wSR=0; + static rt_ubase_t wGP; rt_uint8_t *stk; struct pt_regs *pt; @@ -25,26 +25,27 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad rt_uint32_t i; /* Get stack aligned */ - stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); + stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stack_addr, 8); stk -= sizeof(struct pt_regs); pt = (struct pt_regs*)stk; +#ifndef ARCH_MIPS64 for (i = 0; i < 8; ++i) { pt->pad0[i] = 0xdeadbeef; } - +#endif /* Fill Stack register numbers */ for (i = 0; i < 32; ++i) { pt->regs[i] = 0xdeadbeef; } - pt->regs[REG_SP] = (rt_uint32_t)stk; - pt->regs[REG_A0] = (rt_uint32_t)parameter; - pt->regs[REG_GP] = (rt_uint32_t)$GP; - pt->regs[REG_FP] = (rt_uint32_t)0x0; - pt->regs[REG_RA] = (rt_uint32_t)texit; + pt->regs[REG_SP] = (rt_ubase_t)stk; + pt->regs[REG_A0] = (rt_ubase_t)parameter; + pt->regs[REG_GP] = (rt_ubase_t)$GP; + pt->regs[REG_FP] = (rt_ubase_t)0x0; + pt->regs[REG_RA] = (rt_ubase_t)texit; pt->hi = 0x0; pt->lo = 0x0; @@ -53,7 +54,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad pt->cp0_status |= (ST0_CU1 | ST0_FR); #endif pt->cp0_cause = read_c0_cause(); - pt->cp0_epc = (rt_uint32_t)tentry; + pt->cp0_epc = (rt_ubase_t)tentry; pt->cp0_badvaddr = 0x0; return stk; diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h index 77d55f6934..b5a038d1f6 100644 --- a/libcpu/mips/common/stackframe.h +++ b/libcpu/mips/common/stackframe.h @@ -159,11 +159,11 @@ .endm .macro RESTORE_TEMP - LONG_L $24, PT_LO(sp) + lw $24, PT_LO(sp) LONG_L $8, PT_R8(sp) LONG_L $9, PT_R9(sp) mtlo $24 - LONG_L $24, PT_HI(sp) + lw $24, PT_HI(sp) LONG_L $10, PT_R10(sp) LONG_L $11, PT_R11(sp) mthi $24 -- cgit v1.3.1 From c024e2e485c813aa1c70e079f61fe50a80d8215c Mon Sep 17 00:00:00 2001 From: bigmagic Date: Tue, 7 Apr 2020 11:26:30 +0800 Subject: add ls2k bsp config --- bsp/ls2kdev/.config | 9 +++------ bsp/ls2kdev/applications/main.c | 2 +- bsp/ls2kdev/rtconfig.h | 7 +------ libcpu/mips/common/exception.c | 6 +++--- libcpu/mips/common/stackframe.h | 4 ++-- 5 files changed, 10 insertions(+), 18 deletions(-) (limited to 'libcpu/mips/common/stackframe.h') diff --git a/bsp/ls2kdev/.config b/bsp/ls2kdev/.config index 20cf03b625..d8a97b46b0 100644 --- a/bsp/ls2kdev/.config +++ b/bsp/ls2kdev/.config @@ -20,13 +20,10 @@ CONFIG_RT_USING_HOOK=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 CONFIG_IDLE_THREAD_STACK_SIZE=2048 -CONFIG_RT_USING_TIMER_SOFT=y -CONFIG_RT_TIMER_THREAD_PRIO=20 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 +# CONFIG_RT_USING_TIMER_SOFT is not set CONFIG_RT_DEBUG=y # CONFIG_RT_DEBUG_COLOR is not set -CONFIG_RT_DEBUG_INIT_CONFIG=y -CONFIG_RT_DEBUG_INIT=1 +# CONFIG_RT_DEBUG_INIT_CONFIG is not set # CONFIG_RT_DEBUG_THREAD_CONFIG is not set # CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set # CONFIG_RT_DEBUG_IPC_CONFIG is not set @@ -65,7 +62,7 @@ CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_DEVICE_OPS is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLEBUF_SIZE=256 CONFIG_RT_CONSOLE_DEVICE_NAME="uart" CONFIG_RT_VER_NUM=0x40003 # CONFIG_RT_USING_CPU_FFS is not set diff --git a/bsp/ls2kdev/applications/main.c b/bsp/ls2kdev/applications/main.c index 54691f0f89..bd975f4825 100644 --- a/bsp/ls2kdev/applications/main.c +++ b/bsp/ls2kdev/applications/main.c @@ -12,6 +12,6 @@ int main(int argc, char** argv) { - rt_kprintf("ls2k1000:hello rtthread!\n"); + rt_kprintf("Hi, this is RT-Thread!!\n"); return 0; } diff --git a/bsp/ls2kdev/rtconfig.h b/bsp/ls2kdev/rtconfig.h index 80f068c5c0..aaeed71df5 100644 --- a/bsp/ls2kdev/rtconfig.h +++ b/bsp/ls2kdev/rtconfig.h @@ -16,12 +16,7 @@ #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 #define IDLE_THREAD_STACK_SIZE 2048 -#define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 20 -#define RT_TIMER_THREAD_STACK_SIZE 2048 #define RT_DEBUG -#define RT_DEBUG_INIT_CONFIG -#define RT_DEBUG_INIT 1 /* Inter-Thread communication */ @@ -41,7 +36,7 @@ #define RT_USING_DEVICE #define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart" #define RT_VER_NUM 0x40003 #define ARCH_MIPS64 diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c index 11192955cf..cd7d97e6c0 100644 --- a/libcpu/mips/common/exception.c +++ b/libcpu/mips/common/exception.c @@ -117,14 +117,14 @@ int rt_hw_exception_init(void) void rt_general_exc_dispatch(struct pt_regs *regs) { - rt_ubase_t cause, exccode; + rt_ubase_t exccode = 0; - exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; if (exccode == 0) { rt_ubase_t status, pending; status = read_c0_status(); - pending = (cause & CAUSEF_IP) & (status & ST0_IM); + + pending = (CAUSEF_IP) & (status & ST0_IM); if (pending & CAUSEF_IP0) rt_do_mips_cpu_irq(0); if (pending & CAUSEF_IP1) diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h index b5a038d1f6..258f9a994f 100644 --- a/libcpu/mips/common/stackframe.h +++ b/libcpu/mips/common/stackframe.h @@ -60,11 +60,11 @@ mfhi v1 LONG_S $8, PT_R8(sp) LONG_S $9, PT_R9(sp) - LONG_S v1, PT_HI(sp) + sw v1, PT_HI(sp) mflo v1 LONG_S $10, PT_R10(sp) LONG_S $11, PT_R11(sp) - LONG_S v1, PT_LO(sp) + sw v1, PT_LO(sp) LONG_S $12, PT_R12(sp) LONG_S $13, PT_R13(sp) LONG_S $14, PT_R14(sp) -- cgit v1.3.1 From 3d0bdf4bb65bcb676b120ae273c8c28e7f52b911 Mon Sep 17 00:00:00 2001 From: michael Date: Tue, 25 Aug 2020 11:52:07 +0800 Subject: MIPS:improvement FPU support --- libcpu/mips/common/stackframe.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'libcpu/mips/common/stackframe.h') diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h index 258f9a994f..4f1157aebf 100644 --- a/libcpu/mips/common/stackframe.h +++ b/libcpu/mips/common/stackframe.h @@ -22,7 +22,9 @@ #ifdef RT_USING_FPU /* Ensure CU1 (FPU) is enabled */ MFC0 v1, CP0_STATUS - ori v1, ST0_CU1 + lui t1, %hi(ST0_CU1) + addiu t1, t1, %lo(ST0_CU1) + or v1, v1, t1 MTC0 v1, CP0_STATUS SSNOP cfc1 v1, fcr31 @@ -125,11 +127,13 @@ #ifdef RT_USING_FPU /* Ensure CU1 (FPU) is enabled */ MFC0 v1, CP0_STATUS - ori v1, ST0_CU1 + lui t1, %hi(ST0_CU1) + addiu t1, t1, %lo(ST0_CU1) + or v1, v1, t1 MTC0 v1, CP0_STATUS SSNOP LONG_L v1, PT_FPU_FCSR31(sp) - ctc1 v1, fcsr31 + ctc1 v1, fcr31 l.d $f0, PT_FPU_R0(sp) l.d $f2, PT_FPU_R2(sp) l.d $f4, PT_FPU_R4(sp) -- cgit v1.3.1 From bd95f3a94f53d1fd379e659ea9a56789d9fe471d Mon Sep 17 00:00:00 2001 From: bigmagic Date: Wed, 26 Aug 2020 12:03:01 +0800 Subject: fix mips stackframe and exception --- libcpu/Kconfig | 4 ++++ libcpu/mips/common/context_gcc.S | 21 +++++++++++---------- libcpu/mips/common/exception_gcc.S | 8 +++++++- libcpu/mips/common/stackframe.h | 2 ++ 4 files changed, 24 insertions(+), 11 deletions(-) (limited to 'libcpu/mips/common/stackframe.h') diff --git a/libcpu/Kconfig b/libcpu/Kconfig index e355664de2..ae2767dec9 100644 --- a/libcpu/Kconfig +++ b/libcpu/Kconfig @@ -82,6 +82,10 @@ config ARCH_MIPS config ARCH_MIPS64 bool + select ARCH_CPU_64BIT + +config ARCH_CPU_64BIT + bool config ARCH_MIPS_XBURST bool diff --git a/libcpu/mips/common/context_gcc.S b/libcpu/mips/common/context_gcc.S index cdcdede39a..3fdbe374c9 100644 --- a/libcpu/mips/common/context_gcc.S +++ b/libcpu/mips/common/context_gcc.S @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2019-12-04 Jiaxun Yang Initial version + * 2020-07-26 lizhirui Fixed some problems */ #ifndef __ASSEMBLY__ @@ -56,12 +57,12 @@ rt_hw_context_switch_interrupt: bnez t1, _reswitch nop li t1, 0x01 /* set rt_thread_switch_interrupt_flag to 1 */ - sw t1, 0(t0) + LONG_S t1, 0(t0) PTR_LA t0, rt_interrupt_from_thread /* set rt_interrupt_from_thread */ - sw a0, 0(t0) + LONG_S a0, 0(t0) _reswitch: PTR_LA t0, rt_interrupt_to_thread /* set rt_interrupt_to_thread */ - sw a1, 0(t0) + LONG_S a1, 0(t0) jr ra nop @@ -97,24 +98,24 @@ mips_irq_handle: * rt_hw_context_switch_interrupt_do and do not return */ PTR_LA k0, rt_thread_switch_interrupt_flag - lw k1, 0(k0) + LONG_L k1, 0(k0) beqz k1, spurious_interrupt nop - sw zero, 0(k0) /* clear flag */ + LONG_S zero, 0(k0) /* clear flag */ nop /* * switch to the new thread */ PTR_LA k0, rt_interrupt_from_thread - lw k1, 0(k0) + LONG_L k1, 0(k0) nop - sw sp, 0(k1) /* store sp in preempted task TCB */ + LONG_S sp, 0(k1) /* store sp in preempted task TCB */ PTR_LA k0, rt_interrupt_to_thread - lw k1, 0(k0) + LONG_L k1, 0(k0) nop - lw sp, 0(k1) /* get new task stack pointer */ + LONG_L sp, 0(k1) /* get new task stack pointer */ j spurious_interrupt nop diff --git a/libcpu/mips/common/exception_gcc.S b/libcpu/mips/common/exception_gcc.S index 9664438ac1..c685928a84 100644 --- a/libcpu/mips/common/exception_gcc.S +++ b/libcpu/mips/common/exception_gcc.S @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2020, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2019-12-04 Jiaxun Yang Initial version + * 2020-07-26 lizhirui Add xtlb exception entry */ #ifndef __ASSEMBLY__ #define __ASSEMBLY__ @@ -26,6 +27,11 @@ tlb_refill_exception: b _general_exception_handler nop + /* 0x080 - XTLB refill handler */ + .org ebase_start + 0x080 + b _general_exception_handler + nop + /* 0x100 - Cache error handler */ .org ebase_start + 0x100 j cache_error_handler diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h index 4f1157aebf..bb92a18c9c 100644 --- a/libcpu/mips/common/stackframe.h +++ b/libcpu/mips/common/stackframe.h @@ -206,6 +206,8 @@ li v1, ~(ST0_CU1 | ST0_FR | ST0_IM) and v0, v1 or v0, a0 + li v1, (ST0_KX | ST0_SX | ST0_UX) + or v0, v1 mtc0 v0, CP0_STATUS LONG_L v1, PT_EPC(sp) MTC0 v1, CP0_EPC -- cgit v1.3.1