From 2d0974908659bd41d748e69fac0166c37b15cb02 Mon Sep 17 00:00:00 2001 From: Shell Date: Tue, 14 Feb 2023 23:08:32 +0800 Subject: [rt-smart] PV_OFFSET as a variable (#6904) * [rt-smart/mem] remove pv_offset * [rt-smart] list kernel space command * [rt-smart] restore ioremap region * [revert] restore kernel space isolation * [rt-smart/pv_off] code format * [rt-smart] add get_pvoff() * [pvoffset] pvoff as constant for C codes * [pvoff] pvoff as interfaces --- libcpu/Kconfig | 7 ------ libcpu/aarch64/common/mmu.c | 9 ++++++- libcpu/aarch64/common/mmu.h | 2 +- libcpu/aarch64/common/trap.c | 1 + libcpu/aarch64/cortex-a/entry_point.S | 44 ++++++++++++++++------------------- libcpu/arm/cortex-a/mmu.c | 3 ++- libcpu/arm/cortex-a/start_gcc.S | 20 ++++++++++++---- libcpu/risc-v/t-head/c906/mmu.c | 4 +++- libcpu/risc-v/virt64/mmu.c | 5 +++- 9 files changed, 55 insertions(+), 40 deletions(-) (limited to 'libcpu') diff --git a/libcpu/Kconfig b/libcpu/Kconfig index 616600b179..17a57199b9 100644 --- a/libcpu/Kconfig +++ b/libcpu/Kconfig @@ -87,13 +87,6 @@ config KERNEL_VADDR_START default 0x80000000 if ARCH_RISCV depends on ARCH_MM_MMU -config PV_OFFSET - hex "The offset of kernel physical address and virtural address" - default 0x1000040000000 if ARCH_ARMV8 - default 0xa0000000 if ARCH_ARM - default 0x0 if ARCH_RISCV - depends on ARCH_MM_MMU - config RT_IOREMAP_LATE bool "Support to create IO mapping in the kernel address space after system initlalization." default n diff --git a/libcpu/aarch64/common/mmu.c b/libcpu/aarch64/common/mmu.c index d567d111d9..b175450dc7 100644 --- a/libcpu/aarch64/common/mmu.c +++ b/libcpu/aarch64/common/mmu.c @@ -309,6 +309,9 @@ void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr) mdesc->vaddr_start + 1, .prefer = (void *)mdesc->vaddr_start}; + if (mdesc->paddr_start == (rt_size_t)ARCH_MAP_FAILED) + mdesc->paddr_start = mdesc->vaddr_start + PV_OFFSET; + rt_aspace_map_phy_static(aspace, &mdesc->varea, &hint, attr, mdesc->paddr_start >> MM_PAGE_SHIFT, &err); mdesc++; @@ -656,10 +659,14 @@ int rt_hw_mmu_control(struct rt_aspace *aspace, void *vaddr, size_t size, return err; } -void rt_hw_mmu_setup_early(unsigned long *tbl0, unsigned long *tbl1, +void rt_hw_mem_setup_early(unsigned long *tbl0, unsigned long *tbl1, unsigned long size, unsigned long pv_off) { int ret; + + /* setup pv off */ + rt_kmem_pvoff_set(pv_off); + unsigned long va = KERNEL_VADDR_START; unsigned long count = (size + ARCH_SECTION_MASK) >> ARCH_SECTION_SHIFT; unsigned long normal_attr = MMU_MAP_CUSTOM(MMU_AP_KAUN, NORMAL_MEM); diff --git a/libcpu/aarch64/common/mmu.h b/libcpu/aarch64/common/mmu.h index 6dc8cdca31..912ee6fdb9 100644 --- a/libcpu/aarch64/common/mmu.h +++ b/libcpu/aarch64/common/mmu.h @@ -74,7 +74,7 @@ struct mem_desc struct rt_aspace; void rt_hw_mmu_ktbl_set(unsigned long tbl); -void rt_hw_mmu_setup_early(unsigned long *tbl0, unsigned long *tbl1, +void rt_hw_mem_setup_early(unsigned long *tbl0, unsigned long *tbl1, unsigned long size, unsigned long pv_off); void rt_hw_mmu_setup(struct rt_aspace *aspace, struct mem_desc *mdesc, int desc_nr); diff --git a/libcpu/aarch64/common/trap.c b/libcpu/aarch64/common/trap.c index 0a2dd2e9ed..7527440f9f 100644 --- a/libcpu/aarch64/common/trap.c +++ b/libcpu/aarch64/common/trap.c @@ -45,6 +45,7 @@ void check_user_fault(struct rt_hw_exp_stack *regs, uint32_t pc_adj, char *info) #ifdef LWP_USING_CORE_DUMP lwp_core_dump(regs, pc_adj); #endif + backtrace((unsigned long)regs->pc, (unsigned long)regs->x30, (unsigned long)regs->x29); sys_exit(-1); } } diff --git a/libcpu/aarch64/cortex-a/entry_point.S b/libcpu/aarch64/cortex-a/entry_point.S index 89c383a1e5..a73b420781 100644 --- a/libcpu/aarch64/cortex-a/entry_point.S +++ b/libcpu/aarch64/cortex-a/entry_point.S @@ -78,12 +78,12 @@ __start: eret /* exception return. from EL2. continue from .L__in_el1 */ +.macro GET_PHY reg, symbol + adrp \reg, \symbol + add \reg, \reg, #:lo12:\symbol +.endm + .L__in_el1: -#ifdef RT_USING_LWP - ldr x9, =PV_OFFSET -#else - mov x9, #0 -#endif mov sp, x1 /* in EL1. Set sp to _start */ /* Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction */ @@ -91,15 +91,13 @@ __start: msr cpacr_el1, x1 /* clear bss */ - adrp x1, __bss_start /* get bss start address */ - add x1, x1, #:lo12:__bss_start - adrp x2, __bss_end - add x1, x1, #:lo12:__bss_end - sub x2, x2, x1 /* get bss size */ + GET_PHY x1, __bss_start + GET_PHY x2, __bss_end + sub x2, x2, x1 /* get bss size */ - and x3, x2, #7 /* x3 is < 7 */ + and x3, x2, #7 /* x3 is < 7 */ ldr x4, =~0x7 - and x2, x2, x4 /* mask ~7 */ + and x2, x2, x4 /* mask ~7 */ .L__clean_bss_loop: cbz x2, .L__clean_bss_loop_1 @@ -116,7 +114,7 @@ __start: .L__jump_to_entry: /* jump to C code, should not return */ bl mmu_tcr_init - adr x1, __start + adr x1, __start /* install early page table */ ldr x0, =~0x1fffff and x0, x1, x0 add x1, x0, #0x1000 @@ -125,11 +123,13 @@ __start: msr ttbr1_el1, x1 dsb sy - ldr x2, =0x40000000 /* map 1G memory for kernel space */ -#ifdef RT_USING_LWP - ldr x3, =PV_OFFSET +#ifdef RT_USING_SMART + ldr x2, =__start + GET_PHY x3, __start + sub x3, x3, x2 #endif - bl rt_hw_mmu_setup_early + ldr x2, =0x40000000 /* map 1G memory for kernel space */ + bl rt_hw_mem_setup_early ldr x30, =after_mmu_enable /* set LR to after_mmu_enable function, it's a v_addr */ @@ -152,7 +152,7 @@ __start: ret after_mmu_enable: -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART mrs x0, tcr_el1 /* disable ttbr0, only using kernel space */ orr x0, x0, #(1 << 7) msr tcr_el1, x0 @@ -172,7 +172,7 @@ after_mmu_enable: * secondary cpu */ -.globl _secondary_cpu_entry +.global _secondary_cpu_entry _secondary_cpu_entry: bl rt_hw_cpu_id_set adr x1, __start @@ -225,10 +225,6 @@ _secondary_cpu_entry: eret /* exception return. from EL2. continue from .L__in_el1 */ .L__in_el1_cpux: - adr x19, .L__in_el1_cpux - ldr x8, =.L__in_el1_cpux - sub x19, x19, x8 /* get PV_OFFSET */ - mrs x0, tpidr_el1 /* each cpu init stack is 8k */ sub x1, x1, x0, lsl #13 @@ -244,7 +240,7 @@ _secondary_cpu_entry: bl mmu_tcr_init - adr x1, __start + adr x1, __start /* GET & setup early page table */ ldr x0, =~0x1fffff and x0, x1, x0 add x1, x0, #0x1000 diff --git a/libcpu/arm/cortex-a/mmu.c b/libcpu/arm/cortex-a/mmu.c index 150dd98b27..12d441d8e9 100644 --- a/libcpu/arm/cortex-a/mmu.c +++ b/libcpu/arm/cortex-a/mmu.c @@ -24,7 +24,6 @@ #include "ioremap.h" #else #define KERNEL_VADDR_START 0 -#define PV_OFFSET 0 #endif /* level1 page table, each entry for 1MB memory. */ @@ -59,6 +58,8 @@ void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size) /* set page table */ for(; size > 0; size--) { + if (mdesc->paddr_start == (rt_uint32_t)ARCH_MAP_FAILED) + mdesc->paddr_start = mdesc->vaddr_start + PV_OFFSET; rt_hw_mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end, mdesc->paddr_start, mdesc->attr); mdesc++; diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S index 94f96468fa..b1cddebe0b 100644 --- a/libcpu/arm/cortex-a/start_gcc.S +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -102,7 +102,10 @@ continue: isb #ifdef RT_USING_SMART - ldr r5, =PV_OFFSET + /* load r5 with PV_OFFSET */ + ldr r7, =_reset + adr r5, _reset + sub r5, r5, r7 mov r7, #0x100000 sub r7, #1 @@ -166,6 +169,9 @@ bss_loop: strlo r0,[r1],#4 /* clear 4 bytes */ blo bss_loop /* loop until done */ + mov r0, r5 + bl rt_kmem_pvoff_set + #ifdef RT_USING_SMP mrc p15, 0, r1, c1, c0, 1 mov r0, #(1<<6) @@ -173,7 +179,10 @@ bss_loop: mcr p15, 0, r1, c1, c0, 1 /* enable smp */ #endif - /* initialize the mmu table and enable mmu */ + /** + * void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size) + * initialize the mmu table and enable mmu + */ ldr r0, =platform_mem_desc ldr r1, =platform_mem_desc_size ldr r1, [r1] @@ -595,16 +604,19 @@ vector_resv: bl rt_hw_trap_resv b . -#ifdef RT_USING_SMP .global rt_hw_clz rt_hw_clz: clz r0, r0 bx lr +#ifdef RT_USING_SMP + .global rt_secondary_cpu_entry rt_secondary_cpu_entry: #ifdef RT_USING_SMART - ldr r5, =PV_OFFSET + ldr r0, =_reset + adr r5, _reset + sub r5, r5, r0 ldr lr, =after_enable_mmu_n ldr r0, =init_mtbl diff --git a/libcpu/risc-v/t-head/c906/mmu.c b/libcpu/risc-v/t-head/c906/mmu.c index dc3ba0cfdd..cc696ec6cb 100644 --- a/libcpu/risc-v/t-head/c906/mmu.c +++ b/libcpu/risc-v/t-head/c906/mmu.c @@ -30,7 +30,6 @@ #endif #ifndef RT_USING_SMART -#define PV_OFFSET 0 #define USER_VADDR_START 0 #endif @@ -533,6 +532,9 @@ void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr) mdesc->vaddr_start + 1, .prefer = (void *)mdesc->vaddr_start}; + if (mdesc->paddr_start == (rt_size_t)ARCH_MAP_FAILED) + mdesc->paddr_start = mdesc->vaddr_start + PV_OFFSET; + rt_aspace_map_phy_static(aspace, &mdesc->varea, &hint, attr, mdesc->paddr_start >> MM_PAGE_SHIFT, &err); mdesc++; diff --git a/libcpu/risc-v/virt64/mmu.c b/libcpu/risc-v/virt64/mmu.c index 6752ff306c..6d4cc6463e 100644 --- a/libcpu/risc-v/virt64/mmu.c +++ b/libcpu/risc-v/virt64/mmu.c @@ -25,12 +25,12 @@ #include #ifdef RT_USING_SMART +#include #include #include #endif #ifndef RT_USING_SMART -#define PV_OFFSET 0 #define USER_VADDR_START 0 #endif @@ -476,6 +476,9 @@ void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr) mdesc->vaddr_start + 1, .prefer = (void *)mdesc->vaddr_start}; + if (mdesc->paddr_start == (rt_size_t)ARCH_MAP_FAILED) + mdesc->paddr_start = mdesc->vaddr_start + PV_OFFSET; + rt_aspace_map_phy_static(aspace, &mdesc->varea, &hint, attr, mdesc->paddr_start >> MM_PAGE_SHIFT, &err); mdesc++; -- cgit v1.3.1