From ee61d78b184040327dbe83f2941932bd15b8e9c5 Mon Sep 17 00:00:00 2001
From: duhuanpeng <548708880@qq.com>
Date: Wed, 25 Mar 2020 23:12:22 +0800
Subject: MIPS: inline routine should be static here

gcc will remove this "unused" routine and cause a linking error.
symbol not found when linking.

Signed-off-by: duhuanpeng <548708880@qq.com>
---
 libcpu/mips/common/mips_fpu.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/mips/common/mips_fpu.h b/libcpu/mips/common/mips_fpu.h
index d6351f7655..50df3746a5 100644
--- a/libcpu/mips/common/mips_fpu.h
+++ b/libcpu/mips/common/mips_fpu.h
@@ -18,7 +18,7 @@
  * init hardware FPU
  */
 #ifdef RT_USING_FPU
-inline void rt_hw_fpu_init(void)
+rt_inline void rt_hw_fpu_init(void)
 {
     rt_uint32_t c0_status = 0;
     rt_uint32_t c1_status = 0;
@@ -38,7 +38,7 @@ inline void rt_hw_fpu_init(void)
     return ;
 }
 #else
-    inline void rt_hw_fpu_init(void){} /* Do nothing */
+    rt_inline void rt_hw_fpu_init(void){} /* Do nothing */
 #endif
 
 #endif
-- 
cgit v1.3.1


From f295149f20e2c1f29c8321929d0e56721fe91ac2 Mon Sep 17 00:00:00 2001
From: duhuanpeng <548708880@qq.com>
Date: Fri, 3 Apr 2020 20:32:07 +0800
Subject: MIPS: fix inline assembly for FPU

Signed-off-by: duhuanpeng <548708880@qq.com>
---
 libcpu/mips/common/mips_regs.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'libcpu')

diff --git a/libcpu/mips/common/mips_regs.h b/libcpu/mips/common/mips_regs.h
index c5dd727e23..a13e24b539 100644
--- a/libcpu/mips/common/mips_regs.h
+++ b/libcpu/mips/common/mips_regs.h
@@ -999,7 +999,7 @@ do {									\
 
 #define write_32bit_cp0_set1_register(register,value)           \
         __asm__ __volatile__(                                   \
-        "ctc0\t%0,"STR(register)"\n\t"				\
+        "ctc0\t%0,$"STR(register)"\n\t"				\
     "nop"							\
         : : "r" (value));
 
@@ -1037,14 +1037,14 @@ do {									\
     __asm__ __volatile__(                                   \
     ".set\tpush\n\t"					\
     ".set\treorder\n\t"					\
-        "cfc1\t%0,"STR(source)"\n\t"                            \
+        "cfc1\t%0,$"STR(source)"\n\t"                            \
     ".set\tpop"						\
         : "=r" (__res));                                        \
         __res;})
 
 #define write_32bit_cp1_register(register,value)                \
         __asm__ __volatile__(                                   \
-        "ctc1\t%0,"STR(register)"\n\t"				\
+        "ctc1\t%0,$"STR(register)"\n\t"				\
     "nop"							\
         : : "r" (value));
 
-- 
cgit v1.3.1


From b3c7bc964bdab9a4ff04f06e9cfb85bd2f9c6107 Mon Sep 17 00:00:00 2001
From: Jonne <qzhang1535@gmail.com>
Date: Fri, 10 Apr 2020 21:40:33 +0800
Subject: 更新mini2440 bsp包: 1、加入Kconfig以支持图形化菜单配置
 2、编译脚本中添加动态模块编译参数 3、开启自动初始化机制支持
 4、重构串口驱动以解决开启posix支持后终端无响应问题 5、解决dm9000网卡驱动link
 up问题 6、添加mnt.c文件用来挂载文件系统
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 bsp/mini2440/.config                    | 513 ++++++++++++++++++++++++++++++++
 bsp/mini2440/Kconfig                    |  28 ++
 bsp/mini2440/SConstruct                 |   4 +-
 bsp/mini2440/applications/application.c | 252 ----------------
 bsp/mini2440/applications/main.c        |  28 ++
 bsp/mini2440/applications/mnt.c         |  23 ++
 bsp/mini2440/applications/startup.c     | 165 ----------
 bsp/mini2440/drivers/SConscript         |   4 +-
 bsp/mini2440/drivers/board.c            | 154 +++-------
 bsp/mini2440/drivers/board.h            |   1 -
 bsp/mini2440/drivers/console.c          | 180 -----------
 bsp/mini2440/drivers/dm9000.c           |   7 +-
 bsp/mini2440/drivers/dm9000.h           |   2 +-
 bsp/mini2440/drivers/key.c              |   2 +-
 bsp/mini2440/drivers/sdcard.c           |   9 +-
 bsp/mini2440/drivers/touch.c            |   2 +-
 bsp/mini2440/drivers/uart.c             | 183 ++++++++++++
 bsp/mini2440/rtconfig.h                 | 359 +++++++++++++---------
 bsp/mini2440/rtconfig.py                |  13 +-
 libcpu/arm/s3c24x0/serial.c             | 291 ------------------
 libcpu/arm/s3c24x0/serial.h             |  66 ----
 21 files changed, 1063 insertions(+), 1223 deletions(-)
 create mode 100644 bsp/mini2440/.config
 create mode 100644 bsp/mini2440/Kconfig
 delete mode 100644 bsp/mini2440/applications/application.c
 create mode 100644 bsp/mini2440/applications/main.c
 create mode 100644 bsp/mini2440/applications/mnt.c
 delete mode 100644 bsp/mini2440/applications/startup.c
 delete mode 100644 bsp/mini2440/drivers/console.c
 create mode 100644 bsp/mini2440/drivers/uart.c
 delete mode 100644 libcpu/arm/s3c24x0/serial.c
 delete mode 100644 libcpu/arm/s3c24x0/serial.h

(limited to 'libcpu')

diff --git a/bsp/mini2440/.config b/bsp/mini2440/.config
new file mode 100644
index 0000000000..e10689caa8
--- /dev/null
+++ b/bsp/mini2440/.config
@@ -0,0 +1,513 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+CONFIG_BOARD_MINI2440=y
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_MEMHEAP=y
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
+CONFIG_RT_VER_NUM=0x40003
+CONFIG_ARCH_ARM=y
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_ARM_ARM9=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+CONFIG_RT_USING_CPLUSPLUS=y
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=5
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=5
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_RT_USING_DFS_ELMFAT=y
+
+#
+# elm-chan's FatFs, Generic FAT Filesystem Module
+#
+CONFIG_RT_DFS_ELM_CODE_PAGE=437
+CONFIG_RT_DFS_ELM_WORD_ACCESS=y
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+CONFIG_RT_DFS_ELM_USE_LFN_3=y
+CONFIG_RT_DFS_ELM_USE_LFN=3
+CONFIG_RT_DFS_ELM_MAX_LFN=255
+CONFIG_RT_DFS_ELM_DRIVES=2
+CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512
+# CONFIG_RT_DFS_ELM_USE_ERASE is not set
+CONFIG_RT_DFS_ELM_REENTRANT=y
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+CONFIG_RT_USING_DFS_RAMFS=y
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+# CONFIG_RT_USING_DFS_NFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+CONFIG_RT_USING_PTHREADS=y
+CONFIG_PTHREAD_NUM_MAX=8
+CONFIG_RT_USING_POSIX=y
+CONFIG_RT_USING_POSIX_MMAP=y
+CONFIG_RT_USING_POSIX_TERMIOS=y
+CONFIG_RT_USING_POSIX_AIO=y
+CONFIG_RT_USING_MODULE=y
+CONFIG_RT_USING_CUSTOM_DLMODULE=y
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+CONFIG_RT_USING_SAL=y
+
+#
+# protocol stack implement
+#
+CONFIG_SAL_USING_LWIP=y
+CONFIG_SAL_USING_POSIX=y
+
+#
+# Network interface device
+#
+CONFIG_RT_USING_NETDEV=y
+CONFIG_NETDEV_USING_IFCONFIG=y
+CONFIG_NETDEV_USING_PING=y
+CONFIG_NETDEV_USING_NETSTAT=y
+CONFIG_NETDEV_USING_AUTO_DEFAULT=y
+# CONFIG_NETDEV_USING_IPV6 is not set
+CONFIG_NETDEV_IPV4=1
+CONFIG_NETDEV_IPV6=0
+# CONFIG_NETDEV_IPV6_SCOPES is not set
+
+#
+# light weight TCP/IP stack
+#
+CONFIG_RT_USING_LWIP=y
+# CONFIG_RT_USING_LWIP141 is not set
+# CONFIG_RT_USING_LWIP202 is not set
+CONFIG_RT_USING_LWIP210=y
+# CONFIG_RT_USING_LWIP_IPV6 is not set
+CONFIG_RT_LWIP_IGMP=y
+CONFIG_RT_LWIP_ICMP=y
+# CONFIG_RT_LWIP_SNMP is not set
+CONFIG_RT_LWIP_DNS=y
+CONFIG_RT_LWIP_DHCP=y
+CONFIG_IP_SOF_BROADCAST=1
+CONFIG_IP_SOF_BROADCAST_RECV=1
+
+#
+# Static IPv4 Address
+#
+CONFIG_RT_LWIP_IPADDR="192.168.0.30"
+CONFIG_RT_LWIP_GWADDR="192.168.0.1"
+CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
+CONFIG_RT_LWIP_UDP=y
+CONFIG_RT_LWIP_TCP=y
+CONFIG_RT_LWIP_RAW=y
+# CONFIG_RT_LWIP_PPP is not set
+CONFIG_RT_MEMP_NUM_NETCONN=8
+CONFIG_RT_LWIP_PBUF_NUM=16
+CONFIG_RT_LWIP_RAW_PCB_NUM=4
+CONFIG_RT_LWIP_UDP_PCB_NUM=4
+CONFIG_RT_LWIP_TCP_PCB_NUM=4
+CONFIG_RT_LWIP_TCP_SEG_NUM=40
+CONFIG_RT_LWIP_TCP_SND_BUF=8196
+CONFIG_RT_LWIP_TCP_WND=8196
+CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
+CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
+CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
+# CONFIG_LWIP_NO_RX_THREAD is not set
+# CONFIG_LWIP_NO_TX_THREAD is not set
+CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
+CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
+CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
+# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
+CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
+CONFIG_LWIP_NETIF_LINK_CALLBACK=1
+CONFIG_SO_REUSE=1
+CONFIG_LWIP_SO_RCVTIMEO=1
+CONFIG_LWIP_SO_SNDTIMEO=1
+CONFIG_LWIP_SO_RCVBUF=1
+CONFIG_RT_LWIP_NETIF_LOOPBACK=y
+CONFIG_LWIP_NETIF_LOOPBACK=1
+CONFIG_RT_LWIP_STATS=y
+# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
+CONFIG_RT_LWIP_USING_PING=y
+# CONFIG_RT_LWIP_DEBUG is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+# CONFIG_LWIP_USING_DHCPD is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+CONFIG_RT_USING_RYM=y
+CONFIG_YMODEM_USING_CRC_TABLE=y
+CONFIG_YMODEM_USING_FILE_TRANSFER=y
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_LWP is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
diff --git a/bsp/mini2440/Kconfig b/bsp/mini2440/Kconfig
new file mode 100644
index 0000000000..44da5183eb
--- /dev/null
+++ b/bsp/mini2440/Kconfig
@@ -0,0 +1,28 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+config BOARD_MINI2440
+    bool "mini2440"
+    select ARCH_ARM_ARM9
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+
diff --git a/bsp/mini2440/SConstruct b/bsp/mini2440/SConstruct
index a89673811c..93120f79ec 100644
--- a/bsp/mini2440/SConstruct
+++ b/bsp/mini2440/SConstruct
@@ -27,8 +27,8 @@ Export('rtconfig')
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT)
 
-if GetDepend('RT_USING_RTGUI'):
-    objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
+#if GetDepend('RT_USING_RTGUI'):
+#    objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
 
 # libc testsuite 
 # objs = objs + SConscript(RTT_ROOT + '/examples/libc/SConscript', variant_dir='build/examples/libc', duplicate=0)
diff --git a/bsp/mini2440/applications/application.c b/bsp/mini2440/applications/application.c
deleted file mode 100644
index 89dbfb6b19..0000000000
--- a/bsp/mini2440/applications/application.c
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author		Notes
- * 2007-11-20     Yi.Qiu		add rtgui application
- * 2008-6-28      Bernard		no rtgui init
- */
-
-/**
- * @addtogroup mini2440
- */
- 
-/*@{*/
-
-#include <rtthread.h>
-#include "touch.h"
-#include "lcd.h"
-#include "led.h"
-#include "dm9000.h"
-
-#ifdef RT_USING_DFS
-/* dfs filesystem:ELM FatFs filesystem init */
-#include <dfs_elm.h>
-/* dfs Filesystem APIs */
-#include <dfs_fs.h>
-#ifdef RT_USING_DFS_UFFS
-/* dfs filesystem:UFFS filesystem init */
-#include <dfs_uffs.h>
-#endif
-#endif
-
-#ifdef RT_USING_LWIP
-#include <netif/ethernetif.h>
-#endif
-
-#ifdef RT_USING_RTGUI
-#include <rtgui/rtgui.h>
-#endif
-
-#ifdef RT_USING_FTK
-#include "ftk.h"
-#endif
-
-#define RT_INIT_THREAD_STACK_SIZE (2*1024)
-
-#ifdef RT_USING_DFS_ROMFS
-#include <dfs_romfs.h>
-#endif
-
-#ifdef RT_USING_FTK
-static int argc = 1;
-static char* argv[] = {"ftk", NULL};
-
-void rt_ftk_thread_entry(void *parameter)
-{
-	int FTK_MAIN(int argc, char *argv[]);
-
-	FTK_MAIN(argc, argv);
-
-	return;
-}
-
-#endif
-
-void rt_init_thread_entry(void *parameter)
-{
-/* Filesystem Initialization */
-#ifdef RT_USING_DFS
-	{
-		/* init the device filesystem */
-		dfs_init();
-
-#if defined(RT_USING_DFS_ELMFAT)
-		/* init the elm chan FatFs filesystam*/
-		elm_init();
-		/* mount sd card fat partition 1 as root directory */
-		if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
-		{
-			rt_kprintf("File System initialized!\n");
-		}
-		else
-			rt_kprintf("File System initialzation failed!\n");
-#endif
-
-#if defined(RT_USING_DFS_ROMFS)
-		dfs_romfs_init();
-		if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
-		{
-			rt_kprintf("ROM File System initialized!\n");
-		}
-		else
-			rt_kprintf("ROM File System initialzation failed!\n");
-#endif
-
-#if defined(RT_USING_DFS_DEVFS)
-		devfs_init();
-		if (dfs_mount(RT_NULL, "/dev", "devfs", 0, 0) == 0)
-			rt_kprintf("Device File System initialized!\n");
-		else
-			rt_kprintf("Device File System initialzation failed!\n");
-
-		#ifdef RT_USING_NEWLIB
-		/* init libc */
-		libc_system_init("uart0");
-		#endif
-#endif
-
-#if defined(RT_USING_DFS) && defined(RT_USING_LWIP) && defined(RT_USING_DFS_NFS)
-		/* NFSv3 Initialization */
-		nfs_init();
-
-		if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
-			rt_kprintf("NFSv3 File System initialized!\n");
-		else
-			rt_kprintf("NFSv3 File System initialzation failed!\n");
-#endif
-
-#if defined(RT_USING_DFS_UFFS)
-		/* init the uffs filesystem */
-		dfs_uffs_init();
-
-		/* mount flash device as flash directory */
-		if (dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
-			rt_kprintf("UFFS File System initialized!\n");
-		else
-			rt_kprintf("UFFS File System initialzation failed!\n");
-#endif
-	}
-#endif
-
-#ifdef RT_USING_RTGUI
-	{
-		extern void rtgui_system_server_init(void);
-
-		rt_device_t lcd;
-		
-		/* init lcd */
-		rt_hw_lcd_init();
-			
-		/* init touch panel */
-		rtgui_touch_hw_init();	
-
-		/* init keypad */
-		rt_hw_key_init();
-
-		/* find lcd device */
-		lcd = rt_device_find("lcd");
-
-		/* set lcd device as rtgui graphic driver */		
-		rtgui_graphic_set_device(lcd);
-
-		/* initalize rtgui system server */
-		rtgui_system_server_init();
-	}
-#endif
-
-/* LwIP Initialization */
-#ifdef RT_USING_LWIP
-	{
-		extern void lwip_sys_init(void);
-		eth_system_device_init();
-
-		/* register ethernetif device */
-		rt_hw_dm9000_init();
-
-		/* init lwip system */
-		lwip_sys_init();
-		rt_kprintf("TCP/IP initialized!\n");
-	}
-#endif
-
-#ifdef RT_USING_FTK
-	{
-		rt_thread_t ftk_thread;
-
-		/* init lcd */
-		rt_hw_lcd_init();
-
-		/* init touch panel */
-		rtgui_touch_hw_init();	
-
-		/* init keypad */
-		rt_hw_key_init();
-
-		/* create ftk thread */
-		ftk_thread = rt_thread_create("ftk",
-									rt_ftk_thread_entry, RT_NULL,
-									10 * 1024, 8, 20);	
-
-		/* startup ftk thread */
-		if (ftk_thread != RT_NULL)
-			rt_thread_startup(ftk_thread);		
-	}
-#endif
-}
-
-void rt_led_thread_entry(void *parameter)
-{
-	while (1)
-	{
-		/* light on leds for one second */
-		rt_hw_led_on(LED2|LED3);
-		rt_hw_led_off(LED1|LED4);
-		rt_thread_delay(100);
-
-		/* light off leds for one second */
-		rt_hw_led_off(LED2|LED3);
-		rt_hw_led_on(LED1|LED4);
-		rt_thread_delay(100);
-	}
-}
-
-int rt_application_init(void)
-{
-	rt_thread_t init_thread;
-	rt_thread_t led_thread;
-
-#if (RT_THREAD_PRIORITY_MAX == 32)
-	init_thread = rt_thread_create("init",
-								rt_init_thread_entry, RT_NULL,
-								RT_INIT_THREAD_STACK_SIZE, 8, 20);
-
-	led_thread = rt_thread_create("led",
-								rt_led_thread_entry, RT_NULL,
-								512, 20, 20);
-#else
-	init_thread = rt_thread_create("init",
-								rt_init_thread_entry, RT_NULL,
-								RT_INIT_THREAD_STACK_SIZE, 80, 20);
-
-	led_thread = rt_thread_create("led",
-								rt_led_thread_entry, RT_NULL,
-								512, 200, 20);
-#endif
-
-	if (init_thread != RT_NULL)
-		rt_thread_startup(init_thread);
-
-	if (led_thread != RT_NULL)
-		rt_thread_startup(led_thread);
-
-	return 0;
-}
-
-/*@}*/
diff --git a/bsp/mini2440/applications/main.c b/bsp/mini2440/applications/main.c
new file mode 100644
index 0000000000..a67ff93f7a
--- /dev/null
+++ b/bsp/mini2440/applications/main.c
@@ -0,0 +1,28 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <rtthread.h>
+
+#include "led.h"
+
+int main(void)
+{
+    printf("hello rt-thread\n");
+
+    while (1)
+    {
+        /* light on leds for one second */
+        rt_hw_led_on(LED2|LED3);
+        rt_hw_led_off(LED1|LED4);
+        rt_thread_delay(100);
+    
+        /* light off leds for one second */
+        rt_hw_led_off(LED2|LED3);
+        rt_hw_led_on(LED1|LED4);
+        rt_thread_delay(100);
+    }   
+
+    return 0;
+}
+
+
diff --git a/bsp/mini2440/applications/mnt.c b/bsp/mini2440/applications/mnt.c
new file mode 100644
index 0000000000..fc9f915167
--- /dev/null
+++ b/bsp/mini2440/applications/mnt.c
@@ -0,0 +1,23 @@
+#include <rtthread.h>
+
+#ifdef RT_USING_DFS
+#include <dfs_fs.h>
+#include "dfs_ramfs.h"
+
+int mnt_init(void)
+{
+
+    if(dfs_mount(RT_NULL, "/", "ram", 0, dfs_ramfs_create(rt_malloc(1024),1024)) == 0)
+    {
+        rt_kprintf("RAM file system initializated!\n");
+    }
+    else
+    {
+        rt_kprintf("RAM file system initializate failed!\n");
+    }
+
+    return 0;
+}
+INIT_ENV_EXPORT(mnt_init);
+#endif
+
diff --git a/bsp/mini2440/applications/startup.c b/bsp/mini2440/applications/startup.c
deleted file mode 100644
index fab223d834..0000000000
--- a/bsp/mini2440/applications/startup.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2006-02-26     Bernard      first implementation
- * 2006-05-05     Bernard      add two test thread
- * 2006-08-10     Bernard      use rt_show_version to display version information
- * 2008-07-14     Bernard      modify the heap memory init parameter
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include <s3c24x0.h>
-#ifdef RT_USING_FINSH
-#include <finsh.h>
-#endif
-
-extern void rt_hw_interrupt_init(void);
-extern void rt_hw_board_init(void);
-extern void rt_hw_rtc_init(void);
-extern void rt_serial_init(void);
-extern void rt_system_timer_init(void);
-extern void rt_system_scheduler_init(void);
-extern void rt_thread_idle_init(void);
-extern void rt_hw_cpu_icache_enable(void);
-extern void rt_show_version(void);
-extern void rt_system_heap_init(void*, void*);
-extern void rt_hw_finsh_init(void);
-extern void rt_application_init(void);
-
-extern struct serial_device uart0;
-extern struct rt_device uart0_device;
-extern struct serial_device uart2;
-extern struct rt_device uart2_device;
-
-/**
- * @addtogroup mini2440
- */
-
-/*@{*/
-#if defined(__CC_ARM)
-	extern int Image$$ER_ZI$$ZI$$Base;
-	extern int Image$$ER_ZI$$ZI$$Length;
-	extern int Image$$ER_ZI$$ZI$$Limit;
-#elif (defined (__GNUC__))
-	rt_uint8_t _irq_stack_start[1024];
-	rt_uint8_t _fiq_stack_start[1024];
-	rt_uint8_t _undefined_stack_start[512];
-	rt_uint8_t _abort_stack_start[512];
-	rt_uint8_t _svc_stack_start[4096] SECTION(".nobss");
-	extern unsigned char __bss_start;
-	extern unsigned char __bss_end;
-#endif
-
-#ifdef RT_USING_FINSH
-extern int finsh_system_init(void);
-#endif
-
-/**
- * This function will startup RT-Thread RTOS.
- */
-void rtthread_startup(void)
-{
-	/* enable cpu cache */
-	rt_hw_cpu_icache_enable();
-	rt_hw_cpu_dcache_enable();
-
-	/* init hardware interrupt */
-	rt_hw_interrupt_init();
-
-	/* init board */
-	rt_hw_board_init();
-
-	/* show version */
-	rt_show_version();
-
-	/* init tick */
-	rt_system_tick_init();
-
-	/* init kernel object */
-	rt_system_object_init();
-
-	/* init timer system */
-	rt_system_timer_init();
-
-	/* init heap memory system */
-#ifdef __CC_ARM
-	rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x33F00000);
-#else
-	rt_system_heap_init((void*)&__bss_end, (void*)0x33F00000);
-#endif
-
-#ifdef RT_USING_MODULE
-	/* init module system*/
-	rt_system_module_init();
-#endif
-
-	/* init scheduler system */
-	rt_system_scheduler_init();
-
-#ifdef RT_USING_DEVICE
-	/* register uart0 */
-	rt_hw_serial_register(&uart0_device, "uart0",
-		RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-		&uart0);
-
-	/* register uart2, used for RTI debug */
-	rt_hw_serial_register(&uart2_device, "uart2",
-		RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
-		&uart2);
-
-#ifdef RT_USING_DFS
-	rt_hw_sdcard_init();
-#ifdef RT_USING_DFS_UFFS
-	rt_hw_nand_init();
-#endif
-#endif
-
-	/* rtc init */
-	rt_hw_rtc_init();
-#endif
-
-	/* init application */
-	rt_application_init();
-
-#ifdef RT_USING_FINSH
-	/* init finsh */
-	finsh_system_init();
-#ifdef RT_USING_DEVICE
-	finsh_set_device("uart0");
-#endif
-#endif
-
-	rt_system_timer_thread_init();
-
-	/* init idle thread */
-	rt_thread_idle_init();
-
-	/* start scheduler */
-	rt_system_scheduler_start();
-
-	/* never reach here */
-	return ;
-}
-
-int main(void)
-{
-	/* disable interrupt first */
-	rt_hw_interrupt_disable();
-
-	/* startup RT-Thread RTOS */
-	rtthread_startup();
-
-	return 0;
-}
-
-/*@}*/
diff --git a/bsp/mini2440/drivers/SConscript b/bsp/mini2440/drivers/SConscript
index 55c8b43cd5..8b36ce3aab 100644
--- a/bsp/mini2440/drivers/SConscript
+++ b/bsp/mini2440/drivers/SConscript
@@ -8,7 +8,7 @@ cwd     = os.path.join(str(Dir('#')), 'drivers')
 src = Split("""
 board.c
 led.c
-console.c
+uart.c
 """)
 
 if GetDepend('RT_USING_DFS'):
@@ -18,7 +18,7 @@ if GetDepend('RT_USING_LWIP'):
 	src += ['dm9000.c']
 
 if GetDepend('RT_USING_RTGUI'):
-    	src += ['touch.c', 'key.c', 'calibration.c']
+    	src += ['touch.c', 'key.c']
 
 if GetDepend('RT_USING_FTK'):
     	src += ['touch.c', 'key.c']
diff --git a/bsp/mini2440/drivers/board.c b/bsp/mini2440/drivers/board.c
index fc623386b4..14e2e426df 100644
--- a/bsp/mini2440/drivers/board.c
+++ b/bsp/mini2440/drivers/board.c
@@ -26,6 +26,29 @@
  */
 /*@{*/
 
+#if defined(__CC_ARM)
+    extern int Image$$ER_ZI$$ZI$$Base;
+    extern int Image$$ER_ZI$$ZI$$Length;
+    extern int Image$$ER_ZI$$ZI$$Limit;
+#elif (defined (__GNUC__))
+    rt_uint8_t _irq_stack_start[1024];
+    rt_uint8_t _fiq_stack_start[1024];
+    rt_uint8_t _undefined_stack_start[512];
+    rt_uint8_t _abort_stack_start[512];
+    rt_uint8_t _svc_stack_start[4096] SECTION(".nobss");
+#endif
+
+#if defined(__CC_ARM)
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#define HEAP_BEGIN      ((void*)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif defined(__GNUC__)
+extern int __bss_end;
+#define HEAP_BEGIN      (((void*)&__bss_end) + 0x1000)
+#endif
+
+#define HEAP_END        (void*)(0x33F00000)
+
+
 extern rt_uint32_t PCLK, FCLK, HCLK, UCLK;
 
 extern void rt_hw_clock_init(void);
@@ -35,26 +58,6 @@ extern void rt_hw_get_clock(void);
 extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn);
 extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
 
-#define UART0	((struct uartport *)&U0BASE)
-struct serial_int_rx uart0_int_rx;
-struct serial_device uart0 =
-{
-	UART0,
-	&uart0_int_rx,
-	RT_NULL
-};
-struct rt_device uart0_device;
-
-#define UART2	((struct uartport *)&U2BASE)
-struct serial_int_rx uart2_int_rx;
-struct serial_device uart2 =
-{
-	UART2,
-	&uart2_int_rx,
-	RT_NULL
-};
-struct rt_device uart2_device;
-
 /**
  * This function will handle rtos timer
  */
@@ -63,92 +66,6 @@ static void rt_timer_handler(int vector, void *param)
 	rt_tick_increase();
 }
 
-/**
- * This function will handle serial
- */
-static void rt_serial0_handler(int vector, void *param)
-{
-	INTSUBMSK |= (BIT_SUB_RXD0);
-
-	rt_hw_serial_isr(&uart0_device);
-
-	SUBSRCPND |= BIT_SUB_RXD0;
-
-	/* Unmask sub interrupt (RXD0) */
-	INTSUBMSK  &=~(BIT_SUB_RXD0);
-}
-
-/**
- * This function will handle serial
- */
-static void rt_serial2_handler(int vector, void *param)
-{
-	INTSUBMSK |= (BIT_SUB_RXD2);
-
-	rt_hw_serial_isr(&uart2_device);
-
-	SUBSRCPND |= BIT_SUB_RXD2;
-
-	/* Unmask sub interrupt (RXD0) */
-	INTSUBMSK  &=~(BIT_SUB_RXD2);
-}
-
-/**
- * This function will handle init uart
- */
-static void rt_hw_uart_init(void)
-{
-	int i;
-	/* UART0 port configure */
-	GPHCON |= 0xAA;
-	/* PULLUP is disable */
-	GPHUP |= 0xF;
-
-	/* FIFO enable, Tx/Rx FIFO clear */
-	uart0.uart_device->ufcon = 0x0;
-	/* disable the flow control */
-	uart0.uart_device->umcon = 0x0;
-	/* Normal,No parity,1 stop,8 bit */
-	uart0.uart_device->ulcon = 0x3;
-	/*
-	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
-	 * normal,interrupt or polling
-	 */
-	uart0.uart_device->ucon = 0x245;
-	/* Set uart0 bps */
-	uart0.uart_device->ubrd = (rt_int32_t)(PCLK / (BPS * 16)) - 1;
-	/* output PCLK to UART0/1, PWMTIMER */
-	CLKCON |= 0x0D00;
-
-	/* FIFO enable, Tx/Rx FIFO clear */
-	uart2.uart_device->ufcon = 0x0;
-	/* disable the flow control */
-	uart2.uart_device->umcon = 0x0;
-	/* Normal,No parity,1 stop,8 bit */
-	uart2.uart_device->ulcon = 0x3;
-	/*
-	 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
-	 * normal,interrupt or polling
-	 */
-	uart2.uart_device->ucon = 0x245;
-	/* Set uart0 bps */
-	uart2.uart_device->ubrd = (rt_int32_t)(PCLK / (BPS * 16)) - 1;
-
-	for (i = 0; i < 100; i++);
-
-	/* install uart0 isr */
-	INTSUBMSK &= ~(BIT_SUB_RXD0);
-
-	/* install uart2 isr */
-	INTSUBMSK &= ~(BIT_SUB_RXD2);
-
-	rt_hw_interrupt_install(INTUART0, rt_serial0_handler, RT_NULL, "UART0");
-	rt_hw_interrupt_umask(INTUART0);
-
-	rt_hw_interrupt_install(INTUART2, rt_serial2_handler, RT_NULL, "UART2");
-	rt_hw_interrupt_umask(INTUART2);
-}
-
 /**
  * This function will init timer4 for system ticks
  */
@@ -177,6 +94,12 @@ static  void rt_hw_timer_init(void)
  */
 void rt_hw_board_init(void)
 {
+	rt_hw_cpu_icache_enable();
+	rt_hw_cpu_dcache_enable();
+
+	/* init hardware interrupt */
+	rt_hw_interrupt_init();
+
 	/* initialize the system clock */
 	rt_hw_clock_init();
 
@@ -186,14 +109,27 @@ void rt_hw_board_init(void)
 	/* initialize led port */
 	rt_hw_led_init();
 
-	/* initialize uart */
-	rt_hw_uart_init();
-
 	/* initialize mmu */
 	rt_hw_mmu_init();
 
 	/* initialize timer4 */
 	rt_hw_timer_init();
+
+	/* initialize system heap */
+	rt_system_heap_init(HEAP_BEGIN, HEAP_END);
+
+	rt_components_board_init();
+
+#ifdef RT_USING_CONSOLE
+	rt_console_set_device("uart0");
+#endif
+
 }
 
+#ifdef RT_USING_MODULE
+int rt_system_module_init(void)
+{
+    return 0;
+}
+#endif
 /*@}*/
diff --git a/bsp/mini2440/drivers/board.h b/bsp/mini2440/drivers/board.h
index 2635ab147a..434f725216 100644
--- a/bsp/mini2440/drivers/board.h
+++ b/bsp/mini2440/drivers/board.h
@@ -16,7 +16,6 @@
 #define __BOARD_H__
 
 #include <s3c24x0.h>
-#include <serial.h>
 
 void rt_hw_board_init(void);
 void rt_hw_sdcard_init(void);
diff --git a/bsp/mini2440/drivers/console.c b/bsp/mini2440/drivers/console.c
deleted file mode 100644
index 70a57a7370..0000000000
--- a/bsp/mini2440/drivers/console.c
+++ /dev/null
@@ -1,180 +0,0 @@
-#include <rtthread.h>
-
-#include <serial.h>
-
-#define RT_CONSOLE_WIDTH		240
-#define RT_CONSOLE_HEIGHT		320
-
-#define RT_CONSOLE_FONT_WIDTH	8
-#define RT_CONSOLE_FONT_HEIGHT	16
-
-#define RT_CONSOLE_COL			(RT_CONSOLE_WIDTH/RT_CONSOLE_FONT_WIDTH)
-#define RT_CONSOLE_ROW			(RT_CONSOLE_HEIGHT/RT_CONSOLE_FONT_HEIGHT)
-
-#define RT_CONSOLE_TAB			4
-
-#define RT_CONSOLE_FOREPIXEL	(0x001f)
-
-extern struct serial_device uart0;
-
-struct rt_console
-{
-	rt_uint8_t* video_ptr;
-	rt_uint8_t* font_ptr;
-
-	/* bpp and pixel of width */
-	rt_uint8_t bpp;
-	rt_uint32_t pitch;
-
-	/* current cursor */
-	rt_uint8_t current_col;
-	rt_uint8_t current_row;
-};
-struct rt_console console;
-
-void rt_hw_console_init(rt_uint8_t* video_ptr, rt_uint8_t* font_ptr, rt_uint8_t bpp);
-void rt_hw_console_newline(void);
-void rt_hw_console_putc(char c);
-void rt_hw_console_clear(void);
-
-void rt_hw_console_init(rt_uint8_t* video_ptr, rt_uint8_t* font_ptr, rt_uint8_t bpp)
-{
-	rt_memset(&console, 0, sizeof(struct rt_console));
-
-	console.video_ptr = video_ptr;
-	console.font_ptr = font_ptr;
-	console.bpp = bpp;
-	console.pitch = console.bpp * RT_CONSOLE_WIDTH;
-
-	rt_hw_console_clear();
-}
-
-void rt_hw_console_putc(char c)
-{
-	switch (c)
-	{
-        case 10:
-        case 11:
-        case 12:
-        case 13:
-			/* to next line */
-            rt_hw_console_newline();
-            console.current_col = 0;
-            break;
-
-        case 9:
-            console.current_col += RT_CONSOLE_TAB;
-            break;
-
-        default:
-			{
-				rt_uint8_t* font_ptr;
-				register rt_uint32_t cursor;
-				register rt_uint32_t i, j;
-
-				if (console.current_col == RT_CONSOLE_COL)
-				{
-					rt_hw_console_newline();
-					console.current_col = 0;
-
-					rt_hw_console_putc(c);
-					return;
-				}
-
-				font_ptr = console.font_ptr + c * RT_CONSOLE_FONT_HEIGHT;
-				cursor = (console.current_row * RT_CONSOLE_FONT_HEIGHT) * console.pitch
-					+ console.current_col * RT_CONSOLE_FONT_WIDTH * console.bpp;
-
-				for (i = 0; i < RT_CONSOLE_FONT_HEIGHT; i ++ )
-				{
-					for (j = 0; j < RT_CONSOLE_FONT_WIDTH; j ++)
-					{
-						if ( ((font_ptr[i] >> (7-j)) & 0x01) != 0 )
-						{
-							/* draw a pixel */
-							rt_uint8_t *ptr = &(console.video_ptr[cursor + i * console.pitch + j * console.bpp]);
-							switch(console.bpp)
-							{
-							case 1:
-								*ptr = RT_CONSOLE_FOREPIXEL;
-								break;
-							case 2:
-								*(rt_uint16_t*)ptr = RT_CONSOLE_FOREPIXEL;
-								break;
-							case 3:
-								ptr[0] = RT_CONSOLE_FOREPIXEL & 0xff;
-								ptr[1] = (RT_CONSOLE_FOREPIXEL >> 8) & 0xff;
-								ptr[2] = (RT_CONSOLE_FOREPIXEL >> 16) & 0xff;
-								break;
-							case 4:
-								*(rt_uint32_t*)ptr = RT_CONSOLE_FOREPIXEL;
-								break;
-							}
-						}
-					}
-				}
-
-				console.current_col ++;
-			}
-			break;
-	}
-}
-
-void rt_hw_console_newline()
-{
-	console.current_row ++;
-	if (console.current_row >= RT_CONSOLE_ROW)
-	{
-		rt_uint32_t i;
-
-		/* scroll to next line */
-		for (i = 0; i < RT_CONSOLE_ROW - 1; i ++)
-		{
-			rt_memcpy(console.video_ptr + i * RT_CONSOLE_FONT_HEIGHT * console.pitch,
-				console.video_ptr + (i + 1) * RT_CONSOLE_FONT_HEIGHT * console.pitch,
-				RT_CONSOLE_FONT_HEIGHT * console.pitch);
-		}
-
-		/* clear last line */
-		rt_memset(console.video_ptr + (RT_CONSOLE_ROW - 1) * RT_CONSOLE_FONT_HEIGHT * console.pitch,
-			0,
-			RT_CONSOLE_FONT_HEIGHT * console.pitch);
-
-		console.current_row = RT_CONSOLE_ROW - 1;
-	}
-}
-
-void rt_hw_console_clear()
-{
-	console.current_col = 0;
-	console.current_row = 0;
-
-	rt_memset(console.video_ptr, 0, RT_CONSOLE_HEIGHT * console.pitch);
-}
-
-/* write one character to serial, must not trigger interrupt */
-void rt_hw_serial_putc(const char c)
-{
-	/*
-		to be polite with serial console add a line feed
-		to the carriage return character
-	*/
-	if (c=='\n')rt_hw_serial_putc('\r');
-
-	while (!(uart0.uart_device->ustat & USTAT_TXB_EMPTY));
-	uart0.uart_device->utxh = (c & 0x1FF);
-}
-
-/**
- * This function is used by rt_kprintf to display a string on console.
- *
- * @param str the displayed string
- */
-void rt_hw_console_output(const char* str)
-{
-	while (*str)
-	{
-		rt_hw_serial_putc(*str++);
-	}
-}
-
diff --git a/bsp/mini2440/drivers/dm9000.c b/bsp/mini2440/drivers/dm9000.c
index e3f1f0d634..22afb322c7 100644
--- a/bsp/mini2440/drivers/dm9000.c
+++ b/bsp/mini2440/drivers/dm9000.c
@@ -287,6 +287,9 @@ static rt_err_t rt_dm9000_init(rt_device_t dev)
 		}
 	}
 
+	/* send a notify */
+	eth_device_linkchange(&dm9000_device.parent, RT_TRUE);
+
 	/* see what we've got */
 	lnk = phy_read(17) >> 12;
 	rt_kprintf("operating at ");
@@ -588,7 +591,7 @@ void INTEINT4_7_handler(int irqno, void *param)
 	EINTPEND = eint_pend;
 }
 
-void rt_hw_dm9000_init()
+int rt_hw_dm9000_init()
 {
 	/* Set GPF7 as EINT7 */
 	GPFCON = GPFCON & (~(3 << 14)) | (2 << 14);
@@ -641,6 +644,8 @@ void rt_hw_dm9000_init()
 	rt_hw_interrupt_umask(INTEINT4_7);
 }
 
+INIT_DEVICE_EXPORT(rt_hw_dm9000_init);
+
 void dm9000a(void)
 {
 	rt_kprintf("\n");
diff --git a/bsp/mini2440/drivers/dm9000.h b/bsp/mini2440/drivers/dm9000.h
index 1dda60bfd2..28499c22d8 100644
--- a/bsp/mini2440/drivers/dm9000.h
+++ b/bsp/mini2440/drivers/dm9000.h
@@ -143,6 +143,6 @@
 
 #define GPCR_GEP_CNTL       (1<<0)
 
-void rt_hw_dm9000_init(void);
+int rt_hw_dm9000_init(void);
 
 #endif
diff --git a/bsp/mini2440/drivers/key.c b/bsp/mini2440/drivers/key.c
index 3c73c7a788..d75ffd6d26 100644
--- a/bsp/mini2440/drivers/key.c
+++ b/bsp/mini2440/drivers/key.c
@@ -79,7 +79,7 @@ static void rt_hw_key_isr(void)
 /**
  * This function is only for QEMU emulation
  */
-static void rt_key_handler(int vector)
+static void rt_key_handler(int vector, void *param)
 {
 	INTSUBMSK |= (BIT_SUB_RXD1);
 
diff --git a/bsp/mini2440/drivers/sdcard.c b/bsp/mini2440/drivers/sdcard.c
index b2ab684e48..0f5b79bb25 100644
--- a/bsp/mini2440/drivers/sdcard.c
+++ b/bsp/mini2440/drivers/sdcard.c
@@ -550,7 +550,7 @@ static rt_size_t rt_sdcard_write(rt_device_t dev,
     return size;
 }
 
-void rt_hw_sdcard_init(void)
+int rt_hw_sdcard_init(void)
 {
     rt_uint8_t i, status;
     rt_uint8_t *sector;
@@ -574,7 +574,7 @@ void rt_hw_sdcard_init(void)
         {
             rt_kprintf("allocate partition sector buffer failed\n");
 
-            return;
+            return RT_ERROR;
         }
         status = sd_readblock(0, sector);
         if (status == RT_EOK)
@@ -637,12 +637,15 @@ void rt_hw_sdcard_init(void)
         /* release sector buffer */
         rt_free(sector);
 
-        return;
+        return RT_ERROR; 
     }
     else
     {
         rt_kprintf("sdcard init failed\n");
     }
+
+    return RT_EOK;
 }
 
+INIT_BOARD_EXPORT(rt_hw_sdcard_init);
 #endif
diff --git a/bsp/mini2440/drivers/touch.c b/bsp/mini2440/drivers/touch.c
index 08d41080be..e584c379e3 100644
--- a/bsp/mini2440/drivers/touch.c
+++ b/bsp/mini2440/drivers/touch.c
@@ -349,7 +349,7 @@ static void s3c2410_intc_stylus_updown(void)
 	SUBSRCPND |= BIT_SUB_TC;
 }
 
-static void rt_touch_handler(int irqno)
+static void rt_touch_handler(int irqno, void *param)
 {
 	if (SUBSRCPND & BIT_SUB_ADC)
 	{
diff --git a/bsp/mini2440/drivers/uart.c b/bsp/mini2440/drivers/uart.c
new file mode 100644
index 0000000000..f7bf1d9461
--- /dev/null
+++ b/bsp/mini2440/drivers/uart.c
@@ -0,0 +1,183 @@
+/*
+ * File      : uart.c
+ * Drivers for s3c2440 uarts.
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-09     Jonne        Code refactoring for new bsp
+ */
+
+#include <rthw.h>
+#include <rtdevice.h>
+#include <board.h>
+
+#define ULCON_OFS				0x00
+#define UCON_OFS				0x04
+#define UFCON_OFS				0x08
+#define UMCON_OFS				0x0c
+#define UTRSTAT_OFS				0x10
+#define UERSTAT_OFS				0x14
+#define UFSTAT_OFS				0x18
+#define UMSTAT_OFS				0x1c
+#define UTXH_OFS				0x20
+#define URXH_OFS				0x24
+#define UBRDIV_OFS				0x28
+
+#define readl(addr)             (*(volatile unsigned long *)(addr))
+#define writel(addr, value)     (*(volatile unsigned long *)(addr) = value)  
+
+#define PCLK_HZ                 50000000
+
+struct hw_uart_device
+{
+    rt_uint32_t hw_base;
+    rt_uint32_t irqno;
+};
+
+static rt_err_t s3c2440_serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg) 
+{
+    struct hw_uart_device* uart = serial->parent.user_data;
+
+    writel(uart->hw_base + UBRDIV_OFS, PCLK_HZ / (cfg->baud_rate * 16));
+
+    writel(uart->hw_base + ULCON_OFS, 0x03);// 8bit data, 1bit stop, No parity
+    writel(uart->hw_base + UCON_OFS, 0x05);
+    writel(uart->hw_base + UFCON_OFS, 0x00);
+    writel(uart->hw_base + UMCON_OFS, 0x00);
+
+	return RT_EOK;
+}
+
+static rt_err_t s3c2440_serial_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+	struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL); 
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        INTSUBMSK |= BIT_SUB_RXD0;
+		
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        INTSUBMSK &= ~(BIT_SUB_RXD0);
+        break;
+    }
+
+    return RT_EOK;
+}
+static int s3c2440_putc(struct rt_serial_device *serial, char c)
+{
+    struct hw_uart_device* uart = serial->parent.user_data;
+
+    while(!(readl(uart->hw_base + UTRSTAT_OFS) & (1<<2))) 
+    {
+    }
+
+    writel(uart->hw_base + UTXH_OFS, c);
+    
+    return 0;
+
+     
+}
+static int s3c2440_getc(struct rt_serial_device *serial)
+{
+    struct hw_uart_device* uart = serial->parent.user_data;
+    int ch = -1;
+
+    if(readl(uart->hw_base + UTRSTAT_OFS) & (1<<0)) 
+    {
+        ch = readl(uart->hw_base + URXH_OFS) & 0x000000FF;
+    }
+    
+    return ch;
+}
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device *)param;
+
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    
+    /*clear SUBSRCPND*/ 
+    if(irqno == INTUART0) 
+    {
+        SUBSRCPND = BIT_SUB_RXD0;
+    } 
+    else if(irqno == INTUART1) 
+    {
+        SUBSRCPND = BIT_SUB_RXD1;
+    }
+    else 
+    {
+        SUBSRCPND = BIT_SUB_RXD2;
+    }
+}
+
+static struct rt_uart_ops s3c2440_uart_ops = {
+		.configure = s3c2440_serial_configure,
+		.control = s3c2440_serial_control,
+		.putc = s3c2440_putc,
+		.getc = s3c2440_getc
+};
+
+
+static struct rt_serial_device _serial0 = {
+	.ops = &s3c2440_uart_ops,
+	.config = RT_SERIAL_CONFIG_DEFAULT,
+	.serial_rx = NULL,
+	.serial_tx = NULL
+};
+static struct hw_uart_device _hwserial0 = {
+	.hw_base = 0x50000000,
+	.irqno = INTUART0
+};
+
+static struct rt_serial_device _serial1 = {
+	.ops = &s3c2440_uart_ops,
+	.config = RT_SERIAL_CONFIG_DEFAULT,
+	.serial_rx = NULL,
+	.serial_tx = NULL
+};
+static struct hw_uart_device _hwserial1 = {
+	.hw_base = 0x50004000,
+	.irqno = INTUART1
+};
+
+static struct rt_serial_device _serial2 = {
+	.ops = &s3c2440_uart_ops,
+	.config = RT_SERIAL_CONFIG_DEFAULT,
+	.serial_rx = NULL,
+	.serial_tx = NULL
+};
+static struct hw_uart_device _hwserial2 = {
+	.hw_base = 0x50008000,
+	.irqno = INTUART2
+};
+
+
+int rt_hw_uart_init(void)
+{
+    /* register UART0 device */
+    rt_hw_serial_register(&_serial0, "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &_hwserial0);
+    rt_hw_interrupt_install(_hwserial0.irqno, rt_hw_uart_isr, &_serial0, "uart0");
+    rt_hw_interrupt_umask(INTUART0);
+	
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial1, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &_hwserial1);
+    rt_hw_interrupt_install(_hwserial1.irqno, rt_hw_uart_isr, &_serial1, "uart1");
+    rt_hw_interrupt_umask(INTUART1);
+
+    /* register UART2 device */
+    rt_hw_serial_register(&_serial2, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, &_hwserial2);
+    rt_hw_interrupt_install(_hwserial2.irqno, rt_hw_uart_isr, &_serial2, "uart2");
+    rt_hw_interrupt_umask(INTUART2);
+
+    return 0;
+}
+
+INIT_BOARD_EXPORT(rt_hw_uart_init);
diff --git a/bsp/mini2440/rtconfig.h b/bsp/mini2440/rtconfig.h
index 8147715c8f..5d65b46148 100644
--- a/bsp/mini2440/rtconfig.h
+++ b/bsp/mini2440/rtconfig.h
@@ -1,176 +1,243 @@
-/* RT-Thread config file */
-#ifndef __RTTHREAD_CFG_H__
-#define __RTTHREAD_CFG_H__
-
-// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
-
-// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
-#define RT_NAME_MAX	32
-// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
-#define RT_ALIGN_SIZE	4
-// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
-// <item description="8">8</item>
-// <item description="32">32</item>
-// <item description="256">256</item>
-// </integer>
-#define RT_THREAD_PRIORITY_MAX	256
-// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
-#define RT_TICK_PER_SECOND	100
-// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
-// #define RT_DEBUG
-// <bool name="RT_THREAD_DEBUG" description="Thread debug enable" default="false" />
-// #define RT_THREAD_DEBUG
-// <bool name="RT_USING_OVERFLOW_CHECK" description="Thread stack over flow detect" default="true" />
-#define RT_USING_OVERFLOW_CHECK
-// <bool name="RT_USING_INTERRUPT_INFO" description="Show more interrupt description" default="true" />
-#define RT_USING_INTERRUPT_INFO
-// </section>
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+#define BOARD_MINI2440
 
-// <bool name="RT_USING_HOOK" description="Using hook functions" default="true" />
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
-// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
-// #define RT_USING_TIMER_SOFT
-// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
-#define RT_TIMER_THREAD_PRIO	8
-// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
-#define RT_TIMER_THREAD_STACK_SIZE	512
-// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
-#define RT_TIMER_TICK_PER_SECOND	10
-// </section>
-
-// <section name="IPC" description="Inter-Thread communication" default="always" >
-// <bool name="RT_USING_SEMAPHORE" description="Using semaphore in the system" default="true" />
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
 #define RT_USING_SEMAPHORE
-// <bool name="RT_USING_MUTEX" description="Using mutex in the system" default="true" />
 #define RT_USING_MUTEX
-// <bool name="RT_USING_EVENT" description="Using event group in the system" default="true" />
 #define RT_USING_EVENT
-// <bool name="RT_USING_MAILBOX" description="Using mailbox in the system" default="true" />
 #define RT_USING_MAILBOX
-// <bool name="RT_USING_MESSAGEQUEUE" description="Using message queue in the system" default="true" />
 #define RT_USING_MESSAGEQUEUE
-// </section>
 
-// <section name="MM" description="Memory Management" default="always" >
-// <bool name="RT_USING_MEMPOOL" description="Using Memory Pool Management in the system" default="true" />
+/* Memory Management */
+
 #define RT_USING_MEMPOOL
-// <bool name="RT_USING_HEAP" description="Using Dynamic Heap Management in the system" default="true" />
-#define RT_USING_HEAP
-// <bool name="RT_USING_SMALL_MEM" description="Optimizing for small memory" default="false" />
+#define RT_USING_MEMHEAP
 #define RT_USING_SMALL_MEM
-// <bool name="RT_USING_SLAB" description="Using SLAB memory management for large memory" default="false" />
-// #define RT_USING_SLAB
-// </section>
+#define RT_USING_HEAP
 
-// <section name="RT_USING_DEVICE" description="Using Device Driver Framework" default="true" >
-#define RT_USING_DEVICE
-#define RT_USING_DEVICE_IPC
-// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
-#define RT_USING_UART0
-// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
-#define RT_UART_RX_BUFFER_SIZE	64
-// </section>
+/* Kernel Device Object */
 
-// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
+#define RT_USING_DEVICE
 #define RT_USING_CONSOLE
-// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
-#define RT_CONSOLEBUF_SIZE	128
-// </section>
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart"
+#define RT_VER_NUM 0x40003
+#define ARCH_ARM
+#define ARCH_ARM_ARM9
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+#define RT_USING_CPLUSPLUS
+
+/* Command shell */
 
-// <section name="RT_USING_FINSH" description="Using finsh as shell, which is a C-Express shell" default="true" >
 #define RT_USING_FINSH
-// <bool name="FINSH_USING_SYMTAB" description="Using symbol table in finsh shell" default="true" />
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
 #define FINSH_USING_SYMTAB
-// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
 #define FINSH_USING_DESCRIPTION
-// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
-#define FINSH_THREAD_STACK_SIZE	4096
-// </section>
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
 
-// <section name="LIBC" description="C Runtime library setting" default="always" >
-// <bool name="RT_USING_LIBC" description="Using C library" default="true" />
-#define RT_USING_LIBC
-// <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
-#define RT_USING_PTHREADS
-// </section>
+/* Device virtual file system */
 
-// <section name="RT_USING_DFS" description="Device file system" default="true" >
 #define RT_USING_DFS
-// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
 #define DFS_USING_WORKDIR
-// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
-#define DFS_FILESYSTEMS_MAX	2
-// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
-#define DFS_FD_MAX	4
-// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
+#define DFS_FILESYSTEMS_MAX 5
+#define DFS_FILESYSTEM_TYPES_MAX 5
+#define DFS_FD_MAX 16
 #define RT_USING_DFS_ELMFAT
-// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
-// <item description="LFN1">1</item>
-// <item description="LFN1">2</item>
-// </integer>
-#define RT_DFS_ELM_USE_LFN	1
-// <integer name="RT_DFS_ELM_CODE_PAGE" description="OEM code page" default="936">
-#define RT_DFS_ELM_CODE_PAGE	936
-// <bool name="RT_DFS_ELM_CODE_PAGE_FILE" description="Using OEM code page file" default="false" />
-// #define RT_DFS_ELM_CODE_PAGE_FILE
-// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
-#define RT_DFS_ELM_MAX_LFN	255
-// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
-// #define RT_USING_DFS_YAFFS2
-// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
-// #define RT_USING_DFS_UFFS
-// <bool name="RT_USING_DFS_DEVFS" description="Using devfs for device objects" default="true" />
+
+/* elm-chan's FatFs, Generic FAT Filesystem Module */
+
+#define RT_DFS_ELM_CODE_PAGE 437
+#define RT_DFS_ELM_WORD_ACCESS
+#define RT_DFS_ELM_USE_LFN_3
+#define RT_DFS_ELM_USE_LFN 3
+#define RT_DFS_ELM_MAX_LFN 255
+#define RT_DFS_ELM_DRIVES 2
+#define RT_DFS_ELM_MAX_SECTOR_SIZE 512
+#define RT_DFS_ELM_REENTRANT
 #define RT_USING_DFS_DEVFS
-// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
-// #define RT_USING_DFS_NFS
-// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
-#define RT_NFS_HOST_EXPORT	"192.168.1.5:/"
-// </section>
+#define RT_USING_DFS_RAMFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_PTHREADS
+#define PTHREAD_NUM_MAX 8
+#define RT_USING_POSIX
+#define RT_USING_POSIX_MMAP
+#define RT_USING_POSIX_TERMIOS
+#define RT_USING_POSIX_AIO
+#define RT_USING_MODULE
+#define RT_USING_CUSTOM_DLMODULE
+
+/* Network */
+
+/* Socket abstraction layer */
+
+#define RT_USING_SAL
+
+/* protocol stack implement */
+
+#define SAL_USING_LWIP
+#define SAL_USING_POSIX
+
+/* Network interface device */
+
+#define RT_USING_NETDEV
+#define NETDEV_USING_IFCONFIG
+#define NETDEV_USING_PING
+#define NETDEV_USING_NETSTAT
+#define NETDEV_USING_AUTO_DEFAULT
+#define NETDEV_IPV4 1
+#define NETDEV_IPV6 0
+
+/* light weight TCP/IP stack */
 
-// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
 #define RT_USING_LWIP
-// <bool name="RT_LWIP_ICMP" description="Enable ICMP protocol" default="true" />
+#define RT_USING_LWIP210
+#define RT_LWIP_IGMP
 #define RT_LWIP_ICMP
-// <bool name="RT_LWIP_IGMP" description="Enable IGMP protocol" default="false" />
-// #define RT_LWIP_IGMP
-// <bool name="RT_LWIP_UDP" description="Enable UDP protocol" default="true" />
+#define RT_LWIP_DNS
+#define RT_LWIP_DHCP
+#define IP_SOF_BROADCAST 1
+#define IP_SOF_BROADCAST_RECV 1
+
+/* Static IPv4 Address */
+
+#define RT_LWIP_IPADDR "192.168.0.30"
+#define RT_LWIP_GWADDR "192.168.0.1"
+#define RT_LWIP_MSKADDR "255.255.255.0"
 #define RT_LWIP_UDP
-// <bool name="RT_LWIP_TCP" description="Enable TCP protocol" default="true" />
 #define RT_LWIP_TCP
-// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
-#define RT_LWIP_DNS
-// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
-#define RT_LWIP_TCP_PCB_NUM	5
-// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
-#define RT_LWIP_TCP_SND_BUF	8192
-// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
-#define RT_LWIP_TCP_WND	8192
-// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
-// #define RT_LWIP_SNMP
-// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
-// #define RT_LWIP_DHCP
-// <integer name="RT_LWIP_TCP_SEG_NUM" description="the number of simultaneously queued TCP" default="8" />
-#define RT_LWIP_TCP_SEG_NUM	40
-// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
-#define RT_LWIP_TCPTHREAD_PRIORITY	12
-// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE	32
-// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
-#define RT_LWIP_TCPTHREAD_STACKSIZE	4096
-// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
-#define RT_LWIP_ETHTHREAD_PRIORITY	144
-// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE	32
-// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
-#define RT_LWIP_ETHTHREAD_STACKSIZE	512
-// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
-#define RT_LWIP_IPADDR "192.168.1.30"
-// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
-#define RT_LWIP_GWADDR  "192.168.1.1"
-// <ipaddr name="RT_LWIP_MSKADDR" description="Mask address of device" default="255.255.255.0" />
-#define RT_LWIP_MSKADDR  "255.255.255.0"
-// </section>
-
-// </RDTConfigurator>
+#define RT_LWIP_RAW
+#define RT_MEMP_NUM_NETCONN 8
+#define RT_LWIP_PBUF_NUM 16
+#define RT_LWIP_RAW_PCB_NUM 4
+#define RT_LWIP_UDP_PCB_NUM 4
+#define RT_LWIP_TCP_PCB_NUM 4
+#define RT_LWIP_TCP_SEG_NUM 40
+#define RT_LWIP_TCP_SND_BUF 8196
+#define RT_LWIP_TCP_WND 8196
+#define RT_LWIP_TCPTHREAD_PRIORITY 10
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
+#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
+#define RT_LWIP_ETHTHREAD_PRIORITY 12
+#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
+#define LWIP_NETIF_STATUS_CALLBACK 1
+#define LWIP_NETIF_LINK_CALLBACK 1
+#define SO_REUSE 1
+#define LWIP_SO_RCVTIMEO 1
+#define LWIP_SO_SNDTIMEO 1
+#define LWIP_SO_RCVBUF 1
+#define RT_LWIP_NETIF_LOOPBACK
+#define LWIP_NETIF_LOOPBACK 1
+#define RT_LWIP_STATS
+#define RT_LWIP_USING_PING
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+#define RT_USING_RYM
+#define YMODEM_USING_CRC_TABLE
+#define YMODEM_USING_FILE_TRANSFER
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
 
 #endif
diff --git a/bsp/mini2440/rtconfig.py b/bsp/mini2440/rtconfig.py
index dd574acb16..106597711a 100644
--- a/bsp/mini2440/rtconfig.py
+++ b/bsp/mini2440/rtconfig.py
@@ -9,14 +9,14 @@ ARCH     = 'arm'
 CPU      = 's3c24x0'
 TextBase = '0x30000000'
 
-CROSS_TOOL 	= 'keil'
+CROSS_TOOL 	= 'gcc'
 
 if os.getenv('RTT_CC'):
     CROSS_TOOL = os.getenv('RTT_CC')
 
 if  CROSS_TOOL == 'gcc':
     PLATFORM 	= 'gcc'
-    EXEC_PATH 	= 'C:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
+    EXEC_PATH 	= '/opt/gcc-arm-none-eabi-6_2-2016q4/bin'
 elif CROSS_TOOL == 'keil':
     PLATFORM 	= 'armcc'
     EXEC_PATH 	= 'C:/Keil'
@@ -43,12 +43,21 @@ if PLATFORM == 'gcc':
     SIZE = PREFIX + 'size'
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY = PREFIX + 'objcopy'
+    STRIP = PREFIX + 'strip'
 
     DEVICE = ' -mcpu=arm920t'
     CFLAGS = DEVICE
     AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + ' -DTEXT_BASE=' + TextBase
     LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread_mini2440.map,-cref,-u,_start  -nostartfiles -T mini2440_ram.ld' + ' -Ttext ' + TextBase
 
+    # module setting 
+    CXXFLAGS = ' -Woverloaded-virtual -fno-exceptions -fno-rtti '
+    M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC '
+    M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC'
+    M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\
+                                    ' -shared -fPIC -nostartfiles -static-libgcc'
+    M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
+
     CPATH = ''
     LPATH = ''
 
diff --git a/libcpu/arm/s3c24x0/serial.c b/libcpu/arm/s3c24x0/serial.c
deleted file mode 100644
index 1eca1b1110..0000000000
--- a/libcpu/arm/s3c24x0/serial.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2006-03-13     Bernard      first version
- * 2009-04-20     yi.qiu      modified according bernard's stm32 version
- */
-
-#include <rtthread.h>
-
-#include "serial.h"
-
-/**
- * @addtogroup S3C24X0
- */
-/*@{*/
-
-/* RT-Thread Device Interface */
-/**
- * This function initializes serial
- */
-static rt_err_t rt_serial_init(rt_device_t dev)
-{
-    struct serial_device* uart = (struct serial_device*) dev->user_data;
-
-    if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
-    {
-
-        if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-        {
-            rt_memset(uart->int_rx->rx_buffer, 0,
-                      sizeof(uart->int_rx->rx_buffer));
-            uart->int_rx->read_index = uart->int_rx->save_index = 0;
-        }
-
-        if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-        {
-            rt_memset(uart->int_tx->tx_buffer, 0,
-                      sizeof(uart->int_tx->tx_buffer));
-            uart->int_tx->write_index = uart->int_tx->save_index = 0;
-        }
-
-        dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
-    }
-
-    return RT_EOK;
-}
-
-/* save a char to serial buffer */
-static void rt_serial_savechar(struct serial_device* uart, char ch)
-{
-    rt_base_t level;
-
-    /* disable interrupt */
-    level = rt_hw_interrupt_disable();
-
-    uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch;
-    uart->int_rx->save_index ++;
-    if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
-        uart->int_rx->save_index = 0;
-
-    /* if the next position is read index, discard this 'read char' */
-    if (uart->int_rx->save_index == uart->int_rx->read_index)
-    {
-        uart->int_rx->read_index ++;
-        if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
-            uart->int_rx->read_index = 0;
-    }
-
-    /* enable interrupt */
-    rt_hw_interrupt_enable(level);
-}
-
-static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
-{
-    RT_ASSERT(dev != RT_NULL);
-
-    return RT_EOK;
-}
-
-static rt_err_t rt_serial_close(rt_device_t dev)
-{
-    RT_ASSERT(dev != RT_NULL);
-
-    return RT_EOK;
-}
-
-static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
-{
-    rt_uint8_t* ptr;
-    rt_err_t err_code;
-    struct serial_device* uart;
-
-    ptr = buffer;
-    err_code = RT_EOK;
-    uart = (struct serial_device*)dev->user_data;
-
-    if (ptr == RT_NULL)
-    {
-        err_code = -RT_ENOMEM;
-        rt_set_errno(err_code);
-        return -RT_ENOMEM;
-    }
-    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-    {
-        rt_base_t level;
-
-        /* interrupt mode Rx */
-        while (size)
-        {
-            if (uart->int_rx->read_index != uart->int_rx->save_index)
-            {
-                *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
-                size --;
-
-                /* disable interrupt */
-                level = rt_hw_interrupt_disable();
-
-                uart->int_rx->read_index ++;
-                if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
-                    uart->int_rx->read_index = 0;
-
-                /* enable interrupt */
-                rt_hw_interrupt_enable(level);
-            }
-            else
-            {
-                /* set error code */
-                err_code = -RT_EEMPTY;
-                break;
-            }
-        }
-    }
-    else
-    {
-        /* polling mode */
-        while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
-        {
-            while (uart->uart_device->ustat & USTAT_RCV_READY)
-            {
-                *ptr = uart->uart_device->urxh & 0xff;
-                ptr ++;
-            }
-        }
-    }
-
-    /* set error code */
-    rt_set_errno(err_code);
-    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-}
-
-static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
-{
-    rt_uint8_t* ptr;
-    rt_err_t err_code;
-    struct serial_device* uart;
-
-    err_code = RT_EOK;
-    ptr = (rt_uint8_t*)buffer;
-    uart = (struct serial_device*)dev->user_data;
-
-    if (ptr == RT_NULL)
-    {
-        err_code = -RT_ENOMEM;
-        rt_set_errno(err_code);
-        return -RT_ENOMEM;
-    }
-    if (dev->flag & RT_DEVICE_FLAG_INT_TX)
-    {
-        /* interrupt mode Tx */
-        while (uart->int_tx->save_index != uart->int_tx->write_index)
-        {
-            /* save on tx buffer */
-            uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++;
-
-            -- size;
-
-            /* move to next position */
-            uart->int_tx->save_index ++;
-
-            /* wrap save index */
-            if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE)
-                uart->int_tx->save_index = 0;
-        }
-
-        /* set error code */
-        if (size > 0)
-            err_code = -RT_EFULL;
-    }
-    else
-    {
-        /* polling mode */
-        while (size)
-        {
-            /*
-             * to be polite with serial console add a line feed
-             * to the carriage return character
-             */
-            if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM))
-            {
-                while (!(uart->uart_device->ustat & USTAT_TXB_EMPTY));
-                uart->uart_device->utxh = '\r';
-            }
-
-            while (!(uart->uart_device->ustat & USTAT_TXB_EMPTY));
-            uart->uart_device->utxh = (*ptr & 0xFF);
-
-            ++ptr;
-            --size;
-        }
-    }
-
-    /* set error code */
-    rt_set_errno(err_code);
-    return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-}
-
-static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args)
-{
-    RT_ASSERT(dev != RT_NULL);
-
-    switch (cmd)
-    {
-    case RT_DEVICE_CTRL_SUSPEND:
-        /* suspend device */
-        dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
-        break;
-
-    case RT_DEVICE_CTRL_RESUME:
-        /* resume device */
-        dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
-        break;
-    }
-
-    return RT_EOK;
-}
-
-/*
- * serial register
- */
-rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial)
-{
-    RT_ASSERT(device != RT_NULL);
-
-    device->type        = RT_Device_Class_Char;
-    device->rx_indicate = RT_NULL;
-    device->tx_complete = RT_NULL;
-    device->init        = rt_serial_init;
-    device->open        = rt_serial_open;
-    device->close       = rt_serial_close;
-    device->read        = rt_serial_read;
-    device->write       = rt_serial_write;
-    device->control     = rt_serial_control;
-    device->user_data   = serial;
-
-    /* register a character device */
-    return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
-}
-
-/* ISR for serial interrupt */
-void rt_hw_serial_isr(rt_device_t device)
-{
-    struct serial_device* uart = (struct serial_device*) device->user_data;
-
-    /* interrupt mode receive */
-    RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
-
-    /* save on rx buffer */
-    while (uart->uart_device->ustat & USTAT_RCV_READY)
-    {
-        rt_serial_savechar(uart, uart->uart_device->urxh & 0xff);
-    }
-
-    /* invoke callback */
-    if (device->rx_indicate != RT_NULL)
-    {
-        rt_size_t rx_length;
-
-        /* get rx length */
-        rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
-                    UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
-                    uart->int_rx->save_index - uart->int_rx->read_index;
-
-        device->rx_indicate(device, rx_length);
-    }
-}
-
-/*@}*/
diff --git a/libcpu/arm/s3c24x0/serial.h b/libcpu/arm/s3c24x0/serial.h
deleted file mode 100644
index 8a647ef35f..0000000000
--- a/libcpu/arm/s3c24x0/serial.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- */
-#ifndef __RT_HW_SERIAL_H__
-#define __RT_HW_SERIAL_H__
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "s3c24x0.h"
-
-#define	USTAT_RCV_READY		0x01   	/* receive data ready */ 
-#define	USTAT_TXB_EMPTY		0x02   	/* tx buffer empty */
-#define BPS					115200	/* serial baudrate */
-
-#define UART_RX_BUFFER_SIZE		64
-#define UART_TX_BUFFER_SIZE		64
-
-struct serial_int_rx
-{
-	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
-	rt_uint32_t read_index, save_index;
-};
-
-struct serial_int_tx
-{
-	rt_uint8_t  tx_buffer[UART_TX_BUFFER_SIZE];
-	rt_uint32_t write_index, save_index;
-};
-
-typedef struct uartport
-{
-	volatile rt_uint32_t ulcon;
-	volatile rt_uint32_t ucon;
-	volatile rt_uint32_t ufcon;
-	volatile rt_uint32_t umcon;
-	volatile rt_uint32_t ustat;
-	volatile rt_uint32_t urxb;
-	volatile rt_uint32_t ufstat;
-	volatile rt_uint32_t umstat;
-	volatile rt_uint32_t utxh;	
-	volatile rt_uint32_t urxh;	
-	volatile rt_uint32_t ubrd;
-}uartport;
-
-struct serial_device
-{
-	uartport* uart_device;
-	
-	/* rx structure */
-	struct serial_int_rx* int_rx;
-
-	/* tx structure */
-	struct serial_int_tx* int_tx;
-};
-
-rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial);
-
-void rt_hw_serial_isr(rt_device_t device);
-
-#endif
-- 
cgit v1.3.1


From fb8c7829a8a861f9837912ecf926899f48349967 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Thu, 16 Apr 2020 16:10:57 +0800
Subject: add raspi4 bsp

---
 bsp/raspberry-pi/raspi4/.config                 | 455 ++++++++++++++++++++++++
 bsp/raspberry-pi/raspi4/Kconfig                 |  29 ++
 bsp/raspberry-pi/raspi4/README.md               | 100 ++++++
 bsp/raspberry-pi/raspi4/SConscript              |  14 +
 bsp/raspberry-pi/raspi4/SConstruct              |  30 ++
 bsp/raspberry-pi/raspi4/applications/SConscript |   9 +
 bsp/raspberry-pi/raspi4/applications/main.c     |  19 +
 bsp/raspberry-pi/raspi4/driver/Kconfig          |  97 +++++
 bsp/raspberry-pi/raspi4/driver/SConscript       |   9 +
 bsp/raspberry-pi/raspi4/driver/board.c          |  98 +++++
 bsp/raspberry-pi/raspi4/driver/board.h          |  25 ++
 bsp/raspberry-pi/raspi4/driver/drv_gpio.c       | 117 ++++++
 bsp/raspberry-pi/raspi4/driver/drv_gpio.h       |  79 ++++
 bsp/raspberry-pi/raspi4/driver/drv_uart.c       | 158 ++++++++
 bsp/raspberry-pi/raspi4/driver/drv_uart.h       |  84 +++++
 bsp/raspberry-pi/raspi4/driver/iomap.h          |  13 +
 bsp/raspberry-pi/raspi4/link.lds                | 153 ++++++++
 bsp/raspberry-pi/raspi4/rtconfig.h              | 179 ++++++++++
 bsp/raspberry-pi/raspi4/rtconfig.py             |  51 +++
 libcpu/aarch64/SConscript                       |   3 +
 libcpu/aarch64/common/SConscript                |  24 ++
 libcpu/aarch64/common/armv8.h                   |  63 ++++
 libcpu/aarch64/common/cache.S                   | 151 ++++++++
 libcpu/aarch64/common/context_gcc.S             | 351 ++++++++++++++++++
 libcpu/aarch64/common/cp15.h                    | 166 +++++++++
 libcpu/aarch64/common/cpu.c                     |  91 +++++
 libcpu/aarch64/common/cpu_gcc.S                 |  82 +++++
 libcpu/aarch64/common/gic/SConscript            |  24 ++
 libcpu/aarch64/common/gic/gic_pl400.c           | 368 +++++++++++++++++++
 libcpu/aarch64/common/gic/gic_pl400.h           |  35 ++
 libcpu/aarch64/common/mmu.c                     | 367 +++++++++++++++++++
 libcpu/aarch64/common/mmu.h                     |  78 ++++
 libcpu/aarch64/common/startup_gcc.S             |  13 +
 libcpu/aarch64/common/vector_gcc.S              |  61 ++++
 libcpu/aarch64/cortex-a53/SConscript            |  15 +-
 libcpu/aarch64/cortex-a53/armv8.h               |  63 ----
 libcpu/aarch64/cortex-a53/cache.S               | 151 --------
 libcpu/aarch64/cortex-a53/context_gcc.S         | 351 ------------------
 libcpu/aarch64/cortex-a53/cp15.h                | 166 ---------
 libcpu/aarch64/cortex-a53/cpu.c                 |  91 -----
 libcpu/aarch64/cortex-a53/cpu_gcc.S             |  82 -----
 libcpu/aarch64/cortex-a53/interrupt.h           |   6 +-
 libcpu/aarch64/cortex-a53/mmu.c                 | 367 -------------------
 libcpu/aarch64/cortex-a53/mmu.h                 |  78 ----
 libcpu/aarch64/cortex-a53/startup_gcc.S         |  13 -
 libcpu/aarch64/cortex-a53/vector_gcc.S          |  61 ----
 libcpu/aarch64/cortex-a57/SConscript            |  13 +
 libcpu/aarch64/cortex-a57/entry_point.S         | 111 ++++++
 libcpu/aarch64/cortex-a57/interrupt.c           |  73 ++++
 libcpu/aarch64/cortex-a57/interrupt.h           |  27 ++
 libcpu/aarch64/cortex-a57/stack.c               |  90 +++++
 libcpu/aarch64/cortex-a57/trap.c                |  98 +++++
 52 files changed, 4016 insertions(+), 1436 deletions(-)
 create mode 100644 bsp/raspberry-pi/raspi4/.config
 create mode 100644 bsp/raspberry-pi/raspi4/Kconfig
 create mode 100644 bsp/raspberry-pi/raspi4/README.md
 create mode 100644 bsp/raspberry-pi/raspi4/SConscript
 create mode 100644 bsp/raspberry-pi/raspi4/SConstruct
 create mode 100644 bsp/raspberry-pi/raspi4/applications/SConscript
 create mode 100644 bsp/raspberry-pi/raspi4/applications/main.c
 create mode 100644 bsp/raspberry-pi/raspi4/driver/Kconfig
 create mode 100644 bsp/raspberry-pi/raspi4/driver/SConscript
 create mode 100644 bsp/raspberry-pi/raspi4/driver/board.c
 create mode 100644 bsp/raspberry-pi/raspi4/driver/board.h
 create mode 100644 bsp/raspberry-pi/raspi4/driver/drv_gpio.c
 create mode 100644 bsp/raspberry-pi/raspi4/driver/drv_gpio.h
 create mode 100644 bsp/raspberry-pi/raspi4/driver/drv_uart.c
 create mode 100644 bsp/raspberry-pi/raspi4/driver/drv_uart.h
 create mode 100644 bsp/raspberry-pi/raspi4/driver/iomap.h
 create mode 100644 bsp/raspberry-pi/raspi4/link.lds
 create mode 100644 bsp/raspberry-pi/raspi4/rtconfig.h
 create mode 100644 bsp/raspberry-pi/raspi4/rtconfig.py
 create mode 100644 libcpu/aarch64/common/SConscript
 create mode 100644 libcpu/aarch64/common/armv8.h
 create mode 100644 libcpu/aarch64/common/cache.S
 create mode 100644 libcpu/aarch64/common/context_gcc.S
 create mode 100644 libcpu/aarch64/common/cp15.h
 create mode 100644 libcpu/aarch64/common/cpu.c
 create mode 100644 libcpu/aarch64/common/cpu_gcc.S
 create mode 100644 libcpu/aarch64/common/gic/SConscript
 create mode 100644 libcpu/aarch64/common/gic/gic_pl400.c
 create mode 100644 libcpu/aarch64/common/gic/gic_pl400.h
 create mode 100644 libcpu/aarch64/common/mmu.c
 create mode 100644 libcpu/aarch64/common/mmu.h
 create mode 100644 libcpu/aarch64/common/startup_gcc.S
 create mode 100644 libcpu/aarch64/common/vector_gcc.S
 delete mode 100644 libcpu/aarch64/cortex-a53/armv8.h
 delete mode 100644 libcpu/aarch64/cortex-a53/cache.S
 delete mode 100644 libcpu/aarch64/cortex-a53/context_gcc.S
 delete mode 100644 libcpu/aarch64/cortex-a53/cp15.h
 delete mode 100644 libcpu/aarch64/cortex-a53/cpu.c
 delete mode 100644 libcpu/aarch64/cortex-a53/cpu_gcc.S
 delete mode 100644 libcpu/aarch64/cortex-a53/mmu.c
 delete mode 100644 libcpu/aarch64/cortex-a53/mmu.h
 delete mode 100644 libcpu/aarch64/cortex-a53/startup_gcc.S
 delete mode 100644 libcpu/aarch64/cortex-a53/vector_gcc.S
 create mode 100644 libcpu/aarch64/cortex-a57/SConscript
 create mode 100644 libcpu/aarch64/cortex-a57/entry_point.S
 create mode 100644 libcpu/aarch64/cortex-a57/interrupt.c
 create mode 100644 libcpu/aarch64/cortex-a57/interrupt.h
 create mode 100644 libcpu/aarch64/cortex-a57/stack.c
 create mode 100644 libcpu/aarch64/cortex-a57/trap.c

(limited to 'libcpu')

diff --git a/bsp/raspberry-pi/raspi4/.config b/bsp/raspberry-pi/raspi4/.config
new file mode 100644
index 0000000000..e300d0217b
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/.config
@@ -0,0 +1,455 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=2048
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
+CONFIG_RT_VER_NUM=0x40003
+CONFIG_ARCH_CPU_64BIT=y
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# Privated Packages of RealThread
+#
+# CONFIG_PKG_USING_CODEC is not set
+# CONFIG_PKG_USING_PLAYER is not set
+# CONFIG_PKG_USING_MPLAYER is not set
+# CONFIG_PKG_USING_PERSIMMON_SRC is not set
+# CONFIG_PKG_USING_JS_PERSIMMON is not set
+# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
+
+#
+# Network Utilities
+#
+# CONFIG_PKG_USING_WICED is not set
+# CONFIG_PKG_USING_CLOUDSDK is not set
+# CONFIG_PKG_USING_POWER_MANAGER is not set
+# CONFIG_PKG_USING_RT_OTA is not set
+# CONFIG_PKG_USING_RDBD_SRC is not set
+# CONFIG_PKG_USING_RTINSIGHT is not set
+# CONFIG_PKG_USING_SMARTCONFIG is not set
+# CONFIG_PKG_USING_RTX is not set
+# CONFIG_RT_USING_TESTCASE is not set
+# CONFIG_PKG_USING_NGHTTP2 is not set
+# CONFIG_PKG_USING_AVS is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_STS is not set
+# CONFIG_PKG_USING_DLMS is not set
+# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
+# CONFIG_PKG_USING_ZBAR is not set
+CONFIG_BCM2711_SOC=y
+# CONFIG_BSP_SUPPORT_FPU is not set
+
+#
+# Hardware Drivers Config
+#
+
+#
+# BCM Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_RT_USING_UART0=y
+CONFIG_BSP_USING_GIC=y
+CONFIG_BSP_USING_GIC400=y
+# CONFIG_BSP_USING_GIC500 is not set
+CONFIG_BSP_USING_PIN=y
+CONFIG_BSP_USING_CORETIMER=y
+# CONFIG_BSP_USING_SYSTIMER is not set
+# CONFIG_BSP_USING_WDT is not set
+# CONFIG_BSP_USING_RTC is not set
+# CONFIG_BSP_USING_SDIO is not set
+
+#
+# Board Peripheral Drivers
+#
+# CONFIG_BSP_USING_HDMI is not set
diff --git a/bsp/raspberry-pi/raspi4/Kconfig b/bsp/raspberry-pi/raspi4/Kconfig
new file mode 100644
index 0000000000..e71ed3d54b
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/Kconfig
@@ -0,0 +1,29 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config BCM2711_SOC
+    bool
+    select ARCH_ARM_CORTEX_A57
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_CPU_64BIT
+    default y
+
+source "driver/Kconfig"
diff --git a/bsp/raspberry-pi/raspi4/README.md b/bsp/raspberry-pi/raspi4/README.md
new file mode 100644
index 0000000000..28e00f96c0
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/README.md
@@ -0,0 +1,100 @@
+# Raspberry PI 3-64板级支持包说明
+
+## 1. 简介
+
+树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发，莓派3有三个发行版本：
+
+* B : 4核 Broadcom BCM2837 (ARMv8-A) 1.2GHz，双核VideoCore IV GPU，1GB内存，100 Base-T Ethernet
+* B+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 1GB LPDDR2 SDRAM， GigaE over USB 2.0
+* A+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 512MB LPDDR2 SDRAM
+
+这份RT-Thread BSP是针对 Raspberry Pi 3 64位模式的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
+
+
+## 2. 编译说明
+
+### 2.1 Window上的环境搭建
+
+Windows环境下推荐使用[env工具][1]进行编译。
+
+首先下载Linux上的gcc工具，版本为gcc-arm-8.3选择aarch64-elf就可以。
+
+将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。
+
+接着修改`bsp\raspberry-pi\raspi3-64\rtconfig.py`
+
+修改路径：
+
+```
+EXEC_PATH = r'E:/env_released_1.1.2/env/tools/gnu_gcc/arm_gcc/gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf/bin'
+```
+
+然后在`bsp\raspberry-pi\raspi3-64\`下输入scons编译即可。
+
+### 2.2 Linux上的环境搭建
+
+Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。
+
+直接进入`bsp\raspberry-pi\raspi3-64`，输入scons编译即可。
+
+
+## 3. 执行
+
+### 3.1 下载[raspbian镜像][3]，生成可以运行的raspbian SD卡
+
+Windows下，去[etcher.io][4]下载etcher,这是个可以烧写img的工具
+
+解开下载的镜像文件, linux下使用如下的命令
+
+```
+unzip 2018-06-27-raspbian-stretch-lite.zip
+```
+
+准备一张空SD卡，linux环境下，插入电脑并执行
+
+```
+sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync
+```
+
+**注意: /dev/xxx 要换成真实环境中的SD卡所在设置，千万不要弄错。**
+
+Windows环境下，执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。
+
+最后把kernel8.img放入SD boot分区，删除其它 kernel*.img。
+
+### 3.2 准备好串口线
+
+目前版本是使用raspi3的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示(图片中的板子是pi2，GPIO引脚是一样的)：
+
+![raspi2](figures/raspi_uart.png)
+
+串口参数： 115200 8N1 ，硬件和软件流控为关。
+
+按上面的方法做好SD卡后，插入树莓派，通电可以在串口上看到如下所示的输出信息：
+
+```text
+ heap: 0x00020b20 - 0x00400000
+
+ \ | /
+- RT -     Thread Operating System
+ / | \     3.1.0 build Aug 23 2019
+ 2006 - 2019 Copyright by rt-thread team
+Hello RT-Thread!
+msh >
+```
+
+## 4. 支持情况
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | UART0|
+
+## 5. 联系人信息
+
+维护人：[bernard][5]
+
+[1]: https://www.rt-thread.org/page/download.html
+[2]: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads
+[3]: https://downloads.raspberrypi.org/raspbian_lite_latest
+[4]: https://etcher.io
+[5]: https://github.com/BernardXiong
diff --git a/bsp/raspberry-pi/raspi4/SConscript b/bsp/raspberry-pi/raspi4/SConscript
new file mode 100644
index 0000000000..c7ef7659ec
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/raspberry-pi/raspi4/SConstruct b/bsp/raspberry-pi/raspi4/SConstruct
new file mode 100644
index 0000000000..93f349aab8
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/SConstruct
@@ -0,0 +1,30 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# make a building
+DoBuilding(TARGET, objs)
+
diff --git a/bsp/raspberry-pi/raspi4/applications/SConscript b/bsp/raspberry-pi/raspi4/applications/SConscript
new file mode 100644
index 0000000000..533df8ac31
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/applications/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/raspberry-pi/raspi4/applications/main.c b/bsp/raspberry-pi/raspi4/applications/main.c
new file mode 100644
index 0000000000..9664e67d01
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/applications/main.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+int main(int argc, char** argv)
+{
+    rt_kprintf("Hi, this is RT-Thread!!\n");
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi4/driver/Kconfig b/bsp/raspberry-pi/raspi4/driver/Kconfig
new file mode 100644
index 0000000000..208b4b4300
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/Kconfig
@@ -0,0 +1,97 @@
+
+config BSP_SUPPORT_FPU
+    bool "Using Float"
+    default n
+
+menu "Hardware Drivers Config"
+    menu "BCM Peripheral Drivers"
+        menuconfig BSP_USING_UART
+            bool "Using UART"
+            select RT_USING_SERIAL
+            default y
+
+            if BSP_USING_UART
+                config RT_USING_UART0
+                bool "Enabel UART 0"
+                default y
+            endif
+            
+        menuconfig BSP_USING_GIC
+            bool "Enable GIC"
+            select RT_USING_GIC
+            default y
+        if BSP_USING_GIC
+            config BSP_USING_GIC400
+                bool "Enable GIC400"
+                default y
+            config BSP_USING_GIC500
+                bool "Enable GIC500"
+                default n
+        endif
+
+        config BSP_USING_PIN
+            bool "Using PIN"
+            select RT_USING_PIN
+            default y
+
+        config BSP_USING_CORETIMER
+            bool "Using core timer"
+            select RT_USING_CORETIMER
+            default y
+
+        menuconfig BSP_USING_SYSTIMER
+            bool "Enable SYSTIMER"
+            select BSP_USING_SYSTIMER
+            default n
+
+        if  BSP_USING_SYSTIMER
+            config RT_USING_SYSTIMER1
+                bool "Enable sys timer1"
+                default n
+            config RT_USING_SYSTIMER3
+                bool "Enable sys timer3"
+                default n
+        endif
+
+        config BSP_USING_WDT
+            bool "Enable WDT"
+            select RT_USING_WDT
+            default n
+
+        menuconfig BSP_USING_RTC
+            bool "Enable RTC"
+            select RT_USING_RTC
+            default n
+
+        if BSP_USING_RTC
+            config BSP_USING_ALARM
+                bool "Enable Alarm"
+                select RT_USING_ALARM
+                default n
+        endif
+        
+        menuconfig BSP_USING_SDIO
+            bool "Enable SDIO"
+            select RT_USING_SDIO
+            default n
+
+        if BSP_USING_SDIO
+            config BSP_USING_SDIO0
+                bool "Enable SDIO0"
+                select RT_USING_SDIO
+                default n
+        endif
+    endmenu
+
+    menu "Board Peripheral Drivers"
+        menuconfig BSP_USING_HDMI
+            bool "Enable HDMI"
+            default n
+
+        if BSP_USING_HDMI
+            config BSP_USING_HDMI_DISPLAY
+                bool "HDMI DISPLAY"
+                default n
+        endif
+    endmenu
+endmenu
diff --git a/bsp/raspberry-pi/raspi4/driver/SConscript b/bsp/raspberry-pi/raspi4/driver/SConscript
new file mode 100644
index 0000000000..533df8ac31
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/raspberry-pi/raspi4/driver/board.c b/bsp/raspberry-pi/raspi4/driver/board.c
new file mode 100644
index 0000000000..9716755b72
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/board.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "drv_uart.h"
+
+#include "cp15.h"
+#include "mmu.h"
+
+static rt_uint64_t timerStep;
+// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
+#define CORE0_TIMER_IRQ_CTRL    HWREG32(0xFF800040)
+#define TIMER_IRQ               30
+#define NON_SECURE_TIMER_IRQ    (1 << 1)
+
+int rt_hw_get_gtimer_frq(void);
+void rt_hw_set_gtimer_val(rt_uint64_t value);
+int rt_hw_get_gtimer_val(void);
+int rt_hw_get_cntpct_val(void);
+void rt_hw_gtimer_enable(void);
+
+void core0_timer_enable_interrupt_controller()
+{
+    CORE0_TIMER_IRQ_CTRL |= NON_SECURE_TIMER_IRQ;
+}
+
+void rt_hw_timer_isr(int vector, void *parameter)
+{
+    rt_hw_set_gtimer_val(timerStep);
+    rt_tick_increase();
+}
+
+void rt_hw_timer_init(void)
+{
+    rt_hw_interrupt_install(TIMER_IRQ, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_umask(TIMER_IRQ);
+    __ISB();
+    timerStep = rt_hw_get_gtimer_frq();
+    __DSB();
+    timerStep /= RT_TICK_PER_SECOND;
+    
+    rt_hw_gtimer_enable();
+    rt_hw_set_gtimer_val(timerStep);
+    core0_timer_enable_interrupt_controller();
+}
+
+void idle_wfi(void)
+{
+    asm volatile ("wfi");
+}
+
+/**
+ *  Initialize the Hardware related stuffs. Called from rtthread_startup() 
+ *  after interrupt disabled.
+ */
+void rt_hw_board_init(void)
+{
+    mmu_init();
+    armv8_map(0, 0, 0x6400000, MEM_ATTR_MEMORY);
+    armv8_map(0xFE200000, 0xFE200000, 0x200000, MEM_ATTR_IO);//uart gpio
+    armv8_map(0xFF800000, 0xFF800000, 0x200000, MEM_ATTR_IO);//gic timer
+    mmu_enable();
+
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
+    rt_hw_vector_init();    // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors);
+
+    /* initialize timer for os tick */
+    rt_hw_timer_init();
+    rt_thread_idle_sethook(idle_wfi);
+
+    /* initialize uart */
+    rt_hw_uart_init();      // driver/drv_uart.c
+#ifdef RT_USING_CONSOLE
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif /* RT_USING_CONSOLE */
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
\ No newline at end of file
diff --git a/bsp/raspberry-pi/raspi4/driver/board.h b/bsp/raspberry-pi/raspi4/driver/board.h
new file mode 100644
index 0000000000..66805464f2
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/board.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include <stdint.h>
+
+extern unsigned char __bss_start;
+extern unsigned char __bss_end;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__bss_end
+#define RT_HW_HEAP_END      (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
+
+void rt_hw_board_init(void);
+
+#endif
+
diff --git a/bsp/raspberry-pi/raspi4/driver/drv_gpio.c b/bsp/raspberry-pi/raspi4/driver/drv_gpio.c
new file mode 100644
index 0000000000..4317a358e0
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/drv_gpio.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include "drv_gpio.h"
+
+#ifdef BSP_USING_PIN
+
+static void raspi_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
+{
+    uint32_t fselnum = pin / 10;
+    uint32_t fselrest = pin % 10;
+
+    uint32_t gpfsel = 0;
+    gpfsel &= ~((uint32_t)(0x07 << (fselrest * 3)));
+    gpfsel |= (uint32_t)(mode << (fselrest * 3));
+
+    switch (fselnum)
+    {
+    case 0:
+        GPIO_REG_GPFSEL0(GPIO_BASE) = gpfsel;
+        break;
+    case 1:
+        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+        break;
+    case 2:
+        GPIO_REG_GPFSEL2(GPIO_BASE) = gpfsel;
+        break;
+    case 3:
+        GPIO_REG_GPFSEL3(GPIO_BASE) = gpfsel;
+        break;
+    case 4:
+        GPIO_REG_GPFSEL4(GPIO_BASE) = gpfsel;
+        break;
+    case 5:
+        GPIO_REG_GPFSEL5(GPIO_BASE) = gpfsel;
+        break;
+    default:
+        break;
+    }
+}
+
+static void raspi_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
+{
+    uint32_t num = pin / 32;
+
+    if(num == 0)
+    {
+        if(value == 0)
+        {
+            GPIO_REG_GPSET0(GPIO_BASE) = 1 << (pin % 32);
+        }
+        else
+        {
+            GPIO_REG_GPCLR0(GPIO_BASE) = 1 << (pin % 32);
+        }
+    }
+    else
+    {
+        if(value == 0)
+        {
+            GPIO_REG_GPSET1(GPIO_BASE) = 1 << (pin % 32);
+        }
+        else
+        {
+            GPIO_REG_GPCLR1(GPIO_BASE) = 1 << (pin % 32);
+        }
+        
+    }
+}
+
+static int raspi_pin_read(struct rt_device *device, rt_base_t pin)
+{
+    return 0;
+}
+
+static rt_err_t raspi_pin_attach_irq(struct rt_device *device, rt_int32_t pin, rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    return RT_EOK;
+}
+
+static rt_err_t raspi_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    return RT_EOK;
+}
+
+rt_err_t raspi_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+    return RT_EOK;
+}
+
+static const struct rt_pin_ops ops =
+{
+    raspi_pin_mode,
+    raspi_pin_write,
+    raspi_pin_read,
+    raspi_pin_attach_irq,
+    raspi_pin_detach_irq,
+    raspi_pin_irq_enable,
+};
+#endif
+
+int rt_hw_gpio_init(void)
+{
+#ifdef BSP_USING_PIN
+    rt_device_pin_register("gpio", &ops, RT_NULL);
+#endif
+
+    return 0;
+}
+INIT_DEVICE_EXPORT(rt_hw_gpio_init);
diff --git a/bsp/raspberry-pi/raspi4/driver/drv_gpio.h b/bsp/raspberry-pi/raspi4/driver/drv_gpio.h
new file mode 100644
index 0000000000..ebc9452cec
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/drv_gpio.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "interrupt.h"
+
+#define GPIO_BASE (0xFE000000 + 0x00200000)
+
+#define GPIO_REG_GPFSEL0(BASE)             HWREG32(BASE + 0x00)
+#define GPIO_REG_GPFSEL1(BASE)             HWREG32(BASE + 0x04)
+#define GPIO_REG_GPFSEL2(BASE)             HWREG32(BASE + 0x08)
+#define GPIO_REG_GPFSEL3(BASE)             HWREG32(BASE + 0x0C)
+#define GPIO_REG_GPFSEL4(BASE)             HWREG32(BASE + 0x10)
+#define GPIO_REG_GPFSEL5(BASE)             HWREG32(BASE + 0x14)
+#define GPIO_REG_REV0(BASE)                HWREG32(BASE + 0x18)
+#define GPIO_REG_GPSET0(BASE)              HWREG32(BASE + 0x1C)
+#define GPIO_REG_GPSET1(BASE)              HWREG32(BASE + 0x20)
+#define GPIO_REG_REV1(BASE)                HWREG32(BASE + 0x24)
+#define GPIO_REG_GPCLR0(BASE)              HWREG32(BASE + 0x28)
+#define GPIO_REG_GPCLR1(BASE)              HWREG32(BASE + 0x2C)
+#define GPIO_REG_REV2(BASE)                HWREG32(BASE + 0x30)
+#define GPIO_REG_GPLEV0(BASE)              HWREG32(BASE + 0x34)
+#define GPIO_REG_GPLEV1(BASE)              HWREG32(BASE + 0x38)
+#define GPIO_REG_REV3(BASE)                HWREG32(BASE + 0x3C)
+#define GPIO_REG_GPEDS0(BASE)              HWREG32(BASE + 0x40)
+#define GPIO_REG_GPEDS1(BASE)              HWREG32(BASE + 0x44)
+#define GPIO_REG_REV4(BASE)                HWREG32(BASE + 0x48)
+#define GPIO_REG_GPREN0(BASE)              HWREG32(BASE + 0x4C)
+#define GPIO_REG_GPREN1(BASE)              HWREG32(BASE + 0x50)
+#define GPIO_REG_REV5(BASE)                HWREG32(BASE + 0x54)
+#define GPIO_REG_GPFEN0(BASE)              HWREG32(BASE + 0x58)
+#define GPIO_REG_GPFEN1(BASE)              HWREG32(BASE + 0x5C)
+#define GPIO_REG_REV6(BASE)                HWREG32(BASE + 0x60)
+#define GPIO_REG_GPHEN0(BASE)              HWREG32(BASE + 0x64)
+#define GPIO_REG_GPHEN1(BASE)              HWREG32(BASE + 0x68)
+#define GPIO_REG_REV7(BASE)                HWREG32(BASE + 0x6C)
+#define GPIO_REG_GPLEN0(BASE)              HWREG32(BASE + 0x70)
+#define GPIO_REG_GPLEN1(BASE)              HWREG32(BASE + 0x74)
+#define GPIO_REG_REV8(BASE)                HWREG32(BASE + 0x78)
+#define GPIO_REG_GPAREN0(BASE)             HWREG32(BASE + 0x7C)
+#define GPIO_REG_GPAREN1(BASE)             HWREG32(BASE + 0x80)
+#define GPIO_REG_REV11(BASE)               HWREG32(BASE + 0x84)
+#define GPIO_REG_GPAFEN0(BASE)             HWREG32(BASE + 0x88)
+#define GPIO_REG_GPAFEN1(BASE)             HWREG32(BASE + 0x8C)
+#define GPIO_REG_REV10(BASE)               HWREG32(BASE + 0x90)
+#define GPIO_REG_GPPUD(BASE)               HWREG32(BASE + 0x94)
+#define GPIO_REG_GPPUDCLK0(BASE)           HWREG32(BASE + 0x98)
+#define GPIO_REG_GPPUDCLK1(BASE)           HWREG32(BASE + 0x9C)
+#define GPIO_REG_REV9(BASE)                HWREG32(BASE + 0xA0)
+#define GPIO_REG_TEST(BASE)                HWREG32(BASE + 0xA4)
+
+typedef enum {
+    INPUT = 0b000,
+    OUTPUT = 0b001,
+    ALT0 = 0b100,
+    ALT1 = 0b101,
+    ALT2 = 0b110,
+    ALT3 = 0b111,
+    ALT4 = 0b011,
+    ALT5 = 0b010
+} GPIO_FUNC;
+
+
+int rt_hw_gpio_init(void);
+
+#endif /* __DRV_GPIO_H__ */
diff --git a/bsp/raspberry-pi/raspi4/driver/drv_uart.c b/bsp/raspberry-pi/raspi4/driver/drv_uart.c
new file mode 100644
index 0000000000..a7ac1b5892
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/drv_uart.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include "board.h"
+#include "drv_uart.h"
+#include "drv_gpio.h"
+
+#define UART0_BASE            (0xFE000000 + 0x00201000)
+#define PL011_BASE            UART0_BASE
+#define IRQ_PL011             (121 + 32)
+
+#define UART_REFERENCE_CLOCK 48000000
+
+struct hw_uart_device
+{
+    rt_ubase_t hw_base;
+    rt_uint32_t irqno;
+};
+
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct hw_uart_device *uart;
+    uint32_t bauddiv = (UART_REFERENCE_CLOCK / cfg->baud_rate)* 1000 / 16;
+    uint32_t ibrd = bauddiv / 1000;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+    if(uart->hw_base == PL011_BASE)
+    {
+        uint32_t gpfsel = 0;
+
+        gpfsel &= ~((uint32_t)(0x07 << (4 * 3)));
+        gpfsel |= (uint32_t)(ALT0 << (4 * 3));
+        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+
+        gpfsel &= ~((uint32_t)(0x07 << (5 * 3)));
+        gpfsel |= (uint32_t)(ALT0 << (5 * 3));
+        GPIO_REG_GPFSEL1(GPIO_BASE) = gpfsel;
+
+        PL011_REG_CR(uart->hw_base) = 0;/*Clear UART setting*/
+        PL011_REG_LCRH(uart->hw_base) = 0;/*disable FIFO*/
+        PL011_REG_IBRD(uart->hw_base) = ibrd;
+        PL011_REG_FBRD(uart->hw_base) = (((bauddiv - ibrd * 1000) * 64 + 500) / 1000);
+        PL011_REG_LCRH(uart->hw_base) = PL011_LCRH_WLEN_8;/*FIFO*/
+        PL011_REG_CR(uart->hw_base) = PL011_CR_UARTEN | PL011_CR_TXE | PL011_CR_RXE;/*art enable, TX/RX enable*/
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        PL011_REG_IMSC(uart->hw_base) &= ~((uint32_t)PL011_IMSC_RXIM);
+        rt_hw_interrupt_mask(uart->irqno);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        PL011_REG_IMSC(uart->hw_base) |= PL011_IMSC_RXIM;
+        rt_hw_interrupt_umask(uart->irqno);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    while ((PL011_REG_FR(uart->hw_base) & PL011_FR_TXFF));
+    PL011_REG_DR(uart->hw_base) = (uint8_t)c;
+
+    return 1;
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    int ch = -1;
+    struct hw_uart_device *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct hw_uart_device *)serial->parent.user_data;
+
+    if((PL011_REG_FR(uart->hw_base) & PL011_FR_RXFE) == 0)
+    {
+        ch = PL011_REG_DR(uart->hw_base) & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+static void rt_hw_uart_isr(int irqno, void *param)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device*)param; 
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    PL011_REG_ICR(UART0_BASE) = PL011_INTERRUPT_RECEIVE;
+}
+
+
+/* UART device driver structure */
+static struct hw_uart_device _uart0_device =
+{
+    PL011_BASE,
+    IRQ_PL011,
+};
+
+static struct rt_serial_device _serial0;
+
+int rt_hw_uart_init(void)
+{
+    struct hw_uart_device *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    uart = &_uart0_device;
+
+    _serial0.ops    = &_uart_ops;
+    _serial0.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&_serial0, "uart",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+    rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, &_serial0, "uart");
+
+    return 0;
+}
diff --git a/bsp/raspberry-pi/raspi4/driver/drv_uart.h b/bsp/raspberry-pi/raspi4/driver/drv_uart.h
new file mode 100644
index 0000000000..4f23d7b46e
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/drv_uart.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef DRV_UART_H__
+#define DRV_UART_H__
+
+// register's bit
+#define PL011_FR_RI          (1 << 8)
+#define PL011_FR_TXFE        (1 << 7)
+#define PL011_FR_RXFF        (1 << 6)
+#define PL011_FR_TXFF        (1 << 5)
+#define PL011_FR_RXFE        (1 << 4)
+#define PL011_FR_BUSY        (1 << 3)
+#define PL011_FR_DCD         (1 << 2)
+#define PL011_FR_DSR         (1 << 1)
+#define PL011_FR_CTS         (1 << 0)
+
+#define PL011_LCRH_SPS       (1 << 7)
+#define PL011_LCRH_WLEN_8    (3 << 5)
+#define PL011_LCRH_WLEN_7    (2 << 5)
+#define PL011_LCRH_WLEN_6    (1 << 5)
+#define PL011_LCRH_WLEN_5    (0 << 5)
+#define PL011_LCRH_FEN       (1 << 4)
+#define PL011_LCRH_STP2      (1 << 3)
+#define PL011_LCRH_EPS       (1 << 2)
+#define PL011_LCRH_PEN       (1 << 1)
+#define PL011_LCRH_BRK       (1 << 0)
+
+#define PL011_CR_CTSEN       (1 << 15)
+#define PL011_CR_RTSEN       (1 << 14)
+#define PL011_CR_RTS         (1 << 11)
+#define PL011_CR_DTR         (1 << 10)
+#define PL011_CR_RXE         (1 << 9)
+#define PL011_CR_TXE         (1 << 8)
+#define PL011_CR_LBE         (1 << 7)
+#define PL011_CR_SIRLP       (1 << 2)
+#define PL011_CR_SIREN       (1 << 1)
+#define PL011_CR_UARTEN      (1 << 0)
+
+#define PL011_IMSC_TXIM      (1 << 5)
+#define PL011_IMSC_RXIM      (1 << 4)
+
+#define PL011_INTERRUPT_OVERRUN_ERROR   (1 << 10)
+#define PL011_INTERRUPT_BREAK_ERROR     (1 << 9)
+#define PL011_INTERRUPT_PARITY_ERROR    (1 << 8)
+#define PL011_INTERRUPT_FRAMING_ERROR   (1 << 7)
+#define PL011_INTERRUPT_RECEIVE_TIMEOUT (1 << 6)
+#define PL011_INTERRUPT_TRANSMIT        (1 << 5)
+#define PL011_INTERRUPT_RECEIVE         (1 << 4)
+#define PL011_INTERRUPT_nUARTCTS        (1 << 1)
+
+#define PL011_REG_DR(BASE)              HWREG32(BASE + 0x00)
+#define PL011_REG_RSRECR(BASE)          HWREG32(BASE + 0x04)
+#define PL011_REG_RESERVED0(BASE)       HWREG32(BASE + 0x08)
+#define PL011_REG_FR(BASE)              HWREG32(BASE + 0x18)
+#define PL011_REG_RESERVED1(BASE)       HWREG32(BASE + 0x1C)
+#define PL011_REG_ILPR(BASE)            HWREG32(BASE + 0x20)
+#define PL011_REG_IBRD(BASE)            HWREG32(BASE + 0x24)
+#define PL011_REG_FBRD(BASE)            HWREG32(BASE + 0x28)
+#define PL011_REG_LCRH(BASE)            HWREG32(BASE + 0x2C)
+#define PL011_REG_CR(BASE)              HWREG32(BASE + 0x30)
+#define PL011_REG_IFLS(BASE)            HWREG32(BASE + 0x34)
+#define PL011_REG_IMSC(BASE)            HWREG32(BASE + 0x38)
+#define PL011_REG_RIS(BASE)             HWREG32(BASE + 0x3C)
+#define PL011_REG_MIS(BASE)             HWREG32(BASE + 0x40)
+#define PL011_REG_ICR(BASE)             HWREG32(BASE + 0x44)
+#define PL011_REG_DMACR(BASE)           HWREG32(BASE + 0x48)
+#define PL011_REG_RESERVED2(BASE)       HWREG32(BASE + 0x4C)
+#define PL011_REG_ITCR(BASE)            HWREG32(BASE + 0x80)
+#define PL011_REG_ITIP(BASE)            HWREG32(BASE + 0x84)
+#define PL011_REG_ITOP(BASE)            HWREG32(BASE + 0x88)
+#define PL011_REG_TDR(BASE)             HWREG32(BASE + 0x8C)
+
+int rt_hw_uart_init(void);
+
+#endif /* DRV_UART_H__ */
+
diff --git a/bsp/raspberry-pi/raspi4/driver/iomap.h b/bsp/raspberry-pi/raspi4/driver/iomap.h
new file mode 100644
index 0000000000..00fc2025d9
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/driver/iomap.h
@@ -0,0 +1,13 @@
+#ifndef __RASPI4_H__
+#define __RASPI4_H__
+
+#define INTC_BASE   0xff800000
+#define GIC_V2_DISTRIBUTOR_BASE     (INTC_BASE + 0x00041000)
+#define GIC_V2_CPU_INTERFACE_BASE   (INTC_BASE + 0x00042000)
+#define GIC_V2_HYPERVISOR_BASE      (INTC_BASE + 0x00044000)
+#define GIC_V2_VIRTUAL_CPU_BASE     (INTC_BASE + 0x00046000)
+
+#define GIC_PL400_DISTRIBUTOR_PPTR  GIC_V2_DISTRIBUTOR_BASE
+#define GIC_PL400_CONTROLLER_PPTR   GIC_V2_CPU_INTERFACE_BASE
+
+#endif
\ No newline at end of file
diff --git a/bsp/raspberry-pi/raspi4/link.lds b/bsp/raspberry-pi/raspi4/link.lds
new file mode 100644
index 0000000000..b7b2dcc32c
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/link.lds
@@ -0,0 +1,153 @@
+/*
+ * File      : link.lds
+ * COPYRIGHT (C) 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * 2017-5-30     bernard       first version
+ */
+
+/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */
+
+SECTIONS
+{
+    . = 0x80000;
+    . = ALIGN(4096);
+    .text :
+    {
+        KEEP(*(.text.entrypoint))       /* The entry point */
+        *(.vectors)
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        *(COMMON)
+        
+        /* section information for finsh shell */
+        . = ALIGN(16);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(16);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(16);
+
+        /* section information for initial. */
+        . = ALIGN(16);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(16);
+
+        . = ALIGN(16);
+        _etext = .;
+    }
+
+    .eh_frame_hdr :
+    {
+         *(.eh_frame_hdr)
+         *(.eh_frame_entry)
+    }
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+
+    . = ALIGN(16);
+    .data :
+    {
+     *(.data)
+     *(.data.*)
+
+     *(.data1)
+     *(.data1.*)
+
+     . = ALIGN(16);
+     _gp = ABSOLUTE(.);     /* Base of small data */
+
+     *(.sdata)
+     *(.sdata.*)
+    }
+
+    . = ALIGN(16);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        KEEP(*(SORT(.ctors.*)))
+        KEEP(*(.ctors))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(16);
+    .bss :
+    {
+        PROVIDE(__bss_start = .);
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        
+        PROVIDE(__bss_end = .);
+    }
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+
+__bss_size = (__bss_end - __bss_start)>>3;
diff --git a/bsp/raspberry-pi/raspi4/rtconfig.h b/bsp/raspberry-pi/raspi4/rtconfig.h
new file mode 100644
index 0000000000..049e117559
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/rtconfig.h
@@ -0,0 +1,179 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 2048
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 2048
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart"
+#define RT_VER_NUM 0x40003
+#define ARCH_CPU_64BIT
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_POSIX
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+
+/* Privated Packages of RealThread */
+
+
+/* Network Utilities */
+
+#define BCM2711_SOC
+
+/* Hardware Drivers Config */
+
+/* BCM Peripheral Drivers */
+
+#define BSP_USING_UART
+#define RT_USING_UART0
+#define BSP_USING_GIC
+#define BSP_USING_GIC400
+#define BSP_USING_PIN
+#define BSP_USING_CORETIMER
+
+/* Board Peripheral Drivers */
+
+
+#endif
diff --git a/bsp/raspberry-pi/raspi4/rtconfig.py b/bsp/raspberry-pi/raspi4/rtconfig.py
new file mode 100644
index 0000000000..228ec0176a
--- /dev/null
+++ b/bsp/raspberry-pi/raspi4/rtconfig.py
@@ -0,0 +1,51 @@
+import os
+
+# toolchains options
+ARCH        ='aarch64'
+CPU         ='cortex-a57'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+PLATFORM    = 'gcc'
+EXEC_PATH   = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'  
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    # PREFIX = 'arm-none-eabi-'
+    PREFIX = 'aarch64-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE = ' -march=armv8-a -mtune=cortex-a57'
+    CFLAGS = DEVICE + ' -Wall'
+    AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
+    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
diff --git a/libcpu/aarch64/SConscript b/libcpu/aarch64/SConscript
index 453afe4b3e..5fca2b473b 100644
--- a/libcpu/aarch64/SConscript
+++ b/libcpu/aarch64/SConscript
@@ -9,6 +9,9 @@ cwd   = GetCurrentDir()
 group = []
 list  = os.listdir(cwd)
 
+# add common code files
+group = group + SConscript(os.path.join('common', 'SConscript'))
+
 # cpu porting code files
 if rtconfig.CPU != 'common':
     group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
diff --git a/libcpu/aarch64/common/SConscript b/libcpu/aarch64/common/SConscript
new file mode 100644
index 0000000000..72fb8e26c3
--- /dev/null
+++ b/libcpu/aarch64/common/SConscript
@@ -0,0 +1,24 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
+
+# build for sub-directory
+list = os.listdir(cwd)
+objs = []
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+group = group + objs
+
+
+Return('group')
diff --git a/libcpu/aarch64/common/armv8.h b/libcpu/aarch64/common/armv8.h
new file mode 100644
index 0000000000..4350890544
--- /dev/null
+++ b/libcpu/aarch64/common/armv8.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ */
+
+#ifndef __ARMV8_H__
+#define __ARMV8_H__
+
+/* the exception stack without VFP registers */
+struct rt_hw_exp_stack
+{
+	unsigned long long pc;
+	unsigned long long spsr;
+	unsigned long long x30;
+	unsigned long long xz;
+	unsigned long long x28;
+	unsigned long long x29;
+	unsigned long long x26;
+	unsigned long long x27;
+	unsigned long long x24;
+	unsigned long long x25;
+	unsigned long long x22;
+	unsigned long long x23;
+	unsigned long long x20;
+	unsigned long long x21;
+	unsigned long long x18;	
+	unsigned long long x19;
+	unsigned long long x16;
+	unsigned long long x17;
+	unsigned long long x14;
+	unsigned long long x15;
+	unsigned long long x12;
+	unsigned long long x13;
+	unsigned long long x10;
+	unsigned long long x11;
+	unsigned long long x8;
+	unsigned long long x9;
+	unsigned long long x6;
+	unsigned long long x7;
+	unsigned long long x4;
+	unsigned long long x5;
+	unsigned long long x2;
+	unsigned long long x3;
+	unsigned long long x0;
+	unsigned long long x1;
+};
+
+#define SP_ELx						( ( unsigned long long ) 0x01 )
+#define SP_EL0						( ( unsigned long long ) 0x00 )
+#define PSTATE_EL1					( ( unsigned long long ) 0x04 )
+#define PSTATE_EL2					( ( unsigned long long ) 0x08 )
+#define PSTATE_EL3					( ( unsigned long long ) 0x0c )
+
+rt_ubase_t rt_hw_get_current_el(void);
+void rt_hw_set_elx_env(void);
+void rt_hw_set_current_vbar(rt_ubase_t addr);
+
+#endif
diff --git a/libcpu/aarch64/common/cache.S b/libcpu/aarch64/common/cache.S
new file mode 100644
index 0000000000..7f295a2b02
--- /dev/null
+++ b/libcpu/aarch64/common/cache.S
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author             Notes
+ * 2020-03-17     bigmagic           first version
+ */
+
+/*
+ * void __asm_dcache_level(level)
+ *
+ * flush or invalidate one level cache.
+ *
+ * x0: cache level
+ * x1: 0 clean & invalidate, 1 invalidate only
+ * x2~x9: clobbered
+ */
+.globl __asm_dcache_level
+__asm_dcache_level:
+    lsl    x12, x0, #1
+    msr    csselr_el1, x12        /* select cache level */
+    isb                /* sync change of cssidr_el1 */
+    mrs    x6, ccsidr_el1        /* read the new cssidr_el1 */
+    and    x2, x6, #7        /* x2 <- log2(cache line size)-4 */
+    add    x2, x2, #4        /* x2 <- log2(cache line size) */
+    mov    x3, #0x3ff
+    and    x3, x3, x6, lsr #3    /* x3 <- max number of #ways */
+    clz    w5, w3            /* bit position of #ways */
+    mov    x4, #0x7fff
+    and    x4, x4, x6, lsr #13    /* x4 <- max number of #sets */
+    /* x12 <- cache level << 1 */
+    /* x2 <- line length offset */
+    /* x3 <- number of cache ways - 1 */
+    /* x4 <- number of cache sets - 1 */
+    /* x5 <- bit position of #ways */
+
+loop_set:
+    mov    x6, x3            /* x6 <- working copy of #ways */
+loop_way:
+    lsl    x7, x6, x5
+    orr    x9, x12, x7        /* map way and level to cisw value */
+    lsl    x7, x4, x2
+    orr    x9, x9, x7        /* map set number to cisw value */
+    tbz    w1, #0, 1f
+    dc    isw, x9
+    b    2f
+1:    dc    cisw, x9        /* clean & invalidate by set/way */
+2:    subs    x6, x6, #1        /* decrement the way */
+    b.ge    loop_way
+    subs    x4, x4, #1        /* decrement the set */
+    b.ge    loop_set
+
+    ret
+
+/*
+ * void __asm_flush_dcache_all(int invalidate_only)
+ *
+ * x0: 0 clean & invalidate, 1 invalidate only
+ *
+ * flush or invalidate all data cache by SET/WAY.
+ */
+.globl __asm_dcache_all
+__asm_dcache_all:
+    mov    x1, x0
+    dsb    sy
+    mrs    x10, clidr_el1        /* read clidr_el1 */
+    lsr    x11, x10, #24
+    and    x11, x11, #0x7        /* x11 <- loc */
+    cbz    x11, finished        /* if loc is 0, exit */
+    mov    x15, lr
+    mov    x0, #0            /* start flush at cache level 0 */
+    /* x0  <- cache level */
+    /* x10 <- clidr_el1 */
+    /* x11 <- loc */
+    /* x15 <- return address */
+
+loop_level:
+    lsl    x12, x0, #1
+    add    x12, x12, x0        /* x0 <- tripled cache level */
+    lsr    x12, x10, x12
+    and    x12, x12, #7        /* x12 <- cache type */
+    cmp    x12, #2
+    b.lt    skip            /* skip if no cache or icache */
+    bl    __asm_dcache_level    /* x1 = 0 flush, 1 invalidate */
+skip:
+    add    x0, x0, #1        /* increment cache level */
+    cmp    x11, x0
+    b.gt    loop_level
+
+    mov    x0, #0
+    msr    csselr_el1, x0        /* restore csselr_el1 */
+    dsb    sy
+    isb
+    mov    lr, x15
+
+finished:
+    ret
+
+.globl __asm_flush_dcache_all
+__asm_flush_dcache_all:
+    mov    x0, #0
+    b    __asm_dcache_all
+
+.globl __asm_invalidate_dcache_all
+__asm_invalidate_dcache_all:
+    mov    x0, #0x1
+    b    __asm_dcache_all
+
+/*
+ * void __asm_flush_dcache_range(start, end)
+ *
+ * clean & invalidate data cache in the range
+ *
+ * x0: start address
+ * x1: end address
+ */
+.globl __asm_flush_dcache_range
+__asm_flush_dcache_range:
+    mrs    x3, ctr_el0
+    lsr    x3, x3, #16
+    and    x3, x3, #0xf
+    mov    x2, #4
+    lsl    x2, x2, x3        /* cache line size */
+
+    /* x2 <- minimal cache line size in cache system */
+    sub    x3, x2, #1
+    bic    x0, x0, x3
+1:    dc    civac, x0    /* clean & invalidate data or unified cache */
+    add    x0, x0, x2
+    cmp    x0, x1
+    b.lo    1b
+    dsb    sy
+    ret
+
+/*
+ * void __asm_invalidate_icache_all(void)
+ *
+ * invalidate all tlb entries.
+ */
+.globl __asm_invalidate_icache_all
+__asm_invalidate_icache_all:
+    ic    ialluis
+    isb    sy
+    ret
+
+.globl __asm_flush_l3_cache
+__asm_flush_l3_cache:
+    mov    x0, #0            /* return status as success */
+    ret
\ No newline at end of file
diff --git a/libcpu/aarch64/common/context_gcc.S b/libcpu/aarch64/common/context_gcc.S
new file mode 100644
index 0000000000..934db7ed84
--- /dev/null
+++ b/libcpu/aarch64/common/context_gcc.S
@@ -0,0 +1,351 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-06     ZhaoXiaowei    the first version
+ */
+
+  /*
+ *enable gtimer
+ */
+.globl rt_hw_gtimer_enable
+rt_hw_gtimer_enable:
+	MOV X0,#1
+	MSR CNTP_CTL_EL0,X0
+	RET
+
+/*
+ *set gtimer CNTP_TVAL_EL0 value
+ */
+.globl rt_hw_set_gtimer_val
+rt_hw_set_gtimer_val:
+	MSR CNTP_TVAL_EL0,X0
+	RET
+
+/*
+ *get gtimer CNTP_TVAL_EL0 value
+ */
+.globl rt_hw_get_gtimer_val
+rt_hw_get_gtimer_val:
+	MRS X0,CNTP_TVAL_EL0
+	RET
+
+
+.globl rt_hw_get_cntpct_val
+rt_hw_get_cntpct_val:
+	MRS X0, CNTPCT_EL0
+	RET
+
+/*
+ *get gtimer frq value
+ */
+.globl rt_hw_get_gtimer_frq
+rt_hw_get_gtimer_frq:
+	MRS X0,CNTFRQ_EL0
+	RET
+
+.macro SAVE_CONTEXT
+
+    /* Switch to use the EL0 stack pointer. */
+    MSR 	SPSEL, #0
+
+    /* Save the entire context. */
+    STP 	X0, X1, [SP, #-0x10]!
+    STP 	X2, X3, [SP, #-0x10]!
+    STP 	X4, X5, [SP, #-0x10]!
+    STP 	X6, X7, [SP, #-0x10]!
+    STP 	X8, X9, [SP, #-0x10]!
+    STP 	X10, X11, [SP, #-0x10]!
+    STP 	X12, X13, [SP, #-0x10]!
+    STP 	X14, X15, [SP, #-0x10]!
+    STP 	X16, X17, [SP, #-0x10]!
+    STP 	X18, X19, [SP, #-0x10]!
+    STP 	X20, X21, [SP, #-0x10]!
+    STP 	X22, X23, [SP, #-0x10]!
+    STP 	X24, X25, [SP, #-0x10]!
+    STP 	X26, X27, [SP, #-0x10]!
+    STP 	X28, X29, [SP, #-0x10]!
+    STP 	X30, XZR, [SP, #-0x10]!
+
+    MRS		X0, CurrentEL
+    CMP		X0, 0xc
+    B.EQ	3f
+    CMP		X0, 0x8
+    B.EQ	2f
+    CMP		X0, 0x4
+    B.EQ	1f
+    B 		.
+3:
+    MRS		X3, SPSR_EL3
+    /* Save the ELR. */
+    MRS		X2, ELR_EL3
+    B		0f
+2:
+    MRS		X3, SPSR_EL2
+    /* Save the ELR. */
+    MRS		X2, ELR_EL2
+    B		0f
+1:
+    MRS		X3, SPSR_EL1
+    MRS		X2, ELR_EL1
+    B		0f
+0:
+
+    STP 	X2, X3, [SP, #-0x10]!
+
+    MOV 	X0, SP   /* Move SP into X0 for saving. */
+
+    /* Switch to use the ELx stack pointer. */
+    MSR 	SPSEL, #1
+
+    .endm
+
+.macro SAVE_CONTEXT_T
+
+    /* Switch to use the EL0 stack pointer. */
+    MSR 	SPSEL, #0
+
+    /* Save the entire context. */
+    STP 	X0, X1, [SP, #-0x10]!
+    STP 	X2, X3, [SP, #-0x10]!
+    STP 	X4, X5, [SP, #-0x10]!
+    STP 	X6, X7, [SP, #-0x10]!
+    STP 	X8, X9, [SP, #-0x10]!
+    STP 	X10, X11, [SP, #-0x10]!
+    STP 	X12, X13, [SP, #-0x10]!
+    STP 	X14, X15, [SP, #-0x10]!
+    STP 	X16, X17, [SP, #-0x10]!
+    STP 	X18, X19, [SP, #-0x10]!
+    STP 	X20, X21, [SP, #-0x10]!
+    STP 	X22, X23, [SP, #-0x10]!
+    STP 	X24, X25, [SP, #-0x10]!
+    STP 	X26, X27, [SP, #-0x10]!
+    STP 	X28, X29, [SP, #-0x10]!
+    STP 	X30, XZR, [SP, #-0x10]!
+
+    MRS		X0, CurrentEL
+    CMP		X0, 0xc
+    B.EQ	3f
+    CMP		X0, 0x8
+    B.EQ	2f
+    CMP		X0, 0x4
+    B.EQ	1f
+    B 		.
+3:
+    MRS		X3, SPSR_EL3
+    MOV		X2, X30
+    B		0f
+2:
+    MRS		X3, SPSR_EL2
+    MOV		X2, X30
+    B		0f
+1:
+    MRS		X3, SPSR_EL1
+    MOV		X2, X30
+    B		0f
+0:
+
+    STP 	X2, X3, [SP, #-0x10]!
+
+    MOV 	X0, SP   /* Move SP into X0 for saving. */
+
+    /* Switch to use the ELx stack pointer. */
+    MSR 	SPSEL, #1
+
+    .endm
+
+.macro RESTORE_CONTEXT
+
+    /* Switch to use the EL0 stack pointer. */
+    MSR 	SPSEL, #0
+
+    /* Set the SP to point to the stack of the task being restored. */
+    MOV		SP, X0
+
+    LDP 	X2, X3, [SP], #0x10  /* SPSR and ELR. */
+
+    MRS		X0, CurrentEL
+    CMP		X0, 0xc
+    B.EQ	3f
+    CMP		X0, 0x8
+    B.EQ	2f
+    CMP		X0, 0x4
+    B.EQ	1f
+    B 		.
+3:
+    MSR		SPSR_EL3, X3
+    MSR		ELR_EL3, X2
+    B		0f
+2:
+    MSR		SPSR_EL2, X3
+    MSR		ELR_EL2, X2
+    B		0f
+1:
+    MSR		SPSR_EL1, X3
+    MSR		ELR_EL1, X2
+    B		0f
+0:
+
+    LDP 	X30, XZR, [SP], #0x10
+    LDP 	X28, X29, [SP], #0x10
+    LDP 	X26, X27, [SP], #0x10
+    LDP 	X24, X25, [SP], #0x10
+    LDP 	X22, X23, [SP], #0x10
+    LDP 	X20, X21, [SP], #0x10
+    LDP 	X18, X19, [SP], #0x10
+    LDP 	X16, X17, [SP], #0x10
+    LDP 	X14, X15, [SP], #0x10
+    LDP 	X12, X13, [SP], #0x10
+    LDP 	X10, X11, [SP], #0x10
+    LDP 	X8, X9, [SP], #0x10
+    LDP 	X6, X7, [SP], #0x10
+    LDP 	X4, X5, [SP], #0x10
+    LDP 	X2, X3, [SP], #0x10
+    LDP 	X0, X1, [SP], #0x10
+
+    /* Switch to use the ELx stack pointer.  _RB_ Might not be required. */
+    MSR 	SPSEL, #1
+
+    ERET
+
+    .endm
+
+.text
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    MRS      X0, DAIF
+    MSR      DAIFSet, #3
+    DSB      SY
+    RET
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    DSB     SY
+    MOV     X1, #0xC0
+    ANDS    X0, X0, X1
+    B.NE    rt_hw_interrupt_enable_exit
+    MSR     DAIFClr, #3
+rt_hw_interrupt_enable_exit:
+    RET
+
+/*
+ * void rt_hw_context_switch_to(rt_ubase_t to);
+ * r0 --> to
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    LDR		X0, [X0]
+    RESTORE_CONTEXT
+
+.text
+/*
+ * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
+ * r0 --> from
+ * r1 --> to
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+
+    MOV		X8,X0
+    MOV		X9,X1
+
+    SAVE_CONTEXT_T
+    
+    STR		X0, [X8]            // store sp in preempted tasks TCB
+    LDR		X0, [X9]            // get new task stack pointer
+    
+    RESTORE_CONTEXT
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
+ */
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+    ADR 	X2, rt_thread_switch_interrupt_flag
+    LDR 	X3, [X2]
+    CMP 	X3, #1
+    B.EQ 	_reswitch
+    ADR 	X4, rt_interrupt_from_thread   // set rt_interrupt_from_thread
+    MOV 	X3, #1              // set rt_thread_switch_interrupt_flag to 1
+    STR 	X0, [X4]
+    STR 	X3, [X2]
+_reswitch:
+    ADR 	X2, rt_interrupt_to_thread     // set rt_interrupt_to_thread
+    STR 	X1, [X2]
+    RET
+
+.text
+
+// -- Exception handlers ----------------------------------
+
+    .align  8
+.globl vector_fiq
+vector_fiq:
+    SAVE_CONTEXT
+    STP 	X0, X1, [SP, #-0x10]!
+    BL      rt_hw_trap_fiq
+    LDP 	X0, X1, [SP], #0x10
+    RESTORE_CONTEXT
+
+.globl      rt_interrupt_enter
+.globl      rt_interrupt_leave
+.globl      rt_thread_switch_interrupt_flag
+.globl      rt_interrupt_from_thread
+.globl      rt_interrupt_to_thread
+
+
+// -------------------------------------------------------------------
+
+    .align  8
+.globl vector_irq
+vector_irq:
+    SAVE_CONTEXT
+    STP 	X0, X1, [SP, #-0x10]!
+
+    BL      rt_interrupt_enter
+    BL      rt_hw_trap_irq
+    BL      rt_interrupt_leave
+    
+    LDP 	X0, X1, [SP], #0x10
+
+    // if rt_thread_switch_interrupt_flag set, jump to
+    // rt_hw_context_switch_interrupt_do and don't return
+    ADR 	X1, rt_thread_switch_interrupt_flag
+    LDR     X2, [X1]
+    CMP     X2, #1
+    B.NE     vector_irq_exit
+
+    MOV     X2,  #0         // clear flag
+    STR     X2,  [X1]
+
+    ADR     X3,  rt_interrupt_from_thread
+    LDR     X4,  [X3]
+    STR     x0,  [X4]       // store sp in preempted tasks's TCB
+
+    ADR     x3,  rt_interrupt_to_thread
+    LDR     X4,  [X3]
+    LDR     x0,  [X4]       // get new task's stack pointer
+    
+vector_irq_exit:	
+    RESTORE_CONTEXT
+
+// -------------------------------------------------
+
+    .align  8
+    .globl  vector_error
+vector_error:
+    SAVE_CONTEXT
+    BL      rt_hw_trap_error
+    B       .
diff --git a/libcpu/aarch64/common/cp15.h b/libcpu/aarch64/common/cp15.h
new file mode 100644
index 0000000000..f3ffd6f857
--- /dev/null
+++ b/libcpu/aarch64/common/cp15.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ */
+
+#ifndef __CP15_H__
+#define __CP15_H__
+
+#ifndef   __STATIC_FORCEINLINE
+#define __STATIC_FORCEINLINE     __attribute__((always_inline)) static inline
+#endif
+
+#define __WFI()    __asm__ volatile ("wfi":::"memory")
+
+#define __WFE()    __asm__ volatile ("wfe":::"memory")
+
+#define __SEV()    __asm__ volatile ("sev")
+
+__STATIC_FORCEINLINE  void __ISB(void)
+{
+    __asm__ volatile ("isb 0xF":::"memory");
+}
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE  void __DSB(void)
+{
+    __asm__ volatile ("dsb 0xF":::"memory");
+}
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+
+__STATIC_FORCEINLINE  void __DMB(void)
+{
+    __asm__ volatile ("dmb 0xF":::"memory");
+}
+
+#ifdef RT_USING_SMP
+static inline void send_ipi_msg(int cpu, int ipi_vector)
+{
+    IPI_MAILBOX_SET(cpu) = 1 << ipi_vector;
+}
+
+static inline void setup_bootstrap_addr(int cpu, int addr)
+{
+	CORE_MAILBOX3_SET(cpu) = addr;
+}
+
+static inline void enable_cpu_ipi_intr(int cpu)
+{
+    COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK;
+}
+
+static inline void enable_cpu_timer_intr(int cpu)
+{
+	CORETIMER_INTCTL(cpu) = 0x8;
+}
+
+static inline void enable_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 1;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
+}
+
+static inline void disable_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 0;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
+}
+
+static inline  void mask_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 2;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
+}
+
+static inline void unmask_cntv(void)
+{
+    rt_uint32_t cntv_ctl;
+    cntv_ctl = 1;
+    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
+}
+
+static inline rt_uint64_t read_cntvct(void)
+{
+    rt_uint32_t val,val1;
+    asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1));
+    return (val);
+}
+
+static inline rt_uint64_t read_cntvoff(void)
+{
+
+    rt_uint64_t val;
+    asm volatile("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val));
+    return (val);
+}
+
+static inline rt_uint32_t read_cntv_tval(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val) );
+    return val;
+}
+
+
+static inline  void write_cntv_tval(rt_uint32_t val)
+{
+    asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val) );
+    return;
+}
+
+static inline rt_uint32_t read_cntfrq(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val) );
+    return val;
+}
+
+
+static inline  rt_uint32_t read_cntctrl(void)
+{
+    rt_uint32_t val;
+    asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val) );
+    return val;
+}
+
+static inline uint32_t write_cntctrl(uint32_t val)
+{
+
+    asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val) );
+    return val;
+}
+#endif
+
+unsigned long rt_cpu_get_smp_id(void);
+
+void rt_cpu_mmu_disable(void);
+void rt_cpu_mmu_enable(void);
+void rt_cpu_tlb_set(volatile unsigned long*);
+
+void rt_cpu_dcache_clean_flush(void);
+void rt_cpu_icache_flush(void);
+
+void rt_cpu_vector_set_base(rt_ubase_t addr);
+void rt_hw_mmu_init(void);
+void rt_hw_vector_init(void);
+
+void set_timer_counter(unsigned int counter);
+void set_timer_control(unsigned int control);
+#endif
diff --git a/libcpu/aarch64/common/cpu.c b/libcpu/aarch64/common/cpu.c
new file mode 100644
index 0000000000..962a53a071
--- /dev/null
+++ b/libcpu/aarch64/common/cpu.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-15     Bernard      first version
+ * 2019-07-28     zdzn         add smp support
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <board.h>
+#include "cp15.h"
+
+int rt_hw_cpu_id(void)
+{
+    int cpu_id;
+    rt_base_t value;
+
+    __asm__ volatile (
+            "mrs %0, mpidr_el1"
+            :"=r"(value)
+            );
+    cpu_id = value & 0xf;
+    return cpu_id;
+};
+
+#ifdef RT_USING_SMP
+void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
+{
+    lock->slock = 0;
+}
+
+void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
+{
+    unsigned long tmp;
+    unsigned long newval;
+    rt_hw_spinlock_t lockval;
+    __asm__ __volatile__(
+            "pld [%0]"
+            ::"r"(&lock->slock)
+            );
+
+    __asm__ __volatile__(
+            "1: ldrex   %0, [%3]\n"
+            "   add %1, %0, %4\n"
+            "   strex   %2, %1, [%3]\n"
+            "   teq %2, #0\n"
+            "   bne 1b"
+            : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
+            : "r" (&lock->slock), "I" (1 << 16)
+            : "cc");
+
+    while (lockval.tickets.next != lockval.tickets.owner) {
+        __WFE();
+        lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
+    }
+
+    __DMB();
+}
+
+void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
+{
+    __DMB();
+    lock->tickets.owner++;
+    __DSB();
+    __SEV();
+}
+#endif /*RT_USING_SMP*/
+
+/**
+ * @addtogroup ARM CPU
+ */
+/*@{*/
+
+/** shutdown CPU */
+void rt_hw_cpu_shutdown()
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}
+
+/*@}*/
diff --git a/libcpu/aarch64/common/cpu_gcc.S b/libcpu/aarch64/common/cpu_gcc.S
new file mode 100644
index 0000000000..b8c8b8768c
--- /dev/null
+++ b/libcpu/aarch64/common/cpu_gcc.S
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Date           Author       Notes
+ * 2018-10-06     ZhaoXiaowei    the first version
+ */
+ 
+.text
+.globl rt_hw_get_current_el
+rt_hw_get_current_el:
+	MRS		X0, CurrentEL
+	CMP		X0, 0xc
+	B.EQ	3f
+	CMP		X0, 0x8
+	B.EQ	2f
+	CMP		X0, 0x4
+	B.EQ	1f
+	
+	LDR		X0, =0
+	B		0f
+3:
+	LDR		X0, =3
+	B		0f
+2:
+	LDR		X0, =2
+	B		0f
+1:
+	LDR		X0, =1
+	B		0f
+0:
+	RET
+
+
+.globl rt_hw_set_current_vbar
+rt_hw_set_current_vbar:
+	MRS		X1, CurrentEL
+	CMP		X1, 0xc
+	B.EQ	3f
+	CMP		X1, 0x8
+	B.EQ	2f
+	CMP		X1, 0x4
+	B.EQ	1f
+	B		0f
+3:
+	MSR		VBAR_EL3,X0
+	B		0f
+2:
+	MSR		VBAR_EL2,X0
+	B		0f
+1:
+	MSR		VBAR_EL1,X0
+	B		0f
+0:
+	RET
+
+    
+.globl rt_hw_set_elx_env
+rt_hw_set_elx_env:
+	MRS		X1, CurrentEL
+	CMP		X1, 0xc
+	B.EQ	3f
+	CMP		X1, 0x8
+	B.EQ	2f
+	CMP		X1, 0x4
+	B.EQ	1f
+	B		0f
+3:
+	MRS		X0, SCR_EL3
+	ORR		X0, X0, #0xF			/* SCR_EL3.NS|IRQ|FIQ|EA */
+	MSR		SCR_EL3, X0
+	B		0f
+2:
+	MRS	X0, HCR_EL2
+	ORR	X0, X0, #0x38
+	MSR	HCR_EL2, X0
+	B		0f
+1:
+	B		0f
+0:
+	RET
diff --git a/libcpu/aarch64/common/gic/SConscript b/libcpu/aarch64/common/gic/SConscript
new file mode 100644
index 0000000000..b114ba7678
--- /dev/null
+++ b/libcpu/aarch64/common/gic/SConscript
@@ -0,0 +1,24 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+CPPPATH = [cwd]
+
+gic400_group = Split('''
+gic_pl400.c
+''')
+
+gic500_group = Split('''
+gic_pl500.c
+''')
+
+src = ()
+if GetDepend('BSP_USING_GIC400'):
+	src = gic400_group
+if GetDepend('BSP_USING_GIC500'):
+	src = gic500_group
+
+group = DefineGroup('gic', src, depend = ['BSP_USING_GIC'], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/aarch64/common/gic/gic_pl400.c b/libcpu/aarch64/common/gic/gic_pl400.c
new file mode 100644
index 0000000000..eb35c5b2a4
--- /dev/null
+++ b/libcpu/aarch64/common/gic/gic_pl400.c
@@ -0,0 +1,368 @@
+/*
+ * Copyright 2014, General Dynamics C4 Systems
+ *
+ * This software may be distributed and modified according to the terms of
+ * the GNU General Public License version 2. Note that NO WARRANTY is provided.
+ * See "LICENSE_GPLv2.txt" for details.
+ *
+ * @TAG(GD_GPL)
+ */
+
+#include "gic_pl400.h"
+#include "iomap.h"
+
+#define BIT(n) (1ul<<(n))
+#define MASK(n) (BIT(n)-1ul)
+
+/* Setters/getters helpers */
+#define IRQ_REG(IRQ) ((IRQ) / 32)
+#define IRQ_BIT(IRQ) BIT((IRQ) % 32)
+#define IRQ_MASK MASK(10)
+#define IS_IRQ_VALID(X) (((X)&IRQ_MASK) < SPECIAL_IRQ_START)
+
+#define CPU(X) (1<<(X))
+#define TARGET_CPU_ALLINT(CPU) ( \
+        ( ((CPU)&0xff)<<0  ) |\
+        ( ((CPU)&0xff)<<8  ) |\
+        ( ((CPU)&0xff)<<16 ) |\
+        ( ((CPU)&0xff)<<24 ) \
+    )
+#define TARGET_CPU0_ALLINT   TARGET_CPU_ALLINT(CPU(0))
+
+
+#define IRQ_SET_ALL 0xffffffff;
+
+/* Special IRQ's */
+#define SPECIAL_IRQ_START 1020
+#define IRQ_NONE          1023
+
+/* Memory map for GIC distributor */
+struct gic_dist_map {
+    uint32_t enable;                /* 0x000 */
+    uint32_t ic_type;               /* 0x004 */
+    uint32_t dist_ident;            /* 0x008 */
+    uint32_t res1[29];              /* [0x00C, 0x080) */
+
+    uint32_t group[32];          /* [0x080, 0x100) */
+
+    uint32_t enable_set[32];        /* [0x100, 0x180) */
+    uint32_t enable_clr[32];        /* [0x180, 0x200) */
+    uint32_t pending_set[32];       /* [0x200, 0x280) */
+    uint32_t pending_clr[32];       /* [0x280, 0x300) */
+    uint32_t active[32];            /* [0x300, 0x380) */
+    uint32_t active_clr[32];        /* [0x380, 0x400) */
+
+    uint32_t priority[255];         /* [0x400, 0x7FC) */
+    uint32_t res2;                  /* 0x7FC */
+
+    uint32_t targets[255];          /* [0x800, 0xBFC) */
+    uint32_t res3;                  /* 0xBFC */
+
+    uint32_t config[64];             /* [0xC00, 0xD00) */
+
+    uint32_t ppi_status;            /* [0xD00, 0xD04) */
+    uint32_t spi_status[15];        /* [0xD04, 0xD40) */
+    uint32_t res4[112];              /* [0xD40, 0xF00) */
+
+    uint32_t sgi_control;           /* 0xF00 */
+    uint32_t res5[3];               /* [0xF04, 0xF10) */
+    uint32_t sgi_pending_clr[4];    /* [0xF10, 0xF20) */
+    uint32_t sgi_pending_set[4];    /* [0xF20, 0xF30) */
+    uint32_t res10[40];             /* [0xF30, 0xFD0) */
+
+    uint32_t periph_id[8];         /* [0xFD0, 0xFF0) */
+    uint32_t component_id[4];       /* [0xFF0, 0xFFF] */
+};
+
+
+/* Memory map for GIC  cpu interface */
+struct gic_cpu_iface_map {
+    uint32_t icontrol;              /*  0x000         */
+    uint32_t pri_msk_c;             /*  0x004         */
+    uint32_t bp_c;                  /*  0x008         */
+    uint32_t int_ack;               /*  0x00C         */
+    uint32_t eoi;                   /*  0x010         */
+    uint32_t run_priority;          /*  0x014         */
+    uint32_t hi_pend;               /*  0x018         */
+    uint32_t ns_alias_bp_c;         /*  0x01C         */
+    uint32_t ns_alias_ack;          /*  0x020 GIC_PL400 only */
+    uint32_t ns_alias_eoi;          /*  0x024 GIC_PL400 only */
+    uint32_t ns_alias_hi_pend;      /*  0x028 GIC_PL400 only */
+
+    uint32_t res1[41];              /* [0x02C, 0x0D0) */
+    uint32_t active_priority[4];    /* [0x0D0, 0xC0] GIC_PL400 only */
+    uint32_t ns_active_priority[4]; /* [0xE0,0xF0] GIC_PL400 only */
+    uint32_t res4[3];               /* [0xF0, 0xFC] */
+
+    uint32_t cpu_if_ident;          /*  0x0FC         */
+    uint32_t deactive;              /* [0x1000] */
+};
+
+volatile struct gic_dist_map *gic_dist =
+    (volatile struct gic_dist_map*)(GIC_PL400_DISTRIBUTOR_PPTR);
+
+volatile struct gic_cpu_iface_map *gic_cpuiface =
+    (volatile struct gic_cpu_iface_map*)(GIC_PL400_CONTROLLER_PPTR);
+
+/* Helpers */
+static inline int
+is_irq_pending(irq_t irq)
+{
+    int word = irq / 32;
+    int bit = irq & 0x1f;
+    return !!(gic_dist->pending_set[word] & BIT(bit));
+}
+
+static inline int
+is_irq_active(irq_t irq)
+{
+    int word = irq / 32;
+    int bit = irq & 0x1f;
+    return !!(gic_dist->active[word] & BIT(bit));
+}
+
+static inline int
+is_irq_enabled(irq_t irq)
+{
+    int word = irq / 32;
+    int bit = irq & 0x1f;
+    return !!(gic_dist->enable_set[word] & BIT(bit));
+}
+
+static inline int
+is_irq_edge_triggered(irq_t irq)
+{
+    int word = irq / 16;
+    int bit = ((irq & 0xf) * 2);
+    return !!(gic_dist->config[word] & BIT(bit + 1));
+}
+
+static inline int
+is_irq_1_N(irq_t irq)
+{
+    int word = irq / 16;
+    int bit = ((irq & 0xf) * 2);
+    return !!(gic_dist->config[word] & BIT(bit + 0));
+}
+
+static inline int
+is_irq_N_N(irq_t irq)
+{
+    return !(is_irq_1_N(irq));
+}
+
+static inline void
+dist_pending_clr(irq_t irq)
+{
+    int word = irq / 32;
+    int bit = irq & 0x1f;
+    /* Using |= here is detrimental to your health */
+    gic_dist->pending_clr[word] = BIT(bit);
+}
+
+static inline void
+dist_pending_set(irq_t irq)
+{
+    int word = irq / 32;
+    int bit = irq & 0x1f;
+    gic_dist->pending_set[word] = BIT(bit);
+}
+
+static inline void
+dist_enable_clr(irq_t irq)
+{
+    int word = irq / 32;
+    int bit = irq & 0x1f;
+    /* Using |= here is detrimental to your health */
+    gic_dist->enable_clr[word] = BIT(bit);
+}
+
+static inline void
+dist_enable_set(irq_t irq)
+{
+    int word = irq / 32;
+    int bit = irq & 0x1f;
+    gic_dist->enable_set[word] = BIT(bit);
+}
+
+/**
+   DONT_TRANSLATE
+ */
+static void dist_init(void)
+{
+    int i;
+    int nirqs = 32 * ((gic_dist->ic_type & 0x1f) + 1);
+    gic_dist->enable = 0;
+
+#if 0
+    /* configure to group 0 for security */
+    for (i = 0; i < nirqs; i += 32) {
+        gic_dist->group[i / 32] = 0xffffffff;
+    }
+#endif
+
+    for (i = 0; i < nirqs; i += 32) {
+        /* disable */
+        gic_dist->enable_clr[i / 32] = IRQ_SET_ALL;
+        /* clear pending */
+        gic_dist->pending_clr[i / 32] = IRQ_SET_ALL;
+    }
+
+    /* reset interrupts priority */
+    for (i = 32; i < nirqs; i += 4) {
+        gic_dist->priority[i / 4] = 0x0;
+    }
+
+    /*
+     * reset int target to cpu 0
+     * (Should really query which processor we're running on and use that)
+     */
+    for (i = 0; i < nirqs; i += 4) {
+        gic_dist->targets[i / 4] = TARGET_CPU0_ALLINT;
+    }
+
+    /* level-triggered, 1-N */
+    for (i = 64; i < nirqs; i += 32) {
+        gic_dist->config[i / 32] = 0;
+        //gic_dist->config[i / 32] = 0x55555555;
+    }
+    /* enable the int controller */
+    gic_dist->enable = 1;
+}
+
+/**
+   DONT_TRANSLATE
+ */
+static void cpu_iface_init(void)
+{
+    uint32_t i;
+
+    /* For non-Exynos4, the registers are banked per CPU, need to clear them */
+    gic_dist->enable_clr[0] = IRQ_SET_ALL;
+    gic_dist->pending_clr[0] = IRQ_SET_ALL;
+    gic_dist->priority[0] = 0x00;
+    /* put everything in group 0 */
+
+    /* clear any software generated interrupts */
+    for (i = 0; i < 16; i += 4) {
+        gic_dist->sgi_pending_clr[i / 4] = IRQ_SET_ALL;
+    }
+
+    gic_cpuiface->icontrol = 0;
+    gic_cpuiface->pri_msk_c = 0x000000f0;
+    gic_cpuiface->bp_c = 0x00000003;
+
+    while (((i = gic_cpuiface->int_ack) & IRQ_MASK) != IRQ_NONE) {
+        gic_cpuiface->eoi = i;
+    }
+    gic_cpuiface->icontrol = 0x1;
+}
+
+/**
+   DONT_TRANSLATE
+ */
+void initIRQController(void)
+{
+    dist_init();
+    cpu_iface_init();
+}
+
+
+
+/*
+ * The only sane way to get an GIC IRQ number that can be properly
+ * ACKED later is through the int_ack register. Unfortunately, reading
+ * this register changes the interrupt state to pending so future
+ * reads will not return the same value For this reason, we have a
+ * global variable to store the IRQ number.
+ */
+static uint32_t active_irq = IRQ_NONE;
+
+/**
+   DONT_TRANSLATE
+ */
+interrupt_t
+getActiveIRQ(void)
+{
+    uint32_t irq;
+    if (!IS_IRQ_VALID(active_irq)) {
+        active_irq = gic_cpuiface->int_ack;
+    }
+
+    if (IS_IRQ_VALID(active_irq)) {
+        irq = active_irq & IRQ_MASK;
+    } else {
+        irq = 1023;
+    }
+
+    return irq;
+}
+
+/*
+ * GIC has 4 states: pending->active(+pending)->inactive
+ * seL4 expects two states: active->inactive.
+ * We ignore the active state in GIC to conform
+ */
+/**
+   DONT_TRANSLATE
+ */
+bool_t
+isIRQPending(void)
+{
+    return IS_IRQ_VALID(gic_cpuiface->hi_pend);
+}
+
+
+/**
+   DONT_TRANSLATE
+ */
+void
+maskInterrupt(bool_t disable, interrupt_t irq)
+{
+    if (disable) {
+        dist_enable_clr(irq);
+    } else {
+        dist_enable_set(irq);
+    }
+}
+
+/**
+   DONT_TRANSLATE
+ */
+void
+ackInterrupt(irq_t irq)
+{
+    if (!(IS_IRQ_VALID(active_irq) && (active_irq & IRQ_MASK) == irq)) {
+		return;
+	}
+    if (is_irq_edge_triggered(irq)) {
+        dist_pending_clr(irq);
+    }
+    gic_cpuiface->eoi = active_irq;
+    active_irq = IRQ_NONE;
+}
+
+void
+handleSpuriousIRQ(void)
+{
+}
+
+void rt_hw_interrupt_mask(int vector)
+{
+    maskInterrupt(1, vector);
+}
+
+void rt_hw_interrupt_umask(int vector)
+{
+    maskInterrupt(0, vector);
+}
+
+int rt_hw_interrupt_get_irq(void)
+{
+    return getActiveIRQ();
+}
+
+void rt_hw_interrupt_ack(int fiq_irq)
+{
+    return ackInterrupt(fiq_irq);
+}
diff --git a/libcpu/aarch64/common/gic/gic_pl400.h b/libcpu/aarch64/common/gic/gic_pl400.h
new file mode 100644
index 0000000000..a43583bd7c
--- /dev/null
+++ b/libcpu/aarch64/common/gic/gic_pl400.h
@@ -0,0 +1,35 @@
+
+#ifndef __ARCH_MACHINE_GIC_PL400_H
+#define __ARCH_MACHINE_GIC_PL400_H
+
+#include <stdint.h>
+
+typedef uint16_t interrupt_t;
+typedef uint16_t irq_t;
+typedef uint64_t  bool_t;
+
+/** MODIFIES: [*] */
+interrupt_t getActiveIRQ(void);
+/** MODIFIES: [*] */
+interrupt_t getPendingIRQ(void);
+/** MODIFIES: [*] */
+bool_t isIRQPending(void);
+/** MODIFIES: [*] */
+void maskInterrupt(bool_t disable, interrupt_t irq);
+/** MODIFIES: [*] */
+void ackInterrupt(irq_t irq);
+/** MODIFIES: [*] */
+static inline void setInterruptMode(irq_t irq, bool_t levelTrigger, bool_t polarityLow) { }
+
+/** MODIFIES: [*] */
+void initIRQController(void);
+
+void handleSpuriousIRQ(void);
+
+void rt_hw_interrupt_umask(int vector);
+
+int rt_hw_interrupt_get_irq(void);
+
+void rt_hw_interrupt_ack(int fiq_irq);
+#endif /* !__ARCH_MACHINE_GIC400_H */
+
diff --git a/libcpu/aarch64/common/mmu.c b/libcpu/aarch64/common/mmu.c
new file mode 100644
index 0000000000..b799143084
--- /dev/null
+++ b/libcpu/aarch64/common/mmu.c
@@ -0,0 +1,367 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author             Notes
+ * 2020-02-20     bigmagic           first version
+ */
+#include <mmu.h>
+#include <stddef.h>
+#include <rthw.h>
+
+#define TTBR_CNP    1
+
+typedef unsigned long int    uint64_t;
+
+static unsigned long main_tbl[512 * 20] __attribute__((aligned (4096)));
+
+#define IS_ALIGNED(x, a)        (((x) & ((typeof(x))(a) - 1)) == 0)
+
+#define PMD_TYPE_SECT        (1 << 0)
+
+#define PMD_TYPE_TABLE        (3 << 0)
+
+#define PTE_TYPE_PAGE        (3 << 0)
+
+#define BITS_PER_VA          39
+
+/* Granule size of 4KB is being used */
+#define GRANULE_SIZE_SHIFT         12
+#define GRANULE_SIZE               (1 << GRANULE_SIZE_SHIFT)
+#define XLAT_ADDR_MASK             ((1UL << BITS_PER_VA) - GRANULE_SIZE)
+
+#define PMD_TYPE_MASK               (3 << 0)
+
+int free_idx = 1;
+
+void __asm_invalidate_icache_all(void);
+void __asm_flush_dcache_all(void);
+int __asm_flush_l3_cache(void);
+void __asm_flush_dcache_range(unsigned long long start, unsigned long long end);
+void __asm_invalidate_dcache_all(void);
+void __asm_invalidate_icache_all(void);
+
+void mmu_memset(char *dst, char v,  size_t len)
+{
+    while (len--)
+    {
+        *dst++ = v;
+    }
+}
+
+static unsigned long __page_off = 0;
+static unsigned long get_free_page(void) 
+{
+    __page_off += 512;
+    return (unsigned long)(main_tbl + __page_off);
+}
+
+
+static inline unsigned int get_sctlr(void)
+{
+    unsigned int val;
+    asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
+    return val;
+}
+
+static inline void set_sctlr(unsigned int val)
+{
+    asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
+    asm volatile("isb");
+}
+
+void mmu_init(void)
+{
+    unsigned long val64;
+    unsigned long val32;
+
+    val64 = 0x007f6eUL;
+    __asm__ volatile("msr MAIR_EL1, %0\n dsb sy\n"::"r"(val64));
+    __asm__ volatile("mrs %0, MAIR_EL1\n dsb sy\n":"=r"(val64));
+
+    //TCR_EL1
+    val32 = (16UL << 0)//48bit
+        | (0x0UL << 6)
+        | (0x0UL << 7)
+        | (0x3UL << 8)
+        | (0x3UL << 10)//Inner Shareable
+        | (0x2UL << 12)
+        | (0x0UL << 14)//4K
+        | (0x0UL << 16)
+        | (0x0UL << 22)
+        | (0x1UL << 23)
+        | (0x2UL << 30)
+        | (0x1UL << 32)
+        | (0x0UL << 35)
+        | (0x0UL << 36)
+        | (0x0UL << 37)
+        | (0x0UL << 38);
+    __asm__ volatile("msr TCR_EL1, %0\n"::"r"(val32));
+    __asm__ volatile("mrs %0, TCR_EL1\n":"=r"(val32));
+
+    __asm__ volatile("msr TTBR0_EL1, %0\n dsb sy\n"::"r"(main_tbl));
+    __asm__ volatile("mrs %0, TTBR0_EL1\n dsb sy\n":"=r"(val64));
+
+    mmu_memset((char *)main_tbl, 0, 4096);
+}
+
+void mmu_enable(void)
+{
+    unsigned long val64;
+    unsigned long val32;
+
+    __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val64));
+    val64 &= ~0x1000; //disable I
+    __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\n isb sy\n"::"r"(val64));
+
+    __asm__ volatile("IC IALLUIS\n dsb sy\n isb sy\n");
+    __asm__ volatile("tlbi vmalle1\n dsb sy\n isb sy\n");
+
+    //SCTLR_EL1, turn on mmu
+    __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val32));
+    val32 |= 0x1005; //enable mmu, I C M
+    __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32));
+    rt_hw_icache_enable();
+    rt_hw_dcache_enable();
+
+}
+
+static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) 
+{
+    int level;
+    unsigned long* cur_lv_tbl = lv0_tbl;
+    unsigned long page;
+    unsigned long off;
+    int level_shift = 39;
+
+    if (va & (0x200000UL - 1)) 
+    {
+        return MMU_MAP_ERROR_VANOTALIGN;
+    }
+    if (pa & (0x200000UL - 1)) 
+    {
+        return MMU_MAP_ERROR_PANOTALIGN;
+    }
+    for (level = 0; level < 2; level++) 
+    {
+        off = (va >> level_shift);
+        off &= MMU_LEVEL_MASK;
+        if ((cur_lv_tbl[off] & 1) == 0) 
+        {
+            page = get_free_page();
+            if (!page) 
+            {
+                return MMU_MAP_ERROR_NOPAGE;
+            }
+            mmu_memset((char *)page, 0, 4096);
+            cur_lv_tbl[off] = page | 0x3UL;
+        }
+        page = cur_lv_tbl[off];
+        if (!(page & 0x2)) 
+        {
+            //is block! error!
+            return MMU_MAP_ERROR_CONFLICT;
+        }
+        cur_lv_tbl = (unsigned long*)(page & 0x0000fffffffff000UL);
+        level_shift -= 9;
+    }
+    attr &= 0xfff0000000000ffcUL;
+    pa |= (attr | 0x1UL); //block
+    off = (va >> 21);
+    off &= MMU_LEVEL_MASK;
+    cur_lv_tbl[off] = pa;
+    return 0;
+}
+
+int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr)
+{
+    int i;
+    int ret;
+
+    if (va & (0x200000 - 1))
+    {
+        return -1;
+    }
+    if (pa & (0x200000 - 1))
+    {
+        return -1;
+    }
+    for (i = 0; i < count; i++)
+    {
+        ret = map_single_page_2M((unsigned long *)main_tbl, va, pa, attr);
+        va += 0x200000;
+        pa += 0x200000;
+        if (ret != 0)
+        {
+            return ret;
+        }
+    }
+    return 0;
+}
+
+static void set_table(uint64_t *pt, uint64_t *table_addr)
+{
+    uint64_t val;
+    val = (0x3UL | (uint64_t)table_addr);
+    *pt = val;
+}
+
+void mmu_memset2(unsigned char *dst, char v,  int len)
+{
+    while (len--)
+    {
+        *dst++ = v;
+    }
+}
+
+static uint64_t *create_table(void)
+{
+    uint64_t *new_table = (uint64_t *)((unsigned char *)&main_tbl[0] + free_idx * 4096); //+ free_idx * GRANULE_SIZE;
+    /* Mark all entries as invalid */
+    mmu_memset2((unsigned char *)new_table, 0, 4096);
+    free_idx++;
+    return new_table;
+}
+
+static int pte_type(uint64_t *pte)
+{
+    return *pte & PMD_TYPE_MASK;
+}
+
+static int level2shift(int level)
+{
+    /* Page is 12 bits wide, every level translates 9 bits */
+    return (12 + 9 * (3 - level));
+}
+
+static uint64_t *get_level_table(uint64_t *pte)
+{
+    uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK);
+    
+    if (pte_type(pte) != PMD_TYPE_TABLE) 
+    {
+        table = create_table();
+        set_table(pte, table);
+    }
+    return table;
+}
+
+static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t attr)
+{
+    uint64_t block_size = 0;
+    uint64_t block_shift = 0;
+    uint64_t *pte;
+    uint64_t idx = 0;
+    uint64_t addr = 0;
+    uint64_t *table = 0;
+    int level = 0;
+
+    addr = virt;
+    while (size) 
+    {
+        table = &main_tbl[0];
+        for (level = 0; level < 4; level++) 
+        {
+            block_shift = level2shift(level);
+            idx = addr >> block_shift;
+            idx = idx%512;
+            block_size = (uint64_t)(1L << block_shift);
+            pte = table + idx;
+
+            if (size >= block_size && IS_ALIGNED(addr, block_size)) 
+            {
+                attr &= 0xfff0000000000ffcUL;
+                if(level != 3)
+                {
+                    *pte = phys | (attr | 0x1UL);
+                }
+                else
+                {
+                    *pte = phys | (attr | 0x3UL);
+                }
+                addr += block_size;
+                phys += block_size;
+                size -= block_size;
+                break;
+            }
+            table = get_level_table(pte);
+        }
+    }
+}
+
+void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr)
+{
+    map_region(va, pa, size, attr);
+}
+
+void rt_hw_dcache_enable(void)
+{
+    if (!(get_sctlr() & CR_M)) 
+    {
+        rt_kprintf("please init mmu!\n");
+    }
+    else
+    {
+        set_sctlr(get_sctlr() | CR_C);
+    }
+}
+
+void rt_hw_dcache_flush_all(void)
+{
+    int ret;
+
+    __asm_flush_dcache_all();
+    ret = __asm_flush_l3_cache();
+    if (ret)
+    {
+        rt_kprintf("flushing dcache returns 0x%x\n", ret);
+    }
+    else
+    {
+        rt_kprintf("flushing dcache successfully.\n");
+    }
+}
+
+void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size)
+{
+    __asm_flush_dcache_range(start_addr, start_addr + size);
+}
+void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size)
+{
+    __asm_flush_dcache_range(start_addr, start_addr + size);
+}
+
+void rt_hw_dcache_invalidate_all(void)
+{
+    __asm_invalidate_dcache_all();
+}
+
+void rt_hw_dcache_disable(void)
+{
+    /* if cache isn't enabled no need to disable */
+    if(!(get_sctlr() & CR_C))
+    {
+        rt_kprintf("need enable cache!\n");
+        return;
+    }
+    set_sctlr(get_sctlr() & ~CR_C);
+}
+
+//icache
+void rt_hw_icache_enable(void)
+{
+    __asm_invalidate_icache_all();
+    set_sctlr(get_sctlr() | CR_I);
+}
+
+void rt_hw_icache_invalidate_all(void)
+{
+    __asm_invalidate_icache_all();
+}
+
+void rt_hw_icache_disable(void)
+{
+    set_sctlr(get_sctlr() & ~CR_I);
+}
\ No newline at end of file
diff --git a/libcpu/aarch64/common/mmu.h b/libcpu/aarch64/common/mmu.h
new file mode 100644
index 0000000000..6a66472c79
--- /dev/null
+++ b/libcpu/aarch64/common/mmu.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author             Notes
+ * 2020-02-20     bigmagic           first version
+ */
+
+#ifndef  __MMU_H__
+#define  __MMU_H__
+
+/*
+ * CR1 bits (CP#15 CR1)
+ */
+#define CR_M    (1 << 0)    /* MMU enable                */
+#define CR_A    (1 << 1)    /* Alignment abort enable        */
+#define CR_C    (1 << 2)    /* Dcache enable            */
+#define CR_W    (1 << 3)    /* Write buffer enable            */
+#define CR_P    (1 << 4)    /* 32-bit exception handler        */
+#define CR_D    (1 << 5)    /* 32-bit data address range        */
+#define CR_L    (1 << 6)    /* Implementation defined        */
+#define CR_B    (1 << 7)    /* Big endian                */
+#define CR_S    (1 << 8)    /* System MMU protection        */
+#define CR_R    (1 << 9)    /* ROM MMU protection            */
+#define CR_F    (1 << 10)    /* Implementation defined        */
+#define CR_Z    (1 << 11)    /* Implementation defined        */
+#define CR_I    (1 << 12)    /* Icache enable            */
+#define CR_V    (1 << 13)    /* Vectors relocated to 0xffff0000    */
+#define CR_RR   (1 << 14)    /* Round Robin cache replacement    */
+#define CR_L4   (1 << 15)    /* LDR pc can set T bit            */
+#define CR_DT   (1 << 16)
+#define CR_IT   (1 << 18)
+#define CR_ST   (1 << 19)
+#define CR_FI   (1 << 21)    /* Fast interrupt (lower latency mode)    */
+#define CR_U    (1 << 22)    /* Unaligned access operation        */
+#define CR_XP   (1 << 23)    /* Extended page tables            */
+#define CR_VE   (1 << 24)    /* Vectored interrupts            */
+#define CR_EE   (1 << 25)    /* Exception (Big) Endian        */
+#define CR_TRE  (1 << 28)    /* TEX remap enable            */
+#define CR_AFE  (1 << 29)    /* Access flag enable            */
+#define CR_TE   (1 << 30)    /* Thumb exception enable        */
+
+#define MMU_LEVEL_MASK 0x1ffUL
+#define MMU_MAP_ERROR_VANOTALIGN  -1
+#define MMU_MAP_ERROR_PANOTALIGN  -2
+#define MMU_MAP_ERROR_NOPAGE      -3
+#define MMU_MAP_ERROR_CONFLICT    -4
+
+#define MEM_ATTR_MEMORY ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2))
+#define MEM_ATTR_IO     ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2))
+
+#define BUS_ADDRESS(phys)    (((phys) & ~0xC0000000)  |  0xC0000000)
+
+void mmu_init(void);
+
+void mmu_enable(void);
+
+int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr);
+
+void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr);
+
+//dcache
+void rt_hw_dcache_enable(void);
+void rt_hw_dcache_flush_all(void);
+void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size);
+void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size);
+void rt_hw_dcache_invalidate_all(void);
+void rt_hw_dcache_disable(void);
+
+//icache
+void rt_hw_icache_enable(void);
+void rt_hw_icache_invalidate_all(void);
+void rt_hw_icache_disable(void);
+
+
+#endif  /*__MMU_H__*/
diff --git a/libcpu/aarch64/common/startup_gcc.S b/libcpu/aarch64/common/startup_gcc.S
new file mode 100644
index 0000000000..ea4268148c
--- /dev/null
+++ b/libcpu/aarch64/common/startup_gcc.S
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+
+    .global	Reset_Handler
+    .section ".start", "ax"
+Reset_Handler:
+    nop
diff --git a/libcpu/aarch64/common/vector_gcc.S b/libcpu/aarch64/common/vector_gcc.S
new file mode 100644
index 0000000000..fc88cce7f8
--- /dev/null
+++ b/libcpu/aarch64/common/vector_gcc.S
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Date           Author       Notes
+ * 2018-10-06     ZhaoXiaowei    the first version
+ */
+ 
+.text
+
+.globl system_vectors
+.globl vector_error
+.globl vector_irq
+.globl vector_fiq
+
+system_vectors:
+.align 11
+    .set    VBAR, system_vectors
+    .org    VBAR
+    // Exception from CurrentEL (EL1) with SP_EL0 (SPSEL=1)
+    .org (VBAR + 0x00 + 0)
+    B vector_error      // 			Synchronous
+    .org (VBAR + 0x80 + 0)
+    B vector_irq        //          IRQ/vIRQ
+    .org (VBAR + 0x100 + 0)
+    B vector_fiq        //          FIQ/vFIQ
+    .org (VBAR + 0x180 + 0)
+    B vector_error      //          Error/vError
+
+    // Exception from CurrentEL (EL1) with SP_ELn
+    .org (VBAR + 0x200 + 0)
+    B vector_error      // 			Synchronous
+    .org (VBAR + 0x280 + 0)
+    B vector_irq    	// 			IRQ/vIRQ
+    .org (VBAR + 0x300 + 0)
+    B vector_fiq        //          FIQ/vFIQ
+    .org (VBAR + 0x380 + 0)
+    B vector_error
+
+    // Exception from lower EL, aarch64
+    .org (VBAR + 0x400 + 0)
+    B vector_error
+    .org (VBAR + 0x480 + 0)
+    B vector_error
+    .org (VBAR + 0x500 + 0)
+    B vector_error
+    .org (VBAR + 0x580 + 0)
+    B vector_error
+
+    // Exception from lower EL, aarch32
+    .org (VBAR + 0x600 + 0)
+    B vector_error
+    .org (VBAR + 0x680 + 0)
+    B vector_error
+    .org (VBAR + 0x700 + 0)
+    B vector_error
+    .org (VBAR + 0x780 + 0)
+    B vector_error
+    .org (VBAR + 0x800 + 0)
+    B vector_error
diff --git a/libcpu/aarch64/cortex-a53/SConscript b/libcpu/aarch64/cortex-a53/SConscript
index 75e170a0cf..c6a4817802 100644
--- a/libcpu/aarch64/cortex-a53/SConscript
+++ b/libcpu/aarch64/cortex-a53/SConscript
@@ -1,16 +1,13 @@
+# RT-Thread building script for component
+
 from building import *
 
+Import('rtconfig')
+
 cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp')
-asm_src = Split('''
-context_gcc.S
-vector_gcc.S
-entry_point.S
-cpu_gcc.S
-cache.S
-''')
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
 CPPPATH = [cwd]
 
-group = DefineGroup('cpu', src + asm_src, depend = [''], CPPPATH = CPPPATH)
+group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')
diff --git a/libcpu/aarch64/cortex-a53/armv8.h b/libcpu/aarch64/cortex-a53/armv8.h
deleted file mode 100644
index 4350890544..0000000000
--- a/libcpu/aarch64/cortex-a53/armv8.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-15     Bernard      first version
- */
-
-#ifndef __ARMV8_H__
-#define __ARMV8_H__
-
-/* the exception stack without VFP registers */
-struct rt_hw_exp_stack
-{
-	unsigned long long pc;
-	unsigned long long spsr;
-	unsigned long long x30;
-	unsigned long long xz;
-	unsigned long long x28;
-	unsigned long long x29;
-	unsigned long long x26;
-	unsigned long long x27;
-	unsigned long long x24;
-	unsigned long long x25;
-	unsigned long long x22;
-	unsigned long long x23;
-	unsigned long long x20;
-	unsigned long long x21;
-	unsigned long long x18;	
-	unsigned long long x19;
-	unsigned long long x16;
-	unsigned long long x17;
-	unsigned long long x14;
-	unsigned long long x15;
-	unsigned long long x12;
-	unsigned long long x13;
-	unsigned long long x10;
-	unsigned long long x11;
-	unsigned long long x8;
-	unsigned long long x9;
-	unsigned long long x6;
-	unsigned long long x7;
-	unsigned long long x4;
-	unsigned long long x5;
-	unsigned long long x2;
-	unsigned long long x3;
-	unsigned long long x0;
-	unsigned long long x1;
-};
-
-#define SP_ELx						( ( unsigned long long ) 0x01 )
-#define SP_EL0						( ( unsigned long long ) 0x00 )
-#define PSTATE_EL1					( ( unsigned long long ) 0x04 )
-#define PSTATE_EL2					( ( unsigned long long ) 0x08 )
-#define PSTATE_EL3					( ( unsigned long long ) 0x0c )
-
-rt_ubase_t rt_hw_get_current_el(void);
-void rt_hw_set_elx_env(void);
-void rt_hw_set_current_vbar(rt_ubase_t addr);
-
-#endif
diff --git a/libcpu/aarch64/cortex-a53/cache.S b/libcpu/aarch64/cortex-a53/cache.S
deleted file mode 100644
index 7f295a2b02..0000000000
--- a/libcpu/aarch64/cortex-a53/cache.S
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author             Notes
- * 2020-03-17     bigmagic           first version
- */
-
-/*
- * void __asm_dcache_level(level)
- *
- * flush or invalidate one level cache.
- *
- * x0: cache level
- * x1: 0 clean & invalidate, 1 invalidate only
- * x2~x9: clobbered
- */
-.globl __asm_dcache_level
-__asm_dcache_level:
-    lsl    x12, x0, #1
-    msr    csselr_el1, x12        /* select cache level */
-    isb                /* sync change of cssidr_el1 */
-    mrs    x6, ccsidr_el1        /* read the new cssidr_el1 */
-    and    x2, x6, #7        /* x2 <- log2(cache line size)-4 */
-    add    x2, x2, #4        /* x2 <- log2(cache line size) */
-    mov    x3, #0x3ff
-    and    x3, x3, x6, lsr #3    /* x3 <- max number of #ways */
-    clz    w5, w3            /* bit position of #ways */
-    mov    x4, #0x7fff
-    and    x4, x4, x6, lsr #13    /* x4 <- max number of #sets */
-    /* x12 <- cache level << 1 */
-    /* x2 <- line length offset */
-    /* x3 <- number of cache ways - 1 */
-    /* x4 <- number of cache sets - 1 */
-    /* x5 <- bit position of #ways */
-
-loop_set:
-    mov    x6, x3            /* x6 <- working copy of #ways */
-loop_way:
-    lsl    x7, x6, x5
-    orr    x9, x12, x7        /* map way and level to cisw value */
-    lsl    x7, x4, x2
-    orr    x9, x9, x7        /* map set number to cisw value */
-    tbz    w1, #0, 1f
-    dc    isw, x9
-    b    2f
-1:    dc    cisw, x9        /* clean & invalidate by set/way */
-2:    subs    x6, x6, #1        /* decrement the way */
-    b.ge    loop_way
-    subs    x4, x4, #1        /* decrement the set */
-    b.ge    loop_set
-
-    ret
-
-/*
- * void __asm_flush_dcache_all(int invalidate_only)
- *
- * x0: 0 clean & invalidate, 1 invalidate only
- *
- * flush or invalidate all data cache by SET/WAY.
- */
-.globl __asm_dcache_all
-__asm_dcache_all:
-    mov    x1, x0
-    dsb    sy
-    mrs    x10, clidr_el1        /* read clidr_el1 */
-    lsr    x11, x10, #24
-    and    x11, x11, #0x7        /* x11 <- loc */
-    cbz    x11, finished        /* if loc is 0, exit */
-    mov    x15, lr
-    mov    x0, #0            /* start flush at cache level 0 */
-    /* x0  <- cache level */
-    /* x10 <- clidr_el1 */
-    /* x11 <- loc */
-    /* x15 <- return address */
-
-loop_level:
-    lsl    x12, x0, #1
-    add    x12, x12, x0        /* x0 <- tripled cache level */
-    lsr    x12, x10, x12
-    and    x12, x12, #7        /* x12 <- cache type */
-    cmp    x12, #2
-    b.lt    skip            /* skip if no cache or icache */
-    bl    __asm_dcache_level    /* x1 = 0 flush, 1 invalidate */
-skip:
-    add    x0, x0, #1        /* increment cache level */
-    cmp    x11, x0
-    b.gt    loop_level
-
-    mov    x0, #0
-    msr    csselr_el1, x0        /* restore csselr_el1 */
-    dsb    sy
-    isb
-    mov    lr, x15
-
-finished:
-    ret
-
-.globl __asm_flush_dcache_all
-__asm_flush_dcache_all:
-    mov    x0, #0
-    b    __asm_dcache_all
-
-.globl __asm_invalidate_dcache_all
-__asm_invalidate_dcache_all:
-    mov    x0, #0x1
-    b    __asm_dcache_all
-
-/*
- * void __asm_flush_dcache_range(start, end)
- *
- * clean & invalidate data cache in the range
- *
- * x0: start address
- * x1: end address
- */
-.globl __asm_flush_dcache_range
-__asm_flush_dcache_range:
-    mrs    x3, ctr_el0
-    lsr    x3, x3, #16
-    and    x3, x3, #0xf
-    mov    x2, #4
-    lsl    x2, x2, x3        /* cache line size */
-
-    /* x2 <- minimal cache line size in cache system */
-    sub    x3, x2, #1
-    bic    x0, x0, x3
-1:    dc    civac, x0    /* clean & invalidate data or unified cache */
-    add    x0, x0, x2
-    cmp    x0, x1
-    b.lo    1b
-    dsb    sy
-    ret
-
-/*
- * void __asm_invalidate_icache_all(void)
- *
- * invalidate all tlb entries.
- */
-.globl __asm_invalidate_icache_all
-__asm_invalidate_icache_all:
-    ic    ialluis
-    isb    sy
-    ret
-
-.globl __asm_flush_l3_cache
-__asm_flush_l3_cache:
-    mov    x0, #0            /* return status as success */
-    ret
\ No newline at end of file
diff --git a/libcpu/aarch64/cortex-a53/context_gcc.S b/libcpu/aarch64/cortex-a53/context_gcc.S
deleted file mode 100644
index 934db7ed84..0000000000
--- a/libcpu/aarch64/cortex-a53/context_gcc.S
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-10-06     ZhaoXiaowei    the first version
- */
-
-  /*
- *enable gtimer
- */
-.globl rt_hw_gtimer_enable
-rt_hw_gtimer_enable:
-	MOV X0,#1
-	MSR CNTP_CTL_EL0,X0
-	RET
-
-/*
- *set gtimer CNTP_TVAL_EL0 value
- */
-.globl rt_hw_set_gtimer_val
-rt_hw_set_gtimer_val:
-	MSR CNTP_TVAL_EL0,X0
-	RET
-
-/*
- *get gtimer CNTP_TVAL_EL0 value
- */
-.globl rt_hw_get_gtimer_val
-rt_hw_get_gtimer_val:
-	MRS X0,CNTP_TVAL_EL0
-	RET
-
-
-.globl rt_hw_get_cntpct_val
-rt_hw_get_cntpct_val:
-	MRS X0, CNTPCT_EL0
-	RET
-
-/*
- *get gtimer frq value
- */
-.globl rt_hw_get_gtimer_frq
-rt_hw_get_gtimer_frq:
-	MRS X0,CNTFRQ_EL0
-	RET
-
-.macro SAVE_CONTEXT
-
-    /* Switch to use the EL0 stack pointer. */
-    MSR 	SPSEL, #0
-
-    /* Save the entire context. */
-    STP 	X0, X1, [SP, #-0x10]!
-    STP 	X2, X3, [SP, #-0x10]!
-    STP 	X4, X5, [SP, #-0x10]!
-    STP 	X6, X7, [SP, #-0x10]!
-    STP 	X8, X9, [SP, #-0x10]!
-    STP 	X10, X11, [SP, #-0x10]!
-    STP 	X12, X13, [SP, #-0x10]!
-    STP 	X14, X15, [SP, #-0x10]!
-    STP 	X16, X17, [SP, #-0x10]!
-    STP 	X18, X19, [SP, #-0x10]!
-    STP 	X20, X21, [SP, #-0x10]!
-    STP 	X22, X23, [SP, #-0x10]!
-    STP 	X24, X25, [SP, #-0x10]!
-    STP 	X26, X27, [SP, #-0x10]!
-    STP 	X28, X29, [SP, #-0x10]!
-    STP 	X30, XZR, [SP, #-0x10]!
-
-    MRS		X0, CurrentEL
-    CMP		X0, 0xc
-    B.EQ	3f
-    CMP		X0, 0x8
-    B.EQ	2f
-    CMP		X0, 0x4
-    B.EQ	1f
-    B 		.
-3:
-    MRS		X3, SPSR_EL3
-    /* Save the ELR. */
-    MRS		X2, ELR_EL3
-    B		0f
-2:
-    MRS		X3, SPSR_EL2
-    /* Save the ELR. */
-    MRS		X2, ELR_EL2
-    B		0f
-1:
-    MRS		X3, SPSR_EL1
-    MRS		X2, ELR_EL1
-    B		0f
-0:
-
-    STP 	X2, X3, [SP, #-0x10]!
-
-    MOV 	X0, SP   /* Move SP into X0 for saving. */
-
-    /* Switch to use the ELx stack pointer. */
-    MSR 	SPSEL, #1
-
-    .endm
-
-.macro SAVE_CONTEXT_T
-
-    /* Switch to use the EL0 stack pointer. */
-    MSR 	SPSEL, #0
-
-    /* Save the entire context. */
-    STP 	X0, X1, [SP, #-0x10]!
-    STP 	X2, X3, [SP, #-0x10]!
-    STP 	X4, X5, [SP, #-0x10]!
-    STP 	X6, X7, [SP, #-0x10]!
-    STP 	X8, X9, [SP, #-0x10]!
-    STP 	X10, X11, [SP, #-0x10]!
-    STP 	X12, X13, [SP, #-0x10]!
-    STP 	X14, X15, [SP, #-0x10]!
-    STP 	X16, X17, [SP, #-0x10]!
-    STP 	X18, X19, [SP, #-0x10]!
-    STP 	X20, X21, [SP, #-0x10]!
-    STP 	X22, X23, [SP, #-0x10]!
-    STP 	X24, X25, [SP, #-0x10]!
-    STP 	X26, X27, [SP, #-0x10]!
-    STP 	X28, X29, [SP, #-0x10]!
-    STP 	X30, XZR, [SP, #-0x10]!
-
-    MRS		X0, CurrentEL
-    CMP		X0, 0xc
-    B.EQ	3f
-    CMP		X0, 0x8
-    B.EQ	2f
-    CMP		X0, 0x4
-    B.EQ	1f
-    B 		.
-3:
-    MRS		X3, SPSR_EL3
-    MOV		X2, X30
-    B		0f
-2:
-    MRS		X3, SPSR_EL2
-    MOV		X2, X30
-    B		0f
-1:
-    MRS		X3, SPSR_EL1
-    MOV		X2, X30
-    B		0f
-0:
-
-    STP 	X2, X3, [SP, #-0x10]!
-
-    MOV 	X0, SP   /* Move SP into X0 for saving. */
-
-    /* Switch to use the ELx stack pointer. */
-    MSR 	SPSEL, #1
-
-    .endm
-
-.macro RESTORE_CONTEXT
-
-    /* Switch to use the EL0 stack pointer. */
-    MSR 	SPSEL, #0
-
-    /* Set the SP to point to the stack of the task being restored. */
-    MOV		SP, X0
-
-    LDP 	X2, X3, [SP], #0x10  /* SPSR and ELR. */
-
-    MRS		X0, CurrentEL
-    CMP		X0, 0xc
-    B.EQ	3f
-    CMP		X0, 0x8
-    B.EQ	2f
-    CMP		X0, 0x4
-    B.EQ	1f
-    B 		.
-3:
-    MSR		SPSR_EL3, X3
-    MSR		ELR_EL3, X2
-    B		0f
-2:
-    MSR		SPSR_EL2, X3
-    MSR		ELR_EL2, X2
-    B		0f
-1:
-    MSR		SPSR_EL1, X3
-    MSR		ELR_EL1, X2
-    B		0f
-0:
-
-    LDP 	X30, XZR, [SP], #0x10
-    LDP 	X28, X29, [SP], #0x10
-    LDP 	X26, X27, [SP], #0x10
-    LDP 	X24, X25, [SP], #0x10
-    LDP 	X22, X23, [SP], #0x10
-    LDP 	X20, X21, [SP], #0x10
-    LDP 	X18, X19, [SP], #0x10
-    LDP 	X16, X17, [SP], #0x10
-    LDP 	X14, X15, [SP], #0x10
-    LDP 	X12, X13, [SP], #0x10
-    LDP 	X10, X11, [SP], #0x10
-    LDP 	X8, X9, [SP], #0x10
-    LDP 	X6, X7, [SP], #0x10
-    LDP 	X4, X5, [SP], #0x10
-    LDP 	X2, X3, [SP], #0x10
-    LDP 	X0, X1, [SP], #0x10
-
-    /* Switch to use the ELx stack pointer.  _RB_ Might not be required. */
-    MSR 	SPSEL, #1
-
-    ERET
-
-    .endm
-
-.text
-/*
- * rt_base_t rt_hw_interrupt_disable();
- */
-.globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    MRS      X0, DAIF
-    MSR      DAIFSet, #3
-    DSB      SY
-    RET
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level);
- */
-.globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
-    DSB     SY
-    MOV     X1, #0xC0
-    ANDS    X0, X0, X1
-    B.NE    rt_hw_interrupt_enable_exit
-    MSR     DAIFClr, #3
-rt_hw_interrupt_enable_exit:
-    RET
-
-/*
- * void rt_hw_context_switch_to(rt_ubase_t to);
- * r0 --> to
- */
-.globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    LDR		X0, [X0]
-    RESTORE_CONTEXT
-
-.text
-/*
- * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
- * r0 --> from
- * r1 --> to
- */
-.globl rt_hw_context_switch
-rt_hw_context_switch:
-
-    MOV		X8,X0
-    MOV		X9,X1
-
-    SAVE_CONTEXT_T
-    
-    STR		X0, [X8]            // store sp in preempted tasks TCB
-    LDR		X0, [X9]            // get new task stack pointer
-    
-    RESTORE_CONTEXT
-
-/*
- * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
- */
-.globl rt_thread_switch_interrupt_flag
-.globl rt_interrupt_from_thread
-.globl rt_interrupt_to_thread
-.globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
-    ADR 	X2, rt_thread_switch_interrupt_flag
-    LDR 	X3, [X2]
-    CMP 	X3, #1
-    B.EQ 	_reswitch
-    ADR 	X4, rt_interrupt_from_thread   // set rt_interrupt_from_thread
-    MOV 	X3, #1              // set rt_thread_switch_interrupt_flag to 1
-    STR 	X0, [X4]
-    STR 	X3, [X2]
-_reswitch:
-    ADR 	X2, rt_interrupt_to_thread     // set rt_interrupt_to_thread
-    STR 	X1, [X2]
-    RET
-
-.text
-
-// -- Exception handlers ----------------------------------
-
-    .align  8
-.globl vector_fiq
-vector_fiq:
-    SAVE_CONTEXT
-    STP 	X0, X1, [SP, #-0x10]!
-    BL      rt_hw_trap_fiq
-    LDP 	X0, X1, [SP], #0x10
-    RESTORE_CONTEXT
-
-.globl      rt_interrupt_enter
-.globl      rt_interrupt_leave
-.globl      rt_thread_switch_interrupt_flag
-.globl      rt_interrupt_from_thread
-.globl      rt_interrupt_to_thread
-
-
-// -------------------------------------------------------------------
-
-    .align  8
-.globl vector_irq
-vector_irq:
-    SAVE_CONTEXT
-    STP 	X0, X1, [SP, #-0x10]!
-
-    BL      rt_interrupt_enter
-    BL      rt_hw_trap_irq
-    BL      rt_interrupt_leave
-    
-    LDP 	X0, X1, [SP], #0x10
-
-    // if rt_thread_switch_interrupt_flag set, jump to
-    // rt_hw_context_switch_interrupt_do and don't return
-    ADR 	X1, rt_thread_switch_interrupt_flag
-    LDR     X2, [X1]
-    CMP     X2, #1
-    B.NE     vector_irq_exit
-
-    MOV     X2,  #0         // clear flag
-    STR     X2,  [X1]
-
-    ADR     X3,  rt_interrupt_from_thread
-    LDR     X4,  [X3]
-    STR     x0,  [X4]       // store sp in preempted tasks's TCB
-
-    ADR     x3,  rt_interrupt_to_thread
-    LDR     X4,  [X3]
-    LDR     x0,  [X4]       // get new task's stack pointer
-    
-vector_irq_exit:	
-    RESTORE_CONTEXT
-
-// -------------------------------------------------
-
-    .align  8
-    .globl  vector_error
-vector_error:
-    SAVE_CONTEXT
-    BL      rt_hw_trap_error
-    B       .
diff --git a/libcpu/aarch64/cortex-a53/cp15.h b/libcpu/aarch64/cortex-a53/cp15.h
deleted file mode 100644
index f3ffd6f857..0000000000
--- a/libcpu/aarch64/cortex-a53/cp15.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-15     Bernard      first version
- */
-
-#ifndef __CP15_H__
-#define __CP15_H__
-
-#ifndef   __STATIC_FORCEINLINE
-#define __STATIC_FORCEINLINE     __attribute__((always_inline)) static inline
-#endif
-
-#define __WFI()    __asm__ volatile ("wfi":::"memory")
-
-#define __WFE()    __asm__ volatile ("wfe":::"memory")
-
-#define __SEV()    __asm__ volatile ("sev")
-
-__STATIC_FORCEINLINE  void __ISB(void)
-{
-    __asm__ volatile ("isb 0xF":::"memory");
-}
-
-/**
-  \brief   Data Synchronization Barrier
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-__STATIC_FORCEINLINE  void __DSB(void)
-{
-    __asm__ volatile ("dsb 0xF":::"memory");
-}
-
-/**
-  \brief   Data Memory Barrier
-  \details Ensures the apparent order of the explicit memory operations before
-           and after the instruction, without ensuring their completion.
- */
-
-__STATIC_FORCEINLINE  void __DMB(void)
-{
-    __asm__ volatile ("dmb 0xF":::"memory");
-}
-
-#ifdef RT_USING_SMP
-static inline void send_ipi_msg(int cpu, int ipi_vector)
-{
-    IPI_MAILBOX_SET(cpu) = 1 << ipi_vector;
-}
-
-static inline void setup_bootstrap_addr(int cpu, int addr)
-{
-	CORE_MAILBOX3_SET(cpu) = addr;
-}
-
-static inline void enable_cpu_ipi_intr(int cpu)
-{
-    COREMB_INTCTL(cpu) = IPI_MAILBOX_INT_MASK;
-}
-
-static inline void enable_cpu_timer_intr(int cpu)
-{
-	CORETIMER_INTCTL(cpu) = 0x8;
-}
-
-static inline void enable_cntv(void)
-{
-    rt_uint32_t cntv_ctl;
-    cntv_ctl = 1;
-    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
-}
-
-static inline void disable_cntv(void)
-{
-    rt_uint32_t cntv_ctl;
-    cntv_ctl = 0;
-    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
-}
-
-static inline  void mask_cntv(void)
-{
-    rt_uint32_t cntv_ctl;
-    cntv_ctl = 2;
-    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
-}
-
-static inline void unmask_cntv(void)
-{
-    rt_uint32_t cntv_ctl;
-    cntv_ctl = 1;
-    asm volatile ("mcr p15, 0, %0, c14, c3, 1" :: "r"(cntv_ctl) ); // write CNTV_CTL
-}
-
-static inline rt_uint64_t read_cntvct(void)
-{
-    rt_uint32_t val,val1;
-    asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (val),"=r" (val1));
-    return (val);
-}
-
-static inline rt_uint64_t read_cntvoff(void)
-{
-
-    rt_uint64_t val;
-    asm volatile("mrrc p15, 4, %Q0, %R0, c14" : "=r" (val));
-    return (val);
-}
-
-static inline rt_uint32_t read_cntv_tval(void)
-{
-    rt_uint32_t val;
-    asm volatile ("mrc p15, 0, %0, c14, c3, 0" : "=r"(val) );
-    return val;
-}
-
-
-static inline  void write_cntv_tval(rt_uint32_t val)
-{
-    asm volatile ("mcr p15, 0, %0, c14, c3, 0" :: "r"(val) );
-    return;
-}
-
-static inline rt_uint32_t read_cntfrq(void)
-{
-    rt_uint32_t val;
-    asm volatile ("mrc p15, 0, %0, c14, c0, 0" : "=r"(val) );
-    return val;
-}
-
-
-static inline  rt_uint32_t read_cntctrl(void)
-{
-    rt_uint32_t val;
-    asm volatile ("mrc p15, 0, %0, c14, c1, 0" : "=r"(val) );
-    return val;
-}
-
-static inline uint32_t write_cntctrl(uint32_t val)
-{
-
-    asm volatile ("mcr p15, 0, %0, c14, c1, 0" : :"r"(val) );
-    return val;
-}
-#endif
-
-unsigned long rt_cpu_get_smp_id(void);
-
-void rt_cpu_mmu_disable(void);
-void rt_cpu_mmu_enable(void);
-void rt_cpu_tlb_set(volatile unsigned long*);
-
-void rt_cpu_dcache_clean_flush(void);
-void rt_cpu_icache_flush(void);
-
-void rt_cpu_vector_set_base(rt_ubase_t addr);
-void rt_hw_mmu_init(void);
-void rt_hw_vector_init(void);
-
-void set_timer_counter(unsigned int counter);
-void set_timer_control(unsigned int control);
-#endif
diff --git a/libcpu/aarch64/cortex-a53/cpu.c b/libcpu/aarch64/cortex-a53/cpu.c
deleted file mode 100644
index 962a53a071..0000000000
--- a/libcpu/aarch64/cortex-a53/cpu.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-15     Bernard      first version
- * 2019-07-28     zdzn         add smp support
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include <board.h>
-#include "cp15.h"
-
-int rt_hw_cpu_id(void)
-{
-    int cpu_id;
-    rt_base_t value;
-
-    __asm__ volatile (
-            "mrs %0, mpidr_el1"
-            :"=r"(value)
-            );
-    cpu_id = value & 0xf;
-    return cpu_id;
-};
-
-#ifdef RT_USING_SMP
-void rt_hw_spin_lock_init(rt_hw_spinlock_t *lock)
-{
-    lock->slock = 0;
-}
-
-void rt_hw_spin_lock(rt_hw_spinlock_t *lock)
-{
-    unsigned long tmp;
-    unsigned long newval;
-    rt_hw_spinlock_t lockval;
-    __asm__ __volatile__(
-            "pld [%0]"
-            ::"r"(&lock->slock)
-            );
-
-    __asm__ __volatile__(
-            "1: ldrex   %0, [%3]\n"
-            "   add %1, %0, %4\n"
-            "   strex   %2, %1, [%3]\n"
-            "   teq %2, #0\n"
-            "   bne 1b"
-            : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
-            : "r" (&lock->slock), "I" (1 << 16)
-            : "cc");
-
-    while (lockval.tickets.next != lockval.tickets.owner) {
-        __WFE();
-        lockval.tickets.owner = *(volatile unsigned short *)(&lock->tickets.owner);
-    }
-
-    __DMB();
-}
-
-void rt_hw_spin_unlock(rt_hw_spinlock_t *lock)
-{
-    __DMB();
-    lock->tickets.owner++;
-    __DSB();
-    __SEV();
-}
-#endif /*RT_USING_SMP*/
-
-/**
- * @addtogroup ARM CPU
- */
-/*@{*/
-
-/** shutdown CPU */
-void rt_hw_cpu_shutdown()
-{
-    rt_uint32_t level;
-    rt_kprintf("shutdown...\n");
-
-    level = rt_hw_interrupt_disable();
-    while (level)
-    {
-        RT_ASSERT(0);
-    }
-}
-
-/*@}*/
diff --git a/libcpu/aarch64/cortex-a53/cpu_gcc.S b/libcpu/aarch64/cortex-a53/cpu_gcc.S
deleted file mode 100644
index b8c8b8768c..0000000000
--- a/libcpu/aarch64/cortex-a53/cpu_gcc.S
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Date           Author       Notes
- * 2018-10-06     ZhaoXiaowei    the first version
- */
- 
-.text
-.globl rt_hw_get_current_el
-rt_hw_get_current_el:
-	MRS		X0, CurrentEL
-	CMP		X0, 0xc
-	B.EQ	3f
-	CMP		X0, 0x8
-	B.EQ	2f
-	CMP		X0, 0x4
-	B.EQ	1f
-	
-	LDR		X0, =0
-	B		0f
-3:
-	LDR		X0, =3
-	B		0f
-2:
-	LDR		X0, =2
-	B		0f
-1:
-	LDR		X0, =1
-	B		0f
-0:
-	RET
-
-
-.globl rt_hw_set_current_vbar
-rt_hw_set_current_vbar:
-	MRS		X1, CurrentEL
-	CMP		X1, 0xc
-	B.EQ	3f
-	CMP		X1, 0x8
-	B.EQ	2f
-	CMP		X1, 0x4
-	B.EQ	1f
-	B		0f
-3:
-	MSR		VBAR_EL3,X0
-	B		0f
-2:
-	MSR		VBAR_EL2,X0
-	B		0f
-1:
-	MSR		VBAR_EL1,X0
-	B		0f
-0:
-	RET
-
-    
-.globl rt_hw_set_elx_env
-rt_hw_set_elx_env:
-	MRS		X1, CurrentEL
-	CMP		X1, 0xc
-	B.EQ	3f
-	CMP		X1, 0x8
-	B.EQ	2f
-	CMP		X1, 0x4
-	B.EQ	1f
-	B		0f
-3:
-	MRS		X0, SCR_EL3
-	ORR		X0, X0, #0xF			/* SCR_EL3.NS|IRQ|FIQ|EA */
-	MSR		SCR_EL3, X0
-	B		0f
-2:
-	MRS	X0, HCR_EL2
-	ORR	X0, X0, #0x38
-	MSR	HCR_EL2, X0
-	B		0f
-1:
-	B		0f
-0:
-	RET
diff --git a/libcpu/aarch64/cortex-a53/interrupt.h b/libcpu/aarch64/cortex-a53/interrupt.h
index 3533d3818c..8e741ed4e6 100644
--- a/libcpu/aarch64/cortex-a53/interrupt.h
+++ b/libcpu/aarch64/cortex-a53/interrupt.h
@@ -1,11 +1,11 @@
-
 /*
  * Copyright (c) 2006-2020, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author       Notes
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
  */
 
 #ifndef __INTERRUPT_H__
@@ -19,8 +19,6 @@
 #define INT_IRQ     0x00
 #define INT_FIQ     0x01
 
-//void rt_hw_vector_init(void);
-
 void rt_hw_interrupt_init(void);
 void rt_hw_interrupt_mask(int vector);
 void rt_hw_interrupt_umask(int vector);
diff --git a/libcpu/aarch64/cortex-a53/mmu.c b/libcpu/aarch64/cortex-a53/mmu.c
deleted file mode 100644
index b799143084..0000000000
--- a/libcpu/aarch64/cortex-a53/mmu.c
+++ /dev/null
@@ -1,367 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author             Notes
- * 2020-02-20     bigmagic           first version
- */
-#include <mmu.h>
-#include <stddef.h>
-#include <rthw.h>
-
-#define TTBR_CNP    1
-
-typedef unsigned long int    uint64_t;
-
-static unsigned long main_tbl[512 * 20] __attribute__((aligned (4096)));
-
-#define IS_ALIGNED(x, a)        (((x) & ((typeof(x))(a) - 1)) == 0)
-
-#define PMD_TYPE_SECT        (1 << 0)
-
-#define PMD_TYPE_TABLE        (3 << 0)
-
-#define PTE_TYPE_PAGE        (3 << 0)
-
-#define BITS_PER_VA          39
-
-/* Granule size of 4KB is being used */
-#define GRANULE_SIZE_SHIFT         12
-#define GRANULE_SIZE               (1 << GRANULE_SIZE_SHIFT)
-#define XLAT_ADDR_MASK             ((1UL << BITS_PER_VA) - GRANULE_SIZE)
-
-#define PMD_TYPE_MASK               (3 << 0)
-
-int free_idx = 1;
-
-void __asm_invalidate_icache_all(void);
-void __asm_flush_dcache_all(void);
-int __asm_flush_l3_cache(void);
-void __asm_flush_dcache_range(unsigned long long start, unsigned long long end);
-void __asm_invalidate_dcache_all(void);
-void __asm_invalidate_icache_all(void);
-
-void mmu_memset(char *dst, char v,  size_t len)
-{
-    while (len--)
-    {
-        *dst++ = v;
-    }
-}
-
-static unsigned long __page_off = 0;
-static unsigned long get_free_page(void) 
-{
-    __page_off += 512;
-    return (unsigned long)(main_tbl + __page_off);
-}
-
-
-static inline unsigned int get_sctlr(void)
-{
-    unsigned int val;
-    asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
-    return val;
-}
-
-static inline void set_sctlr(unsigned int val)
-{
-    asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
-    asm volatile("isb");
-}
-
-void mmu_init(void)
-{
-    unsigned long val64;
-    unsigned long val32;
-
-    val64 = 0x007f6eUL;
-    __asm__ volatile("msr MAIR_EL1, %0\n dsb sy\n"::"r"(val64));
-    __asm__ volatile("mrs %0, MAIR_EL1\n dsb sy\n":"=r"(val64));
-
-    //TCR_EL1
-    val32 = (16UL << 0)//48bit
-        | (0x0UL << 6)
-        | (0x0UL << 7)
-        | (0x3UL << 8)
-        | (0x3UL << 10)//Inner Shareable
-        | (0x2UL << 12)
-        | (0x0UL << 14)//4K
-        | (0x0UL << 16)
-        | (0x0UL << 22)
-        | (0x1UL << 23)
-        | (0x2UL << 30)
-        | (0x1UL << 32)
-        | (0x0UL << 35)
-        | (0x0UL << 36)
-        | (0x0UL << 37)
-        | (0x0UL << 38);
-    __asm__ volatile("msr TCR_EL1, %0\n"::"r"(val32));
-    __asm__ volatile("mrs %0, TCR_EL1\n":"=r"(val32));
-
-    __asm__ volatile("msr TTBR0_EL1, %0\n dsb sy\n"::"r"(main_tbl));
-    __asm__ volatile("mrs %0, TTBR0_EL1\n dsb sy\n":"=r"(val64));
-
-    mmu_memset((char *)main_tbl, 0, 4096);
-}
-
-void mmu_enable(void)
-{
-    unsigned long val64;
-    unsigned long val32;
-
-    __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val64));
-    val64 &= ~0x1000; //disable I
-    __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\n isb sy\n"::"r"(val64));
-
-    __asm__ volatile("IC IALLUIS\n dsb sy\n isb sy\n");
-    __asm__ volatile("tlbi vmalle1\n dsb sy\n isb sy\n");
-
-    //SCTLR_EL1, turn on mmu
-    __asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val32));
-    val32 |= 0x1005; //enable mmu, I C M
-    __asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32));
-    rt_hw_icache_enable();
-    rt_hw_dcache_enable();
-
-}
-
-static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) 
-{
-    int level;
-    unsigned long* cur_lv_tbl = lv0_tbl;
-    unsigned long page;
-    unsigned long off;
-    int level_shift = 39;
-
-    if (va & (0x200000UL - 1)) 
-    {
-        return MMU_MAP_ERROR_VANOTALIGN;
-    }
-    if (pa & (0x200000UL - 1)) 
-    {
-        return MMU_MAP_ERROR_PANOTALIGN;
-    }
-    for (level = 0; level < 2; level++) 
-    {
-        off = (va >> level_shift);
-        off &= MMU_LEVEL_MASK;
-        if ((cur_lv_tbl[off] & 1) == 0) 
-        {
-            page = get_free_page();
-            if (!page) 
-            {
-                return MMU_MAP_ERROR_NOPAGE;
-            }
-            mmu_memset((char *)page, 0, 4096);
-            cur_lv_tbl[off] = page | 0x3UL;
-        }
-        page = cur_lv_tbl[off];
-        if (!(page & 0x2)) 
-        {
-            //is block! error!
-            return MMU_MAP_ERROR_CONFLICT;
-        }
-        cur_lv_tbl = (unsigned long*)(page & 0x0000fffffffff000UL);
-        level_shift -= 9;
-    }
-    attr &= 0xfff0000000000ffcUL;
-    pa |= (attr | 0x1UL); //block
-    off = (va >> 21);
-    off &= MMU_LEVEL_MASK;
-    cur_lv_tbl[off] = pa;
-    return 0;
-}
-
-int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr)
-{
-    int i;
-    int ret;
-
-    if (va & (0x200000 - 1))
-    {
-        return -1;
-    }
-    if (pa & (0x200000 - 1))
-    {
-        return -1;
-    }
-    for (i = 0; i < count; i++)
-    {
-        ret = map_single_page_2M((unsigned long *)main_tbl, va, pa, attr);
-        va += 0x200000;
-        pa += 0x200000;
-        if (ret != 0)
-        {
-            return ret;
-        }
-    }
-    return 0;
-}
-
-static void set_table(uint64_t *pt, uint64_t *table_addr)
-{
-    uint64_t val;
-    val = (0x3UL | (uint64_t)table_addr);
-    *pt = val;
-}
-
-void mmu_memset2(unsigned char *dst, char v,  int len)
-{
-    while (len--)
-    {
-        *dst++ = v;
-    }
-}
-
-static uint64_t *create_table(void)
-{
-    uint64_t *new_table = (uint64_t *)((unsigned char *)&main_tbl[0] + free_idx * 4096); //+ free_idx * GRANULE_SIZE;
-    /* Mark all entries as invalid */
-    mmu_memset2((unsigned char *)new_table, 0, 4096);
-    free_idx++;
-    return new_table;
-}
-
-static int pte_type(uint64_t *pte)
-{
-    return *pte & PMD_TYPE_MASK;
-}
-
-static int level2shift(int level)
-{
-    /* Page is 12 bits wide, every level translates 9 bits */
-    return (12 + 9 * (3 - level));
-}
-
-static uint64_t *get_level_table(uint64_t *pte)
-{
-    uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK);
-    
-    if (pte_type(pte) != PMD_TYPE_TABLE) 
-    {
-        table = create_table();
-        set_table(pte, table);
-    }
-    return table;
-}
-
-static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t attr)
-{
-    uint64_t block_size = 0;
-    uint64_t block_shift = 0;
-    uint64_t *pte;
-    uint64_t idx = 0;
-    uint64_t addr = 0;
-    uint64_t *table = 0;
-    int level = 0;
-
-    addr = virt;
-    while (size) 
-    {
-        table = &main_tbl[0];
-        for (level = 0; level < 4; level++) 
-        {
-            block_shift = level2shift(level);
-            idx = addr >> block_shift;
-            idx = idx%512;
-            block_size = (uint64_t)(1L << block_shift);
-            pte = table + idx;
-
-            if (size >= block_size && IS_ALIGNED(addr, block_size)) 
-            {
-                attr &= 0xfff0000000000ffcUL;
-                if(level != 3)
-                {
-                    *pte = phys | (attr | 0x1UL);
-                }
-                else
-                {
-                    *pte = phys | (attr | 0x3UL);
-                }
-                addr += block_size;
-                phys += block_size;
-                size -= block_size;
-                break;
-            }
-            table = get_level_table(pte);
-        }
-    }
-}
-
-void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr)
-{
-    map_region(va, pa, size, attr);
-}
-
-void rt_hw_dcache_enable(void)
-{
-    if (!(get_sctlr() & CR_M)) 
-    {
-        rt_kprintf("please init mmu!\n");
-    }
-    else
-    {
-        set_sctlr(get_sctlr() | CR_C);
-    }
-}
-
-void rt_hw_dcache_flush_all(void)
-{
-    int ret;
-
-    __asm_flush_dcache_all();
-    ret = __asm_flush_l3_cache();
-    if (ret)
-    {
-        rt_kprintf("flushing dcache returns 0x%x\n", ret);
-    }
-    else
-    {
-        rt_kprintf("flushing dcache successfully.\n");
-    }
-}
-
-void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size)
-{
-    __asm_flush_dcache_range(start_addr, start_addr + size);
-}
-void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size)
-{
-    __asm_flush_dcache_range(start_addr, start_addr + size);
-}
-
-void rt_hw_dcache_invalidate_all(void)
-{
-    __asm_invalidate_dcache_all();
-}
-
-void rt_hw_dcache_disable(void)
-{
-    /* if cache isn't enabled no need to disable */
-    if(!(get_sctlr() & CR_C))
-    {
-        rt_kprintf("need enable cache!\n");
-        return;
-    }
-    set_sctlr(get_sctlr() & ~CR_C);
-}
-
-//icache
-void rt_hw_icache_enable(void)
-{
-    __asm_invalidate_icache_all();
-    set_sctlr(get_sctlr() | CR_I);
-}
-
-void rt_hw_icache_invalidate_all(void)
-{
-    __asm_invalidate_icache_all();
-}
-
-void rt_hw_icache_disable(void)
-{
-    set_sctlr(get_sctlr() & ~CR_I);
-}
\ No newline at end of file
diff --git a/libcpu/aarch64/cortex-a53/mmu.h b/libcpu/aarch64/cortex-a53/mmu.h
deleted file mode 100644
index 6a66472c79..0000000000
--- a/libcpu/aarch64/cortex-a53/mmu.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author             Notes
- * 2020-02-20     bigmagic           first version
- */
-
-#ifndef  __MMU_H__
-#define  __MMU_H__
-
-/*
- * CR1 bits (CP#15 CR1)
- */
-#define CR_M    (1 << 0)    /* MMU enable                */
-#define CR_A    (1 << 1)    /* Alignment abort enable        */
-#define CR_C    (1 << 2)    /* Dcache enable            */
-#define CR_W    (1 << 3)    /* Write buffer enable            */
-#define CR_P    (1 << 4)    /* 32-bit exception handler        */
-#define CR_D    (1 << 5)    /* 32-bit data address range        */
-#define CR_L    (1 << 6)    /* Implementation defined        */
-#define CR_B    (1 << 7)    /* Big endian                */
-#define CR_S    (1 << 8)    /* System MMU protection        */
-#define CR_R    (1 << 9)    /* ROM MMU protection            */
-#define CR_F    (1 << 10)    /* Implementation defined        */
-#define CR_Z    (1 << 11)    /* Implementation defined        */
-#define CR_I    (1 << 12)    /* Icache enable            */
-#define CR_V    (1 << 13)    /* Vectors relocated to 0xffff0000    */
-#define CR_RR   (1 << 14)    /* Round Robin cache replacement    */
-#define CR_L4   (1 << 15)    /* LDR pc can set T bit            */
-#define CR_DT   (1 << 16)
-#define CR_IT   (1 << 18)
-#define CR_ST   (1 << 19)
-#define CR_FI   (1 << 21)    /* Fast interrupt (lower latency mode)    */
-#define CR_U    (1 << 22)    /* Unaligned access operation        */
-#define CR_XP   (1 << 23)    /* Extended page tables            */
-#define CR_VE   (1 << 24)    /* Vectored interrupts            */
-#define CR_EE   (1 << 25)    /* Exception (Big) Endian        */
-#define CR_TRE  (1 << 28)    /* TEX remap enable            */
-#define CR_AFE  (1 << 29)    /* Access flag enable            */
-#define CR_TE   (1 << 30)    /* Thumb exception enable        */
-
-#define MMU_LEVEL_MASK 0x1ffUL
-#define MMU_MAP_ERROR_VANOTALIGN  -1
-#define MMU_MAP_ERROR_PANOTALIGN  -2
-#define MMU_MAP_ERROR_NOPAGE      -3
-#define MMU_MAP_ERROR_CONFLICT    -4
-
-#define MEM_ATTR_MEMORY ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x1UL << 2))
-#define MEM_ATTR_IO     ((0x1UL << 10) | (0x2UL << 8) | (0x0UL << 6) | (0x2UL << 2))
-
-#define BUS_ADDRESS(phys)    (((phys) & ~0xC0000000)  |  0xC0000000)
-
-void mmu_init(void);
-
-void mmu_enable(void);
-
-int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr);
-
-void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr);
-
-//dcache
-void rt_hw_dcache_enable(void);
-void rt_hw_dcache_flush_all(void);
-void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size);
-void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size);
-void rt_hw_dcache_invalidate_all(void);
-void rt_hw_dcache_disable(void);
-
-//icache
-void rt_hw_icache_enable(void);
-void rt_hw_icache_invalidate_all(void);
-void rt_hw_icache_disable(void);
-
-
-#endif  /*__MMU_H__*/
diff --git a/libcpu/aarch64/cortex-a53/startup_gcc.S b/libcpu/aarch64/cortex-a53/startup_gcc.S
deleted file mode 100644
index ea4268148c..0000000000
--- a/libcpu/aarch64/cortex-a53/startup_gcc.S
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- */
-
-    .global	Reset_Handler
-    .section ".start", "ax"
-Reset_Handler:
-    nop
diff --git a/libcpu/aarch64/cortex-a53/vector_gcc.S b/libcpu/aarch64/cortex-a53/vector_gcc.S
deleted file mode 100644
index fc88cce7f8..0000000000
--- a/libcpu/aarch64/cortex-a53/vector_gcc.S
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Date           Author       Notes
- * 2018-10-06     ZhaoXiaowei    the first version
- */
- 
-.text
-
-.globl system_vectors
-.globl vector_error
-.globl vector_irq
-.globl vector_fiq
-
-system_vectors:
-.align 11
-    .set    VBAR, system_vectors
-    .org    VBAR
-    // Exception from CurrentEL (EL1) with SP_EL0 (SPSEL=1)
-    .org (VBAR + 0x00 + 0)
-    B vector_error      // 			Synchronous
-    .org (VBAR + 0x80 + 0)
-    B vector_irq        //          IRQ/vIRQ
-    .org (VBAR + 0x100 + 0)
-    B vector_fiq        //          FIQ/vFIQ
-    .org (VBAR + 0x180 + 0)
-    B vector_error      //          Error/vError
-
-    // Exception from CurrentEL (EL1) with SP_ELn
-    .org (VBAR + 0x200 + 0)
-    B vector_error      // 			Synchronous
-    .org (VBAR + 0x280 + 0)
-    B vector_irq    	// 			IRQ/vIRQ
-    .org (VBAR + 0x300 + 0)
-    B vector_fiq        //          FIQ/vFIQ
-    .org (VBAR + 0x380 + 0)
-    B vector_error
-
-    // Exception from lower EL, aarch64
-    .org (VBAR + 0x400 + 0)
-    B vector_error
-    .org (VBAR + 0x480 + 0)
-    B vector_error
-    .org (VBAR + 0x500 + 0)
-    B vector_error
-    .org (VBAR + 0x580 + 0)
-    B vector_error
-
-    // Exception from lower EL, aarch32
-    .org (VBAR + 0x600 + 0)
-    B vector_error
-    .org (VBAR + 0x680 + 0)
-    B vector_error
-    .org (VBAR + 0x700 + 0)
-    B vector_error
-    .org (VBAR + 0x780 + 0)
-    B vector_error
-    .org (VBAR + 0x800 + 0)
-    B vector_error
diff --git a/libcpu/aarch64/cortex-a57/SConscript b/libcpu/aarch64/cortex-a57/SConscript
new file mode 100644
index 0000000000..c6a4817802
--- /dev/null
+++ b/libcpu/aarch64/cortex-a57/SConscript
@@ -0,0 +1,13 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/aarch64/cortex-a57/entry_point.S b/libcpu/aarch64/cortex-a57/entry_point.S
new file mode 100644
index 0000000000..6d2c69226b
--- /dev/null
+++ b/libcpu/aarch64/cortex-a57/entry_point.S
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Date           Author       Notes
+ * 2020-01-15     bigmagic    the first version
+ */
+
+.section ".text.entrypoint"
+
+.set EL1_stack,         __el1_stack
+
+.global _start
+
+// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware
+// loads 'kernel8.img' file in.
+_start:
+    // read cpu id, stop slave cores
+    mrs     x1, mpidr_el1            // MPIDR_EL1: Multi-Processor Affinity Register
+    and     x1, x1, #3
+    cbz     x1, .L__cpu_0             // .L prefix is the local label in ELF 
+
+    // cpu id > 0, stop
+    // cpu id == 0 will also goto here after returned from entry() if possible
+.L__current_cpu_idle:
+    wfe
+    b       .L__current_cpu_idle
+
+.L__cpu_0:  // cpu id == 0
+
+    // set stack before our code
+
+	/* Define stack pointer for current exception level */
+	// ldr	x2, =EL1_stack
+	// mov	sp, x2
+
+    ldr     x1, =_start
+
+    // set up EL1
+    mrs     x0, CurrentEL           // CurrentEL Register. bit 2, 3. Others reserved
+    and     x0, x0, #12             // clear reserved bits
+
+    // running at EL3?
+    cmp     x0, #12                // 1100b. So, EL3
+    bne     .L__not_in_el3         // 11?  !EL3 -> 5:
+
+    // should never be executed, just for completeness. (EL3)
+    mov     x2, #0x5b1
+    msr     scr_el3, x2            // SCR_ELn  Secure Configuration Register
+    mov     x2, #0x3c9
+    msr     spsr_el3, x2           // SPSR_ELn. Saved Program Status Register. 1111001001
+    adr     x2, .L__not_in_el3   
+    msr     elr_el3, x2
+    eret                           // Exception Return: from EL3, continue from .L__not_in_el3
+
+    // running at EL2 or EL1
+.L__not_in_el3:    
+    cmp     x0, #4                 // 0x04  0100 EL1
+    beq     .L__in_el1             // EL1 -> 5:
+
+    // in EL2
+    msr     sp_el1, x1             // Set sp of EL1 to _start
+
+    // enable CNTP for EL1
+    mrs     x0, cnthctl_el2         // Counter-timer Hypervisor Control register
+    orr     x0, x0, #3
+    msr     cnthctl_el2, x0
+    msr     cntvoff_el2, xzr
+
+    // enable AArch64 in EL1
+    mov     x0, #(1 << 31)          // AArch64
+    orr     x0, x0, #(1 << 1)       // SWIO hardwired on Pi3
+    msr     hcr_el2, x0
+    mrs     x0, hcr_el2
+
+    // change execution level to EL1
+    mov     x2, #0x3c4
+    msr     spsr_el2, x2        // 1111000100
+    adr     x2, .L__in_el1
+    msr     elr_el2, x2
+    eret                        // exception return. from EL2. continue from .L__in_el1
+
+.L__in_el1:
+    mov     sp, x1             // in EL1. Set sp to _start
+
+    // Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction
+    mov     x1, #0x00300000       // Don't trap any SIMD/FP instructions in both EL0 and EL1
+    msr     cpacr_el1, x1
+
+    mrs x1, sctlr_el1
+    orr x1, x1, #(1 << 12)
+    bic x1, x1, #(3 << 3)
+    bic x1, x1, #(1 << 1)
+    msr sctlr_el1, x1
+
+    // clear bss
+    ldr     x1, =__bss_start
+    ldr     w2, =__bss_size
+
+.L__clean_bss_loop:
+    cbz     w2, .L__jump_to_entry
+    str     xzr, [x1], #8
+    sub     w2, w2, #1
+    cbnz    w2, .L__clean_bss_loop
+
+    // jump to C code, should not return
+.L__jump_to_entry:
+    bl      entry
+    // for failsafe, halt this core too
+    b       .L__current_cpu_idle
diff --git a/libcpu/aarch64/cortex-a57/interrupt.c b/libcpu/aarch64/cortex-a57/interrupt.c
new file mode 100644
index 0000000000..d770259d61
--- /dev/null
+++ b/libcpu/aarch64/cortex-a57/interrupt.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <gic_pl400.h>
+#include <board.h>
+#include <armv8.h>
+
+#define MAX_HANDLERS                256
+
+#ifdef RT_USING_SMP
+#define rt_interrupt_nest rt_cpu_self()->irq_nest
+#else
+extern volatile rt_uint8_t rt_interrupt_nest;
+#endif
+
+extern int system_vectors;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+
+rt_ubase_t rt_interrupt_from_thread;
+rt_ubase_t rt_interrupt_to_thread;
+rt_ubase_t rt_thread_switch_interrupt_flag;
+
+void rt_hw_vector_init(void)
+{
+    rt_hw_set_current_vbar((rt_ubase_t)&system_vectors);  // cpu_gcc.S
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    initIRQController();
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+    }
+
+    return old_handler;
+}
\ No newline at end of file
diff --git a/libcpu/aarch64/cortex-a57/interrupt.h b/libcpu/aarch64/cortex-a57/interrupt.h
new file mode 100644
index 0000000000..0d2d4867c7
--- /dev/null
+++ b/libcpu/aarch64/cortex-a57/interrupt.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#include <rthw.h>
+#include <board.h>
+
+#define INT_IRQ     0x00
+#define INT_FIQ     0x01
+
+void rt_hw_interrupt_init(void);
+void rt_hw_interrupt_mask(int vector);
+void rt_hw_interrupt_umask(int vector);
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name);
+
+#endif
diff --git a/libcpu/aarch64/cortex-a57/stack.c b/libcpu/aarch64/cortex-a57/stack.c
new file mode 100644
index 0000000000..68222c2c67
--- /dev/null
+++ b/libcpu/aarch64/cortex-a57/stack.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-23     Bernard      the first version
+ * 2011-10-05     Bernard      add thumb mode
+ */
+#include <rtthread.h>
+#include <board.h>
+
+#include <armv8.h>
+
+#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0)
+#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0)
+#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0)
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry 
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+	rt_uint8_t *stack_addr, void *texit)
+{
+	rt_ubase_t *stk;
+	rt_ubase_t current_el;
+
+	stk 	 = (rt_ubase_t*)stack_addr;
+
+	*(--stk) = ( rt_ubase_t ) 11;			/* X1 */
+	*(--stk) = ( rt_ubase_t ) parameter; 	/* X0 */
+	*(--stk) = ( rt_ubase_t ) 33;			/* X3 */
+	*(--stk) = ( rt_ubase_t ) 22;			/* X2 */
+	*(--stk) = ( rt_ubase_t ) 55;			/* X5 */
+	*(--stk) = ( rt_ubase_t ) 44;			/* X4 */
+	*(--stk) = ( rt_ubase_t ) 77;			/* X7 */
+	*(--stk) = ( rt_ubase_t ) 66;			/* X6 */
+	*(--stk) = ( rt_ubase_t ) 99;			/* X9 */
+	*(--stk) = ( rt_ubase_t ) 88;			/* X8 */
+	*(--stk) = ( rt_ubase_t ) 11;			/* X11 */
+	*(--stk) = ( rt_ubase_t ) 10;			/* X10 */
+	*(--stk) = ( rt_ubase_t ) 13;			/* X13 */
+	*(--stk) = ( rt_ubase_t ) 12;			/* X12 */
+	*(--stk) = ( rt_ubase_t ) 15;			/* X15 */
+	*(--stk) = ( rt_ubase_t ) 14;			/* X14 */
+	*(--stk) = ( rt_ubase_t ) 17;			/* X17 */
+	*(--stk) = ( rt_ubase_t ) 16;			/* X16 */
+	*(--stk) = ( rt_ubase_t ) 19;			/* X19 */
+	*(--stk) = ( rt_ubase_t ) 18;			/* X18 */
+	*(--stk) = ( rt_ubase_t ) 21;			/* X21 */
+	*(--stk) = ( rt_ubase_t ) 20;			/* X20 */
+	*(--stk) = ( rt_ubase_t ) 23;			/* X23 */
+	*(--stk) = ( rt_ubase_t ) 22;			/* X22 */
+	*(--stk) = ( rt_ubase_t ) 25;			/* X25 */
+	*(--stk) = ( rt_ubase_t ) 24;			/* X24 */
+	*(--stk) = ( rt_ubase_t ) 27;			/* X27 */
+	*(--stk) = ( rt_ubase_t ) 26;			/* X26 */
+	*(--stk) = ( rt_ubase_t ) 29;			/* X29 */
+	*(--stk) = ( rt_ubase_t ) 28;			/* X28 */
+	*(--stk) = ( rt_ubase_t ) 0;			/* XZR - has no effect, used so there are an even number of registers. */
+	*(--stk) = ( rt_ubase_t ) texit;		/* X30 - procedure call link register. */
+
+	current_el = rt_hw_get_current_el();
+
+	if(current_el == 3)
+	{
+		*(--stk) = INITIAL_SPSR_EL3;
+	}
+	else if(current_el == 2)
+	{
+		*(--stk) = INITIAL_SPSR_EL2;
+	}
+	else
+	{
+		*(--stk) = INITIAL_SPSR_EL1;
+	}
+
+	*(--stk) = ( rt_ubase_t ) tentry; 		/* Exception return address. */
+
+	/* return task's current stack address */
+	return (rt_uint8_t *)stk;
+}
diff --git a/libcpu/aarch64/cortex-a57/trap.c b/libcpu/aarch64/cortex-a57/trap.c
new file mode 100644
index 0000000000..d93aa18fd6
--- /dev/null
+++ b/libcpu/aarch64/cortex-a57/trap.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * 
+ * Date           Author       Notes
+ * 2018-10-06     ZhaoXiaowei    the first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "interrupt.h"
+#include "armv8.h"
+
+extern struct rt_thread *rt_current_thread;
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3);
+    rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7);
+	rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
+	rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
+	rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
+	rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
+    rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27);
+	rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
+	rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
+	rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
+}
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("error exception:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+#define GIC_ACK_INTID_MASK              0x000003ff
+
+int rt_hw_interrupt_get_irq(void);
+void rt_hw_interrupt_ack(int fiq_irq);
+
+void rt_hw_trap_irq(void)
+{
+    void *param;
+    int ir; 
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    ir = rt_hw_interrupt_get_irq();
+    if (ir == 1023)
+    {
+        /* Spurious interrupt */
+        return;
+    }
+
+    /* get interrupt service routine */
+    isr_func = isr_table[ir].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+    isr_table[ir].counter++;
+#endif
+    if (isr_func)
+    {
+        /* Interrupt for myself. */
+        param = isr_table[ir].param;
+        /* turn to interrupt service routine */
+        isr_func(ir, param);
+    }
+
+    /* end of interrupt */
+    rt_hw_interrupt_ack(ir);
+
+}
+
+void rt_hw_trap_fiq(void)
+{
+}
-- 
cgit v1.3.1


From a120c914bb003646010d1d385be36b5260284132 Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Thu, 16 Apr 2020 16:42:07 +0800
Subject: add bsp/raspi4 readme

---
 bsp/raspberry-pi/raspi3-64/README.md    |   2 +-
 bsp/raspberry-pi/raspi4/Kconfig         |   2 +-
 bsp/raspberry-pi/raspi4/README.md       |  81 +++++++++--------------
 bsp/raspberry-pi/raspi4/rtconfig.py     |   2 +-
 libcpu/aarch64/cortex-a57/SConscript    |  13 ----
 libcpu/aarch64/cortex-a57/entry_point.S | 111 --------------------------------
 libcpu/aarch64/cortex-a57/interrupt.c   |  73 ---------------------
 libcpu/aarch64/cortex-a57/interrupt.h   |  27 --------
 libcpu/aarch64/cortex-a57/stack.c       |  90 --------------------------
 libcpu/aarch64/cortex-a57/trap.c        |  98 ----------------------------
 libcpu/aarch64/cortex-a72/SConscript    |  13 ++++
 libcpu/aarch64/cortex-a72/entry_point.S | 111 ++++++++++++++++++++++++++++++++
 libcpu/aarch64/cortex-a72/interrupt.c   |  73 +++++++++++++++++++++
 libcpu/aarch64/cortex-a72/interrupt.h   |  27 ++++++++
 libcpu/aarch64/cortex-a72/stack.c       |  90 ++++++++++++++++++++++++++
 libcpu/aarch64/cortex-a72/trap.c        |  98 ++++++++++++++++++++++++++++
 16 files changed, 446 insertions(+), 465 deletions(-)
 delete mode 100644 libcpu/aarch64/cortex-a57/SConscript
 delete mode 100644 libcpu/aarch64/cortex-a57/entry_point.S
 delete mode 100644 libcpu/aarch64/cortex-a57/interrupt.c
 delete mode 100644 libcpu/aarch64/cortex-a57/interrupt.h
 delete mode 100644 libcpu/aarch64/cortex-a57/stack.c
 delete mode 100644 libcpu/aarch64/cortex-a57/trap.c
 create mode 100644 libcpu/aarch64/cortex-a72/SConscript
 create mode 100644 libcpu/aarch64/cortex-a72/entry_point.S
 create mode 100644 libcpu/aarch64/cortex-a72/interrupt.c
 create mode 100644 libcpu/aarch64/cortex-a72/interrupt.h
 create mode 100644 libcpu/aarch64/cortex-a72/stack.c
 create mode 100644 libcpu/aarch64/cortex-a72/trap.c

(limited to 'libcpu')

diff --git a/bsp/raspberry-pi/raspi3-64/README.md b/bsp/raspberry-pi/raspi3-64/README.md
index 28e00f96c0..576b13ed0e 100644
--- a/bsp/raspberry-pi/raspi3-64/README.md
+++ b/bsp/raspberry-pi/raspi3-64/README.md
@@ -17,7 +17,7 @@
 
 Windows环境下推荐使用[env工具][1]进行编译。
 
-首先下载Linux上的gcc工具，版本为gcc-arm-8.3选择aarch64-elf就可以。
+首先下载windows上的aarch64的gcc交叉编译工具，版本为gcc-arm-8.3选择aarch64-elf就可以。
 
 将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。
 
diff --git a/bsp/raspberry-pi/raspi4/Kconfig b/bsp/raspberry-pi/raspi4/Kconfig
index e71ed3d54b..075a5d81aa 100644
--- a/bsp/raspberry-pi/raspi4/Kconfig
+++ b/bsp/raspberry-pi/raspi4/Kconfig
@@ -20,7 +20,7 @@ source "$PKGS_DIR/Kconfig"
 
 config BCM2711_SOC
     bool
-    select ARCH_ARM_CORTEX_A57
+    select ARCH_ARM_CORTEX_A72
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
     select ARCH_CPU_64BIT
diff --git a/bsp/raspberry-pi/raspi4/README.md b/bsp/raspberry-pi/raspi4/README.md
index 28e00f96c0..1e7411894e 100644
--- a/bsp/raspberry-pi/raspi4/README.md
+++ b/bsp/raspberry-pi/raspi4/README.md
@@ -1,86 +1,67 @@
-# Raspberry PI 3-64板级支持包说明
+# Raspberry PI 4板级支持包说明
 
 ## 1. 简介
 
-树莓派由注册于英国的慈善组织“Raspberry Pi 基金会”开发，莓派3有三个发行版本：
+树莓派4B的核心处理器为博通BCM2711（四核1.5GHz，Cortex A72架构，树莓派3是四核A53）。LPDDR4内存，由5V/3A USB-C供电或GPIO 5V。
 
-* B : 4核 Broadcom BCM2837 (ARMv8-A) 1.2GHz，双核VideoCore IV GPU，1GB内存，100 Base-T Ethernet
-* B+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 1GB LPDDR2 SDRAM， GigaE over USB 2.0
-* A+: 4核 Broadcom BCM2837B0 Cortex-A53 (ARMv8) 1.4GHz, 512MB LPDDR2 SDRAM
+外设支持上，引入了双频Wi-Fi，蓝牙5.0，千兆网卡，MIPI CSI相机接口，两个USB口，40个扩展帧。
 
-这份RT-Thread BSP是针对 Raspberry Pi 3 64位模式的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
+这份RT-Thread BSP是针对 Raspberry Pi 4的一份移植，树莓派价格便宜, 使用者甚众，是研究和运行RT-Thread的可选平台之一。
 
 
 ## 2. 编译说明
 
-### 2.1 Window上的环境搭建
-
-Windows环境下推荐使用[env工具][1]进行编译。
-
-首先下载Linux上的gcc工具，版本为gcc-arm-8.3选择aarch64-elf就可以。
-
-将推荐将gcc解压到`\env\tools\gnu_gcc\arm_gcc`目录下。
-
-接着修改`bsp\raspberry-pi\raspi3-64\rtconfig.py`
+Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。
 
-修改路径：
+将工具链解压到指定目录,并修改当前bsp下的`EXEC_PATH`为自定义gcc目录。
 
 ```
-EXEC_PATH = r'E:/env_released_1.1.2/env/tools/gnu_gcc/arm_gcc/gcc-arm-8.3-2019.03-i686-mingw32-aarch64-elf/bin'
+PLATFORM    = 'gcc'
+EXEC_PATH   = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/'  
 ```
 
-然后在`bsp\raspberry-pi\raspi3-64\`下输入scons编译即可。
-
-### 2.2 Linux上的环境搭建
-
-Linux下推荐使用[gcc工具][2]。Linux版本下gcc版本可采用`gcc-arm-8.3-2019.03-x86_64-aarch64-elf`。
-
-直接进入`bsp\raspberry-pi\raspi3-64`，输入scons编译即可。
+直接进入`bsp\raspberry-pi\raspi4`，输入scons编译即可。
 
 
 ## 3. 执行
 
-### 3.1 下载[raspbian镜像][3]，生成可以运行的raspbian SD卡
-
-Windows下，去[etcher.io][4]下载etcher,这是个可以烧写img的工具
-
-解开下载的镜像文件, linux下使用如下的命令
+### 3.1 下载**Raspberry Pi Imager**，生成可以运行的raspbian SD卡
 
-```
-unzip 2018-06-27-raspbian-stretch-lite.zip
-```
-
-准备一张空SD卡，linux环境下，插入电脑并执行
+首先下载镜像
 
-```
-sudo dd if=2018-06-27-raspbian-stretch-lite.img of=/dev/xxx bs=32M conv=fsync
-```
+* [Raspberry Pi Imager for Ubuntu](https://downloads.raspberrypi.org/imager/imager_amd64.deb)
+* [Raspberry Pi Imager for Windows](https://downloads.raspberrypi.org/imager/imager.exe)
+* [Raspberry Pi Imager for macOS](https://downloads.raspberrypi.org/imager/imager.dmg)
 
-**注意: /dev/xxx 要换成真实环境中的SD卡所在设置，千万不要弄错。**
+### 3.2 准备好串口线
 
-Windows环境下，执行etcher选择解压后的2018-06-27-raspbian-stretch-lite.img文件和SD卡就可以开始烧写了。
+目前版本是使用raspi4的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示：
 
-最后把kernel8.img放入SD boot分区，删除其它 kernel*.img。
+![raspi2](../raspi3-32/figures/raspberrypi-console.png)
 
-### 3.2 准备好串口线
+串口参数： 115200 8N1 ，硬件和软件流控为关。
 
-目前版本是使用raspi3的 GPIO 14, GPIO 15来作路口输出，连线情况如下图所示(图片中的板子是pi2，GPIO引脚是一样的)：
+### 3.3 程序下载
 
-![raspi2](figures/raspi_uart.png)
+当编译生成了rtthread.bin文件后，我们可以将该文件放到sd卡上，并修改sd卡中的`config.txt`文件如下：
 
-串口参数： 115200 8N1 ，硬件和软件流控为关。
+```
+enable_uart=1
+arm_64bit=1
+kernel=rtthread.bin
+```
 
-按上面的方法做好SD卡后，插入树莓派，通电可以在串口上看到如下所示的输出信息：
+按上面的方法做好SD卡后，插入树莓派4，通电可以在串口上看到如下所示的输出信息：
 
 ```text
- heap: 0x00020b20 - 0x00400000
+heap: 0x000c9350 - 0x040c9350
 
  \ | /
 - RT -     Thread Operating System
- / | \     3.1.0 build Aug 23 2019
- 2006 - 2019 Copyright by rt-thread team
-Hello RT-Thread!
-msh >
+ / | \     4.0.3 build Apr 16 2020
+ 2006 - 2020 Copyright by rt-thread team
+Hi, this is RT-Thread!!
+msh />
 ```
 
 ## 4. 支持情况
diff --git a/bsp/raspberry-pi/raspi4/rtconfig.py b/bsp/raspberry-pi/raspi4/rtconfig.py
index 228ec0176a..9265b016be 100644
--- a/bsp/raspberry-pi/raspi4/rtconfig.py
+++ b/bsp/raspberry-pi/raspi4/rtconfig.py
@@ -2,7 +2,7 @@ import os
 
 # toolchains options
 ARCH        ='aarch64'
-CPU         ='cortex-a57'
+CPU         ='cortex-a72'
 CROSS_TOOL  ='gcc'
 
 if os.getenv('RTT_ROOT'):
diff --git a/libcpu/aarch64/cortex-a57/SConscript b/libcpu/aarch64/cortex-a57/SConscript
deleted file mode 100644
index c6a4817802..0000000000
--- a/libcpu/aarch64/cortex-a57/SConscript
+++ /dev/null
@@ -1,13 +0,0 @@
-# RT-Thread building script for component
-
-from building import *
-
-Import('rtconfig')
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
-CPPPATH = [cwd]
-
-group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
-
-Return('group')
diff --git a/libcpu/aarch64/cortex-a57/entry_point.S b/libcpu/aarch64/cortex-a57/entry_point.S
deleted file mode 100644
index 6d2c69226b..0000000000
--- a/libcpu/aarch64/cortex-a57/entry_point.S
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Date           Author       Notes
- * 2020-01-15     bigmagic    the first version
- */
-
-.section ".text.entrypoint"
-
-.set EL1_stack,         __el1_stack
-
-.global _start
-
-// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware
-// loads 'kernel8.img' file in.
-_start:
-    // read cpu id, stop slave cores
-    mrs     x1, mpidr_el1            // MPIDR_EL1: Multi-Processor Affinity Register
-    and     x1, x1, #3
-    cbz     x1, .L__cpu_0             // .L prefix is the local label in ELF 
-
-    // cpu id > 0, stop
-    // cpu id == 0 will also goto here after returned from entry() if possible
-.L__current_cpu_idle:
-    wfe
-    b       .L__current_cpu_idle
-
-.L__cpu_0:  // cpu id == 0
-
-    // set stack before our code
-
-	/* Define stack pointer for current exception level */
-	// ldr	x2, =EL1_stack
-	// mov	sp, x2
-
-    ldr     x1, =_start
-
-    // set up EL1
-    mrs     x0, CurrentEL           // CurrentEL Register. bit 2, 3. Others reserved
-    and     x0, x0, #12             // clear reserved bits
-
-    // running at EL3?
-    cmp     x0, #12                // 1100b. So, EL3
-    bne     .L__not_in_el3         // 11?  !EL3 -> 5:
-
-    // should never be executed, just for completeness. (EL3)
-    mov     x2, #0x5b1
-    msr     scr_el3, x2            // SCR_ELn  Secure Configuration Register
-    mov     x2, #0x3c9
-    msr     spsr_el3, x2           // SPSR_ELn. Saved Program Status Register. 1111001001
-    adr     x2, .L__not_in_el3   
-    msr     elr_el3, x2
-    eret                           // Exception Return: from EL3, continue from .L__not_in_el3
-
-    // running at EL2 or EL1
-.L__not_in_el3:    
-    cmp     x0, #4                 // 0x04  0100 EL1
-    beq     .L__in_el1             // EL1 -> 5:
-
-    // in EL2
-    msr     sp_el1, x1             // Set sp of EL1 to _start
-
-    // enable CNTP for EL1
-    mrs     x0, cnthctl_el2         // Counter-timer Hypervisor Control register
-    orr     x0, x0, #3
-    msr     cnthctl_el2, x0
-    msr     cntvoff_el2, xzr
-
-    // enable AArch64 in EL1
-    mov     x0, #(1 << 31)          // AArch64
-    orr     x0, x0, #(1 << 1)       // SWIO hardwired on Pi3
-    msr     hcr_el2, x0
-    mrs     x0, hcr_el2
-
-    // change execution level to EL1
-    mov     x2, #0x3c4
-    msr     spsr_el2, x2        // 1111000100
-    adr     x2, .L__in_el1
-    msr     elr_el2, x2
-    eret                        // exception return. from EL2. continue from .L__in_el1
-
-.L__in_el1:
-    mov     sp, x1             // in EL1. Set sp to _start
-
-    // Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction
-    mov     x1, #0x00300000       // Don't trap any SIMD/FP instructions in both EL0 and EL1
-    msr     cpacr_el1, x1
-
-    mrs x1, sctlr_el1
-    orr x1, x1, #(1 << 12)
-    bic x1, x1, #(3 << 3)
-    bic x1, x1, #(1 << 1)
-    msr sctlr_el1, x1
-
-    // clear bss
-    ldr     x1, =__bss_start
-    ldr     w2, =__bss_size
-
-.L__clean_bss_loop:
-    cbz     w2, .L__jump_to_entry
-    str     xzr, [x1], #8
-    sub     w2, w2, #1
-    cbnz    w2, .L__clean_bss_loop
-
-    // jump to C code, should not return
-.L__jump_to_entry:
-    bl      entry
-    // for failsafe, halt this core too
-    b       .L__current_cpu_idle
diff --git a/libcpu/aarch64/cortex-a57/interrupt.c b/libcpu/aarch64/cortex-a57/interrupt.c
deleted file mode 100644
index d770259d61..0000000000
--- a/libcpu/aarch64/cortex-a57/interrupt.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author         Notes
- * 2020-04-16     bigmagic       first version
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#include <gic_pl400.h>
-#include <board.h>
-#include <armv8.h>
-
-#define MAX_HANDLERS                256
-
-#ifdef RT_USING_SMP
-#define rt_interrupt_nest rt_cpu_self()->irq_nest
-#else
-extern volatile rt_uint8_t rt_interrupt_nest;
-#endif
-
-extern int system_vectors;
-
-/* exception and interrupt handler table */
-struct rt_irq_desc isr_table[MAX_HANDLERS];
-
-rt_ubase_t rt_interrupt_from_thread;
-rt_ubase_t rt_interrupt_to_thread;
-rt_ubase_t rt_thread_switch_interrupt_flag;
-
-void rt_hw_vector_init(void)
-{
-    rt_hw_set_current_vbar((rt_ubase_t)&system_vectors);  // cpu_gcc.S
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
-    initIRQController();
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param new_handler the interrupt service routine to be installed
- * @param old_handler the old interrupt service routine
- */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, const char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-    if (vector < MAX_HANDLERS)
-    {
-        old_handler = isr_table[vector].handler;
-
-        if (handler != RT_NULL)
-        {
-#ifdef RT_USING_INTERRUPT_INFO
-            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-            isr_table[vector].handler = handler;
-            isr_table[vector].param = param;
-        }
-    }
-
-    return old_handler;
-}
\ No newline at end of file
diff --git a/libcpu/aarch64/cortex-a57/interrupt.h b/libcpu/aarch64/cortex-a57/interrupt.h
deleted file mode 100644
index 0d2d4867c7..0000000000
--- a/libcpu/aarch64/cortex-a57/interrupt.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author         Notes
- * 2020-04-16     bigmagic       first version
- */
-
-#ifndef __INTERRUPT_H__
-#define __INTERRUPT_H__
-
-#include <rthw.h>
-#include <board.h>
-
-#define INT_IRQ     0x00
-#define INT_FIQ     0x01
-
-void rt_hw_interrupt_init(void);
-void rt_hw_interrupt_mask(int vector);
-void rt_hw_interrupt_umask(int vector);
-
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, const char *name);
-
-#endif
diff --git a/libcpu/aarch64/cortex-a57/stack.c b/libcpu/aarch64/cortex-a57/stack.c
deleted file mode 100644
index 68222c2c67..0000000000
--- a/libcpu/aarch64/cortex-a57/stack.c
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2011-09-23     Bernard      the first version
- * 2011-10-05     Bernard      add thumb mode
- */
-#include <rtthread.h>
-#include <board.h>
-
-#include <armv8.h>
-
-#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0)
-#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0)
-#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0)
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry 
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-	rt_uint8_t *stack_addr, void *texit)
-{
-	rt_ubase_t *stk;
-	rt_ubase_t current_el;
-
-	stk 	 = (rt_ubase_t*)stack_addr;
-
-	*(--stk) = ( rt_ubase_t ) 11;			/* X1 */
-	*(--stk) = ( rt_ubase_t ) parameter; 	/* X0 */
-	*(--stk) = ( rt_ubase_t ) 33;			/* X3 */
-	*(--stk) = ( rt_ubase_t ) 22;			/* X2 */
-	*(--stk) = ( rt_ubase_t ) 55;			/* X5 */
-	*(--stk) = ( rt_ubase_t ) 44;			/* X4 */
-	*(--stk) = ( rt_ubase_t ) 77;			/* X7 */
-	*(--stk) = ( rt_ubase_t ) 66;			/* X6 */
-	*(--stk) = ( rt_ubase_t ) 99;			/* X9 */
-	*(--stk) = ( rt_ubase_t ) 88;			/* X8 */
-	*(--stk) = ( rt_ubase_t ) 11;			/* X11 */
-	*(--stk) = ( rt_ubase_t ) 10;			/* X10 */
-	*(--stk) = ( rt_ubase_t ) 13;			/* X13 */
-	*(--stk) = ( rt_ubase_t ) 12;			/* X12 */
-	*(--stk) = ( rt_ubase_t ) 15;			/* X15 */
-	*(--stk) = ( rt_ubase_t ) 14;			/* X14 */
-	*(--stk) = ( rt_ubase_t ) 17;			/* X17 */
-	*(--stk) = ( rt_ubase_t ) 16;			/* X16 */
-	*(--stk) = ( rt_ubase_t ) 19;			/* X19 */
-	*(--stk) = ( rt_ubase_t ) 18;			/* X18 */
-	*(--stk) = ( rt_ubase_t ) 21;			/* X21 */
-	*(--stk) = ( rt_ubase_t ) 20;			/* X20 */
-	*(--stk) = ( rt_ubase_t ) 23;			/* X23 */
-	*(--stk) = ( rt_ubase_t ) 22;			/* X22 */
-	*(--stk) = ( rt_ubase_t ) 25;			/* X25 */
-	*(--stk) = ( rt_ubase_t ) 24;			/* X24 */
-	*(--stk) = ( rt_ubase_t ) 27;			/* X27 */
-	*(--stk) = ( rt_ubase_t ) 26;			/* X26 */
-	*(--stk) = ( rt_ubase_t ) 29;			/* X29 */
-	*(--stk) = ( rt_ubase_t ) 28;			/* X28 */
-	*(--stk) = ( rt_ubase_t ) 0;			/* XZR - has no effect, used so there are an even number of registers. */
-	*(--stk) = ( rt_ubase_t ) texit;		/* X30 - procedure call link register. */
-
-	current_el = rt_hw_get_current_el();
-
-	if(current_el == 3)
-	{
-		*(--stk) = INITIAL_SPSR_EL3;
-	}
-	else if(current_el == 2)
-	{
-		*(--stk) = INITIAL_SPSR_EL2;
-	}
-	else
-	{
-		*(--stk) = INITIAL_SPSR_EL1;
-	}
-
-	*(--stk) = ( rt_ubase_t ) tentry; 		/* Exception return address. */
-
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
-}
diff --git a/libcpu/aarch64/cortex-a57/trap.c b/libcpu/aarch64/cortex-a57/trap.c
deleted file mode 100644
index d93aa18fd6..0000000000
--- a/libcpu/aarch64/cortex-a57/trap.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (c) 2006-2020, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- * 
- * Date           Author       Notes
- * 2018-10-06     ZhaoXiaowei    the first version
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-
-#include "interrupt.h"
-#include "armv8.h"
-
-extern struct rt_thread *rt_current_thread;
-#ifdef RT_USING_FINSH
-extern long list_thread(void);
-#endif
-
-/**
- * this function will show registers of CPU
- *
- * @param regs the registers point
- */
-void rt_hw_show_register(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("Execption:\n");
-    rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3);
-    rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7);
-	rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
-	rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
-	rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
-	rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
-    rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27);
-	rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
-	rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
-	rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
-}
-
-/**
- * When comes across an instruction which it cannot handle,
- * it takes the undefined instruction trap.
- *
- * @param regs system registers
- *
- * @note never invoke this function in application
- */
-void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
-{
-    rt_kprintf("error exception:\n");
-    rt_hw_show_register(regs);
-#ifdef RT_USING_FINSH
-    list_thread();
-#endif
-    rt_hw_cpu_shutdown();
-}
-
-#define GIC_ACK_INTID_MASK              0x000003ff
-
-int rt_hw_interrupt_get_irq(void);
-void rt_hw_interrupt_ack(int fiq_irq);
-
-void rt_hw_trap_irq(void)
-{
-    void *param;
-    int ir; 
-    rt_isr_handler_t isr_func;
-    extern struct rt_irq_desc isr_table[];
-
-    ir = rt_hw_interrupt_get_irq();
-    if (ir == 1023)
-    {
-        /* Spurious interrupt */
-        return;
-    }
-
-    /* get interrupt service routine */
-    isr_func = isr_table[ir].handler;
-#ifdef RT_USING_INTERRUPT_INFO
-    isr_table[ir].counter++;
-#endif
-    if (isr_func)
-    {
-        /* Interrupt for myself. */
-        param = isr_table[ir].param;
-        /* turn to interrupt service routine */
-        isr_func(ir, param);
-    }
-
-    /* end of interrupt */
-    rt_hw_interrupt_ack(ir);
-
-}
-
-void rt_hw_trap_fiq(void)
-{
-}
diff --git a/libcpu/aarch64/cortex-a72/SConscript b/libcpu/aarch64/cortex-a72/SConscript
new file mode 100644
index 0000000000..c6a4817802
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/SConscript
@@ -0,0 +1,13 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('common', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/aarch64/cortex-a72/entry_point.S b/libcpu/aarch64/cortex-a72/entry_point.S
new file mode 100644
index 0000000000..6d2c69226b
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/entry_point.S
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Date           Author       Notes
+ * 2020-01-15     bigmagic    the first version
+ */
+
+.section ".text.entrypoint"
+
+.set EL1_stack,         __el1_stack
+
+.global _start
+
+// This symbol is set to 0x80000 in ld script. That is the address that raspi3's firmware
+// loads 'kernel8.img' file in.
+_start:
+    // read cpu id, stop slave cores
+    mrs     x1, mpidr_el1            // MPIDR_EL1: Multi-Processor Affinity Register
+    and     x1, x1, #3
+    cbz     x1, .L__cpu_0             // .L prefix is the local label in ELF 
+
+    // cpu id > 0, stop
+    // cpu id == 0 will also goto here after returned from entry() if possible
+.L__current_cpu_idle:
+    wfe
+    b       .L__current_cpu_idle
+
+.L__cpu_0:  // cpu id == 0
+
+    // set stack before our code
+
+	/* Define stack pointer for current exception level */
+	// ldr	x2, =EL1_stack
+	// mov	sp, x2
+
+    ldr     x1, =_start
+
+    // set up EL1
+    mrs     x0, CurrentEL           // CurrentEL Register. bit 2, 3. Others reserved
+    and     x0, x0, #12             // clear reserved bits
+
+    // running at EL3?
+    cmp     x0, #12                // 1100b. So, EL3
+    bne     .L__not_in_el3         // 11?  !EL3 -> 5:
+
+    // should never be executed, just for completeness. (EL3)
+    mov     x2, #0x5b1
+    msr     scr_el3, x2            // SCR_ELn  Secure Configuration Register
+    mov     x2, #0x3c9
+    msr     spsr_el3, x2           // SPSR_ELn. Saved Program Status Register. 1111001001
+    adr     x2, .L__not_in_el3   
+    msr     elr_el3, x2
+    eret                           // Exception Return: from EL3, continue from .L__not_in_el3
+
+    // running at EL2 or EL1
+.L__not_in_el3:    
+    cmp     x0, #4                 // 0x04  0100 EL1
+    beq     .L__in_el1             // EL1 -> 5:
+
+    // in EL2
+    msr     sp_el1, x1             // Set sp of EL1 to _start
+
+    // enable CNTP for EL1
+    mrs     x0, cnthctl_el2         // Counter-timer Hypervisor Control register
+    orr     x0, x0, #3
+    msr     cnthctl_el2, x0
+    msr     cntvoff_el2, xzr
+
+    // enable AArch64 in EL1
+    mov     x0, #(1 << 31)          // AArch64
+    orr     x0, x0, #(1 << 1)       // SWIO hardwired on Pi3
+    msr     hcr_el2, x0
+    mrs     x0, hcr_el2
+
+    // change execution level to EL1
+    mov     x2, #0x3c4
+    msr     spsr_el2, x2        // 1111000100
+    adr     x2, .L__in_el1
+    msr     elr_el2, x2
+    eret                        // exception return. from EL2. continue from .L__in_el1
+
+.L__in_el1:
+    mov     sp, x1             // in EL1. Set sp to _start
+
+    // Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction
+    mov     x1, #0x00300000       // Don't trap any SIMD/FP instructions in both EL0 and EL1
+    msr     cpacr_el1, x1
+
+    mrs x1, sctlr_el1
+    orr x1, x1, #(1 << 12)
+    bic x1, x1, #(3 << 3)
+    bic x1, x1, #(1 << 1)
+    msr sctlr_el1, x1
+
+    // clear bss
+    ldr     x1, =__bss_start
+    ldr     w2, =__bss_size
+
+.L__clean_bss_loop:
+    cbz     w2, .L__jump_to_entry
+    str     xzr, [x1], #8
+    sub     w2, w2, #1
+    cbnz    w2, .L__clean_bss_loop
+
+    // jump to C code, should not return
+.L__jump_to_entry:
+    bl      entry
+    // for failsafe, halt this core too
+    b       .L__current_cpu_idle
diff --git a/libcpu/aarch64/cortex-a72/interrupt.c b/libcpu/aarch64/cortex-a72/interrupt.c
new file mode 100644
index 0000000000..d770259d61
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/interrupt.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <gic_pl400.h>
+#include <board.h>
+#include <armv8.h>
+
+#define MAX_HANDLERS                256
+
+#ifdef RT_USING_SMP
+#define rt_interrupt_nest rt_cpu_self()->irq_nest
+#else
+extern volatile rt_uint8_t rt_interrupt_nest;
+#endif
+
+extern int system_vectors;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+
+rt_ubase_t rt_interrupt_from_thread;
+rt_ubase_t rt_interrupt_to_thread;
+rt_ubase_t rt_thread_switch_interrupt_flag;
+
+void rt_hw_vector_init(void)
+{
+    rt_hw_set_current_vbar((rt_ubase_t)&system_vectors);  // cpu_gcc.S
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    initIRQController();
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+    }
+
+    return old_handler;
+}
\ No newline at end of file
diff --git a/libcpu/aarch64/cortex-a72/interrupt.h b/libcpu/aarch64/cortex-a72/interrupt.h
new file mode 100644
index 0000000000..0d2d4867c7
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/interrupt.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author         Notes
+ * 2020-04-16     bigmagic       first version
+ */
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+#include <rthw.h>
+#include <board.h>
+
+#define INT_IRQ     0x00
+#define INT_FIQ     0x01
+
+void rt_hw_interrupt_init(void);
+void rt_hw_interrupt_mask(int vector);
+void rt_hw_interrupt_umask(int vector);
+
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, const char *name);
+
+#endif
diff --git a/libcpu/aarch64/cortex-a72/stack.c b/libcpu/aarch64/cortex-a72/stack.c
new file mode 100644
index 0000000000..68222c2c67
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/stack.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-23     Bernard      the first version
+ * 2011-10-05     Bernard      add thumb mode
+ */
+#include <rtthread.h>
+#include <board.h>
+
+#include <armv8.h>
+
+#define INITIAL_SPSR_EL3 (PSTATE_EL3 | SP_EL0)
+#define INITIAL_SPSR_EL2 (PSTATE_EL2 | SP_EL0)
+#define INITIAL_SPSR_EL1 (PSTATE_EL1 | SP_EL0)
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry 
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+	rt_uint8_t *stack_addr, void *texit)
+{
+	rt_ubase_t *stk;
+	rt_ubase_t current_el;
+
+	stk 	 = (rt_ubase_t*)stack_addr;
+
+	*(--stk) = ( rt_ubase_t ) 11;			/* X1 */
+	*(--stk) = ( rt_ubase_t ) parameter; 	/* X0 */
+	*(--stk) = ( rt_ubase_t ) 33;			/* X3 */
+	*(--stk) = ( rt_ubase_t ) 22;			/* X2 */
+	*(--stk) = ( rt_ubase_t ) 55;			/* X5 */
+	*(--stk) = ( rt_ubase_t ) 44;			/* X4 */
+	*(--stk) = ( rt_ubase_t ) 77;			/* X7 */
+	*(--stk) = ( rt_ubase_t ) 66;			/* X6 */
+	*(--stk) = ( rt_ubase_t ) 99;			/* X9 */
+	*(--stk) = ( rt_ubase_t ) 88;			/* X8 */
+	*(--stk) = ( rt_ubase_t ) 11;			/* X11 */
+	*(--stk) = ( rt_ubase_t ) 10;			/* X10 */
+	*(--stk) = ( rt_ubase_t ) 13;			/* X13 */
+	*(--stk) = ( rt_ubase_t ) 12;			/* X12 */
+	*(--stk) = ( rt_ubase_t ) 15;			/* X15 */
+	*(--stk) = ( rt_ubase_t ) 14;			/* X14 */
+	*(--stk) = ( rt_ubase_t ) 17;			/* X17 */
+	*(--stk) = ( rt_ubase_t ) 16;			/* X16 */
+	*(--stk) = ( rt_ubase_t ) 19;			/* X19 */
+	*(--stk) = ( rt_ubase_t ) 18;			/* X18 */
+	*(--stk) = ( rt_ubase_t ) 21;			/* X21 */
+	*(--stk) = ( rt_ubase_t ) 20;			/* X20 */
+	*(--stk) = ( rt_ubase_t ) 23;			/* X23 */
+	*(--stk) = ( rt_ubase_t ) 22;			/* X22 */
+	*(--stk) = ( rt_ubase_t ) 25;			/* X25 */
+	*(--stk) = ( rt_ubase_t ) 24;			/* X24 */
+	*(--stk) = ( rt_ubase_t ) 27;			/* X27 */
+	*(--stk) = ( rt_ubase_t ) 26;			/* X26 */
+	*(--stk) = ( rt_ubase_t ) 29;			/* X29 */
+	*(--stk) = ( rt_ubase_t ) 28;			/* X28 */
+	*(--stk) = ( rt_ubase_t ) 0;			/* XZR - has no effect, used so there are an even number of registers. */
+	*(--stk) = ( rt_ubase_t ) texit;		/* X30 - procedure call link register. */
+
+	current_el = rt_hw_get_current_el();
+
+	if(current_el == 3)
+	{
+		*(--stk) = INITIAL_SPSR_EL3;
+	}
+	else if(current_el == 2)
+	{
+		*(--stk) = INITIAL_SPSR_EL2;
+	}
+	else
+	{
+		*(--stk) = INITIAL_SPSR_EL1;
+	}
+
+	*(--stk) = ( rt_ubase_t ) tentry; 		/* Exception return address. */
+
+	/* return task's current stack address */
+	return (rt_uint8_t *)stk;
+}
diff --git a/libcpu/aarch64/cortex-a72/trap.c b/libcpu/aarch64/cortex-a72/trap.c
new file mode 100644
index 0000000000..d93aa18fd6
--- /dev/null
+++ b/libcpu/aarch64/cortex-a72/trap.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * 
+ * Date           Author       Notes
+ * 2018-10-06     ZhaoXiaowei    the first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "interrupt.h"
+#include "armv8.h"
+
+extern struct rt_thread *rt_current_thread;
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3);
+    rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7);
+	rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
+	rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
+	rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
+	rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
+    rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27);
+	rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
+	rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
+	rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
+}
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("error exception:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+#define GIC_ACK_INTID_MASK              0x000003ff
+
+int rt_hw_interrupt_get_irq(void);
+void rt_hw_interrupt_ack(int fiq_irq);
+
+void rt_hw_trap_irq(void)
+{
+    void *param;
+    int ir; 
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    ir = rt_hw_interrupt_get_irq();
+    if (ir == 1023)
+    {
+        /* Spurious interrupt */
+        return;
+    }
+
+    /* get interrupt service routine */
+    isr_func = isr_table[ir].handler;
+#ifdef RT_USING_INTERRUPT_INFO
+    isr_table[ir].counter++;
+#endif
+    if (isr_func)
+    {
+        /* Interrupt for myself. */
+        param = isr_table[ir].param;
+        /* turn to interrupt service routine */
+        isr_func(ir, param);
+    }
+
+    /* end of interrupt */
+    rt_hw_interrupt_ack(ir);
+
+}
+
+void rt_hw_trap_fiq(void)
+{
+}
-- 
cgit v1.3.1


From 709e0d5799a57e9904d856fd94a935bd1deb153d Mon Sep 17 00:00:00 2001
From: bigmagic <zhaofujin@rt-thread.com>
Date: Thu, 16 Apr 2020 18:48:27 +0800
Subject: add bsp/raspi4 gicv2

---
 bsp/raspberry-pi/raspi4/driver/board.c |   7 +-
 bsp/raspberry-pi/raspi4/driver/iomap.h |   1 +
 bsp/raspberry-pi/raspi4/rtconfig.py    |   2 +-
 libcpu/aarch64/common/gic/gic_pl400.c  | 478 +++++++++++++--------------------
 libcpu/aarch64/common/gic/gic_pl400.h  |  94 ++++---
 libcpu/aarch64/cortex-a72/interrupt.c  |  50 +++-
 6 files changed, 299 insertions(+), 333 deletions(-)

(limited to 'libcpu')

diff --git a/bsp/raspberry-pi/raspi4/driver/board.c b/bsp/raspberry-pi/raspi4/driver/board.c
index 9716755b72..46d629a35d 100644
--- a/bsp/raspberry-pi/raspi4/driver/board.c
+++ b/bsp/raspberry-pi/raspi4/driver/board.c
@@ -75,10 +75,6 @@ void rt_hw_board_init(void)
     rt_hw_interrupt_init(); // in libcpu/interrupt.c. Set some data structures, no operation on device
     rt_hw_vector_init();    // in libcpu/interrupt.c. == rt_cpu_vector_set_base((rt_ubase_t)&system_vectors);
 
-    /* initialize timer for os tick */
-    rt_hw_timer_init();
-    rt_thread_idle_sethook(idle_wfi);
-
     /* initialize uart */
     rt_hw_uart_init();      // driver/drv_uart.c
 #ifdef RT_USING_CONSOLE
@@ -91,6 +87,9 @@ void rt_hw_board_init(void)
     rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
     rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
 #endif
+        /* initialize timer for os tick */
+    rt_hw_timer_init();
+    rt_thread_idle_sethook(idle_wfi);
 
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
diff --git a/bsp/raspberry-pi/raspi4/driver/iomap.h b/bsp/raspberry-pi/raspi4/driver/iomap.h
index 00fc2025d9..675cd147e3 100644
--- a/bsp/raspberry-pi/raspi4/driver/iomap.h
+++ b/bsp/raspberry-pi/raspi4/driver/iomap.h
@@ -1,6 +1,7 @@
 #ifndef __RASPI4_H__
 #define __RASPI4_H__
 
+#define ARM_GIC_NR_IRQS     512
 #define INTC_BASE   0xff800000
 #define GIC_V2_DISTRIBUTOR_BASE     (INTC_BASE + 0x00041000)
 #define GIC_V2_CPU_INTERFACE_BASE   (INTC_BASE + 0x00042000)
diff --git a/bsp/raspberry-pi/raspi4/rtconfig.py b/bsp/raspberry-pi/raspi4/rtconfig.py
index 9265b016be..a1dd168d3d 100644
--- a/bsp/raspberry-pi/raspi4/rtconfig.py
+++ b/bsp/raspberry-pi/raspi4/rtconfig.py
@@ -32,7 +32,7 @@ if PLATFORM == 'gcc':
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY  = PREFIX + 'objcopy'
 
-    DEVICE = ' -march=armv8-a -mtune=cortex-a57'
+    DEVICE = ' -march=armv8-a -mtune=cortex-a72'
     CFLAGS = DEVICE + ' -Wall'
     AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
     LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,system_vectors -T link.lds'
diff --git a/libcpu/aarch64/common/gic/gic_pl400.c b/libcpu/aarch64/common/gic/gic_pl400.c
index eb35c5b2a4..4d003a9dcd 100644
--- a/libcpu/aarch64/common/gic/gic_pl400.c
+++ b/libcpu/aarch64/common/gic/gic_pl400.c
@@ -1,368 +1,262 @@
 /*
- * Copyright 2014, General Dynamics C4 Systems
+ * Copyright (c) 2006-2018, RT-Thread Development Team
  *
- * This software may be distributed and modified according to the terms of
- * the GNU General Public License version 2. Note that NO WARRANTY is provided.
- * See "LICENSE_GPLv2.txt" for details.
+ * SPDX-License-Identifier: Apache-2.0
  *
- * @TAG(GD_GPL)
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ * 2014-04-03     Grissiom     many enhancements
+ * 2018-11-22     Jesven       add rt_hw_ipi_send()
+ *                             add rt_hw_ipi_handler_install()
  */
+#include <rtthread.h>
 
 #include "gic_pl400.h"
+#include "cp15.h"
 #include "iomap.h"
 
-#define BIT(n) (1ul<<(n))
-#define MASK(n) (BIT(n)-1ul)
-
-/* Setters/getters helpers */
-#define IRQ_REG(IRQ) ((IRQ) / 32)
-#define IRQ_BIT(IRQ) BIT((IRQ) % 32)
-#define IRQ_MASK MASK(10)
-#define IS_IRQ_VALID(X) (((X)&IRQ_MASK) < SPECIAL_IRQ_START)
+#define ARM_GIC_MAX_NR 1
+struct arm_gic
+{
+    rt_uint32_t offset;         /* the first interrupt index in the vector table */
 
-#define CPU(X) (1<<(X))
-#define TARGET_CPU_ALLINT(CPU) ( \
-        ( ((CPU)&0xff)<<0  ) |\
-        ( ((CPU)&0xff)<<8  ) |\
-        ( ((CPU)&0xff)<<16 ) |\
-        ( ((CPU)&0xff)<<24 ) \
-    )
-#define TARGET_CPU0_ALLINT   TARGET_CPU_ALLINT(CPU(0))
+    rt_uint32_t dist_hw_base;   /* the base address of the gic distributor */
+    rt_uint32_t cpu_hw_base;    /* the base addrees of the gic cpu interface */
+};
 
+/* 'ARM_GIC_MAX_NR' is the number of cores */
+static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
 
-#define IRQ_SET_ALL 0xffffffff;
+static unsigned int _gic_max_irq;
 
-/* Special IRQ's */
-#define SPECIAL_IRQ_START 1020
-#define IRQ_NONE          1023
+int arm_gic_get_active_irq(rt_uint32_t index)
+{
+    int irq;
 
-/* Memory map for GIC distributor */
-struct gic_dist_map {
-    uint32_t enable;                /* 0x000 */
-    uint32_t ic_type;               /* 0x004 */
-    uint32_t dist_ident;            /* 0x008 */
-    uint32_t res1[29];              /* [0x00C, 0x080) */
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
 
-    uint32_t group[32];          /* [0x080, 0x100) */
+    irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
+    irq += _gic_table[index].offset;
+    return irq;
+}
 
-    uint32_t enable_set[32];        /* [0x100, 0x180) */
-    uint32_t enable_clr[32];        /* [0x180, 0x200) */
-    uint32_t pending_set[32];       /* [0x200, 0x280) */
-    uint32_t pending_clr[32];       /* [0x280, 0x300) */
-    uint32_t active[32];            /* [0x300, 0x380) */
-    uint32_t active_clr[32];        /* [0x380, 0x400) */
+void arm_gic_ack(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
 
-    uint32_t priority[255];         /* [0x400, 0x7FC) */
-    uint32_t res2;                  /* 0x7FC */
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
 
-    uint32_t targets[255];          /* [0x800, 0xBFC) */
-    uint32_t res3;                  /* 0xBFC */
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
 
-    uint32_t config[64];             /* [0xC00, 0xD00) */
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+}
 
-    uint32_t ppi_status;            /* [0xD00, 0xD04) */
-    uint32_t spi_status[15];        /* [0xD04, 0xD40) */
-    uint32_t res4[112];              /* [0xD40, 0xF00) */
+void arm_gic_mask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
 
-    uint32_t sgi_control;           /* 0xF00 */
-    uint32_t res5[3];               /* [0xF04, 0xF10) */
-    uint32_t sgi_pending_clr[4];    /* [0xF10, 0xF20) */
-    uint32_t sgi_pending_set[4];    /* [0xF20, 0xF30) */
-    uint32_t res10[40];             /* [0xF30, 0xFD0) */
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
 
-    uint32_t periph_id[8];         /* [0xFD0, 0xFF0) */
-    uint32_t component_id[4];       /* [0xFF0, 0xFFF] */
-};
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
 
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
 
-/* Memory map for GIC  cpu interface */
-struct gic_cpu_iface_map {
-    uint32_t icontrol;              /*  0x000         */
-    uint32_t pri_msk_c;             /*  0x004         */
-    uint32_t bp_c;                  /*  0x008         */
-    uint32_t int_ack;               /*  0x00C         */
-    uint32_t eoi;                   /*  0x010         */
-    uint32_t run_priority;          /*  0x014         */
-    uint32_t hi_pend;               /*  0x018         */
-    uint32_t ns_alias_bp_c;         /*  0x01C         */
-    uint32_t ns_alias_ack;          /*  0x020 GIC_PL400 only */
-    uint32_t ns_alias_eoi;          /*  0x024 GIC_PL400 only */
-    uint32_t ns_alias_hi_pend;      /*  0x028 GIC_PL400 only */
-
-    uint32_t res1[41];              /* [0x02C, 0x0D0) */
-    uint32_t active_priority[4];    /* [0x0D0, 0xC0] GIC_PL400 only */
-    uint32_t ns_active_priority[4]; /* [0xE0,0xF0] GIC_PL400 only */
-    uint32_t res4[3];               /* [0xF0, 0xFC] */
-
-    uint32_t cpu_if_ident;          /*  0x0FC         */
-    uint32_t deactive;              /* [0x1000] */
-};
+void arm_gic_clear_pending(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
 
-volatile struct gic_dist_map *gic_dist =
-    (volatile struct gic_dist_map*)(GIC_PL400_DISTRIBUTOR_PPTR);
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
 
-volatile struct gic_cpu_iface_map *gic_cpuiface =
-    (volatile struct gic_cpu_iface_map*)(GIC_PL400_CONTROLLER_PPTR);
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
 
-/* Helpers */
-static inline int
-is_irq_pending(irq_t irq)
-{
-    int word = irq / 32;
-    int bit = irq & 0x1f;
-    return !!(gic_dist->pending_set[word] & BIT(bit));
+    GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
 }
 
-static inline int
-is_irq_active(irq_t irq)
+void arm_gic_clear_active(rt_uint32_t index, int irq)
 {
-    int word = irq / 32;
-    int bit = irq & 0x1f;
-    return !!(gic_dist->active[word] & BIT(bit));
-}
+    rt_uint32_t mask = 1 << (irq % 32);
 
-static inline int
-is_irq_enabled(irq_t irq)
-{
-    int word = irq / 32;
-    int bit = irq & 0x1f;
-    return !!(gic_dist->enable_set[word] & BIT(bit));
-}
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
 
-static inline int
-is_irq_edge_triggered(irq_t irq)
-{
-    int word = irq / 16;
-    int bit = ((irq & 0xf) * 2);
-    return !!(gic_dist->config[word] & BIT(bit + 1));
-}
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
 
-static inline int
-is_irq_1_N(irq_t irq)
-{
-    int word = irq / 16;
-    int bit = ((irq & 0xf) * 2);
-    return !!(gic_dist->config[word] & BIT(bit + 0));
+    GIC_DIST_ACTIVE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
 }
 
-static inline int
-is_irq_N_N(irq_t irq)
+/* Set up the cpu mask for the specific interrupt */
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
 {
-    return !(is_irq_1_N(irq));
-}
+    rt_uint32_t old_tgt;
 
-static inline void
-dist_pending_clr(irq_t irq)
-{
-    int word = irq / 32;
-    int bit = irq & 0x1f;
-    /* Using |= here is detrimental to your health */
-    gic_dist->pending_clr[word] = BIT(bit);
-}
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
 
-static inline void
-dist_pending_set(irq_t irq)
-{
-    int word = irq / 32;
-    int bit = irq & 0x1f;
-    gic_dist->pending_set[word] = BIT(bit);
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
+
+    old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
+    old_tgt |=   cpumask << ((irq % 4)*8);
+
+    GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
 }
 
-static inline void
-dist_enable_clr(irq_t irq)
+void arm_gic_umask(rt_uint32_t index, int irq)
 {
-    int word = irq / 32;
-    int bit = irq & 0x1f;
-    /* Using |= here is detrimental to your health */
-    gic_dist->enable_clr[word] = BIT(bit);
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
 }
 
-static inline void
-dist_enable_set(irq_t irq)
+void arm_gic_dump_type(rt_uint32_t index)
 {
-    int word = irq / 32;
-    int bit = irq & 0x1f;
-    gic_dist->enable_set[word] = BIT(bit);
+    unsigned int gic_type;
+
+    gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
+    rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
+               (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
+               _gic_table[index].dist_hw_base,
+               _gic_max_irq,
+               gic_type & (1 << 10) ? "has" : "no",
+               gic_type);
 }
 
-/**
-   DONT_TRANSLATE
- */
-static void dist_init(void)
+void arm_gic_dump(rt_uint32_t index)
 {
-    int i;
-    int nirqs = 32 * ((gic_dist->ic_type & 0x1f) + 1);
-    gic_dist->enable = 0;
-
-#if 0
-    /* configure to group 0 for security */
-    for (i = 0; i < nirqs; i += 32) {
-        gic_dist->group[i / 32] = 0xffffffff;
-    }
-#endif
-
-    for (i = 0; i < nirqs; i += 32) {
-        /* disable */
-        gic_dist->enable_clr[i / 32] = IRQ_SET_ALL;
-        /* clear pending */
-        gic_dist->pending_clr[i / 32] = IRQ_SET_ALL;
-    }
-
-    /* reset interrupts priority */
-    for (i = 32; i < nirqs; i += 4) {
-        gic_dist->priority[i / 4] = 0x0;
+    unsigned int i, k;
+
+    k = GIC_CPU_HIGHPRI(_gic_table[index].cpu_hw_base);
+    rt_kprintf("--- high pending priority: %d(%08x)\n", k, k);
+    rt_kprintf("--- hw mask ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base,
+                                       i * 32));
     }
-
-    /*
-     * reset int target to cpu 0
-     * (Should really query which processor we're running on and use that)
-     */
-    for (i = 0; i < nirqs; i += 4) {
-        gic_dist->targets[i / 4] = TARGET_CPU0_ALLINT;
+    rt_kprintf("\n--- hw pending ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_PENDING_SET(_gic_table[index].dist_hw_base,
+                                        i * 32));
     }
-
-    /* level-triggered, 1-N */
-    for (i = 64; i < nirqs; i += 32) {
-        gic_dist->config[i / 32] = 0;
-        //gic_dist->config[i / 32] = 0x55555555;
+    rt_kprintf("\n--- hw active ---\n");
+    for (i = 0; i < _gic_max_irq / 32; i++)
+    {
+        rt_kprintf("0x%08x, ",
+                   GIC_DIST_ACTIVE_SET(_gic_table[index].dist_hw_base,
+                                       i * 32));
     }
-    /* enable the int controller */
-    gic_dist->enable = 1;
+    rt_kprintf("\n");
 }
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+FINSH_FUNCTION_EXPORT_ALIAS(arm_gic_dump, gic, show gic status);
+#endif
 
-/**
-   DONT_TRANSLATE
- */
-static void cpu_iface_init(void)
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
 {
-    uint32_t i;
+    unsigned int gic_type, i;
+    rt_uint32_t cpumask = 1 << 0;
 
-    /* For non-Exynos4, the registers are banked per CPU, need to clear them */
-    gic_dist->enable_clr[0] = IRQ_SET_ALL;
-    gic_dist->pending_clr[0] = IRQ_SET_ALL;
-    gic_dist->priority[0] = 0x00;
-    /* put everything in group 0 */
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
 
-    /* clear any software generated interrupts */
-    for (i = 0; i < 16; i += 4) {
-        gic_dist->sgi_pending_clr[i / 4] = IRQ_SET_ALL;
-    }
+    _gic_table[index].dist_hw_base = dist_base;
+    _gic_table[index].offset = irq_start;
 
-    gic_cpuiface->icontrol = 0;
-    gic_cpuiface->pri_msk_c = 0x000000f0;
-    gic_cpuiface->bp_c = 0x00000003;
+    /* Find out how many interrupts are supported. */
+    gic_type = GIC_DIST_TYPE(dist_base);
+    _gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
 
-    while (((i = gic_cpuiface->int_ack) & IRQ_MASK) != IRQ_NONE) {
-        gic_cpuiface->eoi = i;
-    }
-    gic_cpuiface->icontrol = 0x1;
-}
+    /*
+     * The GIC only supports up to 1020 interrupt sources.
+     * Limit this to either the architected maximum, or the
+     * platform maximum.
+     */
+    if (_gic_max_irq > 1020)
+        _gic_max_irq = 1020;
+    if (_gic_max_irq > ARM_GIC_NR_IRQS) /* the platform maximum interrupts */
+        _gic_max_irq = ARM_GIC_NR_IRQS;
 
-/**
-   DONT_TRANSLATE
- */
-void initIRQController(void)
-{
-    dist_init();
-    cpu_iface_init();
-}
+    cpumask |= cpumask << 8;
+    cpumask |= cpumask << 16;
+    cpumask |= cpumask << 24;
 
+    GIC_DIST_CTRL(dist_base) = 0x0;
 
+    /* Set all global interrupts to be level triggered, active low. */
+    for (i = 32; i < _gic_max_irq; i += 16)
+        GIC_DIST_CONFIG(dist_base, i) = 0x0;
 
-/*
- * The only sane way to get an GIC IRQ number that can be properly
- * ACKED later is through the int_ack register. Unfortunately, reading
- * this register changes the interrupt state to pending so future
- * reads will not return the same value For this reason, we have a
- * global variable to store the IRQ number.
- */
-static uint32_t active_irq = IRQ_NONE;
-
-/**
-   DONT_TRANSLATE
- */
-interrupt_t
-getActiveIRQ(void)
-{
-    uint32_t irq;
-    if (!IS_IRQ_VALID(active_irq)) {
-        active_irq = gic_cpuiface->int_ack;
-    }
+    /* Set all global interrupts to this CPU only. */
+    for (i = 32; i < _gic_max_irq; i += 4)
+        GIC_DIST_TARGET(dist_base, i) = cpumask;
 
-    if (IS_IRQ_VALID(active_irq)) {
-        irq = active_irq & IRQ_MASK;
-    } else {
-        irq = 1023;
-    }
+    /* Set priority on all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 4)
+        GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
 
-    return irq;
-}
+    /* Disable all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
 
-/*
- * GIC has 4 states: pending->active(+pending)->inactive
- * seL4 expects two states: active->inactive.
- * We ignore the active state in GIC to conform
- */
-/**
-   DONT_TRANSLATE
- */
-bool_t
-isIRQPending(void)
-{
-    return IS_IRQ_VALID(gic_cpuiface->hi_pend);
-}
+#if 0
+    /* All interrupts defaults to IGROUP1(IRQ). */
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_IGROUP(dist_base, i) = 0xffffffff;
+#endif
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_IGROUP(dist_base, i) = 0;
 
+    /* Enable group0 and group1 interrupt forwarding. */
+    GIC_DIST_CTRL(dist_base) = 0x01;
 
-/**
-   DONT_TRANSLATE
- */
-void
-maskInterrupt(bool_t disable, interrupt_t irq)
-{
-    if (disable) {
-        dist_enable_clr(irq);
-    } else {
-        dist_enable_set(irq);
-    }
+    return 0;
 }
 
-/**
-   DONT_TRANSLATE
- */
-void
-ackInterrupt(irq_t irq)
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
 {
-    if (!(IS_IRQ_VALID(active_irq) && (active_irq & IRQ_MASK) == irq)) {
-		return;
-	}
-    if (is_irq_edge_triggered(irq)) {
-        dist_pending_clr(irq);
-    }
-    gic_cpuiface->eoi = active_irq;
-    active_irq = IRQ_NONE;
-}
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
 
-void
-handleSpuriousIRQ(void)
-{
-}
+    _gic_table[index].cpu_hw_base = cpu_base;
 
-void rt_hw_interrupt_mask(int vector)
-{
-    maskInterrupt(1, vector);
-}
+    GIC_CPU_PRIMASK(cpu_base) = 0xf0;
+    GIC_CPU_BINPOINT(cpu_base) = 0x7;
+    /* Enable CPU interrupt */
+    GIC_CPU_CTRL(cpu_base) = 0x01;
 
-void rt_hw_interrupt_umask(int vector)
-{
-    maskInterrupt(0, vector);
+    return 0;
 }
 
-int rt_hw_interrupt_get_irq(void)
+void arm_gic_set_group(rt_uint32_t index, int vector, int group)
 {
-    return getActiveIRQ();
+    /* As for GICv2, there are only group0 and group1. */
+    RT_ASSERT(group <= 1);
+    RT_ASSERT(vector < _gic_max_irq);
+
+    if (group == 0)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) &= ~(1 << (vector % 32));
+    }
+    else if (group == 1)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) |=  (1 << (vector % 32));
+    }
 }
 
-void rt_hw_interrupt_ack(int fiq_irq)
-{
-    return ackInterrupt(fiq_irq);
-}
diff --git a/libcpu/aarch64/common/gic/gic_pl400.h b/libcpu/aarch64/common/gic/gic_pl400.h
index a43583bd7c..fa20846ea2 100644
--- a/libcpu/aarch64/common/gic/gic_pl400.h
+++ b/libcpu/aarch64/common/gic/gic_pl400.h
@@ -1,35 +1,61 @@
-
-#ifndef __ARCH_MACHINE_GIC_PL400_H
-#define __ARCH_MACHINE_GIC_PL400_H
-
-#include <stdint.h>
-
-typedef uint16_t interrupt_t;
-typedef uint16_t irq_t;
-typedef uint64_t  bool_t;
-
-/** MODIFIES: [*] */
-interrupt_t getActiveIRQ(void);
-/** MODIFIES: [*] */
-interrupt_t getPendingIRQ(void);
-/** MODIFIES: [*] */
-bool_t isIRQPending(void);
-/** MODIFIES: [*] */
-void maskInterrupt(bool_t disable, interrupt_t irq);
-/** MODIFIES: [*] */
-void ackInterrupt(irq_t irq);
-/** MODIFIES: [*] */
-static inline void setInterruptMode(irq_t irq, bool_t levelTrigger, bool_t polarityLow) { }
-
-/** MODIFIES: [*] */
-void initIRQController(void);
-
-void handleSpuriousIRQ(void);
-
-void rt_hw_interrupt_umask(int vector);
-
-int rt_hw_interrupt_get_irq(void);
-
-void rt_hw_interrupt_ack(int fiq_irq);
-#endif /* !__ARCH_MACHINE_GIC400_H */
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ */
+
+#ifndef __GIC_PL400_H__
+#define __GIC_PL400_H__
+
+#include <rthw.h>
+#include <board.h>
+
+#define __REG32(x) (*((volatile unsigned int*)((rt_uint64_t)x)))
+
+#define GIC_CPU_CTRL(hw_base)               __REG32((hw_base) + 0x00)
+#define GIC_CPU_PRIMASK(hw_base)            __REG32((hw_base) + 0x04)
+#define GIC_CPU_BINPOINT(hw_base)           __REG32((hw_base) + 0x08)
+#define GIC_CPU_INTACK(hw_base)             __REG32((hw_base) + 0x0c)
+#define GIC_CPU_EOI(hw_base)                __REG32((hw_base) + 0x10)
+#define GIC_CPU_RUNNINGPRI(hw_base)         __REG32((hw_base) + 0x14)
+#define GIC_CPU_HIGHPRI(hw_base)            __REG32((hw_base) + 0x18)
+
+#define GIC_DIST_CTRL(hw_base)              __REG32((hw_base) + 0x000)
+#define GIC_DIST_TYPE(hw_base)              __REG32((hw_base) + 0x004)
+#define GIC_DIST_IGROUP(hw_base, n)         __REG32((hw_base) + 0x080 + ((n)/32) * 4)
+#define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100 + ((n)/32) * 4)
+#define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180 + ((n)/32) * 4)
+#define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200 + ((n)/32) * 4)
+#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280 + ((n)/32) * 4)
+#define GIC_DIST_ACTIVE_SET(hw_base, n)     __REG32((hw_base) + 0x300 + ((n)/32) * 4)
+#define GIC_DIST_ACTIVE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x380 + ((n)/32) * 4)
+#define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400 +  ((n)/4) * 4)
+#define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800 +  ((n)/4) * 4)
+#define GIC_DIST_CONFIG(hw_base, n)         __REG32((hw_base) + 0xc00 + ((n)/16) * 4)
+#define GIC_DIST_SOFTINT(hw_base)           __REG32((hw_base) + 0xf00)
+#define GIC_DIST_CPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf10 + ((n)/4) * 4)
+#define GIC_DIST_ICPIDR2(hw_base)           __REG32((hw_base) + 0xfe8)
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
+
+void arm_gic_mask(rt_uint32_t index, int irq);
+void arm_gic_umask(rt_uint32_t index, int irq);
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
+void arm_gic_set_group(rt_uint32_t index, int vector, int group);
+
+int arm_gic_get_active_irq(rt_uint32_t index);
+void arm_gic_ack(rt_uint32_t index, int irq);
+
+void arm_gic_clear_active(rt_uint32_t index, int irq);
+void arm_gic_clear_pending(rt_uint32_t index, int irq);
+
+void arm_gic_dump_type(rt_uint32_t index);
+void arm_gic_dump(rt_uint32_t index);
+
+#endif
 
diff --git a/libcpu/aarch64/cortex-a72/interrupt.c b/libcpu/aarch64/cortex-a72/interrupt.c
index d770259d61..6fec968dc2 100644
--- a/libcpu/aarch64/cortex-a72/interrupt.c
+++ b/libcpu/aarch64/cortex-a72/interrupt.c
@@ -13,8 +13,10 @@
 #include <gic_pl400.h>
 #include <board.h>
 #include <armv8.h>
+#include "iomap.h"
 
 #define MAX_HANDLERS                256
+#define GIC_ACK_INTID_MASK          0x000003ff
 
 #ifdef RT_USING_SMP
 #define rt_interrupt_nest rt_cpu_self()->irq_nest
@@ -41,7 +43,15 @@ void rt_hw_vector_init(void)
  */
 void rt_hw_interrupt_init(void)
 {
-    initIRQController();
+
+    rt_uint32_t gic_cpu_base = 0;
+    rt_uint32_t gic_dist_base = 0;
+
+    /* initialize ARM GIC */
+    gic_dist_base = GIC_PL400_DISTRIBUTOR_PPTR;
+    gic_cpu_base = GIC_PL400_CONTROLLER_PPTR;
+    arm_gic_dist_init(0, gic_dist_base, 0);
+    arm_gic_cpu_init(0, gic_cpu_base);
 }
 
 /**
@@ -70,4 +80,40 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
     }
 
     return old_handler;
-}
\ No newline at end of file
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+    arm_gic_mask(0, vector);
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    arm_gic_umask(0, vector);
+}
+
+/**
+ * This function returns the active interrupt number.
+ * @param none
+ */
+int rt_hw_interrupt_get_irq(void)
+{
+    return arm_gic_get_active_irq(0) & GIC_ACK_INTID_MASK;
+}
+
+/**
+ * This function acknowledges the interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_ack(int vector)
+{
+    arm_gic_ack(0, vector);
+}
-- 
cgit v1.3.1


From 90f41ef8a2a9e7f71343be12d2f73122e17b1fc2 Mon Sep 17 00:00:00 2001
From: David Lin <linpeng1577@gmail.com>
Date: Fri, 17 Apr 2020 19:12:18 +0800
Subject: Update start_gcc.S

---
 libcpu/arm/s3c24x0/start_gcc.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'libcpu')

diff --git a/libcpu/arm/s3c24x0/start_gcc.S b/libcpu/arm/s3c24x0/start_gcc.S
index 4adc458094..cc2b2f6310 100644
--- a/libcpu/arm/s3c24x0/start_gcc.S
+++ b/libcpu/arm/s3c24x0/start_gcc.S
@@ -191,7 +191,7 @@ reset:
 copy_loop:
 	ldmia	r0!, {r3-r10}			/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}			/* copy to   target address [r1]    */
-	cmp		r0, r2					/* until source end addreee [r2]    */
+	cmp		r0, r2			/* until source end address [r2]    */
 	ble		copy_loop
 
 	/* setup stack */
-- 
cgit v1.3.1


From 5e507448ee71499aa1fbaa1f273372318f569331 Mon Sep 17 00:00:00 2001
From: David Lin <linpeng1577@gmail.com>
Date: Fri, 17 Apr 2020 19:18:52 +0800
Subject: Update start_gcc.S

---
 libcpu/arm/s3c44b0/start_gcc.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'libcpu')

diff --git a/libcpu/arm/s3c44b0/start_gcc.S b/libcpu/arm/s3c44b0/start_gcc.S
index 65b3d422dd..4c448a344f 100644
--- a/libcpu/arm/s3c44b0/start_gcc.S
+++ b/libcpu/arm/s3c44b0/start_gcc.S
@@ -107,7 +107,7 @@ reset:
 copy_loop:
 	ldmia	r0!, {r3-r10}	/* copy from source address [r0]    */
 	stmia	r1!, {r3-r10}	/* copy to   target address [r1]    */
-	cmp	r0, r2				/* until source end addreee [r2]    */
+	cmp	r0, r2		/* until source end address [r2]    */
 	ble	copy_loop
 #endif
 	
-- 
cgit v1.3.1


From ee4cabe69f90cd2bde042d7d8d114e420b09319f Mon Sep 17 00:00:00 2001
From: Huaqi Fang <578567190@qq.com>
Date: Fri, 17 Apr 2020 21:07:29 +0800
Subject: [BSP][Nuclei] Add Nuclei RISC-V Processor support

* Nuclei RISC-V Processor support is added both RV32 and RV64
* Nuclei RVSTAR BSP is added, UART driver is added
* MSH works well in RVSTAR board

---------------------------

Squashed commit of the following:

commit b7368bc2ed725c42f9adc297d0e9cf3ed706a520
Author: Huaqi Fang <578567190@qq.com>
Date:   Fri Apr 17 14:38:54 2020 +0800

    [BSP][Nuclei] Pretty source code

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 2c42a997f7b5d8aa53bdaf19ccb30596091a112d
Author: Huaqi Fang <578567190@qq.com>
Date:   Thu Apr 16 15:51:03 2020 +0800

    [libcpu] Remove ARCH_NUCLEI in libcpu kconfig

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 915ad4c076ff3d7cebda896537605e7f7939b7af
Author: Huaqi Fang <578567190@qq.com>
Date:   Thu Apr 16 15:50:00 2020 +0800

    [BSP][Nuclei] Remove ARCH_NUCLEI in bsp KConfig

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit fe43869c79675a25669447d57ea5d77385e07ca5
Author: Huaqi Fang <578567190@qq.com>
Date:   Wed Apr 15 12:43:20 2020 +0800

    [BSP][NUCLEI] Simply application main.c

    Remove previous complicated application of gd32vf103_rvstar

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 8fd31727bc7ff51c83a3c47840cff1bfb100c0ba
Author: Huaqi Fang <578567190@qq.com>
Date:   Wed Apr 15 12:38:04 2020 +0800

    [BSP][NUCLEI] Format application and board source code

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit b432308b20cdf24dfcc1398511d1d83bce6a9df2
Author: Huaqi Fang <578567190@qq.com>
Date:   Wed Apr 15 11:58:28 2020 +0800

    [BSP][Nuclei] Format source code of drivers of gd32vf103

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 7366173d749d8a51ed8d48eca09007d27aee8ad8
Author: Huaqi Fang <578567190@qq.com>
Date:   Wed Apr 15 11:54:02 2020 +0800

    [LIBCPU][NUCLEI] Optimize nuclei cpu portable code

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 8c2cd4745b7279a6721946d119441bbf7fd1a9c2
Author: Huaqi Fang <578567190@qq.com>
Date:   Tue Apr 14 15:45:42 2020 +0800

    nuclei: Update README.md

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit fa8a2f24ea5e4dbce714ffda16c1ce558e5b5ddb
Author: Huaqi Fang <578567190@qq.com>
Date:   Tue Apr 14 14:06:54 2020 +0800

    nuclei: Add gpio driver not tested

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 1be40bc50be43dfcdd105291bd24355498f9fef3
Author: Huaqi Fang <578567190@qq.com>
Date:   Thu Apr 9 14:55:22 2020 +0800

    Nuclei: Update README.md

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 4c8beb204b7ee3e38c04e1f23a1f7e4ce48aa196
Author: Huaqi Fang <578567190@qq.com>
Date:   Thu Apr 9 10:20:25 2020 +0800

    Nuclei: Change idle stack size from 256 to 396 bytes

    If changed to 396 bytes, then debug optimization level changed
    from O2 to O0, and the application can run successfully without
    stack overflow issue of tidle0 task
    warning: tidle0 stack is close to end of stack address.

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit da2bcf5c56ef32b611405a8e591ecd3f1e598b11
Author: Huaqi Fang <578567190@qq.com>
Date:   Thu Apr 9 10:11:40 2020 +0800

    nuclei: Remove unused kconfig

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 0b932c677a7934d60e70da141744790aec202ef6
Author: Huaqi Fang <578567190@qq.com>
Date:   Thu Apr 9 09:32:22 2020 +0800

    nuclei: optimize drivers support

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 0431f6f01f6efab2900de552abede83639415431
Author: Huaqi Fang <578567190@qq.com>
Date:   Wed Apr 8 19:28:02 2020 +0800

    tools: Update mkdist.py for nuclei bsp

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 0e1f502edfddff93a4a66c041be68560ef4828eb
Author: Huaqi Fang <578567190@qq.com>
Date:   Wed Apr 8 18:46:58 2020 +0800

    nuclei: optimize rvstar support directory

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 1131f6e6483d8f2fbafe07f4e598fc8f802ee85d
Author: Huaqi Fang <578567190@qq.com>
Date:   Wed Apr 8 18:37:24 2020 +0800

    nuclei: update kconfig

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit ad81c1d3bf9d80d2b561c94e903e7ce4ca2c68c6
Author: Huaqi Fang <578567190@qq.com>
Date:   Wed Apr 8 15:43:00 2020 +0800

    nuclei: Rename board name

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit d780138a1abf5da5097cc89e6a428ebeae06f284
Author: Huaqi Fang <578567190@qq.com>
Date:   Tue Apr 7 09:36:19 2020 +0800

    libcpu: Add Nuclei arch option in KConfig

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 60320d34b1d88315efe1b566fd6bc75c69851f06
Author: Huaqi Fang <578567190@qq.com>
Date:   Fri Apr 3 16:51:01 2020 +0800

    nuclei: Update nuclei sdk of rt-thread support

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit a042b806efe0ea3bc9dba80ebc7696e5941ba35f
Author: Huaqi Fang <578567190@qq.com>
Date:   Fri Apr 3 11:34:09 2020 +0800

    nuclei: modify application for not print anything

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 2a9603adcb584b29886a2b93ded2473f4e8bffb1
Author: Huaqi Fang <578567190@qq.com>
Date:   Fri Apr 3 11:31:01 2020 +0800

    nuclei: Add .gitignore for nuclei bsp

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 34aaf6aebae75c3ee9d38cc17e6bdb826ed9e357
Author: Huaqi Fang <578567190@qq.com>
Date:   Fri Apr 3 11:28:06 2020 +0800

    nuclei_sdk: update link script of rvstar to contain rt-thread needed sections

            /* section information for finsh shell */
            . = ALIGN(4);
            __fsymtab_start = .;
            KEEP(*(FSymTab))
            __fsymtab_end = .;

            . = ALIGN(4);
            __vsymtab_start = .;
            KEEP(*(VSymTab))
            __vsymtab_end = .;

            /* section information for initial. */
            . = ALIGN(4);
            __rt_init_start = .;
            KEEP(*(SORT(.rti_fn*)))
            __rt_init_end = .;

    The above code placed in rodata section

    Signed-off-by: Huaqi Fang <578567190@qq.com>

commit 3451466e9d8da3c3c8a631be69f3c7a5e6220c21
Author: Huaqi Fang <578567190@qq.com>
Date:   Fri Apr 3 10:04:42 2020 +0800

    bsp: Add initial commit of nuclei rvstar board bsp

    Signed-off-by: Huaqi Fang <578567190@qq.com>

Signed-off-by: Huaqi Fang <578567190@qq.com>
---
 bsp/nuclei/.gitignore                              |  26 ++
 bsp/nuclei/gd32vf103_rvstar/.config                | 453 ++++++++++++++++++
 bsp/nuclei/gd32vf103_rvstar/Kconfig                |  28 ++
 bsp/nuclei/gd32vf103_rvstar/README.md              | 209 +++++++++
 bsp/nuclei/gd32vf103_rvstar/SConscript             |  17 +
 bsp/nuclei/gd32vf103_rvstar/SConstruct             |  85 ++++
 .../gd32vf103_rvstar/applications/SConscript       |  11 +
 bsp/nuclei/gd32vf103_rvstar/applications/main.c    |  19 +
 bsp/nuclei/gd32vf103_rvstar/board/Kconfig          |  47 ++
 bsp/nuclei/gd32vf103_rvstar/board/SConscript       |  11 +
 bsp/nuclei/gd32vf103_rvstar/board/board.c          |  67 +++
 bsp/nuclei/gd32vf103_rvstar/board/board.h          |  21 +
 bsp/nuclei/gd32vf103_rvstar/rtconfig.h             | 181 +++++++
 bsp/nuclei/gd32vf103_rvstar/rtconfig.py            |  58 +++
 .../libraries/gd32vf103/HAL_Drivers/SConscript     |  21 +
 .../libraries/gd32vf103/HAL_Drivers/drv_config.h   |  26 ++
 .../libraries/gd32vf103/HAL_Drivers/drv_gpio.c     | 520 +++++++++++++++++++++
 .../libraries/gd32vf103/HAL_Drivers/drv_gpio.h     |  51 ++
 .../libraries/gd32vf103/HAL_Drivers/drv_usart.c    | 347 ++++++++++++++
 .../libraries/gd32vf103/HAL_Drivers/drv_usart.h    |  36 ++
 libcpu/risc-v/SConscript                           |   3 +-
 libcpu/risc-v/nuclei/SConscript                    |  14 +
 libcpu/risc-v/nuclei/context_gcc.S                 | 188 ++++++++
 libcpu/risc-v/nuclei/cpuport.c                     | 259 ++++++++++
 libcpu/risc-v/nuclei/cpuport.h                     |  40 ++
 libcpu/risc-v/nuclei/interrupt_gcc.S               | 218 +++++++++
 tools/mkdist.py                                    |   7 +
 27 files changed, 2962 insertions(+), 1 deletion(-)
 create mode 100644 bsp/nuclei/.gitignore
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/.config
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/Kconfig
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/README.md
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/SConscript
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/SConstruct
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/applications/SConscript
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/applications/main.c
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/board/Kconfig
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/board/SConscript
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/board/board.c
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/board/board.h
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/rtconfig.h
 create mode 100644 bsp/nuclei/gd32vf103_rvstar/rtconfig.py
 create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript
 create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h
 create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c
 create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h
 create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c
 create mode 100644 bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h
 create mode 100644 libcpu/risc-v/nuclei/SConscript
 create mode 100644 libcpu/risc-v/nuclei/context_gcc.S
 create mode 100644 libcpu/risc-v/nuclei/cpuport.c
 create mode 100644 libcpu/risc-v/nuclei/cpuport.h
 create mode 100644 libcpu/risc-v/nuclei/interrupt_gcc.S

(limited to 'libcpu')

diff --git a/bsp/nuclei/.gitignore b/bsp/nuclei/.gitignore
new file mode 100644
index 0000000000..975dcc6995
--- /dev/null
+++ b/bsp/nuclei/.gitignore
@@ -0,0 +1,26 @@
+*.i
+*.o
+*.d
+*.elf
+*.diss
+*.map
+*.bin
+*.log
+.vscode
+
+*.dump
+*.verilog
+
+*.swp
+*.swo
+
+prebuilt_tools/
+setup_config.sh
+setup_config.bat
+
+tags
+TAGS
+TAG
+CTAGS
+Makefile.local
+Makefile.global
diff --git a/bsp/nuclei/gd32vf103_rvstar/.config b/bsp/nuclei/gd32vf103_rvstar/.config
new file mode 100644
index 0000000000..c68135acc4
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/.config
@@ -0,0 +1,453 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=396
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+CONFIG_RT_DEBUG_INIT_CONFIG=y
+CONFIG_RT_DEBUG_INIT=1
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart4"
+CONFIG_RT_VER_NUM=0x40003
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV32=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+# CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=2
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_UFFS is not set
+# CONFIG_RT_USING_DFS_JFFS2 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX=y
+# CONFIG_RT_USING_POSIX_MMAP is not set
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+CONFIG_PKG_USING_NUCLEI_SDK=y
+CONFIG_PKG_NUCLEI_SDK_PATH="/packages/peripherals/nuclei_sdk"
+# CONFIG_PKG_USING_NUCLEI_SDK_V023 is not set
+CONFIG_PKG_USING_NUCLEI_SDK_LATEST_VERSION=y
+CONFIG_PKG_NUCLEI_SDK_VER="latest"
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_GD32VF103V=y
+
+#
+# Onboard Peripheral Drivers
+#
+CONFIG_BSP_USING_UART_CONSOLE=y
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+# CONFIG_BSP_USING_UART0 is not set
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+CONFIG_BSP_USING_UART4=y
+
+#
+# Board extended module Drivers
+#
+CONFIG_SOC_GD32VF103=y
diff --git a/bsp/nuclei/gd32vf103_rvstar/Kconfig b/bsp/nuclei/gd32vf103_rvstar/Kconfig
new file mode 100644
index 0000000000..fb1ab0ffd5
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/Kconfig
@@ -0,0 +1,28 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+ 
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
+
+config SOC_GD32VF103
+    bool
+    select ARCH_RISCV32
+    select PKG_USING_NUCLEI_SDK
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
diff --git a/bsp/nuclei/gd32vf103_rvstar/README.md b/bsp/nuclei/gd32vf103_rvstar/README.md
new file mode 100644
index 0000000000..f9575aa2ee
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/README.md
@@ -0,0 +1,209 @@
+# 芯来科技RVSTAR开发板 #
+
+## 简介
+
+**RVSTAR开发板** 是由芯来科技公司推出的基于采用芯来科技RISC-V架构处理器芯片的GD32VF103的开发板。
+
+更多关于 **RVSTAR开发板** 开发板的详细资料请参见 [RVSTAR开发板快速入门](https://www.rvmcu.com/quickstart-quickstart-index-u-RV_STAR.html)
+
+### 板载资源
+
+| 硬件 | 描述 |
+| ---  | --- |
+| 内核 | Nuclei N205 |
+| 架构 | 32-bit RV32IMAC |
+| 主频 | 108 MHz |
+
+## 工具安装
+
+### 安装工具链
+
+请根据[安装Nuclei RISC-V GCC Toolchain和OpenOCD](https://doc.nucleisys.com/nuclei_sdk/quickstart.html#setup-tools-and-environment) 来安装依赖的工具。
+
+### 添加环境变量
+
+将Nuclei RISC-V GCC Toolchain和OpenOCD的环境变量进行设置。
+
+#### Windows
+
+假设工具安装在 **D:\Software\Nuclei**目录下, 则可以修改系统环境变量**PATH**,
+将**D:\Software\Nuclei\gcc\bin;D:\Software\Nuclei\openocd\bin;**增加到**PATH**中。
+
+或者在ENV工具命令行中运行
+
+~~~cmd
+set PATH=D:\Software\Nuclei\gcc\bin;D:\Software\Nuclei\openocd\bin;%PATH%
+~~~
+
+#### Linux
+
+假设工具安装在 **~/Software/Nuclei**目录下, 通过在Linux的``.bashrc``增加如下一行代码
+来添加环境变量。
+
+~~~bash
+export PATH=~/Software/Nuclei/gcc/bin:~/Software/Nuclei/openocd/bin:$PATH
+~~~
+
+或者在ENV工具命令行中运行
+
+~~~bash
+export PATH=~/Software/Nuclei/gcc/bin:~/Software/Nuclei/openocd/bin:$PATH
+~~~
+
+**注意**: 对应的RISC-V GCC和OPENOCD的路径请替换成自己安装的路径。
+
+## 烧写及执行
+
+### [驱动设置](https://doc.nucleisys.com/nuclei_board_labs/hw/hw.html#on-board-debugger-driver)
+
+### 编译程序
+
+下载好[RT-Thread](https://github.com/RT-Thread/rt-thread)的代码和[ENV工具](https://www.rt-thread.org/document/site/tutorial/env-video/)以后。
+
+按照ENV工具的教程, 在**rt-thread\bsp\nuclei\gd32vf103_rvstar**目录打开ENV工具命令行。
+
+**注意**: 请确保Nuclei GCC和Nuclei OpenOCD的路径设置正确无误。
+
+1. 运行 ``pkgs --update``来下载最新的依赖的**Nuclei SDK**开发包
+2. **可选**: 运行 ``menuconfig``来进行内核配置
+3. 运行 ``scons -c``清理之前的编译结果
+4. 运行 ``scons``来进行代码的编译
+
+### 下载程序
+
+在保证程序能够正常编译后, 在相同ENV终端执行``scons --run upload``进行代码的下载。
+
+正常下载的输出如下:
+
+~~~
+scons: Reading SConscript files ...
+Supported downloaded modes for board gd32vf103v_rvstar are flashxip, chosen downloaded mode is flashxip
+Upload application rtthread.elf using openocd and gdb
+riscv-nuclei-elf-gdb rtthread.elf -ex "set remotetimeout 240"                     -ex "target remote | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg"                     --batch -ex "monitor halt" -ex "monitor flash protect 0 0 last off" -ex "load"                     -ex "monitor resume" -ex "monitor shutdown" -ex "quit"
+D:\Software\Nuclei\gcc\bin\riscv-nuclei-elf-gdb.exe: warning: Couldn't determine a path for the index cache directory.
+
+Nuclei OpenOCD, 64-bit Open On-Chip Debugger 0.10.0+dev-00014-g0eae03214 (2019-12-12-07:43)
+Licensed under GNU GPL v2
+For bug reports, read
+        http://openocd.org/doc/doxygen/bugs.html
+rt_thread_idle_entry (parameter=0x0) at D:\workspace\Sourcecode\rt-thread\src\idle.c:251
+251                 if (idle_hook_list[i] != RT_NULL)
+cleared protection for sectors 0 through 127 on flash bank 0
+
+Loading section .init, size 0x264 lma 0x8000000
+Loading section .text, size 0x140de lma 0x8000280
+Loading section .rodata, size 0x37c0 lma 0x8014360
+Loading section .data, size 0x404 lma 0x8017b20
+Start address 0x800015c, load size 98054
+Transfer rate: 8 KB/sec, 10894 bytes/write.
+shutdown command invoked
+A debugging session is active.
+
+        Inferior 1 [Remote target] will be detached.
+
+Quit anyway? (y or n) [answered Y; input not from terminal]
+Remote communication error.  Target disconnected.: Success.
+~~~
+
+下载程序之后, 连接串口(115200-N-8-1), 可以看到 RT-Thread 的输出信息：
+
+```
+initialize rti_board_start:0 done
+
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.3 build Apr  9 2020
+ 2006 - 2020 Copyright by rt-thread team
+do components initialization.
+initialize rti_board_end:0 done
+initialize dfs_init:0 done
+initialize libc_system_init:0 done
+initialize finsh_system_init:0 done
+msh />
+```
+
+在串口终端(我这里使用的是TeraTerm)输入``ps``即可查看当前线程工作情况:
+
+~~~
+msh />ps
+thread   pri  status      sp     stack size max used left tick  error
+-------- ---  ------- ---------- ----------  ------  ---------- ---
+thread01  19  suspend 0x00000158 0x0000018c    87%   0x00000005 000
+thread00  19  suspend 0x00000158 0x0000018c    87%   0x00000005 000
+tshell    20  running 0x00000258 0x00001000    18%   0x00000004 000
+tidle0    31  ready   0x000000a8 0x0000018c    59%   0x0000000e 000
+timer      4  suspend 0x000000f8 0x00000200    49%   0x00000009 000
+main      10  suspend 0x00000168 0x00000800    36%   0x00000006 000
+msh />
+~~~
+
+### 调试程序
+
+在保证程序编译成功后, 在相同ENV终端执行``scons --run debug``进行代码在命令行下进行GDB调试。
+
+正常的调试输出如下：
+
+~~~
+scons: Reading SConscript files ...
+Supported downloaded modes for board gd32vf103v_rvstar are flashxip, chosen downloaded mode is flashxip
+Debug application rtthread.elf using openocd and gdb
+riscv-nuclei-elf-gdb rtthread.elf -ex "set remotetimeout 240"                     -ex "target remote | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg"
+D:\Software\Nuclei\gcc\bin\riscv-nuclei-elf-gdb.exe: warning: Couldn't determine a path for the index cache directory.
+GNU gdb (GDB) 8.3.0.20190516-git
+Copyright (C) 2019 Free Software Foundation, Inc.
+License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
+This is free software: you are free to change and redistribute it.
+There is NO WARRANTY, to the extent permitted by law.
+Type "show copying" and "show warranty" for details.
+This GDB was configured as "--host=i686-w64-mingw32 --target=riscv-nuclei-elf".
+Type "show configuration" for configuration details.
+For bug reporting instructions, please see:
+<http://www.gnu.org/software/gdb/bugs/>.
+Find the GDB manual and other documentation resources online at:
+    <http://www.gnu.org/software/gdb/documentation/>.
+
+For help, type "help".
+Type "apropos word" to search for commands related to "word"...
+Reading symbols from rtthread.elf...
+Remote debugging using | openocd --pipe -f D:/workspace/Sourcecode/rt-thread/bsp/nuclei/gd32vf103_rvstar/packages/nuclei_sdk-latest/SoC/gd32vf103/Board/gd32vf103v_rvstar/openocd_gd32vf103.cfg Nuclei OpenOCD, 64-bit Open On-Chip Debugger 0.10.0+dev-00014-g0eae03214 (2019-12-12-07:43)
+Licensed under GNU GPL v2
+For bug reports, read
+        http://openocd.org/doc/doxygen/bugs.html
+rt_thread_idle_entry (parameter=0x0) at D:\workspace\Sourcecode\rt-thread\src\idle.c:249
+249             for (i = 0; i < RT_IDLE_HOOK_LIST_SIZE; i++)
+(gdb)
+(gdb) b main.c:35
+Breakpoint 1 at 0x8000290: file applications\main.c, line 35.
+(gdb) c
+Continuing.
+Note: automatically using hardware breakpoints for read-only addresses.
+
+Breakpoint 1, thread_entry (parameter=0x0) at applications\main.c:35
+35              rt_thread_mdelay(500);
+(gdb)
+~~~
+
+调试例子参见如下文档:
+
+* https://doc.nucleisys.com/nuclei_sdk/quickstart.html#debug-application
+
+为了更方便的进行调试, 也可以下载**Nuclei Studio**集成开发环境, 创建一个Debug Configuration, 选择编译好的
+ELF文件, 然后配置OPENOCD和GDB即可, OPENOCD配置文件路径为**bsp\nuclei\gd32vf103_rvstar\packages\nuclei_sdk-latest\SoC\gd32vf103\Board\gd32vf103v_rvstar\openocd_gd32vf103.cfg**
+
+
+## 驱动支持情况
+
+| 驱动 | 支持情况  |  备注  |
+| ------ | ----  | :------:  |
+| UART | 支持 | RV-STAR板载串口是UART4 |
+
+**注:**
+
+- 适配RT-Thread的驱动框架的代码在 [../libraries/gd32vf103/HAL_Drivers](../libraries/gd32vf103/HAL_Drivers)目录下。
+- 如果有开发者想适配更多的驱动, 请在对应目录下增加驱动适配支持。
+
+## 联系人信息
+
+维护人：
+- [fanghuaqi](https://github.com/fanghuaqi)
+
diff --git a/bsp/nuclei/gd32vf103_rvstar/SConscript b/bsp/nuclei/gd32vf103_rvstar/SConscript
new file mode 100644
index 0000000000..014c428d0a
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/SConscript
@@ -0,0 +1,17 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+ASFLAGS = ' -I' + cwd
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/nuclei/gd32vf103_rvstar/SConstruct b/bsp/nuclei/gd32vf103_rvstar/SConstruct
new file mode 100644
index 0000000000..7adcd69070
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/SConstruct
@@ -0,0 +1,85 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+AddOption('--run',
+        dest = 'run',
+        type='string',
+        nargs=1,
+        action = 'store',
+        default = "",
+        help = 'Upload or debug application using openocd')
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+GDB = rtconfig.GDB
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+bsp_library_type = rtconfig.NUCLEI_SDK_SOC
+rtconfig.BSP_LIBRARY_TYPE = bsp_library_type
+
+openocd_cfg = rtconfig.NUCLEI_SDK_OPENOCD_CFG.replace('\\', '/')
+
+# include hal drivers
+hal_sconscript = os.path.join(libraries_path_prefix, bsp_library_type, 'HAL_Drivers', 'SConscript')
+
+if os.path.isfile(hal_sconscript):
+    objs.extend(SConscript(hal_sconscript))
+
+# make a building
+DoBuilding(TARGET, objs)
+
+# Run upload or debug if --run=upload or --upload=debug
+run_target = GetOption('run')
+SUPPORT_RUN_TARGETS = ["upload", "debug"]
+if run_target in SUPPORT_RUN_TARGETS:
+    if os.path.isfile(TARGET):
+        if run_target == "upload":
+            upload_cmd = '{} {} -ex "set remotetimeout 240" \
+                    -ex "target remote | openocd --pipe -f {}" \
+                    --batch -ex "monitor halt" -ex "monitor flash protect 0 0 last off" -ex "load" \
+                    -ex "monitor resume" -ex "monitor shutdown" -ex "quit"'.format(GDB, TARGET, openocd_cfg)
+            print("Upload application {} using openocd and gdb".format(TARGET))
+            print(upload_cmd)
+            os.system(upload_cmd)
+        elif run_target == "debug":
+            debug_cmd = '{} {} -ex "set remotetimeout 240" \
+                    -ex "target remote | openocd --pipe -f {}"'.format(GDB, TARGET, openocd_cfg)
+            print("Debug application {} using openocd and gdb".format(TARGET))
+            print(debug_cmd)
+            os.system(debug_cmd)
+    else:
+        print(TARGET + ' not exist, please run scons first!!')
+    exit(0)
diff --git a/bsp/nuclei/gd32vf103_rvstar/applications/SConscript b/bsp/nuclei/gd32vf103_rvstar/applications/SConscript
new file mode 100644
index 0000000000..ef1c39fd83
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/applications/SConscript
@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd, ]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/nuclei/gd32vf103_rvstar/applications/main.c b/bsp/nuclei/gd32vf103_rvstar/applications/main.c
new file mode 100644
index 0000000000..7da5f0da45
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/applications/main.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-15     hqfang       first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+int main(int argc, char *argv[])
+{
+    return RT_EOK;
+}
+
+/******************** end of file *******************/
\ No newline at end of file
diff --git a/bsp/nuclei/gd32vf103_rvstar/board/Kconfig b/bsp/nuclei/gd32vf103_rvstar/board/Kconfig
new file mode 100644
index 0000000000..5165ac7629
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/board/Kconfig
@@ -0,0 +1,47 @@
+menu "Hardware Drivers Config"
+
+config SOC_GD32VF103V
+    bool
+    select SOC_SERIES_GD32VF103V
+    default y
+
+menu "Onboard Peripheral Drivers"
+
+    config BSP_USING_UART_CONSOLE
+        bool "Enable UART CONSOLE"
+        select BSP_USING_UART
+        select BSP_USING_UART4
+        default y
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "Enable UART0"
+                default n
+            config BSP_USING_UART1
+                bool "Enable UART1"
+                default n
+            config BSP_USING_UART2
+                bool "Enable UART2"
+                default n
+            config BSP_USING_UART3
+                bool "Enable UART3"
+                default n
+            config BSP_USING_UART4
+                bool "Enable UART4"
+                default n
+        endif
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
diff --git a/bsp/nuclei/gd32vf103_rvstar/board/SConscript b/bsp/nuclei/gd32vf103_rvstar/board/SConscript
new file mode 100644
index 0000000000..148c99f42c
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/board/SConscript
@@ -0,0 +1,11 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/nuclei/gd32vf103_rvstar/board/board.c b/bsp/nuclei/gd32vf103_rvstar/board/board.c
new file mode 100644
index 0000000000..7dad875006
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/board/board.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-02     hqfang       first version
+ *
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "cpuport.h"
+
+#ifdef RT_USING_SERIAL
+    #include <drv_usart.h>
+#endif
+
+/** _end symbol defined in linker script of Nuclei SDK */
+extern void *_end;
+
+/** _heap_end symbol defined in linker script of Nuclei SDK */
+extern void *_heap_end;
+#define HEAP_BEGIN  &_end
+#define HEAP_END    &_heap_end
+
+/*
+ * - Implemented and defined in Nuclei SDK system_<Device>.c file
+ * - Required macro NUCLEI_BANNER set to 0
+ */
+extern void _init(void);
+
+/**
+ * @brief Setup hardware board for rt-thread
+ *
+ */
+void rt_hw_board_init(void)
+{
+    /* OS Tick Configuration */
+    rt_hw_ticksetup();
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *) HEAP_BEGIN, (void *) HEAP_END);
+#endif
+
+    _init(); // __libc_init_array is not used in RT-Thread
+
+    /* USART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_usart_init();
+#endif
+
+    /* Set the shell console output device */
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    /* Board underlying hardware initialization */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+/******************** end of file *******************/
+
diff --git a/bsp/nuclei/gd32vf103_rvstar/board/board.h b/bsp/nuclei/gd32vf103_rvstar/board/board.h
new file mode 100644
index 0000000000..4e571e3ee2
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/board/board.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author          Notes
+ * 2020-04-02     hqfang          first version
+ *
+ */
+
+#ifndef __BOARD__
+#define __BOARD__
+
+#include "nuclei_sdk_hal.h"
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD__ */
+
+/******************** end of file *******************/
diff --git a/bsp/nuclei/gd32vf103_rvstar/rtconfig.h b/bsp/nuclei/gd32vf103_rvstar/rtconfig.h
new file mode 100644
index 0000000000..2498e39e9d
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/rtconfig.h
@@ -0,0 +1,181 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 396
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_DEBUG
+#define RT_DEBUG_COLOR
+#define RT_DEBUG_INIT_CONFIG
+#define RT_DEBUG_INIT 1
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart4"
+#define RT_VER_NUM 0x40003
+#define ARCH_RISCV
+#define ARCH_RISCV32
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_CMD_SIZE 80
+#define FINSH_USING_MSH
+#define FINSH_USING_MSH_DEFAULT
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 2
+#define DFS_FILESYSTEM_TYPES_MAX 2
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_USING_POSIX
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+#define PKG_USING_NUCLEI_SDK
+#define PKG_USING_NUCLEI_SDK_LATEST_VERSION
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+
+/* Hardware Drivers Config */
+
+#define SOC_GD32VF103V
+
+/* Onboard Peripheral Drivers */
+
+#define BSP_USING_UART_CONSOLE
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define BSP_USING_UART4
+
+/* Board extended module Drivers */
+
+#define SOC_GD32VF103
+
+#endif
diff --git a/bsp/nuclei/gd32vf103_rvstar/rtconfig.py b/bsp/nuclei/gd32vf103_rvstar/rtconfig.py
new file mode 100644
index 0000000000..8136b392f8
--- /dev/null
+++ b/bsp/nuclei/gd32vf103_rvstar/rtconfig.py
@@ -0,0 +1,58 @@
+import os
+
+# toolchains options
+ARCH='risc-v'
+CPU='nuclei'
+CROSS_TOOL='gcc'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if CROSS_TOOL == 'gcc':
+    PLATFORM  = 'gcc'
+    EXEC_PATH = 'D:/Software/Nuclei/gcc/bin'
+else:
+    print("CROSS_TOOL = {} not yet supported" % CROSS_TOOL)
+
+# if os.getenv('RTT_EXEC_PATH'):
+#     EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+# Fixed configurations below
+NUCLEI_SDK_SOC = "gd32vf103"
+NUCLEI_SDK_BOARD = "gd32vf103v_rvstar"
+NUCLEI_SDK_DOWNLOAD = "flashxip"
+NUCLEI_SDK_CORE = "n205"
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX  = 'riscv-nuclei-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    GDB     = PREFIX + 'gdb'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    CFLAGS  = ' -ffunction-sections -fdata-sections -fno-common '
+    AFLAGS  = CFLAGS
+    LFLAGS  = ' --specs=nano.specs --specs=nosys.specs -nostartfiles -Wl,--gc-sections '
+    LFLAGS += ' -Wl,-cref,-Map=rtthread.map'
+    LFLAGS  += ' -u _isatty -u _write -u _sbrk -u _read -u _close -u _fstat -u _lseek '
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -ggdb'
+        AFLAGS += ' -ggdb'
+    else:
+        CFLAGS += ' -O2 -Os'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript
new file mode 100644
index 0000000000..4761127102
--- /dev/null
+++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/SConscript
@@ -0,0 +1,21 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+""")
+
+if GetDepend(['RT_USING_PIN']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['RT_USING_SERIAL']):
+    src += ['drv_usart.c']
+
+path =  [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')
diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h
new file mode 100644
index 0000000000..bb24afa19e
--- /dev/null
+++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_config.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2020-04-08     hqfang            first version
+ */
+
+#ifndef __DRV_CONFIG_H__
+#define __DRV_CONFIG_H__
+
+#include <board.h>
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c
new file mode 100644
index 0000000000..75ab81f18e
--- /dev/null
+++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.c
@@ -0,0 +1,520 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2020-04-09     hqfang            first version
+ */
+
+#include "drv_gpio.h"
+
+#ifdef RT_USING_PIN
+
+static const struct pin_index pins[] =
+{
+
+    __GD32_PIN(0, A, 0),
+    __GD32_PIN(1, A, 1),
+    __GD32_PIN(2, A, 2),
+    __GD32_PIN(3, A, 3),
+    __GD32_PIN(4, A, 4),
+    __GD32_PIN(5, A, 5),
+    __GD32_PIN(6, A, 6),
+    __GD32_PIN(7, A, 7),
+    __GD32_PIN(8, A, 8),
+    __GD32_PIN(9, A, 9),
+    __GD32_PIN(10, A, 10),
+    __GD32_PIN(11, A, 11),
+    __GD32_PIN(12, A, 12),
+    __GD32_PIN(13, A, 13),
+    __GD32_PIN(14, A, 14),
+    __GD32_PIN(15, A, 15),
+
+    __GD32_PIN(16, B, 0),
+    __GD32_PIN(17, B, 1),
+    __GD32_PIN(18, B, 2),
+    __GD32_PIN(19, B, 3),
+    __GD32_PIN(20, B, 4),
+    __GD32_PIN(21, B, 5),
+    __GD32_PIN(22, B, 6),
+    __GD32_PIN(23, B, 7),
+    __GD32_PIN(24, B, 8),
+    __GD32_PIN(25, B, 9),
+    __GD32_PIN(26, B, 10),
+    __GD32_PIN(27, B, 11),
+    __GD32_PIN(28, B, 12),
+    __GD32_PIN(29, B, 13),
+    __GD32_PIN(30, B, 14),
+    __GD32_PIN(31, B, 15),
+
+    __GD32_PIN(32, C, 0),
+    __GD32_PIN(33, C, 1),
+    __GD32_PIN(34, C, 2),
+    __GD32_PIN(35, C, 3),
+    __GD32_PIN(36, C, 4),
+    __GD32_PIN(37, C, 5),
+    __GD32_PIN(38, C, 6),
+    __GD32_PIN(39, C, 7),
+    __GD32_PIN(40, C, 8),
+    __GD32_PIN(41, C, 9),
+    __GD32_PIN(42, C, 10),
+    __GD32_PIN(43, C, 11),
+    __GD32_PIN(44, C, 12),
+    __GD32_PIN(45, C, 13),
+    __GD32_PIN(46, C, 14),
+    __GD32_PIN(47, C, 15),
+
+    __GD32_PIN(48, D, 0),
+    __GD32_PIN(49, D, 1),
+    __GD32_PIN(50, D, 2),
+    __GD32_PIN(51, D, 3),
+    __GD32_PIN(52, D, 4),
+    __GD32_PIN(53, D, 5),
+    __GD32_PIN(54, D, 6),
+    __GD32_PIN(55, D, 7),
+    __GD32_PIN(56, D, 8),
+    __GD32_PIN(57, D, 9),
+    __GD32_PIN(58, D, 10),
+    __GD32_PIN(59, D, 11),
+    __GD32_PIN(60, D, 12),
+    __GD32_PIN(61, D, 13),
+    __GD32_PIN(62, D, 14),
+    __GD32_PIN(63, D, 15),
+
+    __GD32_PIN(64, E, 0),
+    __GD32_PIN(65, E, 1),
+    __GD32_PIN(66, E, 2),
+    __GD32_PIN(67, E, 3),
+    __GD32_PIN(68, E, 4),
+    __GD32_PIN(69, E, 5),
+    __GD32_PIN(70, E, 6),
+    __GD32_PIN(71, E, 7),
+    __GD32_PIN(72, E, 8),
+    __GD32_PIN(73, E, 9),
+    __GD32_PIN(74, E, 10),
+    __GD32_PIN(75, E, 11),
+    __GD32_PIN(76, E, 12),
+    __GD32_PIN(77, E, 13),
+    __GD32_PIN(78, E, 14),
+    __GD32_PIN(79, E, 15),
+};
+
+static const struct pin_irq_map pin_irq_map[] =
+{
+    {GPIO_PIN_0, EXTI0_IRQn},
+    {GPIO_PIN_1, EXTI1_IRQn},
+    {GPIO_PIN_2, EXTI2_IRQn},
+    {GPIO_PIN_3, EXTI3_IRQn},
+    {GPIO_PIN_4, EXTI4_IRQn},
+    {GPIO_PIN_5, EXTI5_9_IRQn},
+    {GPIO_PIN_6, EXTI5_9_IRQn},
+    {GPIO_PIN_7, EXTI5_9_IRQn},
+    {GPIO_PIN_8, EXTI5_9_IRQn},
+    {GPIO_PIN_9, EXTI5_9_IRQn},
+    {GPIO_PIN_10, EXTI10_15_IRQn},
+    {GPIO_PIN_11, EXTI10_15_IRQn},
+    {GPIO_PIN_12, EXTI10_15_IRQn},
+    {GPIO_PIN_13, EXTI10_15_IRQn},
+    {GPIO_PIN_14, EXTI10_15_IRQn},
+    {GPIO_PIN_15, EXTI10_15_IRQn},
+};
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+};
+static uint32_t pin_irq_enable_mask = 0;
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+static const struct pin_index *get_pin(uint8_t pin)
+{
+    const struct pin_index *index;
+
+    if (pin < ITEM_NUM(pins))
+    {
+        index = &pins[pin];
+        if (index->index == -1)
+            index = RT_NULL;
+    }
+    else
+    {
+        index = RT_NULL;
+    }
+
+    return index;
+};
+
+static void gd32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    const struct pin_index *index;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    gpio_bit_write(index->gpio, index->pin, (bit_status)value);
+}
+
+static int gd32_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    int value;
+    const struct pin_index *index;
+
+    value = PIN_LOW;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return value;
+    }
+
+    value = gpio_input_bit_get(index->gpio, index->pin);
+
+    return value;
+}
+
+static void gd32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    const struct pin_index *index;
+    rt_uint32_t pin_mode;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    pin_mode = GPIO_MODE_OUT_PP;
+
+    switch (mode)
+    {
+    case PIN_MODE_OUTPUT:
+        /* output setting */
+        pin_mode = GPIO_MODE_OUT_PP;
+        break;
+    case PIN_MODE_OUTPUT_OD:
+        /* output setting: od. */
+        pin_mode = GPIO_MODE_OUT_OD;
+        break;
+    case PIN_MODE_INPUT:
+        /* input setting: not pull. */
+        pin_mode = GPIO_MODE_IN_FLOATING;
+        break;
+    case PIN_MODE_INPUT_PULLUP:
+        /* input setting: pull up. */
+        pin_mode = GPIO_MODE_IPU;
+        break;
+    case PIN_MODE_INPUT_PULLDOWN:
+        /* input setting: pull down. */
+        pin_mode = GPIO_MODE_IPD;
+        break;
+    default:
+        break;
+    }
+
+    gpio_init(index->gpio, pin_mode, GPIO_OSPEED_50MHZ, index->pin);
+}
+
+rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
+{
+    int i;
+    for (i = 0; i < 32; i++)
+    {
+        if ((0x01 << i) == bit)
+        {
+            return i;
+        }
+    }
+    return -1;
+}
+
+rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
+{
+    rt_int32_t mapindex = bit2bitno(pinbit);
+    if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_NULL;
+    }
+    return &pin_irq_map[mapindex];
+};
+
+static rt_err_t gd32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                    rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    irqindex = bit2bitno(index->pin);
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == pin &&
+            pin_irq_hdr_tab[irqindex].hdr == hdr &&
+            pin_irq_hdr_tab[irqindex].mode == mode &&
+            pin_irq_hdr_tab[irqindex].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    if (pin_irq_hdr_tab[irqindex].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EBUSY;
+    }
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t gd32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    irqindex = bit2bitno(index->pin);
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    pin_irq_hdr_tab[irqindex].pin = -1;
+    pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+    pin_irq_hdr_tab[irqindex].mode = 0;
+    pin_irq_hdr_tab[irqindex].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t gd32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                                    rt_uint32_t enabled)
+{
+    const struct pin_index *index;
+    const struct pin_irq_map *irqmap;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    exti_trig_type_enum trigger_mode;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        irqindex = bit2bitno(index->pin);
+        if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+        {
+            return RT_ENOSYS;
+        }
+
+        level = rt_hw_interrupt_disable();
+
+        if (pin_irq_hdr_tab[irqindex].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_ENOSYS;
+        }
+
+        irqmap = &pin_irq_map[irqindex];
+
+        switch (pin_irq_hdr_tab[irqindex].mode)
+        {
+        case PIN_IRQ_MODE_RISING:
+            trigger_mode = EXTI_TRIG_RISING;
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            trigger_mode = EXTI_TRIG_FALLING;
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            trigger_mode = EXTI_TRIG_BOTH;
+            break;
+        default:
+            rt_hw_interrupt_enable(level);
+            return RT_EINVAL;
+        }
+        /* connect EXTI line to  GPIO pin */
+        gpio_exti_source_select(index->gpio, index->pin);
+
+        /* configure EXTI line */
+        exti_init((exti_line_enum)(index->pin), EXTI_INTERRUPT, trigger_mode);
+        exti_interrupt_flag_clear((exti_line_enum)(index->pin));
+
+        /* enable and set interrupt priority */
+        ECLIC_SetShvIRQ(irqmap->irqno, ECLIC_NON_VECTOR_INTERRUPT);
+        ECLIC_SetLevelIRQ(irqmap->irqno, 1);
+        ECLIC_EnableIRQ(irqmap->irqno);
+        pin_irq_enable_mask |= irqmap->pinbit;
+
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        irqmap = get_pin_irq_map(index->pin);
+        if (irqmap == RT_NULL)
+        {
+            return RT_EINVAL;
+        }
+        if ((irqmap->pinbit >= GPIO_PIN_5) && (irqmap->pinbit <= GPIO_PIN_9))
+        {
+            if (!(pin_irq_enable_mask & (GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | GPIO_PIN_8 | GPIO_PIN_9)))
+            {
+                ECLIC_DisableIRQ(irqmap->irqno);
+            }
+        }
+        else if ((irqmap->pinbit >= GPIO_PIN_10) && (irqmap->pinbit <= GPIO_PIN_15))
+        {
+            if (!(pin_irq_enable_mask & (GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15)))
+            {
+                ECLIC_DisableIRQ(irqmap->irqno);
+            }
+        }
+        else
+        {
+            ECLIC_DisableIRQ(irqmap->irqno);
+        }
+    }
+    else
+    {
+        return -RT_ENOSYS;
+    }
+
+    return RT_EOK;
+}
+const static struct rt_pin_ops _gd32_pin_ops =
+{
+    gd32_pin_mode,
+    gd32_pin_write,
+    gd32_pin_read,
+    gd32_pin_attach_irq,
+    gd32_pin_dettach_irq,
+    gd32_pin_irq_enable,
+};
+
+rt_inline void pin_irq_hdr(int irqno)
+{
+    if (pin_irq_hdr_tab[irqno].hdr)
+    {
+        pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+    }
+}
+
+void GD32_GPIO_EXTI_IRQHandler(rt_int8_t exti_line)
+{
+    if (RESET != exti_interrupt_flag_get((exti_line_enum)(1 << exti_line)))
+    {
+        pin_irq_hdr(exti_line);
+        exti_interrupt_flag_clear((exti_line_enum)(1 << exti_line));
+    }
+}
+
+void EXTI0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(0);
+    rt_interrupt_leave();
+}
+void EXTI1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(1);
+    rt_interrupt_leave();
+}
+void EXTI2_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(2);
+    rt_interrupt_leave();
+}
+void EXTI3_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(3);
+    rt_interrupt_leave();
+}
+void EXTI4_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(4);
+    rt_interrupt_leave();
+}
+void EXTI5_9_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(5);
+    GD32_GPIO_EXTI_IRQHandler(6);
+    GD32_GPIO_EXTI_IRQHandler(7);
+    GD32_GPIO_EXTI_IRQHandler(8);
+    GD32_GPIO_EXTI_IRQHandler(9);
+    rt_interrupt_leave();
+}
+void EXTI10_15_IRQHandler(void)
+{
+    rt_interrupt_enter();
+    GD32_GPIO_EXTI_IRQHandler(10);
+    GD32_GPIO_EXTI_IRQHandler(11);
+    GD32_GPIO_EXTI_IRQHandler(12);
+    GD32_GPIO_EXTI_IRQHandler(13);
+    GD32_GPIO_EXTI_IRQHandler(14);
+    GD32_GPIO_EXTI_IRQHandler(15);
+    rt_interrupt_leave();
+}
+
+int rt_hw_pin_init(void)
+{
+    rcu_periph_clock_enable(RCU_GPIOA);
+    rcu_periph_clock_enable(RCU_GPIOB);
+    rcu_periph_clock_enable(RCU_GPIOC);
+    rcu_periph_clock_enable(RCU_GPIOD);
+    rcu_periph_clock_enable(RCU_GPIOE);
+    rcu_periph_clock_enable(RCU_AF);
+    return rt_device_pin_register("pin", &_gd32_pin_ops, RT_NULL);
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+#endif /* RT_USING_PIN */
diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h
new file mode 100644
index 0000000000..93d24a8317
--- /dev/null
+++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_gpio.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2018-11-06     balanceTWK        first version
+ * 2020-04-15     hqfang            Modify for gd32vf103
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_config.h>
+
+#define __GD32_PORT(port)  GPIO##port
+
+#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIOA)/(0x0400UL) )) + PIN)
+
+#define __GD32_PIN(index, gpio, gpio_index)                                \
+    {                                                                      \
+        index, GPIO##gpio, GPIO_PIN_##gpio_index                           \
+    }
+
+#define __GD32_PIN_RESERVE                                                 \
+    {                                                                      \
+        -1, 0, 0                                                           \
+    }
+
+/* GD32 GPIO driver */
+struct pin_index
+{
+    int index;
+    uint32_t gpio;
+    uint32_t pin;
+};
+
+struct pin_irq_map
+{
+    rt_uint16_t pinbit;
+    IRQn_Type irqno;
+};
+
+int rt_hw_pin_init(void);
+
+#endif /* __DRV_GPIO_H__ */
+
diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c
new file mode 100644
index 0000000000..00fac33b3e
--- /dev/null
+++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.c
@@ -0,0 +1,347 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-07-23     tyustli      first version
+ * 2020-04-02     hqfang       modified for Nuclei
+ */
+
+#include <drv_usart.h>
+
+#ifdef RT_USING_SERIAL
+
+#if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) \
+    && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4)
+    #error "Please define at least one BSP_USING_UARTx"
+    /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+enum
+{
+#ifdef BSP_USING_UART0
+    GDUART0_INDEX,
+#endif
+#ifdef BSP_USING_UART1
+    GDUART1_INDEX,
+#endif
+#ifdef BSP_USING_UART2
+    GDUART2_INDEX,
+#endif
+#ifdef BSP_USING_UART3
+    GDUART3_INDEX,
+#endif
+#ifdef BSP_USING_UART4
+    GDUART4_INDEX,
+#endif
+};
+
+static struct gd32_uart_config uart_config[] =
+{
+#ifdef BSP_USING_UART0
+    {
+        "uart0",
+        USART0,
+        USART0_IRQn,
+    },
+#endif
+#ifdef BSP_USING_UART1
+    {
+        "uart1",
+        USART1,
+        USART1_IRQn,
+    },
+#endif
+#ifdef BSP_USING_UART2
+    {
+        "uart2",
+        USART2,
+        USART2_IRQn,
+    },
+#endif
+#ifdef BSP_USING_UART3
+    {
+        "uart3",
+        USART3,
+        USART3_IRQn,
+    },
+#endif
+#ifdef BSP_USING_UART4
+    {
+        "uart4",
+        UART4,
+        UART4_IRQn,
+    },
+#endif
+};
+
+static struct gd32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
+
+static rt_err_t gd32_configure(struct rt_serial_device *serial,
+                               struct serial_configure *cfg)
+{
+    struct gd32_uart *usart_obj;
+    struct gd32_uart_config *usart;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    usart_obj = (struct gd32_uart *) serial->parent.user_data;
+    usart = usart_obj->config;
+    RT_ASSERT(usart != RT_NULL);
+
+    usart_deinit(usart->uart_base);
+    usart_baudrate_set(usart->uart_base, cfg->baud_rate);
+
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_8:
+        usart_word_length_set(usart->uart_base, USART_WL_8BIT);
+        break;
+
+    case DATA_BITS_9:
+        usart_word_length_set(usart->uart_base, USART_WL_9BIT);
+        break;
+    default:
+        usart_word_length_set(usart->uart_base, USART_WL_8BIT);
+        break;
+    }
+
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_1:
+        usart_stop_bit_set(usart->uart_base, USART_STB_1BIT);
+        break;
+    case STOP_BITS_2:
+        usart_stop_bit_set(usart->uart_base, USART_STB_2BIT);
+        break;
+    default:
+        usart_stop_bit_set(usart->uart_base, USART_STB_1BIT);
+        break;
+    }
+
+    switch (cfg->parity)
+    {
+    case PARITY_NONE:
+        usart_parity_config(usart->uart_base, USART_PM_NONE);
+        break;
+    case PARITY_ODD:
+        usart_parity_config(usart->uart_base, USART_PM_ODD);
+        break;
+    case PARITY_EVEN:
+        usart_parity_config(usart->uart_base, USART_PM_EVEN);
+        break;
+    default:
+        usart_parity_config(usart->uart_base, USART_PM_NONE);
+        break;
+    }
+    usart_hardware_flow_rts_config(usart->uart_base, USART_RTS_DISABLE);
+    usart_hardware_flow_cts_config(usart->uart_base, USART_RTS_DISABLE);
+    usart_receive_config(usart->uart_base, USART_RECEIVE_ENABLE);
+    usart_transmit_config(usart->uart_base, USART_TRANSMIT_ENABLE);
+    usart_enable(usart->uart_base);
+
+    return RT_EOK;
+}
+
+static rt_err_t gd32_control(struct rt_serial_device *serial, int cmd,
+                             void *arg)
+{
+    struct gd32_uart *usart_obj;
+    struct gd32_uart_config *usart;
+
+    RT_ASSERT(serial != RT_NULL);
+    usart_obj = (struct gd32_uart *) serial->parent.user_data;
+    usart = usart_obj->config;
+    RT_ASSERT(usart != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        ECLIC_DisableIRQ(usart->irqn);
+        usart_interrupt_disable(usart->uart_base, USART_INT_RBNE);
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        ECLIC_EnableIRQ(usart->irqn);
+        /* enable USART0 receive interrupt */
+        usart_interrupt_enable(usart->uart_base, USART_INT_RBNE);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int gd32_putc(struct rt_serial_device *serial, char ch)
+{
+    struct gd32_uart *usart_obj;
+    struct gd32_uart_config *usart;
+
+    RT_ASSERT(serial != RT_NULL);
+    usart_obj = (struct gd32_uart *) serial->parent.user_data;
+    usart = usart_obj->config;
+    RT_ASSERT(usart != RT_NULL);
+
+    usart_data_transmit(usart->uart_base, (uint8_t) ch);
+    while (usart_flag_get(usart->uart_base, USART_FLAG_TBE) == RESET);
+
+    return 1;
+}
+
+static int gd32_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct gd32_uart *usart_obj;
+    struct gd32_uart_config *usart;
+
+    RT_ASSERT(serial != RT_NULL);
+    usart_obj = (struct gd32_uart *) serial->parent.user_data;
+    usart = usart_obj->config;
+    RT_ASSERT(usart != RT_NULL);
+
+    ch = -1;
+    if (RESET != usart_flag_get(usart->uart_base, USART_FLAG_RBNE))
+    {
+        ch = usart_data_receive(usart->uart_base) & 0xff;
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops gd32_uart_ops = { gd32_configure, gd32_control,
+           gd32_putc, gd32_getc,
+           RT_NULL
+};
+
+static void usart_isr(struct rt_serial_device *serial)
+{
+    struct gd32_uart *usart_obj;
+    struct gd32_uart_config *usart;
+
+    RT_ASSERT(serial != RT_NULL);
+    usart_obj = (struct gd32_uart *) serial->parent.user_data;
+    usart = usart_obj->config;
+    RT_ASSERT(usart != RT_NULL);
+
+    if ((usart_interrupt_flag_get(usart->uart_base, USART_INT_FLAG_RBNE)
+            != RESET)
+            && (RESET != usart_flag_get(usart->uart_base, USART_FLAG_RBNE)))
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+        usart_interrupt_flag_clear(usart->uart_base, USART_INT_FLAG_RBNE);
+        usart_flag_clear(usart->uart_base, USART_FLAG_RBNE);
+    }
+    else
+    {
+        if (usart_flag_get(usart->uart_base, USART_FLAG_CTSF) != RESET)
+        {
+            usart_flag_clear(usart->uart_base, USART_FLAG_CTSF);
+        }
+
+        if (usart_flag_get(usart->uart_base, USART_FLAG_LBDF) != RESET)
+        {
+            usart_flag_clear(usart->uart_base, USART_FLAG_LBDF);
+        }
+
+        if (usart_flag_get(usart->uart_base, USART_FLAG_TC) != RESET)
+        {
+            usart_flag_clear(usart->uart_base, USART_FLAG_TC);
+        }
+    }
+}
+
+#ifdef BSP_USING_UART0
+
+void USART0_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    usart_isr(&uart_obj[GDUART0_INDEX].serial);
+
+    rt_interrupt_leave();
+}
+
+#endif
+
+#ifdef BSP_USING_UART1
+
+void USART1_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    usart_isr(&uart_obj[GDUART1_INDEX].serial);
+
+    rt_interrupt_leave();
+}
+
+#endif
+
+#ifdef BSP_USING_UART2
+
+void USART2_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    usart_isr(&uart_obj[GDUART2_INDEX].serial);
+
+    rt_interrupt_leave();
+}
+
+#endif
+
+#ifdef BSP_USING_UART3
+
+void UART3_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    usart_isr(&uart_obj[GDUART3_INDEX].serial);
+
+    rt_interrupt_leave();
+}
+
+#endif
+
+#ifdef BSP_USING_UART4
+
+void UART4_IRQHandler(void)
+{
+    rt_interrupt_enter();
+
+    usart_isr(&uart_obj[GDUART4_INDEX].serial);
+
+    rt_interrupt_leave();
+}
+
+#endif
+
+int rt_hw_usart_init(void)
+{
+    rt_size_t obj_num;
+    int index;
+
+    obj_num = sizeof(uart_obj) / sizeof(struct gd32_uart);
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    rt_err_t result = 0;
+
+    for (index = 0; index < obj_num; index++)
+    {
+        /* init UART object */
+        uart_obj[index].config = &uart_config[index];
+        uart_obj[index].serial.ops = &gd32_uart_ops;
+        uart_obj[index].serial.config = config;
+
+        /* register UART device */
+        result = rt_hw_serial_register(&uart_obj[index].serial,
+                                       uart_obj[index].config->name,
+                                       RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX
+                                       | RT_DEVICE_FLAG_INT_TX, &uart_obj[index]);
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    return result;
+}
+
+#endif /* RT_USING_SERIAL */
+
+/******************** end of file *******************/
diff --git a/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h
new file mode 100644
index 0000000000..176720c4a2
--- /dev/null
+++ b/bsp/nuclei/libraries/gd32vf103/HAL_Drivers/drv_usart.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-15     hqfang       first version
+ */
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <drv_config.h>
+
+/* gd32 config class */
+struct gd32_uart_config
+{
+    const char *name;
+    uint32_t uart_base;
+    IRQn_Type irqn;
+};
+
+/* gd32 uart dirver class */
+struct gd32_uart
+{
+    struct gd32_uart_config *config;
+    struct rt_serial_device serial;
+};
+
+int rt_hw_usart_init(void);
+
+#endif /* __DRV_USART_H__ */
+
+/******************* end of file *******************/
diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript
index 640e46a4fb..024cc5ba44 100644
--- a/libcpu/risc-v/SConscript
+++ b/libcpu/risc-v/SConscript
@@ -10,7 +10,8 @@ group = []
 list  = os.listdir(cwd)
 
 # add common code files
-group = group + SConscript(os.path.join('common', 'SConscript'))
+if rtconfig.CPU != "nuclei":
+    group = group + SConscript(os.path.join('common', 'SConscript'))
 
 # cpu porting code files
 group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
diff --git a/libcpu/risc-v/nuclei/SConscript b/libcpu/risc-v/nuclei/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/risc-v/nuclei/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/risc-v/nuclei/context_gcc.S b/libcpu/risc-v/nuclei/context_gcc.S
new file mode 100644
index 0000000000..fda453940d
--- /dev/null
+++ b/libcpu/risc-v/nuclei/context_gcc.S
@@ -0,0 +1,188 @@
+/*
+ * Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/03/26     Huaqi        First Nuclei RISC-V porting implementation
+ */
+
+#include "riscv_encoding.h"
+
+#ifndef __riscv_32e
+#define RT_SAVED_REGNUM         30
+#else
+#define RT_SAVED_REGNUM         14
+#endif
+
+#define RT_CONTEXT_SIZE         (RT_SAVED_REGNUM * REGBYTES)
+
+    .extern rt_interrupt_from_thread
+    .extern rt_interrupt_to_thread
+
+
+.section    .text
+
+
+/*
+ * void rt_hw_context_switch_to(rt_ubase_t to);
+ * a0 --> to_thread
+ */
+    .globl rt_hw_context_switch_to
+
+/* Start the first task.  This also clears the bit that indicates the FPU is
+	in use in case the FPU was used before the scheduler was started - which
+	would otherwise result in the unnecessary leaving of space in the stack
+	for lazy saving of FPU registers. */
+.align 3
+rt_hw_context_switch_to:
+    /* Setup Interrupt Stack using
+       The stack that was used by main()
+       before the scheduler is started is
+       no longer required after the scheduler is started.
+       Interrupt stack pointer is stored in CSR_MSCRATCH */
+    la t0, _sp
+    csrw CSR_MSCRATCH, t0
+    LOAD sp, 0x0(a0)                /* Read sp from first TCB member(a0) */
+
+    /* Pop PC from stack and set MEPC */
+    LOAD t0,  0  * REGBYTES(sp)
+    csrw CSR_MEPC, t0
+    /* Pop mstatus from stack and set it */
+    LOAD t0,  (RT_SAVED_REGNUM - 1)  * REGBYTES(sp)
+    csrw CSR_MSTATUS, t0
+    /* Interrupt still disable here */
+    /* Restore Registers from Stack */
+    LOAD x1,  1  * REGBYTES(sp)    /* RA */
+    LOAD x5,  2  * REGBYTES(sp)
+    LOAD x6,  3  * REGBYTES(sp)
+    LOAD x7,  4  * REGBYTES(sp)
+    LOAD x8,  5  * REGBYTES(sp)
+    LOAD x9,  6  * REGBYTES(sp)
+    LOAD x10, 7  * REGBYTES(sp)
+    LOAD x11, 8  * REGBYTES(sp)
+    LOAD x12, 9  * REGBYTES(sp)
+    LOAD x13, 10 * REGBYTES(sp)
+    LOAD x14, 11 * REGBYTES(sp)
+    LOAD x15, 12 * REGBYTES(sp)
+#ifndef __riscv_32e
+    LOAD x16, 13 * REGBYTES(sp)
+    LOAD x17, 14 * REGBYTES(sp)
+    LOAD x18, 15 * REGBYTES(sp)
+    LOAD x19, 16 * REGBYTES(sp)
+    LOAD x20, 17 * REGBYTES(sp)
+    LOAD x21, 18 * REGBYTES(sp)
+    LOAD x22, 19 * REGBYTES(sp)
+    LOAD x23, 20 * REGBYTES(sp)
+    LOAD x24, 21 * REGBYTES(sp)
+    LOAD x25, 22 * REGBYTES(sp)
+    LOAD x26, 23 * REGBYTES(sp)
+    LOAD x27, 24 * REGBYTES(sp)
+    LOAD x28, 25 * REGBYTES(sp)
+    LOAD x29, 26 * REGBYTES(sp)
+    LOAD x30, 27 * REGBYTES(sp)
+    LOAD x31, 28 * REGBYTES(sp)
+#endif
+
+    addi sp, sp, RT_CONTEXT_SIZE
+
+    mret
+
+.align 2
+.global eclic_msip_handler
+eclic_msip_handler:
+    addi sp, sp, -RT_CONTEXT_SIZE
+    STORE x1,  1  * REGBYTES(sp)    /* RA */
+    STORE x5,  2  * REGBYTES(sp)
+    STORE x6,  3  * REGBYTES(sp)
+    STORE x7,  4  * REGBYTES(sp)
+    STORE x8,  5  * REGBYTES(sp)
+    STORE x9,  6  * REGBYTES(sp)
+    STORE x10, 7  * REGBYTES(sp)
+    STORE x11, 8  * REGBYTES(sp)
+    STORE x12, 9  * REGBYTES(sp)
+    STORE x13, 10 * REGBYTES(sp)
+    STORE x14, 11 * REGBYTES(sp)
+    STORE x15, 12 * REGBYTES(sp)
+#ifndef __riscv_32e
+    STORE x16, 13 * REGBYTES(sp)
+    STORE x17, 14 * REGBYTES(sp)
+    STORE x18, 15 * REGBYTES(sp)
+    STORE x19, 16 * REGBYTES(sp)
+    STORE x20, 17 * REGBYTES(sp)
+    STORE x21, 18 * REGBYTES(sp)
+    STORE x22, 19 * REGBYTES(sp)
+    STORE x23, 20 * REGBYTES(sp)
+    STORE x24, 21 * REGBYTES(sp)
+    STORE x25, 22 * REGBYTES(sp)
+    STORE x26, 23 * REGBYTES(sp)
+    STORE x27, 24 * REGBYTES(sp)
+    STORE x28, 25 * REGBYTES(sp)
+    STORE x29, 26 * REGBYTES(sp)
+    STORE x30, 27 * REGBYTES(sp)
+    STORE x31, 28 * REGBYTES(sp)
+#endif
+    /* Push mstatus to stack */
+    csrr t0, CSR_MSTATUS
+    STORE t0,  (RT_SAVED_REGNUM - 1)  * REGBYTES(sp)
+
+    /* Push additional registers */
+
+    /* Store sp to task stack */
+    LOAD t0, rt_interrupt_from_thread
+    STORE sp, 0(t0)
+
+    csrr t0, CSR_MEPC
+    STORE t0, 0(sp)
+
+    jal rt_hw_taskswitch
+
+    /* Switch task context */
+    LOAD t0, rt_interrupt_to_thread
+    LOAD sp, 0x0(t0)
+
+    /* Pop PC from stack and set MEPC */
+    LOAD t0,  0  * REGBYTES(sp)
+    csrw CSR_MEPC, t0
+
+    /* Pop additional registers */
+
+    /* Pop mstatus from stack and set it */
+    LOAD t0,  (RT_SAVED_REGNUM - 1)  * REGBYTES(sp)
+    csrw CSR_MSTATUS, t0
+    /* Interrupt still disable here */
+    /* Restore Registers from Stack */
+    LOAD x1,  1  * REGBYTES(sp)    /* RA */
+    LOAD x5,  2  * REGBYTES(sp)
+    LOAD x6,  3  * REGBYTES(sp)
+    LOAD x7,  4  * REGBYTES(sp)
+    LOAD x8,  5  * REGBYTES(sp)
+    LOAD x9,  6  * REGBYTES(sp)
+    LOAD x10, 7  * REGBYTES(sp)
+    LOAD x11, 8  * REGBYTES(sp)
+    LOAD x12, 9  * REGBYTES(sp)
+    LOAD x13, 10 * REGBYTES(sp)
+    LOAD x14, 11 * REGBYTES(sp)
+    LOAD x15, 12 * REGBYTES(sp)
+#ifndef __riscv_32e
+    LOAD x16, 13 * REGBYTES(sp)
+    LOAD x17, 14 * REGBYTES(sp)
+    LOAD x18, 15 * REGBYTES(sp)
+    LOAD x19, 16 * REGBYTES(sp)
+    LOAD x20, 17 * REGBYTES(sp)
+    LOAD x21, 18 * REGBYTES(sp)
+    LOAD x22, 19 * REGBYTES(sp)
+    LOAD x23, 20 * REGBYTES(sp)
+    LOAD x24, 21 * REGBYTES(sp)
+    LOAD x25, 22 * REGBYTES(sp)
+    LOAD x26, 23 * REGBYTES(sp)
+    LOAD x27, 24 * REGBYTES(sp)
+    LOAD x28, 25 * REGBYTES(sp)
+    LOAD x29, 26 * REGBYTES(sp)
+    LOAD x30, 27 * REGBYTES(sp)
+    LOAD x31, 28 * REGBYTES(sp)
+#endif
+
+    addi sp, sp, RT_CONTEXT_SIZE
+    mret
diff --git a/libcpu/risc-v/nuclei/cpuport.c b/libcpu/risc-v/nuclei/cpuport.c
new file mode 100644
index 0000000000..fad9afdf4c
--- /dev/null
+++ b/libcpu/risc-v/nuclei/cpuport.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/03/26     Huaqi        Nuclei RISC-V Core porting code.
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include "cpuport.h"
+
+#define SYSTICK_TICK_CONST                      (SOC_TIMER_FREQ / RT_TICK_PER_SECOND)
+
+/* Interrupt level for kernel systimer interrupt and software timer interrupt */
+#define RT_KERNEL_INTERRUPT_LEVEL               1
+
+/* Initial CSR MSTATUS value when thread created */
+#define RT_INITIAL_MSTATUS                      (MSTATUS_MPP | MSTATUS_MPIE | MSTATUS_FS_INITIAL)
+
+/**
+ * @brief from thread used interrupt context switch
+ * 
+ */
+volatile rt_ubase_t  rt_interrupt_from_thread = 0;
+/**
+ * @brief to thread used interrupt context switch
+ * 
+ */
+volatile rt_ubase_t  rt_interrupt_to_thread   = 0;
+/**
+ * @brief flag to indicate context switch in interrupt or not
+ * 
+ */
+volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0;
+
+/**
+ * @brief thread stack frame of saved context
+ * 
+ */
+struct rt_hw_stack_frame
+{
+    rt_ubase_t epc;        /*!< epc - epc    - program counter                     */
+    rt_ubase_t ra;         /*!< x1  - ra     - return address for jumps            */
+    rt_ubase_t t0;         /*!< x5  - t0     - temporary register 0                */
+    rt_ubase_t t1;         /*!< x6  - t1     - temporary register 1                */
+    rt_ubase_t t2;         /*!< x7  - t2     - temporary register 2                */
+    rt_ubase_t s0_fp;      /*!< x8  - s0/fp  - saved register 0 or frame pointer   */
+    rt_ubase_t s1;         /*!< x9  - s1     - saved register 1                    */
+    rt_ubase_t a0;         /*!< x10 - a0     - return value or function argument 0 */
+    rt_ubase_t a1;         /*!< x11 - a1     - return value or function argument 1 */
+    rt_ubase_t a2;         /*!< x12 - a2     - function argument 2                 */
+    rt_ubase_t a3;         /*!< x13 - a3     - function argument 3                 */
+    rt_ubase_t a4;         /*!< x14 - a4     - function argument 4                 */
+    rt_ubase_t a5;         /*!< x15 - a5     - function argument 5                 */
+#ifndef __riscv_32e
+    rt_ubase_t a6;         /*!< x16 - a6     - function argument 6                 */
+    rt_ubase_t a7;         /*!< x17 - s7     - function argument 7                 */
+    rt_ubase_t s2;         /*!< x18 - s2     - saved register 2                    */
+    rt_ubase_t s3;         /*!< x19 - s3     - saved register 3                    */
+    rt_ubase_t s4;         /*!< x20 - s4     - saved register 4                    */
+    rt_ubase_t s5;         /*!< x21 - s5     - saved register 5                    */
+    rt_ubase_t s6;         /*!< x22 - s6     - saved register 6                    */
+    rt_ubase_t s7;         /*!< x23 - s7     - saved register 7                    */
+    rt_ubase_t s8;         /*!< x24 - s8     - saved register 8                    */
+    rt_ubase_t s9;         /*!< x25 - s9     - saved register 9                    */
+    rt_ubase_t s10;        /*!< x26 - s10    - saved register 10                   */
+    rt_ubase_t s11;        /*!< x27 - s11    - saved register 11                   */
+    rt_ubase_t t3;         /*!< x28 - t3     - temporary register 3                */
+    rt_ubase_t t4;         /*!< x29 - t4     - temporary register 4                */
+    rt_ubase_t t5;         /*!< x30 - t5     - temporary register 5                */
+    rt_ubase_t t6;         /*!< x31 - t6     - temporary register 6                */
+#endif
+    rt_ubase_t mstatus;    /*!<              - machine status register             */
+};
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void       *tentry,
+                             void       *parameter,
+                             rt_uint8_t *stack_addr,
+                             void       *texit)
+{
+    struct rt_hw_stack_frame *frame;
+    rt_uint8_t         *stk;
+    int                i;
+
+    stk  = stack_addr + sizeof(rt_ubase_t);
+    stk  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
+    stk -= sizeof(struct rt_hw_stack_frame);
+
+    frame = (struct rt_hw_stack_frame *)stk;
+
+    for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
+    {
+        ((rt_ubase_t *)frame)[i] = 0xdeadbeef;
+    }
+
+    frame->ra      = (rt_ubase_t)texit;
+    frame->a0      = (rt_ubase_t)parameter;
+    frame->epc     = (rt_ubase_t)tentry;
+
+    frame->mstatus = RT_INITIAL_MSTATUS;
+
+    return stk;
+}
+
+/**
+ * @brief Do rt-thread context switch in interrupt context
+ * 
+ * @param from thread sp of from thread
+ * @param to thread sp of to thread
+ */
+void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
+{
+    if (rt_thread_switch_interrupt_flag == 0)
+        rt_interrupt_from_thread = from;
+
+    rt_interrupt_to_thread = to;
+    rt_thread_switch_interrupt_flag = 1;
+    RT_YIELD();
+}
+
+/**
+ * @brief Do rt-thread context switch in task context
+ * 
+ * @param from thread sp of from thread
+ * @param to thread sp of to thread
+ */
+void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to)
+{
+    rt_interrupt_from_thread = from;
+    rt_interrupt_to_thread = to;
+    RT_YIELD();
+}
+
+/**
+ * @brief shutdown CPU
+ * 
+ */
+void rt_hw_cpu_shutdown()
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}
+
+/**
+ * @brief Do extra task switch code
+ * 
+ * @details
+ * 
+ * - Clear software timer interrupt request flag
+ * - clear rt_thread_switch_interrupt_flag to 0
+ */
+void rt_hw_taskswitch(void)
+{
+    /* Clear Software IRQ, A MUST */
+    SysTimer_ClearSWIRQ();
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+/**
+ * @brief Setup systimer and software timer interrupt
+ * 
+ * @details 
+ * 
+ * - Set Systimer interrupt as NON-VECTOR interrupt with lowest interrupt level
+ * - Set software timer interrupt as VECTOR interrupt with lowest interrupt level
+ * - Enable these two interrupts
+ */
+void rt_hw_ticksetup(void)
+{
+    uint64_t ticks = SYSTICK_TICK_CONST;
+
+    /* Make SWI and SysTick the lowest priority interrupts. */
+    /* Stop and clear the SysTimer. SysTimer as Non-Vector Interrupt */
+    SysTick_Config(ticks);
+    ECLIC_DisableIRQ(SysTimer_IRQn);
+    ECLIC_SetLevelIRQ(SysTimer_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
+    ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT);
+    ECLIC_EnableIRQ(SysTimer_IRQn);
+
+    /* Set SWI interrupt level to lowest level/priority, SysTimerSW as Vector Interrupt */
+    ECLIC_SetShvIRQ(SysTimerSW_IRQn, ECLIC_VECTOR_INTERRUPT);
+    ECLIC_SetLevelIRQ(SysTimerSW_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
+    ECLIC_EnableIRQ(SysTimerSW_IRQn);
+}
+
+/**
+ * systimer interrupt handler eclic_mtip_handler
+ * is hard coded in startup_<Device>.S
+ * We define SysTick_Handler as eclic_mtip_handler
+ * for easy understanding
+ */
+#define SysTick_Handler     eclic_mtip_handler
+
+/**
+ * @brief This is the timer interrupt service routine.
+ * 
+ */
+void SysTick_Handler(void)
+{
+    /* Reload systimer */
+    SysTick_Reload(SYSTICK_TICK_CONST);
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    /* tick increase */
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief Disable cpu interrupt
+ * 
+ * @details
+ * 
+ * - Disable cpu interrupt by clear MIE bit in MSTATUS
+ * - Return the previous value in MSTATUS before clear MIE bit
+ * 
+ * @return the previous value in MSTATUS before clear MIE bit 
+ */
+rt_base_t rt_hw_interrupt_disable(void)
+{
+    return __RV_CSR_READ_CLEAR(CSR_MSTATUS, MSTATUS_MIE);
+}
+
+/**
+ * @brief Restore previous saved interrupt status
+ * 
+ * @param level previous saved MSTATUS value
+ */
+void rt_hw_interrupt_enable(rt_base_t level)
+{
+    __RV_CSR_WRITE(CSR_MSTATUS, level);
+}
diff --git a/libcpu/risc-v/nuclei/cpuport.h b/libcpu/risc-v/nuclei/cpuport.h
new file mode 100644
index 0000000000..3736f0078a
--- /dev/null
+++ b/libcpu/risc-v/nuclei/cpuport.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/03/26     hqfang       Nuclei RISC-V Core porting code.
+ */
+
+#ifndef __CPUPORT_H__
+#define __CPUPORT_H__
+
+#include <rtconfig.h>
+#include <nuclei_sdk_soc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Scheduler utilities. */
+#define RT_YIELD()                                                              \
+{                                                                               \
+    /* Set a software interrupt(SWI) request to request a context switch. */    \
+    SysTimer_SetSWIRQ();                                                        \
+    /* Barriers are normally not required but do ensure the code is completely  \
+    within the specified behaviour for the architecture. */                     \
+    __RWMB();                                                                   \
+    __FENCE_I();                                                                \
+}
+
+extern void rt_hw_ticksetup(void);
+extern void rt_hw_taskswitch(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/libcpu/risc-v/nuclei/interrupt_gcc.S b/libcpu/risc-v/nuclei/interrupt_gcc.S
new file mode 100644
index 0000000000..02a3e3e760
--- /dev/null
+++ b/libcpu/risc-v/nuclei/interrupt_gcc.S
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020/03/26     hqfang       First Nuclei RISC-V porting implementation
+ */
+
+#include "riscv_encoding.h"
+
+.section    .text.entry
+.align 8
+
+/**
+ * \brief  Global interrupt disabled
+ * \details
+ *  This function disable global interrupt.
+ * \remarks
+ *  - All the interrupt requests will be ignored by CPU.
+ */
+.macro DISABLE_MIE
+    csrc CSR_MSTATUS, MSTATUS_MIE
+.endm
+
+/**
+ * \brief  Macro for context save
+ * \details
+ * This macro save ABI defined caller saved registers in the stack.
+ * \remarks
+ * - This Macro could use to save context when you enter to interrupt
+ * or exception
+*/
+/* Save caller registers */
+.macro SAVE_CONTEXT
+    csrrw sp, CSR_MSCRATCHCSWL, sp
+    /* Allocate stack space for context saving */
+#ifndef __riscv_32e
+    addi sp, sp, -20*REGBYTES
+#else
+    addi sp, sp, -14*REGBYTES
+#endif /* __riscv_32e */
+
+    STORE x1, 0*REGBYTES(sp)
+    STORE x4, 1*REGBYTES(sp)
+    STORE x5, 2*REGBYTES(sp)
+    STORE x6, 3*REGBYTES(sp)
+    STORE x7, 4*REGBYTES(sp)
+    STORE x10, 5*REGBYTES(sp)
+    STORE x11, 6*REGBYTES(sp)
+    STORE x12, 7*REGBYTES(sp)
+    STORE x13, 8*REGBYTES(sp)
+    STORE x14, 9*REGBYTES(sp)
+    STORE x15, 10*REGBYTES(sp)
+#ifndef __riscv_32e
+    STORE x16, 14*REGBYTES(sp)
+    STORE x17, 15*REGBYTES(sp)
+    STORE x28, 16*REGBYTES(sp)
+    STORE x29, 17*REGBYTES(sp)
+    STORE x30, 18*REGBYTES(sp)
+    STORE x31, 19*REGBYTES(sp)
+#endif /* __riscv_32e */
+.endm
+
+/**
+ * \brief  Macro for restore caller registers
+ * \details
+ * This macro restore ABI defined caller saved registers from stack.
+ * \remarks
+ * - You could use this macro to restore context before you want return
+ * from interrupt or exeception
+ */
+/* Restore caller registers */
+.macro RESTORE_CONTEXT
+    LOAD x1, 0*REGBYTES(sp)
+    LOAD x4, 1*REGBYTES(sp)
+    LOAD x5, 2*REGBYTES(sp)
+    LOAD x6, 3*REGBYTES(sp)
+    LOAD x7, 4*REGBYTES(sp)
+    LOAD x10, 5*REGBYTES(sp)
+    LOAD x11, 6*REGBYTES(sp)
+    LOAD x12, 7*REGBYTES(sp)
+    LOAD x13, 8*REGBYTES(sp)
+    LOAD x14, 9*REGBYTES(sp)
+    LOAD x15, 10*REGBYTES(sp)
+#ifndef __riscv_32e
+    LOAD x16, 14*REGBYTES(sp)
+    LOAD x17, 15*REGBYTES(sp)
+    LOAD x28, 16*REGBYTES(sp)
+    LOAD x29, 17*REGBYTES(sp)
+    LOAD x30, 18*REGBYTES(sp)
+    LOAD x31, 19*REGBYTES(sp)
+
+    /* De-allocate the stack space */
+    addi sp, sp, 20*REGBYTES
+#else
+    /* De-allocate the stack space */
+    addi sp, sp, 14*REGBYTES
+#endif /* __riscv_32e */
+    csrrw sp, CSR_MSCRATCHCSWL, sp
+.endm
+
+/**
+ * \brief  Macro for save necessary CSRs to stack
+ * \details
+ * This macro store MCAUSE, MEPC, MSUBM to stack.
+ */
+.macro SAVE_CSR_CONTEXT
+    /* Store CSR mcause to stack using pushmcause */
+    csrrwi  x0, CSR_PUSHMCAUSE, 11
+    /* Store CSR mepc to stack using pushmepc */
+    csrrwi  x0, CSR_PUSHMEPC, 12
+    /* Store CSR msub to stack using pushmsub */
+    csrrwi  x0, CSR_PUSHMSUBM, 13
+.endm
+
+/**
+ * \brief  Macro for restore necessary CSRs from stack
+ * \details
+ * This macro restore MSUBM, MEPC, MCAUSE from stack.
+ */
+.macro RESTORE_CSR_CONTEXT
+    LOAD x5,  13*REGBYTES(sp)
+    csrw CSR_MSUBM, x5
+    LOAD x5,  12*REGBYTES(sp)
+    csrw CSR_MEPC, x5
+    LOAD x5,  11*REGBYTES(sp)
+    csrw CSR_MCAUSE, x5
+.endm
+
+/**
+ * \brief  Exception/NMI Entry
+ * \details
+ * This function provide common entry functions for exception/nmi.
+ * \remarks
+ * This function provide a default exception/nmi entry.
+ * ABI defined caller save register and some CSR registers
+ * to be saved before enter interrupt handler and be restored before return.
+ */
+.section .text.trap
+/* In CLIC mode, the exeception entry must be 64bytes aligned */
+.align 6
+.global exc_entry
+exc_entry:
+    /* Save the caller saving registers (context) */
+    SAVE_CONTEXT
+    /* Save the necessary CSR registers */
+    SAVE_CSR_CONTEXT
+
+    /*
+     * Set the exception handler function arguments
+     * argument 1: mcause value
+     * argument 2: current stack point(SP) value
+     */
+    csrr a0, mcause
+    mv a1, sp
+    /*
+     * TODO: Call the exception handler function
+     * By default, the function template is provided in
+     * system_Device.c, you can adjust it as you want
+     */
+    call core_exception_handler
+
+    /* Restore the necessary CSR registers */
+    RESTORE_CSR_CONTEXT
+    /* Restore the caller saving registers (context) */
+    RESTORE_CONTEXT
+
+    /* Return to regular code */
+    mret
+
+/**
+ * \brief  Non-Vector Interrupt Entry
+ * \details
+ * This function provide common entry functions for handling
+ * non-vector interrupts
+ * \remarks
+ * This function provide a default non-vector interrupt entry.
+ * ABI defined caller save register and some CSR registers need
+ * to be saved before enter interrupt handler and be restored before return.
+ */
+.section      .text.irq
+/* In CLIC mode, the interrupt entry must be 4bytes aligned */
+.align 2
+.global irq_entry
+/* This label will be set to MTVT2 register */
+irq_entry:
+    /* Save the caller saving registers (context) */
+    SAVE_CONTEXT
+    /* Save the necessary CSR registers */
+    SAVE_CSR_CONTEXT
+
+    /* This special CSR read/write operation, which is actually
+     * claim the CLIC to find its pending highest ID, if the ID
+     * is not 0, then automatically enable the mstatus.MIE, and
+     * jump to its vector-entry-label, and update the link register
+     */
+    csrrw ra, CSR_JALMNXTI, ra
+
+    /* Critical section with interrupts disabled */
+    DISABLE_MIE
+
+    /* Restore the necessary CSR registers */
+    RESTORE_CSR_CONTEXT
+    /* Restore the caller saving registers (context) */
+    RESTORE_CONTEXT
+
+    /* Return to regular code */
+    mret
+
+/* Default Handler for Exceptions / Interrupts */
+.global default_intexc_handler
+Undef_Handler:
+default_intexc_handler:
+1:
+	j 1b
+
diff --git a/tools/mkdist.py b/tools/mkdist.py
index 7e4b9a8bbe..ec527d87e1 100644
--- a/tools/mkdist.py
+++ b/tools/mkdist.py
@@ -345,6 +345,13 @@ def MkDist(program, BSP_ROOT, RTT_ROOT, Env, rttide = None):
         bsp_copy_files(os.path.join(library_path, Env['bsp_lib_type']), os.path.join(library_dir, Env['bsp_lib_type']))
         shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig'))
 
+    # copy nuclei bsp libiary files
+    if os.path.basename(os.path.dirname(BSP_ROOT)) == 'nuclei':
+        print("=> copy nuclei bsp library")
+        library_path = os.path.join(os.path.dirname(BSP_ROOT), 'libraries')
+        library_dir  = os.path.join(dist_dir, 'libraries')
+        bsp_copy_files(os.path.join(library_path, Env['bsp_lib_type']), os.path.join(library_dir, Env['bsp_lib_type']))
+
     # do bsp special dist handle
     if 'dist_handle' in Env:
         print("=> start dist handle")
-- 
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