From 68ca9f07a60ad5cbe52b37b52299327b6246e7f7 Mon Sep 17 00:00:00 2001 From: guo Date: Fri, 16 Dec 2022 18:38:28 +0800 Subject: [rt-smart] 弱化 RT_USING_LWP，使用 RT_USING_SMART 作为宏配置 (#6740) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * [dfs] sync cromfs * [rt-smart]Weaken RT_USING_LWP, use RT_USING_SMART as macro configuration * [format] fix some format issue. --- libcpu/Kconfig | 13 +++++-------- libcpu/arm/cortex-a/backtrace.c | 4 ++-- libcpu/arm/cortex-a/cache.c | 2 +- libcpu/arm/cortex-a/context_gcc.S | 26 +++++++++++++------------- libcpu/arm/cortex-a/interrupt.c | 4 ++-- libcpu/arm/cortex-a/mmu.c | 6 +++--- libcpu/arm/cortex-a/mmu.h | 4 ++-- libcpu/arm/cortex-a/stack.c | 2 +- libcpu/arm/cortex-a/start_gcc.S | 28 ++++++++++++++-------------- libcpu/arm/cortex-a/trap.c | 10 +++++----- libcpu/arm/cortex-a/vector_gcc.S | 2 +- libcpu/mips/gs264/mmu.c | 16 ++++++++-------- libcpu/mips/gs264/mmu.h | 4 ++-- libcpu/risc-v/t-head/c906/cache.c | 2 +- libcpu/risc-v/t-head/c906/context_gcc.S | 4 ++-- libcpu/risc-v/t-head/c906/interrupt_gcc.S | 2 +- libcpu/risc-v/t-head/c906/trap.c | 6 +++--- libcpu/risc-v/virt64/context_gcc.S | 4 ++-- 18 files changed, 68 insertions(+), 71 deletions(-) (limited to 'libcpu') diff --git a/libcpu/Kconfig b/libcpu/Kconfig index 0114d62d42..0257f44190 100644 --- a/libcpu/Kconfig +++ b/libcpu/Kconfig @@ -79,28 +79,25 @@ config ARCH_ARM_MMU select ARCH_MM_MMU depends on ARCH_ARM -config RT_USING_USERSPACE - bool "Isolated user space" - default n - depends on ARCH_MM_MMU - +if RT_USING_SMART config KERNEL_VADDR_START hex "The virtural address of kernel start" default 0xc0000000 if ARCH_ARM default 0x80000000 if ARCH_RISCV - depends on RT_USING_USERSPACE + depends on ARCH_MM_MMU config PV_OFFSET hex "The offset of kernel physical address and virtural address" default 0xa0000000 if ARCH_ARM default 0x0 if ARCH_RISCV - depends on RT_USING_USERSPACE + depends on ARCH_MM_MMU config RT_IOREMAP_LATE bool "Support to create IO mapping in the kernel address space after system initlalization." default n depends on ARCH_ARM_CORTEX_A - depends on RT_USING_USERSPACE + depends on ARCH_MM_MMU +endif config ARCH_ARM_ARM9 bool diff --git a/libcpu/arm/cortex-a/backtrace.c b/libcpu/arm/cortex-a/backtrace.c index 4a5718bf9f..9837c734cc 100644 --- a/libcpu/arm/cortex-a/backtrace.c +++ b/libcpu/arm/cortex-a/backtrace.c @@ -27,7 +27,7 @@ #define DBG_LVL DBG_INFO #include -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART #include #include #include @@ -520,7 +520,7 @@ void rt_unwind(struct rt_hw_exp_stack *regs, unsigned int pc_adj) e_regs.ARM_sp = regs->sp; e_regs.ARM_lr = regs->lr; e_regs.ARM_pc = regs->pc - pc_adj; -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART if (!lwp_user_accessable((void *)e_regs.ARM_pc, sizeof (void *))) { e_regs.ARM_pc = regs->lr - sizeof(void *); diff --git a/libcpu/arm/cortex-a/cache.c b/libcpu/arm/cortex-a/cache.c index c243e8e358..2b609f2ff9 100644 --- a/libcpu/arm/cortex-a/cache.c +++ b/libcpu/arm/cortex-a/cache.c @@ -154,7 +154,7 @@ rt_base_t rt_hw_cpu_dcache_status(void) return 0; } -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART #define ICACHE (1<<0) #define DCACHE (1<<1) #define BCACHE (ICACHE|DCACHE) diff --git a/libcpu/arm/cortex-a/context_gcc.S b/libcpu/arm/cortex-a/context_gcc.S index 77ca0a7aa2..c4531dede5 100644 --- a/libcpu/arm/cortex-a/context_gcc.S +++ b/libcpu/arm/cortex-a/context_gcc.S @@ -45,12 +45,12 @@ rt_hw_context_switch_to: #ifdef RT_USING_SMP mov r0, r1 bl rt_cpus_lock_status_restore -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART bl rt_thread_self bl lwp_user_setting_restore #endif #else -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART bl rt_thread_self mov r4, r0 bl lwp_mmu_switch @@ -85,7 +85,7 @@ rt_hw_context_switch: stmfd sp!, {r4} @ push cpsr -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART stmfd sp, {r13, r14}^ @ push usr_sp usr_lr sub sp, #8 #endif @@ -108,12 +108,12 @@ rt_hw_context_switch: #ifdef RT_USING_SMP mov r0, r2 bl rt_cpus_lock_status_restore -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART bl rt_thread_self bl lwp_user_setting_restore #endif #else -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART bl rt_thread_self mov r4, r0 bl lwp_mmu_switch @@ -149,9 +149,9 @@ rt_hw_context_switch_interrupt: * r2 :addr of to_thread's sp * r3 :to_thread's tcb */ -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART push {r0 - r3, lr} -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART bl rt_thread_self bl lwp_user_setting_save #endif @@ -161,11 +161,11 @@ rt_hw_context_switch_interrupt: ldr sp, [r2] mov r0, r3 -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART mov r4, r0 #endif bl rt_cpus_lock_status_restore -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART mov r0, r4 bl lwp_user_setting_restore #endif @@ -177,7 +177,7 @@ rt_hw_context_switch_interrupt: * r2 :from_thread's tcb * r3 :to_thread's tcb */ -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART /* now to_thread(r3) not used */ ldr ip, =rt_thread_switch_interrupt_flag ldr r3, [ip] @@ -187,7 +187,7 @@ rt_hw_context_switch_interrupt: str r0, [r3] mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 str r3, [ip] -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART push {r1, lr} mov r0, r2 bl lwp_user_setting_save @@ -239,14 +239,14 @@ rt_hw_context_switch_exit: 1: #endif -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART ldmfd sp, {r13, r14}^ /* usr_sp, usr_lr */ add sp, #8 #endif ldmfd sp!, {r1} msr spsr_cxsf, r1 /* original mode */ -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART and r1, #0x1f cmp r1, #0x10 bne 1f diff --git a/libcpu/arm/cortex-a/interrupt.c b/libcpu/arm/cortex-a/interrupt.c index 6cf7362554..fb257cc2de 100644 --- a/libcpu/arm/cortex-a/interrupt.c +++ b/libcpu/arm/cortex-a/interrupt.c @@ -69,7 +69,7 @@ void rt_hw_interrupt_init(void) rt_memset(isr_table, 0x00, sizeof(isr_table)); /* initialize ARM GIC */ -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART gic_dist_base = (uint32_t)rt_hw_mmu_map(&mmu_info, 0, (void*)platform_get_gic_dist_base(), 0x2000, MMU_MAP_K_RW); gic_cpu_base = (uint32_t)rt_hw_mmu_map(&mmu_info, 0, (void*)platform_get_gic_cpu_base(), 0x1000, MMU_MAP_K_RW); #else @@ -99,7 +99,7 @@ void rt_hw_interrupt_init(void) rt_memset(isr_table, 0x00, sizeof(isr_table)); /* initialize ARM GIC */ -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART gic_dist_base = (uint32_t)rt_hw_mmu_map(&mmu_info, 0, (void*)platform_get_gic_dist_base(), 0x2000, MMU_MAP_K_RW); #else gic_dist_base = platform_get_gic_dist_base(); diff --git a/libcpu/arm/cortex-a/mmu.c b/libcpu/arm/cortex-a/mmu.c index 47f7676ace..19fd0f10d2 100644 --- a/libcpu/arm/cortex-a/mmu.c +++ b/libcpu/arm/cortex-a/mmu.c @@ -16,7 +16,7 @@ #include "cp15.h" #include "mmu.h" -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART #include #include "page.h" #endif @@ -24,7 +24,7 @@ /* level1 page table, each entry for 1MB memory. */ volatile unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); -#ifndef RT_USING_LWP +#ifndef RT_USING_SMART static rt_mutex_t mm_lock = RT_NULL; void rt_mm_lock(void) @@ -323,7 +323,7 @@ int rt_hw_mmu_ioremap_init(rt_mmu_info *mmu_info, void* v_address, size_t size) return 0; } -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART static size_t find_vaddr(rt_mmu_info *mmu_info, int pages) { size_t l1_off, l2_off; diff --git a/libcpu/arm/cortex-a/mmu.h b/libcpu/arm/cortex-a/mmu.h index 0bd80dd06c..923d10df4b 100644 --- a/libcpu/arm/cortex-a/mmu.h +++ b/libcpu/arm/cortex-a/mmu.h @@ -19,7 +19,7 @@ #define SHAREDEVICE (1<<2) /* shared device */ #define STRONGORDER (0<<2) /* strong ordered */ #define XN (1<<4) /* eXecute Never */ -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART #define AP_RW (1<<10) /* supervisor=RW, user=No */ #define AP_RO ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */ #else @@ -100,7 +100,7 @@ int rt_hw_mmu_map_init(rt_mmu_info *mmu_info, void* v_address, size_t size, size int rt_hw_mmu_ioremap_init(rt_mmu_info *mmu_info, void* v_address, size_t size); void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size); -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr); void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr); #else diff --git a/libcpu/arm/cortex-a/stack.c b/libcpu/arm/cortex-a/stack.c index 875794bade..ec2a51a8e8 100644 --- a/libcpu/arm/cortex-a/stack.c +++ b/libcpu/arm/cortex-a/stack.c @@ -56,7 +56,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, else *(--stk) = SVCMODE; /* arm mode */ -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART *(--stk) = 0; /* user lr */ *(--stk) = 0; /* user sp*/ #endif diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S index e77579ff21..865f005dc8 100644 --- a/libcpu/arm/cortex-a/start_gcc.S +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -22,7 +22,7 @@ .equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */ .equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */ -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART .data .align 14 init_mtbl: @@ -101,7 +101,7 @@ continue: dsb isb -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART ldr r5, =PV_OFFSET mov r7, #0x100000 @@ -179,7 +179,7 @@ bss_loop: ldr r1, [r1] bl rt_hw_init_mmu_table -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART ldr r0, =MMUTable /* vaddr */ add r0, r5 /* to paddr */ bl rt_hw_mmu_switch @@ -225,7 +225,7 @@ stack_setup: bx lr -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART .align 2 .global enable_mmu enable_mmu: @@ -331,7 +331,7 @@ vector_irq: mrs r1, spsr /* original mode */ stmfd r0!, {r1} -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART stmfd r0, {r13, r14}^ /* usr_sp, usr_lr */ sub r0, #8 #endif @@ -379,7 +379,7 @@ vector_irq: cmp r1, #1 beq rt_hw_context_switch_interrupt_do -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART ldmfd sp!, {r0-r12,lr} cps #Mode_SVC push {r0-r12} @@ -430,7 +430,7 @@ rt_hw_context_switch_interrupt_do: stmfd sp!, {r1-r4} /* push old task's r0-r3 */ stmfd sp!, {r0} /* push old task's cpsr */ -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART stmfd sp, {r13, r14}^ /*push usr_sp, usr_lr */ sub sp, #8 #endif @@ -457,7 +457,7 @@ rt_hw_context_switch_interrupt_do: ldr sp, [r6] /* get new task's stack pointer */ bl rt_thread_self -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART mov r4, r0 bl lwp_mmu_switch mov r0, r4 @@ -477,7 +477,7 @@ rt_hw_context_switch_interrupt_do: 1: #endif -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART ldmfd sp, {r13, r14}^ /*pop usr_sp, usr_lr */ add sp, #8 #endif @@ -485,7 +485,7 @@ rt_hw_context_switch_interrupt_do: ldmfd sp!, {r4} /* pop new task's cpsr to spsr */ msr spsr_cxsf, r4 -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART and r4, #0x1f cmp r4, #0x10 bne 1f @@ -543,7 +543,7 @@ vector_undef: .globl vector_pabt vector_pabt: push_svc_reg -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART /* cp Mode_ABT stack to SVC */ sub sp, sp, #17 * 4 /* Sizeof(struct rt_hw_exp_stack) */ mov lr, r0 @@ -571,7 +571,7 @@ vector_pabt: .globl vector_dabt vector_dabt: push_svc_reg -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART /* cp Mode_ABT stack to SVC */ sub sp, sp, #17 * 4 /* Sizeof(struct rt_hw_exp_stack) */ mov lr, r0 @@ -610,7 +610,7 @@ rt_hw_clz: .global rt_secondary_cpu_entry rt_secondary_cpu_entry: -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART ldr r5, =PV_OFFSET ldr lr, =after_enable_mmu_n @@ -641,7 +641,7 @@ after_enable_mmu_n: bl stack_setup /* initialize the mmu table and enable mmu */ -#ifndef RT_USING_USERSPACE +#ifndef RT_USING_SMART bl rt_hw_mmu_init #endif diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c index 82bb6f2f78..79897cd39c 100644 --- a/libcpu/arm/cortex-a/trap.c +++ b/libcpu/arm/cortex-a/trap.c @@ -19,7 +19,7 @@ extern long list_thread(void); #endif -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART #include #include @@ -70,7 +70,7 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs) rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); rt_kprintf("cpsr:0x%08x\n", regs->cpsr); -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART { uint32_t v; asm volatile ("MRC p15, 0, %0, c5, c0, 0":"=r"(v)); @@ -128,7 +128,7 @@ void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) } } #endif -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART check_user_fault(regs, 4, "User undefined instruction"); #endif rt_unwind(regs, 4); @@ -169,7 +169,7 @@ void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) */ void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) { -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART if (dbg_check_event(regs, 4)) { return; @@ -195,7 +195,7 @@ void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) */ void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) { -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART if (dbg_check_event(regs, 8)) { return; diff --git a/libcpu/arm/cortex-a/vector_gcc.S b/libcpu/arm/cortex-a/vector_gcc.S index eb872db71f..8f72feb352 100644 --- a/libcpu/arm/cortex-a/vector_gcc.S +++ b/libcpu/arm/cortex-a/vector_gcc.S @@ -15,7 +15,7 @@ .globl system_vectors system_vectors: -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART b _reset #else ldr pc, _vector_reset diff --git a/libcpu/mips/gs264/mmu.c b/libcpu/mips/gs264/mmu.c index 1dcf0a445d..6b07c70549 100644 --- a/libcpu/mips/gs264/mmu.c +++ b/libcpu/mips/gs264/mmu.c @@ -319,7 +319,7 @@ static size_t find_vaddr(rt_mmu_info *mmu_info, int pages) return 0; } -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART static int check_vaddr(rt_mmu_info *mmu_info, void *va, int pages) { size_t loop_va = (size_t)va & ~ARCH_PAGE_MASK; @@ -398,7 +398,7 @@ static void __rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t npages (*ref_cnt)--; if (!*ref_cnt) { -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART rt_pages_free(mmu_l2, 0); #else rt_free_align(mmu_l2); @@ -438,7 +438,7 @@ static int __rt_hw_mmu_map(rt_mmu_info *mmu_info, void* v_addr, void* p_addr, si } else { -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART mmu_l2 = (size_t*)rt_pages_alloc(0); #else mmu_l2 = (size_t*)rt_malloc_align(ARCH_PAGE_TBL_SIZE * 2, ARCH_PAGE_TBL_SIZE); @@ -480,7 +480,7 @@ static void rt_hw_cpu_tlb_invalidate(void) mmu_clear_itlb(); } -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART void *_rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr) { size_t pa_s, pa_e; @@ -551,7 +551,7 @@ void *_rt_hw_mmu_map(rt_mmu_info *mmu_info, void* p_addr, size_t size, size_t at } #endif -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART static int __rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void* v_addr, size_t npages, size_t attr) { size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK; @@ -695,7 +695,7 @@ void *rt_hw_kernel_phys_to_virt(void *p_addr, size_t size) { void *v_addr = 0; - #ifdef RT_USING_USERSPACE + #ifdef RT_USING_SMART extern rt_mmu_info mmu_info; v_addr = rt_hw_mmu_map(&mmu_info, 0, p_addr, size, MMU_MAP_K_RW); #else @@ -705,7 +705,7 @@ void *rt_hw_kernel_phys_to_virt(void *p_addr, size_t size) return v_addr; } -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr) { void *ret; @@ -802,7 +802,7 @@ void *rt_hw_mmu_v2p(rt_mmu_info *mmu_info, void* v_addr) return ret; } -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART void init_mm_setup(unsigned int *mtbl, unsigned int size, unsigned int pv_off) { unsigned int va; diff --git a/libcpu/mips/gs264/mmu.h b/libcpu/mips/gs264/mmu.h index 22a749af64..db12b03d93 100644 --- a/libcpu/mips/gs264/mmu.h +++ b/libcpu/mips/gs264/mmu.h @@ -20,7 +20,7 @@ #define SHAREDEVICE (1<<2) /* shared device */ #define STRONGORDER (0<<2) /* strong ordered */ #define XN (1<<4) /* execute Never */ -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART #define AP_RW (1<<10) /* supervisor=RW, user=No */ #define AP_RO ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */ #else @@ -98,7 +98,7 @@ void *mmu_table_get(); void switch_mmu(void *mmu_table); int rt_hw_mmu_map_init(rt_mmu_info *mmu_info, void* v_address, size_t size, size_t *vtable, size_t pv_off); -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART void *rt_hw_mmu_map(rt_mmu_info *mmu_info, void *v_addr, void* p_addr, size_t size, size_t attr); void *rt_hw_mmu_map_auto(rt_mmu_info *mmu_info, void *v_addr, size_t size, size_t attr); #else diff --git a/libcpu/risc-v/t-head/c906/cache.c b/libcpu/risc-v/t-head/c906/cache.c index 34f2baff34..bcb313bbc7 100644 --- a/libcpu/risc-v/t-head/c906/cache.c +++ b/libcpu/risc-v/t-head/c906/cache.c @@ -128,7 +128,7 @@ void rt_hw_sync_cache_local(void *addr, int size) rt_hw_cpu_icache_invalidate_local(addr, size); } -#ifdef RT_USING_LWP +#ifdef RT_USING_SMART #include #define ICACHE (1 << 0) #define DCACHE (1 << 1) diff --git a/libcpu/risc-v/t-head/c906/context_gcc.S b/libcpu/risc-v/t-head/c906/context_gcc.S index d121eac67d..1442e2bf0a 100644 --- a/libcpu/risc-v/t-head/c906/context_gcc.S +++ b/libcpu/risc-v/t-head/c906/context_gcc.S @@ -21,7 +21,7 @@ rt_hw_context_switch_to: la s0, rt_current_thread LOAD s1, (s0) - #ifdef RT_USING_USERSPACE + #ifdef RT_USING_SMART mv a0, s1 jal lwp_mmu_switch #endif @@ -54,7 +54,7 @@ rt_hw_context_switch: la s0, rt_current_thread LOAD s1, (s0) - #ifdef RT_USING_USERSPACE + #ifdef RT_USING_SMART mv a0, s1 jal lwp_mmu_switch #endif diff --git a/libcpu/risc-v/t-head/c906/interrupt_gcc.S b/libcpu/risc-v/t-head/c906/interrupt_gcc.S index 6b80950fea..084dfa25f4 100644 --- a/libcpu/risc-v/t-head/c906/interrupt_gcc.S +++ b/libcpu/risc-v/t-head/c906/interrupt_gcc.S @@ -93,7 +93,7 @@ copy_context_loop_interrupt: LOAD s1, 0(s0) LOAD sp, 0(s1) - #ifdef RT_USING_USERSPACE + #ifdef RT_USING_SMART mv a0, s1 jal rt_thread_sp_to_thread jal lwp_mmu_switch diff --git a/libcpu/risc-v/t-head/c906/trap.c b/libcpu/risc-v/t-head/c906/trap.c index 831ea3b0a2..beca180831 100644 --- a/libcpu/risc-v/t-head/c906/trap.c +++ b/libcpu/risc-v/t-head/c906/trap.c @@ -26,7 +26,7 @@ #include "rt_interrupt.h" #include "plic.h" -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART #include "riscv_mmu.h" #include "mmu.h" #include "page.h" @@ -112,7 +112,7 @@ void dump_regs(struct rt_hw_stack_frame *regs) rt_size_t satp_v = read_csr(satp); rt_kprintf("satp = 0x%p\n",satp_v); -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART rt_kprintf("\tCurrent Page Table(Physical) = 0x%p\n",__MASKVALUE(satp_v,__MASK(44)) << PAGE_OFFSET_BIT); rt_kprintf("\tCurrent ASID = 0x%p\n",__MASKVALUE(satp_v >> 44,__MASK(16)) << PAGE_OFFSET_BIT); #endif @@ -238,7 +238,7 @@ void handle_trap(rt_size_t scause,rt_size_t stval,rt_size_t sepc,struct rt_hw_st } else { -#ifdef RT_USING_USERSPACE +#ifdef RT_USING_SMART /* page fault */ if (id == EP_LOAD_PAGE_FAULT || id == EP_STORE_PAGE_FAULT) diff --git a/libcpu/risc-v/virt64/context_gcc.S b/libcpu/risc-v/virt64/context_gcc.S index 23a0b014e9..c1fe828822 100644 --- a/libcpu/risc-v/virt64/context_gcc.S +++ b/libcpu/risc-v/virt64/context_gcc.S @@ -78,7 +78,7 @@ rt_hw_context_switch_to: la s0, rt_current_thread LOAD s1, (s0) - #ifdef RT_USING_USERSPACE + #ifdef RT_USING_SMART mv a0, s1 jal lwp_mmu_switch #endif @@ -106,7 +106,7 @@ rt_hw_context_switch: la s0, rt_current_thread LOAD s1, (s0) - #ifdef RT_USING_USERSPACE + #ifdef RT_USING_SMART mv a0, s1 jal lwp_mmu_switch #endif -- cgit v1.3.1