From 72961172033fcb3a96e6fb1758b5ca0e1aebe455 Mon Sep 17 00:00:00 2001 From: wdfk-prog <1425075683@qq.com> Date: Tue, 7 Feb 2023 20:14:35 +0800 Subject: [cortex-m7]rt_hw_cpu_dcache_ops函数uint32_t替换为rt_uint32_t MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- libcpu/arm/cortex-m7/cpu_cache.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'libcpu') diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c index a6c0d62fcf..94e03df5a7 100644 --- a/libcpu/arm/cortex-m7/cpu_cache.c +++ b/libcpu/arm/cortex-m7/cpu_cache.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2021, RT-Thread Development Team + * Copyright (c) 2006-2023, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -73,15 +73,15 @@ void rt_hw_cpu_dcache_ops(int ops, void* addr, int size) if ((ops & clean_invalid) == clean_invalid) { - SCB_CleanInvalidateDCache_by_Addr((uint32_t *)startAddr, size_byte); + SCB_CleanInvalidateDCache_by_Addr((rt_uint32_t *)startAddr, size_byte); } else if (ops & RT_HW_CACHE_FLUSH) { - SCB_CleanDCache_by_Addr((uint32_t *)startAddr, size_byte); + SCB_CleanDCache_by_Addr((rt_uint32_t *)startAddr, size_byte); } else if (ops & RT_HW_CACHE_INVALIDATE) { - SCB_InvalidateDCache_by_Addr((uint32_t *)startAddr, size_byte); + SCB_InvalidateDCache_by_Addr((rt_uint32_t *)startAddr, size_byte); } else { -- cgit v1.3.1