From be2dec978d86fa4b00e74c2340486b8cfb7f44b2 Mon Sep 17 00:00:00 2001 From: BernardXiong Date: Tue, 19 Oct 2021 15:00:46 +0800 Subject: [BSP] fix the compiling issue for qemu-riscv64 --- libcpu/risc-v/virt64/tick.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'libcpu') diff --git a/libcpu/risc-v/virt64/tick.c b/libcpu/risc-v/virt64/tick.c index d6970ec417..53f555da9d 100644 --- a/libcpu/risc-v/virt64/tick.c +++ b/libcpu/risc-v/virt64/tick.c @@ -36,7 +36,7 @@ int tick_isr(void) #ifdef RISCV_S_MODE sbi_set_timer(get_ticks() + tick_cycles); #else - *(uint64_t*)CLINT_MTIMECMP(r_mhartid()) = *(uint64_t*)CLINT_MTIME + tick_cycles; + *(uint64_t*)CLINT_MTIMECMP(__raw_hartid()) = *(uint64_t*)CLINT_MTIME + tick_cycles; #endif return 0; @@ -62,7 +62,7 @@ int rt_hw_tick_init(void) #else clear_csr(mie, MIP_MTIP); clear_csr(mip, MIP_MTIP); - *(uint64_t*)CLINT_MTIMECMP(r_mhartid()) = *(uint64_t*)CLINT_MTIME + interval; + *(uint64_t*)CLINT_MTIMECMP(__raw_hartid()) = *(uint64_t*)CLINT_MTIME + interval; set_csr(mie, MIP_MTIP); #endif return 0; -- cgit v1.3.1